From a16f65c7d117419bd266c28a1901ef129a337569 Mon Sep 17 00:00:00 2001 From: svn2git Date: Sun, 1 May 1994 00:00:00 -0800 Subject: Release FreeBSD 1.1 This commit was manufactured to restore the state of the 1.1-RELEASE image. Releases prior to 5.3-RELEASE are omitting the secure/ and crypto/ subdirs. --- gnu/usr.bin/cc/lib/Makefile | 21 + gnu/usr.bin/cc/lib/aux-output.c | 1921 +++++++ gnu/usr.bin/cc/lib/basic-block.h | 68 + gnu/usr.bin/cc/lib/c-common.c | 1222 +++++ gnu/usr.bin/cc/lib/c-lex.h | 79 + gnu/usr.bin/cc/lib/c-parse.h | 65 + gnu/usr.bin/cc/lib/c-tree.h | 447 ++ gnu/usr.bin/cc/lib/caller-save.c | 780 +++ gnu/usr.bin/cc/lib/calls.c | 2891 +++++++++++ gnu/usr.bin/cc/lib/combine.c | 10025 ++++++++++++++++++++++++++++++++++++ gnu/usr.bin/cc/lib/conditions.h | 115 + gnu/usr.bin/cc/lib/config.h | 52 + gnu/usr.bin/cc/lib/convert.c | 443 ++ gnu/usr.bin/cc/lib/convert.h | 23 + gnu/usr.bin/cc/lib/cse.c | 8243 +++++++++++++++++++++++++++++ gnu/usr.bin/cc/lib/dbxout.c | 2439 +++++++++ gnu/usr.bin/cc/lib/defaults.h | 120 + gnu/usr.bin/cc/lib/dwarfout.c | 5647 ++++++++++++++++++++ gnu/usr.bin/cc/lib/emit-rtl.c | 3137 +++++++++++ gnu/usr.bin/cc/lib/explow.c | 1055 ++++ gnu/usr.bin/cc/lib/expmed.c | 3160 ++++++++++++ gnu/usr.bin/cc/lib/expr.c | 7994 ++++++++++++++++++++++++++++ gnu/usr.bin/cc/lib/expr.h | 812 +++ gnu/usr.bin/cc/lib/final.c | 2740 ++++++++++ gnu/usr.bin/cc/lib/flags.h | 344 ++ gnu/usr.bin/cc/lib/flow.c | 2674 ++++++++++ gnu/usr.bin/cc/lib/fold-const.c | 4479 ++++++++++++++++ gnu/usr.bin/cc/lib/function.c | 4913 ++++++++++++++++++ gnu/usr.bin/cc/lib/function.h | 203 + gnu/usr.bin/cc/lib/gbl-ctors.h | 80 + gnu/usr.bin/cc/lib/getpwd.c | 94 + gnu/usr.bin/cc/lib/glimits.h | 83 + gnu/usr.bin/cc/lib/global.c | 1660 ++++++ gnu/usr.bin/cc/lib/gstddef.h | 217 + gnu/usr.bin/cc/lib/gvarargs.h | 169 + gnu/usr.bin/cc/lib/hard-reg-set.h | 267 + gnu/usr.bin/cc/lib/i386/bsd.h | 132 + gnu/usr.bin/cc/lib/i386/gas.h | 158 + gnu/usr.bin/cc/lib/i386/gstabs.h | 9 + gnu/usr.bin/cc/lib/i386/i386.h | 1591 ++++++ gnu/usr.bin/cc/lib/i386/perform.h | 93 + gnu/usr.bin/cc/lib/i386/unix.h | 145 + gnu/usr.bin/cc/lib/input.h | 46 + gnu/usr.bin/cc/lib/insn-attr.h | 19 + gnu/usr.bin/cc/lib/insn-attrtab.c | 14 + gnu/usr.bin/cc/lib/insn-codes.h | 174 + gnu/usr.bin/cc/lib/insn-config.h | 12 + gnu/usr.bin/cc/lib/insn-emit.c | 2708 ++++++++++ gnu/usr.bin/cc/lib/insn-extract.c | 505 ++ gnu/usr.bin/cc/lib/insn-flags.h | 522 ++ gnu/usr.bin/cc/lib/insn-opinit.c | 179 + gnu/usr.bin/cc/lib/insn-output.c | 5899 +++++++++++++++++++++ gnu/usr.bin/cc/lib/insn-peep.c | 28 + gnu/usr.bin/cc/lib/insn-recog.c | 6158 ++++++++++++++++++++++ gnu/usr.bin/cc/lib/integrate.c | 2902 +++++++++++ gnu/usr.bin/cc/lib/integrate.h | 120 + gnu/usr.bin/cc/lib/jump.c | 4235 +++++++++++++++ gnu/usr.bin/cc/lib/lib.mk | 196 + gnu/usr.bin/cc/lib/local-alloc.c | 2173 ++++++++ gnu/usr.bin/cc/lib/longlong.h | 1004 ++++ gnu/usr.bin/cc/lib/loop.c | 6508 +++++++++++++++++++++++ gnu/usr.bin/cc/lib/loop.h | 169 + gnu/usr.bin/cc/lib/machmode.def | 117 + gnu/usr.bin/cc/lib/machmode.h | 166 + gnu/usr.bin/cc/lib/obstack.c | 454 ++ gnu/usr.bin/cc/lib/obstack.h | 484 ++ gnu/usr.bin/cc/lib/optabs.c | 3614 +++++++++++++ gnu/usr.bin/cc/lib/output.h | 171 + gnu/usr.bin/cc/lib/print-rtl.c | 328 ++ gnu/usr.bin/cc/lib/print-tree.c | 630 +++ gnu/usr.bin/cc/lib/real.c | 5060 ++++++++++++++++++ gnu/usr.bin/cc/lib/real.h | 363 ++ gnu/usr.bin/cc/lib/recog.c | 1961 +++++++ gnu/usr.bin/cc/lib/recog.h | 120 + gnu/usr.bin/cc/lib/reg-stack.c | 2897 +++++++++++ gnu/usr.bin/cc/lib/regclass.c | 1673 ++++++ gnu/usr.bin/cc/lib/regs.h | 148 + gnu/usr.bin/cc/lib/reload.c | 5435 +++++++++++++++++++ gnu/usr.bin/cc/lib/reload.h | 247 + gnu/usr.bin/cc/lib/reload1.c | 6774 ++++++++++++++++++++++++ gnu/usr.bin/cc/lib/reorg.c | 4115 +++++++++++++++ gnu/usr.bin/cc/lib/rtl.c | 860 ++++ gnu/usr.bin/cc/lib/rtl.def | 760 +++ gnu/usr.bin/cc/lib/rtl.h | 917 ++++ gnu/usr.bin/cc/lib/rtlanal.c | 1594 ++++++ gnu/usr.bin/cc/lib/sched.c | 4675 +++++++++++++++++ gnu/usr.bin/cc/lib/sdbout.c | 1484 ++++++ gnu/usr.bin/cc/lib/stmt.c | 4749 +++++++++++++++++ gnu/usr.bin/cc/lib/stor-layout.c | 1170 +++++ gnu/usr.bin/cc/lib/stupid.c | 544 ++ gnu/usr.bin/cc/lib/tconfig.h | 48 + gnu/usr.bin/cc/lib/tm.h | 172 + gnu/usr.bin/cc/lib/toplev.c | 3509 +++++++++++++ gnu/usr.bin/cc/lib/tree.c | 3341 ++++++++++++ gnu/usr.bin/cc/lib/tree.def | 645 +++ gnu/usr.bin/cc/lib/tree.h | 1507 ++++++ gnu/usr.bin/cc/lib/typeclass.h | 14 + gnu/usr.bin/cc/lib/unroll.c | 3251 ++++++++++++ gnu/usr.bin/cc/lib/varasm.c | 3033 +++++++++++ gnu/usr.bin/cc/lib/version.c | 1 + gnu/usr.bin/cc/lib/xcoffout.c | 484 ++ 101 files changed, 171896 insertions(+) create mode 100644 gnu/usr.bin/cc/lib/Makefile create mode 100644 gnu/usr.bin/cc/lib/aux-output.c create mode 100644 gnu/usr.bin/cc/lib/basic-block.h create mode 100644 gnu/usr.bin/cc/lib/c-common.c create mode 100644 gnu/usr.bin/cc/lib/c-lex.h create mode 100644 gnu/usr.bin/cc/lib/c-parse.h create mode 100644 gnu/usr.bin/cc/lib/c-tree.h create mode 100644 gnu/usr.bin/cc/lib/caller-save.c create mode 100644 gnu/usr.bin/cc/lib/calls.c create mode 100644 gnu/usr.bin/cc/lib/combine.c create mode 100644 gnu/usr.bin/cc/lib/conditions.h create mode 100644 gnu/usr.bin/cc/lib/config.h create mode 100644 gnu/usr.bin/cc/lib/convert.c create mode 100644 gnu/usr.bin/cc/lib/convert.h create mode 100644 gnu/usr.bin/cc/lib/cse.c create mode 100644 gnu/usr.bin/cc/lib/dbxout.c create mode 100644 gnu/usr.bin/cc/lib/defaults.h create mode 100644 gnu/usr.bin/cc/lib/dwarfout.c create mode 100644 gnu/usr.bin/cc/lib/emit-rtl.c create mode 100644 gnu/usr.bin/cc/lib/explow.c create mode 100644 gnu/usr.bin/cc/lib/expmed.c create mode 100644 gnu/usr.bin/cc/lib/expr.c create mode 100644 gnu/usr.bin/cc/lib/expr.h create mode 100644 gnu/usr.bin/cc/lib/final.c create mode 100644 gnu/usr.bin/cc/lib/flags.h create mode 100644 gnu/usr.bin/cc/lib/flow.c create mode 100644 gnu/usr.bin/cc/lib/fold-const.c create mode 100644 gnu/usr.bin/cc/lib/function.c create mode 100644 gnu/usr.bin/cc/lib/function.h create mode 100644 gnu/usr.bin/cc/lib/gbl-ctors.h create mode 100644 gnu/usr.bin/cc/lib/getpwd.c create mode 100644 gnu/usr.bin/cc/lib/glimits.h create mode 100644 gnu/usr.bin/cc/lib/global.c create mode 100644 gnu/usr.bin/cc/lib/gstddef.h create mode 100644 gnu/usr.bin/cc/lib/gvarargs.h create mode 100644 gnu/usr.bin/cc/lib/hard-reg-set.h create mode 100644 gnu/usr.bin/cc/lib/i386/bsd.h create mode 100644 gnu/usr.bin/cc/lib/i386/gas.h create mode 100644 gnu/usr.bin/cc/lib/i386/gstabs.h create mode 100644 gnu/usr.bin/cc/lib/i386/i386.h create mode 100644 gnu/usr.bin/cc/lib/i386/perform.h create mode 100644 gnu/usr.bin/cc/lib/i386/unix.h create mode 100644 gnu/usr.bin/cc/lib/input.h create mode 100644 gnu/usr.bin/cc/lib/insn-attr.h create mode 100644 gnu/usr.bin/cc/lib/insn-attrtab.c create mode 100644 gnu/usr.bin/cc/lib/insn-codes.h create mode 100644 gnu/usr.bin/cc/lib/insn-config.h create mode 100644 gnu/usr.bin/cc/lib/insn-emit.c create mode 100644 gnu/usr.bin/cc/lib/insn-extract.c create mode 100644 gnu/usr.bin/cc/lib/insn-flags.h create mode 100644 gnu/usr.bin/cc/lib/insn-opinit.c create mode 100644 gnu/usr.bin/cc/lib/insn-output.c create mode 100644 gnu/usr.bin/cc/lib/insn-peep.c create mode 100644 gnu/usr.bin/cc/lib/insn-recog.c create mode 100644 gnu/usr.bin/cc/lib/integrate.c create mode 100644 gnu/usr.bin/cc/lib/integrate.h create mode 100644 gnu/usr.bin/cc/lib/jump.c create mode 100644 gnu/usr.bin/cc/lib/lib.mk create mode 100644 gnu/usr.bin/cc/lib/local-alloc.c create mode 100644 gnu/usr.bin/cc/lib/longlong.h create mode 100644 gnu/usr.bin/cc/lib/loop.c create mode 100644 gnu/usr.bin/cc/lib/loop.h create mode 100644 gnu/usr.bin/cc/lib/machmode.def create mode 100644 gnu/usr.bin/cc/lib/machmode.h create mode 100644 gnu/usr.bin/cc/lib/obstack.c create mode 100644 gnu/usr.bin/cc/lib/obstack.h create mode 100644 gnu/usr.bin/cc/lib/optabs.c create mode 100644 gnu/usr.bin/cc/lib/output.h create mode 100644 gnu/usr.bin/cc/lib/print-rtl.c create mode 100644 gnu/usr.bin/cc/lib/print-tree.c create mode 100644 gnu/usr.bin/cc/lib/real.c create mode 100644 gnu/usr.bin/cc/lib/real.h create mode 100644 gnu/usr.bin/cc/lib/recog.c create mode 100644 gnu/usr.bin/cc/lib/recog.h create mode 100644 gnu/usr.bin/cc/lib/reg-stack.c create mode 100644 gnu/usr.bin/cc/lib/regclass.c create mode 100644 gnu/usr.bin/cc/lib/regs.h create mode 100644 gnu/usr.bin/cc/lib/reload.c create mode 100644 gnu/usr.bin/cc/lib/reload.h create mode 100644 gnu/usr.bin/cc/lib/reload1.c create mode 100644 gnu/usr.bin/cc/lib/reorg.c create mode 100644 gnu/usr.bin/cc/lib/rtl.c create mode 100644 gnu/usr.bin/cc/lib/rtl.def create mode 100644 gnu/usr.bin/cc/lib/rtl.h create mode 100644 gnu/usr.bin/cc/lib/rtlanal.c create mode 100644 gnu/usr.bin/cc/lib/sched.c create mode 100644 gnu/usr.bin/cc/lib/sdbout.c create mode 100644 gnu/usr.bin/cc/lib/stmt.c create mode 100644 gnu/usr.bin/cc/lib/stor-layout.c create mode 100644 gnu/usr.bin/cc/lib/stupid.c create mode 100644 gnu/usr.bin/cc/lib/tconfig.h create mode 100644 gnu/usr.bin/cc/lib/tm.h create mode 100644 gnu/usr.bin/cc/lib/toplev.c create mode 100644 gnu/usr.bin/cc/lib/tree.c create mode 100644 gnu/usr.bin/cc/lib/tree.def create mode 100644 gnu/usr.bin/cc/lib/tree.h create mode 100644 gnu/usr.bin/cc/lib/typeclass.h create mode 100644 gnu/usr.bin/cc/lib/unroll.c create mode 100644 gnu/usr.bin/cc/lib/varasm.c create mode 100644 gnu/usr.bin/cc/lib/version.c create mode 100644 gnu/usr.bin/cc/lib/xcoffout.c (limited to 'gnu/usr.bin/cc/lib') diff --git a/gnu/usr.bin/cc/lib/Makefile b/gnu/usr.bin/cc/lib/Makefile new file mode 100644 index 000000000000..233f45711cca --- /dev/null +++ b/gnu/usr.bin/cc/lib/Makefile @@ -0,0 +1,21 @@ +LIB = gcc2 + +CFLAGS += -I${.CURDIR} -DNOFPU +NOPROFILE=no +NOPIC=no + +SRCS = aux-output.c c-common.c caller-save.c calls.c combine.c \ + convert.c cse.c dbxout.c dwarfout.c emit-rtl.c explow.c \ + expmed.c expr.c final.c flow.c fold-const.c function.c \ + getpwd.c global.c insn-attrtab.c insn-emit.c insn-extract.c \ + insn-opinit.c insn-output.c insn-peep.c insn-recog.c \ + integrate.c jump.c local-alloc.c loop.c obstack.c optabs.c \ + print-rtl.c print-tree.c real.c recog.c reg-stack.c regclass.c \ + reload.c reload1.c reorg.c rtl.c rtlanal.c sched.c sdbout.c \ + stmt.c stor-layout.c stupid.c toplev.c tree.c unroll.c \ + varasm.c version.c xcoffout.c + +install: + @echo -n + +.include "lib.mk" diff --git a/gnu/usr.bin/cc/lib/aux-output.c b/gnu/usr.bin/cc/lib/aux-output.c new file mode 100644 index 000000000000..d0b11961b7b4 --- /dev/null +++ b/gnu/usr.bin/cc/lib/aux-output.c @@ -0,0 +1,1921 @@ +/* Subroutines for insn-output.c for Intel 80386. + Copyright (C) 1988, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include +#include +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "output.h" +#include "insn-attr.h" +#include "tree.h" +#include "flags.h" + +#ifdef EXTRA_CONSTRAINT +/* If EXTRA_CONSTRAINT is defined, then the 'S' + constraint in REG_CLASS_FROM_LETTER will no longer work, and various + asm statements that need 'S' for class SIREG will break. */ + error EXTRA_CONSTRAINT conflicts with S constraint letter +/* The previous line used to be #error, but some compilers barf + even if the conditional was untrue. */ +#endif + +#define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx)) + +extern FILE *asm_out_file; +extern char *strcat (); + +char *singlemove_string (); +char *output_move_const_single (); +char *output_fp_cc0_set (); + +char *hi_reg_name[] = HI_REGISTER_NAMES; +char *qi_reg_name[] = QI_REGISTER_NAMES; +char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES; + +/* Array of the smallest class containing reg number REGNO, indexed by + REGNO. Used by REGNO_REG_CLASS in i386.h. */ + +enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = +{ + /* ax, dx, cx, bx */ + AREG, DREG, CREG, BREG, + /* si, di, bp, sp */ + SIREG, DIREG, INDEX_REGS, GENERAL_REGS, + /* FP registers */ + FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS, + FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, + /* arg pointer */ + INDEX_REGS +}; + +/* Test and compare insns in i386.md store the information needed to + generate branch and scc insns here. */ + +struct rtx_def *i386_compare_op0, *i386_compare_op1; +struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); + +/* Output an insn whose source is a 386 integer register. SRC is the + rtx for the register, and TEMPLATE is the op-code template. SRC may + be either SImode or DImode. + + The template will be output with operands[0] as SRC, and operands[1] + as a pointer to the top of the 386 stack. So a call from floatsidf2 + would look like this: + + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + + where %z0 corresponds to the caller's operands[1], and is used to + emit the proper size suffix. + + ??? Extend this to handle HImode - a 387 can load and store HImode + values directly. */ + +void +output_op_from_reg (src, template) + rtx src; + char *template; +{ + rtx xops[4]; + + xops[0] = src; + xops[1] = AT_SP (Pmode); + xops[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (src))); + xops[3] = stack_pointer_rtx; + + if (GET_MODE_SIZE (GET_MODE (src)) > UNITS_PER_WORD) + { + rtx high = gen_rtx (REG, SImode, REGNO (src) + 1); + output_asm_insn (AS1 (push%L0,%0), &high); + } + output_asm_insn (AS1 (push%L0,%0), &src); + + output_asm_insn (template, xops); + + output_asm_insn (AS2 (add%L3,%2,%3), xops); +} + +/* Output an insn to pop an value from the 387 top-of-stack to 386 + register DEST. The 387 register stack is popped if DIES is true. If + the mode of DEST is an integer mode, a `fist' integer store is done, + otherwise a `fst' float store is done. */ + +void +output_to_reg (dest, dies) + rtx dest; + int dies; +{ + rtx xops[4]; + + xops[0] = AT_SP (Pmode); + xops[1] = stack_pointer_rtx; + xops[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (dest))); + xops[3] = dest; + + output_asm_insn (AS2 (sub%L1,%2,%1), xops); + + if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT) + { + if (dies) + output_asm_insn (AS1 (fistp%z3,%y0), xops); + else + output_asm_insn (AS1 (fist%z3,%y0), xops); + } + else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT) + { + if (dies) + output_asm_insn (AS1 (fstp%z3,%y0), xops); + else + output_asm_insn (AS1 (fst%z3,%y0), xops); + } + else + abort (); + + output_asm_insn (AS1 (pop%L0,%0), &dest); + + if (GET_MODE_SIZE (GET_MODE (dest)) > UNITS_PER_WORD) + { + dest = gen_rtx (REG, SImode, REGNO (dest) + 1); + output_asm_insn (AS1 (pop%L0,%0), &dest); + } +} + +char * +singlemove_string (operands) + rtx *operands; +{ + rtx x; + if (GET_CODE (operands[0]) == MEM + && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC) + { + if (XEXP (x, 0) != stack_pointer_rtx) + abort (); + return "push%L1 %1"; + } + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + return output_move_const_single (operands); + } + else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG) + return AS2 (mov%L0,%1,%0); + else if (CONSTANT_P (operands[1])) + return AS2 (mov%L0,%1,%0); + else + { + output_asm_insn ("push%L1 %1", operands); + return "pop%L0 %0"; + } +} + +/* Return a REG that occurs in ADDR with coefficient 1. + ADDR can be effectively incremented by incrementing REG. */ + +static rtx +find_addr_reg (addr) + rtx addr; +{ + while (GET_CODE (addr) == PLUS) + { + if (GET_CODE (XEXP (addr, 0)) == REG) + addr = XEXP (addr, 0); + else if (GET_CODE (XEXP (addr, 1)) == REG) + addr = XEXP (addr, 1); + else if (CONSTANT_P (XEXP (addr, 0))) + addr = XEXP (addr, 1); + else if (CONSTANT_P (XEXP (addr, 1))) + addr = XEXP (addr, 0); + else + abort (); + } + if (GET_CODE (addr) == REG) + return addr; + abort (); +} + +/* Output an insn to add the constant N to the register X. */ + +static void +asm_add (n, x) + int n; + rtx x; +{ + rtx xops[2]; + xops[1] = x; + if (n < 0) + { + xops[0] = GEN_INT (-n); + output_asm_insn (AS2 (sub%L0,%0,%1), xops); + } + else if (n > 0) + { + xops[0] = GEN_INT (n); + output_asm_insn (AS2 (add%L0,%0,%1), xops); + } +} + +/* Output assembler code to perform a doubleword move insn + with operands OPERANDS. */ + +char * +output_move_double (operands) + rtx *operands; +{ + enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; + rtx latehalf[2]; + rtx addreg0 = 0, addreg1 = 0; + int dest_overlapped_low = 0; + + /* First classify both operands. */ + + if (REG_P (operands[0])) + optype0 = REGOP; + else if (offsettable_memref_p (operands[0])) + optype0 = OFFSOP; + else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) + optype0 = POPOP; + else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + optype0 = PUSHOP; + else if (GET_CODE (operands[0]) == MEM) + optype0 = MEMOP; + else + optype0 = RNDOP; + + if (REG_P (operands[1])) + optype1 = REGOP; + else if (CONSTANT_P (operands[1])) + optype1 = CNSTOP; + else if (offsettable_memref_p (operands[1])) + optype1 = OFFSOP; + else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) + optype1 = POPOP; + else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) + optype1 = PUSHOP; + else if (GET_CODE (operands[1]) == MEM) + optype1 = MEMOP; + else + optype1 = RNDOP; + + /* Check for the cases that the operand constraints are not + supposed to allow to happen. Abort if we get one, + because generating code for these cases is painful. */ + + if (optype0 == RNDOP || optype1 == RNDOP) + abort (); + + /* If one operand is decrementing and one is incrementing + decrement the former register explicitly + and change that operand into ordinary indexing. */ + + if (optype0 == PUSHOP && optype1 == POPOP) + { + operands[0] = XEXP (XEXP (operands[0], 0), 0); + asm_add (-8, operands[0]); + operands[0] = gen_rtx (MEM, DImode, operands[0]); + optype0 = OFFSOP; + } + if (optype0 == POPOP && optype1 == PUSHOP) + { + operands[1] = XEXP (XEXP (operands[1], 0), 0); + asm_add (-8, operands[1]); + operands[1] = gen_rtx (MEM, DImode, operands[1]); + optype1 = OFFSOP; + } + + /* If an operand is an unoffsettable memory ref, find a register + we can increment temporarily to make it refer to the second word. */ + + if (optype0 == MEMOP) + addreg0 = find_addr_reg (XEXP (operands[0], 0)); + + if (optype1 == MEMOP) + addreg1 = find_addr_reg (XEXP (operands[1], 0)); + + /* Ok, we can do one word at a time. + Normally we do the low-numbered word first, + but if either operand is autodecrementing then we + do the high-numbered word first. + + In either case, set up in LATEHALF the operands to use + for the high-numbered word and in some cases alter the + operands in OPERANDS to be suitable for the low-numbered word. */ + + if (optype0 == REGOP) + latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + else if (optype0 == OFFSOP) + latehalf[0] = adj_offsettable_operand (operands[0], 4); + else + latehalf[0] = operands[0]; + + if (optype1 == REGOP) + latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + else if (optype1 == OFFSOP) + latehalf[1] = adj_offsettable_operand (operands[1], 4); + else if (optype1 == CNSTOP) + { + if (GET_CODE (operands[1]) == CONST_DOUBLE) + split_double (operands[1], &operands[1], &latehalf[1]); + else if (CONSTANT_P (operands[1])) + { + if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0) + latehalf[1] = constm1_rtx; + else + latehalf[1] = const0_rtx; + } + } + else + latehalf[1] = operands[1]; + + /* If insn is effectively movd N (sp),-(sp) then we will do the + high word first. We should use the adjusted operand 1 (which is N+4 (sp)) + for the low word as well, to compensate for the first decrement of sp. */ + if (optype0 == PUSHOP + && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM + && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) + operands[1] = latehalf[1]; + + /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), + if the upper part of reg N does not appear in the MEM, arrange to + emit the move late-half first. Otherwise, compute the MEM address + into the upper part of N and use that as a pointer to the memory + operand. */ + if (optype0 == REGOP + && (optype1 == OFFSOP || optype1 == MEMOP)) + { + if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) + && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) + { + /* If both halves of dest are used in the src memory address, + compute the address into latehalf of dest. */ + rtx xops[2]; + xops[0] = latehalf[0]; + xops[1] = XEXP (operands[1], 0); + output_asm_insn (AS2 (lea%L0,%a1,%0), xops); + operands[1] = gen_rtx (MEM, DImode, latehalf[0]); + latehalf[1] = adj_offsettable_operand (operands[1], 4); + } + else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))) + /* If the low half of dest is mentioned in the source memory + address, the arrange to emit the move late half first. */ + dest_overlapped_low = 1; + } + + /* If one or both operands autodecrementing, + do the two words, high-numbered first. */ + + /* Likewise, the first move would clobber the source of the second one, + do them in the other order. This happens only for registers; + such overlap can't happen in memory unless the user explicitly + sets it up, and that is an undefined circumstance. */ + + if (optype0 == PUSHOP || optype1 == PUSHOP + || (optype0 == REGOP && optype1 == REGOP + && REGNO (operands[0]) == REGNO (latehalf[1])) + || dest_overlapped_low) + { + /* Make any unoffsettable addresses point at high-numbered word. */ + if (addreg0) + asm_add (4, addreg0); + if (addreg1) + asm_add (4, addreg1); + + /* Do that word. */ + output_asm_insn (singlemove_string (latehalf), latehalf); + + /* Undo the adds we just did. */ + if (addreg0) + asm_add (-4, addreg0); + if (addreg1) + asm_add (-4, addreg1); + + /* Do low-numbered word. */ + return singlemove_string (operands); + } + + /* Normal case: do the two words, low-numbered first. */ + + output_asm_insn (singlemove_string (operands), operands); + + /* Make any unoffsettable addresses point at high-numbered word. */ + if (addreg0) + asm_add (4, addreg0); + if (addreg1) + asm_add (4, addreg1); + + /* Do that word. */ + output_asm_insn (singlemove_string (latehalf), latehalf); + + /* Undo the adds we just did. */ + if (addreg0) + asm_add (-4, addreg0); + if (addreg1) + asm_add (-4, addreg1); + + return ""; +} + +int +standard_80387_constant_p (x) + rtx x; +{ +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + REAL_VALUE_TYPE d; + jmp_buf handler; + int is0, is1; + + if (setjmp (handler)) + return 0; + + set_float_handler (handler); + REAL_VALUE_FROM_CONST_DOUBLE (d, x); + is0 = REAL_VALUES_EQUAL (d, dconst0); + is1 = REAL_VALUES_EQUAL (d, dconst1); + set_float_handler (NULL_PTR); + + if (is0) + return 1; + + if (is1) + return 2; + + /* Note that on the 80387, other constants, such as pi, + are much slower to load as standard constants + than to load from doubles in memory! */ +#endif + + return 0; +} + +char * +output_move_const_single (operands) + rtx *operands; +{ + if (FP_REG_P (operands[0])) + { + int conval = standard_80387_constant_p (operands[1]); + + if (conval == 1) + return "fldz"; + + if (conval == 2) + return "fld1"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + union { int i[2]; double d;} u1; + union { int i; float f;} u2; + u1.i[0] = CONST_DOUBLE_LOW (operands[1]); + u1.i[1] = CONST_DOUBLE_HIGH (operands[1]); + u2.f = u1.d; + operands[1] = GEN_INT (u2.i); + } + return singlemove_string (operands); +} + +/* Returns 1 if OP is either a symbol reference or a sum of a symbol + reference and a constant. */ + +int +symbolic_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + switch (GET_CODE (op)) + { + case SYMBOL_REF: + case LABEL_REF: + return 1; + case CONST: + op = XEXP (op, 0); + return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF + || GET_CODE (XEXP (op, 0)) == LABEL_REF) + && GET_CODE (XEXP (op, 1)) == CONST_INT); + default: + return 0; + } +} + +/* Test for a valid operand for a call instruction. + Don't allow the arg pointer register or virtual regs + since they may change into reg + const, which the patterns + can't handle yet. */ + +int +call_insn_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == MEM + && ((CONSTANT_ADDRESS_P (XEXP (op, 0)) + /* This makes a difference for PIC. */ + && general_operand (XEXP (op, 0), Pmode)) + || (GET_CODE (XEXP (op, 0)) == REG + && XEXP (op, 0) != arg_pointer_rtx + && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER + && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) + return 1; + return 0; +} + +/* Like call_insn_operand but allow (mem (symbol_ref ...)) + even if pic. */ + +int +expander_call_insn_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == MEM + && (CONSTANT_ADDRESS_P (XEXP (op, 0)) + || (GET_CODE (XEXP (op, 0)) == REG + && XEXP (op, 0) != arg_pointer_rtx + && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER + && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) + return 1; + return 0; +} + +/* Returns 1 if OP contains a symbol reference */ + +int +symbolic_reference_mentioned_p (op) + rtx op; +{ + register char *fmt; + register int i; + + if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) + return 1; + + fmt = GET_RTX_FORMAT (GET_CODE (op)); + for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + + for (j = XVECLEN (op, i) - 1; j >= 0; j--) + if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) + return 1; + } + else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) + return 1; + } + + return 0; +} + +/* Return a legitimate reference for ORIG (an address) using the + register REG. If REG is 0, a new pseudo is generated. + + There are three types of references that must be handled: + + 1. Global data references must load the address from the GOT, via + the PIC reg. An insn is emitted to do this load, and the reg is + returned. + + 2. Static data references must compute the address as an offset + from the GOT, whose base is in the PIC reg. An insn is emitted to + compute the address into a reg, and the reg is returned. Static + data objects have SYMBOL_REF_FLAG set to differentiate them from + global data objects. + + 3. Constant pool addresses must be handled special. They are + considered legitimate addresses, but only if not used with regs. + When printed, the output routines know to print the reference with the + PIC reg, even though the PIC reg doesn't appear in the RTL. + + GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC + reg also appears in the address (except for constant pool references, + noted above). + + "switch" statements also require special handling when generating + PIC code. See comments by the `casesi' insn in i386.md for details. */ + +rtx +legitimize_pic_address (orig, reg) + rtx orig; + rtx reg; +{ + rtx addr = orig; + rtx new = orig; + + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) + { + if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr)) + reg = new = orig; + else + { + if (reg == 0) + reg = gen_reg_rtx (Pmode); + + if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr)) + new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig); + else + new = gen_rtx (MEM, Pmode, + gen_rtx (PLUS, Pmode, + pic_offset_table_rtx, orig)); + + emit_move_insn (reg, new); + } + current_function_uses_pic_offset_table = 1; + return reg; + } + else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) + { + rtx base; + + if (GET_CODE (addr) == CONST) + { + addr = XEXP (addr, 0); + if (GET_CODE (addr) != PLUS) + abort (); + } + + if (XEXP (addr, 0) == pic_offset_table_rtx) + return orig; + + if (reg == 0) + reg = gen_reg_rtx (Pmode); + + base = legitimize_pic_address (XEXP (addr, 0), reg); + addr = legitimize_pic_address (XEXP (addr, 1), + base == reg ? NULL_RTX : reg); + + if (GET_CODE (addr) == CONST_INT) + return plus_constant (base, INTVAL (addr)); + + if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1))) + { + base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0)); + addr = XEXP (addr, 1); + } + return gen_rtx (PLUS, Pmode, base, addr); + } + return new; +} + +/* Emit insns to move operands[1] into operands[0]. */ + +void +emit_pic_move (operands, mode) + rtx *operands; + enum machine_mode mode; +{ + rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); + + if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) + operands[1] = (rtx) force_reg (SImode, operands[1]); + else + operands[1] = legitimize_pic_address (operands[1], temp); +} + +/* This function generates the assembly code for function entry. + FILE is an stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. */ + +void +function_prologue (file, size) + FILE *file; + int size; +{ + register int regno; + int limit; + rtx xops[4]; + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + + xops[0] = stack_pointer_rtx; + xops[1] = frame_pointer_rtx; + xops[2] = GEN_INT (size); + if (frame_pointer_needed) + { + output_asm_insn ("push%L1 %1", xops); + output_asm_insn (AS2 (mov%L0,%0,%1), xops); + } + + if (size) + output_asm_insn (AS2 (sub%L0,%2,%0), xops); + + /* Note If use enter it is NOT reversed args. + This one is not reversed from intel!! + I think enter is slower. Also sdb doesn't like it. + But if you want it the code is: + { + xops[3] = const0_rtx; + output_asm_insn ("enter %2,%3", xops); + } + */ + limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); + for (regno = limit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + output_asm_insn ("push%L0 %0", xops); + } + + if (pic_reg_used) + { + xops[0] = pic_offset_table_rtx; + xops[1] = (rtx) gen_label_rtx (); + + output_asm_insn (AS1 (call,%P1), xops); + ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1])); + output_asm_insn (AS1 (pop%L0,%0), xops); + output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops); + } +} + +/* Return 1 if it is appropriate to emit `ret' instructions in the + body of a function. Do this only if the epilogue is simple, needing a + couple of insns. Prior to reloading, we can't tell how many registers + must be saved, so return 0 then. + + If NON_SAVING_SETJMP is defined and true, then it is not possible + for the epilogue to be simple, so return 0. This is a special case + since NON_SAVING_SETJMP will not cause regs_ever_live to change until + final, but jump_optimize may need to know sooner if a `return' is OK. */ + +int +simple_386_epilogue () +{ + int regno; + int nregs = 0; + int reglimit = (frame_pointer_needed + ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + +#ifdef NON_SAVING_SETJMP + if (NON_SAVING_SETJMP && current_function_calls_setjmp) + return 0; +#endif + + if (! reload_completed) + return 0; + + for (regno = reglimit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + nregs++; + + return nregs == 0 || ! frame_pointer_needed; +} + +/* This function generates the assembly code for function exit. + FILE is an stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to deallocate. */ + +void +function_epilogue (file, size) + FILE *file; + int size; +{ + register int regno; + register int nregs, limit; + int offset; + rtx xops[3]; + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + + /* Compute the number of registers to pop */ + + limit = (frame_pointer_needed + ? FRAME_POINTER_REGNUM + : STACK_POINTER_REGNUM); + + nregs = 0; + + for (regno = limit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + nregs++; + + /* sp is often unreliable so we must go off the frame pointer, + */ + + /* In reality, we may not care if sp is unreliable, because we can + restore the register relative to the frame pointer. In theory, + since each move is the same speed as a pop, and we don't need the + leal, this is faster. For now restore multiple registers the old + way. */ + + offset = -size - (nregs * UNITS_PER_WORD); + + xops[2] = stack_pointer_rtx; + + if (nregs > 1 || ! frame_pointer_needed) + { + if (frame_pointer_needed) + { + xops[0] = adj_offsettable_operand (AT_BP (Pmode), offset); + output_asm_insn (AS2 (lea%L2,%0,%2), xops); + } + + for (regno = 0; regno < limit; regno++) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + output_asm_insn ("pop%L0 %0", xops); + } + } + else + for (regno = 0; regno < limit; regno++) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset); + output_asm_insn (AS2 (mov%L0,%1,%0), xops); + offset += 4; + } + + if (frame_pointer_needed) + { + /* On i486, mov & pop is faster than "leave". */ + + if (TARGET_486) + { + xops[0] = frame_pointer_rtx; + output_asm_insn (AS2 (mov%L2,%0,%2), xops); + output_asm_insn ("pop%L0 %0", xops); + } + else + output_asm_insn ("leave", xops); + } + else if (size) + { + /* If there is no frame pointer, we must still release the frame. */ + + xops[0] = GEN_INT (size); + output_asm_insn (AS2 (add%L2,%0,%2), xops); + } + + if (current_function_pops_args && current_function_args_size) + { + xops[1] = GEN_INT (current_function_pops_args); + + /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If + asked to pop more, pop return address, do explicit add, and jump + indirectly to the caller. */ + + if (current_function_pops_args >= 32768) + { + /* ??? Which register to use here? */ + xops[0] = gen_rtx (REG, SImode, 2); + output_asm_insn ("pop%L0 %0", xops); + output_asm_insn (AS2 (add%L2,%1,%2), xops); + output_asm_insn ("jmp %*%0", xops); + } + else + output_asm_insn ("ret %1", xops); + } + else + output_asm_insn ("ret", xops); +} + +/* Print an integer constant expression in assembler syntax. Addition + and subtraction are the only arithmetic that may appear in these + expressions. FILE is the stdio stream to write to, X is the rtx, and + CODE is the operand print code from the output string. */ + +static void +output_pic_addr_const (file, x, code) + FILE *file; + rtx x; + int code; +{ + char buf[256]; + + switch (GET_CODE (x)) + { + case PC: + if (flag_pic) + putc ('.', file); + else + abort (); + break; + + case SYMBOL_REF: + case LABEL_REF: + if (GET_CODE (x) == SYMBOL_REF) + assemble_name (file, XSTR (x, 0)); + else + { + ASM_GENERATE_INTERNAL_LABEL (buf, "L", + CODE_LABEL_NUMBER (XEXP (x, 0))); + assemble_name (asm_out_file, buf); + } + + if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) + fprintf (file, "@GOTOFF(%%ebx)"); + else if (code == 'P') + fprintf (file, "@PLT"); + else if (GET_CODE (x) == LABEL_REF || ! SYMBOL_REF_FLAG (x)) + fprintf (file, "@GOT"); + else + fprintf (file, "@GOTOFF"); + + break; + + case CODE_LABEL: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); + assemble_name (asm_out_file, buf); + break; + + case CONST_INT: + fprintf (file, "%d", INTVAL (x)); + break; + + case CONST: + /* This used to output parentheses around the expression, + but that does not work on the 386 (either ATT or BSD assembler). */ + output_pic_addr_const (file, XEXP (x, 0), code); + break; + + case CONST_DOUBLE: + if (GET_MODE (x) == VOIDmode) + { + /* We can use %d if the number is <32 bits and positive. */ + if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0) + fprintf (file, "0x%x%08x", + CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x)); + else + fprintf (file, "%d", CONST_DOUBLE_LOW (x)); + } + else + /* We can't handle floating point constants; + PRINT_OPERAND must handle them. */ + output_operand_lossage ("floating constant misused"); + break; + + case PLUS: + /* Some assemblers need integer constants to appear last (eg masm). */ + if (GET_CODE (XEXP (x, 0)) == CONST_INT) + { + output_pic_addr_const (file, XEXP (x, 1), code); + if (INTVAL (XEXP (x, 0)) >= 0) + fprintf (file, "+"); + output_pic_addr_const (file, XEXP (x, 0), code); + } + else + { + output_pic_addr_const (file, XEXP (x, 0), code); + if (INTVAL (XEXP (x, 1)) >= 0) + fprintf (file, "+"); + output_pic_addr_const (file, XEXP (x, 1), code); + } + break; + + case MINUS: + output_pic_addr_const (file, XEXP (x, 0), code); + fprintf (file, "-"); + output_pic_addr_const (file, XEXP (x, 1), code); + break; + + default: + output_operand_lossage ("invalid expression as operand"); + } +} + +/* Meaning of CODE: + f -- float insn (print a CONST_DOUBLE as a float rather than in hex). + D,L,W,B,Q,S -- print the opcode suffix for specified size of operand. + R -- print the prefix for register names. + z -- print the opcode suffix for the size of the current operand. + * -- print a star (in certain assembler syntax) + w -- print the operand as if it's a "word" (HImode) even if it isn't. + c -- don't print special prefixes before constant operands. +*/ + +void +print_operand (file, x, code) + FILE *file; + rtx x; + int code; +{ + if (code) + { + switch (code) + { + case '*': + if (USE_STAR) + putc ('*', file); + return; + + case 'L': + PUT_OP_SIZE (code, 'l', file); + return; + + case 'W': + PUT_OP_SIZE (code, 'w', file); + return; + + case 'B': + PUT_OP_SIZE (code, 'b', file); + return; + + case 'Q': + PUT_OP_SIZE (code, 'l', file); + return; + + case 'S': + PUT_OP_SIZE (code, 's', file); + return; + + case 'z': + /* 387 opcodes don't get size suffixes if the operands are + registers. */ + + if (STACK_REG_P (x)) + return; + + /* this is the size of op from size of operand */ + switch (GET_MODE_SIZE (GET_MODE (x))) + { + case 1: + PUT_OP_SIZE ('B', 'b', file); + return; + + case 2: + PUT_OP_SIZE ('W', 'w', file); + return; + + case 4: + if (GET_MODE (x) == SFmode) + { + PUT_OP_SIZE ('S', 's', file); + return; + } + else + PUT_OP_SIZE ('L', 'l', file); + return; + + case 8: + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) + { +#ifdef GAS_MNEMONICS + PUT_OP_SIZE ('Q', 'q', file); + return; +#else + PUT_OP_SIZE ('Q', 'l', file); /* Fall through */ +#endif + } + + PUT_OP_SIZE ('Q', 'l', file); + return; + } + + case 'b': + case 'w': + case 'k': + case 'h': + case 'y': + case 'P': + break; + + default: + { + char str[50]; + + sprintf (str, "invalid operand code `%c'", code); + output_operand_lossage (str); + } + } + } + if (GET_CODE (x) == REG) + { + PRINT_REG (x, code, file); + } + else if (GET_CODE (x) == MEM) + { + PRINT_PTR (x, file); + if (CONSTANT_ADDRESS_P (XEXP (x, 0))) + { + if (flag_pic) + output_pic_addr_const (file, XEXP (x, 0), code); + else + output_addr_const (file, XEXP (x, 0)); + } + else + output_address (XEXP (x, 0)); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) + { + union { double d; int i[2]; } u; + union { float f; int i; } u1; + u.i[0] = CONST_DOUBLE_LOW (x); + u.i[1] = CONST_DOUBLE_HIGH (x); + u1.f = u.d; + PRINT_IMMED_PREFIX (file); + fprintf (file, "0x%x", u1.i); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) + { + union { double d; int i[2]; } u; + u.i[0] = CONST_DOUBLE_LOW (x); + u.i[1] = CONST_DOUBLE_HIGH (x); + fprintf (file, "%.22e", u.d); + } + else + { + if (code != 'P') + { + if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) + PRINT_IMMED_PREFIX (file); + else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF + || GET_CODE (x) == LABEL_REF) + PRINT_OFFSET_PREFIX (file); + } + if (flag_pic) + output_pic_addr_const (file, x, code); + else + output_addr_const (file, x); + } +} + +/* Print a memory operand whose address is ADDR. */ + +void +print_operand_address (file, addr) + FILE *file; + register rtx addr; +{ + register rtx reg1, reg2, breg, ireg; + rtx offset; + + switch (GET_CODE (addr)) + { + case REG: + ADDR_BEG (file); + fprintf (file, "%se", RP); + fputs (hi_reg_name[REGNO (addr)], file); + ADDR_END (file); + break; + + case PLUS: + reg1 = 0; + reg2 = 0; + ireg = 0; + breg = 0; + offset = 0; + if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) + { + offset = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) + { + offset = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) != PLUS) ; + else if (GET_CODE (XEXP (addr, 0)) == MULT) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == MULT) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + else if (GET_CODE (XEXP (addr, 0)) == REG) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == REG) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) + { + if (reg1 == 0) reg1 = addr; + else reg2 = addr; + addr = 0; + } + if (offset != 0) + { + if (addr != 0) abort (); + addr = offset; + } + if ((reg1 && GET_CODE (reg1) == MULT) + || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) + { + breg = reg2; + ireg = reg1; + } + else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) + { + breg = reg1; + ireg = reg2; + } + + if (ireg != 0 || breg != 0) + { + int scale = 1; + + if (addr != 0) + { + if (GET_CODE (addr) == LABEL_REF) + output_asm_label (addr); + else + { + if (flag_pic) + output_pic_addr_const (file, addr, 0); + else + output_addr_const (file, addr); + } + } + + if (ireg != 0 && GET_CODE (ireg) == MULT) + { + scale = INTVAL (XEXP (ireg, 1)); + ireg = XEXP (ireg, 0); + } + + /* The stack pointer can only appear as a base register, + never an index register, so exchange the regs if it is wrong. */ + + if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM) + { + rtx tmp; + + tmp = breg; + breg = ireg; + ireg = tmp; + } + + /* output breg+ireg*scale */ + PRINT_B_I_S (breg, ireg, scale, file); + break; + } + + case MULT: + { + int scale; + if (GET_CODE (XEXP (addr, 0)) == CONST_INT) + { + scale = INTVAL (XEXP (addr, 0)); + ireg = XEXP (addr, 1); + } + else + { + scale = INTVAL (XEXP (addr, 1)); + ireg = XEXP (addr, 0); + } + output_addr_const (file, const0_rtx); + PRINT_B_I_S ((rtx) 0, ireg, scale, file); + } + break; + + default: + if (GET_CODE (addr) == CONST_INT + && INTVAL (addr) < 0x8000 + && INTVAL (addr) >= -0x8000) + fprintf (file, "%d", INTVAL (addr)); + else + { + if (flag_pic) + output_pic_addr_const (file, addr, 0); + else + output_addr_const (file, addr); + } + } +} + +/* Set the cc_status for the results of an insn whose pattern is EXP. + On the 80386, we assume that only test and compare insns, as well + as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT, LSHIFT, + ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully. + Also, we assume that jumps, moves and sCOND don't affect the condition + codes. All else clobbers the condition codes, by assumption. + + We assume that ALL integer add, minus, etc. instructions effect the + condition codes. This MUST be consistent with i386.md. + + We don't record any float test or compare - the redundant test & + compare check in final.c does not handle stack-like regs correctly. */ + +void +notice_update_cc (exp) + rtx exp; +{ + if (GET_CODE (exp) == SET) + { + /* Jumps do not alter the cc's. */ + if (SET_DEST (exp) == pc_rtx) + return; + /* Moving register or memory into a register: + it doesn't alter the cc's, but it might invalidate + the RTX's which we remember the cc's came from. + (Note that moving a constant 0 or 1 MAY set the cc's). */ + if (REG_P (SET_DEST (exp)) + && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM + || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) + { + if (cc_status.value1 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) + cc_status.value1 = 0; + if (cc_status.value2 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) + cc_status.value2 = 0; + return; + } + /* Moving register into memory doesn't alter the cc's. + It may invalidate the RTX's which we remember the cc's came from. */ + if (GET_CODE (SET_DEST (exp)) == MEM + && (REG_P (SET_SRC (exp)) + || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) + { + if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM) + cc_status.value1 = 0; + if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM) + cc_status.value2 = 0; + return; + } + /* Function calls clobber the cc's. */ + else if (GET_CODE (SET_SRC (exp)) == CALL) + { + CC_STATUS_INIT; + return; + } + /* Tests and compares set the cc's in predictable ways. */ + else if (SET_DEST (exp) == cc0_rtx) + { + CC_STATUS_INIT; + cc_status.value1 = SET_SRC (exp); + return; + } + /* Certain instructions effect the condition codes. */ + else if (GET_MODE (SET_SRC (exp)) == SImode + || GET_MODE (SET_SRC (exp)) == HImode + || GET_MODE (SET_SRC (exp)) == QImode) + switch (GET_CODE (SET_SRC (exp))) + { + case ASHIFTRT: case LSHIFTRT: + case ASHIFT: case LSHIFT: + /* Shifts on the 386 don't set the condition codes if the + shift count is zero. */ + if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT) + { + CC_STATUS_INIT; + break; + } + /* We assume that the CONST_INT is non-zero (this rtx would + have been deleted if it were zero. */ + + case PLUS: case MINUS: case NEG: + case AND: case IOR: case XOR: + cc_status.flags = CC_NO_OVERFLOW; + cc_status.value1 = SET_SRC (exp); + cc_status.value2 = SET_DEST (exp); + break; + + default: + CC_STATUS_INIT; + } + else + { + CC_STATUS_INIT; + } + } + else if (GET_CODE (exp) == PARALLEL + && GET_CODE (XVECEXP (exp, 0, 0)) == SET) + { + if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx) + return; + if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx) + { + CC_STATUS_INIT; + if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)))) + cc_status.flags |= CC_IN_80387; + else + cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0)); + return; + } + CC_STATUS_INIT; + } + else + { + CC_STATUS_INIT; + } +} + +/* Split one or more DImode RTL references into pairs of SImode + references. The RTL can be REG, offsettable MEM, integer constant, or + CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to + split and "num" is its length. lo_half and hi_half are output arrays + that parallel "operands". */ + +void +split_di (operands, num, lo_half, hi_half) + rtx operands[]; + int num; + rtx lo_half[], hi_half[]; +{ + while (num--) + { + if (GET_CODE (operands[num]) == REG) + { + lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num])); + hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1); + } + else if (CONSTANT_P (operands[num])) + { + split_double (operands[num], &lo_half[num], &hi_half[num]); + } + else if (offsettable_memref_p (operands[num])) + { + lo_half[num] = operands[num]; + hi_half[num] = adj_offsettable_operand (operands[num], 4); + } + else + abort(); + } +} + +/* Return 1 if this is a valid binary operation on a 387. + OP is the expression matched, and MODE is its mode. */ + +int +binary_387_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + + switch (GET_CODE (op)) + { + case PLUS: + case MINUS: + case MULT: + case DIV: + return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; + + default: + return 0; + } +} + +/* Return 1 if this is a valid conversion operation on a 387. + OP is the expression matched, and MODE is its mode. */ + +int +convert_387_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + + switch (GET_CODE (op)) + { + case FLOAT: + return GET_MODE (XEXP (op, 0)) == SImode; + + case FLOAT_EXTEND: + return mode == DFmode && GET_MODE (XEXP (op, 0)) == SFmode; + + default: + return 0; + } +} + +/* Return 1 if this is a valid shift or rotate operation on a 386. + OP is the expression matched, and MODE is its mode. */ + +int +shift_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + rtx operand = XEXP (op, 0); + + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + + if (GET_MODE (operand) != GET_MODE (op) + || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT) + return 0; + + return (GET_CODE (op) == ASHIFT + || GET_CODE (op) == ASHIFTRT + || GET_CODE (op) == LSHIFTRT + || GET_CODE (op) == ROTATE + || GET_CODE (op) == ROTATERT); +} + +/* Return 1 if OP is COMPARE rtx with mode VOIDmode. + MODE is not used. */ + +int +VOIDmode_compare_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode; +} + +/* Output code to perform a 387 binary operation in INSN, one of PLUS, + MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3] + is the expression of the binary operation. The output may either be + emitted here, or returned to the caller, like all output_* functions. + + There is no guarantee that the operands are the same mode, as they + might be within FLOAT or FLOAT_EXTEND expressions. */ + +char * +output_387_binary_op (insn, operands) + rtx insn; + rtx *operands; +{ + rtx temp; + char *base_op; + static char buf[100]; + + switch (GET_CODE (operands[3])) + { + case PLUS: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fiadd"; + else + base_op = "fadd"; + break; + + case MINUS: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fisub"; + else + base_op = "fsub"; + break; + + case MULT: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fimul"; + else + base_op = "fmul"; + break; + + case DIV: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fidiv"; + else + base_op = "fdiv"; + break; + + default: + abort (); + } + + strcpy (buf, base_op); + + switch (GET_CODE (operands[3])) + { + case MULT: + case PLUS: + if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) + { + temp = operands[2]; + operands[2] = operands[1]; + operands[1] = temp; + } + + if (GET_CODE (operands[2]) == MEM) + return strcat (buf, AS1 (%z2,%2)); + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); + RET; + } + else if (NON_STACK_REG_P (operands[2])) + { + output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); + RET; + } + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) + return strcat (buf, AS2 (p,%2,%0)); + + if (STACK_TOP_P (operands[0])) + return strcat (buf, AS2 (,%y2,%0)); + else + return strcat (buf, AS2 (,%2,%0)); + + case MINUS: + case DIV: + if (GET_CODE (operands[1]) == MEM) + return strcat (buf, AS1 (r%z1,%1)); + + if (GET_CODE (operands[2]) == MEM) + return strcat (buf, AS1 (%z2,%2)); + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1))); + RET; + } + else if (NON_STACK_REG_P (operands[2])) + { + output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); + RET; + } + + if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) + abort (); + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) + return strcat (buf, AS2 (rp,%2,%0)); + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) + return strcat (buf, AS2 (p,%1,%0)); + + if (STACK_TOP_P (operands[0])) + { + if (STACK_TOP_P (operands[1])) + return strcat (buf, AS2 (,%y2,%0)); + else + return strcat (buf, AS2 (r,%y1,%0)); + } + else if (STACK_TOP_P (operands[1])) + return strcat (buf, AS2 (,%1,%0)); + else + return strcat (buf, AS2 (r,%2,%0)); + + default: + abort (); + } +} + +/* Output code for INSN to convert a float to a signed int. OPERANDS + are the insn operands. The output may be SFmode or DFmode and the + input operand may be SImode or DImode. As a special case, make sure + that the 387 stack top dies if the output mode is DImode, because the + hardware requires this. */ + +char * +output_fix_trunc (insn, operands) + rtx insn; + rtx *operands; +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + rtx xops[2]; + + if (! STACK_TOP_P (operands[1]) || + (GET_MODE (operands[0]) == DImode && ! stack_top_dies)) + abort (); + + xops[0] = GEN_INT (12); + xops[1] = operands[4]; + + output_asm_insn (AS1 (fnstc%W2,%2), operands); + output_asm_insn (AS2 (mov%L2,%2,%4), operands); + output_asm_insn (AS2 (mov%B1,%0,%h1), xops); + output_asm_insn (AS2 (mov%L4,%4,%3), operands); + output_asm_insn (AS1 (fldc%W3,%3), operands); + + if (NON_STACK_REG_P (operands[0])) + output_to_reg (operands[0], stack_top_dies); + else if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + output_asm_insn (AS1 (fistp%z0,%0), operands); + else + output_asm_insn (AS1 (fist%z0,%0), operands); + } + else + abort (); + + return AS1 (fldc%W2,%2); +} + +/* Output code for INSN to compare OPERANDS. The two operands might + not have the same mode: one might be within a FLOAT or FLOAT_EXTEND + expression. If the compare is in mode CCFPEQmode, use an opcode that + will not fault if a qNaN is present. */ + +char * +output_float_compare (insn, operands) + rtx insn; + rtx *operands; +{ + int stack_top_dies; + rtx body = XVECEXP (PATTERN (insn), 0, 0); + int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode; + + if (! STACK_TOP_P (operands[0])) + abort (); + + stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (STACK_REG_P (operands[1]) + && stack_top_dies + && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[1]) != FIRST_STACK_REG) + { + /* If both the top of the 387 stack dies, and the other operand + is also a stack register that dies, then this must be a + `fcompp' float compare */ + + if (unordered_compare) + output_asm_insn ("fucompp", operands); + else + output_asm_insn ("fcompp", operands); + } + else + { + static char buf[100]; + + /* Decide if this is the integer or float compare opcode, or the + unordered float compare. */ + + if (unordered_compare) + strcpy (buf, "fucom"); + else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT) + strcpy (buf, "fcom"); + else + strcpy (buf, "ficom"); + + /* Modify the opcode if the 387 stack is to be popped. */ + + if (stack_top_dies) + strcat (buf, "p"); + + if (NON_STACK_REG_P (operands[1])) + output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); + else + output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands); + } + + /* Now retrieve the condition code. */ + + return output_fp_cc0_set (insn); +} + +/* Output opcodes to transfer the results of FP compare or test INSN + from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the + result of the compare or test is unordered, no comparison operator + succeeds except NE. Return an output template, if any. */ + +char * +output_fp_cc0_set (insn) + rtx insn; +{ + rtx xops[3]; + rtx unordered_label; + rtx next; + enum rtx_code code; + + xops[0] = gen_rtx (REG, HImode, 0); + output_asm_insn (AS1 (fnsts%W0,%0), xops); + + if (! TARGET_IEEE_FP) + return "sahf"; + + next = next_cc0_user (insn); + if (next == NULL_RTX) + abort (); + + if (GET_CODE (next) == JUMP_INSN + && GET_CODE (PATTERN (next)) == SET + && SET_DEST (PATTERN (next)) == pc_rtx + && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) + { + code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); + } + else if (GET_CODE (PATTERN (next)) == SET) + { + code = GET_CODE (SET_SRC (PATTERN (next))); + } + else + abort (); + + xops[0] = gen_rtx (REG, QImode, 0); + + switch (code) + { + case GT: + xops[1] = GEN_INT (0x45); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + /* je label */ + break; + + case LT: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x01); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* je label */ + break; + + case GE: + xops[1] = GEN_INT (0x05); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + /* je label */ + break; + + case LE: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS1 (dec%B0,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* jb label */ + break; + + case EQ: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* je label */ + break; + + case NE: + xops[1] = GEN_INT (0x44); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (xor%B0,%2,%h0), xops); + /* jne label */ + break; + + case GTU: + case LTU: + case GEU: + case LEU: + default: + abort (); + } + RET; +} + +#define MAX_386_STACK_LOCALS 2 + +static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; + +/* Clear stack slot assignments remembered from previous functions. + This is called from INIT_EXPANDERS once before RTL is emitted for each + function. */ + +void +clear_386_stack_locals () +{ + enum machine_mode mode; + int n; + + for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; + mode = (enum machine_mode) ((int) mode + 1)) + for (n = 0; n < MAX_386_STACK_LOCALS; n++) + i386_stack_locals[(int) mode][n] = NULL_RTX; +} + +/* Return a MEM corresponding to a stack slot with mode MODE. + Allocate a new slot if necessary. + + The RTL for a function can have several slots available: N is + which slot to use. */ + +rtx +assign_386_stack_local (mode, n) + enum machine_mode mode; + int n; +{ + if (n < 0 || n >= MAX_386_STACK_LOCALS) + abort (); + + if (i386_stack_locals[(int) mode][n] == NULL_RTX) + i386_stack_locals[(int) mode][n] + = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); + + return i386_stack_locals[(int) mode][n]; +} diff --git a/gnu/usr.bin/cc/lib/basic-block.h b/gnu/usr.bin/cc/lib/basic-block.h new file mode 100644 index 000000000000..fb0d10eed13c --- /dev/null +++ b/gnu/usr.bin/cc/lib/basic-block.h @@ -0,0 +1,68 @@ +/* Define control and data flow tables, and regsets. + Copyright (C) 1987 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* Number of bits in each actual element of a regset. */ + +#define REGSET_ELT_BITS HOST_BITS_PER_WIDE_INT + +/* Type to use for a regset element. Note that lots of code assumes + that the initial part of a regset that contains information on the + hard registers is the same format as a HARD_REG_SET. */ + +#define REGSET_ELT_TYPE HOST_WIDE_INT + +/* Define the type for a pointer to a set with a bit for each + (hard or pseudo) register. */ + +typedef REGSET_ELT_TYPE *regset; + +/* Size of a regset for the current function, + in (1) bytes and (2) elements. */ + +extern int regset_bytes; +extern int regset_size; + +/* Number of basic blocks in the current function. */ + +extern int n_basic_blocks; + +/* Index by basic block number, get first insn in the block. */ + +extern rtx *basic_block_head; + +/* Index by basic block number, get last insn in the block. */ + +extern rtx *basic_block_end; + +/* Index by basic block number, get address of regset + describing the registers live at the start of that block. */ + +extern regset *basic_block_live_at_start; + +/* Indexed by n, gives number of basic block that (REG n) is used in. + If the value is REG_BLOCK_GLOBAL (-2), + it means (REG n) is used in more than one basic block. + REG_BLOCK_UNKNOWN (-1) means it hasn't been seen yet so we don't know. + This information remains valid for the rest of the compilation + of the current function; it is used to control register allocation. */ + +#define REG_BLOCK_UNKNOWN -1 +#define REG_BLOCK_GLOBAL -2 +extern int *reg_basic_block; diff --git a/gnu/usr.bin/cc/lib/c-common.c b/gnu/usr.bin/cc/lib/c-common.c new file mode 100644 index 000000000000..7e0691e0079f --- /dev/null +++ b/gnu/usr.bin/cc/lib/c-common.c @@ -0,0 +1,1222 @@ +/* Subroutines shared by all languages that are variants of C. + Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include "config.h" +#include "tree.h" +#include "c-lex.h" +#include "c-tree.h" +#include "flags.h" +#include "obstack.h" +#include + +extern struct obstack permanent_obstack; + +/* Make bindings for __FUNCTION__ and __PRETTY_FUNCTION__. */ + +void +declare_function_name () +{ + tree decl, type, init; + char *name, *printable_name; + int len; + + if (current_function_decl == NULL) + { + name = ""; + printable_name = "top level"; + } + else + { + char *kind = "function"; + if (TREE_CODE (TREE_TYPE (current_function_decl)) == METHOD_TYPE) + kind = "method"; + /* Allow functions to be nameless (such as artificial ones). */ + if (DECL_NAME (current_function_decl)) + name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl)); + else + name = ""; + printable_name = (*decl_printable_name) (current_function_decl, &kind); + } + + /* If the default size of char arrays isn't big enough for the name, + make a bigger one. */ + len = strlen (name) + 1; + type = char_array_type_node; + if (TREE_INT_CST_LOW (TYPE_MAX_VALUE (TREE_TYPE (char_array_type_node))) + < len) + type = build_array_type (char_type_node, + build_index_type (build_int_2 (len, 0))); + + push_obstacks_nochange (); + decl = build_decl (VAR_DECL, get_identifier ("__FUNCTION__"), type); + TREE_STATIC (decl) = 1; + TREE_READONLY (decl) = 1; + DECL_SOURCE_LINE (decl) = 0; + DECL_IN_SYSTEM_HEADER (decl) = 1; + DECL_IGNORED_P (decl) = 1; + init = build_string (len, name); + TREE_TYPE (init) = type; + DECL_INITIAL (decl) = init; + finish_decl (pushdecl (decl), init, NULL_TREE); + + len = strlen (printable_name) + 1; + type = char_array_type_node; + if (TREE_INT_CST_LOW (TYPE_MAX_VALUE (TREE_TYPE (char_array_type_node))) + < len) + type = build_array_type (char_type_node, + build_index_type (build_int_2 (len, 0))); + + push_obstacks_nochange (); + decl = build_decl (VAR_DECL, get_identifier ("__PRETTY_FUNCTION__"), type); + TREE_STATIC (decl) = 1; + TREE_READONLY (decl) = 1; + DECL_SOURCE_LINE (decl) = 0; + DECL_IN_SYSTEM_HEADER (decl) = 1; + DECL_IGNORED_P (decl) = 1; + init = build_string (len, printable_name); + TREE_TYPE (init) = type; + DECL_INITIAL (decl) = init; + finish_decl (pushdecl (decl), init, NULL_TREE); +} + +/* Given a chain of STRING_CST nodes, + concatenate them into one STRING_CST + and give it a suitable array-of-chars data type. */ + +tree +combine_strings (strings) + tree strings; +{ + register tree value, t; + register int length = 1; + int wide_length = 0; + int wide_flag = 0; + int wchar_bytes = TYPE_PRECISION (wchar_type_node) / BITS_PER_UNIT; + int nchars; + + if (TREE_CHAIN (strings)) + { + /* More than one in the chain, so concatenate. */ + register char *p, *q; + + /* Don't include the \0 at the end of each substring, + except for the last one. + Count wide strings and ordinary strings separately. */ + for (t = strings; t; t = TREE_CHAIN (t)) + { + if (TREE_TYPE (t) == wchar_array_type_node) + { + wide_length += (TREE_STRING_LENGTH (t) - wchar_bytes); + wide_flag = 1; + } + else + length += (TREE_STRING_LENGTH (t) - 1); + } + + /* If anything is wide, the non-wides will be converted, + which makes them take more space. */ + if (wide_flag) + length = length * wchar_bytes + wide_length; + + p = savealloc (length); + + /* Copy the individual strings into the new combined string. + If the combined string is wide, convert the chars to ints + for any individual strings that are not wide. */ + + q = p; + for (t = strings; t; t = TREE_CHAIN (t)) + { + int len = (TREE_STRING_LENGTH (t) + - ((TREE_TYPE (t) == wchar_array_type_node) + ? wchar_bytes : 1)); + if ((TREE_TYPE (t) == wchar_array_type_node) == wide_flag) + { + bcopy (TREE_STRING_POINTER (t), q, len); + q += len; + } + else + { + int i; + for (i = 0; i < len; i++) + ((int *) q)[i] = TREE_STRING_POINTER (t)[i]; + q += len * wchar_bytes; + } + } + if (wide_flag) + { + int i; + for (i = 0; i < wchar_bytes; i++) + *q++ = 0; + } + else + *q = 0; + + value = make_node (STRING_CST); + TREE_STRING_POINTER (value) = p; + TREE_STRING_LENGTH (value) = length; + TREE_CONSTANT (value) = 1; + } + else + { + value = strings; + length = TREE_STRING_LENGTH (value); + if (TREE_TYPE (value) == wchar_array_type_node) + wide_flag = 1; + } + + /* Compute the number of elements, for the array type. */ + nchars = wide_flag ? length / wchar_bytes : length; + + /* Create the array type for the string constant. + -Wwrite-strings says make the string constant an array of const char + so that copying it to a non-const pointer will get a warning. */ + if (warn_write_strings + && (! flag_traditional && ! flag_writable_strings)) + { + tree elements + = build_type_variant (wide_flag ? wchar_type_node : char_type_node, + 1, 0); + TREE_TYPE (value) + = build_array_type (elements, + build_index_type (build_int_2 (nchars - 1, 0))); + } + else + TREE_TYPE (value) + = build_array_type (wide_flag ? wchar_type_node : char_type_node, + build_index_type (build_int_2 (nchars - 1, 0))); + TREE_CONSTANT (value) = 1; + TREE_STATIC (value) = 1; + return value; +} + +/* Process the attributes listed in ATTRIBUTES + and install them in DECL. */ + +void +decl_attributes (decl, attributes) + tree decl, attributes; +{ + tree a; + for (a = attributes; a; a = TREE_CHAIN (a)) + if (TREE_VALUE (a) == get_identifier ("packed")) + { + if (TREE_CODE (decl) == FIELD_DECL) + DECL_PACKED (decl) = 1; + /* We can't set DECL_PACKED for a VAR_DECL, because the bit is + used for DECL_REGISTER. It wouldn't mean anything anyway. */ + } + else if (TREE_VALUE (a) != 0 + && TREE_CODE (TREE_VALUE (a)) == TREE_LIST + && TREE_PURPOSE (TREE_VALUE (a)) == get_identifier ("mode")) + { + int i; + char *specified_name + = IDENTIFIER_POINTER (TREE_VALUE (TREE_VALUE (a))); + + /* Give this decl a type with the specified mode. */ + for (i = 0; i < NUM_MACHINE_MODES; i++) + if (!strcmp (specified_name, GET_MODE_NAME (i))) + { + tree type + = type_for_mode (i, TREE_UNSIGNED (TREE_TYPE (decl))); + if (type != 0) + { + TREE_TYPE (decl) = type; + DECL_SIZE (decl) = 0; + layout_decl (decl, 0); + } + else + error ("no data type for mode `%s'", specified_name); + break; + } + if (i == NUM_MACHINE_MODES) + error ("unknown machine mode `%s'", specified_name); + } + else if (TREE_VALUE (a) != 0 + && TREE_CODE (TREE_VALUE (a)) == TREE_LIST + && TREE_PURPOSE (TREE_VALUE (a)) == get_identifier ("aligned")) + { + int align = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (a))) + * BITS_PER_UNIT; + + if (exact_log2 (align) == -1) + error_with_decl (decl, + "requested alignment of `%s' is not a power of 2"); + else if (TREE_CODE (decl) != VAR_DECL + && TREE_CODE (decl) != FIELD_DECL) + error_with_decl (decl, + "alignment specified for `%s'"); + else + DECL_ALIGN (decl) = align; + } + else if (TREE_VALUE (a) != 0 + && TREE_CODE (TREE_VALUE (a)) == TREE_LIST + && TREE_PURPOSE (TREE_VALUE (a)) == get_identifier ("format")) + { + tree list = TREE_VALUE (TREE_VALUE (a)); + tree format_type = TREE_PURPOSE (list); + int format_num = TREE_INT_CST_LOW (TREE_PURPOSE (TREE_VALUE (list))); + int first_arg_num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list))); + int is_scan; + tree argument; + int arg_num; + + if (TREE_CODE (decl) != FUNCTION_DECL) + { + error_with_decl (decl, + "argument format specified for non-function `%s'"); + return; + } + + if (format_type == get_identifier ("printf")) + is_scan = 0; + else if (format_type == get_identifier ("scanf")) + is_scan = 1; + else + { + error_with_decl (decl, "unrecognized format specifier for `%s'"); + return; + } + + if (first_arg_num != 0 && first_arg_num <= format_num) + { + error_with_decl (decl, + "format string arg follows the args to be formatted, for `%s'"); + return; + } + + /* Verify that the format_num argument is actually a string, in case + the format attribute is in error. */ + argument = TYPE_ARG_TYPES (TREE_TYPE (decl)); + for (arg_num = 1; ; ++arg_num) + { + if (argument == 0 || arg_num == format_num) + break; + argument = TREE_CHAIN (argument); + } + if (! argument + || TREE_CODE (TREE_VALUE (argument)) != POINTER_TYPE + || (TYPE_MAIN_VARIANT (TREE_TYPE (TREE_VALUE (argument))) + != char_type_node)) + { + error_with_decl (decl, + "format string arg not a string type, for `%s'"); + return; + } + if (first_arg_num != 0) + { + /* Verify that first_arg_num points to the last arg, the ... */ + while (argument) + arg_num++, argument = TREE_CHAIN (argument); + if (arg_num != first_arg_num) + { + error_with_decl (decl, + "args to be formatted is not ..., for `%s'"); + return; + } + } + + record_format_info (DECL_NAME (decl), is_scan, format_num, + first_arg_num); + } +} + +/* Print a warning if a constant expression had overflow in folding. + Invoke this function on every expression that the language + requires to be a constant expression. + Note the ANSI C standard says it is erroneous for a + constant expression to overflow. */ + +void +constant_expression_warning (value) + tree value; +{ + if (TREE_CODE (value) == INTEGER_CST && TREE_CONSTANT_OVERFLOW (value)) + { + /* ??? This is a warning, not a pedwarn, in 2.4, + because it happens in contexts that are not + "constant expressions" in ANSI C. + Fix the problem differently in 2.5. */ + warning ("overflow in constant expression"); + /* Suppress duplicate warnings. */ + TREE_CONSTANT_OVERFLOW (value) = 0; + } +} + +/* Print a warning if an expression had overflow in folding. + Invoke this function on every expression that + (1) appears in the source code, and + (2) might be a constant expression that overflowed, and + (3) is not already checked by convert_and_check; + however, do not invoke this function on operands of explicit casts. */ + +void +overflow_warning (value) + tree value; +{ + if (TREE_CODE (value) == INTEGER_CST && TREE_CONSTANT_OVERFLOW (value)) + { + /* ??? This is a warning, not a pedwarn, in 2.4, + because it happens in contexts that are not + "constant expressions" in ANSI C. + Fix the problem differently in 2.5. */ + warning ("integer overflow in expression"); + TREE_CONSTANT_OVERFLOW (value) = 0; + } +} + +/* Print a warning if a large constant is truncated to unsigned, + or if -Wconversion is used and a constant < 0 is converted to unsigned. + Invoke this function on every expression that might be implicitly + converted to an unsigned type. */ + +void +unsigned_conversion_warning (result, operand) + tree result, operand; +{ + if (TREE_CODE (operand) == INTEGER_CST + && TREE_CODE (TREE_TYPE (result)) == INTEGER_TYPE + && TREE_UNSIGNED (TREE_TYPE (result)) + && !int_fits_type_p (operand, TREE_TYPE (result))) + { + if (!int_fits_type_p (operand, signed_type (TREE_TYPE (result)))) + /* This detects cases like converting -129 or 256 to unsigned char. */ + pedwarn ("large integer implicitly truncated to unsigned type"); + else if (warn_conversion) + pedwarn ("negative integer implicitly converted to unsigned type"); + } +} + +/* Convert EXPR to TYPE, warning about conversion problems with constants. + Invoke this function on every expression that is converted implicitly, + i.e. because of language rules and not because of an explicit cast. */ + +tree +convert_and_check (type, expr) + tree type, expr; +{ + tree t = convert (type, expr); + if (TREE_CODE (t) == INTEGER_CST) + { + if (TREE_UNSIGNED (TREE_TYPE (expr)) + && !TREE_UNSIGNED (type) + && TREE_CODE (TREE_TYPE (expr)) == INTEGER_TYPE + && TYPE_PRECISION (type) == TYPE_PRECISION (TREE_TYPE (expr))) + /* No warning for converting 0x80000000 to int. */ + TREE_CONSTANT_OVERFLOW (t) = 0; + else if (TREE_CONSTANT_OVERFLOW (t)) + { + /* ??? This is a warning, not a pedwarn, in 2.4, + because it happens in contexts that are not + "constant expressions" in ANSI C. + Fix the problem differently in 2.5. */ + warning ("overflow in implicit constant conversion"); + TREE_CONSTANT_OVERFLOW (t) = 0; + } + else + unsigned_conversion_warning (t, expr); + } + return t; +} + +void +c_expand_expr_stmt (expr) + tree expr; +{ + /* Do default conversion if safe and possibly important, + in case within ({...}). */ + if ((TREE_CODE (TREE_TYPE (expr)) == ARRAY_TYPE && lvalue_p (expr)) + || TREE_CODE (TREE_TYPE (expr)) == FUNCTION_TYPE) + expr = default_conversion (expr); + + if (TREE_TYPE (expr) != error_mark_node + && TYPE_SIZE (TREE_TYPE (expr)) == 0 + && TREE_CODE (TREE_TYPE (expr)) != ARRAY_TYPE) + error ("expression statement has incomplete type"); + + expand_expr_stmt (expr); +} + +/* Validate the expression after `case' and apply default promotions. */ + +tree +check_case_value (value) + tree value; +{ + if (value == NULL_TREE) + return value; + + /* Strip NON_LVALUE_EXPRs since we aren't using as an lvalue. */ + STRIP_TYPE_NOPS (value); + + if (TREE_CODE (value) != INTEGER_CST + && value != error_mark_node) + { + error ("case label does not reduce to an integer constant"); + value = error_mark_node; + } + else + /* Promote char or short to int. */ + value = default_conversion (value); + + constant_expression_warning (value); + + return value; +} + +/* Return an integer type with BITS bits of precision, + that is unsigned if UNSIGNEDP is nonzero, otherwise signed. */ + +tree +type_for_size (bits, unsignedp) + unsigned bits; + int unsignedp; +{ + if (bits == TYPE_PRECISION (signed_char_type_node)) + return unsignedp ? unsigned_char_type_node : signed_char_type_node; + + if (bits == TYPE_PRECISION (short_integer_type_node)) + return unsignedp ? short_unsigned_type_node : short_integer_type_node; + + if (bits == TYPE_PRECISION (integer_type_node)) + return unsignedp ? unsigned_type_node : integer_type_node; + + if (bits == TYPE_PRECISION (long_integer_type_node)) + return unsignedp ? long_unsigned_type_node : long_integer_type_node; + + if (bits == TYPE_PRECISION (long_long_integer_type_node)) + return (unsignedp ? long_long_unsigned_type_node + : long_long_integer_type_node); + + if (bits <= TYPE_PRECISION (intQI_type_node)) + return unsignedp ? unsigned_intQI_type_node : intQI_type_node; + + if (bits <= TYPE_PRECISION (intHI_type_node)) + return unsignedp ? unsigned_intHI_type_node : intHI_type_node; + + if (bits <= TYPE_PRECISION (intSI_type_node)) + return unsignedp ? unsigned_intSI_type_node : intSI_type_node; + + if (bits <= TYPE_PRECISION (intDI_type_node)) + return unsignedp ? unsigned_intDI_type_node : intDI_type_node; + + return 0; +} + +/* Return a data type that has machine mode MODE. + If the mode is an integer, + then UNSIGNEDP selects between signed and unsigned types. */ + +tree +type_for_mode (mode, unsignedp) + enum machine_mode mode; + int unsignedp; +{ + if (mode == TYPE_MODE (signed_char_type_node)) + return unsignedp ? unsigned_char_type_node : signed_char_type_node; + + if (mode == TYPE_MODE (short_integer_type_node)) + return unsignedp ? short_unsigned_type_node : short_integer_type_node; + + if (mode == TYPE_MODE (integer_type_node)) + return unsignedp ? unsigned_type_node : integer_type_node; + + if (mode == TYPE_MODE (long_integer_type_node)) + return unsignedp ? long_unsigned_type_node : long_integer_type_node; + + if (mode == TYPE_MODE (long_long_integer_type_node)) + return unsignedp ? long_long_unsigned_type_node : long_long_integer_type_node; + + if (mode == TYPE_MODE (intQI_type_node)) + return unsignedp ? unsigned_intQI_type_node : intQI_type_node; + + if (mode == TYPE_MODE (intHI_type_node)) + return unsignedp ? unsigned_intHI_type_node : intHI_type_node; + + if (mode == TYPE_MODE (intSI_type_node)) + return unsignedp ? unsigned_intSI_type_node : intSI_type_node; + + if (mode == TYPE_MODE (intDI_type_node)) + return unsignedp ? unsigned_intDI_type_node : intDI_type_node; + + if (mode == TYPE_MODE (float_type_node)) + return float_type_node; + + if (mode == TYPE_MODE (double_type_node)) + return double_type_node; + + if (mode == TYPE_MODE (long_double_type_node)) + return long_double_type_node; + + if (mode == TYPE_MODE (build_pointer_type (char_type_node))) + return build_pointer_type (char_type_node); + + if (mode == TYPE_MODE (build_pointer_type (integer_type_node))) + return build_pointer_type (integer_type_node); + + return 0; +} + +/* Print an error message for invalid operands to arith operation CODE. + NOP_EXPR is used as a special case (see truthvalue_conversion). */ + +void +binary_op_error (code) + enum tree_code code; +{ + register char *opname; + switch (code) + { + case NOP_EXPR: + error ("invalid truth-value expression"); + return; + + case PLUS_EXPR: + opname = "+"; break; + case MINUS_EXPR: + opname = "-"; break; + case MULT_EXPR: + opname = "*"; break; + case MAX_EXPR: + opname = "max"; break; + case MIN_EXPR: + opname = "min"; break; + case EQ_EXPR: + opname = "=="; break; + case NE_EXPR: + opname = "!="; break; + case LE_EXPR: + opname = "<="; break; + case GE_EXPR: + opname = ">="; break; + case LT_EXPR: + opname = "<"; break; + case GT_EXPR: + opname = ">"; break; + case LSHIFT_EXPR: + opname = "<<"; break; + case RSHIFT_EXPR: + opname = ">>"; break; + case TRUNC_MOD_EXPR: + case FLOOR_MOD_EXPR: + opname = "%"; break; + case TRUNC_DIV_EXPR: + case FLOOR_DIV_EXPR: + opname = "/"; break; + case BIT_AND_EXPR: + opname = "&"; break; + case BIT_IOR_EXPR: + opname = "|"; break; + case TRUTH_ANDIF_EXPR: + opname = "&&"; break; + case TRUTH_ORIF_EXPR: + opname = "||"; break; + case BIT_XOR_EXPR: + opname = "^"; break; + case LROTATE_EXPR: + case RROTATE_EXPR: + opname = "rotate"; break; + } + error ("invalid operands to binary %s", opname); +} + +/* Subroutine of build_binary_op, used for comparison operations. + See if the operands have both been converted from subword integer types + and, if so, perhaps change them both back to their original type. + + The arguments of this function are all pointers to local variables + of build_binary_op: OP0_PTR is &OP0, OP1_PTR is &OP1, + RESTYPE_PTR is &RESULT_TYPE and RESCODE_PTR is &RESULTCODE. + + If this function returns nonzero, it means that the comparison has + a constant value. What this function returns is an expression for + that value. */ + +tree +shorten_compare (op0_ptr, op1_ptr, restype_ptr, rescode_ptr) + tree *op0_ptr, *op1_ptr; + tree *restype_ptr; + enum tree_code *rescode_ptr; +{ + register tree type; + tree op0 = *op0_ptr; + tree op1 = *op1_ptr; + int unsignedp0, unsignedp1; + int real1, real2; + tree primop0, primop1; + enum tree_code code = *rescode_ptr; + + /* Throw away any conversions to wider types + already present in the operands. */ + + primop0 = get_narrower (op0, &unsignedp0); + primop1 = get_narrower (op1, &unsignedp1); + + /* Handle the case that OP0 does not *contain* a conversion + but it *requires* conversion to FINAL_TYPE. */ + + if (op0 == primop0 && TREE_TYPE (op0) != *restype_ptr) + unsignedp0 = TREE_UNSIGNED (TREE_TYPE (op0)); + if (op1 == primop1 && TREE_TYPE (op1) != *restype_ptr) + unsignedp1 = TREE_UNSIGNED (TREE_TYPE (op1)); + + /* If one of the operands must be floated, we cannot optimize. */ + real1 = TREE_CODE (TREE_TYPE (primop0)) == REAL_TYPE; + real2 = TREE_CODE (TREE_TYPE (primop1)) == REAL_TYPE; + + /* If first arg is constant, swap the args (changing operation + so value is preserved), for canonicalization. */ + + if (TREE_CONSTANT (primop0)) + { + register tree tem = primop0; + register int temi = unsignedp0; + primop0 = primop1; + primop1 = tem; + tem = op0; + op0 = op1; + op1 = tem; + *op0_ptr = op0; + *op1_ptr = op1; + unsignedp0 = unsignedp1; + unsignedp1 = temi; + temi = real1; + real1 = real2; + real2 = temi; + + switch (code) + { + case LT_EXPR: + code = GT_EXPR; + break; + case GT_EXPR: + code = LT_EXPR; + break; + case LE_EXPR: + code = GE_EXPR; + break; + case GE_EXPR: + code = LE_EXPR; + break; + } + *rescode_ptr = code; + } + + /* If comparing an integer against a constant more bits wide, + maybe we can deduce a value of 1 or 0 independent of the data. + Or else truncate the constant now + rather than extend the variable at run time. + + This is only interesting if the constant is the wider arg. + Also, it is not safe if the constant is unsigned and the + variable arg is signed, since in this case the variable + would be sign-extended and then regarded as unsigned. + Our technique fails in this case because the lowest/highest + possible unsigned results don't follow naturally from the + lowest/highest possible values of the variable operand. + For just EQ_EXPR and NE_EXPR there is another technique that + could be used: see if the constant can be faithfully represented + in the other operand's type, by truncating it and reextending it + and see if that preserves the constant's value. */ + + if (!real1 && !real2 + && TREE_CODE (primop1) == INTEGER_CST + && TYPE_PRECISION (TREE_TYPE (primop0)) < TYPE_PRECISION (*restype_ptr)) + { + int min_gt, max_gt, min_lt, max_lt; + tree maxval, minval; + /* 1 if comparison is nominally unsigned. */ + int unsignedp = TREE_UNSIGNED (*restype_ptr); + tree val; + + type = signed_or_unsigned_type (unsignedp0, TREE_TYPE (primop0)); + + maxval = TYPE_MAX_VALUE (type); + minval = TYPE_MIN_VALUE (type); + + if (unsignedp && !unsignedp0) + *restype_ptr = signed_type (*restype_ptr); + + if (TREE_TYPE (primop1) != *restype_ptr) + primop1 = convert (*restype_ptr, primop1); + if (type != *restype_ptr) + { + minval = convert (*restype_ptr, minval); + maxval = convert (*restype_ptr, maxval); + } + + if (unsignedp && unsignedp0) + { + min_gt = INT_CST_LT_UNSIGNED (primop1, minval); + max_gt = INT_CST_LT_UNSIGNED (primop1, maxval); + min_lt = INT_CST_LT_UNSIGNED (minval, primop1); + max_lt = INT_CST_LT_UNSIGNED (maxval, primop1); + } + else + { + min_gt = INT_CST_LT (primop1, minval); + max_gt = INT_CST_LT (primop1, maxval); + min_lt = INT_CST_LT (minval, primop1); + max_lt = INT_CST_LT (maxval, primop1); + } + + val = 0; + /* This used to be a switch, but Genix compiler can't handle that. */ + if (code == NE_EXPR) + { + if (max_lt || min_gt) + val = integer_one_node; + } + else if (code == EQ_EXPR) + { + if (max_lt || min_gt) + val = integer_zero_node; + } + else if (code == LT_EXPR) + { + if (max_lt) + val = integer_one_node; + if (!min_lt) + val = integer_zero_node; + } + else if (code == GT_EXPR) + { + if (min_gt) + val = integer_one_node; + if (!max_gt) + val = integer_zero_node; + } + else if (code == LE_EXPR) + { + if (!max_gt) + val = integer_one_node; + if (min_gt) + val = integer_zero_node; + } + else if (code == GE_EXPR) + { + if (!min_lt) + val = integer_one_node; + if (max_lt) + val = integer_zero_node; + } + + /* If primop0 was sign-extended and unsigned comparison specd, + we did a signed comparison above using the signed type bounds. + But the comparison we output must be unsigned. + + Also, for inequalities, VAL is no good; but if the signed + comparison had *any* fixed result, it follows that the + unsigned comparison just tests the sign in reverse + (positive values are LE, negative ones GE). + So we can generate an unsigned comparison + against an extreme value of the signed type. */ + + if (unsignedp && !unsignedp0) + { + if (val != 0) + switch (code) + { + case LT_EXPR: + case GE_EXPR: + primop1 = TYPE_MIN_VALUE (type); + val = 0; + break; + + case LE_EXPR: + case GT_EXPR: + primop1 = TYPE_MAX_VALUE (type); + val = 0; + break; + } + type = unsigned_type (type); + } + + if (!max_gt && !unsignedp0) + { + /* This is the case of (char)x >?< 0x80, which people used to use + expecting old C compilers to change the 0x80 into -0x80. */ + if (val == integer_zero_node) + warning ("comparison is always 0 due to limited range of data type"); + if (val == integer_one_node) + warning ("comparison is always 1 due to limited range of data type"); + } + + if (!min_lt && unsignedp0) + { + /* This is the case of (unsigned char)x >?< -1 or < 0. */ + if (val == integer_zero_node) + warning ("comparison is always 0 due to limited range of data type"); + if (val == integer_one_node) + warning ("comparison is always 1 due to limited range of data type"); + } + + if (val != 0) + { + /* Don't forget to evaluate PRIMOP0 if it has side effects. */ + if (TREE_SIDE_EFFECTS (primop0)) + return build (COMPOUND_EXPR, TREE_TYPE (val), primop0, val); + return val; + } + + /* Value is not predetermined, but do the comparison + in the type of the operand that is not constant. + TYPE is already properly set. */ + } + else if (real1 && real2 + && (TYPE_PRECISION (TREE_TYPE (primop0)) + == TYPE_PRECISION (TREE_TYPE (primop1)))) + type = TREE_TYPE (primop0); + + /* If args' natural types are both narrower than nominal type + and both extend in the same manner, compare them + in the type of the wider arg. + Otherwise must actually extend both to the nominal + common type lest different ways of extending + alter the result. + (eg, (short)-1 == (unsigned short)-1 should be 0.) */ + + else if (unsignedp0 == unsignedp1 && real1 == real2 + && TYPE_PRECISION (TREE_TYPE (primop0)) < TYPE_PRECISION (*restype_ptr) + && TYPE_PRECISION (TREE_TYPE (primop1)) < TYPE_PRECISION (*restype_ptr)) + { + type = common_type (TREE_TYPE (primop0), TREE_TYPE (primop1)); + type = signed_or_unsigned_type (unsignedp0 + || TREE_UNSIGNED (*restype_ptr), + type); + /* Make sure shorter operand is extended the right way + to match the longer operand. */ + primop0 = convert (signed_or_unsigned_type (unsignedp0, TREE_TYPE (primop0)), + primop0); + primop1 = convert (signed_or_unsigned_type (unsignedp1, TREE_TYPE (primop1)), + primop1); + } + else + { + /* Here we must do the comparison on the nominal type + using the args exactly as we received them. */ + type = *restype_ptr; + primop0 = op0; + primop1 = op1; + + if (!real1 && !real2 && integer_zerop (primop1) + && TREE_UNSIGNED (TREE_TYPE (primop0))) + { + tree value = 0; + switch (code) + { + case GE_EXPR: + if (extra_warnings) + warning ("unsigned value >= 0 is always 1"); + value = integer_one_node; + break; + + case LT_EXPR: + if (extra_warnings) + warning ("unsigned value < 0 is always 0"); + value = integer_zero_node; + } + + if (value != 0) + { + /* Don't forget to evaluate PRIMOP0 if it has side effects. */ + if (TREE_SIDE_EFFECTS (primop0)) + return build (COMPOUND_EXPR, TREE_TYPE (value), + primop0, value); + return value; + } + } + } + + *op0_ptr = convert (type, primop0); + *op1_ptr = convert (type, primop1); + + *restype_ptr = integer_type_node; + + return 0; +} + +/* Prepare expr to be an argument of a TRUTH_NOT_EXPR, + or validate its data type for an `if' or `while' statement or ?..: exp. + + This preparation consists of taking the ordinary + representation of an expression expr and producing a valid tree + boolean expression describing whether expr is nonzero. We could + simply always do build_binary_op (NE_EXPR, expr, integer_zero_node, 1), + but we optimize comparisons, &&, ||, and !. + + The resulting type should always be `integer_type_node'. */ + +tree +truthvalue_conversion (expr) + tree expr; +{ + register enum tree_code code; + + if (TREE_CODE (expr) == ERROR_MARK) + return expr; + +#if 0 /* This appears to be wrong for C++. */ + /* These really should return error_mark_node after 2.4 is stable. + But not all callers handle ERROR_MARK properly. */ + switch (TREE_CODE (TREE_TYPE (expr))) + { + case RECORD_TYPE: + error ("struct type value used where scalar is required"); + return integer_zero_node; + + case UNION_TYPE: + error ("union type value used where scalar is required"); + return integer_zero_node; + + case ARRAY_TYPE: + error ("array type value used where scalar is required"); + return integer_zero_node; + + default: + break; + } +#endif /* 0 */ + + switch (TREE_CODE (expr)) + { + /* It is simpler and generates better code to have only TRUTH_*_EXPR + or comparison expressions as truth values at this level. */ +#if 0 + case COMPONENT_REF: + /* A one-bit unsigned bit-field is already acceptable. */ + if (1 == TREE_INT_CST_LOW (DECL_SIZE (TREE_OPERAND (expr, 1))) + && TREE_UNSIGNED (TREE_OPERAND (expr, 1))) + return expr; + break; +#endif + + case EQ_EXPR: + /* It is simpler and generates better code to have only TRUTH_*_EXPR + or comparison expressions as truth values at this level. */ +#if 0 + if (integer_zerop (TREE_OPERAND (expr, 1))) + return build_unary_op (TRUTH_NOT_EXPR, TREE_OPERAND (expr, 0), 0); +#endif + case NE_EXPR: case LE_EXPR: case GE_EXPR: case LT_EXPR: case GT_EXPR: + case TRUTH_ANDIF_EXPR: + case TRUTH_ORIF_EXPR: + case TRUTH_AND_EXPR: + case TRUTH_OR_EXPR: + case TRUTH_XOR_EXPR: + case ERROR_MARK: + return expr; + + case INTEGER_CST: + return integer_zerop (expr) ? integer_zero_node : integer_one_node; + + case REAL_CST: + return real_zerop (expr) ? integer_zero_node : integer_one_node; + + case ADDR_EXPR: + if (TREE_SIDE_EFFECTS (TREE_OPERAND (expr, 0))) + return build (COMPOUND_EXPR, integer_type_node, + TREE_OPERAND (expr, 0), integer_one_node); + else + return integer_one_node; + + case COMPLEX_EXPR: + return build_binary_op ((TREE_SIDE_EFFECTS (TREE_OPERAND (expr, 1)) + ? TRUTH_AND_EXPR : TRUTH_ANDIF_EXPR), + truthvalue_conversion (TREE_OPERAND (expr, 0)), + truthvalue_conversion (TREE_OPERAND (expr, 1)), + 0); + + case NEGATE_EXPR: + case ABS_EXPR: + case FLOAT_EXPR: + case FFS_EXPR: + /* These don't change whether an object is non-zero or zero. */ + return truthvalue_conversion (TREE_OPERAND (expr, 0)); + + case LROTATE_EXPR: + case RROTATE_EXPR: + /* These don't change whether an object is zero or non-zero, but + we can't ignore them if their second arg has side-effects. */ + if (TREE_SIDE_EFFECTS (TREE_OPERAND (expr, 1))) + return build (COMPOUND_EXPR, integer_type_node, TREE_OPERAND (expr, 1), + truthvalue_conversion (TREE_OPERAND (expr, 0))); + else + return truthvalue_conversion (TREE_OPERAND (expr, 0)); + + case COND_EXPR: + /* Distribute the conversion into the arms of a COND_EXPR. */ + return fold (build (COND_EXPR, integer_type_node, TREE_OPERAND (expr, 0), + truthvalue_conversion (TREE_OPERAND (expr, 1)), + truthvalue_conversion (TREE_OPERAND (expr, 2)))); + + case CONVERT_EXPR: + /* Don't cancel the effect of a CONVERT_EXPR from a REFERENCE_TYPE, + since that affects how `default_conversion' will behave. */ + if (TREE_CODE (TREE_TYPE (expr)) == REFERENCE_TYPE + || TREE_CODE (TREE_TYPE (TREE_OPERAND (expr, 0))) == REFERENCE_TYPE) + break; + /* fall through... */ + case NOP_EXPR: + /* If this is widening the argument, we can ignore it. */ + if (TYPE_PRECISION (TREE_TYPE (expr)) + >= TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (expr, 0)))) + return truthvalue_conversion (TREE_OPERAND (expr, 0)); + break; + + case MINUS_EXPR: + /* With IEEE arithmetic, x - x may not equal 0, so we can't optimize + this case. */ + if (TARGET_FLOAT_FORMAT == IEEE_FLOAT_FORMAT + && TREE_CODE (TREE_TYPE (expr)) == REAL_TYPE) + break; + /* fall through... */ + case BIT_XOR_EXPR: + /* This and MINUS_EXPR can be changed into a comparison of the + two objects. */ + if (TREE_TYPE (TREE_OPERAND (expr, 0)) + == TREE_TYPE (TREE_OPERAND (expr, 1))) + return build_binary_op (NE_EXPR, TREE_OPERAND (expr, 0), + TREE_OPERAND (expr, 1), 1); + return build_binary_op (NE_EXPR, TREE_OPERAND (expr, 0), + fold (build1 (NOP_EXPR, + TREE_TYPE (TREE_OPERAND (expr, 0)), + TREE_OPERAND (expr, 1))), 1); + + case MODIFY_EXPR: + if (warn_parentheses && C_EXP_ORIGINAL_CODE (expr) == MODIFY_EXPR) + warning ("suggest parentheses around assignment used as truth value"); + break; + } + + if (TREE_CODE (TREE_TYPE (expr)) == COMPLEX_TYPE) + return (build_binary_op + ((TREE_SIDE_EFFECTS (expr) + ? TRUTH_AND_EXPR : TRUTH_ANDIF_EXPR), + truthvalue_conversion (build_unary_op (REALPART_EXPR, expr, 0)), + truthvalue_conversion (build_unary_op (IMAGPART_EXPR, expr, 0)), + 0)); + + return build_binary_op (NE_EXPR, expr, integer_zero_node, 1); +} + +/* Read the rest of a #-directive from input stream FINPUT. + In normal use, the directive name and the white space after it + have already been read, so they won't be included in the result. + We allow for the fact that the directive line may contain + a newline embedded within a character or string literal which forms + a part of the directive. + + The value is a string in a reusable buffer. It remains valid + only until the next time this function is called. */ + +char * +get_directive_line (finput) + register FILE *finput; +{ + static char *directive_buffer = NULL; + static unsigned buffer_length = 0; + register char *p; + register char *buffer_limit; + register int looking_for = 0; + register int char_escaped = 0; + + if (buffer_length == 0) + { + directive_buffer = (char *)xmalloc (128); + buffer_length = 128; + } + + buffer_limit = &directive_buffer[buffer_length]; + + for (p = directive_buffer; ; ) + { + int c; + + /* Make buffer bigger if it is full. */ + if (p >= buffer_limit) + { + register unsigned bytes_used = (p - directive_buffer); + + buffer_length *= 2; + directive_buffer + = (char *)xrealloc (directive_buffer, buffer_length); + p = &directive_buffer[bytes_used]; + buffer_limit = &directive_buffer[buffer_length]; + } + + c = getc (finput); + + /* Discard initial whitespace. */ + if ((c == ' ' || c == '\t') && p == directive_buffer) + continue; + + /* Detect the end of the directive. */ + if (c == '\n' && looking_for == 0) + { + ungetc (c, finput); + c = '\0'; + } + + *p++ = c; + + if (c == 0) + return directive_buffer; + + /* Handle string and character constant syntax. */ + if (looking_for) + { + if (looking_for == c && !char_escaped) + looking_for = 0; /* Found terminator... stop looking. */ + } + else + if (c == '\'' || c == '"') + looking_for = c; /* Don't stop buffering until we see another + another one of these (or an EOF). */ + + /* Handle backslash. */ + char_escaped = (c == '\\' && ! char_escaped); + } +} + +/* Make a variant type in the proper way for C/C++, propagating qualifiers + down to the element type of an array. */ + +tree +c_build_type_variant (type, constp, volatilep) + tree type; + int constp, volatilep; +{ + if (TREE_CODE (type) == ARRAY_TYPE) + { + tree real_main_variant = TYPE_MAIN_VARIANT (type); + int permanent = TREE_PERMANENT (type); + + if (permanent) + push_obstacks (&permanent_obstack, &permanent_obstack); + type = build_array_type (c_build_type_variant (TREE_TYPE (type), + constp, volatilep), + TYPE_DOMAIN (type)); + TYPE_MAIN_VARIANT (type) = real_main_variant; + if (permanent) + pop_obstacks (); + } + return build_type_variant (type, constp, volatilep); +} diff --git a/gnu/usr.bin/cc/lib/c-lex.h b/gnu/usr.bin/cc/lib/c-lex.h new file mode 100644 index 000000000000..ae67d4c11126 --- /dev/null +++ b/gnu/usr.bin/cc/lib/c-lex.h @@ -0,0 +1,79 @@ +/* Define constants for communication with c-parse.y. + Copyright (C) 1987, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + + +enum rid +{ + RID_UNUSED, + RID_INT, + RID_CHAR, + RID_FLOAT, + RID_DOUBLE, + RID_VOID, + RID_UNUSED1, + + RID_UNSIGNED, + RID_SHORT, + RID_LONG, + RID_AUTO, + RID_STATIC, + RID_EXTERN, + RID_REGISTER, + RID_TYPEDEF, + RID_SIGNED, + RID_CONST, + RID_VOLATILE, + RID_INLINE, + RID_NOALIAS, + RID_ITERATOR, + RID_COMPLEX, + + RID_IN, + RID_OUT, + RID_INOUT, + RID_BYCOPY, + RID_ONEWAY, + RID_ID, + + RID_MAX +}; + +#define NORID RID_UNUSED + +#define RID_FIRST_MODIFIER RID_UNSIGNED + +/* The elements of `ridpointers' are identifier nodes + for the reserved type names and storage classes. + It is indexed by a RID_... value. */ +extern tree ridpointers[(int) RID_MAX]; + +/* the declaration found for the last IDENTIFIER token read in. + yylex must look this up to detect typedefs, which get token type TYPENAME, + so it is left around in case the identifier is not a typedef but is + used in a context which makes it a reference to a variable. */ +extern tree lastiddecl; + +extern char *token_buffer; /* Pointer to token buffer. */ + +extern tree make_pointer_declarator (); +extern void reinit_parse_for_function (); +extern int yylex (); + +extern char *get_directive_line (); diff --git a/gnu/usr.bin/cc/lib/c-parse.h b/gnu/usr.bin/cc/lib/c-parse.h new file mode 100644 index 000000000000..dab903ee8f1e --- /dev/null +++ b/gnu/usr.bin/cc/lib/c-parse.h @@ -0,0 +1,65 @@ +typedef union {long itype; tree ttype; enum tree_code code; + char *filename; int lineno; } YYSTYPE; +#define IDENTIFIER 258 +#define TYPENAME 259 +#define SCSPEC 260 +#define TYPESPEC 261 +#define TYPE_QUAL 262 +#define CONSTANT 263 +#define STRING 264 +#define ELLIPSIS 265 +#define SIZEOF 266 +#define ENUM 267 +#define STRUCT 268 +#define UNION 269 +#define IF 270 +#define ELSE 271 +#define WHILE 272 +#define DO 273 +#define FOR 274 +#define SWITCH 275 +#define CASE 276 +#define DEFAULT 277 +#define BREAK 278 +#define CONTINUE 279 +#define RETURN 280 +#define GOTO 281 +#define ASM_KEYWORD 282 +#define TYPEOF 283 +#define ALIGNOF 284 +#define ALIGN 285 +#define ATTRIBUTE 286 +#define EXTENSION 287 +#define LABEL 288 +#define REALPART 289 +#define IMAGPART 290 +#define ASSIGN 291 +#define OROR 292 +#define ANDAND 293 +#define EQCOMPARE 294 +#define ARITHCOMPARE 295 +#define LSHIFT 296 +#define RSHIFT 297 +#define UNARY 298 +#define PLUSPLUS 299 +#define MINUSMINUS 300 +#define HYPERUNARY 301 +#define POINTSAT 302 +#define INTERFACE 303 +#define IMPLEMENTATION 304 +#define END 305 +#define SELECTOR 306 +#define DEFS 307 +#define ENCODE 308 +#define CLASSNAME 309 +#define PUBLIC 310 +#define PRIVATE 311 +#define PROTECTED 312 +#define PROTOCOL 313 +#define OBJECTNAME 314 +#define CLASS 315 +#define ALIAS 316 +#define OBJC_STRING 317 + + +extern YYSTYPE yylval; diff --git a/gnu/usr.bin/cc/lib/c-tree.h b/gnu/usr.bin/cc/lib/c-tree.h new file mode 100644 index 000000000000..1450b300efbc --- /dev/null +++ b/gnu/usr.bin/cc/lib/c-tree.h @@ -0,0 +1,447 @@ +/* Definitions for C parsing and type checking. + Copyright (C) 1987, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef _C_TREE_H +#define _C_TREE_H + +#ifndef STDIO_PROTO +#ifdef BUFSIZ +#define STDIO_PROTO(ARGS) PROTO(ARGS) +#else +#define STDIO_PROTO(ARGS) () +#endif +#endif + +/* Language-dependent contents of an identifier. */ + +/* The limbo_value is used for block level extern declarations, which need + to be type checked against subsequent extern declarations. They can't + be referenced after they fall out of scope, so they can't be global. */ + +struct lang_identifier +{ + struct tree_identifier ignore; + tree global_value, local_value, label_value, implicit_decl; + tree error_locus, limbo_value; +}; + +/* Macros for access to language-specific slots in an identifier. */ +/* Each of these slots contains a DECL node or null. */ + +/* This represents the value which the identifier has in the + file-scope namespace. */ +#define IDENTIFIER_GLOBAL_VALUE(NODE) \ + (((struct lang_identifier *)(NODE))->global_value) +/* This represents the value which the identifier has in the current + scope. */ +#define IDENTIFIER_LOCAL_VALUE(NODE) \ + (((struct lang_identifier *)(NODE))->local_value) +/* This represents the value which the identifier has as a label in + the current label scope. */ +#define IDENTIFIER_LABEL_VALUE(NODE) \ + (((struct lang_identifier *)(NODE))->label_value) +/* This records the extern decl of this identifier, if it has had one + at any point in this compilation. */ +#define IDENTIFIER_LIMBO_VALUE(NODE) \ + (((struct lang_identifier *)(NODE))->limbo_value) +/* This records the implicit function decl of this identifier, if it + has had one at any point in this compilation. */ +#define IDENTIFIER_IMPLICIT_DECL(NODE) \ + (((struct lang_identifier *)(NODE))->implicit_decl) +/* This is the last function in which we printed an "undefined variable" + message for this identifier. Value is a FUNCTION_DECL or null. */ +#define IDENTIFIER_ERROR_LOCUS(NODE) \ + (((struct lang_identifier *)(NODE))->error_locus) + +/* In identifiers, C uses the following fields in a special way: + TREE_PUBLIC to record that there was a previous local extern decl. + TREE_USED to record that such a decl was used. + TREE_ADDRESSABLE to record that the address of such a decl was used. */ + +/* Nonzero means reject anything that ANSI standard C forbids. */ +extern int pedantic; + +/* In a RECORD_TYPE or UNION_TYPE, nonzero if any component is read-only. */ +#define C_TYPE_FIELDS_READONLY(type) TREE_LANG_FLAG_1 (type) + +/* In a RECORD_TYPE or UNION_TYPE, nonzero if any component is volatile. */ +#define C_TYPE_FIELDS_VOLATILE(type) TREE_LANG_FLAG_2 (type) + +/* In a RECORD_TYPE or UNION_TYPE or ENUMERAL_TYPE + nonzero if the definition of the type has already started. */ +#define C_TYPE_BEING_DEFINED(type) TYPE_LANG_FLAG_0 (type) + +/* In a RECORD_TYPE, a sorted array of the fields of the type. */ +struct lang_type +{ + int len; + tree elts[1]; +}; + +/* Mark which labels are explicitly declared. + These may be shadowed, and may be referenced from nested functions. */ +#define C_DECLARED_LABEL_FLAG(label) TREE_LANG_FLAG_1 (label) + +/* Record whether a type or decl was written with nonconstant size. + Note that TYPE_SIZE may have simplified to a constant. */ +#define C_TYPE_VARIABLE_SIZE(type) TYPE_LANG_FLAG_1 (type) +#define C_DECL_VARIABLE_SIZE(type) DECL_LANG_FLAG_0 (type) + +/* Record in each node resulting from a binary operator + what operator was specified for it. */ +#define C_EXP_ORIGINAL_CODE(exp) ((enum tree_code) TREE_COMPLEXITY (exp)) + +#if 0 /* Not used. */ +/* Record whether a decl for a function or function pointer has + already been mentioned (in a warning) because it was called + but didn't have a prototype. */ +#define C_MISSING_PROTOTYPE_WARNED(decl) DECL_LANG_FLAG_2(decl) +#endif + +/* Store a value in that field. */ +#define C_SET_EXP_ORIGINAL_CODE(exp, code) \ + (TREE_COMPLEXITY (exp) = (int)(code)) + +/* Record whether a typedef for type `int' was actually `signed int'. */ +#define C_TYPEDEF_EXPLICITLY_SIGNED(exp) DECL_LANG_FLAG_1 ((exp)) + +/* Nonzero for a declaration of a built in function if there has been no + occasion that would declare the function in ordinary C. + Using the function draws a pedantic warning in this case. */ +#define C_DECL_ANTICIPATED(exp) DECL_LANG_FLAG_3 ((exp)) + +/* For FUNCTION_TYPE, a hidden list of types of arguments. The same as + TYPE_ARG_TYPES for functions with prototypes, but created for functions + without prototypes. */ +#define TYPE_ACTUAL_ARG_TYPES(NODE) TYPE_NONCOPIED_PARTS (NODE) + +/* Nonzero if the type T promotes to itself. + ANSI C states explicitly the list of types that promote; + in particular, short promotes to int even if they have the same width. */ +#define C_PROMOTING_INTEGER_TYPE_P(t) \ + (TREE_CODE ((t)) == INTEGER_TYPE \ + && (TYPE_MAIN_VARIANT (t) == char_type_node \ + || TYPE_MAIN_VARIANT (t) == signed_char_type_node \ + || TYPE_MAIN_VARIANT (t) == unsigned_char_type_node \ + || TYPE_MAIN_VARIANT (t) == short_integer_type_node \ + || TYPE_MAIN_VARIANT (t) == short_unsigned_type_node)) + +/* In a VAR_DECL, means the variable is really an iterator. */ +#define ITERATOR_P(D) (DECL_LANG_FLAG_4(D)) + +/* In a VAR_DECL for an iterator, means we are within + an explicit loop over that iterator. */ +#define ITERATOR_BOUND_P(NODE) ((NODE)->common.readonly_flag) + +/* in c-lang.c and objc-act.c */ +extern tree lookup_interface PROTO((tree)); +extern tree is_class_name PROTO((tree)); +extern void maybe_objc_check_decl PROTO((tree)); +extern int maybe_objc_comptypes PROTO((tree, tree, int)); +extern tree maybe_building_objc_message_expr PROTO((void)); +extern tree maybe_objc_method_name PROTO((tree)); +extern int recognize_objc_keyword PROTO((void)); +extern tree build_objc_string PROTO((int, char *)); + +/* in c-aux-info.c */ +extern void gen_aux_info_record PROTO((tree, int, int, int)); + +/* in c-common.c */ +/* Print an error message for invalid operands to arith operation CODE. + NOP_EXPR is used as a special case (see truthvalue_conversion). */ +extern void binary_op_error PROTO((enum tree_code)); +extern void c_expand_expr_stmt PROTO((tree)); +/* Validate the expression after `case' and apply default promotions. */ +extern tree check_case_value PROTO((tree)); +/* Concatenate a list of STRING_CST nodes into one STRING_CST. */ +extern tree combine_strings PROTO((tree)); +extern void constant_expression_warning PROTO((tree)); +extern void decl_attributes PROTO((tree, tree)); +extern void declare_function_name PROTO((void)); +extern tree convert_and_check PROTO((tree, tree)); +extern void overflow_warning PROTO((tree)); +extern void unsigned_conversion_warning PROTO((tree, tree)); +/* Read the rest of the current #-directive line. */ +extern char *get_directive_line STDIO_PROTO((FILE *)); +/* Subroutine of build_binary_op, used for comparison operations. + See if the operands have both been converted from subword integer types + and, if so, perhaps change them both back to their original type. */ +extern tree shorten_compare PROTO((tree *, tree *, tree *, enum tree_code *)); +/* Prepare expr to be an argument of a TRUTH_NOT_EXPR, + or validate its data type for an `if' or `while' statement or ?..: exp. */ +extern tree truthvalue_conversion PROTO((tree)); +extern tree type_for_mode PROTO((enum machine_mode, int)); +extern tree type_for_size PROTO((unsigned, int)); + +/* in c-convert.c */ +extern tree convert PROTO((tree, tree)); + +/* in c-decl.c */ +/* Standard named or nameless data types of the C compiler. */ +extern tree char_array_type_node; +extern tree char_type_node; +extern tree const_ptr_type_node; +extern tree const_string_type_node; +extern tree default_function_type; +extern tree double_ftype_double; +extern tree double_ftype_double_double; +extern tree double_type_node; +extern tree float_type_node; +extern tree intDI_type_node; +extern tree intHI_type_node; +extern tree intQI_type_node; +extern tree intSI_type_node; +extern tree int_array_type_node; +extern tree int_ftype_cptr_cptr_sizet; +extern tree int_ftype_int; +extern tree int_ftype_ptr_ptr_int; +extern tree int_ftype_string_string; +extern tree integer_type_node; +extern tree long_double_type_node; +extern tree long_ftype_long; +extern tree long_integer_type_node; +extern tree long_long_integer_type_node; +extern tree long_long_unsigned_type_node; +extern tree long_unsigned_type_node; +extern tree complex_integer_type_node; +extern tree complex_float_type_node; +extern tree complex_double_type_node; +extern tree complex_long_double_type_node; +extern tree ptr_type_node; +extern tree ptrdiff_type_node; +extern tree short_integer_type_node; +extern tree short_unsigned_type_node; +extern tree signed_char_type_node; +extern tree signed_wchar_type_node; +extern tree string_ftype_ptr_ptr; +extern tree string_type_node; +extern tree unsigned_char_type_node; +extern tree unsigned_intDI_type_node; +extern tree unsigned_intHI_type_node; +extern tree unsigned_intQI_type_node; +extern tree unsigned_intSI_type_node; +extern tree unsigned_type_node; +extern tree unsigned_wchar_type_node; +extern tree void_ftype_ptr_int_int; +extern tree void_ftype_ptr_ptr_int; +extern tree void_type_node; +extern tree wchar_array_type_node; +extern tree wchar_type_node; + +extern tree build_enumerator PROTO((tree, tree)); +/* Declare a predefined function. Return the declaration. */ +extern tree builtin_function PROTO((char *, tree, enum built_in_function function_, char *)); +/* Add qualifiers to a type, in the fashion for C. */ +extern tree c_build_type_variant PROTO((tree, int, int)); +extern int c_decode_option PROTO((char *)); +extern void c_mark_varargs PROTO((void)); +extern tree check_identifier PROTO((tree, tree)); +extern void clear_parm_order PROTO((void)); +extern tree combine_parm_decls PROTO((tree, tree, int)); +extern int complete_array_type PROTO((tree, tree, int)); +extern void declare_parm_level PROTO((int)); +extern tree define_label PROTO((char *, int, tree)); +extern void delete_block PROTO((tree)); +extern void finish_decl PROTO((tree, tree, tree)); +extern tree finish_enum PROTO((tree, tree)); +extern void finish_function PROTO((int)); +extern tree finish_struct PROTO((tree, tree)); +extern tree get_parm_info PROTO((int)); +extern tree getdecls PROTO((void)); +extern tree gettags PROTO((void)); +extern int global_bindings_p PROTO((void)); +extern tree grokfield PROTO((char *, int, tree, tree, tree)); +extern tree groktypename PROTO((tree)); +extern tree groktypename_in_parm_context PROTO((tree)); +extern tree implicitly_declare PROTO((tree)); +extern int in_parm_level_p PROTO((void)); +extern void init_decl_processing PROTO((void)); +extern void insert_block PROTO((tree)); +extern void keep_next_level PROTO((void)); +extern int kept_level_p PROTO((void)); +extern tree lookup_label PROTO((tree)); +extern tree lookup_name PROTO((tree)); +extern tree lookup_name_current_level PROTO((tree)); +extern tree maybe_build_cleanup PROTO((tree)); +extern void parmlist_tags_warning PROTO((void)); +extern void pending_xref_error PROTO((void)); +extern void pop_c_function_context PROTO((void)); +extern void pop_label_level PROTO((void)); +extern tree poplevel PROTO((int, int, int)); +extern void print_lang_decl PROTO((void)); +extern void print_lang_identifier STDIO_PROTO((FILE *, tree, + int)); +extern void print_lang_type PROTO((void)); +extern void push_c_function_context PROTO((void)); +extern void push_label_level PROTO((void)); +extern void push_parm_decl PROTO((tree)); +extern tree pushdecl PROTO((tree)); +extern tree pushdecl_top_level PROTO((tree)); +extern void pushlevel PROTO((int)); +extern void pushtag PROTO((tree, tree)); +extern void set_block PROTO((tree)); +extern tree shadow_label PROTO((tree)); +extern void shadow_record_fields PROTO((tree)); +extern void shadow_tag PROTO((tree)); +extern void shadow_tag_warned PROTO((tree, int)); +extern tree start_enum PROTO((tree)); +extern int start_function PROTO((tree, tree, int)); +extern tree start_decl PROTO((tree, tree, int)); +extern tree start_struct PROTO((enum tree_code, tree)); +extern void store_parm_decls PROTO((void)); +extern tree xref_tag PROTO((enum tree_code, tree)); + +/* in c-typeck.c */ +extern tree build_array_ref PROTO((tree, tree)); +extern tree build_binary_op PROTO((enum tree_code, tree, tree, int)); +extern tree build_c_cast PROTO((tree, tree)); +extern tree build_component_ref PROTO((tree, tree)); +extern tree build_compound_expr PROTO((tree)); +extern tree build_conditional_expr PROTO((tree, tree, tree)); +extern tree build_function_call PROTO((tree, tree)); +extern tree build_indirect_ref PROTO((tree, char *)); +extern tree build_modify_expr PROTO((tree, enum tree_code, tree)); +extern tree build_unary_op PROTO((enum tree_code, tree, int)); +extern tree c_alignof PROTO((tree)); +extern tree c_alignof_expr PROTO((tree)); +extern tree c_sizeof PROTO((tree)); +extern tree c_expand_start_case PROTO((tree)); +/* Given two integer or real types, return the type for their sum. + Given two compatible ANSI C types, returns the merged type. */ +extern tree common_type PROTO((tree, tree)); +extern tree default_conversion PROTO((tree)); +extern tree digest_init PROTO((tree, tree, tree *, int, int, char *)); +extern tree parser_build_binary_op PROTO((enum tree_code, tree, tree)); +extern tree require_complete_type PROTO((tree)); +extern void store_init_value PROTO((tree, tree)); + +/* in c-iterate.c */ +extern void iterator_expand PROTO((tree)); +extern void iterator_for_loop_start PROTO((tree)); +extern void iterator_for_loop_end PROTO((tree)); +extern void iterator_for_loop_record PROTO((tree)); +extern void push_iterator_stack PROTO((void)); +extern void pop_iterator_stack PROTO((void)); + +/* Set to 0 at beginning of a function definition, set to 1 if + a return statement that specifies a return value is seen. */ + +extern int current_function_returns_value; + +/* Set to 0 at beginning of a function definition, set to 1 if + a return statement with no argument is seen. */ + +extern int current_function_returns_null; + +/* Nonzero means `$' can be in an identifier. */ + +extern int dollars_in_ident; + +/* Nonzero means allow type mismatches in conditional expressions; + just make their values `void'. */ + +extern int flag_cond_mismatch; + +/* Nonzero means don't recognize the keyword `asm'. */ + +extern int flag_no_asm; + +/* Nonzero means ignore `#ident' directives. */ + +extern int flag_no_ident; + +/* Nonzero means warn about implicit declarations. */ + +extern int warn_implicit; + +/* Nonzero means give string constants the type `const char *' + to get extra warnings from them. These warnings will be too numerous + to be useful, except in thoroughly ANSIfied programs. */ + +extern int warn_write_strings; + +/* Nonzero means warn about sizeof (function) or addition/subtraction + of function pointers. */ + +extern int warn_pointer_arith; + +/* Nonzero means warn for all old-style non-prototype function decls. */ + +extern int warn_strict_prototypes; + +/* Nonzero means warn about multiple (redundant) decls for the same single + variable or function. */ + +extern int warn_redundant_decls; + +/* Nonzero means warn about extern declarations of objects not at + file-scope level and about *all* declarations of functions (whether + extern or static) not at file-scope level. Note that we exclude + implicit function declarations. To get warnings about those, use + -Wimplicit. */ + +extern int warn_nested_externs; + +/* Nonzero means warn about pointer casts that can drop a type qualifier + from the pointer target type. */ + +extern int warn_cast_qual; + +/* Warn about traditional constructs whose meanings changed in ANSI C. */ + +extern int warn_traditional; + +/* Warn about *printf or *scanf format/argument anomalies. */ + +extern int warn_format; + +/* Warn about a subscript that has type char. */ + +extern int warn_char_subscripts; + +/* Warn if a type conversion is done that might have confusing results. */ + +extern int warn_conversion; + +/* Nonzero means do some things the same way PCC does. */ + +extern int flag_traditional; + +/* Nonzero means warn about suggesting putting in ()'s. */ + +extern int warn_parentheses; + +/* Warn if initializer is not completely bracketed. */ + +extern int warn_missing_braces; + +/* Nonzero means this is a function to call to perform comptypes + on two record types. */ + +extern int (*comptypes_record_hook) (); + +/* Nonzero means we are reading code that came from a system header file. */ + +extern int system_header_p; + +/* Nonzero enables objc features. */ + +extern int doing_objc_thang; + +#endif /* not _C_TREE_H */ diff --git a/gnu/usr.bin/cc/lib/caller-save.c b/gnu/usr.bin/cc/lib/caller-save.c new file mode 100644 index 000000000000..ecdc20aa600d --- /dev/null +++ b/gnu/usr.bin/cc/lib/caller-save.c @@ -0,0 +1,780 @@ +/* Save and restore call-clobbered registers which are live across a call. + Copyright (C) 1989, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "flags.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "recog.h" +#include "basic-block.h" +#include "reload.h" +#include "expr.h" + +/* Modes for each hard register that we can save. The smallest mode is wide + enough to save the entire contents of the register. When saving the + register because it is live we first try to save in multi-register modes. + If that is not possible the save is done one register at a time. */ + +static enum machine_mode + regno_save_mode[FIRST_PSEUDO_REGISTER][MOVE_MAX / UNITS_PER_WORD + 1]; + +/* For each hard register, a place on the stack where it can be saved, + if needed. */ + +static rtx + regno_save_mem[FIRST_PSEUDO_REGISTER][MOVE_MAX / UNITS_PER_WORD + 1]; + +/* We will only make a register eligible for caller-save if it can be + saved in its widest mode with a simple SET insn as long as the memory + address is valid. We record the INSN_CODE is those insns here since + when we emit them, the addresses might not be valid, so they might not + be recognized. */ + +static enum insn_code + reg_save_code[FIRST_PSEUDO_REGISTER][MOVE_MAX / UNITS_PER_WORD + 1]; +static enum insn_code + reg_restore_code[FIRST_PSEUDO_REGISTER][MOVE_MAX / UNITS_PER_WORD + 1]; + +/* Set of hard regs currently live (during scan of all insns). */ + +static HARD_REG_SET hard_regs_live; + +/* Set of hard regs currently residing in save area (during insn scan). */ + +static HARD_REG_SET hard_regs_saved; + +/* Set of hard regs which need to be restored before referenced. */ + +static HARD_REG_SET hard_regs_need_restore; + +/* Number of registers currently in hard_regs_saved. */ + +int n_regs_saved; + +static enum machine_mode choose_hard_reg_mode PROTO((int, int)); +static void set_reg_live PROTO((rtx, rtx)); +static void clear_reg_live PROTO((rtx)); +static void restore_referenced_regs PROTO((rtx, rtx, enum machine_mode)); +static int insert_save_restore PROTO((rtx, int, int, + enum machine_mode, int)); + +/* Return a machine mode that is legitimate for hard reg REGNO and large + enough to save nregs. If we can't find one, return VOIDmode. */ + +static enum machine_mode +choose_hard_reg_mode (regno, nregs) + int regno; + int nregs; +{ + enum machine_mode found_mode = VOIDmode, mode; + + /* We first look for the largest integer mode that can be validly + held in REGNO. If none, we look for the largest floating-point mode. + If we still didn't find a valid mode, try CCmode. */ + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + if (HARD_REGNO_NREGS (regno, mode) == nregs + && HARD_REGNO_MODE_OK (regno, mode)) + found_mode = mode; + + if (found_mode != VOIDmode) + return found_mode; + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + if (HARD_REGNO_NREGS (regno, mode) == nregs + && HARD_REGNO_MODE_OK (regno, mode)) + found_mode = mode; + + if (found_mode != VOIDmode) + return found_mode; + + if (HARD_REGNO_NREGS (regno, CCmode) == nregs + && HARD_REGNO_MODE_OK (regno, CCmode)) + return CCmode; + + /* We can't find a mode valid for this register. */ + return VOIDmode; +} + +/* Initialize for caller-save. + + Look at all the hard registers that are used by a call and for which + regclass.c has not already excluded from being used across a call. + + Ensure that we can find a mode to save the register and that there is a + simple insn to save and restore the register. This latter check avoids + problems that would occur if we tried to save the MQ register of some + machines directly into memory. */ + +void +init_caller_save () +{ + char *first_obj = (char *) oballoc (0); + rtx addr_reg; + int offset; + rtx address; + int i, j; + + /* First find all the registers that we need to deal with and all + the modes that they can have. If we can't find a mode to use, + we can't have the register live over calls. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + if (call_used_regs[i] && ! call_fixed_regs[i]) + { + for (j = 1; j <= MOVE_MAX / UNITS_PER_WORD; j++) + { + regno_save_mode[i][j] = choose_hard_reg_mode (i, j); + if (regno_save_mode[i][j] == VOIDmode && j == 1) + { + call_fixed_regs[i] = 1; + SET_HARD_REG_BIT (call_fixed_reg_set, i); + } + } + } + else + regno_save_mode[i][1] = VOIDmode; + } + + /* The following code tries to approximate the conditions under which + we can easily save and restore a register without scratch registers or + other complexities. It will usually work, except under conditions where + the validity of an insn operand is dependent on the address offset. + No such cases are currently known. + + We first find a typical offset from some BASE_REG_CLASS register. + This address is chosen by finding the first register in the class + and by finding the smallest power of two that is a valid offset from + that register in every mode we will use to save registers. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (TEST_HARD_REG_BIT (reg_class_contents[(int) BASE_REG_CLASS], i)) + break; + + if (i == FIRST_PSEUDO_REGISTER) + abort (); + + addr_reg = gen_rtx (REG, Pmode, i); + + for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1) + { + address = gen_rtx (PLUS, Pmode, addr_reg, GEN_INT (offset)); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (regno_save_mode[i][1] != VOIDmode + && ! strict_memory_address_p (regno_save_mode[i][1], address)) + break; + + if (i == FIRST_PSEUDO_REGISTER) + break; + } + + /* If we didn't find a valid address, we must use register indirect. */ + if (offset == 0) + address = addr_reg; + + /* Next we try to form an insn to save and restore the register. We + see if such an insn is recognized and meets its constraints. */ + + start_sequence (); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + for (j = 1; j <= MOVE_MAX / UNITS_PER_WORD; j++) + if (regno_save_mode[i][j] != VOIDmode) + { + rtx mem = gen_rtx (MEM, regno_save_mode[i][j], address); + rtx reg = gen_rtx (REG, regno_save_mode[i][j], i); + rtx savepat = gen_rtx (SET, VOIDmode, mem, reg); + rtx restpat = gen_rtx (SET, VOIDmode, reg, mem); + rtx saveinsn = emit_insn (savepat); + rtx restinsn = emit_insn (restpat); + int ok; + + reg_save_code[i][j] = recog_memoized (saveinsn); + reg_restore_code[i][j] = recog_memoized (restinsn); + + /* Now extract both insns and see if we can meet their constraints. */ + ok = (reg_save_code[i][j] != -1 && reg_restore_code[i][j] != -1); + if (ok) + { + insn_extract (saveinsn); + ok = constrain_operands (reg_save_code[i][j], 1); + insn_extract (restinsn); + ok &= constrain_operands (reg_restore_code[i][j], 1); + } + + if (! ok) + { + regno_save_mode[i][j] = VOIDmode; + if (j == 1) + { + call_fixed_regs[i] = 1; + SET_HARD_REG_BIT (call_fixed_reg_set, i); + } + } + } + + end_sequence (); + + obfree (first_obj); +} + +/* Initialize save areas by showing that we haven't allocated any yet. */ + +void +init_save_areas () +{ + int i, j; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + for (j = 1; j <= MOVE_MAX / UNITS_PER_WORD; j++) + regno_save_mem[i][j] = 0; +} + +/* Allocate save areas for any hard registers that might need saving. + We take a conservative approach here and look for call-clobbered hard + registers that are assigned to pseudos that cross calls. This may + overestimate slightly (especially if some of these registers are later + used as spill registers), but it should not be significant. + + Then perform register elimination in the addresses of the save area + locations; return 1 if all eliminated addresses are strictly valid. + We assume that our caller has set up the elimination table to the + worst (largest) possible offsets. + + Set *PCHANGED to 1 if we had to allocate some memory for the save area. + + Future work: + + In the fallback case we should iterate backwards across all possible + modes for the save, choosing the largest available one instead of + falling back to the smallest mode immediately. (eg TF -> DF -> SF). + + We do not try to use "move multiple" instructions that exist + on some machines (such as the 68k moveml). It could be a win to try + and use them when possible. The hard part is doing it in a way that is + machine independent since they might be saving non-consecutive + registers. (imagine caller-saving d0,d1,a0,a1 on the 68k) */ + +int +setup_save_areas (pchanged) + int *pchanged; +{ + int i, j, k; + HARD_REG_SET hard_regs_used; + int ok = 1; + + + /* Allocate space in the save area for the largest multi-register + pseudos first, then work backwards to single register + pseudos. */ + + /* Find and record all call-used hard-registers in this function. */ + CLEAR_HARD_REG_SET (hard_regs_used); + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (reg_renumber[i] >= 0 && reg_n_calls_crossed[i] > 0) + { + int regno = reg_renumber[i]; + int endregno + = regno + HARD_REGNO_NREGS (regno, GET_MODE (regno_reg_rtx[i])); + int nregs = endregno - regno; + + for (j = 0; j < nregs; j++) + { + if (call_used_regs[regno+j]) + SET_HARD_REG_BIT (hard_regs_used, regno+j); + } + } + + /* Now run through all the call-used hard-registers and allocate + space for them in the caller-save area. Try to allocate space + in a manner which allows multi-register saves/restores to be done. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + for (j = MOVE_MAX / UNITS_PER_WORD; j > 0; j--) + { + int ok = 1; + int do_save; + + /* If no mode exists for this size, try another. Also break out + if we have already saved this hard register. */ + if (regno_save_mode[i][j] == VOIDmode || regno_save_mem[i][1] != 0) + continue; + + /* See if any register in this group has been saved. */ + do_save = 1; + for (k = 0; k < j; k++) + if (regno_save_mem[i + k][1]) + { + do_save = 0; + break; + } + if (! do_save) + continue; + + for (k = 0; k < j; k++) + { + int regno = i + k; + ok &= (TEST_HARD_REG_BIT (hard_regs_used, regno) != 0); + } + + /* We have found an acceptable mode to store in. */ + if (ok) + { + + regno_save_mem[i][j] + = assign_stack_local (regno_save_mode[i][j], + GET_MODE_SIZE (regno_save_mode[i][j]), 0); + + /* Setup single word save area just in case... */ + for (k = 0; k < j; k++) + { + /* This should not depend on WORDS_BIG_ENDIAN. + The order of words in regs is the same as in memory. */ + rtx temp = gen_rtx (MEM, regno_save_mode[i+k][1], + XEXP (regno_save_mem[i][j], 0)); + + regno_save_mem[i+k][1] + = adj_offsettable_operand (temp, k * UNITS_PER_WORD); + } + *pchanged = 1; + } + } + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + for (j = 1; j <= MOVE_MAX / UNITS_PER_WORD; j++) + if (regno_save_mem[i][j] != 0) + ok &= strict_memory_address_p (GET_MODE (regno_save_mem[i][j]), + XEXP (eliminate_regs (regno_save_mem[i][j], 0, NULL_RTX), 0)); + + return ok; +} + +/* Find the places where hard regs are live across calls and save them. + + INSN_MODE is the mode to assign to any insns that we add. This is used + by reload to determine whether or not reloads or register eliminations + need be done on these insns. */ + +void +save_call_clobbered_regs (insn_mode) + enum machine_mode insn_mode; +{ + rtx insn; + int b; + + for (b = 0; b < n_basic_blocks; b++) + { + regset regs_live = basic_block_live_at_start[b]; + rtx prev_block_last = PREV_INSN (basic_block_head[b]); + REGSET_ELT_TYPE bit; + int offset, i, j; + int regno; + + /* Compute hard regs live at start of block -- this is the + real hard regs marked live, plus live pseudo regs that + have been renumbered to hard regs. No registers have yet been + saved because we restore all of them before the end of the basic + block. */ + +#ifdef HARD_REG_SET + hard_regs_live = *regs_live; +#else + COPY_HARD_REG_SET (hard_regs_live, regs_live); +#endif + + CLEAR_HARD_REG_SET (hard_regs_saved); + CLEAR_HARD_REG_SET (hard_regs_need_restore); + n_regs_saved = 0; + + for (offset = 0, i = 0; offset < regset_size; offset++) + { + if (regs_live[offset] == 0) + i += REGSET_ELT_BITS; + else + for (bit = 1; bit && i < max_regno; bit <<= 1, i++) + if ((regs_live[offset] & bit) + && (regno = reg_renumber[i]) >= 0) + for (j = regno; + j < regno + HARD_REGNO_NREGS (regno, + PSEUDO_REGNO_MODE (i)); + j++) + SET_HARD_REG_BIT (hard_regs_live, j); + + } + + /* Now scan the insns in the block, keeping track of what hard + regs are live as we go. When we see a call, save the live + call-clobbered hard regs. */ + + for (insn = basic_block_head[b]; ; insn = NEXT_INSN (insn)) + { + RTX_CODE code = GET_CODE (insn); + + if (GET_RTX_CLASS (code) == 'i') + { + rtx link; + + /* If some registers have been saved, see if INSN references + any of them. We must restore them before the insn if so. */ + + if (n_regs_saved) + restore_referenced_regs (PATTERN (insn), insn, insn_mode); + + /* NB: the normal procedure is to first enliven any + registers set by insn, then deaden any registers that + had their last use at insn. This is incorrect now, + since multiple pseudos may have been mapped to the + same hard reg, and the death notes are ambiguous. So + it must be done in the other, safe, order. */ + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_DEAD) + clear_reg_live (XEXP (link, 0)); + + /* When we reach a call, we need to save all registers that are + live, call-used, not fixed, and not already saved. We must + test at this point because registers that die in a CALL_INSN + are not live across the call and likewise for registers that + are born in the CALL_INSN. */ + + if (code == CALL_INSN) + { + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (call_used_regs[regno] && ! call_fixed_regs[regno] + && TEST_HARD_REG_BIT (hard_regs_live, regno) + && ! TEST_HARD_REG_BIT (hard_regs_saved, regno)) + regno += insert_save_restore (insn, 1, regno, + insn_mode, 0); +#ifdef HARD_REG_SET + hard_regs_need_restore = hard_regs_saved; +#else + COPY_HARD_REG_SET (hard_regs_need_restore, + hard_regs_saved); +#endif + + /* Must recompute n_regs_saved. */ + n_regs_saved = 0; + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) + n_regs_saved++; + + } + + note_stores (PATTERN (insn), set_reg_live); + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_UNUSED) + clear_reg_live (XEXP (link, 0)); + } + + if (insn == basic_block_end[b]) + break; + } + + /* At the end of the basic block, we must restore any registers that + remain saved. If the last insn in the block is a JUMP_INSN, put + the restore before the insn, otherwise, put it after the insn. */ + + if (n_regs_saved) + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (TEST_HARD_REG_BIT (hard_regs_need_restore, regno)) + regno += insert_save_restore ((GET_CODE (insn) == JUMP_INSN + ? insn : NEXT_INSN (insn)), 0, + regno, insn_mode, MOVE_MAX / UNITS_PER_WORD); + + /* If we added any insns at the start of the block, update the start + of the block to point at those insns. */ + basic_block_head[b] = NEXT_INSN (prev_block_last); + } +} + +/* Here from note_stores when an insn stores a value in a register. + Set the proper bit or bits in hard_regs_live. All pseudos that have + been assigned hard regs have had their register number changed already, + so we can ignore pseudos. */ + +static void +set_reg_live (reg, setter) + rtx reg, setter; +{ + register int regno, endregno, i; + enum machine_mode mode = GET_MODE (reg); + int word = 0; + + if (GET_CODE (reg) == SUBREG) + { + word = SUBREG_WORD (reg); + reg = SUBREG_REG (reg); + } + + if (GET_CODE (reg) != REG || REGNO (reg) >= FIRST_PSEUDO_REGISTER) + return; + + regno = REGNO (reg) + word; + endregno = regno + HARD_REGNO_NREGS (regno, mode); + + for (i = regno; i < endregno; i++) + { + SET_HARD_REG_BIT (hard_regs_live, i); + CLEAR_HARD_REG_BIT (hard_regs_saved, i); + CLEAR_HARD_REG_BIT (hard_regs_need_restore, i); + } +} + +/* Here when a REG_DEAD note records the last use of a reg. Clear + the appropriate bit or bits in hard_regs_live. Again we can ignore + pseudos. */ + +static void +clear_reg_live (reg) + rtx reg; +{ + register int regno, endregno, i; + + if (GET_CODE (reg) != REG || REGNO (reg) >= FIRST_PSEUDO_REGISTER) + return; + + regno = REGNO (reg); + endregno= regno + HARD_REGNO_NREGS (regno, GET_MODE (reg)); + + for (i = regno; i < endregno; i++) + { + CLEAR_HARD_REG_BIT (hard_regs_live, i); + CLEAR_HARD_REG_BIT (hard_regs_need_restore, i); + CLEAR_HARD_REG_BIT (hard_regs_saved, i); + } +} + +/* If any register currently residing in the save area is referenced in X, + which is part of INSN, emit code to restore the register in front of INSN. + INSN_MODE is the mode to assign to any insns that we add. */ + +static void +restore_referenced_regs (x, insn, insn_mode) + rtx x; + rtx insn; + enum machine_mode insn_mode; +{ + enum rtx_code code = GET_CODE (x); + char *fmt; + int i, j; + + if (code == CLOBBER) + return; + + if (code == REG) + { + int regno = REGNO (x); + + /* If this is a pseudo, scan its memory location, since it might + involve the use of another register, which might be saved. */ + + if (regno >= FIRST_PSEUDO_REGISTER + && reg_equiv_mem[regno] != 0) + restore_referenced_regs (XEXP (reg_equiv_mem[regno], 0), + insn, insn_mode); + else if (regno >= FIRST_PSEUDO_REGISTER + && reg_equiv_address[regno] != 0) + restore_referenced_regs (reg_equiv_address[regno], + insn, insn_mode); + + /* Otherwise if this is a hard register, restore any piece of it that + is currently saved. */ + + else if (regno < FIRST_PSEUDO_REGISTER) + { + int numregs = HARD_REGNO_NREGS (regno, GET_MODE (x)); + /* Save at most SAVEREGS at a time. This can not be larger than + MOVE_MAX, because that causes insert_save_restore to fail. */ + int saveregs = MIN (numregs, MOVE_MAX / UNITS_PER_WORD); + int endregno = regno + numregs; + + for (i = regno; i < endregno; i++) + if (TEST_HARD_REG_BIT (hard_regs_need_restore, i)) + i += insert_save_restore (insn, 0, i, insn_mode, saveregs); + } + + return; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + restore_referenced_regs (XEXP (x, i), insn, insn_mode); + else if (fmt[i] == 'E') + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + restore_referenced_regs (XVECEXP (x, i, j), insn, insn_mode); + } +} + +/* Insert a sequence of insns to save or restore, SAVE_P says which, + REGNO. Place these insns in front of INSN. INSN_MODE is the mode + to assign to these insns. MAXRESTORE is the maximum number of registers + which should be restored during this call (when SAVE_P == 0). It should + never be less than 1 since we only work with entire registers. + + Note that we have verified in init_caller_save that we can do this + with a simple SET, so use it. Set INSN_CODE to what we save there + since the address might not be valid so the insn might not be recognized. + These insns will be reloaded and have register elimination done by + find_reload, so we need not worry about that here. + + Return the extra number of registers saved. */ + +static int +insert_save_restore (insn, save_p, regno, insn_mode, maxrestore) + rtx insn; + int save_p; + int regno; + enum machine_mode insn_mode; + int maxrestore; +{ + rtx pat; + enum insn_code code; + int i, numregs; + + /* A common failure mode if register status is not correct in the RTL + is for this routine to be called with a REGNO we didn't expect to + save. That will cause us to write an insn with a (nil) SET_DEST + or SET_SRC. Instead of doing so and causing a crash later, check + for this common case and abort here instead. This will remove one + step in debugging such problems. */ + + if (regno_save_mem[regno][1] == 0) + abort (); + + /* If INSN is a CALL_INSN, we must insert our insns before any + USE insns in front of the CALL_INSN. */ + + if (GET_CODE (insn) == CALL_INSN) + while (GET_CODE (PREV_INSN (insn)) == INSN + && GET_CODE (PATTERN (PREV_INSN (insn))) == USE) + insn = PREV_INSN (insn); + +#ifdef HAVE_cc0 + /* If INSN references CC0, put our insns in front of the insn that sets + CC0. This is always safe, since the only way we could be passed an + insn that references CC0 is for a restore, and doing a restore earlier + isn't a problem. We do, however, assume here that CALL_INSNs don't + reference CC0. Guard against non-INSN's like CODE_LABEL. */ + + if ((GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) + && reg_referenced_p (cc0_rtx, PATTERN (insn))) + insn = prev_nonnote_insn (insn); +#endif + + /* Get the pattern to emit and update our status. */ + if (save_p) + { + int i, j, k; + int ok; + + /* See if we can save several registers with a single instruction. + Work backwards to the single register case. */ + for (i = MOVE_MAX / UNITS_PER_WORD; i > 0; i--) + { + ok = 1; + if (regno_save_mem[regno][i] != 0) + for (j = 0; j < i; j++) + { + if (! call_used_regs[regno + j] || call_fixed_regs[regno + j] + || ! TEST_HARD_REG_BIT (hard_regs_live, regno + j) + || TEST_HARD_REG_BIT (hard_regs_saved, regno + j)) + ok = 0; + } + else + continue; + + /* Must do this one save at a time */ + if (! ok) + continue; + + pat = gen_rtx (SET, VOIDmode, regno_save_mem[regno][i], + gen_rtx (REG, GET_MODE (regno_save_mem[regno][i]), regno)); + code = reg_save_code[regno][i]; + + /* Set hard_regs_saved for all the registers we saved. */ + for (k = 0; k < i; k++) + { + SET_HARD_REG_BIT (hard_regs_saved, regno + k); + SET_HARD_REG_BIT (hard_regs_need_restore, regno + k); + n_regs_saved++; + } + + numregs = i; + break; + } + } + else + { + int i, j, k; + int ok; + + /* See if we can restore `maxrestore' registers at once. Work + backwards to the single register case. */ + for (i = maxrestore; i > 0; i--) + { + ok = 1; + if (regno_save_mem[regno][i]) + for (j = 0; j < i; j++) + { + if (! TEST_HARD_REG_BIT (hard_regs_need_restore, regno + j)) + ok = 0; + } + else + continue; + + /* Must do this one restore at a time */ + if (! ok) + continue; + + pat = gen_rtx (SET, VOIDmode, + gen_rtx (REG, GET_MODE (regno_save_mem[regno][i]), + regno), + regno_save_mem[regno][i]); + code = reg_restore_code[regno][i]; + + + /* Clear status for all registers we restored. */ + for (k = 0; k < i; k++) + { + CLEAR_HARD_REG_BIT (hard_regs_need_restore, regno + k); + n_regs_saved--; + } + + numregs = i; + break; + } + } + /* Emit the insn and set the code and mode. */ + + insn = emit_insn_before (pat, insn); + PUT_MODE (insn, insn_mode); + INSN_CODE (insn) = code; + + /* Tell our callers how many extra registers we saved/restored */ + return numregs - 1; +} diff --git a/gnu/usr.bin/cc/lib/calls.c b/gnu/usr.bin/cc/lib/calls.c new file mode 100644 index 000000000000..dc867aec1094 --- /dev/null +++ b/gnu/usr.bin/cc/lib/calls.c @@ -0,0 +1,2891 @@ +/* Convert function calls to rtl insns, for GNU C compiler. + Copyright (C) 1989, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include "config.h" +#include "rtl.h" +#include "tree.h" +#include "flags.h" +#include "expr.h" +#include "gvarargs.h" +#include "insn-flags.h" + +/* Decide whether a function's arguments should be processed + from first to last or from last to first. + + They should if the stack and args grow in opposite directions, but + only if we have push insns. */ + +#ifdef PUSH_ROUNDING + +#if defined (STACK_GROWS_DOWNWARD) != defined (ARGS_GROW_DOWNARD) +#define PUSH_ARGS_REVERSED /* If it's last to first */ +#endif + +#endif + +/* Like STACK_BOUNDARY but in units of bytes, not bits. */ +#define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT) + +/* Data structure and subroutines used within expand_call. */ + +struct arg_data +{ + /* Tree node for this argument. */ + tree tree_value; + /* Mode for value; TYPE_MODE unless promoted. */ + enum machine_mode mode; + /* Current RTL value for argument, or 0 if it isn't precomputed. */ + rtx value; + /* Initially-compute RTL value for argument; only for const functions. */ + rtx initial_value; + /* Register to pass this argument in, 0 if passed on stack, or an + EXPR_LIST if the arg is to be copied into multiple different + registers. */ + rtx reg; + /* If REG was promoted from the actual mode of the argument expression, + indicates whether the promotion is sign- or zero-extended. */ + int unsignedp; + /* Number of registers to use. 0 means put the whole arg in registers. + Also 0 if not passed in registers. */ + int partial; + /* Non-zero if argument must be passed on stack. + Note that some arguments may be passed on the stack + even though pass_on_stack is zero, just because FUNCTION_ARG says so. + pass_on_stack identifies arguments that *cannot* go in registers. */ + int pass_on_stack; + /* Offset of this argument from beginning of stack-args. */ + struct args_size offset; + /* Similar, but offset to the start of the stack slot. Different from + OFFSET if this arg pads downward. */ + struct args_size slot_offset; + /* Size of this argument on the stack, rounded up for any padding it gets, + parts of the argument passed in registers do not count. + If REG_PARM_STACK_SPACE is defined, then register parms + are counted here as well. */ + struct args_size size; + /* Location on the stack at which parameter should be stored. The store + has already been done if STACK == VALUE. */ + rtx stack; + /* Location on the stack of the start of this argument slot. This can + differ from STACK if this arg pads downward. This location is known + to be aligned to FUNCTION_ARG_BOUNDARY. */ + rtx stack_slot; +#ifdef ACCUMULATE_OUTGOING_ARGS + /* Place that this stack area has been saved, if needed. */ + rtx save_area; +#endif +#ifdef STRICT_ALIGNMENT + /* If an argument's alignment does not permit direct copying into registers, + copy in smaller-sized pieces into pseudos. These are stored in a + block pointed to by this field. The next field says how many + word-sized pseudos we made. */ + rtx *aligned_regs; + int n_aligned_regs; +#endif +}; + +#ifdef ACCUMULATE_OUTGOING_ARGS +/* A vector of one char per byte of stack space. A byte if non-zero if + the corresponding stack location has been used. + This vector is used to prevent a function call within an argument from + clobbering any stack already set up. */ +static char *stack_usage_map; + +/* Size of STACK_USAGE_MAP. */ +static int highest_outgoing_arg_in_use; + +/* stack_arg_under_construction is nonzero when an argument may be + initialized with a constructor call (including a C function that + returns a BLKmode struct) and expand_call must take special action + to make sure the object being constructed does not overlap the + argument list for the constructor call. */ +int stack_arg_under_construction; +#endif + +static int calls_function PROTO((tree, int)); +static void emit_call_1 PROTO((rtx, tree, int, int, rtx, rtx, int, + rtx, int)); +static void store_one_arg PROTO ((struct arg_data *, rtx, int, int, + tree, int)); + +/* If WHICH is 1, return 1 if EXP contains a call to the built-in function + `alloca'. + + If WHICH is 0, return 1 if EXP contains a call to any function. + Actually, we only need return 1 if evaluating EXP would require pushing + arguments on the stack, but that is too difficult to compute, so we just + assume any function call might require the stack. */ + +static int +calls_function (exp, which) + tree exp; + int which; +{ + register int i; + int type = TREE_CODE_CLASS (TREE_CODE (exp)); + int length = tree_code_length[(int) TREE_CODE (exp)]; + + /* Only expressions and references can contain calls. */ + + if (type != 'e' && type != '<' && type != '1' && type != '2' && type != 'r' + && type != 'b') + return 0; + + switch (TREE_CODE (exp)) + { + case CALL_EXPR: + if (which == 0) + return 1; + else if (TREE_CODE (TREE_OPERAND (exp, 0)) == ADDR_EXPR + && (TREE_CODE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0)) + == FUNCTION_DECL) + && DECL_BUILT_IN (TREE_OPERAND (TREE_OPERAND (exp, 0), 0)) + && (DECL_FUNCTION_CODE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0)) + == BUILT_IN_ALLOCA)) + return 1; + + /* Third operand is RTL. */ + length = 2; + break; + + case SAVE_EXPR: + if (SAVE_EXPR_RTL (exp) != 0) + return 0; + break; + + case BLOCK: + { + register tree local; + + for (local = BLOCK_VARS (exp); local; local = TREE_CHAIN (local)) + if (DECL_INITIAL (local) != 0 + && calls_function (DECL_INITIAL (local), which)) + return 1; + } + { + register tree subblock; + + for (subblock = BLOCK_SUBBLOCKS (exp); + subblock; + subblock = TREE_CHAIN (subblock)) + if (calls_function (subblock, which)) + return 1; + } + return 0; + + case METHOD_CALL_EXPR: + length = 3; + break; + + case WITH_CLEANUP_EXPR: + length = 1; + break; + + case RTL_EXPR: + return 0; + } + + for (i = 0; i < length; i++) + if (TREE_OPERAND (exp, i) != 0 + && calls_function (TREE_OPERAND (exp, i), which)) + return 1; + + return 0; +} + +/* Force FUNEXP into a form suitable for the address of a CALL, + and return that as an rtx. Also load the static chain register + if FNDECL is a nested function. + + USE_INSNS points to a variable holding a chain of USE insns + to which a USE of the static chain + register should be added, if required. */ + +rtx +prepare_call_address (funexp, fndecl, use_insns) + rtx funexp; + tree fndecl; + rtx *use_insns; +{ + rtx static_chain_value = 0; + + funexp = protect_from_queue (funexp, 0); + + if (fndecl != 0) + /* Get possible static chain value for nested function in C. */ + static_chain_value = lookup_static_chain (fndecl); + + /* Make a valid memory address and copy constants thru pseudo-regs, + but not for a constant address if -fno-function-cse. */ + if (GET_CODE (funexp) != SYMBOL_REF) + funexp = memory_address (FUNCTION_MODE, funexp); + else + { +#ifndef NO_FUNCTION_CSE + if (optimize && ! flag_no_function_cse) +#ifdef NO_RECURSIVE_FUNCTION_CSE + if (fndecl != current_function_decl) +#endif + funexp = force_reg (Pmode, funexp); +#endif + } + + if (static_chain_value != 0) + { + emit_move_insn (static_chain_rtx, static_chain_value); + + /* Put the USE insn in the chain we were passed. It will later be + output immediately in front of the CALL insn. */ + push_to_sequence (*use_insns); + emit_insn (gen_rtx (USE, VOIDmode, static_chain_rtx)); + *use_insns = get_insns (); + end_sequence (); + } + + return funexp; +} + +/* Generate instructions to call function FUNEXP, + and optionally pop the results. + The CALL_INSN is the first insn generated. + + FUNTYPE is the data type of the function, or, for a library call, + the identifier for the name of the call. This is given to the + macro RETURN_POPS_ARGS to determine whether this function pops its own args. + + STACK_SIZE is the number of bytes of arguments on the stack, + rounded up to STACK_BOUNDARY; zero if the size is variable. + This is both to put into the call insn and + to generate explicit popping code if necessary. + + STRUCT_VALUE_SIZE is the number of bytes wanted in a structure value. + It is zero if this call doesn't want a structure value. + + NEXT_ARG_REG is the rtx that results from executing + FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1) + just after all the args have had their registers assigned. + This could be whatever you like, but normally it is the first + arg-register beyond those used for args in this call, + or 0 if all the arg-registers are used in this call. + It is passed on to `gen_call' so you can put this info in the call insn. + + VALREG is a hard register in which a value is returned, + or 0 if the call does not return a value. + + OLD_INHIBIT_DEFER_POP is the value that `inhibit_defer_pop' had before + the args to this call were processed. + We restore `inhibit_defer_pop' to that value. + + USE_INSNS is a chain of USE insns to be emitted immediately before + the actual CALL insn. + + IS_CONST is true if this is a `const' call. */ + +static void +emit_call_1 (funexp, funtype, stack_size, struct_value_size, next_arg_reg, + valreg, old_inhibit_defer_pop, use_insns, is_const) + rtx funexp; + tree funtype; + int stack_size; + int struct_value_size; + rtx next_arg_reg; + rtx valreg; + int old_inhibit_defer_pop; + rtx use_insns; + int is_const; +{ + rtx stack_size_rtx = GEN_INT (stack_size); + rtx struct_value_size_rtx = GEN_INT (struct_value_size); + rtx call_insn; + int already_popped = 0; + + /* Ensure address is valid. SYMBOL_REF is already valid, so no need, + and we don't want to load it into a register as an optimization, + because prepare_call_address already did it if it should be done. */ + if (GET_CODE (funexp) != SYMBOL_REF) + funexp = memory_address (FUNCTION_MODE, funexp); + +#ifndef ACCUMULATE_OUTGOING_ARGS +#if defined (HAVE_call_pop) && defined (HAVE_call_value_pop) + if (HAVE_call_pop && HAVE_call_value_pop + && (RETURN_POPS_ARGS (funtype, stack_size) > 0 || stack_size == 0)) + { + rtx n_pop = GEN_INT (RETURN_POPS_ARGS (funtype, stack_size)); + rtx pat; + + /* If this subroutine pops its own args, record that in the call insn + if possible, for the sake of frame pointer elimination. */ + if (valreg) + pat = gen_call_value_pop (valreg, + gen_rtx (MEM, FUNCTION_MODE, funexp), + stack_size_rtx, next_arg_reg, n_pop); + else + pat = gen_call_pop (gen_rtx (MEM, FUNCTION_MODE, funexp), + stack_size_rtx, next_arg_reg, n_pop); + + emit_call_insn (pat); + already_popped = 1; + } + else +#endif +#endif + +#if defined (HAVE_call) && defined (HAVE_call_value) + if (HAVE_call && HAVE_call_value) + { + if (valreg) + emit_call_insn (gen_call_value (valreg, + gen_rtx (MEM, FUNCTION_MODE, funexp), + stack_size_rtx, next_arg_reg, + NULL_RTX)); + else + emit_call_insn (gen_call (gen_rtx (MEM, FUNCTION_MODE, funexp), + stack_size_rtx, next_arg_reg, + struct_value_size_rtx)); + } + else +#endif + abort (); + + /* Find the CALL insn we just emitted and write the USE insns before it. */ + for (call_insn = get_last_insn (); + call_insn && GET_CODE (call_insn) != CALL_INSN; + call_insn = PREV_INSN (call_insn)) + ; + + if (! call_insn) + abort (); + + /* Put the USE insns before the CALL. */ + emit_insns_before (use_insns, call_insn); + + /* If this is a const call, then set the insn's unchanging bit. */ + if (is_const) + CONST_CALL_P (call_insn) = 1; + + /* Restore this now, so that we do defer pops for this call's args + if the context of the call as a whole permits. */ + inhibit_defer_pop = old_inhibit_defer_pop; + +#ifndef ACCUMULATE_OUTGOING_ARGS + /* If returning from the subroutine does not automatically pop the args, + we need an instruction to pop them sooner or later. + Perhaps do it now; perhaps just record how much space to pop later. + + If returning from the subroutine does pop the args, indicate that the + stack pointer will be changed. */ + + if (stack_size != 0 && RETURN_POPS_ARGS (funtype, stack_size) > 0) + { + if (!already_popped) + emit_insn (gen_rtx (CLOBBER, VOIDmode, stack_pointer_rtx)); + stack_size -= RETURN_POPS_ARGS (funtype, stack_size); + stack_size_rtx = GEN_INT (stack_size); + } + + if (stack_size != 0) + { + if (flag_defer_pop && inhibit_defer_pop == 0 && !is_const) + pending_stack_adjust += stack_size; + else + adjust_stack (stack_size_rtx); + } +#endif +} + +/* Generate all the code for a function call + and return an rtx for its value. + Store the value in TARGET (specified as an rtx) if convenient. + If the value is stored in TARGET then TARGET is returned. + If IGNORE is nonzero, then we ignore the value of the function call. */ + +rtx +expand_call (exp, target, ignore) + tree exp; + rtx target; + int ignore; +{ + /* List of actual parameters. */ + tree actparms = TREE_OPERAND (exp, 1); + /* RTX for the function to be called. */ + rtx funexp; + /* Tree node for the function to be called (not the address!). */ + tree funtree; + /* Data type of the function. */ + tree funtype; + /* Declaration of the function being called, + or 0 if the function is computed (not known by name). */ + tree fndecl = 0; + char *name = 0; + + /* Register in which non-BLKmode value will be returned, + or 0 if no value or if value is BLKmode. */ + rtx valreg; + /* Address where we should return a BLKmode value; + 0 if value not BLKmode. */ + rtx structure_value_addr = 0; + /* Nonzero if that address is being passed by treating it as + an extra, implicit first parameter. Otherwise, + it is passed by being copied directly into struct_value_rtx. */ + int structure_value_addr_parm = 0; + /* Size of aggregate value wanted, or zero if none wanted + or if we are using the non-reentrant PCC calling convention + or expecting the value in registers. */ + int struct_value_size = 0; + /* Nonzero if called function returns an aggregate in memory PCC style, + by returning the address of where to find it. */ + int pcc_struct_value = 0; + + /* Number of actual parameters in this call, including struct value addr. */ + int num_actuals; + /* Number of named args. Args after this are anonymous ones + and they must all go on the stack. */ + int n_named_args; + /* Count arg position in order args appear. */ + int argpos; + + /* Vector of information about each argument. + Arguments are numbered in the order they will be pushed, + not the order they are written. */ + struct arg_data *args; + + /* Total size in bytes of all the stack-parms scanned so far. */ + struct args_size args_size; + /* Size of arguments before any adjustments (such as rounding). */ + struct args_size original_args_size; + /* Data on reg parms scanned so far. */ + CUMULATIVE_ARGS args_so_far; + /* Nonzero if a reg parm has been scanned. */ + int reg_parm_seen; + /* Nonzero if this is an indirect function call. */ + int current_call_is_indirect = 0; + + /* Nonzero if we must avoid push-insns in the args for this call. + If stack space is allocated for register parameters, but not by the + caller, then it is preallocated in the fixed part of the stack frame. + So the entire argument block must then be preallocated (i.e., we + ignore PUSH_ROUNDING in that case). */ + +#if defined(REG_PARM_STACK_SPACE) && ! defined(OUTGOING_REG_PARM_STACK_SPACE) + int must_preallocate = 1; +#else +#ifdef PUSH_ROUNDING + int must_preallocate = 0; +#else + int must_preallocate = 1; +#endif +#endif + + /* Size of the stack reserved for parameter registers. */ + int reg_parm_stack_space = 0; + + /* 1 if scanning parms front to back, -1 if scanning back to front. */ + int inc; + /* Address of space preallocated for stack parms + (on machines that lack push insns), or 0 if space not preallocated. */ + rtx argblock = 0; + + /* Nonzero if it is plausible that this is a call to alloca. */ + int may_be_alloca; + /* Nonzero if this is a call to setjmp or a related function. */ + int returns_twice; + /* Nonzero if this is a call to `longjmp'. */ + int is_longjmp; + /* Nonzero if this is a call to an inline function. */ + int is_integrable = 0; + /* Nonzero if this is a call to a `const' function. + Note that only explicitly named functions are handled as `const' here. */ + int is_const = 0; + /* Nonzero if this is a call to a `volatile' function. */ + int is_volatile = 0; +#if defined(ACCUMULATE_OUTGOING_ARGS) && defined(REG_PARM_STACK_SPACE) + /* Define the boundary of the register parm stack space that needs to be + save, if any. */ + int low_to_save = -1, high_to_save; + rtx save_area = 0; /* Place that it is saved */ +#endif + +#ifdef ACCUMULATE_OUTGOING_ARGS + int initial_highest_arg_in_use = highest_outgoing_arg_in_use; + char *initial_stack_usage_map = stack_usage_map; +#endif + + rtx old_stack_level = 0; + int old_pending_adj; + int old_stack_arg_under_construction; + int old_inhibit_defer_pop = inhibit_defer_pop; + tree old_cleanups = cleanups_this_call; + + rtx use_insns = 0; + + register tree p; + register int i, j; + + /* See if we can find a DECL-node for the actual function. + As a result, decide whether this is a call to an integrable function. */ + + p = TREE_OPERAND (exp, 0); + if (TREE_CODE (p) == ADDR_EXPR) + { + fndecl = TREE_OPERAND (p, 0); + if (TREE_CODE (fndecl) != FUNCTION_DECL) + { + /* May still be a `const' function if it is + a call through a pointer-to-const. + But we don't handle that. */ + fndecl = 0; + } + else + { + if (!flag_no_inline + && fndecl != current_function_decl + && DECL_SAVED_INSNS (fndecl)) + is_integrable = 1; + else if (! TREE_ADDRESSABLE (fndecl)) + { + /* In case this function later becomes inlinable, + record that there was already a non-inline call to it. + + Use abstraction instead of setting TREE_ADDRESSABLE + directly. */ + if (DECL_INLINE (fndecl) && extra_warnings && warn_inline + && !flag_no_inline) + warning_with_decl (fndecl, "can't inline call to `%s' which was declared inline"); + mark_addressable (fndecl); + } + + if (TREE_READONLY (fndecl) && ! TREE_THIS_VOLATILE (fndecl) + && TYPE_MODE (TREE_TYPE (exp)) != VOIDmode) + is_const = 1; + } + } + + is_volatile = TYPE_VOLATILE (TREE_TYPE (TREE_TYPE (p))); + +#ifdef REG_PARM_STACK_SPACE +#ifdef MAYBE_REG_PARM_STACK_SPACE + reg_parm_stack_space = MAYBE_REG_PARM_STACK_SPACE; +#else + reg_parm_stack_space = REG_PARM_STACK_SPACE (fndecl); +#endif +#endif + + /* Warn if this value is an aggregate type, + regardless of which calling convention we are using for it. */ + if (warn_aggregate_return + && (TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (exp)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (exp)) == QUAL_UNION_TYPE + || TREE_CODE (TREE_TYPE (exp)) == ARRAY_TYPE)) + warning ("function call has aggregate value"); + + /* Set up a place to return a structure. */ + + /* Cater to broken compilers. */ + if (aggregate_value_p (exp)) + { + /* This call returns a big structure. */ + is_const = 0; + +#ifdef PCC_STATIC_STRUCT_RETURN + { + pcc_struct_value = 1; + is_integrable = 0; /* Easier than making that case work right. */ + } +#else /* not PCC_STATIC_STRUCT_RETURN */ + { + struct_value_size = int_size_in_bytes (TREE_TYPE (exp)); + + if (struct_value_size < 0) + abort (); + + if (target && GET_CODE (target) == MEM) + structure_value_addr = XEXP (target, 0); + else + { + /* Assign a temporary on the stack to hold the value. */ + + /* For variable-sized objects, we must be called with a target + specified. If we were to allocate space on the stack here, + we would have no way of knowing when to free it. */ + + structure_value_addr + = XEXP (assign_stack_temp (BLKmode, struct_value_size, 1), 0); + target = 0; + } + } +#endif /* not PCC_STATIC_STRUCT_RETURN */ + } + + /* If called function is inline, try to integrate it. */ + + if (is_integrable) + { + rtx temp; + rtx before_call = get_last_insn (); + + temp = expand_inline_function (fndecl, actparms, target, + ignore, TREE_TYPE (exp), + structure_value_addr); + + /* If inlining succeeded, return. */ + if ((HOST_WIDE_INT) temp != -1) + { + /* Perform all cleanups needed for the arguments of this call + (i.e. destructors in C++). It is ok if these destructors + clobber RETURN_VALUE_REG, because the only time we care about + this is when TARGET is that register. But in C++, we take + care to never return that register directly. */ + expand_cleanups_to (old_cleanups); + +#ifdef ACCUMULATE_OUTGOING_ARGS + /* If the outgoing argument list must be preserved, push + the stack before executing the inlined function if it + makes any calls. */ + + for (i = reg_parm_stack_space - 1; i >= 0; i--) + if (i < highest_outgoing_arg_in_use && stack_usage_map[i] != 0) + break; + + if (stack_arg_under_construction || i >= 0) + { + rtx insn = NEXT_INSN (before_call), seq; + + /* Look for a call in the inline function code. + If OUTGOING_ARGS_SIZE (DECL_SAVED_INSNS (fndecl)) is + nonzero then there is a call and it is not necessary + to scan the insns. */ + + if (OUTGOING_ARGS_SIZE (DECL_SAVED_INSNS (fndecl)) == 0) + for (; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == CALL_INSN) + break; + + if (insn) + { + /* Reserve enough stack space so that the largest + argument list of any function call in the inline + function does not overlap the argument list being + evaluated. This is usually an overestimate because + allocate_dynamic_stack_space reserves space for an + outgoing argument list in addition to the requested + space, but there is no way to ask for stack space such + that an argument list of a certain length can be + safely constructed. */ + + int adjust = OUTGOING_ARGS_SIZE (DECL_SAVED_INSNS (fndecl)); +#ifdef REG_PARM_STACK_SPACE + /* Add the stack space reserved for register arguments + in the inline function. What is really needed is the + largest value of reg_parm_stack_space in the inline + function, but that is not available. Using the current + value of reg_parm_stack_space is wrong, but gives + correct results on all supported machines. */ + adjust += reg_parm_stack_space; +#endif + start_sequence (); + emit_stack_save (SAVE_BLOCK, &old_stack_level, NULL_RTX); + allocate_dynamic_stack_space (GEN_INT (adjust), + NULL_RTX, BITS_PER_UNIT); + seq = get_insns (); + end_sequence (); + emit_insns_before (seq, NEXT_INSN (before_call)); + emit_stack_restore (SAVE_BLOCK, old_stack_level, NULL_RTX); + } + } +#endif + + /* If the result is equivalent to TARGET, return TARGET to simplify + checks in store_expr. They can be equivalent but not equal in the + case of a function that returns BLKmode. */ + if (temp != target && rtx_equal_p (temp, target)) + return target; + return temp; + } + + /* If inlining failed, mark FNDECL as needing to be compiled + separately after all. */ + mark_addressable (fndecl); + } + + /* When calling a const function, we must pop the stack args right away, + so that the pop is deleted or moved with the call. */ + if (is_const) + NO_DEFER_POP; + + function_call_count++; + + if (fndecl && DECL_NAME (fndecl)) + name = IDENTIFIER_POINTER (DECL_NAME (fndecl)); + + /* On some machines (such as the PA) indirect calls have a different + calling convention than normal calls. FUNCTION_ARG in the target + description can look at current_call_is_indirect to determine which + calling convention to use. */ + current_call_is_indirect = (fndecl == 0); +#if 0 + = TREE_CODE (TREE_OPERAND (exp, 0)) == NON_LVALUE_EXPR ? 1 : 0; +#endif + +#if 0 + /* Unless it's a call to a specific function that isn't alloca, + if it has one argument, we must assume it might be alloca. */ + + may_be_alloca = + (!(fndecl != 0 && strcmp (name, "alloca")) + && actparms != 0 + && TREE_CHAIN (actparms) == 0); +#else + /* We assume that alloca will always be called by name. It + makes no sense to pass it as a pointer-to-function to + anything that does not understand its behavior. */ + may_be_alloca = + (name && ((IDENTIFIER_LENGTH (DECL_NAME (fndecl)) == 6 + && name[0] == 'a' + && ! strcmp (name, "alloca")) + || (IDENTIFIER_LENGTH (DECL_NAME (fndecl)) == 16 + && name[0] == '_' + && ! strcmp (name, "__builtin_alloca")))); +#endif + + /* See if this is a call to a function that can return more than once + or a call to longjmp. */ + + returns_twice = 0; + is_longjmp = 0; + + if (name != 0 && IDENTIFIER_LENGTH (DECL_NAME (fndecl)) <= 15) + { + char *tname = name; + + if (name[0] == '_') + tname += ((name[1] == '_' && name[2] == 'x') ? 3 : 1); + + if (tname[0] == 's') + { + returns_twice + = ((tname[1] == 'e' + && (! strcmp (tname, "setjmp") + || ! strcmp (tname, "setjmp_syscall"))) + || (tname[1] == 'i' + && ! strcmp (tname, "sigsetjmp")) + || (tname[1] == 'a' + && ! strcmp (tname, "savectx"))); + if (tname[1] == 'i' + && ! strcmp (tname, "siglongjmp")) + is_longjmp = 1; + } + else if ((tname[0] == 'q' && tname[1] == 's' + && ! strcmp (tname, "qsetjmp")) + || (tname[0] == 'v' && tname[1] == 'f' + && ! strcmp (tname, "vfork"))) + returns_twice = 1; + + else if (tname[0] == 'l' && tname[1] == 'o' + && ! strcmp (tname, "longjmp")) + is_longjmp = 1; + } + + if (may_be_alloca) + current_function_calls_alloca = 1; + + /* Don't let pending stack adjusts add up to too much. + Also, do all pending adjustments now + if there is any chance this might be a call to alloca. */ + + if (pending_stack_adjust >= 32 + || (pending_stack_adjust > 0 && may_be_alloca)) + do_pending_stack_adjust (); + + /* Operand 0 is a pointer-to-function; get the type of the function. */ + funtype = TREE_TYPE (TREE_OPERAND (exp, 0)); + if (TREE_CODE (funtype) != POINTER_TYPE) + abort (); + funtype = TREE_TYPE (funtype); + + /* Push the temporary stack slot level so that we can free temporaries used + by each of the arguments separately. */ + push_temp_slots (); + + /* Start updating where the next arg would go. */ + INIT_CUMULATIVE_ARGS (args_so_far, funtype, NULL_RTX); + + /* If struct_value_rtx is 0, it means pass the address + as if it were an extra parameter. */ + if (structure_value_addr && struct_value_rtx == 0) + { +#ifdef ACCUMULATE_OUTGOING_ARGS + /* If the stack will be adjusted, make sure the structure address + does not refer to virtual_outgoing_args_rtx. */ + rtx temp = (stack_arg_under_construction + ? copy_addr_to_reg (structure_value_addr) + : force_reg (Pmode, structure_value_addr)); +#else + rtx temp = force_reg (Pmode, structure_value_addr); +#endif + + actparms + = tree_cons (error_mark_node, + make_tree (build_pointer_type (TREE_TYPE (funtype)), + temp), + actparms); + structure_value_addr_parm = 1; + } + + /* Count the arguments and set NUM_ACTUALS. */ + for (p = actparms, i = 0; p; p = TREE_CHAIN (p)) i++; + num_actuals = i; + + /* Compute number of named args. + Normally, don't include the last named arg if anonymous args follow. + (If no anonymous args follow, the result of list_length + is actually one too large.) + + If SETUP_INCOMING_VARARGS is defined, this machine will be able to + place unnamed args that were passed in registers into the stack. So + treat all args as named. This allows the insns emitting for a specific + argument list to be independent of the function declaration. + + If SETUP_INCOMING_VARARGS is not defined, we do not have any reliable + way to pass unnamed args in registers, so we must force them into + memory. */ +#ifndef SETUP_INCOMING_VARARGS + if (TYPE_ARG_TYPES (funtype) != 0) + n_named_args + = list_length (TYPE_ARG_TYPES (funtype)) - 1 + /* Count the struct value address, if it is passed as a parm. */ + + structure_value_addr_parm; + else +#endif + /* If we know nothing, treat all args as named. */ + n_named_args = num_actuals; + + /* Make a vector to hold all the information about each arg. */ + args = (struct arg_data *) alloca (num_actuals * sizeof (struct arg_data)); + bzero (args, num_actuals * sizeof (struct arg_data)); + + args_size.constant = 0; + args_size.var = 0; + + /* In this loop, we consider args in the order they are written. + We fill up ARGS from the front of from the back if necessary + so that in any case the first arg to be pushed ends up at the front. */ + +#ifdef PUSH_ARGS_REVERSED + i = num_actuals - 1, inc = -1; + /* In this case, must reverse order of args + so that we compute and push the last arg first. */ +#else + i = 0, inc = 1; +#endif + + /* I counts args in order (to be) pushed; ARGPOS counts in order written. */ + for (p = actparms, argpos = 0; p; p = TREE_CHAIN (p), i += inc, argpos++) + { + tree type = TREE_TYPE (TREE_VALUE (p)); + enum machine_mode mode; + + args[i].tree_value = TREE_VALUE (p); + + /* Replace erroneous argument with constant zero. */ + if (type == error_mark_node || TYPE_SIZE (type) == 0) + args[i].tree_value = integer_zero_node, type = integer_type_node; + + /* Decide where to pass this arg. + + args[i].reg is nonzero if all or part is passed in registers. + + args[i].partial is nonzero if part but not all is passed in registers, + and the exact value says how many words are passed in registers. + + args[i].pass_on_stack is nonzero if the argument must at least be + computed on the stack. It may then be loaded back into registers + if args[i].reg is nonzero. + + These decisions are driven by the FUNCTION_... macros and must agree + with those made by function.c. */ + +#ifdef FUNCTION_ARG_PASS_BY_REFERENCE + /* See if this argument should be passed by invisible reference. */ + if (FUNCTION_ARG_PASS_BY_REFERENCE (args_so_far, TYPE_MODE (type), type, + argpos < n_named_args)) + { +#ifdef FUNCTION_ARG_CALLEE_COPIES + if (FUNCTION_ARG_CALLEE_COPIES (args_so_far, TYPE_MODE (type), type, + argpos < n_named_args) + /* If it's in a register, we must make a copy of it too. */ + /* ??? Is this a sufficient test? Is there a better one? */ + && !(TREE_CODE (args[i].tree_value) == VAR_DECL + && REG_P (DECL_RTL (args[i].tree_value)))) + { + args[i].tree_value = build1 (ADDR_EXPR, + build_pointer_type (type), + args[i].tree_value); + type = build_pointer_type (type); + } + else +#endif + { + /* We make a copy of the object and pass the address to the + function being called. */ + rtx copy; + + if (TYPE_SIZE (type) == 0 + || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) + { + /* This is a variable-sized object. Make space on the stack + for it. */ + rtx size_rtx = expr_size (TREE_VALUE (p)); + + if (old_stack_level == 0) + { + emit_stack_save (SAVE_BLOCK, &old_stack_level, NULL_RTX); + old_pending_adj = pending_stack_adjust; + pending_stack_adjust = 0; + } + + copy = gen_rtx (MEM, BLKmode, + allocate_dynamic_stack_space (size_rtx, + NULL_RTX, + TYPE_ALIGN (type))); + } + else + { + int size = int_size_in_bytes (type); + copy = assign_stack_temp (TYPE_MODE (type), size, 1); + } + + store_expr (args[i].tree_value, copy, 0); + + args[i].tree_value = build1 (ADDR_EXPR, + build_pointer_type (type), + make_tree (type, copy)); + type = build_pointer_type (type); + } + } +#endif /* FUNCTION_ARG_PASS_BY_REFERENCE */ + + mode = TYPE_MODE (type); + +#ifdef PROMOTE_FUNCTION_ARGS + /* Compute the mode in which the arg is actually to be extended to. */ + if (TREE_CODE (type) == INTEGER_TYPE || TREE_CODE (type) == ENUMERAL_TYPE + || TREE_CODE (type) == BOOLEAN_TYPE || TREE_CODE (type) == CHAR_TYPE + || TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == POINTER_TYPE + || TREE_CODE (type) == OFFSET_TYPE) + { + int unsignedp = TREE_UNSIGNED (type); + PROMOTE_MODE (mode, unsignedp, type); + args[i].unsignedp = unsignedp; + } +#endif + + args[i].mode = mode; + args[i].reg = FUNCTION_ARG (args_so_far, mode, type, + argpos < n_named_args); +#ifdef FUNCTION_ARG_PARTIAL_NREGS + if (args[i].reg) + args[i].partial + = FUNCTION_ARG_PARTIAL_NREGS (args_so_far, mode, type, + argpos < n_named_args); +#endif + + args[i].pass_on_stack = MUST_PASS_IN_STACK (mode, type); + + /* If FUNCTION_ARG returned an (expr_list (nil) FOO), it means that + we are to pass this arg in the register(s) designated by FOO, but + also to pass it in the stack. */ + if (args[i].reg && GET_CODE (args[i].reg) == EXPR_LIST + && XEXP (args[i].reg, 0) == 0) + args[i].pass_on_stack = 1, args[i].reg = XEXP (args[i].reg, 1); + + /* If this is an addressable type, we must preallocate the stack + since we must evaluate the object into its final location. + + If this is to be passed in both registers and the stack, it is simpler + to preallocate. */ + if (TREE_ADDRESSABLE (type) + || (args[i].pass_on_stack && args[i].reg != 0)) + must_preallocate = 1; + + /* If this is an addressable type, we cannot pre-evaluate it. Thus, + we cannot consider this function call constant. */ + if (TREE_ADDRESSABLE (type)) + is_const = 0; + + /* Compute the stack-size of this argument. */ + if (args[i].reg == 0 || args[i].partial != 0 +#ifdef REG_PARM_STACK_SPACE + || reg_parm_stack_space > 0 +#endif + || args[i].pass_on_stack) + locate_and_pad_parm (mode, type, +#ifdef STACK_PARMS_IN_REG_PARM_AREA + 1, +#else + args[i].reg != 0, +#endif + fndecl, &args_size, &args[i].offset, + &args[i].size); + +#ifndef ARGS_GROW_DOWNWARD + args[i].slot_offset = args_size; +#endif + +#ifndef REG_PARM_STACK_SPACE + /* If a part of the arg was put into registers, + don't include that part in the amount pushed. */ + if (! args[i].pass_on_stack) + args[i].size.constant -= ((args[i].partial * UNITS_PER_WORD) + / (PARM_BOUNDARY / BITS_PER_UNIT) + * (PARM_BOUNDARY / BITS_PER_UNIT)); +#endif + + /* Update ARGS_SIZE, the total stack space for args so far. */ + + args_size.constant += args[i].size.constant; + if (args[i].size.var) + { + ADD_PARM_SIZE (args_size, args[i].size.var); + } + + /* Since the slot offset points to the bottom of the slot, + we must record it after incrementing if the args grow down. */ +#ifdef ARGS_GROW_DOWNWARD + args[i].slot_offset = args_size; + + args[i].slot_offset.constant = -args_size.constant; + if (args_size.var) + { + SUB_PARM_SIZE (args[i].slot_offset, args_size.var); + } +#endif + + /* Increment ARGS_SO_FAR, which has info about which arg-registers + have been used, etc. */ + + FUNCTION_ARG_ADVANCE (args_so_far, TYPE_MODE (type), type, + argpos < n_named_args); + } + +#ifdef FINAL_REG_PARM_STACK_SPACE + reg_parm_stack_space = FINAL_REG_PARM_STACK_SPACE (args_size.constant, + args_size.var); +#endif + + /* Compute the actual size of the argument block required. The variable + and constant sizes must be combined, the size may have to be rounded, + and there may be a minimum required size. */ + + original_args_size = args_size; + if (args_size.var) + { + /* If this function requires a variable-sized argument list, don't try to + make a cse'able block for this call. We may be able to do this + eventually, but it is too complicated to keep track of what insns go + in the cse'able block and which don't. */ + + is_const = 0; + must_preallocate = 1; + + args_size.var = ARGS_SIZE_TREE (args_size); + args_size.constant = 0; + +#ifdef STACK_BOUNDARY + if (STACK_BOUNDARY != BITS_PER_UNIT) + args_size.var = round_up (args_size.var, STACK_BYTES); +#endif + +#ifdef REG_PARM_STACK_SPACE + if (reg_parm_stack_space > 0) + { + args_size.var + = size_binop (MAX_EXPR, args_size.var, + size_int (REG_PARM_STACK_SPACE (fndecl))); + +#ifndef OUTGOING_REG_PARM_STACK_SPACE + /* The area corresponding to register parameters is not to count in + the size of the block we need. So make the adjustment. */ + args_size.var + = size_binop (MINUS_EXPR, args_size.var, + size_int (reg_parm_stack_space)); +#endif + } +#endif + } + else + { +#ifdef STACK_BOUNDARY + args_size.constant = (((args_size.constant + (STACK_BYTES - 1)) + / STACK_BYTES) * STACK_BYTES); +#endif + +#ifdef REG_PARM_STACK_SPACE + args_size.constant = MAX (args_size.constant, + reg_parm_stack_space); +#ifdef MAYBE_REG_PARM_STACK_SPACE + if (reg_parm_stack_space == 0) + args_size.constant = 0; +#endif +#ifndef OUTGOING_REG_PARM_STACK_SPACE + args_size.constant -= reg_parm_stack_space; +#endif +#endif + } + + /* See if we have or want to preallocate stack space. + + If we would have to push a partially-in-regs parm + before other stack parms, preallocate stack space instead. + + If the size of some parm is not a multiple of the required stack + alignment, we must preallocate. + + If the total size of arguments that would otherwise create a copy in + a temporary (such as a CALL) is more than half the total argument list + size, preallocation is faster. + + Another reason to preallocate is if we have a machine (like the m88k) + where stack alignment is required to be maintained between every + pair of insns, not just when the call is made. However, we assume here + that such machines either do not have push insns (and hence preallocation + would occur anyway) or the problem is taken care of with + PUSH_ROUNDING. */ + + if (! must_preallocate) + { + int partial_seen = 0; + int copy_to_evaluate_size = 0; + + for (i = 0; i < num_actuals && ! must_preallocate; i++) + { + if (args[i].partial > 0 && ! args[i].pass_on_stack) + partial_seen = 1; + else if (partial_seen && args[i].reg == 0) + must_preallocate = 1; + + if (TYPE_MODE (TREE_TYPE (args[i].tree_value)) == BLKmode + && (TREE_CODE (args[i].tree_value) == CALL_EXPR + || TREE_CODE (args[i].tree_value) == TARGET_EXPR + || TREE_CODE (args[i].tree_value) == COND_EXPR + || TREE_ADDRESSABLE (TREE_TYPE (args[i].tree_value)))) + copy_to_evaluate_size + += int_size_in_bytes (TREE_TYPE (args[i].tree_value)); + } + + if (copy_to_evaluate_size * 2 >= args_size.constant + && args_size.constant > 0) + must_preallocate = 1; + } + + /* If the structure value address will reference the stack pointer, we must + stabilize it. We don't need to do this if we know that we are not going + to adjust the stack pointer in processing this call. */ + + if (structure_value_addr + && (reg_mentioned_p (virtual_stack_dynamic_rtx, structure_value_addr) + || reg_mentioned_p (virtual_outgoing_args_rtx, structure_value_addr)) + && (args_size.var +#ifndef ACCUMULATE_OUTGOING_ARGS + || args_size.constant +#endif + )) + structure_value_addr = copy_to_reg (structure_value_addr); + + /* If this function call is cse'able, precompute all the parameters. + Note that if the parameter is constructed into a temporary, this will + cause an additional copy because the parameter will be constructed + into a temporary location and then copied into the outgoing arguments. + If a parameter contains a call to alloca and this function uses the + stack, precompute the parameter. */ + + /* If we preallocated the stack space, and some arguments must be passed + on the stack, then we must precompute any parameter which contains a + function call which will store arguments on the stack. + Otherwise, evaluating the parameter may clobber previous parameters + which have already been stored into the stack. */ + + for (i = 0; i < num_actuals; i++) + if (is_const + || ((args_size.var != 0 || args_size.constant != 0) + && calls_function (args[i].tree_value, 1)) + || (must_preallocate && (args_size.var != 0 || args_size.constant != 0) + && calls_function (args[i].tree_value, 0))) + { + args[i].initial_value = args[i].value + = expand_expr (args[i].tree_value, NULL_RTX, VOIDmode, 0); + + if (GET_MODE (args[i].value ) != VOIDmode + && GET_MODE (args[i].value) != args[i].mode) + args[i].value = convert_to_mode (args[i].mode, args[i].value, + args[i].unsignedp); + preserve_temp_slots (args[i].value); + + free_temp_slots (); + + /* ANSI doesn't require a sequence point here, + but PCC has one, so this will avoid some problems. */ + emit_queue (); + } + + /* Now we are about to start emitting insns that can be deleted + if a libcall is deleted. */ + if (is_const) + start_sequence (); + + /* If we have no actual push instructions, or shouldn't use them, + make space for all args right now. */ + + if (args_size.var != 0) + { + if (old_stack_level == 0) + { + emit_stack_save (SAVE_BLOCK, &old_stack_level, NULL_RTX); + old_pending_adj = pending_stack_adjust; + pending_stack_adjust = 0; +#ifdef ACCUMULATE_OUTGOING_ARGS + /* stack_arg_under_construction says whether a stack arg is + being constructed at the old stack level. Pushing the stack + gets a clean outgoing argument block. */ + old_stack_arg_under_construction = stack_arg_under_construction; + stack_arg_under_construction = 0; +#endif + } + argblock = push_block (ARGS_SIZE_RTX (args_size), 0, 0); + } + else if (must_preallocate) + { + /* Note that we must go through the motions of allocating an argument + block even if the size is zero because we may be storing args + in the area reserved for register arguments, which may be part of + the stack frame. */ + int needed = args_size.constant; + +#ifdef ACCUMULATE_OUTGOING_ARGS + /* Store the maximum argument space used. It will be pushed by the + prologue. + + Since the stack pointer will never be pushed, it is possible for + the evaluation of a parm to clobber something we have already + written to the stack. Since most function calls on RISC machines + do not use the stack, this is uncommon, but must work correctly. + + Therefore, we save any area of the stack that was already written + and that we are using. Here we set up to do this by making a new + stack usage map from the old one. The actual save will be done + by store_one_arg. + + Another approach might be to try to reorder the argument + evaluations to avoid this conflicting stack usage. */ + + if (needed > current_function_outgoing_args_size) + current_function_outgoing_args_size = needed; + +#if defined(REG_PARM_STACK_SPACE) && ! defined(OUTGOING_REG_PARM_STACK_SPACE) + /* Since we will be writing into the entire argument area, the + map must be allocated for its entire size, not just the part that + is the responsibility of the caller. */ + needed += reg_parm_stack_space; +#endif + +#ifdef ARGS_GROW_DOWNWARD + highest_outgoing_arg_in_use = MAX (initial_highest_arg_in_use, + needed + 1); +#else + highest_outgoing_arg_in_use = MAX (initial_highest_arg_in_use, needed); +#endif + stack_usage_map = (char *) alloca (highest_outgoing_arg_in_use); + + if (initial_highest_arg_in_use) + bcopy (initial_stack_usage_map, stack_usage_map, + initial_highest_arg_in_use); + + if (initial_highest_arg_in_use != highest_outgoing_arg_in_use) + bzero (&stack_usage_map[initial_highest_arg_in_use], + highest_outgoing_arg_in_use - initial_highest_arg_in_use); + needed = 0; + + /* The address of the outgoing argument list must not be copied to a + register here, because argblock would be left pointing to the + wrong place after the call to allocate_dynamic_stack_space below. */ + + argblock = virtual_outgoing_args_rtx; + +#else /* not ACCUMULATE_OUTGOING_ARGS */ + if (inhibit_defer_pop == 0) + { + /* Try to reuse some or all of the pending_stack_adjust + to get this space. Maybe we can avoid any pushing. */ + if (needed > pending_stack_adjust) + { + needed -= pending_stack_adjust; + pending_stack_adjust = 0; + } + else + { + pending_stack_adjust -= needed; + needed = 0; + } + } + /* Special case this because overhead of `push_block' in this + case is non-trivial. */ + if (needed == 0) + argblock = virtual_outgoing_args_rtx; + else + argblock = push_block (GEN_INT (needed), 0, 0); + + /* We only really need to call `copy_to_reg' in the case where push + insns are going to be used to pass ARGBLOCK to a function + call in ARGS. In that case, the stack pointer changes value + from the allocation point to the call point, and hence + the value of VIRTUAL_OUTGOING_ARGS_RTX changes as well. + But might as well always do it. */ + argblock = copy_to_reg (argblock); +#endif /* not ACCUMULATE_OUTGOING_ARGS */ + } + + +#ifdef ACCUMULATE_OUTGOING_ARGS + /* The save/restore code in store_one_arg handles all cases except one: + a constructor call (including a C function returning a BLKmode struct) + to initialize an argument. */ + if (stack_arg_under_construction) + { +#if defined(REG_PARM_STACK_SPACE) && ! defined(OUTGOING_REG_PARM_STACK_SPACE) + rtx push_size = GEN_INT (reg_parm_stack_space + args_size.constant); +#else + rtx push_size = GEN_INT (args_size.constant); +#endif + if (old_stack_level == 0) + { + emit_stack_save (SAVE_BLOCK, &old_stack_level, NULL_RTX); + old_pending_adj = pending_stack_adjust; + pending_stack_adjust = 0; + /* stack_arg_under_construction says whether a stack arg is + being constructed at the old stack level. Pushing the stack + gets a clean outgoing argument block. */ + old_stack_arg_under_construction = stack_arg_under_construction; + stack_arg_under_construction = 0; + /* Make a new map for the new argument list. */ + stack_usage_map = (char *)alloca (highest_outgoing_arg_in_use); + bzero (stack_usage_map, highest_outgoing_arg_in_use); + highest_outgoing_arg_in_use = 0; + } + allocate_dynamic_stack_space (push_size, NULL_RTX, BITS_PER_UNIT); + } + /* If argument evaluation might modify the stack pointer, copy the + address of the argument list to a register. */ + for (i = 0; i < num_actuals; i++) + if (args[i].pass_on_stack) + { + argblock = copy_addr_to_reg (argblock); + break; + } +#endif + + + /* If we preallocated stack space, compute the address of each argument. + We need not ensure it is a valid memory address here; it will be + validized when it is used. */ + if (argblock) + { + rtx arg_reg = argblock; + int arg_offset = 0; + + if (GET_CODE (argblock) == PLUS) + arg_reg = XEXP (argblock, 0), arg_offset = INTVAL (XEXP (argblock, 1)); + + for (i = 0; i < num_actuals; i++) + { + rtx offset = ARGS_SIZE_RTX (args[i].offset); + rtx slot_offset = ARGS_SIZE_RTX (args[i].slot_offset); + rtx addr; + + /* Skip this parm if it will not be passed on the stack. */ + if (! args[i].pass_on_stack && args[i].reg != 0) + continue; + + if (GET_CODE (offset) == CONST_INT) + addr = plus_constant (arg_reg, INTVAL (offset)); + else + addr = gen_rtx (PLUS, Pmode, arg_reg, offset); + + addr = plus_constant (addr, arg_offset); + args[i].stack = gen_rtx (MEM, args[i].mode, addr); + + if (GET_CODE (slot_offset) == CONST_INT) + addr = plus_constant (arg_reg, INTVAL (slot_offset)); + else + addr = gen_rtx (PLUS, Pmode, arg_reg, slot_offset); + + addr = plus_constant (addr, arg_offset); + args[i].stack_slot = gen_rtx (MEM, args[i].mode, addr); + } + } + +#ifdef PUSH_ARGS_REVERSED +#ifdef STACK_BOUNDARY + /* If we push args individually in reverse order, perform stack alignment + before the first push (the last arg). */ + if (argblock == 0) + anti_adjust_stack (GEN_INT (args_size.constant + - original_args_size.constant)); +#endif +#endif + + /* Don't try to defer pops if preallocating, not even from the first arg, + since ARGBLOCK probably refers to the SP. */ + if (argblock) + NO_DEFER_POP; + + /* Get the function to call, in the form of RTL. */ + if (fndecl) + /* Get a SYMBOL_REF rtx for the function address. */ + funexp = XEXP (DECL_RTL (fndecl), 0); + else + /* Generate an rtx (probably a pseudo-register) for the address. */ + { + funexp = expand_expr (TREE_OPERAND (exp, 0), NULL_RTX, VOIDmode, 0); + free_temp_slots (); /* FUNEXP can't be BLKmode */ + emit_queue (); + } + + /* Figure out the register where the value, if any, will come back. */ + valreg = 0; + if (TYPE_MODE (TREE_TYPE (exp)) != VOIDmode + && ! structure_value_addr) + { + if (pcc_struct_value) + valreg = hard_function_value (build_pointer_type (TREE_TYPE (exp)), + fndecl); + else + valreg = hard_function_value (TREE_TYPE (exp), fndecl); + } + + /* Precompute all register parameters. It isn't safe to compute anything + once we have started filling any specific hard regs. */ + reg_parm_seen = 0; + for (i = 0; i < num_actuals; i++) + if (args[i].reg != 0 && ! args[i].pass_on_stack) + { + reg_parm_seen = 1; + + if (args[i].value == 0) + { + args[i].value = expand_expr (args[i].tree_value, NULL_RTX, + VOIDmode, 0); + preserve_temp_slots (args[i].value); + free_temp_slots (); + + /* ANSI doesn't require a sequence point here, + but PCC has one, so this will avoid some problems. */ + emit_queue (); + } + + /* If we are to promote the function arg to a wider mode, + do it now. */ + + if (GET_MODE (args[i].value) != VOIDmode + && GET_MODE (args[i].value) != args[i].mode) + args[i].value = convert_to_mode (args[i].mode, args[i].value, + args[i].unsignedp); + } + +#if defined(ACCUMULATE_OUTGOING_ARGS) && defined(REG_PARM_STACK_SPACE) + /* The argument list is the property of the called routine and it + may clobber it. If the fixed area has been used for previous + parameters, we must save and restore it. + + Here we compute the boundary of the that needs to be saved, if any. */ + +#ifdef ARGS_GROW_DOWNWARD + for (i = 0; i < reg_parm_stack_space + 1; i++) +#else + for (i = 0; i < reg_parm_stack_space; i++) +#endif + { + if (i >= highest_outgoing_arg_in_use + || stack_usage_map[i] == 0) + continue; + + if (low_to_save == -1) + low_to_save = i; + + high_to_save = i; + } + + if (low_to_save >= 0) + { + int num_to_save = high_to_save - low_to_save + 1; + enum machine_mode save_mode + = mode_for_size (num_to_save * BITS_PER_UNIT, MODE_INT, 1); + rtx stack_area; + + /* If we don't have the required alignment, must do this in BLKmode. */ + if ((low_to_save & (MIN (GET_MODE_SIZE (save_mode), + BIGGEST_ALIGNMENT / UNITS_PER_WORD) - 1))) + save_mode = BLKmode; + + stack_area = gen_rtx (MEM, save_mode, + memory_address (save_mode, + +#ifdef ARGS_GROW_DOWNWARD + plus_constant (argblock, + - high_to_save) +#else + plus_constant (argblock, + low_to_save) +#endif + )); + if (save_mode == BLKmode) + { + save_area = assign_stack_temp (BLKmode, num_to_save, 1); + emit_block_move (validize_mem (save_area), stack_area, + GEN_INT (num_to_save), + PARM_BOUNDARY / BITS_PER_UNIT); + } + else + { + save_area = gen_reg_rtx (save_mode); + emit_move_insn (save_area, stack_area); + } + } +#endif + + + /* Now store (and compute if necessary) all non-register parms. + These come before register parms, since they can require block-moves, + which could clobber the registers used for register parms. + Parms which have partial registers are not stored here, + but we do preallocate space here if they want that. */ + + for (i = 0; i < num_actuals; i++) + if (args[i].reg == 0 || args[i].pass_on_stack) + store_one_arg (&args[i], argblock, may_be_alloca, + args_size.var != 0, fndecl, reg_parm_stack_space); + +#ifdef STRICT_ALIGNMENT + /* If we have a parm that is passed in registers but not in memory + and whose alignment does not permit a direct copy into registers, + make a group of pseudos that correspond to each register that we + will later fill. */ + + for (i = 0; i < num_actuals; i++) + if (args[i].reg != 0 && ! args[i].pass_on_stack + && args[i].mode == BLKmode + && (TYPE_ALIGN (TREE_TYPE (args[i].tree_value)) + < MIN (BIGGEST_ALIGNMENT, BITS_PER_WORD))) + { + int bytes = int_size_in_bytes (TREE_TYPE (args[i].tree_value)); + + args[i].n_aligned_regs + = args[i].partial ? args[i].partial + : (bytes + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; + + args[i].aligned_regs = (rtx *) alloca (sizeof (rtx) + * args[i].n_aligned_regs); + + for (j = 0; j < args[i].n_aligned_regs; j++) + { + rtx reg = gen_reg_rtx (word_mode); + rtx word = operand_subword_force (args[i].value, j, BLKmode); + int bitsize = TYPE_ALIGN (TREE_TYPE (args[i].tree_value)); + int bitpos; + + args[i].aligned_regs[j] = reg; + + /* Clobber REG and move each partword into it. Ensure we don't + go past the end of the structure. Note that the loop below + works because we've already verified that padding + and endianness are compatible. */ + + emit_insn (gen_rtx (CLOBBER, VOIDmode, reg)); + + for (bitpos = 0; + bitpos < BITS_PER_WORD && bytes > 0; + bitpos += bitsize, bytes -= bitsize / BITS_PER_UNIT) + { + int xbitpos = (BYTES_BIG_ENDIAN + ? BITS_PER_WORD - bitpos - bitsize + : bitpos); + + store_bit_field (reg, bitsize, xbitpos, word_mode, + extract_bit_field (word, bitsize, xbitpos, 1, + NULL_RTX, word_mode, + word_mode, + bitsize / BITS_PER_UNIT, + BITS_PER_WORD), + bitsize / BITS_PER_UNIT, BITS_PER_WORD); + } + } + } +#endif + + /* Now store any partially-in-registers parm. + This is the last place a block-move can happen. */ + if (reg_parm_seen) + for (i = 0; i < num_actuals; i++) + if (args[i].partial != 0 && ! args[i].pass_on_stack) + store_one_arg (&args[i], argblock, may_be_alloca, + args_size.var != 0, fndecl, reg_parm_stack_space); + +#ifndef PUSH_ARGS_REVERSED +#ifdef STACK_BOUNDARY + /* If we pushed args in forward order, perform stack alignment + after pushing the last arg. */ + if (argblock == 0) + anti_adjust_stack (GEN_INT (args_size.constant + - original_args_size.constant)); +#endif +#endif + + /* If register arguments require space on the stack and stack space + was not preallocated, allocate stack space here for arguments + passed in registers. */ +#if ! defined(ALLOCATE_OUTGOING_ARGS) && defined(OUTGOING_REG_PARM_STACK_SPACE) + if (must_preallocate == 0 && reg_parm_stack_space > 0) + anti_adjust_stack (GEN_INT (reg_parm_stack_space)); +#endif + + /* Pass the function the address in which to return a structure value. */ + if (structure_value_addr && ! structure_value_addr_parm) + { + emit_move_insn (struct_value_rtx, + force_reg (Pmode, + force_operand (structure_value_addr, + NULL_RTX))); + if (GET_CODE (struct_value_rtx) == REG) + { + push_to_sequence (use_insns); + emit_insn (gen_rtx (USE, VOIDmode, struct_value_rtx)); + use_insns = get_insns (); + end_sequence (); + } + } + + /* Now do the register loads required for any wholly-register parms or any + parms which are passed both on the stack and in a register. Their + expressions were already evaluated. + + Mark all register-parms as living through the call, putting these USE + insns in a list headed by USE_INSNS. */ + + for (i = 0; i < num_actuals; i++) + { + rtx list = args[i].reg; + int partial = args[i].partial; + + while (list) + { + rtx reg; + int nregs; + + /* Process each register that needs to get this arg. */ + if (GET_CODE (list) == EXPR_LIST) + reg = XEXP (list, 0), list = XEXP (list, 1); + else + reg = list, list = 0; + + /* Set to non-zero if must move a word at a time, even if just one + word (e.g, partial == 1 && mode == DFmode). Set to zero if + we just use a normal move insn. */ + nregs = (partial ? partial + : (TYPE_MODE (TREE_TYPE (args[i].tree_value)) == BLKmode + ? ((int_size_in_bytes (TREE_TYPE (args[i].tree_value)) + + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) + : 0)); + + /* If simple case, just do move. If normal partial, store_one_arg + has already loaded the register for us. In all other cases, + load the register(s) from memory. */ + + if (nregs == 0) + emit_move_insn (reg, args[i].value); + +#ifdef STRICT_ALIGNMENT + /* If we have pre-computed the values to put in the registers in + the case of non-aligned structures, copy them in now. */ + + else if (args[i].n_aligned_regs != 0) + for (j = 0; j < args[i].n_aligned_regs; j++) + emit_move_insn (gen_rtx (REG, word_mode, REGNO (reg) + j), + args[i].aligned_regs[j]); +#endif + + else if (args[i].partial == 0 || args[i].pass_on_stack) + move_block_to_reg (REGNO (reg), + validize_mem (args[i].value), nregs, + args[i].mode); + + push_to_sequence (use_insns); + if (nregs == 0) + emit_insn (gen_rtx (USE, VOIDmode, reg)); + else + use_regs (REGNO (reg), nregs); + use_insns = get_insns (); + end_sequence (); + + /* PARTIAL referred only to the first register, so clear it for the + next time. */ + partial = 0; + } + } + + /* Perform postincrements before actually calling the function. */ + emit_queue (); + + /* All arguments and registers used for the call must be set up by now! */ + + funexp = prepare_call_address (funexp, fndecl, &use_insns); + + /* Generate the actual call instruction. */ + emit_call_1 (funexp, funtype, args_size.constant, struct_value_size, + FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1), + valreg, old_inhibit_defer_pop, use_insns, is_const); + + /* If call is cse'able, make appropriate pair of reg-notes around it. + Test valreg so we don't crash; may safely ignore `const' + if return type is void. */ + if (is_const && valreg != 0) + { + rtx note = 0; + rtx temp = gen_reg_rtx (GET_MODE (valreg)); + rtx insns; + + /* Construct an "equal form" for the value which mentions all the + arguments in order as well as the function name. */ +#ifdef PUSH_ARGS_REVERSED + for (i = 0; i < num_actuals; i++) + note = gen_rtx (EXPR_LIST, VOIDmode, args[i].initial_value, note); +#else + for (i = num_actuals - 1; i >= 0; i--) + note = gen_rtx (EXPR_LIST, VOIDmode, args[i].initial_value, note); +#endif + note = gen_rtx (EXPR_LIST, VOIDmode, funexp, note); + + insns = get_insns (); + end_sequence (); + + emit_libcall_block (insns, temp, valreg, note); + + valreg = temp; + } + + /* For calls to `setjmp', etc., inform flow.c it should complain + if nonvolatile values are live. */ + + if (returns_twice) + { + emit_note (name, NOTE_INSN_SETJMP); + current_function_calls_setjmp = 1; + } + + if (is_longjmp) + current_function_calls_longjmp = 1; + + /* Notice functions that cannot return. + If optimizing, insns emitted below will be dead. + If not optimizing, they will exist, which is useful + if the user uses the `return' command in the debugger. */ + + if (is_volatile || is_longjmp) + emit_barrier (); + + /* If value type not void, return an rtx for the value. */ + + /* If there are cleanups to be called, don't use a hard reg as target. */ + if (cleanups_this_call != old_cleanups + && target && REG_P (target) + && REGNO (target) < FIRST_PSEUDO_REGISTER) + target = 0; + + if (TYPE_MODE (TREE_TYPE (exp)) == VOIDmode + || ignore) + { + target = const0_rtx; + } + else if (structure_value_addr) + { + if (target == 0 || GET_CODE (target) != MEM) + { + target = gen_rtx (MEM, TYPE_MODE (TREE_TYPE (exp)), + memory_address (TYPE_MODE (TREE_TYPE (exp)), + structure_value_addr)); + MEM_IN_STRUCT_P (target) + = (TREE_CODE (TREE_TYPE (exp)) == ARRAY_TYPE + || TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (exp)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (exp)) == QUAL_UNION_TYPE); + } + } + else if (pcc_struct_value) + { + if (target == 0) + { + /* We used leave the value in the location that it is + returned in, but that causes problems if it is used more + than once in one expression. Rather than trying to track + when a copy is required, we always copy when TARGET is + not specified. This calling sequence is only used on + a few machines and TARGET is usually nonzero. */ + if (TYPE_MODE (TREE_TYPE (exp)) == BLKmode) + { + target = assign_stack_temp (BLKmode, + int_size_in_bytes (TREE_TYPE (exp)), + 0); + + /* Save this temp slot around the pop below. */ + preserve_temp_slots (target); + } + else + target = gen_reg_rtx (TYPE_MODE (TREE_TYPE (exp))); + } + + if (TYPE_MODE (TREE_TYPE (exp)) != BLKmode) + emit_move_insn (target, gen_rtx (MEM, TYPE_MODE (TREE_TYPE (exp)), + copy_to_reg (valreg))); + else + emit_block_move (target, gen_rtx (MEM, BLKmode, copy_to_reg (valreg)), + expr_size (exp), + TYPE_ALIGN (TREE_TYPE (exp)) / BITS_PER_UNIT); + } + else if (target && GET_MODE (target) == TYPE_MODE (TREE_TYPE (exp)) + && GET_MODE (target) == GET_MODE (valreg)) + /* TARGET and VALREG cannot be equal at this point because the latter + would not have REG_FUNCTION_VALUE_P true, while the former would if + it were referring to the same register. + + If they refer to the same register, this move will be a no-op, except + when function inlining is being done. */ + emit_move_insn (target, valreg); + else + target = copy_to_reg (valreg); + +#ifdef PROMOTE_FUNCTION_RETURN + /* If we promoted this return value, make the proper SUBREG. TARGET + might be const0_rtx here, so be careful. */ + if (GET_CODE (target) == REG + && GET_MODE (target) != TYPE_MODE (TREE_TYPE (exp))) + { + enum machine_mode mode = TYPE_MODE (TREE_TYPE (exp)); + int unsignedp = TREE_UNSIGNED (TREE_TYPE (exp)); + + if (TREE_CODE (TREE_TYPE (exp)) == INTEGER_TYPE + || TREE_CODE (TREE_TYPE (exp)) == ENUMERAL_TYPE + || TREE_CODE (TREE_TYPE (exp)) == BOOLEAN_TYPE + || TREE_CODE (TREE_TYPE (exp)) == CHAR_TYPE + || TREE_CODE (TREE_TYPE (exp)) == REAL_TYPE + || TREE_CODE (TREE_TYPE (exp)) == POINTER_TYPE + || TREE_CODE (TREE_TYPE (exp)) == OFFSET_TYPE) + { + PROMOTE_MODE (mode, unsignedp, TREE_TYPE (exp)); + } + + /* If we didn't promote as expected, something is wrong. */ + if (mode != GET_MODE (target)) + abort (); + + target = gen_rtx (SUBREG, TYPE_MODE (TREE_TYPE (exp)), target, 0); + SUBREG_PROMOTED_VAR_P (target) = 1; + SUBREG_PROMOTED_UNSIGNED_P (target) = unsignedp; + } +#endif + + /* Perform all cleanups needed for the arguments of this call + (i.e. destructors in C++). */ + expand_cleanups_to (old_cleanups); + + /* If size of args is variable or this was a constructor call for a stack + argument, restore saved stack-pointer value. */ + + if (old_stack_level) + { + emit_stack_restore (SAVE_BLOCK, old_stack_level, NULL_RTX); + pending_stack_adjust = old_pending_adj; +#ifdef ACCUMULATE_OUTGOING_ARGS + stack_arg_under_construction = old_stack_arg_under_construction; + highest_outgoing_arg_in_use = initial_highest_arg_in_use; + stack_usage_map = initial_stack_usage_map; +#endif + } +#ifdef ACCUMULATE_OUTGOING_ARGS + else + { +#ifdef REG_PARM_STACK_SPACE + if (save_area) + { + enum machine_mode save_mode = GET_MODE (save_area); + rtx stack_area + = gen_rtx (MEM, save_mode, + memory_address (save_mode, +#ifdef ARGS_GROW_DOWNWARD + plus_constant (argblock, - high_to_save) +#else + plus_constant (argblock, low_to_save) +#endif + )); + + if (save_mode != BLKmode) + emit_move_insn (stack_area, save_area); + else + emit_block_move (stack_area, validize_mem (save_area), + GEN_INT (high_to_save - low_to_save + 1), + PARM_BOUNDARY / BITS_PER_UNIT); + } +#endif + + /* If we saved any argument areas, restore them. */ + for (i = 0; i < num_actuals; i++) + if (args[i].save_area) + { + enum machine_mode save_mode = GET_MODE (args[i].save_area); + rtx stack_area + = gen_rtx (MEM, save_mode, + memory_address (save_mode, + XEXP (args[i].stack_slot, 0))); + + if (save_mode != BLKmode) + emit_move_insn (stack_area, args[i].save_area); + else + emit_block_move (stack_area, validize_mem (args[i].save_area), + GEN_INT (args[i].size.constant), + PARM_BOUNDARY / BITS_PER_UNIT); + } + + highest_outgoing_arg_in_use = initial_highest_arg_in_use; + stack_usage_map = initial_stack_usage_map; + } +#endif + + /* If this was alloca, record the new stack level for nonlocal gotos. + Check for the handler slots since we might not have a save area + for non-local gotos. */ + + if (may_be_alloca && nonlocal_goto_handler_slot != 0) + emit_stack_save (SAVE_NONLOCAL, &nonlocal_goto_stack_level, NULL_RTX); + + pop_temp_slots (); + + return target; +} + +/* Output a library call to function FUN (a SYMBOL_REF rtx) + (emitting the queue unless NO_QUEUE is nonzero), + for a value of mode OUTMODE, + with NARGS different arguments, passed as alternating rtx values + and machine_modes to convert them to. + The rtx values should have been passed through protect_from_queue already. + + NO_QUEUE will be true if and only if the library call is a `const' call + which will be enclosed in REG_LIBCALL/REG_RETVAL notes; it is equivalent + to the variable is_const in expand_call. + + NO_QUEUE must be true for const calls, because if it isn't, then + any pending increment will be emitted between REG_LIBCALL/REG_RETVAL notes, + and will be lost if the libcall sequence is optimized away. + + NO_QUEUE must be false for non-const calls, because if it isn't, the + call insn will have its CONST_CALL_P bit set, and it will be incorrectly + optimized. For instance, the instruction scheduler may incorrectly + move memory references across the non-const call. */ + +void +emit_library_call (va_alist) + va_dcl +{ + va_list p; + /* Total size in bytes of all the stack-parms scanned so far. */ + struct args_size args_size; + /* Size of arguments before any adjustments (such as rounding). */ + struct args_size original_args_size; + register int argnum; + enum machine_mode outmode; + int nargs; + rtx fun; + rtx orgfun; + int inc; + int count; + rtx argblock = 0; + CUMULATIVE_ARGS args_so_far; + struct arg { rtx value; enum machine_mode mode; rtx reg; int partial; + struct args_size offset; struct args_size size; }; + struct arg *argvec; + int old_inhibit_defer_pop = inhibit_defer_pop; + int no_queue = 0; + rtx use_insns; + /* library calls are never indirect calls. */ + int current_call_is_indirect = 0; + + va_start (p); + orgfun = fun = va_arg (p, rtx); + no_queue = va_arg (p, int); + outmode = va_arg (p, enum machine_mode); + nargs = va_arg (p, int); + + /* Copy all the libcall-arguments out of the varargs data + and into a vector ARGVEC. + + Compute how to pass each argument. We only support a very small subset + of the full argument passing conventions to limit complexity here since + library functions shouldn't have many args. */ + + argvec = (struct arg *) alloca (nargs * sizeof (struct arg)); + + INIT_CUMULATIVE_ARGS (args_so_far, NULL_TREE, fun); + + args_size.constant = 0; + args_size.var = 0; + + for (count = 0; count < nargs; count++) + { + rtx val = va_arg (p, rtx); + enum machine_mode mode = va_arg (p, enum machine_mode); + + /* We cannot convert the arg value to the mode the library wants here; + must do it earlier where we know the signedness of the arg. */ + if (mode == BLKmode + || (GET_MODE (val) != mode && GET_MODE (val) != VOIDmode)) + abort (); + + /* On some machines, there's no way to pass a float to a library fcn. + Pass it as a double instead. */ +#ifdef LIBGCC_NEEDS_DOUBLE + if (LIBGCC_NEEDS_DOUBLE && mode == SFmode) + val = convert_to_mode (DFmode, val, 0), mode = DFmode; +#endif + + /* There's no need to call protect_from_queue, because + either emit_move_insn or emit_push_insn will do that. */ + + /* Make sure it is a reasonable operand for a move or push insn. */ + if (GET_CODE (val) != REG && GET_CODE (val) != MEM + && ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val))) + val = force_operand (val, NULL_RTX); + + argvec[count].value = val; + argvec[count].mode = mode; + +#ifdef FUNCTION_ARG_PASS_BY_REFERENCE + if (FUNCTION_ARG_PASS_BY_REFERENCE (args_so_far, mode, NULL_TREE, 1)) + abort (); +#endif + + argvec[count].reg = FUNCTION_ARG (args_so_far, mode, NULL_TREE, 1); + if (argvec[count].reg && GET_CODE (argvec[count].reg) == EXPR_LIST) + abort (); +#ifdef FUNCTION_ARG_PARTIAL_NREGS + argvec[count].partial + = FUNCTION_ARG_PARTIAL_NREGS (args_so_far, mode, NULL_TREE, 1); +#else + argvec[count].partial = 0; +#endif + + locate_and_pad_parm (mode, NULL_TREE, + argvec[count].reg && argvec[count].partial == 0, + NULL_TREE, &args_size, &argvec[count].offset, + &argvec[count].size); + + if (argvec[count].size.var) + abort (); + +#ifndef REG_PARM_STACK_SPACE + if (argvec[count].partial) + argvec[count].size.constant -= argvec[count].partial * UNITS_PER_WORD; +#endif + + if (argvec[count].reg == 0 || argvec[count].partial != 0 +#ifdef REG_PARM_STACK_SPACE + || 1 +#endif + ) + args_size.constant += argvec[count].size.constant; + +#ifdef ACCUMULATE_OUTGOING_ARGS + /* If this arg is actually passed on the stack, it might be + clobbering something we already put there (this library call might + be inside the evaluation of an argument to a function whose call + requires the stack). This will only occur when the library call + has sufficient args to run out of argument registers. Abort in + this case; if this ever occurs, code must be added to save and + restore the arg slot. */ + + if (argvec[count].reg == 0 || argvec[count].partial != 0) + abort (); +#endif + + FUNCTION_ARG_ADVANCE (args_so_far, mode, (tree)0, 1); + } + va_end (p); + + /* If this machine requires an external definition for library + functions, write one out. */ + assemble_external_libcall (fun); + + original_args_size = args_size; +#ifdef STACK_BOUNDARY + args_size.constant = (((args_size.constant + (STACK_BYTES - 1)) + / STACK_BYTES) * STACK_BYTES); +#endif + +#ifdef REG_PARM_STACK_SPACE + args_size.constant = MAX (args_size.constant, + REG_PARM_STACK_SPACE (NULL_TREE)); +#ifndef OUTGOING_REG_PARM_STACK_SPACE + args_size.constant -= REG_PARM_STACK_SPACE (NULL_TREE); +#endif +#endif + +#ifdef ACCUMULATE_OUTGOING_ARGS + if (args_size.constant > current_function_outgoing_args_size) + current_function_outgoing_args_size = args_size.constant; + args_size.constant = 0; +#endif + +#ifndef PUSH_ROUNDING + argblock = push_block (GEN_INT (args_size.constant), 0, 0); +#endif + +#ifdef PUSH_ARGS_REVERSED +#ifdef STACK_BOUNDARY + /* If we push args individually in reverse order, perform stack alignment + before the first push (the last arg). */ + if (argblock == 0) + anti_adjust_stack (GEN_INT (args_size.constant + - original_args_size.constant)); +#endif +#endif + +#ifdef PUSH_ARGS_REVERSED + inc = -1; + argnum = nargs - 1; +#else + inc = 1; + argnum = 0; +#endif + + /* Push the args that need to be pushed. */ + + for (count = 0; count < nargs; count++, argnum += inc) + { + register enum machine_mode mode = argvec[argnum].mode; + register rtx val = argvec[argnum].value; + rtx reg = argvec[argnum].reg; + int partial = argvec[argnum].partial; + + if (! (reg != 0 && partial == 0)) + emit_push_insn (val, mode, NULL_TREE, NULL_RTX, 0, partial, reg, 0, + argblock, GEN_INT (argvec[count].offset.constant)); + NO_DEFER_POP; + } + +#ifndef PUSH_ARGS_REVERSED +#ifdef STACK_BOUNDARY + /* If we pushed args in forward order, perform stack alignment + after pushing the last arg. */ + if (argblock == 0) + anti_adjust_stack (GEN_INT (args_size.constant + - original_args_size.constant)); +#endif +#endif + +#ifdef PUSH_ARGS_REVERSED + argnum = nargs - 1; +#else + argnum = 0; +#endif + + /* Now load any reg parms into their regs. */ + + for (count = 0; count < nargs; count++, argnum += inc) + { + register enum machine_mode mode = argvec[argnum].mode; + register rtx val = argvec[argnum].value; + rtx reg = argvec[argnum].reg; + int partial = argvec[argnum].partial; + + if (reg != 0 && partial == 0) + emit_move_insn (reg, val); + NO_DEFER_POP; + } + + /* For version 1.37, try deleting this entirely. */ + if (! no_queue) + emit_queue (); + + /* Any regs containing parms remain in use through the call. */ + start_sequence (); + for (count = 0; count < nargs; count++) + if (argvec[count].reg != 0) + emit_insn (gen_rtx (USE, VOIDmode, argvec[count].reg)); + + use_insns = get_insns (); + end_sequence (); + + fun = prepare_call_address (fun, NULL_TREE, &use_insns); + + /* Don't allow popping to be deferred, since then + cse'ing of library calls could delete a call and leave the pop. */ + NO_DEFER_POP; + + /* We pass the old value of inhibit_defer_pop + 1 to emit_call_1, which + will set inhibit_defer_pop to that value. */ + + emit_call_1 (fun, get_identifier (XSTR (orgfun, 0)), args_size.constant, 0, + FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1), + outmode != VOIDmode ? hard_libcall_value (outmode) : NULL_RTX, + old_inhibit_defer_pop + 1, use_insns, no_queue); + + /* Now restore inhibit_defer_pop to its actual original value. */ + OK_DEFER_POP; +} + +/* Like emit_library_call except that an extra argument, VALUE, + comes second and says where to store the result. + (If VALUE is zero, the result comes in the function value register.) */ + +void +emit_library_call_value (va_alist) + va_dcl +{ + va_list p; + /* Total size in bytes of all the stack-parms scanned so far. */ + struct args_size args_size; + /* Size of arguments before any adjustments (such as rounding). */ + struct args_size original_args_size; + register int argnum; + enum machine_mode outmode; + int nargs; + rtx fun; + rtx orgfun; + int inc; + int count; + rtx argblock = 0; + CUMULATIVE_ARGS args_so_far; + struct arg { rtx value; enum machine_mode mode; rtx reg; int partial; + struct args_size offset; struct args_size size; }; + struct arg *argvec; + int old_inhibit_defer_pop = inhibit_defer_pop; + int no_queue = 0; + rtx use_insns; + rtx value; + rtx mem_value = 0; + /* library calls are never indirect calls. */ + int current_call_is_indirect = 0; + + va_start (p); + orgfun = fun = va_arg (p, rtx); + value = va_arg (p, rtx); + no_queue = va_arg (p, int); + outmode = va_arg (p, enum machine_mode); + nargs = va_arg (p, int); + + /* If this kind of value comes back in memory, + decide where in memory it should come back. */ + if (RETURN_IN_MEMORY (type_for_mode (outmode, 0))) + { + if (GET_CODE (value) == MEM) + mem_value = value; + else + mem_value = assign_stack_temp (outmode, GET_MODE_SIZE (outmode), 0); + } + + /* ??? Unfinished: must pass the memory address as an argument. */ + + /* Copy all the libcall-arguments out of the varargs data + and into a vector ARGVEC. + + Compute how to pass each argument. We only support a very small subset + of the full argument passing conventions to limit complexity here since + library functions shouldn't have many args. */ + + argvec = (struct arg *) alloca ((nargs + 1) * sizeof (struct arg)); + + INIT_CUMULATIVE_ARGS (args_so_far, NULL_TREE, fun); + + args_size.constant = 0; + args_size.var = 0; + + count = 0; + + /* If there's a structure value address to be passed, + either pass it in the special place, or pass it as an extra argument. */ + if (mem_value) + { + rtx addr = XEXP (mem_value, 0); + + if (! struct_value_rtx) + { + nargs++; + + /* Make sure it is a reasonable operand for a move or push insn. */ + if (GET_CODE (addr) != REG && GET_CODE (addr) != MEM + && ! (CONSTANT_P (addr) && LEGITIMATE_CONSTANT_P (addr))) + addr = force_operand (addr, NULL_RTX); + + argvec[count].value = addr; + argvec[count].mode = outmode; + argvec[count].partial = 0; + + argvec[count].reg = FUNCTION_ARG (args_so_far, outmode, NULL_TREE, 1); +#ifdef FUNCTION_ARG_PARTIAL_NREGS + if (FUNCTION_ARG_PARTIAL_NREGS (args_so_far, outmode, NULL_TREE, 1)) + abort (); +#endif + + locate_and_pad_parm (outmode, NULL_TREE, + argvec[count].reg && argvec[count].partial == 0, + NULL_TREE, &args_size, &argvec[count].offset, + &argvec[count].size); + + + if (argvec[count].reg == 0 || argvec[count].partial != 0 +#ifdef REG_PARM_STACK_SPACE + || 1 +#endif + ) + args_size.constant += argvec[count].size.constant; + + FUNCTION_ARG_ADVANCE (args_so_far, outmode, (tree)0, 1); + } + } + + for (; count < nargs; count++) + { + rtx val = va_arg (p, rtx); + enum machine_mode mode = va_arg (p, enum machine_mode); + + /* We cannot convert the arg value to the mode the library wants here; + must do it earlier where we know the signedness of the arg. */ + if (mode == BLKmode + || (GET_MODE (val) != mode && GET_MODE (val) != VOIDmode)) + abort (); + + /* On some machines, there's no way to pass a float to a library fcn. + Pass it as a double instead. */ +#ifdef LIBGCC_NEEDS_DOUBLE + if (LIBGCC_NEEDS_DOUBLE && mode == SFmode) + val = convert_to_mode (DFmode, val, 0), mode = DFmode; +#endif + + /* There's no need to call protect_from_queue, because + either emit_move_insn or emit_push_insn will do that. */ + + /* Make sure it is a reasonable operand for a move or push insn. */ + if (GET_CODE (val) != REG && GET_CODE (val) != MEM + && ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val))) + val = force_operand (val, NULL_RTX); + + argvec[count].value = val; + argvec[count].mode = mode; + +#ifdef FUNCTION_ARG_PASS_BY_REFERENCE + if (FUNCTION_ARG_PASS_BY_REFERENCE (args_so_far, mode, NULL_TREE, 1)) + abort (); +#endif + + argvec[count].reg = FUNCTION_ARG (args_so_far, mode, NULL_TREE, 1); + if (argvec[count].reg && GET_CODE (argvec[count].reg) == EXPR_LIST) + abort (); +#ifdef FUNCTION_ARG_PARTIAL_NREGS + argvec[count].partial + = FUNCTION_ARG_PARTIAL_NREGS (args_so_far, mode, NULL_TREE, 1); +#else + argvec[count].partial = 0; +#endif + + locate_and_pad_parm (mode, NULL_TREE, + argvec[count].reg && argvec[count].partial == 0, + NULL_TREE, &args_size, &argvec[count].offset, + &argvec[count].size); + + if (argvec[count].size.var) + abort (); + +#ifndef REG_PARM_STACK_SPACE + if (argvec[count].partial) + argvec[count].size.constant -= argvec[count].partial * UNITS_PER_WORD; +#endif + + if (argvec[count].reg == 0 || argvec[count].partial != 0 +#ifdef REG_PARM_STACK_SPACE + || 1 +#endif + ) + args_size.constant += argvec[count].size.constant; + +#ifdef ACCUMULATE_OUTGOING_ARGS + /* If this arg is actually passed on the stack, it might be + clobbering something we already put there (this library call might + be inside the evaluation of an argument to a function whose call + requires the stack). This will only occur when the library call + has sufficient args to run out of argument registers. Abort in + this case; if this ever occurs, code must be added to save and + restore the arg slot. */ + + if (argvec[count].reg == 0 || argvec[count].partial != 0) + abort (); +#endif + + FUNCTION_ARG_ADVANCE (args_so_far, mode, (tree)0, 1); + } + va_end (p); + + /* If this machine requires an external definition for library + functions, write one out. */ + assemble_external_libcall (fun); + + original_args_size = args_size; +#ifdef STACK_BOUNDARY + args_size.constant = (((args_size.constant + (STACK_BYTES - 1)) + / STACK_BYTES) * STACK_BYTES); +#endif + +#ifdef REG_PARM_STACK_SPACE + args_size.constant = MAX (args_size.constant, + REG_PARM_STACK_SPACE (NULL_TREE)); +#ifndef OUTGOING_REG_PARM_STACK_SPACE + args_size.constant -= REG_PARM_STACK_SPACE (NULL_TREE); +#endif +#endif + +#ifdef ACCUMULATE_OUTGOING_ARGS + if (args_size.constant > current_function_outgoing_args_size) + current_function_outgoing_args_size = args_size.constant; + args_size.constant = 0; +#endif + +#ifndef PUSH_ROUNDING + argblock = push_block (GEN_INT (args_size.constant), 0, 0); +#endif + +#ifdef PUSH_ARGS_REVERSED +#ifdef STACK_BOUNDARY + /* If we push args individually in reverse order, perform stack alignment + before the first push (the last arg). */ + if (argblock == 0) + anti_adjust_stack (GEN_INT (args_size.constant + - original_args_size.constant)); +#endif +#endif + +#ifdef PUSH_ARGS_REVERSED + inc = -1; + argnum = nargs - 1; +#else + inc = 1; + argnum = 0; +#endif + + /* Push the args that need to be pushed. */ + + for (count = 0; count < nargs; count++, argnum += inc) + { + register enum machine_mode mode = argvec[argnum].mode; + register rtx val = argvec[argnum].value; + rtx reg = argvec[argnum].reg; + int partial = argvec[argnum].partial; + + if (! (reg != 0 && partial == 0)) + emit_push_insn (val, mode, NULL_TREE, NULL_RTX, 0, partial, reg, 0, + argblock, GEN_INT (argvec[count].offset.constant)); + NO_DEFER_POP; + } + +#ifndef PUSH_ARGS_REVERSED +#ifdef STACK_BOUNDARY + /* If we pushed args in forward order, perform stack alignment + after pushing the last arg. */ + if (argblock == 0) + anti_adjust_stack (GEN_INT (args_size.constant + - original_args_size.constant)); +#endif +#endif + +#ifdef PUSH_ARGS_REVERSED + argnum = nargs - 1; +#else + argnum = 0; +#endif + + /* Now load any reg parms into their regs. */ + + if (mem_value != 0 && struct_value_rtx != 0) + emit_move_insn (struct_value_rtx, XEXP (mem_value, 0)); + + for (count = 0; count < nargs; count++, argnum += inc) + { + register enum machine_mode mode = argvec[argnum].mode; + register rtx val = argvec[argnum].value; + rtx reg = argvec[argnum].reg; + int partial = argvec[argnum].partial; + + if (reg != 0 && partial == 0) + emit_move_insn (reg, val); + NO_DEFER_POP; + } + +#if 0 + /* For version 1.37, try deleting this entirely. */ + if (! no_queue) + emit_queue (); +#endif + + /* Any regs containing parms remain in use through the call. */ + start_sequence (); + for (count = 0; count < nargs; count++) + if (argvec[count].reg != 0) + emit_insn (gen_rtx (USE, VOIDmode, argvec[count].reg)); + + use_insns = get_insns (); + end_sequence (); + + fun = prepare_call_address (fun, NULL_TREE, &use_insns); + + /* Don't allow popping to be deferred, since then + cse'ing of library calls could delete a call and leave the pop. */ + NO_DEFER_POP; + + /* We pass the old value of inhibit_defer_pop + 1 to emit_call_1, which + will set inhibit_defer_pop to that value. */ + + emit_call_1 (fun, get_identifier (XSTR (orgfun, 0)), args_size.constant, 0, + FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1), + outmode != VOIDmode ? hard_libcall_value (outmode) : NULL_RTX, + old_inhibit_defer_pop + 1, use_insns, no_queue); + + /* Now restore inhibit_defer_pop to its actual original value. */ + OK_DEFER_POP; + + /* Copy the value to the right place. */ + if (outmode != VOIDmode) + { + if (mem_value) + { + if (value == 0) + value = hard_libcall_value (outmode); + if (value != mem_value) + emit_move_insn (value, mem_value); + } + else if (value != 0) + emit_move_insn (value, hard_libcall_value (outmode)); + } +} + +#if 0 +/* Return an rtx which represents a suitable home on the stack + given TYPE, the type of the argument looking for a home. + This is called only for BLKmode arguments. + + SIZE is the size needed for this target. + ARGS_ADDR is the address of the bottom of the argument block for this call. + OFFSET describes this parameter's offset into ARGS_ADDR. It is meaningless + if this machine uses push insns. */ + +static rtx +target_for_arg (type, size, args_addr, offset) + tree type; + rtx size; + rtx args_addr; + struct args_size offset; +{ + rtx target; + rtx offset_rtx = ARGS_SIZE_RTX (offset); + + /* We do not call memory_address if possible, + because we want to address as close to the stack + as possible. For non-variable sized arguments, + this will be stack-pointer relative addressing. */ + if (GET_CODE (offset_rtx) == CONST_INT) + target = plus_constant (args_addr, INTVAL (offset_rtx)); + else + { + /* I have no idea how to guarantee that this + will work in the presence of register parameters. */ + target = gen_rtx (PLUS, Pmode, args_addr, offset_rtx); + target = memory_address (QImode, target); + } + + return gen_rtx (MEM, BLKmode, target); +} +#endif + +/* Store a single argument for a function call + into the register or memory area where it must be passed. + *ARG describes the argument value and where to pass it. + + ARGBLOCK is the address of the stack-block for all the arguments, + or 0 on a machine where arguments are pushed individually. + + MAY_BE_ALLOCA nonzero says this could be a call to `alloca' + so must be careful about how the stack is used. + + VARIABLE_SIZE nonzero says that this was a variable-sized outgoing + argument stack. This is used if ACCUMULATE_OUTGOING_ARGS to indicate + that we need not worry about saving and restoring the stack. + + FNDECL is the declaration of the function we are calling. */ + +static void +store_one_arg (arg, argblock, may_be_alloca, variable_size, fndecl, + reg_parm_stack_space) + struct arg_data *arg; + rtx argblock; + int may_be_alloca; + int variable_size; + tree fndecl; + int reg_parm_stack_space; +{ + register tree pval = arg->tree_value; + rtx reg = 0; + int partial = 0; + int used = 0; + int i, lower_bound, upper_bound; + + if (TREE_CODE (pval) == ERROR_MARK) + return; + +#ifdef ACCUMULATE_OUTGOING_ARGS + /* If this is being stored into a pre-allocated, fixed-size, stack area, + save any previous data at that location. */ + if (argblock && ! variable_size && arg->stack) + { +#ifdef ARGS_GROW_DOWNWARD + /* stack_slot is negative, but we want to index stack_usage_map */ + /* with positive values. */ + if (GET_CODE (XEXP (arg->stack_slot, 0)) == PLUS) + upper_bound = -INTVAL (XEXP (XEXP (arg->stack_slot, 0), 1)) + 1; + else + abort (); + + lower_bound = upper_bound - arg->size.constant; +#else + if (GET_CODE (XEXP (arg->stack_slot, 0)) == PLUS) + lower_bound = INTVAL (XEXP (XEXP (arg->stack_slot, 0), 1)); + else + lower_bound = 0; + + upper_bound = lower_bound + arg->size.constant; +#endif + + for (i = lower_bound; i < upper_bound; i++) + if (stack_usage_map[i] +#ifdef REG_PARM_STACK_SPACE + /* Don't store things in the fixed argument area at this point; + it has already been saved. */ + && i > reg_parm_stack_space +#endif + ) + break; + + if (i != upper_bound) + { + /* We need to make a save area. See what mode we can make it. */ + enum machine_mode save_mode + = mode_for_size (arg->size.constant * BITS_PER_UNIT, MODE_INT, 1); + rtx stack_area + = gen_rtx (MEM, save_mode, + memory_address (save_mode, XEXP (arg->stack_slot, 0))); + + if (save_mode == BLKmode) + { + arg->save_area = assign_stack_temp (BLKmode, + arg->size.constant, 1); + emit_block_move (validize_mem (arg->save_area), stack_area, + GEN_INT (arg->size.constant), + PARM_BOUNDARY / BITS_PER_UNIT); + } + else + { + arg->save_area = gen_reg_rtx (save_mode); + emit_move_insn (arg->save_area, stack_area); + } + } + } +#endif + + /* If this isn't going to be placed on both the stack and in registers, + set up the register and number of words. */ + if (! arg->pass_on_stack) + reg = arg->reg, partial = arg->partial; + + if (reg != 0 && partial == 0) + /* Being passed entirely in a register. We shouldn't be called in + this case. */ + abort (); + +#ifdef STRICT_ALIGNMENT + /* If this arg needs special alignment, don't load the registers + here. */ + if (arg->n_aligned_regs != 0) + reg = 0; +#endif + + /* If this is being partially passed in a register, but multiple locations + are specified, we assume that the one partially used is the one that is + listed first. */ + if (reg && GET_CODE (reg) == EXPR_LIST) + reg = XEXP (reg, 0); + + /* If this is being passed partially in a register, we can't evaluate + it directly into its stack slot. Otherwise, we can. */ + if (arg->value == 0) + { +#ifdef ACCUMULATE_OUTGOING_ARGS + /* stack_arg_under_construction is nonzero if a function argument is + being evaluated directly into the outgoing argument list and + expand_call must take special action to preserve the argument list + if it is called recursively. + + For scalar function arguments stack_usage_map is sufficient to + determine which stack slots must be saved and restored. Scalar + arguments in general have pass_on_stack == 0. + + If this argument is initialized by a function which takes the + address of the argument (a C++ constructor or a C function + returning a BLKmode structure), then stack_usage_map is + insufficient and expand_call must push the stack around the + function call. Such arguments have pass_on_stack == 1. + + Note that it is always safe to set stack_arg_under_construction, + but this generates suboptimal code if set when not needed. */ + + if (arg->pass_on_stack) + stack_arg_under_construction++; +#endif + arg->value = expand_expr (pval, partial ? NULL_RTX : arg->stack, + VOIDmode, 0); + + /* If we are promoting object (or for any other reason) the mode + doesn't agree, convert the mode. */ + + if (GET_MODE (arg->value) != VOIDmode + && GET_MODE (arg->value) != arg->mode) + arg->value = convert_to_mode (arg->mode, arg->value, arg->unsignedp); + +#ifdef ACCUMULATE_OUTGOING_ARGS + if (arg->pass_on_stack) + stack_arg_under_construction--; +#endif + } + + /* Don't allow anything left on stack from computation + of argument to alloca. */ + if (may_be_alloca) + do_pending_stack_adjust (); + + if (arg->value == arg->stack) + /* If the value is already in the stack slot, we are done. */ + ; + else if (arg->mode != BLKmode) + { + register int size; + + /* Argument is a scalar, not entirely passed in registers. + (If part is passed in registers, arg->partial says how much + and emit_push_insn will take care of putting it there.) + + Push it, and if its size is less than the + amount of space allocated to it, + also bump stack pointer by the additional space. + Note that in C the default argument promotions + will prevent such mismatches. */ + + size = GET_MODE_SIZE (arg->mode); + /* Compute how much space the push instruction will push. + On many machines, pushing a byte will advance the stack + pointer by a halfword. */ +#ifdef PUSH_ROUNDING + size = PUSH_ROUNDING (size); +#endif + used = size; + + /* Compute how much space the argument should get: + round up to a multiple of the alignment for arguments. */ + if (none != FUNCTION_ARG_PADDING (arg->mode, TREE_TYPE (pval))) + used = (((size + PARM_BOUNDARY / BITS_PER_UNIT - 1) + / (PARM_BOUNDARY / BITS_PER_UNIT)) + * (PARM_BOUNDARY / BITS_PER_UNIT)); + + /* This isn't already where we want it on the stack, so put it there. + This can either be done with push or copy insns. */ + emit_push_insn (arg->value, arg->mode, TREE_TYPE (pval), NULL_RTX, + 0, partial, reg, used - size, + argblock, ARGS_SIZE_RTX (arg->offset)); + } + else + { + /* BLKmode, at least partly to be pushed. */ + + register int excess; + rtx size_rtx; + + /* Pushing a nonscalar. + If part is passed in registers, PARTIAL says how much + and emit_push_insn will take care of putting it there. */ + + /* Round its size up to a multiple + of the allocation unit for arguments. */ + + if (arg->size.var != 0) + { + excess = 0; + size_rtx = ARGS_SIZE_RTX (arg->size); + } + else + { + /* PUSH_ROUNDING has no effect on us, because + emit_push_insn for BLKmode is careful to avoid it. */ + excess = (arg->size.constant - int_size_in_bytes (TREE_TYPE (pval)) + + partial * UNITS_PER_WORD); + size_rtx = expr_size (pval); + } + + emit_push_insn (arg->value, arg->mode, TREE_TYPE (pval), size_rtx, + TYPE_ALIGN (TREE_TYPE (pval)) / BITS_PER_UNIT, partial, + reg, excess, argblock, ARGS_SIZE_RTX (arg->offset)); + } + + + /* Unless this is a partially-in-register argument, the argument is now + in the stack. + + ??? Note that this can change arg->value from arg->stack to + arg->stack_slot and it matters when they are not the same. + It isn't totally clear that this is correct in all cases. */ + if (partial == 0) + arg->value = arg->stack_slot; + + /* Once we have pushed something, pops can't safely + be deferred during the rest of the arguments. */ + NO_DEFER_POP; + + /* ANSI doesn't require a sequence point here, + but PCC has one, so this will avoid some problems. */ + emit_queue (); + + /* Free any temporary slots made in processing this argument. */ + free_temp_slots (); + +#ifdef ACCUMULATE_OUTGOING_ARGS + /* Now mark the segment we just used. */ + if (argblock && ! variable_size && arg->stack) + for (i = lower_bound; i < upper_bound; i++) + stack_usage_map[i] = 1; +#endif +} diff --git a/gnu/usr.bin/cc/lib/combine.c b/gnu/usr.bin/cc/lib/combine.c new file mode 100644 index 000000000000..7aa534879f5b --- /dev/null +++ b/gnu/usr.bin/cc/lib/combine.c @@ -0,0 +1,10025 @@ +/* Optimize by combining instructions for GNU compiler. + Copyright (C) 1987, 1988, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This module is essentially the "combiner" phase of the U. of Arizona + Portable Optimizer, but redone to work on our list-structured + representation for RTL instead of their string representation. + + The LOG_LINKS of each insn identify the most recent assignment + to each REG used in the insn. It is a list of previous insns, + each of which contains a SET for a REG that is used in this insn + and not used or set in between. LOG_LINKs never cross basic blocks. + They were set up by the preceding pass (lifetime analysis). + + We try to combine each pair of insns joined by a logical link. + We also try to combine triples of insns A, B and C when + C has a link back to B and B has a link back to A. + + LOG_LINKS does not have links for use of the CC0. They don't + need to, because the insn that sets the CC0 is always immediately + before the insn that tests it. So we always regard a branch + insn as having a logical link to the preceding insn. The same is true + for an insn explicitly using CC0. + + We check (with use_crosses_set_p) to avoid combining in such a way + as to move a computation to a place where its value would be different. + + Combination is done by mathematically substituting the previous + insn(s) values for the regs they set into the expressions in + the later insns that refer to these regs. If the result is a valid insn + for our target machine, according to the machine description, + we install it, delete the earlier insns, and update the data flow + information (LOG_LINKS and REG_NOTES) for what we did. + + There are a few exceptions where the dataflow information created by + flow.c aren't completely updated: + + - reg_live_length is not updated + - reg_n_refs is not adjusted in the rare case when a register is + no longer required in a computation + - there are extremely rare cases (see distribute_regnotes) when a + REG_DEAD note is lost + - a LOG_LINKS entry that refers to an insn with multiple SETs may be + removed because there is no way to know which register it was + linking + + To simplify substitution, we combine only when the earlier insn(s) + consist of only a single assignment. To simplify updating afterward, + we never combine when a subroutine call appears in the middle. + + Since we do not represent assignments to CC0 explicitly except when that + is all an insn does, there is no LOG_LINKS entry in an insn that uses + the condition code for the insn that set the condition code. + Fortunately, these two insns must be consecutive. + Therefore, every JUMP_INSN is taken to have an implicit logical link + to the preceding insn. This is not quite right, since non-jumps can + also use the condition code; but in practice such insns would not + combine anyway. */ + +#include "config.h" +#include "gvarargs.h" +#include "rtl.h" +#include "flags.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "expr.h" +#include "basic-block.h" +#include "insn-config.h" +#include "insn-flags.h" +#include "insn-codes.h" +#include "insn-attr.h" +#include "recog.h" +#include "real.h" +#include + +/* It is not safe to use ordinary gen_lowpart in combine. + Use gen_lowpart_for_combine instead. See comments there. */ +#define gen_lowpart dont_use_gen_lowpart_you_dummy + +/* If byte loads either zero- or sign- extend, define BYTE_LOADS_EXTEND + for cases when we don't care which is true. Define LOAD_EXTEND to + be ZERO_EXTEND or SIGN_EXTEND, depending on which was defined. */ + +#ifdef BYTE_LOADS_ZERO_EXTEND +#define BYTE_LOADS_EXTEND +#define LOAD_EXTEND ZERO_EXTEND +#endif + +#ifdef BYTE_LOADS_SIGN_EXTEND +#define BYTE_LOADS_EXTEND +#define LOAD_EXTEND SIGN_EXTEND +#endif + +/* Number of attempts to combine instructions in this function. */ + +static int combine_attempts; + +/* Number of attempts that got as far as substitution in this function. */ + +static int combine_merges; + +/* Number of instructions combined with added SETs in this function. */ + +static int combine_extras; + +/* Number of instructions combined in this function. */ + +static int combine_successes; + +/* Totals over entire compilation. */ + +static int total_attempts, total_merges, total_extras, total_successes; + +/* Vector mapping INSN_UIDs to cuids. + The cuids are like uids but increase monotonically always. + Combine always uses cuids so that it can compare them. + But actually renumbering the uids, which we used to do, + proves to be a bad idea because it makes it hard to compare + the dumps produced by earlier passes with those from later passes. */ + +static int *uid_cuid; + +/* Get the cuid of an insn. */ + +#define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)]) + +/* Maximum register number, which is the size of the tables below. */ + +static int combine_max_regno; + +/* Record last point of death of (hard or pseudo) register n. */ + +static rtx *reg_last_death; + +/* Record last point of modification of (hard or pseudo) register n. */ + +static rtx *reg_last_set; + +/* Record the cuid of the last insn that invalidated memory + (anything that writes memory, and subroutine calls, but not pushes). */ + +static int mem_last_set; + +/* Record the cuid of the last CALL_INSN + so we can tell whether a potential combination crosses any calls. */ + +static int last_call_cuid; + +/* When `subst' is called, this is the insn that is being modified + (by combining in a previous insn). The PATTERN of this insn + is still the old pattern partially modified and it should not be + looked at, but this may be used to examine the successors of the insn + to judge whether a simplification is valid. */ + +static rtx subst_insn; + +/* This is the lowest CUID that `subst' is currently dealing with. + get_last_value will not return a value if the register was set at or + after this CUID. If not for this mechanism, we could get confused if + I2 or I1 in try_combine were an insn that used the old value of a register + to obtain a new value. In that case, we might erroneously get the + new value of the register when we wanted the old one. */ + +static int subst_low_cuid; + +/* This is the value of undobuf.num_undo when we started processing this + substitution. This will prevent gen_rtx_combine from re-used a piece + from the previous expression. Doing so can produce circular rtl + structures. */ + +static int previous_num_undos; + +/* The next group of arrays allows the recording of the last value assigned + to (hard or pseudo) register n. We use this information to see if a + operation being processed is redundant given a prior operation performed + on the register. For example, an `and' with a constant is redundant if + all the zero bits are already known to be turned off. + + We use an approach similar to that used by cse, but change it in the + following ways: + + (1) We do not want to reinitialize at each label. + (2) It is useful, but not critical, to know the actual value assigned + to a register. Often just its form is helpful. + + Therefore, we maintain the following arrays: + + reg_last_set_value the last value assigned + reg_last_set_label records the value of label_tick when the + register was assigned + reg_last_set_table_tick records the value of label_tick when a + value using the register is assigned + reg_last_set_invalid set to non-zero when it is not valid + to use the value of this register in some + register's value + + To understand the usage of these tables, it is important to understand + the distinction between the value in reg_last_set_value being valid + and the register being validly contained in some other expression in the + table. + + Entry I in reg_last_set_value is valid if it is non-zero, and either + reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick. + + Register I may validly appear in any expression returned for the value + of another register if reg_n_sets[i] is 1. It may also appear in the + value for register J if reg_last_set_label[i] < reg_last_set_label[j] or + reg_last_set_invalid[j] is zero. + + If an expression is found in the table containing a register which may + not validly appear in an expression, the register is replaced by + something that won't match, (clobber (const_int 0)). + + reg_last_set_invalid[i] is set non-zero when register I is being assigned + to and reg_last_set_table_tick[i] == label_tick. */ + +/* Record last value assigned to (hard or pseudo) register n. */ + +static rtx *reg_last_set_value; + +/* Record the value of label_tick when the value for register n is placed in + reg_last_set_value[n]. */ + +static int *reg_last_set_label; + +/* Record the value of label_tick when an expression involving register n + is placed in reg_last_set_value. */ + +static int *reg_last_set_table_tick; + +/* Set non-zero if references to register n in expressions should not be + used. */ + +static char *reg_last_set_invalid; + +/* Incremented for each label. */ + +static int label_tick; + +/* Some registers that are set more than once and used in more than one + basic block are nevertheless always set in similar ways. For example, + a QImode register may be loaded from memory in two places on a machine + where byte loads zero extend. + + We record in the following array what we know about the nonzero + bits of a register, specifically which bits are known to be zero. + + If an entry is zero, it means that we don't know anything special. */ + +static unsigned HOST_WIDE_INT *reg_nonzero_bits; + +/* Mode used to compute significance in reg_nonzero_bits. It is the largest + integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ + +static enum machine_mode nonzero_bits_mode; + +/* Nonzero if we know that a register has some leading bits that are always + equal to the sign bit. */ + +static char *reg_sign_bit_copies; + +/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used. + It is zero while computing them and after combine has completed. This + former test prevents propagating values based on previously set values, + which can be incorrect if a variable is modified in a loop. */ + +static int nonzero_sign_valid; + +/* These arrays are maintained in parallel with reg_last_set_value + and are used to store the mode in which the register was last set, + the bits that were known to be zero when it was last set, and the + number of sign bits copies it was known to have when it was last set. */ + +static enum machine_mode *reg_last_set_mode; +static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits; +static char *reg_last_set_sign_bit_copies; + +/* Record one modification to rtl structure + to be undone by storing old_contents into *where. + is_int is 1 if the contents are an int. */ + +struct undo +{ + int is_int; + union {rtx rtx; int i;} old_contents; + union {rtx *rtx; int *i;} where; +}; + +/* Record a bunch of changes to be undone, up to MAX_UNDO of them. + num_undo says how many are currently recorded. + + storage is nonzero if we must undo the allocation of new storage. + The value of storage is what to pass to obfree. + + other_insn is nonzero if we have modified some other insn in the process + of working on subst_insn. It must be verified too. */ + +#define MAX_UNDO 50 + +struct undobuf +{ + int num_undo; + char *storage; + struct undo undo[MAX_UNDO]; + rtx other_insn; +}; + +static struct undobuf undobuf; + +/* Substitute NEWVAL, an rtx expression, into INTO, a place in some + insn. The substitution can be undone by undo_all. If INTO is already + set to NEWVAL, do not record this change. Because computing NEWVAL might + also call SUBST, we have to compute it before we put anything into + the undo table. */ + +#define SUBST(INTO, NEWVAL) \ + do { rtx _new = (NEWVAL); \ + if (undobuf.num_undo < MAX_UNDO) \ + { \ + undobuf.undo[undobuf.num_undo].is_int = 0; \ + undobuf.undo[undobuf.num_undo].where.rtx = &INTO; \ + undobuf.undo[undobuf.num_undo].old_contents.rtx = INTO; \ + INTO = _new; \ + if (undobuf.undo[undobuf.num_undo].old_contents.rtx != INTO) \ + undobuf.num_undo++; \ + } \ + } while (0) + +/* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT + expression. + Note that substitution for the value of a CONST_INT is not safe. */ + +#define SUBST_INT(INTO, NEWVAL) \ + do { if (undobuf.num_undo < MAX_UNDO) \ +{ \ + undobuf.undo[undobuf.num_undo].is_int = 1; \ + undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \ + undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \ + INTO = NEWVAL; \ + if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \ + undobuf.num_undo++; \ + } \ + } while (0) + +/* Number of times the pseudo being substituted for + was found and replaced. */ + +static int n_occurrences; + +static void set_nonzero_bits_and_sign_copies (); +static void setup_incoming_promotions (); +static void move_deaths (); +rtx remove_death (); +static void record_value_for_reg (); +static void record_dead_and_set_regs (); +static int use_crosses_set_p (); +static rtx try_combine (); +static rtx *find_split_point (); +static rtx subst (); +static void undo_all (); +static int reg_dead_at_p (); +static rtx expand_compound_operation (); +static rtx expand_field_assignment (); +static rtx make_extraction (); +static int get_pos_from_mask (); +static rtx force_to_mode (); +static rtx known_cond (); +static rtx make_field_assignment (); +static rtx make_compound_operation (); +static rtx apply_distributive_law (); +static rtx simplify_and_const_int (); +static unsigned HOST_WIDE_INT nonzero_bits (); +static int num_sign_bit_copies (); +static int merge_outer_ops (); +static rtx simplify_shift_const (); +static int recog_for_combine (); +static rtx gen_lowpart_for_combine (); +static rtx gen_rtx_combine (); +static rtx gen_binary (); +static rtx gen_unary (); +static enum rtx_code simplify_comparison (); +static int reversible_comparison_p (); +static int get_last_value_validate (); +static rtx get_last_value (); +static void distribute_notes (); +static void distribute_links (); + +/* Main entry point for combiner. F is the first insn of the function. + NREGS is the first unused pseudo-reg number. */ + +void +combine_instructions (f, nregs) + rtx f; + int nregs; +{ + register rtx insn, next, prev; + register int i; + register rtx links, nextlinks; + + combine_attempts = 0; + combine_merges = 0; + combine_extras = 0; + combine_successes = 0; + undobuf.num_undo = previous_num_undos = 0; + + combine_max_regno = nregs; + + reg_last_death = (rtx *) alloca (nregs * sizeof (rtx)); + reg_last_set = (rtx *) alloca (nregs * sizeof (rtx)); + reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx)); + reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int)); + reg_last_set_label = (int *) alloca (nregs * sizeof (int)); + reg_last_set_invalid = (char *) alloca (nregs * sizeof (char)); + reg_last_set_mode + = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode)); + reg_last_set_nonzero_bits + = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT)); + reg_last_set_sign_bit_copies + = (char *) alloca (nregs * sizeof (char)); + + reg_nonzero_bits + = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT)); + reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char)); + + bzero (reg_last_death, nregs * sizeof (rtx)); + bzero (reg_last_set, nregs * sizeof (rtx)); + bzero (reg_last_set_value, nregs * sizeof (rtx)); + bzero (reg_last_set_table_tick, nregs * sizeof (int)); + bzero (reg_last_set_label, nregs * sizeof (int)); + bzero (reg_last_set_invalid, nregs * sizeof (char)); + bzero (reg_last_set_mode, nregs * sizeof (enum machine_mode)); + bzero (reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT)); + bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char)); + bzero (reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT)); + bzero (reg_sign_bit_copies, nregs * sizeof (char)); + + init_recog_no_volatile (); + + /* Compute maximum uid value so uid_cuid can be allocated. */ + + for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) + if (INSN_UID (insn) > i) + i = INSN_UID (insn); + + uid_cuid = (int *) alloca ((i + 1) * sizeof (int)); + + nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); + + /* Don't use reg_nonzero_bits when computing it. This can cause problems + when, for example, we have j <<= 1 in a loop. */ + + nonzero_sign_valid = 0; + + /* Compute the mapping from uids to cuids. + Cuids are numbers assigned to insns, like uids, + except that cuids increase monotonically through the code. + + Scan all SETs and see if we can deduce anything about what + bits are known to be zero for some registers and how many copies + of the sign bit are known to exist for those registers. + + Also set any known values so that we can use it while searching + for what bits are known to be set. */ + + label_tick = 1; + + setup_incoming_promotions (); + + for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) + { + INSN_CUID (insn) = ++i; + subst_low_cuid = i; + subst_insn = insn; + + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies); + record_dead_and_set_regs (insn); + } + + if (GET_CODE (insn) == CODE_LABEL) + label_tick++; + } + + nonzero_sign_valid = 1; + + /* Now scan all the insns in forward order. */ + + label_tick = 1; + last_call_cuid = 0; + mem_last_set = 0; + bzero (reg_last_death, nregs * sizeof (rtx)); + bzero (reg_last_set, nregs * sizeof (rtx)); + bzero (reg_last_set_value, nregs * sizeof (rtx)); + bzero (reg_last_set_table_tick, nregs * sizeof (int)); + bzero (reg_last_set_label, nregs * sizeof (int)); + bzero (reg_last_set_invalid, nregs * sizeof (char)); + + setup_incoming_promotions (); + + for (insn = f; insn; insn = next ? next : NEXT_INSN (insn)) + { + next = 0; + + if (GET_CODE (insn) == CODE_LABEL) + label_tick++; + + else if (GET_CODE (insn) == INSN + || GET_CODE (insn) == CALL_INSN + || GET_CODE (insn) == JUMP_INSN) + { + /* Try this insn with each insn it links back to. */ + + for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) + if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0) + goto retry; + + /* Try each sequence of three linked insns ending with this one. */ + + for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) + for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks; + nextlinks = XEXP (nextlinks, 1)) + if ((next = try_combine (insn, XEXP (links, 0), + XEXP (nextlinks, 0))) != 0) + goto retry; + +#ifdef HAVE_cc0 + /* Try to combine a jump insn that uses CC0 + with a preceding insn that sets CC0, and maybe with its + logical predecessor as well. + This is how we make decrement-and-branch insns. + We need this special code because data flow connections + via CC0 do not get entered in LOG_LINKS. */ + + if (GET_CODE (insn) == JUMP_INSN + && (prev = prev_nonnote_insn (insn)) != 0 + && GET_CODE (prev) == INSN + && sets_cc0_p (PATTERN (prev))) + { + if ((next = try_combine (insn, prev, NULL_RTX)) != 0) + goto retry; + + for (nextlinks = LOG_LINKS (prev); nextlinks; + nextlinks = XEXP (nextlinks, 1)) + if ((next = try_combine (insn, prev, + XEXP (nextlinks, 0))) != 0) + goto retry; + } + + /* Do the same for an insn that explicitly references CC0. */ + if (GET_CODE (insn) == INSN + && (prev = prev_nonnote_insn (insn)) != 0 + && GET_CODE (prev) == INSN + && sets_cc0_p (PATTERN (prev)) + && GET_CODE (PATTERN (insn)) == SET + && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) + { + if ((next = try_combine (insn, prev, NULL_RTX)) != 0) + goto retry; + + for (nextlinks = LOG_LINKS (prev); nextlinks; + nextlinks = XEXP (nextlinks, 1)) + if ((next = try_combine (insn, prev, + XEXP (nextlinks, 0))) != 0) + goto retry; + } + + /* Finally, see if any of the insns that this insn links to + explicitly references CC0. If so, try this insn, that insn, + and its predecessor if it sets CC0. */ + for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) + if (GET_CODE (XEXP (links, 0)) == INSN + && GET_CODE (PATTERN (XEXP (links, 0))) == SET + && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) + && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 + && GET_CODE (prev) == INSN + && sets_cc0_p (PATTERN (prev)) + && (next = try_combine (insn, XEXP (links, 0), prev)) != 0) + goto retry; +#endif + + /* Try combining an insn with two different insns whose results it + uses. */ + for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) + for (nextlinks = XEXP (links, 1); nextlinks; + nextlinks = XEXP (nextlinks, 1)) + if ((next = try_combine (insn, XEXP (links, 0), + XEXP (nextlinks, 0))) != 0) + goto retry; + + if (GET_CODE (insn) != NOTE) + record_dead_and_set_regs (insn); + + retry: + ; + } + } + + total_attempts += combine_attempts; + total_merges += combine_merges; + total_extras += combine_extras; + total_successes += combine_successes; + + nonzero_sign_valid = 0; +} + +/* Set up any promoted values for incoming argument registers. */ + +static void +setup_incoming_promotions () +{ +#ifdef PROMOTE_FUNCTION_ARGS + int regno; + rtx reg; + enum machine_mode mode; + int unsignedp; + rtx first = get_insns (); + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (FUNCTION_ARG_REGNO_P (regno) + && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0) + record_value_for_reg (reg, first, + gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, + GET_MODE (reg), + gen_rtx (CLOBBER, mode, const0_rtx))); +#endif +} + +/* Called via note_stores. If X is a pseudo that is used in more than + one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being + set, record what bits are known zero. If we are clobbering X, + ignore this "set" because the clobbered value won't be used. + + If we are setting only a portion of X and we can't figure out what + portion, assume all bits will be used since we don't know what will + be happening. + + Similarly, set how many bits of X are known to be copies of the sign bit + at all locations in the function. This is the smallest number implied + by any set of X. */ + +static void +set_nonzero_bits_and_sign_copies (x, set) + rtx x; + rtx set; +{ + int num; + + if (GET_CODE (x) == REG + && REGNO (x) >= FIRST_PSEUDO_REGISTER + && reg_n_sets[REGNO (x)] > 1 + && reg_basic_block[REGNO (x)] < 0 + /* If this register is undefined at the start of the file, we can't + say what its contents were. */ + && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS))) + && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) + { + if (GET_CODE (set) == CLOBBER) + { + reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); + reg_sign_bit_copies[REGNO (x)] = 0; + return; + } + + /* If this is a complex assignment, see if we can convert it into a + simple assignment. */ + set = expand_field_assignment (set); + + /* If this is a simple assignment, or we have a paradoxical SUBREG, + set what we know about X. */ + + if (SET_DEST (set) == x + || (GET_CODE (SET_DEST (set)) == SUBREG + && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) + && SUBREG_REG (SET_DEST (set)) == x)) + { + rtx src = SET_SRC (set); + +#ifdef SHORT_IMMEDIATES_SIGN_EXTEND + /* If X is narrower than a word and SRC is a non-negative + constant that would appear negative in the mode of X, + sign-extend it for use in reg_nonzero_bits because some + machines (maybe most) will actually do the sign-extension + and this is the conservative approach. + + ??? For 2.5, try to tighten up the MD files in this regard + instead of this kludge. */ + + if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD + && GET_CODE (src) == CONST_INT + && INTVAL (src) > 0 + && 0 != (INTVAL (src) + & ((HOST_WIDE_INT) 1 + << GET_MODE_BITSIZE (GET_MODE (x))))) + src = GEN_INT (INTVAL (src) + | ((HOST_WIDE_INT) (-1) + << GET_MODE_BITSIZE (GET_MODE (x)))); +#endif + + reg_nonzero_bits[REGNO (x)] + |= nonzero_bits (src, nonzero_bits_mode); + num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); + if (reg_sign_bit_copies[REGNO (x)] == 0 + || reg_sign_bit_copies[REGNO (x)] > num) + reg_sign_bit_copies[REGNO (x)] = num; + } + else + { + reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); + reg_sign_bit_copies[REGNO (x)] = 0; + } + } +} + +/* See if INSN can be combined into I3. PRED and SUCC are optionally + insns that were previously combined into I3 or that will be combined + into the merger of INSN and I3. + + Return 0 if the combination is not allowed for any reason. + + If the combination is allowed, *PDEST will be set to the single + destination of INSN and *PSRC to the single source, and this function + will return 1. */ + +static int +can_combine_p (insn, i3, pred, succ, pdest, psrc) + rtx insn; + rtx i3; + rtx pred, succ; + rtx *pdest, *psrc; +{ + int i; + rtx set = 0, src, dest; + rtx p, link; + int all_adjacent = (succ ? (next_active_insn (insn) == succ + && next_active_insn (succ) == i3) + : next_active_insn (insn) == i3); + + /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. + or a PARALLEL consisting of such a SET and CLOBBERs. + + If INSN has CLOBBER parallel parts, ignore them for our processing. + By definition, these happen during the execution of the insn. When it + is merged with another insn, all bets are off. If they are, in fact, + needed and aren't also supplied in I3, they may be added by + recog_for_combine. Otherwise, it won't match. + + We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED + note. + + Get the source and destination of INSN. If more than one, can't + combine. */ + + if (GET_CODE (PATTERN (insn)) == SET) + set = PATTERN (insn); + else if (GET_CODE (PATTERN (insn)) == PARALLEL + && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) + { + for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) + { + rtx elt = XVECEXP (PATTERN (insn), 0, i); + + switch (GET_CODE (elt)) + { + /* We can ignore CLOBBERs. */ + case CLOBBER: + break; + + case SET: + /* Ignore SETs whose result isn't used but not those that + have side-effects. */ + if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) + && ! side_effects_p (elt)) + break; + + /* If we have already found a SET, this is a second one and + so we cannot combine with this insn. */ + if (set) + return 0; + + set = elt; + break; + + default: + /* Anything else means we can't combine. */ + return 0; + } + } + + if (set == 0 + /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, + so don't do anything with it. */ + || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) + return 0; + } + else + return 0; + + if (set == 0) + return 0; + + set = expand_field_assignment (set); + src = SET_SRC (set), dest = SET_DEST (set); + + /* Don't eliminate a store in the stack pointer. */ + if (dest == stack_pointer_rtx + /* Don't install a subreg involving two modes not tieable. + It can worsen register allocation, and can even make invalid reload + insns, since the reg inside may need to be copied from in the + outside mode, and that may be invalid if it is an fp reg copied in + integer mode. As a special exception, we can allow this if + I3 is simply copying DEST, a REG, to CC0. */ + || (GET_CODE (src) == SUBREG + && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src))) +#ifdef HAVE_cc0 + && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET + && SET_DEST (PATTERN (i3)) == cc0_rtx + && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3))) +#endif + ) + /* If we couldn't eliminate a field assignment, we can't combine. */ + || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART + /* Don't combine with an insn that sets a register to itself if it has + a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ + || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) + /* Can't merge a function call. */ + || GET_CODE (src) == CALL + /* Don't substitute into an incremented register. */ + || FIND_REG_INC_NOTE (i3, dest) + || (succ && FIND_REG_INC_NOTE (succ, dest)) + /* Don't combine the end of a libcall into anything. */ + || find_reg_note (insn, REG_RETVAL, NULL_RTX) + /* Make sure that DEST is not used after SUCC but before I3. */ + || (succ && ! all_adjacent + && reg_used_between_p (dest, succ, i3)) + /* Make sure that the value that is to be substituted for the register + does not use any registers whose values alter in between. However, + If the insns are adjacent, a use can't cross a set even though we + think it might (this can happen for a sequence of insns each setting + the same destination; reg_last_set of that register might point to + a NOTE). Also, don't move a volatile asm or UNSPEC_VOLATILE across + any other insns. */ + || (! all_adjacent + && (use_crosses_set_p (src, INSN_CUID (insn)) + || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) + || GET_CODE (src) == UNSPEC_VOLATILE)) + /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get + better register allocation by not doing the combine. */ + || find_reg_note (i3, REG_NO_CONFLICT, dest) + || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) + /* Don't combine across a CALL_INSN, because that would possibly + change whether the life span of some REGs crosses calls or not, + and it is a pain to update that information. + Exception: if source is a constant, moving it later can't hurt. + Accept that special case, because it helps -fforce-addr a lot. */ + || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) + return 0; + + /* DEST must either be a REG or CC0. */ + if (GET_CODE (dest) == REG) + { + /* If register alignment is being enforced for multi-word items in all + cases except for parameters, it is possible to have a register copy + insn referencing a hard register that is not allowed to contain the + mode being copied and which would not be valid as an operand of most + insns. Eliminate this problem by not combining with such an insn. + + Also, on some machines we don't want to extend the life of a hard + register. */ + + if (GET_CODE (src) == REG + && ((REGNO (dest) < FIRST_PSEUDO_REGISTER + && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) +#ifdef SMALL_REGISTER_CLASSES + /* Don't extend the life of a hard register. */ + || REGNO (src) < FIRST_PSEUDO_REGISTER +#else + || (REGNO (src) < FIRST_PSEUDO_REGISTER + && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))) +#endif + )) + return 0; + } + else if (GET_CODE (dest) != CC0) + return 0; + + /* Don't substitute for a register intended as a clobberable operand. + Similarly, don't substitute an expression containing a register that + will be clobbered in I3. */ + if (GET_CODE (PATTERN (i3)) == PARALLEL) + for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) + if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER + && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), + src) + || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))) + return 0; + + /* If INSN contains anything volatile, or is an `asm' (whether volatile + or not), reject, unless nothing volatile comes between it and I3, + with the exception of SUCC. */ + + if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) + for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) + if (GET_RTX_CLASS (GET_CODE (p)) == 'i' + && p != succ && volatile_refs_p (PATTERN (p))) + return 0; + + /* If INSN or I2 contains an autoincrement or autodecrement, + make sure that register is not used between there and I3, + and not already used in I3 either. + Also insist that I3 not be a jump; if it were one + and the incremented register were spilled, we would lose. */ + +#ifdef AUTO_INC_DEC + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_INC + && (GET_CODE (i3) == JUMP_INSN + || reg_used_between_p (XEXP (link, 0), insn, i3) + || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) + return 0; +#endif + +#ifdef HAVE_cc0 + /* Don't combine an insn that follows a CC0-setting insn. + An insn that uses CC0 must not be separated from the one that sets it. + We do, however, allow I2 to follow a CC0-setting insn if that insn + is passed as I1; in that case it will be deleted also. + We also allow combining in this case if all the insns are adjacent + because that would leave the two CC0 insns adjacent as well. + It would be more logical to test whether CC0 occurs inside I1 or I2, + but that would be much slower, and this ought to be equivalent. */ + + p = prev_nonnote_insn (insn); + if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p)) + && ! all_adjacent) + return 0; +#endif + + /* If we get here, we have passed all the tests and the combination is + to be allowed. */ + + *pdest = dest; + *psrc = src; + + return 1; +} + +/* LOC is the location within I3 that contains its pattern or the component + of a PARALLEL of the pattern. We validate that it is valid for combining. + + One problem is if I3 modifies its output, as opposed to replacing it + entirely, we can't allow the output to contain I2DEST or I1DEST as doing + so would produce an insn that is not equivalent to the original insns. + + Consider: + + (set (reg:DI 101) (reg:DI 100)) + (set (subreg:SI (reg:DI 101) 0) ) + + This is NOT equivalent to: + + (parallel [(set (subreg:SI (reg:DI 100) 0) ) + (set (reg:DI 101) (reg:DI 100))]) + + Not only does this modify 100 (in which case it might still be valid + if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. + + We can also run into a problem if I2 sets a register that I1 + uses and I1 gets directly substituted into I3 (not via I2). In that + case, we would be getting the wrong value of I2DEST into I3, so we + must reject the combination. This case occurs when I2 and I1 both + feed into I3, rather than when I1 feeds into I2, which feeds into I3. + If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source + of a SET must prevent combination from occurring. + + On machines where SMALL_REGISTER_CLASSES is defined, we don't combine + if the destination of a SET is a hard register. + + Before doing the above check, we first try to expand a field assignment + into a set of logical operations. + + If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which + we place a register that is both set and used within I3. If more than one + such register is detected, we fail. + + Return 1 if the combination is valid, zero otherwise. */ + +static int +combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed) + rtx i3; + rtx *loc; + rtx i2dest; + rtx i1dest; + int i1_not_in_src; + rtx *pi3dest_killed; +{ + rtx x = *loc; + + if (GET_CODE (x) == SET) + { + rtx set = expand_field_assignment (x); + rtx dest = SET_DEST (set); + rtx src = SET_SRC (set); + rtx inner_dest = dest, inner_src = src; + + SUBST (*loc, set); + + while (GET_CODE (inner_dest) == STRICT_LOW_PART + || GET_CODE (inner_dest) == SUBREG + || GET_CODE (inner_dest) == ZERO_EXTRACT) + inner_dest = XEXP (inner_dest, 0); + + /* We probably don't need this any more now that LIMIT_RELOAD_CLASS + was added. */ +#if 0 + while (GET_CODE (inner_src) == STRICT_LOW_PART + || GET_CODE (inner_src) == SUBREG + || GET_CODE (inner_src) == ZERO_EXTRACT) + inner_src = XEXP (inner_src, 0); + + /* If it is better that two different modes keep two different pseudos, + avoid combining them. This avoids producing the following pattern + on a 386: + (set (subreg:SI (reg/v:QI 21) 0) + (lshiftrt:SI (reg/v:SI 20) + (const_int 24))) + If that were made, reload could not handle the pair of + reg 20/21, since it would try to get any GENERAL_REGS + but some of them don't handle QImode. */ + + if (rtx_equal_p (inner_src, i2dest) + && GET_CODE (inner_dest) == REG + && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest))) + return 0; +#endif + + /* Check for the case where I3 modifies its output, as + discussed above. */ + if ((inner_dest != dest + && (reg_overlap_mentioned_p (i2dest, inner_dest) + || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) + /* This is the same test done in can_combine_p except that we + allow a hard register with SMALL_REGISTER_CLASSES if SRC is a + CALL operation. */ + || (GET_CODE (inner_dest) == REG + && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER +#ifdef SMALL_REGISTER_CLASSES + && GET_CODE (src) != CALL +#else + && ! HARD_REGNO_MODE_OK (REGNO (inner_dest), + GET_MODE (inner_dest)) +#endif + ) + + || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) + return 0; + + /* If DEST is used in I3, it is being killed in this insn, + so record that for later. + Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the + STACK_POINTER_REGNUM, since these are always considered to be + live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ + if (pi3dest_killed && GET_CODE (dest) == REG + && reg_referenced_p (dest, PATTERN (i3)) + && REGNO (dest) != FRAME_POINTER_REGNUM +#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM + && (REGNO (dest) != ARG_POINTER_REGNUM + || ! fixed_regs [REGNO (dest)]) +#endif + && REGNO (dest) != STACK_POINTER_REGNUM) + { + if (*pi3dest_killed) + return 0; + + *pi3dest_killed = dest; + } + } + + else if (GET_CODE (x) == PARALLEL) + { + int i; + + for (i = 0; i < XVECLEN (x, 0); i++) + if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, + i1_not_in_src, pi3dest_killed)) + return 0; + } + + return 1; +} + +/* Try to combine the insns I1 and I2 into I3. + Here I1 and I2 appear earlier than I3. + I1 can be zero; then we combine just I2 into I3. + + It we are combining three insns and the resulting insn is not recognized, + try splitting it into two insns. If that happens, I2 and I3 are retained + and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 + are pseudo-deleted. + + If we created two insns, return I2; otherwise return I3. + Return 0 if the combination does not work. Then nothing is changed. */ + +static rtx +try_combine (i3, i2, i1) + register rtx i3, i2, i1; +{ + /* New patterns for I3 and I3, respectively. */ + rtx newpat, newi2pat = 0; + /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ + int added_sets_1, added_sets_2; + /* Total number of SETs to put into I3. */ + int total_sets; + /* Nonzero is I2's body now appears in I3. */ + int i2_is_used; + /* INSN_CODEs for new I3, new I2, and user of condition code. */ + int insn_code_number, i2_code_number, other_code_number; + /* Contains I3 if the destination of I3 is used in its source, which means + that the old life of I3 is being killed. If that usage is placed into + I2 and not in I3, a REG_DEAD note must be made. */ + rtx i3dest_killed = 0; + /* SET_DEST and SET_SRC of I2 and I1. */ + rtx i2dest, i2src, i1dest = 0, i1src = 0; + /* PATTERN (I2), or a copy of it in certain cases. */ + rtx i2pat; + /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ + int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0; + int i1_feeds_i3 = 0; + /* Notes that must be added to REG_NOTES in I3 and I2. */ + rtx new_i3_notes, new_i2_notes; + + int maxreg; + rtx temp; + register rtx link; + int i; + + /* If any of I1, I2, and I3 isn't really an insn, we can't do anything. + This can occur when flow deletes an insn that it has merged into an + auto-increment address. We also can't do anything if I3 has a + REG_LIBCALL note since we don't want to disrupt the contiguity of a + libcall. */ + + if (GET_RTX_CLASS (GET_CODE (i3)) != 'i' + || GET_RTX_CLASS (GET_CODE (i2)) != 'i' + || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i') + || find_reg_note (i3, REG_LIBCALL, NULL_RTX)) + return 0; + + combine_attempts++; + + undobuf.num_undo = previous_num_undos = 0; + undobuf.other_insn = 0; + + /* Save the current high-water-mark so we can free storage if we didn't + accept this combination. */ + undobuf.storage = (char *) oballoc (0); + + /* If I1 and I2 both feed I3, they can be in any order. To simplify the + code below, set I1 to be the earlier of the two insns. */ + if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) + temp = i1, i1 = i2, i2 = temp; + + /* First check for one important special-case that the code below will + not handle. Namely, the case where I1 is zero, I2 has multiple sets, + and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, + we may be able to replace that destination with the destination of I3. + This occurs in the common code where we compute both a quotient and + remainder into a structure, in which case we want to do the computation + directly into the structure to avoid register-register copies. + + We make very conservative checks below and only try to handle the + most common cases of this. For example, we only handle the case + where I2 and I3 are adjacent to avoid making difficult register + usage tests. */ + + if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET + && GET_CODE (SET_SRC (PATTERN (i3))) == REG + && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER +#ifdef SMALL_REGISTER_CLASSES + && (GET_CODE (SET_DEST (PATTERN (i3))) != REG + || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER) +#endif + && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) + && GET_CODE (PATTERN (i2)) == PARALLEL + && ! side_effects_p (SET_DEST (PATTERN (i3))) + /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code + below would need to check what is inside (and reg_overlap_mentioned_p + doesn't support those codes anyway). Don't allow those destinations; + the resulting insn isn't likely to be recognized anyway. */ + && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT + && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART + && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), + SET_DEST (PATTERN (i3))) + && next_real_insn (i2) == i3) + { + rtx p2 = PATTERN (i2); + + /* Make sure that the destination of I3, + which we are going to substitute into one output of I2, + is not used within another output of I2. We must avoid making this: + (parallel [(set (mem (reg 69)) ...) + (set (reg 69) ...)]) + which is not well-defined as to order of actions. + (Besides, reload can't handle output reloads for this.) + + The problem can also happen if the dest of I3 is a memory ref, + if another dest in I2 is an indirect memory ref. */ + for (i = 0; i < XVECLEN (p2, 0); i++) + if (GET_CODE (XVECEXP (p2, 0, i)) == SET + && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), + SET_DEST (XVECEXP (p2, 0, i)))) + break; + + if (i == XVECLEN (p2, 0)) + for (i = 0; i < XVECLEN (p2, 0); i++) + if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) + { + combine_merges++; + + subst_insn = i3; + subst_low_cuid = INSN_CUID (i2); + + added_sets_2 = 0; + i2dest = SET_SRC (PATTERN (i3)); + + /* Replace the dest in I2 with our dest and make the resulting + insn the new pattern for I3. Then skip to where we + validate the pattern. Everything was set up above. */ + SUBST (SET_DEST (XVECEXP (p2, 0, i)), + SET_DEST (PATTERN (i3))); + + newpat = p2; + goto validate_replacement; + } + } + +#ifndef HAVE_cc0 + /* If we have no I1 and I2 looks like: + (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) + (set Y OP)]) + make up a dummy I1 that is + (set Y OP) + and change I2 to be + (set (reg:CC X) (compare:CC Y (const_int 0))) + + (We can ignore any trailing CLOBBERs.) + + This undoes a previous combination and allows us to match a branch-and- + decrement insn. */ + + if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL + && XVECLEN (PATTERN (i2), 0) >= 2 + && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET + && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) + == MODE_CC) + && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE + && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx + && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET + && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG + && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), + SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) + { + for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) + if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) + break; + + if (i == 1) + { + /* We make I1 with the same INSN_UID as I2. This gives it + the same INSN_CUID for value tracking. Our fake I1 will + never appear in the insn stream so giving it the same INSN_UID + as I2 will not cause a problem. */ + + i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2, + XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0); + + SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); + SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), + SET_DEST (PATTERN (i1))); + } + } +#endif + + /* Verify that I2 and I1 are valid for combining. */ + if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) + || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) + { + undo_all (); + return 0; + } + + /* Record whether I2DEST is used in I2SRC and similarly for the other + cases. Knowing this will help in register status updating below. */ + i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); + i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); + i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); + + /* See if I1 directly feeds into I3. It does if I1DEST is not used + in I2SRC. */ + i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); + + /* Ensure that I3's pattern can be the destination of combines. */ + if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, + i1 && i2dest_in_i1src && i1_feeds_i3, + &i3dest_killed)) + { + undo_all (); + return 0; + } + + /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. + We used to do this EXCEPT in one case: I3 has a post-inc in an + output operand. However, that exception can give rise to insns like + mov r3,(r3)+ + which is a famous insn on the PDP-11 where the value of r3 used as the + source was model-dependent. Avoid this sort of thing. */ + +#if 0 + if (!(GET_CODE (PATTERN (i3)) == SET + && GET_CODE (SET_SRC (PATTERN (i3))) == REG + && GET_CODE (SET_DEST (PATTERN (i3))) == MEM + && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC + || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) + /* It's not the exception. */ +#endif +#ifdef AUTO_INC_DEC + for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_INC + && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) + || (i1 != 0 + && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) + { + undo_all (); + return 0; + } +#endif + + /* See if the SETs in I1 or I2 need to be kept around in the merged + instruction: whenever the value set there is still needed past I3. + For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. + + For the SET in I1, we have two cases: If I1 and I2 independently + feed into I3, the set in I1 needs to be kept around if I1DEST dies + or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set + in I1 needs to be kept around unless I1DEST dies or is set in either + I2 or I3. We can distinguish these cases by seeing if I2SRC mentions + I1DEST. If so, we know I1 feeds into I2. */ + + added_sets_2 = ! dead_or_set_p (i3, i2dest); + + added_sets_1 + = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) + : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); + + /* If the set in I2 needs to be kept around, we must make a copy of + PATTERN (I2), so that when we substitute I1SRC for I1DEST in + PATTERN (I2), we are only substituting for the original I1DEST, not into + an already-substituted copy. This also prevents making self-referential + rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to + I2DEST. */ + + i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL + ? gen_rtx (SET, VOIDmode, i2dest, i2src) + : PATTERN (i2)); + + if (added_sets_2) + i2pat = copy_rtx (i2pat); + + combine_merges++; + + /* Substitute in the latest insn for the regs set by the earlier ones. */ + + maxreg = max_reg_num (); + + subst_insn = i3; + + /* It is possible that the source of I2 or I1 may be performing an + unneeded operation, such as a ZERO_EXTEND of something that is known + to have the high part zero. Handle that case by letting subst look at + the innermost one of them. + + Another way to do this would be to have a function that tries to + simplify a single insn instead of merging two or more insns. We don't + do this because of the potential of infinite loops and because + of the potential extra memory required. However, doing it the way + we are is a bit of a kludge and doesn't catch all cases. + + But only do this if -fexpensive-optimizations since it slows things down + and doesn't usually win. */ + + if (flag_expensive_optimizations) + { + /* Pass pc_rtx so no substitutions are done, just simplifications. + The cases that we are interested in here do not involve the few + cases were is_replaced is checked. */ + if (i1) + { + subst_low_cuid = INSN_CUID (i1); + i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); + } + else + { + subst_low_cuid = INSN_CUID (i2); + i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); + } + + previous_num_undos = undobuf.num_undo; + } + +#ifndef HAVE_cc0 + /* Many machines that don't use CC0 have insns that can both perform an + arithmetic operation and set the condition code. These operations will + be represented as a PARALLEL with the first element of the vector + being a COMPARE of an arithmetic operation with the constant zero. + The second element of the vector will set some pseudo to the result + of the same arithmetic operation. If we simplify the COMPARE, we won't + match such a pattern and so will generate an extra insn. Here we test + for this case, where both the comparison and the operation result are + needed, and make the PARALLEL by just replacing I2DEST in I3SRC with + I2SRC. Later we will make the PARALLEL that contains I2. */ + + if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET + && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE + && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx + && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) + { + rtx *cc_use; + enum machine_mode compare_mode; + + newpat = PATTERN (i3); + SUBST (XEXP (SET_SRC (newpat), 0), i2src); + + i2_is_used = 1; + +#ifdef EXTRA_CC_MODES + /* See if a COMPARE with the operand we substituted in should be done + with the mode that is currently being used. If not, do the same + processing we do in `subst' for a SET; namely, if the destination + is used only once, try to replace it with a register of the proper + mode and also replace the COMPARE. */ + if (undobuf.other_insn == 0 + && (cc_use = find_single_use (SET_DEST (newpat), i3, + &undobuf.other_insn)) + && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), + i2src, const0_rtx)) + != GET_MODE (SET_DEST (newpat)))) + { + int regno = REGNO (SET_DEST (newpat)); + rtx new_dest = gen_rtx (REG, compare_mode, regno); + + if (regno < FIRST_PSEUDO_REGISTER + || (reg_n_sets[regno] == 1 && ! added_sets_2 + && ! REG_USERVAR_P (SET_DEST (newpat)))) + { + if (regno >= FIRST_PSEUDO_REGISTER) + SUBST (regno_reg_rtx[regno], new_dest); + + SUBST (SET_DEST (newpat), new_dest); + SUBST (XEXP (*cc_use, 0), new_dest); + SUBST (SET_SRC (newpat), + gen_rtx_combine (COMPARE, compare_mode, + i2src, const0_rtx)); + } + else + undobuf.other_insn = 0; + } +#endif + } + else +#endif + { + n_occurrences = 0; /* `subst' counts here */ + + /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we + need to make a unique copy of I2SRC each time we substitute it + to avoid self-referential rtl. */ + + subst_low_cuid = INSN_CUID (i2); + newpat = subst (PATTERN (i3), i2dest, i2src, 0, + ! i1_feeds_i3 && i1dest_in_i1src); + previous_num_undos = undobuf.num_undo; + + /* Record whether i2's body now appears within i3's body. */ + i2_is_used = n_occurrences; + } + + /* If we already got a failure, don't try to do more. Otherwise, + try to substitute in I1 if we have it. */ + + if (i1 && GET_CODE (newpat) != CLOBBER) + { + /* Before we can do this substitution, we must redo the test done + above (see detailed comments there) that ensures that I1DEST + isn't mentioned in any SETs in NEWPAT that are field assignments. */ + + if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, + 0, NULL_PTR)) + { + undo_all (); + return 0; + } + + n_occurrences = 0; + subst_low_cuid = INSN_CUID (i1); + newpat = subst (newpat, i1dest, i1src, 0, 0); + previous_num_undos = undobuf.num_undo; + } + + /* Fail if an autoincrement side-effect has been duplicated. Be careful + to count all the ways that I2SRC and I1SRC can be used. */ + if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 + && i2_is_used + added_sets_2 > 1) + || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 + && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) + > 1)) + /* Fail if we tried to make a new register (we used to abort, but there's + really no reason to). */ + || max_reg_num () != maxreg + /* Fail if we couldn't do something and have a CLOBBER. */ + || GET_CODE (newpat) == CLOBBER) + { + undo_all (); + return 0; + } + + /* If the actions of the earlier insns must be kept + in addition to substituting them into the latest one, + we must make a new PARALLEL for the latest insn + to hold additional the SETs. */ + + if (added_sets_1 || added_sets_2) + { + combine_extras++; + + if (GET_CODE (newpat) == PARALLEL) + { + rtvec old = XVEC (newpat, 0); + total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; + newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets)); + bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0), + sizeof (old->elem[0]) * old->num_elem); + } + else + { + rtx old = newpat; + total_sets = 1 + added_sets_1 + added_sets_2; + newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets)); + XVECEXP (newpat, 0, 0) = old; + } + + if (added_sets_1) + XVECEXP (newpat, 0, --total_sets) + = (GET_CODE (PATTERN (i1)) == PARALLEL + ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1)); + + if (added_sets_2) + { + /* If there is no I1, use I2's body as is. We used to also not do + the subst call below if I2 was substituted into I3, + but that could lose a simplification. */ + if (i1 == 0) + XVECEXP (newpat, 0, --total_sets) = i2pat; + else + /* See comment where i2pat is assigned. */ + XVECEXP (newpat, 0, --total_sets) + = subst (i2pat, i1dest, i1src, 0, 0); + } + } + + /* We come here when we are replacing a destination in I2 with the + destination of I3. */ + validate_replacement: + + /* Is the result of combination a valid instruction? */ + insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); + + /* If the result isn't valid, see if it is a PARALLEL of two SETs where + the second SET's destination is a register that is unused. In that case, + we just need the first SET. This can occur when simplifying a divmod + insn. We *must* test for this case here because the code below that + splits two independent SETs doesn't handle this case correctly when it + updates the register status. Also check the case where the first + SET's destination is unused. That would not cause incorrect code, but + does cause an unneeded insn to remain. */ + + if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL + && XVECLEN (newpat, 0) == 2 + && GET_CODE (XVECEXP (newpat, 0, 0)) == SET + && GET_CODE (XVECEXP (newpat, 0, 1)) == SET + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG + && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1))) + && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1))) + && asm_noperands (newpat) < 0) + { + newpat = XVECEXP (newpat, 0, 0); + insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); + } + + else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL + && XVECLEN (newpat, 0) == 2 + && GET_CODE (XVECEXP (newpat, 0, 0)) == SET + && GET_CODE (XVECEXP (newpat, 0, 1)) == SET + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG + && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0))) + && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0))) + && asm_noperands (newpat) < 0) + { + newpat = XVECEXP (newpat, 0, 1); + insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); + } + + /* See if this is an XOR. If so, perhaps the problem is that the + constant is out of range. Replace it with a complemented XOR with + a complemented constant; it might be in range. */ + + else if (insn_code_number < 0 && GET_CODE (newpat) == SET + && GET_CODE (SET_SRC (newpat)) == XOR + && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT + && ((temp = simplify_unary_operation (NOT, + GET_MODE (SET_SRC (newpat)), + XEXP (SET_SRC (newpat), 1), + GET_MODE (SET_SRC (newpat)))) + != 0)) + { + enum machine_mode i_mode = GET_MODE (SET_SRC (newpat)); + rtx pat + = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat), + gen_unary (NOT, i_mode, + gen_binary (XOR, i_mode, + XEXP (SET_SRC (newpat), 0), + temp))); + + insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes); + if (insn_code_number >= 0) + newpat = pat; + } + + /* If we were combining three insns and the result is a simple SET + with no ASM_OPERANDS that wasn't recognized, try to split it into two + insns. There are two ways to do this. It can be split using a + machine-specific method (like when you have an addition of a large + constant) or by combine in the function find_split_point. */ + + if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET + && asm_noperands (newpat) < 0) + { + rtx m_split, *split; + rtx ni2dest = i2dest; + + /* See if the MD file can split NEWPAT. If it can't, see if letting it + use I2DEST as a scratch register will help. In the latter case, + convert I2DEST to the mode of the source of NEWPAT if we can. */ + + m_split = split_insns (newpat, i3); + + /* We can only use I2DEST as a scratch reg if it doesn't overlap any + inputs of NEWPAT. */ + + /* ??? If I2DEST is not safe, and I1DEST exists, then it would be + possible to try that as a scratch reg. This would require adding + more code to make it work though. */ + + if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat)) + { + /* If I2DEST is a hard register or the only use of a pseudo, + we can change its mode. */ + if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest) + && GET_MODE (SET_DEST (newpat)) != VOIDmode + && GET_CODE (i2dest) == REG + && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER + || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2 + && ! REG_USERVAR_P (i2dest)))) + ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)), + REGNO (i2dest)); + + m_split = split_insns (gen_rtx (PARALLEL, VOIDmode, + gen_rtvec (2, newpat, + gen_rtx (CLOBBER, + VOIDmode, + ni2dest))), + i3); + } + + if (m_split && GET_CODE (m_split) == SEQUENCE + && XVECLEN (m_split, 0) == 2 + && (next_real_insn (i2) == i3 + || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)), + INSN_CUID (i2)))) + { + rtx i2set, i3set; + rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1)); + newi2pat = PATTERN (XVECEXP (m_split, 0, 0)); + + i3set = single_set (XVECEXP (m_split, 0, 1)); + i2set = single_set (XVECEXP (m_split, 0, 0)); + + /* In case we changed the mode of I2DEST, replace it in the + pseudo-register table here. We can't do it above in case this + code doesn't get executed and we do a split the other way. */ + + if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) + SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest); + + i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); + + /* If I2 or I3 has multiple SETs, we won't know how to track + register status, so don't use these insns. */ + + if (i2_code_number >= 0 && i2set && i3set) + insn_code_number = recog_for_combine (&newi3pat, i3, + &new_i3_notes); + + if (insn_code_number >= 0) + newpat = newi3pat; + + /* It is possible that both insns now set the destination of I3. + If so, we must show an extra use of it. */ + + if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG + && GET_CODE (SET_DEST (i2set)) == REG + && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set))) + reg_n_sets[REGNO (SET_DEST (i2set))]++; + } + + /* If we can split it and use I2DEST, go ahead and see if that + helps things be recognized. Verify that none of the registers + are set between I2 and I3. */ + if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 +#ifdef HAVE_cc0 + && GET_CODE (i2dest) == REG +#endif + /* We need I2DEST in the proper mode. If it is a hard register + or the only use of a pseudo, we can change its mode. */ + && (GET_MODE (*split) == GET_MODE (i2dest) + || GET_MODE (*split) == VOIDmode + || REGNO (i2dest) < FIRST_PSEUDO_REGISTER + || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2 + && ! REG_USERVAR_P (i2dest))) + && (next_real_insn (i2) == i3 + || ! use_crosses_set_p (*split, INSN_CUID (i2))) + /* We can't overwrite I2DEST if its value is still used by + NEWPAT. */ + && ! reg_referenced_p (i2dest, newpat)) + { + rtx newdest = i2dest; + + /* Get NEWDEST as a register in the proper mode. We have already + validated that we can do this. */ + if (GET_MODE (i2dest) != GET_MODE (*split) + && GET_MODE (*split) != VOIDmode) + { + newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest)); + + if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) + SUBST (regno_reg_rtx[REGNO (i2dest)], newdest); + } + + /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to + an ASHIFT. This can occur if it was inside a PLUS and hence + appeared to be a memory address. This is a kludge. */ + if (GET_CODE (*split) == MULT + && GET_CODE (XEXP (*split, 1)) == CONST_INT + && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) + SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split), + XEXP (*split, 0), GEN_INT (i))); + +#ifdef INSN_SCHEDULING + /* If *SPLIT is a paradoxical SUBREG, when we split it, it should + be written as a ZERO_EXTEND. */ + if (GET_CODE (*split) == SUBREG + && GET_CODE (SUBREG_REG (*split)) == MEM) + SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split), + XEXP (*split, 0))); +#endif + + newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split); + SUBST (*split, newdest); + i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); + if (i2_code_number >= 0) + insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); + } + } + + /* Check for a case where we loaded from memory in a narrow mode and + then sign extended it, but we need both registers. In that case, + we have a PARALLEL with both loads from the same memory location. + We can split this into a load from memory followed by a register-register + copy. This saves at least one insn, more if register allocation can + eliminate the copy. */ + + else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 + && GET_CODE (newpat) == PARALLEL + && XVECLEN (newpat, 0) == 2 + && GET_CODE (XVECEXP (newpat, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND + && GET_CODE (XVECEXP (newpat, 0, 1)) == SET + && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), + XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) + && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), + INSN_CUID (i2)) + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART + && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), + SET_SRC (XVECEXP (newpat, 0, 1))) + && ! find_reg_note (i3, REG_UNUSED, + SET_DEST (XVECEXP (newpat, 0, 0)))) + { + rtx ni2dest; + + newi2pat = XVECEXP (newpat, 0, 0); + ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); + newpat = XVECEXP (newpat, 0, 1); + SUBST (SET_SRC (newpat), + gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest)); + i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); + if (i2_code_number >= 0) + insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); + + if (insn_code_number >= 0) + { + rtx insn; + rtx link; + + /* If we will be able to accept this, we have made a change to the + destination of I3. This can invalidate a LOG_LINKS pointing + to I3. No other part of combine.c makes such a transformation. + + The new I3 will have a destination that was previously the + destination of I1 or I2 and which was used in i2 or I3. Call + distribute_links to make a LOG_LINK from the next use of + that destination. */ + + PATTERN (i3) = newpat; + distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX)); + + /* I3 now uses what used to be its destination and which is + now I2's destination. That means we need a LOG_LINK from + I3 to I2. But we used to have one, so we still will. + + However, some later insn might be using I2's dest and have + a LOG_LINK pointing at I3. We must remove this link. + The simplest way to remove the link is to point it at I1, + which we know will be a NOTE. */ + + for (insn = NEXT_INSN (i3); + insn && GET_CODE (insn) != CODE_LABEL + && GET_CODE (PREV_INSN (insn)) != JUMP_INSN; + insn = NEXT_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_referenced_p (ni2dest, PATTERN (insn))) + { + for (link = LOG_LINKS (insn); link; + link = XEXP (link, 1)) + if (XEXP (link, 0) == i3) + XEXP (link, 0) = i1; + + break; + } + } + } + } + + /* Similarly, check for a case where we have a PARALLEL of two independent + SETs but we started with three insns. In this case, we can do the sets + as two separate insns. This case occurs when some SET allows two + other insns to combine, but the destination of that SET is still live. */ + + else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 + && GET_CODE (newpat) == PARALLEL + && XVECLEN (newpat, 0) == 2 + && GET_CODE (XVECEXP (newpat, 0, 0)) == SET + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART + && GET_CODE (XVECEXP (newpat, 0, 1)) == SET + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART + && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), + INSN_CUID (i2)) + /* Don't pass sets with (USE (MEM ...)) dests to the following. */ + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE + && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), + XVECEXP (newpat, 0, 0)) + && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), + XVECEXP (newpat, 0, 1))) + { + newi2pat = XVECEXP (newpat, 0, 1); + newpat = XVECEXP (newpat, 0, 0); + + i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); + if (i2_code_number >= 0) + insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); + } + + /* If it still isn't recognized, fail and change things back the way they + were. */ + if ((insn_code_number < 0 + /* Is the result a reasonable ASM_OPERANDS? */ + && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) + { + undo_all (); + return 0; + } + + /* If we had to change another insn, make sure it is valid also. */ + if (undobuf.other_insn) + { + rtx other_notes = REG_NOTES (undobuf.other_insn); + rtx other_pat = PATTERN (undobuf.other_insn); + rtx new_other_notes; + rtx note, next; + + other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, + &new_other_notes); + + if (other_code_number < 0 && ! check_asm_operands (other_pat)) + { + undo_all (); + return 0; + } + + PATTERN (undobuf.other_insn) = other_pat; + + /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they + are still valid. Then add any non-duplicate notes added by + recog_for_combine. */ + for (note = REG_NOTES (undobuf.other_insn); note; note = next) + { + next = XEXP (note, 1); + + if (REG_NOTE_KIND (note) == REG_UNUSED + && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) + { + if (GET_CODE (XEXP (note, 0)) == REG) + reg_n_deaths[REGNO (XEXP (note, 0))]--; + + remove_note (undobuf.other_insn, note); + } + } + + for (note = new_other_notes; note; note = XEXP (note, 1)) + if (GET_CODE (XEXP (note, 0)) == REG) + reg_n_deaths[REGNO (XEXP (note, 0))]++; + + distribute_notes (new_other_notes, undobuf.other_insn, + undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX); + } + + /* We now know that we can do this combination. Merge the insns and + update the status of registers and LOG_LINKS. */ + + { + rtx i3notes, i2notes, i1notes = 0; + rtx i3links, i2links, i1links = 0; + rtx midnotes = 0; + int all_adjacent = (next_real_insn (i2) == i3 + && (i1 == 0 || next_real_insn (i1) == i2)); + register int regno; + /* Compute which registers we expect to eliminate. */ + rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src + ? 0 : i2dest); + rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest; + + /* Get the old REG_NOTES and LOG_LINKS from all our insns and + clear them. */ + i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); + i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); + if (i1) + i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); + + /* Ensure that we do not have something that should not be shared but + occurs multiple times in the new insns. Check this by first + resetting all the `used' flags and then copying anything is shared. */ + + reset_used_flags (i3notes); + reset_used_flags (i2notes); + reset_used_flags (i1notes); + reset_used_flags (newpat); + reset_used_flags (newi2pat); + if (undobuf.other_insn) + reset_used_flags (PATTERN (undobuf.other_insn)); + + i3notes = copy_rtx_if_shared (i3notes); + i2notes = copy_rtx_if_shared (i2notes); + i1notes = copy_rtx_if_shared (i1notes); + newpat = copy_rtx_if_shared (newpat); + newi2pat = copy_rtx_if_shared (newi2pat); + if (undobuf.other_insn) + reset_used_flags (PATTERN (undobuf.other_insn)); + + INSN_CODE (i3) = insn_code_number; + PATTERN (i3) = newpat; + if (undobuf.other_insn) + INSN_CODE (undobuf.other_insn) = other_code_number; + + /* We had one special case above where I2 had more than one set and + we replaced a destination of one of those sets with the destination + of I3. In that case, we have to update LOG_LINKS of insns later + in this basic block. Note that this (expensive) case is rare. */ + + if (GET_CODE (PATTERN (i2)) == PARALLEL) + for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) + if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG + && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest + && ! find_reg_note (i2, REG_UNUSED, + SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) + { + register rtx insn; + + for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn)) + { + if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i') + for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) + if (XEXP (link, 0) == i2) + XEXP (link, 0) = i3; + + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == JUMP_INSN) + break; + } + } + + LOG_LINKS (i3) = 0; + REG_NOTES (i3) = 0; + LOG_LINKS (i2) = 0; + REG_NOTES (i2) = 0; + + if (newi2pat) + { + INSN_CODE (i2) = i2_code_number; + PATTERN (i2) = newi2pat; + } + else + { + PUT_CODE (i2, NOTE); + NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (i2) = 0; + } + + if (i1) + { + LOG_LINKS (i1) = 0; + REG_NOTES (i1) = 0; + PUT_CODE (i1, NOTE); + NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (i1) = 0; + } + + /* Get death notes for everything that is now used in either I3 or + I2 and used to die in a previous insn. */ + + move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes); + if (newi2pat) + move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes); + + /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ + if (i3notes) + distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX, + elim_i2, elim_i1); + if (i2notes) + distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX, + elim_i2, elim_i1); + if (i1notes) + distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX, + elim_i2, elim_i1); + if (midnotes) + distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, + elim_i2, elim_i1); + + /* Distribute any notes added to I2 or I3 by recog_for_combine. We + know these are REG_UNUSED and want them to go to the desired insn, + so we always pass it as i3. We have not counted the notes in + reg_n_deaths yet, so we need to do so now. */ + + if (newi2pat && new_i2_notes) + { + for (temp = new_i2_notes; temp; temp = XEXP (temp, 1)) + if (GET_CODE (XEXP (temp, 0)) == REG) + reg_n_deaths[REGNO (XEXP (temp, 0))]++; + + distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX); + } + + if (new_i3_notes) + { + for (temp = new_i3_notes; temp; temp = XEXP (temp, 1)) + if (GET_CODE (XEXP (temp, 0)) == REG) + reg_n_deaths[REGNO (XEXP (temp, 0))]++; + + distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX); + } + + /* If I3DEST was used in I3SRC, it really died in I3. We may need to + put a REG_DEAD note for it somewhere. Similarly for I2 and I1. + Show an additional death due to the REG_DEAD note we make here. If + we discard it in distribute_notes, we will decrement it again. */ + + if (i3dest_killed) + { + if (GET_CODE (i3dest_killed) == REG) + reg_n_deaths[REGNO (i3dest_killed)]++; + + distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed, + NULL_RTX), + NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, + NULL_RTX, NULL_RTX); + } + + /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets + I2DEST or I1DEST, the death must be somewhere before I2, not I3. If + we passed I3 in that case, it might delete I2. */ + + if (i2dest_in_i2src) + { + if (GET_CODE (i2dest) == REG) + reg_n_deaths[REGNO (i2dest)]++; + + if (newi2pat && reg_set_p (i2dest, newi2pat)) + distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX), + NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); + else + distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX), + NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, + NULL_RTX, NULL_RTX); + } + + if (i1dest_in_i1src) + { + if (GET_CODE (i1dest) == REG) + reg_n_deaths[REGNO (i1dest)]++; + + if (newi2pat && reg_set_p (i1dest, newi2pat)) + distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX), + NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); + else + distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX), + NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, + NULL_RTX, NULL_RTX); + } + + distribute_links (i3links); + distribute_links (i2links); + distribute_links (i1links); + + if (GET_CODE (i2dest) == REG) + { + rtx link; + rtx i2_insn = 0, i2_val = 0, set; + + /* The insn that used to set this register doesn't exist, and + this life of the register may not exist either. See if one of + I3's links points to an insn that sets I2DEST. If it does, + that is now the last known value for I2DEST. If we don't update + this and I2 set the register to a value that depended on its old + contents, we will get confused. If this insn is used, thing + will be set correctly in combine_instructions. */ + + for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) + if ((set = single_set (XEXP (link, 0))) != 0 + && rtx_equal_p (i2dest, SET_DEST (set))) + i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); + + record_value_for_reg (i2dest, i2_insn, i2_val); + + /* If the reg formerly set in I2 died only once and that was in I3, + zero its use count so it won't make `reload' do any work. */ + if (! added_sets_2 && newi2pat == 0) + { + regno = REGNO (i2dest); + reg_n_sets[regno]--; + if (reg_n_sets[regno] == 0 + && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS)))) + reg_n_refs[regno] = 0; + } + } + + if (i1 && GET_CODE (i1dest) == REG) + { + rtx link; + rtx i1_insn = 0, i1_val = 0, set; + + for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) + if ((set = single_set (XEXP (link, 0))) != 0 + && rtx_equal_p (i1dest, SET_DEST (set))) + i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); + + record_value_for_reg (i1dest, i1_insn, i1_val); + + regno = REGNO (i1dest); + if (! added_sets_1) + { + reg_n_sets[regno]--; + if (reg_n_sets[regno] == 0 + && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS)))) + reg_n_refs[regno] = 0; + } + } + + /* Update reg_nonzero_bits et al for any changes that may have been made + to this insn. */ + + note_stores (newpat, set_nonzero_bits_and_sign_copies); + if (newi2pat) + note_stores (newi2pat, set_nonzero_bits_and_sign_copies); + + /* If I3 is now an unconditional jump, ensure that it has a + BARRIER following it since it may have initially been a + conditional jump. It may also be the last nonnote insn. */ + + if ((GET_CODE (newpat) == RETURN || simplejump_p (i3)) + && ((temp = next_nonnote_insn (i3)) == NULL_RTX + || GET_CODE (temp) != BARRIER)) + emit_barrier_after (i3); + } + + combine_successes++; + + return newi2pat ? i2 : i3; +} + +/* Undo all the modifications recorded in undobuf. */ + +static void +undo_all () +{ + register int i; + if (undobuf.num_undo > MAX_UNDO) + undobuf.num_undo = MAX_UNDO; + for (i = undobuf.num_undo - 1; i >= 0; i--) + { + if (undobuf.undo[i].is_int) + *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i; + else + *undobuf.undo[i].where.rtx = undobuf.undo[i].old_contents.rtx; + + } + + obfree (undobuf.storage); + undobuf.num_undo = 0; +} + +/* Find the innermost point within the rtx at LOC, possibly LOC itself, + where we have an arithmetic expression and return that point. LOC will + be inside INSN. + + try_combine will call this function to see if an insn can be split into + two insns. */ + +static rtx * +find_split_point (loc, insn) + rtx *loc; + rtx insn; +{ + rtx x = *loc; + enum rtx_code code = GET_CODE (x); + rtx *split; + int len = 0, pos, unsignedp; + rtx inner; + + /* First special-case some codes. */ + switch (code) + { + case SUBREG: +#ifdef INSN_SCHEDULING + /* If we are making a paradoxical SUBREG invalid, it becomes a split + point. */ + if (GET_CODE (SUBREG_REG (x)) == MEM) + return loc; +#endif + return find_split_point (&SUBREG_REG (x), insn); + + case MEM: +#ifdef HAVE_lo_sum + /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it + using LO_SUM and HIGH. */ + if (GET_CODE (XEXP (x, 0)) == CONST + || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) + { + SUBST (XEXP (x, 0), + gen_rtx_combine (LO_SUM, Pmode, + gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)), + XEXP (x, 0))); + return &XEXP (XEXP (x, 0), 0); + } +#endif + + /* If we have a PLUS whose second operand is a constant and the + address is not valid, perhaps will can split it up using + the machine-specific way to split large constants. We use + the first psuedo-reg (one of the virtual regs) as a placeholder; + it will not remain in the result. */ + if (GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) + { + rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; + rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)), + subst_insn); + + /* This should have produced two insns, each of which sets our + placeholder. If the source of the second is a valid address, + we can make put both sources together and make a split point + in the middle. */ + + if (seq && XVECLEN (seq, 0) == 2 + && GET_CODE (XVECEXP (seq, 0, 0)) == INSN + && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET + && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg + && ! reg_mentioned_p (reg, + SET_SRC (PATTERN (XVECEXP (seq, 0, 0)))) + && GET_CODE (XVECEXP (seq, 0, 1)) == INSN + && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET + && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg + && memory_address_p (GET_MODE (x), + SET_SRC (PATTERN (XVECEXP (seq, 0, 1))))) + { + rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0))); + rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1))); + + /* Replace the placeholder in SRC2 with SRC1. If we can + find where in SRC2 it was placed, that can become our + split point and we can replace this address with SRC2. + Just try two obvious places. */ + + src2 = replace_rtx (src2, reg, src1); + split = 0; + if (XEXP (src2, 0) == src1) + split = &XEXP (src2, 0); + else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' + && XEXP (XEXP (src2, 0), 0) == src1) + split = &XEXP (XEXP (src2, 0), 0); + + if (split) + { + SUBST (XEXP (x, 0), src2); + return split; + } + } + + /* If that didn't work, perhaps the first operand is complex and + needs to be computed separately, so make a split point there. + This will occur on machines that just support REG + CONST + and have a constant moved through some previous computation. */ + + else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o' + && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG + && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0)))) + == 'o'))) + return &XEXP (XEXP (x, 0), 0); + } + break; + + case SET: +#ifdef HAVE_cc0 + /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a + ZERO_EXTRACT, the most likely reason why this doesn't match is that + we need to put the operand into a register. So split at that + point. */ + + if (SET_DEST (x) == cc0_rtx + && GET_CODE (SET_SRC (x)) != COMPARE + && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT + && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o' + && ! (GET_CODE (SET_SRC (x)) == SUBREG + && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o')) + return &SET_SRC (x); +#endif + + /* See if we can split SET_SRC as it stands. */ + split = find_split_point (&SET_SRC (x), insn); + if (split && split != &SET_SRC (x)) + return split; + + /* See if this is a bitfield assignment with everything constant. If + so, this is an IOR of an AND, so split it into that. */ + if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT + && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) + <= HOST_BITS_PER_WIDE_INT) + && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT + && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT + && GET_CODE (SET_SRC (x)) == CONST_INT + && ((INTVAL (XEXP (SET_DEST (x), 1)) + + INTVAL (XEXP (SET_DEST (x), 2))) + <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) + && ! side_effects_p (XEXP (SET_DEST (x), 0))) + { + int pos = INTVAL (XEXP (SET_DEST (x), 2)); + int len = INTVAL (XEXP (SET_DEST (x), 1)); + int src = INTVAL (SET_SRC (x)); + rtx dest = XEXP (SET_DEST (x), 0); + enum machine_mode mode = GET_MODE (dest); + unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; + +#if BITS_BIG_ENDIAN + pos = GET_MODE_BITSIZE (mode) - len - pos; +#endif + + if (src == mask) + SUBST (SET_SRC (x), + gen_binary (IOR, mode, dest, GEN_INT (src << pos))); + else + SUBST (SET_SRC (x), + gen_binary (IOR, mode, + gen_binary (AND, mode, dest, + GEN_INT (~ (mask << pos) + & GET_MODE_MASK (mode))), + GEN_INT (src << pos))); + + SUBST (SET_DEST (x), dest); + + split = find_split_point (&SET_SRC (x), insn); + if (split && split != &SET_SRC (x)) + return split; + } + + /* Otherwise, see if this is an operation that we can split into two. + If so, try to split that. */ + code = GET_CODE (SET_SRC (x)); + + switch (code) + { + case AND: + /* If we are AND'ing with a large constant that is only a single + bit and the result is only being used in a context where we + need to know if it is zero or non-zero, replace it with a bit + extraction. This will avoid the large constant, which might + have taken more than one insn to make. If the constant were + not a valid argument to the AND but took only one insn to make, + this is no worse, but if it took more than one insn, it will + be better. */ + + if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT + && GET_CODE (XEXP (SET_SRC (x), 0)) == REG + && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 + && GET_CODE (SET_DEST (x)) == REG + && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0 + && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) + && XEXP (*split, 0) == SET_DEST (x) + && XEXP (*split, 1) == const0_rtx) + { + SUBST (SET_SRC (x), + make_extraction (GET_MODE (SET_DEST (x)), + XEXP (SET_SRC (x), 0), + pos, NULL_RTX, 1, 1, 0, 0)); + return find_split_point (loc, insn); + } + break; + + case SIGN_EXTEND: + inner = XEXP (SET_SRC (x), 0); + pos = 0; + len = GET_MODE_BITSIZE (GET_MODE (inner)); + unsignedp = 0; + break; + + case SIGN_EXTRACT: + case ZERO_EXTRACT: + if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT + && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) + { + inner = XEXP (SET_SRC (x), 0); + len = INTVAL (XEXP (SET_SRC (x), 1)); + pos = INTVAL (XEXP (SET_SRC (x), 2)); + +#if BITS_BIG_ENDIAN + pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; +#endif + unsignedp = (code == ZERO_EXTRACT); + } + break; + } + + if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) + { + enum machine_mode mode = GET_MODE (SET_SRC (x)); + + /* For unsigned, we have a choice of a shift followed by an + AND or two shifts. Use two shifts for field sizes where the + constant might be too large. We assume here that we can + always at least get 8-bit constants in an AND insn, which is + true for every current RISC. */ + + if (unsignedp && len <= 8) + { + SUBST (SET_SRC (x), + gen_rtx_combine + (AND, mode, + gen_rtx_combine (LSHIFTRT, mode, + gen_lowpart_for_combine (mode, inner), + GEN_INT (pos)), + GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); + + split = find_split_point (&SET_SRC (x), insn); + if (split && split != &SET_SRC (x)) + return split; + } + else + { + SUBST (SET_SRC (x), + gen_rtx_combine + (unsignedp ? LSHIFTRT : ASHIFTRT, mode, + gen_rtx_combine (ASHIFT, mode, + gen_lowpart_for_combine (mode, inner), + GEN_INT (GET_MODE_BITSIZE (mode) + - len - pos)), + GEN_INT (GET_MODE_BITSIZE (mode) - len))); + + split = find_split_point (&SET_SRC (x), insn); + if (split && split != &SET_SRC (x)) + return split; + } + } + + /* See if this is a simple operation with a constant as the second + operand. It might be that this constant is out of range and hence + could be used as a split point. */ + if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' + || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' + || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<') + && CONSTANT_P (XEXP (SET_SRC (x), 1)) + && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o' + || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG + && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0)))) + == 'o')))) + return &XEXP (SET_SRC (x), 1); + + /* Finally, see if this is a simple operation with its first operand + not in a register. The operation might require this operand in a + register, so return it as a split point. We can always do this + because if the first operand were another operation, we would have + already found it as a split point. */ + if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' + || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' + || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<' + || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1') + && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) + return &XEXP (SET_SRC (x), 0); + + return 0; + + case AND: + case IOR: + /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, + it is better to write this as (not (ior A B)) so we can split it. + Similarly for IOR. */ + if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) + { + SUBST (*loc, + gen_rtx_combine (NOT, GET_MODE (x), + gen_rtx_combine (code == IOR ? AND : IOR, + GET_MODE (x), + XEXP (XEXP (x, 0), 0), + XEXP (XEXP (x, 1), 0)))); + return find_split_point (loc, insn); + } + + /* Many RISC machines have a large set of logical insns. If the + second operand is a NOT, put it first so we will try to split the + other operand first. */ + if (GET_CODE (XEXP (x, 1)) == NOT) + { + rtx tem = XEXP (x, 0); + SUBST (XEXP (x, 0), XEXP (x, 1)); + SUBST (XEXP (x, 1), tem); + } + break; + } + + /* Otherwise, select our actions depending on our rtx class. */ + switch (GET_RTX_CLASS (code)) + { + case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ + case '3': + split = find_split_point (&XEXP (x, 2), insn); + if (split) + return split; + /* ... fall through ... */ + case '2': + case 'c': + case '<': + split = find_split_point (&XEXP (x, 1), insn); + if (split) + return split; + /* ... fall through ... */ + case '1': + /* Some machines have (and (shift ...) ...) insns. If X is not + an AND, but XEXP (X, 0) is, use it as our split point. */ + if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) + return &XEXP (x, 0); + + split = find_split_point (&XEXP (x, 0), insn); + if (split) + return split; + return loc; + } + + /* Otherwise, we don't have a split point. */ + return 0; +} + +/* Throughout X, replace FROM with TO, and return the result. + The result is TO if X is FROM; + otherwise the result is X, but its contents may have been modified. + If they were modified, a record was made in undobuf so that + undo_all will (among other things) return X to its original state. + + If the number of changes necessary is too much to record to undo, + the excess changes are not made, so the result is invalid. + The changes already made can still be undone. + undobuf.num_undo is incremented for such changes, so by testing that + the caller can tell whether the result is valid. + + `n_occurrences' is incremented each time FROM is replaced. + + IN_DEST is non-zero if we are processing the SET_DEST of a SET. + + UNIQUE_COPY is non-zero if each substitution must be unique. We do this + by copying if `n_occurrences' is non-zero. */ + +static rtx +subst (x, from, to, in_dest, unique_copy) + register rtx x, from, to; + int in_dest; + int unique_copy; +{ + register char *fmt; + register int len, i; + register enum rtx_code code = GET_CODE (x), orig_code = code; + rtx temp; + enum machine_mode mode = GET_MODE (x); + enum machine_mode op0_mode = VOIDmode; + rtx other_insn; + rtx *cc_use; + int n_restarts = 0; + +/* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe + replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM). + If it is 0, that cannot be done. We can now do this for any MEM + because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded. + If not for that, MEM's would very rarely be safe. */ + +/* Reject MODEs bigger than a word, because we might not be able + to reference a two-register group starting with an arbitrary register + (and currently gen_lowpart might crash for a SUBREG). */ + +#define FAKE_EXTEND_SAFE_P(MODE, FROM) \ + (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) + +/* Two expressions are equal if they are identical copies of a shared + RTX or if they are both registers with the same register number + and mode. */ + +#define COMBINE_RTX_EQUAL_P(X,Y) \ + ((X) == (Y) \ + || (GET_CODE (X) == REG && GET_CODE (Y) == REG \ + && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) + + if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) + { + n_occurrences++; + return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); + } + + /* If X and FROM are the same register but different modes, they will + not have been seen as equal above. However, flow.c will make a + LOG_LINKS entry for that case. If we do nothing, we will try to + rerecognize our original insn and, when it succeeds, we will + delete the feeding insn, which is incorrect. + + So force this insn not to match in this (rare) case. */ + if (! in_dest && code == REG && GET_CODE (from) == REG + && REGNO (x) == REGNO (from)) + return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); + + /* If this is an object, we are done unless it is a MEM or LO_SUM, both + of which may contain things that can be combined. */ + if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o') + return x; + + /* It is possible to have a subexpression appear twice in the insn. + Suppose that FROM is a register that appears within TO. + Then, after that subexpression has been scanned once by `subst', + the second time it is scanned, TO may be found. If we were + to scan TO here, we would find FROM within it and create a + self-referent rtl structure which is completely wrong. */ + if (COMBINE_RTX_EQUAL_P (x, to)) + return to; + + len = GET_RTX_LENGTH (code); + fmt = GET_RTX_FORMAT (code); + + /* We don't need to process a SET_DEST that is a register, CC0, or PC, so + set up to skip this common case. All other cases where we want to + suppress replacing something inside a SET_SRC are handled via the + IN_DEST operand. */ + if (code == SET + && (GET_CODE (SET_DEST (x)) == REG + || GET_CODE (SET_DEST (x)) == CC0 + || GET_CODE (SET_DEST (x)) == PC)) + fmt = "ie"; + + /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */ + if (fmt[0] == 'e') + op0_mode = GET_MODE (XEXP (x, 0)); + + for (i = 0; i < len; i++) + { + if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + { + register rtx new; + if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) + { + new = (unique_copy && n_occurrences ? copy_rtx (to) : to); + n_occurrences++; + } + else + { + new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy); + + /* If this substitution failed, this whole thing fails. */ + if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) + return new; + } + + SUBST (XVECEXP (x, i, j), new); + } + } + else if (fmt[i] == 'e') + { + register rtx new; + + if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) + { + new = (unique_copy && n_occurrences ? copy_rtx (to) : to); + n_occurrences++; + } + else + /* If we are in a SET_DEST, suppress most cases unless we + have gone inside a MEM, in which case we want to + simplify the address. We assume here that things that + are actually part of the destination have their inner + parts in the first expression. This is true for SUBREG, + STRICT_LOW_PART, and ZERO_EXTRACT, which are the only + things aside from REG and MEM that should appear in a + SET_DEST. */ + new = subst (XEXP (x, i), from, to, + (((in_dest + && (code == SUBREG || code == STRICT_LOW_PART + || code == ZERO_EXTRACT)) + || code == SET) + && i == 0), unique_copy); + + /* If we found that we will have to reject this combination, + indicate that by returning the CLOBBER ourselves, rather than + an expression containing it. This will speed things up as + well as prevent accidents where two CLOBBERs are considered + to be equal, thus producing an incorrect simplification. */ + + if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) + return new; + + SUBST (XEXP (x, i), new); + } + } + + /* We come back to here if we have replaced the expression with one of + a different code and it is likely that further simplification will be + possible. */ + + restart: + + /* If we have restarted more than 4 times, we are probably looping, so + give up. */ + if (++n_restarts > 4) + return x; + + /* If we are restarting at all, it means that we no longer know the + original mode of operand 0 (since we have probably changed the + form of X). */ + + if (n_restarts > 1) + op0_mode = VOIDmode; + + code = GET_CODE (x); + + /* If this is a commutative operation, put a constant last and a complex + expression first. We don't need to do this for comparisons here. */ + if (GET_RTX_CLASS (code) == 'c' + && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT) + || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o' + && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o') + || (GET_CODE (XEXP (x, 0)) == SUBREG + && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o' + && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'))) + { + temp = XEXP (x, 0); + SUBST (XEXP (x, 0), XEXP (x, 1)); + SUBST (XEXP (x, 1), temp); + } + + /* If this is a PLUS, MINUS, or MULT, and the first operand is the + sign extension of a PLUS with a constant, reverse the order of the sign + extension and the addition. Note that this not the same as the original + code, but overflow is undefined for signed values. Also note that the + PLUS will have been partially moved "inside" the sign-extension, so that + the first operand of X will really look like: + (ashiftrt (plus (ashift A C4) C5) C4). + We convert this to + (plus (ashiftrt (ashift A C4) C2) C4) + and replace the first operand of X with that expression. Later parts + of this function may simplify the expression further. + + For example, if we start with (mult (sign_extend (plus A C1)) C2), + we swap the SIGN_EXTEND and PLUS. Later code will apply the + distributive law to produce (plus (mult (sign_extend X) C1) C3). + + We do this to simplify address expressions. */ + + if ((code == PLUS || code == MINUS || code == MULT) + && GET_CODE (XEXP (x, 0)) == ASHIFTRT + && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS + && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT + && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1) + && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT + && (temp = simplify_binary_operation (ASHIFTRT, mode, + XEXP (XEXP (XEXP (x, 0), 0), 1), + XEXP (XEXP (x, 0), 1))) != 0) + { + rtx new + = simplify_shift_const (NULL_RTX, ASHIFT, mode, + XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0), + INTVAL (XEXP (XEXP (x, 0), 1))); + + new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new, + INTVAL (XEXP (XEXP (x, 0), 1))); + + SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp)); + } + + /* If this is a simple operation applied to an IF_THEN_ELSE, try + applying it to the arms of the IF_THEN_ELSE. This often simplifies + things. Don't deal with operations that change modes here. */ + + if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c') + && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE) + { + /* Don't do this by using SUBST inside X since we might be messing + up a shared expression. */ + rtx cond = XEXP (XEXP (x, 0), 0); + rtx t_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 1), + XEXP (x, 1)), + pc_rtx, pc_rtx, 0, 0); + rtx f_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 2), + XEXP (x, 1)), + pc_rtx, pc_rtx, 0, 0); + + + x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm); + goto restart; + } + + else if (GET_RTX_CLASS (code) == '1' + && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE + && GET_MODE (XEXP (x, 0)) == mode) + { + rtx cond = XEXP (XEXP (x, 0), 0); + rtx t_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 1)), + pc_rtx, pc_rtx, 0, 0); + rtx f_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 2)), + pc_rtx, pc_rtx, 0, 0); + + x = gen_rtx_combine (IF_THEN_ELSE, mode, cond, t_arm, f_arm); + goto restart; + } + + /* Try to fold this expression in case we have constants that weren't + present before. */ + temp = 0; + switch (GET_RTX_CLASS (code)) + { + case '1': + temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); + break; + case '<': + temp = simplify_relational_operation (code, op0_mode, + XEXP (x, 0), XEXP (x, 1)); +#ifdef FLOAT_STORE_FLAG_VALUE + if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) + temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x)) + : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x))); +#endif + break; + case 'c': + case '2': + temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); + break; + case 'b': + case '3': + temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), + XEXP (x, 1), XEXP (x, 2)); + break; + } + + if (temp) + x = temp, code = GET_CODE (temp); + + /* First see if we can apply the inverse distributive law. */ + if (code == PLUS || code == MINUS || code == IOR || code == XOR) + { + x = apply_distributive_law (x); + code = GET_CODE (x); + } + + /* If CODE is an associative operation not otherwise handled, see if we + can associate some operands. This can win if they are constants or + if they are logically related (i.e. (a & b) & a. */ + if ((code == PLUS || code == MINUS + || code == MULT || code == AND || code == IOR || code == XOR + || code == DIV || code == UDIV + || code == SMAX || code == SMIN || code == UMAX || code == UMIN) + && GET_MODE_CLASS (mode) == MODE_INT) + { + if (GET_CODE (XEXP (x, 0)) == code) + { + rtx other = XEXP (XEXP (x, 0), 0); + rtx inner_op0 = XEXP (XEXP (x, 0), 1); + rtx inner_op1 = XEXP (x, 1); + rtx inner; + + /* Make sure we pass the constant operand if any as the second + one if this is a commutative operation. */ + if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c') + { + rtx tem = inner_op0; + inner_op0 = inner_op1; + inner_op1 = tem; + } + inner = simplify_binary_operation (code == MINUS ? PLUS + : code == DIV ? MULT + : code == UDIV ? MULT + : code, + mode, inner_op0, inner_op1); + + /* For commutative operations, try the other pair if that one + didn't simplify. */ + if (inner == 0 && GET_RTX_CLASS (code) == 'c') + { + other = XEXP (XEXP (x, 0), 1); + inner = simplify_binary_operation (code, mode, + XEXP (XEXP (x, 0), 0), + XEXP (x, 1)); + } + + if (inner) + { + x = gen_binary (code, mode, other, inner); + goto restart; + + } + } + } + + /* A little bit of algebraic simplification here. */ + switch (code) + { + case MEM: + /* Ensure that our address has any ASHIFTs converted to MULT in case + address-recognizing predicates are called later. */ + temp = make_compound_operation (XEXP (x, 0), MEM); + SUBST (XEXP (x, 0), temp); + break; + + case SUBREG: + /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG + is paradoxical. If we can't do that safely, then it becomes + something nonsensical so that this combination won't take place. */ + + if (GET_CODE (SUBREG_REG (x)) == MEM + && (GET_MODE_SIZE (mode) + <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) + { + rtx inner = SUBREG_REG (x); + int endian_offset = 0; + /* Don't change the mode of the MEM + if that would change the meaning of the address. */ + if (MEM_VOLATILE_P (SUBREG_REG (x)) + || mode_dependent_address_p (XEXP (inner, 0))) + return gen_rtx (CLOBBER, mode, const0_rtx); + +#if BYTES_BIG_ENDIAN + if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) + endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode); + if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD) + endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner)); +#endif + /* Note if the plus_constant doesn't make a valid address + then this combination won't be accepted. */ + x = gen_rtx (MEM, mode, + plus_constant (XEXP (inner, 0), + (SUBREG_WORD (x) * UNITS_PER_WORD + + endian_offset))); + MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner); + RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner); + MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner); + return x; + } + + /* If we are in a SET_DEST, these other cases can't apply. */ + if (in_dest) + return x; + + /* Changing mode twice with SUBREG => just change it once, + or not at all if changing back to starting mode. */ + if (GET_CODE (SUBREG_REG (x)) == SUBREG) + { + if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x))) + && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0) + return SUBREG_REG (SUBREG_REG (x)); + + SUBST_INT (SUBREG_WORD (x), + SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x))); + SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x))); + } + + /* SUBREG of a hard register => just change the register number + and/or mode. If the hard register is not valid in that mode, + suppress this combination. If the hard register is the stack, + frame, or argument pointer, leave this as a SUBREG. */ + + if (GET_CODE (SUBREG_REG (x)) == REG + && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER + && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM +#endif + && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM) + { + if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x), + mode)) + return gen_rtx (REG, mode, + REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)); + else + return gen_rtx (CLOBBER, mode, const0_rtx); + } + + /* For a constant, try to pick up the part we want. Handle a full + word and low-order part. Only do this if we are narrowing + the constant; if it is being widened, we have no idea what + the extra bits will have been set to. */ + + if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode + && GET_MODE_SIZE (mode) == UNITS_PER_WORD + && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD + && GET_MODE_CLASS (mode) == MODE_INT) + { + temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x), + 0, op0_mode); + if (temp) + return temp; + } + + /* If we want a subreg of a constant, at offset 0, + take the low bits. On a little-endian machine, that's + always valid. On a big-endian machine, it's valid + only if the constant's mode fits in one word. */ + if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x) + && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode) +#if WORDS_BIG_ENDIAN + && GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD +#endif + ) + return gen_lowpart_for_combine (mode, SUBREG_REG (x)); + + /* If we are narrowing the object, we need to see if we can simplify + the expression for the object knowing that we only need the + low-order bits. */ + + if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) + && subreg_lowpart_p (x)) + return force_to_mode (SUBREG_REG (x), mode, GET_MODE_BITSIZE (mode), + NULL_RTX); + break; + + case NOT: + /* (not (plus X -1)) can become (neg X). */ + if (GET_CODE (XEXP (x, 0)) == PLUS + && XEXP (XEXP (x, 0), 1) == constm1_rtx) + { + x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0)); + goto restart; + } + + /* Similarly, (not (neg X)) is (plus X -1). */ + if (GET_CODE (XEXP (x, 0)) == NEG) + { + x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx); + goto restart; + } + + /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */ + if (GET_CODE (XEXP (x, 0)) == XOR + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && (temp = simplify_unary_operation (NOT, mode, + XEXP (XEXP (x, 0), 1), + mode)) != 0) + { + SUBST (XEXP (XEXP (x, 0), 1), temp); + return XEXP (x, 0); + } + + /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands + other than 1, but that is not valid. We could do a similar + simplification for (not (lshiftrt C X)) where C is just the sign bit, + but this doesn't seem common enough to bother with. */ + if (GET_CODE (XEXP (x, 0)) == ASHIFT + && XEXP (XEXP (x, 0), 0) == const1_rtx) + { + x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx), + XEXP (XEXP (x, 0), 1)); + goto restart; + } + + if (GET_CODE (XEXP (x, 0)) == SUBREG + && subreg_lowpart_p (XEXP (x, 0)) + && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) + < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0))))) + && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT + && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx) + { + enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0))); + + x = gen_rtx (ROTATE, inner_mode, + gen_unary (NOT, inner_mode, const1_rtx), + XEXP (SUBREG_REG (XEXP (x, 0)), 1)); + x = gen_lowpart_for_combine (mode, x); + goto restart; + } + +#if STORE_FLAG_VALUE == -1 + /* (not (comparison foo bar)) can be done by reversing the comparison + code if valid. */ + if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' + && reversible_comparison_p (XEXP (x, 0))) + return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))), + mode, XEXP (XEXP (x, 0), 0), + XEXP (XEXP (x, 0), 1)); + + /* (ashiftrt foo C) where C is the number of bits in FOO minus 1 + is (lt foo (const_int 0)), so we can perform the above + simplification. */ + + if (XEXP (x, 1) == const1_rtx + && GET_CODE (XEXP (x, 0)) == ASHIFTRT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1) + return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx); +#endif + + /* Apply De Morgan's laws to reduce number of patterns for machines + with negating logical insns (and-not, nand, etc.). If result has + only one NOT, put it first, since that is how the patterns are + coded. */ + + if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND) + { + rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1); + + if (GET_CODE (in1) == NOT) + in1 = XEXP (in1, 0); + else + in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1); + + if (GET_CODE (in2) == NOT) + in2 = XEXP (in2, 0); + else if (GET_CODE (in2) == CONST_INT + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) + in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2)); + else + in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2); + + if (GET_CODE (in2) == NOT) + { + rtx tem = in2; + in2 = in1; in1 = tem; + } + + x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR, + mode, in1, in2); + goto restart; + } + break; + + case NEG: + /* (neg (plus X 1)) can become (not X). */ + if (GET_CODE (XEXP (x, 0)) == PLUS + && XEXP (XEXP (x, 0), 1) == const1_rtx) + { + x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0)); + goto restart; + } + + /* Similarly, (neg (not X)) is (plus X 1). */ + if (GET_CODE (XEXP (x, 0)) == NOT) + { + x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx); + goto restart; + } + + /* (neg (minus X Y)) can become (minus Y X). */ + if (GET_CODE (XEXP (x, 0)) == MINUS + && (GET_MODE_CLASS (mode) != MODE_FLOAT + /* x-y != -(y-x) with IEEE floating point. */ + || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT)) + { + x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1), + XEXP (XEXP (x, 0), 0)); + goto restart; + } + + /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */ + if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx + && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1) + { + x = gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx); + goto restart; + } + + /* NEG commutes with ASHIFT since it is multiplication. Only do this + if we can then eliminate the NEG (e.g., + if the operand is a constant). */ + + if (GET_CODE (XEXP (x, 0)) == ASHIFT) + { + temp = simplify_unary_operation (NEG, mode, + XEXP (XEXP (x, 0), 0), mode); + if (temp) + { + SUBST (XEXP (XEXP (x, 0), 0), temp); + return XEXP (x, 0); + } + } + + temp = expand_compound_operation (XEXP (x, 0)); + + /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be + replaced by (lshiftrt X C). This will convert + (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ + + if (GET_CODE (temp) == ASHIFTRT + && GET_CODE (XEXP (temp, 1)) == CONST_INT + && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) + { + x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0), + INTVAL (XEXP (temp, 1))); + goto restart; + } + + /* If X has only a single bit that might be nonzero, say, bit I, convert + (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of + MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to + (sign_extract X 1 Y). But only do this if TEMP isn't a register + or a SUBREG of one since we'd be making the expression more + complex if it was just a register. */ + + if (GET_CODE (temp) != REG + && ! (GET_CODE (temp) == SUBREG + && GET_CODE (SUBREG_REG (temp)) == REG) + && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) + { + rtx temp1 = simplify_shift_const + (NULL_RTX, ASHIFTRT, mode, + simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, + GET_MODE_BITSIZE (mode) - 1 - i), + GET_MODE_BITSIZE (mode) - 1 - i); + + /* If all we did was surround TEMP with the two shifts, we + haven't improved anything, so don't use it. Otherwise, + we are better off with TEMP1. */ + if (GET_CODE (temp1) != ASHIFTRT + || GET_CODE (XEXP (temp1, 0)) != ASHIFT + || XEXP (XEXP (temp1, 0), 0) != temp) + { + x = temp1; + goto restart; + } + } + break; + + case FLOAT_TRUNCATE: + /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */ + if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND + && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) + return XEXP (XEXP (x, 0), 0); + break; + +#ifdef HAVE_cc0 + case COMPARE: + /* Convert (compare FOO (const_int 0)) to FOO unless we aren't + using cc0, in which case we want to leave it as a COMPARE + so we can distinguish it from a register-register-copy. */ + if (XEXP (x, 1) == const0_rtx) + return XEXP (x, 0); + + /* In IEEE floating point, x-0 is not the same as x. */ + if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT) + && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) + return XEXP (x, 0); + break; +#endif + + case CONST: + /* (const (const X)) can become (const X). Do it this way rather than + returning the inner CONST since CONST can be shared with a + REG_EQUAL note. */ + if (GET_CODE (XEXP (x, 0)) == CONST) + SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); + break; + +#ifdef HAVE_lo_sum + case LO_SUM: + /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we + can add in an offset. find_split_point will split this address up + again if it doesn't match. */ + if (GET_CODE (XEXP (x, 0)) == HIGH + && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) + return XEXP (x, 1); + break; +#endif + + case PLUS: + /* If we have (plus (plus (A const) B)), associate it so that CONST is + outermost. That's because that's the way indexed addresses are + supposed to appear. This code used to check many more cases, but + they are now checked elsewhere. */ + if (GET_CODE (XEXP (x, 0)) == PLUS + && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) + return gen_binary (PLUS, mode, + gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), + XEXP (x, 1)), + XEXP (XEXP (x, 0), 1)); + + /* (plus (xor (and (const_int pow2 - 1)) ) <-c>) + when c is (const_int (pow2 + 1) / 2) is a sign extension of a + bit-field and can be replaced by either a sign_extend or a + sign_extract. The `and' may be a zero_extend. */ + if (GET_CODE (XEXP (x, 0)) == XOR + && GET_CODE (XEXP (x, 1)) == CONST_INT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1)) + && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND + && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT + && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) + == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) + || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND + && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) + == i + 1)))) + { + x = simplify_shift_const + (NULL_RTX, ASHIFTRT, mode, + simplify_shift_const (NULL_RTX, ASHIFT, mode, + XEXP (XEXP (XEXP (x, 0), 0), 0), + GET_MODE_BITSIZE (mode) - (i + 1)), + GET_MODE_BITSIZE (mode) - (i + 1)); + goto restart; + } + + /* If only the low-order bit of X is possible nonzero, (plus x -1) + can become (ashiftrt (ashift (xor x 1) C) C) where C is + the bitsize of the mode - 1. This allows simplification of + "a = (b & 8) == 0;" */ + if (XEXP (x, 1) == constm1_rtx + && GET_CODE (XEXP (x, 0)) != REG + && ! (GET_CODE (XEXP (x,0)) == SUBREG + && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG) + && nonzero_bits (XEXP (x, 0), mode) == 1) + { + x = simplify_shift_const + (NULL_RTX, ASHIFTRT, mode, + simplify_shift_const (NULL_RTX, ASHIFT, mode, + gen_rtx_combine (XOR, mode, + XEXP (x, 0), const1_rtx), + GET_MODE_BITSIZE (mode) - 1), + GET_MODE_BITSIZE (mode) - 1); + goto restart; + } + + /* If we are adding two things that have no bits in common, convert + the addition into an IOR. This will often be further simplified, + for example in cases like ((a & 1) + (a & 2)), which can + become a & 3. */ + + if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && (nonzero_bits (XEXP (x, 0), mode) + & nonzero_bits (XEXP (x, 1), mode)) == 0) + { + x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); + goto restart; + } + break; + + case MINUS: + /* (minus (and (const_int -pow2))) becomes + (and (const_int pow2-1)) */ + if (GET_CODE (XEXP (x, 1)) == AND + && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT + && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 + && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) + { + x = simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), + - INTVAL (XEXP (XEXP (x, 1), 1)) - 1); + goto restart; + } + break; + + case MULT: + /* If we have (mult (plus A B) C), apply the distributive law and then + the inverse distributive law to see if things simplify. This + occurs mostly in addresses, often when unrolling loops. */ + + if (GET_CODE (XEXP (x, 0)) == PLUS) + { + x = apply_distributive_law + (gen_binary (PLUS, mode, + gen_binary (MULT, mode, + XEXP (XEXP (x, 0), 0), XEXP (x, 1)), + gen_binary (MULT, mode, + XEXP (XEXP (x, 0), 1), XEXP (x, 1)))); + + if (GET_CODE (x) != MULT) + goto restart; + } + + /* If this is multiplication by a power of two and its first operand is + a shift, treat the multiply as a shift to allow the shifts to + possibly combine. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 + && (GET_CODE (XEXP (x, 0)) == ASHIFT + || GET_CODE (XEXP (x, 0)) == LSHIFTRT + || GET_CODE (XEXP (x, 0)) == ASHIFTRT + || GET_CODE (XEXP (x, 0)) == ROTATE + || GET_CODE (XEXP (x, 0)) == ROTATERT)) + { + x = simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i); + goto restart; + } + + /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */ + if (GET_CODE (XEXP (x, 0)) == ASHIFT + && XEXP (XEXP (x, 0), 0) == const1_rtx) + return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1), + XEXP (XEXP (x, 0), 1)); + break; + + case UDIV: + /* If this is a divide by a power of two, treat it as a shift if + its first operand is a shift. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 + && (GET_CODE (XEXP (x, 0)) == ASHIFT + || GET_CODE (XEXP (x, 0)) == LSHIFTRT + || GET_CODE (XEXP (x, 0)) == ASHIFTRT + || GET_CODE (XEXP (x, 0)) == ROTATE + || GET_CODE (XEXP (x, 0)) == ROTATERT)) + { + x = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); + goto restart; + } + break; + + case EQ: case NE: + case GT: case GTU: case GE: case GEU: + case LT: case LTU: case LE: case LEU: + /* If the first operand is a condition code, we can't do anything + with it. */ + if (GET_CODE (XEXP (x, 0)) == COMPARE + || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC +#ifdef HAVE_cc0 + && XEXP (x, 0) != cc0_rtx +#endif + )) + { + rtx op0 = XEXP (x, 0); + rtx op1 = XEXP (x, 1); + enum rtx_code new_code; + + if (GET_CODE (op0) == COMPARE) + op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); + + /* Simplify our comparison, if possible. */ + new_code = simplify_comparison (code, &op0, &op1); + +#if STORE_FLAG_VALUE == 1 + /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X + if only the low-order bit is possibly nonzero in X (such as when + X is a ZERO_EXTRACT of one bit. Similarly, we can convert + EQ to (xor X 1). Remove any ZERO_EXTRACT we made when thinking + this was a comparison. It may now be simpler to use, e.g., an + AND. If a ZERO_EXTRACT is indeed appropriate, it will + be placed back by the call to make_compound_operation in the + SET case. */ + if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT + && op1 == const0_rtx + && nonzero_bits (op0, GET_MODE (op0)) == 1) + return gen_lowpart_for_combine (mode, + expand_compound_operation (op0)); + else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT + && op1 == const0_rtx + && nonzero_bits (op0, GET_MODE (op0)) == 1) + { + op0 = expand_compound_operation (op0); + + x = gen_rtx_combine (XOR, mode, + gen_lowpart_for_combine (mode, op0), + const1_rtx); + goto restart; + } +#endif + +#if STORE_FLAG_VALUE == -1 + /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0) + to (neg x) if only the low-order bit of X can be nonzero. + This converts (ne (zero_extract X 1 Y) 0) to + (sign_extract X 1 Y). */ + if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT + && op1 == const0_rtx + && nonzero_bits (op0, GET_MODE (op0)) == 1) + { + op0 = expand_compound_operation (op0); + x = gen_rtx_combine (NEG, mode, + gen_lowpart_for_combine (mode, op0)); + goto restart; + } +#endif + + /* If STORE_FLAG_VALUE says to just test the sign bit and X has just + one bit that might be nonzero, we can convert (ne x 0) to + (ashift x c) where C puts the bit in the sign bit. Remove any + AND with STORE_FLAG_VALUE when we are done, since we are only + going to test the sign bit. */ + if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && (STORE_FLAG_VALUE + == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) + && op1 == const0_rtx + && mode == GET_MODE (op0) + && (i = exact_log2 (nonzero_bits (op0, GET_MODE (op0)))) >= 0) + { + x = simplify_shift_const (NULL_RTX, ASHIFT, mode, + expand_compound_operation (op0), + GET_MODE_BITSIZE (mode) - 1 - i); + if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) + return XEXP (x, 0); + else + return x; + } + + /* If the code changed, return a whole new comparison. */ + if (new_code != code) + return gen_rtx_combine (new_code, mode, op0, op1); + + /* Otherwise, keep this operation, but maybe change its operands. + This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ + SUBST (XEXP (x, 0), op0); + SUBST (XEXP (x, 1), op1); + } + break; + + case IF_THEN_ELSE: + /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register + used in it is being compared against certain values. Get the + true and false comparisons and see if that says anything about the + value of each arm. */ + + if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' + && reversible_comparison_p (XEXP (x, 0)) + && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG) + { + HOST_WIDE_INT nzb; + rtx from = XEXP (XEXP (x, 0), 0); + enum rtx_code true_code = GET_CODE (XEXP (x, 0)); + enum rtx_code false_code = reverse_condition (true_code); + rtx true_val = XEXP (XEXP (x, 0), 1); + rtx false_val = true_val; + rtx true_arm = XEXP (x, 1); + rtx false_arm = XEXP (x, 2); + int swapped = 0; + + /* If FALSE_CODE is EQ, swap the codes and arms. */ + + if (false_code == EQ) + { + swapped = 1, true_code = EQ, false_code = NE; + true_arm = XEXP (x, 2), false_arm = XEXP (x, 1); + } + + /* If we are comparing against zero and the expression being tested + has only a single bit that might be nonzero, that is its value + when it is not equal to zero. Similarly if it is known to be + -1 or 0. */ + + if (true_code == EQ && true_val == const0_rtx + && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) + false_code = EQ, false_val = GEN_INT (nzb); + else if (true_code == EQ && true_val == const0_rtx + && (num_sign_bit_copies (from, GET_MODE (from)) + == GET_MODE_BITSIZE (GET_MODE (from)))) + false_code = EQ, false_val = constm1_rtx; + + /* Now simplify an arm if we know the value of the register + in the branch and it is used in the arm. Be carefull due to + the potential of locally-shared RTL. */ + + if (reg_mentioned_p (from, true_arm)) + true_arm = subst (known_cond (copy_rtx (true_arm), true_code, + from, true_val), + pc_rtx, pc_rtx, 0, 0); + if (reg_mentioned_p (from, false_arm)) + false_arm = subst (known_cond (copy_rtx (false_arm), false_code, + from, false_val), + pc_rtx, pc_rtx, 0, 0); + + SUBST (XEXP (x, 1), swapped ? false_arm : true_arm); + SUBST (XEXP (x, 2), swapped ? true_arm : false_arm); + } + + /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be + reversed, do so to avoid needing two sets of patterns for + subtract-and-branch insns. Similarly if we have a constant in that + position or if the third operand is the same as the first operand + of the comparison. */ + + if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' + && reversible_comparison_p (XEXP (x, 0)) + && (XEXP (x, 1) == pc_rtx || GET_CODE (XEXP (x, 1)) == CONST_INT + || rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0)))) + { + SUBST (XEXP (x, 0), + gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))), + GET_MODE (XEXP (x, 0)), + XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1))); + + temp = XEXP (x, 1); + SUBST (XEXP (x, 1), XEXP (x, 2)); + SUBST (XEXP (x, 2), temp); + } + + /* If the two arms are identical, we don't need the comparison. */ + + if (rtx_equal_p (XEXP (x, 1), XEXP (x, 2)) + && ! side_effects_p (XEXP (x, 0))) + return XEXP (x, 1); + + /* Look for cases where we have (abs x) or (neg (abs X)). */ + + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_CODE (XEXP (x, 2)) == NEG + && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 2), 0)) + && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' + && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0)) + && ! side_effects_p (XEXP (x, 1))) + switch (GET_CODE (XEXP (x, 0))) + { + case GT: + case GE: + x = gen_unary (ABS, mode, XEXP (x, 1)); + goto restart; + case LT: + case LE: + x = gen_unary (NEG, mode, gen_unary (ABS, mode, XEXP (x, 1))); + goto restart; + } + + /* Look for MIN or MAX. */ + + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' + && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)) + && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 2)) + && ! side_effects_p (XEXP (x, 0))) + switch (GET_CODE (XEXP (x, 0))) + { + case GE: + case GT: + x = gen_binary (SMAX, mode, XEXP (x, 1), XEXP (x, 2)); + goto restart; + case LE: + case LT: + x = gen_binary (SMIN, mode, XEXP (x, 1), XEXP (x, 2)); + goto restart; + case GEU: + case GTU: + x = gen_binary (UMAX, mode, XEXP (x, 1), XEXP (x, 2)); + goto restart; + case LEU: + case LTU: + x = gen_binary (UMIN, mode, XEXP (x, 1), XEXP (x, 2)); + goto restart; + } + + /* If we have something like (if_then_else (ne A 0) (OP X C) X), + A is known to be either 0 or 1, and OP is an identity when its + second operand is zero, this can be done as (OP X (mult A C)). + Similarly if A is known to be 0 or -1 and also similarly if we have + a ZERO_EXTEND or SIGN_EXTEND as long as X is already extended (so + we don't destroy it). */ + + if (mode != VOIDmode + && (GET_CODE (XEXP (x, 0)) == EQ || GET_CODE (XEXP (x, 0)) == NE) + && XEXP (XEXP (x, 0), 1) == const0_rtx + && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1 + || (num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode) + == GET_MODE_BITSIZE (mode)))) + { + rtx nz = make_compound_operation (GET_CODE (XEXP (x, 0)) == NE + ? XEXP (x, 1) : XEXP (x, 2)); + rtx z = GET_CODE (XEXP (x, 0)) == NE ? XEXP (x, 2) : XEXP (x, 1); + rtx dir = (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1 + ? const1_rtx : constm1_rtx); + rtx c = 0; + enum machine_mode m = mode; + enum rtx_code op, extend_op = 0; + + if ((GET_CODE (nz) == PLUS || GET_CODE (nz) == MINUS + || GET_CODE (nz) == IOR || GET_CODE (nz) == XOR + || GET_CODE (nz) == ASHIFT + || GET_CODE (nz) == LSHIFTRT || GET_CODE (nz) == ASHIFTRT) + && rtx_equal_p (XEXP (nz, 0), z)) + c = XEXP (nz, 1), op = GET_CODE (nz); + else if (GET_CODE (nz) == SIGN_EXTEND + && (GET_CODE (XEXP (nz, 0)) == PLUS + || GET_CODE (XEXP (nz, 0)) == MINUS + || GET_CODE (XEXP (nz, 0)) == IOR + || GET_CODE (XEXP (nz, 0)) == XOR + || GET_CODE (XEXP (nz, 0)) == ASHIFT + || GET_CODE (XEXP (nz, 0)) == LSHIFTRT + || GET_CODE (XEXP (nz, 0)) == ASHIFTRT) + && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG + && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0)) + && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z) + && (num_sign_bit_copies (z, GET_MODE (z)) + >= (GET_MODE_BITSIZE (mode) + - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (nz, 0), 0)))))) + { + c = XEXP (XEXP (nz, 0), 1); + op = GET_CODE (XEXP (nz, 0)); + extend_op = SIGN_EXTEND; + m = GET_MODE (XEXP (nz, 0)); + } + else if (GET_CODE (nz) == ZERO_EXTEND + && (GET_CODE (XEXP (nz, 0)) == PLUS + || GET_CODE (XEXP (nz, 0)) == MINUS + || GET_CODE (XEXP (nz, 0)) == IOR + || GET_CODE (XEXP (nz, 0)) == XOR + || GET_CODE (XEXP (nz, 0)) == ASHIFT + || GET_CODE (XEXP (nz, 0)) == LSHIFTRT + || GET_CODE (XEXP (nz, 0)) == ASHIFTRT) + && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0)) + && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z) + && ((nonzero_bits (z, GET_MODE (z)) + & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (nz, 0), 0)))) + == 0)) + { + c = XEXP (XEXP (nz, 0), 1); + op = GET_CODE (XEXP (nz, 0)); + extend_op = ZERO_EXTEND; + m = GET_MODE (XEXP (nz, 0)); + } + + if (c && ! side_effects_p (c) && ! side_effects_p (z)) + { + temp + = gen_binary (MULT, m, + gen_lowpart_for_combine (m, + XEXP (XEXP (x, 0), 0)), + gen_binary (MULT, m, c, dir)); + + temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp); + + if (extend_op != 0) + temp = gen_unary (extend_op, mode, temp); + + return temp; + } + } + break; + + case ZERO_EXTRACT: + case SIGN_EXTRACT: + case ZERO_EXTEND: + case SIGN_EXTEND: + /* If we are processing SET_DEST, we are done. */ + if (in_dest) + return x; + + x = expand_compound_operation (x); + if (GET_CODE (x) != code) + goto restart; + break; + + case SET: + /* (set (pc) (return)) gets written as (return). */ + if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN) + return SET_SRC (x); + + /* Convert this into a field assignment operation, if possible. */ + x = make_field_assignment (x); + + /* If we are setting CC0 or if the source is a COMPARE, look for the + use of the comparison result and try to simplify it unless we already + have used undobuf.other_insn. */ + if ((GET_CODE (SET_SRC (x)) == COMPARE +#ifdef HAVE_cc0 + || SET_DEST (x) == cc0_rtx +#endif + ) + && (cc_use = find_single_use (SET_DEST (x), subst_insn, + &other_insn)) != 0 + && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) + && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<' + && XEXP (*cc_use, 0) == SET_DEST (x)) + { + enum rtx_code old_code = GET_CODE (*cc_use); + enum rtx_code new_code; + rtx op0, op1; + int other_changed = 0; + enum machine_mode compare_mode = GET_MODE (SET_DEST (x)); + + if (GET_CODE (SET_SRC (x)) == COMPARE) + op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1); + else + op0 = SET_SRC (x), op1 = const0_rtx; + + /* Simplify our comparison, if possible. */ + new_code = simplify_comparison (old_code, &op0, &op1); + +#ifdef EXTRA_CC_MODES + /* If this machine has CC modes other than CCmode, check to see + if we need to use a different CC mode here. */ + compare_mode = SELECT_CC_MODE (new_code, op0, op1); +#endif /* EXTRA_CC_MODES */ + +#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES) + /* If the mode changed, we have to change SET_DEST, the mode + in the compare, and the mode in the place SET_DEST is used. + If SET_DEST is a hard register, just build new versions with + the proper mode. If it is a pseudo, we lose unless it is only + time we set the pseudo, in which case we can safely change + its mode. */ + if (compare_mode != GET_MODE (SET_DEST (x))) + { + int regno = REGNO (SET_DEST (x)); + rtx new_dest = gen_rtx (REG, compare_mode, regno); + + if (regno < FIRST_PSEUDO_REGISTER + || (reg_n_sets[regno] == 1 + && ! REG_USERVAR_P (SET_DEST (x)))) + { + if (regno >= FIRST_PSEUDO_REGISTER) + SUBST (regno_reg_rtx[regno], new_dest); + + SUBST (SET_DEST (x), new_dest); + SUBST (XEXP (*cc_use, 0), new_dest); + other_changed = 1; + } + } +#endif + + /* If the code changed, we have to build a new comparison + in undobuf.other_insn. */ + if (new_code != old_code) + { + unsigned HOST_WIDE_INT mask; + + SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use), + SET_DEST (x), const0_rtx)); + + /* If the only change we made was to change an EQ into an + NE or vice versa, OP0 has only one bit that might be nonzero, + and OP1 is zero, check if changing the user of the condition + code will produce a valid insn. If it won't, we can keep + the original code in that insn by surrounding our operation + with an XOR. */ + + if (((old_code == NE && new_code == EQ) + || (old_code == EQ && new_code == NE)) + && ! other_changed && op1 == const0_rtx + && (GET_MODE_BITSIZE (GET_MODE (op0)) + <= HOST_BITS_PER_WIDE_INT) + && (exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) + >= 0)) + { + rtx pat = PATTERN (other_insn), note = 0; + + if ((recog_for_combine (&pat, other_insn, ¬e) < 0 + && ! check_asm_operands (pat))) + { + PUT_CODE (*cc_use, old_code); + other_insn = 0; + + op0 = gen_binary (XOR, GET_MODE (op0), op0, + GEN_INT (mask)); + } + } + + other_changed = 1; + } + + if (other_changed) + undobuf.other_insn = other_insn; + +#ifdef HAVE_cc0 + /* If we are now comparing against zero, change our source if + needed. If we do not use cc0, we always have a COMPARE. */ + if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx) + SUBST (SET_SRC (x), op0); + else +#endif + + /* Otherwise, if we didn't previously have a COMPARE in the + correct mode, we need one. */ + if (GET_CODE (SET_SRC (x)) != COMPARE + || GET_MODE (SET_SRC (x)) != compare_mode) + SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode, + op0, op1)); + else + { + /* Otherwise, update the COMPARE if needed. */ + SUBST (XEXP (SET_SRC (x), 0), op0); + SUBST (XEXP (SET_SRC (x), 1), op1); + } + } + else + { + /* Get SET_SRC in a form where we have placed back any + compound expressions. Then do the checks below. */ + temp = make_compound_operation (SET_SRC (x), SET); + SUBST (SET_SRC (x), temp); + } + + /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some + operation, and X being a REG or (subreg (reg)), we may be able to + convert this to (set (subreg:m2 x) (op)). + + We can always do this if M1 is narrower than M2 because that + means that we only care about the low bits of the result. + + However, on most machines (those with neither BYTE_LOADS_ZERO_EXTEND + nor BYTES_LOADS_SIGN_EXTEND defined), we cannot perform a + narrower operation that requested since the high-order bits will + be undefined. On machine where BYTE_LOADS_*_EXTEND is defined, + however, this transformation is safe as long as M1 and M2 have + the same number of words. */ + + if (GET_CODE (SET_SRC (x)) == SUBREG + && subreg_lowpart_p (SET_SRC (x)) + && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o' + && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1)) + / UNITS_PER_WORD) + == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))) + + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) +#ifndef BYTE_LOADS_EXTEND + && (GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))) +#endif + && (GET_CODE (SET_DEST (x)) == REG + || (GET_CODE (SET_DEST (x)) == SUBREG + && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG))) + { + SUBST (SET_DEST (x), + gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_SRC (x))), + SET_DEST (x))); + SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x))); + } + +#ifdef BYTE_LOADS_EXTEND + /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with + M wider than N, this would require a paradoxical subreg. + Replace the subreg with a zero_extend to avoid the reload that + would otherwise be required. */ + + if (GET_CODE (SET_SRC (x)) == SUBREG + && subreg_lowpart_p (SET_SRC (x)) + && SUBREG_WORD (SET_SRC (x)) == 0 + && (GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))) + && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM) + SUBST (SET_SRC (x), gen_rtx_combine (LOAD_EXTEND, + GET_MODE (SET_SRC (x)), + XEXP (SET_SRC (x), 0))); +#endif + +#ifndef HAVE_conditional_move + + /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, + and we are comparing an item known to be 0 or -1 against 0, use a + logical operation instead. Check for one of the arms being an IOR + of the other arm with some value. We compute three terms to be + IOR'ed together. In practice, at most two will be nonzero. Then + we do the IOR's. */ + + if (GET_CODE (SET_DEST (x)) != PC + && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE + && (GET_CODE (XEXP (SET_SRC (x), 0)) == EQ + || GET_CODE (XEXP (SET_SRC (x), 0)) == NE) + && XEXP (XEXP (SET_SRC (x), 0), 1) == const0_rtx + && (num_sign_bit_copies (XEXP (XEXP (SET_SRC (x), 0), 0), + GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))) + == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0)))) + && ! side_effects_p (SET_SRC (x))) + { + rtx true = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE + ? XEXP (SET_SRC (x), 1) : XEXP (SET_SRC (x), 2)); + rtx false = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE + ? XEXP (SET_SRC (x), 2) : XEXP (SET_SRC (x), 1)); + rtx term1 = const0_rtx, term2, term3; + + if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false)) + term1 = false, true = XEXP (true, 1), false = const0_rtx; + else if (GET_CODE (true) == IOR + && rtx_equal_p (XEXP (true, 1), false)) + term1 = false, true = XEXP (true, 0), false = const0_rtx; + else if (GET_CODE (false) == IOR + && rtx_equal_p (XEXP (false, 0), true)) + term1 = true, false = XEXP (false, 1), true = const0_rtx; + else if (GET_CODE (false) == IOR + && rtx_equal_p (XEXP (false, 1), true)) + term1 = true, false = XEXP (false, 0), true = const0_rtx; + + term2 = gen_binary (AND, GET_MODE (SET_SRC (x)), + XEXP (XEXP (SET_SRC (x), 0), 0), true); + term3 = gen_binary (AND, GET_MODE (SET_SRC (x)), + gen_unary (NOT, GET_MODE (SET_SRC (x)), + XEXP (XEXP (SET_SRC (x), 0), 0)), + false); + + SUBST (SET_SRC (x), + gen_binary (IOR, GET_MODE (SET_SRC (x)), + gen_binary (IOR, GET_MODE (SET_SRC (x)), + term1, term2), + term3)); + } +#endif + break; + + case AND: + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + x = simplify_and_const_int (x, mode, XEXP (x, 0), + INTVAL (XEXP (x, 1))); + + /* If we have (ior (and (X C1) C2)) and the next restart would be + the last, simplify this by making C1 as small as possible + and then exit. */ + if (n_restarts >= 3 && GET_CODE (x) == IOR + && GET_CODE (XEXP (x, 0)) == AND + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && GET_CODE (XEXP (x, 1)) == CONST_INT) + { + temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0), + GEN_INT (INTVAL (XEXP (XEXP (x, 0), 1)) + & ~ INTVAL (XEXP (x, 1)))); + return gen_binary (IOR, mode, temp, XEXP (x, 1)); + } + + if (GET_CODE (x) != AND) + goto restart; + } + + /* Convert (A | B) & A to A. */ + if (GET_CODE (XEXP (x, 0)) == IOR + && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)) + || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))) + && ! side_effects_p (XEXP (XEXP (x, 0), 0)) + && ! side_effects_p (XEXP (XEXP (x, 0), 1))) + return XEXP (x, 1); + + /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single + insn (and may simplify more). */ + else if (GET_CODE (XEXP (x, 0)) == XOR + && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)) + && ! side_effects_p (XEXP (x, 1))) + { + x = gen_binary (AND, mode, + gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)), + XEXP (x, 1)); + goto restart; + } + else if (GET_CODE (XEXP (x, 0)) == XOR + && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)) + && ! side_effects_p (XEXP (x, 1))) + { + x = gen_binary (AND, mode, + gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)), + XEXP (x, 1)); + goto restart; + } + + /* Similarly for (~ (A ^ B)) & A. */ + else if (GET_CODE (XEXP (x, 0)) == NOT + && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR + && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1)) + && ! side_effects_p (XEXP (x, 1))) + { + x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1), + XEXP (x, 1)); + goto restart; + } + else if (GET_CODE (XEXP (x, 0)) == NOT + && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR + && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1)) + && ! side_effects_p (XEXP (x, 1))) + { + x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0), + XEXP (x, 1)); + goto restart; + } + + /* If we have (and A B) with A not an object but that is known to + be -1 or 0, this is equivalent to the expression + (if_then_else (ne A (const_int 0)) B (const_int 0)) + We make this conversion because it may allow further + simplifications and then allow use of conditional move insns. + If the machine doesn't have condition moves, code in case SET + will convert the IF_THEN_ELSE back to the logical operation. + We build the IF_THEN_ELSE here in case further simplification + is possible (e.g., we can convert it to ABS). */ + + if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' + && ! (GET_CODE (XEXP (x, 0)) == SUBREG + && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o') + && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) + == GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))) + { + rtx op0 = XEXP (x, 0); + rtx op1 = const0_rtx; + enum rtx_code comp_code + = simplify_comparison (NE, &op0, &op1); + + x = gen_rtx_combine (IF_THEN_ELSE, mode, + gen_binary (comp_code, VOIDmode, op0, op1), + XEXP (x, 1), const0_rtx); + goto restart; + } + + /* In the following group of tests (and those in case IOR below), + we start with some combination of logical operations and apply + the distributive law followed by the inverse distributive law. + Most of the time, this results in no change. However, if some of + the operands are the same or inverses of each other, simplifications + will result. + + For example, (and (ior A B) (not B)) can occur as the result of + expanding a bit field assignment. When we apply the distributive + law to this, we get (ior (and (A (not B))) (and (B (not B)))), + which then simplifies to (and (A (not B))). */ + + /* If we have (and (ior A B) C), apply the distributive law and then + the inverse distributive law to see if things simplify. */ + + if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR) + { + x = apply_distributive_law + (gen_binary (GET_CODE (XEXP (x, 0)), mode, + gen_binary (AND, mode, + XEXP (XEXP (x, 0), 0), XEXP (x, 1)), + gen_binary (AND, mode, + XEXP (XEXP (x, 0), 1), XEXP (x, 1)))); + if (GET_CODE (x) != AND) + goto restart; + } + + if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR) + { + x = apply_distributive_law + (gen_binary (GET_CODE (XEXP (x, 1)), mode, + gen_binary (AND, mode, + XEXP (XEXP (x, 1), 0), XEXP (x, 0)), + gen_binary (AND, mode, + XEXP (XEXP (x, 1), 1), XEXP (x, 0)))); + if (GET_CODE (x) != AND) + goto restart; + } + + /* Similarly, taking advantage of the fact that + (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */ + + if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR) + { + x = apply_distributive_law + (gen_binary (XOR, mode, + gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0), + XEXP (XEXP (x, 1), 0)), + gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0), + XEXP (XEXP (x, 1), 1)))); + if (GET_CODE (x) != AND) + goto restart; + } + + else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR) + { + x = apply_distributive_law + (gen_binary (XOR, mode, + gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0), + XEXP (XEXP (x, 0), 0)), + gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0), + XEXP (XEXP (x, 0), 1)))); + if (GET_CODE (x) != AND) + goto restart; + } + break; + + case IOR: + /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && (nonzero_bits (XEXP (x, 0), mode) & ~ INTVAL (XEXP (x, 1))) == 0) + return XEXP (x, 1); + + /* Convert (A & B) | A to A. */ + if (GET_CODE (XEXP (x, 0)) == AND + && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)) + || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))) + && ! side_effects_p (XEXP (XEXP (x, 0), 0)) + && ! side_effects_p (XEXP (XEXP (x, 0), 1))) + return XEXP (x, 1); + + /* If we have (ior (and A B) C), apply the distributive law and then + the inverse distributive law to see if things simplify. */ + + if (GET_CODE (XEXP (x, 0)) == AND) + { + x = apply_distributive_law + (gen_binary (AND, mode, + gen_binary (IOR, mode, + XEXP (XEXP (x, 0), 0), XEXP (x, 1)), + gen_binary (IOR, mode, + XEXP (XEXP (x, 0), 1), XEXP (x, 1)))); + + if (GET_CODE (x) != IOR) + goto restart; + } + + if (GET_CODE (XEXP (x, 1)) == AND) + { + x = apply_distributive_law + (gen_binary (AND, mode, + gen_binary (IOR, mode, + XEXP (XEXP (x, 1), 0), XEXP (x, 0)), + gen_binary (IOR, mode, + XEXP (XEXP (x, 1), 1), XEXP (x, 0)))); + + if (GET_CODE (x) != IOR) + goto restart; + } + + /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the + mode size to (rotate A CX). */ + + if (((GET_CODE (XEXP (x, 0)) == ASHIFT + && GET_CODE (XEXP (x, 1)) == LSHIFTRT) + || (GET_CODE (XEXP (x, 1)) == ASHIFT + && GET_CODE (XEXP (x, 0)) == LSHIFTRT)) + && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0)) + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT + && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1)) + == GET_MODE_BITSIZE (mode))) + { + rtx shift_count; + + if (GET_CODE (XEXP (x, 0)) == ASHIFT) + shift_count = XEXP (XEXP (x, 0), 1); + else + shift_count = XEXP (XEXP (x, 1), 1); + x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count); + goto restart; + } + break; + + case XOR: + /* Convert (XOR (NOT x) (NOT y)) to (XOR x y). + Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for + (NOT y). */ + { + int num_negated = 0; + rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1); + + if (GET_CODE (in1) == NOT) + num_negated++, in1 = XEXP (in1, 0); + if (GET_CODE (in2) == NOT) + num_negated++, in2 = XEXP (in2, 0); + + if (num_negated == 2) + { + SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); + SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0)); + } + else if (num_negated == 1) + { + x = gen_unary (NOT, mode, + gen_binary (XOR, mode, in1, in2)); + goto restart; + } + } + + /* Convert (xor (and A B) B) to (and (not A) B). The latter may + correspond to a machine insn or result in further simplifications + if B is a constant. */ + + if (GET_CODE (XEXP (x, 0)) == AND + && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)) + && ! side_effects_p (XEXP (x, 1))) + { + x = gen_binary (AND, mode, + gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)), + XEXP (x, 1)); + goto restart; + } + else if (GET_CODE (XEXP (x, 0)) == AND + && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)) + && ! side_effects_p (XEXP (x, 1))) + { + x = gen_binary (AND, mode, + gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)), + XEXP (x, 1)); + goto restart; + } + + +#if STORE_FLAG_VALUE == 1 + /* (xor (comparison foo bar) (const_int 1)) can become the reversed + comparison. */ + if (XEXP (x, 1) == const1_rtx + && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' + && reversible_comparison_p (XEXP (x, 0))) + return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))), + mode, XEXP (XEXP (x, 0), 0), + XEXP (XEXP (x, 0), 1)); + + /* (lshiftrt foo C) where C is the number of bits in FOO minus 1 + is (lt foo (const_int 0)), so we can perform the above + simplification. */ + + if (XEXP (x, 1) == const1_rtx + && GET_CODE (XEXP (x, 0)) == LSHIFTRT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1) + return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx); +#endif + + /* (xor (comparison foo bar) (const_int sign-bit)) + when STORE_FLAG_VALUE is the sign bit. */ + if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && (STORE_FLAG_VALUE + == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) + && XEXP (x, 1) == const_true_rtx + && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' + && reversible_comparison_p (XEXP (x, 0))) + return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))), + mode, XEXP (XEXP (x, 0), 0), + XEXP (XEXP (x, 0), 1)); + break; + + case ABS: + /* (abs (neg )) -> (abs ) */ + if (GET_CODE (XEXP (x, 0)) == NEG) + SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); + + /* If operand is something known to be positive, ignore the ABS. */ + if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS + || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) + <= HOST_BITS_PER_WIDE_INT) + && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) + & ((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) + == 0))) + return XEXP (x, 0); + + + /* If operand is known to be only -1 or 0, convert ABS to NEG. */ + if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode)) + { + x = gen_rtx_combine (NEG, mode, XEXP (x, 0)); + goto restart; + } + break; + + case FFS: + /* (ffs (*_extend )) = (ffs ) */ + if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND + || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) + SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); + break; + + case FLOAT: + /* (float (sign_extend )) = (float ). */ + if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) + SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); + break; + + case LSHIFT: + case ASHIFT: + case LSHIFTRT: + case ASHIFTRT: + case ROTATE: + case ROTATERT: + /* If this is a shift by a constant amount, simplify it. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + x = simplify_shift_const (x, code, mode, XEXP (x, 0), + INTVAL (XEXP (x, 1))); + if (GET_CODE (x) != code) + goto restart; + } + +#ifdef SHIFT_COUNT_TRUNCATED + else if (GET_CODE (XEXP (x, 1)) != REG) + SUBST (XEXP (x, 1), + force_to_mode (XEXP (x, 1), GET_MODE (x), + exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))), + NULL_RTX)); +#endif + + break; + } + + return x; +} + +/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound + operations" because they can be replaced with two more basic operations. + ZERO_EXTEND is also considered "compound" because it can be replaced with + an AND operation, which is simpler, though only one operation. + + The function expand_compound_operation is called with an rtx expression + and will convert it to the appropriate shifts and AND operations, + simplifying at each stage. + + The function make_compound_operation is called to convert an expression + consisting of shifts and ANDs into the equivalent compound expression. + It is the inverse of this function, loosely speaking. */ + +static rtx +expand_compound_operation (x) + rtx x; +{ + int pos = 0, len; + int unsignedp = 0; + int modewidth; + rtx tem; + + switch (GET_CODE (x)) + { + case ZERO_EXTEND: + unsignedp = 1; + case SIGN_EXTEND: + /* We can't necessarily use a const_int for a multiword mode; + it depends on implicitly extending the value. + Since we don't know the right way to extend it, + we can't tell whether the implicit way is right. + + Even for a mode that is no wider than a const_int, + we can't win, because we need to sign extend one of its bits through + the rest of it, and we don't know which bit. */ + if (GET_CODE (XEXP (x, 0)) == CONST_INT) + return x; + + if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0))) + return x; + + len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); + /* If the inner object has VOIDmode (the only way this can happen + is if it is a ASM_OPERANDS), we can't do anything since we don't + know how much masking to do. */ + if (len == 0) + return x; + + break; + + case ZERO_EXTRACT: + unsignedp = 1; + case SIGN_EXTRACT: + /* If the operand is a CLOBBER, just return it. */ + if (GET_CODE (XEXP (x, 0)) == CLOBBER) + return XEXP (x, 0); + + if (GET_CODE (XEXP (x, 1)) != CONST_INT + || GET_CODE (XEXP (x, 2)) != CONST_INT + || GET_MODE (XEXP (x, 0)) == VOIDmode) + return x; + + len = INTVAL (XEXP (x, 1)); + pos = INTVAL (XEXP (x, 2)); + + /* If this goes outside the object being extracted, replace the object + with a (use (mem ...)) construct that only combine understands + and is used only for this purpose. */ + if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) + SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0))); + +#if BITS_BIG_ENDIAN + pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; +#endif + break; + + default: + return x; + } + + /* If we reach here, we want to return a pair of shifts. The inner + shift is a left shift of BITSIZE - POS - LEN bits. The outer + shift is a right shift of BITSIZE - LEN bits. It is arithmetic or + logical depending on the value of UNSIGNEDP. + + If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be + converted into an AND of a shift. + + We must check for the case where the left shift would have a negative + count. This can happen in a case like (x >> 31) & 255 on machines + that can't shift by a constant. On those machines, we would first + combine the shift with the AND to produce a variable-position + extraction. Then the constant of 31 would be substituted in to produce + a such a position. */ + + modewidth = GET_MODE_BITSIZE (GET_MODE (x)); + if (modewidth >= pos - len) + tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, + GET_MODE (x), + simplify_shift_const (NULL_RTX, ASHIFT, + GET_MODE (x), + XEXP (x, 0), + modewidth - pos - len), + modewidth - len); + + else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) + tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), + simplify_shift_const (NULL_RTX, LSHIFTRT, + GET_MODE (x), + XEXP (x, 0), pos), + ((HOST_WIDE_INT) 1 << len) - 1); + else + /* Any other cases we can't handle. */ + return x; + + + /* If we couldn't do this for some reason, return the original + expression. */ + if (GET_CODE (tem) == CLOBBER) + return x; + + return tem; +} + +/* X is a SET which contains an assignment of one object into + a part of another (such as a bit-field assignment, STRICT_LOW_PART, + or certain SUBREGS). If possible, convert it into a series of + logical operations. + + We half-heartedly support variable positions, but do not at all + support variable lengths. */ + +static rtx +expand_field_assignment (x) + rtx x; +{ + rtx inner; + rtx pos; /* Always counts from low bit. */ + int len; + rtx mask; + enum machine_mode compute_mode; + + /* Loop until we find something we can't simplify. */ + while (1) + { + if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART + && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) + { + inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); + len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); + pos = const0_rtx; + } + else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT + && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) + { + inner = XEXP (SET_DEST (x), 0); + len = INTVAL (XEXP (SET_DEST (x), 1)); + pos = XEXP (SET_DEST (x), 2); + + /* If the position is constant and spans the width of INNER, + surround INNER with a USE to indicate this. */ + if (GET_CODE (pos) == CONST_INT + && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) + inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner); + +#if BITS_BIG_ENDIAN + if (GET_CODE (pos) == CONST_INT) + pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len + - INTVAL (pos)); + else if (GET_CODE (pos) == MINUS + && GET_CODE (XEXP (pos, 1)) == CONST_INT + && (INTVAL (XEXP (pos, 1)) + == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) + /* If position is ADJUST - X, new position is X. */ + pos = XEXP (pos, 0); + else + pos = gen_binary (MINUS, GET_MODE (pos), + GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) + - len), + pos); +#endif + } + + /* A SUBREG between two modes that occupy the same numbers of words + can be done by moving the SUBREG to the source. */ + else if (GET_CODE (SET_DEST (x)) == SUBREG + && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) + + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) + == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) + + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) + { + x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)), + gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))), + SET_SRC (x))); + continue; + } + else + break; + + while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) + inner = SUBREG_REG (inner); + + compute_mode = GET_MODE (inner); + + /* Compute a mask of LEN bits, if we can do this on the host machine. */ + if (len < HOST_BITS_PER_WIDE_INT) + mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); + else + break; + + /* Now compute the equivalent expression. Make a copy of INNER + for the SET_DEST in case it is a MEM into which we will substitute; + we don't want shared RTL in that case. */ + x = gen_rtx (SET, VOIDmode, copy_rtx (inner), + gen_binary (IOR, compute_mode, + gen_binary (AND, compute_mode, + gen_unary (NOT, compute_mode, + gen_binary (ASHIFT, + compute_mode, + mask, pos)), + inner), + gen_binary (ASHIFT, compute_mode, + gen_binary (AND, compute_mode, + gen_lowpart_for_combine + (compute_mode, + SET_SRC (x)), + mask), + pos))); + } + + return x; +} + +/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, + it is an RTX that represents a variable starting position; otherwise, + POS is the (constant) starting bit position (counted from the LSB). + + INNER may be a USE. This will occur when we started with a bitfield + that went outside the boundary of the object in memory, which is + allowed on most machines. To isolate this case, we produce a USE + whose mode is wide enough and surround the MEM with it. The only + code that understands the USE is this routine. If it is not removed, + it will cause the resulting insn not to match. + + UNSIGNEDP is non-zero for an unsigned reference and zero for a + signed reference. + + IN_DEST is non-zero if this is a reference in the destination of a + SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero, + a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will + be used. + + IN_COMPARE is non-zero if we are in a COMPARE. This means that a + ZERO_EXTRACT should be built even for bits starting at bit 0. + + MODE is the desired mode of the result (if IN_DEST == 0). */ + +static rtx +make_extraction (mode, inner, pos, pos_rtx, len, + unsignedp, in_dest, in_compare) + enum machine_mode mode; + rtx inner; + int pos; + rtx pos_rtx; + int len; + int unsignedp; + int in_dest, in_compare; +{ + /* This mode describes the size of the storage area + to fetch the overall value from. Within that, we + ignore the POS lowest bits, etc. */ + enum machine_mode is_mode = GET_MODE (inner); + enum machine_mode inner_mode; + enum machine_mode wanted_mem_mode = byte_mode; + enum machine_mode pos_mode = word_mode; + enum machine_mode extraction_mode = word_mode; + enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); + int spans_byte = 0; + rtx new = 0; + rtx orig_pos_rtx = pos_rtx; + + /* Get some information about INNER and get the innermost object. */ + if (GET_CODE (inner) == USE) + /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */ + /* We don't need to adjust the position because we set up the USE + to pretend that it was a full-word object. */ + spans_byte = 1, inner = XEXP (inner, 0); + else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) + { + /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), + consider just the QI as the memory to extract from. + The subreg adds or removes high bits; its mode is + irrelevant to the meaning of this extraction, + since POS and LEN count from the lsb. */ + if (GET_CODE (SUBREG_REG (inner)) == MEM) + is_mode = GET_MODE (SUBREG_REG (inner)); + inner = SUBREG_REG (inner); + } + + inner_mode = GET_MODE (inner); + + if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) + pos = INTVAL (pos_rtx), pos_rtx = 0; + + /* See if this can be done without an extraction. We never can if the + width of the field is not the same as that of some integer mode. For + registers, we can only avoid the extraction if the position is at the + low-order bit and this is either not in the destination or we have the + appropriate STRICT_LOW_PART operation available. + + For MEM, we can avoid an extract if the field starts on an appropriate + boundary and we can change the mode of the memory reference. However, + we cannot directly access the MEM if we have a USE and the underlying + MEM is not TMODE. This combination means that MEM was being used in a + context where bits outside its mode were being referenced; that is only + valid in bit-field insns. */ + + if (tmode != BLKmode + && ! (spans_byte && inner_mode != tmode) + && ((pos_rtx == 0 && pos == 0 && GET_CODE (inner) != MEM + && (! in_dest + || (GET_CODE (inner) == REG + && (movstrict_optab->handlers[(int) tmode].insn_code + != CODE_FOR_nothing)))) + || (GET_CODE (inner) == MEM && pos_rtx == 0 + && (pos + % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) + : BITS_PER_UNIT)) == 0 + /* We can't do this if we are widening INNER_MODE (it + may not be aligned, for one thing). */ + && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) + && (inner_mode == tmode + || (! mode_dependent_address_p (XEXP (inner, 0)) + && ! MEM_VOLATILE_P (inner)))))) + { + /* If INNER is a MEM, make a new MEM that encompasses just the desired + field. If the original and current mode are the same, we need not + adjust the offset. Otherwise, we do if bytes big endian. + + If INNER is not a MEM, get a piece consisting of the just the field + of interest (in this case POS must be 0). */ + + if (GET_CODE (inner) == MEM) + { + int offset; + /* POS counts from lsb, but make OFFSET count in memory order. */ + if (BYTES_BIG_ENDIAN) + offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; + else + offset = pos / BITS_PER_UNIT; + + new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset)); + RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner); + MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner); + MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner); + } + else if (GET_CODE (inner) == REG) + /* We can't call gen_lowpart_for_combine here since we always want + a SUBREG and it would sometimes return a new hard register. */ + new = gen_rtx (SUBREG, tmode, inner, + (WORDS_BIG_ENDIAN + && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD + ? ((GET_MODE_SIZE (inner_mode) - GET_MODE_SIZE (tmode)) + / UNITS_PER_WORD) + : 0)); + else + new = force_to_mode (inner, tmode, len, NULL_RTX); + + /* If this extraction is going into the destination of a SET, + make a STRICT_LOW_PART unless we made a MEM. */ + + if (in_dest) + return (GET_CODE (new) == MEM ? new + : (GET_CODE (new) != SUBREG + ? gen_rtx (CLOBBER, tmode, const0_rtx) + : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new))); + + /* Otherwise, sign- or zero-extend unless we already are in the + proper mode. */ + + return (mode == tmode ? new + : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, + mode, new)); + } + + /* Unless this is a COMPARE or we have a funny memory reference, + don't do anything with zero-extending field extracts starting at + the low-order bit since they are simple AND operations. */ + if (pos_rtx == 0 && pos == 0 && ! in_dest + && ! in_compare && ! spans_byte && unsignedp) + return 0; + + /* Get the mode to use should INNER be a MEM, the mode for the position, + and the mode for the result. */ +#ifdef HAVE_insv + if (in_dest) + { + wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0]; + pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2]; + extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3]; + } +#endif + +#ifdef HAVE_extzv + if (! in_dest && unsignedp) + { + wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1]; + pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3]; + extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0]; + } +#endif + +#ifdef HAVE_extv + if (! in_dest && ! unsignedp) + { + wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1]; + pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3]; + extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0]; + } +#endif + + /* Never narrow an object, since that might not be safe. */ + + if (mode != VOIDmode + && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) + extraction_mode = mode; + + if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode + && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) + pos_mode = GET_MODE (pos_rtx); + + /* If this is not from memory or we have to change the mode of memory and + cannot, the desired mode is EXTRACTION_MODE. */ + if (GET_CODE (inner) != MEM + || (inner_mode != wanted_mem_mode + && (mode_dependent_address_p (XEXP (inner, 0)) + || MEM_VOLATILE_P (inner)))) + wanted_mem_mode = extraction_mode; + +#if BITS_BIG_ENDIAN + /* If position is constant, compute new position. Otherwise, build + subtraction. */ + if (pos_rtx == 0) + pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode)) + - len - pos); + else + pos_rtx + = gen_rtx_combine (MINUS, GET_MODE (pos_rtx), + GEN_INT (MAX (GET_MODE_BITSIZE (is_mode), + GET_MODE_BITSIZE (wanted_mem_mode)) + - len), + pos_rtx); +#endif + + /* If INNER has a wider mode, make it smaller. If this is a constant + extract, try to adjust the byte to point to the byte containing + the value. */ + if (wanted_mem_mode != VOIDmode + && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode) + && ((GET_CODE (inner) == MEM + && (inner_mode == wanted_mem_mode + || (! mode_dependent_address_p (XEXP (inner, 0)) + && ! MEM_VOLATILE_P (inner)))))) + { + int offset = 0; + + /* The computations below will be correct if the machine is big + endian in both bits and bytes or little endian in bits and bytes. + If it is mixed, we must adjust. */ + + /* If bytes are big endian and we had a paradoxical SUBREG, we must + adjust OFFSET to compensate. */ +#if BYTES_BIG_ENDIAN + if (! spans_byte + && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) + offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); +#endif + + /* If this is a constant position, we can move to the desired byte. */ + if (pos_rtx == 0) + { + offset += pos / BITS_PER_UNIT; + pos %= GET_MODE_BITSIZE (wanted_mem_mode); + } + +#if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN + if (! spans_byte && is_mode != wanted_mem_mode) + offset = (GET_MODE_SIZE (is_mode) + - GET_MODE_SIZE (wanted_mem_mode) - offset); +#endif + + if (offset != 0 || inner_mode != wanted_mem_mode) + { + rtx newmem = gen_rtx (MEM, wanted_mem_mode, + plus_constant (XEXP (inner, 0), offset)); + RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner); + MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner); + MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner); + inner = newmem; + } + } + + /* If INNER is not memory, we can always get it into the proper mode. */ + else if (GET_CODE (inner) != MEM) + inner = force_to_mode (inner, extraction_mode, + (pos < 0 ? GET_MODE_BITSIZE (extraction_mode) + : len + pos), + NULL_RTX); + + /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we + have to zero extend. Otherwise, we can just use a SUBREG. */ + if (pos_rtx != 0 + && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) + pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx); + else if (pos_rtx != 0 + && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) + pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx); + + /* Make POS_RTX unless we already have it and it is correct. If we don't + have a POS_RTX but we do have an ORIG_POS_RTX, the latter must + be a CONST_INT. */ + if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) + pos_rtx = orig_pos_rtx; + + else if (pos_rtx == 0) + pos_rtx = GEN_INT (pos); + + /* Make the required operation. See if we can use existing rtx. */ + new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, + extraction_mode, inner, GEN_INT (len), pos_rtx); + if (! in_dest) + new = gen_lowpart_for_combine (mode, new); + + return new; +} + +/* Look at the expression rooted at X. Look for expressions + equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. + Form these expressions. + + Return the new rtx, usually just X. + + Also, for machines like the Vax that don't have logical shift insns, + try to convert logical to arithmetic shift operations in cases where + they are equivalent. This undoes the canonicalizations to logical + shifts done elsewhere. + + We try, as much as possible, to re-use rtl expressions to save memory. + + IN_CODE says what kind of expression we are processing. Normally, it is + SET. In a memory address (inside a MEM, PLUS or minus, the latter two + being kludges), it is MEM. When processing the arguments of a comparison + or a COMPARE against zero, it is COMPARE. */ + +static rtx +make_compound_operation (x, in_code) + rtx x; + enum rtx_code in_code; +{ + enum rtx_code code = GET_CODE (x); + enum machine_mode mode = GET_MODE (x); + int mode_width = GET_MODE_BITSIZE (mode); + enum rtx_code next_code; + int i, count; + rtx new = 0; + rtx tem; + char *fmt; + + /* Select the code to be used in recursive calls. Once we are inside an + address, we stay there. If we have a comparison, set to COMPARE, + but once inside, go back to our default of SET. */ + + next_code = (code == MEM || code == PLUS || code == MINUS ? MEM + : ((code == COMPARE || GET_RTX_CLASS (code) == '<') + && XEXP (x, 1) == const0_rtx) ? COMPARE + : in_code == COMPARE ? SET : in_code); + + /* Process depending on the code of this operation. If NEW is set + non-zero, it will be returned. */ + + switch (code) + { + case ASHIFT: + case LSHIFT: + /* Convert shifts by constants into multiplications if inside + an address. */ + if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT + && INTVAL (XEXP (x, 1)) >= 0) + { + new = make_compound_operation (XEXP (x, 0), next_code); + new = gen_rtx_combine (MULT, mode, new, + GEN_INT ((HOST_WIDE_INT) 1 + << INTVAL (XEXP (x, 1)))); + } + break; + + case AND: + /* If the second operand is not a constant, we can't do anything + with it. */ + if (GET_CODE (XEXP (x, 1)) != CONST_INT) + break; + + /* If the constant is a power of two minus one and the first operand + is a logical right shift, make an extraction. */ + if (GET_CODE (XEXP (x, 0)) == LSHIFTRT + && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) + { + new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); + new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1, + 0, in_code == COMPARE); + } + + /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ + else if (GET_CODE (XEXP (x, 0)) == SUBREG + && subreg_lowpart_p (XEXP (x, 0)) + && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT + && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) + { + new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), + next_code); + new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0, + XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, + 0, in_code == COMPARE); + } + + /* If we are have (and (rotate X C) M) and C is larger than the number + of bits in M, this is an extraction. */ + + else if (GET_CODE (XEXP (x, 0)) == ROTATE + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 + && i <= INTVAL (XEXP (XEXP (x, 0), 1))) + { + new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); + new = make_extraction (mode, new, + (GET_MODE_BITSIZE (mode) + - INTVAL (XEXP (XEXP (x, 0), 1))), + NULL_RTX, i, 1, 0, in_code == COMPARE); + } + + /* On machines without logical shifts, if the operand of the AND is + a logical shift and our mask turns off all the propagated sign + bits, we can replace the logical shift with an arithmetic shift. */ + else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing + && (lshr_optab->handlers[(int) mode].insn_code + == CODE_FOR_nothing) + && GET_CODE (XEXP (x, 0)) == LSHIFTRT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 + && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT + && mode_width <= HOST_BITS_PER_WIDE_INT) + { + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); + + mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); + if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) + SUBST (XEXP (x, 0), + gen_rtx_combine (ASHIFTRT, mode, + make_compound_operation (XEXP (XEXP (x, 0), 0), + next_code), + XEXP (XEXP (x, 0), 1))); + } + + /* If the constant is one less than a power of two, this might be + representable by an extraction even if no shift is present. + If it doesn't end up being a ZERO_EXTEND, we will ignore it unless + we are in a COMPARE. */ + else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) + new = make_extraction (mode, + make_compound_operation (XEXP (x, 0), + next_code), + 0, NULL_RTX, i, 1, 0, in_code == COMPARE); + + /* If we are in a comparison and this is an AND with a power of two, + convert this into the appropriate bit extract. */ + else if (in_code == COMPARE + && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) + new = make_extraction (mode, + make_compound_operation (XEXP (x, 0), + next_code), + i, NULL_RTX, 1, 1, 0, 1); + + break; + + case LSHIFTRT: + /* If the sign bit is known to be zero, replace this with an + arithmetic shift. */ + if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing + && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing + && mode_width <= HOST_BITS_PER_WIDE_INT + && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) + { + new = gen_rtx_combine (ASHIFTRT, mode, + make_compound_operation (XEXP (x, 0), + next_code), + XEXP (x, 1)); + break; + } + + /* ... fall through ... */ + + case ASHIFTRT: + /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, + this is a SIGN_EXTRACT. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && GET_CODE (XEXP (x, 0)) == ASHIFT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1))) + { + new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); + new = make_extraction (mode, new, + (INTVAL (XEXP (x, 1)) + - INTVAL (XEXP (XEXP (x, 0), 1))), + NULL_RTX, mode_width - INTVAL (XEXP (x, 1)), + code == LSHIFTRT, 0, in_code == COMPARE); + } + + /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these + cases, we are better off returning a SIGN_EXTEND of the operation. */ + + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND + || GET_CODE (XEXP (x, 0)) == XOR + || GET_CODE (XEXP (x, 0)) == PLUS) + && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT + && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && 0 == (INTVAL (XEXP (XEXP (x, 0), 1)) + & (((HOST_WIDE_INT) 1 + << (MIN (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)), + INTVAL (XEXP (x, 1))) + - 1))))) + { + rtx c1 = XEXP (XEXP (XEXP (x, 0), 0), 1); + rtx c2 = XEXP (x, 1); + rtx c3 = XEXP (XEXP (x, 0), 1); + HOST_WIDE_INT newop1; + rtx inner = XEXP (XEXP (XEXP (x, 0), 0), 0); + + /* If C1 > C2, INNER needs to have the shift performed on it + for C1-C2 bits. */ + if (INTVAL (c1) > INTVAL (c2)) + { + inner = gen_binary (ASHIFT, mode, inner, + GEN_INT (INTVAL (c1) - INTVAL (c2))); + c1 = c2; + } + + newop1 = INTVAL (c3) >> INTVAL (c1); + new = make_compound_operation (inner, + GET_CODE (XEXP (x, 0)) == PLUS + ? MEM : GET_CODE (XEXP (x, 0))); + new = make_extraction (mode, + gen_binary (GET_CODE (XEXP (x, 0)), mode, new, + GEN_INT (newop1)), + INTVAL (c2) - INTVAL (c1), + NULL_RTX, mode_width - INTVAL (c2), + code == LSHIFTRT, 0, in_code == COMPARE); + } + + /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && GET_CODE (XEXP (x, 0)) == NEG + && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT + && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) + { + new = make_compound_operation (XEXP (XEXP (XEXP (x, 0), 0), 0), + next_code); + new = make_extraction (mode, + gen_unary (GET_CODE (XEXP (x, 0)), mode, + new, 0), + (INTVAL (XEXP (x, 1)) + - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))), + NULL_RTX, mode_width - INTVAL (XEXP (x, 1)), + code == LSHIFTRT, 0, in_code == COMPARE); + } + break; + + case SUBREG: + /* Call ourselves recursively on the inner expression. If we are + narrowing the object and it has a different RTL code from + what it originally did, do this SUBREG as a force_to_mode. */ + + tem = make_compound_operation (SUBREG_REG (x), in_code); + if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) + && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) + && subreg_lowpart_p (x)) + { + rtx newer = force_to_mode (tem, mode, + GET_MODE_BITSIZE (mode), NULL_RTX); + + /* If we have something other than a SUBREG, we might have + done an expansion, so rerun outselves. */ + if (GET_CODE (newer) != SUBREG) + newer = make_compound_operation (newer, in_code); + + return newer; + } + } + + if (new) + { + x = gen_lowpart_for_combine (mode, new); + code = GET_CODE (x); + } + + /* Now recursively process each operand of this operation. */ + fmt = GET_RTX_FORMAT (code); + for (i = 0; i < GET_RTX_LENGTH (code); i++) + if (fmt[i] == 'e') + { + new = make_compound_operation (XEXP (x, i), next_code); + SUBST (XEXP (x, i), new); + } + + return x; +} + +/* Given M see if it is a value that would select a field of bits + within an item, but not the entire word. Return -1 if not. + Otherwise, return the starting position of the field, where 0 is the + low-order bit. + + *PLEN is set to the length of the field. */ + +static int +get_pos_from_mask (m, plen) + unsigned HOST_WIDE_INT m; + int *plen; +{ + /* Get the bit number of the first 1 bit from the right, -1 if none. */ + int pos = exact_log2 (m & - m); + + if (pos < 0) + return -1; + + /* Now shift off the low-order zero bits and see if we have a power of + two minus 1. */ + *plen = exact_log2 ((m >> pos) + 1); + + if (*plen <= 0) + return -1; + + return pos; +} + +/* Rewrite X so that it is an expression in MODE. We only care about the + low-order BITS bits so we can ignore AND operations that just clear + higher-order bits. + + Also, if REG is non-zero and X is a register equal in value to REG, + replace X with REG. */ + +static rtx +force_to_mode (x, mode, bits, reg) + rtx x; + enum machine_mode mode; + int bits; + rtx reg; +{ + enum rtx_code code = GET_CODE (x); + enum machine_mode op_mode = mode; + + /* If X is narrower than MODE or if BITS is larger than the size of MODE, + just get X in the proper mode. */ + + if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) + || bits > GET_MODE_BITSIZE (mode)) + return gen_lowpart_for_combine (mode, x); + + switch (code) + { + case SIGN_EXTEND: + case ZERO_EXTEND: + case ZERO_EXTRACT: + case SIGN_EXTRACT: + x = expand_compound_operation (x); + if (GET_CODE (x) != code) + return force_to_mode (x, mode, bits, reg); + break; + + case REG: + if (reg != 0 && (rtx_equal_p (get_last_value (reg), x) + || rtx_equal_p (reg, get_last_value (x)))) + x = reg; + break; + + case CONST_INT: + if (bits < HOST_BITS_PER_WIDE_INT) + x = GEN_INT (INTVAL (x) & (((HOST_WIDE_INT) 1 << bits) - 1)); + return x; + + case SUBREG: + /* Ignore low-order SUBREGs. */ + if (subreg_lowpart_p (x)) + return force_to_mode (SUBREG_REG (x), mode, bits, reg); + break; + + case AND: + /* If this is an AND with a constant. Otherwise, we fall through to + do the general binary case. */ + + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + HOST_WIDE_INT mask = INTVAL (XEXP (x, 1)); + int len = exact_log2 (mask + 1); + rtx op = XEXP (x, 0); + + /* If this is masking some low-order bits, we may be able to + impose a stricter constraint on what bits of the operand are + required. */ + + op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits, + reg); + + if (bits < HOST_BITS_PER_WIDE_INT) + mask &= ((HOST_WIDE_INT) 1 << bits) - 1; + + /* If we have no AND in MODE, use the original mode for the + operation. */ + + if (and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) + op_mode = GET_MODE (x); + + x = simplify_and_const_int (x, op_mode, op, mask); + + /* If X is still an AND, see if it is an AND with a mask that + is just some low-order bits. If so, and it is BITS wide (it + can't be wider), we don't need it. */ + + if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT + && bits < HOST_BITS_PER_WIDE_INT + && INTVAL (XEXP (x, 1)) == ((HOST_WIDE_INT) 1 << bits) - 1) + x = XEXP (x, 0); + + break; + } + + /* ... fall through ... */ + + case PLUS: + case MINUS: + case MULT: + case IOR: + case XOR: + /* For most binary operations, just propagate into the operation and + change the mode if we have an operation of that mode. */ + + if ((code == PLUS + && add_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) + || (code == MINUS + && sub_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) + || (code == MULT && (smul_optab->handlers[(int) mode].insn_code + == CODE_FOR_nothing)) + || (code == AND + && and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) + || (code == IOR + && ior_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) + || (code == XOR && (xor_optab->handlers[(int) mode].insn_code + == CODE_FOR_nothing))) + op_mode = GET_MODE (x); + + x = gen_binary (code, op_mode, + gen_lowpart_for_combine (op_mode, + force_to_mode (XEXP (x, 0), + mode, bits, + reg)), + gen_lowpart_for_combine (op_mode, + force_to_mode (XEXP (x, 1), + mode, bits, + reg))); + break; + + case ASHIFT: + case LSHIFT: + /* For left shifts, do the same, but just for the first operand. + However, we cannot do anything with shifts where we cannot + guarantee that the counts are smaller than the size of the mode + because such a count will have a different meaning in a + wider mode. + + If we can narrow the shift and know the count, we need even fewer + bits of the first operand. */ + + if (! (GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) + && ! (GET_MODE (XEXP (x, 1)) != VOIDmode + && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) + < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) + break; + + if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits) + bits -= INTVAL (XEXP (x, 1)); + + if ((code == ASHIFT + && ashl_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) + || (code == LSHIFT && (lshl_optab->handlers[(int) mode].insn_code + == CODE_FOR_nothing))) + op_mode = GET_MODE (x); + + x = gen_binary (code, op_mode, + gen_lowpart_for_combine (op_mode, + force_to_mode (XEXP (x, 0), + mode, bits, + reg)), + XEXP (x, 1)); + break; + + case LSHIFTRT: + /* Here we can only do something if the shift count is a constant and + the count plus BITS is no larger than the width of MODE. In that + case, we can do the shift in MODE. */ + + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode)) + { + rtx inner = force_to_mode (XEXP (x, 0), mode, + bits + INTVAL (XEXP (x, 1)), reg); + + if (lshr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) + op_mode = GET_MODE (x); + + x = gen_binary (LSHIFTRT, op_mode, + gen_lowpart_for_combine (op_mode, inner), + XEXP (x, 1)); + } + break; + + case ASHIFTRT: + /* If this is a sign-extension operation that just affects bits + we don't care about, remove it. */ + + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) >= 0 + && INTVAL (XEXP (x, 1)) <= GET_MODE_BITSIZE (GET_MODE (x)) - bits + && GET_CODE (XEXP (x, 0)) == ASHIFT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1))) + return force_to_mode (XEXP (XEXP (x, 0), 0), mode, bits, reg); + break; + + case NEG: + case NOT: + if ((code == NEG + && neg_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) + || (code == NOT && (one_cmpl_optab->handlers[(int) mode].insn_code + == CODE_FOR_nothing))) + op_mode = GET_MODE (x); + + /* Handle these similarly to the way we handle most binary operations. */ + x = gen_unary (code, op_mode, + gen_lowpart_for_combine (op_mode, + force_to_mode (XEXP (x, 0), mode, + bits, reg))); + break; + + case IF_THEN_ELSE: + /* We have no way of knowing if the IF_THEN_ELSE can itself be + written in a narrower mode. We play it safe and do not do so. */ + + SUBST (XEXP (x, 1), + gen_lowpart_for_combine (GET_MODE (x), + force_to_mode (XEXP (x, 1), mode, + bits, reg))); + SUBST (XEXP (x, 2), + gen_lowpart_for_combine (GET_MODE (x), + force_to_mode (XEXP (x, 2), mode, + bits, reg))); + break; + } + + /* Ensure we return a value of the proper mode. */ + return gen_lowpart_for_combine (mode, x); +} + +/* Return the value of expression X given the fact that condition COND + is known to be true when applied to REG as its first operand and VAL + as its second. X is known to not be shared and so can be modified in + place. + + We only handle the simplest cases, and specifically those cases that + arise with IF_THEN_ELSE expressions. */ + +static rtx +known_cond (x, cond, reg, val) + rtx x; + enum rtx_code cond; + rtx reg, val; +{ + enum rtx_code code = GET_CODE (x); + rtx new, temp; + char *fmt; + int i, j; + + if (side_effects_p (x)) + return x; + + if (cond == EQ && rtx_equal_p (x, reg)) + return val; + + /* If X is (abs REG) and we know something about REG's relationship + with zero, we may be able to simplify this. */ + + if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) + switch (cond) + { + case GE: case GT: case EQ: + return XEXP (x, 0); + case LT: case LE: + return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0)); + } + + /* The only other cases we handle are MIN, MAX, and comparisons if the + operands are the same as REG and VAL. */ + + else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') + { + if (rtx_equal_p (XEXP (x, 0), val)) + cond = swap_condition (cond), temp = val, val = reg, reg = temp; + + if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) + { + if (GET_RTX_CLASS (code) == '<') + return (comparison_dominates_p (cond, code) ? const_true_rtx + : (comparison_dominates_p (cond, + reverse_condition (code)) + ? const0_rtx : x)); + + else if (code == SMAX || code == SMIN + || code == UMIN || code == UMAX) + { + int unsignedp = (code == UMIN || code == UMAX); + + if (code == SMAX || code == UMAX) + cond = reverse_condition (cond); + + switch (cond) + { + case GE: case GT: + return unsignedp ? x : XEXP (x, 1); + case LE: case LT: + return unsignedp ? x : XEXP (x, 0); + case GEU: case GTU: + return unsignedp ? XEXP (x, 1) : x; + case LEU: case LTU: + return unsignedp ? XEXP (x, 0) : x; + } + } + } + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); + else if (fmt[i] == 'E') + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), + cond, reg, val)); + } + + return x; +} + +/* See if X, a SET operation, can be rewritten as a bit-field assignment. + Return that assignment if so. + + We only handle the most common cases. */ + +static rtx +make_field_assignment (x) + rtx x; +{ + rtx dest = SET_DEST (x); + rtx src = SET_SRC (x); + rtx ourdest; + rtx assign; + HOST_WIDE_INT c1; + int pos, len; + rtx other; + enum machine_mode mode; + + /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is + a clear of a one-bit field. We will have changed it to + (and (rotate (const_int -2) POS) DEST), so check for that. Also check + for a SUBREG. */ + + if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE + && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT + && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 + && (rtx_equal_p (dest, XEXP (src, 1)) + || rtx_equal_p (dest, get_last_value (XEXP (src, 1))) + || rtx_equal_p (get_last_value (dest), XEXP (src, 1)))) + { + assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), + 1, 1, 1, 0); + return gen_rtx (SET, VOIDmode, assign, const0_rtx); + } + + else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG + && subreg_lowpart_p (XEXP (src, 0)) + && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) + < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) + && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE + && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 + && (rtx_equal_p (dest, XEXP (src, 1)) + || rtx_equal_p (dest, get_last_value (XEXP (src, 1))) + || rtx_equal_p (get_last_value (dest), XEXP (src, 1)))) + { + assign = make_extraction (VOIDmode, dest, 0, + XEXP (SUBREG_REG (XEXP (src, 0)), 1), + 1, 1, 1, 0); + return gen_rtx (SET, VOIDmode, assign, const0_rtx); + } + + /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a + one-bit field. */ + else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT + && XEXP (XEXP (src, 0), 0) == const1_rtx + && (rtx_equal_p (dest, XEXP (src, 1)) + || rtx_equal_p (dest, get_last_value (XEXP (src, 1))) + || rtx_equal_p (get_last_value (dest), XEXP (src, 1)))) + { + assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), + 1, 1, 1, 0); + return gen_rtx (SET, VOIDmode, assign, const1_rtx); + } + + /* The other case we handle is assignments into a constant-position + field. They look like (ior (and DEST C1) OTHER). If C1 represents + a mask that has all one bits except for a group of zero bits and + OTHER is known to have zeros where C1 has ones, this is such an + assignment. Compute the position and length from C1. Shift OTHER + to the appropriate position, force it to the required mode, and + make the extraction. Check for the AND in both operands. */ + + if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND + && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT + && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest) + || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest)) + || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest))) + c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1); + else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND + && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT + && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest) + || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest)) + || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)), + dest))) + c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0); + else + return x; + + pos = get_pos_from_mask (~c1, &len); + if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) + || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT + && (c1 & nonzero_bits (other, GET_MODE (other))) != 0)) + return x; + + assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); + + /* The mode to use for the source is the mode of the assignment, or of + what is inside a possible STRICT_LOW_PART. */ + mode = (GET_CODE (assign) == STRICT_LOW_PART + ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); + + /* Shift OTHER right POS places and make it the source, restricting it + to the proper length and mode. */ + + src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT, + GET_MODE (src), other, pos), + mode, len, dest); + + return gen_rtx_combine (SET, VOIDmode, assign, src); +} + +/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) + if so. */ + +static rtx +apply_distributive_law (x) + rtx x; +{ + enum rtx_code code = GET_CODE (x); + rtx lhs, rhs, other; + rtx tem; + enum rtx_code inner_code; + + /* Distributivity is not true for floating point. + It can change the value. So don't do it. + -- rms and moshier@world.std.com. */ + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) + return x; + + /* The outer operation can only be one of the following: */ + if (code != IOR && code != AND && code != XOR + && code != PLUS && code != MINUS) + return x; + + lhs = XEXP (x, 0), rhs = XEXP (x, 1); + + /* If either operand is a primitive we can't do anything, so get out fast. */ + if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o' + || GET_RTX_CLASS (GET_CODE (rhs)) == 'o') + return x; + + lhs = expand_compound_operation (lhs); + rhs = expand_compound_operation (rhs); + inner_code = GET_CODE (lhs); + if (inner_code != GET_CODE (rhs)) + return x; + + /* See if the inner and outer operations distribute. */ + switch (inner_code) + { + case LSHIFTRT: + case ASHIFTRT: + case AND: + case IOR: + /* These all distribute except over PLUS. */ + if (code == PLUS || code == MINUS) + return x; + break; + + case MULT: + if (code != PLUS && code != MINUS) + return x; + break; + + case ASHIFT: + case LSHIFT: + /* These are also multiplies, so they distribute over everything. */ + break; + + case SUBREG: + /* Non-paradoxical SUBREGs distributes over all operations, provided + the inner modes and word numbers are the same, this is an extraction + of a low-order part, we don't convert an fp operation to int or + vice versa, and we would not be converting a single-word + operation into a multi-word operation. The latter test is not + required, but it prevents generating unneeded multi-word operations. + Some of the previous tests are redundant given the latter test, but + are retained because they are required for correctness. + + We produce the result slightly differently in this case. */ + + if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) + || SUBREG_WORD (lhs) != SUBREG_WORD (rhs) + || ! subreg_lowpart_p (lhs) + || (GET_MODE_CLASS (GET_MODE (lhs)) + != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) + || (GET_MODE_SIZE (GET_MODE (lhs)) + < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) + || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD) + return x; + + tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)), + SUBREG_REG (lhs), SUBREG_REG (rhs)); + return gen_lowpart_for_combine (GET_MODE (x), tem); + + default: + return x; + } + + /* Set LHS and RHS to the inner operands (A and B in the example + above) and set OTHER to the common operand (C in the example). + These is only one way to do this unless the inner operation is + commutative. */ + if (GET_RTX_CLASS (inner_code) == 'c' + && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) + other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); + else if (GET_RTX_CLASS (inner_code) == 'c' + && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) + other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); + else if (GET_RTX_CLASS (inner_code) == 'c' + && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) + other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); + else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) + other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); + else + return x; + + /* Form the new inner operation, seeing if it simplifies first. */ + tem = gen_binary (code, GET_MODE (x), lhs, rhs); + + /* There is one exception to the general way of distributing: + (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */ + if (code == XOR && inner_code == IOR) + { + inner_code = AND; + other = gen_unary (NOT, GET_MODE (x), other); + } + + /* We may be able to continuing distributing the result, so call + ourselves recursively on the inner operation before forming the + outer operation, which we return. */ + return gen_binary (inner_code, GET_MODE (x), + apply_distributive_law (tem), other); +} + +/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done + in MODE. + + Return an equivalent form, if different from X. Otherwise, return X. If + X is zero, we are to always construct the equivalent form. */ + +static rtx +simplify_and_const_int (x, mode, varop, constop) + rtx x; + enum machine_mode mode; + rtx varop; + unsigned HOST_WIDE_INT constop; +{ + register enum machine_mode tmode; + register rtx temp; + unsigned HOST_WIDE_INT nonzero; + + /* There is a large class of optimizations based on the principle that + some operations produce results where certain bits are known to be zero, + and hence are not significant to the AND. For example, if we have just + done a left shift of one bit, the low-order bit is known to be zero and + hence an AND with a mask of ~1 would not do anything. + + At the end of the following loop, we set: + + VAROP to be the item to be AND'ed with; + CONSTOP to the constant value to AND it with. */ + + while (1) + { + /* If we ever encounter a mode wider than the host machine's widest + integer size, we can't compute the masks accurately, so give up. */ + if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_WIDE_INT) + break; + + /* Unless one of the cases below does a `continue', + a `break' will be executed to exit the loop. */ + + switch (GET_CODE (varop)) + { + case CLOBBER: + /* If VAROP is a (clobber (const_int)), return it since we know + we are generating something that won't match. */ + return varop; + +#if ! BITS_BIG_ENDIAN + case USE: + /* VAROP is a (use (mem ..)) that was made from a bit-field + extraction that spanned the boundary of the MEM. If we are + now masking so it is within that boundary, we don't need the + USE any more. */ + if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0) + { + varop = XEXP (varop, 0); + continue; + } + break; +#endif + + case SUBREG: + if (subreg_lowpart_p (varop) + /* We can ignore the effect this SUBREG if it narrows the mode + or, on machines where byte operations extend, if the + constant masks to zero all the bits the mode doesn't have. */ + && ((GET_MODE_SIZE (GET_MODE (varop)) + < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))) +#ifdef BYTE_LOADS_EXTEND + || (0 == (constop + & GET_MODE_MASK (GET_MODE (varop)) + & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop))))) +#endif + )) + { + varop = SUBREG_REG (varop); + continue; + } + break; + + case ZERO_EXTRACT: + case SIGN_EXTRACT: + case ZERO_EXTEND: + case SIGN_EXTEND: + /* Try to expand these into a series of shifts and then work + with that result. If we can't, for example, if the extract + isn't at a fixed position, give up. */ + temp = expand_compound_operation (varop); + if (temp != varop) + { + varop = temp; + continue; + } + break; + + case AND: + if (GET_CODE (XEXP (varop, 1)) == CONST_INT) + { + constop &= INTVAL (XEXP (varop, 1)); + varop = XEXP (varop, 0); + continue; + } + break; + + case IOR: + case XOR: + /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and + LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...) + operation which may be a bitfield extraction. Ensure + that the constant we form is not wider than the mode of + VAROP. */ + + if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT + && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0 + && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT + && GET_CODE (XEXP (varop, 1)) == CONST_INT + && ((INTVAL (XEXP (XEXP (varop, 0), 1)) + + floor_log2 (INTVAL (XEXP (varop, 1)))) + < GET_MODE_BITSIZE (GET_MODE (varop))) + && (INTVAL (XEXP (varop, 1)) + & ~ nonzero_bits (XEXP (varop, 0), GET_MODE (varop)) == 0)) + { + temp = GEN_INT ((INTVAL (XEXP (varop, 1)) & constop) + << INTVAL (XEXP (XEXP (varop, 0), 1))); + temp = gen_binary (GET_CODE (varop), GET_MODE (varop), + XEXP (XEXP (varop, 0), 0), temp); + varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop), + temp, XEXP (varop, 1)); + continue; + } + + /* Apply the AND to both branches of the IOR or XOR, then try to + apply the distributive law. This may eliminate operations + if either branch can be simplified because of the AND. + It may also make some cases more complex, but those cases + probably won't match a pattern either with or without this. */ + return + gen_lowpart_for_combine + (mode, apply_distributive_law + (gen_rtx_combine + (GET_CODE (varop), GET_MODE (varop), + simplify_and_const_int (NULL_RTX, GET_MODE (varop), + XEXP (varop, 0), constop), + simplify_and_const_int (NULL_RTX, GET_MODE (varop), + XEXP (varop, 1), constop)))); + + case NOT: + /* (and (not FOO)) is (and (xor FOO CONST)), so if FOO is an + LSHIFTRT, we can do the same as above. Ensure that the constant + we form is not wider than the mode of VAROP. */ + + if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT + && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0 + && (INTVAL (XEXP (XEXP (varop, 0), 1)) + floor_log2 (constop) + < GET_MODE_BITSIZE (GET_MODE (varop))) + && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT) + { + temp = GEN_INT (constop << INTVAL (XEXP (XEXP (varop, 0), 1))); + temp = gen_binary (XOR, GET_MODE (varop), + XEXP (XEXP (varop, 0), 0), temp); + varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop), + temp, XEXP (XEXP (varop, 0), 1)); + continue; + } + break; + + case ASHIFTRT: + /* If we are just looking for the sign bit, we don't need this + shift at all, even if it has a variable count. */ + if (constop == ((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1))) + { + varop = XEXP (varop, 0); + continue; + } + + /* If this is a shift by a constant, get a mask that contains + those bits that are not copies of the sign bit. We then have + two cases: If CONSTOP only includes those bits, this can be + a logical shift, which may allow simplifications. If CONSTOP + is a single-bit field not within those bits, we are requesting + a copy of the sign bit and hence can shift the sign bit to + the appropriate location. */ + if (GET_CODE (XEXP (varop, 1)) == CONST_INT + && INTVAL (XEXP (varop, 1)) >= 0 + && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_WIDE_INT) + { + int i = -1; + + nonzero = GET_MODE_MASK (GET_MODE (varop)); + nonzero >>= INTVAL (XEXP (varop, 1)); + + if ((constop & ~ nonzero) == 0 + || (i = exact_log2 (constop)) >= 0) + { + varop = simplify_shift_const + (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), + i < 0 ? INTVAL (XEXP (varop, 1)) + : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i); + if (GET_CODE (varop) != ASHIFTRT) + continue; + } + } + + /* If our mask is 1, convert this to a LSHIFTRT. This can be done + even if the shift count isn't a constant. */ + if (constop == 1) + varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop), + XEXP (varop, 0), XEXP (varop, 1)); + break; + + case LSHIFTRT: + /* If we have (and (lshiftrt FOO C1) C2) where the combination of the + shift and AND produces only copies of the sign bit (C2 is one less + than a power of two), we can do this with just a shift. */ + + if (GET_CODE (XEXP (varop, 1)) == CONST_INT + && ((INTVAL (XEXP (varop, 1)) + + num_sign_bit_copies (XEXP (varop, 0), + GET_MODE (XEXP (varop, 0)))) + >= GET_MODE_BITSIZE (GET_MODE (varop))) + && exact_log2 (constop + 1) >= 0) + varop + = gen_rtx_combine (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), + GEN_INT (GET_MODE_BITSIZE (GET_MODE (varop)) + - exact_log2 (constop + 1))); + break; + + case NE: + /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is + included in STORE_FLAG_VALUE and FOO has no bits that might be + nonzero not in CONST. */ + if ((constop & ~ STORE_FLAG_VALUE) == 0 + && XEXP (varop, 0) == const0_rtx + && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0) + { + varop = XEXP (varop, 0); + continue; + } + break; + + case PLUS: + /* In (and (plus FOO C1) M), if M is a mask that just turns off + low-order bits (as in an alignment operation) and FOO is already + aligned to that boundary, we can convert remove this AND + and possibly the PLUS if it is now adding zero. */ + if (GET_CODE (XEXP (varop, 1)) == CONST_INT + && exact_log2 (-constop) >= 0 + && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0) + { + varop = plus_constant (XEXP (varop, 0), + INTVAL (XEXP (varop, 1)) & constop); + constop = ~0; + break; + } + + /* ... fall through ... */ + + case MINUS: + /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one + less than powers of two and M2 is narrower than M1, we can + eliminate the inner AND. This occurs when incrementing + bit fields. */ + + if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT + || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND) + SUBST (XEXP (varop, 0), + expand_compound_operation (XEXP (varop, 0))); + + if (GET_CODE (XEXP (varop, 0)) == AND + && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT + && exact_log2 (constop + 1) >= 0 + && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0 + && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0) + SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0)); + break; + } + + break; + } + + /* If we have reached a constant, this whole thing is constant. */ + if (GET_CODE (varop) == CONST_INT) + return GEN_INT (constop & INTVAL (varop)); + + /* See what bits may be nonzero in VAROP. Unlike the general case of + a call to nonzero_bits, here we don't care about bits outside + MODE. */ + + nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); + + /* Turn off all bits in the constant that are known to already be zero. + Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS + which is tested below. */ + + constop &= nonzero; + + /* If we don't have any bits left, return zero. */ + if (constop == 0) + return const0_rtx; + + /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG + if we already had one (just check for the simplest cases). */ + if (x && GET_CODE (XEXP (x, 0)) == SUBREG + && GET_MODE (XEXP (x, 0)) == mode + && SUBREG_REG (XEXP (x, 0)) == varop) + varop = XEXP (x, 0); + else + varop = gen_lowpart_for_combine (mode, varop); + + /* If we can't make the SUBREG, try to return what we were given. */ + if (GET_CODE (varop) == CLOBBER) + return x ? x : varop; + + /* If we are only masking insignificant bits, return VAROP. */ + if (constop == nonzero) + x = varop; + + /* Otherwise, return an AND. See how much, if any, of X we can use. */ + else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode) + x = gen_rtx_combine (AND, mode, varop, GEN_INT (constop)); + + else + { + if (GET_CODE (XEXP (x, 1)) != CONST_INT + || INTVAL (XEXP (x, 1)) != constop) + SUBST (XEXP (x, 1), GEN_INT (constop)); + + SUBST (XEXP (x, 0), varop); + } + + return x; +} + +/* Given an expression, X, compute which bits in X can be non-zero. + We don't care about bits outside of those defined in MODE. + + For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is + a shift, AND, or zero_extract, we can do better. */ + +static unsigned HOST_WIDE_INT +nonzero_bits (x, mode) + rtx x; + enum machine_mode mode; +{ + unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode); + unsigned HOST_WIDE_INT inner_nz; + enum rtx_code code; + int mode_width = GET_MODE_BITSIZE (mode); + rtx tem; + + /* If X is wider than MODE, use its mode instead. */ + if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width) + { + mode = GET_MODE (x); + nonzero = GET_MODE_MASK (mode); + mode_width = GET_MODE_BITSIZE (mode); + } + + if (mode_width > HOST_BITS_PER_WIDE_INT) + /* Our only callers in this case look for single bit values. So + just return the mode mask. Those tests will then be false. */ + return nonzero; + + code = GET_CODE (x); + switch (code) + { + case REG: +#ifdef STACK_BOUNDARY + /* If this is the stack pointer, we may know something about its + alignment. If PUSH_ROUNDING is defined, it is possible for the + stack to be momentarily aligned only to that amount, so we pick + the least alignment. */ + + if (x == stack_pointer_rtx) + { + int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; + +#ifdef PUSH_ROUNDING + sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment); +#endif + + return nonzero & ~ (sp_alignment - 1); + } +#endif + + /* If X is a register whose nonzero bits value is current, use it. + Otherwise, if X is a register whose value we can find, use that + value. Otherwise, use the previously-computed global nonzero bits + for this register. */ + + if (reg_last_set_value[REGNO (x)] != 0 + && reg_last_set_mode[REGNO (x)] == mode + && (reg_n_sets[REGNO (x)] == 1 + || reg_last_set_label[REGNO (x)] == label_tick) + && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) + return reg_last_set_nonzero_bits[REGNO (x)]; + + tem = get_last_value (x); + + if (tem) + { +#ifdef SHORT_IMMEDIATES_SIGN_EXTEND + /* If X is narrower than MODE and TEM is a non-negative + constant that would appear negative in the mode of X, + sign-extend it for use in reg_nonzero_bits because some + machines (maybe most) will actually do the sign-extension + and this is the conservative approach. + + ??? For 2.5, try to tighten up the MD files in this regard + instead of this kludge. */ + + if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width + && GET_CODE (tem) == CONST_INT + && INTVAL (tem) > 0 + && 0 != (INTVAL (tem) + & ((HOST_WIDE_INT) 1 + << GET_MODE_BITSIZE (GET_MODE (x))))) + tem = GEN_INT (INTVAL (tem) + | ((HOST_WIDE_INT) (-1) + << GET_MODE_BITSIZE (GET_MODE (x)))); +#endif + return nonzero_bits (tem, mode); + } + else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)]) + return reg_nonzero_bits[REGNO (x)] & nonzero; + else + return nonzero; + + case CONST_INT: +#ifdef SHORT_IMMEDIATES_SIGN_EXTEND + /* If X is negative in MODE, sign-extend the value. */ + if (INTVAL (x) > 0 + && 0 != (INTVAL (x) + & ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (GET_MODE (x))))) + return (INTVAL (x) + | ((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (GET_MODE (x)))); +#endif + + return INTVAL (x); + +#ifdef BYTE_LOADS_ZERO_EXTEND + case MEM: + /* In many, if not most, RISC machines, reading a byte from memory + zeros the rest of the register. Noticing that fact saves a lot + of extra zero-extends. */ + nonzero &= GET_MODE_MASK (GET_MODE (x)); + break; +#endif + +#if STORE_FLAG_VALUE == 1 + case EQ: case NE: + case GT: case GTU: + case LT: case LTU: + case GE: case GEU: + case LE: case LEU: + + if (GET_MODE_CLASS (mode) == MODE_INT) + nonzero = 1; + + /* A comparison operation only sets the bits given by its mode. The + rest are set undefined. */ + if (GET_MODE_SIZE (GET_MODE (x)) < mode_width) + nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x))); + break; +#endif + + case NEG: + if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) + == GET_MODE_BITSIZE (GET_MODE (x))) + nonzero = 1; + + if (GET_MODE_SIZE (GET_MODE (x)) < mode_width) + nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x))); + break; + + case ABS: + if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) + == GET_MODE_BITSIZE (GET_MODE (x))) + nonzero = 1; + break; + + case TRUNCATE: + nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode)); + break; + + case ZERO_EXTEND: + nonzero &= nonzero_bits (XEXP (x, 0), mode); + if (GET_MODE (XEXP (x, 0)) != VOIDmode) + nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); + break; + + case SIGN_EXTEND: + /* If the sign bit is known clear, this is the same as ZERO_EXTEND. + Otherwise, show all the bits in the outer mode but not the inner + may be non-zero. */ + inner_nz = nonzero_bits (XEXP (x, 0), mode); + if (GET_MODE (XEXP (x, 0)) != VOIDmode) + { + inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); + if (inner_nz & + (((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))) + inner_nz |= (GET_MODE_MASK (mode) + & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))); + } + + nonzero &= inner_nz; + break; + + case AND: + nonzero &= (nonzero_bits (XEXP (x, 0), mode) + & nonzero_bits (XEXP (x, 1), mode)); + break; + + case XOR: case IOR: + case UMIN: case UMAX: case SMIN: case SMAX: + nonzero &= (nonzero_bits (XEXP (x, 0), mode) + | nonzero_bits (XEXP (x, 1), mode)); + break; + + case PLUS: case MINUS: + case MULT: + case DIV: case UDIV: + case MOD: case UMOD: + /* We can apply the rules of arithmetic to compute the number of + high- and low-order zero bits of these operations. We start by + computing the width (position of the highest-order non-zero bit) + and the number of low-order zero bits for each value. */ + { + unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode); + unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode); + int width0 = floor_log2 (nz0) + 1; + int width1 = floor_log2 (nz1) + 1; + int low0 = floor_log2 (nz0 & -nz0); + int low1 = floor_log2 (nz1 & -nz1); + int op0_maybe_minusp = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); + int op1_maybe_minusp = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); + int result_width = mode_width; + int result_low = 0; + + switch (code) + { + case PLUS: + result_width = MAX (width0, width1) + 1; + result_low = MIN (low0, low1); + break; + case MINUS: + result_low = MIN (low0, low1); + break; + case MULT: + result_width = width0 + width1; + result_low = low0 + low1; + break; + case DIV: + if (! op0_maybe_minusp && ! op1_maybe_minusp) + result_width = width0; + break; + case UDIV: + result_width = width0; + break; + case MOD: + if (! op0_maybe_minusp && ! op1_maybe_minusp) + result_width = MIN (width0, width1); + result_low = MIN (low0, low1); + break; + case UMOD: + result_width = MIN (width0, width1); + result_low = MIN (low0, low1); + break; + } + + if (result_width < mode_width) + nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1; + + if (result_low > 0) + nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1); + } + break; + + case ZERO_EXTRACT: + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) + nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1; + break; + + case SUBREG: + /* If this is a SUBREG formed for a promoted variable that has + been zero-extended, we know that at least the high-order bits + are zero, though others might be too. */ + + if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x)) + nonzero = (GET_MODE_MASK (GET_MODE (x)) + & nonzero_bits (SUBREG_REG (x), GET_MODE (x))); + + /* If the inner mode is a single word for both the host and target + machines, we can compute this from which bits of the inner + object might be nonzero. */ + if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD + && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) + <= HOST_BITS_PER_WIDE_INT)) + { + nonzero &= nonzero_bits (SUBREG_REG (x), mode); +#ifndef BYTE_LOADS_EXTEND + /* On many CISC machines, accessing an object in a wider mode + causes the high-order bits to become undefined. So they are + not known to be zero. */ + if (GET_MODE_SIZE (GET_MODE (x)) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) + nonzero |= (GET_MODE_MASK (GET_MODE (x)) + & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))); +#endif + } + break; + + case ASHIFTRT: + case LSHIFTRT: + case ASHIFT: + case LSHIFT: + case ROTATE: + /* The nonzero bits are in two classes: any bits within MODE + that aren't in GET_MODE (x) are always significant. The rest of the + nonzero bits are those that are significant in the operand of + the shift when shifted the appropriate number of bits. This + shows that high-order bits are cleared by the right shift and + low-order bits by left shifts. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) >= 0 + && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) + { + enum machine_mode inner_mode = GET_MODE (x); + int width = GET_MODE_BITSIZE (inner_mode); + int count = INTVAL (XEXP (x, 1)); + unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode); + unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode); + unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask; + unsigned HOST_WIDE_INT outer = 0; + + if (mode_width > width) + outer = (op_nonzero & nonzero & ~ mode_mask); + + if (code == LSHIFTRT) + inner >>= count; + else if (code == ASHIFTRT) + { + inner >>= count; + + /* If the sign bit may have been nonzero before the shift, we + need to mark all the places it could have been copied to + by the shift as possibly nonzero. */ + if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count))) + inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count); + } + else if (code == LSHIFT || code == ASHIFT) + inner <<= count; + else + inner = ((inner << (count % width) + | (inner >> (width - (count % width)))) & mode_mask); + + nonzero &= (outer | inner); + } + break; + + case FFS: + /* This is at most the number of bits in the mode. */ + nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1; + break; + + case IF_THEN_ELSE: + nonzero &= (nonzero_bits (XEXP (x, 1), mode) + | nonzero_bits (XEXP (x, 2), mode)); + break; + } + + return nonzero; +} + +/* Return the number of bits at the high-order end of X that are known to + be equal to the sign bit. This number will always be between 1 and + the number of bits in the mode of X. MODE is the mode to be used + if X is VOIDmode. */ + +static int +num_sign_bit_copies (x, mode) + rtx x; + enum machine_mode mode; +{ + enum rtx_code code = GET_CODE (x); + int bitwidth; + int num0, num1, result; + unsigned HOST_WIDE_INT nonzero; + rtx tem; + + /* If we weren't given a mode, use the mode of X. If the mode is still + VOIDmode, we don't know anything. */ + + if (mode == VOIDmode) + mode = GET_MODE (x); + + if (mode == VOIDmode) + return 1; + + bitwidth = GET_MODE_BITSIZE (mode); + + switch (code) + { + case REG: + + if (reg_last_set_value[REGNO (x)] != 0 + && reg_last_set_mode[REGNO (x)] == mode + && (reg_n_sets[REGNO (x)] == 1 + || reg_last_set_label[REGNO (x)] == label_tick) + && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) + return reg_last_set_sign_bit_copies[REGNO (x)]; + + tem = get_last_value (x); + if (tem != 0) + return num_sign_bit_copies (tem, mode); + + if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0) + return reg_sign_bit_copies[REGNO (x)]; + break; + +#ifdef BYTE_LOADS_SIGN_EXTEND + case MEM: + /* Some RISC machines sign-extend all loads of smaller than a word. */ + return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1); +#endif + + case CONST_INT: + /* If the constant is negative, take its 1's complement and remask. + Then see how many zero bits we have. */ + nonzero = INTVAL (x) & GET_MODE_MASK (mode); + if (bitwidth <= HOST_BITS_PER_WIDE_INT + && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) + nonzero = (~ nonzero) & GET_MODE_MASK (mode); + + return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); + + case SUBREG: + /* If this is a SUBREG for a promoted object that is sign-extended + and we are looking at it in a wider mode, we know that at least the + high-order bits are known to be sign bit copies. */ + + if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x)) + return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1, + num_sign_bit_copies (SUBREG_REG (x), mode)); + + /* For a smaller object, just ignore the high bits. */ + if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))) + { + num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode); + return MAX (1, (num0 + - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) + - bitwidth))); + } + +#ifdef BYTE_LOADS_EXTEND + /* For paradoxical SUBREGs, just look inside since, on machines with + one of these defined, we assume that operations are actually + performed on the full register. Note that we are passing MODE + to the recursive call, so the number of sign bit copies will + remain relative to that mode, not the inner mode. */ + + if (GET_MODE_SIZE (GET_MODE (x)) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) + return num_sign_bit_copies (SUBREG_REG (x), mode); +#endif + + break; + + case SIGN_EXTRACT: + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + return MAX (1, bitwidth - INTVAL (XEXP (x, 1))); + break; + + case SIGN_EXTEND: + return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) + + num_sign_bit_copies (XEXP (x, 0), VOIDmode)); + + case TRUNCATE: + /* For a smaller object, just ignore the high bits. */ + num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode); + return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) + - bitwidth))); + + case NOT: + return num_sign_bit_copies (XEXP (x, 0), mode); + + case ROTATE: case ROTATERT: + /* If we are rotating left by a number of bits less than the number + of sign bit copies, we can just subtract that amount from the + number. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth) + { + num0 = num_sign_bit_copies (XEXP (x, 0), mode); + return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1)) + : bitwidth - INTVAL (XEXP (x, 1)))); + } + break; + + case NEG: + /* In general, this subtracts one sign bit copy. But if the value + is known to be positive, the number of sign bit copies is the + same as that of the input. Finally, if the input has just one bit + that might be nonzero, all the bits are copies of the sign bit. */ + nonzero = nonzero_bits (XEXP (x, 0), mode); + if (nonzero == 1) + return bitwidth; + + num0 = num_sign_bit_copies (XEXP (x, 0), mode); + if (num0 > 1 + && bitwidth <= HOST_BITS_PER_WIDE_INT + && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero)) + num0--; + + return num0; + + case IOR: case AND: case XOR: + case SMIN: case SMAX: case UMIN: case UMAX: + /* Logical operations will preserve the number of sign-bit copies. + MIN and MAX operations always return one of the operands. */ + num0 = num_sign_bit_copies (XEXP (x, 0), mode); + num1 = num_sign_bit_copies (XEXP (x, 1), mode); + return MIN (num0, num1); + + case PLUS: case MINUS: + /* For addition and subtraction, we can have a 1-bit carry. However, + if we are subtracting 1 from a positive number, there will not + be such a carry. Furthermore, if the positive number is known to + be 0 or 1, we know the result is either -1 or 0. */ + + if (code == PLUS && XEXP (x, 1) == constm1_rtx + && bitwidth <= HOST_BITS_PER_WIDE_INT) + { + nonzero = nonzero_bits (XEXP (x, 0), mode); + if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0) + return (nonzero == 1 || nonzero == 0 ? bitwidth + : bitwidth - floor_log2 (nonzero) - 1); + } + + num0 = num_sign_bit_copies (XEXP (x, 0), mode); + num1 = num_sign_bit_copies (XEXP (x, 1), mode); + return MAX (1, MIN (num0, num1) - 1); + + case MULT: + /* The number of bits of the product is the sum of the number of + bits of both terms. However, unless one of the terms if known + to be positive, we must allow for an additional bit since negating + a negative number can remove one sign bit copy. */ + + num0 = num_sign_bit_copies (XEXP (x, 0), mode); + num1 = num_sign_bit_copies (XEXP (x, 1), mode); + + result = bitwidth - (bitwidth - num0) - (bitwidth - num1); + if (result > 0 + && bitwidth <= HOST_BITS_PER_WIDE_INT + && ((nonzero_bits (XEXP (x, 0), mode) + & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) + && (nonzero_bits (XEXP (x, 1), mode) + & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0)) + result--; + + return MAX (1, result); + + case UDIV: + /* The result must be <= the first operand. */ + return num_sign_bit_copies (XEXP (x, 0), mode); + + case UMOD: + /* The result must be <= the scond operand. */ + return num_sign_bit_copies (XEXP (x, 1), mode); + + case DIV: + /* Similar to unsigned division, except that we have to worry about + the case where the divisor is negative, in which case we have + to add 1. */ + result = num_sign_bit_copies (XEXP (x, 0), mode); + if (result > 1 + && bitwidth <= HOST_BITS_PER_WIDE_INT + && (nonzero_bits (XEXP (x, 1), mode) + & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) + result --; + + return result; + + case MOD: + result = num_sign_bit_copies (XEXP (x, 1), mode); + if (result > 1 + && bitwidth <= HOST_BITS_PER_WIDE_INT + && (nonzero_bits (XEXP (x, 1), mode) + & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) + result --; + + return result; + + case ASHIFTRT: + /* Shifts by a constant add to the number of bits equal to the + sign bit. */ + num0 = num_sign_bit_copies (XEXP (x, 0), mode); + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) > 0) + num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1))); + + return num0; + + case ASHIFT: + case LSHIFT: + /* Left shifts destroy copies. */ + if (GET_CODE (XEXP (x, 1)) != CONST_INT + || INTVAL (XEXP (x, 1)) < 0 + || INTVAL (XEXP (x, 1)) >= bitwidth) + return 1; + + num0 = num_sign_bit_copies (XEXP (x, 0), mode); + return MAX (1, num0 - INTVAL (XEXP (x, 1))); + + case IF_THEN_ELSE: + num0 = num_sign_bit_copies (XEXP (x, 1), mode); + num1 = num_sign_bit_copies (XEXP (x, 2), mode); + return MIN (num0, num1); + +#if STORE_FLAG_VALUE == -1 + case EQ: case NE: case GE: case GT: case LE: case LT: + case GEU: case GTU: case LEU: case LTU: + return bitwidth; +#endif + } + + /* If we haven't been able to figure it out by one of the above rules, + see if some of the high-order bits are known to be zero. If so, + count those bits and return one less than that amount. If we can't + safely compute the mask for this mode, always return BITWIDTH. */ + + if (bitwidth > HOST_BITS_PER_WIDE_INT) + return 1; + + nonzero = nonzero_bits (x, mode); + return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) + ? 1 : bitwidth - floor_log2 (nonzero) - 1); +} + +/* Return the number of "extended" bits there are in X, when interpreted + as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For + unsigned quantities, this is the number of high-order zero bits. + For signed quantities, this is the number of copies of the sign bit + minus 1. In both case, this function returns the number of "spare" + bits. For example, if two quantities for which this function returns + at least 1 are added, the addition is known not to overflow. + + This function will always return 0 unless called during combine, which + implies that it must be called from a define_split. */ + +int +extended_count (x, mode, unsignedp) + rtx x; + enum machine_mode mode; + int unsignedp; +{ + if (nonzero_sign_valid == 0) + return 0; + + return (unsignedp + ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && (GET_MODE_BITSIZE (mode) - 1 + - floor_log2 (nonzero_bits (x, mode)))) + : num_sign_bit_copies (x, mode) - 1); +} + +/* This function is called from `simplify_shift_const' to merge two + outer operations. Specifically, we have already found that we need + to perform operation *POP0 with constant *PCONST0 at the outermost + position. We would now like to also perform OP1 with constant CONST1 + (with *POP0 being done last). + + Return 1 if we can do the operation and update *POP0 and *PCONST0 with + the resulting operation. *PCOMP_P is set to 1 if we would need to + complement the innermost operand, otherwise it is unchanged. + + MODE is the mode in which the operation will be done. No bits outside + the width of this mode matter. It is assumed that the width of this mode + is smaller than or equal to HOST_BITS_PER_WIDE_INT. + + If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS, + IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper + result is simply *PCONST0. + + If the resulting operation cannot be expressed as one operation, we + return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ + +static int +merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p) + enum rtx_code *pop0; + HOST_WIDE_INT *pconst0; + enum rtx_code op1; + HOST_WIDE_INT const1; + enum machine_mode mode; + int *pcomp_p; +{ + enum rtx_code op0 = *pop0; + HOST_WIDE_INT const0 = *pconst0; + + const0 &= GET_MODE_MASK (mode); + const1 &= GET_MODE_MASK (mode); + + /* If OP0 is an AND, clear unimportant bits in CONST1. */ + if (op0 == AND) + const1 &= const0; + + /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or + if OP0 is SET. */ + + if (op1 == NIL || op0 == SET) + return 1; + + else if (op0 == NIL) + op0 = op1, const0 = const1; + + else if (op0 == op1) + { + switch (op0) + { + case AND: + const0 &= const1; + break; + case IOR: + const0 |= const1; + break; + case XOR: + const0 ^= const1; + break; + case PLUS: + const0 += const1; + break; + case NEG: + op0 = NIL; + break; + } + } + + /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ + else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) + return 0; + + /* If the two constants aren't the same, we can't do anything. The + remaining six cases can all be done. */ + else if (const0 != const1) + return 0; + + else + switch (op0) + { + case IOR: + if (op1 == AND) + /* (a & b) | b == b */ + op0 = SET; + else /* op1 == XOR */ + /* (a ^ b) | b == a | b */ + ; + break; + + case XOR: + if (op1 == AND) + /* (a & b) ^ b == (~a) & b */ + op0 = AND, *pcomp_p = 1; + else /* op1 == IOR */ + /* (a | b) ^ b == a & ~b */ + op0 = AND, *pconst0 = ~ const0; + break; + + case AND: + if (op1 == IOR) + /* (a | b) & b == b */ + op0 = SET; + else /* op1 == XOR */ + /* (a ^ b) & b) == (~a) & b */ + *pcomp_p = 1; + break; + } + + /* Check for NO-OP cases. */ + const0 &= GET_MODE_MASK (mode); + if (const0 == 0 + && (op0 == IOR || op0 == XOR || op0 == PLUS)) + op0 = NIL; + else if (const0 == 0 && op0 == AND) + op0 = SET; + else if (const0 == GET_MODE_MASK (mode) && op0 == AND) + op0 = NIL; + + *pop0 = op0; + *pconst0 = const0; + + return 1; +} + +/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. + The result of the shift is RESULT_MODE. X, if non-zero, is an expression + that we started with. + + The shift is normally computed in the widest mode we find in VAROP, as + long as it isn't a different number of words than RESULT_MODE. Exceptions + are ASHIFTRT and ROTATE, which are always done in their original mode, */ + +static rtx +simplify_shift_const (x, code, result_mode, varop, count) + rtx x; + enum rtx_code code; + enum machine_mode result_mode; + rtx varop; + int count; +{ + enum rtx_code orig_code = code; + int orig_count = count; + enum machine_mode mode = result_mode; + enum machine_mode shift_mode, tmode; + int mode_words + = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; + /* We form (outer_op (code varop count) (outer_const)). */ + enum rtx_code outer_op = NIL; + HOST_WIDE_INT outer_const; + rtx const_rtx; + int complement_p = 0; + rtx new; + + /* If we were given an invalid count, don't do anything except exactly + what was requested. */ + + if (count < 0 || count > GET_MODE_BITSIZE (mode)) + { + if (x) + return x; + + return gen_rtx (code, mode, varop, GEN_INT (count)); + } + + /* Unless one of the branches of the `if' in this loop does a `continue', + we will `break' the loop after the `if'. */ + + while (count != 0) + { + /* If we have an operand of (clobber (const_int 0)), just return that + value. */ + if (GET_CODE (varop) == CLOBBER) + return varop; + + /* If we discovered we had to complement VAROP, leave. Making a NOT + here would cause an infinite loop. */ + if (complement_p) + break; + + /* Convert ROTATETRT to ROTATE. */ + if (code == ROTATERT) + code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count; + + /* Canonicalize LSHIFT to ASHIFT. */ + if (code == LSHIFT) + code = ASHIFT; + + /* We need to determine what mode we will do the shift in. If the + shift is a ASHIFTRT or ROTATE, we must always do it in the mode it + was originally done in. Otherwise, we can do it in MODE, the widest + mode encountered. */ + shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode); + + /* Handle cases where the count is greater than the size of the mode + minus 1. For ASHIFT, use the size minus one as the count (this can + occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, + take the count modulo the size. For other shifts, the result is + zero. + + Since these shifts are being produced by the compiler by combining + multiple operations, each of which are defined, we know what the + result is supposed to be. */ + + if (count > GET_MODE_BITSIZE (shift_mode) - 1) + { + if (code == ASHIFTRT) + count = GET_MODE_BITSIZE (shift_mode) - 1; + else if (code == ROTATE || code == ROTATERT) + count %= GET_MODE_BITSIZE (shift_mode); + else + { + /* We can't simply return zero because there may be an + outer op. */ + varop = const0_rtx; + count = 0; + break; + } + } + + /* Negative counts are invalid and should not have been made (a + programmer-specified negative count should have been handled + above). */ + else if (count < 0) + abort (); + + /* An arithmetic right shift of a quantity known to be -1 or 0 + is a no-op. */ + if (code == ASHIFTRT + && (num_sign_bit_copies (varop, shift_mode) + == GET_MODE_BITSIZE (shift_mode))) + { + count = 0; + break; + } + + /* If we are doing an arithmetic right shift and discarding all but + the sign bit copies, this is equivalent to doing a shift by the + bitsize minus one. Convert it into that shift because it will often + allow other simplifications. */ + + if (code == ASHIFTRT + && (count + num_sign_bit_copies (varop, shift_mode) + >= GET_MODE_BITSIZE (shift_mode))) + count = GET_MODE_BITSIZE (shift_mode) - 1; + + /* We simplify the tests below and elsewhere by converting + ASHIFTRT to LSHIFTRT if we know the sign bit is clear. + `make_compound_operation' will convert it to a ASHIFTRT for + those machines (such as Vax) that don't have a LSHIFTRT. */ + if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT + && code == ASHIFTRT + && ((nonzero_bits (varop, shift_mode) + & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) + == 0)) + code = LSHIFTRT; + + switch (GET_CODE (varop)) + { + case SIGN_EXTEND: + case ZERO_EXTEND: + case SIGN_EXTRACT: + case ZERO_EXTRACT: + new = expand_compound_operation (varop); + if (new != varop) + { + varop = new; + continue; + } + break; + + case MEM: + /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH + minus the width of a smaller mode, we can do this with a + SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ + if ((code == ASHIFTRT || code == LSHIFTRT) + && ! mode_dependent_address_p (XEXP (varop, 0)) + && ! MEM_VOLATILE_P (varop) + && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, + MODE_INT, 1)) != BLKmode) + { +#if BYTES_BIG_ENDIAN + new = gen_rtx (MEM, tmode, XEXP (varop, 0)); +#else + new = gen_rtx (MEM, tmode, + plus_constant (XEXP (varop, 0), + count / BITS_PER_UNIT)); + RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop); + MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop); + MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop); +#endif + varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND + : ZERO_EXTEND, mode, new); + count = 0; + continue; + } + break; + + case USE: + /* Similar to the case above, except that we can only do this if + the resulting mode is the same as that of the underlying + MEM and adjust the address depending on the *bits* endianness + because of the way that bit-field extract insns are defined. */ + if ((code == ASHIFTRT || code == LSHIFTRT) + && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, + MODE_INT, 1)) != BLKmode + && tmode == GET_MODE (XEXP (varop, 0))) + { +#if BITS_BIG_ENDIAN + new = XEXP (varop, 0); +#else + new = copy_rtx (XEXP (varop, 0)); + SUBST (XEXP (new, 0), + plus_constant (XEXP (new, 0), + count / BITS_PER_UNIT)); +#endif + + varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND + : ZERO_EXTEND, mode, new); + count = 0; + continue; + } + break; + + case SUBREG: + /* If VAROP is a SUBREG, strip it as long as the inner operand has + the same number of words as what we've seen so far. Then store + the widest mode in MODE. */ + if (subreg_lowpart_p (varop) + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) + > GET_MODE_SIZE (GET_MODE (varop))) + && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) + + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) + == mode_words)) + { + varop = SUBREG_REG (varop); + if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) + mode = GET_MODE (varop); + continue; + } + break; + + case MULT: + /* Some machines use MULT instead of ASHIFT because MULT + is cheaper. But it is still better on those machines to + merge two shifts into one. */ + if (GET_CODE (XEXP (varop, 1)) == CONST_INT + && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) + { + varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0), + GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));; + continue; + } + break; + + case UDIV: + /* Similar, for when divides are cheaper. */ + if (GET_CODE (XEXP (varop, 1)) == CONST_INT + && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) + { + varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), + GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1))))); + continue; + } + break; + + case ASHIFTRT: + /* If we are extracting just the sign bit of an arithmetic right + shift, that shift is not needed. */ + if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1) + { + varop = XEXP (varop, 0); + continue; + } + + /* ... fall through ... */ + + case LSHIFTRT: + case ASHIFT: + case LSHIFT: + case ROTATE: + /* Here we have two nested shifts. The result is usually the + AND of a new shift with a mask. We compute the result below. */ + if (GET_CODE (XEXP (varop, 1)) == CONST_INT + && INTVAL (XEXP (varop, 1)) >= 0 + && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) + && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) + { + enum rtx_code first_code = GET_CODE (varop); + int first_count = INTVAL (XEXP (varop, 1)); + unsigned HOST_WIDE_INT mask; + rtx mask_rtx; + rtx inner; + + if (first_code == LSHIFT) + first_code = ASHIFT; + + /* We have one common special case. We can't do any merging if + the inner code is an ASHIFTRT of a smaller mode. However, if + we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) + with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), + we can convert it to + (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). + This simplifies certain SIGN_EXTEND operations. */ + if (code == ASHIFT && first_code == ASHIFTRT + && (GET_MODE_BITSIZE (result_mode) + - GET_MODE_BITSIZE (GET_MODE (varop))) == count) + { + /* C3 has the low-order C1 bits zero. */ + + mask = (GET_MODE_MASK (mode) + & ~ (((HOST_WIDE_INT) 1 << first_count) - 1)); + + varop = simplify_and_const_int (NULL_RTX, result_mode, + XEXP (varop, 0), mask); + varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, + varop, count); + count = first_count; + code = ASHIFTRT; + continue; + } + + /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more + than C1 high-order bits equal to the sign bit, we can convert + this to either an ASHIFT or a ASHIFTRT depending on the + two counts. + + We cannot do this if VAROP's mode is not SHIFT_MODE. */ + + if (code == ASHIFTRT && first_code == ASHIFT + && GET_MODE (varop) == shift_mode + && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) + > first_count)) + { + count -= first_count; + if (count < 0) + count = - count, code = ASHIFT; + varop = XEXP (varop, 0); + continue; + } + + /* There are some cases we can't do. If CODE is ASHIFTRT, + we can only do this if FIRST_CODE is also ASHIFTRT. + + We can't do the case when CODE is ROTATE and FIRST_CODE is + ASHIFTRT. + + If the mode of this shift is not the mode of the outer shift, + we can't do this if either shift is ASHIFTRT or ROTATE. + + Finally, we can't do any of these if the mode is too wide + unless the codes are the same. + + Handle the case where the shift codes are the same + first. */ + + if (code == first_code) + { + if (GET_MODE (varop) != result_mode + && (code == ASHIFTRT || code == ROTATE)) + break; + + count += first_count; + varop = XEXP (varop, 0); + continue; + } + + if (code == ASHIFTRT + || (code == ROTATE && first_code == ASHIFTRT) + || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT + || (GET_MODE (varop) != result_mode + && (first_code == ASHIFTRT || first_code == ROTATE + || code == ROTATE))) + break; + + /* To compute the mask to apply after the shift, shift the + nonzero bits of the inner shift the same way the + outer shift will. */ + + mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); + + mask_rtx + = simplify_binary_operation (code, result_mode, mask_rtx, + GEN_INT (count)); + + /* Give up if we can't compute an outer operation to use. */ + if (mask_rtx == 0 + || GET_CODE (mask_rtx) != CONST_INT + || ! merge_outer_ops (&outer_op, &outer_const, AND, + INTVAL (mask_rtx), + result_mode, &complement_p)) + break; + + /* If the shifts are in the same direction, we add the + counts. Otherwise, we subtract them. */ + if ((code == ASHIFTRT || code == LSHIFTRT) + == (first_code == ASHIFTRT || first_code == LSHIFTRT)) + count += first_count; + else + count -= first_count; + + /* If COUNT is positive, the new shift is usually CODE, + except for the two exceptions below, in which case it is + FIRST_CODE. If the count is negative, FIRST_CODE should + always be used */ + if (count > 0 + && ((first_code == ROTATE && code == ASHIFT) + || (first_code == ASHIFTRT && code == LSHIFTRT))) + code = first_code; + else if (count < 0) + code = first_code, count = - count; + + varop = XEXP (varop, 0); + continue; + } + + /* If we have (A << B << C) for any shift, we can convert this to + (A << C << B). This wins if A is a constant. Only try this if + B is not a constant. */ + + else if (GET_CODE (varop) == code + && GET_CODE (XEXP (varop, 1)) != CONST_INT + && 0 != (new + = simplify_binary_operation (code, mode, + XEXP (varop, 0), + GEN_INT (count)))) + { + varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1)); + count = 0; + continue; + } + break; + + case NOT: + /* Make this fit the case below. */ + varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0), + GEN_INT (GET_MODE_MASK (mode))); + continue; + + case IOR: + case AND: + case XOR: + /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) + with C the size of VAROP - 1 and the shift is logical if + STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, + we have an (le X 0) operation. If we have an arithmetic shift + and STORE_FLAG_VALUE is 1 or we have a logical shift with + STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ + + if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS + && XEXP (XEXP (varop, 0), 1) == constm1_rtx + && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) + && (code == LSHIFTRT || code == ASHIFTRT) + && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 + && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) + { + count = 0; + varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1), + const0_rtx); + + if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) + varop = gen_rtx_combine (NEG, GET_MODE (varop), varop); + + continue; + } + + /* If we have (shift (logical)), move the logical to the outside + to allow it to possibly combine with another logical and the + shift to combine with another shift. This also canonicalizes to + what a ZERO_EXTRACT looks like. Also, some machines have + (and (shift)) insns. */ + + if (GET_CODE (XEXP (varop, 1)) == CONST_INT + && (new = simplify_binary_operation (code, result_mode, + XEXP (varop, 1), + GEN_INT (count))) != 0 + && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), + INTVAL (new), result_mode, &complement_p)) + { + varop = XEXP (varop, 0); + continue; + } + + /* If we can't do that, try to simplify the shift in each arm of the + logical expression, make a new logical expression, and apply + the inverse distributive law. */ + { + rtx lhs = simplify_shift_const (NULL_RTX, code, result_mode, + XEXP (varop, 0), count); + rtx rhs = simplify_shift_const (NULL_RTX, code, result_mode, + XEXP (varop, 1), count); + + varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs); + varop = apply_distributive_law (varop); + + count = 0; + } + break; + + case EQ: + /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE + says that the sign bit can be tested, FOO has mode MODE, C is + GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit + may be nonzero. */ + if (code == LSHIFT + && XEXP (varop, 1) == const0_rtx + && GET_MODE (XEXP (varop, 0)) == result_mode + && count == GET_MODE_BITSIZE (result_mode) - 1 + && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT + && ((STORE_FLAG_VALUE + & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1)))) + && nonzero_bits (XEXP (varop, 0), result_mode) == 1 + && merge_outer_ops (&outer_op, &outer_const, XOR, + (HOST_WIDE_INT) 1, result_mode, + &complement_p)) + { + varop = XEXP (varop, 0); + count = 0; + continue; + } + break; + + case NEG: + /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less + than the number of bits in the mode is equivalent to A. */ + if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 + && nonzero_bits (XEXP (varop, 0), result_mode) == 1) + { + varop = XEXP (varop, 0); + count = 0; + continue; + } + + /* NEG commutes with ASHIFT since it is multiplication. Move the + NEG outside to allow shifts to combine. */ + if (code == ASHIFT + && merge_outer_ops (&outer_op, &outer_const, NEG, + (HOST_WIDE_INT) 0, result_mode, + &complement_p)) + { + varop = XEXP (varop, 0); + continue; + } + break; + + case PLUS: + /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C + is one less than the number of bits in the mode is + equivalent to (xor A 1). */ + if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 + && XEXP (varop, 1) == constm1_rtx + && nonzero_bits (XEXP (varop, 0), result_mode) == 1 + && merge_outer_ops (&outer_op, &outer_const, XOR, + (HOST_WIDE_INT) 1, result_mode, + &complement_p)) + { + count = 0; + varop = XEXP (varop, 0); + continue; + } + + /* If we have (xshiftrt (plus FOO BAR) C), and the only bits + that might be nonzero in BAR are those being shifted out and those + bits are known zero in FOO, we can replace the PLUS with FOO. + Similarly in the other operand order. This code occurs when + we are computing the size of a variable-size array. */ + + if ((code == ASHIFTRT || code == LSHIFTRT) + && count < HOST_BITS_PER_WIDE_INT + && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 + && (nonzero_bits (XEXP (varop, 1), result_mode) + & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) + { + varop = XEXP (varop, 0); + continue; + } + else if ((code == ASHIFTRT || code == LSHIFTRT) + && count < HOST_BITS_PER_WIDE_INT + && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT + && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) + >> count) + && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) + & nonzero_bits (XEXP (varop, 1), + result_mode))) + { + varop = XEXP (varop, 1); + continue; + } + + /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ + if (code == ASHIFT + && GET_CODE (XEXP (varop, 1)) == CONST_INT + && (new = simplify_binary_operation (ASHIFT, result_mode, + XEXP (varop, 1), + GEN_INT (count))) != 0 + && merge_outer_ops (&outer_op, &outer_const, PLUS, + INTVAL (new), result_mode, &complement_p)) + { + varop = XEXP (varop, 0); + continue; + } + break; + + case MINUS: + /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) + with C the size of VAROP - 1 and the shift is logical if + STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, + we have a (gt X 0) operation. If the shift is arithmetic with + STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, + we have a (neg (gt X 0)) operation. */ + + if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT + && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 + && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) + && (code == LSHIFTRT || code == ASHIFTRT) + && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (varop, 0), 1)) == count + && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) + { + count = 0; + varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1), + const0_rtx); + + if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) + varop = gen_rtx_combine (NEG, GET_MODE (varop), varop); + + continue; + } + break; + } + + break; + } + + /* We need to determine what mode to do the shift in. If the shift is + a ASHIFTRT or ROTATE, we must always do it in the mode it was originally + done in. Otherwise, we can do it in MODE, the widest mode encountered. + The code we care about is that of the shift that will actually be done, + not the shift that was originally requested. */ + shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode); + + /* We have now finished analyzing the shift. The result should be + a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If + OUTER_OP is non-NIL, it is an operation that needs to be applied + to the result of the shift. OUTER_CONST is the relevant constant, + but we must turn off all bits turned off in the shift. + + If we were passed a value for X, see if we can use any pieces of + it. If not, make new rtx. */ + + if (x && GET_RTX_CLASS (GET_CODE (x)) == '2' + && GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) == count) + const_rtx = XEXP (x, 1); + else + const_rtx = GEN_INT (count); + + if (x && GET_CODE (XEXP (x, 0)) == SUBREG + && GET_MODE (XEXP (x, 0)) == shift_mode + && SUBREG_REG (XEXP (x, 0)) == varop) + varop = XEXP (x, 0); + else if (GET_MODE (varop) != shift_mode) + varop = gen_lowpart_for_combine (shift_mode, varop); + + /* If we can't make the SUBREG, try to return what we were given. */ + if (GET_CODE (varop) == CLOBBER) + return x ? x : varop; + + new = simplify_binary_operation (code, shift_mode, varop, const_rtx); + if (new != 0) + x = new; + else + { + if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode) + x = gen_rtx_combine (code, shift_mode, varop, const_rtx); + + SUBST (XEXP (x, 0), varop); + SUBST (XEXP (x, 1), const_rtx); + } + + /* If we were doing a LSHIFTRT in a wider mode than it was originally, + turn off all the bits that the shift would have turned off. */ + if (orig_code == LSHIFTRT && result_mode != shift_mode) + x = simplify_and_const_int (NULL_RTX, shift_mode, x, + GET_MODE_MASK (result_mode) >> orig_count); + + /* Do the remainder of the processing in RESULT_MODE. */ + x = gen_lowpart_for_combine (result_mode, x); + + /* If COMPLEMENT_P is set, we have to complement X before doing the outer + operation. */ + if (complement_p) + x = gen_unary (NOT, result_mode, x); + + if (outer_op != NIL) + { + if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) + outer_const &= GET_MODE_MASK (result_mode); + + if (outer_op == AND) + x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); + else if (outer_op == SET) + /* This means that we have determined that the result is + equivalent to a constant. This should be rare. */ + x = GEN_INT (outer_const); + else if (GET_RTX_CLASS (outer_op) == '1') + x = gen_unary (outer_op, result_mode, x); + else + x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const)); + } + + return x; +} + +/* Like recog, but we receive the address of a pointer to a new pattern. + We try to match the rtx that the pointer points to. + If that fails, we may try to modify or replace the pattern, + storing the replacement into the same pointer object. + + Modifications include deletion or addition of CLOBBERs. + + PNOTES is a pointer to a location where any REG_UNUSED notes added for + the CLOBBERs are placed. + + The value is the final insn code from the pattern ultimately matched, + or -1. */ + +static int +recog_for_combine (pnewpat, insn, pnotes) + rtx *pnewpat; + rtx insn; + rtx *pnotes; +{ + register rtx pat = *pnewpat; + int insn_code_number; + int num_clobbers_to_add = 0; + int i; + rtx notes = 0; + + /* Is the result of combination a valid instruction? */ + insn_code_number = recog (pat, insn, &num_clobbers_to_add); + + /* If it isn't, there is the possibility that we previously had an insn + that clobbered some register as a side effect, but the combined + insn doesn't need to do that. So try once more without the clobbers + unless this represents an ASM insn. */ + + if (insn_code_number < 0 && ! check_asm_operands (pat) + && GET_CODE (pat) == PARALLEL) + { + int pos; + + for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) + if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) + { + if (i != pos) + SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); + pos++; + } + + SUBST_INT (XVECLEN (pat, 0), pos); + + if (pos == 1) + pat = XVECEXP (pat, 0, 0); + + insn_code_number = recog (pat, insn, &num_clobbers_to_add); + } + + /* If we had any clobbers to add, make a new pattern than contains + them. Then check to make sure that all of them are dead. */ + if (num_clobbers_to_add) + { + rtx newpat = gen_rtx (PARALLEL, VOIDmode, + gen_rtvec (GET_CODE (pat) == PARALLEL + ? XVECLEN (pat, 0) + num_clobbers_to_add + : num_clobbers_to_add + 1)); + + if (GET_CODE (pat) == PARALLEL) + for (i = 0; i < XVECLEN (pat, 0); i++) + XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); + else + XVECEXP (newpat, 0, 0) = pat; + + add_clobbers (newpat, insn_code_number); + + for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; + i < XVECLEN (newpat, 0); i++) + { + if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG + && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) + return -1; + notes = gen_rtx (EXPR_LIST, REG_UNUSED, + XEXP (XVECEXP (newpat, 0, i), 0), notes); + } + pat = newpat; + } + + *pnewpat = pat; + *pnotes = notes; + + return insn_code_number; +} + +/* Like gen_lowpart but for use by combine. In combine it is not possible + to create any new pseudoregs. However, it is safe to create + invalid memory addresses, because combine will try to recognize + them and all they will do is make the combine attempt fail. + + If for some reason this cannot do its job, an rtx + (clobber (const_int 0)) is returned. + An insn containing that will not be recognized. */ + +#undef gen_lowpart + +static rtx +gen_lowpart_for_combine (mode, x) + enum machine_mode mode; + register rtx x; +{ + rtx result; + + if (GET_MODE (x) == mode) + return x; + + /* We can only support MODE being wider than a word if X is a + constant integer or has a mode the same size. */ + + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD + && ! ((GET_MODE (x) == VOIDmode + && (GET_CODE (x) == CONST_INT + || GET_CODE (x) == CONST_DOUBLE)) + || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode))) + return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); + + /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart + won't know what to do. So we will strip off the SUBREG here and + process normally. */ + if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM) + { + x = SUBREG_REG (x); + if (GET_MODE (x) == mode) + return x; + } + + result = gen_lowpart_common (mode, x); + if (result) + return result; + + if (GET_CODE (x) == MEM) + { + register int offset = 0; + rtx new; + + /* Refuse to work on a volatile memory ref or one with a mode-dependent + address. */ + if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) + return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); + + /* If we want to refer to something bigger than the original memref, + generate a perverse subreg instead. That will force a reload + of the original memref X. */ + if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)) + return gen_rtx (SUBREG, mode, x, 0); + +#if WORDS_BIG_ENDIAN + offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) + - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); +#endif +#if BYTES_BIG_ENDIAN + /* Adjust the address so that the address-after-the-data + is unchanged. */ + offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) + - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); +#endif + new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset)); + RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x); + MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x); + MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x); + return new; + } + + /* If X is a comparison operator, rewrite it in a new mode. This + probably won't match, but may allow further simplifications. */ + else if (GET_RTX_CLASS (GET_CODE (x)) == '<') + return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1)); + + /* If we couldn't simplify X any other way, just enclose it in a + SUBREG. Normally, this SUBREG won't match, but some patterns may + include an explicit SUBREG or we may simplify it further in combine. */ + else + { + int word = 0; + + if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) + word = ((GET_MODE_SIZE (GET_MODE (x)) + - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) + / UNITS_PER_WORD); + return gen_rtx (SUBREG, mode, x, word); + } +} + +/* Make an rtx expression. This is a subset of gen_rtx and only supports + expressions of 1, 2, or 3 operands, each of which are rtx expressions. + + If the identical expression was previously in the insn (in the undobuf), + it will be returned. Only if it is not found will a new expression + be made. */ + +/*VARARGS2*/ +static rtx +gen_rtx_combine (va_alist) + va_dcl +{ + va_list p; + enum rtx_code code; + enum machine_mode mode; + int n_args; + rtx args[3]; + int i, j; + char *fmt; + rtx rt; + + va_start (p); + code = va_arg (p, enum rtx_code); + mode = va_arg (p, enum machine_mode); + n_args = GET_RTX_LENGTH (code); + fmt = GET_RTX_FORMAT (code); + + if (n_args == 0 || n_args > 3) + abort (); + + /* Get each arg and verify that it is supposed to be an expression. */ + for (j = 0; j < n_args; j++) + { + if (*fmt++ != 'e') + abort (); + + args[j] = va_arg (p, rtx); + } + + /* See if this is in undobuf. Be sure we don't use objects that came + from another insn; this could produce circular rtl structures. */ + + for (i = previous_num_undos; i < undobuf.num_undo; i++) + if (!undobuf.undo[i].is_int + && GET_CODE (undobuf.undo[i].old_contents.rtx) == code + && GET_MODE (undobuf.undo[i].old_contents.rtx) == mode) + { + for (j = 0; j < n_args; j++) + if (XEXP (undobuf.undo[i].old_contents.rtx, j) != args[j]) + break; + + if (j == n_args) + return undobuf.undo[i].old_contents.rtx; + } + + /* Otherwise make a new rtx. We know we have 1, 2, or 3 args. + Use rtx_alloc instead of gen_rtx because it's faster on RISC. */ + rt = rtx_alloc (code); + PUT_MODE (rt, mode); + XEXP (rt, 0) = args[0]; + if (n_args > 1) + { + XEXP (rt, 1) = args[1]; + if (n_args > 2) + XEXP (rt, 2) = args[2]; + } + return rt; +} + +/* These routines make binary and unary operations by first seeing if they + fold; if not, a new expression is allocated. */ + +static rtx +gen_binary (code, mode, op0, op1) + enum rtx_code code; + enum machine_mode mode; + rtx op0, op1; +{ + rtx result; + rtx tem; + + if (GET_RTX_CLASS (code) == 'c' + && (GET_CODE (op0) == CONST_INT + || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT))) + tem = op0, op0 = op1, op1 = tem; + + if (GET_RTX_CLASS (code) == '<') + { + enum machine_mode op_mode = GET_MODE (op0); + if (op_mode == VOIDmode) + op_mode = GET_MODE (op1); + result = simplify_relational_operation (code, op_mode, op0, op1); + } + else + result = simplify_binary_operation (code, mode, op0, op1); + + if (result) + return result; + + /* Put complex operands first and constants second. */ + if (GET_RTX_CLASS (code) == 'c' + && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT) + || (GET_RTX_CLASS (GET_CODE (op0)) == 'o' + && GET_RTX_CLASS (GET_CODE (op1)) != 'o') + || (GET_CODE (op0) == SUBREG + && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o' + && GET_RTX_CLASS (GET_CODE (op1)) != 'o'))) + return gen_rtx_combine (code, mode, op1, op0); + + return gen_rtx_combine (code, mode, op0, op1); +} + +static rtx +gen_unary (code, mode, op0) + enum rtx_code code; + enum machine_mode mode; + rtx op0; +{ + rtx result = simplify_unary_operation (code, mode, op0, mode); + + if (result) + return result; + + return gen_rtx_combine (code, mode, op0); +} + +/* Simplify a comparison between *POP0 and *POP1 where CODE is the + comparison code that will be tested. + + The result is a possibly different comparison code to use. *POP0 and + *POP1 may be updated. + + It is possible that we might detect that a comparison is either always + true or always false. However, we do not perform general constant + folding in combine, so this knowledge isn't useful. Such tautologies + should have been detected earlier. Hence we ignore all such cases. */ + +static enum rtx_code +simplify_comparison (code, pop0, pop1) + enum rtx_code code; + rtx *pop0; + rtx *pop1; +{ + rtx op0 = *pop0; + rtx op1 = *pop1; + rtx tem, tem1; + int i; + enum machine_mode mode, tmode; + + /* Try a few ways of applying the same transformation to both operands. */ + while (1) + { + /* If both operands are the same constant shift, see if we can ignore the + shift. We can if the shift is a rotate or if the bits shifted out of + this shift are known to be zero for both inputs and if the type of + comparison is compatible with the shift. */ + if (GET_CODE (op0) == GET_CODE (op1) + && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT + && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) + || ((GET_CODE (op0) == LSHIFTRT + || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT) + && (code != GT && code != LT && code != GE && code != LE)) + || (GET_CODE (op0) == ASHIFTRT + && (code != GTU && code != LTU + && code != GEU && code != GEU))) + && GET_CODE (XEXP (op0, 1)) == CONST_INT + && INTVAL (XEXP (op0, 1)) >= 0 + && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT + && XEXP (op0, 1) == XEXP (op1, 1)) + { + enum machine_mode mode = GET_MODE (op0); + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); + int shift_count = INTVAL (XEXP (op0, 1)); + + if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) + mask &= (mask >> shift_count) << shift_count; + else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT) + mask = (mask & (mask << shift_count)) >> shift_count; + + if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0 + && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0) + op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); + else + break; + } + + /* If both operands are AND's of a paradoxical SUBREG by constant, the + SUBREGs are of the same mode, and, in both cases, the AND would + be redundant if the comparison was done in the narrower mode, + do the comparison in the narrower mode (e.g., we are AND'ing with 1 + and the operand's possibly nonzero bits are 0xffffff01; in that case + if we only care about QImode, we don't need the AND). This case + occurs if the output mode of an scc insn is not SImode and + STORE_FLAG_VALUE == 1 (e.g., the 386). */ + + else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND + && GET_CODE (XEXP (op0, 1)) == CONST_INT + && GET_CODE (XEXP (op1, 1)) == CONST_INT + && GET_CODE (XEXP (op0, 0)) == SUBREG + && GET_CODE (XEXP (op1, 0)) == SUBREG + && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))) + && (GET_MODE (SUBREG_REG (XEXP (op0, 0))) + == GET_MODE (SUBREG_REG (XEXP (op1, 0)))) + && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) + <= HOST_BITS_PER_WIDE_INT) + && (nonzero_bits (SUBREG_REG (XEXP (op0, 0)), + GET_MODE (SUBREG_REG (XEXP (op0, 0)))) + & ~ INTVAL (XEXP (op0, 1))) == 0 + && (nonzero_bits (SUBREG_REG (XEXP (op1, 0)), + GET_MODE (SUBREG_REG (XEXP (op1, 0)))) + & ~ INTVAL (XEXP (op1, 1))) == 0) + { + op0 = SUBREG_REG (XEXP (op0, 0)); + op1 = SUBREG_REG (XEXP (op1, 0)); + + /* the resulting comparison is always unsigned since we masked off + the original sign bit. */ + code = unsigned_condition (code); + } + else + break; + } + + /* If the first operand is a constant, swap the operands and adjust the + comparison code appropriately. */ + if (CONSTANT_P (op0)) + { + tem = op0, op0 = op1, op1 = tem; + code = swap_condition (code); + } + + /* We now enter a loop during which we will try to simplify the comparison. + For the most part, we only are concerned with comparisons with zero, + but some things may really be comparisons with zero but not start + out looking that way. */ + + while (GET_CODE (op1) == CONST_INT) + { + enum machine_mode mode = GET_MODE (op0); + int mode_width = GET_MODE_BITSIZE (mode); + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); + int equality_comparison_p; + int sign_bit_comparison_p; + int unsigned_comparison_p; + HOST_WIDE_INT const_op; + + /* We only want to handle integral modes. This catches VOIDmode, + CCmode, and the floating-point modes. An exception is that we + can handle VOIDmode if OP0 is a COMPARE or a comparison + operation. */ + + if (GET_MODE_CLASS (mode) != MODE_INT + && ! (mode == VOIDmode + && (GET_CODE (op0) == COMPARE + || GET_RTX_CLASS (GET_CODE (op0)) == '<'))) + break; + + /* Get the constant we are comparing against and turn off all bits + not on in our mode. */ + const_op = INTVAL (op1); + if (mode_width <= HOST_BITS_PER_WIDE_INT) + const_op &= mask; + + /* If we are comparing against a constant power of two and the value + being compared can only have that single bit nonzero (e.g., it was + `and'ed with that bit), we can replace this with a comparison + with zero. */ + if (const_op + && (code == EQ || code == NE || code == GE || code == GEU + || code == LT || code == LTU) + && mode_width <= HOST_BITS_PER_WIDE_INT + && exact_log2 (const_op) >= 0 + && nonzero_bits (op0, mode) == const_op) + { + code = (code == EQ || code == GE || code == GEU ? NE : EQ); + op1 = const0_rtx, const_op = 0; + } + + /* Similarly, if we are comparing a value known to be either -1 or + 0 with -1, change it to the opposite comparison against zero. */ + + if (const_op == -1 + && (code == EQ || code == NE || code == GT || code == LE + || code == GEU || code == LTU) + && num_sign_bit_copies (op0, mode) == mode_width) + { + code = (code == EQ || code == LE || code == GEU ? NE : EQ); + op1 = const0_rtx, const_op = 0; + } + + /* Do some canonicalizations based on the comparison code. We prefer + comparisons against zero and then prefer equality comparisons. + If we can reduce the size of a constant, we will do that too. */ + + switch (code) + { + case LT: + /* < C is equivalent to <= (C - 1) */ + if (const_op > 0) + { + const_op -= 1; + op1 = GEN_INT (const_op); + code = LE; + /* ... fall through to LE case below. */ + } + else + break; + + case LE: + /* <= C is equivalent to < (C + 1); we do this for C < 0 */ + if (const_op < 0) + { + const_op += 1; + op1 = GEN_INT (const_op); + code = LT; + } + + /* If we are doing a <= 0 comparison on a value known to have + a zero sign bit, we can replace this with == 0. */ + else if (const_op == 0 + && mode_width <= HOST_BITS_PER_WIDE_INT + && (nonzero_bits (op0, mode) + & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) + code = EQ; + break; + + case GE: + /* >= C is equivalent to > (C - 1). */ + if (const_op > 0) + { + const_op -= 1; + op1 = GEN_INT (const_op); + code = GT; + /* ... fall through to GT below. */ + } + else + break; + + case GT: + /* > C is equivalent to >= (C + 1); we do this for C < 0*/ + if (const_op < 0) + { + const_op += 1; + op1 = GEN_INT (const_op); + code = GE; + } + + /* If we are doing a > 0 comparison on a value known to have + a zero sign bit, we can replace this with != 0. */ + else if (const_op == 0 + && mode_width <= HOST_BITS_PER_WIDE_INT + && (nonzero_bits (op0, mode) + & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) + code = NE; + break; + + case LTU: + /* < C is equivalent to <= (C - 1). */ + if (const_op > 0) + { + const_op -= 1; + op1 = GEN_INT (const_op); + code = LEU; + /* ... fall through ... */ + } + + /* (unsigned) < 0x80000000 is equivalent to >= 0. */ + else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)) + { + const_op = 0, op1 = const0_rtx; + code = GE; + break; + } + else + break; + + case LEU: + /* unsigned <= 0 is equivalent to == 0 */ + if (const_op == 0) + code = EQ; + + /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ + else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1) + { + const_op = 0, op1 = const0_rtx; + code = GE; + } + break; + + case GEU: + /* >= C is equivalent to < (C - 1). */ + if (const_op > 1) + { + const_op -= 1; + op1 = GEN_INT (const_op); + code = GTU; + /* ... fall through ... */ + } + + /* (unsigned) >= 0x80000000 is equivalent to < 0. */ + else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)) + { + const_op = 0, op1 = const0_rtx; + code = LT; + } + else + break; + + case GTU: + /* unsigned > 0 is equivalent to != 0 */ + if (const_op == 0) + code = NE; + + /* (unsigned) > 0x7fffffff is equivalent to < 0. */ + else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1) + { + const_op = 0, op1 = const0_rtx; + code = LT; + } + break; + } + + /* Compute some predicates to simplify code below. */ + + equality_comparison_p = (code == EQ || code == NE); + sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); + unsigned_comparison_p = (code == LTU || code == LEU || code == GTU + || code == LEU); + + /* Now try cases based on the opcode of OP0. If none of the cases + does a "continue", we exit this loop immediately after the + switch. */ + + switch (GET_CODE (op0)) + { + case ZERO_EXTRACT: + /* If we are extracting a single bit from a variable position in + a constant that has only a single bit set and are comparing it + with zero, we can convert this into an equality comparison + between the position and the location of the single bit. We can't + do this if bit endian and we don't have an extzv since we then + can't know what mode to use for the endianness adjustment. */ + +#if ! BITS_BIG_ENDIAN || defined (HAVE_extzv) + if (GET_CODE (XEXP (op0, 0)) == CONST_INT + && XEXP (op0, 1) == const1_rtx + && equality_comparison_p && const_op == 0 + && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) + { +#if BITS_BIG_ENDIAN + i = (GET_MODE_BITSIZE + (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i); +#endif + + op0 = XEXP (op0, 2); + op1 = GEN_INT (i); + const_op = i; + + /* Result is nonzero iff shift count is equal to I. */ + code = reverse_condition (code); + continue; + } +#endif + + /* ... fall through ... */ + + case SIGN_EXTRACT: + tem = expand_compound_operation (op0); + if (tem != op0) + { + op0 = tem; + continue; + } + break; + + case NOT: + /* If testing for equality, we can take the NOT of the constant. */ + if (equality_comparison_p + && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) + { + op0 = XEXP (op0, 0); + op1 = tem; + continue; + } + + /* If just looking at the sign bit, reverse the sense of the + comparison. */ + if (sign_bit_comparison_p) + { + op0 = XEXP (op0, 0); + code = (code == GE ? LT : GE); + continue; + } + break; + + case NEG: + /* If testing for equality, we can take the NEG of the constant. */ + if (equality_comparison_p + && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) + { + op0 = XEXP (op0, 0); + op1 = tem; + continue; + } + + /* The remaining cases only apply to comparisons with zero. */ + if (const_op != 0) + break; + + /* When X is ABS or is known positive, + (neg X) is < 0 if and only if X != 0. */ + + if (sign_bit_comparison_p + && (GET_CODE (XEXP (op0, 0)) == ABS + || (mode_width <= HOST_BITS_PER_WIDE_INT + && (nonzero_bits (XEXP (op0, 0), mode) + & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) + { + op0 = XEXP (op0, 0); + code = (code == LT ? NE : EQ); + continue; + } + + /* If we have NEG of something whose two high-order bits are the + same, we know that "(-a) < 0" is equivalent to "a > 0". */ + if (num_sign_bit_copies (op0, mode) >= 2) + { + op0 = XEXP (op0, 0); + code = swap_condition (code); + continue; + } + break; + + case ROTATE: + /* If we are testing equality and our count is a constant, we + can perform the inverse operation on our RHS. */ + if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT + && (tem = simplify_binary_operation (ROTATERT, mode, + op1, XEXP (op0, 1))) != 0) + { + op0 = XEXP (op0, 0); + op1 = tem; + continue; + } + + /* If we are doing a < 0 or >= 0 comparison, it means we are testing + a particular bit. Convert it to an AND of a constant of that + bit. This will be converted into a ZERO_EXTRACT. */ + if (const_op == 0 && sign_bit_comparison_p + && GET_CODE (XEXP (op0, 1)) == CONST_INT + && mode_width <= HOST_BITS_PER_WIDE_INT) + { + op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), + ((HOST_WIDE_INT) 1 + << (mode_width - 1 + - INTVAL (XEXP (op0, 1))))); + code = (code == LT ? NE : EQ); + continue; + } + + /* ... fall through ... */ + + case ABS: + /* ABS is ignorable inside an equality comparison with zero. */ + if (const_op == 0 && equality_comparison_p) + { + op0 = XEXP (op0, 0); + continue; + } + break; + + + case SIGN_EXTEND: + /* Can simplify (compare (zero/sign_extend FOO) CONST) + to (compare FOO CONST) if CONST fits in FOO's mode and we + are either testing inequality or have an unsigned comparison + with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */ + if (! unsigned_comparison_p + && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) + <= HOST_BITS_PER_WIDE_INT) + && ((unsigned HOST_WIDE_INT) const_op + < (((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))) + { + op0 = XEXP (op0, 0); + continue; + } + break; + + case SUBREG: + /* Check for the case where we are comparing A - C1 with C2, + both constants are smaller than 1/2 the maxium positive + value in MODE, and the comparison is equality or unsigned. + In that case, if A is either zero-extended to MODE or has + sufficient sign bits so that the high-order bit in MODE + is a copy of the sign in the inner mode, we can prove that it is + safe to do the operation in the wider mode. This simplifies + many range checks. */ + + if (mode_width <= HOST_BITS_PER_WIDE_INT + && subreg_lowpart_p (op0) + && GET_CODE (SUBREG_REG (op0)) == PLUS + && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT + && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0 + && (- INTVAL (XEXP (SUBREG_REG (op0), 1)) + < GET_MODE_MASK (mode) / 2) + && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2 + && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0), + GET_MODE (SUBREG_REG (op0))) + & ~ GET_MODE_MASK (mode)) + || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0), + GET_MODE (SUBREG_REG (op0))) + > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) + - GET_MODE_BITSIZE (mode))))) + { + op0 = SUBREG_REG (op0); + continue; + } + + /* If the inner mode is narrower and we are extracting the low part, + we can treat the SUBREG as if it were a ZERO_EXTEND. */ + if (subreg_lowpart_p (op0) + && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) + /* Fall through */ ; + else + break; + + /* ... fall through ... */ + + case ZERO_EXTEND: + if ((unsigned_comparison_p || equality_comparison_p) + && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) + <= HOST_BITS_PER_WIDE_INT) + && ((unsigned HOST_WIDE_INT) const_op + < GET_MODE_MASK (GET_MODE (XEXP (op0, 0))))) + { + op0 = XEXP (op0, 0); + continue; + } + break; + + case PLUS: + /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do + this for equality comparisons due to pathological cases involving + overflows. */ + if (equality_comparison_p + && 0 != (tem = simplify_binary_operation (MINUS, mode, + op1, XEXP (op0, 1)))) + { + op0 = XEXP (op0, 0); + op1 = tem; + continue; + } + + /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ + if (const_op == 0 && XEXP (op0, 1) == constm1_rtx + && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) + { + op0 = XEXP (XEXP (op0, 0), 0); + code = (code == LT ? EQ : NE); + continue; + } + break; + + case MINUS: + /* (eq (minus A B) C) -> (eq A (plus B C)) or + (eq B (minus A C)), whichever simplifies. We can only do + this for equality comparisons due to pathological cases involving + overflows. */ + if (equality_comparison_p + && 0 != (tem = simplify_binary_operation (PLUS, mode, + XEXP (op0, 1), op1))) + { + op0 = XEXP (op0, 0); + op1 = tem; + continue; + } + + if (equality_comparison_p + && 0 != (tem = simplify_binary_operation (MINUS, mode, + XEXP (op0, 0), op1))) + { + op0 = XEXP (op0, 1); + op1 = tem; + continue; + } + + /* The sign bit of (minus (ashiftrt X C) X), where C is the number + of bits in X minus 1, is one iff X > 0. */ + if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT + && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 + && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) + { + op0 = XEXP (op0, 1); + code = (code == GE ? LE : GT); + continue; + } + break; + + case XOR: + /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification + if C is zero or B is a constant. */ + if (equality_comparison_p + && 0 != (tem = simplify_binary_operation (XOR, mode, + XEXP (op0, 1), op1))) + { + op0 = XEXP (op0, 0); + op1 = tem; + continue; + } + break; + + case EQ: case NE: + case LT: case LTU: case LE: case LEU: + case GT: case GTU: case GE: case GEU: + /* We can't do anything if OP0 is a condition code value, rather + than an actual data value. */ + if (const_op != 0 +#ifdef HAVE_cc0 + || XEXP (op0, 0) == cc0_rtx +#endif + || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) + break; + + /* Get the two operands being compared. */ + if (GET_CODE (XEXP (op0, 0)) == COMPARE) + tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); + else + tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); + + /* Check for the cases where we simply want the result of the + earlier test or the opposite of that result. */ + if (code == NE + || (code == EQ && reversible_comparison_p (op0)) + || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT + && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT + && (STORE_FLAG_VALUE + & (((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) + && (code == LT + || (code == GE && reversible_comparison_p (op0))))) + { + code = (code == LT || code == NE + ? GET_CODE (op0) : reverse_condition (GET_CODE (op0))); + op0 = tem, op1 = tem1; + continue; + } + break; + + case IOR: + /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero + iff X <= 0. */ + if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS + && XEXP (XEXP (op0, 0), 1) == constm1_rtx + && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) + { + op0 = XEXP (op0, 1); + code = (code == GE ? GT : LE); + continue; + } + break; + + case AND: + /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This + will be converted to a ZERO_EXTRACT later. */ + if (const_op == 0 && equality_comparison_p + && (GET_CODE (XEXP (op0, 0)) == ASHIFT + || GET_CODE (XEXP (op0, 0)) == LSHIFT) + && XEXP (XEXP (op0, 0), 0) == const1_rtx) + { + op0 = simplify_and_const_int + (op0, mode, gen_rtx_combine (LSHIFTRT, mode, + XEXP (op0, 1), + XEXP (XEXP (op0, 0), 1)), + (HOST_WIDE_INT) 1); + continue; + } + + /* If we are comparing (and (lshiftrt X C1) C2) for equality with + zero and X is a comparison and C1 and C2 describe only bits set + in STORE_FLAG_VALUE, we can compare with X. */ + if (const_op == 0 && equality_comparison_p + && mode_width <= HOST_BITS_PER_WIDE_INT + && GET_CODE (XEXP (op0, 1)) == CONST_INT + && GET_CODE (XEXP (op0, 0)) == LSHIFTRT + && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 + && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) + { + mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) + << INTVAL (XEXP (XEXP (op0, 0), 1))); + if ((~ STORE_FLAG_VALUE & mask) == 0 + && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<' + || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 + && GET_RTX_CLASS (GET_CODE (tem)) == '<'))) + { + op0 = XEXP (XEXP (op0, 0), 0); + continue; + } + } + + /* If we are doing an equality comparison of an AND of a bit equal + to the sign bit, replace this with a LT or GE comparison of + the underlying value. */ + if (equality_comparison_p + && const_op == 0 + && GET_CODE (XEXP (op0, 1)) == CONST_INT + && mode_width <= HOST_BITS_PER_WIDE_INT + && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) + == (HOST_WIDE_INT) 1 << (mode_width - 1))) + { + op0 = XEXP (op0, 0); + code = (code == EQ ? GE : LT); + continue; + } + + /* If this AND operation is really a ZERO_EXTEND from a narrower + mode, the constant fits within that mode, and this is either an + equality or unsigned comparison, try to do this comparison in + the narrower mode. */ + if ((equality_comparison_p || unsigned_comparison_p) + && GET_CODE (XEXP (op0, 1)) == CONST_INT + && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) + & GET_MODE_MASK (mode)) + + 1)) >= 0 + && const_op >> i == 0 + && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) + { + op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0)); + continue; + } + break; + + case ASHIFT: + case LSHIFT: + /* If we have (compare (xshift FOO N) (const_int C)) and + the high order N bits of FOO (N+1 if an inequality comparison) + are known to be zero, we can do this by comparing FOO with C + shifted right N bits so long as the low-order N bits of C are + zero. */ + if (GET_CODE (XEXP (op0, 1)) == CONST_INT + && INTVAL (XEXP (op0, 1)) >= 0 + && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) + < HOST_BITS_PER_WIDE_INT) + && ((const_op + & ((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1) == 0) + && mode_width <= HOST_BITS_PER_WIDE_INT + && (nonzero_bits (XEXP (op0, 0), mode) + & ~ (mask >> (INTVAL (XEXP (op0, 1)) + + ! equality_comparison_p))) == 0) + { + const_op >>= INTVAL (XEXP (op0, 1)); + op1 = GEN_INT (const_op); + op0 = XEXP (op0, 0); + continue; + } + + /* If we are doing a sign bit comparison, it means we are testing + a particular bit. Convert it to the appropriate AND. */ + if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT + && mode_width <= HOST_BITS_PER_WIDE_INT) + { + op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), + ((HOST_WIDE_INT) 1 + << (mode_width - 1 + - INTVAL (XEXP (op0, 1))))); + code = (code == LT ? NE : EQ); + continue; + } + + /* If this an equality comparison with zero and we are shifting + the low bit to the sign bit, we can convert this to an AND of the + low-order bit. */ + if (const_op == 0 && equality_comparison_p + && GET_CODE (XEXP (op0, 1)) == CONST_INT + && INTVAL (XEXP (op0, 1)) == mode_width - 1) + { + op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), + (HOST_WIDE_INT) 1); + continue; + } + break; + + case ASHIFTRT: + /* If this is an equality comparison with zero, we can do this + as a logical shift, which might be much simpler. */ + if (equality_comparison_p && const_op == 0 + && GET_CODE (XEXP (op0, 1)) == CONST_INT) + { + op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, + XEXP (op0, 0), + INTVAL (XEXP (op0, 1))); + continue; + } + + /* If OP0 is a sign extension and CODE is not an unsigned comparison, + do the comparison in a narrower mode. */ + if (! unsigned_comparison_p + && GET_CODE (XEXP (op0, 1)) == CONST_INT + && GET_CODE (XEXP (op0, 0)) == ASHIFT + && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) + && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), + MODE_INT, 1)) != BLKmode + && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode) + || ((unsigned HOST_WIDE_INT) - const_op + <= GET_MODE_MASK (tmode)))) + { + op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0)); + continue; + } + + /* ... fall through ... */ + case LSHIFTRT: + /* If we have (compare (xshiftrt FOO N) (const_int C)) and + the low order N bits of FOO are known to be zero, we can do this + by comparing FOO with C shifted left N bits so long as no + overflow occurs. */ + if (GET_CODE (XEXP (op0, 1)) == CONST_INT + && INTVAL (XEXP (op0, 1)) >= 0 + && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT + && mode_width <= HOST_BITS_PER_WIDE_INT + && (nonzero_bits (XEXP (op0, 0), mode) + & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 + && (const_op == 0 + || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1)) + < mode_width))) + { + const_op <<= INTVAL (XEXP (op0, 1)); + op1 = GEN_INT (const_op); + op0 = XEXP (op0, 0); + continue; + } + + /* If we are using this shift to extract just the sign bit, we + can replace this with an LT or GE comparison. */ + if (const_op == 0 + && (equality_comparison_p || sign_bit_comparison_p) + && GET_CODE (XEXP (op0, 1)) == CONST_INT + && INTVAL (XEXP (op0, 1)) == mode_width - 1) + { + op0 = XEXP (op0, 0); + code = (code == NE || code == GT ? LT : GE); + continue; + } + break; + } + + break; + } + + /* Now make any compound operations involved in this comparison. Then, + check for an outmost SUBREG on OP0 that isn't doing anything or is + paradoxical. The latter case can only occur when it is known that the + "extra" bits will be zero. Therefore, it is safe to remove the SUBREG. + We can never remove a SUBREG for a non-equality comparison because the + sign bit is in a different place in the underlying object. */ + + op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); + op1 = make_compound_operation (op1, SET); + + if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) + && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT + && (code == NE || code == EQ) + && ((GET_MODE_SIZE (GET_MODE (op0)) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))) + { + op0 = SUBREG_REG (op0); + op1 = gen_lowpart_for_combine (GET_MODE (op0), op1); + } + + else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) + && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT + && (code == NE || code == EQ) + && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) + <= HOST_BITS_PER_WIDE_INT) + && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0))) + & ~ GET_MODE_MASK (GET_MODE (op0))) == 0 + && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), + op1), + (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) + & ~ GET_MODE_MASK (GET_MODE (op0))) == 0)) + op0 = SUBREG_REG (op0), op1 = tem; + + /* We now do the opposite procedure: Some machines don't have compare + insns in all modes. If OP0's mode is an integer mode smaller than a + word and we can't do a compare in that mode, see if there is a larger + mode for which we can do the compare. There are a number of cases in + which we can use the wider mode. */ + + mode = GET_MODE (op0); + if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_SIZE (mode) < UNITS_PER_WORD + && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) + for (tmode = GET_MODE_WIDER_MODE (mode); + (tmode != VOIDmode + && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); + tmode = GET_MODE_WIDER_MODE (tmode)) + if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing) + { + /* If the only nonzero bits in OP0 and OP1 are those in the + narrower mode and this is an equality or unsigned comparison, + we can use the wider mode. Similarly for sign-extended + values and equality or signed comparisons. */ + if (((code == EQ || code == NE + || code == GEU || code == GTU || code == LEU || code == LTU) + && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0 + && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0) + || ((code == EQ || code == NE + || code == GE || code == GT || code == LE || code == LT) + && (num_sign_bit_copies (op0, tmode) + > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)) + && (num_sign_bit_copies (op1, tmode) + > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)))) + { + op0 = gen_lowpart_for_combine (tmode, op0); + op1 = gen_lowpart_for_combine (tmode, op1); + break; + } + + /* If this is a test for negative, we can make an explicit + test of the sign bit. */ + + if (op1 == const0_rtx && (code == LT || code == GE) + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) + { + op0 = gen_binary (AND, tmode, + gen_lowpart_for_combine (tmode, op0), + GEN_INT ((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (mode) - 1))); + code = (code == LT) ? NE : EQ; + break; + } + } + + *pop0 = op0; + *pop1 = op1; + + return code; +} + +/* Return 1 if we know that X, a comparison operation, is not operating + on a floating-point value or is EQ or NE, meaning that we can safely + reverse it. */ + +static int +reversible_comparison_p (x) + rtx x; +{ + if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + || GET_CODE (x) == NE || GET_CODE (x) == EQ) + return 1; + + switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0)))) + { + case MODE_INT: + return 1; + + case MODE_CC: + x = get_last_value (XEXP (x, 0)); + return (x && GET_CODE (x) == COMPARE + && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT); + } + + return 0; +} + +/* Utility function for following routine. Called when X is part of a value + being stored into reg_last_set_value. Sets reg_last_set_table_tick + for each register mentioned. Similar to mention_regs in cse.c */ + +static void +update_table_tick (x) + rtx x; +{ + register enum rtx_code code = GET_CODE (x); + register char *fmt = GET_RTX_FORMAT (code); + register int i; + + if (code == REG) + { + int regno = REGNO (x); + int endregno = regno + (regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); + + for (i = regno; i < endregno; i++) + reg_last_set_table_tick[i] = label_tick; + + return; + } + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + /* Note that we can't have an "E" in values stored; see + get_last_value_validate. */ + if (fmt[i] == 'e') + update_table_tick (XEXP (x, i)); +} + +/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we + are saying that the register is clobbered and we no longer know its + value. If INSN is zero, don't update reg_last_set; this is only permitted + with VALUE also zero and is used to invalidate the register. */ + +static void +record_value_for_reg (reg, insn, value) + rtx reg; + rtx insn; + rtx value; +{ + int regno = REGNO (reg); + int endregno = regno + (regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1); + int i; + + /* If VALUE contains REG and we have a previous value for REG, substitute + the previous value. */ + if (value && insn && reg_overlap_mentioned_p (reg, value)) + { + rtx tem; + + /* Set things up so get_last_value is allowed to see anything set up to + our insn. */ + subst_low_cuid = INSN_CUID (insn); + tem = get_last_value (reg); + + if (tem) + value = replace_rtx (copy_rtx (value), reg, tem); + } + + /* For each register modified, show we don't know its value, that + its value has been updated, and that we don't know the location of + the death of the register. */ + for (i = regno; i < endregno; i ++) + { + if (insn) + reg_last_set[i] = insn; + reg_last_set_value[i] = 0; + reg_last_death[i] = 0; + } + + /* Mark registers that are being referenced in this value. */ + if (value) + update_table_tick (value); + + /* Now update the status of each register being set. + If someone is using this register in this block, set this register + to invalid since we will get confused between the two lives in this + basic block. This makes using this register always invalid. In cse, we + scan the table to invalidate all entries using this register, but this + is too much work for us. */ + + for (i = regno; i < endregno; i++) + { + reg_last_set_label[i] = label_tick; + if (value && reg_last_set_table_tick[i] == label_tick) + reg_last_set_invalid[i] = 1; + else + reg_last_set_invalid[i] = 0; + } + + /* The value being assigned might refer to X (like in "x++;"). In that + case, we must replace it with (clobber (const_int 0)) to prevent + infinite loops. */ + if (value && ! get_last_value_validate (&value, + reg_last_set_label[regno], 0)) + { + value = copy_rtx (value); + if (! get_last_value_validate (&value, reg_last_set_label[regno], 1)) + value = 0; + } + + /* For the main register being modified, update the value, the mode, the + nonzero bits, and the number of sign bit copies. */ + + reg_last_set_value[regno] = value; + + if (value) + { + subst_low_cuid = INSN_CUID (insn); + reg_last_set_mode[regno] = GET_MODE (reg); + reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg)); + reg_last_set_sign_bit_copies[regno] + = num_sign_bit_copies (value, GET_MODE (reg)); + } +} + +/* Used for communication between the following two routines. */ +static rtx record_dead_insn; + +/* Called via note_stores from record_dead_and_set_regs to handle one + SET or CLOBBER in an insn. */ + +static void +record_dead_and_set_regs_1 (dest, setter) + rtx dest, setter; +{ + if (GET_CODE (dest) == REG) + { + /* If we are setting the whole register, we know its value. Otherwise + show that we don't know the value. We can handle SUBREG in + some cases. */ + if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) + record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); + else if (GET_CODE (setter) == SET + && GET_CODE (SET_DEST (setter)) == SUBREG + && SUBREG_REG (SET_DEST (setter)) == dest + && subreg_lowpart_p (SET_DEST (setter))) + record_value_for_reg (dest, record_dead_insn, + gen_lowpart_for_combine (GET_MODE (dest), + SET_SRC (setter))); + else + record_value_for_reg (dest, record_dead_insn, NULL_RTX); + } + else if (GET_CODE (dest) == MEM + /* Ignore pushes, they clobber nothing. */ + && ! push_operand (dest, GET_MODE (dest))) + mem_last_set = INSN_CUID (record_dead_insn); +} + +/* Update the records of when each REG was most recently set or killed + for the things done by INSN. This is the last thing done in processing + INSN in the combiner loop. + + We update reg_last_set, reg_last_set_value, reg_last_death, and also the + similar information mem_last_set (which insn most recently modified memory) + and last_call_cuid (which insn was the most recent subroutine call). */ + +static void +record_dead_and_set_regs (insn) + rtx insn; +{ + register rtx link; + int i; + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + { + if (REG_NOTE_KIND (link) == REG_DEAD + && GET_CODE (XEXP (link, 0)) == REG) + { + int regno = REGNO (XEXP (link, 0)); + int endregno + = regno + (regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0))) + : 1); + + for (i = regno; i < endregno; i++) + reg_last_death[i] = insn; + } + else if (REG_NOTE_KIND (link) == REG_INC) + record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); + } + + if (GET_CODE (insn) == CALL_INSN) + { + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (call_used_regs[i]) + { + reg_last_set_value[i] = 0; + reg_last_death[i] = 0; + } + + last_call_cuid = mem_last_set = INSN_CUID (insn); + } + + record_dead_insn = insn; + note_stores (PATTERN (insn), record_dead_and_set_regs_1); +} + +/* Utility routine for the following function. Verify that all the registers + mentioned in *LOC are valid when *LOC was part of a value set when + label_tick == TICK. Return 0 if some are not. + + If REPLACE is non-zero, replace the invalid reference with + (clobber (const_int 0)) and return 1. This replacement is useful because + we often can get useful information about the form of a value (e.g., if + it was produced by a shift that always produces -1 or 0) even though + we don't know exactly what registers it was produced from. */ + +static int +get_last_value_validate (loc, tick, replace) + rtx *loc; + int tick; + int replace; +{ + rtx x = *loc; + char *fmt = GET_RTX_FORMAT (GET_CODE (x)); + int len = GET_RTX_LENGTH (GET_CODE (x)); + int i; + + if (GET_CODE (x) == REG) + { + int regno = REGNO (x); + int endregno = regno + (regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); + int j; + + for (j = regno; j < endregno; j++) + if (reg_last_set_invalid[j] + /* If this is a pseudo-register that was only set once, it is + always valid. */ + || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1) + && reg_last_set_label[j] > tick)) + { + if (replace) + *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); + return replace; + } + + return 1; + } + + for (i = 0; i < len; i++) + if ((fmt[i] == 'e' + && get_last_value_validate (&XEXP (x, i), tick, replace) == 0) + /* Don't bother with these. They shouldn't occur anyway. */ + || fmt[i] == 'E') + return 0; + + /* If we haven't found a reason for it to be invalid, it is valid. */ + return 1; +} + +/* Get the last value assigned to X, if known. Some registers + in the value may be replaced with (clobber (const_int 0)) if their value + is known longer known reliably. */ + +static rtx +get_last_value (x) + rtx x; +{ + int regno; + rtx value; + + /* If this is a non-paradoxical SUBREG, get the value of its operand and + then convert it to the desired mode. If this is a paradoxical SUBREG, + we cannot predict what values the "extra" bits might have. */ + if (GET_CODE (x) == SUBREG + && subreg_lowpart_p (x) + && (GET_MODE_SIZE (GET_MODE (x)) + <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) + && (value = get_last_value (SUBREG_REG (x))) != 0) + return gen_lowpart_for_combine (GET_MODE (x), value); + + if (GET_CODE (x) != REG) + return 0; + + regno = REGNO (x); + value = reg_last_set_value[regno]; + + /* If we don't have a value or if it isn't for this basic block, return 0. */ + + if (value == 0 + || (reg_n_sets[regno] != 1 + && reg_last_set_label[regno] != label_tick)) + return 0; + + /* If the value was set in a later insn that the ones we are processing, + we can't use it even if the register was only set once, but make a quick + check to see if the previous insn set it to something. This is commonly + the case when the same pseudo is used by repeated insns. */ + + if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid) + { + rtx insn, set; + + for (insn = prev_nonnote_insn (subst_insn); + insn && INSN_CUID (insn) >= subst_low_cuid; + insn = prev_nonnote_insn (insn)) + ; + + if (insn + && (set = single_set (insn)) != 0 + && rtx_equal_p (SET_DEST (set), x)) + { + value = SET_SRC (set); + + /* Make sure that VALUE doesn't reference X. Replace any + expliit references with a CLOBBER. If there are any remaining + references (rare), don't use the value. */ + + if (reg_mentioned_p (x, value)) + value = replace_rtx (copy_rtx (value), x, + gen_rtx (CLOBBER, GET_MODE (x), const0_rtx)); + + if (reg_overlap_mentioned_p (x, value)) + return 0; + } + else + return 0; + } + + /* If the value has all its registers valid, return it. */ + if (get_last_value_validate (&value, reg_last_set_label[regno], 0)) + return value; + + /* Otherwise, make a copy and replace any invalid register with + (clobber (const_int 0)). If that fails for some reason, return 0. */ + + value = copy_rtx (value); + if (get_last_value_validate (&value, reg_last_set_label[regno], 1)) + return value; + + return 0; +} + +/* Return nonzero if expression X refers to a REG or to memory + that is set in an instruction more recent than FROM_CUID. */ + +static int +use_crosses_set_p (x, from_cuid) + register rtx x; + int from_cuid; +{ + register char *fmt; + register int i; + register enum rtx_code code = GET_CODE (x); + + if (code == REG) + { + register int regno = REGNO (x); +#ifdef PUSH_ROUNDING + /* Don't allow uses of the stack pointer to be moved, + because we don't know whether the move crosses a push insn. */ + if (regno == STACK_POINTER_REGNUM) + return 1; +#endif + return (reg_last_set[regno] + && INSN_CUID (reg_last_set[regno]) > from_cuid); + } + + if (code == MEM && mem_last_set > from_cuid) + return 1; + + fmt = GET_RTX_FORMAT (code); + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) + return 1; + } + else if (fmt[i] == 'e' + && use_crosses_set_p (XEXP (x, i), from_cuid)) + return 1; + } + return 0; +} + +/* Define three variables used for communication between the following + routines. */ + +static int reg_dead_regno, reg_dead_endregno; +static int reg_dead_flag; + +/* Function called via note_stores from reg_dead_at_p. + + If DEST is within [reg_dead_rengno, reg_dead_endregno), set + reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ + +static void +reg_dead_at_p_1 (dest, x) + rtx dest; + rtx x; +{ + int regno, endregno; + + if (GET_CODE (dest) != REG) + return; + + regno = REGNO (dest); + endregno = regno + (regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1); + + if (reg_dead_endregno > regno && reg_dead_regno < endregno) + reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; +} + +/* Return non-zero if REG is known to be dead at INSN. + + We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER + referencing REG, it is dead. If we hit a SET referencing REG, it is + live. Otherwise, see if it is live or dead at the start of the basic + block we are in. */ + +static int +reg_dead_at_p (reg, insn) + rtx reg; + rtx insn; +{ + int block, i; + + /* Set variables for reg_dead_at_p_1. */ + reg_dead_regno = REGNO (reg); + reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (reg_dead_regno, + GET_MODE (reg)) + : 1); + + reg_dead_flag = 0; + + /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or + beginning of function. */ + for (; insn && GET_CODE (insn) != CODE_LABEL; + insn = prev_nonnote_insn (insn)) + { + note_stores (PATTERN (insn), reg_dead_at_p_1); + if (reg_dead_flag) + return reg_dead_flag == 1 ? 1 : 0; + + if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) + return 1; + } + + /* Get the basic block number that we were in. */ + if (insn == 0) + block = 0; + else + { + for (block = 0; block < n_basic_blocks; block++) + if (insn == basic_block_head[block]) + break; + + if (block == n_basic_blocks) + return 0; + } + + for (i = reg_dead_regno; i < reg_dead_endregno; i++) + if (basic_block_live_at_start[block][i / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS))) + return 0; + + return 1; +} + +/* Remove register number REGNO from the dead registers list of INSN. + + Return the note used to record the death, if there was one. */ + +rtx +remove_death (regno, insn) + int regno; + rtx insn; +{ + register rtx note = find_regno_note (insn, REG_DEAD, regno); + + if (note) + { + reg_n_deaths[regno]--; + remove_note (insn, note); + } + + return note; +} + +/* For each register (hardware or pseudo) used within expression X, if its + death is in an instruction with cuid between FROM_CUID (inclusive) and + TO_INSN (exclusive), put a REG_DEAD note for that register in the + list headed by PNOTES. + + This is done when X is being merged by combination into TO_INSN. These + notes will then be distributed as needed. */ + +static void +move_deaths (x, from_cuid, to_insn, pnotes) + rtx x; + int from_cuid; + rtx to_insn; + rtx *pnotes; +{ + register char *fmt; + register int len, i; + register enum rtx_code code = GET_CODE (x); + + if (code == REG) + { + register int regno = REGNO (x); + register rtx where_dead = reg_last_death[regno]; + + if (where_dead && INSN_CUID (where_dead) >= from_cuid + && INSN_CUID (where_dead) < INSN_CUID (to_insn)) + { + rtx note = remove_death (regno, where_dead); + + /* It is possible for the call above to return 0. This can occur + when reg_last_death points to I2 or I1 that we combined with. + In that case make a new note. + + We must also check for the case where X is a hard register + and NOTE is a death note for a range of hard registers + including X. In that case, we must put REG_DEAD notes for + the remaining registers in place of NOTE. */ + + if (note != 0 && regno < FIRST_PSEUDO_REGISTER + && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) + != GET_MODE_SIZE (GET_MODE (x)))) + { + int deadregno = REGNO (XEXP (note, 0)); + int deadend + = (deadregno + HARD_REGNO_NREGS (deadregno, + GET_MODE (XEXP (note, 0)))); + int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); + int i; + + for (i = deadregno; i < deadend; i++) + if (i < regno || i >= ourend) + REG_NOTES (where_dead) + = gen_rtx (EXPR_LIST, REG_DEAD, + gen_rtx (REG, word_mode, i), + REG_NOTES (where_dead)); + } + + if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) + { + XEXP (note, 1) = *pnotes; + *pnotes = note; + } + else + *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes); + + reg_n_deaths[regno]++; + } + + return; + } + + else if (GET_CODE (x) == SET) + { + rtx dest = SET_DEST (x); + + move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes); + + /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG + that accesses one word of a multi-word item, some + piece of everything register in the expression is used by + this insn, so remove any old death. */ + + if (GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == STRICT_LOW_PART + || (GET_CODE (dest) == SUBREG + && (((GET_MODE_SIZE (GET_MODE (dest)) + + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) + + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) + { + move_deaths (dest, from_cuid, to_insn, pnotes); + return; + } + + /* If this is some other SUBREG, we know it replaces the entire + value, so use that as the destination. */ + if (GET_CODE (dest) == SUBREG) + dest = SUBREG_REG (dest); + + /* If this is a MEM, adjust deaths of anything used in the address. + For a REG (the only other possibility), the entire value is + being replaced so the old value is not used in this insn. */ + + if (GET_CODE (dest) == MEM) + move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes); + return; + } + + else if (GET_CODE (x) == CLOBBER) + return; + + len = GET_RTX_LENGTH (code); + fmt = GET_RTX_FORMAT (code); + + for (i = 0; i < len; i++) + { + if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes); + } + else if (fmt[i] == 'e') + move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes); + } +} + +/* Return 1 if X is the target of a bit-field assignment in BODY, the + pattern of an insn. X must be a REG. */ + +static int +reg_bitfield_target_p (x, body) + rtx x; + rtx body; +{ + int i; + + if (GET_CODE (body) == SET) + { + rtx dest = SET_DEST (body); + rtx target; + int regno, tregno, endregno, endtregno; + + if (GET_CODE (dest) == ZERO_EXTRACT) + target = XEXP (dest, 0); + else if (GET_CODE (dest) == STRICT_LOW_PART) + target = SUBREG_REG (XEXP (dest, 0)); + else + return 0; + + if (GET_CODE (target) == SUBREG) + target = SUBREG_REG (target); + + if (GET_CODE (target) != REG) + return 0; + + tregno = REGNO (target), regno = REGNO (x); + if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) + return target == x; + + endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target)); + endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); + + return endregno > tregno && regno < endtregno; + } + + else if (GET_CODE (body) == PARALLEL) + for (i = XVECLEN (body, 0) - 1; i >= 0; i--) + if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) + return 1; + + return 0; +} + +/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them + as appropriate. I3 and I2 are the insns resulting from the combination + insns including FROM (I2 may be zero). + + ELIM_I2 and ELIM_I1 are either zero or registers that we know will + not need REG_DEAD notes because they are being substituted for. This + saves searching in the most common cases. + + Each note in the list is either ignored or placed on some insns, depending + on the type of note. */ + +static void +distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1) + rtx notes; + rtx from_insn; + rtx i3, i2; + rtx elim_i2, elim_i1; +{ + rtx note, next_note; + rtx tem; + + for (note = notes; note; note = next_note) + { + rtx place = 0, place2 = 0; + + /* If this NOTE references a pseudo register, ensure it references + the latest copy of that register. */ + if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG + && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER) + XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))]; + + next_note = XEXP (note, 1); + switch (REG_NOTE_KIND (note)) + { + case REG_UNUSED: + /* If this register is set or clobbered in I3, put the note there + unless there is one already. */ + if (reg_set_p (XEXP (note, 0), PATTERN (i3))) + { + if (! (GET_CODE (XEXP (note, 0)) == REG + ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) + : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) + place = i3; + } + /* Otherwise, if this register is used by I3, then this register + now dies here, so we must put a REG_DEAD note here unless there + is one already. */ + else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) + && ! (GET_CODE (XEXP (note, 0)) == REG + ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0))) + : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) + { + PUT_REG_NOTE_KIND (note, REG_DEAD); + place = i3; + } + break; + + case REG_EQUAL: + case REG_EQUIV: + case REG_NONNEG: + /* These notes say something about results of an insn. We can + only support them if they used to be on I3 in which case they + remain on I3. Otherwise they are ignored. + + If the note refers to an expression that is not a constant, we + must also ignore the note since we cannot tell whether the + equivalence is still true. It might be possible to do + slightly better than this (we only have a problem if I2DEST + or I1DEST is present in the expression), but it doesn't + seem worth the trouble. */ + + if (from_insn == i3 + && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) + place = i3; + break; + + case REG_INC: + case REG_NO_CONFLICT: + case REG_LABEL: + /* These notes say something about how a register is used. They must + be present on any use of the register in I2 or I3. */ + if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) + place = i3; + + if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) + { + if (place) + place2 = i2; + else + place = i2; + } + break; + + case REG_WAS_0: + /* It is too much trouble to try to see if this note is still + correct in all situations. It is better to simply delete it. */ + break; + + case REG_RETVAL: + /* If the insn previously containing this note still exists, + put it back where it was. Otherwise move it to the previous + insn. Adjust the corresponding REG_LIBCALL note. */ + if (GET_CODE (from_insn) != NOTE) + place = from_insn; + else + { + tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX); + place = prev_real_insn (from_insn); + if (tem && place) + XEXP (tem, 0) = place; + } + break; + + case REG_LIBCALL: + /* This is handled similarly to REG_RETVAL. */ + if (GET_CODE (from_insn) != NOTE) + place = from_insn; + else + { + tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX); + place = next_real_insn (from_insn); + if (tem && place) + XEXP (tem, 0) = place; + } + break; + + case REG_DEAD: + /* If the register is used as an input in I3, it dies there. + Similarly for I2, if it is non-zero and adjacent to I3. + + If the register is not used as an input in either I3 or I2 + and it is not one of the registers we were supposed to eliminate, + there are two possibilities. We might have a non-adjacent I2 + or we might have somehow eliminated an additional register + from a computation. For example, we might have had A & B where + we discover that B will always be zero. In this case we will + eliminate the reference to A. + + In both cases, we must search to see if we can find a previous + use of A and put the death note there. */ + + if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) + place = i3; + else if (i2 != 0 && next_nonnote_insn (i2) == i3 + && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) + place = i2; + + if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1) + break; + + /* If the register is used in both I2 and I3 and it dies in I3, + we might have added another reference to it. If reg_n_refs + was 2, bump it to 3. This has to be correct since the + register must have been set somewhere. The reason this is + done is because local-alloc.c treats 2 references as a + special case. */ + + if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG + && reg_n_refs[REGNO (XEXP (note, 0))]== 2 + && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) + reg_n_refs[REGNO (XEXP (note, 0))] = 3; + + if (place == 0) + for (tem = prev_nonnote_insn (i3); + tem && (GET_CODE (tem) == INSN + || GET_CODE (tem) == CALL_INSN); + tem = prev_nonnote_insn (tem)) + { + /* If the register is being set at TEM, see if that is all + TEM is doing. If so, delete TEM. Otherwise, make this + into a REG_UNUSED note instead. */ + if (reg_set_p (XEXP (note, 0), PATTERN (tem))) + { + rtx set = single_set (tem); + + /* Verify that it was the set, and not a clobber that + modified the register. */ + + if (set != 0 && ! side_effects_p (SET_SRC (set)) + && rtx_equal_p (XEXP (note, 0), SET_DEST (set))) + { + /* Move the notes and links of TEM elsewhere. + This might delete other dead insns recursively. + First set the pattern to something that won't use + any register. */ + + PATTERN (tem) = pc_rtx; + + distribute_notes (REG_NOTES (tem), tem, tem, + NULL_RTX, NULL_RTX, NULL_RTX); + distribute_links (LOG_LINKS (tem)); + + PUT_CODE (tem, NOTE); + NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (tem) = 0; + } + else + { + PUT_REG_NOTE_KIND (note, REG_UNUSED); + + /* If there isn't already a REG_UNUSED note, put one + here. */ + if (! find_regno_note (tem, REG_UNUSED, + REGNO (XEXP (note, 0)))) + place = tem; + break; + } + } + else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))) + { + place = tem; + break; + } + } + + /* If the register is set or already dead at PLACE, we needn't do + anything with this note if it is still a REG_DEAD note. + + Note that we cannot use just `dead_or_set_p' here since we can + convert an assignment to a register into a bit-field assignment. + Therefore, we must also omit the note if the register is the + target of a bitfield assignment. */ + + if (place && REG_NOTE_KIND (note) == REG_DEAD) + { + int regno = REGNO (XEXP (note, 0)); + + if (dead_or_set_p (place, XEXP (note, 0)) + || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) + { + /* Unless the register previously died in PLACE, clear + reg_last_death. [I no longer understand why this is + being done.] */ + if (reg_last_death[regno] != place) + reg_last_death[regno] = 0; + place = 0; + } + else + reg_last_death[regno] = place; + + /* If this is a death note for a hard reg that is occupying + multiple registers, ensure that we are still using all + parts of the object. If we find a piece of the object + that is unused, we must add a USE for that piece before + PLACE and put the appropriate REG_DEAD note on it. + + An alternative would be to put a REG_UNUSED for the pieces + on the insn that set the register, but that can't be done if + it is not in the same block. It is simpler, though less + efficient, to add the USE insns. */ + + if (place && regno < FIRST_PSEUDO_REGISTER + && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1) + { + int endregno + = regno + HARD_REGNO_NREGS (regno, + GET_MODE (XEXP (note, 0))); + int all_used = 1; + int i; + + for (i = regno; i < endregno; i++) + if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)) + { + rtx piece = gen_rtx (REG, word_mode, i); + rtx p; + + /* See if we already placed a USE note for this + register in front of PLACE. */ + for (p = place; + GET_CODE (PREV_INSN (p)) == INSN + && GET_CODE (PATTERN (PREV_INSN (p))) == USE; + p = PREV_INSN (p)) + if (rtx_equal_p (piece, + XEXP (PATTERN (PREV_INSN (p)), 0))) + { + p = 0; + break; + } + + if (p) + { + rtx use_insn + = emit_insn_before (gen_rtx (USE, VOIDmode, + piece), + p); + REG_NOTES (use_insn) + = gen_rtx (EXPR_LIST, REG_DEAD, piece, + REG_NOTES (use_insn)); + } + + all_used = 0; + } + + /* Check for the case where the register dying partially + overlaps the register set by this insn. */ + if (all_used) + for (i = regno; i < endregno; i++) + if (dead_or_set_regno_p (place, i)) + { + all_used = 0; + break; + } + + if (! all_used) + { + /* Put only REG_DEAD notes for pieces that are + still used and that are not already dead or set. */ + + for (i = regno; i < endregno; i++) + { + rtx piece = gen_rtx (REG, word_mode, i); + + if (reg_referenced_p (piece, PATTERN (place)) + && ! dead_or_set_p (place, piece) + && ! reg_bitfield_target_p (piece, + PATTERN (place))) + REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD, + piece, + REG_NOTES (place)); + } + + place = 0; + } + } + } + break; + + default: + /* Any other notes should not be present at this point in the + compilation. */ + abort (); + } + + if (place) + { + XEXP (note, 1) = REG_NOTES (place); + REG_NOTES (place) = note; + } + else if ((REG_NOTE_KIND (note) == REG_DEAD + || REG_NOTE_KIND (note) == REG_UNUSED) + && GET_CODE (XEXP (note, 0)) == REG) + reg_n_deaths[REGNO (XEXP (note, 0))]--; + + if (place2) + { + if ((REG_NOTE_KIND (note) == REG_DEAD + || REG_NOTE_KIND (note) == REG_UNUSED) + && GET_CODE (XEXP (note, 0)) == REG) + reg_n_deaths[REGNO (XEXP (note, 0))]++; + + REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note), + XEXP (note, 0), REG_NOTES (place2)); + } + } +} + +/* Similarly to above, distribute the LOG_LINKS that used to be present on + I3, I2, and I1 to new locations. This is also called in one case to + add a link pointing at I3 when I3's destination is changed. */ + +static void +distribute_links (links) + rtx links; +{ + rtx link, next_link; + + for (link = links; link; link = next_link) + { + rtx place = 0; + rtx insn; + rtx set, reg; + + next_link = XEXP (link, 1); + + /* If the insn that this link points to is a NOTE or isn't a single + set, ignore it. In the latter case, it isn't clear what we + can do other than ignore the link, since we can't tell which + register it was for. Such links wouldn't be used by combine + anyway. + + It is not possible for the destination of the target of the link to + have been changed by combine. The only potential of this is if we + replace I3, I2, and I1 by I3 and I2. But in that case the + destination of I2 also remains unchanged. */ + + if (GET_CODE (XEXP (link, 0)) == NOTE + || (set = single_set (XEXP (link, 0))) == 0) + continue; + + reg = SET_DEST (set); + while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT + || GET_CODE (reg) == SIGN_EXTRACT + || GET_CODE (reg) == STRICT_LOW_PART) + reg = XEXP (reg, 0); + + /* A LOG_LINK is defined as being placed on the first insn that uses + a register and points to the insn that sets the register. Start + searching at the next insn after the target of the link and stop + when we reach a set of the register or the end of the basic block. + + Note that this correctly handles the link that used to point from + I3 to I2. Also note that not much searching is typically done here + since most links don't point very far away. */ + + for (insn = NEXT_INSN (XEXP (link, 0)); + (insn && GET_CODE (insn) != CODE_LABEL + && GET_CODE (PREV_INSN (insn)) != JUMP_INSN); + insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_overlap_mentioned_p (reg, PATTERN (insn))) + { + if (reg_referenced_p (reg, PATTERN (insn))) + place = insn; + break; + } + + /* If we found a place to put the link, place it there unless there + is already a link to the same insn as LINK at that point. */ + + if (place) + { + rtx link2; + + for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) + if (XEXP (link2, 0) == XEXP (link, 0)) + break; + + if (link2 == 0) + { + XEXP (link, 1) = LOG_LINKS (place); + LOG_LINKS (place) = link; + } + } + } +} + +void +dump_combine_stats (file) + FILE *file; +{ + fprintf + (file, + ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", + combine_attempts, combine_merges, combine_extras, combine_successes); +} + +void +dump_combine_total_stats (file) + FILE *file; +{ + fprintf + (file, + "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", + total_attempts, total_merges, total_extras, total_successes); +} diff --git a/gnu/usr.bin/cc/lib/conditions.h b/gnu/usr.bin/cc/lib/conditions.h new file mode 100644 index 000000000000..e7319377f37a --- /dev/null +++ b/gnu/usr.bin/cc/lib/conditions.h @@ -0,0 +1,115 @@ +/* Definitions for condition code handling in final.c and output routines. + Copyright (C) 1987 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* None of the things in the files exist if we don't use CC0. */ + +#ifdef HAVE_cc0 + +/* The variable cc_status says how to interpret the condition code. + It is set by output routines for an instruction that sets the cc's + and examined by output routines for jump instructions. + + cc_status contains two components named `value1' and `value2' + that record two equivalent expressions for the values that the + condition codes were set from. (Either or both may be null if + there is no useful expression to record.) These fields are + used for eliminating redundant test and compare instructions + in the cases where the condition codes were already set by the + previous instruction. + + cc_status.flags contains flags which say that the condition codes + were set in a nonstandard manner. The output of jump instructions + uses these flags to compensate and produce the standard result + with the nonstandard condition codes. Standard flags are defined here. + The tm.h file can also define other machine-dependent flags. + + cc_status also contains a machine-dependent component `mdep' + whose type, `CC_STATUS_MDEP', may be defined as a macro in the + tm.h file. */ + +#ifndef CC_STATUS_MDEP +#define CC_STATUS_MDEP int +#endif + +#ifndef CC_STATUS_MDEP_INIT +#define CC_STATUS_MDEP_INIT 0 +#endif + +typedef struct {int flags; rtx value1, value2; CC_STATUS_MDEP mdep;} CC_STATUS; + +/* While outputting an insn as assembler code, + this is the status BEFORE that insn. */ +extern CC_STATUS cc_prev_status; + +/* While outputting an insn as assembler code, + this is being altered to the status AFTER that insn. */ +extern CC_STATUS cc_status; + +/* These are the machine-independent flags: */ + +/* Set if the sign of the cc value is inverted: + output a following jump-if-less as a jump-if-greater, etc. */ +#define CC_REVERSED 1 + +/* This bit means that the current setting of the N bit is bogus + and conditional jumps should use the Z bit in its place. + This state obtains when an extraction of a signed single-bit field + or an arithmetic shift right of a byte by 7 bits + is turned into a btst, because btst does not set the N bit. */ +#define CC_NOT_POSITIVE 2 + +/* This bit means that the current setting of the N bit is bogus + and conditional jumps should pretend that the N bit is clear. + Used after extraction of an unsigned bit + or logical shift right of a byte by 7 bits is turned into a btst. + The btst does not alter the N bit, but the result of that shift + or extract is never negative. */ +#define CC_NOT_NEGATIVE 4 + +/* This bit means that the current setting of the overflow flag + is bogus and conditional jumps should pretend there is no overflow. */ +#define CC_NO_OVERFLOW 010 + +/* This bit means that what ought to be in the Z bit + should be tested as the complement of the N bit. */ +#define CC_Z_IN_NOT_N 020 + +/* This bit means that what ought to be in the Z bit + should be tested as the N bit. */ +#define CC_Z_IN_N 040 + +/* Nonzero if we must invert the sense of the following branch, i.e. + change EQ to NE. This is not safe for IEEE floating point operations! + It is intended for use only when a combination of arithmetic + or logical insns can leave the condition codes set in a fortuitous + (though inverted) state. */ +#define CC_INVERTED 0100 + +/* Nonzero if we must convert signed condition operators to unsigned. + This is only used by machine description files. */ +#define CC_NOT_SIGNED 0200 + +/* This is how to initialize the variable cc_status. + final does this at appropriate moments. */ + +#define CC_STATUS_INIT \ + (cc_status.flags = 0, cc_status.value1 = 0, cc_status.value2 = 0, \ + CC_STATUS_MDEP_INIT) + +#endif diff --git a/gnu/usr.bin/cc/lib/config.h b/gnu/usr.bin/cc/lib/config.h new file mode 100644 index 000000000000..0c71d617504d --- /dev/null +++ b/gnu/usr.bin/cc/lib/config.h @@ -0,0 +1,52 @@ +/* Configuration for GNU C-compiler for Intel 80386. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef i386 +#define i386 +#endif + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +/* If compiled with GNU C, use the built-in alloca */ +#ifdef __GNUC__ +#undef alloca +#define alloca __builtin_alloca +#endif + +#define ASM_SPEC " %| %{fpic:-k} %{fPIC:-k}" +#define LINK_SPEC \ + "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}" + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ + +#include "tm.h" diff --git a/gnu/usr.bin/cc/lib/convert.c b/gnu/usr.bin/cc/lib/convert.c new file mode 100644 index 000000000000..d073ac3ee625 --- /dev/null +++ b/gnu/usr.bin/cc/lib/convert.c @@ -0,0 +1,443 @@ +/* Utility routines for data type conversion for GNU C. + Copyright (C) 1987, 1988, 1991, 1992 Free Software Foundation, Inc. + +This file is part of GNU C. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* These routines are somewhat language-independent utility function + intended to be called by the language-specific convert () functions. */ + +#include "config.h" +#include "tree.h" +#include "flags.h" +#include "convert.h" + +/* Convert EXPR to some pointer type TYPE. + + EXPR must be pointer, integer, enumeral, or literal zero; + in other cases error is called. */ + +tree +convert_to_pointer (type, expr) + tree type, expr; +{ + register tree intype = TREE_TYPE (expr); + register enum tree_code form = TREE_CODE (intype); + + if (integer_zerop (expr)) + { + if (type == TREE_TYPE (null_pointer_node)) + return null_pointer_node; + expr = build_int_2 (0, 0); + TREE_TYPE (expr) = type; + return expr; + } + + if (form == POINTER_TYPE) + return build1 (NOP_EXPR, type, expr); + + + if (form == INTEGER_TYPE || form == ENUMERAL_TYPE) + { + if (type_precision (intype) == POINTER_SIZE) + return build1 (CONVERT_EXPR, type, expr); + expr = convert (type_for_size (POINTER_SIZE, 0), expr); + /* Modes may be different but sizes should be the same. */ + if (GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (expr))) + != GET_MODE_SIZE (TYPE_MODE (type))) + /* There is supposed to be some integral type + that is the same width as a pointer. */ + abort (); + return convert_to_pointer (type, expr); + } + + error ("cannot convert to a pointer type"); + + return null_pointer_node; +} + +/* Convert EXPR to some floating-point type TYPE. + + EXPR must be float, integer, or enumeral; + in other cases error is called. */ + +tree +convert_to_real (type, expr) + tree type, expr; +{ + register enum tree_code form = TREE_CODE (TREE_TYPE (expr)); + + if (form == REAL_TYPE) + return build1 (flag_float_store ? CONVERT_EXPR : NOP_EXPR, + type, expr); + + if (form == INTEGER_TYPE || form == ENUMERAL_TYPE) + return build1 (FLOAT_EXPR, type, expr); + + if (form == COMPLEX_TYPE) + return convert (type, fold (build1 (REALPART_EXPR, + TREE_TYPE (TREE_TYPE (expr)), expr))); + + if (form == POINTER_TYPE) + error ("pointer value used where a floating point value was expected"); + else + error ("aggregate value used where a float was expected"); + + { + register tree tem = make_node (REAL_CST); + TREE_TYPE (tem) = type; + TREE_REAL_CST (tem) = REAL_VALUE_ATOF ("0.0", TYPE_MODE (type)); + return tem; + } +} + +/* Convert EXPR to some integer (or enum) type TYPE. + + EXPR must be pointer, integer, discrete (enum, char, or bool), or float; + in other cases error is called. + + The result of this is always supposed to be a newly created tree node + not in use in any existing structure. */ + +tree +convert_to_integer (type, expr) + tree type, expr; +{ + register tree intype = TREE_TYPE (expr); + register enum tree_code form = TREE_CODE (intype); + + if (form == POINTER_TYPE) + { + if (integer_zerop (expr)) + expr = integer_zero_node; + else + expr = fold (build1 (CONVERT_EXPR, + type_for_size (POINTER_SIZE, 0), expr)); + intype = TREE_TYPE (expr); + form = TREE_CODE (intype); + if (intype == type) + return expr; + } + + if (form == INTEGER_TYPE || form == ENUMERAL_TYPE + || form == BOOLEAN_TYPE || form == CHAR_TYPE) + { + register unsigned outprec = TYPE_PRECISION (type); + register unsigned inprec = TYPE_PRECISION (intype); + register enum tree_code ex_form = TREE_CODE (expr); + + /* If we are widening the type, put in an explicit conversion. + Similarly if we are not changing the width. However, if this is + a logical operation that just returns 0 or 1, we can change the + type of the expression (see below). */ + + if (TREE_CODE_CLASS (ex_form) == '<' + || ex_form == TRUTH_AND_EXPR || ex_form == TRUTH_ANDIF_EXPR + || ex_form == TRUTH_OR_EXPR || ex_form == TRUTH_ORIF_EXPR + || ex_form == TRUTH_XOR_EXPR || ex_form == TRUTH_NOT_EXPR) + { + TREE_TYPE (expr) = type; + return expr; + } + else if (outprec >= inprec) + return build1 (NOP_EXPR, type, expr); + +/* Here detect when we can distribute the truncation down past some arithmetic. + For example, if adding two longs and converting to an int, + we can equally well convert both to ints and then add. + For the operations handled here, such truncation distribution + is always safe. + It is desirable in these cases: + 1) when truncating down to full-word from a larger size + 2) when truncating takes no work. + 3) when at least one operand of the arithmetic has been extended + (as by C's default conversions). In this case we need two conversions + if we do the arithmetic as already requested, so we might as well + truncate both and then combine. Perhaps that way we need only one. + + Note that in general we cannot do the arithmetic in a type + shorter than the desired result of conversion, even if the operands + are both extended from a shorter type, because they might overflow + if combined in that type. The exceptions to this--the times when + two narrow values can be combined in their narrow type even to + make a wider result--are handled by "shorten" in build_binary_op. */ + + switch (ex_form) + { + case RSHIFT_EXPR: + /* We can pass truncation down through right shifting + when the shift count is a nonpositive constant. */ + if (TREE_CODE (TREE_OPERAND (expr, 1)) == INTEGER_CST + && tree_int_cst_lt (TREE_OPERAND (expr, 1), integer_one_node)) + goto trunc1; + break; + + case LSHIFT_EXPR: + /* We can pass truncation down through left shifting + when the shift count is a nonnegative constant. */ + if (TREE_CODE (TREE_OPERAND (expr, 1)) == INTEGER_CST + && ! tree_int_cst_lt (TREE_OPERAND (expr, 1), integer_zero_node) + && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) + { + /* If shift count is less than the width of the truncated type, + really shift. */ + if (tree_int_cst_lt (TREE_OPERAND (expr, 1), TYPE_SIZE (type))) + /* In this case, shifting is like multiplication. */ + goto trunc1; + else + { + /* If it is >= that width, result is zero. + Handling this with trunc1 would give the wrong result: + (int) ((long long) a << 32) is well defined (as 0) + but (int) a << 32 is undefined and would get a + warning. */ + + tree t = convert_to_integer (type, integer_zero_node); + + /* If the original expression had side-effects, we must + preserve it. */ + if (TREE_SIDE_EFFECTS (expr)) + return build (COMPOUND_EXPR, type, expr, t); + else + return t; + } + } + break; + + case MAX_EXPR: + case MIN_EXPR: + case MULT_EXPR: + { + tree arg0 = get_unwidened (TREE_OPERAND (expr, 0), type); + tree arg1 = get_unwidened (TREE_OPERAND (expr, 1), type); + + /* Don't distribute unless the output precision is at least as big + as the actual inputs. Otherwise, the comparison of the + truncated values will be wrong. */ + if (outprec >= TYPE_PRECISION (TREE_TYPE (arg0)) + && outprec >= TYPE_PRECISION (TREE_TYPE (arg1)) + /* If signedness of arg0 and arg1 don't match, + we can't necessarily find a type to compare them in. */ + && (TREE_UNSIGNED (TREE_TYPE (arg0)) + == TREE_UNSIGNED (TREE_TYPE (arg1)))) + goto trunc1; + break; + } + + case PLUS_EXPR: + case MINUS_EXPR: + case BIT_AND_EXPR: + case BIT_IOR_EXPR: + case BIT_XOR_EXPR: + case BIT_ANDTC_EXPR: + trunc1: + { + tree arg0 = get_unwidened (TREE_OPERAND (expr, 0), type); + tree arg1 = get_unwidened (TREE_OPERAND (expr, 1), type); + + if (outprec >= BITS_PER_WORD + || TRULY_NOOP_TRUNCATION (outprec, inprec) + || inprec > TYPE_PRECISION (TREE_TYPE (arg0)) + || inprec > TYPE_PRECISION (TREE_TYPE (arg1))) + { + /* Do the arithmetic in type TYPEX, + then convert result to TYPE. */ + register tree typex = type; + + /* Can't do arithmetic in enumeral types + so use an integer type that will hold the values. */ + if (TREE_CODE (typex) == ENUMERAL_TYPE) + typex = type_for_size (TYPE_PRECISION (typex), + TREE_UNSIGNED (typex)); + + /* But now perhaps TYPEX is as wide as INPREC. + In that case, do nothing special here. + (Otherwise would recurse infinitely in convert. */ + if (TYPE_PRECISION (typex) != inprec) + { + /* Don't do unsigned arithmetic where signed was wanted, + or vice versa. + Exception: if either of the original operands were + unsigned then can safely do the work as unsigned. + And we may need to do it as unsigned + if we truncate to the original size. */ + typex = ((TREE_UNSIGNED (TREE_TYPE (expr)) + || TREE_UNSIGNED (TREE_TYPE (arg0)) + || TREE_UNSIGNED (TREE_TYPE (arg1))) + ? unsigned_type (typex) : signed_type (typex)); + return convert (type, + fold (build (ex_form, typex, + convert (typex, arg0), + convert (typex, arg1), + 0))); + } + } + } + break; + + case NEGATE_EXPR: + case BIT_NOT_EXPR: + case ABS_EXPR: + { + register tree typex = type; + + /* Can't do arithmetic in enumeral types + so use an integer type that will hold the values. */ + if (TREE_CODE (typex) == ENUMERAL_TYPE) + typex = type_for_size (TYPE_PRECISION (typex), + TREE_UNSIGNED (typex)); + + /* But now perhaps TYPEX is as wide as INPREC. + In that case, do nothing special here. + (Otherwise would recurse infinitely in convert. */ + if (TYPE_PRECISION (typex) != inprec) + { + /* Don't do unsigned arithmetic where signed was wanted, + or vice versa. */ + typex = (TREE_UNSIGNED (TREE_TYPE (expr)) + ? unsigned_type (typex) : signed_type (typex)); + return convert (type, + fold (build1 (ex_form, typex, + convert (typex, + TREE_OPERAND (expr, 0))))); + } + } + + case NOP_EXPR: + /* If truncating after truncating, might as well do all at once. + If truncating after extending, we may get rid of wasted work. */ + return convert (type, get_unwidened (TREE_OPERAND (expr, 0), type)); + + case COND_EXPR: + /* Can treat the two alternative values like the operands + of an arithmetic expression. */ + { + tree arg1 = get_unwidened (TREE_OPERAND (expr, 1), type); + tree arg2 = get_unwidened (TREE_OPERAND (expr, 2), type); + + if (outprec >= BITS_PER_WORD + || TRULY_NOOP_TRUNCATION (outprec, inprec) + || inprec > TYPE_PRECISION (TREE_TYPE (arg1)) + || inprec > TYPE_PRECISION (TREE_TYPE (arg2))) + { + /* Do the arithmetic in type TYPEX, + then convert result to TYPE. */ + register tree typex = type; + + /* Can't do arithmetic in enumeral types + so use an integer type that will hold the values. */ + if (TREE_CODE (typex) == ENUMERAL_TYPE) + typex = type_for_size (TYPE_PRECISION (typex), + TREE_UNSIGNED (typex)); + + /* But now perhaps TYPEX is as wide as INPREC. + In that case, do nothing special here. + (Otherwise would recurse infinitely in convert. */ + if (TYPE_PRECISION (typex) != inprec) + { + /* Don't do unsigned arithmetic where signed was wanted, + or vice versa. */ + typex = (TREE_UNSIGNED (TREE_TYPE (expr)) + ? unsigned_type (typex) : signed_type (typex)); + return convert (type, + fold (build (COND_EXPR, typex, + TREE_OPERAND (expr, 0), + convert (typex, arg1), + convert (typex, arg2)))); + } + else + /* It is sometimes worthwhile + to push the narrowing down through the conditional. */ + return fold (build (COND_EXPR, type, + TREE_OPERAND (expr, 0), + convert (type, TREE_OPERAND (expr, 1)), + convert (type, TREE_OPERAND (expr, 2)))); + } + } + + } + + return build1 (NOP_EXPR, type, expr); + } + + if (form == REAL_TYPE) + return build1 (FIX_TRUNC_EXPR, type, expr); + + if (form == COMPLEX_TYPE) + return convert (type, fold (build1 (REALPART_EXPR, + TREE_TYPE (TREE_TYPE (expr)), expr))); + + error ("aggregate value used where an integer was expected"); + + { + register tree tem = build_int_2 (0, 0); + TREE_TYPE (tem) = type; + return tem; + } +} + +/* Convert EXPR to the complex type TYPE in the usual ways. */ + +tree +convert_to_complex (type, expr) + tree type, expr; +{ + register enum tree_code form = TREE_CODE (TREE_TYPE (expr)); + tree subtype = TREE_TYPE (type); + + if (form == REAL_TYPE || form == INTEGER_TYPE || form == ENUMERAL_TYPE) + { + expr = convert (subtype, expr); + return build (COMPLEX_EXPR, type, expr, + convert (subtype, integer_zero_node)); + } + + if (form == COMPLEX_TYPE) + { + tree elt_type = TREE_TYPE (TREE_TYPE (expr)); + if (TYPE_MAIN_VARIANT (elt_type) == TYPE_MAIN_VARIANT (subtype)) + return expr; + else if (TREE_CODE (expr) == COMPLEX_EXPR) + return fold (build (COMPLEX_EXPR, + type, + convert (subtype, TREE_OPERAND (expr, 0)), + convert (subtype, TREE_OPERAND (expr, 1)))); + else + { + expr = save_expr (expr); + return fold (build (COMPLEX_EXPR, + type, + convert (subtype, + fold (build1 (REALPART_EXPR, + TREE_TYPE (TREE_TYPE (expr)), + expr))), + convert (subtype, + fold (build1 (IMAGPART_EXPR, + TREE_TYPE (TREE_TYPE (expr)), + expr))))); + } + } + + if (form == POINTER_TYPE) + error ("pointer value used where a complex was expected"); + else + error ("aggregate value used where a complex was expected"); + + return build (COMPLEX_EXPR, type, + convert (subtype, integer_zero_node), + convert (subtype, integer_zero_node)); +} diff --git a/gnu/usr.bin/cc/lib/convert.h b/gnu/usr.bin/cc/lib/convert.h new file mode 100644 index 000000000000..b2c8c7947573 --- /dev/null +++ b/gnu/usr.bin/cc/lib/convert.h @@ -0,0 +1,23 @@ +/* Definition of functions in convert.c. + Copyright (C) 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +extern tree convert_to_integer PROTO ((tree, tree)); +extern tree convert_to_pointer PROTO ((tree, tree)); +extern tree convert_to_real PROTO ((tree, tree)); +extern tree convert_to_complex PROTO ((tree, tree)); diff --git a/gnu/usr.bin/cc/lib/cse.c b/gnu/usr.bin/cc/lib/cse.c new file mode 100644 index 000000000000..792fa7b2f5f5 --- /dev/null +++ b/gnu/usr.bin/cc/lib/cse.c @@ -0,0 +1,8243 @@ +/* Common subexpression elimination for GNU compiler. + Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "flags.h" +#include "real.h" +#include "insn-config.h" +#include "recog.h" + +#include +#include + +/* The basic idea of common subexpression elimination is to go + through the code, keeping a record of expressions that would + have the same value at the current scan point, and replacing + expressions encountered with the cheapest equivalent expression. + + It is too complicated to keep track of the different possibilities + when control paths merge; so, at each label, we forget all that is + known and start fresh. This can be described as processing each + basic block separately. Note, however, that these are not quite + the same as the basic blocks found by a later pass and used for + data flow analysis and register packing. We do not need to start fresh + after a conditional jump instruction if there is no label there. + + We use two data structures to record the equivalent expressions: + a hash table for most expressions, and several vectors together + with "quantity numbers" to record equivalent (pseudo) registers. + + The use of the special data structure for registers is desirable + because it is faster. It is possible because registers references + contain a fairly small number, the register number, taken from + a contiguously allocated series, and two register references are + identical if they have the same number. General expressions + do not have any such thing, so the only way to retrieve the + information recorded on an expression other than a register + is to keep it in a hash table. + +Registers and "quantity numbers": + + At the start of each basic block, all of the (hardware and pseudo) + registers used in the function are given distinct quantity + numbers to indicate their contents. During scan, when the code + copies one register into another, we copy the quantity number. + When a register is loaded in any other way, we allocate a new + quantity number to describe the value generated by this operation. + `reg_qty' records what quantity a register is currently thought + of as containing. + + All real quantity numbers are greater than or equal to `max_reg'. + If register N has not been assigned a quantity, reg_qty[N] will equal N. + + Quantity numbers below `max_reg' do not exist and none of the `qty_...' + variables should be referenced with an index below `max_reg'. + + We also maintain a bidirectional chain of registers for each + quantity number. `qty_first_reg', `qty_last_reg', + `reg_next_eqv' and `reg_prev_eqv' hold these chains. + + The first register in a chain is the one whose lifespan is least local. + Among equals, it is the one that was seen first. + We replace any equivalent register with that one. + + If two registers have the same quantity number, it must be true that + REG expressions with `qty_mode' must be in the hash table for both + registers and must be in the same class. + + The converse is not true. Since hard registers may be referenced in + any mode, two REG expressions might be equivalent in the hash table + but not have the same quantity number if the quantity number of one + of the registers is not the same mode as those expressions. + +Constants and quantity numbers + + When a quantity has a known constant value, that value is stored + in the appropriate element of qty_const. This is in addition to + putting the constant in the hash table as is usual for non-regs. + + Whether a reg or a constant is preferred is determined by the configuration + macro CONST_COSTS and will often depend on the constant value. In any + event, expressions containing constants can be simplified, by fold_rtx. + + When a quantity has a known nearly constant value (such as an address + of a stack slot), that value is stored in the appropriate element + of qty_const. + + Integer constants don't have a machine mode. However, cse + determines the intended machine mode from the destination + of the instruction that moves the constant. The machine mode + is recorded in the hash table along with the actual RTL + constant expression so that different modes are kept separate. + +Other expressions: + + To record known equivalences among expressions in general + we use a hash table called `table'. It has a fixed number of buckets + that contain chains of `struct table_elt' elements for expressions. + These chains connect the elements whose expressions have the same + hash codes. + + Other chains through the same elements connect the elements which + currently have equivalent values. + + Register references in an expression are canonicalized before hashing + the expression. This is done using `reg_qty' and `qty_first_reg'. + The hash code of a register reference is computed using the quantity + number, not the register number. + + When the value of an expression changes, it is necessary to remove from the + hash table not just that expression but all expressions whose values + could be different as a result. + + 1. If the value changing is in memory, except in special cases + ANYTHING referring to memory could be changed. That is because + nobody knows where a pointer does not point. + The function `invalidate_memory' removes what is necessary. + + The special cases are when the address is constant or is + a constant plus a fixed register such as the frame pointer + or a static chain pointer. When such addresses are stored in, + we can tell exactly which other such addresses must be invalidated + due to overlap. `invalidate' does this. + All expressions that refer to non-constant + memory addresses are also invalidated. `invalidate_memory' does this. + + 2. If the value changing is a register, all expressions + containing references to that register, and only those, + must be removed. + + Because searching the entire hash table for expressions that contain + a register is very slow, we try to figure out when it isn't necessary. + Precisely, this is necessary only when expressions have been + entered in the hash table using this register, and then the value has + changed, and then another expression wants to be added to refer to + the register's new value. This sequence of circumstances is rare + within any one basic block. + + The vectors `reg_tick' and `reg_in_table' are used to detect this case. + reg_tick[i] is incremented whenever a value is stored in register i. + reg_in_table[i] holds -1 if no references to register i have been + entered in the table; otherwise, it contains the value reg_tick[i] had + when the references were entered. If we want to enter a reference + and reg_in_table[i] != reg_tick[i], we must scan and remove old references. + Until we want to enter a new entry, the mere fact that the two vectors + don't match makes the entries be ignored if anyone tries to match them. + + Registers themselves are entered in the hash table as well as in + the equivalent-register chains. However, the vectors `reg_tick' + and `reg_in_table' do not apply to expressions which are simple + register references. These expressions are removed from the table + immediately when they become invalid, and this can be done even if + we do not immediately search for all the expressions that refer to + the register. + + A CLOBBER rtx in an instruction invalidates its operand for further + reuse. A CLOBBER or SET rtx whose operand is a MEM:BLK + invalidates everything that resides in memory. + +Related expressions: + + Constant expressions that differ only by an additive integer + are called related. When a constant expression is put in + the table, the related expression with no constant term + is also entered. These are made to point at each other + so that it is possible to find out if there exists any + register equivalent to an expression related to a given expression. */ + +/* One plus largest register number used in this function. */ + +static int max_reg; + +/* Length of vectors indexed by quantity number. + We know in advance we will not need a quantity number this big. */ + +static int max_qty; + +/* Next quantity number to be allocated. + This is 1 + the largest number needed so far. */ + +static int next_qty; + +/* Indexed by quantity number, gives the first (or last) (pseudo) register + in the chain of registers that currently contain this quantity. */ + +static int *qty_first_reg; +static int *qty_last_reg; + +/* Index by quantity number, gives the mode of the quantity. */ + +static enum machine_mode *qty_mode; + +/* Indexed by quantity number, gives the rtx of the constant value of the + quantity, or zero if it does not have a known value. + A sum of the frame pointer (or arg pointer) plus a constant + can also be entered here. */ + +static rtx *qty_const; + +/* Indexed by qty number, gives the insn that stored the constant value + recorded in `qty_const'. */ + +static rtx *qty_const_insn; + +/* The next three variables are used to track when a comparison between a + quantity and some constant or register has been passed. In that case, we + know the results of the comparison in case we see it again. These variables + record a comparison that is known to be true. */ + +/* Indexed by qty number, gives the rtx code of a comparison with a known + result involving this quantity. If none, it is UNKNOWN. */ +static enum rtx_code *qty_comparison_code; + +/* Indexed by qty number, gives the constant being compared against in a + comparison of known result. If no such comparison, it is undefined. + If the comparison is not with a constant, it is zero. */ + +static rtx *qty_comparison_const; + +/* Indexed by qty number, gives the quantity being compared against in a + comparison of known result. If no such comparison, if it undefined. + If the comparison is not with a register, it is -1. */ + +static int *qty_comparison_qty; + +#ifdef HAVE_cc0 +/* For machines that have a CC0, we do not record its value in the hash + table since its use is guaranteed to be the insn immediately following + its definition and any other insn is presumed to invalidate it. + + Instead, we store below the value last assigned to CC0. If it should + happen to be a constant, it is stored in preference to the actual + assigned value. In case it is a constant, we store the mode in which + the constant should be interpreted. */ + +static rtx prev_insn_cc0; +static enum machine_mode prev_insn_cc0_mode; +#endif + +/* Previous actual insn. 0 if at first insn of basic block. */ + +static rtx prev_insn; + +/* Insn being scanned. */ + +static rtx this_insn; + +/* Index by (pseudo) register number, gives the quantity number + of the register's current contents. */ + +static int *reg_qty; + +/* Index by (pseudo) register number, gives the number of the next (or + previous) (pseudo) register in the chain of registers sharing the same + value. + + Or -1 if this register is at the end of the chain. + + If reg_qty[N] == N, reg_next_eqv[N] is undefined. */ + +static int *reg_next_eqv; +static int *reg_prev_eqv; + +/* Index by (pseudo) register number, gives the number of times + that register has been altered in the current basic block. */ + +static int *reg_tick; + +/* Index by (pseudo) register number, gives the reg_tick value at which + rtx's containing this register are valid in the hash table. + If this does not equal the current reg_tick value, such expressions + existing in the hash table are invalid. + If this is -1, no expressions containing this register have been + entered in the table. */ + +static int *reg_in_table; + +/* A HARD_REG_SET containing all the hard registers for which there is + currently a REG expression in the hash table. Note the difference + from the above variables, which indicate if the REG is mentioned in some + expression in the table. */ + +static HARD_REG_SET hard_regs_in_table; + +/* A HARD_REG_SET containing all the hard registers that are invalidated + by a CALL_INSN. */ + +static HARD_REG_SET regs_invalidated_by_call; + +/* Two vectors of ints: + one containing max_reg -1's; the other max_reg + 500 (an approximation + for max_qty) elements where element i contains i. + These are used to initialize various other vectors fast. */ + +static int *all_minus_one; +static int *consec_ints; + +/* CUID of insn that starts the basic block currently being cse-processed. */ + +static int cse_basic_block_start; + +/* CUID of insn that ends the basic block currently being cse-processed. */ + +static int cse_basic_block_end; + +/* Vector mapping INSN_UIDs to cuids. + The cuids are like uids but increase monotonically always. + We use them to see whether a reg is used outside a given basic block. */ + +static int *uid_cuid; + +/* Highest UID in UID_CUID. */ +static int max_uid; + +/* Get the cuid of an insn. */ + +#define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)]) + +/* Nonzero if cse has altered conditional jump insns + in such a way that jump optimization should be redone. */ + +static int cse_jumps_altered; + +/* canon_hash stores 1 in do_not_record + if it notices a reference to CC0, PC, or some other volatile + subexpression. */ + +static int do_not_record; + +/* canon_hash stores 1 in hash_arg_in_memory + if it notices a reference to memory within the expression being hashed. */ + +static int hash_arg_in_memory; + +/* canon_hash stores 1 in hash_arg_in_struct + if it notices a reference to memory that's part of a structure. */ + +static int hash_arg_in_struct; + +/* The hash table contains buckets which are chains of `struct table_elt's, + each recording one expression's information. + That expression is in the `exp' field. + + Those elements with the same hash code are chained in both directions + through the `next_same_hash' and `prev_same_hash' fields. + + Each set of expressions with equivalent values + are on a two-way chain through the `next_same_value' + and `prev_same_value' fields, and all point with + the `first_same_value' field at the first element in + that chain. The chain is in order of increasing cost. + Each element's cost value is in its `cost' field. + + The `in_memory' field is nonzero for elements that + involve any reference to memory. These elements are removed + whenever a write is done to an unidentified location in memory. + To be safe, we assume that a memory address is unidentified unless + the address is either a symbol constant or a constant plus + the frame pointer or argument pointer. + + The `in_struct' field is nonzero for elements that + involve any reference to memory inside a structure or array. + + The `related_value' field is used to connect related expressions + (that differ by adding an integer). + The related expressions are chained in a circular fashion. + `related_value' is zero for expressions for which this + chain is not useful. + + The `cost' field stores the cost of this element's expression. + + The `is_const' flag is set if the element is a constant (including + a fixed address). + + The `flag' field is used as a temporary during some search routines. + + The `mode' field is usually the same as GET_MODE (`exp'), but + if `exp' is a CONST_INT and has no machine mode then the `mode' + field is the mode it was being used as. Each constant is + recorded separately for each mode it is used with. */ + + +struct table_elt +{ + rtx exp; + struct table_elt *next_same_hash; + struct table_elt *prev_same_hash; + struct table_elt *next_same_value; + struct table_elt *prev_same_value; + struct table_elt *first_same_value; + struct table_elt *related_value; + int cost; + enum machine_mode mode; + char in_memory; + char in_struct; + char is_const; + char flag; +}; + +#define HASHBITS 16 + +/* We don't want a lot of buckets, because we rarely have very many + things stored in the hash table, and a lot of buckets slows + down a lot of loops that happen frequently. */ +#define NBUCKETS 31 + +/* Compute hash code of X in mode M. Special-case case where X is a pseudo + register (hard registers may require `do_not_record' to be set). */ + +#define HASH(X, M) \ + (GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER \ + ? ((((int) REG << 7) + reg_qty[REGNO (X)]) % NBUCKETS) \ + : canon_hash (X, M) % NBUCKETS) + +/* Determine whether register number N is considered a fixed register for CSE. + It is desirable to replace other regs with fixed regs, to reduce need for + non-fixed hard regs. + A reg wins if it is either the frame pointer or designated as fixed, + but not if it is an overlapping register. */ +#ifdef OVERLAPPING_REGNO_P +#define FIXED_REGNO_P(N) \ + (((N) == FRAME_POINTER_REGNUM || fixed_regs[N]) \ + && ! OVERLAPPING_REGNO_P ((N))) +#else +#define FIXED_REGNO_P(N) \ + ((N) == FRAME_POINTER_REGNUM || fixed_regs[N]) +#endif + +/* Compute cost of X, as stored in the `cost' field of a table_elt. Fixed + hard registers and pointers into the frame are the cheapest with a cost + of 0. Next come pseudos with a cost of one and other hard registers with + a cost of 2. Aside from these special cases, call `rtx_cost'. */ + +#define CHEAP_REG(N) \ + ((N) == FRAME_POINTER_REGNUM || (N) == STACK_POINTER_REGNUM \ + || (N) == ARG_POINTER_REGNUM \ + || ((N) >= FIRST_VIRTUAL_REGISTER && (N) <= LAST_VIRTUAL_REGISTER) \ + || ((N) < FIRST_PSEUDO_REGISTER \ + && FIXED_REGNO_P (N) && REGNO_REG_CLASS (N) != NO_REGS)) + +#define COST(X) \ + (GET_CODE (X) == REG \ + ? (CHEAP_REG (REGNO (X)) ? 0 \ + : REGNO (X) >= FIRST_PSEUDO_REGISTER ? 1 \ + : 2) \ + : rtx_cost (X, SET) * 2) + +/* Determine if the quantity number for register X represents a valid index + into the `qty_...' variables. */ + +#define REGNO_QTY_VALID_P(N) (reg_qty[N] != (N)) + +static struct table_elt *table[NBUCKETS]; + +/* Chain of `struct table_elt's made so far for this function + but currently removed from the table. */ + +static struct table_elt *free_element_chain; + +/* Number of `struct table_elt' structures made so far for this function. */ + +static int n_elements_made; + +/* Maximum value `n_elements_made' has had so far in this compilation + for functions previously processed. */ + +static int max_elements_made; + +/* Surviving equivalence class when two equivalence classes are merged + by recording the effects of a jump in the last insn. Zero if the + last insn was not a conditional jump. */ + +static struct table_elt *last_jump_equiv_class; + +/* Set to the cost of a constant pool reference if one was found for a + symbolic constant. If this was found, it means we should try to + convert constants into constant pool entries if they don't fit in + the insn. */ + +static int constant_pool_entries_cost; + +/* Bits describing what kind of values in memory must be invalidated + for a particular instruction. If all three bits are zero, + no memory refs need to be invalidated. Each bit is more powerful + than the preceding ones, and if a bit is set then the preceding + bits are also set. + + Here is how the bits are set: + Pushing onto the stack invalidates only the stack pointer, + writing at a fixed address invalidates only variable addresses, + writing in a structure element at variable address + invalidates all but scalar variables, + and writing in anything else at variable address invalidates everything. */ + +struct write_data +{ + int sp : 1; /* Invalidate stack pointer. */ + int var : 1; /* Invalidate variable addresses. */ + int nonscalar : 1; /* Invalidate all but scalar variables. */ + int all : 1; /* Invalidate all memory refs. */ +}; + +/* Define maximum length of a branch path. */ + +#define PATHLENGTH 10 + +/* This data describes a block that will be processed by cse_basic_block. */ + +struct cse_basic_block_data { + /* Lowest CUID value of insns in block. */ + int low_cuid; + /* Highest CUID value of insns in block. */ + int high_cuid; + /* Total number of SETs in block. */ + int nsets; + /* Last insn in the block. */ + rtx last; + /* Size of current branch path, if any. */ + int path_size; + /* Current branch path, indicating which branches will be taken. */ + struct branch_path { + /* The branch insn. */ + rtx branch; + /* Whether it should be taken or not. AROUND is the same as taken + except that it is used when the destination label is not preceded + by a BARRIER. */ + enum taken {TAKEN, NOT_TAKEN, AROUND} status; + } path[PATHLENGTH]; +}; + +/* Nonzero if X has the form (PLUS frame-pointer integer). We check for + virtual regs here because the simplify_*_operation routines are called + by integrate.c, which is called before virtual register instantiation. */ + +#define FIXED_BASE_PLUS_P(X) \ + ((X) == frame_pointer_rtx || (X) == arg_pointer_rtx \ + || (X) == virtual_stack_vars_rtx \ + || (X) == virtual_incoming_args_rtx \ + || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == CONST_INT \ + && (XEXP (X, 0) == frame_pointer_rtx \ + || XEXP (X, 0) == arg_pointer_rtx \ + || XEXP (X, 0) == virtual_stack_vars_rtx \ + || XEXP (X, 0) == virtual_incoming_args_rtx))) + +/* Similar, but also allows reference to the stack pointer. + + This used to include FIXED_BASE_PLUS_P, however, we can't assume that + arg_pointer_rtx by itself is nonzero, because on at least one machine, + the i960, the arg pointer is zero when it is unused. */ + +#define NONZERO_BASE_PLUS_P(X) \ + ((X) == frame_pointer_rtx \ + || (X) == virtual_stack_vars_rtx \ + || (X) == virtual_incoming_args_rtx \ + || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == CONST_INT \ + && (XEXP (X, 0) == frame_pointer_rtx \ + || XEXP (X, 0) == arg_pointer_rtx \ + || XEXP (X, 0) == virtual_stack_vars_rtx \ + || XEXP (X, 0) == virtual_incoming_args_rtx)) \ + || (X) == stack_pointer_rtx \ + || (X) == virtual_stack_dynamic_rtx \ + || (X) == virtual_outgoing_args_rtx \ + || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == CONST_INT \ + && (XEXP (X, 0) == stack_pointer_rtx \ + || XEXP (X, 0) == virtual_stack_dynamic_rtx \ + || XEXP (X, 0) == virtual_outgoing_args_rtx))) + +static void new_basic_block PROTO((void)); +static void make_new_qty PROTO((int)); +static void make_regs_eqv PROTO((int, int)); +static void delete_reg_equiv PROTO((int)); +static int mention_regs PROTO((rtx)); +static int insert_regs PROTO((rtx, struct table_elt *, int)); +static void free_element PROTO((struct table_elt *)); +static void remove_from_table PROTO((struct table_elt *, int)); +static struct table_elt *get_element PROTO((void)); +static struct table_elt *lookup PROTO((rtx, int, enum machine_mode)), + *lookup_for_remove PROTO((rtx, int, enum machine_mode)); +static rtx lookup_as_function PROTO((rtx, enum rtx_code)); +static struct table_elt *insert PROTO((rtx, struct table_elt *, int, + enum machine_mode)); +static void merge_equiv_classes PROTO((struct table_elt *, + struct table_elt *)); +static void invalidate PROTO((rtx)); +static void remove_invalid_refs PROTO((int)); +static void rehash_using_reg PROTO((rtx)); +static void invalidate_memory PROTO((struct write_data *)); +static void invalidate_for_call PROTO((void)); +static rtx use_related_value PROTO((rtx, struct table_elt *)); +static int canon_hash PROTO((rtx, enum machine_mode)); +static int safe_hash PROTO((rtx, enum machine_mode)); +static int exp_equiv_p PROTO((rtx, rtx, int, int)); +static void set_nonvarying_address_components PROTO((rtx, int, rtx *, + HOST_WIDE_INT *, + HOST_WIDE_INT *)); +static int refers_to_p PROTO((rtx, rtx)); +static int refers_to_mem_p PROTO((rtx, rtx, HOST_WIDE_INT, + HOST_WIDE_INT)); +static int cse_rtx_addr_varies_p PROTO((rtx)); +static rtx canon_reg PROTO((rtx, rtx)); +static void find_best_addr PROTO((rtx, rtx *)); +static enum rtx_code find_comparison_args PROTO((enum rtx_code, rtx *, rtx *, + enum machine_mode *, + enum machine_mode *)); +static rtx cse_gen_binary PROTO((enum rtx_code, enum machine_mode, + rtx, rtx)); +static rtx simplify_plus_minus PROTO((enum rtx_code, enum machine_mode, + rtx, rtx)); +static rtx fold_rtx PROTO((rtx, rtx)); +static rtx equiv_constant PROTO((rtx)); +static void record_jump_equiv PROTO((rtx, int)); +static void record_jump_cond PROTO((enum rtx_code, enum machine_mode, + rtx, rtx, int)); +static void cse_insn PROTO((rtx, int)); +static void note_mem_written PROTO((rtx, struct write_data *)); +static void invalidate_from_clobbers PROTO((struct write_data *, rtx)); +static rtx cse_process_notes PROTO((rtx, rtx)); +static void cse_around_loop PROTO((rtx)); +static void invalidate_skipped_set PROTO((rtx, rtx)); +static void invalidate_skipped_block PROTO((rtx)); +static void cse_check_loop_start PROTO((rtx, rtx)); +static void cse_set_around_loop PROTO((rtx, rtx, rtx)); +static rtx cse_basic_block PROTO((rtx, rtx, struct branch_path *, int)); +static void count_reg_usage PROTO((rtx, int *, int)); + +/* Return an estimate of the cost of computing rtx X. + One use is in cse, to decide which expression to keep in the hash table. + Another is in rtl generation, to pick the cheapest way to multiply. + Other uses like the latter are expected in the future. */ + +/* Return the right cost to give to an operation + to make the cost of the corresponding register-to-register instruction + N times that of a fast register-to-register instruction. */ + +#define COSTS_N_INSNS(N) ((N) * 4 - 2) + +int +rtx_cost (x, outer_code) + rtx x; + enum rtx_code outer_code; +{ + register int i, j; + register enum rtx_code code; + register char *fmt; + register int total; + + if (x == 0) + return 0; + + /* Compute the default costs of certain things. + Note that RTX_COSTS can override the defaults. */ + + code = GET_CODE (x); + switch (code) + { + case MULT: + /* Count multiplication by 2**n as a shift, + because if we are considering it, we would output it as a shift. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) + total = 2; + else + total = COSTS_N_INSNS (5); + break; + case DIV: + case UDIV: + case MOD: + case UMOD: + total = COSTS_N_INSNS (7); + break; + case USE: + /* Used in loop.c and combine.c as a marker. */ + total = 0; + break; + case ASM_OPERANDS: + /* We don't want these to be used in substitutions because + we have no way of validating the resulting insn. So assign + anything containing an ASM_OPERANDS a very high cost. */ + total = 1000; + break; + default: + total = 2; + } + + switch (code) + { + case REG: + return ! CHEAP_REG (REGNO (x)); + + case SUBREG: + /* If we can't tie these modes, make this expensive. The larger + the mode, the more expensive it is. */ + if (! MODES_TIEABLE_P (GET_MODE (x), GET_MODE (SUBREG_REG (x)))) + return COSTS_N_INSNS (2 + + GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD); + return 2; +#ifdef RTX_COSTS + RTX_COSTS (x, code, outer_code); +#endif + CONST_COSTS (x, code, outer_code); + } + + /* Sum the costs of the sub-rtx's, plus cost of this operation, + which is already in total. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + total += rtx_cost (XEXP (x, i), code); + else if (fmt[i] == 'E') + for (j = 0; j < XVECLEN (x, i); j++) + total += rtx_cost (XVECEXP (x, i, j), code); + + return total; +} + +/* Clear the hash table and initialize each register with its own quantity, + for a new basic block. */ + +static void +new_basic_block () +{ + register int i; + + next_qty = max_reg; + + bzero (reg_tick, max_reg * sizeof (int)); + + bcopy (all_minus_one, reg_in_table, max_reg * sizeof (int)); + bcopy (consec_ints, reg_qty, max_reg * sizeof (int)); + CLEAR_HARD_REG_SET (hard_regs_in_table); + + /* The per-quantity values used to be initialized here, but it is + much faster to initialize each as it is made in `make_new_qty'. */ + + for (i = 0; i < NBUCKETS; i++) + { + register struct table_elt *this, *next; + for (this = table[i]; this; this = next) + { + next = this->next_same_hash; + free_element (this); + } + } + + bzero (table, sizeof table); + + prev_insn = 0; + +#ifdef HAVE_cc0 + prev_insn_cc0 = 0; +#endif +} + +/* Say that register REG contains a quantity not in any register before + and initialize that quantity. */ + +static void +make_new_qty (reg) + register int reg; +{ + register int q; + + if (next_qty >= max_qty) + abort (); + + q = reg_qty[reg] = next_qty++; + qty_first_reg[q] = reg; + qty_last_reg[q] = reg; + qty_const[q] = qty_const_insn[q] = 0; + qty_comparison_code[q] = UNKNOWN; + + reg_next_eqv[reg] = reg_prev_eqv[reg] = -1; +} + +/* Make reg NEW equivalent to reg OLD. + OLD is not changing; NEW is. */ + +static void +make_regs_eqv (new, old) + register int new, old; +{ + register int lastr, firstr; + register int q = reg_qty[old]; + + /* Nothing should become eqv until it has a "non-invalid" qty number. */ + if (! REGNO_QTY_VALID_P (old)) + abort (); + + reg_qty[new] = q; + firstr = qty_first_reg[q]; + lastr = qty_last_reg[q]; + + /* Prefer fixed hard registers to anything. Prefer pseudo regs to other + hard regs. Among pseudos, if NEW will live longer than any other reg + of the same qty, and that is beyond the current basic block, + make it the new canonical replacement for this qty. */ + if (! (firstr < FIRST_PSEUDO_REGISTER && FIXED_REGNO_P (firstr)) + /* Certain fixed registers might be of the class NO_REGS. This means + that not only can they not be allocated by the compiler, but + they cannot be used in substitutions or canonicalizations + either. */ + && (new >= FIRST_PSEUDO_REGISTER || REGNO_REG_CLASS (new) != NO_REGS) + && ((new < FIRST_PSEUDO_REGISTER && FIXED_REGNO_P (new)) + || (new >= FIRST_PSEUDO_REGISTER + && (firstr < FIRST_PSEUDO_REGISTER + || ((uid_cuid[regno_last_uid[new]] > cse_basic_block_end + || (uid_cuid[regno_first_uid[new]] + < cse_basic_block_start)) + && (uid_cuid[regno_last_uid[new]] + > uid_cuid[regno_last_uid[firstr]])))))) + { + reg_prev_eqv[firstr] = new; + reg_next_eqv[new] = firstr; + reg_prev_eqv[new] = -1; + qty_first_reg[q] = new; + } + else + { + /* If NEW is a hard reg (known to be non-fixed), insert at end. + Otherwise, insert before any non-fixed hard regs that are at the + end. Registers of class NO_REGS cannot be used as an + equivalent for anything. */ + while (lastr < FIRST_PSEUDO_REGISTER && reg_prev_eqv[lastr] >= 0 + && (REGNO_REG_CLASS (lastr) == NO_REGS || ! FIXED_REGNO_P (lastr)) + && new >= FIRST_PSEUDO_REGISTER) + lastr = reg_prev_eqv[lastr]; + reg_next_eqv[new] = reg_next_eqv[lastr]; + if (reg_next_eqv[lastr] >= 0) + reg_prev_eqv[reg_next_eqv[lastr]] = new; + else + qty_last_reg[q] = new; + reg_next_eqv[lastr] = new; + reg_prev_eqv[new] = lastr; + } +} + +/* Remove REG from its equivalence class. */ + +static void +delete_reg_equiv (reg) + register int reg; +{ + register int n = reg_next_eqv[reg]; + register int p = reg_prev_eqv[reg]; + register int q = reg_qty[reg]; + + /* If invalid, do nothing. N and P above are undefined in that case. */ + if (q == reg) + return; + + if (n != -1) + reg_prev_eqv[n] = p; + else + qty_last_reg[q] = p; + if (p != -1) + reg_next_eqv[p] = n; + else + qty_first_reg[q] = n; + + reg_qty[reg] = reg; +} + +/* Remove any invalid expressions from the hash table + that refer to any of the registers contained in expression X. + + Make sure that newly inserted references to those registers + as subexpressions will be considered valid. + + mention_regs is not called when a register itself + is being stored in the table. + + Return 1 if we have done something that may have changed the hash code + of X. */ + +static int +mention_regs (x) + rtx x; +{ + register enum rtx_code code; + register int i, j; + register char *fmt; + register int changed = 0; + + if (x == 0) + return 0; + + code = GET_CODE (x); + if (code == REG) + { + register int regno = REGNO (x); + register int endregno + = regno + (regno >= FIRST_PSEUDO_REGISTER ? 1 + : HARD_REGNO_NREGS (regno, GET_MODE (x))); + int i; + + for (i = regno; i < endregno; i++) + { + if (reg_in_table[i] >= 0 && reg_in_table[i] != reg_tick[i]) + remove_invalid_refs (i); + + reg_in_table[i] = reg_tick[i]; + } + + return 0; + } + + /* If X is a comparison or a COMPARE and either operand is a register + that does not have a quantity, give it one. This is so that a later + call to record_jump_equiv won't cause X to be assigned a different + hash code and not found in the table after that call. + + It is not necessary to do this here, since rehash_using_reg can + fix up the table later, but doing this here eliminates the need to + call that expensive function in the most common case where the only + use of the register is in the comparison. */ + + if (code == COMPARE || GET_RTX_CLASS (code) == '<') + { + if (GET_CODE (XEXP (x, 0)) == REG + && ! REGNO_QTY_VALID_P (REGNO (XEXP (x, 0)))) + if (insert_regs (XEXP (x, 0), NULL_PTR, 0)) + { + rehash_using_reg (XEXP (x, 0)); + changed = 1; + } + + if (GET_CODE (XEXP (x, 1)) == REG + && ! REGNO_QTY_VALID_P (REGNO (XEXP (x, 1)))) + if (insert_regs (XEXP (x, 1), NULL_PTR, 0)) + { + rehash_using_reg (XEXP (x, 1)); + changed = 1; + } + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + changed |= mention_regs (XEXP (x, i)); + else if (fmt[i] == 'E') + for (j = 0; j < XVECLEN (x, i); j++) + changed |= mention_regs (XVECEXP (x, i, j)); + + return changed; +} + +/* Update the register quantities for inserting X into the hash table + with a value equivalent to CLASSP. + (If the class does not contain a REG, it is irrelevant.) + If MODIFIED is nonzero, X is a destination; it is being modified. + Note that delete_reg_equiv should be called on a register + before insert_regs is done on that register with MODIFIED != 0. + + Nonzero value means that elements of reg_qty have changed + so X's hash code may be different. */ + +static int +insert_regs (x, classp, modified) + rtx x; + struct table_elt *classp; + int modified; +{ + if (GET_CODE (x) == REG) + { + register int regno = REGNO (x); + + /* If REGNO is in the equivalence table already but is of the + wrong mode for that equivalence, don't do anything here. */ + + if (REGNO_QTY_VALID_P (regno) + && qty_mode[reg_qty[regno]] != GET_MODE (x)) + return 0; + + if (modified || ! REGNO_QTY_VALID_P (regno)) + { + if (classp) + for (classp = classp->first_same_value; + classp != 0; + classp = classp->next_same_value) + if (GET_CODE (classp->exp) == REG + && GET_MODE (classp->exp) == GET_MODE (x)) + { + make_regs_eqv (regno, REGNO (classp->exp)); + return 1; + } + + make_new_qty (regno); + qty_mode[reg_qty[regno]] = GET_MODE (x); + return 1; + } + } + + /* If X is a SUBREG, we will likely be inserting the inner register in the + table. If that register doesn't have an assigned quantity number at + this point but does later, the insertion that we will be doing now will + not be accessible because its hash code will have changed. So assign + a quantity number now. */ + + else if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == REG + && ! REGNO_QTY_VALID_P (REGNO (SUBREG_REG (x)))) + { + insert_regs (SUBREG_REG (x), NULL_PTR, 0); + mention_regs (SUBREG_REG (x)); + return 1; + } + else + return mention_regs (x); +} + +/* Look in or update the hash table. */ + +/* Put the element ELT on the list of free elements. */ + +static void +free_element (elt) + struct table_elt *elt; +{ + elt->next_same_hash = free_element_chain; + free_element_chain = elt; +} + +/* Return an element that is free for use. */ + +static struct table_elt * +get_element () +{ + struct table_elt *elt = free_element_chain; + if (elt) + { + free_element_chain = elt->next_same_hash; + return elt; + } + n_elements_made++; + return (struct table_elt *) oballoc (sizeof (struct table_elt)); +} + +/* Remove table element ELT from use in the table. + HASH is its hash code, made using the HASH macro. + It's an argument because often that is known in advance + and we save much time not recomputing it. */ + +static void +remove_from_table (elt, hash) + register struct table_elt *elt; + int hash; +{ + if (elt == 0) + return; + + /* Mark this element as removed. See cse_insn. */ + elt->first_same_value = 0; + + /* Remove the table element from its equivalence class. */ + + { + register struct table_elt *prev = elt->prev_same_value; + register struct table_elt *next = elt->next_same_value; + + if (next) next->prev_same_value = prev; + + if (prev) + prev->next_same_value = next; + else + { + register struct table_elt *newfirst = next; + while (next) + { + next->first_same_value = newfirst; + next = next->next_same_value; + } + } + } + + /* Remove the table element from its hash bucket. */ + + { + register struct table_elt *prev = elt->prev_same_hash; + register struct table_elt *next = elt->next_same_hash; + + if (next) next->prev_same_hash = prev; + + if (prev) + prev->next_same_hash = next; + else if (table[hash] == elt) + table[hash] = next; + else + { + /* This entry is not in the proper hash bucket. This can happen + when two classes were merged by `merge_equiv_classes'. Search + for the hash bucket that it heads. This happens only very + rarely, so the cost is acceptable. */ + for (hash = 0; hash < NBUCKETS; hash++) + if (table[hash] == elt) + table[hash] = next; + } + } + + /* Remove the table element from its related-value circular chain. */ + + if (elt->related_value != 0 && elt->related_value != elt) + { + register struct table_elt *p = elt->related_value; + while (p->related_value != elt) + p = p->related_value; + p->related_value = elt->related_value; + if (p->related_value == p) + p->related_value = 0; + } + + free_element (elt); +} + +/* Look up X in the hash table and return its table element, + or 0 if X is not in the table. + + MODE is the machine-mode of X, or if X is an integer constant + with VOIDmode then MODE is the mode with which X will be used. + + Here we are satisfied to find an expression whose tree structure + looks like X. */ + +static struct table_elt * +lookup (x, hash, mode) + rtx x; + int hash; + enum machine_mode mode; +{ + register struct table_elt *p; + + for (p = table[hash]; p; p = p->next_same_hash) + if (mode == p->mode && ((x == p->exp && GET_CODE (x) == REG) + || exp_equiv_p (x, p->exp, GET_CODE (x) != REG, 0))) + return p; + + return 0; +} + +/* Like `lookup' but don't care whether the table element uses invalid regs. + Also ignore discrepancies in the machine mode of a register. */ + +static struct table_elt * +lookup_for_remove (x, hash, mode) + rtx x; + int hash; + enum machine_mode mode; +{ + register struct table_elt *p; + + if (GET_CODE (x) == REG) + { + int regno = REGNO (x); + /* Don't check the machine mode when comparing registers; + invalidating (REG:SI 0) also invalidates (REG:DF 0). */ + for (p = table[hash]; p; p = p->next_same_hash) + if (GET_CODE (p->exp) == REG + && REGNO (p->exp) == regno) + return p; + } + else + { + for (p = table[hash]; p; p = p->next_same_hash) + if (mode == p->mode && (x == p->exp || exp_equiv_p (x, p->exp, 0, 0))) + return p; + } + + return 0; +} + +/* Look for an expression equivalent to X and with code CODE. + If one is found, return that expression. */ + +static rtx +lookup_as_function (x, code) + rtx x; + enum rtx_code code; +{ + register struct table_elt *p = lookup (x, safe_hash (x, VOIDmode) % NBUCKETS, + GET_MODE (x)); + if (p == 0) + return 0; + + for (p = p->first_same_value; p; p = p->next_same_value) + { + if (GET_CODE (p->exp) == code + /* Make sure this is a valid entry in the table. */ + && exp_equiv_p (p->exp, p->exp, 1, 0)) + return p->exp; + } + + return 0; +} + +/* Insert X in the hash table, assuming HASH is its hash code + and CLASSP is an element of the class it should go in + (or 0 if a new class should be made). + It is inserted at the proper position to keep the class in + the order cheapest first. + + MODE is the machine-mode of X, or if X is an integer constant + with VOIDmode then MODE is the mode with which X will be used. + + For elements of equal cheapness, the most recent one + goes in front, except that the first element in the list + remains first unless a cheaper element is added. The order of + pseudo-registers does not matter, as canon_reg will be called to + find the cheapest when a register is retrieved from the table. + + The in_memory field in the hash table element is set to 0. + The caller must set it nonzero if appropriate. + + You should call insert_regs (X, CLASSP, MODIFY) before calling here, + and if insert_regs returns a nonzero value + you must then recompute its hash code before calling here. + + If necessary, update table showing constant values of quantities. */ + +#define CHEAPER(X,Y) ((X)->cost < (Y)->cost) + +static struct table_elt * +insert (x, classp, hash, mode) + register rtx x; + register struct table_elt *classp; + int hash; + enum machine_mode mode; +{ + register struct table_elt *elt; + + /* If X is a register and we haven't made a quantity for it, + something is wrong. */ + if (GET_CODE (x) == REG && ! REGNO_QTY_VALID_P (REGNO (x))) + abort (); + + /* If X is a hard register, show it is being put in the table. */ + if (GET_CODE (x) == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) + { + int regno = REGNO (x); + int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); + int i; + + for (i = regno; i < endregno; i++) + SET_HARD_REG_BIT (hard_regs_in_table, i); + } + + + /* Put an element for X into the right hash bucket. */ + + elt = get_element (); + elt->exp = x; + elt->cost = COST (x); + elt->next_same_value = 0; + elt->prev_same_value = 0; + elt->next_same_hash = table[hash]; + elt->prev_same_hash = 0; + elt->related_value = 0; + elt->in_memory = 0; + elt->mode = mode; + elt->is_const = (CONSTANT_P (x) + /* GNU C++ takes advantage of this for `this' + (and other const values). */ + || (RTX_UNCHANGING_P (x) + && GET_CODE (x) == REG + && REGNO (x) >= FIRST_PSEUDO_REGISTER) + || FIXED_BASE_PLUS_P (x)); + + if (table[hash]) + table[hash]->prev_same_hash = elt; + table[hash] = elt; + + /* Put it into the proper value-class. */ + if (classp) + { + classp = classp->first_same_value; + if (CHEAPER (elt, classp)) + /* Insert at the head of the class */ + { + register struct table_elt *p; + elt->next_same_value = classp; + classp->prev_same_value = elt; + elt->first_same_value = elt; + + for (p = classp; p; p = p->next_same_value) + p->first_same_value = elt; + } + else + { + /* Insert not at head of the class. */ + /* Put it after the last element cheaper than X. */ + register struct table_elt *p, *next; + for (p = classp; (next = p->next_same_value) && CHEAPER (next, elt); + p = next); + /* Put it after P and before NEXT. */ + elt->next_same_value = next; + if (next) + next->prev_same_value = elt; + elt->prev_same_value = p; + p->next_same_value = elt; + elt->first_same_value = classp; + } + } + else + elt->first_same_value = elt; + + /* If this is a constant being set equivalent to a register or a register + being set equivalent to a constant, note the constant equivalence. + + If this is a constant, it cannot be equivalent to a different constant, + and a constant is the only thing that can be cheaper than a register. So + we know the register is the head of the class (before the constant was + inserted). + + If this is a register that is not already known equivalent to a + constant, we must check the entire class. + + If this is a register that is already known equivalent to an insn, + update `qty_const_insn' to show that `this_insn' is the latest + insn making that quantity equivalent to the constant. */ + + if (elt->is_const && classp && GET_CODE (classp->exp) == REG) + { + qty_const[reg_qty[REGNO (classp->exp)]] + = gen_lowpart_if_possible (qty_mode[reg_qty[REGNO (classp->exp)]], x); + qty_const_insn[reg_qty[REGNO (classp->exp)]] = this_insn; + } + + else if (GET_CODE (x) == REG && classp && ! qty_const[reg_qty[REGNO (x)]]) + { + register struct table_elt *p; + + for (p = classp; p != 0; p = p->next_same_value) + { + if (p->is_const) + { + qty_const[reg_qty[REGNO (x)]] + = gen_lowpart_if_possible (GET_MODE (x), p->exp); + qty_const_insn[reg_qty[REGNO (x)]] = this_insn; + break; + } + } + } + + else if (GET_CODE (x) == REG && qty_const[reg_qty[REGNO (x)]] + && GET_MODE (x) == qty_mode[reg_qty[REGNO (x)]]) + qty_const_insn[reg_qty[REGNO (x)]] = this_insn; + + /* If this is a constant with symbolic value, + and it has a term with an explicit integer value, + link it up with related expressions. */ + if (GET_CODE (x) == CONST) + { + rtx subexp = get_related_value (x); + int subhash; + struct table_elt *subelt, *subelt_prev; + + if (subexp != 0) + { + /* Get the integer-free subexpression in the hash table. */ + subhash = safe_hash (subexp, mode) % NBUCKETS; + subelt = lookup (subexp, subhash, mode); + if (subelt == 0) + subelt = insert (subexp, NULL_PTR, subhash, mode); + /* Initialize SUBELT's circular chain if it has none. */ + if (subelt->related_value == 0) + subelt->related_value = subelt; + /* Find the element in the circular chain that precedes SUBELT. */ + subelt_prev = subelt; + while (subelt_prev->related_value != subelt) + subelt_prev = subelt_prev->related_value; + /* Put new ELT into SUBELT's circular chain just before SUBELT. + This way the element that follows SUBELT is the oldest one. */ + elt->related_value = subelt_prev->related_value; + subelt_prev->related_value = elt; + } + } + + return elt; +} + +/* Given two equivalence classes, CLASS1 and CLASS2, put all the entries from + CLASS2 into CLASS1. This is done when we have reached an insn which makes + the two classes equivalent. + + CLASS1 will be the surviving class; CLASS2 should not be used after this + call. + + Any invalid entries in CLASS2 will not be copied. */ + +static void +merge_equiv_classes (class1, class2) + struct table_elt *class1, *class2; +{ + struct table_elt *elt, *next, *new; + + /* Ensure we start with the head of the classes. */ + class1 = class1->first_same_value; + class2 = class2->first_same_value; + + /* If they were already equal, forget it. */ + if (class1 == class2) + return; + + for (elt = class2; elt; elt = next) + { + int hash; + rtx exp = elt->exp; + enum machine_mode mode = elt->mode; + + next = elt->next_same_value; + + /* Remove old entry, make a new one in CLASS1's class. + Don't do this for invalid entries as we cannot find their + hash code (it also isn't necessary). */ + if (GET_CODE (exp) == REG || exp_equiv_p (exp, exp, 1, 0)) + { + hash_arg_in_memory = 0; + hash_arg_in_struct = 0; + hash = HASH (exp, mode); + + if (GET_CODE (exp) == REG) + delete_reg_equiv (REGNO (exp)); + + remove_from_table (elt, hash); + + if (insert_regs (exp, class1, 0)) + hash = HASH (exp, mode); + new = insert (exp, class1, hash, mode); + new->in_memory = hash_arg_in_memory; + new->in_struct = hash_arg_in_struct; + } + } +} + +/* Remove from the hash table, or mark as invalid, + all expressions whose values could be altered by storing in X. + X is a register, a subreg, or a memory reference with nonvarying address + (because, when a memory reference with a varying address is stored in, + all memory references are removed by invalidate_memory + so specific invalidation is superfluous). + + A nonvarying address may be just a register or just + a symbol reference, or it may be either of those plus + a numeric offset. */ + +static void +invalidate (x) + rtx x; +{ + register int i; + register struct table_elt *p; + rtx base; + HOST_WIDE_INT start, end; + + /* If X is a register, dependencies on its contents + are recorded through the qty number mechanism. + Just change the qty number of the register, + mark it as invalid for expressions that refer to it, + and remove it itself. */ + + if (GET_CODE (x) == REG) + { + register int regno = REGNO (x); + register int hash = HASH (x, GET_MODE (x)); + + /* Remove REGNO from any quantity list it might be on and indicate + that it's value might have changed. If it is a pseudo, remove its + entry from the hash table. + + For a hard register, we do the first two actions above for any + additional hard registers corresponding to X. Then, if any of these + registers are in the table, we must remove any REG entries that + overlap these registers. */ + + delete_reg_equiv (regno); + reg_tick[regno]++; + + if (regno >= FIRST_PSEUDO_REGISTER) + remove_from_table (lookup_for_remove (x, hash, GET_MODE (x)), hash); + else + { + HOST_WIDE_INT in_table + = TEST_HARD_REG_BIT (hard_regs_in_table, regno); + int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); + int tregno, tendregno; + register struct table_elt *p, *next; + + CLEAR_HARD_REG_BIT (hard_regs_in_table, regno); + + for (i = regno + 1; i < endregno; i++) + { + in_table |= TEST_HARD_REG_BIT (hard_regs_in_table, i); + CLEAR_HARD_REG_BIT (hard_regs_in_table, i); + delete_reg_equiv (i); + reg_tick[i]++; + } + + if (in_table) + for (hash = 0; hash < NBUCKETS; hash++) + for (p = table[hash]; p; p = next) + { + next = p->next_same_hash; + + if (GET_CODE (p->exp) != REG + || REGNO (p->exp) >= FIRST_PSEUDO_REGISTER) + continue; + + tregno = REGNO (p->exp); + tendregno + = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (p->exp)); + if (tendregno > regno && tregno < endregno) + remove_from_table (p, hash); + } + } + + return; + } + + if (GET_CODE (x) == SUBREG) + { + if (GET_CODE (SUBREG_REG (x)) != REG) + abort (); + invalidate (SUBREG_REG (x)); + return; + } + + /* X is not a register; it must be a memory reference with + a nonvarying address. Remove all hash table elements + that refer to overlapping pieces of memory. */ + + if (GET_CODE (x) != MEM) + abort (); + + set_nonvarying_address_components (XEXP (x, 0), GET_MODE_SIZE (GET_MODE (x)), + &base, &start, &end); + + for (i = 0; i < NBUCKETS; i++) + { + register struct table_elt *next; + for (p = table[i]; p; p = next) + { + next = p->next_same_hash; + if (refers_to_mem_p (p->exp, base, start, end)) + remove_from_table (p, i); + } + } +} + +/* Remove all expressions that refer to register REGNO, + since they are already invalid, and we are about to + mark that register valid again and don't want the old + expressions to reappear as valid. */ + +static void +remove_invalid_refs (regno) + int regno; +{ + register int i; + register struct table_elt *p, *next; + + for (i = 0; i < NBUCKETS; i++) + for (p = table[i]; p; p = next) + { + next = p->next_same_hash; + if (GET_CODE (p->exp) != REG + && refers_to_regno_p (regno, regno + 1, p->exp, NULL_PTR)) + remove_from_table (p, i); + } +} + +/* Recompute the hash codes of any valid entries in the hash table that + reference X, if X is a register, or SUBREG_REG (X) if X is a SUBREG. + + This is called when we make a jump equivalence. */ + +static void +rehash_using_reg (x) + rtx x; +{ + int i; + struct table_elt *p, *next; + int hash; + + if (GET_CODE (x) == SUBREG) + x = SUBREG_REG (x); + + /* If X is not a register or if the register is known not to be in any + valid entries in the table, we have no work to do. */ + + if (GET_CODE (x) != REG + || reg_in_table[REGNO (x)] < 0 + || reg_in_table[REGNO (x)] != reg_tick[REGNO (x)]) + return; + + /* Scan all hash chains looking for valid entries that mention X. + If we find one and it is in the wrong hash chain, move it. We can skip + objects that are registers, since they are handled specially. */ + + for (i = 0; i < NBUCKETS; i++) + for (p = table[i]; p; p = next) + { + next = p->next_same_hash; + if (GET_CODE (p->exp) != REG && reg_mentioned_p (x, p->exp) + && exp_equiv_p (p->exp, p->exp, 1, 0) + && i != (hash = safe_hash (p->exp, p->mode) % NBUCKETS)) + { + if (p->next_same_hash) + p->next_same_hash->prev_same_hash = p->prev_same_hash; + + if (p->prev_same_hash) + p->prev_same_hash->next_same_hash = p->next_same_hash; + else + table[i] = p->next_same_hash; + + p->next_same_hash = table[hash]; + p->prev_same_hash = 0; + if (table[hash]) + table[hash]->prev_same_hash = p; + table[hash] = p; + } + } +} + +/* Remove from the hash table all expressions that reference memory, + or some of them as specified by *WRITES. */ + +static void +invalidate_memory (writes) + struct write_data *writes; +{ + register int i; + register struct table_elt *p, *next; + int all = writes->all; + int nonscalar = writes->nonscalar; + + for (i = 0; i < NBUCKETS; i++) + for (p = table[i]; p; p = next) + { + next = p->next_same_hash; + if (p->in_memory + && (all + || (nonscalar && p->in_struct) + || cse_rtx_addr_varies_p (p->exp))) + remove_from_table (p, i); + } +} + +/* Remove from the hash table any expression that is a call-clobbered + register. Also update their TICK values. */ + +static void +invalidate_for_call () +{ + int regno, endregno; + int i; + int hash; + struct table_elt *p, *next; + int in_table = 0; + + /* Go through all the hard registers. For each that is clobbered in + a CALL_INSN, remove the register from quantity chains and update + reg_tick if defined. Also see if any of these registers is currently + in the table. */ + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (TEST_HARD_REG_BIT (regs_invalidated_by_call, regno)) + { + delete_reg_equiv (regno); + if (reg_tick[regno] >= 0) + reg_tick[regno]++; + + in_table |= TEST_HARD_REG_BIT (hard_regs_in_table, regno); + } + + /* In the case where we have no call-clobbered hard registers in the + table, we are done. Otherwise, scan the table and remove any + entry that overlaps a call-clobbered register. */ + + if (in_table) + for (hash = 0; hash < NBUCKETS; hash++) + for (p = table[hash]; p; p = next) + { + next = p->next_same_hash; + + if (GET_CODE (p->exp) != REG + || REGNO (p->exp) >= FIRST_PSEUDO_REGISTER) + continue; + + regno = REGNO (p->exp); + endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (p->exp)); + + for (i = regno; i < endregno; i++) + if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) + { + remove_from_table (p, hash); + break; + } + } +} + +/* Given an expression X of type CONST, + and ELT which is its table entry (or 0 if it + is not in the hash table), + return an alternate expression for X as a register plus integer. + If none can be found, return 0. */ + +static rtx +use_related_value (x, elt) + rtx x; + struct table_elt *elt; +{ + register struct table_elt *relt = 0; + register struct table_elt *p, *q; + HOST_WIDE_INT offset; + + /* First, is there anything related known? + If we have a table element, we can tell from that. + Otherwise, must look it up. */ + + if (elt != 0 && elt->related_value != 0) + relt = elt; + else if (elt == 0 && GET_CODE (x) == CONST) + { + rtx subexp = get_related_value (x); + if (subexp != 0) + relt = lookup (subexp, + safe_hash (subexp, GET_MODE (subexp)) % NBUCKETS, + GET_MODE (subexp)); + } + + if (relt == 0) + return 0; + + /* Search all related table entries for one that has an + equivalent register. */ + + p = relt; + while (1) + { + /* This loop is strange in that it is executed in two different cases. + The first is when X is already in the table. Then it is searching + the RELATED_VALUE list of X's class (RELT). The second case is when + X is not in the table. Then RELT points to a class for the related + value. + + Ensure that, whatever case we are in, that we ignore classes that have + the same value as X. */ + + if (rtx_equal_p (x, p->exp)) + q = 0; + else + for (q = p->first_same_value; q; q = q->next_same_value) + if (GET_CODE (q->exp) == REG) + break; + + if (q) + break; + + p = p->related_value; + + /* We went all the way around, so there is nothing to be found. + Alternatively, perhaps RELT was in the table for some other reason + and it has no related values recorded. */ + if (p == relt || p == 0) + break; + } + + if (q == 0) + return 0; + + offset = (get_integer_term (x) - get_integer_term (p->exp)); + /* Note: OFFSET may be 0 if P->xexp and X are related by commutativity. */ + return plus_constant (q->exp, offset); +} + +/* Hash an rtx. We are careful to make sure the value is never negative. + Equivalent registers hash identically. + MODE is used in hashing for CONST_INTs only; + otherwise the mode of X is used. + + Store 1 in do_not_record if any subexpression is volatile. + + Store 1 in hash_arg_in_memory if X contains a MEM rtx + which does not have the RTX_UNCHANGING_P bit set. + In this case, also store 1 in hash_arg_in_struct + if there is a MEM rtx which has the MEM_IN_STRUCT_P bit set. + + Note that cse_insn knows that the hash code of a MEM expression + is just (int) MEM plus the hash code of the address. */ + +static int +canon_hash (x, mode) + rtx x; + enum machine_mode mode; +{ + register int i, j; + register int hash = 0; + register enum rtx_code code; + register char *fmt; + + /* repeat is used to turn tail-recursion into iteration. */ + repeat: + if (x == 0) + return hash; + + code = GET_CODE (x); + switch (code) + { + case REG: + { + register int regno = REGNO (x); + + /* On some machines, we can't record any non-fixed hard register, + because extending its life will cause reload problems. We + consider ap, fp, and sp to be fixed for this purpose. + On all machines, we can't record any global registers. */ + + if (regno < FIRST_PSEUDO_REGISTER + && (global_regs[regno] +#ifdef SMALL_REGISTER_CLASSES + || (! fixed_regs[regno] + && regno != FRAME_POINTER_REGNUM + && regno != ARG_POINTER_REGNUM + && regno != STACK_POINTER_REGNUM) +#endif + )) + { + do_not_record = 1; + return 0; + } + return hash + ((int) REG << 7) + reg_qty[regno]; + } + + case CONST_INT: + hash += ((int) mode + ((int) CONST_INT << 7) + + INTVAL (x) + (INTVAL (x) >> HASHBITS)); + return ((1 << HASHBITS) - 1) & hash; + + case CONST_DOUBLE: + /* This is like the general case, except that it only counts + the integers representing the constant. */ + hash += (int) code + (int) GET_MODE (x); + { + int i; + for (i = 2; i < GET_RTX_LENGTH (CONST_DOUBLE); i++) + { + int tem = XINT (x, i); + hash += ((1 << HASHBITS) - 1) & (tem + (tem >> HASHBITS)); + } + } + return hash; + + /* Assume there is only one rtx object for any given label. */ + case LABEL_REF: + /* Use `and' to ensure a positive number. */ + return (hash + ((HOST_WIDE_INT) LABEL_REF << 7) + + ((HOST_WIDE_INT) XEXP (x, 0) & ((1 << HASHBITS) - 1))); + + case SYMBOL_REF: + return (hash + ((HOST_WIDE_INT) SYMBOL_REF << 7) + + ((HOST_WIDE_INT) XEXP (x, 0) & ((1 << HASHBITS) - 1))); + + case MEM: + if (MEM_VOLATILE_P (x)) + { + do_not_record = 1; + return 0; + } + if (! RTX_UNCHANGING_P (x)) + { + hash_arg_in_memory = 1; + if (MEM_IN_STRUCT_P (x)) hash_arg_in_struct = 1; + } + /* Now that we have already found this special case, + might as well speed it up as much as possible. */ + hash += (int) MEM; + x = XEXP (x, 0); + goto repeat; + + case PRE_DEC: + case PRE_INC: + case POST_DEC: + case POST_INC: + case PC: + case CC0: + case CALL: + case UNSPEC_VOLATILE: + do_not_record = 1; + return 0; + + case ASM_OPERANDS: + if (MEM_VOLATILE_P (x)) + { + do_not_record = 1; + return 0; + } + } + + i = GET_RTX_LENGTH (code) - 1; + hash += (int) code + (int) GET_MODE (x); + fmt = GET_RTX_FORMAT (code); + for (; i >= 0; i--) + { + if (fmt[i] == 'e') + { + rtx tem = XEXP (x, i); + rtx tem1; + + /* If the operand is a REG that is equivalent to a constant, hash + as if we were hashing the constant, since we will be comparing + that way. */ + if (tem != 0 && GET_CODE (tem) == REG + && REGNO_QTY_VALID_P (REGNO (tem)) + && qty_mode[reg_qty[REGNO (tem)]] == GET_MODE (tem) + && (tem1 = qty_const[reg_qty[REGNO (tem)]]) != 0 + && CONSTANT_P (tem1)) + tem = tem1; + + /* If we are about to do the last recursive call + needed at this level, change it into iteration. + This function is called enough to be worth it. */ + if (i == 0) + { + x = tem; + goto repeat; + } + hash += canon_hash (tem, 0); + } + else if (fmt[i] == 'E') + for (j = 0; j < XVECLEN (x, i); j++) + hash += canon_hash (XVECEXP (x, i, j), 0); + else if (fmt[i] == 's') + { + register char *p = XSTR (x, i); + if (p) + while (*p) + { + register int tem = *p++; + hash += ((1 << HASHBITS) - 1) & (tem + (tem >> HASHBITS)); + } + } + else if (fmt[i] == 'i') + { + register int tem = XINT (x, i); + hash += ((1 << HASHBITS) - 1) & (tem + (tem >> HASHBITS)); + } + else + abort (); + } + return hash; +} + +/* Like canon_hash but with no side effects. */ + +static int +safe_hash (x, mode) + rtx x; + enum machine_mode mode; +{ + int save_do_not_record = do_not_record; + int save_hash_arg_in_memory = hash_arg_in_memory; + int save_hash_arg_in_struct = hash_arg_in_struct; + int hash = canon_hash (x, mode); + hash_arg_in_memory = save_hash_arg_in_memory; + hash_arg_in_struct = save_hash_arg_in_struct; + do_not_record = save_do_not_record; + return hash; +} + +/* Return 1 iff X and Y would canonicalize into the same thing, + without actually constructing the canonicalization of either one. + If VALIDATE is nonzero, + we assume X is an expression being processed from the rtl + and Y was found in the hash table. We check register refs + in Y for being marked as valid. + + If EQUAL_VALUES is nonzero, we allow a register to match a constant value + that is known to be in the register. Ordinarily, we don't allow them + to match, because letting them match would cause unpredictable results + in all the places that search a hash table chain for an equivalent + for a given value. A possible equivalent that has different structure + has its hash code computed from different data. Whether the hash code + is the same as that of the the given value is pure luck. */ + +static int +exp_equiv_p (x, y, validate, equal_values) + rtx x, y; + int validate; + int equal_values; +{ + register int i, j; + register enum rtx_code code; + register char *fmt; + + /* Note: it is incorrect to assume an expression is equivalent to itself + if VALIDATE is nonzero. */ + if (x == y && !validate) + return 1; + if (x == 0 || y == 0) + return x == y; + + code = GET_CODE (x); + if (code != GET_CODE (y)) + { + if (!equal_values) + return 0; + + /* If X is a constant and Y is a register or vice versa, they may be + equivalent. We only have to validate if Y is a register. */ + if (CONSTANT_P (x) && GET_CODE (y) == REG + && REGNO_QTY_VALID_P (REGNO (y)) + && GET_MODE (y) == qty_mode[reg_qty[REGNO (y)]] + && rtx_equal_p (x, qty_const[reg_qty[REGNO (y)]]) + && (! validate || reg_in_table[REGNO (y)] == reg_tick[REGNO (y)])) + return 1; + + if (CONSTANT_P (y) && code == REG + && REGNO_QTY_VALID_P (REGNO (x)) + && GET_MODE (x) == qty_mode[reg_qty[REGNO (x)]] + && rtx_equal_p (y, qty_const[reg_qty[REGNO (x)]])) + return 1; + + return 0; + } + + /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ + if (GET_MODE (x) != GET_MODE (y)) + return 0; + + switch (code) + { + case PC: + case CC0: + return x == y; + + case CONST_INT: + return INTVAL (x) == INTVAL (y); + + case LABEL_REF: + case SYMBOL_REF: + return XEXP (x, 0) == XEXP (y, 0); + + case REG: + { + int regno = REGNO (y); + int endregno + = regno + (regno >= FIRST_PSEUDO_REGISTER ? 1 + : HARD_REGNO_NREGS (regno, GET_MODE (y))); + int i; + + /* If the quantities are not the same, the expressions are not + equivalent. If there are and we are not to validate, they + are equivalent. Otherwise, ensure all regs are up-to-date. */ + + if (reg_qty[REGNO (x)] != reg_qty[regno]) + return 0; + + if (! validate) + return 1; + + for (i = regno; i < endregno; i++) + if (reg_in_table[i] != reg_tick[i]) + return 0; + + return 1; + } + + /* For commutative operations, check both orders. */ + case PLUS: + case MULT: + case AND: + case IOR: + case XOR: + case NE: + case EQ: + return ((exp_equiv_p (XEXP (x, 0), XEXP (y, 0), validate, equal_values) + && exp_equiv_p (XEXP (x, 1), XEXP (y, 1), + validate, equal_values)) + || (exp_equiv_p (XEXP (x, 0), XEXP (y, 1), + validate, equal_values) + && exp_equiv_p (XEXP (x, 1), XEXP (y, 0), + validate, equal_values))); + } + + /* Compare the elements. If any pair of corresponding elements + fail to match, return 0 for the whole things. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + switch (fmt[i]) + { + case 'e': + if (! exp_equiv_p (XEXP (x, i), XEXP (y, i), validate, equal_values)) + return 0; + break; + + case 'E': + if (XVECLEN (x, i) != XVECLEN (y, i)) + return 0; + for (j = 0; j < XVECLEN (x, i); j++) + if (! exp_equiv_p (XVECEXP (x, i, j), XVECEXP (y, i, j), + validate, equal_values)) + return 0; + break; + + case 's': + if (strcmp (XSTR (x, i), XSTR (y, i))) + return 0; + break; + + case 'i': + if (XINT (x, i) != XINT (y, i)) + return 0; + break; + + case 'w': + if (XWINT (x, i) != XWINT (y, i)) + return 0; + break; + + case '0': + break; + + default: + abort (); + } + } + + return 1; +} + +/* Return 1 iff any subexpression of X matches Y. + Here we do not require that X or Y be valid (for registers referred to) + for being in the hash table. */ + +static int +refers_to_p (x, y) + rtx x, y; +{ + register int i; + register enum rtx_code code; + register char *fmt; + + repeat: + if (x == y) + return 1; + if (x == 0 || y == 0) + return 0; + + code = GET_CODE (x); + /* If X as a whole has the same code as Y, they may match. + If so, return 1. */ + if (code == GET_CODE (y)) + { + if (exp_equiv_p (x, y, 0, 1)) + return 1; + } + + /* X does not match, so try its subexpressions. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + { + if (i == 0) + { + x = XEXP (x, 0); + goto repeat; + } + else + if (refers_to_p (XEXP (x, i), y)) + return 1; + } + else if (fmt[i] == 'E') + { + int j; + for (j = 0; j < XVECLEN (x, i); j++) + if (refers_to_p (XVECEXP (x, i, j), y)) + return 1; + } + + return 0; +} + +/* Given ADDR and SIZE (a memory address, and the size of the memory reference), + set PBASE, PSTART, and PEND which correspond to the base of the address, + the starting offset, and ending offset respectively. + + ADDR is known to be a nonvarying address. + + cse_address_varies_p returns zero for nonvarying addresses. */ + +static void +set_nonvarying_address_components (addr, size, pbase, pstart, pend) + rtx addr; + int size; + rtx *pbase; + HOST_WIDE_INT *pstart, *pend; +{ + rtx base; + int start, end; + + base = addr; + start = 0; + end = 0; + + /* Registers with nonvarying addresses usually have constant equivalents; + but the frame pointer register is also possible. */ + if (GET_CODE (base) == REG + && qty_const != 0 + && REGNO_QTY_VALID_P (REGNO (base)) + && qty_mode[reg_qty[REGNO (base)]] == GET_MODE (base) + && qty_const[reg_qty[REGNO (base)]] != 0) + base = qty_const[reg_qty[REGNO (base)]]; + else if (GET_CODE (base) == PLUS + && GET_CODE (XEXP (base, 1)) == CONST_INT + && GET_CODE (XEXP (base, 0)) == REG + && qty_const != 0 + && REGNO_QTY_VALID_P (REGNO (XEXP (base, 0))) + && (qty_mode[reg_qty[REGNO (XEXP (base, 0))]] + == GET_MODE (XEXP (base, 0))) + && qty_const[reg_qty[REGNO (XEXP (base, 0))]]) + { + start = INTVAL (XEXP (base, 1)); + base = qty_const[reg_qty[REGNO (XEXP (base, 0))]]; + } + + /* By definition, operand1 of a LO_SUM is the associated constant + address. Use the associated constant address as the base instead. */ + if (GET_CODE (base) == LO_SUM) + base = XEXP (base, 1); + + /* Strip off CONST. */ + if (GET_CODE (base) == CONST) + base = XEXP (base, 0); + + if (GET_CODE (base) == PLUS + && GET_CODE (XEXP (base, 1)) == CONST_INT) + { + start += INTVAL (XEXP (base, 1)); + base = XEXP (base, 0); + } + + end = start + size; + + /* Set the return values. */ + *pbase = base; + *pstart = start; + *pend = end; +} + +/* Return 1 iff any subexpression of X refers to memory + at an address of BASE plus some offset + such that any of the bytes' offsets fall between START (inclusive) + and END (exclusive). + + The value is undefined if X is a varying address (as determined by + cse_rtx_addr_varies_p). This function is not used in such cases. + + When used in the cse pass, `qty_const' is nonzero, and it is used + to treat an address that is a register with a known constant value + as if it were that constant value. + In the loop pass, `qty_const' is zero, so this is not done. */ + +static int +refers_to_mem_p (x, base, start, end) + rtx x, base; + HOST_WIDE_INT start, end; +{ + register HOST_WIDE_INT i; + register enum rtx_code code; + register char *fmt; + + if (GET_CODE (base) == CONST_INT) + { + start += INTVAL (base); + end += INTVAL (base); + base = const0_rtx; + } + + repeat: + if (x == 0) + return 0; + + code = GET_CODE (x); + if (code == MEM) + { + register rtx addr = XEXP (x, 0); /* Get the address. */ + rtx mybase; + HOST_WIDE_INT mystart, myend; + + set_nonvarying_address_components (addr, GET_MODE_SIZE (GET_MODE (x)), + &mybase, &mystart, &myend); + + + /* refers_to_mem_p is never called with varying addresses. + If the base addresses are not equal, there is no chance + of the memory addresses conflicting. */ + if (! rtx_equal_p (mybase, base)) + return 0; + + return myend > start && mystart < end; + } + + /* X does not match, so try its subexpressions. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + { + if (i == 0) + { + x = XEXP (x, 0); + goto repeat; + } + else + if (refers_to_mem_p (XEXP (x, i), base, start, end)) + return 1; + } + else if (fmt[i] == 'E') + { + int j; + for (j = 0; j < XVECLEN (x, i); j++) + if (refers_to_mem_p (XVECEXP (x, i, j), base, start, end)) + return 1; + } + + return 0; +} + +/* Nonzero if X refers to memory at a varying address; + except that a register which has at the moment a known constant value + isn't considered variable. */ + +static int +cse_rtx_addr_varies_p (x) + rtx x; +{ + /* We need not check for X and the equivalence class being of the same + mode because if X is equivalent to a constant in some mode, it + doesn't vary in any mode. */ + + if (GET_CODE (x) == MEM + && GET_CODE (XEXP (x, 0)) == REG + && REGNO_QTY_VALID_P (REGNO (XEXP (x, 0))) + && GET_MODE (XEXP (x, 0)) == qty_mode[reg_qty[REGNO (XEXP (x, 0))]] + && qty_const[reg_qty[REGNO (XEXP (x, 0))]] != 0) + return 0; + + if (GET_CODE (x) == MEM + && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG + && REGNO_QTY_VALID_P (REGNO (XEXP (XEXP (x, 0), 0))) + && (GET_MODE (XEXP (XEXP (x, 0), 0)) + == qty_mode[reg_qty[REGNO (XEXP (XEXP (x, 0), 0))]]) + && qty_const[reg_qty[REGNO (XEXP (XEXP (x, 0), 0))]]) + return 0; + + return rtx_addr_varies_p (x); +} + +/* Canonicalize an expression: + replace each register reference inside it + with the "oldest" equivalent register. + + If INSN is non-zero and we are replacing a pseudo with a hard register + or vice versa, validate_change is used to ensure that INSN remains valid + after we make our substitution. The calls are made with IN_GROUP non-zero + so apply_change_group must be called upon the outermost return from this + function (unless INSN is zero). The result of apply_change_group can + generally be discarded since the changes we are making are optional. */ + +static rtx +canon_reg (x, insn) + rtx x; + rtx insn; +{ + register int i; + register enum rtx_code code; + register char *fmt; + + if (x == 0) + return x; + + code = GET_CODE (x); + switch (code) + { + case PC: + case CC0: + case CONST: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case ADDR_VEC: + case ADDR_DIFF_VEC: + return x; + + case REG: + { + register int first; + + /* Never replace a hard reg, because hard regs can appear + in more than one machine mode, and we must preserve the mode + of each occurrence. Also, some hard regs appear in + MEMs that are shared and mustn't be altered. Don't try to + replace any reg that maps to a reg of class NO_REGS. */ + if (REGNO (x) < FIRST_PSEUDO_REGISTER + || ! REGNO_QTY_VALID_P (REGNO (x))) + return x; + + first = qty_first_reg[reg_qty[REGNO (x)]]; + return (first >= FIRST_PSEUDO_REGISTER ? regno_reg_rtx[first] + : REGNO_REG_CLASS (first) == NO_REGS ? x + : gen_rtx (REG, qty_mode[reg_qty[REGNO (x)]], first)); + } + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + register int j; + + if (fmt[i] == 'e') + { + rtx new = canon_reg (XEXP (x, i), insn); + + /* If replacing pseudo with hard reg or vice versa, ensure the + insn remains valid. Likewise if the insn has MATCH_DUPs. */ + if (insn != 0 && new != 0 + && GET_CODE (new) == REG && GET_CODE (XEXP (x, i)) == REG + && (((REGNO (new) < FIRST_PSEUDO_REGISTER) + != (REGNO (XEXP (x, i)) < FIRST_PSEUDO_REGISTER)) + || insn_n_dups[recog_memoized (insn)] > 0)) + validate_change (insn, &XEXP (x, i), new, 1); + else + XEXP (x, i) = new; + } + else if (fmt[i] == 'E') + for (j = 0; j < XVECLEN (x, i); j++) + XVECEXP (x, i, j) = canon_reg (XVECEXP (x, i, j), insn); + } + + return x; +} + +/* LOC is a location with INSN that is an operand address (the contents of + a MEM). Find the best equivalent address to use that is valid for this + insn. + + On most CISC machines, complicated address modes are costly, and rtx_cost + is a good approximation for that cost. However, most RISC machines have + only a few (usually only one) memory reference formats. If an address is + valid at all, it is often just as cheap as any other address. Hence, for + RISC machines, we use the configuration macro `ADDRESS_COST' to compare the + costs of various addresses. For two addresses of equal cost, choose the one + with the highest `rtx_cost' value as that has the potential of eliminating + the most insns. For equal costs, we choose the first in the equivalence + class. Note that we ignore the fact that pseudo registers are cheaper + than hard registers here because we would also prefer the pseudo registers. + */ + +static void +find_best_addr (insn, loc) + rtx insn; + rtx *loc; +{ + struct table_elt *elt, *p; + rtx addr = *loc; + int our_cost; + int found_better = 1; + int save_do_not_record = do_not_record; + int save_hash_arg_in_memory = hash_arg_in_memory; + int save_hash_arg_in_struct = hash_arg_in_struct; + int hash_code; + int addr_volatile; + int regno; + + /* Do not try to replace constant addresses or addresses of local and + argument slots. These MEM expressions are made only once and inserted + in many instructions, as well as being used to control symbol table + output. It is not safe to clobber them. + + There are some uncommon cases where the address is already in a register + for some reason, but we cannot take advantage of that because we have + no easy way to unshare the MEM. In addition, looking up all stack + addresses is costly. */ + if ((GET_CODE (addr) == PLUS + && GET_CODE (XEXP (addr, 0)) == REG + && GET_CODE (XEXP (addr, 1)) == CONST_INT + && (regno = REGNO (XEXP (addr, 0)), + regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)) + || (GET_CODE (addr) == REG + && (regno = REGNO (addr), + regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)) + || CONSTANT_ADDRESS_P (addr)) + return; + + /* If this address is not simply a register, try to fold it. This will + sometimes simplify the expression. Many simplifications + will not be valid, but some, usually applying the associative rule, will + be valid and produce better code. */ + if (GET_CODE (addr) != REG + && validate_change (insn, loc, fold_rtx (addr, insn), 0)) + addr = *loc; + + /* If this address is not in the hash table, we can't look for equivalences + of the whole address. Also, ignore if volatile. */ + + do_not_record = 0; + hash_code = HASH (addr, Pmode); + addr_volatile = do_not_record; + do_not_record = save_do_not_record; + hash_arg_in_memory = save_hash_arg_in_memory; + hash_arg_in_struct = save_hash_arg_in_struct; + + if (addr_volatile) + return; + + elt = lookup (addr, hash_code, Pmode); + +#ifndef ADDRESS_COST + if (elt) + { + our_cost = elt->cost; + + /* Find the lowest cost below ours that works. */ + for (elt = elt->first_same_value; elt; elt = elt->next_same_value) + if (elt->cost < our_cost + && (GET_CODE (elt->exp) == REG + || exp_equiv_p (elt->exp, elt->exp, 1, 0)) + && validate_change (insn, loc, + canon_reg (copy_rtx (elt->exp), NULL_RTX), 0)) + return; + } +#else + + if (elt) + { + /* We need to find the best (under the criteria documented above) entry + in the class that is valid. We use the `flag' field to indicate + choices that were invalid and iterate until we can't find a better + one that hasn't already been tried. */ + + for (p = elt->first_same_value; p; p = p->next_same_value) + p->flag = 0; + + while (found_better) + { + int best_addr_cost = ADDRESS_COST (*loc); + int best_rtx_cost = (elt->cost + 1) >> 1; + struct table_elt *best_elt = elt; + + found_better = 0; + for (p = elt->first_same_value; p; p = p->next_same_value) + if (! p->flag + && (GET_CODE (p->exp) == REG + || exp_equiv_p (p->exp, p->exp, 1, 0)) + && (ADDRESS_COST (p->exp) < best_addr_cost + || (ADDRESS_COST (p->exp) == best_addr_cost + && (p->cost + 1) >> 1 > best_rtx_cost))) + { + found_better = 1; + best_addr_cost = ADDRESS_COST (p->exp); + best_rtx_cost = (p->cost + 1) >> 1; + best_elt = p; + } + + if (found_better) + { + if (validate_change (insn, loc, + canon_reg (copy_rtx (best_elt->exp), + NULL_RTX), 0)) + return; + else + best_elt->flag = 1; + } + } + } + + /* If the address is a binary operation with the first operand a register + and the second a constant, do the same as above, but looking for + equivalences of the register. Then try to simplify before checking for + the best address to use. This catches a few cases: First is when we + have REG+const and the register is another REG+const. We can often merge + the constants and eliminate one insn and one register. It may also be + that a machine has a cheap REG+REG+const. Finally, this improves the + code on the Alpha for unaligned byte stores. */ + + if (flag_expensive_optimizations + && (GET_RTX_CLASS (GET_CODE (*loc)) == '2' + || GET_RTX_CLASS (GET_CODE (*loc)) == 'c') + && GET_CODE (XEXP (*loc, 0)) == REG + && GET_CODE (XEXP (*loc, 1)) == CONST_INT) + { + rtx c = XEXP (*loc, 1); + + do_not_record = 0; + hash_code = HASH (XEXP (*loc, 0), Pmode); + do_not_record = save_do_not_record; + hash_arg_in_memory = save_hash_arg_in_memory; + hash_arg_in_struct = save_hash_arg_in_struct; + + elt = lookup (XEXP (*loc, 0), hash_code, Pmode); + if (elt == 0) + return; + + /* We need to find the best (under the criteria documented above) entry + in the class that is valid. We use the `flag' field to indicate + choices that were invalid and iterate until we can't find a better + one that hasn't already been tried. */ + + for (p = elt->first_same_value; p; p = p->next_same_value) + p->flag = 0; + + while (found_better) + { + int best_addr_cost = ADDRESS_COST (*loc); + int best_rtx_cost = (COST (*loc) + 1) >> 1; + struct table_elt *best_elt = elt; + rtx best_rtx = *loc; + + found_better = 0; + for (p = elt->first_same_value; p; p = p->next_same_value) + if (! p->flag + && (GET_CODE (p->exp) == REG + || exp_equiv_p (p->exp, p->exp, 1, 0))) + { + rtx new = cse_gen_binary (GET_CODE (*loc), Pmode, p->exp, c); + + if ((ADDRESS_COST (new) < best_addr_cost + || (ADDRESS_COST (new) == best_addr_cost + && (COST (new) + 1) >> 1 > best_rtx_cost))) + { + found_better = 1; + best_addr_cost = ADDRESS_COST (new); + best_rtx_cost = (COST (new) + 1) >> 1; + best_elt = p; + best_rtx = new; + } + } + + if (found_better) + { + if (validate_change (insn, loc, + canon_reg (copy_rtx (best_rtx), + NULL_RTX), 0)) + return; + else + best_elt->flag = 1; + } + } + } +#endif +} + +/* Given an operation (CODE, *PARG1, *PARG2), where code is a comparison + operation (EQ, NE, GT, etc.), follow it back through the hash table and + what values are being compared. + + *PARG1 and *PARG2 are updated to contain the rtx representing the values + actually being compared. For example, if *PARG1 was (cc0) and *PARG2 + was (const_int 0), *PARG1 and *PARG2 will be set to the objects that were + compared to produce cc0. + + The return value is the comparison operator and is either the code of + A or the code corresponding to the inverse of the comparison. */ + +static enum rtx_code +find_comparison_args (code, parg1, parg2, pmode1, pmode2) + enum rtx_code code; + rtx *parg1, *parg2; + enum machine_mode *pmode1, *pmode2; +{ + rtx arg1, arg2; + + arg1 = *parg1, arg2 = *parg2; + + /* If ARG2 is const0_rtx, see what ARG1 is equivalent to. */ + + while (arg2 == CONST0_RTX (GET_MODE (arg1))) + { + /* Set non-zero when we find something of interest. */ + rtx x = 0; + int reverse_code = 0; + struct table_elt *p = 0; + + /* If arg1 is a COMPARE, extract the comparison arguments from it. + On machines with CC0, this is the only case that can occur, since + fold_rtx will return the COMPARE or item being compared with zero + when given CC0. */ + + if (GET_CODE (arg1) == COMPARE && arg2 == const0_rtx) + x = arg1; + + /* If ARG1 is a comparison operator and CODE is testing for + STORE_FLAG_VALUE, get the inner arguments. */ + + else if (GET_RTX_CLASS (GET_CODE (arg1)) == '<') + { + if (code == NE + || (GET_MODE_CLASS (GET_MODE (arg1)) == MODE_INT + && code == LT && STORE_FLAG_VALUE == -1) +#ifdef FLOAT_STORE_FLAG_VALUE + || (GET_MODE_CLASS (GET_MODE (arg1)) == MODE_FLOAT + && FLOAT_STORE_FLAG_VALUE < 0) +#endif + ) + x = arg1; + else if (code == EQ + || (GET_MODE_CLASS (GET_MODE (arg1)) == MODE_INT + && code == GE && STORE_FLAG_VALUE == -1) +#ifdef FLOAT_STORE_FLAG_VALUE + || (GET_MODE_CLASS (GET_MODE (arg1)) == MODE_FLOAT + && FLOAT_STORE_FLAG_VALUE < 0) +#endif + ) + x = arg1, reverse_code = 1; + } + + /* ??? We could also check for + + (ne (and (eq (...) (const_int 1))) (const_int 0)) + + and related forms, but let's wait until we see them occurring. */ + + if (x == 0) + /* Look up ARG1 in the hash table and see if it has an equivalence + that lets us see what is being compared. */ + p = lookup (arg1, safe_hash (arg1, GET_MODE (arg1)) % NBUCKETS, + GET_MODE (arg1)); + if (p) p = p->first_same_value; + + for (; p; p = p->next_same_value) + { + enum machine_mode inner_mode = GET_MODE (p->exp); + + /* If the entry isn't valid, skip it. */ + if (! exp_equiv_p (p->exp, p->exp, 1, 0)) + continue; + + if (GET_CODE (p->exp) == COMPARE + /* Another possibility is that this machine has a compare insn + that includes the comparison code. In that case, ARG1 would + be equivalent to a comparison operation that would set ARG1 to + either STORE_FLAG_VALUE or zero. If this is an NE operation, + ORIG_CODE is the actual comparison being done; if it is an EQ, + we must reverse ORIG_CODE. On machine with a negative value + for STORE_FLAG_VALUE, also look at LT and GE operations. */ + || ((code == NE + || (code == LT + && GET_MODE_CLASS (inner_mode) == MODE_INT + && (GET_MODE_BITSIZE (inner_mode) + <= HOST_BITS_PER_WIDE_INT) + && (STORE_FLAG_VALUE + & ((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (inner_mode) - 1)))) +#ifdef FLOAT_STORE_FLAG_VALUE + || (code == LT + && GET_MODE_CLASS (inner_mode) == MODE_FLOAT + && FLOAT_STORE_FLAG_VALUE < 0) +#endif + ) + && GET_RTX_CLASS (GET_CODE (p->exp)) == '<')) + { + x = p->exp; + break; + } + else if ((code == EQ + || (code == GE + && GET_MODE_CLASS (inner_mode) == MODE_INT + && (GET_MODE_BITSIZE (inner_mode) + <= HOST_BITS_PER_WIDE_INT) + && (STORE_FLAG_VALUE + & ((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (inner_mode) - 1)))) +#ifdef FLOAT_STORE_FLAG_VALUE + || (code == GE + && GET_MODE_CLASS (inner_mode) == MODE_FLOAT + && FLOAT_STORE_FLAG_VALUE < 0) +#endif + ) + && GET_RTX_CLASS (GET_CODE (p->exp)) == '<') + { + reverse_code = 1; + x = p->exp; + break; + } + + /* If this is fp + constant, the equivalent is a better operand since + it may let us predict the value of the comparison. */ + else if (NONZERO_BASE_PLUS_P (p->exp)) + { + arg1 = p->exp; + continue; + } + } + + /* If we didn't find a useful equivalence for ARG1, we are done. + Otherwise, set up for the next iteration. */ + if (x == 0) + break; + + arg1 = XEXP (x, 0), arg2 = XEXP (x, 1); + if (GET_RTX_CLASS (GET_CODE (x)) == '<') + code = GET_CODE (x); + + if (reverse_code) + code = reverse_condition (code); + } + + /* Return our results. Return the modes from before fold_rtx + because fold_rtx might produce const_int, and then it's too late. */ + *pmode1 = GET_MODE (arg1), *pmode2 = GET_MODE (arg2); + *parg1 = fold_rtx (arg1, 0), *parg2 = fold_rtx (arg2, 0); + + return code; +} + +/* Try to simplify a unary operation CODE whose output mode is to be + MODE with input operand OP whose mode was originally OP_MODE. + Return zero if no simplification can be made. */ + +rtx +simplify_unary_operation (code, mode, op, op_mode) + enum rtx_code code; + enum machine_mode mode; + rtx op; + enum machine_mode op_mode; +{ + register int width = GET_MODE_BITSIZE (mode); + + /* The order of these tests is critical so that, for example, we don't + check the wrong mode (input vs. output) for a conversion operation, + such as FIX. At some point, this should be simplified. */ + +#if !defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + if (code == FLOAT && GET_CODE (op) == CONST_INT) + { + REAL_VALUE_TYPE d; + +#ifdef REAL_ARITHMETIC + REAL_VALUE_FROM_INT (d, INTVAL (op), INTVAL (op) < 0 ? ~0 : 0); +#else + d = (double) INTVAL (op); +#endif + return CONST_DOUBLE_FROM_REAL_VALUE (d, mode); + } + else if (code == UNSIGNED_FLOAT && GET_CODE (op) == CONST_INT) + { + REAL_VALUE_TYPE d; + +#ifdef REAL_ARITHMETIC + REAL_VALUE_FROM_INT (d, INTVAL (op), 0); +#else + d = (double) (unsigned int) INTVAL (op); +#endif + return CONST_DOUBLE_FROM_REAL_VALUE (d, mode); + } + + else if (code == FLOAT && GET_CODE (op) == CONST_DOUBLE + && GET_MODE (op) == VOIDmode) + { + REAL_VALUE_TYPE d; + +#ifdef REAL_ARITHMETIC + REAL_VALUE_FROM_INT (d, CONST_DOUBLE_LOW (op), CONST_DOUBLE_HIGH (op)); +#else + if (CONST_DOUBLE_HIGH (op) < 0) + { + d = (double) (~ CONST_DOUBLE_HIGH (op)); + d *= ((double) ((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2)) + * (double) ((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2))); + d += (double) (unsigned HOST_WIDE_INT) (~ CONST_DOUBLE_LOW (op)); + d = (- d - 1.0); + } + else + { + d = (double) CONST_DOUBLE_HIGH (op); + d *= ((double) ((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2)) + * (double) ((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2))); + d += (double) (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (op); + } +#endif /* REAL_ARITHMETIC */ + return CONST_DOUBLE_FROM_REAL_VALUE (d, mode); + } + else if (code == UNSIGNED_FLOAT && GET_CODE (op) == CONST_DOUBLE + && GET_MODE (op) == VOIDmode) + { + REAL_VALUE_TYPE d; + +#ifdef REAL_ARITHMETIC + REAL_VALUE_FROM_UNSIGNED_INT (d, CONST_DOUBLE_LOW (op), + CONST_DOUBLE_HIGH (op)); +#else + d = (double) CONST_DOUBLE_HIGH (op); + d *= ((double) ((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2)) + * (double) ((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2))); + d += (double) (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (op); +#endif /* REAL_ARITHMETIC */ + return CONST_DOUBLE_FROM_REAL_VALUE (d, mode); + } +#endif + + if (GET_CODE (op) == CONST_INT + && width <= HOST_BITS_PER_WIDE_INT && width > 0) + { + register HOST_WIDE_INT arg0 = INTVAL (op); + register HOST_WIDE_INT val; + + switch (code) + { + case NOT: + val = ~ arg0; + break; + + case NEG: + val = - arg0; + break; + + case ABS: + val = (arg0 >= 0 ? arg0 : - arg0); + break; + + case FFS: + /* Don't use ffs here. Instead, get low order bit and then its + number. If arg0 is zero, this will return 0, as desired. */ + arg0 &= GET_MODE_MASK (mode); + val = exact_log2 (arg0 & (- arg0)) + 1; + break; + + case TRUNCATE: + val = arg0; + break; + + case ZERO_EXTEND: + if (op_mode == VOIDmode) + op_mode = mode; + if (GET_MODE_BITSIZE (op_mode) == HOST_BITS_PER_WIDE_INT) + { + /* If we were really extending the mode, + we would have to distinguish between zero-extension + and sign-extension. */ + if (width != GET_MODE_BITSIZE (op_mode)) + abort (); + val = arg0; + } + else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT) + val = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode)); + else + return 0; + break; + + case SIGN_EXTEND: + if (op_mode == VOIDmode) + op_mode = mode; + if (GET_MODE_BITSIZE (op_mode) == HOST_BITS_PER_WIDE_INT) + { + /* If we were really extending the mode, + we would have to distinguish between zero-extension + and sign-extension. */ + if (width != GET_MODE_BITSIZE (op_mode)) + abort (); + val = arg0; + } + else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT) + { + val + = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode)); + if (val + & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (op_mode) - 1))) + val -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode); + } + else + return 0; + break; + + case SQRT: + return 0; + + default: + abort (); + } + + /* Clear the bits that don't belong in our mode, + unless they and our sign bit are all one. + So we get either a reasonable negative value or a reasonable + unsigned value for this mode. */ + if (width < HOST_BITS_PER_WIDE_INT + && ((val & ((HOST_WIDE_INT) (-1) << (width - 1))) + != ((HOST_WIDE_INT) (-1) << (width - 1)))) + val &= (1 << width) - 1; + + return GEN_INT (val); + } + + /* We can do some operations on integer CONST_DOUBLEs. Also allow + for a DImode operation on a CONST_INT. */ + else if (GET_MODE (op) == VOIDmode + && (GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT)) + { + HOST_WIDE_INT l1, h1, lv, hv; + + if (GET_CODE (op) == CONST_DOUBLE) + l1 = CONST_DOUBLE_LOW (op), h1 = CONST_DOUBLE_HIGH (op); + else + l1 = INTVAL (op), h1 = l1 < 0 ? -1 : 0; + + switch (code) + { + case NOT: + lv = ~ l1; + hv = ~ h1; + break; + + case NEG: + neg_double (l1, h1, &lv, &hv); + break; + + case ABS: + if (h1 < 0) + neg_double (l1, h1, &lv, &hv); + else + lv = l1, hv = h1; + break; + + case FFS: + hv = 0; + if (l1 == 0) + lv = HOST_BITS_PER_WIDE_INT + exact_log2 (h1 & (-h1)) + 1; + else + lv = exact_log2 (l1 & (-l1)) + 1; + break; + + case TRUNCATE: + if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) + return GEN_INT (l1 & GET_MODE_MASK (mode)); + else + return 0; + break; + + case ZERO_EXTEND: + if (op_mode == VOIDmode + || GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT) + return 0; + + hv = 0; + lv = l1 & GET_MODE_MASK (op_mode); + break; + + case SIGN_EXTEND: + if (op_mode == VOIDmode + || GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT) + return 0; + else + { + lv = l1 & GET_MODE_MASK (op_mode); + if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT + && (lv & ((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (op_mode) - 1))) != 0) + lv -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode); + + hv = (lv < 0) ? ~ (HOST_WIDE_INT) 0 : 0; + } + break; + + case SQRT: + return 0; + + default: + return 0; + } + + return immed_double_const (lv, hv, mode); + } + +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + else if (GET_CODE (op) == CONST_DOUBLE + && GET_MODE_CLASS (mode) == MODE_FLOAT) + { + REAL_VALUE_TYPE d; + jmp_buf handler; + rtx x; + + if (setjmp (handler)) + /* There used to be a warning here, but that is inadvisable. + People may want to cause traps, and the natural way + to do it should not get a warning. */ + return 0; + + set_float_handler (handler); + + REAL_VALUE_FROM_CONST_DOUBLE (d, op); + + switch (code) + { + case NEG: + d = REAL_VALUE_NEGATE (d); + break; + + case ABS: + if (REAL_VALUE_NEGATIVE (d)) + d = REAL_VALUE_NEGATE (d); + break; + + case FLOAT_TRUNCATE: + d = real_value_truncate (mode, d); + break; + + case FLOAT_EXTEND: + /* All this does is change the mode. */ + break; + + case FIX: + d = REAL_VALUE_RNDZINT (d); + break; + + case UNSIGNED_FIX: + d = REAL_VALUE_UNSIGNED_RNDZINT (d); + break; + + case SQRT: + return 0; + + default: + abort (); + } + + x = immed_real_const_1 (d, mode); + set_float_handler (NULL_PTR); + return x; + } + else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE_CLASS (mode) == MODE_INT + && width <= HOST_BITS_PER_WIDE_INT && width > 0) + { + REAL_VALUE_TYPE d; + jmp_buf handler; + rtx x; + HOST_WIDE_INT val; + + if (setjmp (handler)) + return 0; + + set_float_handler (handler); + + REAL_VALUE_FROM_CONST_DOUBLE (d, op); + + switch (code) + { + case FIX: + val = REAL_VALUE_FIX (d); + break; + + case UNSIGNED_FIX: + val = REAL_VALUE_UNSIGNED_FIX (d); + break; + + default: + abort (); + } + + set_float_handler (NULL_PTR); + + /* Clear the bits that don't belong in our mode, + unless they and our sign bit are all one. + So we get either a reasonable negative value or a reasonable + unsigned value for this mode. */ + if (width < HOST_BITS_PER_WIDE_INT + && ((val & ((HOST_WIDE_INT) (-1) << (width - 1))) + != ((HOST_WIDE_INT) (-1) << (width - 1)))) + val &= ((HOST_WIDE_INT) 1 << width) - 1; + + return GEN_INT (val); + } +#endif + /* This was formerly used only for non-IEEE float. + eggert@twinsun.com says it is safe for IEEE also. */ + else + { + /* There are some simplifications we can do even if the operands + aren't constant. */ + switch (code) + { + case NEG: + case NOT: + /* (not (not X)) == X, similarly for NEG. */ + if (GET_CODE (op) == code) + return XEXP (op, 0); + break; + + case SIGN_EXTEND: + /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2)))) + becomes just the MINUS if its mode is MODE. This allows + folding switch statements on machines using casesi (such as + the Vax). */ + if (GET_CODE (op) == TRUNCATE + && GET_MODE (XEXP (op, 0)) == mode + && GET_CODE (XEXP (op, 0)) == MINUS + && GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF + && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF) + return XEXP (op, 0); + break; + } + + return 0; + } +} + +/* Simplify a binary operation CODE with result mode MODE, operating on OP0 + and OP1. Return 0 if no simplification is possible. + + Don't use this for relational operations such as EQ or LT. + Use simplify_relational_operation instead. */ + +rtx +simplify_binary_operation (code, mode, op0, op1) + enum rtx_code code; + enum machine_mode mode; + rtx op0, op1; +{ + register HOST_WIDE_INT arg0, arg1, arg0s, arg1s; + HOST_WIDE_INT val; + int width = GET_MODE_BITSIZE (mode); + rtx tem; + + /* Relational operations don't work here. We must know the mode + of the operands in order to do the comparison correctly. + Assuming a full word can give incorrect results. + Consider comparing 128 with -128 in QImode. */ + + if (GET_RTX_CLASS (code) == '<') + abort (); + +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + if (GET_MODE_CLASS (mode) == MODE_FLOAT + && GET_CODE (op0) == CONST_DOUBLE && GET_CODE (op1) == CONST_DOUBLE + && mode == GET_MODE (op0) && mode == GET_MODE (op1)) + { + REAL_VALUE_TYPE f0, f1, value; + jmp_buf handler; + + if (setjmp (handler)) + return 0; + + set_float_handler (handler); + + REAL_VALUE_FROM_CONST_DOUBLE (f0, op0); + REAL_VALUE_FROM_CONST_DOUBLE (f1, op1); + f0 = real_value_truncate (mode, f0); + f1 = real_value_truncate (mode, f1); + +#ifdef REAL_ARITHMETIC + REAL_ARITHMETIC (value, rtx_to_tree_code (code), f0, f1); +#else + switch (code) + { + case PLUS: + value = f0 + f1; + break; + case MINUS: + value = f0 - f1; + break; + case MULT: + value = f0 * f1; + break; + case DIV: +#ifndef REAL_INFINITY + if (f1 == 0) + return 0; +#endif + value = f0 / f1; + break; + case SMIN: + value = MIN (f0, f1); + break; + case SMAX: + value = MAX (f0, f1); + break; + default: + abort (); + } +#endif + + set_float_handler (NULL_PTR); + value = real_value_truncate (mode, value); + return immed_real_const_1 (value, mode); + } +#endif /* not REAL_IS_NOT_DOUBLE, or REAL_ARITHMETIC */ + + /* We can fold some multi-word operations. */ + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_CODE (op0) == CONST_DOUBLE + && (GET_CODE (op1) == CONST_DOUBLE || GET_CODE (op1) == CONST_INT)) + { + HOST_WIDE_INT l1, l2, h1, h2, lv, hv; + + l1 = CONST_DOUBLE_LOW (op0), h1 = CONST_DOUBLE_HIGH (op0); + + if (GET_CODE (op1) == CONST_DOUBLE) + l2 = CONST_DOUBLE_LOW (op1), h2 = CONST_DOUBLE_HIGH (op1); + else + l2 = INTVAL (op1), h2 = l2 < 0 ? -1 : 0; + + switch (code) + { + case MINUS: + /* A - B == A + (-B). */ + neg_double (l2, h2, &lv, &hv); + l2 = lv, h2 = hv; + + /* .. fall through ... */ + + case PLUS: + add_double (l1, h1, l2, h2, &lv, &hv); + break; + + case MULT: + mul_double (l1, h1, l2, h2, &lv, &hv); + break; + + case DIV: case MOD: case UDIV: case UMOD: + /* We'd need to include tree.h to do this and it doesn't seem worth + it. */ + return 0; + + case AND: + lv = l1 & l2, hv = h1 & h2; + break; + + case IOR: + lv = l1 | l2, hv = h1 | h2; + break; + + case XOR: + lv = l1 ^ l2, hv = h1 ^ h2; + break; + + case SMIN: + if (h1 < h2 + || (h1 == h2 + && ((unsigned HOST_WIDE_INT) l1 + < (unsigned HOST_WIDE_INT) l2))) + lv = l1, hv = h1; + else + lv = l2, hv = h2; + break; + + case SMAX: + if (h1 > h2 + || (h1 == h2 + && ((unsigned HOST_WIDE_INT) l1 + > (unsigned HOST_WIDE_INT) l2))) + lv = l1, hv = h1; + else + lv = l2, hv = h2; + break; + + case UMIN: + if ((unsigned HOST_WIDE_INT) h1 < (unsigned HOST_WIDE_INT) h2 + || (h1 == h2 + && ((unsigned HOST_WIDE_INT) l1 + < (unsigned HOST_WIDE_INT) l2))) + lv = l1, hv = h1; + else + lv = l2, hv = h2; + break; + + case UMAX: + if ((unsigned HOST_WIDE_INT) h1 > (unsigned HOST_WIDE_INT) h2 + || (h1 == h2 + && ((unsigned HOST_WIDE_INT) l1 + > (unsigned HOST_WIDE_INT) l2))) + lv = l1, hv = h1; + else + lv = l2, hv = h2; + break; + + case LSHIFTRT: case ASHIFTRT: + case ASHIFT: case LSHIFT: + case ROTATE: case ROTATERT: +#ifdef SHIFT_COUNT_TRUNCATED + l2 &= (GET_MODE_BITSIZE (mode) - 1), h2 = 0; +#endif + + if (h2 != 0 || l2 < 0 || l2 >= GET_MODE_BITSIZE (mode)) + return 0; + + if (code == LSHIFTRT || code == ASHIFTRT) + rshift_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv, + code == ASHIFTRT); + else if (code == ASHIFT || code == LSHIFT) + lshift_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv, + code == ASHIFT); + else if (code == ROTATE) + lrotate_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv); + else /* code == ROTATERT */ + rrotate_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv); + break; + + default: + return 0; + } + + return immed_double_const (lv, hv, mode); + } + + if (GET_CODE (op0) != CONST_INT || GET_CODE (op1) != CONST_INT + || width > HOST_BITS_PER_WIDE_INT || width == 0) + { + /* Even if we can't compute a constant result, + there are some cases worth simplifying. */ + + switch (code) + { + case PLUS: + /* In IEEE floating point, x+0 is not the same as x. Similarly + for the other optimizations below. */ + if (TARGET_FLOAT_FORMAT == IEEE_FLOAT_FORMAT + && GET_MODE_CLASS (mode) != MODE_INT) + break; + + if (op1 == CONST0_RTX (mode)) + return op0; + + /* ((-a) + b) -> (b - a) and similarly for (a + (-b)) */ + if (GET_CODE (op0) == NEG) + return cse_gen_binary (MINUS, mode, op1, XEXP (op0, 0)); + else if (GET_CODE (op1) == NEG) + return cse_gen_binary (MINUS, mode, op0, XEXP (op1, 0)); + + /* Handle both-operands-constant cases. We can only add + CONST_INTs to constants since the sum of relocatable symbols + can't be handled by most assemblers. */ + + if (CONSTANT_P (op0) && GET_CODE (op1) == CONST_INT) + return plus_constant (op0, INTVAL (op1)); + else if (CONSTANT_P (op1) && GET_CODE (op0) == CONST_INT) + return plus_constant (op1, INTVAL (op0)); + + /* If one of the operands is a PLUS or a MINUS, see if we can + simplify this by the associative law. + Don't use the associative law for floating point. + The inaccuracy makes it nonassociative, + and subtle programs can break if operations are associated. */ + + if ((GET_MODE_CLASS (mode) == MODE_INT + || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) + && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS + || GET_CODE (op1) == PLUS || GET_CODE (op1) == MINUS) + && (tem = simplify_plus_minus (code, mode, op0, op1)) != 0) + return tem; + break; + + case COMPARE: +#ifdef HAVE_cc0 + /* Convert (compare FOO (const_int 0)) to FOO unless we aren't + using cc0, in which case we want to leave it as a COMPARE + so we can distinguish it from a register-register-copy. + + In IEEE floating point, x-0 is not the same as x. */ + + if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + || GET_MODE_CLASS (mode) == MODE_INT) + && op1 == CONST0_RTX (mode)) + return op0; +#else + /* Do nothing here. */ +#endif + break; + + case MINUS: + /* None of these optimizations can be done for IEEE + floating point. */ + if (TARGET_FLOAT_FORMAT == IEEE_FLOAT_FORMAT + && GET_MODE_CLASS (mode) != MODE_INT + && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) + break; + + /* We can't assume x-x is 0 even with non-IEEE floating point. */ + if (rtx_equal_p (op0, op1) + && ! side_effects_p (op0) + && GET_MODE_CLASS (mode) != MODE_FLOAT + && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) + return const0_rtx; + + /* Change subtraction from zero into negation. */ + if (op0 == CONST0_RTX (mode)) + return gen_rtx (NEG, mode, op1); + + /* (-1 - a) is ~a. */ + if (op0 == constm1_rtx) + return gen_rtx (NOT, mode, op1); + + /* Subtracting 0 has no effect. */ + if (op1 == CONST0_RTX (mode)) + return op0; + + /* (a - (-b)) -> (a + b). */ + if (GET_CODE (op1) == NEG) + return cse_gen_binary (PLUS, mode, op0, XEXP (op1, 0)); + + /* If one of the operands is a PLUS or a MINUS, see if we can + simplify this by the associative law. + Don't use the associative law for floating point. + The inaccuracy makes it nonassociative, + and subtle programs can break if operations are associated. */ + + if ((GET_MODE_CLASS (mode) == MODE_INT + || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) + && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS + || GET_CODE (op1) == PLUS || GET_CODE (op1) == MINUS) + && (tem = simplify_plus_minus (code, mode, op0, op1)) != 0) + return tem; + + /* Don't let a relocatable value get a negative coeff. */ + if (GET_CODE (op1) == CONST_INT) + return plus_constant (op0, - INTVAL (op1)); + break; + + case MULT: + if (op1 == constm1_rtx) + { + tem = simplify_unary_operation (NEG, mode, op0, mode); + + return tem ? tem : gen_rtx (NEG, mode, op0); + } + + /* In IEEE floating point, x*0 is not always 0. */ + if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + || GET_MODE_CLASS (mode) == MODE_INT) + && op1 == CONST0_RTX (mode) + && ! side_effects_p (op0)) + return op1; + + /* In IEEE floating point, x*1 is not equivalent to x for nans. + However, ANSI says we can drop signals, + so we can do this anyway. */ + if (op1 == CONST1_RTX (mode)) + return op0; + + /* Convert multiply by constant power of two into shift. */ + if (GET_CODE (op1) == CONST_INT + && (val = exact_log2 (INTVAL (op1))) >= 0) + return gen_rtx (ASHIFT, mode, op0, GEN_INT (val)); + + if (GET_CODE (op1) == CONST_DOUBLE + && GET_MODE_CLASS (GET_MODE (op1)) == MODE_FLOAT) + { + REAL_VALUE_TYPE d; + jmp_buf handler; + int op1is2, op1ism1; + + if (setjmp (handler)) + return 0; + + set_float_handler (handler); + REAL_VALUE_FROM_CONST_DOUBLE (d, op1); + op1is2 = REAL_VALUES_EQUAL (d, dconst2); + op1ism1 = REAL_VALUES_EQUAL (d, dconstm1); + set_float_handler (NULL_PTR); + + /* x*2 is x+x and x*(-1) is -x */ + if (op1is2 && GET_MODE (op0) == mode) + return gen_rtx (PLUS, mode, op0, copy_rtx (op0)); + + else if (op1ism1 && GET_MODE (op0) == mode) + return gen_rtx (NEG, mode, op0); + } + break; + + case IOR: + if (op1 == const0_rtx) + return op0; + if (GET_CODE (op1) == CONST_INT + && (INTVAL (op1) & GET_MODE_MASK (mode)) == GET_MODE_MASK (mode)) + return op1; + if (rtx_equal_p (op0, op1) && ! side_effects_p (op0)) + return op0; + /* A | (~A) -> -1 */ + if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1)) + || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0))) + && ! side_effects_p (op0) + && GET_MODE_CLASS (mode) != MODE_CC) + return constm1_rtx; + break; + + case XOR: + if (op1 == const0_rtx) + return op0; + if (GET_CODE (op1) == CONST_INT + && (INTVAL (op1) & GET_MODE_MASK (mode)) == GET_MODE_MASK (mode)) + return gen_rtx (NOT, mode, op0); + if (op0 == op1 && ! side_effects_p (op0) + && GET_MODE_CLASS (mode) != MODE_CC) + return const0_rtx; + break; + + case AND: + if (op1 == const0_rtx && ! side_effects_p (op0)) + return const0_rtx; + if (GET_CODE (op1) == CONST_INT + && (INTVAL (op1) & GET_MODE_MASK (mode)) == GET_MODE_MASK (mode)) + return op0; + if (op0 == op1 && ! side_effects_p (op0) + && GET_MODE_CLASS (mode) != MODE_CC) + return op0; + /* A & (~A) -> 0 */ + if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1)) + || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0))) + && ! side_effects_p (op0) + && GET_MODE_CLASS (mode) != MODE_CC) + return const0_rtx; + break; + + case UDIV: + /* Convert divide by power of two into shift (divide by 1 handled + below). */ + if (GET_CODE (op1) == CONST_INT + && (arg1 = exact_log2 (INTVAL (op1))) > 0) + return gen_rtx (LSHIFTRT, mode, op0, GEN_INT (arg1)); + + /* ... fall through ... */ + + case DIV: + if (op1 == CONST1_RTX (mode)) + return op0; + + /* In IEEE floating point, 0/x is not always 0. */ + if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + || GET_MODE_CLASS (mode) == MODE_INT) + && op0 == CONST0_RTX (mode) + && ! side_effects_p (op1)) + return op0; + +#if 0 /* Turned off till an expert says this is a safe thing to do. */ +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + /* Change division by a constant into multiplication. */ + else if (GET_CODE (op1) == CONST_DOUBLE + && GET_MODE_CLASS (GET_MODE (op1)) == MODE_FLOAT + && op1 != CONST0_RTX (mode)) + { + REAL_VALUE_TYPE d; + REAL_VALUE_FROM_CONST_DOUBLE (d, op1); + if (REAL_VALUES_EQUAL (d, dconst0)) + abort(); +#if defined (REAL_ARITHMETIC) + REAL_ARITHMETIC (d, (int) RDIV_EXPR, dconst1, d); + return gen_rtx (MULT, mode, op0, + CONST_DOUBLE_FROM_REAL_VALUE (d, mode)); +#else + return gen_rtx (MULT, mode, op0, + CONST_DOUBLE_FROM_REAL_VALUE (1./d, mode)); + } +#endif +#endif +#endif + break; + + case UMOD: + /* Handle modulus by power of two (mod with 1 handled below). */ + if (GET_CODE (op1) == CONST_INT + && exact_log2 (INTVAL (op1)) > 0) + return gen_rtx (AND, mode, op0, GEN_INT (INTVAL (op1) - 1)); + + /* ... fall through ... */ + + case MOD: + if ((op0 == const0_rtx || op1 == const1_rtx) + && ! side_effects_p (op0) && ! side_effects_p (op1)) + return const0_rtx; + break; + + case ROTATERT: + case ROTATE: + /* Rotating ~0 always results in ~0. */ + if (GET_CODE (op0) == CONST_INT && width <= HOST_BITS_PER_WIDE_INT + && INTVAL (op0) == GET_MODE_MASK (mode) + && ! side_effects_p (op1)) + return op0; + + /* ... fall through ... */ + + case LSHIFT: + case ASHIFT: + case ASHIFTRT: + case LSHIFTRT: + if (op1 == const0_rtx) + return op0; + if (op0 == const0_rtx && ! side_effects_p (op1)) + return op0; + break; + + case SMIN: + if (width <= HOST_BITS_PER_WIDE_INT && GET_CODE (op1) == CONST_INT + && INTVAL (op1) == (HOST_WIDE_INT) 1 << (width -1) + && ! side_effects_p (op0)) + return op1; + else if (rtx_equal_p (op0, op1) && ! side_effects_p (op0)) + return op0; + break; + + case SMAX: + if (width <= HOST_BITS_PER_WIDE_INT && GET_CODE (op1) == CONST_INT + && (INTVAL (op1) + == (unsigned HOST_WIDE_INT) GET_MODE_MASK (mode) >> 1) + && ! side_effects_p (op0)) + return op1; + else if (rtx_equal_p (op0, op1) && ! side_effects_p (op0)) + return op0; + break; + + case UMIN: + if (op1 == const0_rtx && ! side_effects_p (op0)) + return op1; + else if (rtx_equal_p (op0, op1) && ! side_effects_p (op0)) + return op0; + break; + + case UMAX: + if (op1 == constm1_rtx && ! side_effects_p (op0)) + return op1; + else if (rtx_equal_p (op0, op1) && ! side_effects_p (op0)) + return op0; + break; + + default: + abort (); + } + + return 0; + } + + /* Get the integer argument values in two forms: + zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */ + + arg0 = INTVAL (op0); + arg1 = INTVAL (op1); + + if (width < HOST_BITS_PER_WIDE_INT) + { + arg0 &= ((HOST_WIDE_INT) 1 << width) - 1; + arg1 &= ((HOST_WIDE_INT) 1 << width) - 1; + + arg0s = arg0; + if (arg0s & ((HOST_WIDE_INT) 1 << (width - 1))) + arg0s |= ((HOST_WIDE_INT) (-1) << width); + + arg1s = arg1; + if (arg1s & ((HOST_WIDE_INT) 1 << (width - 1))) + arg1s |= ((HOST_WIDE_INT) (-1) << width); + } + else + { + arg0s = arg0; + arg1s = arg1; + } + + /* Compute the value of the arithmetic. */ + + switch (code) + { + case PLUS: + val = arg0s + arg1s; + break; + + case MINUS: + val = arg0s - arg1s; + break; + + case MULT: + val = arg0s * arg1s; + break; + + case DIV: + if (arg1s == 0) + return 0; + val = arg0s / arg1s; + break; + + case MOD: + if (arg1s == 0) + return 0; + val = arg0s % arg1s; + break; + + case UDIV: + if (arg1 == 0) + return 0; + val = (unsigned HOST_WIDE_INT) arg0 / arg1; + break; + + case UMOD: + if (arg1 == 0) + return 0; + val = (unsigned HOST_WIDE_INT) arg0 % arg1; + break; + + case AND: + val = arg0 & arg1; + break; + + case IOR: + val = arg0 | arg1; + break; + + case XOR: + val = arg0 ^ arg1; + break; + + case LSHIFTRT: + /* If shift count is undefined, don't fold it; let the machine do + what it wants. But truncate it if the machine will do that. */ + if (arg1 < 0) + return 0; + +#ifdef SHIFT_COUNT_TRUNCATED + arg1 &= (BITS_PER_WORD - 1); +#endif + + if (arg1 >= width) + return 0; + + val = ((unsigned HOST_WIDE_INT) arg0) >> arg1; + break; + + case ASHIFT: + case LSHIFT: + if (arg1 < 0) + return 0; + +#ifdef SHIFT_COUNT_TRUNCATED + arg1 &= (BITS_PER_WORD - 1); +#endif + + if (arg1 >= width) + return 0; + + val = ((unsigned HOST_WIDE_INT) arg0) << arg1; + break; + + case ASHIFTRT: + if (arg1 < 0) + return 0; + +#ifdef SHIFT_COUNT_TRUNCATED + arg1 &= (BITS_PER_WORD - 1); +#endif + + if (arg1 >= width) + return 0; + + val = arg0s >> arg1; + + /* Bootstrap compiler may not have sign extended the right shift. + Manually extend the sign to insure bootstrap cc matches gcc. */ + if (arg0s < 0 && arg1 > 0) + val |= ((HOST_WIDE_INT) -1) << (HOST_BITS_PER_WIDE_INT - arg1); + + break; + + case ROTATERT: + if (arg1 < 0) + return 0; + + arg1 %= width; + val = ((((unsigned HOST_WIDE_INT) arg0) << (width - arg1)) + | (((unsigned HOST_WIDE_INT) arg0) >> arg1)); + break; + + case ROTATE: + if (arg1 < 0) + return 0; + + arg1 %= width; + val = ((((unsigned HOST_WIDE_INT) arg0) << arg1) + | (((unsigned HOST_WIDE_INT) arg0) >> (width - arg1))); + break; + + case COMPARE: + /* Do nothing here. */ + return 0; + + case SMIN: + val = arg0s <= arg1s ? arg0s : arg1s; + break; + + case UMIN: + val = ((unsigned HOST_WIDE_INT) arg0 + <= (unsigned HOST_WIDE_INT) arg1 ? arg0 : arg1); + break; + + case SMAX: + val = arg0s > arg1s ? arg0s : arg1s; + break; + + case UMAX: + val = ((unsigned HOST_WIDE_INT) arg0 + > (unsigned HOST_WIDE_INT) arg1 ? arg0 : arg1); + break; + + default: + abort (); + } + + /* Clear the bits that don't belong in our mode, unless they and our sign + bit are all one. So we get either a reasonable negative value or a + reasonable unsigned value for this mode. */ + if (width < HOST_BITS_PER_WIDE_INT + && ((val & ((HOST_WIDE_INT) (-1) << (width - 1))) + != ((HOST_WIDE_INT) (-1) << (width - 1)))) + val &= ((HOST_WIDE_INT) 1 << width) - 1; + + return GEN_INT (val); +} + +/* Simplify a PLUS or MINUS, at least one of whose operands may be another + PLUS or MINUS. + + Rather than test for specific case, we do this by a brute-force method + and do all possible simplifications until no more changes occur. Then + we rebuild the operation. */ + +static rtx +simplify_plus_minus (code, mode, op0, op1) + enum rtx_code code; + enum machine_mode mode; + rtx op0, op1; +{ + rtx ops[8]; + int negs[8]; + rtx result, tem; + int n_ops = 2, input_ops = 2, input_consts = 0, n_consts = 0; + int first = 1, negate = 0, changed; + int i, j; + + bzero (ops, sizeof ops); + + /* Set up the two operands and then expand them until nothing has been + changed. If we run out of room in our array, give up; this should + almost never happen. */ + + ops[0] = op0, ops[1] = op1, negs[0] = 0, negs[1] = (code == MINUS); + + changed = 1; + while (changed) + { + changed = 0; + + for (i = 0; i < n_ops; i++) + switch (GET_CODE (ops[i])) + { + case PLUS: + case MINUS: + if (n_ops == 7) + return 0; + + ops[n_ops] = XEXP (ops[i], 1); + negs[n_ops++] = GET_CODE (ops[i]) == MINUS ? !negs[i] : negs[i]; + ops[i] = XEXP (ops[i], 0); + input_ops++; + changed = 1; + break; + + case NEG: + ops[i] = XEXP (ops[i], 0); + negs[i] = ! negs[i]; + changed = 1; + break; + + case CONST: + ops[i] = XEXP (ops[i], 0); + input_consts++; + changed = 1; + break; + + case NOT: + /* ~a -> (-a - 1) */ + if (n_ops != 7) + { + ops[n_ops] = constm1_rtx; + negs[n_ops++] = negs[i]; + ops[i] = XEXP (ops[i], 0); + negs[i] = ! negs[i]; + changed = 1; + } + break; + + case CONST_INT: + if (negs[i]) + ops[i] = GEN_INT (- INTVAL (ops[i])), negs[i] = 0, changed = 1; + break; + } + } + + /* If we only have two operands, we can't do anything. */ + if (n_ops <= 2) + return 0; + + /* Now simplify each pair of operands until nothing changes. The first + time through just simplify constants against each other. */ + + changed = 1; + while (changed) + { + changed = first; + + for (i = 0; i < n_ops - 1; i++) + for (j = i + 1; j < n_ops; j++) + if (ops[i] != 0 && ops[j] != 0 + && (! first || (CONSTANT_P (ops[i]) && CONSTANT_P (ops[j])))) + { + rtx lhs = ops[i], rhs = ops[j]; + enum rtx_code ncode = PLUS; + + if (negs[i] && ! negs[j]) + lhs = ops[j], rhs = ops[i], ncode = MINUS; + else if (! negs[i] && negs[j]) + ncode = MINUS; + + tem = simplify_binary_operation (ncode, mode, lhs, rhs); + if (tem) + { + ops[i] = tem, ops[j] = 0; + negs[i] = negs[i] && negs[j]; + if (GET_CODE (tem) == NEG) + ops[i] = XEXP (tem, 0), negs[i] = ! negs[i]; + + if (GET_CODE (ops[i]) == CONST_INT && negs[i]) + ops[i] = GEN_INT (- INTVAL (ops[i])), negs[i] = 0; + changed = 1; + } + } + + first = 0; + } + + /* Pack all the operands to the lower-numbered entries and give up if + we didn't reduce the number of operands we had. Make sure we + count a CONST as two operands. If we have the same number of + operands, but have made more CONSTs than we had, this is also + an improvement, so accept it. */ + + for (i = 0, j = 0; j < n_ops; j++) + if (ops[j] != 0) + { + ops[i] = ops[j], negs[i++] = negs[j]; + if (GET_CODE (ops[j]) == CONST) + n_consts++; + } + + if (i + n_consts > input_ops + || (i + n_consts == input_ops && n_consts <= input_consts)) + return 0; + + n_ops = i; + + /* If we have a CONST_INT, put it last. */ + for (i = 0; i < n_ops - 1; i++) + if (GET_CODE (ops[i]) == CONST_INT) + { + tem = ops[n_ops - 1], ops[n_ops - 1] = ops[i] , ops[i] = tem; + j = negs[n_ops - 1], negs[n_ops - 1] = negs[i], negs[i] = j; + } + + /* Put a non-negated operand first. If there aren't any, make all + operands positive and negate the whole thing later. */ + for (i = 0; i < n_ops && negs[i]; i++) + ; + + if (i == n_ops) + { + for (i = 0; i < n_ops; i++) + negs[i] = 0; + negate = 1; + } + else if (i != 0) + { + tem = ops[0], ops[0] = ops[i], ops[i] = tem; + j = negs[0], negs[0] = negs[i], negs[i] = j; + } + + /* Now make the result by performing the requested operations. */ + result = ops[0]; + for (i = 1; i < n_ops; i++) + result = cse_gen_binary (negs[i] ? MINUS : PLUS, mode, result, ops[i]); + + return negate ? gen_rtx (NEG, mode, result) : result; +} + +/* Make a binary operation by properly ordering the operands and + seeing if the expression folds. */ + +static rtx +cse_gen_binary (code, mode, op0, op1) + enum rtx_code code; + enum machine_mode mode; + rtx op0, op1; +{ + rtx tem; + + /* Put complex operands first and constants second if commutative. */ + if (GET_RTX_CLASS (code) == 'c' + && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT) + || (GET_RTX_CLASS (GET_CODE (op0)) == 'o' + && GET_RTX_CLASS (GET_CODE (op1)) != 'o') + || (GET_CODE (op0) == SUBREG + && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o' + && GET_RTX_CLASS (GET_CODE (op1)) != 'o'))) + tem = op0, op0 = op1, op1 = tem; + + /* If this simplifies, do it. */ + tem = simplify_binary_operation (code, mode, op0, op1); + + if (tem) + return tem; + + /* Handle addition and subtraction of CONST_INT specially. Otherwise, + just form the operation. */ + + if (code == PLUS && GET_CODE (op1) == CONST_INT + && GET_MODE (op0) != VOIDmode) + return plus_constant (op0, INTVAL (op1)); + else if (code == MINUS && GET_CODE (op1) == CONST_INT + && GET_MODE (op0) != VOIDmode) + return plus_constant (op0, - INTVAL (op1)); + else + return gen_rtx (code, mode, op0, op1); +} + +/* Like simplify_binary_operation except used for relational operators. + MODE is the mode of the operands, not that of the result. */ + +rtx +simplify_relational_operation (code, mode, op0, op1) + enum rtx_code code; + enum machine_mode mode; + rtx op0, op1; +{ + register HOST_WIDE_INT arg0, arg1, arg0s, arg1s; + HOST_WIDE_INT val; + int width = GET_MODE_BITSIZE (mode); + + /* If op0 is a compare, extract the comparison arguments from it. */ + if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) + op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); + + /* What to do with MODE_CC isn't clear yet. + Let's make sure nothing erroneous is done. */ + if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) + return 0; + + /* Unlike the arithmetic operations, we can do the comparison whether + or not WIDTH is larger than HOST_BITS_PER_WIDE_INT because the + CONST_INTs are to be understood as being infinite precision as + is the comparison. So there is no question of overflow. */ + + if (GET_CODE (op0) != CONST_INT || GET_CODE (op1) != CONST_INT || width == 0) + { + /* Even if we can't compute a constant result, + there are some cases worth simplifying. */ + + /* For non-IEEE floating-point, if the two operands are equal, we know + the result. */ + if (rtx_equal_p (op0, op1) + && (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + || GET_MODE_CLASS (GET_MODE (op0)) != MODE_FLOAT)) + return (code == EQ || code == GE || code == LE || code == LEU + || code == GEU) ? const_true_rtx : const0_rtx; + +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + else if (GET_CODE (op0) == CONST_DOUBLE + && GET_CODE (op1) == CONST_DOUBLE + && GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT) + { + REAL_VALUE_TYPE d0, d1; + jmp_buf handler; + int op0lt, op1lt, equal; + + if (setjmp (handler)) + return 0; + + set_float_handler (handler); + REAL_VALUE_FROM_CONST_DOUBLE (d0, op0); + REAL_VALUE_FROM_CONST_DOUBLE (d1, op1); + equal = REAL_VALUES_EQUAL (d0, d1); + op0lt = REAL_VALUES_LESS (d0, d1); + op1lt = REAL_VALUES_LESS (d1, d0); + set_float_handler (NULL_PTR); + + switch (code) + { + case EQ: + return equal ? const_true_rtx : const0_rtx; + case NE: + return !equal ? const_true_rtx : const0_rtx; + case LE: + return equal || op0lt ? const_true_rtx : const0_rtx; + case LT: + return op0lt ? const_true_rtx : const0_rtx; + case GE: + return equal || op1lt ? const_true_rtx : const0_rtx; + case GT: + return op1lt ? const_true_rtx : const0_rtx; + } + } +#endif /* not REAL_IS_NOT_DOUBLE, or REAL_ARITHMETIC */ + + else if (GET_MODE_CLASS (mode) == MODE_INT + && width > HOST_BITS_PER_WIDE_INT + && (GET_CODE (op0) == CONST_DOUBLE + || GET_CODE (op0) == CONST_INT) + && (GET_CODE (op1) == CONST_DOUBLE + || GET_CODE (op1) == CONST_INT)) + { + HOST_WIDE_INT h0, l0, h1, l1; + unsigned HOST_WIDE_INT uh0, ul0, uh1, ul1; + int op0lt, op0ltu, equal; + + if (GET_CODE (op0) == CONST_DOUBLE) + l0 = CONST_DOUBLE_LOW (op0), h0 = CONST_DOUBLE_HIGH (op0); + else + l0 = INTVAL (op0), h0 = l0 < 0 ? -1 : 0; + + if (GET_CODE (op1) == CONST_DOUBLE) + l1 = CONST_DOUBLE_LOW (op1), h1 = CONST_DOUBLE_HIGH (op1); + else + l1 = INTVAL (op1), h1 = l1 < 0 ? -1 : 0; + + uh0 = h0, ul0 = l0, uh1 = h1, ul1 = l1; + + equal = (h0 == h1 && l0 == l1); + op0lt = (h0 < h1 || (h0 == h1 && l0 < l1)); + op0ltu = (uh0 < uh1 || (uh0 == uh1 && ul0 < ul1)); + + switch (code) + { + case EQ: + return equal ? const_true_rtx : const0_rtx; + case NE: + return !equal ? const_true_rtx : const0_rtx; + case LE: + return equal || op0lt ? const_true_rtx : const0_rtx; + case LT: + return op0lt ? const_true_rtx : const0_rtx; + case GE: + return !op0lt ? const_true_rtx : const0_rtx; + case GT: + return !equal && !op0lt ? const_true_rtx : const0_rtx; + case LEU: + return equal || op0ltu ? const_true_rtx : const0_rtx; + case LTU: + return op0ltu ? const_true_rtx : const0_rtx; + case GEU: + return !op0ltu ? const_true_rtx : const0_rtx; + case GTU: + return !equal && !op0ltu ? const_true_rtx : const0_rtx; + } + } + + switch (code) + { + case EQ: + { +#if 0 + /* We can't make this assumption due to #pragma weak */ + if (CONSTANT_P (op0) && op1 == const0_rtx) + return const0_rtx; +#endif + if (NONZERO_BASE_PLUS_P (op0) && op1 == const0_rtx + /* On some machines, the ap reg can be 0 sometimes. */ + && op0 != arg_pointer_rtx) + return const0_rtx; + break; + } + + case NE: +#if 0 + /* We can't make this assumption due to #pragma weak */ + if (CONSTANT_P (op0) && op1 == const0_rtx) + return const_true_rtx; +#endif + if (NONZERO_BASE_PLUS_P (op0) && op1 == const0_rtx + /* On some machines, the ap reg can be 0 sometimes. */ + && op0 != arg_pointer_rtx) + return const_true_rtx; + break; + + case GEU: + /* Unsigned values are never negative, but we must be sure we are + actually comparing a value, not a CC operand. */ + if (op1 == const0_rtx + && GET_MODE_CLASS (mode) == MODE_INT) + return const_true_rtx; + break; + + case LTU: + if (op1 == const0_rtx + && GET_MODE_CLASS (mode) == MODE_INT) + return const0_rtx; + break; + + case LEU: + /* Unsigned values are never greater than the largest + unsigned value. */ + if (GET_CODE (op1) == CONST_INT + && INTVAL (op1) == GET_MODE_MASK (mode) + && GET_MODE_CLASS (mode) == MODE_INT) + return const_true_rtx; + break; + + case GTU: + if (GET_CODE (op1) == CONST_INT + && INTVAL (op1) == GET_MODE_MASK (mode) + && GET_MODE_CLASS (mode) == MODE_INT) + return const0_rtx; + break; + } + + return 0; + } + + /* Get the integer argument values in two forms: + zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */ + + arg0 = INTVAL (op0); + arg1 = INTVAL (op1); + + if (width < HOST_BITS_PER_WIDE_INT) + { + arg0 &= ((HOST_WIDE_INT) 1 << width) - 1; + arg1 &= ((HOST_WIDE_INT) 1 << width) - 1; + + arg0s = arg0; + if (arg0s & ((HOST_WIDE_INT) 1 << (width - 1))) + arg0s |= ((HOST_WIDE_INT) (-1) << width); + + arg1s = arg1; + if (arg1s & ((HOST_WIDE_INT) 1 << (width - 1))) + arg1s |= ((HOST_WIDE_INT) (-1) << width); + } + else + { + arg0s = arg0; + arg1s = arg1; + } + + /* Compute the value of the arithmetic. */ + + switch (code) + { + case NE: + val = arg0 != arg1 ? STORE_FLAG_VALUE : 0; + break; + + case EQ: + val = arg0 == arg1 ? STORE_FLAG_VALUE : 0; + break; + + case LE: + val = arg0s <= arg1s ? STORE_FLAG_VALUE : 0; + break; + + case LT: + val = arg0s < arg1s ? STORE_FLAG_VALUE : 0; + break; + + case GE: + val = arg0s >= arg1s ? STORE_FLAG_VALUE : 0; + break; + + case GT: + val = arg0s > arg1s ? STORE_FLAG_VALUE : 0; + break; + + case LEU: + val = (((unsigned HOST_WIDE_INT) arg0) + <= ((unsigned HOST_WIDE_INT) arg1) ? STORE_FLAG_VALUE : 0); + break; + + case LTU: + val = (((unsigned HOST_WIDE_INT) arg0) + < ((unsigned HOST_WIDE_INT) arg1) ? STORE_FLAG_VALUE : 0); + break; + + case GEU: + val = (((unsigned HOST_WIDE_INT) arg0) + >= ((unsigned HOST_WIDE_INT) arg1) ? STORE_FLAG_VALUE : 0); + break; + + case GTU: + val = (((unsigned HOST_WIDE_INT) arg0) + > ((unsigned HOST_WIDE_INT) arg1) ? STORE_FLAG_VALUE : 0); + break; + + default: + abort (); + } + + /* Clear the bits that don't belong in our mode, unless they and our sign + bit are all one. So we get either a reasonable negative value or a + reasonable unsigned value for this mode. */ + if (width < HOST_BITS_PER_WIDE_INT + && ((val & ((HOST_WIDE_INT) (-1) << (width - 1))) + != ((HOST_WIDE_INT) (-1) << (width - 1)))) + val &= ((HOST_WIDE_INT) 1 << width) - 1; + + return GEN_INT (val); +} + +/* Simplify CODE, an operation with result mode MODE and three operands, + OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became + a constant. Return 0 if no simplifications is possible. */ + +rtx +simplify_ternary_operation (code, mode, op0_mode, op0, op1, op2) + enum rtx_code code; + enum machine_mode mode, op0_mode; + rtx op0, op1, op2; +{ + int width = GET_MODE_BITSIZE (mode); + + /* VOIDmode means "infinite" precision. */ + if (width == 0) + width = HOST_BITS_PER_WIDE_INT; + + switch (code) + { + case SIGN_EXTRACT: + case ZERO_EXTRACT: + if (GET_CODE (op0) == CONST_INT + && GET_CODE (op1) == CONST_INT + && GET_CODE (op2) == CONST_INT + && INTVAL (op1) + INTVAL (op2) <= GET_MODE_BITSIZE (op0_mode) + && width <= HOST_BITS_PER_WIDE_INT) + { + /* Extracting a bit-field from a constant */ + HOST_WIDE_INT val = INTVAL (op0); + +#if BITS_BIG_ENDIAN + val >>= (GET_MODE_BITSIZE (op0_mode) - INTVAL (op2) - INTVAL (op1)); +#else + val >>= INTVAL (op2); +#endif + if (HOST_BITS_PER_WIDE_INT != INTVAL (op1)) + { + /* First zero-extend. */ + val &= ((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1; + /* If desired, propagate sign bit. */ + if (code == SIGN_EXTRACT + && (val & ((HOST_WIDE_INT) 1 << (INTVAL (op1) - 1)))) + val |= ~ (((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1); + } + + /* Clear the bits that don't belong in our mode, + unless they and our sign bit are all one. + So we get either a reasonable negative value or a reasonable + unsigned value for this mode. */ + if (width < HOST_BITS_PER_WIDE_INT + && ((val & ((HOST_WIDE_INT) (-1) << (width - 1))) + != ((HOST_WIDE_INT) (-1) << (width - 1)))) + val &= ((HOST_WIDE_INT) 1 << width) - 1; + + return GEN_INT (val); + } + break; + + case IF_THEN_ELSE: + if (GET_CODE (op0) == CONST_INT) + return op0 != const0_rtx ? op1 : op2; + break; + + default: + abort (); + } + + return 0; +} + +/* If X is a nontrivial arithmetic operation on an argument + for which a constant value can be determined, return + the result of operating on that value, as a constant. + Otherwise, return X, possibly with one or more operands + modified by recursive calls to this function. + + If X is a register whose contents are known, we do NOT + return those contents here. equiv_constant is called to + perform that task. + + INSN is the insn that we may be modifying. If it is 0, make a copy + of X before modifying it. */ + +static rtx +fold_rtx (x, insn) + rtx x; + rtx insn; +{ + register enum rtx_code code; + register enum machine_mode mode; + register char *fmt; + register int i; + rtx new = 0; + int copied = 0; + int must_swap = 0; + + /* Folded equivalents of first two operands of X. */ + rtx folded_arg0; + rtx folded_arg1; + + /* Constant equivalents of first three operands of X; + 0 when no such equivalent is known. */ + rtx const_arg0; + rtx const_arg1; + rtx const_arg2; + + /* The mode of the first operand of X. We need this for sign and zero + extends. */ + enum machine_mode mode_arg0; + + if (x == 0) + return x; + + mode = GET_MODE (x); + code = GET_CODE (x); + switch (code) + { + case CONST: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case REG: + /* No use simplifying an EXPR_LIST + since they are used only for lists of args + in a function call's REG_EQUAL note. */ + case EXPR_LIST: + return x; + +#ifdef HAVE_cc0 + case CC0: + return prev_insn_cc0; +#endif + + case PC: + /* If the next insn is a CODE_LABEL followed by a jump table, + PC's value is a LABEL_REF pointing to that label. That + lets us fold switch statements on the Vax. */ + if (insn && GET_CODE (insn) == JUMP_INSN) + { + rtx next = next_nonnote_insn (insn); + + if (next && GET_CODE (next) == CODE_LABEL + && NEXT_INSN (next) != 0 + && GET_CODE (NEXT_INSN (next)) == JUMP_INSN + && (GET_CODE (PATTERN (NEXT_INSN (next))) == ADDR_VEC + || GET_CODE (PATTERN (NEXT_INSN (next))) == ADDR_DIFF_VEC)) + return gen_rtx (LABEL_REF, Pmode, next); + } + break; + + case SUBREG: + /* See if we previously assigned a constant value to this SUBREG. */ + if ((new = lookup_as_function (x, CONST_INT)) != 0 + || (new = lookup_as_function (x, CONST_DOUBLE)) != 0) + return new; + + /* If this is a paradoxical SUBREG, we have no idea what value the + extra bits would have. However, if the operand is equivalent + to a SUBREG whose operand is the same as our mode, and all the + modes are within a word, we can just use the inner operand + because these SUBREGs just say how to treat the register. */ + + if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) + { + enum machine_mode imode = GET_MODE (SUBREG_REG (x)); + struct table_elt *elt; + + if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD + && GET_MODE_SIZE (imode) <= UNITS_PER_WORD + && (elt = lookup (SUBREG_REG (x), HASH (SUBREG_REG (x), imode), + imode)) != 0) + { + for (elt = elt->first_same_value; + elt; elt = elt->next_same_value) + if (GET_CODE (elt->exp) == SUBREG + && GET_MODE (SUBREG_REG (elt->exp)) == mode + && exp_equiv_p (elt->exp, elt->exp, 1, 0)) + return copy_rtx (SUBREG_REG (elt->exp)); + } + + return x; + } + + /* Fold SUBREG_REG. If it changed, see if we can simplify the SUBREG. + We might be able to if the SUBREG is extracting a single word in an + integral mode or extracting the low part. */ + + folded_arg0 = fold_rtx (SUBREG_REG (x), insn); + const_arg0 = equiv_constant (folded_arg0); + if (const_arg0) + folded_arg0 = const_arg0; + + if (folded_arg0 != SUBREG_REG (x)) + { + new = 0; + + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_SIZE (mode) == UNITS_PER_WORD + && GET_MODE (SUBREG_REG (x)) != VOIDmode) + new = operand_subword (folded_arg0, SUBREG_WORD (x), 0, + GET_MODE (SUBREG_REG (x))); + if (new == 0 && subreg_lowpart_p (x)) + new = gen_lowpart_if_possible (mode, folded_arg0); + if (new) + return new; + } + + /* If this is a narrowing SUBREG and our operand is a REG, see if + we can find an equivalence for REG that is an arithmetic operation + in a wider mode where both operands are paradoxical SUBREGs + from objects of our result mode. In that case, we couldn't report + an equivalent value for that operation, since we don't know what the + extra bits will be. But we can find an equivalence for this SUBREG + by folding that operation is the narrow mode. This allows us to + fold arithmetic in narrow modes when the machine only supports + word-sized arithmetic. + + Also look for a case where we have a SUBREG whose operand is the + same as our result. If both modes are smaller than a word, we + are simply interpreting a register in different modes and we + can use the inner value. */ + + if (GET_CODE (folded_arg0) == REG + && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (folded_arg0)) + && subreg_lowpart_p (x)) + { + struct table_elt *elt; + + /* We can use HASH here since we know that canon_hash won't be + called. */ + elt = lookup (folded_arg0, + HASH (folded_arg0, GET_MODE (folded_arg0)), + GET_MODE (folded_arg0)); + + if (elt) + elt = elt->first_same_value; + + for (; elt; elt = elt->next_same_value) + { + enum rtx_code eltcode = GET_CODE (elt->exp); + + /* Just check for unary and binary operations. */ + if (GET_RTX_CLASS (GET_CODE (elt->exp)) == '1' + && GET_CODE (elt->exp) != SIGN_EXTEND + && GET_CODE (elt->exp) != ZERO_EXTEND + && GET_CODE (XEXP (elt->exp, 0)) == SUBREG + && GET_MODE (SUBREG_REG (XEXP (elt->exp, 0))) == mode) + { + rtx op0 = SUBREG_REG (XEXP (elt->exp, 0)); + + if (GET_CODE (op0) != REG && ! CONSTANT_P (op0)) + op0 = fold_rtx (op0, NULL_RTX); + + op0 = equiv_constant (op0); + if (op0) + new = simplify_unary_operation (GET_CODE (elt->exp), mode, + op0, mode); + } + else if ((GET_RTX_CLASS (GET_CODE (elt->exp)) == '2' + || GET_RTX_CLASS (GET_CODE (elt->exp)) == 'c') + && eltcode != DIV && eltcode != MOD + && eltcode != UDIV && eltcode != UMOD + && eltcode != ASHIFTRT && eltcode != LSHIFTRT + && eltcode != ROTATE && eltcode != ROTATERT + && ((GET_CODE (XEXP (elt->exp, 0)) == SUBREG + && (GET_MODE (SUBREG_REG (XEXP (elt->exp, 0))) + == mode)) + || CONSTANT_P (XEXP (elt->exp, 0))) + && ((GET_CODE (XEXP (elt->exp, 1)) == SUBREG + && (GET_MODE (SUBREG_REG (XEXP (elt->exp, 1))) + == mode)) + || CONSTANT_P (XEXP (elt->exp, 1)))) + { + rtx op0 = gen_lowpart_common (mode, XEXP (elt->exp, 0)); + rtx op1 = gen_lowpart_common (mode, XEXP (elt->exp, 1)); + + if (op0 && GET_CODE (op0) != REG && ! CONSTANT_P (op0)) + op0 = fold_rtx (op0, NULL_RTX); + + if (op0) + op0 = equiv_constant (op0); + + if (op1 && GET_CODE (op1) != REG && ! CONSTANT_P (op1)) + op1 = fold_rtx (op1, NULL_RTX); + + if (op1) + op1 = equiv_constant (op1); + + if (op0 && op1) + new = simplify_binary_operation (GET_CODE (elt->exp), mode, + op0, op1); + } + + else if (GET_CODE (elt->exp) == SUBREG + && GET_MODE (SUBREG_REG (elt->exp)) == mode + && (GET_MODE_SIZE (GET_MODE (folded_arg0)) + <= UNITS_PER_WORD) + && exp_equiv_p (elt->exp, elt->exp, 1, 0)) + new = copy_rtx (SUBREG_REG (elt->exp)); + + if (new) + return new; + } + } + + return x; + + case NOT: + case NEG: + /* If we have (NOT Y), see if Y is known to be (NOT Z). + If so, (NOT Y) simplifies to Z. Similarly for NEG. */ + new = lookup_as_function (XEXP (x, 0), code); + if (new) + return fold_rtx (copy_rtx (XEXP (new, 0)), insn); + break; + + case MEM: + /* If we are not actually processing an insn, don't try to find the + best address. Not only don't we care, but we could modify the + MEM in an invalid way since we have no insn to validate against. */ + if (insn != 0) + find_best_addr (insn, &XEXP (x, 0)); + + { + /* Even if we don't fold in the insn itself, + we can safely do so here, in hopes of getting a constant. */ + rtx addr = fold_rtx (XEXP (x, 0), NULL_RTX); + rtx base = 0; + HOST_WIDE_INT offset = 0; + + if (GET_CODE (addr) == REG + && REGNO_QTY_VALID_P (REGNO (addr)) + && GET_MODE (addr) == qty_mode[reg_qty[REGNO (addr)]] + && qty_const[reg_qty[REGNO (addr)]] != 0) + addr = qty_const[reg_qty[REGNO (addr)]]; + + /* If address is constant, split it into a base and integer offset. */ + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) + base = addr; + else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS + && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT) + { + base = XEXP (XEXP (addr, 0), 0); + offset = INTVAL (XEXP (XEXP (addr, 0), 1)); + } + else if (GET_CODE (addr) == LO_SUM + && GET_CODE (XEXP (addr, 1)) == SYMBOL_REF) + base = XEXP (addr, 1); + + /* If this is a constant pool reference, we can fold it into its + constant to allow better value tracking. */ + if (base && GET_CODE (base) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (base)) + { + rtx constant = get_pool_constant (base); + enum machine_mode const_mode = get_pool_mode (base); + rtx new; + + if (CONSTANT_P (constant) && GET_CODE (constant) != CONST_INT) + constant_pool_entries_cost = COST (constant); + + /* If we are loading the full constant, we have an equivalence. */ + if (offset == 0 && mode == const_mode) + return constant; + + /* If this actually isn't a constant (wierd!), we can't do + anything. Otherwise, handle the two most common cases: + extracting a word from a multi-word constant, and extracting + the low-order bits. Other cases don't seem common enough to + worry about. */ + if (! CONSTANT_P (constant)) + return x; + + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_SIZE (mode) == UNITS_PER_WORD + && offset % UNITS_PER_WORD == 0 + && (new = operand_subword (constant, + offset / UNITS_PER_WORD, + 0, const_mode)) != 0) + return new; + + if (((BYTES_BIG_ENDIAN + && offset == GET_MODE_SIZE (GET_MODE (constant)) - 1) + || (! BYTES_BIG_ENDIAN && offset == 0)) + && (new = gen_lowpart_if_possible (mode, constant)) != 0) + return new; + } + + /* If this is a reference to a label at a known position in a jump + table, we also know its value. */ + if (base && GET_CODE (base) == LABEL_REF) + { + rtx label = XEXP (base, 0); + rtx table_insn = NEXT_INSN (label); + + if (table_insn && GET_CODE (table_insn) == JUMP_INSN + && GET_CODE (PATTERN (table_insn)) == ADDR_VEC) + { + rtx table = PATTERN (table_insn); + + if (offset >= 0 + && (offset / GET_MODE_SIZE (GET_MODE (table)) + < XVECLEN (table, 0))) + return XVECEXP (table, 0, + offset / GET_MODE_SIZE (GET_MODE (table))); + } + if (table_insn && GET_CODE (table_insn) == JUMP_INSN + && GET_CODE (PATTERN (table_insn)) == ADDR_DIFF_VEC) + { + rtx table = PATTERN (table_insn); + + if (offset >= 0 + && (offset / GET_MODE_SIZE (GET_MODE (table)) + < XVECLEN (table, 1))) + { + offset /= GET_MODE_SIZE (GET_MODE (table)); + new = gen_rtx (MINUS, Pmode, XVECEXP (table, 1, offset), + XEXP (table, 0)); + + if (GET_MODE (table) != Pmode) + new = gen_rtx (TRUNCATE, GET_MODE (table), new); + + return new; + } + } + } + + return x; + } + } + + const_arg0 = 0; + const_arg1 = 0; + const_arg2 = 0; + mode_arg0 = VOIDmode; + + /* Try folding our operands. + Then see which ones have constant values known. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + { + rtx arg = XEXP (x, i); + rtx folded_arg = arg, const_arg = 0; + enum machine_mode mode_arg = GET_MODE (arg); + rtx cheap_arg, expensive_arg; + rtx replacements[2]; + int j; + + /* Most arguments are cheap, so handle them specially. */ + switch (GET_CODE (arg)) + { + case REG: + /* This is the same as calling equiv_constant; it is duplicated + here for speed. */ + if (REGNO_QTY_VALID_P (REGNO (arg)) + && qty_const[reg_qty[REGNO (arg)]] != 0 + && GET_CODE (qty_const[reg_qty[REGNO (arg)]]) != REG + && GET_CODE (qty_const[reg_qty[REGNO (arg)]]) != PLUS) + const_arg + = gen_lowpart_if_possible (GET_MODE (arg), + qty_const[reg_qty[REGNO (arg)]]); + break; + + case CONST: + case CONST_INT: + case SYMBOL_REF: + case LABEL_REF: + case CONST_DOUBLE: + const_arg = arg; + break; + +#ifdef HAVE_cc0 + case CC0: + folded_arg = prev_insn_cc0; + mode_arg = prev_insn_cc0_mode; + const_arg = equiv_constant (folded_arg); + break; +#endif + + default: + folded_arg = fold_rtx (arg, insn); + const_arg = equiv_constant (folded_arg); + } + + /* For the first three operands, see if the operand + is constant or equivalent to a constant. */ + switch (i) + { + case 0: + folded_arg0 = folded_arg; + const_arg0 = const_arg; + mode_arg0 = mode_arg; + break; + case 1: + folded_arg1 = folded_arg; + const_arg1 = const_arg; + break; + case 2: + const_arg2 = const_arg; + break; + } + + /* Pick the least expensive of the folded argument and an + equivalent constant argument. */ + if (const_arg == 0 || const_arg == folded_arg + || COST (const_arg) > COST (folded_arg)) + cheap_arg = folded_arg, expensive_arg = const_arg; + else + cheap_arg = const_arg, expensive_arg = folded_arg; + + /* Try to replace the operand with the cheapest of the two + possibilities. If it doesn't work and this is either of the first + two operands of a commutative operation, try swapping them. + If THAT fails, try the more expensive, provided it is cheaper + than what is already there. */ + + if (cheap_arg == XEXP (x, i)) + continue; + + if (insn == 0 && ! copied) + { + x = copy_rtx (x); + copied = 1; + } + + replacements[0] = cheap_arg, replacements[1] = expensive_arg; + for (j = 0; + j < 2 && replacements[j] + && COST (replacements[j]) < COST (XEXP (x, i)); + j++) + { + if (validate_change (insn, &XEXP (x, i), replacements[j], 0)) + break; + + if (code == NE || code == EQ || GET_RTX_CLASS (code) == 'c') + { + validate_change (insn, &XEXP (x, i), XEXP (x, 1 - i), 1); + validate_change (insn, &XEXP (x, 1 - i), replacements[j], 1); + + if (apply_change_group ()) + { + /* Swap them back to be invalid so that this loop can + continue and flag them to be swapped back later. */ + rtx tem; + + tem = XEXP (x, 0); XEXP (x, 0) = XEXP (x, 1); + XEXP (x, 1) = tem; + must_swap = 1; + break; + } + } + } + } + + else if (fmt[i] == 'E') + /* Don't try to fold inside of a vector of expressions. + Doing nothing is harmless. */ + ; + + /* If a commutative operation, place a constant integer as the second + operand unless the first operand is also a constant integer. Otherwise, + place any constant second unless the first operand is also a constant. */ + + if (code == EQ || code == NE || GET_RTX_CLASS (code) == 'c') + { + if (must_swap || (const_arg0 + && (const_arg1 == 0 + || (GET_CODE (const_arg0) == CONST_INT + && GET_CODE (const_arg1) != CONST_INT)))) + { + register rtx tem = XEXP (x, 0); + + if (insn == 0 && ! copied) + { + x = copy_rtx (x); + copied = 1; + } + + validate_change (insn, &XEXP (x, 0), XEXP (x, 1), 1); + validate_change (insn, &XEXP (x, 1), tem, 1); + if (apply_change_group ()) + { + tem = const_arg0, const_arg0 = const_arg1, const_arg1 = tem; + tem = folded_arg0, folded_arg0 = folded_arg1, folded_arg1 = tem; + } + } + } + + /* If X is an arithmetic operation, see if we can simplify it. */ + + switch (GET_RTX_CLASS (code)) + { + case '1': + /* We can't simplify extension ops unless we know the original mode. */ + if ((code == ZERO_EXTEND || code == SIGN_EXTEND) + && mode_arg0 == VOIDmode) + break; + new = simplify_unary_operation (code, mode, + const_arg0 ? const_arg0 : folded_arg0, + mode_arg0); + break; + + case '<': + /* See what items are actually being compared and set FOLDED_ARG[01] + to those values and CODE to the actual comparison code. If any are + constant, set CONST_ARG0 and CONST_ARG1 appropriately. We needn't + do anything if both operands are already known to be constant. */ + + if (const_arg0 == 0 || const_arg1 == 0) + { + struct table_elt *p0, *p1; + rtx true = const_true_rtx, false = const0_rtx; + enum machine_mode mode_arg1; + +#ifdef FLOAT_STORE_FLAG_VALUE + if (GET_MODE_CLASS (mode) == MODE_FLOAT) + { + true = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, mode); + false = CONST0_RTX (mode); + } +#endif + + code = find_comparison_args (code, &folded_arg0, &folded_arg1, + &mode_arg0, &mode_arg1); + const_arg0 = equiv_constant (folded_arg0); + const_arg1 = equiv_constant (folded_arg1); + + /* If the mode is VOIDmode or a MODE_CC mode, we don't know + what kinds of things are being compared, so we can't do + anything with this comparison. */ + + if (mode_arg0 == VOIDmode || GET_MODE_CLASS (mode_arg0) == MODE_CC) + break; + + /* If we do not now have two constants being compared, see if we + can nevertheless deduce some things about the comparison. */ + if (const_arg0 == 0 || const_arg1 == 0) + { + /* Is FOLDED_ARG0 frame-pointer plus a constant? Or non-explicit + constant? These aren't zero, but we don't know their sign. */ + if (const_arg1 == const0_rtx + && (NONZERO_BASE_PLUS_P (folded_arg0) +#if 0 /* Sad to say, on sysvr4, #pragma weak can make a symbol address + come out as 0. */ + || GET_CODE (folded_arg0) == SYMBOL_REF +#endif + || GET_CODE (folded_arg0) == LABEL_REF + || GET_CODE (folded_arg0) == CONST)) + { + if (code == EQ) + return false; + else if (code == NE) + return true; + } + + /* See if the two operands are the same. We don't do this + for IEEE floating-point since we can't assume x == x + since x might be a NaN. */ + + if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + || GET_MODE_CLASS (mode_arg0) != MODE_FLOAT) + && (folded_arg0 == folded_arg1 + || (GET_CODE (folded_arg0) == REG + && GET_CODE (folded_arg1) == REG + && (reg_qty[REGNO (folded_arg0)] + == reg_qty[REGNO (folded_arg1)])) + || ((p0 = lookup (folded_arg0, + (safe_hash (folded_arg0, mode_arg0) + % NBUCKETS), mode_arg0)) + && (p1 = lookup (folded_arg1, + (safe_hash (folded_arg1, mode_arg0) + % NBUCKETS), mode_arg0)) + && p0->first_same_value == p1->first_same_value))) + return ((code == EQ || code == LE || code == GE + || code == LEU || code == GEU) + ? true : false); + + /* If FOLDED_ARG0 is a register, see if the comparison we are + doing now is either the same as we did before or the reverse + (we only check the reverse if not floating-point). */ + else if (GET_CODE (folded_arg0) == REG) + { + int qty = reg_qty[REGNO (folded_arg0)]; + + if (REGNO_QTY_VALID_P (REGNO (folded_arg0)) + && (comparison_dominates_p (qty_comparison_code[qty], code) + || (comparison_dominates_p (qty_comparison_code[qty], + reverse_condition (code)) + && GET_MODE_CLASS (mode_arg0) == MODE_INT)) + && (rtx_equal_p (qty_comparison_const[qty], folded_arg1) + || (const_arg1 + && rtx_equal_p (qty_comparison_const[qty], + const_arg1)) + || (GET_CODE (folded_arg1) == REG + && (reg_qty[REGNO (folded_arg1)] + == qty_comparison_qty[qty])))) + return (comparison_dominates_p (qty_comparison_code[qty], + code) + ? true : false); + } + } + } + + /* If we are comparing against zero, see if the first operand is + equivalent to an IOR with a constant. If so, we may be able to + determine the result of this comparison. */ + + if (const_arg1 == const0_rtx) + { + rtx y = lookup_as_function (folded_arg0, IOR); + rtx inner_const; + + if (y != 0 + && (inner_const = equiv_constant (XEXP (y, 1))) != 0 + && GET_CODE (inner_const) == CONST_INT + && INTVAL (inner_const) != 0) + { + int sign_bitnum = GET_MODE_BITSIZE (mode_arg0) - 1; + int has_sign = (HOST_BITS_PER_WIDE_INT >= sign_bitnum + && (INTVAL (inner_const) + & ((HOST_WIDE_INT) 1 << sign_bitnum))); + rtx true = const_true_rtx, false = const0_rtx; + +#ifdef FLOAT_STORE_FLAG_VALUE + if (GET_MODE_CLASS (mode) == MODE_FLOAT) + { + true = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, mode); + false = CONST0_RTX (mode); + } +#endif + + switch (code) + { + case EQ: + return false; + case NE: + return true; + case LT: case LE: + if (has_sign) + return true; + break; + case GT: case GE: + if (has_sign) + return false; + break; + } + } + } + + new = simplify_relational_operation (code, mode_arg0, + const_arg0 ? const_arg0 : folded_arg0, + const_arg1 ? const_arg1 : folded_arg1); +#ifdef FLOAT_STORE_FLAG_VALUE + if (new != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT) + new = ((new == const0_rtx) ? CONST0_RTX (mode) + : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, mode)); +#endif + break; + + case '2': + case 'c': + switch (code) + { + case PLUS: + /* If the second operand is a LABEL_REF, see if the first is a MINUS + with that LABEL_REF as its second operand. If so, the result is + the first operand of that MINUS. This handles switches with an + ADDR_DIFF_VEC table. */ + if (const_arg1 && GET_CODE (const_arg1) == LABEL_REF) + { + rtx y = lookup_as_function (folded_arg0, MINUS); + + if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF + && XEXP (XEXP (y, 1), 0) == XEXP (const_arg1, 0)) + return XEXP (y, 0); + } + goto from_plus; + + case MINUS: + /* If we have (MINUS Y C), see if Y is known to be (PLUS Z C2). + If so, produce (PLUS Z C2-C). */ + if (const_arg1 != 0 && GET_CODE (const_arg1) == CONST_INT) + { + rtx y = lookup_as_function (XEXP (x, 0), PLUS); + if (y && GET_CODE (XEXP (y, 1)) == CONST_INT) + return fold_rtx (plus_constant (y, -INTVAL (const_arg1)), + NULL_RTX); + } + + /* ... fall through ... */ + + from_plus: + case SMIN: case SMAX: case UMIN: case UMAX: + case IOR: case AND: case XOR: + case MULT: case DIV: case UDIV: + case ASHIFT: case LSHIFTRT: case ASHIFTRT: + /* If we have ( ) for an associative OP and REG + is known to be of similar form, we may be able to replace the + operation with a combined operation. This may eliminate the + intermediate operation if every use is simplified in this way. + Note that the similar optimization done by combine.c only works + if the intermediate operation's result has only one reference. */ + + if (GET_CODE (folded_arg0) == REG + && const_arg1 && GET_CODE (const_arg1) == CONST_INT) + { + int is_shift + = (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT); + rtx y = lookup_as_function (folded_arg0, code); + rtx inner_const; + enum rtx_code associate_code; + rtx new_const; + + if (y == 0 + || 0 == (inner_const + = equiv_constant (fold_rtx (XEXP (y, 1), 0))) + || GET_CODE (inner_const) != CONST_INT + /* If we have compiled a statement like + "if (x == (x & mask1))", and now are looking at + "x & mask2", we will have a case where the first operand + of Y is the same as our first operand. Unless we detect + this case, an infinite loop will result. */ + || XEXP (y, 0) == folded_arg0) + break; + + /* Don't associate these operations if they are a PLUS with the + same constant and it is a power of two. These might be doable + with a pre- or post-increment. Similarly for two subtracts of + identical powers of two with post decrement. */ + + if (code == PLUS && INTVAL (const_arg1) == INTVAL (inner_const) + && (0 +#if defined(HAVE_PRE_INCREMENT) || defined(HAVE_POST_INCREMENT) + || exact_log2 (INTVAL (const_arg1)) >= 0 +#endif +#if defined(HAVE_PRE_DECREMENT) || defined(HAVE_POST_DECREMENT) + || exact_log2 (- INTVAL (const_arg1)) >= 0 +#endif + )) + break; + + /* Compute the code used to compose the constants. For example, + A/C1/C2 is A/(C1 * C2), so if CODE == DIV, we want MULT. */ + + associate_code + = (code == MULT || code == DIV || code == UDIV ? MULT + : is_shift || code == PLUS || code == MINUS ? PLUS : code); + + new_const = simplify_binary_operation (associate_code, mode, + const_arg1, inner_const); + + if (new_const == 0) + break; + + /* If we are associating shift operations, don't let this + produce a shift of the size of the object or larger. + This could occur when we follow a sign-extend by a right + shift on a machine that does a sign-extend as a pair + of shifts. */ + + if (is_shift && GET_CODE (new_const) == CONST_INT + && INTVAL (new_const) >= GET_MODE_BITSIZE (mode)) + { + /* As an exception, we can turn an ASHIFTRT of this + form into a shift of the number of bits - 1. */ + if (code == ASHIFTRT) + new_const = GEN_INT (GET_MODE_BITSIZE (mode) - 1); + else + break; + } + + y = copy_rtx (XEXP (y, 0)); + + /* If Y contains our first operand (the most common way this + can happen is if Y is a MEM), we would do into an infinite + loop if we tried to fold it. So don't in that case. */ + + if (! reg_mentioned_p (folded_arg0, y)) + y = fold_rtx (y, insn); + + return cse_gen_binary (code, mode, y, new_const); + } + } + + new = simplify_binary_operation (code, mode, + const_arg0 ? const_arg0 : folded_arg0, + const_arg1 ? const_arg1 : folded_arg1); + break; + + case 'o': + /* (lo_sum (high X) X) is simply X. */ + if (code == LO_SUM && const_arg0 != 0 + && GET_CODE (const_arg0) == HIGH + && rtx_equal_p (XEXP (const_arg0, 0), const_arg1)) + return const_arg1; + break; + + case '3': + case 'b': + new = simplify_ternary_operation (code, mode, mode_arg0, + const_arg0 ? const_arg0 : folded_arg0, + const_arg1 ? const_arg1 : folded_arg1, + const_arg2 ? const_arg2 : XEXP (x, 2)); + break; + } + + return new ? new : x; +} + +/* Return a constant value currently equivalent to X. + Return 0 if we don't know one. */ + +static rtx +equiv_constant (x) + rtx x; +{ + if (GET_CODE (x) == REG + && REGNO_QTY_VALID_P (REGNO (x)) + && qty_const[reg_qty[REGNO (x)]]) + x = gen_lowpart_if_possible (GET_MODE (x), qty_const[reg_qty[REGNO (x)]]); + + if (x != 0 && CONSTANT_P (x)) + return x; + + /* If X is a MEM, try to fold it outside the context of any insn to see if + it might be equivalent to a constant. That handles the case where it + is a constant-pool reference. Then try to look it up in the hash table + in case it is something whose value we have seen before. */ + + if (GET_CODE (x) == MEM) + { + struct table_elt *elt; + + x = fold_rtx (x, NULL_RTX); + if (CONSTANT_P (x)) + return x; + + elt = lookup (x, safe_hash (x, GET_MODE (x)) % NBUCKETS, GET_MODE (x)); + if (elt == 0) + return 0; + + for (elt = elt->first_same_value; elt; elt = elt->next_same_value) + if (elt->is_const && CONSTANT_P (elt->exp)) + return elt->exp; + } + + return 0; +} + +/* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a fixed-point + number, return an rtx (MEM, SUBREG, or CONST_INT) that refers to the + least-significant part of X. + MODE specifies how big a part of X to return. + + If the requested operation cannot be done, 0 is returned. + + This is similar to gen_lowpart in emit-rtl.c. */ + +rtx +gen_lowpart_if_possible (mode, x) + enum machine_mode mode; + register rtx x; +{ + rtx result = gen_lowpart_common (mode, x); + + if (result) + return result; + else if (GET_CODE (x) == MEM) + { + /* This is the only other case we handle. */ + register int offset = 0; + rtx new; + +#if WORDS_BIG_ENDIAN + offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) + - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); +#endif +#if BYTES_BIG_ENDIAN + /* Adjust the address so that the address-after-the-data + is unchanged. */ + offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) + - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); +#endif + new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset)); + if (! memory_address_p (mode, XEXP (new, 0))) + return 0; + MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x); + RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x); + MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x); + return new; + } + else + return 0; +} + +/* Given INSN, a jump insn, TAKEN indicates if we are following the "taken" + branch. It will be zero if not. + + In certain cases, this can cause us to add an equivalence. For example, + if we are following the taken case of + if (i == 2) + we can add the fact that `i' and '2' are now equivalent. + + In any case, we can record that this comparison was passed. If the same + comparison is seen later, we will know its value. */ + +static void +record_jump_equiv (insn, taken) + rtx insn; + int taken; +{ + int cond_known_true; + rtx op0, op1; + enum machine_mode mode, mode0, mode1; + int reversed_nonequality = 0; + enum rtx_code code; + + /* Ensure this is the right kind of insn. */ + if (! condjump_p (insn) || simplejump_p (insn)) + return; + + /* See if this jump condition is known true or false. */ + if (taken) + cond_known_true = (XEXP (SET_SRC (PATTERN (insn)), 2) == pc_rtx); + else + cond_known_true = (XEXP (SET_SRC (PATTERN (insn)), 1) == pc_rtx); + + /* Get the type of comparison being done and the operands being compared. + If we had to reverse a non-equality condition, record that fact so we + know that it isn't valid for floating-point. */ + code = GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)); + op0 = fold_rtx (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 0), insn); + op1 = fold_rtx (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 1), insn); + + code = find_comparison_args (code, &op0, &op1, &mode0, &mode1); + if (! cond_known_true) + { + reversed_nonequality = (code != EQ && code != NE); + code = reverse_condition (code); + } + + /* The mode is the mode of the non-constant. */ + mode = mode0; + if (mode1 != VOIDmode) + mode = mode1; + + record_jump_cond (code, mode, op0, op1, reversed_nonequality); +} + +/* We know that comparison CODE applied to OP0 and OP1 in MODE is true. + REVERSED_NONEQUALITY is nonzero if CODE had to be swapped. + Make any useful entries we can with that information. Called from + above function and called recursively. */ + +static void +record_jump_cond (code, mode, op0, op1, reversed_nonequality) + enum rtx_code code; + enum machine_mode mode; + rtx op0, op1; + int reversed_nonequality; +{ + int op0_hash_code, op1_hash_code; + int op0_in_memory, op0_in_struct, op1_in_memory, op1_in_struct; + struct table_elt *op0_elt, *op1_elt; + + /* If OP0 and OP1 are known equal, and either is a paradoxical SUBREG, + we know that they are also equal in the smaller mode (this is also + true for all smaller modes whether or not there is a SUBREG, but + is not worth testing for with no SUBREG. */ + + /* Note that GET_MODE (op0) may not equal MODE. */ + if (code == EQ && GET_CODE (op0) == SUBREG + && (GET_MODE_SIZE (GET_MODE (op0)) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))) + { + enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); + rtx tem = gen_lowpart_if_possible (inner_mode, op1); + + record_jump_cond (code, mode, SUBREG_REG (op0), + tem ? tem : gen_rtx (SUBREG, inner_mode, op1, 0), + reversed_nonequality); + } + + if (code == EQ && GET_CODE (op1) == SUBREG + && (GET_MODE_SIZE (GET_MODE (op1)) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op1))))) + { + enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op1)); + rtx tem = gen_lowpart_if_possible (inner_mode, op0); + + record_jump_cond (code, mode, SUBREG_REG (op1), + tem ? tem : gen_rtx (SUBREG, inner_mode, op0, 0), + reversed_nonequality); + } + + /* Similarly, if this is an NE comparison, and either is a SUBREG + making a smaller mode, we know the whole thing is also NE. */ + + /* Note that GET_MODE (op0) may not equal MODE; + if we test MODE instead, we can get an infinite recursion + alternating between two modes each wider than MODE. */ + + if (code == NE && GET_CODE (op0) == SUBREG + && subreg_lowpart_p (op0) + && (GET_MODE_SIZE (GET_MODE (op0)) + < GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))) + { + enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); + rtx tem = gen_lowpart_if_possible (inner_mode, op1); + + record_jump_cond (code, mode, SUBREG_REG (op0), + tem ? tem : gen_rtx (SUBREG, inner_mode, op1, 0), + reversed_nonequality); + } + + if (code == NE && GET_CODE (op1) == SUBREG + && subreg_lowpart_p (op1) + && (GET_MODE_SIZE (GET_MODE (op1)) + < GET_MODE_SIZE (GET_MODE (SUBREG_REG (op1))))) + { + enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op1)); + rtx tem = gen_lowpart_if_possible (inner_mode, op0); + + record_jump_cond (code, mode, SUBREG_REG (op1), + tem ? tem : gen_rtx (SUBREG, inner_mode, op0, 0), + reversed_nonequality); + } + + /* Hash both operands. */ + + do_not_record = 0; + hash_arg_in_memory = 0; + hash_arg_in_struct = 0; + op0_hash_code = HASH (op0, mode); + op0_in_memory = hash_arg_in_memory; + op0_in_struct = hash_arg_in_struct; + + if (do_not_record) + return; + + do_not_record = 0; + hash_arg_in_memory = 0; + hash_arg_in_struct = 0; + op1_hash_code = HASH (op1, mode); + op1_in_memory = hash_arg_in_memory; + op1_in_struct = hash_arg_in_struct; + + if (do_not_record) + return; + + /* Look up both operands. */ + op0_elt = lookup (op0, op0_hash_code, mode); + op1_elt = lookup (op1, op1_hash_code, mode); + + /* If we aren't setting two things equal all we can do is save this + comparison. Similarly if this is floating-point. In the latter + case, OP1 might be zero and both -0.0 and 0.0 are equal to it. + If we record the equality, we might inadvertently delete code + whose intent was to change -0 to +0. */ + + if (code != EQ || GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT) + { + /* If we reversed a floating-point comparison, if OP0 is not a + register, or if OP1 is neither a register or constant, we can't + do anything. */ + + if (GET_CODE (op1) != REG) + op1 = equiv_constant (op1); + + if ((reversed_nonequality && GET_MODE_CLASS (mode) != MODE_INT) + || GET_CODE (op0) != REG || op1 == 0) + return; + + /* Put OP0 in the hash table if it isn't already. This gives it a + new quantity number. */ + if (op0_elt == 0) + { + if (insert_regs (op0, NULL_PTR, 0)) + { + rehash_using_reg (op0); + op0_hash_code = HASH (op0, mode); + } + + op0_elt = insert (op0, NULL_PTR, op0_hash_code, mode); + op0_elt->in_memory = op0_in_memory; + op0_elt->in_struct = op0_in_struct; + } + + qty_comparison_code[reg_qty[REGNO (op0)]] = code; + if (GET_CODE (op1) == REG) + { + /* Look it up again--in case op0 and op1 are the same. */ + op1_elt = lookup (op1, op1_hash_code, mode); + + /* Put OP1 in the hash table so it gets a new quantity number. */ + if (op1_elt == 0) + { + if (insert_regs (op1, NULL_PTR, 0)) + { + rehash_using_reg (op1); + op1_hash_code = HASH (op1, mode); + } + + op1_elt = insert (op1, NULL_PTR, op1_hash_code, mode); + op1_elt->in_memory = op1_in_memory; + op1_elt->in_struct = op1_in_struct; + } + + qty_comparison_qty[reg_qty[REGNO (op0)]] = reg_qty[REGNO (op1)]; + qty_comparison_const[reg_qty[REGNO (op0)]] = 0; + } + else + { + qty_comparison_qty[reg_qty[REGNO (op0)]] = -1; + qty_comparison_const[reg_qty[REGNO (op0)]] = op1; + } + + return; + } + + /* If both are equivalent, merge the two classes. Save this class for + `cse_set_around_loop'. */ + if (op0_elt && op1_elt) + { + merge_equiv_classes (op0_elt, op1_elt); + last_jump_equiv_class = op0_elt; + } + + /* For whichever side doesn't have an equivalence, make one. */ + if (op0_elt == 0) + { + if (insert_regs (op0, op1_elt, 0)) + { + rehash_using_reg (op0); + op0_hash_code = HASH (op0, mode); + } + + op0_elt = insert (op0, op1_elt, op0_hash_code, mode); + op0_elt->in_memory = op0_in_memory; + op0_elt->in_struct = op0_in_struct; + last_jump_equiv_class = op0_elt; + } + + if (op1_elt == 0) + { + if (insert_regs (op1, op0_elt, 0)) + { + rehash_using_reg (op1); + op1_hash_code = HASH (op1, mode); + } + + op1_elt = insert (op1, op0_elt, op1_hash_code, mode); + op1_elt->in_memory = op1_in_memory; + op1_elt->in_struct = op1_in_struct; + last_jump_equiv_class = op1_elt; + } +} + +/* CSE processing for one instruction. + First simplify sources and addresses of all assignments + in the instruction, using previously-computed equivalents values. + Then install the new sources and destinations in the table + of available values. + + If IN_LIBCALL_BLOCK is nonzero, don't record any equivalence made in + the insn. */ + +/* Data on one SET contained in the instruction. */ + +struct set +{ + /* The SET rtx itself. */ + rtx rtl; + /* The SET_SRC of the rtx (the original value, if it is changing). */ + rtx src; + /* The hash-table element for the SET_SRC of the SET. */ + struct table_elt *src_elt; + /* Hash code for the SET_SRC. */ + int src_hash_code; + /* Hash code for the SET_DEST. */ + int dest_hash_code; + /* The SET_DEST, with SUBREG, etc., stripped. */ + rtx inner_dest; + /* Place where the pointer to the INNER_DEST was found. */ + rtx *inner_dest_loc; + /* Nonzero if the SET_SRC is in memory. */ + char src_in_memory; + /* Nonzero if the SET_SRC is in a structure. */ + char src_in_struct; + /* Nonzero if the SET_SRC contains something + whose value cannot be predicted and understood. */ + char src_volatile; + /* Original machine mode, in case it becomes a CONST_INT. */ + enum machine_mode mode; + /* A constant equivalent for SET_SRC, if any. */ + rtx src_const; + /* Hash code of constant equivalent for SET_SRC. */ + int src_const_hash_code; + /* Table entry for constant equivalent for SET_SRC, if any. */ + struct table_elt *src_const_elt; +}; + +static void +cse_insn (insn, in_libcall_block) + rtx insn; + int in_libcall_block; +{ + register rtx x = PATTERN (insn); + rtx tem; + register int i; + register int n_sets = 0; + + /* Records what this insn does to set CC0. */ + rtx this_insn_cc0 = 0; + enum machine_mode this_insn_cc0_mode; + struct write_data writes_memory; + static struct write_data init = {0, 0, 0, 0}; + + rtx src_eqv = 0; + struct table_elt *src_eqv_elt = 0; + int src_eqv_volatile; + int src_eqv_in_memory; + int src_eqv_in_struct; + int src_eqv_hash_code; + + struct set *sets; + + this_insn = insn; + writes_memory = init; + + /* Find all the SETs and CLOBBERs in this instruction. + Record all the SETs in the array `set' and count them. + Also determine whether there is a CLOBBER that invalidates + all memory references, or all references at varying addresses. */ + + if (GET_CODE (x) == SET) + { + sets = (struct set *) alloca (sizeof (struct set)); + sets[0].rtl = x; + + /* Ignore SETs that are unconditional jumps. + They never need cse processing, so this does not hurt. + The reason is not efficiency but rather + so that we can test at the end for instructions + that have been simplified to unconditional jumps + and not be misled by unchanged instructions + that were unconditional jumps to begin with. */ + if (SET_DEST (x) == pc_rtx + && GET_CODE (SET_SRC (x)) == LABEL_REF) + ; + + /* Don't count call-insns, (set (reg 0) (call ...)), as a set. + The hard function value register is used only once, to copy to + someplace else, so it isn't worth cse'ing (and on 80386 is unsafe)! + Ensure we invalidate the destination register. On the 80386 no + other code would invalidate it since it is a fixed_reg. + We need not check the return of apply_change_group; see canon_reg. */ + + else if (GET_CODE (SET_SRC (x)) == CALL) + { + canon_reg (SET_SRC (x), insn); + apply_change_group (); + fold_rtx (SET_SRC (x), insn); + invalidate (SET_DEST (x)); + } + else + n_sets = 1; + } + else if (GET_CODE (x) == PARALLEL) + { + register int lim = XVECLEN (x, 0); + + sets = (struct set *) alloca (lim * sizeof (struct set)); + + /* Find all regs explicitly clobbered in this insn, + and ensure they are not replaced with any other regs + elsewhere in this insn. + When a reg that is clobbered is also used for input, + we should presume that that is for a reason, + and we should not substitute some other register + which is not supposed to be clobbered. + Therefore, this loop cannot be merged into the one below + because a CALL may precede a CLOBBER and refer to the + value clobbered. We must not let a canonicalization do + anything in that case. */ + for (i = 0; i < lim; i++) + { + register rtx y = XVECEXP (x, 0, i); + if (GET_CODE (y) == CLOBBER + && (GET_CODE (XEXP (y, 0)) == REG + || GET_CODE (XEXP (y, 0)) == SUBREG)) + invalidate (XEXP (y, 0)); + } + + for (i = 0; i < lim; i++) + { + register rtx y = XVECEXP (x, 0, i); + if (GET_CODE (y) == SET) + { + /* As above, we ignore unconditional jumps and call-insns and + ignore the result of apply_change_group. */ + if (GET_CODE (SET_SRC (y)) == CALL) + { + canon_reg (SET_SRC (y), insn); + apply_change_group (); + fold_rtx (SET_SRC (y), insn); + invalidate (SET_DEST (y)); + } + else if (SET_DEST (y) == pc_rtx + && GET_CODE (SET_SRC (y)) == LABEL_REF) + ; + else + sets[n_sets++].rtl = y; + } + else if (GET_CODE (y) == CLOBBER) + { + /* If we clobber memory, take note of that, + and canon the address. + This does nothing when a register is clobbered + because we have already invalidated the reg. */ + if (GET_CODE (XEXP (y, 0)) == MEM) + { + canon_reg (XEXP (y, 0), NULL_RTX); + note_mem_written (XEXP (y, 0), &writes_memory); + } + } + else if (GET_CODE (y) == USE + && ! (GET_CODE (XEXP (y, 0)) == REG + && REGNO (XEXP (y, 0)) < FIRST_PSEUDO_REGISTER)) + canon_reg (y, NULL_RTX); + else if (GET_CODE (y) == CALL) + { + /* The result of apply_change_group can be ignored; see + canon_reg. */ + canon_reg (y, insn); + apply_change_group (); + fold_rtx (y, insn); + } + } + } + else if (GET_CODE (x) == CLOBBER) + { + if (GET_CODE (XEXP (x, 0)) == MEM) + { + canon_reg (XEXP (x, 0), NULL_RTX); + note_mem_written (XEXP (x, 0), &writes_memory); + } + } + + /* Canonicalize a USE of a pseudo register or memory location. */ + else if (GET_CODE (x) == USE + && ! (GET_CODE (XEXP (x, 0)) == REG + && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)) + canon_reg (XEXP (x, 0), NULL_RTX); + else if (GET_CODE (x) == CALL) + { + /* The result of apply_change_group can be ignored; see canon_reg. */ + canon_reg (x, insn); + apply_change_group (); + fold_rtx (x, insn); + } + + if (n_sets == 1 && REG_NOTES (insn) != 0) + { + /* Store the equivalent value in SRC_EQV, if different. */ + rtx tem = find_reg_note (insn, REG_EQUAL, NULL_RTX); + + if (tem && ! rtx_equal_p (XEXP (tem, 0), SET_SRC (sets[0].rtl))) + src_eqv = canon_reg (XEXP (tem, 0), NULL_RTX); + } + + /* Canonicalize sources and addresses of destinations. + We do this in a separate pass to avoid problems when a MATCH_DUP is + present in the insn pattern. In that case, we want to ensure that + we don't break the duplicate nature of the pattern. So we will replace + both operands at the same time. Otherwise, we would fail to find an + equivalent substitution in the loop calling validate_change below. + + We used to suppress canonicalization of DEST if it appears in SRC, + but we don't do this any more. */ + + for (i = 0; i < n_sets; i++) + { + rtx dest = SET_DEST (sets[i].rtl); + rtx src = SET_SRC (sets[i].rtl); + rtx new = canon_reg (src, insn); + + if ((GET_CODE (new) == REG && GET_CODE (src) == REG + && ((REGNO (new) < FIRST_PSEUDO_REGISTER) + != (REGNO (src) < FIRST_PSEUDO_REGISTER))) + || insn_n_dups[recog_memoized (insn)] > 0) + validate_change (insn, &SET_SRC (sets[i].rtl), new, 1); + else + SET_SRC (sets[i].rtl) = new; + + if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) + { + validate_change (insn, &XEXP (dest, 1), + canon_reg (XEXP (dest, 1), insn), 1); + validate_change (insn, &XEXP (dest, 2), + canon_reg (XEXP (dest, 2), insn), 1); + } + + while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART + || GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == SIGN_EXTRACT) + dest = XEXP (dest, 0); + + if (GET_CODE (dest) == MEM) + canon_reg (dest, insn); + } + + /* Now that we have done all the replacements, we can apply the change + group and see if they all work. Note that this will cause some + canonicalizations that would have worked individually not to be applied + because some other canonicalization didn't work, but this should not + occur often. + + The result of apply_change_group can be ignored; see canon_reg. */ + + apply_change_group (); + + /* Set sets[i].src_elt to the class each source belongs to. + Detect assignments from or to volatile things + and set set[i] to zero so they will be ignored + in the rest of this function. + + Nothing in this loop changes the hash table or the register chains. */ + + for (i = 0; i < n_sets; i++) + { + register rtx src, dest; + register rtx src_folded; + register struct table_elt *elt = 0, *p; + enum machine_mode mode; + rtx src_eqv_here; + rtx src_const = 0; + rtx src_related = 0; + struct table_elt *src_const_elt = 0; + int src_cost = 10000, src_eqv_cost = 10000, src_folded_cost = 10000; + int src_related_cost = 10000, src_elt_cost = 10000; + /* Set non-zero if we need to call force_const_mem on with the + contents of src_folded before using it. */ + int src_folded_force_flag = 0; + + dest = SET_DEST (sets[i].rtl); + src = SET_SRC (sets[i].rtl); + + /* If SRC is a constant that has no machine mode, + hash it with the destination's machine mode. + This way we can keep different modes separate. */ + + mode = GET_MODE (src) == VOIDmode ? GET_MODE (dest) : GET_MODE (src); + sets[i].mode = mode; + + if (src_eqv) + { + enum machine_mode eqvmode = mode; + if (GET_CODE (dest) == STRICT_LOW_PART) + eqvmode = GET_MODE (SUBREG_REG (XEXP (dest, 0))); + do_not_record = 0; + hash_arg_in_memory = 0; + hash_arg_in_struct = 0; + src_eqv = fold_rtx (src_eqv, insn); + src_eqv_hash_code = HASH (src_eqv, eqvmode); + + /* Find the equivalence class for the equivalent expression. */ + + if (!do_not_record) + src_eqv_elt = lookup (src_eqv, src_eqv_hash_code, eqvmode); + + src_eqv_volatile = do_not_record; + src_eqv_in_memory = hash_arg_in_memory; + src_eqv_in_struct = hash_arg_in_struct; + } + + /* If this is a STRICT_LOW_PART assignment, src_eqv corresponds to the + value of the INNER register, not the destination. So it is not + a legal substitution for the source. But save it for later. */ + if (GET_CODE (dest) == STRICT_LOW_PART) + src_eqv_here = 0; + else + src_eqv_here = src_eqv; + + /* Simplify and foldable subexpressions in SRC. Then get the fully- + simplified result, which may not necessarily be valid. */ + src_folded = fold_rtx (src, insn); + + /* If storing a constant in a bitfield, pre-truncate the constant + so we will be able to record it later. */ + if (GET_CODE (SET_DEST (sets[i].rtl)) == ZERO_EXTRACT + || GET_CODE (SET_DEST (sets[i].rtl)) == SIGN_EXTRACT) + { + rtx width = XEXP (SET_DEST (sets[i].rtl), 1); + + if (GET_CODE (src) == CONST_INT + && GET_CODE (width) == CONST_INT + && INTVAL (width) < HOST_BITS_PER_WIDE_INT + && (INTVAL (src) & ((HOST_WIDE_INT) (-1) << INTVAL (width)))) + src_folded + = GEN_INT (INTVAL (src) & (((HOST_WIDE_INT) 1 + << INTVAL (width)) - 1)); + } + + /* Compute SRC's hash code, and also notice if it + should not be recorded at all. In that case, + prevent any further processing of this assignment. */ + do_not_record = 0; + hash_arg_in_memory = 0; + hash_arg_in_struct = 0; + + sets[i].src = src; + sets[i].src_hash_code = HASH (src, mode); + sets[i].src_volatile = do_not_record; + sets[i].src_in_memory = hash_arg_in_memory; + sets[i].src_in_struct = hash_arg_in_struct; + +#if 0 + /* It is no longer clear why we used to do this, but it doesn't + appear to still be needed. So let's try without it since this + code hurts cse'ing widened ops. */ + /* If source is a perverse subreg (such as QI treated as an SI), + treat it as volatile. It may do the work of an SI in one context + where the extra bits are not being used, but cannot replace an SI + in general. */ + if (GET_CODE (src) == SUBREG + && (GET_MODE_SIZE (GET_MODE (src)) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))) + sets[i].src_volatile = 1; +#endif + + /* Locate all possible equivalent forms for SRC. Try to replace + SRC in the insn with each cheaper equivalent. + + We have the following types of equivalents: SRC itself, a folded + version, a value given in a REG_EQUAL note, or a value related + to a constant. + + Each of these equivalents may be part of an additional class + of equivalents (if more than one is in the table, they must be in + the same class; we check for this). + + If the source is volatile, we don't do any table lookups. + + We note any constant equivalent for possible later use in a + REG_NOTE. */ + + if (!sets[i].src_volatile) + elt = lookup (src, sets[i].src_hash_code, mode); + + sets[i].src_elt = elt; + + if (elt && src_eqv_here && src_eqv_elt) + { + if (elt->first_same_value != src_eqv_elt->first_same_value) + { + /* The REG_EQUAL is indicating that two formerly distinct + classes are now equivalent. So merge them. */ + merge_equiv_classes (elt, src_eqv_elt); + src_eqv_hash_code = HASH (src_eqv, elt->mode); + src_eqv_elt = lookup (src_eqv, src_eqv_hash_code, elt->mode); + } + + src_eqv_here = 0; + } + + else if (src_eqv_elt) + elt = src_eqv_elt; + + /* Try to find a constant somewhere and record it in `src_const'. + Record its table element, if any, in `src_const_elt'. Look in + any known equivalences first. (If the constant is not in the + table, also set `sets[i].src_const_hash_code'). */ + if (elt) + for (p = elt->first_same_value; p; p = p->next_same_value) + if (p->is_const) + { + src_const = p->exp; + src_const_elt = elt; + break; + } + + if (src_const == 0 + && (CONSTANT_P (src_folded) + /* Consider (minus (label_ref L1) (label_ref L2)) as + "constant" here so we will record it. This allows us + to fold switch statements when an ADDR_DIFF_VEC is used. */ + || (GET_CODE (src_folded) == MINUS + && GET_CODE (XEXP (src_folded, 0)) == LABEL_REF + && GET_CODE (XEXP (src_folded, 1)) == LABEL_REF))) + src_const = src_folded, src_const_elt = elt; + else if (src_const == 0 && src_eqv_here && CONSTANT_P (src_eqv_here)) + src_const = src_eqv_here, src_const_elt = src_eqv_elt; + + /* If we don't know if the constant is in the table, get its + hash code and look it up. */ + if (src_const && src_const_elt == 0) + { + sets[i].src_const_hash_code = HASH (src_const, mode); + src_const_elt = lookup (src_const, sets[i].src_const_hash_code, + mode); + } + + sets[i].src_const = src_const; + sets[i].src_const_elt = src_const_elt; + + /* If the constant and our source are both in the table, mark them as + equivalent. Otherwise, if a constant is in the table but the source + isn't, set ELT to it. */ + if (src_const_elt && elt + && src_const_elt->first_same_value != elt->first_same_value) + merge_equiv_classes (elt, src_const_elt); + else if (src_const_elt && elt == 0) + elt = src_const_elt; + + /* See if there is a register linearly related to a constant + equivalent of SRC. */ + if (src_const + && (GET_CODE (src_const) == CONST + || (src_const_elt && src_const_elt->related_value != 0))) + { + src_related = use_related_value (src_const, src_const_elt); + if (src_related) + { + struct table_elt *src_related_elt + = lookup (src_related, HASH (src_related, mode), mode); + if (src_related_elt && elt) + { + if (elt->first_same_value + != src_related_elt->first_same_value) + /* This can occur when we previously saw a CONST + involving a SYMBOL_REF and then see the SYMBOL_REF + twice. Merge the involved classes. */ + merge_equiv_classes (elt, src_related_elt); + + src_related = 0; + src_related_elt = 0; + } + else if (src_related_elt && elt == 0) + elt = src_related_elt; + } + } + + /* See if we have a CONST_INT that is already in a register in a + wider mode. */ + + if (src_const && src_related == 0 && GET_CODE (src_const) == CONST_INT + && GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_BITSIZE (mode) < BITS_PER_WORD) + { + enum machine_mode wider_mode; + + for (wider_mode = GET_MODE_WIDER_MODE (mode); + GET_MODE_BITSIZE (wider_mode) <= BITS_PER_WORD + && src_related == 0; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + { + struct table_elt *const_elt + = lookup (src_const, HASH (src_const, wider_mode), wider_mode); + + if (const_elt == 0) + continue; + + for (const_elt = const_elt->first_same_value; + const_elt; const_elt = const_elt->next_same_value) + if (GET_CODE (const_elt->exp) == REG) + { + src_related = gen_lowpart_if_possible (mode, + const_elt->exp); + break; + } + } + } + + /* Another possibility is that we have an AND with a constant in + a mode narrower than a word. If so, it might have been generated + as part of an "if" which would narrow the AND. If we already + have done the AND in a wider mode, we can use a SUBREG of that + value. */ + + if (flag_expensive_optimizations && ! src_related + && GET_CODE (src) == AND && GET_CODE (XEXP (src, 1)) == CONST_INT + && GET_MODE_SIZE (mode) < UNITS_PER_WORD) + { + enum machine_mode tmode; + rtx new_and = gen_rtx (AND, VOIDmode, NULL_RTX, XEXP (src, 1)); + + for (tmode = GET_MODE_WIDER_MODE (mode); + GET_MODE_SIZE (tmode) <= UNITS_PER_WORD; + tmode = GET_MODE_WIDER_MODE (tmode)) + { + rtx inner = gen_lowpart_if_possible (tmode, XEXP (src, 0)); + struct table_elt *larger_elt; + + if (inner) + { + PUT_MODE (new_and, tmode); + XEXP (new_and, 0) = inner; + larger_elt = lookup (new_and, HASH (new_and, tmode), tmode); + if (larger_elt == 0) + continue; + + for (larger_elt = larger_elt->first_same_value; + larger_elt; larger_elt = larger_elt->next_same_value) + if (GET_CODE (larger_elt->exp) == REG) + { + src_related + = gen_lowpart_if_possible (mode, larger_elt->exp); + break; + } + + if (src_related) + break; + } + } + } + + if (src == src_folded) + src_folded = 0; + + /* At this point, ELT, if non-zero, points to a class of expressions + equivalent to the source of this SET and SRC, SRC_EQV, SRC_FOLDED, + and SRC_RELATED, if non-zero, each contain additional equivalent + expressions. Prune these latter expressions by deleting expressions + already in the equivalence class. + + Check for an equivalent identical to the destination. If found, + this is the preferred equivalent since it will likely lead to + elimination of the insn. Indicate this by placing it in + `src_related'. */ + + if (elt) elt = elt->first_same_value; + for (p = elt; p; p = p->next_same_value) + { + enum rtx_code code = GET_CODE (p->exp); + + /* If the expression is not valid, ignore it. Then we do not + have to check for validity below. In most cases, we can use + `rtx_equal_p', since canonicalization has already been done. */ + if (code != REG && ! exp_equiv_p (p->exp, p->exp, 1, 0)) + continue; + + if (src && GET_CODE (src) == code && rtx_equal_p (src, p->exp)) + src = 0; + else if (src_folded && GET_CODE (src_folded) == code + && rtx_equal_p (src_folded, p->exp)) + src_folded = 0; + else if (src_eqv_here && GET_CODE (src_eqv_here) == code + && rtx_equal_p (src_eqv_here, p->exp)) + src_eqv_here = 0; + else if (src_related && GET_CODE (src_related) == code + && rtx_equal_p (src_related, p->exp)) + src_related = 0; + + /* This is the same as the destination of the insns, we want + to prefer it. Copy it to src_related. The code below will + then give it a negative cost. */ + if (GET_CODE (dest) == code && rtx_equal_p (p->exp, dest)) + src_related = dest; + + } + + /* Find the cheapest valid equivalent, trying all the available + possibilities. Prefer items not in the hash table to ones + that are when they are equal cost. Note that we can never + worsen an insn as the current contents will also succeed. + If we find an equivalent identical to the destination, use it as best, + since this insn will probably be eliminated in that case. */ + if (src) + { + if (rtx_equal_p (src, dest)) + src_cost = -1; + else + src_cost = COST (src); + } + + if (src_eqv_here) + { + if (rtx_equal_p (src_eqv_here, dest)) + src_eqv_cost = -1; + else + src_eqv_cost = COST (src_eqv_here); + } + + if (src_folded) + { + if (rtx_equal_p (src_folded, dest)) + src_folded_cost = -1; + else + src_folded_cost = COST (src_folded); + } + + if (src_related) + { + if (rtx_equal_p (src_related, dest)) + src_related_cost = -1; + else + src_related_cost = COST (src_related); + } + + /* If this was an indirect jump insn, a known label will really be + cheaper even though it looks more expensive. */ + if (dest == pc_rtx && src_const && GET_CODE (src_const) == LABEL_REF) + src_folded = src_const, src_folded_cost = -1; + + /* Terminate loop when replacement made. This must terminate since + the current contents will be tested and will always be valid. */ + while (1) + { + rtx trial; + + /* Skip invalid entries. */ + while (elt && GET_CODE (elt->exp) != REG + && ! exp_equiv_p (elt->exp, elt->exp, 1, 0)) + elt = elt->next_same_value; + + if (elt) src_elt_cost = elt->cost; + + /* Find cheapest and skip it for the next time. For items + of equal cost, use this order: + src_folded, src, src_eqv, src_related and hash table entry. */ + if (src_folded_cost <= src_cost + && src_folded_cost <= src_eqv_cost + && src_folded_cost <= src_related_cost + && src_folded_cost <= src_elt_cost) + { + trial = src_folded, src_folded_cost = 10000; + if (src_folded_force_flag) + trial = force_const_mem (mode, trial); + } + else if (src_cost <= src_eqv_cost + && src_cost <= src_related_cost + && src_cost <= src_elt_cost) + trial = src, src_cost = 10000; + else if (src_eqv_cost <= src_related_cost + && src_eqv_cost <= src_elt_cost) + trial = src_eqv_here, src_eqv_cost = 10000; + else if (src_related_cost <= src_elt_cost) + trial = src_related, src_related_cost = 10000; + else + { + trial = copy_rtx (elt->exp); + elt = elt->next_same_value; + src_elt_cost = 10000; + } + + /* We don't normally have an insn matching (set (pc) (pc)), so + check for this separately here. We will delete such an + insn below. + + Tablejump insns contain a USE of the table, so simply replacing + the operand with the constant won't match. This is simply an + unconditional branch, however, and is therefore valid. Just + insert the substitution here and we will delete and re-emit + the insn later. */ + + if (n_sets == 1 && dest == pc_rtx + && (trial == pc_rtx + || (GET_CODE (trial) == LABEL_REF + && ! condjump_p (insn)))) + { + /* If TRIAL is a label in front of a jump table, we are + really falling through the switch (this is how casesi + insns work), so we must branch around the table. */ + if (GET_CODE (trial) == CODE_LABEL + && NEXT_INSN (trial) != 0 + && GET_CODE (NEXT_INSN (trial)) == JUMP_INSN + && (GET_CODE (PATTERN (NEXT_INSN (trial))) == ADDR_DIFF_VEC + || GET_CODE (PATTERN (NEXT_INSN (trial))) == ADDR_VEC)) + + trial = gen_rtx (LABEL_REF, Pmode, get_label_after (trial)); + + SET_SRC (sets[i].rtl) = trial; + break; + } + + /* Look for a substitution that makes a valid insn. */ + else if (validate_change (insn, &SET_SRC (sets[i].rtl), trial, 0)) + { + /* The result of apply_change_group can be ignored; see + canon_reg. */ + + validate_change (insn, &SET_SRC (sets[i].rtl), + canon_reg (SET_SRC (sets[i].rtl), insn), + 1); + apply_change_group (); + break; + } + + /* If we previously found constant pool entries for + constants and this is a constant, try making a + pool entry. Put it in src_folded unless we already have done + this since that is where it likely came from. */ + + else if (constant_pool_entries_cost + && CONSTANT_P (trial) + && (src_folded == 0 || GET_CODE (src_folded) != MEM) + && GET_MODE_CLASS (mode) != MODE_CC) + { + src_folded_force_flag = 1; + src_folded = trial; + src_folded_cost = constant_pool_entries_cost; + } + } + + src = SET_SRC (sets[i].rtl); + + /* In general, it is good to have a SET with SET_SRC == SET_DEST. + However, there is an important exception: If both are registers + that are not the head of their equivalence class, replace SET_SRC + with the head of the class. If we do not do this, we will have + both registers live over a portion of the basic block. This way, + their lifetimes will likely abut instead of overlapping. */ + if (GET_CODE (dest) == REG + && REGNO_QTY_VALID_P (REGNO (dest)) + && qty_mode[reg_qty[REGNO (dest)]] == GET_MODE (dest) + && qty_first_reg[reg_qty[REGNO (dest)]] != REGNO (dest) + && GET_CODE (src) == REG && REGNO (src) == REGNO (dest) + /* Don't do this if the original insn had a hard reg as + SET_SRC. */ + && (GET_CODE (sets[i].src) != REG + || REGNO (sets[i].src) >= FIRST_PSEUDO_REGISTER)) + /* We can't call canon_reg here because it won't do anything if + SRC is a hard register. */ + { + int first = qty_first_reg[reg_qty[REGNO (src)]]; + + src = SET_SRC (sets[i].rtl) + = first >= FIRST_PSEUDO_REGISTER ? regno_reg_rtx[first] + : gen_rtx (REG, GET_MODE (src), first); + + /* If we had a constant that is cheaper than what we are now + setting SRC to, use that constant. We ignored it when we + thought we could make this into a no-op. */ + if (src_const && COST (src_const) < COST (src) + && validate_change (insn, &SET_SRC (sets[i].rtl), src_const, 0)) + src = src_const; + } + + /* If we made a change, recompute SRC values. */ + if (src != sets[i].src) + { + do_not_record = 0; + hash_arg_in_memory = 0; + hash_arg_in_struct = 0; + sets[i].src = src; + sets[i].src_hash_code = HASH (src, mode); + sets[i].src_volatile = do_not_record; + sets[i].src_in_memory = hash_arg_in_memory; + sets[i].src_in_struct = hash_arg_in_struct; + sets[i].src_elt = lookup (src, sets[i].src_hash_code, mode); + } + + /* If this is a single SET, we are setting a register, and we have an + equivalent constant, we want to add a REG_NOTE. We don't want + to write a REG_EQUAL note for a constant pseudo since verifying that + that pseudo hasn't been eliminated is a pain. Such a note also + won't help anything. */ + if (n_sets == 1 && src_const && GET_CODE (dest) == REG + && GET_CODE (src_const) != REG) + { + rtx tem = find_reg_note (insn, REG_EQUAL, NULL_RTX); + + /* Record the actual constant value in a REG_EQUAL note, making + a new one if one does not already exist. */ + if (tem) + XEXP (tem, 0) = src_const; + else + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, + src_const, REG_NOTES (insn)); + + /* If storing a constant value in a register that + previously held the constant value 0, + record this fact with a REG_WAS_0 note on this insn. + + Note that the *register* is required to have previously held 0, + not just any register in the quantity and we must point to the + insn that set that register to zero. + + Rather than track each register individually, we just see if + the last set for this quantity was for this register. */ + + if (REGNO_QTY_VALID_P (REGNO (dest)) + && qty_const[reg_qty[REGNO (dest)]] == const0_rtx) + { + /* See if we previously had a REG_WAS_0 note. */ + rtx note = find_reg_note (insn, REG_WAS_0, NULL_RTX); + rtx const_insn = qty_const_insn[reg_qty[REGNO (dest)]]; + + if ((tem = single_set (const_insn)) != 0 + && rtx_equal_p (SET_DEST (tem), dest)) + { + if (note) + XEXP (note, 0) = const_insn; + else + REG_NOTES (insn) = gen_rtx (INSN_LIST, REG_WAS_0, + const_insn, REG_NOTES (insn)); + } + } + } + + /* Now deal with the destination. */ + do_not_record = 0; + sets[i].inner_dest_loc = &SET_DEST (sets[0].rtl); + + /* Look within any SIGN_EXTRACT or ZERO_EXTRACT + to the MEM or REG within it. */ + while (GET_CODE (dest) == SIGN_EXTRACT + || GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == SUBREG + || GET_CODE (dest) == STRICT_LOW_PART) + { + sets[i].inner_dest_loc = &XEXP (dest, 0); + dest = XEXP (dest, 0); + } + + sets[i].inner_dest = dest; + + if (GET_CODE (dest) == MEM) + { + dest = fold_rtx (dest, insn); + + /* Decide whether we invalidate everything in memory, + or just things at non-fixed places. + Writing a large aggregate must invalidate everything + because we don't know how long it is. */ + note_mem_written (dest, &writes_memory); + } + + /* Compute the hash code of the destination now, + before the effects of this instruction are recorded, + since the register values used in the address computation + are those before this instruction. */ + sets[i].dest_hash_code = HASH (dest, mode); + + /* Don't enter a bit-field in the hash table + because the value in it after the store + may not equal what was stored, due to truncation. */ + + if (GET_CODE (SET_DEST (sets[i].rtl)) == ZERO_EXTRACT + || GET_CODE (SET_DEST (sets[i].rtl)) == SIGN_EXTRACT) + { + rtx width = XEXP (SET_DEST (sets[i].rtl), 1); + + if (src_const != 0 && GET_CODE (src_const) == CONST_INT + && GET_CODE (width) == CONST_INT + && INTVAL (width) < HOST_BITS_PER_WIDE_INT + && ! (INTVAL (src_const) + & ((HOST_WIDE_INT) (-1) << INTVAL (width)))) + /* Exception: if the value is constant, + and it won't be truncated, record it. */ + ; + else + { + /* This is chosen so that the destination will be invalidated + but no new value will be recorded. + We must invalidate because sometimes constant + values can be recorded for bitfields. */ + sets[i].src_elt = 0; + sets[i].src_volatile = 1; + src_eqv = 0; + src_eqv_elt = 0; + } + } + + /* If only one set in a JUMP_INSN and it is now a no-op, we can delete + the insn. */ + else if (n_sets == 1 && dest == pc_rtx && src == pc_rtx) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + cse_jumps_altered = 1; + /* One less use of the label this insn used to jump to. */ + --LABEL_NUSES (JUMP_LABEL (insn)); + /* No more processing for this set. */ + sets[i].rtl = 0; + } + + /* If this SET is now setting PC to a label, we know it used to + be a conditional or computed branch. So we see if we can follow + it. If it was a computed branch, delete it and re-emit. */ + else if (dest == pc_rtx && GET_CODE (src) == LABEL_REF) + { + rtx p; + + /* If this is not in the format for a simple branch and + we are the only SET in it, re-emit it. */ + if (! simplejump_p (insn) && n_sets == 1) + { + rtx new = emit_jump_insn_before (gen_jump (XEXP (src, 0)), insn); + JUMP_LABEL (new) = XEXP (src, 0); + LABEL_NUSES (XEXP (src, 0))++; + delete_insn (insn); + insn = new; + } + else + /* Otherwise, force rerecognition, since it probably had + a different pattern before. + This shouldn't really be necessary, since whatever + changed the source value above should have done this. + Until the right place is found, might as well do this here. */ + INSN_CODE (insn) = -1; + + /* Now that we've converted this jump to an unconditional jump, + there is dead code after it. Delete the dead code until we + reach a BARRIER, the end of the function, or a label. Do + not delete NOTEs except for NOTE_INSN_DELETED since later + phases assume these notes are retained. */ + + p = insn; + + while (NEXT_INSN (p) != 0 + && GET_CODE (NEXT_INSN (p)) != BARRIER + && GET_CODE (NEXT_INSN (p)) != CODE_LABEL) + { + if (GET_CODE (NEXT_INSN (p)) != NOTE + || NOTE_LINE_NUMBER (NEXT_INSN (p)) == NOTE_INSN_DELETED) + delete_insn (NEXT_INSN (p)); + else + p = NEXT_INSN (p); + } + + /* If we don't have a BARRIER immediately after INSN, put one there. + Much code assumes that there are no NOTEs between a JUMP_INSN and + BARRIER. */ + + if (NEXT_INSN (insn) == 0 + || GET_CODE (NEXT_INSN (insn)) != BARRIER) + emit_barrier_after (insn); + + /* We might have two BARRIERs separated by notes. Delete the second + one if so. */ + + if (p != insn && NEXT_INSN (p) != 0 + && GET_CODE (NEXT_INSN (p)) == BARRIER) + delete_insn (NEXT_INSN (p)); + + cse_jumps_altered = 1; + sets[i].rtl = 0; + } + + /* If destination is volatile, invalidate it and then do no further + processing for this assignment. */ + + else if (do_not_record) + { + if (GET_CODE (dest) == REG || GET_CODE (dest) == SUBREG + || GET_CODE (dest) == MEM) + invalidate (dest); + sets[i].rtl = 0; + } + + if (sets[i].rtl != 0 && dest != SET_DEST (sets[i].rtl)) + sets[i].dest_hash_code = HASH (SET_DEST (sets[i].rtl), mode); + +#ifdef HAVE_cc0 + /* If setting CC0, record what it was set to, or a constant, if it + is equivalent to a constant. If it is being set to a floating-point + value, make a COMPARE with the appropriate constant of 0. If we + don't do this, later code can interpret this as a test against + const0_rtx, which can cause problems if we try to put it into an + insn as a floating-point operand. */ + if (dest == cc0_rtx) + { + this_insn_cc0 = src_const && mode != VOIDmode ? src_const : src; + this_insn_cc0_mode = mode; + if (GET_MODE_CLASS (mode) == MODE_FLOAT) + this_insn_cc0 = gen_rtx (COMPARE, VOIDmode, this_insn_cc0, + CONST0_RTX (mode)); + } +#endif + } + + /* Now enter all non-volatile source expressions in the hash table + if they are not already present. + Record their equivalence classes in src_elt. + This way we can insert the corresponding destinations into + the same classes even if the actual sources are no longer in them + (having been invalidated). */ + + if (src_eqv && src_eqv_elt == 0 && sets[0].rtl != 0 && ! src_eqv_volatile + && ! rtx_equal_p (src_eqv, SET_DEST (sets[0].rtl))) + { + register struct table_elt *elt; + register struct table_elt *classp = sets[0].src_elt; + rtx dest = SET_DEST (sets[0].rtl); + enum machine_mode eqvmode = GET_MODE (dest); + + if (GET_CODE (dest) == STRICT_LOW_PART) + { + eqvmode = GET_MODE (SUBREG_REG (XEXP (dest, 0))); + classp = 0; + } + if (insert_regs (src_eqv, classp, 0)) + src_eqv_hash_code = HASH (src_eqv, eqvmode); + elt = insert (src_eqv, classp, src_eqv_hash_code, eqvmode); + elt->in_memory = src_eqv_in_memory; + elt->in_struct = src_eqv_in_struct; + src_eqv_elt = elt; + } + + for (i = 0; i < n_sets; i++) + if (sets[i].rtl && ! sets[i].src_volatile + && ! rtx_equal_p (SET_SRC (sets[i].rtl), SET_DEST (sets[i].rtl))) + { + if (GET_CODE (SET_DEST (sets[i].rtl)) == STRICT_LOW_PART) + { + /* REG_EQUAL in setting a STRICT_LOW_PART + gives an equivalent for the entire destination register, + not just for the subreg being stored in now. + This is a more interesting equivalence, so we arrange later + to treat the entire reg as the destination. */ + sets[i].src_elt = src_eqv_elt; + sets[i].src_hash_code = src_eqv_hash_code; + } + else + { + /* Insert source and constant equivalent into hash table, if not + already present. */ + register struct table_elt *classp = src_eqv_elt; + register rtx src = sets[i].src; + register rtx dest = SET_DEST (sets[i].rtl); + enum machine_mode mode + = GET_MODE (src) == VOIDmode ? GET_MODE (dest) : GET_MODE (src); + + if (sets[i].src_elt == 0) + { + register struct table_elt *elt; + + /* Note that these insert_regs calls cannot remove + any of the src_elt's, because they would have failed to + match if not still valid. */ + if (insert_regs (src, classp, 0)) + sets[i].src_hash_code = HASH (src, mode); + elt = insert (src, classp, sets[i].src_hash_code, mode); + elt->in_memory = sets[i].src_in_memory; + elt->in_struct = sets[i].src_in_struct; + sets[i].src_elt = classp = elt; + } + + if (sets[i].src_const && sets[i].src_const_elt == 0 + && src != sets[i].src_const + && ! rtx_equal_p (sets[i].src_const, src)) + sets[i].src_elt = insert (sets[i].src_const, classp, + sets[i].src_const_hash_code, mode); + } + } + else if (sets[i].src_elt == 0) + /* If we did not insert the source into the hash table (e.g., it was + volatile), note the equivalence class for the REG_EQUAL value, if any, + so that the destination goes into that class. */ + sets[i].src_elt = src_eqv_elt; + + invalidate_from_clobbers (&writes_memory, x); + + /* Some registers are invalidated by subroutine calls. Memory is + invalidated by non-constant calls. */ + + if (GET_CODE (insn) == CALL_INSN) + { + static struct write_data everything = {0, 1, 1, 1}; + + if (! CONST_CALL_P (insn)) + invalidate_memory (&everything); + invalidate_for_call (); + } + + /* Now invalidate everything set by this instruction. + If a SUBREG or other funny destination is being set, + sets[i].rtl is still nonzero, so here we invalidate the reg + a part of which is being set. */ + + for (i = 0; i < n_sets; i++) + if (sets[i].rtl) + { + register rtx dest = sets[i].inner_dest; + + /* Needed for registers to remove the register from its + previous quantity's chain. + Needed for memory if this is a nonvarying address, unless + we have just done an invalidate_memory that covers even those. */ + if (GET_CODE (dest) == REG || GET_CODE (dest) == SUBREG + || (! writes_memory.all && ! cse_rtx_addr_varies_p (dest))) + invalidate (dest); + } + + /* Make sure registers mentioned in destinations + are safe for use in an expression to be inserted. + This removes from the hash table + any invalid entry that refers to one of these registers. + + We don't care about the return value from mention_regs because + we are going to hash the SET_DEST values unconditionally. */ + + for (i = 0; i < n_sets; i++) + if (sets[i].rtl && GET_CODE (SET_DEST (sets[i].rtl)) != REG) + mention_regs (SET_DEST (sets[i].rtl)); + + /* We may have just removed some of the src_elt's from the hash table. + So replace each one with the current head of the same class. */ + + for (i = 0; i < n_sets; i++) + if (sets[i].rtl) + { + if (sets[i].src_elt && sets[i].src_elt->first_same_value == 0) + /* If elt was removed, find current head of same class, + or 0 if nothing remains of that class. */ + { + register struct table_elt *elt = sets[i].src_elt; + + while (elt && elt->prev_same_value) + elt = elt->prev_same_value; + + while (elt && elt->first_same_value == 0) + elt = elt->next_same_value; + sets[i].src_elt = elt ? elt->first_same_value : 0; + } + } + + /* Now insert the destinations into their equivalence classes. */ + + for (i = 0; i < n_sets; i++) + if (sets[i].rtl) + { + register rtx dest = SET_DEST (sets[i].rtl); + register struct table_elt *elt; + + /* Don't record value if we are not supposed to risk allocating + floating-point values in registers that might be wider than + memory. */ + if ((flag_float_store + && GET_CODE (dest) == MEM + && GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT) + /* Don't record values of destinations set inside a libcall block + since we might delete the libcall. Things should have been set + up so we won't want to reuse such a value, but we play it safe + here. */ + || in_libcall_block + /* If we didn't put a REG_EQUAL value or a source into the hash + table, there is no point is recording DEST. */ + || sets[i].src_elt == 0) + continue; + + /* STRICT_LOW_PART isn't part of the value BEING set, + and neither is the SUBREG inside it. + Note that in this case SETS[I].SRC_ELT is really SRC_EQV_ELT. */ + if (GET_CODE (dest) == STRICT_LOW_PART) + dest = SUBREG_REG (XEXP (dest, 0)); + + if (GET_CODE (dest) == REG || GET_CODE (dest) == SUBREG) + /* Registers must also be inserted into chains for quantities. */ + if (insert_regs (dest, sets[i].src_elt, 1)) + /* If `insert_regs' changes something, the hash code must be + recalculated. */ + sets[i].dest_hash_code = HASH (dest, GET_MODE (dest)); + + elt = insert (dest, sets[i].src_elt, + sets[i].dest_hash_code, GET_MODE (dest)); + elt->in_memory = GET_CODE (sets[i].inner_dest) == MEM; + if (elt->in_memory) + { + /* This implicitly assumes a whole struct + need not have MEM_IN_STRUCT_P. + But a whole struct is *supposed* to have MEM_IN_STRUCT_P. */ + elt->in_struct = (MEM_IN_STRUCT_P (sets[i].inner_dest) + || sets[i].inner_dest != SET_DEST (sets[i].rtl)); + } + + /* If we have (set (subreg:m1 (reg:m2 foo) 0) (bar:m1)), M1 is no + narrower than M2, and both M1 and M2 are the same number of words, + we are also doing (set (reg:m2 foo) (subreg:m2 (bar:m1) 0)) so + make that equivalence as well. + + However, BAR may have equivalences for which gen_lowpart_if_possible + will produce a simpler value than gen_lowpart_if_possible applied to + BAR (e.g., if BAR was ZERO_EXTENDed from M2), so we will scan all + BAR's equivalences. If we don't get a simplified form, make + the SUBREG. It will not be used in an equivalence, but will + cause two similar assignments to be detected. + + Note the loop below will find SUBREG_REG (DEST) since we have + already entered SRC and DEST of the SET in the table. */ + + if (GET_CODE (dest) == SUBREG + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) / UNITS_PER_WORD + == GET_MODE_SIZE (GET_MODE (dest)) / UNITS_PER_WORD) + && (GET_MODE_SIZE (GET_MODE (dest)) + >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))) + && sets[i].src_elt != 0) + { + enum machine_mode new_mode = GET_MODE (SUBREG_REG (dest)); + struct table_elt *elt, *classp = 0; + + for (elt = sets[i].src_elt->first_same_value; elt; + elt = elt->next_same_value) + { + rtx new_src = 0; + int src_hash; + struct table_elt *src_elt; + + /* Ignore invalid entries. */ + if (GET_CODE (elt->exp) != REG + && ! exp_equiv_p (elt->exp, elt->exp, 1, 0)) + continue; + + new_src = gen_lowpart_if_possible (new_mode, elt->exp); + if (new_src == 0) + new_src = gen_rtx (SUBREG, new_mode, elt->exp, 0); + + src_hash = HASH (new_src, new_mode); + src_elt = lookup (new_src, src_hash, new_mode); + + /* Put the new source in the hash table is if isn't + already. */ + if (src_elt == 0) + { + if (insert_regs (new_src, classp, 0)) + src_hash = HASH (new_src, new_mode); + src_elt = insert (new_src, classp, src_hash, new_mode); + src_elt->in_memory = elt->in_memory; + src_elt->in_struct = elt->in_struct; + } + else if (classp && classp != src_elt->first_same_value) + /* Show that two things that we've seen before are + actually the same. */ + merge_equiv_classes (src_elt, classp); + + classp = src_elt->first_same_value; + } + } + } + + /* Special handling for (set REG0 REG1) + where REG0 is the "cheapest", cheaper than REG1. + After cse, REG1 will probably not be used in the sequel, + so (if easily done) change this insn to (set REG1 REG0) and + replace REG1 with REG0 in the previous insn that computed their value. + Then REG1 will become a dead store and won't cloud the situation + for later optimizations. + + Do not make this change if REG1 is a hard register, because it will + then be used in the sequel and we may be changing a two-operand insn + into a three-operand insn. + + Also do not do this if we are operating on a copy of INSN. */ + + if (n_sets == 1 && sets[0].rtl && GET_CODE (SET_DEST (sets[0].rtl)) == REG + && NEXT_INSN (PREV_INSN (insn)) == insn + && GET_CODE (SET_SRC (sets[0].rtl)) == REG + && REGNO (SET_SRC (sets[0].rtl)) >= FIRST_PSEUDO_REGISTER + && REGNO_QTY_VALID_P (REGNO (SET_SRC (sets[0].rtl))) + && (qty_first_reg[reg_qty[REGNO (SET_SRC (sets[0].rtl))]] + == REGNO (SET_DEST (sets[0].rtl)))) + { + rtx prev = PREV_INSN (insn); + while (prev && GET_CODE (prev) == NOTE) + prev = PREV_INSN (prev); + + if (prev && GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SET + && SET_DEST (PATTERN (prev)) == SET_SRC (sets[0].rtl)) + { + rtx dest = SET_DEST (sets[0].rtl); + rtx note = find_reg_note (prev, REG_EQUIV, NULL_RTX); + + validate_change (prev, & SET_DEST (PATTERN (prev)), dest, 1); + validate_change (insn, & SET_DEST (sets[0].rtl), + SET_SRC (sets[0].rtl), 1); + validate_change (insn, & SET_SRC (sets[0].rtl), dest, 1); + apply_change_group (); + + /* If REG1 was equivalent to a constant, REG0 is not. */ + if (note) + PUT_REG_NOTE_KIND (note, REG_EQUAL); + + /* If there was a REG_WAS_0 note on PREV, remove it. Move + any REG_WAS_0 note on INSN to PREV. */ + note = find_reg_note (prev, REG_WAS_0, NULL_RTX); + if (note) + remove_note (prev, note); + + note = find_reg_note (insn, REG_WAS_0, NULL_RTX); + if (note) + { + remove_note (insn, note); + XEXP (note, 1) = REG_NOTES (prev); + REG_NOTES (prev) = note; + } + } + } + + /* If this is a conditional jump insn, record any known equivalences due to + the condition being tested. */ + + last_jump_equiv_class = 0; + if (GET_CODE (insn) == JUMP_INSN + && n_sets == 1 && GET_CODE (x) == SET + && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE) + record_jump_equiv (insn, 0); + +#ifdef HAVE_cc0 + /* If the previous insn set CC0 and this insn no longer references CC0, + delete the previous insn. Here we use the fact that nothing expects CC0 + to be valid over an insn, which is true until the final pass. */ + if (prev_insn && GET_CODE (prev_insn) == INSN + && (tem = single_set (prev_insn)) != 0 + && SET_DEST (tem) == cc0_rtx + && ! reg_mentioned_p (cc0_rtx, x)) + { + PUT_CODE (prev_insn, NOTE); + NOTE_LINE_NUMBER (prev_insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (prev_insn) = 0; + } + + prev_insn_cc0 = this_insn_cc0; + prev_insn_cc0_mode = this_insn_cc0_mode; +#endif + + prev_insn = insn; +} + +/* Store 1 in *WRITES_PTR for those categories of memory ref + that must be invalidated when the expression WRITTEN is stored in. + If WRITTEN is null, say everything must be invalidated. */ + +static void +note_mem_written (written, writes_ptr) + rtx written; + struct write_data *writes_ptr; +{ + static struct write_data everything = {0, 1, 1, 1}; + + if (written == 0) + *writes_ptr = everything; + else if (GET_CODE (written) == MEM) + { + /* Pushing or popping the stack invalidates just the stack pointer. */ + rtx addr = XEXP (written, 0); + if ((GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC + || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) + && GET_CODE (XEXP (addr, 0)) == REG + && REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM) + { + writes_ptr->sp = 1; + return; + } + else if (GET_MODE (written) == BLKmode) + *writes_ptr = everything; + else if (cse_rtx_addr_varies_p (written)) + { + /* A varying address that is a sum indicates an array element, + and that's just as good as a structure element + in implying that we need not invalidate scalar variables. + However, we must allow QImode aliasing of scalars, because the + ANSI C standard allows character pointers to alias anything. */ + if (! ((MEM_IN_STRUCT_P (written) + || GET_CODE (XEXP (written, 0)) == PLUS) + && GET_MODE (written) != QImode)) + writes_ptr->all = 1; + writes_ptr->nonscalar = 1; + } + writes_ptr->var = 1; + } +} + +/* Perform invalidation on the basis of everything about an insn + except for invalidating the actual places that are SET in it. + This includes the places CLOBBERed, and anything that might + alias with something that is SET or CLOBBERed. + + W points to the writes_memory for this insn, a struct write_data + saying which kinds of memory references must be invalidated. + X is the pattern of the insn. */ + +static void +invalidate_from_clobbers (w, x) + struct write_data *w; + rtx x; +{ + /* If W->var is not set, W specifies no action. + If W->all is set, this step gets all memory refs + so they can be ignored in the rest of this function. */ + if (w->var) + invalidate_memory (w); + + if (w->sp) + { + if (reg_tick[STACK_POINTER_REGNUM] >= 0) + reg_tick[STACK_POINTER_REGNUM]++; + + /* This should be *very* rare. */ + if (TEST_HARD_REG_BIT (hard_regs_in_table, STACK_POINTER_REGNUM)) + invalidate (stack_pointer_rtx); + } + + if (GET_CODE (x) == CLOBBER) + { + rtx ref = XEXP (x, 0); + if (ref + && (GET_CODE (ref) == REG || GET_CODE (ref) == SUBREG + || (GET_CODE (ref) == MEM && ! w->all))) + invalidate (ref); + } + else if (GET_CODE (x) == PARALLEL) + { + register int i; + for (i = XVECLEN (x, 0) - 1; i >= 0; i--) + { + register rtx y = XVECEXP (x, 0, i); + if (GET_CODE (y) == CLOBBER) + { + rtx ref = XEXP (y, 0); + if (ref + &&(GET_CODE (ref) == REG || GET_CODE (ref) == SUBREG + || (GET_CODE (ref) == MEM && !w->all))) + invalidate (ref); + } + } + } +} + +/* Process X, part of the REG_NOTES of an insn. Look at any REG_EQUAL notes + and replace any registers in them with either an equivalent constant + or the canonical form of the register. If we are inside an address, + only do this if the address remains valid. + + OBJECT is 0 except when within a MEM in which case it is the MEM. + + Return the replacement for X. */ + +static rtx +cse_process_notes (x, object) + rtx x; + rtx object; +{ + enum rtx_code code = GET_CODE (x); + char *fmt = GET_RTX_FORMAT (code); + int qty; + int i; + + switch (code) + { + case CONST_INT: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + case CONST_DOUBLE: + case PC: + case CC0: + case LO_SUM: + return x; + + case MEM: + XEXP (x, 0) = cse_process_notes (XEXP (x, 0), x); + return x; + + case EXPR_LIST: + case INSN_LIST: + if (REG_NOTE_KIND (x) == REG_EQUAL) + XEXP (x, 0) = cse_process_notes (XEXP (x, 0), NULL_RTX); + if (XEXP (x, 1)) + XEXP (x, 1) = cse_process_notes (XEXP (x, 1), NULL_RTX); + return x; + + case SIGN_EXTEND: + case ZERO_EXTEND: + { + rtx new = cse_process_notes (XEXP (x, 0), object); + /* We don't substitute VOIDmode constants into these rtx, + since they would impede folding. */ + if (GET_MODE (new) != VOIDmode) + validate_change (object, &XEXP (x, 0), new, 0); + return x; + } + + case REG: + i = reg_qty[REGNO (x)]; + + /* Return a constant or a constant register. */ + if (REGNO_QTY_VALID_P (REGNO (x)) + && qty_const[i] != 0 + && (CONSTANT_P (qty_const[i]) + || GET_CODE (qty_const[i]) == REG)) + { + rtx new = gen_lowpart_if_possible (GET_MODE (x), qty_const[i]); + if (new) + return new; + } + + /* Otherwise, canonicalize this register. */ + return canon_reg (x, NULL_RTX); + } + + for (i = 0; i < GET_RTX_LENGTH (code); i++) + if (fmt[i] == 'e') + validate_change (object, &XEXP (x, i), + cse_process_notes (XEXP (x, i), object), 0); + + return x; +} + +/* Find common subexpressions between the end test of a loop and the beginning + of the loop. LOOP_START is the CODE_LABEL at the start of a loop. + + Often we have a loop where an expression in the exit test is used + in the body of the loop. For example "while (*p) *q++ = *p++;". + Because of the way we duplicate the loop exit test in front of the loop, + however, we don't detect that common subexpression. This will be caught + when global cse is implemented, but this is a quite common case. + + This function handles the most common cases of these common expressions. + It is called after we have processed the basic block ending with the + NOTE_INSN_LOOP_END note that ends a loop and the previous JUMP_INSN + jumps to a label used only once. */ + +static void +cse_around_loop (loop_start) + rtx loop_start; +{ + rtx insn; + int i; + struct table_elt *p; + + /* If the jump at the end of the loop doesn't go to the start, we don't + do anything. */ + for (insn = PREV_INSN (loop_start); + insn && (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) >= 0); + insn = PREV_INSN (insn)) + ; + + if (insn == 0 + || GET_CODE (insn) != NOTE + || NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG) + return; + + /* If the last insn of the loop (the end test) was an NE comparison, + we will interpret it as an EQ comparison, since we fell through + the loop. Any equivalences resulting from that comparison are + therefore not valid and must be invalidated. */ + if (last_jump_equiv_class) + for (p = last_jump_equiv_class->first_same_value; p; + p = p->next_same_value) + if (GET_CODE (p->exp) == MEM || GET_CODE (p->exp) == REG + || GET_CODE (p->exp) == SUBREG) + invalidate (p->exp); + + /* Process insns starting after LOOP_START until we hit a CALL_INSN or + a CODE_LABEL (we could handle a CALL_INSN, but it isn't worth it). + + The only thing we do with SET_DEST is invalidate entries, so we + can safely process each SET in order. It is slightly less efficient + to do so, but we only want to handle the most common cases. */ + + for (insn = NEXT_INSN (loop_start); + GET_CODE (insn) != CALL_INSN && GET_CODE (insn) != CODE_LABEL + && ! (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END); + insn = NEXT_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && (GET_CODE (PATTERN (insn)) == SET + || GET_CODE (PATTERN (insn)) == CLOBBER)) + cse_set_around_loop (PATTERN (insn), insn, loop_start); + else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && GET_CODE (PATTERN (insn)) == PARALLEL) + for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) + if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET + || GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == CLOBBER) + cse_set_around_loop (XVECEXP (PATTERN (insn), 0, i), insn, + loop_start); + } +} + +/* Variable used for communications between the next two routines. */ + +static struct write_data skipped_writes_memory; + +/* Process one SET of an insn that was skipped. We ignore CLOBBERs + since they are done elsewhere. This function is called via note_stores. */ + +static void +invalidate_skipped_set (dest, set) + rtx set; + rtx dest; +{ + if (GET_CODE (set) == CLOBBER +#ifdef HAVE_cc0 + || dest == cc0_rtx +#endif + || dest == pc_rtx) + return; + + if (GET_CODE (dest) == MEM) + note_mem_written (dest, &skipped_writes_memory); + + /* There are times when an address can appear varying and be a PLUS + during this scan when it would be a fixed address were we to know + the proper equivalences. So promote "nonscalar" to be "all". */ + if (skipped_writes_memory.nonscalar) + skipped_writes_memory.all = 1; + + if (GET_CODE (dest) == REG || GET_CODE (dest) == SUBREG + || (! skipped_writes_memory.all && ! cse_rtx_addr_varies_p (dest))) + invalidate (dest); +} + +/* Invalidate all insns from START up to the end of the function or the + next label. This called when we wish to CSE around a block that is + conditionally executed. */ + +static void +invalidate_skipped_block (start) + rtx start; +{ + rtx insn; + int i; + static struct write_data init = {0, 0, 0, 0}; + static struct write_data everything = {0, 1, 1, 1}; + + for (insn = start; insn && GET_CODE (insn) != CODE_LABEL; + insn = NEXT_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + continue; + + skipped_writes_memory = init; + + if (GET_CODE (insn) == CALL_INSN) + { + invalidate_for_call (); + skipped_writes_memory = everything; + } + + note_stores (PATTERN (insn), invalidate_skipped_set); + invalidate_from_clobbers (&skipped_writes_memory, PATTERN (insn)); + } +} + +/* Used for communication between the following two routines; contains a + value to be checked for modification. */ + +static rtx cse_check_loop_start_value; + +/* If modifying X will modify the value in CSE_CHECK_LOOP_START_VALUE, + indicate that fact by setting CSE_CHECK_LOOP_START_VALUE to 0. */ + +static void +cse_check_loop_start (x, set) + rtx x; + rtx set; +{ + if (cse_check_loop_start_value == 0 + || GET_CODE (x) == CC0 || GET_CODE (x) == PC) + return; + + if ((GET_CODE (x) == MEM && GET_CODE (cse_check_loop_start_value) == MEM) + || reg_overlap_mentioned_p (x, cse_check_loop_start_value)) + cse_check_loop_start_value = 0; +} + +/* X is a SET or CLOBBER contained in INSN that was found near the start of + a loop that starts with the label at LOOP_START. + + If X is a SET, we see if its SET_SRC is currently in our hash table. + If so, we see if it has a value equal to some register used only in the + loop exit code (as marked by jump.c). + + If those two conditions are true, we search backwards from the start of + the loop to see if that same value was loaded into a register that still + retains its value at the start of the loop. + + If so, we insert an insn after the load to copy the destination of that + load into the equivalent register and (try to) replace our SET_SRC with that + register. + + In any event, we invalidate whatever this SET or CLOBBER modifies. */ + +static void +cse_set_around_loop (x, insn, loop_start) + rtx x; + rtx insn; + rtx loop_start; +{ + rtx p; + struct table_elt *src_elt; + static struct write_data init = {0, 0, 0, 0}; + struct write_data writes_memory; + + writes_memory = init; + + /* If this is a SET, see if we can replace SET_SRC, but ignore SETs that + are setting PC or CC0 or whose SET_SRC is already a register. */ + if (GET_CODE (x) == SET + && GET_CODE (SET_DEST (x)) != PC && GET_CODE (SET_DEST (x)) != CC0 + && GET_CODE (SET_SRC (x)) != REG) + { + src_elt = lookup (SET_SRC (x), + HASH (SET_SRC (x), GET_MODE (SET_DEST (x))), + GET_MODE (SET_DEST (x))); + + if (src_elt) + for (src_elt = src_elt->first_same_value; src_elt; + src_elt = src_elt->next_same_value) + if (GET_CODE (src_elt->exp) == REG && REG_LOOP_TEST_P (src_elt->exp) + && COST (src_elt->exp) < COST (SET_SRC (x))) + { + rtx p, set; + + /* Look for an insn in front of LOOP_START that sets + something in the desired mode to SET_SRC (x) before we hit + a label or CALL_INSN. */ + + for (p = prev_nonnote_insn (loop_start); + p && GET_CODE (p) != CALL_INSN + && GET_CODE (p) != CODE_LABEL; + p = prev_nonnote_insn (p)) + if ((set = single_set (p)) != 0 + && GET_CODE (SET_DEST (set)) == REG + && GET_MODE (SET_DEST (set)) == src_elt->mode + && rtx_equal_p (SET_SRC (set), SET_SRC (x))) + { + /* We now have to ensure that nothing between P + and LOOP_START modified anything referenced in + SET_SRC (x). We know that nothing within the loop + can modify it, or we would have invalidated it in + the hash table. */ + rtx q; + + cse_check_loop_start_value = SET_SRC (x); + for (q = p; q != loop_start; q = NEXT_INSN (q)) + if (GET_RTX_CLASS (GET_CODE (q)) == 'i') + note_stores (PATTERN (q), cse_check_loop_start); + + /* If nothing was changed and we can replace our + SET_SRC, add an insn after P to copy its destination + to what we will be replacing SET_SRC with. */ + if (cse_check_loop_start_value + && validate_change (insn, &SET_SRC (x), + src_elt->exp, 0)) + emit_insn_after (gen_move_insn (src_elt->exp, + SET_DEST (set)), + p); + break; + } + } + } + + /* Now invalidate anything modified by X. */ + note_mem_written (SET_DEST (x), &writes_memory); + + if (writes_memory.var) + invalidate_memory (&writes_memory); + + /* See comment on similar code in cse_insn for explanation of these tests. */ + if (GET_CODE (SET_DEST (x)) == REG || GET_CODE (SET_DEST (x)) == SUBREG + || (GET_CODE (SET_DEST (x)) == MEM && ! writes_memory.all + && ! cse_rtx_addr_varies_p (SET_DEST (x)))) + invalidate (SET_DEST (x)); +} + +/* Find the end of INSN's basic block and return its range, + the total number of SETs in all the insns of the block, the last insn of the + block, and the branch path. + + The branch path indicates which branches should be followed. If a non-zero + path size is specified, the block should be rescanned and a different set + of branches will be taken. The branch path is only used if + FLAG_CSE_FOLLOW_JUMPS or FLAG_CSE_SKIP_BLOCKS is non-zero. + + DATA is a pointer to a struct cse_basic_block_data, defined below, that is + used to describe the block. It is filled in with the information about + the current block. The incoming structure's branch path, if any, is used + to construct the output branch path. */ + +void +cse_end_of_basic_block (insn, data, follow_jumps, after_loop, skip_blocks) + rtx insn; + struct cse_basic_block_data *data; + int follow_jumps; + int after_loop; + int skip_blocks; +{ + rtx p = insn, q; + int nsets = 0; + int low_cuid = INSN_CUID (insn), high_cuid = INSN_CUID (insn); + rtx next = GET_RTX_CLASS (GET_CODE (insn)) == 'i' ? insn : next_real_insn (insn); + int path_size = data->path_size; + int path_entry = 0; + int i; + + /* Update the previous branch path, if any. If the last branch was + previously TAKEN, mark it NOT_TAKEN. If it was previously NOT_TAKEN, + shorten the path by one and look at the previous branch. We know that + at least one branch must have been taken if PATH_SIZE is non-zero. */ + while (path_size > 0) + { + if (data->path[path_size - 1].status != NOT_TAKEN) + { + data->path[path_size - 1].status = NOT_TAKEN; + break; + } + else + path_size--; + } + + /* Scan to end of this basic block. */ + while (p && GET_CODE (p) != CODE_LABEL) + { + /* Don't cse out the end of a loop. This makes a difference + only for the unusual loops that always execute at least once; + all other loops have labels there so we will stop in any case. + Cse'ing out the end of the loop is dangerous because it + might cause an invariant expression inside the loop + to be reused after the end of the loop. This would make it + hard to move the expression out of the loop in loop.c, + especially if it is one of several equivalent expressions + and loop.c would like to eliminate it. + + If we are running after loop.c has finished, we can ignore + the NOTE_INSN_LOOP_END. */ + + if (! after_loop && GET_CODE (p) == NOTE + && NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END) + break; + + /* Don't cse over a call to setjmp; on some machines (eg vax) + the regs restored by the longjmp come from + a later time than the setjmp. */ + if (GET_CODE (p) == NOTE + && NOTE_LINE_NUMBER (p) == NOTE_INSN_SETJMP) + break; + + /* A PARALLEL can have lots of SETs in it, + especially if it is really an ASM_OPERANDS. */ + if (GET_RTX_CLASS (GET_CODE (p)) == 'i' + && GET_CODE (PATTERN (p)) == PARALLEL) + nsets += XVECLEN (PATTERN (p), 0); + else if (GET_CODE (p) != NOTE) + nsets += 1; + + /* Ignore insns made by CSE; they cannot affect the boundaries of + the basic block. */ + + if (INSN_UID (p) <= max_uid && INSN_CUID (p) > high_cuid) + high_cuid = INSN_CUID (p); + if (INSN_UID (p) <= max_uid && INSN_CUID (p) < low_cuid) + low_cuid = INSN_CUID (p); + + /* See if this insn is in our branch path. If it is and we are to + take it, do so. */ + if (path_entry < path_size && data->path[path_entry].branch == p) + { + if (data->path[path_entry].status != NOT_TAKEN) + p = JUMP_LABEL (p); + + /* Point to next entry in path, if any. */ + path_entry++; + } + + /* If this is a conditional jump, we can follow it if -fcse-follow-jumps + was specified, we haven't reached our maximum path length, there are + insns following the target of the jump, this is the only use of the + jump label, and the target label is preceded by a BARRIER. + + Alternatively, we can follow the jump if it branches around a + block of code and there are no other branches into the block. + In this case invalidate_skipped_block will be called to invalidate any + registers set in the block when following the jump. */ + + else if ((follow_jumps || skip_blocks) && path_size < PATHLENGTH - 1 + && GET_CODE (p) == JUMP_INSN + && GET_CODE (PATTERN (p)) == SET + && GET_CODE (SET_SRC (PATTERN (p))) == IF_THEN_ELSE + && LABEL_NUSES (JUMP_LABEL (p)) == 1 + && NEXT_INSN (JUMP_LABEL (p)) != 0) + { + for (q = PREV_INSN (JUMP_LABEL (p)); q; q = PREV_INSN (q)) + if ((GET_CODE (q) != NOTE + || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END + || NOTE_LINE_NUMBER (q) == NOTE_INSN_SETJMP) + && (GET_CODE (q) != CODE_LABEL || LABEL_NUSES (q) != 0)) + break; + + /* If we ran into a BARRIER, this code is an extension of the + basic block when the branch is taken. */ + if (follow_jumps && q != 0 && GET_CODE (q) == BARRIER) + { + /* Don't allow ourself to keep walking around an + always-executed loop. */ + if (next_real_insn (q) == next) + { + p = NEXT_INSN (p); + continue; + } + + /* Similarly, don't put a branch in our path more than once. */ + for (i = 0; i < path_entry; i++) + if (data->path[i].branch == p) + break; + + if (i != path_entry) + break; + + data->path[path_entry].branch = p; + data->path[path_entry++].status = TAKEN; + + /* This branch now ends our path. It was possible that we + didn't see this branch the last time around (when the + insn in front of the target was a JUMP_INSN that was + turned into a no-op). */ + path_size = path_entry; + + p = JUMP_LABEL (p); + /* Mark block so we won't scan it again later. */ + PUT_MODE (NEXT_INSN (p), QImode); + } + /* Detect a branch around a block of code. */ + else if (skip_blocks && q != 0 && GET_CODE (q) != CODE_LABEL) + { + register rtx tmp; + + if (next_real_insn (q) == next) + { + p = NEXT_INSN (p); + continue; + } + + for (i = 0; i < path_entry; i++) + if (data->path[i].branch == p) + break; + + if (i != path_entry) + break; + + /* This is no_labels_between_p (p, q) with an added check for + reaching the end of a function (in case Q precedes P). */ + for (tmp = NEXT_INSN (p); tmp && tmp != q; tmp = NEXT_INSN (tmp)) + if (GET_CODE (tmp) == CODE_LABEL) + break; + + if (tmp == q) + { + data->path[path_entry].branch = p; + data->path[path_entry++].status = AROUND; + + path_size = path_entry; + + p = JUMP_LABEL (p); + /* Mark block so we won't scan it again later. */ + PUT_MODE (NEXT_INSN (p), QImode); + } + } + } + p = NEXT_INSN (p); + } + + data->low_cuid = low_cuid; + data->high_cuid = high_cuid; + data->nsets = nsets; + data->last = p; + + /* If all jumps in the path are not taken, set our path length to zero + so a rescan won't be done. */ + for (i = path_size - 1; i >= 0; i--) + if (data->path[i].status != NOT_TAKEN) + break; + + if (i == -1) + data->path_size = 0; + else + data->path_size = path_size; + + /* End the current branch path. */ + data->path[path_size].branch = 0; +} + +/* Perform cse on the instructions of a function. + F is the first instruction. + NREGS is one plus the highest pseudo-reg number used in the instruction. + + AFTER_LOOP is 1 if this is the cse call done after loop optimization + (only if -frerun-cse-after-loop). + + Returns 1 if jump_optimize should be redone due to simplifications + in conditional jump instructions. */ + +int +cse_main (f, nregs, after_loop, file) + rtx f; + int nregs; + int after_loop; + FILE *file; +{ + struct cse_basic_block_data val; + register rtx insn = f; + register int i; + + cse_jumps_altered = 0; + constant_pool_entries_cost = 0; + val.path_size = 0; + + init_recog (); + + max_reg = nregs; + + all_minus_one = (int *) alloca (nregs * sizeof (int)); + consec_ints = (int *) alloca (nregs * sizeof (int)); + + for (i = 0; i < nregs; i++) + { + all_minus_one[i] = -1; + consec_ints[i] = i; + } + + reg_next_eqv = (int *) alloca (nregs * sizeof (int)); + reg_prev_eqv = (int *) alloca (nregs * sizeof (int)); + reg_qty = (int *) alloca (nregs * sizeof (int)); + reg_in_table = (int *) alloca (nregs * sizeof (int)); + reg_tick = (int *) alloca (nregs * sizeof (int)); + + /* Discard all the free elements of the previous function + since they are allocated in the temporarily obstack. */ + bzero (table, sizeof table); + free_element_chain = 0; + n_elements_made = 0; + + /* Find the largest uid. */ + + max_uid = get_max_uid (); + uid_cuid = (int *) alloca ((max_uid + 1) * sizeof (int)); + bzero (uid_cuid, (max_uid + 1) * sizeof (int)); + + /* Compute the mapping from uids to cuids. + CUIDs are numbers assigned to insns, like uids, + except that cuids increase monotonically through the code. + Don't assign cuids to line-number NOTEs, so that the distance in cuids + between two insns is not affected by -g. */ + + for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) != NOTE + || NOTE_LINE_NUMBER (insn) < 0) + INSN_CUID (insn) = ++i; + else + /* Give a line number note the same cuid as preceding insn. */ + INSN_CUID (insn) = i; + } + + /* Initialize which registers are clobbered by calls. */ + + CLEAR_HARD_REG_SET (regs_invalidated_by_call); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if ((call_used_regs[i] + /* Used to check !fixed_regs[i] here, but that isn't safe; + fixed regs are still call-clobbered, and sched can get + confused if they can "live across calls". + + The frame pointer is always preserved across calls. The arg + pointer is if it is fixed. The stack pointer usually is, unless + RETURN_POPS_ARGS, in which case an explicit CLOBBER + will be present. If we are generating PIC code, the PIC offset + table register is preserved across calls. */ + + && i != STACK_POINTER_REGNUM + && i != FRAME_POINTER_REGNUM +#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM + && ! (i == ARG_POINTER_REGNUM && fixed_regs[i]) +#endif +#ifdef PIC_OFFSET_TABLE_REGNUM + && ! (i == PIC_OFFSET_TABLE_REGNUM && flag_pic) +#endif + ) + || global_regs[i]) + SET_HARD_REG_BIT (regs_invalidated_by_call, i); + + /* Loop over basic blocks. + Compute the maximum number of qty's needed for each basic block + (which is 2 for each SET). */ + insn = f; + while (insn) + { + cse_end_of_basic_block (insn, &val, flag_cse_follow_jumps, after_loop, + flag_cse_skip_blocks); + + /* If this basic block was already processed or has no sets, skip it. */ + if (val.nsets == 0 || GET_MODE (insn) == QImode) + { + PUT_MODE (insn, VOIDmode); + insn = (val.last ? NEXT_INSN (val.last) : 0); + val.path_size = 0; + continue; + } + + cse_basic_block_start = val.low_cuid; + cse_basic_block_end = val.high_cuid; + max_qty = val.nsets * 2; + + if (file) + fprintf (file, ";; Processing block from %d to %d, %d sets.\n", + INSN_UID (insn), val.last ? INSN_UID (val.last) : 0, + val.nsets); + + /* Make MAX_QTY bigger to give us room to optimize + past the end of this basic block, if that should prove useful. */ + if (max_qty < 500) + max_qty = 500; + + max_qty += max_reg; + + /* If this basic block is being extended by following certain jumps, + (see `cse_end_of_basic_block'), we reprocess the code from the start. + Otherwise, we start after this basic block. */ + if (val.path_size > 0) + cse_basic_block (insn, val.last, val.path, 0); + else + { + int old_cse_jumps_altered = cse_jumps_altered; + rtx temp; + + /* When cse changes a conditional jump to an unconditional + jump, we want to reprocess the block, since it will give + us a new branch path to investigate. */ + cse_jumps_altered = 0; + temp = cse_basic_block (insn, val.last, val.path, ! after_loop); + if (cse_jumps_altered == 0 + || (flag_cse_follow_jumps == 0 && flag_cse_skip_blocks == 0)) + insn = temp; + + cse_jumps_altered |= old_cse_jumps_altered; + } + +#ifdef USE_C_ALLOCA + alloca (0); +#endif + } + + /* Tell refers_to_mem_p that qty_const info is not available. */ + qty_const = 0; + + if (max_elements_made < n_elements_made) + max_elements_made = n_elements_made; + + return cse_jumps_altered; +} + +/* Process a single basic block. FROM and TO and the limits of the basic + block. NEXT_BRANCH points to the branch path when following jumps or + a null path when not following jumps. + + AROUND_LOOP is non-zero if we are to try to cse around to the start of a + loop. This is true when we are being called for the last time on a + block and this CSE pass is before loop.c. */ + +static rtx +cse_basic_block (from, to, next_branch, around_loop) + register rtx from, to; + struct branch_path *next_branch; + int around_loop; +{ + register rtx insn; + int to_usage = 0; + int in_libcall_block = 0; + + /* Each of these arrays is undefined before max_reg, so only allocate + the space actually needed and adjust the start below. */ + + qty_first_reg = (int *) alloca ((max_qty - max_reg) * sizeof (int)); + qty_last_reg = (int *) alloca ((max_qty - max_reg) * sizeof (int)); + qty_mode= (enum machine_mode *) alloca ((max_qty - max_reg) * sizeof (enum machine_mode)); + qty_const = (rtx *) alloca ((max_qty - max_reg) * sizeof (rtx)); + qty_const_insn = (rtx *) alloca ((max_qty - max_reg) * sizeof (rtx)); + qty_comparison_code + = (enum rtx_code *) alloca ((max_qty - max_reg) * sizeof (enum rtx_code)); + qty_comparison_qty = (int *) alloca ((max_qty - max_reg) * sizeof (int)); + qty_comparison_const = (rtx *) alloca ((max_qty - max_reg) * sizeof (rtx)); + + qty_first_reg -= max_reg; + qty_last_reg -= max_reg; + qty_mode -= max_reg; + qty_const -= max_reg; + qty_const_insn -= max_reg; + qty_comparison_code -= max_reg; + qty_comparison_qty -= max_reg; + qty_comparison_const -= max_reg; + + new_basic_block (); + + /* TO might be a label. If so, protect it from being deleted. */ + if (to != 0 && GET_CODE (to) == CODE_LABEL) + ++LABEL_NUSES (to); + + for (insn = from; insn != to; insn = NEXT_INSN (insn)) + { + register enum rtx_code code; + + /* See if this is a branch that is part of the path. If so, and it is + to be taken, do so. */ + if (next_branch->branch == insn) + { + enum taken status = next_branch++->status; + if (status != NOT_TAKEN) + { + if (status == TAKEN) + record_jump_equiv (insn, 1); + else + invalidate_skipped_block (NEXT_INSN (insn)); + + /* Set the last insn as the jump insn; it doesn't affect cc0. + Then follow this branch. */ +#ifdef HAVE_cc0 + prev_insn_cc0 = 0; +#endif + prev_insn = insn; + insn = JUMP_LABEL (insn); + continue; + } + } + + code = GET_CODE (insn); + if (GET_MODE (insn) == QImode) + PUT_MODE (insn, VOIDmode); + + if (GET_RTX_CLASS (code) == 'i') + { + /* Process notes first so we have all notes in canonical forms when + looking for duplicate operations. */ + + if (REG_NOTES (insn)) + REG_NOTES (insn) = cse_process_notes (REG_NOTES (insn), NULL_RTX); + + /* Track when we are inside in LIBCALL block. Inside such a block, + we do not want to record destinations. The last insn of a + LIBCALL block is not considered to be part of the block, since + its destination is the result of the block and hence should be + recorded. */ + + if (find_reg_note (insn, REG_LIBCALL, NULL_RTX)) + in_libcall_block = 1; + else if (find_reg_note (insn, REG_RETVAL, NULL_RTX)) + in_libcall_block = 0; + + cse_insn (insn, in_libcall_block); + } + + /* If INSN is now an unconditional jump, skip to the end of our + basic block by pretending that we just did the last insn in the + basic block. If we are jumping to the end of our block, show + that we can have one usage of TO. */ + + if (simplejump_p (insn)) + { + if (to == 0) + return 0; + + if (JUMP_LABEL (insn) == to) + to_usage = 1; + + /* Maybe TO was deleted because the jump is unconditional. + If so, there is nothing left in this basic block. */ + /* ??? Perhaps it would be smarter to set TO + to whatever follows this insn, + and pretend the basic block had always ended here. */ + if (INSN_DELETED_P (to)) + break; + + insn = PREV_INSN (to); + } + + /* See if it is ok to keep on going past the label + which used to end our basic block. Remember that we incremented + the count of that label, so we decrement it here. If we made + a jump unconditional, TO_USAGE will be one; in that case, we don't + want to count the use in that jump. */ + + if (to != 0 && NEXT_INSN (insn) == to + && GET_CODE (to) == CODE_LABEL && --LABEL_NUSES (to) == to_usage) + { + struct cse_basic_block_data val; + + insn = NEXT_INSN (to); + + if (LABEL_NUSES (to) == 0) + delete_insn (to); + + /* Find the end of the following block. Note that we won't be + following branches in this case. If TO was the last insn + in the function, we are done. Similarly, if we deleted the + insn after TO, it must have been because it was preceded by + a BARRIER. In that case, we are done with this block because it + has no continuation. */ + + if (insn == 0 || INSN_DELETED_P (insn)) + return 0; + + to_usage = 0; + val.path_size = 0; + cse_end_of_basic_block (insn, &val, 0, 0, 0); + + /* If the tables we allocated have enough space left + to handle all the SETs in the next basic block, + continue through it. Otherwise, return, + and that block will be scanned individually. */ + if (val.nsets * 2 + next_qty > max_qty) + break; + + cse_basic_block_start = val.low_cuid; + cse_basic_block_end = val.high_cuid; + to = val.last; + + /* Prevent TO from being deleted if it is a label. */ + if (to != 0 && GET_CODE (to) == CODE_LABEL) + ++LABEL_NUSES (to); + + /* Back up so we process the first insn in the extension. */ + insn = PREV_INSN (insn); + } + } + + if (next_qty > max_qty) + abort (); + + /* If we are running before loop.c, we stopped on a NOTE_INSN_LOOP_END, and + the previous insn is the only insn that branches to the head of a loop, + we can cse into the loop. Don't do this if we changed the jump + structure of a loop unless we aren't going to be following jumps. */ + + if ((cse_jumps_altered == 0 + || (flag_cse_follow_jumps == 0 && flag_cse_skip_blocks == 0)) + && around_loop && to != 0 + && GET_CODE (to) == NOTE && NOTE_LINE_NUMBER (to) == NOTE_INSN_LOOP_END + && GET_CODE (PREV_INSN (to)) == JUMP_INSN + && JUMP_LABEL (PREV_INSN (to)) != 0 + && LABEL_NUSES (JUMP_LABEL (PREV_INSN (to))) == 1) + cse_around_loop (JUMP_LABEL (PREV_INSN (to))); + + return to ? NEXT_INSN (to) : 0; +} + +/* Count the number of times registers are used (not set) in X. + COUNTS is an array in which we accumulate the count, INCR is how much + we count each register usage. */ + +static void +count_reg_usage (x, counts, incr) + rtx x; + int *counts; + int incr; +{ + enum rtx_code code = GET_CODE (x); + char *fmt; + int i, j; + + switch (code) + { + case REG: + counts[REGNO (x)] += incr; + return; + + case PC: + case CC0: + case CONST: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case CLOBBER: + return; + + case SET: + /* Unless we are setting a REG, count everything in SET_DEST. */ + if (GET_CODE (SET_DEST (x)) != REG) + count_reg_usage (SET_DEST (x), counts, incr); + count_reg_usage (SET_SRC (x), counts, incr); + return; + + case INSN: + case JUMP_INSN: + case CALL_INSN: + count_reg_usage (PATTERN (x), counts, incr); + + /* Things used in a REG_EQUAL note aren't dead since loop may try to + use them. */ + + if (REG_NOTES (x)) + count_reg_usage (REG_NOTES (x), counts, incr); + return; + + case EXPR_LIST: + case INSN_LIST: + if (REG_NOTE_KIND (x) == REG_EQUAL) + count_reg_usage (XEXP (x, 0), counts, incr); + if (XEXP (x, 1)) + count_reg_usage (XEXP (x, 1), counts, incr); + return; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + count_reg_usage (XEXP (x, i), counts, incr); + else if (fmt[i] == 'E') + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + count_reg_usage (XVECEXP (x, i, j), counts, incr); + } +} + +/* Scan all the insns and delete any that are dead; i.e., they store a register + that is never used or they copy a register to itself. + + This is used to remove insns made obviously dead by cse. It improves the + heuristics in loop since it won't try to move dead invariants out of loops + or make givs for dead quantities. The remaining passes of the compilation + are also sped up. */ + +void +delete_dead_from_cse (insns, nreg) + rtx insns; + int nreg; +{ + int *counts = (int *) alloca (nreg * sizeof (int)); + rtx insn, prev; + rtx tem; + int i; + int in_libcall = 0; + + /* First count the number of times each register is used. */ + bzero (counts, sizeof (int) * nreg); + for (insn = next_real_insn (insns); insn; insn = next_real_insn (insn)) + count_reg_usage (insn, counts, 1); + + /* Go from the last insn to the first and delete insns that only set unused + registers or copy a register to itself. As we delete an insn, remove + usage counts for registers it uses. */ + for (insn = prev_real_insn (get_last_insn ()); insn; insn = prev) + { + int live_insn = 0; + + prev = prev_real_insn (insn); + + /* Don't delete any insns that are part of a libcall block. + Flow or loop might get confused if we did that. Remember + that we are scanning backwards. */ + if (find_reg_note (insn, REG_RETVAL, NULL_RTX)) + in_libcall = 1; + + if (in_libcall) + live_insn = 1; + else if (GET_CODE (PATTERN (insn)) == SET) + { + if (GET_CODE (SET_DEST (PATTERN (insn))) == REG + && SET_DEST (PATTERN (insn)) == SET_SRC (PATTERN (insn))) + ; + +#ifdef HAVE_cc0 + else if (GET_CODE (SET_DEST (PATTERN (insn))) == CC0 + && ! side_effects_p (SET_SRC (PATTERN (insn))) + && ((tem = next_nonnote_insn (insn)) == 0 + || GET_RTX_CLASS (GET_CODE (tem)) != 'i' + || ! reg_referenced_p (cc0_rtx, PATTERN (tem)))) + ; +#endif + else if (GET_CODE (SET_DEST (PATTERN (insn))) != REG + || REGNO (SET_DEST (PATTERN (insn))) < FIRST_PSEUDO_REGISTER + || counts[REGNO (SET_DEST (PATTERN (insn)))] != 0 + || side_effects_p (SET_SRC (PATTERN (insn)))) + live_insn = 1; + } + else if (GET_CODE (PATTERN (insn)) == PARALLEL) + for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) + { + rtx elt = XVECEXP (PATTERN (insn), 0, i); + + if (GET_CODE (elt) == SET) + { + if (GET_CODE (SET_DEST (elt)) == REG + && SET_DEST (elt) == SET_SRC (elt)) + ; + +#ifdef HAVE_cc0 + else if (GET_CODE (SET_DEST (elt)) == CC0 + && ! side_effects_p (SET_SRC (elt)) + && ((tem = next_nonnote_insn (insn)) == 0 + || GET_RTX_CLASS (GET_CODE (tem)) != 'i' + || ! reg_referenced_p (cc0_rtx, PATTERN (tem)))) + ; +#endif + else if (GET_CODE (SET_DEST (elt)) != REG + || REGNO (SET_DEST (elt)) < FIRST_PSEUDO_REGISTER + || counts[REGNO (SET_DEST (elt))] != 0 + || side_effects_p (SET_SRC (elt))) + live_insn = 1; + } + else if (GET_CODE (elt) != CLOBBER && GET_CODE (elt) != USE) + live_insn = 1; + } + else + live_insn = 1; + + /* If this is a dead insn, delete it and show registers in it aren't + being used. */ + + if (! live_insn) + { + count_reg_usage (insn, counts, -1); + delete_insn (insn); + } + + if (find_reg_note (insn, REG_LIBCALL, NULL_RTX)) + in_libcall = 0; + } +} diff --git a/gnu/usr.bin/cc/lib/dbxout.c b/gnu/usr.bin/cc/lib/dbxout.c new file mode 100644 index 000000000000..4f3a348c6024 --- /dev/null +++ b/gnu/usr.bin/cc/lib/dbxout.c @@ -0,0 +1,2439 @@ +/* Output dbx-format symbol table information from GNU compiler. + Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* Output dbx-format symbol table data. + This consists of many symbol table entries, each of them + a .stabs assembler pseudo-op with four operands: + a "name" which is really a description of one symbol and its type, + a "code", which is a symbol defined in stab.h whose name starts with N_, + an unused operand always 0, + and a "value" which is an address or an offset. + The name is enclosed in doublequote characters. + + Each function, variable, typedef, and structure tag + has a symbol table entry to define it. + The beginning and end of each level of name scoping within + a function are also marked by special symbol table entries. + + The "name" consists of the symbol name, a colon, a kind-of-symbol letter, + and a data type number. The data type number may be followed by + "=" and a type definition; normally this will happen the first time + the type number is mentioned. The type definition may refer to + other types by number, and those type numbers may be followed + by "=" and nested definitions. + + This can make the "name" quite long. + When a name is more than 80 characters, we split the .stabs pseudo-op + into two .stabs pseudo-ops, both sharing the same "code" and "value". + The first one is marked as continued with a double-backslash at the + end of its "name". + + The kind-of-symbol letter distinguished function names from global + variables from file-scope variables from parameters from auto + variables in memory from typedef names from register variables. + See `dbxout_symbol'. + + The "code" is mostly redundant with the kind-of-symbol letter + that goes in the "name", but not entirely: for symbols located + in static storage, the "code" says which segment the address is in, + which controls how it is relocated. + + The "value" for a symbol in static storage + is the core address of the symbol (actually, the assembler + label for the symbol). For a symbol located in a stack slot + it is the stack offset; for one in a register, the register number. + For a typedef symbol, it is zero. + + If DEBUG_SYMS_TEXT is defined, all debugging symbols must be + output while in the text section. + + For more on data type definitions, see `dbxout_type'. */ + +/* Include these first, because they may define MIN and MAX. */ +#include +#include + +#include "config.h" +#include "tree.h" +#include "rtl.h" +#include "flags.h" +#include "regs.h" +#include "insn-config.h" +#include "reload.h" +#include "defaults.h" +#include "output.h" /* ASM_OUTPUT_SOURCE_LINE may refer to sdb functions. */ + +#ifndef errno +extern int errno; +#endif + +#ifdef XCOFF_DEBUGGING_INFO +#include "xcoffout.h" +#endif + +#ifndef ASM_STABS_OP +#define ASM_STABS_OP ".stabs" +#endif + +#ifndef ASM_STABN_OP +#define ASM_STABN_OP ".stabn" +#endif + +#ifndef DBX_TYPE_DECL_STABS_CODE +#define DBX_TYPE_DECL_STABS_CODE N_LSYM +#endif + +#ifndef DBX_STATIC_CONST_VAR_CODE +#define DBX_STATIC_CONST_VAR_CODE N_FUN +#endif + +#ifndef DBX_REGPARM_STABS_CODE +#define DBX_REGPARM_STABS_CODE N_RSYM +#endif + +#ifndef DBX_REGPARM_STABS_LETTER +#define DBX_REGPARM_STABS_LETTER 'P' +#endif + +#ifndef DBX_MEMPARM_STABS_LETTER +#define DBX_MEMPARM_STABS_LETTER 'p' +#endif + +/* Nonzero means if the type has methods, only output debugging + information if methods are actually written to the asm file. */ + +static int flag_minimal_debug = 1; + +/* Nonzero if we have actually used any of the GDB extensions + to the debugging format. The idea is that we use them for the + first time only if there's a strong reason, but once we have done that, + we use them whenever convenient. */ + +static int have_used_extensions = 0; + +char *getpwd (); + +/* Typical USG systems don't have stab.h, and they also have + no use for DBX-format debugging info. */ + +#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) + +#ifdef DEBUG_SYMS_TEXT +#define FORCE_TEXT text_section (); +#else +#define FORCE_TEXT +#endif + +#if defined (USG) || defined (NO_STAB_H) +#include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */ +#else +#include /* On BSD, use the system's stab.h. */ + +/* This is a GNU extension we need to reference in this file. */ +#ifndef N_CATCH +#define N_CATCH 0x54 +#endif +#endif /* not USG */ + +#ifdef __GNU_STAB__ +#define STAB_CODE_TYPE enum __stab_debug_code +#else +#define STAB_CODE_TYPE int +#endif + +/* 1 if PARM is passed to this function in memory. */ + +#define PARM_PASSED_IN_MEMORY(PARM) \ + (GET_CODE (DECL_INCOMING_RTL (PARM)) == MEM) + +/* A C expression for the integer offset value of an automatic variable + (N_LSYM) having address X (an RTX). */ +#ifndef DEBUGGER_AUTO_OFFSET +#define DEBUGGER_AUTO_OFFSET(X) \ + (GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) +#endif + +/* A C expression for the integer offset value of an argument (N_PSYM) + having address X (an RTX). The nominal offset is OFFSET. */ +#ifndef DEBUGGER_ARG_OFFSET +#define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET) +#endif + +/* Stream for writing to assembler file. */ + +static FILE *asmfile; + +/* Last source file name mentioned in a NOTE insn. */ + +static char *lastfile; + +/* Current working directory. */ + +static char *cwd; + +enum typestatus {TYPE_UNSEEN, TYPE_XREF, TYPE_DEFINED}; + +/* Vector recording the status of describing C data types. + When we first notice a data type (a tree node), + we assign it a number using next_type_number. + That is its index in this vector. + The vector element says whether we have yet output + the definition of the type. TYPE_XREF says we have + output it as a cross-reference only. */ + +enum typestatus *typevec; + +/* Number of elements of space allocated in `typevec'. */ + +static int typevec_len; + +/* In dbx output, each type gets a unique number. + This is the number for the next type output. + The number, once assigned, is in the TYPE_SYMTAB_ADDRESS field. */ + +static int next_type_number; + +/* In dbx output, we must assign symbol-blocks id numbers + in the order in which their beginnings are encountered. + We output debugging info that refers to the beginning and + end of the ranges of code in each block + with assembler labels LBBn and LBEn, where n is the block number. + The labels are generated in final, which assigns numbers to the + blocks in the same way. */ + +static int next_block_number; + +/* These variables are for dbxout_symbol to communicate to + dbxout_finish_symbol. + current_sym_code is the symbol-type-code, a symbol N_... define in stab.h. + current_sym_value and current_sym_addr are two ways to address the + value to store in the symtab entry. + current_sym_addr if nonzero represents the value as an rtx. + If that is zero, current_sym_value is used. This is used + when the value is an offset (such as for auto variables, + register variables and parms). */ + +static STAB_CODE_TYPE current_sym_code; +static int current_sym_value; +static rtx current_sym_addr; + +/* Number of chars of symbol-description generated so far for the + current symbol. Used by CHARS and CONTIN. */ + +static int current_sym_nchars; + +/* Report having output N chars of the current symbol-description. */ + +#define CHARS(N) (current_sym_nchars += (N)) + +/* Break the current symbol-description, generating a continuation, + if it has become long. */ + +#ifndef DBX_CONTIN_LENGTH +#define DBX_CONTIN_LENGTH 80 +#endif + +#if DBX_CONTIN_LENGTH > 0 +#define CONTIN \ + do {if (current_sym_nchars > DBX_CONTIN_LENGTH) dbxout_continue ();} while (0) +#else +#define CONTIN +#endif + +void dbxout_types (); +void dbxout_args (); +void dbxout_symbol (); +static void dbxout_type_name (); +static void dbxout_type (); +static void dbxout_typedefs (); +static void dbxout_prepare_symbol (); +static void dbxout_finish_symbol (); +static void dbxout_continue (); +static void print_int_cst_octal (); +static void print_octal (); + +#if 0 /* Not clear we will actually need this. */ + +/* Return the absolutized filename for the given relative + filename. Note that if that filename is already absolute, it may + still be returned in a modified form because this routine also + eliminates redundant slashes and single dots and eliminates double + dots to get a shortest possible filename from the given input + filename. The absolutization of relative filenames is made by + assuming that the given filename is to be taken as relative to + the first argument (cwd) or to the current directory if cwd is + NULL. */ + +static char * +abspath (rel_filename) + char *rel_filename; +{ + /* Setup the current working directory as needed. */ + char *abs_buffer + = (char *) alloca (strlen (cwd) + strlen (rel_filename) + 1); + char *endp = abs_buffer; + char *outp, *inp; + char *value; + + /* Copy the filename (possibly preceded by the current working + directory name) into the absolutization buffer. */ + + { + char *src_p; + + if (rel_filename[0] != '/') + { + src_p = cwd; + while (*endp++ = *src_p++) + continue; + *(endp-1) = '/'; /* overwrite null */ + } + src_p = rel_filename; + while (*endp++ = *src_p++) + continue; + if (endp[-1] == '/') + *endp = '\0'; + + /* Now make a copy of abs_buffer into abs_buffer, shortening the + filename (by taking out slashes and dots) as we go. */ + + outp = inp = abs_buffer; + *outp++ = *inp++; /* copy first slash */ + for (;;) + { + if (!inp[0]) + break; + else if (inp[0] == '/' && outp[-1] == '/') + { + inp++; + continue; + } + else if (inp[0] == '.' && outp[-1] == '/') + { + if (!inp[1]) + break; + else if (inp[1] == '/') + { + inp += 2; + continue; + } + else if ((inp[1] == '.') && (inp[2] == 0 || inp[2] == '/')) + { + inp += (inp[2] == '/') ? 3 : 2; + outp -= 2; + while (outp >= abs_buffer && *outp != '/') + outp--; + if (outp < abs_buffer) + { + /* Catch cases like /.. where we try to backup to a + point above the absolute root of the logical file + system. */ + + fprintf (stderr, "%s: invalid file name: %s\n", + pname, rel_filename); + exit (1); + } + *++outp = '\0'; + continue; + } + } + *outp++ = *inp++; + } + + /* On exit, make sure that there is a trailing null, and make sure that + the last character of the returned string is *not* a slash. */ + + *outp = '\0'; + if (outp[-1] == '/') + *--outp = '\0'; + + /* Make a copy (in the heap) of the stuff left in the absolutization + buffer and return a pointer to the copy. */ + + value = (char *) oballoc (strlen (abs_buffer) + 1); + strcpy (value, abs_buffer); + return value; +} +#endif /* 0 */ + +/* At the beginning of compilation, start writing the symbol table. + Initialize `typevec' and output the standard data types of C. */ + +void +dbxout_init (asm_file, input_file_name, syms) + FILE *asm_file; + char *input_file_name; + tree syms; +{ + char ltext_label_name[100]; + + asmfile = asm_file; + + typevec_len = 100; + typevec = (enum typestatus *) xmalloc (typevec_len * sizeof typevec[0]); + bzero (typevec, typevec_len * sizeof typevec[0]); + + /* Convert Ltext into the appropriate format for local labels in case + the system doesn't insert underscores in front of user generated + labels. */ + ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0); + + /* Put the current working directory in an N_SO symbol. */ +#ifndef DBX_WORKING_DIRECTORY /* Only some versions of DBX want this, + but GDB always does. */ + if (use_gnu_debug_info_extensions) +#endif + { + if (cwd || (cwd = getpwd ())) + { +#ifdef DBX_OUTPUT_MAIN_SOURCE_DIRECTORY + DBX_OUTPUT_MAIN_SOURCE_DIRECTORY (asmfile, cwd); +#else /* no DBX_OUTPUT_MAIN_SOURCE_DIRECTORY */ + fprintf (asmfile, "%s \"%s/\",%d,0,0,%s\n", ASM_STABS_OP, + cwd, N_SO, <ext_label_name[1]); +#endif /* no DBX_OUTPUT_MAIN_SOURCE_DIRECTORY */ + } + } + +#ifdef DBX_OUTPUT_MAIN_SOURCE_FILENAME + /* This should NOT be DBX_OUTPUT_SOURCE_FILENAME. That + would give us an N_SOL, and we want an N_SO. */ + DBX_OUTPUT_MAIN_SOURCE_FILENAME (asmfile, input_file_name); +#else /* no DBX_OUTPUT_MAIN_SOURCE_FILENAME */ + /* We include outputting `Ltext:' here, + because that gives you a way to override it. */ + /* Used to put `Ltext:' before the reference, but that loses on sun 4. */ + fprintf (asmfile, "%s \"%s\",%d,0,0,%s\n", ASM_STABS_OP, input_file_name, + N_SO, <ext_label_name[1]); + text_section (); + ASM_OUTPUT_INTERNAL_LABEL (asmfile, "Ltext", 0); +#endif /* no DBX_OUTPUT_MAIN_SOURCE_FILENAME */ + + /* Possibly output something to inform GDB that this compilation was by + GCC. It's easier for GDB to parse it when after the N_SO's. This + is used in Solaris 2. */ +#ifdef ASM_IDENTIFY_GCC_AFTER_SOURCE + ASM_IDENTIFY_GCC_AFTER_SOURCE (asmfile); +#endif + + lastfile = input_file_name; + + next_type_number = 1; + next_block_number = 2; + + /* Make sure that types `int' and `char' have numbers 1 and 2. + Definitions of other integer types will refer to those numbers. + (Actually it should no longer matter what their numbers are. + Also, if any types with tags have been defined, dbxout_symbol + will output them first, so the numbers won't be 1 and 2. That + happens in C++. So it's a good thing it should no longer matter). */ + +#ifdef DBX_OUTPUT_STANDARD_TYPES + DBX_OUTPUT_STANDARD_TYPES (syms); +#else + dbxout_symbol (TYPE_NAME (integer_type_node), 0); + dbxout_symbol (TYPE_NAME (char_type_node), 0); +#endif + + /* Get all permanent types that have typedef names, + and output them all, except for those already output. */ + + dbxout_typedefs (syms); +} + +/* Output any typedef names for types described by TYPE_DECLs in SYMS, + in the reverse order from that which is found in SYMS. */ + +static void +dbxout_typedefs (syms) + tree syms; +{ + if (syms) + { + dbxout_typedefs (TREE_CHAIN (syms)); + if (TREE_CODE (syms) == TYPE_DECL) + { + tree type = TREE_TYPE (syms); + if (TYPE_NAME (type) + && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL + && ! TREE_ASM_WRITTEN (TYPE_NAME (type))) + dbxout_symbol (TYPE_NAME (type), 0); + } + } +} + +/* Output debugging info to FILE to switch to sourcefile FILENAME. */ + +void +dbxout_source_file (file, filename) + FILE *file; + char *filename; +{ + char ltext_label_name[100]; + + if (filename && (lastfile == 0 || strcmp (filename, lastfile))) + { +#ifdef DBX_OUTPUT_SOURCE_FILENAME + DBX_OUTPUT_SOURCE_FILENAME (file, filename); +#else + ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0); + fprintf (file, "%s \"%s\",%d,0,0,%s\n", ASM_STABS_OP, + filename, N_SOL, <ext_label_name[1]); +#endif + lastfile = filename; + } +} + +/* Output a line number symbol entry into output stream FILE, + for source file FILENAME and line number LINENO. */ + +void +dbxout_source_line (file, filename, lineno) + FILE *file; + char *filename; + int lineno; +{ + dbxout_source_file (file, filename); + +#ifdef ASM_OUTPUT_SOURCE_LINE + ASM_OUTPUT_SOURCE_LINE (file, lineno); +#else + fprintf (file, "\t%s %d,0,%d\n", ASM_STABD_OP, N_SLINE, lineno); +#endif +} + +/* At the end of compilation, finish writing the symbol table. + Unless you define DBX_OUTPUT_MAIN_SOURCE_FILE_END, the default is + to do nothing. */ + +void +dbxout_finish (file, filename) + FILE *file; + char *filename; +{ +#ifdef DBX_OUTPUT_MAIN_SOURCE_FILE_END + DBX_OUTPUT_MAIN_SOURCE_FILE_END (file, filename); +#endif /* DBX_OUTPUT_MAIN_SOURCE_FILE_END */ +} + +/* Continue a symbol-description that gets too big. + End one symbol table entry with a double-backslash + and start a new one, eventually producing something like + .stabs "start......\\",code,0,value + .stabs "...rest",code,0,value */ + +static void +dbxout_continue () +{ +#ifdef DBX_CONTIN_CHAR + fprintf (asmfile, "%c", DBX_CONTIN_CHAR); +#else + fprintf (asmfile, "\\\\"); +#endif + dbxout_finish_symbol (NULL_TREE); + fprintf (asmfile, "%s \"", ASM_STABS_OP); + current_sym_nchars = 0; +} + +/* Subroutine of `dbxout_type'. Output the type fields of TYPE. + This must be a separate function because anonymous unions require + recursive calls. */ + +static void +dbxout_type_fields (type) + tree type; +{ + tree tem; + /* Output the name, type, position (in bits), size (in bits) of each + field. */ + for (tem = TYPE_FIELDS (type); tem; tem = TREE_CHAIN (tem)) + { + /* For nameless subunions and subrecords, treat their fields as ours. */ + if (DECL_NAME (tem) == NULL_TREE + && (TREE_CODE (TREE_TYPE (tem)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (tem)) == QUAL_UNION_TYPE + || TREE_CODE (TREE_TYPE (tem)) == RECORD_TYPE)) + dbxout_type_fields (TREE_TYPE (tem)); + /* Omit here local type decls until we know how to support them. */ + else if (TREE_CODE (tem) == TYPE_DECL) + continue; + /* Omit here the nameless fields that are used to skip bits. */ + else if (DECL_NAME (tem) != 0 && TREE_CODE (tem) != CONST_DECL) + { + /* Continue the line if necessary, + but not before the first field. */ + if (tem != TYPE_FIELDS (type)) + CONTIN; + + if (use_gnu_debug_info_extensions + && flag_minimal_debug + && TREE_CODE (tem) == FIELD_DECL + && DECL_VIRTUAL_P (tem) + && DECL_ASSEMBLER_NAME (tem)) + { + have_used_extensions = 1; + CHARS (3 + IDENTIFIER_LENGTH (DECL_NAME (TYPE_NAME (DECL_FCONTEXT (tem))))); + fputs (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (tem)), asmfile); + dbxout_type (DECL_FCONTEXT (tem), 0, 0); + fprintf (asmfile, ":"); + dbxout_type (TREE_TYPE (tem), 0, 0); + fprintf (asmfile, ",%d;", + TREE_INT_CST_LOW (DECL_FIELD_BITPOS (tem))); + continue; + } + + fprintf (asmfile, "%s:", IDENTIFIER_POINTER (DECL_NAME (tem))); + CHARS (2 + IDENTIFIER_LENGTH (DECL_NAME (tem))); + + if (use_gnu_debug_info_extensions + && (TREE_PRIVATE (tem) || TREE_PROTECTED (tem) + || TREE_CODE (tem) != FIELD_DECL)) + { + have_used_extensions = 1; + putc ('/', asmfile); + putc ((TREE_PRIVATE (tem) ? '0' + : TREE_PROTECTED (tem) ? '1' : '2'), + asmfile); + CHARS (2); + } + + dbxout_type ((TREE_CODE (tem) == FIELD_DECL + && DECL_BIT_FIELD_TYPE (tem)) + ? DECL_BIT_FIELD_TYPE (tem) + : TREE_TYPE (tem), 0, 0); + + if (TREE_CODE (tem) == VAR_DECL) + { + if (TREE_STATIC (tem) && use_gnu_debug_info_extensions) + { + char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (tem)); + have_used_extensions = 1; + fprintf (asmfile, ":%s;", name); + CHARS (strlen (name)); + } + else + { + /* If TEM is non-static, GDB won't understand it. */ + fprintf (asmfile, ",0,0;"); + } + } + else if (TREE_CODE (DECL_FIELD_BITPOS (tem)) == INTEGER_CST) + { + fprintf (asmfile, ",%d,%d;", + TREE_INT_CST_LOW (DECL_FIELD_BITPOS (tem)), + TREE_INT_CST_LOW (DECL_SIZE (tem))); + } + else + /* This has yet to be implemented. */ + abort (); + CHARS (23); + } + } +} + +/* Subroutine of `dbxout_type_methods'. Output debug info about the + method described DECL. DEBUG_NAME is an encoding of the method's + type signature. ??? We may be able to do without DEBUG_NAME altogether + now. */ + +static void +dbxout_type_method_1 (decl, debug_name) + tree decl; + char *debug_name; +{ + tree firstarg = TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (decl))); + char c1 = 'A', c2; + + if (TREE_CODE (TREE_TYPE (decl)) == FUNCTION_TYPE) + c2 = '?'; + else /* it's a METHOD_TYPE. */ + { + /* A for normal functions. + B for `const' member functions. + C for `volatile' member functions. + D for `const volatile' member functions. */ + if (TYPE_READONLY (TREE_TYPE (firstarg))) + c1 += 1; + if (TYPE_VOLATILE (TREE_TYPE (firstarg))) + c1 += 2; + + if (DECL_VINDEX (decl)) + c2 = '*'; + else + c2 = '.'; + } + + fprintf (asmfile, ":%s;%c%c%c", debug_name, + TREE_PRIVATE (decl) ? '0' : TREE_PROTECTED (decl) ? '1' : '2', c1, c2); + CHARS (IDENTIFIER_LENGTH (DECL_ASSEMBLER_NAME (decl)) + 6 + - (debug_name - IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); + if (DECL_VINDEX (decl)) + { + fprintf (asmfile, "%d;", + TREE_INT_CST_LOW (DECL_VINDEX (decl))); + dbxout_type (DECL_CONTEXT (decl), 0, 0); + fprintf (asmfile, ";"); + CHARS (8); + } +} + +/* Subroutine of `dbxout_type'. Output debug info about the methods defined + in TYPE. */ + +static void +dbxout_type_methods (type) + register tree type; +{ + /* C++: put out the method names and their parameter lists */ + tree methods = TYPE_METHODS (type); + tree type_encoding; + register tree fndecl; + register tree last; + char formatted_type_identifier_length[16]; + register int type_identifier_length; + + if (methods == NULL_TREE) + return; + + type_encoding = DECL_NAME (TYPE_NAME (type)); + + /* C++: Template classes break some assumptions made by this code about + the class names, constructor names, and encodings for assembler + label names. For now, disable output of dbx info for them. */ + { + char *ptr = IDENTIFIER_POINTER (type_encoding); + /* This should use index. (mrs) */ + while (*ptr && *ptr != '<') ptr++; + if (*ptr != 0) + { + static int warned; + if (!warned) + { + warned = 1; +#ifdef HAVE_TEMPLATES + if (warn_template_debugging) + warning ("dbx info for template class methods not yet supported"); +#endif + } + return; + } + } + + type_identifier_length = IDENTIFIER_LENGTH (type_encoding); + + sprintf(formatted_type_identifier_length, "%d", type_identifier_length); + + if (TREE_CODE (methods) == FUNCTION_DECL) + fndecl = methods; + else if (TREE_VEC_ELT (methods, 0) != NULL_TREE) + fndecl = TREE_VEC_ELT (methods, 0); + else + fndecl = TREE_VEC_ELT (methods, 1); + + while (fndecl) + { + tree name = DECL_NAME (fndecl); + int need_prefix = 1; + + /* Group together all the methods for the same operation. + These differ in the types of the arguments. */ + for (last = NULL_TREE; + fndecl && (last == NULL_TREE || DECL_NAME (fndecl) == DECL_NAME (last)); + fndecl = TREE_CHAIN (fndecl)) + /* Output the name of the field (after overloading), as + well as the name of the field before overloading, along + with its parameter list */ + { + /* This is the "mangled" name of the method. + It encodes the argument types. */ + char *debug_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (fndecl)); + int destructor = 0; + + CONTIN; + + last = fndecl; + + if (DECL_IGNORED_P (fndecl)) + continue; + + if (flag_minimal_debug) + { + /* Detect ordinary methods because their mangled names + start with the operation name. */ + if (!strncmp (IDENTIFIER_POINTER (name), debug_name, + IDENTIFIER_LENGTH (name))) + { + debug_name += IDENTIFIER_LENGTH (name); + if (debug_name[0] == '_' && debug_name[1] == '_') + { + char *method_name = debug_name + 2; + char *length_ptr = formatted_type_identifier_length; + /* Get past const and volatile qualifiers. */ + while (*method_name == 'C' || *method_name == 'V') + method_name++; + /* Skip digits for length of type_encoding. */ + while (*method_name == *length_ptr && *length_ptr) + length_ptr++, method_name++; + if (! strncmp (method_name, + IDENTIFIER_POINTER (type_encoding), + type_identifier_length)) + method_name += type_identifier_length; + debug_name = method_name; + } + } + /* Detect constructors by their style of name mangling. */ + else if (debug_name[0] == '_' && debug_name[1] == '_') + { + char *ctor_name = debug_name + 2; + char *length_ptr = formatted_type_identifier_length; + while (*ctor_name == 'C' || *ctor_name == 'V') + ctor_name++; + /* Skip digits for length of type_encoding. */ + while (*ctor_name == *length_ptr && *length_ptr) + length_ptr++, ctor_name++; + if (!strncmp (IDENTIFIER_POINTER (type_encoding), ctor_name, + type_identifier_length)) + debug_name = ctor_name + type_identifier_length; + } + /* The other alternative is a destructor. */ + else + destructor = 1; + + /* Output the operation name just once, for the first method + that we output. */ + if (need_prefix) + { + fprintf (asmfile, "%s::", IDENTIFIER_POINTER (name)); + CHARS (IDENTIFIER_LENGTH (name) + 2); + need_prefix = 0; + } + } + + dbxout_type (TREE_TYPE (fndecl), 0, destructor); + + dbxout_type_method_1 (fndecl, debug_name); + } + if (!need_prefix) + { + putc (';', asmfile); + CHARS (1); + } + } +} + +/* Emit a "range" type specification, which has the form: + "r;;;". + TYPE is an INTEGER_TYPE. */ + +static void +dbxout_range_type (type) + tree type; +{ + fprintf (asmfile, "r"); + if (TREE_TYPE (type) && TREE_CODE (TREE_TYPE(type)) != INTEGER_TYPE) + dbxout_type (TREE_TYPE (type), 0, 0); + else + { + /* This used to say `r1' and we used to take care + to make sure that `int' was type number 1. */ + fprintf (asmfile, "%d", TYPE_SYMTAB_ADDRESS (integer_type_node)); + } + if (TREE_CODE (TYPE_MIN_VALUE (type)) == INTEGER_CST) + fprintf (asmfile, ";%d", + TREE_INT_CST_LOW (TYPE_MIN_VALUE (type))); + else + fprintf (asmfile, ";0"); + if (TREE_CODE (TYPE_MAX_VALUE (type)) == INTEGER_CST) + fprintf (asmfile, ";%d;", + TREE_INT_CST_LOW (TYPE_MAX_VALUE (type))); + else + fprintf (asmfile, ";-1;"); +} + +/* Output a reference to a type. If the type has not yet been + described in the dbx output, output its definition now. + For a type already defined, just refer to its definition + using the type number. + + If FULL is nonzero, and the type has been described only with + a forward-reference, output the definition now. + If FULL is zero in this case, just refer to the forward-reference + using the number previously allocated. + + If SHOW_ARG_TYPES is nonzero, we output a description of the argument + types for a METHOD_TYPE. */ + +static void +dbxout_type (type, full, show_arg_types) + tree type; + int full; + int show_arg_types; +{ + register tree tem; + static int anonymous_type_number = 0; + + /* If there was an input error and we don't really have a type, + avoid crashing and write something that is at least valid + by assuming `int'. */ + if (type == error_mark_node) + type = integer_type_node; + else + { + type = TYPE_MAIN_VARIANT (type); + if (TYPE_NAME (type) + && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL + && DECL_IGNORED_P (TYPE_NAME (type))) + full = 0; + } + + if (TYPE_SYMTAB_ADDRESS (type) == 0) + { + /* Type has no dbx number assigned. Assign next available number. */ + TYPE_SYMTAB_ADDRESS (type) = next_type_number++; + + /* Make sure type vector is long enough to record about this type. */ + + if (next_type_number == typevec_len) + { + typevec = (enum typestatus *) xrealloc (typevec, typevec_len * 2 * sizeof typevec[0]); + bzero (typevec + typevec_len, typevec_len * sizeof typevec[0]); + typevec_len *= 2; + } + } + + /* Output the number of this type, to refer to it. */ + fprintf (asmfile, "%d", TYPE_SYMTAB_ADDRESS (type)); + CHARS (3); + +#ifdef DBX_TYPE_DEFINED + if (DBX_TYPE_DEFINED (type)) + return; +#endif + + /* If this type's definition has been output or is now being output, + that is all. */ + + switch (typevec[TYPE_SYMTAB_ADDRESS (type)]) + { + case TYPE_UNSEEN: + break; + case TYPE_XREF: + /* If we have already had a cross reference, + and either that's all we want or that's the best we could do, + don't repeat the cross reference. + Sun dbx crashes if we do. */ + if (! full || TYPE_SIZE (type) == 0 + /* No way in DBX fmt to describe a variable size. */ + || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) + return; + break; + case TYPE_DEFINED: + return; + } + +#ifdef DBX_NO_XREFS + /* For systems where dbx output does not allow the `=xsNAME:' syntax, + leave the type-number completely undefined rather than output + a cross-reference. */ + if (TREE_CODE (type) == RECORD_TYPE || TREE_CODE (type) == UNION_TYPE + || TREE_CODE (type) == QUAL_UNION_TYPE + || TREE_CODE (type) == ENUMERAL_TYPE) + + if ((TYPE_NAME (type) != 0 && !full) + || TYPE_SIZE (type) == 0) + { + typevec[TYPE_SYMTAB_ADDRESS (type)] = TYPE_XREF; + return; + } +#endif + + /* Output a definition now. */ + + fprintf (asmfile, "="); + CHARS (1); + + /* Mark it as defined, so that if it is self-referent + we will not get into an infinite recursion of definitions. */ + + typevec[TYPE_SYMTAB_ADDRESS (type)] = TYPE_DEFINED; + + switch (TREE_CODE (type)) + { + case VOID_TYPE: + case LANG_TYPE: + /* For a void type, just define it as itself; ie, "5=5". + This makes us consider it defined + without saying what it is. The debugger will make it + a void type when the reference is seen, and nothing will + ever override that default. */ + fprintf (asmfile, "%d", TYPE_SYMTAB_ADDRESS (type)); + CHARS (3); + break; + + case INTEGER_TYPE: + if (type == char_type_node && ! TREE_UNSIGNED (type)) + /* Output the type `char' as a subrange of itself! + I don't understand this definition, just copied it + from the output of pcc. + This used to use `r2' explicitly and we used to + take care to make sure that `char' was type number 2. */ + fprintf (asmfile, "r%d;0;127;", TYPE_SYMTAB_ADDRESS (type)); + else if (use_gnu_debug_info_extensions && TYPE_PRECISION (type) > BITS_PER_WORD) + { + /* This used to say `r1' and we used to take care + to make sure that `int' was type number 1. */ + fprintf (asmfile, "r%d;", TYPE_SYMTAB_ADDRESS (integer_type_node)); + print_int_cst_octal (TYPE_MIN_VALUE (type)); + fprintf (asmfile, ";"); + print_int_cst_octal (TYPE_MAX_VALUE (type)); + fprintf (asmfile, ";"); + } + else /* Output other integer types as subranges of `int'. */ + dbxout_range_type (type); + CHARS (25); + break; + + case REAL_TYPE: + /* This used to say `r1' and we used to take care + to make sure that `int' was type number 1. */ + fprintf (asmfile, "r%d;%d;0;", TYPE_SYMTAB_ADDRESS (integer_type_node), + int_size_in_bytes (type)); + CHARS (16); + break; + + case CHAR_TYPE: + /* Output the type `char' as a subrange of itself. + That is what pcc seems to do. */ + fprintf (asmfile, "r%d;0;%d;", TYPE_SYMTAB_ADDRESS (char_type_node), + TREE_UNSIGNED (type) ? 255 : 127); + CHARS (9); + break; + + case BOOLEAN_TYPE: /* Define as enumeral type (False, True) */ + fprintf (asmfile, "eFalse:0,True:1,;"); + CHARS (17); + break; + + case FILE_TYPE: + putc ('d', asmfile); + CHARS (1); + dbxout_type (TREE_TYPE (type), 0, 0); + break; + + case COMPLEX_TYPE: + /* Differs from the REAL_TYPE by its new data type number */ + + if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE) + { + fprintf (asmfile, "r%d;%d;0;", + TYPE_SYMTAB_ADDRESS (type), + int_size_in_bytes (TREE_TYPE (type))); + CHARS (15); /* The number is probably incorrect here. */ + } + else + { + /* Output a complex integer type as a structure, + pending some other way to do it. */ + fprintf (asmfile, "s%d", int_size_in_bytes (type)); + + fprintf (asmfile, "real:"); + CHARS (10); + dbxout_type (TREE_TYPE (type), 0, 0); + fprintf (asmfile, ",%d,%d;", + 0, TYPE_PRECISION (TREE_TYPE (type))); + CHARS (8); + fprintf (asmfile, "imag:"); + CHARS (5); + dbxout_type (TREE_TYPE (type), 0, 0); + fprintf (asmfile, ",%d,%d;;", + TYPE_PRECISION (TREE_TYPE (type)), + TYPE_PRECISION (TREE_TYPE (type))); + CHARS (9); + } + break; + + case SET_TYPE: + putc ('S', asmfile); + CHARS (1); + dbxout_type (TREE_TYPE (type), 0, 0); + break; + + case ARRAY_TYPE: + /* Output "a" followed by a range type definition + for the index type of the array + followed by a reference to the target-type. + ar1;0;N;M for a C array of type M and size N+1. */ + tem = TYPE_DOMAIN (type); + if (tem == NULL) + fprintf (asmfile, "ar%d;0;-1;", + TYPE_SYMTAB_ADDRESS (integer_type_node)); + else + { + fprintf (asmfile, "a"); + dbxout_range_type (tem); + } + CHARS (17); + dbxout_type (TREE_TYPE (type), 0, 0); + break; + + case RECORD_TYPE: + case UNION_TYPE: + case QUAL_UNION_TYPE: + { + int i, n_baseclasses = 0; + + if (TYPE_BINFO (type) != 0 && TYPE_BINFO_BASETYPES (type) != 0) + n_baseclasses = TREE_VEC_LENGTH (TYPE_BINFO_BASETYPES (type)); + + /* Output a structure type. */ + if ((TYPE_NAME (type) != 0 + /* Long ago, Tiemann said this creates output that "confuses GDB". + In April 93, mrs@cygnus.com said there is no such problem. + The type decls made automatically by struct specifiers + are marked with DECL_IGNORED_P in C++. */ +#if 0 /* This creates output for anonymous classes which confuses GDB. */ + && ! (TREE_CODE (TYPE_NAME (type)) == TYPE_DECL + && DECL_IGNORED_P (TYPE_NAME (type))) +#endif + && !full) + || TYPE_SIZE (type) == 0 + /* No way in DBX fmt to describe a variable size. */ + || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) + { + /* If the type is just a cross reference, output one + and mark the type as partially described. + If it later becomes defined, we will output + its real definition. + If the type has a name, don't nest its definition within + another type's definition; instead, output an xref + and let the definition come when the name is defined. */ + fprintf (asmfile, (TREE_CODE (type) == RECORD_TYPE) ? "xs" : "xu"); + CHARS (3); +#if 0 /* This assertion is legitimately false in C++. */ + /* We shouldn't be outputting a reference to a type before its + definition unless the type has a tag name. + A typedef name without a tag name should be impossible. */ + if (TREE_CODE (TYPE_NAME (type)) != IDENTIFIER_NODE) + abort (); +#endif + if (TYPE_NAME (type) != 0) + dbxout_type_name (type); + else + fprintf (asmfile, "$$%d", anonymous_type_number++); + fprintf (asmfile, ":"); + typevec[TYPE_SYMTAB_ADDRESS (type)] = TYPE_XREF; + break; + } + + /* Identify record or union, and print its size. */ + fprintf (asmfile, (TREE_CODE (type) == RECORD_TYPE) ? "s%d" : "u%d", + int_size_in_bytes (type)); + + if (use_gnu_debug_info_extensions) + { + if (n_baseclasses) + { + have_used_extensions = 1; + fprintf (asmfile, "!%d,", n_baseclasses); + CHARS (8); + } + } + for (i = 0; i < n_baseclasses; i++) + { + tree child = TREE_VEC_ELT (BINFO_BASETYPES (TYPE_BINFO (type)), i); + if (use_gnu_debug_info_extensions) + { + have_used_extensions = 1; + putc (TREE_VIA_VIRTUAL (child) ? '1' + : '0', + asmfile); + putc (TREE_VIA_PUBLIC (child) ? '2' + : '0', + asmfile); + fprintf (asmfile, "%d,", + TREE_INT_CST_LOW (BINFO_OFFSET (child)) * BITS_PER_UNIT); + CHARS (15); + dbxout_type (BINFO_TYPE (child), 0, 0); + putc (';', asmfile); + } + else + { + /* Print out the base class information with fields + which have the same names at the types they hold. */ + dbxout_type_name (BINFO_TYPE (child)); + putc (':', asmfile); + dbxout_type (BINFO_TYPE (child), full, 0); + fprintf (asmfile, ",%d,%d;", + TREE_INT_CST_LOW (BINFO_OFFSET (child)) * BITS_PER_UNIT, + TREE_INT_CST_LOW (DECL_SIZE (TYPE_NAME (BINFO_TYPE (child)))) * BITS_PER_UNIT); + CHARS (20); + } + } + } + + CHARS (11); + + /* Write out the field declarations. */ + dbxout_type_fields (type); + if (use_gnu_debug_info_extensions && TYPE_METHODS (type) != NULL_TREE) + { + have_used_extensions = 1; + dbxout_type_methods (type); + } + putc (';', asmfile); + + if (use_gnu_debug_info_extensions && TREE_CODE (type) == RECORD_TYPE + /* Avoid the ~ if we don't really need it--it confuses dbx. */ + && TYPE_VFIELD (type)) + { + have_used_extensions = 1; + + /* Tell GDB+ that it may keep reading. */ + putc ('~', asmfile); + + /* We need to write out info about what field this class + uses as its "main" vtable pointer field, because if this + field is inherited from a base class, GDB cannot necessarily + figure out which field it's using in time. */ + if (TYPE_VFIELD (type)) + { + putc ('%', asmfile); + dbxout_type (DECL_FCONTEXT (TYPE_VFIELD (type)), 0, 0); + } + putc (';', asmfile); + CHARS (3); + } + break; + + case ENUMERAL_TYPE: + if ((TYPE_NAME (type) != 0 && !full + && (TREE_CODE (TYPE_NAME (type)) == TYPE_DECL + && ! DECL_IGNORED_P (TYPE_NAME (type)))) + || TYPE_SIZE (type) == 0) + { + fprintf (asmfile, "xe"); + CHARS (3); + dbxout_type_name (type); + typevec[TYPE_SYMTAB_ADDRESS (type)] = TYPE_XREF; + fprintf (asmfile, ":"); + return; + } +#ifdef DBX_OUTPUT_ENUM + DBX_OUTPUT_ENUM (asmfile, type); +#else + putc ('e', asmfile); + CHARS (1); + for (tem = TYPE_VALUES (type); tem; tem = TREE_CHAIN (tem)) + { + fprintf (asmfile, "%s:%d,", IDENTIFIER_POINTER (TREE_PURPOSE (tem)), + TREE_INT_CST_LOW (TREE_VALUE (tem))); + CHARS (11 + IDENTIFIER_LENGTH (TREE_PURPOSE (tem))); + if (TREE_CHAIN (tem) != 0) + CONTIN; + } + putc (';', asmfile); + CHARS (1); +#endif + break; + + case POINTER_TYPE: + putc ('*', asmfile); + CHARS (1); + dbxout_type (TREE_TYPE (type), 0, 0); + break; + + case METHOD_TYPE: + if (use_gnu_debug_info_extensions) + { + have_used_extensions = 1; + putc ('#', asmfile); + CHARS (1); + if (flag_minimal_debug && !show_arg_types) + { + /* Normally, just output the return type. + The argument types are encoded in the method name. */ + putc ('#', asmfile); + dbxout_type (TREE_TYPE (type), 0, 0); + putc (';', asmfile); + CHARS (1); + } + else + { + /* When outputting destructors, we need to write + the argument types out longhand. */ + dbxout_type (TYPE_METHOD_BASETYPE (type), 0, 0); + putc (',', asmfile); + CHARS (1); + dbxout_type (TREE_TYPE (type), 0, 0); + dbxout_args (TYPE_ARG_TYPES (type)); + putc (';', asmfile); + CHARS (1); + } + } + else + { + /* Treat it as a function type. */ + dbxout_type (TREE_TYPE (type), 0, 0); + } + break; + + case OFFSET_TYPE: + if (use_gnu_debug_info_extensions) + { + have_used_extensions = 1; + putc ('@', asmfile); + CHARS (1); + dbxout_type (TYPE_OFFSET_BASETYPE (type), 0, 0); + putc (',', asmfile); + CHARS (1); + dbxout_type (TREE_TYPE (type), 0, 0); + } + else + { + /* Should print as an int, because it is really + just an offset. */ + dbxout_type (integer_type_node, 0, 0); + } + break; + + case REFERENCE_TYPE: + if (use_gnu_debug_info_extensions) + have_used_extensions = 1; + putc (use_gnu_debug_info_extensions ? '&' : '*', asmfile); + CHARS (1); + dbxout_type (TREE_TYPE (type), 0, 0); + break; + + case FUNCTION_TYPE: + putc ('f', asmfile); + CHARS (1); + dbxout_type (TREE_TYPE (type), 0, 0); + break; + + default: + abort (); + } +} + +/* Print the value of integer constant C, in octal, + handling double precision. */ + +static void +print_int_cst_octal (c) + tree c; +{ + unsigned HOST_WIDE_INT high = TREE_INT_CST_HIGH (c); + unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (c); + int excess = (3 - (HOST_BITS_PER_WIDE_INT % 3)); + + fprintf (asmfile, "0"); + + if (excess == 3) + { + print_octal (high, HOST_BITS_PER_WIDE_INT / 3); + print_octal (low, HOST_BITS_PER_WIDE_INT / 3); + } + else + { + unsigned HOST_WIDE_INT beg = high >> excess; + unsigned HOST_WIDE_INT middle + = ((high & (((HOST_WIDE_INT) 1 << excess) - 1)) << (3 - excess) + | (low >> (HOST_BITS_PER_WIDE_INT / 3 * 3))); + unsigned HOST_WIDE_INT end + = low & (((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 3 * 3)) - 1); + fprintf (asmfile, "%o%01o", beg, middle); + print_octal (end, HOST_BITS_PER_WIDE_INT / 3); + } +} + +static void +print_octal (value, digits) + unsigned HOST_WIDE_INT value; + int digits; +{ + int i; + + for (i = digits - 1; i >= 0; i--) + fprintf (asmfile, "%01o", ((value >> (3 * i)) & 7)); +} + +/* Output the name of type TYPE, with no punctuation. + Such names can be set up either by typedef declarations + or by struct, enum and union tags. */ + +static void +dbxout_type_name (type) + register tree type; +{ + tree t; + if (TYPE_NAME (type) == 0) + abort (); + if (TREE_CODE (TYPE_NAME (type)) == IDENTIFIER_NODE) + { + t = TYPE_NAME (type); + } + else if (TREE_CODE (TYPE_NAME (type)) == TYPE_DECL) + { + t = DECL_NAME (TYPE_NAME (type)); + } + else + abort (); + + fprintf (asmfile, "%s", IDENTIFIER_POINTER (t)); + CHARS (IDENTIFIER_LENGTH (t)); +} + +/* Output a .stabs for the symbol defined by DECL, + which must be a ..._DECL node in the normal namespace. + It may be a CONST_DECL, a FUNCTION_DECL, a PARM_DECL or a VAR_DECL. + LOCAL is nonzero if the scope is less than the entire file. */ + +void +dbxout_symbol (decl, local) + tree decl; + int local; +{ + int letter = 0; + tree type = TREE_TYPE (decl); + tree context = NULL_TREE; + int regno = -1; + + /* Cast avoids warning in old compilers. */ + current_sym_code = (STAB_CODE_TYPE) 0; + current_sym_value = 0; + current_sym_addr = 0; + + /* Ignore nameless syms, but don't ignore type tags. */ + + if ((DECL_NAME (decl) == 0 && TREE_CODE (decl) != TYPE_DECL) + || DECL_IGNORED_P (decl)) + return; + + dbxout_prepare_symbol (decl); + + /* The output will always start with the symbol name, + so always count that in the length-output-so-far. */ + + if (DECL_NAME (decl) != 0) + current_sym_nchars = 2 + IDENTIFIER_LENGTH (DECL_NAME (decl)); + + switch (TREE_CODE (decl)) + { + case CONST_DECL: + /* Enum values are defined by defining the enum type. */ + break; + + case FUNCTION_DECL: + if (DECL_RTL (decl) == 0) + return; + if (DECL_EXTERNAL (decl)) + break; + /* Don't mention a nested function under its parent. */ + context = decl_function_context (decl); + if (context == current_function_decl) + break; + if (GET_CODE (DECL_RTL (decl)) != MEM + || GET_CODE (XEXP (DECL_RTL (decl), 0)) != SYMBOL_REF) + break; + FORCE_TEXT; + + fprintf (asmfile, "%s \"%s:%c", ASM_STABS_OP, + IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), + TREE_PUBLIC (decl) ? 'F' : 'f'); + + current_sym_code = N_FUN; + current_sym_addr = XEXP (DECL_RTL (decl), 0); + + if (TREE_TYPE (type)) + dbxout_type (TREE_TYPE (type), 0, 0); + else + dbxout_type (void_type_node, 0, 0); + + /* For a nested function, when that function is compiled, + mention the containing function name + as well as (since dbx wants it) our own assembler-name. */ + if (context != 0) + fprintf (asmfile, ",%s,%s", + IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), + IDENTIFIER_POINTER (DECL_NAME (context))); + + dbxout_finish_symbol (decl); + break; + + case TYPE_DECL: +#if 0 + /* This seems all wrong. Outputting most kinds of types gives no name + at all. A true definition gives no name; a cross-ref for a + structure can give the tag name, but not a type name. + It seems that no typedef name is defined by outputting a type. */ + + /* If this typedef name was defined by outputting the type, + don't duplicate it. */ + if (typevec[TYPE_SYMTAB_ADDRESS (type)] == TYPE_DEFINED + && TYPE_NAME (TREE_TYPE (decl)) == decl) + return; +#endif + /* Don't output the same typedef twice. + And don't output what language-specific stuff doesn't want output. */ + if (TREE_ASM_WRITTEN (decl) || DECL_IGNORED_P (decl)) + return; + + FORCE_TEXT; + + { + int tag_needed = 1; + int did_output = 0; + + if (DECL_NAME (decl)) + { + /* Nonzero means we must output a tag as well as a typedef. */ + tag_needed = 0; + + /* Handle the case of a C++ structure or union + where the TYPE_NAME is a TYPE_DECL + which gives both a typedef name and a tag. */ + /* dbx requires the tag first and the typedef second. */ + if ((TREE_CODE (type) == RECORD_TYPE + || TREE_CODE (type) == UNION_TYPE + || TREE_CODE (type) == QUAL_UNION_TYPE) + && TYPE_NAME (type) == decl + && !(use_gnu_debug_info_extensions && have_used_extensions) + && !TREE_ASM_WRITTEN (TYPE_NAME (type)) + /* Distinguish the implicit typedefs of C++ + from explicit ones that might be found in C. */ + && DECL_SOURCE_LINE (decl) == 0) + { + tree name = TYPE_NAME (type); + if (TREE_CODE (name) == TYPE_DECL) + name = DECL_NAME (name); + + current_sym_code = DBX_TYPE_DECL_STABS_CODE; + current_sym_value = 0; + current_sym_addr = 0; + current_sym_nchars = 2 + IDENTIFIER_LENGTH (name); + + fprintf (asmfile, "%s \"%s:T", ASM_STABS_OP, + IDENTIFIER_POINTER (name)); + dbxout_type (type, 1, 0); + dbxout_finish_symbol (NULL_TREE); + } + + /* Output typedef name. */ + fprintf (asmfile, "%s \"%s:", ASM_STABS_OP, + IDENTIFIER_POINTER (DECL_NAME (decl))); + + /* Short cut way to output a tag also. */ + if ((TREE_CODE (type) == RECORD_TYPE + || TREE_CODE (type) == UNION_TYPE + || TREE_CODE (type) == QUAL_UNION_TYPE) + && TYPE_NAME (type) == decl) + { + if (use_gnu_debug_info_extensions && have_used_extensions) + { + putc ('T', asmfile); + TREE_ASM_WRITTEN (TYPE_NAME (type)) = 1; + } +#if 0 /* Now we generate the tag for this case up above. */ + else + tag_needed = 1; +#endif + } + + putc ('t', asmfile); + current_sym_code = DBX_TYPE_DECL_STABS_CODE; + + dbxout_type (type, 1, 0); + dbxout_finish_symbol (decl); + did_output = 1; + } + + /* Don't output a tag if this is an incomplete type (TYPE_SIZE is + zero). This prevents the sun4 Sun OS 4.x dbx from crashing. */ + + if (tag_needed && TYPE_NAME (type) != 0 && TYPE_SIZE (type) != 0 + && !TREE_ASM_WRITTEN (TYPE_NAME (type))) + { + /* For a TYPE_DECL with no name, but the type has a name, + output a tag. + This is what represents `struct foo' with no typedef. */ + /* In C++, the name of a type is the corresponding typedef. + In C, it is an IDENTIFIER_NODE. */ + tree name = TYPE_NAME (type); + if (TREE_CODE (name) == TYPE_DECL) + name = DECL_NAME (name); + + current_sym_code = DBX_TYPE_DECL_STABS_CODE; + current_sym_value = 0; + current_sym_addr = 0; + current_sym_nchars = 2 + IDENTIFIER_LENGTH (name); + + fprintf (asmfile, "%s \"%s:T", ASM_STABS_OP, + IDENTIFIER_POINTER (name)); + dbxout_type (type, 1, 0); + dbxout_finish_symbol (NULL_TREE); + did_output = 1; + } + + /* If an enum type has no name, it cannot be referred to, + but we must output it anyway, since the enumeration constants + can be referred to. */ + if (!did_output && TREE_CODE (type) == ENUMERAL_TYPE) + { + current_sym_code = DBX_TYPE_DECL_STABS_CODE; + current_sym_value = 0; + current_sym_addr = 0; + current_sym_nchars = 2; + + /* Some debuggers fail when given NULL names, so give this a + harmless name of ` '. */ + fprintf (asmfile, "%s \" :T", ASM_STABS_OP); + dbxout_type (type, 1, 0); + dbxout_finish_symbol (NULL_TREE); + } + + /* Prevent duplicate output of a typedef. */ + TREE_ASM_WRITTEN (decl) = 1; + break; + } + + case PARM_DECL: + /* Parm decls go in their own separate chains + and are output by dbxout_reg_parms and dbxout_parms. */ + abort (); + + case RESULT_DECL: + /* Named return value, treat like a VAR_DECL. */ + case VAR_DECL: + if (DECL_RTL (decl) == 0) + return; + /* Don't mention a variable that is external. + Let the file that defines it describe it. */ + if (DECL_EXTERNAL (decl)) + break; + + /* If the variable is really a constant + and not written in memory, inform the debugger. */ + if (TREE_STATIC (decl) && TREE_READONLY (decl) + && DECL_INITIAL (decl) != 0 + && ! TREE_ASM_WRITTEN (decl) + && (DECL_FIELD_CONTEXT (decl) == NULL_TREE + || TREE_CODE (DECL_FIELD_CONTEXT (decl)) == BLOCK)) + { + if (TREE_PUBLIC (decl) == 0) + { + /* The sun4 assembler does not grok this. */ + char *name = IDENTIFIER_POINTER (DECL_NAME (decl)); + if (TREE_CODE (TREE_TYPE (decl)) == INTEGER_TYPE + || TREE_CODE (TREE_TYPE (decl)) == ENUMERAL_TYPE) + { + HOST_WIDE_INT ival = TREE_INT_CST_LOW (DECL_INITIAL (decl)); +#ifdef DBX_OUTPUT_CONSTANT_SYMBOL + DBX_OUTPUT_CONSTANT_SYMBOL (asmfile, name, ival); +#else + fprintf (asmfile, "%s \"%s:c=i%d\",0x%x,0,0,0\n", + ASM_STABS_OP, name, ival, N_LSYM); +#endif + return; + } + else if (TREE_CODE (TREE_TYPE (decl)) == REAL_TYPE) + { + /* don't know how to do this yet. */ + } + break; + } + /* else it is something we handle like a normal variable. */ + } + + DECL_RTL (decl) = eliminate_regs (DECL_RTL (decl), 0, NULL_RTX); +#ifdef LEAF_REG_REMAP + if (leaf_function) + leaf_renumber_regs_insn (DECL_RTL (decl)); +#endif + + /* Don't mention a variable at all + if it was completely optimized into nothingness. + + If DECL was from an inline function, then it's rtl + is not identically the rtl that was used in this + particular compilation. */ + if (GET_CODE (DECL_RTL (decl)) == REG) + { + regno = REGNO (DECL_RTL (decl)); + if (regno >= FIRST_PSEUDO_REGISTER) + return; + } + else if (GET_CODE (DECL_RTL (decl)) == SUBREG) + { + rtx value = DECL_RTL (decl); + int offset = 0; + while (GET_CODE (value) == SUBREG) + { + offset += SUBREG_WORD (value); + value = SUBREG_REG (value); + } + if (GET_CODE (value) == REG) + { + regno = REGNO (value); + if (regno >= FIRST_PSEUDO_REGISTER) + return; + regno += offset; + } + alter_subreg (DECL_RTL (decl)); + } + + /* The kind-of-variable letter depends on where + the variable is and on the scope of its name: + G and N_GSYM for static storage and global scope, + S for static storage and file scope, + V for static storage and local scope, + for those two, use N_LCSYM if data is in bss segment, + N_STSYM if in data segment, N_FUN otherwise. + (We used N_FUN originally, then changed to N_STSYM + to please GDB. However, it seems that confused ld. + Now GDB has been fixed to like N_FUN, says Kingdon.) + no letter at all, and N_LSYM, for auto variable, + r and N_RSYM for register variable. */ + + if (GET_CODE (DECL_RTL (decl)) == MEM + && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF) + { + if (TREE_PUBLIC (decl)) + { + letter = 'G'; + current_sym_code = N_GSYM; + } + else + { + current_sym_addr = XEXP (DECL_RTL (decl), 0); + + letter = decl_function_context (decl) ? 'V' : 'S'; + + if (!DECL_INITIAL (decl)) + current_sym_code = N_LCSYM; + else if (TREE_READONLY (decl) && ! TREE_THIS_VOLATILE (decl)) + /* This is not quite right, but it's the closest + of all the codes that Unix defines. */ + current_sym_code = DBX_STATIC_CONST_VAR_CODE; + else + { +/* Ultrix `as' seems to need this. */ +#ifdef DBX_STATIC_STAB_DATA_SECTION + data_section (); +#endif + current_sym_code = N_STSYM; + } + } + } + else if (regno >= 0) + { + letter = 'r'; + current_sym_code = N_RSYM; + current_sym_value = DBX_REGISTER_NUMBER (regno); + } + else if (GET_CODE (DECL_RTL (decl)) == MEM + && (GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM + || (GET_CODE (XEXP (DECL_RTL (decl), 0)) == REG + && REGNO (XEXP (DECL_RTL (decl), 0)) != FRAME_POINTER_REGNUM))) + /* If the value is indirect by memory or by a register + that isn't the frame pointer + then it means the object is variable-sized and address through + that register or stack slot. DBX has no way to represent this + so all we can do is output the variable as a pointer. + If it's not a parameter, ignore it. + (VAR_DECLs like this can be made by integrate.c.) */ + { + if (GET_CODE (XEXP (DECL_RTL (decl), 0)) == REG) + { + letter = 'r'; + current_sym_code = N_RSYM; + current_sym_value = DBX_REGISTER_NUMBER (REGNO (XEXP (DECL_RTL (decl), 0))); + } + else + { + current_sym_code = N_LSYM; + /* DECL_RTL looks like (MEM (MEM (PLUS (REG...) (CONST_INT...)))). + We want the value of that CONST_INT. */ + current_sym_value + = DEBUGGER_AUTO_OFFSET (XEXP (XEXP (DECL_RTL (decl), 0), 0)); + } + + /* Effectively do build_pointer_type, but don't cache this type, + since it might be temporary whereas the type it points to + might have been saved for inlining. */ + /* Don't use REFERENCE_TYPE because dbx can't handle that. */ + type = make_node (POINTER_TYPE); + TREE_TYPE (type) = TREE_TYPE (decl); + } + else if (GET_CODE (DECL_RTL (decl)) == MEM + && GET_CODE (XEXP (DECL_RTL (decl), 0)) == REG) + { + current_sym_code = N_LSYM; + current_sym_value = DEBUGGER_AUTO_OFFSET (XEXP (DECL_RTL (decl), 0)); + } + else if (GET_CODE (DECL_RTL (decl)) == MEM + && GET_CODE (XEXP (DECL_RTL (decl), 0)) == PLUS + && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 1)) == CONST_INT) + { + current_sym_code = N_LSYM; + /* DECL_RTL looks like (MEM (PLUS (REG...) (CONST_INT...))) + We want the value of that CONST_INT. */ + current_sym_value = DEBUGGER_AUTO_OFFSET (XEXP (DECL_RTL (decl), 0)); + } + else if (GET_CODE (DECL_RTL (decl)) == MEM + && GET_CODE (XEXP (DECL_RTL (decl), 0)) == CONST) + { + /* Handle an obscure case which can arise when optimizing and + when there are few available registers. (This is *always* + the case for i386/i486 targets). The DECL_RTL looks like + (MEM (CONST ...)) even though this variable is a local `auto' + or a local `register' variable. In effect, what has happened + is that the reload pass has seen that all assignments and + references for one such a local variable can be replaced by + equivalent assignments and references to some static storage + variable, thereby avoiding the need for a register. In such + cases we're forced to lie to debuggers and tell them that + this variable was itself `static'. */ + current_sym_code = N_LCSYM; + letter = 'V'; + current_sym_addr = XEXP (XEXP (DECL_RTL (decl), 0), 0); + } + else + /* Address might be a MEM, when DECL is a variable-sized object. + Or it might be const0_rtx, meaning previous passes + want us to ignore this variable. */ + break; + + /* Ok, start a symtab entry and output the variable name. */ + FORCE_TEXT; + +#ifdef DBX_STATIC_BLOCK_START + DBX_STATIC_BLOCK_START (asmfile, current_sym_code); +#endif + + /* One slight hitch: if this is a VAR_DECL which is a static + class member, we must put out the mangled name instead of the + DECL_NAME. */ + { + char *name; + /* Note also that static member (variable) names DO NOT begin + with underscores in .stabs directives. */ + if (DECL_LANG_SPECIFIC (decl)) + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); + else + name = IDENTIFIER_POINTER (DECL_NAME (decl)); + fprintf (asmfile, "%s \"%s:", ASM_STABS_OP, name); + } + if (letter) putc (letter, asmfile); + dbxout_type (type, 0, 0); + dbxout_finish_symbol (decl); + +#ifdef DBX_STATIC_BLOCK_END + DBX_STATIC_BLOCK_END (asmfile, current_sym_code); +#endif + break; + } +} + +static void +dbxout_prepare_symbol (decl) + tree decl; +{ +#ifdef WINNING_GDB + char *filename = DECL_SOURCE_FILE (decl); + + dbxout_source_file (asmfile, filename); +#endif +} + +static void +dbxout_finish_symbol (sym) + tree sym; +{ +#ifdef DBX_FINISH_SYMBOL + DBX_FINISH_SYMBOL (sym); +#else + int line = 0; + if (use_gnu_debug_info_extensions && sym != 0) + line = DECL_SOURCE_LINE (sym); + + fprintf (asmfile, "\",%d,0,%d,", current_sym_code, line); + if (current_sym_addr) + output_addr_const (asmfile, current_sym_addr); + else + fprintf (asmfile, "%d", current_sym_value); + putc ('\n', asmfile); +#endif +} + +/* Output definitions of all the decls in a chain. */ + +void +dbxout_syms (syms) + tree syms; +{ + while (syms) + { + dbxout_symbol (syms, 1); + syms = TREE_CHAIN (syms); + } +} + +/* The following two functions output definitions of function parameters. + Each parameter gets a definition locating it in the parameter list. + Each parameter that is a register variable gets a second definition + locating it in the register. + + Printing or argument lists in gdb uses the definitions that + locate in the parameter list. But reference to the variable in + expressions uses preferentially the definition as a register. */ + +/* Output definitions, referring to storage in the parmlist, + of all the parms in PARMS, which is a chain of PARM_DECL nodes. */ + +void +dbxout_parms (parms) + tree parms; +{ + for (; parms; parms = TREE_CHAIN (parms)) + if (DECL_NAME (parms) && TREE_TYPE (parms) != error_mark_node) + { + dbxout_prepare_symbol (parms); + + /* Perform any necessary register eliminations on the parameter's rtl, + so that the debugging output will be accurate. */ + DECL_INCOMING_RTL (parms) + = eliminate_regs (DECL_INCOMING_RTL (parms), 0, NULL_RTX); + DECL_RTL (parms) = eliminate_regs (DECL_RTL (parms), 0, NULL_RTX); +#ifdef LEAF_REG_REMAP + if (leaf_function) + { + leaf_renumber_regs_insn (DECL_INCOMING_RTL (parms)); + leaf_renumber_regs_insn (DECL_RTL (parms)); + } +#endif + + if (PARM_PASSED_IN_MEMORY (parms)) + { + rtx addr = XEXP (DECL_INCOMING_RTL (parms), 0); + + /* ??? Here we assume that the parm address is indexed + off the frame pointer or arg pointer. + If that is not true, we produce meaningless results, + but do not crash. */ + if (GET_CODE (addr) == PLUS + && GET_CODE (XEXP (addr, 1)) == CONST_INT) + current_sym_value = INTVAL (XEXP (addr, 1)); + else + current_sym_value = 0; + + current_sym_code = N_PSYM; + current_sym_addr = 0; + + FORCE_TEXT; + if (DECL_NAME (parms)) + { + current_sym_nchars = 2 + IDENTIFIER_LENGTH (DECL_NAME (parms)); + + fprintf (asmfile, "%s \"%s:%c", ASM_STABS_OP, + IDENTIFIER_POINTER (DECL_NAME (parms)), + DBX_MEMPARM_STABS_LETTER); + } + else + { + current_sym_nchars = 8; + fprintf (asmfile, "%s \"(anon):%c", ASM_STABS_OP, + DBX_MEMPARM_STABS_LETTER); + } + + if (GET_CODE (DECL_RTL (parms)) == REG + && REGNO (DECL_RTL (parms)) >= 0 + && REGNO (DECL_RTL (parms)) < FIRST_PSEUDO_REGISTER) + dbxout_type (DECL_ARG_TYPE (parms), 0, 0); + else + { + int original_value = current_sym_value; + + /* This is the case where the parm is passed as an int or double + and it is converted to a char, short or float and stored back + in the parmlist. In this case, describe the parm + with the variable's declared type, and adjust the address + if the least significant bytes (which we are using) are not + the first ones. */ +#if BYTES_BIG_ENDIAN + if (TREE_TYPE (parms) != DECL_ARG_TYPE (parms)) + current_sym_value += (GET_MODE_SIZE (TYPE_MODE (DECL_ARG_TYPE (parms))) + - GET_MODE_SIZE (GET_MODE (DECL_RTL (parms)))); +#endif + + if (GET_CODE (DECL_RTL (parms)) == MEM + && GET_CODE (XEXP (DECL_RTL (parms), 0)) == PLUS + && GET_CODE (XEXP (XEXP (DECL_RTL (parms), 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (DECL_RTL (parms), 0), 1)) == current_sym_value) + dbxout_type (TREE_TYPE (parms), 0, 0); + else + { + current_sym_value = original_value; + dbxout_type (DECL_ARG_TYPE (parms), 0, 0); + } + } + current_sym_value = DEBUGGER_ARG_OFFSET (current_sym_value, addr); + dbxout_finish_symbol (parms); + } + else if (GET_CODE (DECL_RTL (parms)) == REG) + { + rtx best_rtl; + char regparm_letter; + /* Parm passed in registers and lives in registers or nowhere. */ + + current_sym_code = DBX_REGPARM_STABS_CODE; + regparm_letter = DBX_REGPARM_STABS_LETTER; + current_sym_addr = 0; + + /* If parm lives in a register, use that register; + pretend the parm was passed there. It would be more consistent + to describe the register where the parm was passed, + but in practice that register usually holds something else. */ + if (REGNO (DECL_RTL (parms)) >= 0 + && REGNO (DECL_RTL (parms)) < FIRST_PSEUDO_REGISTER) + best_rtl = DECL_RTL (parms); + /* If the parm lives nowhere, + use the register where it was passed. */ + else + best_rtl = DECL_INCOMING_RTL (parms); + current_sym_value = DBX_REGISTER_NUMBER (REGNO (best_rtl)); + + FORCE_TEXT; + if (DECL_NAME (parms)) + { + current_sym_nchars = 2 + IDENTIFIER_LENGTH (DECL_NAME (parms)); + fprintf (asmfile, "%s \"%s:%c", ASM_STABS_OP, + IDENTIFIER_POINTER (DECL_NAME (parms)), + regparm_letter); + } + else + { + current_sym_nchars = 8; + fprintf (asmfile, "%s \"(anon):%c", ASM_STABS_OP, + regparm_letter); + } + + dbxout_type (DECL_ARG_TYPE (parms), 0, 0); + dbxout_finish_symbol (parms); + } + else if (GET_CODE (DECL_RTL (parms)) == MEM + && GET_CODE (XEXP (DECL_RTL (parms), 0)) == REG) +/* && rtx_equal_p (XEXP (DECL_RTL (parms), 0), + DECL_INCOMING_RTL (parms))) */ + { + /* Parm was passed via invisible reference. + That is, its address was passed in a register. + Output it as if it lived in that register. + The debugger will know from the type + that it was actually passed by invisible reference. */ + + char regparm_letter; + /* Parm passed in registers and lives in registers or nowhere. */ + + current_sym_code = DBX_REGPARM_STABS_CODE; + regparm_letter = DBX_REGPARM_STABS_LETTER; + + /* DECL_RTL looks like (MEM (REG...). Get the register number. */ + current_sym_value = REGNO (XEXP (DECL_RTL (parms), 0)); + current_sym_addr = 0; + + FORCE_TEXT; + if (DECL_NAME (parms)) + { + current_sym_nchars = 2 + strlen (IDENTIFIER_POINTER (DECL_NAME (parms))); + + fprintf (asmfile, "%s \"%s:%c", ASM_STABS_OP, + IDENTIFIER_POINTER (DECL_NAME (parms)), + DBX_REGPARM_STABS_LETTER); + } + else + { + current_sym_nchars = 8; + fprintf (asmfile, "%s \"(anon):%c", ASM_STABS_OP, + DBX_REGPARM_STABS_LETTER); + } + + dbxout_type (TREE_TYPE (parms), 0, 0); + dbxout_finish_symbol (parms); + } + else if (GET_CODE (DECL_RTL (parms)) == MEM + && XEXP (DECL_RTL (parms), 0) != const0_rtx + /* ??? A constant address for a parm can happen + when the reg it lives in is equiv to a constant in memory. + Should make this not happen, after 2.4. */ + && ! CONSTANT_P (XEXP (DECL_RTL (parms), 0))) + { + /* Parm was passed in registers but lives on the stack. */ + + current_sym_code = N_PSYM; + /* DECL_RTL looks like (MEM (PLUS (REG...) (CONST_INT...))), + in which case we want the value of that CONST_INT, + or (MEM (REG ...)) or (MEM (MEM ...)), + in which case we use a value of zero. */ + if (GET_CODE (XEXP (DECL_RTL (parms), 0)) == REG + || GET_CODE (XEXP (DECL_RTL (parms), 0)) == MEM) + current_sym_value = 0; + else + current_sym_value = INTVAL (XEXP (XEXP (DECL_RTL (parms), 0), 1)); + current_sym_addr = 0; + + FORCE_TEXT; + if (DECL_NAME (parms)) + { + current_sym_nchars = 2 + strlen (IDENTIFIER_POINTER (DECL_NAME (parms))); + + fprintf (asmfile, "%s \"%s:%c", ASM_STABS_OP, + IDENTIFIER_POINTER (DECL_NAME (parms)), + DBX_MEMPARM_STABS_LETTER); + } + else + { + current_sym_nchars = 8; + fprintf (asmfile, "%s \"(anon):%c", ASM_STABS_OP, + DBX_MEMPARM_STABS_LETTER); + } + + current_sym_value + = DEBUGGER_ARG_OFFSET (current_sym_value, + XEXP (DECL_RTL (parms), 0)); + dbxout_type (TREE_TYPE (parms), 0, 0); + dbxout_finish_symbol (parms); + } + } +} + +/* Output definitions for the places where parms live during the function, + when different from where they were passed, when the parms were passed + in memory. + + It is not useful to do this for parms passed in registers + that live during the function in different registers, because it is + impossible to look in the passed register for the passed value, + so we use the within-the-function register to begin with. + + PARMS is a chain of PARM_DECL nodes. */ + +void +dbxout_reg_parms (parms) + tree parms; +{ + for (; parms; parms = TREE_CHAIN (parms)) + if (DECL_NAME (parms)) + { + dbxout_prepare_symbol (parms); + + /* Report parms that live in registers during the function + but were passed in memory. */ + if (GET_CODE (DECL_RTL (parms)) == REG + && REGNO (DECL_RTL (parms)) >= 0 + && REGNO (DECL_RTL (parms)) < FIRST_PSEUDO_REGISTER + && PARM_PASSED_IN_MEMORY (parms)) + { + current_sym_code = N_RSYM; + current_sym_value = DBX_REGISTER_NUMBER (REGNO (DECL_RTL (parms))); + current_sym_addr = 0; + + FORCE_TEXT; + if (DECL_NAME (parms)) + { + current_sym_nchars = 2 + IDENTIFIER_LENGTH (DECL_NAME (parms)); + fprintf (asmfile, "%s \"%s:r", ASM_STABS_OP, + IDENTIFIER_POINTER (DECL_NAME (parms))); + } + else + { + current_sym_nchars = 8; + fprintf (asmfile, "%s \"(anon):r", ASM_STABS_OP); + } + dbxout_type (TREE_TYPE (parms), 0, 0); + dbxout_finish_symbol (parms); + } + /* Report parms that live in memory but not where they were passed. */ + else if (GET_CODE (DECL_RTL (parms)) == MEM + && GET_CODE (XEXP (DECL_RTL (parms), 0)) == PLUS + && GET_CODE (XEXP (XEXP (DECL_RTL (parms), 0), 1)) == CONST_INT + && PARM_PASSED_IN_MEMORY (parms) + && ! rtx_equal_p (DECL_RTL (parms), DECL_INCOMING_RTL (parms))) + { +#if 0 /* ??? It is not clear yet what should replace this. */ + int offset = DECL_OFFSET (parms) / BITS_PER_UNIT; + /* A parm declared char is really passed as an int, + so it occupies the least significant bytes. + On a big-endian machine those are not the low-numbered ones. */ +#if BYTES_BIG_ENDIAN + if (offset != -1 && TREE_TYPE (parms) != DECL_ARG_TYPE (parms)) + offset += (GET_MODE_SIZE (TYPE_MODE (DECL_ARG_TYPE (parms))) + - GET_MODE_SIZE (GET_MODE (DECL_RTL (parms)))); +#endif + if (INTVAL (XEXP (XEXP (DECL_RTL (parms), 0), 1)) != offset) {...} +#endif + current_sym_code = N_LSYM; + current_sym_value = DEBUGGER_AUTO_OFFSET (XEXP (DECL_RTL (parms), 0)); + current_sym_addr = 0; + FORCE_TEXT; + if (DECL_NAME (parms)) + { + current_sym_nchars = 2 + IDENTIFIER_LENGTH (DECL_NAME (parms)); + fprintf (asmfile, "%s \"%s:", ASM_STABS_OP, + IDENTIFIER_POINTER (DECL_NAME (parms))); + } + else + { + current_sym_nchars = 8; + fprintf (asmfile, "%s \"(anon):", ASM_STABS_OP); + } + dbxout_type (TREE_TYPE (parms), 0, 0); + dbxout_finish_symbol (parms); + } +#if 0 + else if (GET_CODE (DECL_RTL (parms)) == MEM + && GET_CODE (XEXP (DECL_RTL (parms), 0)) == REG) + { + /* Parm was passed via invisible reference. + That is, its address was passed in a register. + Output it as if it lived in that register. + The debugger will know from the type + that it was actually passed by invisible reference. */ + + current_sym_code = N_RSYM; + + /* DECL_RTL looks like (MEM (REG...). Get the register number. */ + current_sym_value = REGNO (XEXP (DECL_RTL (parms), 0)); + current_sym_addr = 0; + + FORCE_TEXT; + if (DECL_NAME (parms)) + { + current_sym_nchars = 2 + strlen (IDENTIFIER_POINTER (DECL_NAME (parms))); + + fprintf (asmfile, "%s \"%s:r", ASM_STABS_OP, + IDENTIFIER_POINTER (DECL_NAME (parms))); + } + else + { + current_sym_nchars = 8; + fprintf (asmfile, "%s \"(anon):r", ASM_STABS_OP); + } + + dbxout_type (TREE_TYPE (parms), 0, 0); + dbxout_finish_symbol (parms); + } +#endif + } +} + +/* Given a chain of ..._TYPE nodes (as come in a parameter list), + output definitions of those names, in raw form */ + +void +dbxout_args (args) + tree args; +{ + while (args) + { + putc (',', asmfile); + dbxout_type (TREE_VALUE (args), 0, 0); + CHARS (1); + args = TREE_CHAIN (args); + } +} + +/* Given a chain of ..._TYPE nodes, + find those which have typedef names and output those names. + This is to ensure those types get output. */ + +void +dbxout_types (types) + register tree types; +{ + while (types) + { + if (TYPE_NAME (types) + && TREE_CODE (TYPE_NAME (types)) == TYPE_DECL + && ! TREE_ASM_WRITTEN (TYPE_NAME (types))) + dbxout_symbol (TYPE_NAME (types), 1); + types = TREE_CHAIN (types); + } +} + +/* Output everything about a symbol block (a BLOCK node + that represents a scope level), + including recursive output of contained blocks. + + BLOCK is the BLOCK node. + DEPTH is its depth within containing symbol blocks. + ARGS is usually zero; but for the outermost block of the + body of a function, it is a chain of PARM_DECLs for the function parameters. + We output definitions of all the register parms + as if they were local variables of that block. + + If -g1 was used, we count blocks just the same, but output nothing + except for the outermost block. + + Actually, BLOCK may be several blocks chained together. + We handle them all in sequence. */ + +static void +dbxout_block (block, depth, args) + register tree block; + int depth; + tree args; +{ + int blocknum; + + while (block) + { + /* Ignore blocks never expanded or otherwise marked as real. */ + if (TREE_USED (block)) + { +#ifndef DBX_LBRAC_FIRST + /* In dbx format, the syms of a block come before the N_LBRAC. */ + if (debug_info_level != DINFO_LEVEL_TERSE || depth == 0) + dbxout_syms (BLOCK_VARS (block)); + if (args) + dbxout_reg_parms (args); +#endif + + /* Now output an N_LBRAC symbol to represent the beginning of + the block. Use the block's tree-walk order to generate + the assembler symbols LBBn and LBEn + that final will define around the code in this block. */ + if (depth > 0 && debug_info_level != DINFO_LEVEL_TERSE) + { + char buf[20]; + blocknum = next_block_number++; + ASM_GENERATE_INTERNAL_LABEL (buf, "LBB", blocknum); + + if (BLOCK_HANDLER_BLOCK (block)) + { + /* A catch block. Must precede N_LBRAC. */ + tree decl = BLOCK_VARS (block); + while (decl) + { +#ifdef DBX_OUTPUT_CATCH + DBX_OUTPUT_CATCH (asmfile, decl, buf); +#else + fprintf (asmfile, "%s \"%s:C1\",%d,0,0,", ASM_STABS_OP, + IDENTIFIER_POINTER (DECL_NAME (decl)), N_CATCH); + assemble_name (asmfile, buf); + fprintf (asmfile, "\n"); +#endif + decl = TREE_CHAIN (decl); + } + } + +#ifdef DBX_OUTPUT_LBRAC + DBX_OUTPUT_LBRAC (asmfile, buf); +#else + fprintf (asmfile, "%s %d,0,0,", ASM_STABN_OP, N_LBRAC); + assemble_name (asmfile, buf); +#if DBX_BLOCKS_FUNCTION_RELATIVE + fputc ('-', asmfile); + assemble_name (asmfile, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); +#endif + fprintf (asmfile, "\n"); +#endif + } + else if (depth > 0) + /* Count blocks the same way regardless of debug_info_level. */ + next_block_number++; + +#ifdef DBX_LBRAC_FIRST + /* On some weird machines, the syms of a block + come after the N_LBRAC. */ + if (debug_info_level != DINFO_LEVEL_TERSE || depth == 0) + dbxout_syms (BLOCK_VARS (block)); + if (args) + dbxout_reg_parms (args); +#endif + + /* Output the subblocks. */ + dbxout_block (BLOCK_SUBBLOCKS (block), depth + 1, NULL_TREE); + + /* Refer to the marker for the end of the block. */ + if (depth > 0 && debug_info_level != DINFO_LEVEL_TERSE) + { + char buf[20]; + ASM_GENERATE_INTERNAL_LABEL (buf, "LBE", blocknum); +#ifdef DBX_OUTPUT_RBRAC + DBX_OUTPUT_RBRAC (asmfile, buf); +#else + fprintf (asmfile, "%s %d,0,0,", ASM_STABN_OP, N_RBRAC); + assemble_name (asmfile, buf); +#if DBX_BLOCKS_FUNCTION_RELATIVE + fputc ('-', asmfile); + assemble_name (asmfile, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); +#endif + fprintf (asmfile, "\n"); +#endif + } + } + block = BLOCK_CHAIN (block); + } +} + +/* Output the information about a function and its arguments and result. + Usually this follows the function's code, + but on some systems, it comes before. */ + +static void +dbxout_really_begin_function (decl) + tree decl; +{ + dbxout_symbol (decl, 0); + dbxout_parms (DECL_ARGUMENTS (decl)); + if (DECL_NAME (DECL_RESULT (decl)) != 0) + dbxout_symbol (DECL_RESULT (decl), 1); +} + +/* Called at beginning of output of function definition. */ + +void +dbxout_begin_function (decl) + tree decl; +{ +#ifdef DBX_FUNCTION_FIRST + dbxout_really_begin_function (decl); +#endif +} + +/* Output dbx data for a function definition. + This includes a definition of the function name itself (a symbol), + definitions of the parameters (locating them in the parameter list) + and then output the block that makes up the function's body + (including all the auto variables of the function). */ + +void +dbxout_function (decl) + tree decl; +{ +#ifndef DBX_FUNCTION_FIRST + dbxout_really_begin_function (decl); +#endif + dbxout_block (DECL_INITIAL (decl), 0, DECL_ARGUMENTS (decl)); +#ifdef DBX_OUTPUT_FUNCTION_END + DBX_OUTPUT_FUNCTION_END (asmfile, decl); +#endif +} +#endif /* DBX_DEBUGGING_INFO */ diff --git a/gnu/usr.bin/cc/lib/defaults.h b/gnu/usr.bin/cc/lib/defaults.h new file mode 100644 index 000000000000..7234206e7d25 --- /dev/null +++ b/gnu/usr.bin/cc/lib/defaults.h @@ -0,0 +1,120 @@ +/* Definitions of various defaults for how to do assembler output + (most of which are designed to be appropriate for GAS or for + some BSD assembler). + + Written by Ron Guilmette (rfg@ncd.com) + +Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable or function named NAME. + LABELNO is an integer which is different for each call. */ + +#ifndef ASM_FORMAT_PRIVATE_NAME +#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ + do { \ + int len = strlen (NAME); \ + char *temp = (char *) alloca (len + 3); \ + temp[0] = 'L'; \ + strcpy (&temp[1], (NAME)); \ + temp[len + 1] = '.'; \ + temp[len + 2] = 0; \ + (OUTPUT) = (char *) alloca (strlen (NAME) + 11); \ + ASM_GENERATE_INTERNAL_LABEL (OUTPUT, temp, LABELNO); \ + } while (0) +#endif + +#ifndef ASM_STABD_OP +#define ASM_STABD_OP ".stabd" +#endif + +/* This is how to output an element of a case-vector that is absolute. + Some targets don't use this, but we have to define it anyway. */ + +#ifndef ASM_OUTPUT_ADDR_VEC_ELT +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ +do { fprintf (FILE, "\t%s\t", ASM_LONG); \ + ASM_OUTPUT_INTERNAL_LABEL (FILE, "L", (VALUE)); \ + fputc ('\n', FILE); \ + } while (0) +#endif + +/* This is how to output an element of a case-vector that is relative. + Some targets don't use this, but we have to define it anyway. */ + +#ifndef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ +do { fprintf (FILE, "\t%s\t", ASM_SHORT); \ + ASM_GENERATE_INTERNAL_LABEL (FILE, "L", (VALUE)); \ + fputc ('-', FILE); \ + ASM_GENERATE_INTERNAL_LABEL (FILE, "L", (REL)); \ + fputc ('\n', FILE); \ + } while (0) +#endif + +/* choose a reasonable default for ASM_OUTPUT_ASCII. */ + +#ifndef ASM_OUTPUT_ASCII +#define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \ + do { \ + FILE *_hide_asm_out_file = (MYFILE); \ + unsigned char *_hide_p = (unsigned char *) (MYSTRING); \ + int _hide_thissize = (MYLENGTH); \ + { \ + FILE *asm_out_file = _hide_asm_out_file; \ + unsigned char *p = _hide_p; \ + int thissize = _hide_thissize; \ + int i; \ + fprintf (asm_out_file, "\t.ascii \""); \ + \ + for (i = 0; i < thissize; i++) \ + { \ + register int c = p[i]; \ + if (c == '\"' || c == '\\') \ + putc ('\\', asm_out_file); \ + if (c >= ' ' && c < 0177) \ + putc (c, asm_out_file); \ + else \ + { \ + fprintf (asm_out_file, "\\%o", c); \ + /* After an octal-escape, if a digit follows, \ + terminate one string constant and start another. \ + The Vax assembler fails to stop reading the escape \ + after three digits, so this is the only way we \ + can get it to parse the data properly. */ \ + if (i < thissize - 1 \ + && p[i + 1] >= '0' && p[i + 1] <= '9') \ + fprintf (asm_out_file, "\"\n\t.ascii \""); \ + } \ + } \ + fprintf (asm_out_file, "\"\n"); \ + } \ + } \ + while (0) +#endif + +#ifndef ASM_IDENTIFY_GCC + /* Default the definition, only if ASM_IDENTIFY_GCC is not set, + because if it is set, we might not want ASM_IDENTIFY_LANGUAGE + outputting labels, if we do want it to, then it must be defined + in the tm.h file. */ +#ifndef ASM_IDENTIFY_LANGUAGE +#define ASM_IDENTIFY_LANGUAGE(FILE) output_lang_identify (FILE); +#endif +#endif diff --git a/gnu/usr.bin/cc/lib/dwarfout.c b/gnu/usr.bin/cc/lib/dwarfout.c new file mode 100644 index 000000000000..cd2dca50a750 --- /dev/null +++ b/gnu/usr.bin/cc/lib/dwarfout.c @@ -0,0 +1,5647 @@ +/* This file contains code written by Ron Guilmette (rfg@ncd.com) for + Network Computing Devices, August, September, October, November 1990. + + Output Dwarf format symbol table information from the GNU C compiler. + Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include "config.h" + +#ifdef DWARF_DEBUGGING_INFO +#include +#include "dwarf.h" +#include "tree.h" +#include "flags.h" +#include "rtl.h" +#include "hard-reg-set.h" +#include "insn-config.h" +#include "reload.h" +#include "output.h" +#include "defaults.h" + +#ifndef DWARF_VERSION +#define DWARF_VERSION 1 +#endif + +/* #define NDEBUG 1 */ +#include "assert.h" + +#if defined(DWARF_TIMESTAMPS) +#if defined(POSIX) +#include +#else /* !defined(POSIX) */ +#include +#if defined(__STDC__) +extern time_t time (time_t *); +#else /* !defined(__STDC__) */ +extern time_t time (); +#endif /* !defined(__STDC__) */ +#endif /* !defined(POSIX) */ +#endif /* defined(DWARF_TIMESTAMPS) */ + +extern char *getpwd (); + +extern char *index (); +extern char *rindex (); + +/* IMPORTANT NOTE: Please see the file README.DWARF for important details + regarding the GNU implementation of Dwarf. */ + +/* NOTE: In the comments in this file, many references are made to + so called "Debugging Information Entries". For the sake of brevity, + this term is abbreviated to `DIE' throughout the remainder of this + file. */ + +/* Note that the implementation of C++ support herein is (as yet) unfinished. + If you want to try to complete it, more power to you. */ + +#if defined(__GNUC__) && (NDEBUG == 1) +#define inline static inline +#else +#define inline static +#endif + +/* How to start an assembler comment. */ +#ifndef ASM_COMMENT_START +#define ASM_COMMENT_START ";#" +#endif + +/* How to print out a register name. */ +#ifndef PRINT_REG +#define PRINT_REG(RTX, CODE, FILE) \ + fprintf ((FILE), "%s", reg_names[REGNO (RTX)]) +#endif + +/* Define a macro which returns non-zero for any tagged type which is + used (directly or indirectly) in the specification of either some + function's return type or some formal parameter of some function. + We use this macro when we are operating in "terse" mode to help us + know what tagged types have to be represented in Dwarf (even in + terse mode) and which ones don't. + + A flag bit with this meaning really should be a part of the normal + GCC ..._TYPE nodes, but at the moment, there is no such bit defined + for these nodes. For now, we have to just fake it. It it safe for + us to simply return zero for all complete tagged types (which will + get forced out anyway if they were used in the specification of some + formal or return type) and non-zero for all incomplete tagged types. +*/ + +#define TYPE_USED_FOR_FUNCTION(tagged_type) (TYPE_SIZE (tagged_type) == 0) + +extern int flag_traditional; +extern char *version_string; +extern char *language_string; + +/* Maximum size (in bytes) of an artificially generated label. */ + +#define MAX_ARTIFICIAL_LABEL_BYTES 30 + +/* Make sure we know the sizes of the various types dwarf can describe. + These are only defaults. If the sizes are different for your target, + you should override these values by defining the appropriate symbols + in your tm.h file. */ + +#ifndef CHAR_TYPE_SIZE +#define CHAR_TYPE_SIZE BITS_PER_UNIT +#endif + +#ifndef SHORT_TYPE_SIZE +#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) +#endif + +#ifndef INT_TYPE_SIZE +#define INT_TYPE_SIZE BITS_PER_WORD +#endif + +#ifndef LONG_TYPE_SIZE +#define LONG_TYPE_SIZE BITS_PER_WORD +#endif + +#ifndef LONG_LONG_TYPE_SIZE +#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) +#endif + +#ifndef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE INT_TYPE_SIZE +#endif + +#ifndef WCHAR_UNSIGNED +#define WCHAR_UNSIGNED 0 +#endif + +#ifndef FLOAT_TYPE_SIZE +#define FLOAT_TYPE_SIZE BITS_PER_WORD +#endif + +#ifndef DOUBLE_TYPE_SIZE +#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) +#endif + +#ifndef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) +#endif + +/* Structure to keep track of source filenames. */ + +struct filename_entry { + unsigned number; + char * name; +}; + +typedef struct filename_entry filename_entry; + +/* Pointer to an array of elements, each one having the structure above. */ + +static filename_entry *filename_table; + +/* Total number of entries in the table (i.e. array) pointed to by + `filename_table'. This is the *total* and includes both used and + unused slots. */ + +static unsigned ft_entries_allocated; + +/* Number of entries in the filename_table which are actually in use. */ + +static unsigned ft_entries; + +/* Size (in elements) of increments by which we may expand the filename + table. Actually, a single hunk of space of this size should be enough + for most typical programs. */ + +#define FT_ENTRIES_INCREMENT 64 + +/* Local pointer to the name of the main input file. Initialized in + dwarfout_init. */ + +static char *primary_filename; + +/* Pointer to the most recent filename for which we produced some line info. */ + +static char *last_filename; + +/* For Dwarf output, we must assign lexical-blocks id numbers + in the order in which their beginnings are encountered. + We output Dwarf debugging info that refers to the beginnings + and ends of the ranges of code for each lexical block with + assembler labels ..Bn and ..Bn.e, where n is the block number. + The labels themselves are generated in final.c, which assigns + numbers to the blocks in the same way. */ + +static unsigned next_block_number = 2; + +/* Counter to generate unique names for DIEs. */ + +static unsigned next_unused_dienum = 1; + +/* Number of the DIE which is currently being generated. */ + +static unsigned current_dienum; + +/* Number to use for the special "pubname" label on the next DIE which + represents a function or data object defined in this compilation + unit which has "extern" linkage. */ + +static next_pubname_number = 0; + +#define NEXT_DIE_NUM pending_sibling_stack[pending_siblings-1] + +/* Pointer to a dynamically allocated list of pre-reserved and still + pending sibling DIE numbers. Note that this list will grow as needed. */ + +static unsigned *pending_sibling_stack; + +/* Counter to keep track of the number of pre-reserved and still pending + sibling DIE numbers. */ + +static unsigned pending_siblings; + +/* The currently allocated size of the above list (expressed in number of + list elements). */ + +static unsigned pending_siblings_allocated; + +/* Size (in elements) of increments by which we may expand the pending + sibling stack. Actually, a single hunk of space of this size should + be enough for most typical programs. */ + +#define PENDING_SIBLINGS_INCREMENT 64 + +/* Non-zero if we are performing our file-scope finalization pass and if + we should force out Dwarf descriptions of any and all file-scope + tagged types which are still incomplete types. */ + +static int finalizing = 0; + +/* A pointer to the base of a list of pending types which we haven't + generated DIEs for yet, but which we will have to come back to + later on. */ + +static tree *pending_types_list; + +/* Number of elements currently allocated for the pending_types_list. */ + +static unsigned pending_types_allocated; + +/* Number of elements of pending_types_list currently in use. */ + +static unsigned pending_types; + +/* Size (in elements) of increments by which we may expand the pending + types list. Actually, a single hunk of space of this size should + be enough for most typical programs. */ + +#define PENDING_TYPES_INCREMENT 64 + +/* Pointer to an artificial RECORD_TYPE which we create in dwarfout_init. + This is used in a hack to help us get the DIEs describing types of + formal parameters to come *after* all of the DIEs describing the formal + parameters themselves. That's necessary in order to be compatible + with what the brain-damaged svr4 SDB debugger requires. */ + +static tree fake_containing_scope; + +/* The number of the current function definition that we are generating + debugging information for. These numbers range from 1 up to the maximum + number of function definitions contained within the current compilation + unit. These numbers are used to create unique labels for various things + contained within various function definitions. */ + +static unsigned current_funcdef_number = 1; + +/* A pointer to the ..._DECL node which we have most recently been working + on. We keep this around just in case something about it looks screwy + and we want to tell the user what the source coordinates for the actual + declaration are. */ + +static tree dwarf_last_decl; + +/* Forward declarations for functions defined in this file. */ + +static void output_type (); +static void type_attribute (); +static void output_decls_for_scope (); +static void output_decl (); +static unsigned lookup_filename (); + +/* Definitions of defaults for assembler-dependent names of various + pseudo-ops and section names. + + Theses may be overridden in your tm.h file (if necessary) for your + particular assembler. The default values provided here correspond to + what is expected by "standard" AT&T System V.4 assemblers. */ + +#ifndef FILE_ASM_OP +#define FILE_ASM_OP ".file" +#endif +#ifndef VERSION_ASM_OP +#define VERSION_ASM_OP ".version" +#endif +#ifndef UNALIGNED_SHORT_ASM_OP +#define UNALIGNED_SHORT_ASM_OP ".2byte" +#endif +#ifndef UNALIGNED_INT_ASM_OP +#define UNALIGNED_INT_ASM_OP ".4byte" +#endif +#ifndef ASM_BYTE_OP +#define ASM_BYTE_OP ".byte" +#endif +#ifndef SET_ASM_OP +#define SET_ASM_OP ".set" +#endif + +/* Pseudo-ops for pushing the current section onto the section stack (and + simultaneously changing to a new section) and for poping back to the + section we were in immediately before this one. Note that most svr4 + assemblers only maintain a one level stack... you can push all the + sections you want, but you can only pop out one level. (The sparc + svr4 assembler is an exception to this general rule.) That's + OK because we only use at most one level of the section stack herein. */ + +#ifndef PUSHSECTION_ASM_OP +#define PUSHSECTION_ASM_OP ".section" +#endif +#ifndef POPSECTION_ASM_OP +#define POPSECTION_ASM_OP ".previous" +#endif + +/* The default format used by the ASM_OUTPUT_PUSH_SECTION macro (see below) + to print the PUSHSECTION_ASM_OP and the section name. The default here + works for almost all svr4 assemblers, except for the sparc, where the + section name must be enclosed in double quotes. (See sparcv4.h.) */ + +#ifndef PUSHSECTION_FORMAT +#define PUSHSECTION_FORMAT "%s\t%s\n" +#endif + +#ifndef DEBUG_SECTION +#define DEBUG_SECTION ".debug" +#endif +#ifndef LINE_SECTION +#define LINE_SECTION ".line" +#endif +#ifndef SFNAMES_SECTION +#define SFNAMES_SECTION ".debug_sfnames" +#endif +#ifndef SRCINFO_SECTION +#define SRCINFO_SECTION ".debug_srcinfo" +#endif +#ifndef MACINFO_SECTION +#define MACINFO_SECTION ".debug_macinfo" +#endif +#ifndef PUBNAMES_SECTION +#define PUBNAMES_SECTION ".debug_pubnames" +#endif +#ifndef ARANGES_SECTION +#define ARANGES_SECTION ".debug_aranges" +#endif +#ifndef TEXT_SECTION +#define TEXT_SECTION ".text" +#endif +#ifndef DATA_SECTION +#define DATA_SECTION ".data" +#endif +#ifndef DATA1_SECTION +#define DATA1_SECTION ".data1" +#endif +#ifndef RODATA_SECTION +#define RODATA_SECTION ".rodata" +#endif +#ifndef RODATA1_SECTION +#define RODATA1_SECTION ".rodata1" +#endif +#ifndef BSS_SECTION +#define BSS_SECTION ".bss" +#endif + +/* Definitions of defaults for formats and names of various special + (artificial) labels which may be generated within this file (when + the -g options is used and DWARF_DEBUGGING_INFO is in effect. + + If necessary, these may be overridden from within your tm.h file, + but typically, you should never need to override these. + + These labels have been hacked (temporarily) so that they all begin with + a `.L' sequence so as to appease the stock sparc/svr4 assembler and the + stock m88k/svr4 assembler, both of which need to see .L at the start of + a label in order to prevent that label from going into the linker symbol + table). When I get time, I'll have to fix this the right way so that we + will use ASM_GENERATE_INTERNAL_LABEL and ASM_OUTPUT_INTERNAL_LABEL herein, + but that will require a rather massive set of changes. For the moment, + the following definitions out to produce the right results for all svr4 + and svr3 assemblers. -- rfg +*/ + +#ifndef TEXT_BEGIN_LABEL +#define TEXT_BEGIN_LABEL ".L_text_b" +#endif +#ifndef TEXT_END_LABEL +#define TEXT_END_LABEL ".L_text_e" +#endif + +#ifndef DATA_BEGIN_LABEL +#define DATA_BEGIN_LABEL ".L_data_b" +#endif +#ifndef DATA_END_LABEL +#define DATA_END_LABEL ".L_data_e" +#endif + +#ifndef DATA1_BEGIN_LABEL +#define DATA1_BEGIN_LABEL ".L_data1_b" +#endif +#ifndef DATA1_END_LABEL +#define DATA1_END_LABEL ".L_data1_e" +#endif + +#ifndef RODATA_BEGIN_LABEL +#define RODATA_BEGIN_LABEL ".L_rodata_b" +#endif +#ifndef RODATA_END_LABEL +#define RODATA_END_LABEL ".L_rodata_e" +#endif + +#ifndef RODATA1_BEGIN_LABEL +#define RODATA1_BEGIN_LABEL ".L_rodata1_b" +#endif +#ifndef RODATA1_END_LABEL +#define RODATA1_END_LABEL ".L_rodata1_e" +#endif + +#ifndef BSS_BEGIN_LABEL +#define BSS_BEGIN_LABEL ".L_bss_b" +#endif +#ifndef BSS_END_LABEL +#define BSS_END_LABEL ".L_bss_e" +#endif + +#ifndef LINE_BEGIN_LABEL +#define LINE_BEGIN_LABEL ".L_line_b" +#endif +#ifndef LINE_LAST_ENTRY_LABEL +#define LINE_LAST_ENTRY_LABEL ".L_line_last" +#endif +#ifndef LINE_END_LABEL +#define LINE_END_LABEL ".L_line_e" +#endif + +#ifndef DEBUG_BEGIN_LABEL +#define DEBUG_BEGIN_LABEL ".L_debug_b" +#endif +#ifndef SFNAMES_BEGIN_LABEL +#define SFNAMES_BEGIN_LABEL ".L_sfnames_b" +#endif +#ifndef SRCINFO_BEGIN_LABEL +#define SRCINFO_BEGIN_LABEL ".L_srcinfo_b" +#endif +#ifndef MACINFO_BEGIN_LABEL +#define MACINFO_BEGIN_LABEL ".L_macinfo_b" +#endif + +#ifndef DIE_BEGIN_LABEL_FMT +#define DIE_BEGIN_LABEL_FMT ".L_D%u" +#endif +#ifndef DIE_END_LABEL_FMT +#define DIE_END_LABEL_FMT ".L_D%u_e" +#endif +#ifndef PUB_DIE_LABEL_FMT +#define PUB_DIE_LABEL_FMT ".L_P%u" +#endif +#ifndef INSN_LABEL_FMT +#define INSN_LABEL_FMT ".L_I%u_%u" +#endif +#ifndef BLOCK_BEGIN_LABEL_FMT +#define BLOCK_BEGIN_LABEL_FMT ".L_B%u" +#endif +#ifndef BLOCK_END_LABEL_FMT +#define BLOCK_END_LABEL_FMT ".L_B%u_e" +#endif +#ifndef SS_BEGIN_LABEL_FMT +#define SS_BEGIN_LABEL_FMT ".L_s%u" +#endif +#ifndef SS_END_LABEL_FMT +#define SS_END_LABEL_FMT ".L_s%u_e" +#endif +#ifndef EE_BEGIN_LABEL_FMT +#define EE_BEGIN_LABEL_FMT ".L_e%u" +#endif +#ifndef EE_END_LABEL_FMT +#define EE_END_LABEL_FMT ".L_e%u_e" +#endif +#ifndef MT_BEGIN_LABEL_FMT +#define MT_BEGIN_LABEL_FMT ".L_t%u" +#endif +#ifndef MT_END_LABEL_FMT +#define MT_END_LABEL_FMT ".L_t%u_e" +#endif +#ifndef LOC_BEGIN_LABEL_FMT +#define LOC_BEGIN_LABEL_FMT ".L_l%u" +#endif +#ifndef LOC_END_LABEL_FMT +#define LOC_END_LABEL_FMT ".L_l%u_e" +#endif +#ifndef BOUND_BEGIN_LABEL_FMT +#define BOUND_BEGIN_LABEL_FMT ".L_b%u_%u_%c" +#endif +#ifndef BOUND_END_LABEL_FMT +#define BOUND_END_LABEL_FMT ".L_b%u_%u_%c_e" +#endif +#ifndef DERIV_BEGIN_LABEL_FMT +#define DERIV_BEGIN_LABEL_FMT ".L_d%u" +#endif +#ifndef DERIV_END_LABEL_FMT +#define DERIV_END_LABEL_FMT ".L_d%u_e" +#endif +#ifndef SL_BEGIN_LABEL_FMT +#define SL_BEGIN_LABEL_FMT ".L_sl%u" +#endif +#ifndef SL_END_LABEL_FMT +#define SL_END_LABEL_FMT ".L_sl%u_e" +#endif +#ifndef BODY_BEGIN_LABEL_FMT +#define BODY_BEGIN_LABEL_FMT ".L_b%u" +#endif +#ifndef BODY_END_LABEL_FMT +#define BODY_END_LABEL_FMT ".L_b%u_e" +#endif +#ifndef FUNC_END_LABEL_FMT +#define FUNC_END_LABEL_FMT ".L_f%u_e" +#endif +#ifndef TYPE_NAME_FMT +#define TYPE_NAME_FMT ".L_T%u" +#endif +#ifndef DECL_NAME_FMT +#define DECL_NAME_FMT ".L_E%u" +#endif +#ifndef LINE_CODE_LABEL_FMT +#define LINE_CODE_LABEL_FMT ".L_LC%u" +#endif +#ifndef SFNAMES_ENTRY_LABEL_FMT +#define SFNAMES_ENTRY_LABEL_FMT ".L_F%u" +#endif +#ifndef LINE_ENTRY_LABEL_FMT +#define LINE_ENTRY_LABEL_FMT ".L_LE%u" +#endif + +/* Definitions of defaults for various types of primitive assembly language + output operations. + + If necessary, these may be overridden from within your tm.h file, + but typically, you shouldn't need to override these. One known + exception is ASM_OUTPUT_DEF which has to be different for stock + sparc/svr4 assemblers. +*/ + +#ifndef ASM_OUTPUT_PUSH_SECTION +#define ASM_OUTPUT_PUSH_SECTION(FILE, SECTION) \ + fprintf ((FILE), PUSHSECTION_FORMAT, PUSHSECTION_ASM_OP, SECTION) +#endif + +#ifndef ASM_OUTPUT_POP_SECTION +#define ASM_OUTPUT_POP_SECTION(FILE) \ + fprintf ((FILE), "\t%s\n", POPSECTION_ASM_OP) +#endif + +#ifndef ASM_OUTPUT_SOURCE_FILENAME +#define ASM_OUTPUT_SOURCE_FILENAME(FILE,NAME) \ + fprintf ((FILE), "\t%s\t\"%s\"\n", FILE_ASM_OP, NAME) +#endif + +#ifndef ASM_OUTPUT_DEF +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ + do { fprintf ((FILE), "\t%s\t", SET_ASM_OP); \ + assemble_name (FILE, LABEL1); \ + fprintf (FILE, ","); \ + assemble_name (FILE, LABEL2); \ + fprintf (FILE, "\n"); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_DELTA2 +#define ASM_OUTPUT_DWARF_DELTA2(FILE,LABEL1,LABEL2) \ + do { fprintf ((FILE), "\t%s\t", UNALIGNED_SHORT_ASM_OP); \ + assemble_name (FILE, LABEL1); \ + fprintf (FILE, "-"); \ + assemble_name (FILE, LABEL2); \ + fprintf (FILE, "\n"); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_DELTA4 +#define ASM_OUTPUT_DWARF_DELTA4(FILE,LABEL1,LABEL2) \ + do { fprintf ((FILE), "\t%s\t", UNALIGNED_INT_ASM_OP); \ + assemble_name (FILE, LABEL1); \ + fprintf (FILE, "-"); \ + assemble_name (FILE, LABEL2); \ + fprintf (FILE, "\n"); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_TAG +#define ASM_OUTPUT_DWARF_TAG(FILE,TAG) \ + do { \ + fprintf ((FILE), "\t%s\t0x%x", \ + UNALIGNED_SHORT_ASM_OP, (unsigned) TAG); \ + if (flag_verbose_asm) \ + fprintf ((FILE), "\t%s %s", \ + ASM_COMMENT_START, dwarf_tag_name (TAG)); \ + fputc ('\n', (FILE)); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_ATTRIBUTE +#define ASM_OUTPUT_DWARF_ATTRIBUTE(FILE,ATTR) \ + do { \ + fprintf ((FILE), "\t%s\t0x%x", \ + UNALIGNED_SHORT_ASM_OP, (unsigned) ATTR); \ + if (flag_verbose_asm) \ + fprintf ((FILE), "\t%s %s", \ + ASM_COMMENT_START, dwarf_attr_name (ATTR)); \ + fputc ('\n', (FILE)); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_STACK_OP +#define ASM_OUTPUT_DWARF_STACK_OP(FILE,OP) \ + do { \ + fprintf ((FILE), "\t%s\t0x%x", ASM_BYTE_OP, (unsigned) OP); \ + if (flag_verbose_asm) \ + fprintf ((FILE), "\t%s %s", \ + ASM_COMMENT_START, dwarf_stack_op_name (OP)); \ + fputc ('\n', (FILE)); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_FUND_TYPE +#define ASM_OUTPUT_DWARF_FUND_TYPE(FILE,FT) \ + do { \ + fprintf ((FILE), "\t%s\t0x%x", \ + UNALIGNED_SHORT_ASM_OP, (unsigned) FT); \ + if (flag_verbose_asm) \ + fprintf ((FILE), "\t%s %s", \ + ASM_COMMENT_START, dwarf_fund_type_name (FT)); \ + fputc ('\n', (FILE)); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_FMT_BYTE +#define ASM_OUTPUT_DWARF_FMT_BYTE(FILE,FMT) \ + do { \ + fprintf ((FILE), "\t%s\t0x%x", ASM_BYTE_OP, (unsigned) FMT); \ + if (flag_verbose_asm) \ + fprintf ((FILE), "\t%s %s", \ + ASM_COMMENT_START, dwarf_fmt_byte_name (FMT)); \ + fputc ('\n', (FILE)); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_TYPE_MODIFIER +#define ASM_OUTPUT_DWARF_TYPE_MODIFIER(FILE,MOD) \ + do { \ + fprintf ((FILE), "\t%s\t0x%x", ASM_BYTE_OP, (unsigned) MOD); \ + if (flag_verbose_asm) \ + fprintf ((FILE), "\t%s %s", \ + ASM_COMMENT_START, dwarf_typemod_name (MOD)); \ + fputc ('\n', (FILE)); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_ADDR +#define ASM_OUTPUT_DWARF_ADDR(FILE,LABEL) \ + do { fprintf ((FILE), "\t%s\t", UNALIGNED_INT_ASM_OP); \ + assemble_name (FILE, LABEL); \ + fprintf (FILE, "\n"); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_ADDR_CONST +#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,RTX) \ + do { \ + fprintf ((FILE), "\t%s\t", UNALIGNED_INT_ASM_OP); \ + output_addr_const ((FILE), (RTX)); \ + fputc ('\n', (FILE)); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_REF +#define ASM_OUTPUT_DWARF_REF(FILE,LABEL) \ + do { fprintf ((FILE), "\t%s\t", UNALIGNED_INT_ASM_OP); \ + assemble_name (FILE, LABEL); \ + fprintf (FILE, "\n"); \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_DATA1 +#define ASM_OUTPUT_DWARF_DATA1(FILE,VALUE) \ + fprintf ((FILE), "\t%s\t0x%x\n", ASM_BYTE_OP, VALUE) +#endif + +#ifndef ASM_OUTPUT_DWARF_DATA2 +#define ASM_OUTPUT_DWARF_DATA2(FILE,VALUE) \ + fprintf ((FILE), "\t%s\t0x%x\n", UNALIGNED_SHORT_ASM_OP, (unsigned) VALUE) +#endif + +#ifndef ASM_OUTPUT_DWARF_DATA4 +#define ASM_OUTPUT_DWARF_DATA4(FILE,VALUE) \ + fprintf ((FILE), "\t%s\t0x%x\n", UNALIGNED_INT_ASM_OP, (unsigned) VALUE) +#endif + +#ifndef ASM_OUTPUT_DWARF_DATA8 +#define ASM_OUTPUT_DWARF_DATA8(FILE,HIGH_VALUE,LOW_VALUE) \ + do { \ + if (WORDS_BIG_ENDIAN) \ + { \ + fprintf ((FILE), "\t%s\t0x%x\n", UNALIGNED_INT_ASM_OP, HIGH_VALUE); \ + fprintf ((FILE), "\t%s\t0x%x\n", UNALIGNED_INT_ASM_OP, LOW_VALUE);\ + } \ + else \ + { \ + fprintf ((FILE), "\t%s\t0x%x\n", UNALIGNED_INT_ASM_OP, LOW_VALUE);\ + fprintf ((FILE), "\t%s\t0x%x\n", UNALIGNED_INT_ASM_OP, HIGH_VALUE); \ + } \ + } while (0) +#endif + +#ifndef ASM_OUTPUT_DWARF_STRING +#define ASM_OUTPUT_DWARF_STRING(FILE,P) \ + ASM_OUTPUT_ASCII ((FILE), P, strlen (P)+1) +#endif + +/************************ general utility functions **************************/ + +inline char * +xstrdup (s) + register char *s; +{ + register char *p = (char *) xmalloc (strlen (s) + 1); + + strcpy (p, s); + return p; +} + +inline int +is_pseudo_reg (rtl) + register rtx rtl; +{ + return (((GET_CODE (rtl) == REG) && (REGNO (rtl) >= FIRST_PSEUDO_REGISTER)) + || ((GET_CODE (rtl) == SUBREG) + && (REGNO (XEXP (rtl, 0)) >= FIRST_PSEUDO_REGISTER))); +} + +inline tree +type_main_variant (type) + register tree type; +{ + type = TYPE_MAIN_VARIANT (type); + + /* There really should be only one main variant among any group of variants + of a given type (and all of the MAIN_VARIANT values for all members of + the group should point to that one type) but sometimes the C front-end + messes this up for array types, so we work around that bug here. */ + + if (TREE_CODE (type) == ARRAY_TYPE) + { + while (type != TYPE_MAIN_VARIANT (type)) + type = TYPE_MAIN_VARIANT (type); + } + + return type; +} + +/* Return non-zero if the given type node represents a tagged type. */ + +inline int +is_tagged_type (type) + register tree type; +{ + register enum tree_code code = TREE_CODE (type); + + return (code == RECORD_TYPE || code == UNION_TYPE + || code == QUAL_UNION_TYPE || code == ENUMERAL_TYPE); +} + +static char * +dwarf_tag_name (tag) + register unsigned tag; +{ + switch (tag) + { + case TAG_padding: return "TAG_padding"; + case TAG_array_type: return "TAG_array_type"; + case TAG_class_type: return "TAG_class_type"; + case TAG_entry_point: return "TAG_entry_point"; + case TAG_enumeration_type: return "TAG_enumeration_type"; + case TAG_formal_parameter: return "TAG_formal_parameter"; + case TAG_global_subroutine: return "TAG_global_subroutine"; + case TAG_global_variable: return "TAG_global_variable"; + case TAG_label: return "TAG_label"; + case TAG_lexical_block: return "TAG_lexical_block"; + case TAG_local_variable: return "TAG_local_variable"; + case TAG_member: return "TAG_member"; + case TAG_pointer_type: return "TAG_pointer_type"; + case TAG_reference_type: return "TAG_reference_type"; + case TAG_compile_unit: return "TAG_compile_unit"; + case TAG_string_type: return "TAG_string_type"; + case TAG_structure_type: return "TAG_structure_type"; + case TAG_subroutine: return "TAG_subroutine"; + case TAG_subroutine_type: return "TAG_subroutine_type"; + case TAG_typedef: return "TAG_typedef"; + case TAG_union_type: return "TAG_union_type"; + case TAG_unspecified_parameters: return "TAG_unspecified_parameters"; + case TAG_variant: return "TAG_variant"; + case TAG_common_block: return "TAG_common_block"; + case TAG_common_inclusion: return "TAG_common_inclusion"; + case TAG_inheritance: return "TAG_inheritance"; + case TAG_inlined_subroutine: return "TAG_inlined_subroutine"; + case TAG_module: return "TAG_module"; + case TAG_ptr_to_member_type: return "TAG_ptr_to_member_type"; + case TAG_set_type: return "TAG_set_type"; + case TAG_subrange_type: return "TAG_subrange_type"; + case TAG_with_stmt: return "TAG_with_stmt"; + + /* GNU extensions. */ + + case TAG_format_label: return "TAG_format_label"; + case TAG_namelist: return "TAG_namelist"; + case TAG_function_template: return "TAG_function_template"; + case TAG_class_template: return "TAG_class_template"; + + default: return "TAG_"; + } +} + +static char * +dwarf_attr_name (attr) + register unsigned attr; +{ + switch (attr) + { + case AT_sibling: return "AT_sibling"; + case AT_location: return "AT_location"; + case AT_name: return "AT_name"; + case AT_fund_type: return "AT_fund_type"; + case AT_mod_fund_type: return "AT_mod_fund_type"; + case AT_user_def_type: return "AT_user_def_type"; + case AT_mod_u_d_type: return "AT_mod_u_d_type"; + case AT_ordering: return "AT_ordering"; + case AT_subscr_data: return "AT_subscr_data"; + case AT_byte_size: return "AT_byte_size"; + case AT_bit_offset: return "AT_bit_offset"; + case AT_bit_size: return "AT_bit_size"; + case AT_element_list: return "AT_element_list"; + case AT_stmt_list: return "AT_stmt_list"; + case AT_low_pc: return "AT_low_pc"; + case AT_high_pc: return "AT_high_pc"; + case AT_language: return "AT_language"; + case AT_member: return "AT_member"; + case AT_discr: return "AT_discr"; + case AT_discr_value: return "AT_discr_value"; + case AT_string_length: return "AT_string_length"; + case AT_common_reference: return "AT_common_reference"; + case AT_comp_dir: return "AT_comp_dir"; + case AT_const_value_string: return "AT_const_value_string"; + case AT_const_value_data2: return "AT_const_value_data2"; + case AT_const_value_data4: return "AT_const_value_data4"; + case AT_const_value_data8: return "AT_const_value_data8"; + case AT_const_value_block2: return "AT_const_value_block2"; + case AT_const_value_block4: return "AT_const_value_block4"; + case AT_containing_type: return "AT_containing_type"; + case AT_default_value_addr: return "AT_default_value_addr"; + case AT_default_value_data2: return "AT_default_value_data2"; + case AT_default_value_data4: return "AT_default_value_data4"; + case AT_default_value_data8: return "AT_default_value_data8"; + case AT_default_value_string: return "AT_default_value_string"; + case AT_friends: return "AT_friends"; + case AT_inline: return "AT_inline"; + case AT_is_optional: return "AT_is_optional"; + case AT_lower_bound_ref: return "AT_lower_bound_ref"; + case AT_lower_bound_data2: return "AT_lower_bound_data2"; + case AT_lower_bound_data4: return "AT_lower_bound_data4"; + case AT_lower_bound_data8: return "AT_lower_bound_data8"; + case AT_private: return "AT_private"; + case AT_producer: return "AT_producer"; + case AT_program: return "AT_program"; + case AT_protected: return "AT_protected"; + case AT_prototyped: return "AT_prototyped"; + case AT_public: return "AT_public"; + case AT_pure_virtual: return "AT_pure_virtual"; + case AT_return_addr: return "AT_return_addr"; + case AT_abstract_origin: return "AT_abstract_origin"; + case AT_start_scope: return "AT_start_scope"; + case AT_stride_size: return "AT_stride_size"; + case AT_upper_bound_ref: return "AT_upper_bound_ref"; + case AT_upper_bound_data2: return "AT_upper_bound_data2"; + case AT_upper_bound_data4: return "AT_upper_bound_data4"; + case AT_upper_bound_data8: return "AT_upper_bound_data8"; + case AT_virtual: return "AT_virtual"; + + /* GNU extensions */ + + case AT_sf_names: return "AT_sf_names"; + case AT_src_info: return "AT_src_info"; + case AT_mac_info: return "AT_mac_info"; + case AT_src_coords: return "AT_src_coords"; + case AT_body_begin: return "AT_body_begin"; + case AT_body_end: return "AT_body_end"; + + default: return "AT_"; + } +} + +static char * +dwarf_stack_op_name (op) + register unsigned op; +{ + switch (op) + { + case OP_REG: return "OP_REG"; + case OP_BASEREG: return "OP_BASEREG"; + case OP_ADDR: return "OP_ADDR"; + case OP_CONST: return "OP_CONST"; + case OP_DEREF2: return "OP_DEREF2"; + case OP_DEREF4: return "OP_DEREF4"; + case OP_ADD: return "OP_ADD"; + default: return "OP_"; + } +} + +static char * +dwarf_typemod_name (mod) + register unsigned mod; +{ + switch (mod) + { + case MOD_pointer_to: return "MOD_pointer_to"; + case MOD_reference_to: return "MOD_reference_to"; + case MOD_const: return "MOD_const"; + case MOD_volatile: return "MOD_volatile"; + default: return "MOD_"; + } +} + +static char * +dwarf_fmt_byte_name (fmt) + register unsigned fmt; +{ + switch (fmt) + { + case FMT_FT_C_C: return "FMT_FT_C_C"; + case FMT_FT_C_X: return "FMT_FT_C_X"; + case FMT_FT_X_C: return "FMT_FT_X_C"; + case FMT_FT_X_X: return "FMT_FT_X_X"; + case FMT_UT_C_C: return "FMT_UT_C_C"; + case FMT_UT_C_X: return "FMT_UT_C_X"; + case FMT_UT_X_C: return "FMT_UT_X_C"; + case FMT_UT_X_X: return "FMT_UT_X_X"; + case FMT_ET: return "FMT_ET"; + default: return "FMT_"; + } +} +static char * +dwarf_fund_type_name (ft) + register unsigned ft; +{ + switch (ft) + { + case FT_char: return "FT_char"; + case FT_signed_char: return "FT_signed_char"; + case FT_unsigned_char: return "FT_unsigned_char"; + case FT_short: return "FT_short"; + case FT_signed_short: return "FT_signed_short"; + case FT_unsigned_short: return "FT_unsigned_short"; + case FT_integer: return "FT_integer"; + case FT_signed_integer: return "FT_signed_integer"; + case FT_unsigned_integer: return "FT_unsigned_integer"; + case FT_long: return "FT_long"; + case FT_signed_long: return "FT_signed_long"; + case FT_unsigned_long: return "FT_unsigned_long"; + case FT_pointer: return "FT_pointer"; + case FT_float: return "FT_float"; + case FT_dbl_prec_float: return "FT_dbl_prec_float"; + case FT_ext_prec_float: return "FT_ext_prec_float"; + case FT_complex: return "FT_complex"; + case FT_dbl_prec_complex: return "FT_dbl_prec_complex"; + case FT_void: return "FT_void"; + case FT_boolean: return "FT_boolean"; + case FT_ext_prec_complex: return "FT_ext_prec_complex"; + case FT_label: return "FT_label"; + + /* GNU extensions. */ + + case FT_long_long: return "FT_long_long"; + case FT_signed_long_long: return "FT_signed_long_long"; + case FT_unsigned_long_long: return "FT_unsigned_long_long"; + + case FT_int8: return "FT_int8"; + case FT_signed_int8: return "FT_signed_int8"; + case FT_unsigned_int8: return "FT_unsigned_int8"; + case FT_int16: return "FT_int16"; + case FT_signed_int16: return "FT_signed_int16"; + case FT_unsigned_int16: return "FT_unsigned_int16"; + case FT_int32: return "FT_int32"; + case FT_signed_int32: return "FT_signed_int32"; + case FT_unsigned_int32: return "FT_unsigned_int32"; + case FT_int64: return "FT_int64"; + case FT_signed_int64: return "FT_signed_int64"; + case FT_unsigned_int64: return "FT_signed_int64"; + + case FT_real32: return "FT_real32"; + case FT_real64: return "FT_real64"; + case FT_real96: return "FT_real96"; + case FT_real128: return "FT_real128"; + + default: return "FT_"; + } +} + +/* Determine the "ultimate origin" of a decl. The decl may be an + inlined instance of an inlined instance of a decl which is local + to an inline function, so we have to trace all of the way back + through the origin chain to find out what sort of node actually + served as the original seed for the given block. */ + +static tree +decl_ultimate_origin (decl) + register tree decl; +{ + register tree immediate_origin = DECL_ABSTRACT_ORIGIN (decl); + + if (immediate_origin == NULL) + return NULL; + else + { + register tree ret_val; + register tree lookahead = immediate_origin; + + do + { + ret_val = lookahead; + lookahead = DECL_ABSTRACT_ORIGIN (ret_val); + } + while (lookahead != NULL && lookahead != ret_val); + return ret_val; + } +} + +/* Determine the "ultimate origin" of a block. The block may be an + inlined instance of an inlined instance of a block which is local + to an inline function, so we have to trace all of the way back + through the origin chain to find out what sort of node actually + served as the original seed for the given block. */ + +static tree +block_ultimate_origin (block) + register tree block; +{ + register tree immediate_origin = BLOCK_ABSTRACT_ORIGIN (block); + + if (immediate_origin == NULL) + return NULL; + else + { + register tree ret_val; + register tree lookahead = immediate_origin; + + do + { + ret_val = lookahead; + lookahead = (TREE_CODE (ret_val) == BLOCK) + ? BLOCK_ABSTRACT_ORIGIN (ret_val) + : NULL; + } + while (lookahead != NULL && lookahead != ret_val); + return ret_val; + } +} + +static void +output_unsigned_leb128 (value) + register unsigned long value; +{ + register unsigned long orig_value = value; + + do + { + register unsigned byte = (value & 0x7f); + + value >>= 7; + if (value != 0) /* more bytes to follow */ + byte |= 0x80; + fprintf (asm_out_file, "\t%s\t0x%x", ASM_BYTE_OP, (unsigned) byte); + if (flag_verbose_asm && value == 0) + fprintf (asm_out_file, "\t%s ULEB128 number - value = %u", + ASM_COMMENT_START, orig_value); + fputc ('\n', asm_out_file); + } + while (value != 0); +} + +static void +output_signed_leb128 (value) + register long value; +{ + register long orig_value = value; + register int negative = (value < 0); + register int more; + + do + { + register unsigned byte = (value & 0x7f); + + value >>= 7; + if (negative) + value |= 0xfe000000; /* manually sign extend */ + if (((value == 0) && ((byte & 0x40) == 0)) + || ((value == -1) && ((byte & 0x40) == 1))) + more = 0; + else + { + byte |= 0x80; + more = 1; + } + fprintf (asm_out_file, "\t%s\t0x%x", ASM_BYTE_OP, (unsigned) byte); + if (flag_verbose_asm && more == 0) + fprintf (asm_out_file, "\t%s SLEB128 number - value = %d", + ASM_COMMENT_START, orig_value); + fputc ('\n', asm_out_file); + } + while (more); +} + +/**************** utility functions for attribute functions ******************/ + +/* Given a pointer to a BLOCK node return non-zero if (and only if) the + node in question represents the outermost pair of curly braces (i.e. + the "body block") of a function or method. + + For any BLOCK node representing a "body block" of a function or method, + the BLOCK_SUPERCONTEXT of the node will point to another BLOCK node + which represents the outermost (function) scope for the function or + method (i.e. the one which includes the formal parameters). The + BLOCK_SUPERCONTEXT of *that* node in turn will point to the relevant + FUNCTION_DECL node. +*/ + +inline int +is_body_block (stmt) + register tree stmt; +{ + if (TREE_CODE (stmt) == BLOCK) + { + register tree parent = BLOCK_SUPERCONTEXT (stmt); + + if (TREE_CODE (parent) == BLOCK) + { + register tree grandparent = BLOCK_SUPERCONTEXT (parent); + + if (TREE_CODE (grandparent) == FUNCTION_DECL) + return 1; + } + } + return 0; +} + +/* Given a pointer to a tree node for some type, return a Dwarf fundamental + type code for the given type. + + This routine must only be called for GCC type nodes that correspond to + Dwarf fundamental types. + + The current Dwarf draft specification calls for Dwarf fundamental types + to accurately reflect the fact that a given type was either a "plain" + integral type or an explicitly "signed" integral type. Unfortunately, + we can't always do this, because GCC may already have thrown away the + information about the precise way in which the type was originally + specified, as in: + + typedef signed int my_type; + + struct s { my_type f; }; + + Since we may be stuck here without enought information to do exactly + what is called for in the Dwarf draft specification, we do the best + that we can under the circumstances and always use the "plain" integral + fundamental type codes for int, short, and long types. That's probably + good enough. The additional accuracy called for in the current DWARF + draft specification is probably never even useful in practice. */ + +static int +fundamental_type_code (type) + register tree type; +{ + if (TREE_CODE (type) == ERROR_MARK) + return 0; + + switch (TREE_CODE (type)) + { + case ERROR_MARK: + return FT_void; + + case VOID_TYPE: + return FT_void; + + case INTEGER_TYPE: + /* Carefully distinguish all the standard types of C, + without messing up if the language is not C. + Note that we check only for the names that contain spaces; + other names might occur by coincidence in other languages. */ + if (TYPE_NAME (type) != 0 + && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL + && DECL_NAME (TYPE_NAME (type)) != 0 + && TREE_CODE (DECL_NAME (TYPE_NAME (type))) == IDENTIFIER_NODE) + { + char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))); + + if (!strcmp (name, "unsigned char")) + return FT_unsigned_char; + if (!strcmp (name, "signed char")) + return FT_signed_char; + if (!strcmp (name, "unsigned int")) + return FT_unsigned_integer; + if (!strcmp (name, "short int")) + return FT_short; + if (!strcmp (name, "short unsigned int")) + return FT_unsigned_short; + if (!strcmp (name, "long int")) + return FT_long; + if (!strcmp (name, "long unsigned int")) + return FT_unsigned_long; + if (!strcmp (name, "long long int")) + return FT_long_long; /* Not grok'ed by svr4 SDB */ + if (!strcmp (name, "long long unsigned int")) + return FT_unsigned_long_long; /* Not grok'ed by svr4 SDB */ + } + + /* Most integer types will be sorted out above, however, for the + sake of special `array index' integer types, the following code + is also provided. */ + + if (TYPE_PRECISION (type) == INT_TYPE_SIZE) + return (TREE_UNSIGNED (type) ? FT_unsigned_integer : FT_integer); + + if (TYPE_PRECISION (type) == LONG_TYPE_SIZE) + return (TREE_UNSIGNED (type) ? FT_unsigned_long : FT_long); + + if (TYPE_PRECISION (type) == LONG_LONG_TYPE_SIZE) + return (TREE_UNSIGNED (type) ? FT_unsigned_long_long : FT_long_long); + + if (TYPE_PRECISION (type) == SHORT_TYPE_SIZE) + return (TREE_UNSIGNED (type) ? FT_unsigned_short : FT_short); + + if (TYPE_PRECISION (type) == CHAR_TYPE_SIZE) + return (TREE_UNSIGNED (type) ? FT_unsigned_char : FT_char); + + abort (); + + case REAL_TYPE: + /* Carefully distinguish all the standard types of C, + without messing up if the language is not C. */ + if (TYPE_NAME (type) != 0 + && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL + && DECL_NAME (TYPE_NAME (type)) != 0 + && TREE_CODE (DECL_NAME (TYPE_NAME (type))) == IDENTIFIER_NODE) + { + char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))); + + /* Note that here we can run afowl of a serious bug in "classic" + svr4 SDB debuggers. They don't seem to understand the + FT_ext_prec_float type (even though they should). */ + + if (!strcmp (name, "long double")) + return FT_ext_prec_float; + } + + if (TYPE_PRECISION (type) == DOUBLE_TYPE_SIZE) + return FT_dbl_prec_float; + if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) + return FT_float; + + /* Note that here we can run afowl of a serious bug in "classic" + svr4 SDB debuggers. They don't seem to understand the + FT_ext_prec_float type (even though they should). */ + + if (TYPE_PRECISION (type) == LONG_DOUBLE_TYPE_SIZE) + return FT_ext_prec_float; + abort (); + + case COMPLEX_TYPE: + return FT_complex; /* GNU FORTRAN COMPLEX type. */ + + case CHAR_TYPE: + return FT_char; /* GNU Pascal CHAR type. Not used in C. */ + + case BOOLEAN_TYPE: + return FT_boolean; /* GNU FORTRAN BOOLEAN type. */ + + default: + abort (); /* No other TREE_CODEs are Dwarf fundamental types. */ + } + return 0; +} + +/* Given a pointer to an arbitrary ..._TYPE tree node, return a pointer to + the Dwarf "root" type for the given input type. The Dwarf "root" type + of a given type is generally the same as the given type, except that if + the given type is a pointer or reference type, then the root type of + the given type is the root type of the "basis" type for the pointer or + reference type. (This definition of the "root" type is recursive.) + Also, the root type of a `const' qualified type or a `volatile' + qualified type is the root type of the given type without the + qualifiers. */ + +static tree +root_type (type) + register tree type; +{ + if (TREE_CODE (type) == ERROR_MARK) + return error_mark_node; + + switch (TREE_CODE (type)) + { + case ERROR_MARK: + return error_mark_node; + + case POINTER_TYPE: + case REFERENCE_TYPE: + return type_main_variant (root_type (TREE_TYPE (type))); + + default: + return type_main_variant (type); + } +} + +/* Given a pointer to an arbitrary ..._TYPE tree node, write out a sequence + of zero or more Dwarf "type-modifier" bytes applicable to the type. */ + +static void +write_modifier_bytes (type, decl_const, decl_volatile) + register tree type; + register int decl_const; + register int decl_volatile; +{ + if (TREE_CODE (type) == ERROR_MARK) + return; + + if (TYPE_READONLY (type) || decl_const) + ASM_OUTPUT_DWARF_TYPE_MODIFIER (asm_out_file, MOD_const); + if (TYPE_VOLATILE (type) || decl_volatile) + ASM_OUTPUT_DWARF_TYPE_MODIFIER (asm_out_file, MOD_volatile); + switch (TREE_CODE (type)) + { + case POINTER_TYPE: + ASM_OUTPUT_DWARF_TYPE_MODIFIER (asm_out_file, MOD_pointer_to); + write_modifier_bytes (TREE_TYPE (type), 0, 0); + return; + + case REFERENCE_TYPE: + ASM_OUTPUT_DWARF_TYPE_MODIFIER (asm_out_file, MOD_reference_to); + write_modifier_bytes (TREE_TYPE (type), 0, 0); + return; + + case ERROR_MARK: + default: + return; + } +} + +/* Given a pointer to an arbitrary ..._TYPE tree node, return non-zero if the + given input type is a Dwarf "fundamental" type. Otherwise return zero. */ + +inline int +type_is_fundamental (type) + register tree type; +{ + switch (TREE_CODE (type)) + { + case ERROR_MARK: + case VOID_TYPE: + case INTEGER_TYPE: + case REAL_TYPE: + case COMPLEX_TYPE: + case BOOLEAN_TYPE: + case CHAR_TYPE: + return 1; + + case SET_TYPE: + case ARRAY_TYPE: + case RECORD_TYPE: + case UNION_TYPE: + case QUAL_UNION_TYPE: + case ENUMERAL_TYPE: + case FUNCTION_TYPE: + case METHOD_TYPE: + case POINTER_TYPE: + case REFERENCE_TYPE: + case STRING_TYPE: + case FILE_TYPE: + case OFFSET_TYPE: + case LANG_TYPE: + return 0; + + default: + abort (); + } + return 0; +} + +/* Given a pointer to some ..._DECL tree node, generate an assembly language + equate directive which will associate a symbolic name with the current DIE. + + The name used is an artificial label generated from the DECL_UID number + associated with the given decl node. The name it gets equated to is the + symbolic label that we (previously) output at the start of the DIE that + we are currently generating. + + Calling this function while generating some "decl related" form of DIE + makes it possible to later refer to the DIE which represents the given + decl simply by re-generating the symbolic name from the ..._DECL node's + UID number. */ + +static void +equate_decl_number_to_die_number (decl) + register tree decl; +{ + /* In the case where we are generating a DIE for some ..._DECL node + which represents either some inline function declaration or some + entity declared within an inline function declaration/definition, + setup a symbolic name for the current DIE so that we have a name + for this DIE that we can easily refer to later on within + AT_abstract_origin attributes. */ + + char decl_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char die_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + sprintf (decl_label, DECL_NAME_FMT, DECL_UID (decl)); + sprintf (die_label, DIE_BEGIN_LABEL_FMT, current_dienum); + ASM_OUTPUT_DEF (asm_out_file, decl_label, die_label); +} + +/* Given a pointer to some ..._TYPE tree node, generate an assembly language + equate directive which will associate a symbolic name with the current DIE. + + The name used is an artificial label generated from the TYPE_UID number + associated with the given type node. The name it gets equated to is the + symbolic label that we (previously) output at the start of the DIE that + we are currently generating. + + Calling this function while generating some "type related" form of DIE + makes it easy to later refer to the DIE which represents the given type + simply by re-generating the alternative name from the ..._TYPE node's + UID number. */ + +inline void +equate_type_number_to_die_number (type) + register tree type; +{ + char type_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char die_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + /* We are generating a DIE to represent the main variant of this type + (i.e the type without any const or volatile qualifiers) so in order + to get the equate to come out right, we need to get the main variant + itself here. */ + + type = type_main_variant (type); + + sprintf (type_label, TYPE_NAME_FMT, TYPE_UID (type)); + sprintf (die_label, DIE_BEGIN_LABEL_FMT, current_dienum); + ASM_OUTPUT_DEF (asm_out_file, type_label, die_label); +} + +static void +output_reg_number (rtl) + register rtx rtl; +{ + register unsigned regno = REGNO (rtl); + + if (regno >= FIRST_PSEUDO_REGISTER) + { + warning_with_decl (dwarf_last_decl, "internal regno botch: regno = %d\n", + regno); + regno = 0; + } + fprintf (asm_out_file, "\t%s\t0x%x", + UNALIGNED_INT_ASM_OP, DBX_REGISTER_NUMBER (regno)); + if (flag_verbose_asm) + { + fprintf (asm_out_file, "\t%s ", ASM_COMMENT_START); + PRINT_REG (rtl, 0, asm_out_file); + } + fputc ('\n', asm_out_file); +} + +/* The following routine is a nice and simple transducer. It converts the + RTL for a variable or parameter (resident in memory) into an equivalent + Dwarf representation of a mechanism for getting the address of that same + variable onto the top of a hypothetical "address evaluation" stack. + + When creating memory location descriptors, we are effectively trans- + forming the RTL for a memory-resident object into its Dwarf postfix + expression equivalent. This routine just recursively descends an + RTL tree, turning it into Dwarf postfix code as it goes. */ + +static void +output_mem_loc_descriptor (rtl) + register rtx rtl; +{ + /* Note that for a dynamically sized array, the location we will + generate a description of here will be the lowest numbered location + which is actually within the array. That's *not* necessarily the + same as the zeroth element of the array. */ + + switch (GET_CODE (rtl)) + { + case SUBREG: + + /* The case of a subreg may arise when we have a local (register) + variable or a formal (register) parameter which doesn't quite + fill up an entire register. For now, just assume that it is + legitimate to make the Dwarf info refer to the whole register + which contains the given subreg. */ + + rtl = XEXP (rtl, 0); + /* Drop thru. */ + + case REG: + + /* Whenever a register number forms a part of the description of + the method for calculating the (dynamic) address of a memory + resident object, DWARF rules require the register number to + be referred to as a "base register". This distinction is not + based in any way upon what category of register the hardware + believes the given register belongs to. This is strictly + DWARF terminology we're dealing with here. + + Note that in cases where the location of a memory-resident data + object could be expressed as: + + OP_ADD (OP_BASEREG (basereg), OP_CONST (0)) + + the actual DWARF location descriptor that we generate may just + be OP_BASEREG (basereg). This may look deceptively like the + object in question was allocated to a register (rather than + in memory) so DWARF consumers need to be aware of the subtle + distinction between OP_REG and OP_BASEREG. */ + + ASM_OUTPUT_DWARF_STACK_OP (asm_out_file, OP_BASEREG); + output_reg_number (rtl); + break; + + case MEM: + output_mem_loc_descriptor (XEXP (rtl, 0)); + ASM_OUTPUT_DWARF_STACK_OP (asm_out_file, OP_DEREF4); + break; + + case CONST: + case SYMBOL_REF: + ASM_OUTPUT_DWARF_STACK_OP (asm_out_file, OP_ADDR); + ASM_OUTPUT_DWARF_ADDR_CONST (asm_out_file, rtl); + break; + + case PLUS: + output_mem_loc_descriptor (XEXP (rtl, 0)); + output_mem_loc_descriptor (XEXP (rtl, 1)); + ASM_OUTPUT_DWARF_STACK_OP (asm_out_file, OP_ADD); + break; + + case CONST_INT: + ASM_OUTPUT_DWARF_STACK_OP (asm_out_file, OP_CONST); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, INTVAL (rtl)); + break; + + default: + abort (); + } +} + +/* Output a proper Dwarf location descriptor for a variable or parameter + which is either allocated in a register or in a memory location. For + a register, we just generate an OP_REG and the register number. For a + memory location we provide a Dwarf postfix expression describing how to + generate the (dynamic) address of the object onto the address stack. */ + +static void +output_loc_descriptor (rtl) + register rtx rtl; +{ + switch (GET_CODE (rtl)) + { + case SUBREG: + + /* The case of a subreg may arise when we have a local (register) + variable or a formal (register) parameter which doesn't quite + fill up an entire register. For now, just assume that it is + legitimate to make the Dwarf info refer to the whole register + which contains the given subreg. */ + + rtl = XEXP (rtl, 0); + /* Drop thru. */ + + case REG: + ASM_OUTPUT_DWARF_STACK_OP (asm_out_file, OP_REG); + output_reg_number (rtl); + break; + + case MEM: + output_mem_loc_descriptor (XEXP (rtl, 0)); + break; + + default: + abort (); /* Should never happen */ + } +} + +/* Given a tree node describing an array bound (either lower or upper) + output a representation for that bound. */ + +static void +output_bound_representation (bound, dim_num, u_or_l) + register tree bound; + register unsigned dim_num; /* For multi-dimensional arrays. */ + register char u_or_l; /* Designates upper or lower bound. */ +{ + switch (TREE_CODE (bound)) + { + + case ERROR_MARK: + return; + + /* All fixed-bounds are represented by INTEGER_CST nodes. */ + + case INTEGER_CST: + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, + (unsigned) TREE_INT_CST_LOW (bound)); + break; + + /* Dynamic bounds may be represented by NOP_EXPR nodes containing + SAVE_EXPR nodes. */ + + case NOP_EXPR: + bound = TREE_OPERAND (bound, 0); + /* ... fall thru... */ + + case SAVE_EXPR: + { + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + sprintf (begin_label, BOUND_BEGIN_LABEL_FMT, + current_dienum, dim_num, u_or_l); + + sprintf (end_label, BOUND_END_LABEL_FMT, + current_dienum, dim_num, u_or_l); + + ASM_OUTPUT_DWARF_DELTA2 (asm_out_file, end_label, begin_label); + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + + /* If we are working on a bound for a dynamic dimension in C, + the dynamic dimension in question had better have a static + (zero) lower bound and a dynamic *upper* bound. */ + + if (u_or_l != 'u') + abort (); + + /* If optimization is turned on, the SAVE_EXPRs that describe + how to access the upper bound values are essentially bogus. + They only describe (at best) how to get at these values at + the points in the generated code right after they have just + been computed. Worse yet, in the typical case, the upper + bound values will not even *be* computed in the optimized + code, so these SAVE_EXPRs are entirely bogus. + + In order to compensate for this fact, we check here to see + if optimization is enabled, and if so, we effectively create + an empty location description for the (unknown and unknowable) + upper bound. + + This should not cause too much trouble for existing (stupid?) + debuggers because they have to deal with empty upper bounds + location descriptions anyway in order to be able to deal with + incomplete array types. + + Of course an intelligent debugger (GDB?) should be able to + comprehend that a missing upper bound specification in a + array type used for a storage class `auto' local array variable + indicates that the upper bound is both unknown (at compile- + time) and unknowable (at run-time) due to optimization. + */ + + if (! optimize) + output_loc_descriptor + (eliminate_regs (SAVE_EXPR_RTL (bound), 0, NULL_RTX)); + + ASM_OUTPUT_LABEL (asm_out_file, end_label); + } + break; + + default: + abort (); + } +} + +/* Recursive function to output a sequence of value/name pairs for + enumeration constants in reversed order. This is called from + enumeration_type_die. */ + +static void +output_enumeral_list (link) + register tree link; +{ + if (link) + { + output_enumeral_list (TREE_CHAIN (link)); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, + (unsigned) TREE_INT_CST_LOW (TREE_VALUE (link))); + ASM_OUTPUT_DWARF_STRING (asm_out_file, + IDENTIFIER_POINTER (TREE_PURPOSE (link))); + } +} + +/* Given an unsigned value, round it up to the lowest multiple of `boundary' + which is not less than the value itself. */ + +inline unsigned +ceiling (value, boundary) + register unsigned value; + register unsigned boundary; +{ + return (((value + boundary - 1) / boundary) * boundary); +} + +/* Given a pointer to what is assumed to be a FIELD_DECL node, return a + pointer to the declared type for the relevant field variable, or return + `integer_type_node' if the given node turns out to be an ERROR_MARK node. */ + +inline tree +field_type (decl) + register tree decl; +{ + register tree type; + + if (TREE_CODE (decl) == ERROR_MARK) + return integer_type_node; + + type = DECL_BIT_FIELD_TYPE (decl); + if (type == NULL) + type = TREE_TYPE (decl); + return type; +} + +/* Given a pointer to a tree node, assumed to be some kind of a ..._TYPE + node, return the alignment in bits for the type, or else return + BITS_PER_WORD if the node actually turns out to be an ERROR_MARK node. */ + +inline unsigned +simple_type_align_in_bits (type) + register tree type; +{ + return (TREE_CODE (type) != ERROR_MARK) ? TYPE_ALIGN (type) : BITS_PER_WORD; +} + +/* Given a pointer to a tree node, assumed to be some kind of a ..._TYPE + node, return the size in bits for the type if it is a constant, or + else return the alignment for the type if the type's size is not + constant, or else return BITS_PER_WORD if the type actually turns out + to be an ERROR_MARK node. */ + +inline unsigned +simple_type_size_in_bits (type) + register tree type; +{ + if (TREE_CODE (type) == ERROR_MARK) + return BITS_PER_WORD; + else + { + register tree type_size_tree = TYPE_SIZE (type); + + if (TREE_CODE (type_size_tree) != INTEGER_CST) + return TYPE_ALIGN (type); + + return (unsigned) TREE_INT_CST_LOW (type_size_tree); + } +} + +/* Given a pointer to what is assumed to be a FIELD_DECL node, compute and + return the byte offset of the lowest addressed byte of the "containing + object" for the given FIELD_DECL, or return 0 if we are unable to deter- + mine what that offset is, either because the argument turns out to be a + pointer to an ERROR_MARK node, or because the offset is actually variable. + (We can't handle the latter case just yet.) */ + +static unsigned +field_byte_offset (decl) + register tree decl; +{ + register unsigned type_align_in_bytes; + register unsigned type_align_in_bits; + register unsigned type_size_in_bits; + register unsigned object_offset_in_align_units; + register unsigned object_offset_in_bits; + register unsigned object_offset_in_bytes; + register tree type; + register tree bitpos_tree; + register tree field_size_tree; + register unsigned bitpos_int; + register unsigned deepest_bitpos; + register unsigned field_size_in_bits; + + if (TREE_CODE (decl) == ERROR_MARK) + return 0; + + if (TREE_CODE (decl) != FIELD_DECL) + abort (); + + type = field_type (decl); + + bitpos_tree = DECL_FIELD_BITPOS (decl); + field_size_tree = DECL_SIZE (decl); + + /* We cannot yet cope with fields whose positions or sizes are variable, + so for now, when we see such things, we simply return 0. Someday, + we may be able to handle such cases, but it will be damn difficult. */ + + if (TREE_CODE (bitpos_tree) != INTEGER_CST) + return 0; + bitpos_int = (unsigned) TREE_INT_CST_LOW (bitpos_tree); + + if (TREE_CODE (field_size_tree) != INTEGER_CST) + return 0; + field_size_in_bits = (unsigned) TREE_INT_CST_LOW (field_size_tree); + + type_size_in_bits = simple_type_size_in_bits (type); + + type_align_in_bits = simple_type_align_in_bits (type); + type_align_in_bytes = type_align_in_bits / BITS_PER_UNIT; + + /* Note that the GCC front-end doesn't make any attempt to keep track + of the starting bit offset (relative to the start of the containing + structure type) of the hypothetical "containing object" for a bit- + field. Thus, when computing the byte offset value for the start of + the "containing object" of a bit-field, we must deduce this infor- + mation on our own. + + This can be rather tricky to do in some cases. For example, handling + the following structure type definition when compiling for an i386/i486 + target (which only aligns long long's to 32-bit boundaries) can be very + tricky: + + struct S { + int field1; + long long field2:31; + }; + + Fortunately, there is a simple rule-of-thumb which can be used in such + cases. When compiling for an i386/i486, GCC will allocate 8 bytes for + the structure shown above. It decides to do this based upon one simple + rule for bit-field allocation. Quite simply, GCC allocates each "con- + taining object" for each bit-field at the first (i.e. lowest addressed) + legitimate alignment boundary (based upon the required minimum alignment + for the declared type of the field) which it can possibly use, subject + to the condition that there is still enough available space remaining + in the containing object (when allocated at the selected point) to + fully accommodate all of the bits of the bit-field itself. + + This simple rule makes it obvious why GCC allocates 8 bytes for each + object of the structure type shown above. When looking for a place to + allocate the "containing object" for `field2', the compiler simply tries + to allocate a 64-bit "containing object" at each successive 32-bit + boundary (starting at zero) until it finds a place to allocate that 64- + bit field such that at least 31 contiguous (and previously unallocated) + bits remain within that selected 64 bit field. (As it turns out, for + the example above, the compiler finds that it is OK to allocate the + "containing object" 64-bit field at bit-offset zero within the + structure type.) + + Here we attempt to work backwards from the limited set of facts we're + given, and we try to deduce from those facts, where GCC must have + believed that the containing object started (within the structure type). + + The value we deduce is then used (by the callers of this routine) to + generate AT_location and AT_bit_offset attributes for fields (both + bit-fields and, in the case of AT_location, regular fields as well). + */ + + /* Figure out the bit-distance from the start of the structure to the + "deepest" bit of the bit-field. */ + deepest_bitpos = bitpos_int + field_size_in_bits; + + /* This is the tricky part. Use some fancy footwork to deduce where the + lowest addressed bit of the containing object must be. */ + object_offset_in_bits + = ceiling (deepest_bitpos, type_align_in_bits) - type_size_in_bits; + + /* Compute the offset of the containing object in "alignment units". */ + object_offset_in_align_units = object_offset_in_bits / type_align_in_bits; + + /* Compute the offset of the containing object in bytes. */ + object_offset_in_bytes = object_offset_in_align_units * type_align_in_bytes; + + return object_offset_in_bytes; +} + +/****************************** attributes *********************************/ + +/* The following routines are responsible for writing out the various types + of Dwarf attributes (and any following data bytes associated with them). + These routines are listed in order based on the numerical codes of their + associated attributes. */ + +/* Generate an AT_sibling attribute. */ + +inline void +sibling_attribute () +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_sibling); + sprintf (label, DIE_BEGIN_LABEL_FMT, NEXT_DIE_NUM); + ASM_OUTPUT_DWARF_REF (asm_out_file, label); +} + +/* Output the form of location attributes suitable for whole variables and + whole parameters. Note that the location attributes for struct fields + are generated by the routine `data_member_location_attribute' below. */ + +static void +location_attribute (rtl) + register rtx rtl; +{ + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_location); + sprintf (begin_label, LOC_BEGIN_LABEL_FMT, current_dienum); + sprintf (end_label, LOC_END_LABEL_FMT, current_dienum); + ASM_OUTPUT_DWARF_DELTA2 (asm_out_file, end_label, begin_label); + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + + /* Handle a special case. If we are about to output a location descriptor + for a variable or parameter which has been optimized out of existence, + don't do that. Instead we output a zero-length location descriptor + value as part of the location attribute. + + A variable which has been optimized out of existence will have a + DECL_RTL value which denotes a pseudo-reg. + + Currently, in some rare cases, variables can have DECL_RTL values + which look like (MEM (REG pseudo-reg#)). These cases are due to + bugs elsewhere in the compiler. We treat such cases + as if the variable(s) in question had been optimized out of existence. + + Note that in all cases where we wish to express the fact that a + variable has been optimized out of existence, we do not simply + suppress the generation of the entire location attribute because + the absence of a location attribute in certain kinds of DIEs is + used to indicate something else entirely... i.e. that the DIE + represents an object declaration, but not a definition. So sayeth + the PLSIG. + */ + + if (! is_pseudo_reg (rtl) + && (GET_CODE (rtl) != MEM || ! is_pseudo_reg (XEXP (rtl, 0)))) + output_loc_descriptor (eliminate_regs (rtl, 0, NULL_RTX)); + + ASM_OUTPUT_LABEL (asm_out_file, end_label); +} + +/* Output the specialized form of location attribute used for data members + of struct and union types. + + In the special case of a FIELD_DECL node which represents a bit-field, + the "offset" part of this special location descriptor must indicate the + distance in bytes from the lowest-addressed byte of the containing + struct or union type to the lowest-addressed byte of the "containing + object" for the bit-field. (See the `field_byte_offset' function above.) + + For any given bit-field, the "containing object" is a hypothetical + object (of some integral or enum type) within which the given bit-field + lives. The type of this hypothetical "containing object" is always the + same as the declared type of the individual bit-field itself (for GCC + anyway... the DWARF spec doesn't actually mandate this). + + Note that it is the size (in bytes) of the hypothetical "containing + object" which will be given in the AT_byte_size attribute for this + bit-field. (See the `byte_size_attribute' function below.) It is + also used when calculating the value of the AT_bit_offset attribute. + (See the `bit_offset_attribute' function below.) +*/ + +static void +data_member_location_attribute (decl) + register tree decl; +{ + register unsigned object_offset_in_bytes = field_byte_offset (decl); + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_location); + sprintf (begin_label, LOC_BEGIN_LABEL_FMT, current_dienum); + sprintf (end_label, LOC_END_LABEL_FMT, current_dienum); + ASM_OUTPUT_DWARF_DELTA2 (asm_out_file, end_label, begin_label); + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + ASM_OUTPUT_DWARF_STACK_OP (asm_out_file, OP_CONST); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, object_offset_in_bytes); + ASM_OUTPUT_DWARF_STACK_OP (asm_out_file, OP_ADD); + ASM_OUTPUT_LABEL (asm_out_file, end_label); +} + +/* Output an AT_const_value attribute for a variable or a parameter which + does not have a "location" either in memory or in a register. These + things can arise in GNU C when a constant is passed as an actual + parameter to an inlined function. They can also arise in C++ where + declared constants do not necessarily get memory "homes". */ + +static void +const_value_attribute (rtl) + register rtx rtl; +{ + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_const_value_block4); + sprintf (begin_label, LOC_BEGIN_LABEL_FMT, current_dienum); + sprintf (end_label, LOC_END_LABEL_FMT, current_dienum); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, end_label, begin_label); + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + + switch (GET_CODE (rtl)) + { + case CONST_INT: + /* Note that a CONST_INT rtx could represent either an integer or + a floating-point constant. A CONST_INT is used whenever the + constant will fit into a single word. In all such cases, the + original mode of the constant value is wiped out, and the + CONST_INT rtx is assigned VOIDmode. Since we no longer have + precise mode information for these constants, we always just + output them using 4 bytes. */ + + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, (unsigned) INTVAL (rtl)); + break; + + case CONST_DOUBLE: + /* Note that a CONST_DOUBLE rtx could represent either an integer + or a floating-point constant. A CONST_DOUBLE is used whenever + the constant requires more than one word in order to be adequately + represented. In all such cases, the original mode of the constant + value is preserved as the mode of the CONST_DOUBLE rtx, but for + simplicity we always just output CONST_DOUBLEs using 8 bytes. */ + + ASM_OUTPUT_DWARF_DATA8 (asm_out_file, + (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (rtl), + (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (rtl)); + break; + + case CONST_STRING: + ASM_OUTPUT_DWARF_STRING (asm_out_file, XSTR (rtl, 0)); + break; + + case SYMBOL_REF: + case LABEL_REF: + case CONST: + ASM_OUTPUT_DWARF_ADDR_CONST (asm_out_file, rtl); + break; + + case PLUS: + /* In cases where an inlined instance of an inline function is passed + the address of an `auto' variable (which is local to the caller) + we can get a situation where the DECL_RTL of the artificial + local variable (for the inlining) which acts as a stand-in for + the corresponding formal parameter (of the inline function) + will look like (plus:SI (reg:SI FRAME_PTR) (const_int ...)). + This is not exactly a compile-time constant expression, but it + isn't the address of the (artificial) local variable either. + Rather, it represents the *value* which the artificial local + variable always has during its lifetime. We currently have no + way to represent such quasi-constant values in Dwarf, so for now + we just punt and generate an AT_const_value attribute with form + FORM_BLOCK4 and a length of zero. */ + break; + + default: + abort (); /* No other kinds of rtx should be possible here. */ + } + + ASM_OUTPUT_LABEL (asm_out_file, end_label); +} + +/* Generate *either* an AT_location attribute or else an AT_const_value + data attribute for a variable or a parameter. We generate the + AT_const_value attribute only in those cases where the given + variable or parameter does not have a true "location" either in + memory or in a register. This can happen (for example) when a + constant is passed as an actual argument in a call to an inline + function. (It's possible that these things can crop up in other + ways also.) Note that one type of constant value which can be + passed into an inlined function is a constant pointer. This can + happen for example if an actual argument in an inlined function + call evaluates to a compile-time constant address. */ + +static void +location_or_const_value_attribute (decl) + register tree decl; +{ + register rtx rtl; + + if (TREE_CODE (decl) == ERROR_MARK) + return; + + if ((TREE_CODE (decl) != VAR_DECL) && (TREE_CODE (decl) != PARM_DECL)) + { + /* Should never happen. */ + abort (); + return; + } + + /* Here we have to decide where we are going to say the parameter "lives" + (as far as the debugger is concerned). We only have a couple of choices. + GCC provides us with DECL_RTL and with DECL_INCOMING_RTL. DECL_RTL + normally indicates where the parameter lives during most of the activa- + tion of the function. If optimization is enabled however, this could + be either NULL or else a pseudo-reg. Both of those cases indicate that + the parameter doesn't really live anywhere (as far as the code generation + parts of GCC are concerned) during most of the function's activation. + That will happen (for example) if the parameter is never referenced + within the function. + + We could just generate a location descriptor here for all non-NULL + non-pseudo values of DECL_RTL and ignore all of the rest, but we can + be a little nicer than that if we also consider DECL_INCOMING_RTL in + cases where DECL_RTL is NULL or is a pseudo-reg. + + Note however that we can only get away with using DECL_INCOMING_RTL as + a backup substitute for DECL_RTL in certain limited cases. In cases + where DECL_ARG_TYPE(decl) indicates the same type as TREE_TYPE(decl) + we can be sure that the parameter was passed using the same type as it + is declared to have within the function, and that its DECL_INCOMING_RTL + points us to a place where a value of that type is passed. In cases + where DECL_ARG_TYPE(decl) and TREE_TYPE(decl) are different types + however, we cannot (in general) use DECL_INCOMING_RTL as a backup + substitute for DECL_RTL because in these cases, DECL_INCOMING_RTL + points us to a value of some type which is *different* from the type + of the parameter itself. Thus, if we tried to use DECL_INCOMING_RTL + to generate a location attribute in such cases, the debugger would + end up (for example) trying to fetch a `float' from a place which + actually contains the first part of a `double'. That would lead to + really incorrect and confusing output at debug-time, and we don't + want that now do we? + + So in general, we DO NOT use DECL_INCOMING_RTL as a backup for DECL_RTL + in cases where DECL_ARG_TYPE(decl) != TREE_TYPE(decl). There are a + couple of cute exceptions however. On little-endian machines we can + get away with using DECL_INCOMING_RTL even when DECL_ARG_TYPE(decl) is + not the same as TREE_TYPE(decl) but only when DECL_ARG_TYPE(decl) is + an integral type which is smaller than TREE_TYPE(decl). These cases + arise when (on a little-endian machine) a non-prototyped function has + a parameter declared to be of type `short' or `char'. In such cases, + TREE_TYPE(decl) will be `short' or `char', DECL_ARG_TYPE(decl) will be + `int', and DECL_INCOMING_RTL will point to the lowest-order byte of the + passed `int' value. If the debugger then uses that address to fetch a + `short' or a `char' (on a little-endian machine) the result will be the + correct data, so we allow for such exceptional cases below. + + Note that our goal here is to describe the place where the given formal + parameter lives during most of the function's activation (i.e. between + the end of the prologue and the start of the epilogue). We'll do that + as best as we can. Note however that if the given formal parameter is + modified sometime during the execution of the function, then a stack + backtrace (at debug-time) will show the function as having been called + with the *new* value rather than the value which was originally passed + in. This happens rarely enough that it is not a major problem, but it + *is* a problem, and I'd like to fix it. A future version of dwarfout.c + may generate two additional attributes for any given TAG_formal_parameter + DIE which will describe the "passed type" and the "passed location" for + the given formal parameter in addition to the attributes we now generate + to indicate the "declared type" and the "active location" for each + parameter. This additional set of attributes could be used by debuggers + for stack backtraces. + + Separately, note that sometimes DECL_RTL can be NULL and DECL_INCOMING_RTL + can be NULL also. This happens (for example) for inlined-instances of + inline function formal parameters which are never referenced. This really + shouldn't be happening. All PARM_DECL nodes should get valid non-NULL + DECL_INCOMING_RTL values, but integrate.c doesn't currently generate + these values for inlined instances of inline function parameters, so + when we see such cases, we are just SOL (shit-out-of-luck) for the time + being (until integrate.c gets fixed). + */ + + /* Use DECL_RTL as the "location" unless we find something better. */ + rtl = DECL_RTL (decl); + + if (TREE_CODE (decl) == PARM_DECL) + if (rtl == NULL_RTX || is_pseudo_reg (rtl)) + { + /* This decl represents a formal parameter which was optimized out. */ + register tree declared_type = type_main_variant (TREE_TYPE (decl)); + register tree passed_type = type_main_variant (DECL_ARG_TYPE (decl)); + + /* Note that DECL_INCOMING_RTL may be NULL in here, but we handle + *all* cases where (rtl == NULL_RTX) just below. */ + + if (declared_type == passed_type) + rtl = DECL_INCOMING_RTL (decl); +#if (BYTES_BIG_ENDIAN == 0) + else + if (TREE_CODE (declared_type) == INTEGER_TYPE) + if (TYPE_SIZE (declared_type) <= TYPE_SIZE (passed_type)) + rtl = DECL_INCOMING_RTL (decl); +#endif /* (BYTES_BIG_ENDIAN == 0) */ + } + + if (rtl == NULL_RTX) + return; + + switch (GET_CODE (rtl)) + { + case CONST_INT: + case CONST_DOUBLE: + case CONST_STRING: + case SYMBOL_REF: + case LABEL_REF: + case CONST: + case PLUS: /* DECL_RTL could be (plus (reg ...) (const_int ...)) */ + const_value_attribute (rtl); + break; + + case MEM: + case REG: + case SUBREG: + location_attribute (rtl); + break; + + default: + abort (); /* Should never happen. */ + } +} + +/* Generate an AT_name attribute given some string value to be included as + the value of the attribute. */ + +inline void +name_attribute (name_string) + register char *name_string; +{ + if (name_string && *name_string) + { + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_name); + ASM_OUTPUT_DWARF_STRING (asm_out_file, name_string); + } +} + +inline void +fund_type_attribute (ft_code) + register unsigned ft_code; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_fund_type); + ASM_OUTPUT_DWARF_FUND_TYPE (asm_out_file, ft_code); +} + +static void +mod_fund_type_attribute (type, decl_const, decl_volatile) + register tree type; + register int decl_const; + register int decl_volatile; +{ + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_mod_fund_type); + sprintf (begin_label, MT_BEGIN_LABEL_FMT, current_dienum); + sprintf (end_label, MT_END_LABEL_FMT, current_dienum); + ASM_OUTPUT_DWARF_DELTA2 (asm_out_file, end_label, begin_label); + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + write_modifier_bytes (type, decl_const, decl_volatile); + ASM_OUTPUT_DWARF_FUND_TYPE (asm_out_file, + fundamental_type_code (root_type (type))); + ASM_OUTPUT_LABEL (asm_out_file, end_label); +} + +inline void +user_def_type_attribute (type) + register tree type; +{ + char ud_type_name[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_user_def_type); + sprintf (ud_type_name, TYPE_NAME_FMT, TYPE_UID (type)); + ASM_OUTPUT_DWARF_REF (asm_out_file, ud_type_name); +} + +static void +mod_u_d_type_attribute (type, decl_const, decl_volatile) + register tree type; + register int decl_const; + register int decl_volatile; +{ + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char ud_type_name[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_mod_u_d_type); + sprintf (begin_label, MT_BEGIN_LABEL_FMT, current_dienum); + sprintf (end_label, MT_END_LABEL_FMT, current_dienum); + ASM_OUTPUT_DWARF_DELTA2 (asm_out_file, end_label, begin_label); + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + write_modifier_bytes (type, decl_const, decl_volatile); + sprintf (ud_type_name, TYPE_NAME_FMT, TYPE_UID (root_type (type))); + ASM_OUTPUT_DWARF_REF (asm_out_file, ud_type_name); + ASM_OUTPUT_LABEL (asm_out_file, end_label); +} + +#ifdef USE_ORDERING_ATTRIBUTE +inline void +ordering_attribute (ordering) + register unsigned ordering; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_ordering); + ASM_OUTPUT_DWARF_DATA2 (asm_out_file, ordering); +} +#endif /* defined(USE_ORDERING_ATTRIBUTE) */ + +/* Note that the block of subscript information for an array type also + includes information about the element type of type given array type. */ + +static void +subscript_data_attribute (type) + register tree type; +{ + register unsigned dimension_number; + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_subscr_data); + sprintf (begin_label, SS_BEGIN_LABEL_FMT, current_dienum); + sprintf (end_label, SS_END_LABEL_FMT, current_dienum); + ASM_OUTPUT_DWARF_DELTA2 (asm_out_file, end_label, begin_label); + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + + /* The GNU compilers represent multidimensional array types as sequences + of one dimensional array types whose element types are themselves array + types. Here we squish that down, so that each multidimensional array + type gets only one array_type DIE in the Dwarf debugging info. The + draft Dwarf specification say that we are allowed to do this kind + of compression in C (because there is no difference between an + array or arrays and a multidimensional array in C) but for other + source languages (e.g. Ada) we probably shouldn't do this. */ + + for (dimension_number = 0; + TREE_CODE (type) == ARRAY_TYPE; + type = TREE_TYPE (type), dimension_number++) + { + register tree domain = TYPE_DOMAIN (type); + + /* Arrays come in three flavors. Unspecified bounds, fixed + bounds, and (in GNU C only) variable bounds. Handle all + three forms here. */ + + if (domain) + { + /* We have an array type with specified bounds. */ + + register tree lower = TYPE_MIN_VALUE (domain); + register tree upper = TYPE_MAX_VALUE (domain); + + /* Handle only fundamental types as index types for now. */ + + if (! type_is_fundamental (domain)) + abort (); + + /* Output the representation format byte for this dimension. */ + + ASM_OUTPUT_DWARF_FMT_BYTE (asm_out_file, + FMT_CODE (1, + TREE_CODE (lower) == INTEGER_CST, + TREE_CODE (upper) == INTEGER_CST)); + + /* Output the index type for this dimension. */ + + ASM_OUTPUT_DWARF_FUND_TYPE (asm_out_file, + fundamental_type_code (domain)); + + /* Output the representation for the lower bound. */ + + output_bound_representation (lower, dimension_number, 'l'); + + /* Output the representation for the upper bound. */ + + output_bound_representation (upper, dimension_number, 'u'); + } + else + { + /* We have an array type with an unspecified length. For C and + C++ we can assume that this really means that (a) the index + type is an integral type, and (b) the lower bound is zero. + Note that Dwarf defines the representation of an unspecified + (upper) bound as being a zero-length location description. */ + + /* Output the array-bounds format byte. */ + + ASM_OUTPUT_DWARF_FMT_BYTE (asm_out_file, FMT_FT_C_X); + + /* Output the (assumed) index type. */ + + ASM_OUTPUT_DWARF_FUND_TYPE (asm_out_file, FT_integer); + + /* Output the (assumed) lower bound (constant) value. */ + + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, 0); + + /* Output the (empty) location description for the upper bound. */ + + ASM_OUTPUT_DWARF_DATA2 (asm_out_file, 0); + } + } + + /* Output the prefix byte that says that the element type is comming up. */ + + ASM_OUTPUT_DWARF_FMT_BYTE (asm_out_file, FMT_ET); + + /* Output a representation of the type of the elements of this array type. */ + + type_attribute (type, 0, 0); + + ASM_OUTPUT_LABEL (asm_out_file, end_label); +} + +static void +byte_size_attribute (tree_node) + register tree tree_node; +{ + register unsigned size; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_byte_size); + switch (TREE_CODE (tree_node)) + { + case ERROR_MARK: + size = 0; + break; + + case ENUMERAL_TYPE: + case RECORD_TYPE: + case UNION_TYPE: + case QUAL_UNION_TYPE: + size = int_size_in_bytes (tree_node); + break; + + case FIELD_DECL: + /* For a data member of a struct or union, the AT_byte_size is + generally given as the number of bytes normally allocated for + an object of the *declared* type of the member itself. This + is true even for bit-fields. */ + size = simple_type_size_in_bits (field_type (tree_node)) + / BITS_PER_UNIT; + break; + + default: + abort (); + } + + /* Note that `size' might be -1 when we get to this point. If it + is, that indicates that the byte size of the entity in question + is variable. We have no good way of expressing this fact in Dwarf + at the present time, so just let the -1 pass on through. */ + + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, size); +} + +/* For a FIELD_DECL node which represents a bit-field, output an attribute + which specifies the distance in bits from the highest order bit of the + "containing object" for the bit-field to the highest order bit of the + bit-field itself. + + For any given bit-field, the "containing object" is a hypothetical + object (of some integral or enum type) within which the given bit-field + lives. The type of this hypothetical "containing object" is always the + same as the declared type of the individual bit-field itself. + + The determination of the exact location of the "containing object" for + a bit-field is rather complicated. It's handled by the `field_byte_offset' + function (above). + + Note that it is the size (in bytes) of the hypothetical "containing + object" which will be given in the AT_byte_size attribute for this + bit-field. (See `byte_size_attribute' above.) +*/ + +inline void +bit_offset_attribute (decl) + register tree decl; +{ + register unsigned object_offset_in_bytes = field_byte_offset (decl); + register tree type = DECL_BIT_FIELD_TYPE (decl); + register tree bitpos_tree = DECL_FIELD_BITPOS (decl); + register unsigned bitpos_int; + register unsigned highest_order_object_bit_offset; + register unsigned highest_order_field_bit_offset; + register unsigned bit_offset; + + assert (TREE_CODE (decl) == FIELD_DECL); /* Must be a field. */ + assert (type); /* Must be a bit field. */ + + /* We can't yet handle bit-fields whose offsets are variable, so if we + encounter such things, just return without generating any attribute + whatsoever. */ + + if (TREE_CODE (bitpos_tree) != INTEGER_CST) + return; + bitpos_int = (unsigned) TREE_INT_CST_LOW (bitpos_tree); + + /* Note that the bit offset is always the distance (in bits) from the + highest-order bit of the "containing object" to the highest-order + bit of the bit-field itself. Since the "high-order end" of any + object or field is different on big-endian and little-endian machines, + the computation below must take account of these differences. */ + + highest_order_object_bit_offset = object_offset_in_bytes * BITS_PER_UNIT; + highest_order_field_bit_offset = bitpos_int; + +#if (BYTES_BIG_ENDIAN == 0) + highest_order_field_bit_offset + += (unsigned) TREE_INT_CST_LOW (DECL_SIZE (decl)); + + highest_order_object_bit_offset += simple_type_size_in_bits (type); +#endif /* (BYTES_BIG_ENDIAN == 0) */ + + bit_offset = +#if (BYTES_BIG_ENDIAN == 0) + highest_order_object_bit_offset - highest_order_field_bit_offset; +#else /* (BYTES_BIG_ENDIAN != 0) */ + highest_order_field_bit_offset - highest_order_object_bit_offset; +#endif /* (BYTES_BIG_ENDIAN != 0) */ + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_bit_offset); + ASM_OUTPUT_DWARF_DATA2 (asm_out_file, bit_offset); +} + +/* For a FIELD_DECL node which represents a bit field, output an attribute + which specifies the length in bits of the given field. */ + +inline void +bit_size_attribute (decl) + register tree decl; +{ + assert (TREE_CODE (decl) == FIELD_DECL); /* Must be a field. */ + assert (DECL_BIT_FIELD_TYPE (decl)); /* Must be a bit field. */ + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_bit_size); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, + (unsigned) TREE_INT_CST_LOW (DECL_SIZE (decl))); +} + +/* The following routine outputs the `element_list' attribute for enumeration + type DIEs. The element_lits attribute includes the names and values of + all of the enumeration constants associated with the given enumeration + type. */ + +inline void +element_list_attribute (element) + register tree element; +{ + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_element_list); + sprintf (begin_label, EE_BEGIN_LABEL_FMT, current_dienum); + sprintf (end_label, EE_END_LABEL_FMT, current_dienum); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, end_label, begin_label); + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + + /* Here we output a list of value/name pairs for each enumeration constant + defined for this enumeration type (as required), but we do it in REVERSE + order. The order is the one required by the draft #5 Dwarf specification + published by the UI/PLSIG. */ + + output_enumeral_list (element); /* Recursively output the whole list. */ + + ASM_OUTPUT_LABEL (asm_out_file, end_label); +} + +/* Generate an AT_stmt_list attribute. These are normally present only in + DIEs with a TAG_compile_unit tag. */ + +inline void +stmt_list_attribute (label) + register char *label; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_stmt_list); + /* Don't use ASM_OUTPUT_DWARF_DATA4 here. */ + ASM_OUTPUT_DWARF_ADDR (asm_out_file, label); +} + +/* Generate an AT_low_pc attribute for a label DIE, a lexical_block DIE or + for a subroutine DIE. */ + +inline void +low_pc_attribute (asm_low_label) + register char *asm_low_label; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_low_pc); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, asm_low_label); +} + +/* Generate an AT_high_pc attribute for a lexical_block DIE or for a + subroutine DIE. */ + +inline void +high_pc_attribute (asm_high_label) + register char *asm_high_label; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_high_pc); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, asm_high_label); +} + +/* Generate an AT_body_begin attribute for a subroutine DIE. */ + +inline void +body_begin_attribute (asm_begin_label) + register char *asm_begin_label; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_body_begin); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, asm_begin_label); +} + +/* Generate an AT_body_end attribute for a subroutine DIE. */ + +inline void +body_end_attribute (asm_end_label) + register char *asm_end_label; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_body_end); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, asm_end_label); +} + +/* Generate an AT_language attribute given a LANG value. These attributes + are used only within TAG_compile_unit DIEs. */ + +inline void +language_attribute (language_code) + register unsigned language_code; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_language); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, language_code); +} + +inline void +member_attribute (context) + register tree context; +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + /* Generate this attribute only for members in C++. */ + + if (context != NULL && is_tagged_type (context)) + { + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_member); + sprintf (label, TYPE_NAME_FMT, TYPE_UID (context)); + ASM_OUTPUT_DWARF_REF (asm_out_file, label); + } +} + +inline void +string_length_attribute (upper_bound) + register tree upper_bound; +{ + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_string_length); + sprintf (begin_label, SL_BEGIN_LABEL_FMT, current_dienum); + sprintf (end_label, SL_END_LABEL_FMT, current_dienum); + ASM_OUTPUT_DWARF_DELTA2 (asm_out_file, end_label, begin_label); + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + output_bound_representation (upper_bound, 0, 'u'); + ASM_OUTPUT_LABEL (asm_out_file, end_label); +} + +inline void +comp_dir_attribute (dirname) + register char *dirname; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_comp_dir); + ASM_OUTPUT_DWARF_STRING (asm_out_file, dirname); +} + +inline void +sf_names_attribute (sf_names_start_label) + register char *sf_names_start_label; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_sf_names); + /* Don't use ASM_OUTPUT_DWARF_DATA4 here. */ + ASM_OUTPUT_DWARF_ADDR (asm_out_file, sf_names_start_label); +} + +inline void +src_info_attribute (src_info_start_label) + register char *src_info_start_label; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_src_info); + /* Don't use ASM_OUTPUT_DWARF_DATA4 here. */ + ASM_OUTPUT_DWARF_ADDR (asm_out_file, src_info_start_label); +} + +inline void +mac_info_attribute (mac_info_start_label) + register char *mac_info_start_label; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_mac_info); + /* Don't use ASM_OUTPUT_DWARF_DATA4 here. */ + ASM_OUTPUT_DWARF_ADDR (asm_out_file, mac_info_start_label); +} + +inline void +prototyped_attribute (func_type) + register tree func_type; +{ + if ((strcmp (language_string, "GNU C") == 0) + && (TYPE_ARG_TYPES (func_type) != NULL)) + { + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_prototyped); + ASM_OUTPUT_DWARF_STRING (asm_out_file, ""); + } +} + +inline void +producer_attribute (producer) + register char *producer; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_producer); + ASM_OUTPUT_DWARF_STRING (asm_out_file, producer); +} + +inline void +inline_attribute (decl) + register tree decl; +{ + if (DECL_INLINE (decl)) + { + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_inline); + ASM_OUTPUT_DWARF_STRING (asm_out_file, ""); + } +} + +inline void +containing_type_attribute (containing_type) + register tree containing_type; +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_containing_type); + sprintf (label, TYPE_NAME_FMT, TYPE_UID (containing_type)); + ASM_OUTPUT_DWARF_REF (asm_out_file, label); +} + +inline void +abstract_origin_attribute (origin) + register tree origin; +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_abstract_origin); + switch (TREE_CODE_CLASS (TREE_CODE (origin))) + { + case 'd': + sprintf (label, DECL_NAME_FMT, DECL_UID (origin)); + break; + + case 't': + sprintf (label, TYPE_NAME_FMT, TYPE_UID (origin)); + break; + + default: + abort (); /* Should never happen. */ + + } + ASM_OUTPUT_DWARF_REF (asm_out_file, label); +} + +#ifdef DWARF_DECL_COORDINATES +inline void +src_coords_attribute (src_fileno, src_lineno) + register unsigned src_fileno; + register unsigned src_lineno; +{ + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_src_coords); + ASM_OUTPUT_DWARF_DATA2 (asm_out_file, src_fileno); + ASM_OUTPUT_DWARF_DATA2 (asm_out_file, src_lineno); +} +#endif /* defined(DWARF_DECL_COORDINATES) */ + +inline void +pure_or_virtual_attribute (func_decl) + register tree func_decl; +{ + if (DECL_VIRTUAL_P (func_decl)) + { +#if 0 /* DECL_ABSTRACT_VIRTUAL_P is C++-specific. */ + if (DECL_ABSTRACT_VIRTUAL_P (func_decl)) + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_pure_virtual); + else +#endif + ASM_OUTPUT_DWARF_ATTRIBUTE (asm_out_file, AT_virtual); + ASM_OUTPUT_DWARF_STRING (asm_out_file, ""); + } +} + +/************************* end of attributes *****************************/ + +/********************* utility routines for DIEs *************************/ + +/* Output an AT_name attribute and an AT_src_coords attribute for the + given decl, but only if it actually has a name. */ + +static void +name_and_src_coords_attributes (decl) + register tree decl; +{ + register tree decl_name = DECL_NAME (decl); + + if (decl_name && IDENTIFIER_POINTER (decl_name)) + { + name_attribute (IDENTIFIER_POINTER (decl_name)); +#ifdef DWARF_DECL_COORDINATES + { + register unsigned file_index; + + /* This is annoying, but we have to pop out of the .debug section + for a moment while we call `lookup_filename' because calling it + may cause a temporary switch into the .debug_sfnames section and + most svr4 assemblers are not smart enough be be able to nest + section switches to any depth greater than one. Note that we + also can't skirt this issue by delaying all output to the + .debug_sfnames section unit the end of compilation because that + would cause us to have inter-section forward references and + Fred Fish sez that m68k/svr4 assemblers botch those. */ + + ASM_OUTPUT_POP_SECTION (asm_out_file); + file_index = lookup_filename (DECL_SOURCE_FILE (decl)); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, DEBUG_SECTION); + + src_coords_attribute (file_index, DECL_SOURCE_LINE (decl)); + } +#endif /* defined(DWARF_DECL_COORDINATES) */ + } +} + +/* Many forms of DIEs contain a "type description" part. The following + routine writes out these "type descriptor" parts. */ + +static void +type_attribute (type, decl_const, decl_volatile) + register tree type; + register int decl_const; + register int decl_volatile; +{ + register enum tree_code code = TREE_CODE (type); + register int root_type_modified; + + if (TREE_CODE (type) == ERROR_MARK) + return; + + /* Handle a special case. For functions whose return type is void, + we generate *no* type attribute. (Note that no object may have + type `void', so this only applies to function return types. */ + + if (TREE_CODE (type) == VOID_TYPE) + return; + + root_type_modified = (code == POINTER_TYPE || code == REFERENCE_TYPE + || decl_const || decl_volatile + || TYPE_READONLY (type) || TYPE_VOLATILE (type)); + + if (type_is_fundamental (root_type (type))) + if (root_type_modified) + mod_fund_type_attribute (type, decl_const, decl_volatile); + else + fund_type_attribute (fundamental_type_code (type)); + else + if (root_type_modified) + mod_u_d_type_attribute (type, decl_const, decl_volatile); + else + /* We have to get the type_main_variant here (and pass that to the + `user_def_type_attribute' routine) because the ..._TYPE node we + have might simply be a *copy* of some original type node (where + the copy was created to help us keep track of typedef names) + and that copy might have a different TYPE_UID from the original + ..._TYPE node. (Note that when `equate_type_number_to_die_number' + is labeling a given type DIE for future reference, it always and + only creates labels for DIEs representing *main variants*, and it + never even knows about non-main-variants.) */ + user_def_type_attribute (type_main_variant (type)); +} + +/* Given a tree pointer to a struct, class, union, or enum type node, return + a pointer to the (string) tag name for the given type, or zero if the + type was declared without a tag. */ + +static char * +type_tag (type) + register tree type; +{ + register char *name = 0; + + if (TYPE_NAME (type) != 0) + { + register tree t = 0; + + /* Find the IDENTIFIER_NODE for the type name. */ + if (TREE_CODE (TYPE_NAME (type)) == IDENTIFIER_NODE) + t = TYPE_NAME (type); +#if 0 + /* The g++ front end makes the TYPE_NAME of *each* tagged type point + to a TYPE_DECL node, regardless of whether or not a `typedef' was + involved. This is distinctly different from what the gcc front-end + does. It always makes the TYPE_NAME for each tagged type be either + NULL (signifying an anonymous tagged type) or else a pointer to an + IDENTIFIER_NODE. Obviously, we would like to generate correct Dwarf + for both C and C++, but given this inconsistency in the TREE + representation of tagged types for C and C++ in the GNU front-ends, + we cannot support both languages correctly unless we introduce some + front-end specific code here, and rms objects to that, so we can + only generate correct Dwarf for one of these two languages. C is + more important, so for now we'll do the right thing for C and let + g++ go fish. */ + + else + if (TREE_CODE (TYPE_NAME (type)) == TYPE_DECL) + t = DECL_NAME (TYPE_NAME (type)); +#endif + /* Now get the name as a string, or invent one. */ + if (t != 0) + name = IDENTIFIER_POINTER (t); + } + + return (name == 0 || *name == '\0') ? 0 : name; +} + +inline void +dienum_push () +{ + /* Start by checking if the pending_sibling_stack needs to be expanded. + If necessary, expand it. */ + + if (pending_siblings == pending_siblings_allocated) + { + pending_siblings_allocated += PENDING_SIBLINGS_INCREMENT; + pending_sibling_stack + = (unsigned *) xrealloc (pending_sibling_stack, + pending_siblings_allocated * sizeof(unsigned)); + } + + pending_siblings++; + NEXT_DIE_NUM = next_unused_dienum++; +} + +/* Pop the sibling stack so that the most recently pushed DIEnum becomes the + NEXT_DIE_NUM. */ + +inline void +dienum_pop () +{ + pending_siblings--; +} + +inline tree +member_declared_type (member) + register tree member; +{ + return (DECL_BIT_FIELD_TYPE (member)) + ? DECL_BIT_FIELD_TYPE (member) + : TREE_TYPE (member); +} + +/******************************* DIEs ************************************/ + +/* Output routines for individual types of DIEs. */ + +/* Note that every type of DIE (except a null DIE) gets a sibling. */ + +static void +output_array_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_array_type); + sibling_attribute (); + equate_type_number_to_die_number (type); + member_attribute (TYPE_CONTEXT (type)); + + /* I believe that we can default the array ordering. SDB will probably + do the right things even if AT_ordering is not present. It's not + even an issue until we start to get into multidimensional arrays + anyway. If SDB is ever caught doing the Wrong Thing for multi- + dimensional arrays, then we'll have to put the AT_ordering attribute + back in. (But if and when we find out that we need to put these in, + we will only do so for multidimensional arrays. After all, we don't + want to waste space in the .debug section now do we?) */ + +#ifdef USE_ORDERING_ATTRIBUTE + ordering_attribute (ORD_row_major); +#endif /* defined(USE_ORDERING_ATTRIBUTE) */ + + subscript_data_attribute (type); +} + +static void +output_set_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_set_type); + sibling_attribute (); + equate_type_number_to_die_number (type); + member_attribute (TYPE_CONTEXT (type)); + type_attribute (TREE_TYPE (type), 0, 0); +} + +#if 0 +/* Implement this when there is a GNU FORTRAN or GNU Ada front end. */ +static void +output_entry_point_die (arg) + register void *arg; +{ + register tree decl = arg; + register tree origin = decl_ultimate_origin (decl); + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_entry_point); + sibling_attribute (); + dienum_push (); + if (origin != NULL) + abstract_origin_attribute (origin); + else + { + name_and_src_coords_attributes (decl); + member_attribute (DECL_CONTEXT (decl)); + type_attribute (TREE_TYPE (TREE_TYPE (decl)), 0, 0); + } + if (DECL_ABSTRACT (decl)) + equate_decl_number_to_die_number (decl); + else + low_pc_attribute (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); +} +#endif + +/* Output a DIE to represent an inlined instance of an enumeration type. */ + +static void +output_inlined_enumeration_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_enumeration_type); + sibling_attribute (); + assert (TREE_ASM_WRITTEN (type)); + abstract_origin_attribute (type); +} + +/* Output a DIE to represent an inlined instance of a structure type. */ + +static void +output_inlined_structure_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_structure_type); + sibling_attribute (); + assert (TREE_ASM_WRITTEN (type)); + abstract_origin_attribute (type); +} + +/* Output a DIE to represent an inlined instance of a union type. */ + +static void +output_inlined_union_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_union_type); + sibling_attribute (); + assert (TREE_ASM_WRITTEN (type)); + abstract_origin_attribute (type); +} + +/* Output a DIE to represent an enumeration type. Note that these DIEs + include all of the information about the enumeration values also. + This information is encoded into the element_list attribute. */ + +static void +output_enumeration_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_enumeration_type); + sibling_attribute (); + equate_type_number_to_die_number (type); + name_attribute (type_tag (type)); + member_attribute (TYPE_CONTEXT (type)); + + /* Handle a GNU C/C++ extension, i.e. incomplete enum types. If the + given enum type is incomplete, do not generate the AT_byte_size + attribute or the AT_element_list attribute. */ + + if (TYPE_SIZE (type)) + { + byte_size_attribute (type); + element_list_attribute (TYPE_FIELDS (type)); + } +} + +/* Output a DIE to represent either a real live formal parameter decl or + to represent just the type of some formal parameter position in some + function type. + + Note that this routine is a bit unusual because its argument may be + a ..._DECL node (i.e. either a PARM_DECL or perhaps a VAR_DECL which + represents an inlining of some PARM_DECL) or else some sort of a + ..._TYPE node. If it's the former then this function is being called + to output a DIE to represent a formal parameter object (or some inlining + thereof). If it's the latter, then this function is only being called + to output a TAG_formal_parameter DIE to stand as a placeholder for some + formal argument type of some subprogram type. */ + +static void +output_formal_parameter_die (arg) + register void *arg; +{ + register tree node = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_formal_parameter); + sibling_attribute (); + + switch (TREE_CODE_CLASS (TREE_CODE (node))) + { + case 'd': /* We were called with some kind of a ..._DECL node. */ + { + register tree origin = decl_ultimate_origin (node); + + if (origin != NULL) + abstract_origin_attribute (origin); + else + { + name_and_src_coords_attributes (node); + type_attribute (TREE_TYPE (node), + TREE_READONLY (node), TREE_THIS_VOLATILE (node)); + } + if (DECL_ABSTRACT (node)) + equate_decl_number_to_die_number (node); + else + location_or_const_value_attribute (node); + } + break; + + case 't': /* We were called with some kind of a ..._TYPE node. */ + type_attribute (node, 0, 0); + break; + + default: + abort (); /* Should never happen. */ + } +} + +/* Output a DIE to represent a declared function (either file-scope + or block-local) which has "external linkage" (according to ANSI-C). */ + +static void +output_global_subroutine_die (arg) + register void *arg; +{ + register tree decl = arg; + register tree origin = decl_ultimate_origin (decl); + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_global_subroutine); + sibling_attribute (); + dienum_push (); + if (origin != NULL) + abstract_origin_attribute (origin); + else + { + register tree type = TREE_TYPE (decl); + + name_and_src_coords_attributes (decl); + inline_attribute (decl); + prototyped_attribute (type); + member_attribute (DECL_CONTEXT (decl)); + type_attribute (TREE_TYPE (type), 0, 0); + pure_or_virtual_attribute (decl); + } + if (DECL_ABSTRACT (decl)) + equate_decl_number_to_die_number (decl); + else + { + if (! DECL_EXTERNAL (decl)) + { + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + low_pc_attribute (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); + sprintf (label, FUNC_END_LABEL_FMT, current_funcdef_number); + high_pc_attribute (label); + sprintf (label, BODY_BEGIN_LABEL_FMT, current_funcdef_number); + body_begin_attribute (label); + sprintf (label, BODY_END_LABEL_FMT, current_funcdef_number); + body_end_attribute (label); + } + } +} + +/* Output a DIE to represent a declared data object (either file-scope + or block-local) which has "external linkage" (according to ANSI-C). */ + +static void +output_global_variable_die (arg) + register void *arg; +{ + register tree decl = arg; + register tree origin = decl_ultimate_origin (decl); + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_global_variable); + sibling_attribute (); + if (origin != NULL) + abstract_origin_attribute (origin); + else + { + name_and_src_coords_attributes (decl); + member_attribute (DECL_CONTEXT (decl)); + type_attribute (TREE_TYPE (decl), + TREE_READONLY (decl), TREE_THIS_VOLATILE (decl)); + } + if (DECL_ABSTRACT (decl)) + equate_decl_number_to_die_number (decl); + else + { + if (!DECL_EXTERNAL (decl)) + location_or_const_value_attribute (decl); + } +} + +static void +output_label_die (arg) + register void *arg; +{ + register tree decl = arg; + register tree origin = decl_ultimate_origin (decl); + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_label); + sibling_attribute (); + if (origin != NULL) + abstract_origin_attribute (origin); + else + name_and_src_coords_attributes (decl); + if (DECL_ABSTRACT (decl)) + equate_decl_number_to_die_number (decl); + else + { + register rtx insn = DECL_RTL (decl); + + if (GET_CODE (insn) == CODE_LABEL) + { + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + /* When optimization is enabled (via -O) some parts of the compiler + (e.g. jump.c and cse.c) may try to delete CODE_LABEL insns which + represent source-level labels which were explicitly declared by + the user. This really shouldn't be happening though, so catch + it if it ever does happen. */ + + if (INSN_DELETED_P (insn)) + abort (); /* Should never happen. */ + + sprintf (label, INSN_LABEL_FMT, current_funcdef_number, + (unsigned) INSN_UID (insn)); + low_pc_attribute (label); + } + } +} + +static void +output_lexical_block_die (arg) + register void *arg; +{ + register tree stmt = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_lexical_block); + sibling_attribute (); + dienum_push (); + if (! BLOCK_ABSTRACT (stmt)) + { + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + sprintf (begin_label, BLOCK_BEGIN_LABEL_FMT, next_block_number); + low_pc_attribute (begin_label); + sprintf (end_label, BLOCK_END_LABEL_FMT, next_block_number); + high_pc_attribute (end_label); + } +} + +static void +output_inlined_subroutine_die (arg) + register void *arg; +{ + register tree stmt = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_inlined_subroutine); + sibling_attribute (); + dienum_push (); + abstract_origin_attribute (block_ultimate_origin (stmt)); + if (! BLOCK_ABSTRACT (stmt)) + { + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + sprintf (begin_label, BLOCK_BEGIN_LABEL_FMT, next_block_number); + low_pc_attribute (begin_label); + sprintf (end_label, BLOCK_END_LABEL_FMT, next_block_number); + high_pc_attribute (end_label); + } +} + +/* Output a DIE to represent a declared data object (either file-scope + or block-local) which has "internal linkage" (according to ANSI-C). */ + +static void +output_local_variable_die (arg) + register void *arg; +{ + register tree decl = arg; + register tree origin = decl_ultimate_origin (decl); + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_local_variable); + sibling_attribute (); + if (origin != NULL) + abstract_origin_attribute (origin); + else + { + name_and_src_coords_attributes (decl); + member_attribute (DECL_CONTEXT (decl)); + type_attribute (TREE_TYPE (decl), + TREE_READONLY (decl), TREE_THIS_VOLATILE (decl)); + } + if (DECL_ABSTRACT (decl)) + equate_decl_number_to_die_number (decl); + else + location_or_const_value_attribute (decl); +} + +static void +output_member_die (arg) + register void *arg; +{ + register tree decl = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_member); + sibling_attribute (); + name_and_src_coords_attributes (decl); + member_attribute (DECL_CONTEXT (decl)); + type_attribute (member_declared_type (decl), + TREE_READONLY (decl), TREE_THIS_VOLATILE (decl)); + if (DECL_BIT_FIELD_TYPE (decl)) /* If this is a bit field... */ + { + byte_size_attribute (decl); + bit_size_attribute (decl); + bit_offset_attribute (decl); + } + data_member_location_attribute (decl); +} + +#if 0 +/* Don't generate either pointer_type DIEs or reference_type DIEs. Use + modified types instead. + + We keep this code here just in case these types of DIEs may be needed + to represent certain things in other languages (e.g. Pascal) someday. +*/ + +static void +output_pointer_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_pointer_type); + sibling_attribute (); + equate_type_number_to_die_number (type); + member_attribute (TYPE_CONTEXT (type)); + type_attribute (TREE_TYPE (type), 0, 0); +} + +static void +output_reference_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_reference_type); + sibling_attribute (); + equate_type_number_to_die_number (type); + member_attribute (TYPE_CONTEXT (type)); + type_attribute (TREE_TYPE (type), 0, 0); +} +#endif + +static void +output_ptr_to_mbr_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_ptr_to_member_type); + sibling_attribute (); + equate_type_number_to_die_number (type); + member_attribute (TYPE_CONTEXT (type)); + containing_type_attribute (TYPE_OFFSET_BASETYPE (type)); + type_attribute (TREE_TYPE (type), 0, 0); +} + +static void +output_compile_unit_die (arg) + register void *arg; +{ + register char *main_input_filename = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_compile_unit); + sibling_attribute (); + dienum_push (); + name_attribute (main_input_filename); + + { + char producer[250]; + + sprintf (producer, "%s %s", language_string, version_string); + producer_attribute (producer); + } + + if (strcmp (language_string, "GNU C++") == 0) + language_attribute (LANG_C_PLUS_PLUS); + else if (flag_traditional) + language_attribute (LANG_C); + else + language_attribute (LANG_C89); + low_pc_attribute (TEXT_BEGIN_LABEL); + high_pc_attribute (TEXT_END_LABEL); + if (debug_info_level >= DINFO_LEVEL_NORMAL) + stmt_list_attribute (LINE_BEGIN_LABEL); + last_filename = xstrdup (main_input_filename); + + { + char *wd = getpwd (); + if (wd) + comp_dir_attribute (wd); + } + + if (debug_info_level >= DINFO_LEVEL_NORMAL) + { + sf_names_attribute (SFNAMES_BEGIN_LABEL); + src_info_attribute (SRCINFO_BEGIN_LABEL); + if (debug_info_level >= DINFO_LEVEL_VERBOSE) + mac_info_attribute (MACINFO_BEGIN_LABEL); + } +} + +static void +output_string_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_string_type); + sibling_attribute (); + member_attribute (TYPE_CONTEXT (type)); + + /* Fudge the string length attribute for now. */ + + string_length_attribute (TYPE_MAX_VALUE (TYPE_DOMAIN (type))); +} + +static void +output_structure_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_structure_type); + sibling_attribute (); + equate_type_number_to_die_number (type); + name_attribute (type_tag (type)); + member_attribute (TYPE_CONTEXT (type)); + + /* If this type has been completed, then give it a byte_size attribute + and prepare to give a list of members. Otherwise, don't do either of + these things. In the latter case, we will not be generating a list + of members (since we don't have any idea what they might be for an + incomplete type). */ + + if (TYPE_SIZE (type)) + { + dienum_push (); + byte_size_attribute (type); + } +} + +/* Output a DIE to represent a declared function (either file-scope + or block-local) which has "internal linkage" (according to ANSI-C). */ + +static void +output_local_subroutine_die (arg) + register void *arg; +{ + register tree decl = arg; + register tree origin = decl_ultimate_origin (decl); + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_subroutine); + sibling_attribute (); + dienum_push (); + if (origin != NULL) + abstract_origin_attribute (origin); + else + { + register tree type = TREE_TYPE (decl); + + name_and_src_coords_attributes (decl); + inline_attribute (decl); + prototyped_attribute (type); + member_attribute (DECL_CONTEXT (decl)); + type_attribute (TREE_TYPE (type), 0, 0); + pure_or_virtual_attribute (decl); + } + if (DECL_ABSTRACT (decl)) + equate_decl_number_to_die_number (decl); + else + { + /* Avoid getting screwed up in cases where a function was declared + static but where no definition was ever given for it. */ + + if (TREE_ASM_WRITTEN (decl)) + { + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + low_pc_attribute (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); + sprintf (label, FUNC_END_LABEL_FMT, current_funcdef_number); + high_pc_attribute (label); + sprintf (label, BODY_BEGIN_LABEL_FMT, current_funcdef_number); + body_begin_attribute (label); + sprintf (label, BODY_END_LABEL_FMT, current_funcdef_number); + body_end_attribute (label); + } + } +} + +static void +output_subroutine_type_die (arg) + register void *arg; +{ + register tree type = arg; + register tree return_type = TREE_TYPE (type); + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_subroutine_type); + sibling_attribute (); + dienum_push (); + equate_type_number_to_die_number (type); + prototyped_attribute (type); + member_attribute (TYPE_CONTEXT (type)); + type_attribute (return_type, 0, 0); +} + +static void +output_typedef_die (arg) + register void *arg; +{ + register tree decl = arg; + register tree origin = decl_ultimate_origin (decl); + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_typedef); + sibling_attribute (); + if (origin != NULL) + abstract_origin_attribute (origin); + else + { + name_and_src_coords_attributes (decl); + member_attribute (DECL_CONTEXT (decl)); + type_attribute (TREE_TYPE (decl), + TREE_READONLY (decl), TREE_THIS_VOLATILE (decl)); + } + if (DECL_ABSTRACT (decl)) + equate_decl_number_to_die_number (decl); +} + +static void +output_union_type_die (arg) + register void *arg; +{ + register tree type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_union_type); + sibling_attribute (); + equate_type_number_to_die_number (type); + name_attribute (type_tag (type)); + member_attribute (TYPE_CONTEXT (type)); + + /* If this type has been completed, then give it a byte_size attribute + and prepare to give a list of members. Otherwise, don't do either of + these things. In the latter case, we will not be generating a list + of members (since we don't have any idea what they might be for an + incomplete type). */ + + if (TYPE_SIZE (type)) + { + dienum_push (); + byte_size_attribute (type); + } +} + +/* Generate a special type of DIE used as a stand-in for a trailing ellipsis + at the end of an (ANSI prototyped) formal parameters list. */ + +static void +output_unspecified_parameters_die (arg) + register void *arg; +{ + register tree decl_or_type = arg; + + ASM_OUTPUT_DWARF_TAG (asm_out_file, TAG_unspecified_parameters); + sibling_attribute (); + + /* This kludge is here only for the sake of being compatible with what + the USL CI5 C compiler does. The specification of Dwarf Version 1 + doesn't say that TAG_unspecified_parameters DIEs should contain any + attributes other than the AT_sibling attribute, but they are certainly + allowed to contain additional attributes, and the CI5 compiler + generates AT_name, AT_fund_type, and AT_location attributes within + TAG_unspecified_parameters DIEs which appear in the child lists for + DIEs representing function definitions, so we do likewise here. */ + + if (TREE_CODE (decl_or_type) == FUNCTION_DECL && DECL_INITIAL (decl_or_type)) + { + name_attribute ("..."); + fund_type_attribute (FT_pointer); + /* location_attribute (?); */ + } +} + +static void +output_padded_null_die (arg) + register void *arg; +{ + ASM_OUTPUT_ALIGN (asm_out_file, 2); /* 2**2 == 4 */ +} + +/*************************** end of DIEs *********************************/ + +/* Generate some type of DIE. This routine generates the generic outer + wrapper stuff which goes around all types of DIE's (regardless of their + TAGs. All forms of DIEs start with a DIE-specific label, followed by a + DIE-length word, followed by the guts of the DIE itself. After the guts + of the DIE, there must always be a terminator label for the DIE. */ + +static void +output_die (die_specific_output_function, param) + register void (*die_specific_output_function)(); + register void *param; +{ + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + char end_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + current_dienum = NEXT_DIE_NUM; + NEXT_DIE_NUM = next_unused_dienum; + + sprintf (begin_label, DIE_BEGIN_LABEL_FMT, current_dienum); + sprintf (end_label, DIE_END_LABEL_FMT, current_dienum); + + /* Write a label which will act as the name for the start of this DIE. */ + + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + + /* Write the DIE-length word. */ + + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, end_label, begin_label); + + /* Fill in the guts of the DIE. */ + + next_unused_dienum++; + die_specific_output_function (param); + + /* Write a label which will act as the name for the end of this DIE. */ + + ASM_OUTPUT_LABEL (asm_out_file, end_label); +} + +static void +end_sibling_chain () +{ + char begin_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + current_dienum = NEXT_DIE_NUM; + NEXT_DIE_NUM = next_unused_dienum; + + sprintf (begin_label, DIE_BEGIN_LABEL_FMT, current_dienum); + + /* Write a label which will act as the name for the start of this DIE. */ + + ASM_OUTPUT_LABEL (asm_out_file, begin_label); + + /* Write the DIE-length word. */ + + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, 4); + + dienum_pop (); +} + +/* Generate a list of nameless TAG_formal_parameter DIEs (and perhaps a + TAG_unspecified_parameters DIE) to represent the types of the formal + parameters as specified in some function type specification (except + for those which appear as part of a function *definition*). + + Note that we must be careful here to output all of the parameter DIEs + *before* we output any DIEs needed to represent the types of the formal + parameters. This keeps svr4 SDB happy because it (incorrectly) thinks + that the first non-parameter DIE it sees ends the formal parameter list. +*/ + +static void +output_formal_types (function_or_method_type) + register tree function_or_method_type; +{ + register tree link; + register tree formal_type = NULL; + register tree first_parm_type = TYPE_ARG_TYPES (function_or_method_type); + + /* In the case where we are generating a formal types list for a C++ + non-static member function type, skip over the first thing on the + TYPE_ARG_TYPES list because it only represents the type of the + hidden `this pointer'. The debugger should be able to figure + out (without being explicitly told) that this non-static member + function type takes a `this pointer' and should be able to figure + what the type of that hidden parameter is from the AT_member + attribute of the parent TAG_subroutine_type DIE. */ + + if (TREE_CODE (function_or_method_type) == METHOD_TYPE) + first_parm_type = TREE_CHAIN (first_parm_type); + + /* Make our first pass over the list of formal parameter types and output + a TAG_formal_parameter DIE for each one. */ + + for (link = first_parm_type; link; link = TREE_CHAIN (link)) + { + formal_type = TREE_VALUE (link); + if (formal_type == void_type_node) + break; + + /* Output a (nameless) DIE to represent the formal parameter itself. */ + + output_die (output_formal_parameter_die, formal_type); + } + + /* If this function type has an ellipsis, add a TAG_unspecified_parameters + DIE to the end of the parameter list. */ + + if (formal_type != void_type_node) + output_die (output_unspecified_parameters_die, function_or_method_type); + + /* Make our second (and final) pass over the list of formal parameter types + and output DIEs to represent those types (as necessary). */ + + for (link = TYPE_ARG_TYPES (function_or_method_type); + link; + link = TREE_CHAIN (link)) + { + formal_type = TREE_VALUE (link); + if (formal_type == void_type_node) + break; + + output_type (formal_type, function_or_method_type); + } +} + +/* Remember a type in the pending_types_list. */ + +static void +pend_type (type) + register tree type; +{ + if (pending_types == pending_types_allocated) + { + pending_types_allocated += PENDING_TYPES_INCREMENT; + pending_types_list + = (tree *) xrealloc (pending_types_list, + sizeof (tree) * pending_types_allocated); + } + pending_types_list[pending_types++] = type; + + /* Mark the pending type as having been output already (even though + it hasn't been). This prevents the type from being added to the + pending_types_list more than once. */ + + TREE_ASM_WRITTEN (type) = 1; +} + +/* Return non-zero if it is legitimate to output DIEs to represent a + given type while we are generating the list of child DIEs for some + DIE (e.g. a function or lexical block DIE) associated with a given scope. + + See the comments within the function for a description of when it is + considered legitimate to output DIEs for various kinds of types. + + Note that TYPE_CONTEXT(type) may be NULL (to indicate global scope) + or it may point to a BLOCK node (for types local to a block), or to a + FUNCTION_DECL node (for types local to the heading of some function + definition), or to a FUNCTION_TYPE node (for types local to the + prototyped parameter list of a function type specification), or to a + RECORD_TYPE, UNION_TYPE, or QUAL_UNION_TYPE node + (in the case of C++ nested types). + + The `scope' parameter should likewise be NULL or should point to a + BLOCK node, a FUNCTION_DECL node, a FUNCTION_TYPE node, a RECORD_TYPE + node, a UNION_TYPE node, or a QUAL_UNION_TYPE node. + + This function is used only for deciding when to "pend" and when to + "un-pend" types to/from the pending_types_list. + + Note that we sometimes make use of this "type pending" feature in a + rather twisted way to temporarily delay the production of DIEs for the + types of formal parameters. (We do this just to make svr4 SDB happy.) + It order to delay the production of DIEs representing types of formal + parameters, callers of this function supply `fake_containing_scope' as + the `scope' parameter to this function. Given that fake_containing_scope + is a tagged type which is *not* the containing scope for *any* other type, + the desired effect is achieved, i.e. output of DIEs representing types + is temporarily suspended, and any type DIEs which would have otherwise + been output are instead placed onto the pending_types_list. Later on, + we force these (temporarily pended) types to be output simply by calling + `output_pending_types_for_scope' with an actual argument equal to the + true scope of the types we temporarily pended. +*/ + +inline int +type_ok_for_scope (type, scope) + register tree type; + register tree scope; +{ + /* Tagged types (i.e. struct, union, and enum types) must always be + output only in the scopes where they actually belong (or else the + scoping of their own tag names and the scoping of their member + names will be incorrect). Non-tagged-types on the other hand can + generally be output anywhere, except that svr4 SDB really doesn't + want to see them nested within struct or union types, so here we + say it is always OK to immediately output any such a (non-tagged) + type, so long as we are not within such a context. Note that the + only kinds of non-tagged types which we will be dealing with here + (for C and C++ anyway) will be array types and function types. */ + + return is_tagged_type (type) + ? (TYPE_CONTEXT (type) == scope) + : (scope == NULL_TREE || ! is_tagged_type (scope)); +} + +/* Output any pending types (from the pending_types list) which we can output + now (taking into account the scope that we are working on now). + + For each type output, remove the given type from the pending_types_list + *before* we try to output it. + + Note that we have to process the list in beginning-to-end order, + because the call made here to output_type may cause yet more types + to be added to the end of the list, and we may have to output some + of them too. +*/ + +static void +output_pending_types_for_scope (containing_scope) + register tree containing_scope; +{ + register unsigned i; + + for (i = 0; i < pending_types; ) + { + register tree type = pending_types_list[i]; + + if (type_ok_for_scope (type, containing_scope)) + { + register tree *mover; + register tree *limit; + + pending_types--; + limit = &pending_types_list[pending_types]; + for (mover = &pending_types_list[i]; mover < limit; mover++) + *mover = *(mover+1); + + /* Un-mark the type as having been output already (because it + hasn't been, really). Then call output_type to generate a + Dwarf representation of it. */ + + TREE_ASM_WRITTEN (type) = 0; + output_type (type, containing_scope); + + /* Don't increment the loop counter in this case because we + have shifted all of the subsequent pending types down one + element in the pending_types_list array. */ + } + else + i++; + } +} + +static void +output_type (type, containing_scope) + register tree type; + register tree containing_scope; +{ + if (type == 0 || type == error_mark_node) + return; + + /* We are going to output a DIE to represent the unqualified version of + of this type (i.e. without any const or volatile qualifiers) so get + the main variant (i.e. the unqualified version) of this type now. */ + + type = type_main_variant (type); + + if (TREE_ASM_WRITTEN (type)) + return; + + /* Don't generate any DIEs for this type now unless it is OK to do so + (based upon what `type_ok_for_scope' tells us). */ + + if (! type_ok_for_scope (type, containing_scope)) + { + pend_type (type); + return; + } + + switch (TREE_CODE (type)) + { + case ERROR_MARK: + break; + + case POINTER_TYPE: + case REFERENCE_TYPE: + /* For these types, all that is required is that we output a DIE + (or a set of DIEs) to represent the "basis" type. */ + output_type (TREE_TYPE (type), containing_scope); + break; + + case OFFSET_TYPE: + /* This code is used for C++ pointer-to-data-member types. */ + /* Output a description of the relevant class type. */ + output_type (TYPE_OFFSET_BASETYPE (type), containing_scope); + /* Output a description of the type of the object pointed to. */ + output_type (TREE_TYPE (type), containing_scope); + /* Now output a DIE to represent this pointer-to-data-member type + itself. */ + output_die (output_ptr_to_mbr_type_die, type); + break; + + case SET_TYPE: + output_type (TREE_TYPE (type), containing_scope); + output_die (output_set_type_die, type); + break; + + case FILE_TYPE: + output_type (TREE_TYPE (type), containing_scope); + abort (); /* No way to represent these in Dwarf yet! */ + break; + + case STRING_TYPE: + output_type (TREE_TYPE (type), containing_scope); + output_die (output_string_type_die, type); + break; + + case FUNCTION_TYPE: + /* Force out return type (in case it wasn't forced out already). */ + output_type (TREE_TYPE (type), containing_scope); + output_die (output_subroutine_type_die, type); + output_formal_types (type); + end_sibling_chain (); + break; + + case METHOD_TYPE: + /* Force out return type (in case it wasn't forced out already). */ + output_type (TREE_TYPE (type), containing_scope); + output_die (output_subroutine_type_die, type); + output_formal_types (type); + end_sibling_chain (); + break; + + case ARRAY_TYPE: + { + register tree element_type; + + element_type = TREE_TYPE (type); + while (TREE_CODE (element_type) == ARRAY_TYPE) + element_type = TREE_TYPE (element_type); + + output_type (element_type, containing_scope); + output_die (output_array_type_die, type); + } + break; + + case ENUMERAL_TYPE: + case RECORD_TYPE: + case UNION_TYPE: + case QUAL_UNION_TYPE: + + /* For a non-file-scope tagged type, we can always go ahead and + output a Dwarf description of this type right now, even if + the type in question is still incomplete, because if this + local type *was* ever completed anywhere within its scope, + that complete definition would already have been attached to + this RECORD_TYPE, UNION_TYPE, QUAL_UNION_TYPE or ENUMERAL_TYPE + node by the time we reach this point. That's true because of the + way the front-end does its processing of file-scope declarations (of + functions and class types) within which other types might be + nested. The C and C++ front-ends always gobble up such "local + scope" things en-mass before they try to output *any* debugging + information for any of the stuff contained inside them and thus, + we get the benefit here of what is (in effect) a pre-resolution + of forward references to tagged types in local scopes. + + Note however that for file-scope tagged types we cannot assume + that such pre-resolution of forward references has taken place. + A given file-scope tagged type may appear to be incomplete when + we reach this point, but it may yet be given a full definition + (at file-scope) later on during compilation. In order to avoid + generating a premature (and possibly incorrect) set of Dwarf + DIEs for such (as yet incomplete) file-scope tagged types, we + generate nothing at all for as-yet incomplete file-scope tagged + types here unless we are making our special "finalization" pass + for file-scope things at the very end of compilation. At that + time, we will certainly know as much about each file-scope tagged + type as we are ever going to know, so at that point in time, we + can safely generate correct Dwarf descriptions for these file- + scope tagged types. + */ + + if (TYPE_SIZE (type) == 0 && TYPE_CONTEXT (type) == NULL && !finalizing) + return; /* EARLY EXIT! Avoid setting TREE_ASM_WRITTEN. */ + + /* Prevent infinite recursion in cases where the type of some + member of this type is expressed in terms of this type itself. */ + + TREE_ASM_WRITTEN (type) = 1; + + /* Output a DIE to represent the tagged type itself. */ + + switch (TREE_CODE (type)) + { + case ENUMERAL_TYPE: + output_die (output_enumeration_type_die, type); + return; /* a special case -- nothing left to do so just return */ + + case RECORD_TYPE: + output_die (output_structure_type_die, type); + break; + + case UNION_TYPE: + case QUAL_UNION_TYPE: + output_die (output_union_type_die, type); + break; + + default: + abort (); /* Should never happen. */ + } + + /* If this is not an incomplete type, output descriptions of + each of its members. + + Note that as we output the DIEs necessary to represent the + members of this record or union type, we will also be trying + to output DIEs to represent the *types* of those members. + However the `output_type' function (above) will specifically + avoid generating type DIEs for member types *within* the list + of member DIEs for this (containing) type execpt for those + types (of members) which are explicitly marked as also being + members of this (containing) type themselves. The g++ front- + end can force any given type to be treated as a member of some + other (containing) type by setting the TYPE_CONTEXT of the + given (member) type to point to the TREE node representing the + appropriate (containing) type. + */ + + if (TYPE_SIZE (type)) + { + { + register tree normal_member; + + /* First output info about the data members and type members. */ + + for (normal_member = TYPE_FIELDS (type); + normal_member; + normal_member = TREE_CHAIN (normal_member)) + output_decl (normal_member, type); + } + + { + register tree vec_base; + + /* Now output info about the function members (if any). */ + + vec_base = TYPE_METHODS (type); + if (vec_base) + { + register tree first_func_member = TREE_VEC_ELT (vec_base, 0); + register tree func_member; + + /* This isn't documented, but the first element of the + vector of member functions can be NULL in cases where + the class type in question didn't have either a + constructor or a destructor declared for it. We have + to make allowances for that here. */ + + if (first_func_member == NULL) + first_func_member = TREE_VEC_ELT (vec_base, 1); + + for (func_member = first_func_member; + func_member; + func_member = TREE_CHAIN (func_member)) + output_decl (func_member, type); + } + } + + /* RECORD_TYPEs, UNION_TYPEs, and QUAL_UNION_TYPEs are themselves + scopes (at least in C++) so we must now output any nested + pending types which are local just to this type. */ + + output_pending_types_for_scope (type); + + end_sibling_chain (); /* Terminate member chain. */ + } + + break; + + case VOID_TYPE: + case INTEGER_TYPE: + case REAL_TYPE: + case COMPLEX_TYPE: + case BOOLEAN_TYPE: + case CHAR_TYPE: + break; /* No DIEs needed for fundamental types. */ + + case LANG_TYPE: /* No Dwarf representation currently defined. */ + break; + + default: + abort (); + } + + TREE_ASM_WRITTEN (type) = 1; +} + +static void +output_tagged_type_instantiation (type) + register tree type; +{ + if (type == 0 || type == error_mark_node) + return; + + /* We are going to output a DIE to represent the unqualified version of + of this type (i.e. without any const or volatile qualifiers) so make + sure that we have the main variant (i.e. the unqualified version) of + this type now. */ + + assert (type == type_main_variant (type)); + + assert (TREE_ASM_WRITTEN (type)); + + switch (TREE_CODE (type)) + { + case ERROR_MARK: + break; + + case ENUMERAL_TYPE: + output_die (output_inlined_enumeration_type_die, type); + break; + + case RECORD_TYPE: + output_die (output_inlined_structure_type_die, type); + break; + + case UNION_TYPE: + case QUAL_UNION_TYPE: + output_die (output_inlined_union_type_die, type); + break; + + default: + abort (); /* Should never happen. */ + } +} + +/* Output a TAG_lexical_block DIE followed by DIEs to represent all of + the things which are local to the given block. */ + +static void +output_block (stmt) + register tree stmt; +{ + register int must_output_die = 0; + register tree origin; + register enum tree_code origin_code; + + /* Ignore blocks never really used to make RTL. */ + + if (! stmt || ! TREE_USED (stmt)) + return; + + /* Determine the "ultimate origin" of this block. This block may be an + inlined instance of an inlined instance of inline function, so we + have to trace all of the way back through the origin chain to find + out what sort of node actually served as the original seed for the + creation of the current block. */ + + origin = block_ultimate_origin (stmt); + origin_code = (origin != NULL) ? TREE_CODE (origin) : ERROR_MARK; + + /* Determine if we need to output any Dwarf DIEs at all to represent this + block. */ + + if (origin_code == FUNCTION_DECL) + /* The outer scopes for inlinings *must* always be represented. We + generate TAG_inlined_subroutine DIEs for them. (See below.) */ + must_output_die = 1; + else + { + /* In the case where the current block represents an inlining of the + "body block" of an inline function, we must *NOT* output any DIE + for this block because we have already output a DIE to represent + the whole inlined function scope and the "body block" of any + function doesn't really represent a different scope according to + ANSI C rules. So we check here to make sure that this block does + not represent a "body block inlining" before trying to set the + `must_output_die' flag. */ + + if (origin == NULL || ! is_body_block (origin)) + { + /* Determine if this block directly contains any "significant" + local declarations which we will need to output DIEs for. */ + + if (debug_info_level > DINFO_LEVEL_TERSE) + /* We are not in terse mode so *any* local declaration counts + as being a "significant" one. */ + must_output_die = (BLOCK_VARS (stmt) != NULL); + else + { + register tree decl; + + /* We are in terse mode, so only local (nested) function + definitions count as "significant" local declarations. */ + + for (decl = BLOCK_VARS (stmt); decl; decl = TREE_CHAIN (decl)) + if (TREE_CODE (decl) == FUNCTION_DECL && DECL_INITIAL (decl)) + { + must_output_die = 1; + break; + } + } + } + } + + /* It would be a waste of space to generate a Dwarf TAG_lexical_block + DIE for any block which contains no significant local declarations + at all. Rather, in such cases we just call `output_decls_for_scope' + so that any needed Dwarf info for any sub-blocks will get properly + generated. Note that in terse mode, our definition of what constitutes + a "significant" local declaration gets restricted to include only + inlined function instances and local (nested) function definitions. */ + + if (must_output_die) + { + output_die ((origin_code == FUNCTION_DECL) + ? output_inlined_subroutine_die + : output_lexical_block_die, + stmt); + output_decls_for_scope (stmt); + end_sibling_chain (); + } + else + output_decls_for_scope (stmt); +} + +/* Output all of the decls declared within a given scope (also called + a `binding contour') and (recursively) all of it's sub-blocks. */ + +static void +output_decls_for_scope (stmt) + register tree stmt; +{ + /* Ignore blocks never really used to make RTL. */ + + if (! stmt || ! TREE_USED (stmt)) + return; + + if (! BLOCK_ABSTRACT (stmt)) + next_block_number++; + + /* Output the DIEs to represent all of the data objects, functions, + typedefs, and tagged types declared directly within this block + but not within any nested sub-blocks. */ + + { + register tree decl; + + for (decl = BLOCK_VARS (stmt); decl; decl = TREE_CHAIN (decl)) + output_decl (decl, stmt); + } + + output_pending_types_for_scope (stmt); + + /* Output the DIEs to represent all sub-blocks (and the items declared + therein) of this block. */ + + { + register tree subblocks; + + for (subblocks = BLOCK_SUBBLOCKS (stmt); + subblocks; + subblocks = BLOCK_CHAIN (subblocks)) + output_block (subblocks); + } +} + +/* Output Dwarf .debug information for a decl described by DECL. */ + +static void +output_decl (decl, containing_scope) + register tree decl; + register tree containing_scope; +{ + /* Make a note of the decl node we are going to be working on. We may + need to give the user the source coordinates of where it appeared in + case we notice (later on) that something about it looks screwy. */ + + dwarf_last_decl = decl; + + if (TREE_CODE (decl) == ERROR_MARK) + return; + + /* If this ..._DECL node is marked to be ignored, then ignore it. + But don't ignore a function definition, since that would screw + up our count of blocks, and that it turn will completely screw up the + the labels we will reference in subsequent AT_low_pc and AT_high_pc + attributes (for subsequent blocks). */ + + if (DECL_IGNORED_P (decl) && TREE_CODE (decl) != FUNCTION_DECL) + return; + + switch (TREE_CODE (decl)) + { + case CONST_DECL: + /* The individual enumerators of an enum type get output when we + output the Dwarf representation of the relevant enum type itself. */ + break; + + case FUNCTION_DECL: + /* If we are in terse mode, don't output any DIEs to represent + mere function declarations. Also, if we are conforming + to the DWARF version 1 specification, don't output DIEs for + mere function declarations. */ + + if (DECL_INITIAL (decl) == NULL_TREE) +#if (DWARF_VERSION > 1) + if (debug_info_level <= DINFO_LEVEL_TERSE) +#endif + break; + + /* Before we describe the FUNCTION_DECL itself, make sure that we + have described its return type. */ + + output_type (TREE_TYPE (TREE_TYPE (decl)), containing_scope); + + /* If the following DIE will represent a function definition for a + function with "extern" linkage, output a special "pubnames" DIE + label just ahead of the actual DIE. A reference to this label + was already generated in the .debug_pubnames section sub-entry + for this function definition. */ + + if (TREE_PUBLIC (decl)) + { + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + sprintf (label, PUB_DIE_LABEL_FMT, next_pubname_number++); + ASM_OUTPUT_LABEL (asm_out_file, label); + } + + /* Now output a DIE to represent the function itself. */ + + output_die (TREE_PUBLIC (decl) || DECL_EXTERNAL (decl) + ? output_global_subroutine_die + : output_local_subroutine_die, + decl); + + /* Now output descriptions of the arguments for this function. + This gets (unnecessarily?) complex because of the fact that + the DECL_ARGUMENT list for a FUNCTION_DECL doesn't indicate + cases where there was a trailing `...' at the end of the formal + parameter list. In order to find out if there was a trailing + ellipsis or not, we must instead look at the type associated + with the FUNCTION_DECL. This will be a node of type FUNCTION_TYPE. + If the chain of type nodes hanging off of this FUNCTION_TYPE node + ends with a void_type_node then there should *not* be an ellipsis + at the end. */ + + /* In the case where we are describing a mere function declaration, all + we need to do here (and all we *can* do here) is to describe + the *types* of its formal parameters. */ + + if (DECL_INITIAL (decl) == NULL_TREE) + output_formal_types (TREE_TYPE (decl)); + else + { + register tree arg_decls = DECL_ARGUMENTS (decl); + + { + register tree last_arg; + + last_arg = (arg_decls && TREE_CODE (arg_decls) != ERROR_MARK) + ? tree_last (arg_decls) + : NULL; + + /* Generate DIEs to represent all known formal parameters, but + don't do it if this looks like a varargs function. A given + function is considered to be a varargs function if (and only + if) its last named argument is named `__builtin_va_alist'. */ + + if (! last_arg + || ! DECL_NAME (last_arg) + || strcmp (IDENTIFIER_POINTER (DECL_NAME (last_arg)), + "__builtin_va_alist")) + { + register tree parm; + + /* WARNING! Kludge zone ahead! Here we have a special + hack for svr4 SDB compatibility. Instead of passing the + current FUNCTION_DECL node as the second parameter (i.e. + the `containing_scope' parameter) to `output_decl' (as + we ought to) we instead pass a pointer to our own private + fake_containing_scope node. That node is a RECORD_TYPE + node which NO OTHER TYPE may ever actually be a member of. + + This pointer will ultimately get passed into `output_type' + as its `containing_scope' parameter. `Output_type' will + then perform its part in the hack... i.e. it will pend + the type of the formal parameter onto the pending_types + list. Later on, when we are done generating the whole + sequence of formal parameter DIEs for this function + definition, we will un-pend all previously pended types + of formal parameters for this function definition. + + This whole kludge prevents any type DIEs from being + mixed in with the formal parameter DIEs. That's good + because svr4 SDB believes that the list of formal + parameter DIEs for a function ends wherever the first + non-formal-parameter DIE appears. Thus, we have to + keep the formal parameter DIEs segregated. They must + all appear (consecutively) at the start of the list of + children for the DIE representing the function definition. + Then (and only then) may we output any additional DIEs + needed to represent the types of these formal parameters. + */ + + for (parm = arg_decls; parm; parm = TREE_CHAIN (parm)) + if (TREE_CODE (parm) == PARM_DECL) + output_decl (parm, fake_containing_scope); + + /* Now that we have finished generating all of the DIEs to + represent the formal parameters themselves, force out + any DIEs needed to represent their types. We do this + simply by un-pending all previously pended types which + can legitimately go into the chain of children DIEs for + the current FUNCTION_DECL. */ + + output_pending_types_for_scope (decl); + } + } + + /* Now try to decide if we should put an ellipsis at the end. */ + + { + register int has_ellipsis = TRUE; /* default assumption */ + register tree fn_arg_types = TYPE_ARG_TYPES (TREE_TYPE (decl)); + + if (fn_arg_types) + { + /* This function declaration/definition was prototyped. */ + + /* If the list of formal argument types ends with a + void_type_node, then the formals list did *not* end + with an ellipsis. */ + + if (TREE_VALUE (tree_last (fn_arg_types)) == void_type_node) + has_ellipsis = FALSE; + } + else + { + /* This function declaration/definition was not prototyped. */ + + /* Note that all non-prototyped function *declarations* are + assumed to represent varargs functions (until proven + otherwise). */ + + if (DECL_INITIAL (decl)) /* if this is a func definition */ + { + if (!arg_decls) + has_ellipsis = FALSE; /* no args == (void) */ + else + { + /* For a non-prototyped function definition which + declares one or more formal parameters, if the name + of the first formal parameter is *not* + __builtin_va_alist then we must assume that this + is *not* a varargs function. */ + + if (DECL_NAME (arg_decls) + && strcmp (IDENTIFIER_POINTER (DECL_NAME (arg_decls)), + "__builtin_va_alist")) + has_ellipsis = FALSE; + } + } + } + + if (has_ellipsis) + output_die (output_unspecified_parameters_die, decl); + } + } + + /* Output Dwarf info for all of the stuff within the body of the + function (if it has one - it may be just a declaration). */ + + { + register tree outer_scope = DECL_INITIAL (decl); + + if (outer_scope && TREE_CODE (outer_scope) != ERROR_MARK) + { + /* Note that here, `outer_scope' is a pointer to the outermost + BLOCK node created to represent a function. + This outermost BLOCK actually represents the outermost + binding contour for the function, i.e. the contour in which + the function's formal parameters and labels get declared. + + Curiously, it appears that the front end doesn't actually + put the PARM_DECL nodes for the current function onto the + BLOCK_VARS list for this outer scope. (They are strung + off of the DECL_ARGUMENTS list for the function instead.) + The BLOCK_VARS list for the `outer_scope' does provide us + with a list of the LABEL_DECL nodes for the function however, + and we output DWARF info for those here. + + Just within the `outer_scope' there will be another BLOCK + node representing the function's outermost pair of curly + braces. We musn't generate a lexical_block DIE for this + outermost pair of curly braces because that is not really an + independent scope according to ANSI C rules. Rather, it is + the same scope in which the parameters were declared. */ + + { + register tree label; + + for (label = BLOCK_VARS (outer_scope); + label; + label = TREE_CHAIN (label)) + output_decl (label, outer_scope); + } + + /* Note here that `BLOCK_SUBBLOCKS (outer_scope)' points to a + list of BLOCK nodes which is always only one element long. + That one element represents the outermost pair of curley + braces for the function body. */ + + output_decls_for_scope (BLOCK_SUBBLOCKS (outer_scope)); + + /* Finally, force out any pending types which are local to the + outermost block of this function definition. These will + all have a TYPE_CONTEXT which points to the FUNCTION_DECL + node itself. */ + + output_pending_types_for_scope (decl); + } + } + + /* Generate a terminator for the list of stuff `owned' by this + function. */ + + end_sibling_chain (); + + break; + + case TYPE_DECL: + /* If we are in terse mode, don't generate any DIEs to represent + any actual typedefs. Note that even when we are in terse mode, + we must still output DIEs to represent those tagged types which + are used (directly or indirectly) in the specification of either + a return type or a formal parameter type of some function. */ + + if (debug_info_level <= DINFO_LEVEL_TERSE) + if (DECL_NAME (decl) != NULL + || ! TYPE_USED_FOR_FUNCTION (TREE_TYPE (decl))) + return; + + /* In the special case of a null-named TYPE_DECL node (representing + the declaration of some type tag), if the given TYPE_DECL is + marked as having been instantiated from some other (original) + TYPE_DECL node (e.g. one which was generated within the original + definition of an inline function) we have to generate a special + (abbreviated) TAG_structure_type, TAG_union_type, or + TAG_enumeration-type DIE here. */ + + if (! DECL_NAME (decl) && DECL_ABSTRACT_ORIGIN (decl)) + { + output_tagged_type_instantiation (TREE_TYPE (decl)); + return; + } + + output_type (TREE_TYPE (decl), containing_scope); + + /* Note that unlike the gcc front end (which generates a NULL named + TYPE_DECL node for each complete tagged type, each array type, + and each function type node created) the g++ front end generates + a *named* TYPE_DECL node for each tagged type node created. + Unfortunately, these g++ TYPE_DECL nodes cause us to output many + superfluous and unnecessary TAG_typedef DIEs here. When g++ is + fixed to stop generating these superfluous named TYPE_DECL nodes, + the superfluous TAG_typedef DIEs will likewise cease. */ + + if (DECL_NAME (decl)) + /* Output a DIE to represent the typedef itself. */ + output_die (output_typedef_die, decl); + break; + + case LABEL_DECL: + if (debug_info_level >= DINFO_LEVEL_NORMAL) + output_die (output_label_die, decl); + break; + + case VAR_DECL: + /* If we are conforming to the DWARF version 1 specification, don't + generated any DIEs to represent mere external object declarations. */ + +#if (DWARF_VERSION <= 1) + if (DECL_EXTERNAL (decl) && ! TREE_PUBLIC (decl)) + break; +#endif + + /* If we are in terse mode, don't generate any DIEs to represent + any variable declarations or definitions. */ + + if (debug_info_level <= DINFO_LEVEL_TERSE) + break; + + /* Output any DIEs that are needed to specify the type of this data + object. */ + + output_type (TREE_TYPE (decl), containing_scope); + + /* If the following DIE will represent a data object definition for a + data object with "extern" linkage, output a special "pubnames" DIE + label just ahead of the actual DIE. A reference to this label + was already generated in the .debug_pubnames section sub-entry + for this data object definition. */ + + if (TREE_PUBLIC (decl) && ! DECL_ABSTRACT (decl)) + { + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + sprintf (label, PUB_DIE_LABEL_FMT, next_pubname_number++); + ASM_OUTPUT_LABEL (asm_out_file, label); + } + + /* Now output the DIE to represent the data object itself. This gets + complicated because of the possibility that the VAR_DECL really + represents an inlined instance of a formal parameter for an inline + function. */ + + { + register void (*func) (); + register tree origin = decl_ultimate_origin (decl); + + if (origin != NULL && TREE_CODE (origin) == PARM_DECL) + func = output_formal_parameter_die; + else + { + if (TREE_PUBLIC (decl) || DECL_EXTERNAL (decl)) + func = output_global_variable_die; + else + func = output_local_variable_die; + } + output_die (func, decl); + } + break; + + case FIELD_DECL: + /* Ignore the nameless fields that are used to skip bits. */ + if (DECL_NAME (decl) != 0) + { + output_type (member_declared_type (decl), containing_scope); + output_die (output_member_die, decl); + } + break; + + case PARM_DECL: + /* Force out the type of this formal, if it was not forced out yet. + Note that here we can run afowl of a bug in "classic" svr4 SDB. + It should be able to grok the presence of type DIEs within a list + of TAG_formal_parameter DIEs, but it doesn't. */ + + output_type (TREE_TYPE (decl), containing_scope); + output_die (output_formal_parameter_die, decl); + break; + + default: + abort (); + } +} + +void +dwarfout_file_scope_decl (decl, set_finalizing) + register tree decl; + register int set_finalizing; +{ + if (TREE_CODE (decl) == ERROR_MARK) + return; + + /* If this ..._DECL node is marked to be ignored, then ignore it. We + gotta hope that the node in question doesn't represent a function + definition. If it does, then totally ignoring it is bound to screw + up our count of blocks, and that it turn will completely screw up the + the labels we will reference in subsequent AT_low_pc and AT_high_pc + attributes (for subsequent blocks). (It's too bad that BLOCK nodes + don't carry their own sequence numbers with them!) */ + + if (DECL_IGNORED_P (decl)) + { + if (TREE_CODE (decl) == FUNCTION_DECL && DECL_INITIAL (decl) != NULL) + abort (); + return; + } + + switch (TREE_CODE (decl)) + { + case FUNCTION_DECL: + + /* Ignore this FUNCTION_DECL if it refers to a builtin declaration of + a builtin function. Explicit programmer-supplied declarations of + these same functions should NOT be ignored however. */ + + if (DECL_EXTERNAL (decl) && DECL_FUNCTION_CODE (decl)) + return; + + /* What we would really like to do here is to filter out all mere + file-scope declarations of file-scope functions which are never + referenced later within this translation unit (and keep all of + ones that *are* referenced later on) but we aren't clarvoiant, + so we have no idea which functions will be referenced in the + future (i.e. later on within the current translation unit). + So here we just ignore all file-scope function declarations + which are not also definitions. If and when the debugger needs + to know something about these funcstion, it wil have to hunt + around and find the DWARF information associated with the + *definition* of the function. + + Note that we can't just check `DECL_EXTERNAL' to find out which + FUNCTION_DECL nodes represent definitions and which ones represent + mere declarations. We have to check `DECL_INITIAL' instead. That's + because the C front-end supports some weird semantics for "extern + inline" function definitions. These can get inlined within the + current translation unit (an thus, we need to generate DWARF info + for their abstract instances so that the DWARF info for the + concrete inlined instances can have something to refer to) but + the compiler never generates any out-of-lines instances of such + things (despite the fact that they *are* definitions). The + important point is that the C front-end marks these "extern inline" + functions as DECL_EXTERNAL, but we need to generate DWARf for them + anyway. + + Note that the C++ front-end also plays some similar games for inline + function definitions appearing within include files which also + contain `#pragma interface' pragmas. */ + + if (DECL_INITIAL (decl) == NULL_TREE) + return; + + if (TREE_PUBLIC (decl) + && ! DECL_EXTERNAL (decl) + && ! DECL_ABSTRACT (decl)) + { + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + /* Output a .debug_pubnames entry for a public function + defined in this compilation unit. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, PUBNAMES_SECTION); + sprintf (label, PUB_DIE_LABEL_FMT, next_pubname_number); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, label); + ASM_OUTPUT_DWARF_STRING (asm_out_file, + IDENTIFIER_POINTER (DECL_NAME (decl))); + ASM_OUTPUT_POP_SECTION (asm_out_file); + } + + break; + + case VAR_DECL: + + /* Ignore this VAR_DECL if it refers to a file-scope extern data + object declaration and if the declaration was never even + referenced from within this entire compilation unit. We + suppress these DIEs in order to save space in the .debug section + (by eliminating entries which are probably useless). Note that + we must not suppress block-local extern declarations (whether + used or not) because that would screw-up the debugger's name + lookup mechanism and cause it to miss things which really ought + to be in scope at a given point. */ + + if (DECL_EXTERNAL (decl) && !TREE_USED (decl)) + return; + + if (TREE_PUBLIC (decl) + && ! DECL_EXTERNAL (decl) + && GET_CODE (DECL_RTL (decl)) == MEM + && ! DECL_ABSTRACT (decl)) + { + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + if (debug_info_level >= DINFO_LEVEL_NORMAL) + { + /* Output a .debug_pubnames entry for a public variable + defined in this compilation unit. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, PUBNAMES_SECTION); + sprintf (label, PUB_DIE_LABEL_FMT, next_pubname_number); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, label); + ASM_OUTPUT_DWARF_STRING (asm_out_file, + IDENTIFIER_POINTER (DECL_NAME (decl))); + ASM_OUTPUT_POP_SECTION (asm_out_file); + } + + if (DECL_INITIAL (decl) == NULL) + { + /* Output a .debug_aranges entry for a public variable + which is tentatively defined in this compilation unit. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, ARANGES_SECTION); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, + IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, + (unsigned) int_size_in_bytes (TREE_TYPE (decl))); + ASM_OUTPUT_POP_SECTION (asm_out_file); + } + } + + /* If we are in terse mode, don't generate any DIEs to represent + any variable declarations or definitions. */ + + if (debug_info_level <= DINFO_LEVEL_TERSE) + return; + + break; + + case TYPE_DECL: + /* Don't bother trying to generate any DIEs to represent any of the + normal built-in types for the language we are compiling, except + in cases where the types in question are *not* DWARF fundamental + types. We make an exception in the case of non-fundamental types + for the sake of objective C (and perhaps C++) because the GNU + front-ends for these languages may in fact create certain "built-in" + types which are (for example) RECORD_TYPEs. In such cases, we + really need to output these (non-fundamental) types because other + DIEs may contain references to them. */ + + if (DECL_SOURCE_LINE (decl) == 0 + && type_is_fundamental (TREE_TYPE (decl))) + return; + + /* If we are in terse mode, don't generate any DIEs to represent + any actual typedefs. Note that even when we are in terse mode, + we must still output DIEs to represent those tagged types which + are used (directly or indirectly) in the specification of either + a return type or a formal parameter type of some function. */ + + if (debug_info_level <= DINFO_LEVEL_TERSE) + if (DECL_NAME (decl) != NULL + || ! TYPE_USED_FOR_FUNCTION (TREE_TYPE (decl))) + return; + + break; + + default: + return; + } + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, DEBUG_SECTION); + finalizing = set_finalizing; + output_decl (decl, NULL_TREE); + + /* NOTE: The call above to `output_decl' may have caused one or more + file-scope named types (i.e. tagged types) to be placed onto the + pending_types_list. We have to get those types off of that list + at some point, and this is the perfect time to do it. If we didn't + take them off now, they might still be on the list when cc1 finally + exits. That might be OK if it weren't for the fact that when we put + types onto the pending_types_list, we set the TREE_ASM_WRITTEN flag + for these types, and that causes them never to be output unless + `output_pending_types_for_scope' takes them off of the list and un-sets + their TREE_ASM_WRITTEN flags. */ + + output_pending_types_for_scope (NULL_TREE); + + /* The above call should have totally emptied the pending_types_list. */ + + assert (pending_types == 0); + + ASM_OUTPUT_POP_SECTION (asm_out_file); + + if (TREE_CODE (decl) == FUNCTION_DECL && DECL_INITIAL (decl) != NULL) + current_funcdef_number++; +} + +/* Output a marker (i.e. a label) for the beginning of the generated code + for a lexical block. */ + +void +dwarfout_begin_block (blocknum) + register unsigned blocknum; +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + text_section (); + sprintf (label, BLOCK_BEGIN_LABEL_FMT, blocknum); + ASM_OUTPUT_LABEL (asm_out_file, label); +} + +/* Output a marker (i.e. a label) for the end of the generated code + for a lexical block. */ + +void +dwarfout_end_block (blocknum) + register unsigned blocknum; +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + text_section (); + sprintf (label, BLOCK_END_LABEL_FMT, blocknum); + ASM_OUTPUT_LABEL (asm_out_file, label); +} + +/* Output a marker (i.e. a label) at a point in the assembly code which + corresponds to a given source level label. */ + +void +dwarfout_label (insn) + register rtx insn; +{ + if (debug_info_level >= DINFO_LEVEL_NORMAL) + { + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + text_section (); + sprintf (label, INSN_LABEL_FMT, current_funcdef_number, + (unsigned) INSN_UID (insn)); + ASM_OUTPUT_LABEL (asm_out_file, label); + } +} + +/* Output a marker (i.e. a label) for the point in the generated code where + the real body of the function begins (after parameters have been moved + to their home locations). */ + +void +dwarfout_begin_function () +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + text_section (); + sprintf (label, BODY_BEGIN_LABEL_FMT, current_funcdef_number); + ASM_OUTPUT_LABEL (asm_out_file, label); +} + +/* Output a marker (i.e. a label) for the point in the generated code where + the real body of the function ends (just before the epilogue code). */ + +void +dwarfout_end_function () +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + text_section (); + sprintf (label, BODY_END_LABEL_FMT, current_funcdef_number); + ASM_OUTPUT_LABEL (asm_out_file, label); +} + +/* Output a marker (i.e. a label) for the absolute end of the generated code + for a function definition. This gets called *after* the epilogue code + has been generated. */ + +void +dwarfout_end_epilogue () +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + /* Output a label to mark the endpoint of the code generated for this + function. */ + + sprintf (label, FUNC_END_LABEL_FMT, current_funcdef_number); + ASM_OUTPUT_LABEL (asm_out_file, label); +} + +static void +shuffle_filename_entry (new_zeroth) + register filename_entry *new_zeroth; +{ + filename_entry temp_entry; + register filename_entry *limit_p; + register filename_entry *move_p; + + if (new_zeroth == &filename_table[0]) + return; + + temp_entry = *new_zeroth; + + /* Shift entries up in the table to make room at [0]. */ + + limit_p = &filename_table[0]; + for (move_p = new_zeroth; move_p > limit_p; move_p--) + *move_p = *(move_p-1); + + /* Install the found entry at [0]. */ + + filename_table[0] = temp_entry; +} + +/* Create a new (string) entry for the .debug_sfnames section. */ + +static void +generate_new_sfname_entry () +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, SFNAMES_SECTION); + sprintf (label, SFNAMES_ENTRY_LABEL_FMT, filename_table[0].number); + ASM_OUTPUT_LABEL (asm_out_file, label); + ASM_OUTPUT_DWARF_STRING (asm_out_file, + filename_table[0].name + ? filename_table[0].name + : ""); + ASM_OUTPUT_POP_SECTION (asm_out_file); +} + +/* Lookup a filename (in the list of filenames that we know about here in + dwarfout.c) and return its "index". The index of each (known) filename + is just a unique number which is associated with only that one filename. + We need such numbers for the sake of generating labels (in the + .debug_sfnames section) and references to those unique labels (in the + .debug_srcinfo and .debug_macinfo sections). + + If the filename given as an argument is not found in our current list, + add it to the list and assign it the next available unique index number. + + Whatever we do (i.e. whether we find a pre-existing filename or add a new + one), we shuffle the filename found (or added) up to the zeroth entry of + our list of filenames (which is always searched linearly). We do this so + as to optimize the most common case for these filename lookups within + dwarfout.c. The most common case by far is the case where we call + lookup_filename to lookup the very same filename that we did a lookup + on the last time we called lookup_filename. We make sure that this + common case is fast because such cases will constitute 99.9% of the + lookups we ever do (in practice). + + If we add a new filename entry to our table, we go ahead and generate + the corresponding entry in the .debug_sfnames section right away. + Doing so allows us to avoid tickling an assembler bug (present in some + m68k assemblers) which yields assembly-time errors in cases where the + difference of two label addresses is taken and where the two labels + are in a section *other* than the one where the difference is being + calculated, and where at least one of the two symbol references is a + forward reference. (This bug could be tickled by our .debug_srcinfo + entries if we don't output their corresponding .debug_sfnames entries + before them.) +*/ + +static unsigned +lookup_filename (file_name) + char *file_name; +{ + register filename_entry *search_p; + register filename_entry *limit_p = &filename_table[ft_entries]; + + for (search_p = filename_table; search_p < limit_p; search_p++) + if (!strcmp (file_name, search_p->name)) + { + /* When we get here, we have found the filename that we were + looking for in the filename_table. Now we want to make sure + that it gets moved to the zero'th entry in the table (if it + is not already there) so that subsequent attempts to find the + same filename will find it as quickly as possible. */ + + shuffle_filename_entry (search_p); + return filename_table[0].number; + } + + /* We come here whenever we have a new filename which is not registered + in the current table. Here we add it to the table. */ + + /* Prepare to add a new table entry by making sure there is enough space + in the table to do so. If not, expand the current table. */ + + if (ft_entries == ft_entries_allocated) + { + ft_entries_allocated += FT_ENTRIES_INCREMENT; + filename_table + = (filename_entry *) + xrealloc (filename_table, + ft_entries_allocated * sizeof (filename_entry)); + } + + /* Initially, add the new entry at the end of the filename table. */ + + filename_table[ft_entries].number = ft_entries; + filename_table[ft_entries].name = xstrdup (file_name); + + /* Shuffle the new entry into filename_table[0]. */ + + shuffle_filename_entry (&filename_table[ft_entries]); + + if (debug_info_level >= DINFO_LEVEL_NORMAL) + generate_new_sfname_entry (); + + ft_entries++; + return filename_table[0].number; +} + +static void +generate_srcinfo_entry (line_entry_num, files_entry_num) + unsigned line_entry_num; + unsigned files_entry_num; +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, SRCINFO_SECTION); + sprintf (label, LINE_ENTRY_LABEL_FMT, line_entry_num); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, label, LINE_BEGIN_LABEL); + sprintf (label, SFNAMES_ENTRY_LABEL_FMT, files_entry_num); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, label, SFNAMES_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); +} + +void +dwarfout_line (filename, line) + register char *filename; + register unsigned line; +{ + if (debug_info_level >= DINFO_LEVEL_NORMAL) + { + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + static unsigned last_line_entry_num = 0; + static unsigned prev_file_entry_num = (unsigned) -1; + register unsigned this_file_entry_num = lookup_filename (filename); + + text_section (); + sprintf (label, LINE_CODE_LABEL_FMT, ++last_line_entry_num); + ASM_OUTPUT_LABEL (asm_out_file, label); + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, LINE_SECTION); + + if (this_file_entry_num != prev_file_entry_num) + { + char line_entry_label[MAX_ARTIFICIAL_LABEL_BYTES]; + + sprintf (line_entry_label, LINE_ENTRY_LABEL_FMT, last_line_entry_num); + ASM_OUTPUT_LABEL (asm_out_file, line_entry_label); + } + + { + register char *tail = rindex (filename, '/'); + + if (tail != NULL) + filename = tail; + } + + fprintf (asm_out_file, "\t%s\t%u\t%s %s:%u\n", + UNALIGNED_INT_ASM_OP, line, ASM_COMMENT_START, + filename, line); + ASM_OUTPUT_DWARF_DATA2 (asm_out_file, 0xffff); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, label, TEXT_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + if (this_file_entry_num != prev_file_entry_num) + generate_srcinfo_entry (last_line_entry_num, this_file_entry_num); + prev_file_entry_num = this_file_entry_num; + } +} + +/* Generate an entry in the .debug_macinfo section. */ + +static void +generate_macinfo_entry (type_and_offset, string) + register char *type_and_offset; + register char *string; +{ + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, MACINFO_SECTION); + fprintf (asm_out_file, "\t%s\t%s\n", UNALIGNED_INT_ASM_OP, type_and_offset); + ASM_OUTPUT_DWARF_STRING (asm_out_file, string); + ASM_OUTPUT_POP_SECTION (asm_out_file); +} + +void +dwarfout_start_new_source_file (filename) + register char *filename; +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + char type_and_offset[MAX_ARTIFICIAL_LABEL_BYTES*3]; + + sprintf (label, SFNAMES_ENTRY_LABEL_FMT, lookup_filename (filename)); + sprintf (type_and_offset, "0x%08x+%s-%s", + ((unsigned) MACINFO_start << 24), label, SFNAMES_BEGIN_LABEL); + generate_macinfo_entry (type_and_offset, ""); +} + +void +dwarfout_resume_previous_source_file (lineno) + register unsigned lineno; +{ + char type_and_offset[MAX_ARTIFICIAL_LABEL_BYTES*2]; + + sprintf (type_and_offset, "0x%08x+%u", + ((unsigned) MACINFO_resume << 24), lineno); + generate_macinfo_entry (type_and_offset, ""); +} + +/* Called from check_newline in c-parse.y. The `buffer' parameter + contains the tail part of the directive line, i.e. the part which + is past the initial whitespace, #, whitespace, directive-name, + whitespace part. */ + +void +dwarfout_define (lineno, buffer) + register unsigned lineno; + register char *buffer; +{ + static int initialized = 0; + char type_and_offset[MAX_ARTIFICIAL_LABEL_BYTES*2]; + + if (!initialized) + { + dwarfout_start_new_source_file (primary_filename); + initialized = 1; + } + sprintf (type_and_offset, "0x%08x+%u", + ((unsigned) MACINFO_define << 24), lineno); + generate_macinfo_entry (type_and_offset, buffer); +} + +/* Called from check_newline in c-parse.y. The `buffer' parameter + contains the tail part of the directive line, i.e. the part which + is past the initial whitespace, #, whitespace, directive-name, + whitespace part. */ + +void +dwarfout_undef (lineno, buffer) + register unsigned lineno; + register char *buffer; +{ + char type_and_offset[MAX_ARTIFICIAL_LABEL_BYTES*2]; + + sprintf (type_and_offset, "0x%08x+%u", + ((unsigned) MACINFO_undef << 24), lineno); + generate_macinfo_entry (type_and_offset, buffer); +} + +/* Set up for Dwarf output at the start of compilation. */ + +void +dwarfout_init (asm_out_file, main_input_filename) + register FILE *asm_out_file; + register char *main_input_filename; +{ + /* Remember the name of the primary input file. */ + + primary_filename = main_input_filename; + + /* Allocate the initial hunk of the pending_sibling_stack. */ + + pending_sibling_stack + = (unsigned *) + xmalloc (PENDING_SIBLINGS_INCREMENT * sizeof (unsigned)); + pending_siblings_allocated = PENDING_SIBLINGS_INCREMENT; + pending_siblings = 1; + + /* Allocate the initial hunk of the filename_table. */ + + filename_table + = (filename_entry *) + xmalloc (FT_ENTRIES_INCREMENT * sizeof (filename_entry)); + ft_entries_allocated = FT_ENTRIES_INCREMENT; + ft_entries = 0; + + /* Allocate the initial hunk of the pending_types_list. */ + + pending_types_list + = (tree *) xmalloc (PENDING_TYPES_INCREMENT * sizeof (tree)); + pending_types_allocated = PENDING_TYPES_INCREMENT; + pending_types = 0; + + /* Create an artificial RECORD_TYPE node which we can use in our hack + to get the DIEs representing types of formal parameters to come out + only *after* the DIEs for the formal parameters themselves. */ + + fake_containing_scope = make_node (RECORD_TYPE); + + /* Output a starting label for the .text section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, TEXT_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, TEXT_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + /* Output a starting label for the .data section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, DATA_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, DATA_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + +#if 0 /* GNU C doesn't currently use .data1. */ + /* Output a starting label for the .data1 section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, DATA1_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, DATA1_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); +#endif + + /* Output a starting label for the .rodata section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, RODATA_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, RODATA_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + +#if 0 /* GNU C doesn't currently use .rodata1. */ + /* Output a starting label for the .rodata1 section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, RODATA1_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, RODATA1_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); +#endif + + /* Output a starting label for the .bss section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, BSS_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, BSS_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + if (debug_info_level >= DINFO_LEVEL_NORMAL) + { + /* Output a starting label and an initial (compilation directory) + entry for the .debug_sfnames section. The starting label will be + referenced by the initial entry in the .debug_srcinfo section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, SFNAMES_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, SFNAMES_BEGIN_LABEL); + { + register char *pwd = getpwd (); + register unsigned len = strlen (pwd); + register char *dirname = (char *) xmalloc (len + 2); + + strcpy (dirname, pwd); + strcpy (dirname + len, "/"); + ASM_OUTPUT_DWARF_STRING (asm_out_file, dirname); + free (dirname); + } + ASM_OUTPUT_POP_SECTION (asm_out_file); + + if (debug_info_level >= DINFO_LEVEL_VERBOSE) + { + /* Output a starting label for the .debug_macinfo section. This + label will be referenced by the AT_mac_info attribute in the + TAG_compile_unit DIE. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, MACINFO_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, MACINFO_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + } + + /* Generate the initial entry for the .line section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, LINE_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, LINE_BEGIN_LABEL); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, LINE_END_LABEL, LINE_BEGIN_LABEL); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, TEXT_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + /* Generate the initial entry for the .debug_srcinfo section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, SRCINFO_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, SRCINFO_BEGIN_LABEL); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, LINE_BEGIN_LABEL); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, SFNAMES_BEGIN_LABEL); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, TEXT_BEGIN_LABEL); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, TEXT_END_LABEL); +#ifdef DWARF_TIMESTAMPS + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, time (NULL)); +#else + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, -1); +#endif + ASM_OUTPUT_POP_SECTION (asm_out_file); + + /* Generate the initial entry for the .debug_pubnames section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, PUBNAMES_SECTION); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, DEBUG_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + /* Generate the initial entry for the .debug_aranges section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, ARANGES_SECTION); + ASM_OUTPUT_DWARF_ADDR (asm_out_file, DEBUG_BEGIN_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + } + + /* Setup first DIE number == 1. */ + NEXT_DIE_NUM = next_unused_dienum++; + + /* Generate the initial DIE for the .debug section. Note that the + (string) value given in the AT_name attribute of the TAG_compile_unit + DIE will (typically) be a relative pathname and that this pathname + should be taken as being relative to the directory from which the + compiler was invoked when the given (base) source file was compiled. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, DEBUG_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, DEBUG_BEGIN_LABEL); + output_die (output_compile_unit_die, main_input_filename); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + fputc ('\n', asm_out_file); +} + +/* Output stuff that dwarf requires at the end of every file. */ + +void +dwarfout_finish () +{ + char label[MAX_ARTIFICIAL_LABEL_BYTES]; + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, DEBUG_SECTION); + + /* Mark the end of the chain of siblings which represent all file-scope + declarations in this compilation unit. */ + + /* The (null) DIE which represents the terminator for the (sibling linked) + list of file-scope items is *special*. Normally, we would just call + end_sibling_chain at this point in order to output a word with the + value `4' and that word would act as the terminator for the list of + DIEs describing file-scope items. Unfortunately, if we were to simply + do that, the label that would follow this DIE in the .debug section + (i.e. `..D2') would *not* be properly aligned (as it must be on some + machines) to a 4 byte boundary. + + In order to force the label `..D2' to get aligned to a 4 byte boundary, + the trick used is to insert extra (otherwise useless) padding bytes + into the (null) DIE that we know must precede the ..D2 label in the + .debug section. The amount of padding required can be anywhere between + 0 and 3 bytes. The length word at the start of this DIE (i.e. the one + with the padding) would normally contain the value 4, but now it will + also have to include the padding bytes, so it will instead have some + value in the range 4..7. + + Fortunately, the rules of Dwarf say that any DIE whose length word + contains *any* value less than 8 should be treated as a null DIE, so + this trick works out nicely. Clever, eh? Don't give me any credit + (or blame). I didn't think of this scheme. I just conformed to it. + */ + + output_die (output_padded_null_die, (void *)0); + dienum_pop (); + + sprintf (label, DIE_BEGIN_LABEL_FMT, NEXT_DIE_NUM); + ASM_OUTPUT_LABEL (asm_out_file, label); /* should be ..D2 */ + ASM_OUTPUT_POP_SECTION (asm_out_file); + + /* Output a terminator label for the .text section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, TEXT_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, TEXT_END_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + /* Output a terminator label for the .data section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, DATA_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, DATA_END_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + +#if 0 /* GNU C doesn't currently use .data1. */ + /* Output a terminator label for the .data1 section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, DATA1_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, DATA1_END_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); +#endif + + /* Output a terminator label for the .rodata section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, RODATA_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, RODATA_END_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + +#if 0 /* GNU C doesn't currently use .rodata1. */ + /* Output a terminator label for the .rodata1 section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, RODATA1_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, RODATA1_END_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); +#endif + + /* Output a terminator label for the .bss section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, BSS_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, BSS_END_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + if (debug_info_level >= DINFO_LEVEL_NORMAL) + { + /* Output a terminating entry for the .line section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, LINE_SECTION); + ASM_OUTPUT_LABEL (asm_out_file, LINE_LAST_ENTRY_LABEL); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, 0); + ASM_OUTPUT_DWARF_DATA2 (asm_out_file, 0xffff); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, TEXT_END_LABEL, TEXT_BEGIN_LABEL); + ASM_OUTPUT_LABEL (asm_out_file, LINE_END_LABEL); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + /* Output a terminating entry for the .debug_srcinfo section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, SRCINFO_SECTION); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, + LINE_LAST_ENTRY_LABEL, LINE_BEGIN_LABEL); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, -1); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + if (debug_info_level >= DINFO_LEVEL_VERBOSE) + { + /* Output terminating entries for the .debug_macinfo section. */ + + dwarfout_resume_previous_source_file (0); + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, MACINFO_SECTION); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, 0); + ASM_OUTPUT_DWARF_STRING (asm_out_file, ""); + ASM_OUTPUT_POP_SECTION (asm_out_file); + } + + /* Generate the terminating entry for the .debug_pubnames section. */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, PUBNAMES_SECTION); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, 0); + ASM_OUTPUT_DWARF_STRING (asm_out_file, ""); + ASM_OUTPUT_POP_SECTION (asm_out_file); + + /* Generate the terminating entries for the .debug_aranges section. + + Note that we want to do this only *after* we have output the end + labels (for the various program sections) which we are going to + refer to here. This allows us to work around a bug in the m68k + svr4 assembler. That assembler gives bogus assembly-time errors + if (within any given section) you try to take the difference of + two relocatable symbols, both of which are located within some + other section, and if one (or both?) of the symbols involved is + being forward-referenced. By generating the .debug_aranges + entries at this late point in the assembly output, we skirt the + issue simply by avoiding forward-references. + */ + + fputc ('\n', asm_out_file); + ASM_OUTPUT_PUSH_SECTION (asm_out_file, ARANGES_SECTION); + + ASM_OUTPUT_DWARF_ADDR (asm_out_file, TEXT_BEGIN_LABEL); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, TEXT_END_LABEL, TEXT_BEGIN_LABEL); + + ASM_OUTPUT_DWARF_ADDR (asm_out_file, DATA_BEGIN_LABEL); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, DATA_END_LABEL, DATA_BEGIN_LABEL); + +#if 0 /* GNU C doesn't currently use .data1. */ + ASM_OUTPUT_DWARF_ADDR (asm_out_file, DATA1_BEGIN_LABEL); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, DATA1_END_LABEL, + DATA1_BEGIN_LABEL); +#endif + + ASM_OUTPUT_DWARF_ADDR (asm_out_file, RODATA_BEGIN_LABEL); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, RODATA_END_LABEL, + RODATA_BEGIN_LABEL); + +#if 0 /* GNU C doesn't currently use .rodata1. */ + ASM_OUTPUT_DWARF_ADDR (asm_out_file, RODATA1_BEGIN_LABEL); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, RODATA1_END_LABEL, + RODATA1_BEGIN_LABEL); +#endif + + ASM_OUTPUT_DWARF_ADDR (asm_out_file, BSS_BEGIN_LABEL); + ASM_OUTPUT_DWARF_DELTA4 (asm_out_file, BSS_END_LABEL, BSS_BEGIN_LABEL); + + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, 0); + ASM_OUTPUT_DWARF_DATA4 (asm_out_file, 0); + + ASM_OUTPUT_POP_SECTION (asm_out_file); + } +} + +#endif /* DWARF_DEBUGGING_INFO */ diff --git a/gnu/usr.bin/cc/lib/emit-rtl.c b/gnu/usr.bin/cc/lib/emit-rtl.c new file mode 100644 index 000000000000..b63f0c8b4791 --- /dev/null +++ b/gnu/usr.bin/cc/lib/emit-rtl.c @@ -0,0 +1,3137 @@ +/* Emit RTL for the GNU C-Compiler expander. + Copyright (C) 1987, 1988, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* Middle-to-low level generation of rtx code and insns. + + This file contains the functions `gen_rtx', `gen_reg_rtx' + and `gen_label_rtx' that are the usual ways of creating rtl + expressions for most purposes. + + It also has the functions for creating insns and linking + them in the doubly-linked chain. + + The patterns of the insns are created by machine-dependent + routines in insn-emit.c, which is generated automatically from + the machine description. These routines use `gen_rtx' to make + the individual rtx's of the pattern; what is machine dependent + is the kind of rtx's they make and what arguments they use. */ + +#include "config.h" +#include "gvarargs.h" +#include "rtl.h" +#include "flags.h" +#include "function.h" +#include "expr.h" +#include "regs.h" +#include "insn-config.h" +#include "real.h" +#include + +/* This is reset to LAST_VIRTUAL_REGISTER + 1 at the start of each function. + After rtl generation, it is 1 plus the largest register number used. */ + +int reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; + +/* This is *not* reset after each function. It gives each CODE_LABEL + in the entire compilation a unique label number. */ + +static int label_num = 1; + +/* Lowest label number in current function. */ + +static int first_label_num; + +/* Highest label number in current function. + Zero means use the value of label_num instead. + This is nonzero only when belatedly compiling an inline function. */ + +static int last_label_num; + +/* Value label_num had when set_new_first_and_last_label_number was called. + If label_num has not changed since then, last_label_num is valid. */ + +static int base_label_num; + +/* Nonzero means do not generate NOTEs for source line numbers. */ + +static int no_line_numbers; + +/* Commonly used rtx's, so that we only need space for one copy. + These are initialized once for the entire compilation. + All of these except perhaps the floating-point CONST_DOUBLEs + are unique; no other rtx-object will be equal to any of these. */ + +rtx pc_rtx; /* (PC) */ +rtx cc0_rtx; /* (CC0) */ +rtx cc1_rtx; /* (CC1) (not actually used nowadays) */ +rtx const0_rtx; /* (CONST_INT 0) */ +rtx const1_rtx; /* (CONST_INT 1) */ +rtx const2_rtx; /* (CONST_INT 2) */ +rtx constm1_rtx; /* (CONST_INT -1) */ +rtx const_true_rtx; /* (CONST_INT STORE_FLAG_VALUE) */ + +/* We record floating-point CONST_DOUBLEs in each floating-point mode for + the values of 0, 1, and 2. For the integer entries and VOIDmode, we + record a copy of const[012]_rtx. */ + +rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; + +REAL_VALUE_TYPE dconst0; +REAL_VALUE_TYPE dconst1; +REAL_VALUE_TYPE dconst2; +REAL_VALUE_TYPE dconstm1; + +/* All references to the following fixed hard registers go through + these unique rtl objects. On machines where the frame-pointer and + arg-pointer are the same register, they use the same unique object. + + After register allocation, other rtl objects which used to be pseudo-regs + may be clobbered to refer to the frame-pointer register. + But references that were originally to the frame-pointer can be + distinguished from the others because they contain frame_pointer_rtx. + + In an inline procedure, the stack and frame pointer rtxs may not be + used for anything else. */ +rtx stack_pointer_rtx; /* (REG:Pmode STACK_POINTER_REGNUM) */ +rtx frame_pointer_rtx; /* (REG:Pmode FRAME_POINTER_REGNUM) */ +rtx arg_pointer_rtx; /* (REG:Pmode ARG_POINTER_REGNUM) */ +rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */ +rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */ +rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ +rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ +rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ + +rtx virtual_incoming_args_rtx; /* (REG:Pmode VIRTUAL_INCOMING_ARGS_REGNUM) */ +rtx virtual_stack_vars_rtx; /* (REG:Pmode VIRTUAL_STACK_VARS_REGNUM) */ +rtx virtual_stack_dynamic_rtx; /* (REG:Pmode VIRTUAL_STACK_DYNAMIC_REGNUM) */ +rtx virtual_outgoing_args_rtx; /* (REG:Pmode VIRTUAL_OUTGOING_ARGS_REGNUM) */ + +/* We make one copy of (const_int C) where C is in + [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] + to save space during the compilation and simplify comparisons of + integers. */ + +#define MAX_SAVED_CONST_INT 64 + +static rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; + +/* The ends of the doubly-linked chain of rtl for the current function. + Both are reset to null at the start of rtl generation for the function. + + start_sequence saves both of these on `sequence_stack' and then + starts a new, nested sequence of insns. */ + +static rtx first_insn = NULL; +static rtx last_insn = NULL; + +/* INSN_UID for next insn emitted. + Reset to 1 for each function compiled. */ + +static int cur_insn_uid = 1; + +/* Line number and source file of the last line-number NOTE emitted. + This is used to avoid generating duplicates. */ + +static int last_linenum = 0; +static char *last_filename = 0; + +/* A vector indexed by pseudo reg number. The allocated length + of this vector is regno_pointer_flag_length. Since this + vector is needed during the expansion phase when the total + number of registers in the function is not yet known, + it is copied and made bigger when necessary. */ + +char *regno_pointer_flag; +int regno_pointer_flag_length; + +/* Indexed by pseudo register number, gives the rtx for that pseudo. + Allocated in parallel with regno_pointer_flag. */ + +rtx *regno_reg_rtx; + +/* Stack of pending (incomplete) sequences saved by `start_sequence'. + Each element describes one pending sequence. + The main insn-chain is saved in the last element of the chain, + unless the chain is empty. */ + +struct sequence_stack *sequence_stack; + +/* start_sequence and gen_sequence can make a lot of rtx expressions which are + shortly thrown away. We use two mechanisms to prevent this waste: + + First, we keep a list of the expressions used to represent the sequence + stack in sequence_element_free_list. + + Second, for sizes up to 5 elements, we keep a SEQUENCE and its associated + rtvec for use by gen_sequence. One entry for each size is sufficient + because most cases are calls to gen_sequence followed by immediately + emitting the SEQUENCE. Reuse is safe since emitting a sequence is + destructive on the insn in it anyway and hence can't be redone. + + We do not bother to save this cached data over nested function calls. + Instead, we just reinitialize them. */ + +#define SEQUENCE_RESULT_SIZE 5 + +static struct sequence_stack *sequence_element_free_list; +static rtx sequence_result[SEQUENCE_RESULT_SIZE]; + +extern int rtx_equal_function_value_matters; + +/* Filename and line number of last line-number note, + whether we actually emitted it or not. */ +extern char *emit_filename; +extern int emit_lineno; + +rtx change_address (); +void init_emit (); + +/* rtx gen_rtx (code, mode, [element1, ..., elementn]) +** +** This routine generates an RTX of the size specified by +** , which is an RTX code. The RTX structure is initialized +** from the arguments through , which are +** interpreted according to the specific RTX type's format. The +** special machine mode associated with the rtx (if any) is specified +** in . +** +** gen_rtx can be invoked in a way which resembles the lisp-like +** rtx it will generate. For example, the following rtx structure: +** +** (plus:QI (mem:QI (reg:SI 1)) +** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3)))) +** +** ...would be generated by the following C code: +** +** gen_rtx (PLUS, QImode, +** gen_rtx (MEM, QImode, +** gen_rtx (REG, SImode, 1)), +** gen_rtx (MEM, QImode, +** gen_rtx (PLUS, SImode, +** gen_rtx (REG, SImode, 2), +** gen_rtx (REG, SImode, 3)))), +*/ + +/*VARARGS2*/ +rtx +gen_rtx (va_alist) + va_dcl +{ + va_list p; + enum rtx_code code; + enum machine_mode mode; + register int i; /* Array indices... */ + register char *fmt; /* Current rtx's format... */ + register rtx rt_val; /* RTX to return to caller... */ + + va_start (p); + code = va_arg (p, enum rtx_code); + mode = va_arg (p, enum machine_mode); + + if (code == CONST_INT) + { + HOST_WIDE_INT arg = va_arg (p, HOST_WIDE_INT); + + if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) + return const_int_rtx[arg + MAX_SAVED_CONST_INT]; + + if (const_true_rtx && arg == STORE_FLAG_VALUE) + return const_true_rtx; + + rt_val = rtx_alloc (code); + INTVAL (rt_val) = arg; + } + else if (code == REG) + { + int regno = va_arg (p, int); + + /* In case the MD file explicitly references the frame pointer, have + all such references point to the same frame pointer. This is used + during frame pointer elimination to distinguish the explicit + references to these registers from pseudos that happened to be + assigned to them. + + If we have eliminated the frame pointer or arg pointer, we will + be using it as a normal register, for example as a spill register. + In such cases, we might be accessing it in a mode that is not + Pmode and therefore cannot use the pre-allocated rtx. + + Also don't do this when we are making new REGs in reload, + since we don't want to get confused with the real pointers. */ + + if (frame_pointer_rtx && regno == FRAME_POINTER_REGNUM && mode == Pmode + && ! reload_in_progress) + return frame_pointer_rtx; +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + if (arg_pointer_rtx && regno == ARG_POINTER_REGNUM && mode == Pmode + && ! reload_in_progress) + return arg_pointer_rtx; +#endif + if (stack_pointer_rtx && regno == STACK_POINTER_REGNUM && mode == Pmode + && ! reload_in_progress) + return stack_pointer_rtx; + else + { + rt_val = rtx_alloc (code); + rt_val->mode = mode; + REGNO (rt_val) = regno; + return rt_val; + } + } + else + { + rt_val = rtx_alloc (code); /* Allocate the storage space. */ + rt_val->mode = mode; /* Store the machine mode... */ + + fmt = GET_RTX_FORMAT (code); /* Find the right format... */ + for (i = 0; i < GET_RTX_LENGTH (code); i++) + { + switch (*fmt++) + { + case '0': /* Unused field. */ + break; + + case 'i': /* An integer? */ + XINT (rt_val, i) = va_arg (p, int); + break; + + case 'w': /* A wide integer? */ + XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT); + break; + + case 's': /* A string? */ + XSTR (rt_val, i) = va_arg (p, char *); + break; + + case 'e': /* An expression? */ + case 'u': /* An insn? Same except when printing. */ + XEXP (rt_val, i) = va_arg (p, rtx); + break; + + case 'E': /* An RTX vector? */ + XVEC (rt_val, i) = va_arg (p, rtvec); + break; + + default: + abort (); + } + } + } + va_end (p); + return rt_val; /* Return the new RTX... */ +} + +/* gen_rtvec (n, [rt1, ..., rtn]) +** +** This routine creates an rtvec and stores within it the +** pointers to rtx's which are its arguments. +*/ + +/*VARARGS1*/ +rtvec +gen_rtvec (va_alist) + va_dcl +{ + int n, i; + va_list p; + rtx *vector; + + va_start (p); + n = va_arg (p, int); + + if (n == 0) + return NULL_RTVEC; /* Don't allocate an empty rtvec... */ + + vector = (rtx *) alloca (n * sizeof (rtx)); + for (i = 0; i < n; i++) + vector[i] = va_arg (p, rtx); + va_end (p); + + return gen_rtvec_v (n, vector); +} + +rtvec +gen_rtvec_v (n, argp) + int n; + rtx *argp; +{ + register int i; + register rtvec rt_val; + + if (n == 0) + return NULL_RTVEC; /* Don't allocate an empty rtvec... */ + + rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ + + for (i = 0; i < n; i++) + rt_val->elem[i].rtx = *argp++; + + return rt_val; +} + +/* Generate a REG rtx for a new pseudo register of mode MODE. + This pseudo is assigned the next sequential register number. */ + +rtx +gen_reg_rtx (mode) + enum machine_mode mode; +{ + register rtx val; + + /* Don't let anything called by or after reload create new registers + (actually, registers can't be created after flow, but this is a good + approximation). */ + + if (reload_in_progress || reload_completed) + abort (); + + /* Make sure regno_pointer_flag and regno_reg_rtx are large + enough to have an element for this pseudo reg number. */ + + if (reg_rtx_no == regno_pointer_flag_length) + { + rtx *new1; + char *new = + (char *) oballoc (regno_pointer_flag_length * 2); + bzero (new, regno_pointer_flag_length * 2); + bcopy (regno_pointer_flag, new, regno_pointer_flag_length); + regno_pointer_flag = new; + + new1 = (rtx *) oballoc (regno_pointer_flag_length * 2 * sizeof (rtx)); + bzero (new1, regno_pointer_flag_length * 2 * sizeof (rtx)); + bcopy (regno_reg_rtx, new1, regno_pointer_flag_length * sizeof (rtx)); + regno_reg_rtx = new1; + + regno_pointer_flag_length *= 2; + } + + val = gen_rtx (REG, mode, reg_rtx_no); + regno_reg_rtx[reg_rtx_no++] = val; + return val; +} + +/* Identify REG as a probable pointer register. */ + +void +mark_reg_pointer (reg) + rtx reg; +{ + REGNO_POINTER_FLAG (REGNO (reg)) = 1; +} + +/* Return 1 plus largest pseudo reg number used in the current function. */ + +int +max_reg_num () +{ + return reg_rtx_no; +} + +/* Return 1 + the largest label number used so far in the current function. */ + +int +max_label_num () +{ + if (last_label_num && label_num == base_label_num) + return last_label_num; + return label_num; +} + +/* Return first label number used in this function (if any were used). */ + +int +get_first_label_num () +{ + return first_label_num; +} + +/* Return a value representing some low-order bits of X, where the number + of low-order bits is given by MODE. Note that no conversion is done + between floating-point and fixed-point values, rather, the bit + representation is returned. + + This function handles the cases in common between gen_lowpart, below, + and two variants in cse.c and combine.c. These are the cases that can + be safely handled at all points in the compilation. + + If this is not a case we can handle, return 0. */ + +rtx +gen_lowpart_common (mode, x) + enum machine_mode mode; + register rtx x; +{ + int word = 0; + + if (GET_MODE (x) == mode) + return x; + + /* MODE must occupy no more words than the mode of X. */ + if (GET_MODE (x) != VOIDmode + && ((GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD + > ((GET_MODE_SIZE (GET_MODE (x)) + (UNITS_PER_WORD - 1)) + / UNITS_PER_WORD))) + return 0; + + if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) + word = ((GET_MODE_SIZE (GET_MODE (x)) + - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) + / UNITS_PER_WORD); + + if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) + && (GET_MODE_CLASS (mode) == MODE_INT + || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) + { + /* If we are getting the low-order part of something that has been + sign- or zero-extended, we can either just use the object being + extended or make a narrower extension. If we want an even smaller + piece than the size of the object being extended, call ourselves + recursively. + + This case is used mostly by combine and cse. */ + + if (GET_MODE (XEXP (x, 0)) == mode) + return XEXP (x, 0); + else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) + return gen_lowpart_common (mode, XEXP (x, 0)); + else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) + return gen_rtx (GET_CODE (x), mode, XEXP (x, 0)); + } + else if (GET_CODE (x) == SUBREG + && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD + || GET_MODE_SIZE (mode) == GET_MODE_UNIT_SIZE (GET_MODE (x)))) + return (GET_MODE (SUBREG_REG (x)) == mode && SUBREG_WORD (x) == 0 + ? SUBREG_REG (x) + : gen_rtx (SUBREG, mode, SUBREG_REG (x), SUBREG_WORD (x))); + else if (GET_CODE (x) == REG) + { + /* If the register is not valid for MODE, return 0. If we don't + do this, there is no way to fix up the resulting REG later. */ + if (REGNO (x) < FIRST_PSEUDO_REGISTER + && ! HARD_REGNO_MODE_OK (REGNO (x) + word, mode)) + return 0; + else if (REGNO (x) < FIRST_PSEUDO_REGISTER + /* integrate.c can't handle parts of a return value register. */ + && (! REG_FUNCTION_VALUE_P (x) + || ! rtx_equal_function_value_matters) + /* We want to keep the stack, frame, and arg pointers + special. */ + && REGNO (x) != FRAME_POINTER_REGNUM +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + && REGNO (x) != ARG_POINTER_REGNUM +#endif + && REGNO (x) != STACK_POINTER_REGNUM) + return gen_rtx (REG, mode, REGNO (x) + word); + else + return gen_rtx (SUBREG, mode, x, word); + } + + /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits + from the low-order part of the constant. */ + else if ((GET_MODE_CLASS (mode) == MODE_INT + || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) + && GET_MODE (x) == VOIDmode + && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) + { + /* If MODE is twice the host word size, X is already the desired + representation. Otherwise, if MODE is wider than a word, we can't + do this. If MODE is exactly a word, return just one CONST_INT. + If MODE is smaller than a word, clear the bits that don't belong + in our mode, unless they and our sign bit are all one. So we get + either a reasonable negative value or a reasonable unsigned value + for this mode. */ + + if (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT) + return x; + else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) + return 0; + else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT) + return (GET_CODE (x) == CONST_INT ? x + : GEN_INT (CONST_DOUBLE_LOW (x))); + else + { + /* MODE must be narrower than HOST_BITS_PER_INT. */ + int width = GET_MODE_BITSIZE (mode); + HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x) + : CONST_DOUBLE_LOW (x)); + + if (((val & ((HOST_WIDE_INT) (-1) << (width - 1))) + != ((HOST_WIDE_INT) (-1) << (width - 1)))) + val &= ((HOST_WIDE_INT) 1 << width) - 1; + + return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x + : GEN_INT (val)); + } + } + + /* If X is an integral constant but we want it in floating-point, it + must be the case that we have a union of an integer and a floating-point + value. If the machine-parameters allow it, simulate that union here + and return the result. The two-word and single-word cases are + different. */ + + else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) + || flag_pretend_float) + && GET_MODE_CLASS (mode) == MODE_FLOAT + && GET_MODE_SIZE (mode) == UNITS_PER_WORD + && GET_CODE (x) == CONST_INT + && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT) +#ifdef REAL_ARITHMETIC + { + REAL_VALUE_TYPE r; + HOST_WIDE_INT i; + + i = INTVAL (x); + r = REAL_VALUE_FROM_TARGET_SINGLE (i); + return immed_real_const_1 (r, mode); + } +#else + { + union {HOST_WIDE_INT i; float d; } u; + + u.i = INTVAL (x); + return immed_real_const_1 (u.d, mode); + } +#endif + else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) + || flag_pretend_float) + && GET_MODE_CLASS (mode) == MODE_FLOAT + && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD + && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) + && GET_MODE (x) == VOIDmode + && (sizeof (double) * HOST_BITS_PER_CHAR + == 2 * HOST_BITS_PER_WIDE_INT)) +#ifdef REAL_ARITHMETIC + { + REAL_VALUE_TYPE r; + HOST_WIDE_INT i[2]; + HOST_WIDE_INT low, high; + + if (GET_CODE (x) == CONST_INT) + low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); + else + low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); + +/* TARGET_DOUBLE takes the addressing order of the target machine. */ +#ifdef WORDS_BIG_ENDIAN + i[0] = high, i[1] = low; +#else + i[0] = low, i[1] = high; +#endif + + r = REAL_VALUE_FROM_TARGET_DOUBLE (i); + return immed_real_const_1 (r, mode); + } +#else + { + union {HOST_WIDE_INT i[2]; double d; } u; + HOST_WIDE_INT low, high; + + if (GET_CODE (x) == CONST_INT) + low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); + else + low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); + +#ifdef HOST_WORDS_BIG_ENDIAN + u.i[0] = high, u.i[1] = low; +#else + u.i[0] = low, u.i[1] = high; +#endif + + return immed_real_const_1 (u.d, mode); + } +#endif + /* Similarly, if this is converting a floating-point value into a + single-word integer. Only do this is the host and target parameters are + compatible. */ + + else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) + || flag_pretend_float) + && (GET_MODE_CLASS (mode) == MODE_INT + || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) + && GET_CODE (x) == CONST_DOUBLE + && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT + && GET_MODE_BITSIZE (mode) == BITS_PER_WORD) + return operand_subword (x, 0, 0, GET_MODE (x)); + + /* Similarly, if this is converting a floating-point value into a + two-word integer, we can do this one word at a time and make an + integer. Only do this is the host and target parameters are + compatible. */ + + else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) + || flag_pretend_float) + && (GET_MODE_CLASS (mode) == MODE_INT + || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) + && GET_CODE (x) == CONST_DOUBLE + && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT + && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD) + { + rtx lowpart = operand_subword (x, WORDS_BIG_ENDIAN, 0, GET_MODE (x)); + rtx highpart = operand_subword (x, ! WORDS_BIG_ENDIAN, 0, GET_MODE (x)); + + if (lowpart && GET_CODE (lowpart) == CONST_INT + && highpart && GET_CODE (highpart) == CONST_INT) + return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode); + } + + /* Otherwise, we can't do this. */ + return 0; +} + +/* Return the real part (which has mode MODE) of a complex value X. + This always comes at the low address in memory. */ + +rtx +gen_realpart (mode, x) + enum machine_mode mode; + register rtx x; +{ + if (WORDS_BIG_ENDIAN) + return gen_highpart (mode, x); + else + return gen_lowpart (mode, x); +} + +/* Return the imaginary part (which has mode MODE) of a complex value X. + This always comes at the high address in memory. */ + +rtx +gen_imagpart (mode, x) + enum machine_mode mode; + register rtx x; +{ + if (WORDS_BIG_ENDIAN) + return gen_lowpart (mode, x); + else + return gen_highpart (mode, x); +} + +/* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value, + return an rtx (MEM, SUBREG, or CONST_INT) that refers to the + least-significant part of X. + MODE specifies how big a part of X to return; + it usually should not be larger than a word. + If X is a MEM whose address is a QUEUED, the value may be so also. */ + +rtx +gen_lowpart (mode, x) + enum machine_mode mode; + register rtx x; +{ + rtx result = gen_lowpart_common (mode, x); + + if (result) + return result; + else if (GET_CODE (x) == MEM) + { + /* The only additional case we can do is MEM. */ + register int offset = 0; + if (WORDS_BIG_ENDIAN) + offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) + - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); + + if (BYTES_BIG_ENDIAN) + /* Adjust the address so that the address-after-the-data + is unchanged. */ + offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) + - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); + + return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); + } + else + abort (); +} + +/* Like `gen_lowpart', but refer to the most significant part. + This is used to access the imaginary part of a complex number. */ + +rtx +gen_highpart (mode, x) + enum machine_mode mode; + register rtx x; +{ + /* This case loses if X is a subreg. To catch bugs early, + complain if an invalid MODE is used even in other cases. */ + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD + && GET_MODE_SIZE (mode) != GET_MODE_UNIT_SIZE (GET_MODE (x))) + abort (); + if (GET_CODE (x) == CONST_DOUBLE +#if !(TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT || defined (REAL_IS_NOT_DOUBLE)) + && GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT +#endif + ) + return gen_rtx (CONST_INT, VOIDmode, + CONST_DOUBLE_HIGH (x) & GET_MODE_MASK (mode)); + else if (GET_CODE (x) == CONST_INT) + return const0_rtx; + else if (GET_CODE (x) == MEM) + { + register int offset = 0; +#if !WORDS_BIG_ENDIAN + offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) + - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); +#endif +#if !BYTES_BIG_ENDIAN + if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) + offset -= (GET_MODE_SIZE (mode) + - MIN (UNITS_PER_WORD, + GET_MODE_SIZE (GET_MODE (x)))); +#endif + return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); + } + else if (GET_CODE (x) == SUBREG) + { + /* The only time this should occur is when we are looking at a + multi-word item with a SUBREG whose mode is the same as that of the + item. It isn't clear what we would do if it wasn't. */ + if (SUBREG_WORD (x) != 0) + abort (); + return gen_highpart (mode, SUBREG_REG (x)); + } + else if (GET_CODE (x) == REG) + { + int word = 0; + +#if !WORDS_BIG_ENDIAN + if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) + word = ((GET_MODE_SIZE (GET_MODE (x)) + - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) + / UNITS_PER_WORD); +#endif + if (REGNO (x) < FIRST_PSEUDO_REGISTER + /* We want to keep the stack, frame, and arg pointers special. */ + && REGNO (x) != FRAME_POINTER_REGNUM +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + && REGNO (x) != ARG_POINTER_REGNUM +#endif + && REGNO (x) != STACK_POINTER_REGNUM) + return gen_rtx (REG, mode, REGNO (x) + word); + else + return gen_rtx (SUBREG, mode, x, word); + } + else + abort (); +} + +/* Return 1 iff X, assumed to be a SUBREG, + refers to the least significant part of its containing reg. + If X is not a SUBREG, always return 1 (it is its own low part!). */ + +int +subreg_lowpart_p (x) + rtx x; +{ + if (GET_CODE (x) != SUBREG) + return 1; + + if (WORDS_BIG_ENDIAN + && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD) + return (SUBREG_WORD (x) + == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) + - MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)) + / UNITS_PER_WORD)); + + return SUBREG_WORD (x) == 0; +} + +/* Return subword I of operand OP. + The word number, I, is interpreted as the word number starting at the + low-order address. Word 0 is the low-order word if not WORDS_BIG_ENDIAN, + otherwise it is the high-order word. + + If we cannot extract the required word, we return zero. Otherwise, an + rtx corresponding to the requested word will be returned. + + VALIDATE_ADDRESS is nonzero if the address should be validated. Before + reload has completed, a valid address will always be returned. After + reload, if a valid address cannot be returned, we return zero. + + If VALIDATE_ADDRESS is zero, we simply form the required address; validating + it is the responsibility of the caller. + + MODE is the mode of OP in case it is a CONST_INT. */ + +rtx +operand_subword (op, i, validate_address, mode) + rtx op; + int i; + int validate_address; + enum machine_mode mode; +{ + HOST_WIDE_INT val; + int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; + + if (mode == VOIDmode) + mode = GET_MODE (op); + + if (mode == VOIDmode) + abort (); + + /* If OP is narrower than a word or if we want a word outside OP, fail. */ + if (mode != BLKmode + && (GET_MODE_SIZE (mode) < UNITS_PER_WORD + || (i + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode))) + return 0; + + /* If OP is already an integer word, return it. */ + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_SIZE (mode) == UNITS_PER_WORD) + return op; + + /* If OP is a REG or SUBREG, we can handle it very simply. */ + if (GET_CODE (op) == REG) + { + /* If the register is not valid for MODE, return 0. If we don't + do this, there is no way to fix up the resulting REG later. */ + if (REGNO (op) < FIRST_PSEUDO_REGISTER + && ! HARD_REGNO_MODE_OK (REGNO (op) + i, word_mode)) + return 0; + else if (REGNO (op) >= FIRST_PSEUDO_REGISTER + || (REG_FUNCTION_VALUE_P (op) + && rtx_equal_function_value_matters) + /* We want to keep the stack, frame, and arg pointers + special. */ + || REGNO (op) == FRAME_POINTER_REGNUM +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + || REGNO (op) == ARG_POINTER_REGNUM +#endif + || REGNO (op) == STACK_POINTER_REGNUM) + return gen_rtx (SUBREG, word_mode, op, i); + else + return gen_rtx (REG, word_mode, REGNO (op) + i); + } + else if (GET_CODE (op) == SUBREG) + return gen_rtx (SUBREG, word_mode, SUBREG_REG (op), i + SUBREG_WORD (op)); + + /* Form a new MEM at the requested address. */ + if (GET_CODE (op) == MEM) + { + rtx addr = plus_constant (XEXP (op, 0), i * UNITS_PER_WORD); + rtx new; + + if (validate_address) + { + if (reload_completed) + { + if (! strict_memory_address_p (word_mode, addr)) + return 0; + } + else + addr = memory_address (word_mode, addr); + } + + new = gen_rtx (MEM, word_mode, addr); + + MEM_VOLATILE_P (new) = MEM_VOLATILE_P (op); + MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (op); + RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); + + return new; + } + + /* The only remaining cases are when OP is a constant. If the host and + target floating formats are the same, handling two-word floating + constants are easy. Note that REAL_VALUE_TO_TARGET_{SINGLE,DOUBLE} + are defined as returning 32 bit and 64-bit values, respectively, + and not values of BITS_PER_WORD and 2 * BITS_PER_WORD bits. */ +#ifdef REAL_ARITHMETIC + if ((HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) + && GET_MODE_CLASS (mode) == MODE_FLOAT + && GET_MODE_BITSIZE (mode) == 64 + && GET_CODE (op) == CONST_DOUBLE) + { + HOST_WIDE_INT k[2]; + REAL_VALUE_TYPE rv; + + REAL_VALUE_FROM_CONST_DOUBLE (rv, op); + REAL_VALUE_TO_TARGET_DOUBLE (rv, k); + + /* We handle 32-bit and 64-bit host words here. Note that the order in + which the words are written depends on the word endianness. + + ??? This is a potential portability problem and should + be fixed at some point. */ + if (HOST_BITS_PER_WIDE_INT == 32) + return GEN_INT (k[i]); + else if (HOST_BITS_PER_WIDE_INT == 64 && i == 0) + return GEN_INT ((k[! WORDS_BIG_ENDIAN] << (HOST_BITS_PER_WIDE_INT / 2)) + | k[WORDS_BIG_ENDIAN]); + else + abort (); + } +#else /* no REAL_ARITHMETIC */ + if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) + || flag_pretend_float) + && GET_MODE_CLASS (mode) == MODE_FLOAT + && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD + && GET_CODE (op) == CONST_DOUBLE) + { + /* The constant is stored in the host's word-ordering, + but we want to access it in the target's word-ordering. Some + compilers don't like a conditional inside macro args, so we have two + copies of the return. */ +#ifdef HOST_WORDS_BIG_ENDIAN + return GEN_INT (i == WORDS_BIG_ENDIAN + ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); +#else + return GEN_INT (i != WORDS_BIG_ENDIAN + ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); +#endif + } +#endif /* no REAL_ARITHMETIC */ + + /* Single word float is a little harder, since single- and double-word + values often do not have the same high-order bits. We have already + verified that we want the only defined word of the single-word value. */ +#ifdef REAL_ARITHMETIC + if ((HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) + && GET_MODE_CLASS (mode) == MODE_FLOAT + && GET_MODE_BITSIZE (mode) == 32 + && GET_CODE (op) == CONST_DOUBLE) + { + HOST_WIDE_INT l; + REAL_VALUE_TYPE rv; + + REAL_VALUE_FROM_CONST_DOUBLE (rv, op); + REAL_VALUE_TO_TARGET_SINGLE (rv, l); + return GEN_INT (l); + } +#else + if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) + || flag_pretend_float) + && GET_MODE_CLASS (mode) == MODE_FLOAT + && GET_MODE_SIZE (mode) == UNITS_PER_WORD + && GET_CODE (op) == CONST_DOUBLE) + { + double d; + union {float f; HOST_WIDE_INT i; } u; + + REAL_VALUE_FROM_CONST_DOUBLE (d, op); + + u.f = d; + return GEN_INT (u.i); + } +#endif /* no REAL_ARITHMETIC */ + + /* The only remaining cases that we can handle are integers. + Convert to proper endianness now since these cases need it. + At this point, i == 0 means the low-order word. + + We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT + in general. However, if OP is (const_int 0), we can just return + it for any word. */ + + if (op == const0_rtx) + return op; + + if (GET_MODE_CLASS (mode) != MODE_INT + || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE) + || BITS_PER_WORD > HOST_BITS_PER_INT) + return 0; + + if (WORDS_BIG_ENDIAN) + i = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - i; + + /* Find out which word on the host machine this value is in and get + it from the constant. */ + val = (i / size_ratio == 0 + ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op)) + : (GET_CODE (op) == CONST_INT + ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op))); + + /* If BITS_PER_WORD is smaller than an int, get the appropriate bits. */ + if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT) + val = ((val >> ((i % size_ratio) * BITS_PER_WORD)) + & (((HOST_WIDE_INT) 1 + << (BITS_PER_WORD % HOST_BITS_PER_WIDE_INT)) - 1)); + + return GEN_INT (val); +} + +/* Similar to `operand_subword', but never return 0. If we can't extract + the required subword, put OP into a register and try again. If that fails, + abort. We always validate the address in this case. It is not valid + to call this function after reload; it is mostly meant for RTL + generation. + + MODE is the mode of OP, in case it is CONST_INT. */ + +rtx +operand_subword_force (op, i, mode) + rtx op; + int i; + enum machine_mode mode; +{ + rtx result = operand_subword (op, i, 1, mode); + + if (result) + return result; + + if (mode != BLKmode && mode != VOIDmode) + op = force_reg (mode, op); + + result = operand_subword (op, i, 1, mode); + if (result == 0) + abort (); + + return result; +} + +/* Given a compare instruction, swap the operands. + A test instruction is changed into a compare of 0 against the operand. */ + +void +reverse_comparison (insn) + rtx insn; +{ + rtx body = PATTERN (insn); + rtx comp; + + if (GET_CODE (body) == SET) + comp = SET_SRC (body); + else + comp = SET_SRC (XVECEXP (body, 0, 0)); + + if (GET_CODE (comp) == COMPARE) + { + rtx op0 = XEXP (comp, 0); + rtx op1 = XEXP (comp, 1); + XEXP (comp, 0) = op1; + XEXP (comp, 1) = op0; + } + else + { + rtx new = gen_rtx (COMPARE, VOIDmode, + CONST0_RTX (GET_MODE (comp)), comp); + if (GET_CODE (body) == SET) + SET_SRC (body) = new; + else + SET_SRC (XVECEXP (body, 0, 0)) = new; + } +} + +/* Return a memory reference like MEMREF, but with its mode changed + to MODE and its address changed to ADDR. + (VOIDmode means don't change the mode. + NULL for ADDR means don't change the address.) */ + +rtx +change_address (memref, mode, addr) + rtx memref; + enum machine_mode mode; + rtx addr; +{ + rtx new; + + if (GET_CODE (memref) != MEM) + abort (); + if (mode == VOIDmode) + mode = GET_MODE (memref); + if (addr == 0) + addr = XEXP (memref, 0); + + /* If reload is in progress or has completed, ADDR must be valid. + Otherwise, we can call memory_address to make it valid. */ + if (reload_completed || reload_in_progress) + { + if (! memory_address_p (mode, addr)) + abort (); + } + else + addr = memory_address (mode, addr); + + new = gen_rtx (MEM, mode, addr); + MEM_VOLATILE_P (new) = MEM_VOLATILE_P (memref); + RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (memref); + MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (memref); + return new; +} + +/* Return a newly created CODE_LABEL rtx with a unique label number. */ + +rtx +gen_label_rtx () +{ + register rtx label = gen_rtx (CODE_LABEL, VOIDmode, 0, 0, 0, + label_num++, NULL_PTR); + LABEL_NUSES (label) = 0; + return label; +} + +/* For procedure integration. */ + +/* Return a newly created INLINE_HEADER rtx. Should allocate this + from a permanent obstack when the opportunity arises. */ + +rtx +gen_inline_header_rtx (first_insn, first_parm_insn, first_labelno, + last_labelno, max_parm_regnum, max_regnum, args_size, + pops_args, stack_slots, function_flags, + outgoing_args_size, original_arg_vector, + original_decl_initial) + rtx first_insn, first_parm_insn; + int first_labelno, last_labelno, max_parm_regnum, max_regnum, args_size; + int pops_args; + rtx stack_slots; + int function_flags; + int outgoing_args_size; + rtvec original_arg_vector; + rtx original_decl_initial; +{ + rtx header = gen_rtx (INLINE_HEADER, VOIDmode, + cur_insn_uid++, NULL_RTX, + first_insn, first_parm_insn, + first_labelno, last_labelno, + max_parm_regnum, max_regnum, args_size, pops_args, + stack_slots, function_flags, outgoing_args_size, + original_arg_vector, original_decl_initial); + return header; +} + +/* Install new pointers to the first and last insns in the chain. + Used for an inline-procedure after copying the insn chain. */ + +void +set_new_first_and_last_insn (first, last) + rtx first, last; +{ + first_insn = first; + last_insn = last; +} + +/* Set the range of label numbers found in the current function. + This is used when belatedly compiling an inline function. */ + +void +set_new_first_and_last_label_num (first, last) + int first, last; +{ + base_label_num = label_num; + first_label_num = first; + last_label_num = last; +} + +/* Save all variables describing the current status into the structure *P. + This is used before starting a nested function. */ + +void +save_emit_status (p) + struct function *p; +{ + p->reg_rtx_no = reg_rtx_no; + p->first_label_num = first_label_num; + p->first_insn = first_insn; + p->last_insn = last_insn; + p->sequence_stack = sequence_stack; + p->cur_insn_uid = cur_insn_uid; + p->last_linenum = last_linenum; + p->last_filename = last_filename; + p->regno_pointer_flag = regno_pointer_flag; + p->regno_pointer_flag_length = regno_pointer_flag_length; + p->regno_reg_rtx = regno_reg_rtx; +} + +/* Restore all variables describing the current status from the structure *P. + This is used after a nested function. */ + +void +restore_emit_status (p) + struct function *p; +{ + int i; + + reg_rtx_no = p->reg_rtx_no; + first_label_num = p->first_label_num; + first_insn = p->first_insn; + last_insn = p->last_insn; + sequence_stack = p->sequence_stack; + cur_insn_uid = p->cur_insn_uid; + last_linenum = p->last_linenum; + last_filename = p->last_filename; + regno_pointer_flag = p->regno_pointer_flag; + regno_pointer_flag_length = p->regno_pointer_flag_length; + regno_reg_rtx = p->regno_reg_rtx; + + /* Clear our cache of rtx expressions for start_sequence and gen_sequence. */ + sequence_element_free_list = 0; + for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) + sequence_result[i] = 0; +} + +/* Go through all the RTL insn bodies and copy any invalid shared structure. + It does not work to do this twice, because the mark bits set here + are not cleared afterwards. */ + +void +unshare_all_rtl (insn) + register rtx insn; +{ + for (; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN + || GET_CODE (insn) == CALL_INSN) + { + PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); + REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); + LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn)); + } + + /* Make sure the addresses of stack slots found outside the insn chain + (such as, in DECL_RTL of a variable) are not shared + with the insn chain. + + This special care is necessary when the stack slot MEM does not + actually appear in the insn chain. If it does appear, its address + is unshared from all else at that point. */ + + copy_rtx_if_shared (stack_slot_list); +} + +/* Mark ORIG as in use, and return a copy of it if it was already in use. + Recursively does the same for subexpressions. */ + +rtx +copy_rtx_if_shared (orig) + rtx orig; +{ + register rtx x = orig; + register int i; + register enum rtx_code code; + register char *format_ptr; + int copied = 0; + + if (x == 0) + return 0; + + code = GET_CODE (x); + + /* These types may be freely shared. */ + + switch (code) + { + case REG: + case QUEUED: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CODE_LABEL: + case PC: + case CC0: + case SCRATCH: + /* SCRATCH must be shared because they represent distinct values. */ + return x; + + case CONST: + /* CONST can be shared if it contains a SYMBOL_REF. If it contains + a LABEL_REF, it isn't sharable. */ + if (GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) + return x; + break; + + case INSN: + case JUMP_INSN: + case CALL_INSN: + case NOTE: + case LABEL_REF: + case BARRIER: + /* The chain of insns is not being copied. */ + return x; + + case MEM: + /* A MEM is allowed to be shared if its address is constant + or is a constant plus one of the special registers. */ + if (CONSTANT_ADDRESS_P (XEXP (x, 0)) + || XEXP (x, 0) == virtual_stack_vars_rtx + || XEXP (x, 0) == virtual_incoming_args_rtx) + return x; + + if (GET_CODE (XEXP (x, 0)) == PLUS + && (XEXP (XEXP (x, 0), 0) == virtual_stack_vars_rtx + || XEXP (XEXP (x, 0), 0) == virtual_incoming_args_rtx) + && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) + { + /* This MEM can appear in more than one place, + but its address better not be shared with anything else. */ + if (! x->used) + XEXP (x, 0) = copy_rtx_if_shared (XEXP (x, 0)); + x->used = 1; + return x; + } + } + + /* This rtx may not be shared. If it has already been seen, + replace it with a copy of itself. */ + + if (x->used) + { + register rtx copy; + + copy = rtx_alloc (code); + bcopy (x, copy, (sizeof (*copy) - sizeof (copy->fld) + + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code))); + x = copy; + copied = 1; + } + x->used = 1; + + /* Now scan the subexpressions recursively. + We can store any replaced subexpressions directly into X + since we know X is not shared! Any vectors in X + must be copied if X was copied. */ + + format_ptr = GET_RTX_FORMAT (code); + + for (i = 0; i < GET_RTX_LENGTH (code); i++) + { + switch (*format_ptr++) + { + case 'e': + XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i)); + break; + + case 'E': + if (XVEC (x, i) != NULL) + { + register int j; + + if (copied) + XVEC (x, i) = gen_rtvec_v (XVECLEN (x, i), &XVECEXP (x, i, 0)); + for (j = 0; j < XVECLEN (x, i); j++) + XVECEXP (x, i, j) + = copy_rtx_if_shared (XVECEXP (x, i, j)); + } + break; + } + } + return x; +} + +/* Clear all the USED bits in X to allow copy_rtx_if_shared to be used + to look for shared sub-parts. */ + +void +reset_used_flags (x) + rtx x; +{ + register int i, j; + register enum rtx_code code; + register char *format_ptr; + int copied = 0; + + if (x == 0) + return; + + code = GET_CODE (x); + + /* These types may be freely shared so we needn't do any reseting + for them. */ + + switch (code) + { + case REG: + case QUEUED: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CODE_LABEL: + case PC: + case CC0: + return; + + case INSN: + case JUMP_INSN: + case CALL_INSN: + case NOTE: + case LABEL_REF: + case BARRIER: + /* The chain of insns is not being copied. */ + return; + } + + x->used = 0; + + format_ptr = GET_RTX_FORMAT (code); + for (i = 0; i < GET_RTX_LENGTH (code); i++) + { + switch (*format_ptr++) + { + case 'e': + reset_used_flags (XEXP (x, i)); + break; + + case 'E': + for (j = 0; j < XVECLEN (x, i); j++) + reset_used_flags (XVECEXP (x, i, j)); + break; + } + } +} + +/* Copy X if necessary so that it won't be altered by changes in OTHER. + Return X or the rtx for the pseudo reg the value of X was copied into. + OTHER must be valid as a SET_DEST. */ + +rtx +make_safe_from (x, other) + rtx x, other; +{ + while (1) + switch (GET_CODE (other)) + { + case SUBREG: + other = SUBREG_REG (other); + break; + case STRICT_LOW_PART: + case SIGN_EXTEND: + case ZERO_EXTEND: + other = XEXP (other, 0); + break; + default: + goto done; + } + done: + if ((GET_CODE (other) == MEM + && ! CONSTANT_P (x) + && GET_CODE (x) != REG + && GET_CODE (x) != SUBREG) + || (GET_CODE (other) == REG + && (REGNO (other) < FIRST_PSEUDO_REGISTER + || reg_mentioned_p (other, x)))) + { + rtx temp = gen_reg_rtx (GET_MODE (x)); + emit_move_insn (temp, x); + return temp; + } + return x; +} + +/* Emission of insns (adding them to the doubly-linked list). */ + +/* Return the first insn of the current sequence or current function. */ + +rtx +get_insns () +{ + return first_insn; +} + +/* Return the last insn emitted in current sequence or current function. */ + +rtx +get_last_insn () +{ + return last_insn; +} + +/* Specify a new insn as the last in the chain. */ + +void +set_last_insn (insn) + rtx insn; +{ + if (NEXT_INSN (insn) != 0) + abort (); + last_insn = insn; +} + +/* Return the last insn emitted, even if it is in a sequence now pushed. */ + +rtx +get_last_insn_anywhere () +{ + struct sequence_stack *stack; + if (last_insn) + return last_insn; + for (stack = sequence_stack; stack; stack = stack->next) + if (stack->last != 0) + return stack->last; + return 0; +} + +/* Return a number larger than any instruction's uid in this function. */ + +int +get_max_uid () +{ + return cur_insn_uid; +} + +/* Return the next insn. If it is a SEQUENCE, return the first insn + of the sequence. */ + +rtx +next_insn (insn) + rtx insn; +{ + if (insn) + { + insn = NEXT_INSN (insn); + if (insn && GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == SEQUENCE) + insn = XVECEXP (PATTERN (insn), 0, 0); + } + + return insn; +} + +/* Return the previous insn. If it is a SEQUENCE, return the last insn + of the sequence. */ + +rtx +previous_insn (insn) + rtx insn; +{ + if (insn) + { + insn = PREV_INSN (insn); + if (insn && GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == SEQUENCE) + insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); + } + + return insn; +} + +/* Return the next insn after INSN that is not a NOTE. This routine does not + look inside SEQUENCEs. */ + +rtx +next_nonnote_insn (insn) + rtx insn; +{ + while (insn) + { + insn = NEXT_INSN (insn); + if (insn == 0 || GET_CODE (insn) != NOTE) + break; + } + + return insn; +} + +/* Return the previous insn before INSN that is not a NOTE. This routine does + not look inside SEQUENCEs. */ + +rtx +prev_nonnote_insn (insn) + rtx insn; +{ + while (insn) + { + insn = PREV_INSN (insn); + if (insn == 0 || GET_CODE (insn) != NOTE) + break; + } + + return insn; +} + +/* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; + or 0, if there is none. This routine does not look inside + SEQUENCEs. */ + +rtx +next_real_insn (insn) + rtx insn; +{ + while (insn) + { + insn = NEXT_INSN (insn); + if (insn == 0 || GET_CODE (insn) == INSN + || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) + break; + } + + return insn; +} + +/* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; + or 0, if there is none. This routine does not look inside + SEQUENCEs. */ + +rtx +prev_real_insn (insn) + rtx insn; +{ + while (insn) + { + insn = PREV_INSN (insn); + if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN + || GET_CODE (insn) == JUMP_INSN) + break; + } + + return insn; +} + +/* Find the next insn after INSN that really does something. This routine + does not look inside SEQUENCEs. Until reload has completed, this is the + same as next_real_insn. */ + +rtx +next_active_insn (insn) + rtx insn; +{ + while (insn) + { + insn = NEXT_INSN (insn); + if (insn == 0 + || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN + || (GET_CODE (insn) == INSN + && (! reload_completed + || (GET_CODE (PATTERN (insn)) != USE + && GET_CODE (PATTERN (insn)) != CLOBBER)))) + break; + } + + return insn; +} + +/* Find the last insn before INSN that really does something. This routine + does not look inside SEQUENCEs. Until reload has completed, this is the + same as prev_real_insn. */ + +rtx +prev_active_insn (insn) + rtx insn; +{ + while (insn) + { + insn = PREV_INSN (insn); + if (insn == 0 + || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN + || (GET_CODE (insn) == INSN + && (! reload_completed + || (GET_CODE (PATTERN (insn)) != USE + && GET_CODE (PATTERN (insn)) != CLOBBER)))) + break; + } + + return insn; +} + +/* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ + +rtx +next_label (insn) + rtx insn; +{ + while (insn) + { + insn = NEXT_INSN (insn); + if (insn == 0 || GET_CODE (insn) == CODE_LABEL) + break; + } + + return insn; +} + +/* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ + +rtx +prev_label (insn) + rtx insn; +{ + while (insn) + { + insn = PREV_INSN (insn); + if (insn == 0 || GET_CODE (insn) == CODE_LABEL) + break; + } + + return insn; +} + +#ifdef HAVE_cc0 +/* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER + and REG_CC_USER notes so we can find it. */ + +void +link_cc0_insns (insn) + rtx insn; +{ + rtx user = next_nonnote_insn (insn); + + if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE) + user = XVECEXP (PATTERN (user), 0, 0); + + REG_NOTES (user) = gen_rtx (INSN_LIST, REG_CC_SETTER, insn, + REG_NOTES (user)); + REG_NOTES (insn) = gen_rtx (INSN_LIST, REG_CC_USER, user, REG_NOTES (insn)); +} + +/* Return the next insn that uses CC0 after INSN, which is assumed to + set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter + applied to the result of this function should yield INSN). + + Normally, this is simply the next insn. However, if a REG_CC_USER note + is present, it contains the insn that uses CC0. + + Return 0 if we can't find the insn. */ + +rtx +next_cc0_user (insn) + rtx insn; +{ + rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); + + if (note) + return XEXP (note, 0); + + insn = next_nonnote_insn (insn); + if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) + insn = XVECEXP (PATTERN (insn), 0, 0); + + if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_mentioned_p (cc0_rtx, PATTERN (insn))) + return insn; + + return 0; +} + +/* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER + note, it is the previous insn. */ + +rtx +prev_cc0_setter (insn) + rtx insn; +{ + rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); + rtx link; + + if (note) + return XEXP (note, 0); + + insn = prev_nonnote_insn (insn); + if (! sets_cc0_p (PATTERN (insn))) + abort (); + + return insn; +} +#endif + +/* Try splitting insns that can be split for better scheduling. + PAT is the pattern which might split. + TRIAL is the insn providing PAT. + BACKWARDS is non-zero if we are scanning insns from last to first. + + If this routine succeeds in splitting, it returns the first or last + replacement insn depending on the value of BACKWARDS. Otherwise, it + returns TRIAL. If the insn to be returned can be split, it will be. */ + +rtx +try_split (pat, trial, backwards) + rtx pat, trial; + int backwards; +{ + rtx before = PREV_INSN (trial); + rtx after = NEXT_INSN (trial); + rtx seq = split_insns (pat, trial); + int has_barrier = 0; + rtx tem; + + /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. + We may need to handle this specially. */ + if (after && GET_CODE (after) == BARRIER) + { + has_barrier = 1; + after = NEXT_INSN (after); + } + + if (seq) + { + /* SEQ can either be a SEQUENCE or the pattern of a single insn. + The latter case will normally arise only when being done so that + it, in turn, will be split (SFmode on the 29k is an example). */ + if (GET_CODE (seq) == SEQUENCE) + { + /* If we are splitting a JUMP_INSN, look for the JUMP_INSN in + SEQ and copy our JUMP_LABEL to it. If JUMP_LABEL is non-zero, + increment the usage count so we don't delete the label. */ + int i; + + if (GET_CODE (trial) == JUMP_INSN) + for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) + if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN) + { + JUMP_LABEL (XVECEXP (seq, 0, i)) = JUMP_LABEL (trial); + + if (JUMP_LABEL (trial)) + LABEL_NUSES (JUMP_LABEL (trial))++; + } + + tem = emit_insn_after (seq, before); + + delete_insn (trial); + if (has_barrier) + emit_barrier_after (tem); + } + /* Avoid infinite loop if the result matches the original pattern. */ + else if (rtx_equal_p (seq, pat)) + return trial; + else + { + PATTERN (trial) = seq; + INSN_CODE (trial) = -1; + } + + /* Set TEM to the insn we should return. */ + tem = backwards ? prev_active_insn (after) : next_active_insn (before); + return try_split (PATTERN (tem), tem, backwards); + } + + return trial; +} + +/* Make and return an INSN rtx, initializing all its slots. + Store PATTERN in the pattern slots. */ + +rtx +make_insn_raw (pattern) + rtx pattern; +{ + register rtx insn; + + insn = rtx_alloc (INSN); + INSN_UID (insn) = cur_insn_uid++; + + PATTERN (insn) = pattern; + INSN_CODE (insn) = -1; + LOG_LINKS (insn) = NULL; + REG_NOTES (insn) = NULL; + + return insn; +} + +/* Like `make_insn' but make a JUMP_INSN instead of an insn. */ + +static rtx +make_jump_insn_raw (pattern) + rtx pattern; +{ + register rtx insn; + + insn = rtx_alloc (JUMP_INSN); + INSN_UID (insn) = cur_insn_uid++; + + PATTERN (insn) = pattern; + INSN_CODE (insn) = -1; + LOG_LINKS (insn) = NULL; + REG_NOTES (insn) = NULL; + JUMP_LABEL (insn) = NULL; + + return insn; +} + +/* Add INSN to the end of the doubly-linked list. + INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ + +void +add_insn (insn) + register rtx insn; +{ + PREV_INSN (insn) = last_insn; + NEXT_INSN (insn) = 0; + + if (NULL != last_insn) + NEXT_INSN (last_insn) = insn; + + if (NULL == first_insn) + first_insn = insn; + + last_insn = insn; +} + +/* Add INSN into the doubly-linked list after insn AFTER. This should be the + only function called to insert an insn once delay slots have been filled + since only it knows how to update a SEQUENCE. */ + +void +add_insn_after (insn, after) + rtx insn, after; +{ + rtx next = NEXT_INSN (after); + + NEXT_INSN (insn) = next; + PREV_INSN (insn) = after; + + if (next) + { + PREV_INSN (next) = insn; + if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) + PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; + } + else if (last_insn == after) + last_insn = insn; + else + { + struct sequence_stack *stack = sequence_stack; + /* Scan all pending sequences too. */ + for (; stack; stack = stack->next) + if (after == stack->last) + stack->last = insn; + } + + NEXT_INSN (after) = insn; + if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE) + { + rtx sequence = PATTERN (after); + NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; + } +} + +/* Delete all insns made since FROM. + FROM becomes the new last instruction. */ + +void +delete_insns_since (from) + rtx from; +{ + if (from == 0) + first_insn = 0; + else + NEXT_INSN (from) = 0; + last_insn = from; +} + +/* Move a consecutive bunch of insns to a different place in the chain. + The insns to be moved are those between FROM and TO. + They are moved to a new position after the insn AFTER. + AFTER must not be FROM or TO or any insn in between. + + This function does not know about SEQUENCEs and hence should not be + called after delay-slot filling has been done. */ + +void +reorder_insns (from, to, after) + rtx from, to, after; +{ + /* Splice this bunch out of where it is now. */ + if (PREV_INSN (from)) + NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); + if (NEXT_INSN (to)) + PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); + if (last_insn == to) + last_insn = PREV_INSN (from); + if (first_insn == from) + first_insn = NEXT_INSN (to); + + /* Make the new neighbors point to it and it to them. */ + if (NEXT_INSN (after)) + PREV_INSN (NEXT_INSN (after)) = to; + + NEXT_INSN (to) = NEXT_INSN (after); + PREV_INSN (from) = after; + NEXT_INSN (after) = from; + if (after == last_insn) + last_insn = to; +} + +/* Return the line note insn preceding INSN. */ + +static rtx +find_line_note (insn) + rtx insn; +{ + if (no_line_numbers) + return 0; + + for (; insn; insn = PREV_INSN (insn)) + if (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) >= 0) + break; + + return insn; +} + +/* Like reorder_insns, but inserts line notes to preserve the line numbers + of the moved insns when debugging. This may insert a note between AFTER + and FROM, and another one after TO. */ + +void +reorder_insns_with_line_notes (from, to, after) + rtx from, to, after; +{ + rtx from_line = find_line_note (from); + rtx after_line = find_line_note (after); + + reorder_insns (from, to, after); + + if (from_line == after_line) + return; + + if (from_line) + emit_line_note_after (NOTE_SOURCE_FILE (from_line), + NOTE_LINE_NUMBER (from_line), + after); + if (after_line) + emit_line_note_after (NOTE_SOURCE_FILE (after_line), + NOTE_LINE_NUMBER (after_line), + to); +} + +/* Emit an insn of given code and pattern + at a specified place within the doubly-linked list. */ + +/* Make an instruction with body PATTERN + and output it before the instruction BEFORE. */ + +rtx +emit_insn_before (pattern, before) + register rtx pattern, before; +{ + register rtx insn = before; + + if (GET_CODE (pattern) == SEQUENCE) + { + register int i; + + for (i = 0; i < XVECLEN (pattern, 0); i++) + { + insn = XVECEXP (pattern, 0, i); + add_insn_after (insn, PREV_INSN (before)); + } + if (XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) + sequence_result[XVECLEN (pattern, 0)] = pattern; + } + else + { + insn = make_insn_raw (pattern); + add_insn_after (insn, PREV_INSN (before)); + } + + return insn; +} + +/* Make an instruction with body PATTERN and code JUMP_INSN + and output it before the instruction BEFORE. */ + +rtx +emit_jump_insn_before (pattern, before) + register rtx pattern, before; +{ + register rtx insn; + + if (GET_CODE (pattern) == SEQUENCE) + insn = emit_insn_before (pattern, before); + else + { + insn = make_jump_insn_raw (pattern); + add_insn_after (insn, PREV_INSN (before)); + } + + return insn; +} + +/* Make an instruction with body PATTERN and code CALL_INSN + and output it before the instruction BEFORE. */ + +rtx +emit_call_insn_before (pattern, before) + register rtx pattern, before; +{ + rtx insn = emit_insn_before (pattern, before); + PUT_CODE (insn, CALL_INSN); + return insn; +} + +/* Make an insn of code BARRIER + and output it before the insn AFTER. */ + +rtx +emit_barrier_before (before) + register rtx before; +{ + register rtx insn = rtx_alloc (BARRIER); + + INSN_UID (insn) = cur_insn_uid++; + + add_insn_after (insn, PREV_INSN (before)); + return insn; +} + +/* Emit a note of subtype SUBTYPE before the insn BEFORE. */ + +rtx +emit_note_before (subtype, before) + int subtype; + rtx before; +{ + register rtx note = rtx_alloc (NOTE); + INSN_UID (note) = cur_insn_uid++; + NOTE_SOURCE_FILE (note) = 0; + NOTE_LINE_NUMBER (note) = subtype; + + add_insn_after (note, PREV_INSN (before)); + return note; +} + +/* Make an insn of code INSN with body PATTERN + and output it after the insn AFTER. */ + +rtx +emit_insn_after (pattern, after) + register rtx pattern, after; +{ + register rtx insn = after; + + if (GET_CODE (pattern) == SEQUENCE) + { + register int i; + + for (i = 0; i < XVECLEN (pattern, 0); i++) + { + insn = XVECEXP (pattern, 0, i); + add_insn_after (insn, after); + after = insn; + } + if (XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) + sequence_result[XVECLEN (pattern, 0)] = pattern; + } + else + { + insn = make_insn_raw (pattern); + add_insn_after (insn, after); + } + + return insn; +} + +/* Similar to emit_insn_after, except that line notes are to be inserted so + as to act as if this insn were at FROM. */ + +void +emit_insn_after_with_line_notes (pattern, after, from) + rtx pattern, after, from; +{ + rtx from_line = find_line_note (from); + rtx after_line = find_line_note (after); + rtx insn = emit_insn_after (pattern, after); + + if (from_line) + emit_line_note_after (NOTE_SOURCE_FILE (from_line), + NOTE_LINE_NUMBER (from_line), + after); + + if (after_line) + emit_line_note_after (NOTE_SOURCE_FILE (after_line), + NOTE_LINE_NUMBER (after_line), + insn); +} + +/* Make an insn of code JUMP_INSN with body PATTERN + and output it after the insn AFTER. */ + +rtx +emit_jump_insn_after (pattern, after) + register rtx pattern, after; +{ + register rtx insn; + + if (GET_CODE (pattern) == SEQUENCE) + insn = emit_insn_after (pattern, after); + else + { + insn = make_jump_insn_raw (pattern); + add_insn_after (insn, after); + } + + return insn; +} + +/* Make an insn of code BARRIER + and output it after the insn AFTER. */ + +rtx +emit_barrier_after (after) + register rtx after; +{ + register rtx insn = rtx_alloc (BARRIER); + + INSN_UID (insn) = cur_insn_uid++; + + add_insn_after (insn, after); + return insn; +} + +/* Emit the label LABEL after the insn AFTER. */ + +rtx +emit_label_after (label, after) + rtx label, after; +{ + /* This can be called twice for the same label + as a result of the confusion that follows a syntax error! + So make it harmless. */ + if (INSN_UID (label) == 0) + { + INSN_UID (label) = cur_insn_uid++; + add_insn_after (label, after); + } + + return label; +} + +/* Emit a note of subtype SUBTYPE after the insn AFTER. */ + +rtx +emit_note_after (subtype, after) + int subtype; + rtx after; +{ + register rtx note = rtx_alloc (NOTE); + INSN_UID (note) = cur_insn_uid++; + NOTE_SOURCE_FILE (note) = 0; + NOTE_LINE_NUMBER (note) = subtype; + add_insn_after (note, after); + return note; +} + +/* Emit a line note for FILE and LINE after the insn AFTER. */ + +rtx +emit_line_note_after (file, line, after) + char *file; + int line; + rtx after; +{ + register rtx note; + + if (no_line_numbers && line > 0) + { + cur_insn_uid++; + return 0; + } + + note = rtx_alloc (NOTE); + INSN_UID (note) = cur_insn_uid++; + NOTE_SOURCE_FILE (note) = file; + NOTE_LINE_NUMBER (note) = line; + add_insn_after (note, after); + return note; +} + +/* Make an insn of code INSN with pattern PATTERN + and add it to the end of the doubly-linked list. + If PATTERN is a SEQUENCE, take the elements of it + and emit an insn for each element. + + Returns the last insn emitted. */ + +rtx +emit_insn (pattern) + rtx pattern; +{ + rtx insn = last_insn; + + if (GET_CODE (pattern) == SEQUENCE) + { + register int i; + + for (i = 0; i < XVECLEN (pattern, 0); i++) + { + insn = XVECEXP (pattern, 0, i); + add_insn (insn); + } + if (XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) + sequence_result[XVECLEN (pattern, 0)] = pattern; + } + else + { + insn = make_insn_raw (pattern); + add_insn (insn); + } + + return insn; +} + +/* Emit the insns in a chain starting with INSN. + Return the last insn emitted. */ + +rtx +emit_insns (insn) + rtx insn; +{ + rtx last = 0; + + while (insn) + { + rtx next = NEXT_INSN (insn); + add_insn (insn); + last = insn; + insn = next; + } + + return last; +} + +/* Emit the insns in a chain starting with INSN and place them in front of + the insn BEFORE. Return the last insn emitted. */ + +rtx +emit_insns_before (insn, before) + rtx insn; + rtx before; +{ + rtx last = 0; + + while (insn) + { + rtx next = NEXT_INSN (insn); + add_insn_after (insn, PREV_INSN (before)); + last = insn; + insn = next; + } + + return last; +} + +/* Emit the insns in a chain starting with FIRST and place them in back of + the insn AFTER. Return the last insn emitted. */ + +rtx +emit_insns_after (first, after) + register rtx first; + register rtx after; +{ + register rtx last; + register rtx after_after; + + if (!after) + abort (); + + if (!first) + return first; + + for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) + continue; + + after_after = NEXT_INSN (after); + + NEXT_INSN (after) = first; + PREV_INSN (first) = after; + NEXT_INSN (last) = after_after; + if (after_after) + PREV_INSN (after_after) = last; + + if (after == last_insn) + last_insn = last; + return last; +} + +/* Make an insn of code JUMP_INSN with pattern PATTERN + and add it to the end of the doubly-linked list. */ + +rtx +emit_jump_insn (pattern) + rtx pattern; +{ + if (GET_CODE (pattern) == SEQUENCE) + return emit_insn (pattern); + else + { + register rtx insn = make_jump_insn_raw (pattern); + add_insn (insn); + return insn; + } +} + +/* Make an insn of code CALL_INSN with pattern PATTERN + and add it to the end of the doubly-linked list. */ + +rtx +emit_call_insn (pattern) + rtx pattern; +{ + if (GET_CODE (pattern) == SEQUENCE) + return emit_insn (pattern); + else + { + register rtx insn = make_insn_raw (pattern); + add_insn (insn); + PUT_CODE (insn, CALL_INSN); + return insn; + } +} + +/* Add the label LABEL to the end of the doubly-linked list. */ + +rtx +emit_label (label) + rtx label; +{ + /* This can be called twice for the same label + as a result of the confusion that follows a syntax error! + So make it harmless. */ + if (INSN_UID (label) == 0) + { + INSN_UID (label) = cur_insn_uid++; + add_insn (label); + } + return label; +} + +/* Make an insn of code BARRIER + and add it to the end of the doubly-linked list. */ + +rtx +emit_barrier () +{ + register rtx barrier = rtx_alloc (BARRIER); + INSN_UID (barrier) = cur_insn_uid++; + add_insn (barrier); + return barrier; +} + +/* Make an insn of code NOTE + with data-fields specified by FILE and LINE + and add it to the end of the doubly-linked list, + but only if line-numbers are desired for debugging info. */ + +rtx +emit_line_note (file, line) + char *file; + int line; +{ + emit_filename = file; + emit_lineno = line; + +#if 0 + if (no_line_numbers) + return 0; +#endif + + return emit_note (file, line); +} + +/* Make an insn of code NOTE + with data-fields specified by FILE and LINE + and add it to the end of the doubly-linked list. + If it is a line-number NOTE, omit it if it matches the previous one. */ + +rtx +emit_note (file, line) + char *file; + int line; +{ + register rtx note; + + if (line > 0) + { + if (file && last_filename && !strcmp (file, last_filename) + && line == last_linenum) + return 0; + last_filename = file; + last_linenum = line; + } + + if (no_line_numbers && line > 0) + { + cur_insn_uid++; + return 0; + } + + note = rtx_alloc (NOTE); + INSN_UID (note) = cur_insn_uid++; + NOTE_SOURCE_FILE (note) = file; + NOTE_LINE_NUMBER (note) = line; + add_insn (note); + return note; +} + +/* Emit a NOTE, and don't omit it even if LINE it the previous note. */ + +rtx +emit_line_note_force (file, line) + char *file; + int line; +{ + last_linenum = -1; + return emit_line_note (file, line); +} + +/* Cause next statement to emit a line note even if the line number + has not changed. This is used at the beginning of a function. */ + +void +force_next_line_note () +{ + last_linenum = -1; +} + +/* Return an indication of which type of insn should have X as a body. + The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ + +enum rtx_code +classify_insn (x) + rtx x; +{ + if (GET_CODE (x) == CODE_LABEL) + return CODE_LABEL; + if (GET_CODE (x) == CALL) + return CALL_INSN; + if (GET_CODE (x) == RETURN) + return JUMP_INSN; + if (GET_CODE (x) == SET) + { + if (SET_DEST (x) == pc_rtx) + return JUMP_INSN; + else if (GET_CODE (SET_SRC (x)) == CALL) + return CALL_INSN; + else + return INSN; + } + if (GET_CODE (x) == PARALLEL) + { + register int j; + for (j = XVECLEN (x, 0) - 1; j >= 0; j--) + if (GET_CODE (XVECEXP (x, 0, j)) == CALL) + return CALL_INSN; + else if (GET_CODE (XVECEXP (x, 0, j)) == SET + && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) + return JUMP_INSN; + else if (GET_CODE (XVECEXP (x, 0, j)) == SET + && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) + return CALL_INSN; + } + return INSN; +} + +/* Emit the rtl pattern X as an appropriate kind of insn. + If X is a label, it is simply added into the insn chain. */ + +rtx +emit (x) + rtx x; +{ + enum rtx_code code = classify_insn (x); + + if (code == CODE_LABEL) + return emit_label (x); + else if (code == INSN) + return emit_insn (x); + else if (code == JUMP_INSN) + { + register rtx insn = emit_jump_insn (x); + if (simplejump_p (insn) || GET_CODE (x) == RETURN) + return emit_barrier (); + return insn; + } + else if (code == CALL_INSN) + return emit_call_insn (x); + else + abort (); +} + +/* Begin emitting insns to a sequence which can be packaged in an RTL_EXPR. */ + +void +start_sequence () +{ + struct sequence_stack *tem; + + if (sequence_element_free_list) + { + /* Reuse a previously-saved struct sequence_stack. */ + tem = sequence_element_free_list; + sequence_element_free_list = tem->next; + } + else + tem = (struct sequence_stack *) permalloc (sizeof (struct sequence_stack)); + + tem->next = sequence_stack; + tem->first = first_insn; + tem->last = last_insn; + + sequence_stack = tem; + + first_insn = 0; + last_insn = 0; +} + +/* Set up the insn chain starting with FIRST + as the current sequence, saving the previously current one. */ + +void +push_to_sequence (first) + rtx first; +{ + rtx last; + + start_sequence (); + + for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); + + first_insn = first; + last_insn = last; +} + +/* Set up the outer-level insn chain + as the current sequence, saving the previously current one. */ + +void +push_topmost_sequence () +{ + struct sequence_stack *stack, *top; + + start_sequence (); + + for (stack = sequence_stack; stack; stack = stack->next) + top = stack; + + first_insn = top->first; + last_insn = top->last; +} + +/* After emitting to the outer-level insn chain, update the outer-level + insn chain, and restore the previous saved state. */ + +void +pop_topmost_sequence () +{ + struct sequence_stack *stack, *top; + + for (stack = sequence_stack; stack; stack = stack->next) + top = stack; + + top->first = first_insn; + top->last = last_insn; + + end_sequence (); +} + +/* After emitting to a sequence, restore previous saved state. + + To get the contents of the sequence just made, + you must call `gen_sequence' *before* calling here. */ + +void +end_sequence () +{ + struct sequence_stack *tem = sequence_stack; + + first_insn = tem->first; + last_insn = tem->last; + sequence_stack = tem->next; + + tem->next = sequence_element_free_list; + sequence_element_free_list = tem; +} + +/* Return 1 if currently emitting into a sequence. */ + +int +in_sequence_p () +{ + return sequence_stack != 0; +} + +/* Generate a SEQUENCE rtx containing the insns already emitted + to the current sequence. + + This is how the gen_... function from a DEFINE_EXPAND + constructs the SEQUENCE that it returns. */ + +rtx +gen_sequence () +{ + rtx result; + rtx tem; + rtvec newvec; + int i; + int len; + + /* Count the insns in the chain. */ + len = 0; + for (tem = first_insn; tem; tem = NEXT_INSN (tem)) + len++; + + /* If only one insn, return its pattern rather than a SEQUENCE. + (Now that we cache SEQUENCE expressions, it isn't worth special-casing + the case of an empty list.) */ + if (len == 1 + && (GET_CODE (first_insn) == INSN + || GET_CODE (first_insn) == JUMP_INSN + || GET_CODE (first_insn) == CALL_INSN)) + return PATTERN (first_insn); + + /* Put them in a vector. See if we already have a SEQUENCE of the + appropriate length around. */ + if (len < SEQUENCE_RESULT_SIZE && (result = sequence_result[len]) != 0) + sequence_result[len] = 0; + else + { + /* Ensure that this rtl goes in saveable_obstack, since we may be + caching it. */ + push_obstacks_nochange (); + rtl_in_saveable_obstack (); + result = gen_rtx (SEQUENCE, VOIDmode, rtvec_alloc (len)); + pop_obstacks (); + } + + for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++) + XVECEXP (result, 0, i) = tem; + + return result; +} + +/* Set up regno_reg_rtx, reg_rtx_no and regno_pointer_flag + according to the chain of insns starting with FIRST. + + Also set cur_insn_uid to exceed the largest uid in that chain. + + This is used when an inline function's rtl is saved + and passed to rest_of_compilation later. */ + +static void restore_reg_data_1 (); + +void +restore_reg_data (first) + rtx first; +{ + register rtx insn; + int i; + register int max_uid = 0; + + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + if (INSN_UID (insn) >= max_uid) + max_uid = INSN_UID (insn); + + switch (GET_CODE (insn)) + { + case NOTE: + case CODE_LABEL: + case BARRIER: + break; + + case JUMP_INSN: + case CALL_INSN: + case INSN: + restore_reg_data_1 (PATTERN (insn)); + break; + } + } + + /* Don't duplicate the uids already in use. */ + cur_insn_uid = max_uid + 1; + + /* If any regs are missing, make them up. + + ??? word_mode is not necessarily the right mode. Most likely these REGs + are never used. At some point this should be checked. */ + + for (i = FIRST_PSEUDO_REGISTER; i < reg_rtx_no; i++) + if (regno_reg_rtx[i] == 0) + regno_reg_rtx[i] = gen_rtx (REG, word_mode, i); +} + +static void +restore_reg_data_1 (orig) + rtx orig; +{ + register rtx x = orig; + register int i; + register enum rtx_code code; + register char *format_ptr; + + code = GET_CODE (x); + + switch (code) + { + case QUEUED: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CODE_LABEL: + case PC: + case CC0: + case LABEL_REF: + return; + + case REG: + if (REGNO (x) >= FIRST_PSEUDO_REGISTER) + { + /* Make sure regno_pointer_flag and regno_reg_rtx are large + enough to have an element for this pseudo reg number. */ + if (REGNO (x) >= reg_rtx_no) + { + reg_rtx_no = REGNO (x); + + if (reg_rtx_no >= regno_pointer_flag_length) + { + int newlen = MAX (regno_pointer_flag_length * 2, + reg_rtx_no + 30); + rtx *new1; + char *new = (char *) oballoc (newlen); + bzero (new, newlen); + bcopy (regno_pointer_flag, new, regno_pointer_flag_length); + + new1 = (rtx *) oballoc (newlen * sizeof (rtx)); + bzero (new1, newlen * sizeof (rtx)); + bcopy (regno_reg_rtx, new1, regno_pointer_flag_length * sizeof (rtx)); + + regno_pointer_flag = new; + regno_reg_rtx = new1; + regno_pointer_flag_length = newlen; + } + reg_rtx_no ++; + } + regno_reg_rtx[REGNO (x)] = x; + } + return; + + case MEM: + if (GET_CODE (XEXP (x, 0)) == REG) + mark_reg_pointer (XEXP (x, 0)); + restore_reg_data_1 (XEXP (x, 0)); + return; + } + + /* Now scan the subexpressions recursively. */ + + format_ptr = GET_RTX_FORMAT (code); + + for (i = 0; i < GET_RTX_LENGTH (code); i++) + { + switch (*format_ptr++) + { + case 'e': + restore_reg_data_1 (XEXP (x, i)); + break; + + case 'E': + if (XVEC (x, i) != NULL) + { + register int j; + + for (j = 0; j < XVECLEN (x, i); j++) + restore_reg_data_1 (XVECEXP (x, i, j)); + } + break; + } + } +} + +/* Initialize data structures and variables in this file + before generating rtl for each function. */ + +void +init_emit () +{ + int i; + + first_insn = NULL; + last_insn = NULL; + cur_insn_uid = 1; + reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; + last_linenum = 0; + last_filename = 0; + first_label_num = label_num; + last_label_num = 0; + sequence_stack = NULL; + + /* Clear the start_sequence/gen_sequence cache. */ + sequence_element_free_list = 0; + for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) + sequence_result[i] = 0; + + /* Init the tables that describe all the pseudo regs. */ + + regno_pointer_flag_length = LAST_VIRTUAL_REGISTER + 101; + + regno_pointer_flag + = (char *) oballoc (regno_pointer_flag_length); + bzero (regno_pointer_flag, regno_pointer_flag_length); + + regno_reg_rtx + = (rtx *) oballoc (regno_pointer_flag_length * sizeof (rtx)); + bzero (regno_reg_rtx, regno_pointer_flag_length * sizeof (rtx)); + + /* Put copies of all the virtual register rtx into regno_reg_rtx. */ + regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; + regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; + regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; + regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; + + /* Indicate that the virtual registers and stack locations are + all pointers. */ + REGNO_POINTER_FLAG (STACK_POINTER_REGNUM) = 1; + REGNO_POINTER_FLAG (FRAME_POINTER_REGNUM) = 1; + REGNO_POINTER_FLAG (ARG_POINTER_REGNUM) = 1; + + REGNO_POINTER_FLAG (VIRTUAL_INCOMING_ARGS_REGNUM) = 1; + REGNO_POINTER_FLAG (VIRTUAL_STACK_VARS_REGNUM) = 1; + REGNO_POINTER_FLAG (VIRTUAL_STACK_DYNAMIC_REGNUM) = 1; + REGNO_POINTER_FLAG (VIRTUAL_OUTGOING_ARGS_REGNUM) = 1; + +#ifdef INIT_EXPANDERS + INIT_EXPANDERS; +#endif +} + +/* Create some permanent unique rtl objects shared between all functions. + LINE_NUMBERS is nonzero if line numbers are to be generated. */ + +void +init_emit_once (line_numbers) + int line_numbers; +{ + int i; + enum machine_mode mode; + + no_line_numbers = ! line_numbers; + + sequence_stack = NULL; + + /* Create the unique rtx's for certain rtx codes and operand values. */ + + pc_rtx = gen_rtx (PC, VOIDmode); + cc0_rtx = gen_rtx (CC0, VOIDmode); + + /* Don't use gen_rtx here since gen_rtx in this case + tries to use these variables. */ + for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) + { + const_int_rtx[i + MAX_SAVED_CONST_INT] = rtx_alloc (CONST_INT); + PUT_MODE (const_int_rtx[i + MAX_SAVED_CONST_INT], VOIDmode); + INTVAL (const_int_rtx[i + MAX_SAVED_CONST_INT]) = i; + } + + /* These four calls obtain some of the rtx expressions made above. */ + const0_rtx = GEN_INT (0); + const1_rtx = GEN_INT (1); + const2_rtx = GEN_INT (2); + constm1_rtx = GEN_INT (-1); + + /* This will usually be one of the above constants, but may be a new rtx. */ + const_true_rtx = GEN_INT (STORE_FLAG_VALUE); + + dconst0 = REAL_VALUE_ATOF ("0", DFmode); + dconst1 = REAL_VALUE_ATOF ("1", DFmode); + dconst2 = REAL_VALUE_ATOF ("2", DFmode); + dconstm1 = REAL_VALUE_ATOF ("-1", DFmode); + + for (i = 0; i <= 2; i++) + { + for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + { + rtx tem = rtx_alloc (CONST_DOUBLE); + union real_extract u; + + bzero (&u, sizeof u); /* Zero any holes in a structure. */ + u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2; + + bcopy (&u, &CONST_DOUBLE_LOW (tem), sizeof u); + CONST_DOUBLE_MEM (tem) = cc0_rtx; + PUT_MODE (tem, mode); + + const_tiny_rtx[i][(int) mode] = tem; + } + + const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + const_tiny_rtx[i][(int) mode] = GEN_INT (i); + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); + mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + const_tiny_rtx[i][(int) mode] = GEN_INT (i); + } + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_CC); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + const_tiny_rtx[0][(int) mode] = const0_rtx; + + stack_pointer_rtx = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM); + frame_pointer_rtx = gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM); + + if (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM) + arg_pointer_rtx = frame_pointer_rtx; + else if (STACK_POINTER_REGNUM == ARG_POINTER_REGNUM) + arg_pointer_rtx = stack_pointer_rtx; + else + arg_pointer_rtx = gen_rtx (REG, Pmode, ARG_POINTER_REGNUM); + + /* Create the virtual registers. Do so here since the following objects + might reference them. */ + + virtual_incoming_args_rtx = gen_rtx (REG, Pmode, + VIRTUAL_INCOMING_ARGS_REGNUM); + virtual_stack_vars_rtx = gen_rtx (REG, Pmode, + VIRTUAL_STACK_VARS_REGNUM); + virtual_stack_dynamic_rtx = gen_rtx (REG, Pmode, + VIRTUAL_STACK_DYNAMIC_REGNUM); + virtual_outgoing_args_rtx = gen_rtx (REG, Pmode, + VIRTUAL_OUTGOING_ARGS_REGNUM); + +#ifdef STRUCT_VALUE + struct_value_rtx = STRUCT_VALUE; +#else + struct_value_rtx = gen_rtx (REG, Pmode, STRUCT_VALUE_REGNUM); +#endif + +#ifdef STRUCT_VALUE_INCOMING + struct_value_incoming_rtx = STRUCT_VALUE_INCOMING; +#else +#ifdef STRUCT_VALUE_INCOMING_REGNUM + struct_value_incoming_rtx + = gen_rtx (REG, Pmode, STRUCT_VALUE_INCOMING_REGNUM); +#else + struct_value_incoming_rtx = struct_value_rtx; +#endif +#endif + +#ifdef STATIC_CHAIN_REGNUM + static_chain_rtx = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM); + +#ifdef STATIC_CHAIN_INCOMING_REGNUM + if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) + static_chain_incoming_rtx = gen_rtx (REG, Pmode, STATIC_CHAIN_INCOMING_REGNUM); + else +#endif + static_chain_incoming_rtx = static_chain_rtx; +#endif + +#ifdef STATIC_CHAIN + static_chain_rtx = STATIC_CHAIN; + +#ifdef STATIC_CHAIN_INCOMING + static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; +#else + static_chain_incoming_rtx = static_chain_rtx; +#endif +#endif + +#ifdef PIC_OFFSET_TABLE_REGNUM + pic_offset_table_rtx = gen_rtx (REG, Pmode, PIC_OFFSET_TABLE_REGNUM); +#endif +} diff --git a/gnu/usr.bin/cc/lib/explow.c b/gnu/usr.bin/cc/lib/explow.c new file mode 100644 index 000000000000..f13129fa0347 --- /dev/null +++ b/gnu/usr.bin/cc/lib/explow.c @@ -0,0 +1,1055 @@ +/* Subroutines for manipulating rtx's in semantically interesting ways. + Copyright (C) 1987, 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include "rtl.h" +#include "tree.h" +#include "flags.h" +#include "expr.h" +#include "hard-reg-set.h" +#include "insn-config.h" +#include "recog.h" +#include "insn-flags.h" +#include "insn-codes.h" + +/* Return an rtx for the sum of X and the integer C. + + This function should be used via the `plus_constant' macro. */ + +rtx +plus_constant_wide (x, c) + register rtx x; + register HOST_WIDE_INT c; +{ + register RTX_CODE code; + register enum machine_mode mode; + register rtx tem; + int all_constant = 0; + + if (c == 0) + return x; + + restart: + + code = GET_CODE (x); + mode = GET_MODE (x); + switch (code) + { + case CONST_INT: + return GEN_INT (INTVAL (x) + c); + + case CONST_DOUBLE: + { + HOST_WIDE_INT l1 = CONST_DOUBLE_LOW (x); + HOST_WIDE_INT h1 = CONST_DOUBLE_HIGH (x); + HOST_WIDE_INT l2 = c; + HOST_WIDE_INT h2 = c < 0 ? ~0 : 0; + HOST_WIDE_INT lv, hv; + + add_double (l1, h1, l2, h2, &lv, &hv); + + return immed_double_const (lv, hv, VOIDmode); + } + + case MEM: + /* If this is a reference to the constant pool, try replacing it with + a reference to a new constant. If the resulting address isn't + valid, don't return it because we have no way to validize it. */ + if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))) + { + tem + = force_const_mem (GET_MODE (x), + plus_constant (get_pool_constant (XEXP (x, 0)), + c)); + if (memory_address_p (GET_MODE (tem), XEXP (tem, 0))) + return tem; + } + break; + + case CONST: + /* If adding to something entirely constant, set a flag + so that we can add a CONST around the result. */ + x = XEXP (x, 0); + all_constant = 1; + goto restart; + + case SYMBOL_REF: + case LABEL_REF: + all_constant = 1; + break; + + case PLUS: + /* The interesting case is adding the integer to a sum. + Look for constant term in the sum and combine + with C. For an integer constant term, we make a combined + integer. For a constant term that is not an explicit integer, + we cannot really combine, but group them together anyway. + + Use a recursive call in case the remaining operand is something + that we handle specially, such as a SYMBOL_REF. */ + + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + return plus_constant (XEXP (x, 0), c + INTVAL (XEXP (x, 1))); + else if (CONSTANT_P (XEXP (x, 0))) + return gen_rtx (PLUS, mode, + plus_constant (XEXP (x, 0), c), + XEXP (x, 1)); + else if (CONSTANT_P (XEXP (x, 1))) + return gen_rtx (PLUS, mode, + XEXP (x, 0), + plus_constant (XEXP (x, 1), c)); + } + + if (c != 0) + x = gen_rtx (PLUS, mode, x, GEN_INT (c)); + + if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) + return x; + else if (all_constant) + return gen_rtx (CONST, mode, x); + else + return x; +} + +/* This is the same as `plus_constant', except that it handles LO_SUM. + + This function should be used via the `plus_constant_for_output' macro. */ + +rtx +plus_constant_for_output_wide (x, c) + register rtx x; + register HOST_WIDE_INT c; +{ + register RTX_CODE code = GET_CODE (x); + register enum machine_mode mode = GET_MODE (x); + int all_constant = 0; + + if (GET_CODE (x) == LO_SUM) + return gen_rtx (LO_SUM, mode, XEXP (x, 0), + plus_constant_for_output (XEXP (x, 1), c)); + + else + return plus_constant (x, c); +} + +/* If X is a sum, return a new sum like X but lacking any constant terms. + Add all the removed constant terms into *CONSTPTR. + X itself is not altered. The result != X if and only if + it is not isomorphic to X. */ + +rtx +eliminate_constant_term (x, constptr) + rtx x; + rtx *constptr; +{ + register rtx x0, x1; + rtx tem; + + if (GET_CODE (x) != PLUS) + return x; + + /* First handle constants appearing at this level explicitly. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && 0 != (tem = simplify_binary_operation (PLUS, GET_MODE (x), *constptr, + XEXP (x, 1))) + && GET_CODE (tem) == CONST_INT) + { + *constptr = tem; + return eliminate_constant_term (XEXP (x, 0), constptr); + } + + tem = const0_rtx; + x0 = eliminate_constant_term (XEXP (x, 0), &tem); + x1 = eliminate_constant_term (XEXP (x, 1), &tem); + if ((x1 != XEXP (x, 1) || x0 != XEXP (x, 0)) + && 0 != (tem = simplify_binary_operation (PLUS, GET_MODE (x), + *constptr, tem)) + && GET_CODE (tem) == CONST_INT) + { + *constptr = tem; + return gen_rtx (PLUS, GET_MODE (x), x0, x1); + } + + return x; +} + +/* Returns the insn that next references REG after INSN, or 0 + if REG is clobbered before next referenced or we cannot find + an insn that references REG in a straight-line piece of code. */ + +rtx +find_next_ref (reg, insn) + rtx reg; + rtx insn; +{ + rtx next; + + for (insn = NEXT_INSN (insn); insn; insn = next) + { + next = NEXT_INSN (insn); + if (GET_CODE (insn) == NOTE) + continue; + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == BARRIER) + return 0; + if (GET_CODE (insn) == INSN + || GET_CODE (insn) == JUMP_INSN + || GET_CODE (insn) == CALL_INSN) + { + if (reg_set_p (reg, insn)) + return 0; + if (reg_mentioned_p (reg, PATTERN (insn))) + return insn; + if (GET_CODE (insn) == JUMP_INSN) + { + if (simplejump_p (insn)) + next = JUMP_LABEL (insn); + else + return 0; + } + if (GET_CODE (insn) == CALL_INSN + && REGNO (reg) < FIRST_PSEUDO_REGISTER + && call_used_regs[REGNO (reg)]) + return 0; + } + else + abort (); + } + return 0; +} + +/* Return an rtx for the size in bytes of the value of EXP. */ + +rtx +expr_size (exp) + tree exp; +{ + return expand_expr (size_in_bytes (TREE_TYPE (exp)), + NULL_RTX, TYPE_MODE (sizetype), 0); +} + +/* Return a copy of X in which all memory references + and all constants that involve symbol refs + have been replaced with new temporary registers. + Also emit code to load the memory locations and constants + into those registers. + + If X contains no such constants or memory references, + X itself (not a copy) is returned. + + If a constant is found in the address that is not a legitimate constant + in an insn, it is left alone in the hope that it might be valid in the + address. + + X may contain no arithmetic except addition, subtraction and multiplication. + Values returned by expand_expr with 1 for sum_ok fit this constraint. */ + +static rtx +break_out_memory_refs (x) + register rtx x; +{ + if (GET_CODE (x) == MEM + || (CONSTANT_P (x) && CONSTANT_ADDRESS_P (x) + && GET_MODE (x) != VOIDmode)) + { + register rtx temp = force_reg (GET_MODE (x), x); + mark_reg_pointer (temp); + x = temp; + } + else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS + || GET_CODE (x) == MULT) + { + register rtx op0 = break_out_memory_refs (XEXP (x, 0)); + register rtx op1 = break_out_memory_refs (XEXP (x, 1)); + if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) + x = gen_rtx (GET_CODE (x), Pmode, op0, op1); + } + return x; +} + +/* Given a memory address or facsimile X, construct a new address, + currently equivalent, that is stable: future stores won't change it. + + X must be composed of constants, register and memory references + combined with addition, subtraction and multiplication: + in other words, just what you can get from expand_expr if sum_ok is 1. + + Works by making copies of all regs and memory locations used + by X and combining them the same way X does. + You could also stabilize the reference to this address + by copying the address to a register with copy_to_reg; + but then you wouldn't get indexed addressing in the reference. */ + +rtx +copy_all_regs (x) + register rtx x; +{ + if (GET_CODE (x) == REG) + { + if (REGNO (x) != FRAME_POINTER_REGNUM) + x = copy_to_reg (x); + } + else if (GET_CODE (x) == MEM) + x = copy_to_reg (x); + else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS + || GET_CODE (x) == MULT) + { + register rtx op0 = copy_all_regs (XEXP (x, 0)); + register rtx op1 = copy_all_regs (XEXP (x, 1)); + if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) + x = gen_rtx (GET_CODE (x), Pmode, op0, op1); + } + return x; +} + +/* Return something equivalent to X but valid as a memory address + for something of mode MODE. When X is not itself valid, this + works by copying X or subexpressions of it into registers. */ + +rtx +memory_address (mode, x) + enum machine_mode mode; + register rtx x; +{ + register rtx oldx; + + /* By passing constant addresses thru registers + we get a chance to cse them. */ + if (! cse_not_expected && CONSTANT_P (x) && CONSTANT_ADDRESS_P (x)) + return force_reg (Pmode, x); + + /* Accept a QUEUED that refers to a REG + even though that isn't a valid address. + On attempting to put this in an insn we will call protect_from_queue + which will turn it into a REG, which is valid. */ + if (GET_CODE (x) == QUEUED + && GET_CODE (QUEUED_VAR (x)) == REG) + return x; + + /* We get better cse by rejecting indirect addressing at this stage. + Let the combiner create indirect addresses where appropriate. + For now, generate the code so that the subexpressions useful to share + are visible. But not if cse won't be done! */ + oldx = x; + if (! cse_not_expected && GET_CODE (x) != REG) + x = break_out_memory_refs (x); + + /* At this point, any valid address is accepted. */ + GO_IF_LEGITIMATE_ADDRESS (mode, x, win); + + /* If it was valid before but breaking out memory refs invalidated it, + use it the old way. */ + if (memory_address_p (mode, oldx)) + goto win2; + + /* Perform machine-dependent transformations on X + in certain cases. This is not necessary since the code + below can handle all possible cases, but machine-dependent + transformations can make better code. */ + LEGITIMIZE_ADDRESS (x, oldx, mode, win); + + /* PLUS and MULT can appear in special ways + as the result of attempts to make an address usable for indexing. + Usually they are dealt with by calling force_operand, below. + But a sum containing constant terms is special + if removing them makes the sum a valid address: + then we generate that address in a register + and index off of it. We do this because it often makes + shorter code, and because the addresses thus generated + in registers often become common subexpressions. */ + if (GET_CODE (x) == PLUS) + { + rtx constant_term = const0_rtx; + rtx y = eliminate_constant_term (x, &constant_term); + if (constant_term == const0_rtx + || ! memory_address_p (mode, y)) + return force_operand (x, NULL_RTX); + + y = gen_rtx (PLUS, GET_MODE (x), copy_to_reg (y), constant_term); + if (! memory_address_p (mode, y)) + return force_operand (x, NULL_RTX); + return y; + } + if (GET_CODE (x) == MULT || GET_CODE (x) == MINUS) + return force_operand (x, NULL_RTX); + + /* If we have a register that's an invalid address, + it must be a hard reg of the wrong class. Copy it to a pseudo. */ + if (GET_CODE (x) == REG) + return copy_to_reg (x); + + /* Last resort: copy the value to a register, since + the register is a valid address. */ + return force_reg (Pmode, x); + + win2: + x = oldx; + win: + if (flag_force_addr && ! cse_not_expected && GET_CODE (x) != REG + /* Don't copy an addr via a reg if it is one of our stack slots. */ + && ! (GET_CODE (x) == PLUS + && (XEXP (x, 0) == virtual_stack_vars_rtx + || XEXP (x, 0) == virtual_incoming_args_rtx))) + { + if (general_operand (x, Pmode)) + return force_reg (Pmode, x); + else + return force_operand (x, NULL_RTX); + } + return x; +} + +/* Like `memory_address' but pretend `flag_force_addr' is 0. */ + +rtx +memory_address_noforce (mode, x) + enum machine_mode mode; + rtx x; +{ + int ambient_force_addr = flag_force_addr; + rtx val; + + flag_force_addr = 0; + val = memory_address (mode, x); + flag_force_addr = ambient_force_addr; + return val; +} + +/* Convert a mem ref into one with a valid memory address. + Pass through anything else unchanged. */ + +rtx +validize_mem (ref) + rtx ref; +{ + if (GET_CODE (ref) != MEM) + return ref; + if (memory_address_p (GET_MODE (ref), XEXP (ref, 0))) + return ref; + /* Don't alter REF itself, since that is probably a stack slot. */ + return change_address (ref, GET_MODE (ref), XEXP (ref, 0)); +} + +/* Return a modified copy of X with its memory address copied + into a temporary register to protect it from side effects. + If X is not a MEM, it is returned unchanged (and not copied). + Perhaps even if it is a MEM, if there is no need to change it. */ + +rtx +stabilize (x) + rtx x; +{ + register rtx addr; + if (GET_CODE (x) != MEM) + return x; + addr = XEXP (x, 0); + if (rtx_unstable_p (addr)) + { + rtx temp = copy_all_regs (addr); + rtx mem; + if (GET_CODE (temp) != REG) + temp = copy_to_reg (temp); + mem = gen_rtx (MEM, GET_MODE (x), temp); + + /* Mark returned memref with in_struct if it's in an array or + structure. Copy const and volatile from original memref. */ + + MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (x) || GET_CODE (addr) == PLUS; + RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (x); + MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (x); + return mem; + } + return x; +} + +/* Copy the value or contents of X to a new temp reg and return that reg. */ + +rtx +copy_to_reg (x) + rtx x; +{ + register rtx temp = gen_reg_rtx (GET_MODE (x)); + + /* If not an operand, must be an address with PLUS and MULT so + do the computation. */ + if (! general_operand (x, VOIDmode)) + x = force_operand (x, temp); + + if (x != temp) + emit_move_insn (temp, x); + + return temp; +} + +/* Like copy_to_reg but always give the new register mode Pmode + in case X is a constant. */ + +rtx +copy_addr_to_reg (x) + rtx x; +{ + return copy_to_mode_reg (Pmode, x); +} + +/* Like copy_to_reg but always give the new register mode MODE + in case X is a constant. */ + +rtx +copy_to_mode_reg (mode, x) + enum machine_mode mode; + rtx x; +{ + register rtx temp = gen_reg_rtx (mode); + + /* If not an operand, must be an address with PLUS and MULT so + do the computation. */ + if (! general_operand (x, VOIDmode)) + x = force_operand (x, temp); + + if (GET_MODE (x) != mode && GET_MODE (x) != VOIDmode) + abort (); + if (x != temp) + emit_move_insn (temp, x); + return temp; +} + +/* Load X into a register if it is not already one. + Use mode MODE for the register. + X should be valid for mode MODE, but it may be a constant which + is valid for all integer modes; that's why caller must specify MODE. + + The caller must not alter the value in the register we return, + since we mark it as a "constant" register. */ + +rtx +force_reg (mode, x) + enum machine_mode mode; + rtx x; +{ + register rtx temp, insn; + + if (GET_CODE (x) == REG) + return x; + temp = gen_reg_rtx (mode); + insn = emit_move_insn (temp, x); + /* Let optimizers know that TEMP's value never changes + and that X can be substituted for it. */ + if (CONSTANT_P (x)) + { + rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); + + if (note) + XEXP (note, 0) = x; + else + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, x, REG_NOTES (insn)); + } + return temp; +} + +/* If X is a memory ref, copy its contents to a new temp reg and return + that reg. Otherwise, return X. */ + +rtx +force_not_mem (x) + rtx x; +{ + register rtx temp; + if (GET_CODE (x) != MEM || GET_MODE (x) == BLKmode) + return x; + temp = gen_reg_rtx (GET_MODE (x)); + emit_move_insn (temp, x); + return temp; +} + +/* Copy X to TARGET (if it's nonzero and a reg) + or to a new temp reg and return that reg. + MODE is the mode to use for X in case it is a constant. */ + +rtx +copy_to_suggested_reg (x, target, mode) + rtx x, target; + enum machine_mode mode; +{ + register rtx temp; + + if (target && GET_CODE (target) == REG) + temp = target; + else + temp = gen_reg_rtx (mode); + + emit_move_insn (temp, x); + return temp; +} + +/* Adjust the stack pointer by ADJUST (an rtx for a number of bytes). + This pops when ADJUST is positive. ADJUST need not be constant. */ + +void +adjust_stack (adjust) + rtx adjust; +{ + rtx temp; + adjust = protect_from_queue (adjust, 0); + + if (adjust == const0_rtx) + return; + + temp = expand_binop (Pmode, +#ifdef STACK_GROWS_DOWNWARD + add_optab, +#else + sub_optab, +#endif + stack_pointer_rtx, adjust, stack_pointer_rtx, 0, + OPTAB_LIB_WIDEN); + + if (temp != stack_pointer_rtx) + emit_move_insn (stack_pointer_rtx, temp); +} + +/* Adjust the stack pointer by minus ADJUST (an rtx for a number of bytes). + This pushes when ADJUST is positive. ADJUST need not be constant. */ + +void +anti_adjust_stack (adjust) + rtx adjust; +{ + rtx temp; + adjust = protect_from_queue (adjust, 0); + + if (adjust == const0_rtx) + return; + + temp = expand_binop (Pmode, +#ifdef STACK_GROWS_DOWNWARD + sub_optab, +#else + add_optab, +#endif + stack_pointer_rtx, adjust, stack_pointer_rtx, 0, + OPTAB_LIB_WIDEN); + + if (temp != stack_pointer_rtx) + emit_move_insn (stack_pointer_rtx, temp); +} + +/* Round the size of a block to be pushed up to the boundary required + by this machine. SIZE is the desired size, which need not be constant. */ + +rtx +round_push (size) + rtx size; +{ +#ifdef STACK_BOUNDARY + int align = STACK_BOUNDARY / BITS_PER_UNIT; + if (align == 1) + return size; + if (GET_CODE (size) == CONST_INT) + { + int new = (INTVAL (size) + align - 1) / align * align; + if (INTVAL (size) != new) + size = GEN_INT (new); + } + else + { + size = expand_divmod (0, CEIL_DIV_EXPR, Pmode, size, GEN_INT (align), + NULL_RTX, 1); + size = expand_mult (Pmode, size, GEN_INT (align), NULL_RTX, 1); + } +#endif /* STACK_BOUNDARY */ + return size; +} + +/* Save the stack pointer for the purpose in SAVE_LEVEL. PSAVE is a pointer + to a previously-created save area. If no save area has been allocated, + this function will allocate one. If a save area is specified, it + must be of the proper mode. + + The insns are emitted after insn AFTER, if nonzero, otherwise the insns + are emitted at the current position. */ + +void +emit_stack_save (save_level, psave, after) + enum save_level save_level; + rtx *psave; + rtx after; +{ + rtx sa = *psave; + /* The default is that we use a move insn and save in a Pmode object. */ + rtx (*fcn) () = gen_move_insn; + enum machine_mode mode = Pmode; + + /* See if this machine has anything special to do for this kind of save. */ + switch (save_level) + { +#ifdef HAVE_save_stack_block + case SAVE_BLOCK: + if (HAVE_save_stack_block) + { + fcn = gen_save_stack_block; + mode = insn_operand_mode[CODE_FOR_save_stack_block][0]; + } + break; +#endif +#ifdef HAVE_save_stack_function + case SAVE_FUNCTION: + if (HAVE_save_stack_function) + { + fcn = gen_save_stack_function; + mode = insn_operand_mode[CODE_FOR_save_stack_function][0]; + } + break; +#endif +#ifdef HAVE_save_stack_nonlocal + case SAVE_NONLOCAL: + if (HAVE_save_stack_nonlocal) + { + fcn = gen_save_stack_nonlocal; + mode = insn_operand_mode[CODE_FOR_save_stack_nonlocal][0]; + } + break; +#endif + } + + /* If there is no save area and we have to allocate one, do so. Otherwise + verify the save area is the proper mode. */ + + if (sa == 0) + { + if (mode != VOIDmode) + { + if (save_level == SAVE_NONLOCAL) + *psave = sa = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); + else + *psave = sa = gen_reg_rtx (mode); + } + } + else + { + if (mode == VOIDmode || GET_MODE (sa) != mode) + abort (); + } + + if (after) + { + rtx seq; + + start_sequence (); + /* We must validize inside the sequence, to ensure that any instructions + created by the validize call also get moved to the right place. */ + if (sa != 0) + sa = validize_mem (sa); + emit_insn (fcn (sa, stack_pointer_rtx)); + seq = gen_sequence (); + end_sequence (); + emit_insn_after (seq, after); + } + else + { + if (sa != 0) + sa = validize_mem (sa); + emit_insn (fcn (sa, stack_pointer_rtx)); + } +} + +/* Restore the stack pointer for the purpose in SAVE_LEVEL. SA is the save + area made by emit_stack_save. If it is zero, we have nothing to do. + + Put any emitted insns after insn AFTER, if nonzero, otherwise at + current position. */ + +void +emit_stack_restore (save_level, sa, after) + enum save_level save_level; + rtx after; + rtx sa; +{ + /* The default is that we use a move insn. */ + rtx (*fcn) () = gen_move_insn; + + /* See if this machine has anything special to do for this kind of save. */ + switch (save_level) + { +#ifdef HAVE_restore_stack_block + case SAVE_BLOCK: + if (HAVE_restore_stack_block) + fcn = gen_restore_stack_block; + break; +#endif +#ifdef HAVE_restore_stack_function + case SAVE_FUNCTION: + if (HAVE_restore_stack_function) + fcn = gen_restore_stack_function; + break; +#endif +#ifdef HAVE_restore_stack_nonlocal + + case SAVE_NONLOCAL: + if (HAVE_restore_stack_nonlocal) + fcn = gen_restore_stack_nonlocal; + break; +#endif + } + + if (sa != 0) + sa = validize_mem (sa); + + if (after) + { + rtx seq; + + start_sequence (); + emit_insn (fcn (stack_pointer_rtx, sa)); + seq = gen_sequence (); + end_sequence (); + emit_insn_after (seq, after); + } + else + emit_insn (fcn (stack_pointer_rtx, sa)); +} + +/* Return an rtx representing the address of an area of memory dynamically + pushed on the stack. This region of memory is always aligned to + a multiple of BIGGEST_ALIGNMENT. + + Any required stack pointer alignment is preserved. + + SIZE is an rtx representing the size of the area. + TARGET is a place in which the address can be placed. + + KNOWN_ALIGN is the alignment (in bits) that we know SIZE has. */ + +rtx +allocate_dynamic_stack_space (size, target, known_align) + rtx size; + rtx target; + int known_align; +{ + /* Ensure the size is in the proper mode. */ + if (GET_MODE (size) != VOIDmode && GET_MODE (size) != Pmode) + size = convert_to_mode (Pmode, size, 1); + + /* We will need to ensure that the address we return is aligned to + BIGGEST_ALIGNMENT. If STACK_DYNAMIC_OFFSET is defined, we don't + always know its final value at this point in the compilation (it + might depend on the size of the outgoing parameter lists, for + example), so we must align the value to be returned in that case. + (Note that STACK_DYNAMIC_OFFSET will have a default non-zero value if + STACK_POINTER_OFFSET or ACCUMULATE_OUTGOING_ARGS are defined). + We must also do an alignment operation on the returned value if + the stack pointer alignment is less strict that BIGGEST_ALIGNMENT. + + If we have to align, we must leave space in SIZE for the hole + that might result from the alignment operation. */ + +#if defined (STACK_DYNAMIC_OFFSET) || defined(STACK_POINTER_OFFSET) || defined (ALLOCATE_OUTGOING_ARGS) +#define MUST_ALIGN +#endif + +#if ! defined (MUST_ALIGN) && (!defined(STACK_BOUNDARY) || STACK_BOUNDARY < BIGGEST_ALIGNMENT) +#define MUST_ALIGN +#endif + +#ifdef MUST_ALIGN + +#if 0 /* It turns out we must always make extra space, if MUST_ALIGN + because we must always round the address up at the end, + because we don't know whether the dynamic offset + will mess up the desired alignment. */ + /* If we have to round the address up regardless of known_align, + make extra space regardless, also. */ + if (known_align % BIGGEST_ALIGNMENT != 0) +#endif + { + if (GET_CODE (size) == CONST_INT) + size = GEN_INT (INTVAL (size) + + (BIGGEST_ALIGNMENT / BITS_PER_UNIT - 1)); + else + size = expand_binop (Pmode, add_optab, size, + GEN_INT (BIGGEST_ALIGNMENT / BITS_PER_UNIT - 1), + NULL_RTX, 1, OPTAB_LIB_WIDEN); + } + +#endif + +#ifdef SETJMP_VIA_SAVE_AREA + /* If setjmp restores regs from a save area in the stack frame, + avoid clobbering the reg save area. Note that the offset of + virtual_incoming_args_rtx includes the preallocated stack args space. + It would be no problem to clobber that, but it's on the wrong side + of the old save area. */ + { + rtx dynamic_offset + = expand_binop (Pmode, sub_optab, virtual_stack_dynamic_rtx, + stack_pointer_rtx, NULL_RTX, 1, OPTAB_LIB_WIDEN); + size = expand_binop (Pmode, add_optab, size, dynamic_offset, + NULL_RTX, 1, OPTAB_LIB_WIDEN); + } +#endif /* SETJMP_VIA_SAVE_AREA */ + + /* Round the size to a multiple of the required stack alignment. + Since the stack if presumed to be rounded before this allocation, + this will maintain the required alignment. + + If the stack grows downward, we could save an insn by subtracting + SIZE from the stack pointer and then aligning the stack pointer. + The problem with this is that the stack pointer may be unaligned + between the execution of the subtraction and alignment insns and + some machines do not allow this. Even on those that do, some + signal handlers malfunction if a signal should occur between those + insns. Since this is an extremely rare event, we have no reliable + way of knowing which systems have this problem. So we avoid even + momentarily mis-aligning the stack. */ + +#ifdef STACK_BOUNDARY + /* If we added a variable amount to SIZE, + we can no longer assume it is aligned. */ +#if !defined (SETJMP_VIA_SAVE_AREA) && !defined (MUST_ALIGN) + if (known_align % STACK_BOUNDARY != 0) +#endif + size = round_push (size); +#endif + + do_pending_stack_adjust (); + + /* Don't use a TARGET that isn't a pseudo. */ + if (target == 0 || GET_CODE (target) != REG + || REGNO (target) < FIRST_PSEUDO_REGISTER) + target = gen_reg_rtx (Pmode); + + mark_reg_pointer (target); + +#ifndef STACK_GROWS_DOWNWARD + emit_move_insn (target, virtual_stack_dynamic_rtx); +#endif + + /* Perform the required allocation from the stack. Some systems do + this differently than simply incrementing/decrementing from the + stack pointer. */ +#ifdef HAVE_allocate_stack + if (HAVE_allocate_stack) + { + enum machine_mode mode + = insn_operand_mode[(int) CODE_FOR_allocate_stack][0]; + + if (insn_operand_predicate[(int) CODE_FOR_allocate_stack][0] + && ! ((*insn_operand_predicate[(int) CODE_FOR_allocate_stack][0]) + (size, mode))) + size = copy_to_mode_reg (mode, size); + + emit_insn (gen_allocate_stack (size)); + } + else +#endif + anti_adjust_stack (size); + +#ifdef STACK_GROWS_DOWNWARD + emit_move_insn (target, virtual_stack_dynamic_rtx); +#endif + +#ifdef MUST_ALIGN +#if 0 /* Even if we know the stack pointer has enough alignment, + there's no way to tell whether virtual_stack_dynamic_rtx shares that + alignment, so we still need to round the address up. */ + if (known_align % BIGGEST_ALIGNMENT != 0) +#endif + { + target = expand_divmod (0, CEIL_DIV_EXPR, Pmode, target, + GEN_INT (BIGGEST_ALIGNMENT / BITS_PER_UNIT), + NULL_RTX, 1); + + target = expand_mult (Pmode, target, + GEN_INT (BIGGEST_ALIGNMENT / BITS_PER_UNIT), + NULL_RTX, 1); + } +#endif + + /* Some systems require a particular insn to refer to the stack + to make the pages exist. */ +#ifdef HAVE_probe + if (HAVE_probe) + emit_insn (gen_probe ()); +#endif + + return target; +} + +/* Return an rtx representing the register or memory location + in which a scalar value of data type VALTYPE + was returned by a function call to function FUNC. + FUNC is a FUNCTION_DECL node if the precise function is known, + otherwise 0. */ + +rtx +hard_function_value (valtype, func) + tree valtype; + tree func; +{ + return FUNCTION_VALUE (valtype, func); +} + +/* Return an rtx representing the register or memory location + in which a scalar value of mode MODE was returned by a library call. */ + +rtx +hard_libcall_value (mode) + enum machine_mode mode; +{ + return LIBCALL_VALUE (mode); +} + +/* Look up the tree code for a given rtx code + to provide the arithmetic operation for REAL_ARITHMETIC. + The function returns an int because the caller may not know + what `enum tree_code' means. */ + +int +rtx_to_tree_code (code) + enum rtx_code code; +{ + enum tree_code tcode; + + switch (code) + { + case PLUS: + tcode = PLUS_EXPR; + break; + case MINUS: + tcode = MINUS_EXPR; + break; + case MULT: + tcode = MULT_EXPR; + break; + case DIV: + tcode = RDIV_EXPR; + break; + case SMIN: + tcode = MIN_EXPR; + break; + case SMAX: + tcode = MAX_EXPR; + break; + default: + tcode = LAST_AND_UNUSED_TREE_CODE; + break; + } + return ((int) tcode); +} diff --git a/gnu/usr.bin/cc/lib/expmed.c b/gnu/usr.bin/cc/lib/expmed.c new file mode 100644 index 000000000000..727f888a5106 --- /dev/null +++ b/gnu/usr.bin/cc/lib/expmed.c @@ -0,0 +1,3160 @@ +/* Medium-level subroutines: convert bit-field store and extract + and shifts, multiplies and divides to rtl instructions. + Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include "rtl.h" +#include "tree.h" +#include "flags.h" +#include "insn-flags.h" +#include "insn-codes.h" +#include "insn-config.h" +#include "expr.h" +#include "real.h" +#include "recog.h" + +static rtx extract_split_bit_field (); +static rtx extract_fixed_bit_field (); +static void store_split_bit_field (); +static void store_fixed_bit_field (); +static rtx mask_rtx (); +static rtx lshift_value (); + +#define CEIL(x,y) (((x) + (y) - 1) / (y)) + +/* Non-zero means multiply instructions are cheaper than shifts. */ +int mult_is_very_cheap; + +/* Non-zero means divides or modulus operations are relatively cheap for + powers of two, so don't use branches; emit the operation instead. + Usually, this will mean that the MD file will emit non-branch + sequences. */ + +static int sdiv_pow2_cheap, smod_pow2_cheap; + +/* For compilers that support multiple targets with different word sizes, + MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example + is the H8/300(H) compiler. */ + +#ifndef MAX_BITS_PER_WORD +#define MAX_BITS_PER_WORD BITS_PER_WORD +#endif + +/* Cost of various pieces of RTL. */ +static int add_cost, mult_cost, negate_cost, zero_cost; +static int shift_cost[MAX_BITS_PER_WORD]; +static int shiftadd_cost[MAX_BITS_PER_WORD]; +static int shiftsub_cost[MAX_BITS_PER_WORD]; + +void +init_expmed () +{ + char *free_point; + /* This is "some random pseudo register" for purposes of calling recog + to see what insns exist. */ + rtx reg = gen_rtx (REG, word_mode, FIRST_PSEUDO_REGISTER); + rtx shift_insn, shiftadd_insn, shiftsub_insn; + int dummy; + int m; + + start_sequence (); + + /* Since we are on the permanent obstack, we must be sure we save this + spot AFTER we call start_sequence, since it will reuse the rtl it + makes. */ + + free_point = (char *) oballoc (0); + + zero_cost = rtx_cost (const0_rtx, 0); + add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET); + + shift_insn = emit_insn (gen_rtx (SET, VOIDmode, reg, + gen_rtx (ASHIFT, word_mode, reg, + const0_rtx))); + + shiftadd_insn = emit_insn (gen_rtx (SET, VOIDmode, reg, + gen_rtx (PLUS, word_mode, + gen_rtx (MULT, word_mode, + reg, const0_rtx), + reg))); + + shiftsub_insn = emit_insn (gen_rtx (SET, VOIDmode, reg, + gen_rtx (MINUS, word_mode, + gen_rtx (MULT, word_mode, + reg, const0_rtx), + reg))); + + init_recog (); + + shift_cost[0] = 0; + shiftadd_cost[0] = shiftsub_cost[0] = add_cost; + + for (m = 1; m < BITS_PER_WORD; m++) + { + shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000; + + XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m); + if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0) + shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET); + + XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1) + = GEN_INT ((HOST_WIDE_INT) 1 << m); + if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0) + shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET); + + XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1) + = GEN_INT ((HOST_WIDE_INT) 1 << m); + if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0) + shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET); + } + + mult_cost = rtx_cost (gen_rtx (MULT, word_mode, reg, reg), SET); + /* For gcc 2.4 keep MULT_COST small to avoid really slow searches + in synth_mult. */ + mult_cost = MIN (12 * add_cost, mult_cost); + negate_cost = rtx_cost (gen_rtx (NEG, word_mode, reg), SET); + + /* 999999 is chosen to avoid any plausible faster special case. */ + mult_is_very_cheap + = (rtx_cost (gen_rtx (MULT, word_mode, reg, GEN_INT (999999)), SET) + < rtx_cost (gen_rtx (ASHIFT, word_mode, reg, GEN_INT (7)), SET)); + + sdiv_pow2_cheap + = (rtx_cost (gen_rtx (DIV, word_mode, reg, GEN_INT (32)), SET) + <= 2 * add_cost); + smod_pow2_cheap + = (rtx_cost (gen_rtx (MOD, word_mode, reg, GEN_INT (32)), SET) + <= 2 * add_cost); + + /* Free the objects we just allocated. */ + end_sequence (); + obfree (free_point); +} + +/* Return an rtx representing minus the value of X. + MODE is the intended mode of the result, + useful if X is a CONST_INT. */ + +rtx +negate_rtx (mode, x) + enum machine_mode mode; + rtx x; +{ + if (GET_CODE (x) == CONST_INT) + { + HOST_WIDE_INT val = - INTVAL (x); + if (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT) + { + /* Sign extend the value from the bits that are significant. */ + if (val & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))) + val |= (HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (mode); + else + val &= ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1; + } + return GEN_INT (val); + } + else + return expand_unop (GET_MODE (x), neg_optab, x, NULL_RTX, 0); +} + +/* Generate code to store value from rtx VALUE + into a bit-field within structure STR_RTX + containing BITSIZE bits starting at bit BITNUM. + FIELDMODE is the machine-mode of the FIELD_DECL node for this field. + ALIGN is the alignment that STR_RTX is known to have, measured in bytes. + TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */ + +/* ??? Note that there are two different ideas here for how + to determine the size to count bits within, for a register. + One is BITS_PER_WORD, and the other is the size of operand 3 + of the insv pattern. (The latter assumes that an n-bit machine + will be able to insert bit fields up to n bits wide.) + It isn't certain that either of these is right. + extract_bit_field has the same quandary. */ + +rtx +store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size) + rtx str_rtx; + register int bitsize; + int bitnum; + enum machine_mode fieldmode; + rtx value; + int align; + int total_size; +{ + int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; + register int offset = bitnum / unit; + register int bitpos = bitnum % unit; + register rtx op0 = str_rtx; + + if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx)) + abort (); + + /* Discount the part of the structure before the desired byte. + We need to know how many bytes are safe to reference after it. */ + if (total_size >= 0) + total_size -= (bitpos / BIGGEST_ALIGNMENT + * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); + + while (GET_CODE (op0) == SUBREG) + { + /* The following line once was done only if WORDS_BIG_ENDIAN, + but I think that is a mistake. WORDS_BIG_ENDIAN is + meaningful at a much higher level; when structures are copied + between memory and regs, the higher-numbered regs + always get higher addresses. */ + offset += SUBREG_WORD (op0); + /* We used to adjust BITPOS here, but now we do the whole adjustment + right after the loop. */ + op0 = SUBREG_REG (op0); + } + +#if BYTES_BIG_ENDIAN + /* If OP0 is a register, BITPOS must count within a word. + But as we have it, it counts within whatever size OP0 now has. + On a bigendian machine, these are not the same, so convert. */ + if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0))) + bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); +#endif + + value = protect_from_queue (value, 0); + + if (flag_force_mem) + value = force_not_mem (value); + + /* Note that the adjustment of BITPOS above has no effect on whether + BITPOS is 0 in a REG bigger than a word. */ + if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD + && (! STRICT_ALIGNMENT || GET_CODE (op0) != MEM) + && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode)) + { + /* Storing in a full-word or multi-word field in a register + can be done with just SUBREG. */ + if (GET_MODE (op0) != fieldmode) + if (GET_CODE (op0) == REG) + op0 = gen_rtx (SUBREG, fieldmode, op0, offset); + else + op0 = change_address (op0, fieldmode, + plus_constant (XEXP (op0, 0), offset)); + emit_move_insn (op0, value); + return value; + } + + /* Storing an lsb-aligned field in a register + can be done with a movestrict instruction. */ + + if (GET_CODE (op0) != MEM +#if BYTES_BIG_ENDIAN + && bitpos + bitsize == unit +#else + && bitpos == 0 +#endif + && bitsize == GET_MODE_BITSIZE (fieldmode) + && (GET_MODE (op0) == fieldmode + || (movstrict_optab->handlers[(int) fieldmode].insn_code + != CODE_FOR_nothing))) + { + /* Get appropriate low part of the value being stored. */ + if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG) + value = gen_lowpart (fieldmode, value); + else if (!(GET_CODE (value) == SYMBOL_REF + || GET_CODE (value) == LABEL_REF + || GET_CODE (value) == CONST)) + value = convert_to_mode (fieldmode, value, 0); + + if (GET_MODE (op0) == fieldmode) + emit_move_insn (op0, value); + else + { + int icode = movstrict_optab->handlers[(int) fieldmode].insn_code; + if(! (*insn_operand_predicate[icode][1]) (value, fieldmode)) + value = copy_to_mode_reg (fieldmode, value); + emit_insn (GEN_FCN (icode) + (gen_rtx (SUBREG, fieldmode, op0, offset), value)); + } + return value; + } + + /* Handle fields bigger than a word. */ + + if (bitsize > BITS_PER_WORD) + { + /* Here we transfer the words of the field + in the order least significant first. + This is because the most significant word is the one which may + be less than full. */ + + int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; + int i; + + /* This is the mode we must force value to, so that there will be enough + subwords to extract. Note that fieldmode will often (always?) be + VOIDmode, because that is what store_field uses to indicate that this + is a bit field, but passing VOIDmode to operand_subword_force will + result in an abort. */ + fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0); + + for (i = 0; i < nwords; i++) + { + /* If I is 0, use the low-order word in both field and target; + if I is 1, use the next to lowest word; and so on. */ + int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); + int bit_offset = (WORDS_BIG_ENDIAN + ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0) + : i * BITS_PER_WORD); + store_bit_field (op0, MIN (BITS_PER_WORD, + bitsize - i * BITS_PER_WORD), + bitnum + bit_offset, word_mode, + operand_subword_force (value, wordnum, fieldmode), + align, total_size); + } + return value; + } + + /* From here on we can assume that the field to be stored in is + a full-word (whatever type that is), since it is shorter than a word. */ + + /* OFFSET is the number of words or bytes (UNIT says which) + from STR_RTX to the first word or byte containing part of the field. */ + + if (GET_CODE (op0) == REG) + { + if (offset != 0 + || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) + op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)), + op0, offset); + offset = 0; + } + else + { + op0 = protect_from_queue (op0, 1); + } + + /* Now OFFSET is nonzero only if OP0 is memory + and is therefore always measured in bytes. */ + +#ifdef HAVE_insv + if (HAVE_insv + && !(bitsize == 1 && GET_CODE (value) == CONST_INT) + /* Ensure insv's size is wide enough for this field. */ + && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3]) + >= bitsize)) + { + int xbitpos = bitpos; + rtx value1; + rtx xop0 = op0; + rtx last = get_last_insn (); + rtx pat; + enum machine_mode maxmode + = insn_operand_mode[(int) CODE_FOR_insv][3]; + + int save_volatile_ok = volatile_ok; + volatile_ok = 1; + + /* If this machine's insv can only insert into a register, or if we + are to force MEMs into a register, copy OP0 into a register and + save it back later. */ + if (GET_CODE (op0) == MEM + && (flag_force_mem + || ! ((*insn_operand_predicate[(int) CODE_FOR_insv][0]) + (op0, VOIDmode)))) + { + rtx tempreg; + enum machine_mode bestmode; + + /* Get the mode to use for inserting into this field. If OP0 is + BLKmode, get the smallest mode consistent with the alignment. If + OP0 is a non-BLKmode object that is no wider than MAXMODE, use its + mode. Otherwise, use the smallest mode containing the field. */ + + if (GET_MODE (op0) == BLKmode + || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode)) + bestmode + = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode, + MEM_VOLATILE_P (op0)); + else + bestmode = GET_MODE (op0); + + if (bestmode == VOIDmode) + goto insv_loses; + + /* Adjust address to point to the containing unit of that mode. */ + unit = GET_MODE_BITSIZE (bestmode); + /* Compute offset as multiple of this unit, counting in bytes. */ + offset = (bitnum / unit) * GET_MODE_SIZE (bestmode); + bitpos = bitnum % unit; + op0 = change_address (op0, bestmode, + plus_constant (XEXP (op0, 0), offset)); + + /* Fetch that unit, store the bitfield in it, then store the unit. */ + tempreg = copy_to_reg (op0); + store_bit_field (tempreg, bitsize, bitpos, fieldmode, value, + align, total_size); + emit_move_insn (op0, tempreg); + return value; + } + volatile_ok = save_volatile_ok; + + /* Add OFFSET into OP0's address. */ + if (GET_CODE (xop0) == MEM) + xop0 = change_address (xop0, byte_mode, + plus_constant (XEXP (xop0, 0), offset)); + + /* If xop0 is a register, we need it in MAXMODE + to make it acceptable to the format of insv. */ + if (GET_CODE (xop0) == SUBREG) + PUT_MODE (xop0, maxmode); + if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) + xop0 = gen_rtx (SUBREG, maxmode, xop0, 0); + + /* On big-endian machines, we count bits from the most significant. + If the bit field insn does not, we must invert. */ + +#if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN + xbitpos = unit - bitsize - xbitpos; +#endif + /* We have been counting XBITPOS within UNIT. + Count instead within the size of the register. */ +#if BITS_BIG_ENDIAN + if (GET_CODE (xop0) != MEM) + xbitpos += GET_MODE_BITSIZE (maxmode) - unit; +#endif + unit = GET_MODE_BITSIZE (maxmode); + + /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */ + value1 = value; + if (GET_MODE (value) != maxmode) + { + if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize) + { + /* Optimization: Don't bother really extending VALUE + if it has all the bits we will actually use. However, + if we must narrow it, be sure we do it correctly. */ + + if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode)) + { + /* Avoid making subreg of a subreg, or of a mem. */ + if (GET_CODE (value1) != REG) + value1 = copy_to_reg (value1); + value1 = gen_rtx (SUBREG, maxmode, value1, 0); + } + else + value1 = gen_lowpart (maxmode, value1); + } + else if (!CONSTANT_P (value)) + /* Parse phase is supposed to make VALUE's data type + match that of the component reference, which is a type + at least as wide as the field; so VALUE should have + a mode that corresponds to that type. */ + abort (); + } + + /* If this machine's insv insists on a register, + get VALUE1 into a register. */ + if (! ((*insn_operand_predicate[(int) CODE_FOR_insv][3]) + (value1, maxmode))) + value1 = force_reg (maxmode, value1); + + pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1); + if (pat) + emit_insn (pat); + else + { + delete_insns_since (last); + store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align); + } + } + else + insv_loses: +#endif + /* Insv is not available; store using shifts and boolean ops. */ + store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align); + return value; +} + +/* Use shifts and boolean operations to store VALUE + into a bit field of width BITSIZE + in a memory location specified by OP0 except offset by OFFSET bytes. + (OFFSET must be 0 if OP0 is a register.) + The field starts at position BITPOS within the byte. + (If OP0 is a register, it may be a full word or a narrower mode, + but BITPOS still counts within a full word, + which is significant on bigendian machines.) + STRUCT_ALIGN is the alignment the structure is known to have (in bytes). + + Note that protect_from_queue has already been done on OP0 and VALUE. */ + +static void +store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align) + register rtx op0; + register int offset, bitsize, bitpos; + register rtx value; + int struct_align; +{ + register enum machine_mode mode; + int total_bits = BITS_PER_WORD; + rtx subtarget, temp; + int all_zero = 0; + int all_one = 0; + + /* Add OFFSET to OP0's address (if it is in memory) + and if a single byte contains the whole bit field + change OP0 to a byte. */ + + /* There is a case not handled here: + a structure with a known alignment of just a halfword + and a field split across two aligned halfwords within the structure. + Or likewise a structure with a known alignment of just a byte + and a field split across two bytes. + Such cases are not supposed to be able to occur. */ + + if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) + { + if (offset != 0) + abort (); + /* Special treatment for a bit field split across two registers. */ + if (bitsize + bitpos > BITS_PER_WORD) + { + store_split_bit_field (op0, bitsize, bitpos, value, BITS_PER_WORD); + return; + } + } + else + { + /* Get the proper mode to use for this field. We want a mode that + includes the entire field. If such a mode would be larger than + a word, we won't be doing the extraction the normal way. */ + + mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, + struct_align * BITS_PER_UNIT, word_mode, + GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)); + + if (mode == VOIDmode) + { + /* The only way this should occur is if the field spans word + boundaries. */ + store_split_bit_field (op0, bitsize, bitpos + offset * BITS_PER_UNIT, + value, struct_align); + return; + } + + total_bits = GET_MODE_BITSIZE (mode); + + /* Get ref to an aligned byte, halfword, or word containing the field. + Adjust BITPOS to be position within a word, + and OFFSET to be the offset of that word. + Then alter OP0 to refer to that word. */ + bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; + offset -= (offset % (total_bits / BITS_PER_UNIT)); + op0 = change_address (op0, mode, + plus_constant (XEXP (op0, 0), offset)); + } + + mode = GET_MODE (op0); + + /* Now MODE is either some integral mode for a MEM as OP0, + or is a full-word for a REG as OP0. TOTAL_BITS corresponds. + The bit field is contained entirely within OP0. + BITPOS is the starting bit number within OP0. + (OP0's mode may actually be narrower than MODE.) */ + +#if BYTES_BIG_ENDIAN + /* BITPOS is the distance between our msb + and that of the containing datum. + Convert it to the distance from the lsb. */ + + bitpos = total_bits - bitsize - bitpos; +#endif + /* Now BITPOS is always the distance between our lsb + and that of OP0. */ + + /* Shift VALUE left by BITPOS bits. If VALUE is not constant, + we must first convert its mode to MODE. */ + + if (GET_CODE (value) == CONST_INT) + { + register HOST_WIDE_INT v = INTVAL (value); + + if (bitsize < HOST_BITS_PER_WIDE_INT) + v &= ((HOST_WIDE_INT) 1 << bitsize) - 1; + + if (v == 0) + all_zero = 1; + else if ((bitsize < HOST_BITS_PER_WIDE_INT + && v == ((HOST_WIDE_INT) 1 << bitsize) - 1) + || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1)) + all_one = 1; + + value = lshift_value (mode, value, bitpos, bitsize); + } + else + { + int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize + && bitpos + bitsize != GET_MODE_BITSIZE (mode)); + + if (GET_MODE (value) != mode) + { + /* If VALUE is a floating-point mode, access it as an integer + of the corresponding size, then convert it. This can occur on + a machine with 64 bit registers that uses SFmode for float. */ + if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT) + { + if (GET_CODE (value) != REG) + value = copy_to_reg (value); + value + = gen_rtx (SUBREG, word_mode, value, 0); + } + + if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG) + && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value))) + value = gen_lowpart (mode, value); + else + value = convert_to_mode (mode, value, 1); + } + + if (must_and) + value = expand_binop (mode, and_optab, value, + mask_rtx (mode, 0, bitsize, 0), + NULL_RTX, 1, OPTAB_LIB_WIDEN); + if (bitpos > 0) + value = expand_shift (LSHIFT_EXPR, mode, value, + build_int_2 (bitpos, 0), NULL_RTX, 1); + } + + /* Now clear the chosen bits in OP0, + except that if VALUE is -1 we need not bother. */ + + subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0; + + if (! all_one) + { + temp = expand_binop (mode, and_optab, op0, + mask_rtx (mode, bitpos, bitsize, 1), + subtarget, 1, OPTAB_LIB_WIDEN); + subtarget = temp; + } + else + temp = op0; + + /* Now logical-or VALUE into OP0, unless it is zero. */ + + if (! all_zero) + temp = expand_binop (mode, ior_optab, temp, value, + subtarget, 1, OPTAB_LIB_WIDEN); + if (op0 != temp) + emit_move_insn (op0, temp); +} + +/* Store a bit field that is split across two words. + + OP0 is the REG, SUBREG or MEM rtx for the first of the two words. + BITSIZE is the field width; BITPOS the position of its first bit + (within the word). + VALUE is the value to store. */ + +static void +store_split_bit_field (op0, bitsize, bitpos, value, align) + rtx op0; + int bitsize, bitpos; + rtx value; + int align; +{ + /* BITSIZE_1 is size of the part in the first word. */ + int bitsize_1 = BITS_PER_WORD - bitpos % BITS_PER_WORD; + /* BITSIZE_2 is size of the rest (in the following word). */ + int bitsize_2 = bitsize - bitsize_1; + rtx part1, part2; + int unit = GET_CODE (op0) == MEM ? BITS_PER_UNIT : BITS_PER_WORD; + int offset = bitpos / unit; + rtx word; + + /* The field must span exactly one word boundary. */ + if (bitpos / BITS_PER_WORD != (bitpos + bitsize - 1) / BITS_PER_WORD - 1) + abort (); + + if (GET_MODE (value) != VOIDmode) + value = convert_to_mode (word_mode, value, 1); + + if (GET_CODE (value) == CONST_DOUBLE + && (part1 = gen_lowpart_common (word_mode, value)) != 0) + value = part1; + + if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT) + value = copy_to_mode_reg (word_mode, value); + + /* Split the value into two parts: + PART1 gets that which goes in the first word; PART2 the other. */ +#if BYTES_BIG_ENDIAN + /* PART1 gets the more significant part. */ + if (GET_CODE (value) == CONST_INT) + { + part1 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value)) >> bitsize_2); + part2 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value)) + & (((HOST_WIDE_INT) 1 << bitsize_2) - 1)); + } + else + { + part1 = extract_fixed_bit_field (word_mode, value, 0, bitsize_1, + BITS_PER_WORD - bitsize, NULL_RTX, 1, + BITS_PER_WORD); + part2 = extract_fixed_bit_field (word_mode, value, 0, bitsize_2, + BITS_PER_WORD - bitsize_2, NULL_RTX, 1, + BITS_PER_WORD); + } +#else + /* PART1 gets the less significant part. */ + if (GET_CODE (value) == CONST_INT) + { + part1 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value)) + & (((HOST_WIDE_INT) 1 << bitsize_1) - 1)); + part2 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value)) >> bitsize_1); + } + else + { + part1 = extract_fixed_bit_field (word_mode, value, 0, bitsize_1, 0, + NULL_RTX, 1, BITS_PER_WORD); + part2 = extract_fixed_bit_field (word_mode, value, 0, bitsize_2, + bitsize_1, NULL_RTX, 1, BITS_PER_WORD); + } +#endif + + /* Store PART1 into the first word. If OP0 is a MEM, pass OP0 and the + offset computed above. Otherwise, get the proper word and pass an + offset of zero. */ + word = (GET_CODE (op0) == MEM ? op0 + : operand_subword (op0, offset, 1, GET_MODE (op0))); + if (word == 0) + abort (); + + store_fixed_bit_field (word, GET_CODE (op0) == MEM ? offset : 0, + bitsize_1, bitpos % unit, part1, align); + + /* Offset op0 by 1 word to get to the following one. */ + if (GET_CODE (op0) == SUBREG) + word = operand_subword (SUBREG_REG (op0), SUBREG_WORD (op0) + offset + 1, + 1, VOIDmode); + else if (GET_CODE (op0) == MEM) + word = op0; + else + word = operand_subword (op0, offset + 1, 1, GET_MODE (op0)); + + if (word == 0) + abort (); + + /* Store PART2 into the second word. */ + store_fixed_bit_field (word, + (GET_CODE (op0) == MEM + ? CEIL (offset + 1, UNITS_PER_WORD) * UNITS_PER_WORD + : 0), + bitsize_2, 0, part2, align); +} + +/* Generate code to extract a byte-field from STR_RTX + containing BITSIZE bits, starting at BITNUM, + and put it in TARGET if possible (if TARGET is nonzero). + Regardless of TARGET, we return the rtx for where the value is placed. + It may be a QUEUED. + + STR_RTX is the structure containing the byte (a REG or MEM). + UNSIGNEDP is nonzero if this is an unsigned bit field. + MODE is the natural mode of the field value once extracted. + TMODE is the mode the caller would like the value to have; + but the value may be returned with type MODE instead. + + ALIGN is the alignment that STR_RTX is known to have, measured in bytes. + TOTAL_SIZE is the size in bytes of the containing structure, + or -1 if varying. + + If a TARGET is specified and we can store in it at no extra cost, + we do so, and return TARGET. + Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred + if they are equally easy. */ + +rtx +extract_bit_field (str_rtx, bitsize, bitnum, unsignedp, + target, mode, tmode, align, total_size) + rtx str_rtx; + register int bitsize; + int bitnum; + int unsignedp; + rtx target; + enum machine_mode mode, tmode; + int align; + int total_size; +{ + int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; + register int offset = bitnum / unit; + register int bitpos = bitnum % unit; + register rtx op0 = str_rtx; + rtx spec_target = target; + rtx spec_target_subreg = 0; + + if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx)) + abort (); + + /* Discount the part of the structure before the desired byte. + We need to know how many bytes are safe to reference after it. */ + if (total_size >= 0) + total_size -= (bitpos / BIGGEST_ALIGNMENT + * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); + + if (tmode == VOIDmode) + tmode = mode; + while (GET_CODE (op0) == SUBREG) + { + offset += SUBREG_WORD (op0); + op0 = SUBREG_REG (op0); + } + +#if BYTES_BIG_ENDIAN + /* If OP0 is a register, BITPOS must count within a word. + But as we have it, it counts within whatever size OP0 now has. + On a bigendian machine, these are not the same, so convert. */ + if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0))) + bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); +#endif + + /* Extracting a full-word or multi-word value + from a structure in a register. + This can be done with just SUBREG. + So too extracting a subword value in + the least significant part of the register. */ + + if (GET_CODE (op0) == REG + && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode) + && bitpos % BITS_PER_WORD == 0) + || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode +#if BYTES_BIG_ENDIAN + && bitpos + bitsize == BITS_PER_WORD +#else + && bitpos == 0 +#endif + ))) + { + enum machine_mode mode1 + = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0); + + if (mode1 != GET_MODE (op0)) + op0 = gen_rtx (SUBREG, mode1, op0, offset); + + if (mode1 != mode) + return convert_to_mode (tmode, op0, unsignedp); + return op0; + } + + /* Handle fields bigger than a word. */ + + if (bitsize > BITS_PER_WORD) + { + /* Here we transfer the words of the field + in the order least significant first. + This is because the most significant word is the one which may + be less than full. */ + + int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; + int i; + + if (target == 0 || GET_CODE (target) != REG) + target = gen_reg_rtx (mode); + + for (i = 0; i < nwords; i++) + { + /* If I is 0, use the low-order word in both field and target; + if I is 1, use the next to lowest word; and so on. */ + int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); + int bit_offset = (WORDS_BIG_ENDIAN + ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD) + : i * BITS_PER_WORD); + rtx target_part = operand_subword (target, wordnum, 1, VOIDmode); + rtx result_part + = extract_bit_field (op0, MIN (BITS_PER_WORD, + bitsize - i * BITS_PER_WORD), + bitnum + bit_offset, + 1, target_part, mode, word_mode, + align, total_size); + + if (target_part == 0) + abort (); + + if (result_part != target_part) + emit_move_insn (target_part, result_part); + } + + return target; + } + + /* From here on we know the desired field is smaller than a word + so we can assume it is an integer. So we can safely extract it as one + size of integer, if necessary, and then truncate or extend + to the size that is wanted. */ + + /* OFFSET is the number of words or bytes (UNIT says which) + from STR_RTX to the first word or byte containing part of the field. */ + + if (GET_CODE (op0) == REG) + { + if (offset != 0 + || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) + op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)), + op0, offset); + offset = 0; + } + else + { + op0 = protect_from_queue (str_rtx, 1); + } + + /* Now OFFSET is nonzero only for memory operands. */ + + if (unsignedp) + { +#ifdef HAVE_extzv + if (HAVE_extzv + && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0]) + >= bitsize)) + { + int xbitpos = bitpos, xoffset = offset; + rtx bitsize_rtx, bitpos_rtx; + rtx last = get_last_insn(); + rtx xop0 = op0; + rtx xtarget = target; + rtx xspec_target = spec_target; + rtx xspec_target_subreg = spec_target_subreg; + rtx pat; + enum machine_mode maxmode + = insn_operand_mode[(int) CODE_FOR_extzv][0]; + + if (GET_CODE (xop0) == MEM) + { + int save_volatile_ok = volatile_ok; + volatile_ok = 1; + + /* Is the memory operand acceptable? */ + if (flag_force_mem + || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][1]) + (xop0, GET_MODE (xop0)))) + { + /* No, load into a reg and extract from there. */ + enum machine_mode bestmode; + + /* Get the mode to use for inserting into this field. If + OP0 is BLKmode, get the smallest mode consistent with the + alignment. If OP0 is a non-BLKmode object that is no + wider than MAXMODE, use its mode. Otherwise, use the + smallest mode containing the field. */ + + if (GET_MODE (xop0) == BLKmode + || (GET_MODE_SIZE (GET_MODE (op0)) + > GET_MODE_SIZE (maxmode))) + bestmode = get_best_mode (bitsize, bitnum, + align * BITS_PER_UNIT, maxmode, + MEM_VOLATILE_P (xop0)); + else + bestmode = GET_MODE (xop0); + + if (bestmode == VOIDmode) + goto extzv_loses; + + /* Compute offset as multiple of this unit, + counting in bytes. */ + unit = GET_MODE_BITSIZE (bestmode); + xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); + xbitpos = bitnum % unit; + xop0 = change_address (xop0, bestmode, + plus_constant (XEXP (xop0, 0), + xoffset)); + /* Fetch it to a register in that size. */ + xop0 = force_reg (bestmode, xop0); + + /* XBITPOS counts within UNIT, which is what is expected. */ + } + else + /* Get ref to first byte containing part of the field. */ + xop0 = change_address (xop0, byte_mode, + plus_constant (XEXP (xop0, 0), xoffset)); + + volatile_ok = save_volatile_ok; + } + + /* If op0 is a register, we need it in MAXMODE (which is usually + SImode). to make it acceptable to the format of extzv. */ + if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) + abort (); + if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) + xop0 = gen_rtx (SUBREG, maxmode, xop0, 0); + + /* On big-endian machines, we count bits from the most significant. + If the bit field insn does not, we must invert. */ +#if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN + xbitpos = unit - bitsize - xbitpos; +#endif + /* Now convert from counting within UNIT to counting in MAXMODE. */ +#if BITS_BIG_ENDIAN + if (GET_CODE (xop0) != MEM) + xbitpos += GET_MODE_BITSIZE (maxmode) - unit; +#endif + unit = GET_MODE_BITSIZE (maxmode); + + if (xtarget == 0 + || (flag_force_mem && GET_CODE (xtarget) == MEM)) + xtarget = xspec_target = gen_reg_rtx (tmode); + + if (GET_MODE (xtarget) != maxmode) + { + if (GET_CODE (xtarget) == REG) + { + int wider = (GET_MODE_SIZE (maxmode) + > GET_MODE_SIZE (GET_MODE (xtarget))); + xtarget = gen_lowpart (maxmode, xtarget); + if (wider) + xspec_target_subreg = xtarget; + } + else + xtarget = gen_reg_rtx (maxmode); + } + + /* If this machine's extzv insists on a register target, + make sure we have one. */ + if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0]) + (xtarget, maxmode))) + xtarget = gen_reg_rtx (maxmode); + + bitsize_rtx = GEN_INT (bitsize); + bitpos_rtx = GEN_INT (xbitpos); + + pat = gen_extzv (protect_from_queue (xtarget, 1), + xop0, bitsize_rtx, bitpos_rtx); + if (pat) + { + emit_insn (pat); + target = xtarget; + spec_target = xspec_target; + spec_target_subreg = xspec_target_subreg; + } + else + { + delete_insns_since (last); + target = extract_fixed_bit_field (tmode, op0, offset, bitsize, + bitpos, target, 1, align); + } + } + else + extzv_loses: +#endif + target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, + target, 1, align); + } + else + { +#ifdef HAVE_extv + if (HAVE_extv + && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0]) + >= bitsize)) + { + int xbitpos = bitpos, xoffset = offset; + rtx bitsize_rtx, bitpos_rtx; + rtx last = get_last_insn(); + rtx xop0 = op0, xtarget = target; + rtx xspec_target = spec_target; + rtx xspec_target_subreg = spec_target_subreg; + rtx pat; + enum machine_mode maxmode + = insn_operand_mode[(int) CODE_FOR_extv][0]; + + if (GET_CODE (xop0) == MEM) + { + /* Is the memory operand acceptable? */ + if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][1]) + (xop0, GET_MODE (xop0)))) + { + /* No, load into a reg and extract from there. */ + enum machine_mode bestmode; + + /* Get the mode to use for inserting into this field. If + OP0 is BLKmode, get the smallest mode consistent with the + alignment. If OP0 is a non-BLKmode object that is no + wider than MAXMODE, use its mode. Otherwise, use the + smallest mode containing the field. */ + + if (GET_MODE (xop0) == BLKmode + || (GET_MODE_SIZE (GET_MODE (op0)) + > GET_MODE_SIZE (maxmode))) + bestmode = get_best_mode (bitsize, bitnum, + align * BITS_PER_UNIT, maxmode, + MEM_VOLATILE_P (xop0)); + else + bestmode = GET_MODE (xop0); + + if (bestmode == VOIDmode) + goto extv_loses; + + /* Compute offset as multiple of this unit, + counting in bytes. */ + unit = GET_MODE_BITSIZE (bestmode); + xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); + xbitpos = bitnum % unit; + xop0 = change_address (xop0, bestmode, + plus_constant (XEXP (xop0, 0), + xoffset)); + /* Fetch it to a register in that size. */ + xop0 = force_reg (bestmode, xop0); + + /* XBITPOS counts within UNIT, which is what is expected. */ + } + else + /* Get ref to first byte containing part of the field. */ + xop0 = change_address (xop0, byte_mode, + plus_constant (XEXP (xop0, 0), xoffset)); + } + + /* If op0 is a register, we need it in MAXMODE (which is usually + SImode) to make it acceptable to the format of extv. */ + if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) + abort (); + if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) + xop0 = gen_rtx (SUBREG, maxmode, xop0, 0); + + /* On big-endian machines, we count bits from the most significant. + If the bit field insn does not, we must invert. */ +#if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN + xbitpos = unit - bitsize - xbitpos; +#endif + /* XBITPOS counts within a size of UNIT. + Adjust to count within a size of MAXMODE. */ +#if BITS_BIG_ENDIAN + if (GET_CODE (xop0) != MEM) + xbitpos += (GET_MODE_BITSIZE (maxmode) - unit); +#endif + unit = GET_MODE_BITSIZE (maxmode); + + if (xtarget == 0 + || (flag_force_mem && GET_CODE (xtarget) == MEM)) + xtarget = xspec_target = gen_reg_rtx (tmode); + + if (GET_MODE (xtarget) != maxmode) + { + if (GET_CODE (xtarget) == REG) + { + int wider = (GET_MODE_SIZE (maxmode) + > GET_MODE_SIZE (GET_MODE (xtarget))); + xtarget = gen_lowpart (maxmode, xtarget); + if (wider) + xspec_target_subreg = xtarget; + } + else + xtarget = gen_reg_rtx (maxmode); + } + + /* If this machine's extv insists on a register target, + make sure we have one. */ + if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][0]) + (xtarget, maxmode))) + xtarget = gen_reg_rtx (maxmode); + + bitsize_rtx = GEN_INT (bitsize); + bitpos_rtx = GEN_INT (xbitpos); + + pat = gen_extv (protect_from_queue (xtarget, 1), + xop0, bitsize_rtx, bitpos_rtx); + if (pat) + { + emit_insn (pat); + target = xtarget; + spec_target = xspec_target; + spec_target_subreg = xspec_target_subreg; + } + else + { + delete_insns_since (last); + target = extract_fixed_bit_field (tmode, op0, offset, bitsize, + bitpos, target, 0, align); + } + } + else + extv_loses: +#endif + target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, + target, 0, align); + } + if (target == spec_target) + return target; + if (target == spec_target_subreg) + return spec_target; + if (GET_MODE (target) != tmode && GET_MODE (target) != mode) + { + /* If the target mode is floating-point, first convert to the + integer mode of that size and then access it as a floating-point + value via a SUBREG. */ + if (GET_MODE_CLASS (tmode) == MODE_FLOAT) + { + target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode), + MODE_INT, 0), + target, unsignedp); + if (GET_CODE (target) != REG) + target = copy_to_reg (target); + return gen_rtx (SUBREG, tmode, target, 0); + } + else + return convert_to_mode (tmode, target, unsignedp); + } + return target; +} + +/* Extract a bit field using shifts and boolean operations + Returns an rtx to represent the value. + OP0 addresses a register (word) or memory (byte). + BITPOS says which bit within the word or byte the bit field starts in. + OFFSET says how many bytes farther the bit field starts; + it is 0 if OP0 is a register. + BITSIZE says how many bits long the bit field is. + (If OP0 is a register, it may be narrower than a full word, + but BITPOS still counts within a full word, + which is significant on bigendian machines.) + + UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value). + If TARGET is nonzero, attempts to store the value there + and return TARGET, but this is not guaranteed. + If TARGET is not used, create a pseudo-reg of mode TMODE for the value. + + ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */ + +static rtx +extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, + target, unsignedp, align) + enum machine_mode tmode; + register rtx op0, target; + register int offset, bitsize, bitpos; + int unsignedp; + int align; +{ + int total_bits = BITS_PER_WORD; + enum machine_mode mode; + + if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) + { + /* Special treatment for a bit field split across two registers. */ + if (bitsize + bitpos > BITS_PER_WORD) + return extract_split_bit_field (op0, bitsize, bitpos, + unsignedp, align); + } + else + { + /* Get the proper mode to use for this field. We want a mode that + includes the entire field. If such a mode would be larger than + a word, we won't be doing the extraction the normal way. */ + + mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, + align * BITS_PER_UNIT, word_mode, + GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)); + + if (mode == VOIDmode) + /* The only way this should occur is if the field spans word + boundaries. */ + return extract_split_bit_field (op0, bitsize, + bitpos + offset * BITS_PER_UNIT, + unsignedp, align); + + total_bits = GET_MODE_BITSIZE (mode); + + /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to + be be in the range 0 to total_bits-1, and put any excess bytes in + OFFSET. */ + if (bitpos >= total_bits) + { + offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT); + bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT) + * BITS_PER_UNIT); + } + + /* Get ref to an aligned byte, halfword, or word containing the field. + Adjust BITPOS to be position within a word, + and OFFSET to be the offset of that word. + Then alter OP0 to refer to that word. */ + bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; + offset -= (offset % (total_bits / BITS_PER_UNIT)); + op0 = change_address (op0, mode, + plus_constant (XEXP (op0, 0), offset)); + } + + mode = GET_MODE (op0); + +#if BYTES_BIG_ENDIAN + /* BITPOS is the distance between our msb and that of OP0. + Convert it to the distance from the lsb. */ + + bitpos = total_bits - bitsize - bitpos; +#endif + /* Now BITPOS is always the distance between the field's lsb and that of OP0. + We have reduced the big-endian case to the little-endian case. */ + + if (unsignedp) + { + if (bitpos) + { + /* If the field does not already start at the lsb, + shift it so it does. */ + tree amount = build_int_2 (bitpos, 0); + /* Maybe propagate the target for the shift. */ + /* But not if we will return it--could confuse integrate.c. */ + rtx subtarget = (target != 0 && GET_CODE (target) == REG + && !REG_FUNCTION_VALUE_P (target) + ? target : 0); + if (tmode != mode) subtarget = 0; + op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1); + } + /* Convert the value to the desired mode. */ + if (mode != tmode) + op0 = convert_to_mode (tmode, op0, 1); + + /* Unless the msb of the field used to be the msb when we shifted, + mask out the upper bits. */ + + if (GET_MODE_BITSIZE (mode) != bitpos + bitsize +#if 0 +#ifdef SLOW_ZERO_EXTEND + /* Always generate an `and' if + we just zero-extended op0 and SLOW_ZERO_EXTEND, since it + will combine fruitfully with the zero-extend. */ + || tmode != mode +#endif +#endif + ) + return expand_binop (GET_MODE (op0), and_optab, op0, + mask_rtx (GET_MODE (op0), 0, bitsize, 0), + target, 1, OPTAB_LIB_WIDEN); + return op0; + } + + /* To extract a signed bit-field, first shift its msb to the msb of the word, + then arithmetic-shift its lsb to the lsb of the word. */ + op0 = force_reg (mode, op0); + if (mode != tmode) + target = 0; + + /* Find the narrowest integer mode that contains the field. */ + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos) + { + op0 = convert_to_mode (mode, op0, 0); + break; + } + + if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos)) + { + tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0); + /* Maybe propagate the target for the shift. */ + /* But not if we will return the result--could confuse integrate.c. */ + rtx subtarget = (target != 0 && GET_CODE (target) == REG + && ! REG_FUNCTION_VALUE_P (target) + ? target : 0); + op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1); + } + + return expand_shift (RSHIFT_EXPR, mode, op0, + build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), + target, 0); +} + +/* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value + of mode MODE with BITSIZE ones followed by BITPOS zeros, or the + complement of that if COMPLEMENT. The mask is truncated if + necessary to the width of mode MODE. */ + +static rtx +mask_rtx (mode, bitpos, bitsize, complement) + enum machine_mode mode; + int bitpos, bitsize, complement; +{ + HOST_WIDE_INT masklow, maskhigh; + + if (bitpos < HOST_BITS_PER_WIDE_INT) + masklow = (HOST_WIDE_INT) -1 << bitpos; + else + masklow = 0; + + if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT) + masklow &= ((unsigned HOST_WIDE_INT) -1 + >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); + + if (bitpos <= HOST_BITS_PER_WIDE_INT) + maskhigh = -1; + else + maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT); + + if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT) + maskhigh &= ((unsigned HOST_WIDE_INT) -1 + >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); + else + maskhigh = 0; + + if (complement) + { + maskhigh = ~maskhigh; + masklow = ~masklow; + } + + return immed_double_const (masklow, maskhigh, mode); +} + +/* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value + VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */ + +static rtx +lshift_value (mode, value, bitpos, bitsize) + enum machine_mode mode; + rtx value; + int bitpos, bitsize; +{ + unsigned HOST_WIDE_INT v = INTVAL (value); + HOST_WIDE_INT low, high; + + if (bitsize < HOST_BITS_PER_WIDE_INT) + v &= ~((HOST_WIDE_INT) -1 << bitsize); + + if (bitpos < HOST_BITS_PER_WIDE_INT) + { + low = v << bitpos; + high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0); + } + else + { + low = 0; + high = v << (bitpos - HOST_BITS_PER_WIDE_INT); + } + + return immed_double_const (low, high, mode); +} + +/* Extract a bit field that is split across two words + and return an RTX for the result. + + OP0 is the REG, SUBREG or MEM rtx for the first of the two words. + BITSIZE is the field width; BITPOS, position of its first bit, in the word. + UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */ + +static rtx +extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align) + rtx op0; + int bitsize, bitpos, unsignedp, align; +{ + /* BITSIZE_1 is size of the part in the first word. */ + int bitsize_1 = BITS_PER_WORD - bitpos % BITS_PER_WORD; + /* BITSIZE_2 is size of the rest (in the following word). */ + int bitsize_2 = bitsize - bitsize_1; + rtx part1, part2, result; + int unit = GET_CODE (op0) == MEM ? BITS_PER_UNIT : BITS_PER_WORD; + int offset = bitpos / unit; + rtx word; + + /* The field must span exactly one word boundary. */ + if (bitpos / BITS_PER_WORD != (bitpos + bitsize - 1) / BITS_PER_WORD - 1) + abort (); + + /* Get the part of the bit field from the first word. If OP0 is a MEM, + pass OP0 and the offset computed above. Otherwise, get the proper + word and pass an offset of zero. */ + word = (GET_CODE (op0) == MEM ? op0 + : operand_subword_force (op0, offset, GET_MODE (op0))); + part1 = extract_fixed_bit_field (word_mode, word, + GET_CODE (op0) == MEM ? offset : 0, + bitsize_1, bitpos % unit, NULL_RTX, + 1, align); + + /* Offset op0 by 1 word to get to the following one. */ + if (GET_CODE (op0) == SUBREG) + word = operand_subword_force (SUBREG_REG (op0), + SUBREG_WORD (op0) + offset + 1, VOIDmode); + else if (GET_CODE (op0) == MEM) + word = op0; + else + word = operand_subword_force (op0, offset + 1, GET_MODE (op0)); + + /* Get the part of the bit field from the second word. */ + part2 = extract_fixed_bit_field (word_mode, word, + (GET_CODE (op0) == MEM + ? CEIL (offset + 1, UNITS_PER_WORD) * UNITS_PER_WORD + : 0), + bitsize_2, 0, NULL_RTX, 1, align); + + /* Shift the more significant part up to fit above the other part. */ +#if BYTES_BIG_ENDIAN + part1 = expand_shift (LSHIFT_EXPR, word_mode, part1, + build_int_2 (bitsize_2, 0), 0, 1); +#else + part2 = expand_shift (LSHIFT_EXPR, word_mode, part2, + build_int_2 (bitsize_1, 0), 0, 1); +#endif + + /* Combine the two parts with bitwise or. This works + because we extracted both parts as unsigned bit fields. */ + result = expand_binop (word_mode, ior_optab, part1, part2, NULL_RTX, 1, + OPTAB_LIB_WIDEN); + + /* Unsigned bit field: we are done. */ + if (unsignedp) + return result; + /* Signed bit field: sign-extend with two arithmetic shifts. */ + result = expand_shift (LSHIFT_EXPR, word_mode, result, + build_int_2 (BITS_PER_WORD - bitsize, 0), + NULL_RTX, 0); + return expand_shift (RSHIFT_EXPR, word_mode, result, + build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0); +} + +/* Add INC into TARGET. */ + +void +expand_inc (target, inc) + rtx target, inc; +{ + rtx value = expand_binop (GET_MODE (target), add_optab, + target, inc, + target, 0, OPTAB_LIB_WIDEN); + if (value != target) + emit_move_insn (target, value); +} + +/* Subtract DEC from TARGET. */ + +void +expand_dec (target, dec) + rtx target, dec; +{ + rtx value = expand_binop (GET_MODE (target), sub_optab, + target, dec, + target, 0, OPTAB_LIB_WIDEN); + if (value != target) + emit_move_insn (target, value); +} + +/* Output a shift instruction for expression code CODE, + with SHIFTED being the rtx for the value to shift, + and AMOUNT the tree for the amount to shift by. + Store the result in the rtx TARGET, if that is convenient. + If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic. + Return the rtx for where the value is. */ + +rtx +expand_shift (code, mode, shifted, amount, target, unsignedp) + enum tree_code code; + register enum machine_mode mode; + rtx shifted; + tree amount; + register rtx target; + int unsignedp; +{ + register rtx op1, temp = 0; + register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR); + register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR); + int try; + + /* Previously detected shift-counts computed by NEGATE_EXPR + and shifted in the other direction; but that does not work + on all machines. */ + + op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0); + + if (op1 == const0_rtx) + return shifted; + + for (try = 0; temp == 0 && try < 3; try++) + { + enum optab_methods methods; + + if (try == 0) + methods = OPTAB_DIRECT; + else if (try == 1) + methods = OPTAB_WIDEN; + else + methods = OPTAB_LIB_WIDEN; + + if (rotate) + { + /* Widening does not work for rotation. */ + if (methods == OPTAB_WIDEN) + continue; + else if (methods == OPTAB_LIB_WIDEN) + { + /* If we are rotating by a constant that is valid and + we have been unable to open-code this by a rotation, + do it as the IOR of two shifts. I.e., to rotate A + by N bits, compute (A << N) | ((unsigned) A >> (C - N)) + where C is the bitsize of A. + + It is theoretically possible that the target machine might + not be able to perform either shift and hence we would + be making two libcalls rather than just the one for the + shift (similarly if IOR could not be done). We will allow + this extremely unlikely lossage to avoid complicating the + code below. */ + + if (GET_CODE (op1) == CONST_INT && INTVAL (op1) > 0 + && INTVAL (op1) < GET_MODE_BITSIZE (mode)) + { + rtx subtarget = target == shifted ? 0 : target; + rtx temp1; + tree other_amount + = build_int_2 (GET_MODE_BITSIZE (mode) - INTVAL (op1), 0); + + shifted = force_reg (mode, shifted); + + temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR, + mode, shifted, amount, subtarget, 1); + temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR, + mode, shifted, other_amount, 0, 1); + return expand_binop (mode, ior_optab, temp, temp1, target, + unsignedp, methods); + } + else + methods = OPTAB_LIB; + } + + temp = expand_binop (mode, + left ? rotl_optab : rotr_optab, + shifted, op1, target, unsignedp, methods); + + /* If we don't have the rotate, but we are rotating by a constant + that is in range, try a rotate in the opposite direction. */ + + if (temp == 0 && GET_CODE (op1) == CONST_INT + && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode)) + temp = expand_binop (mode, + left ? rotr_optab : rotl_optab, + shifted, + GEN_INT (GET_MODE_BITSIZE (mode) + - INTVAL (op1)), + target, unsignedp, methods); + } + else if (unsignedp) + { + temp = expand_binop (mode, + left ? lshl_optab : lshr_optab, + shifted, op1, target, unsignedp, methods); + if (temp == 0 && left) + temp = expand_binop (mode, ashl_optab, + shifted, op1, target, unsignedp, methods); + } + + /* Do arithmetic shifts. + Also, if we are going to widen the operand, we can just as well + use an arithmetic right-shift instead of a logical one. */ + if (temp == 0 && ! rotate + && (! unsignedp || (! left && methods == OPTAB_WIDEN))) + { + enum optab_methods methods1 = methods; + + /* If trying to widen a log shift to an arithmetic shift, + don't accept an arithmetic shift of the same size. */ + if (unsignedp) + methods1 = OPTAB_MUST_WIDEN; + + /* Arithmetic shift */ + + temp = expand_binop (mode, + left ? ashl_optab : ashr_optab, + shifted, op1, target, unsignedp, methods1); + } + +#ifdef HAVE_extzv + /* We can do a logical (unsigned) right shift with a bit-field + extract insn. But first check if one of the above methods worked. */ + if (temp != 0) + return temp; + + if (unsignedp && code == RSHIFT_EXPR && ! BITS_BIG_ENDIAN && HAVE_extzv) + { + enum machine_mode output_mode + = insn_operand_mode[(int) CODE_FOR_extzv][0]; + + if ((methods == OPTAB_DIRECT && mode == output_mode) + || (methods == OPTAB_WIDEN + && GET_MODE_SIZE (mode) < GET_MODE_SIZE (output_mode))) + { + rtx shifted1 = convert_to_mode (output_mode, + protect_from_queue (shifted, 0), + 1); + enum machine_mode length_mode + = insn_operand_mode[(int) CODE_FOR_extzv][2]; + enum machine_mode pos_mode + = insn_operand_mode[(int) CODE_FOR_extzv][3]; + rtx target1 = 0; + rtx last = get_last_insn (); + rtx width; + rtx xop1 = op1; + rtx pat; + + if (target != 0) + target1 = protect_from_queue (target, 1); + + /* We define extract insns as having OUTPUT_MODE in a register + and the mode of operand 1 in memory. Since we want + OUTPUT_MODE, we will always force the operand into a + register. At some point we might want to support MEM + directly. */ + shifted1 = force_reg (output_mode, shifted1); + + /* If we don't have or cannot use a suggested target, + make a place for the result, in the proper mode. */ + if (methods == OPTAB_WIDEN || target1 == 0 + || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0]) + (target1, output_mode))) + target1 = gen_reg_rtx (output_mode); + + xop1 = protect_from_queue (xop1, 0); + xop1 = convert_to_mode (pos_mode, xop1, + TREE_UNSIGNED (TREE_TYPE (amount))); + + /* If this machine's extzv insists on a register for + operand 3 (position), arrange for that. */ + if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][3]) + (xop1, pos_mode))) + xop1 = force_reg (pos_mode, xop1); + + /* WIDTH gets the width of the bit field to extract: + wordsize minus # bits to shift by. */ + if (GET_CODE (xop1) == CONST_INT) + width = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (op1)); + else + { + /* Now get the width in the proper mode. */ + op1 = protect_from_queue (op1, 0); + width = convert_to_mode (length_mode, op1, + TREE_UNSIGNED (TREE_TYPE (amount))); + + width = expand_binop (length_mode, sub_optab, + GEN_INT (GET_MODE_BITSIZE (mode)), + width, NULL_RTX, 0, OPTAB_LIB_WIDEN); + } + + /* If this machine's extzv insists on a register for + operand 2 (length), arrange for that. */ + if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][2]) + (width, length_mode))) + width = force_reg (length_mode, width); + + /* Now extract with WIDTH, omitting OP1 least sig bits. */ + pat = gen_extzv (target1, shifted1, width, xop1); + if (pat) + { + emit_insn (pat); + temp = convert_to_mode (mode, target1, 1); + } + else + delete_insns_since (last); + } + + /* Can also do logical shift with signed bit-field extract + followed by inserting the bit-field at a different position. + That strategy is not yet implemented. */ + } +#endif /* HAVE_extzv */ + } + + if (temp == 0) + abort (); + return temp; +} + +enum alg_code { alg_zero, alg_m, alg_shift, + alg_add_t_m2, alg_sub_t_m2, + alg_add_factor, alg_sub_factor, + alg_add_t2_m, alg_sub_t2_m, + alg_add, alg_subtract, alg_factor, alg_shiftop }; + +/* This structure records a sequence of operations. + `ops' is the number of operations recorded. + `cost' is their total cost. + The operations are stored in `op' and the corresponding + logarithms of the integer coefficients in `log'. + + These are the operations: + alg_zero total := 0; + alg_m total := multiplicand; + alg_shift total := total * coeff + alg_add_t_m2 total := total + multiplicand * coeff; + alg_sub_t_m2 total := total - multiplicand * coeff; + alg_add_factor total := total * coeff + total; + alg_sub_factor total := total * coeff - total; + alg_add_t2_m total := total * coeff + multiplicand; + alg_sub_t2_m total := total * coeff - multiplicand; + + The first operand must be either alg_zero or alg_m. */ + +struct algorithm +{ + short cost; + short ops; + /* The size of the OP and LOG fields are not directly related to the + word size, but the worst-case algorithms will be if we have few + consecutive ones or zeros, i.e., a multiplicand like 10101010101... + In that case we will generate shift-by-2, add, shift-by-2, add,..., + in total wordsize operations. */ + enum alg_code op[MAX_BITS_PER_WORD]; + char log[MAX_BITS_PER_WORD]; +}; + +/* Compute and return the best algorithm for multiplying by T. + The algorithm must cost less than cost_limit + If retval.cost >= COST_LIMIT, no algorithm was found and all + other field of the returned struct are undefined. */ + +static struct algorithm +synth_mult (t, cost_limit) + unsigned HOST_WIDE_INT t; + int cost_limit; +{ + int m; + struct algorithm *best_alg + = (struct algorithm *)alloca (sizeof (struct algorithm)); + struct algorithm *alg_in + = (struct algorithm *)alloca (sizeof (struct algorithm)); + unsigned int cost; + unsigned HOST_WIDE_INT q; + + /* Indicate that no algorithm is yet found. If no algorithm + is found, this value will be returned and indicate failure. */ + best_alg->cost = cost_limit; + + if (cost_limit <= 0) + return *best_alg; + + /* t == 1 can be done in zero cost. */ + if (t == 1) + { + best_alg->ops = 1; + best_alg->cost = 0; + best_alg->op[0] = alg_m; + return *best_alg; + } + + /* t == 0 sometimes has a cost. If it does and it exceeds our limit, + fail now. */ + + else if (t == 0) + { + if (zero_cost >= cost_limit) + return *best_alg; + else + { + best_alg->ops = 1; + best_alg->cost = zero_cost; + best_alg->op[0] = alg_zero; + return *best_alg; + } + } + + /* If we have a group of zero bits at the low-order part of T, try + multiplying by the remaining bits and then doing a shift. */ + + if ((t & 1) == 0) + { + m = floor_log2 (t & -t); /* m = number of low zero bits */ + q = t >> m; + cost = shift_cost[m]; + if (cost < cost_limit) + { + *alg_in = synth_mult (q, cost_limit - cost); + + cost += alg_in->cost; + if (cost < best_alg->cost) + { + struct algorithm *x; + x = alg_in, alg_in = best_alg, best_alg = x; + best_alg->log[best_alg->ops] = m; + best_alg->op[best_alg->ops++] = alg_shift; + best_alg->cost = cost_limit = cost; + } + } + } + + /* If we have an odd number, add or subtract one. */ + if ((t & 1) != 0) + { + unsigned HOST_WIDE_INT w; + + for (w = 1; (w & t) != 0; w <<= 1) + ; + if (w > 2 + /* Reject the case where t is 3. + Thus we prefer addition in that case. */ + && t != 3) + { + /* T ends with ...111. Multiply by (T + 1) and subtract 1. */ + + cost = add_cost; + *alg_in = synth_mult (t + 1, cost_limit - cost); + + cost += alg_in->cost; + if (cost < best_alg->cost) + { + struct algorithm *x; + x = alg_in, alg_in = best_alg, best_alg = x; + best_alg->log[best_alg->ops] = 0; + best_alg->op[best_alg->ops++] = alg_sub_t_m2; + best_alg->cost = cost_limit = cost; + } + } + else + { + /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */ + + cost = add_cost; + *alg_in = synth_mult (t - 1, cost_limit - cost); + + cost += alg_in->cost; + if (cost < best_alg->cost) + { + struct algorithm *x; + x = alg_in, alg_in = best_alg, best_alg = x; + best_alg->log[best_alg->ops] = 0; + best_alg->op[best_alg->ops++] = alg_add_t_m2; + best_alg->cost = cost_limit = cost; + } + } + } + + /* Look for factors of t of the form + t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)). + If we find such a factor, we can multiply by t using an algorithm that + multiplies by q, shift the result by m and add/subtract it to itself. + + We search for large factors first and loop down, even if large factors + are less probable than small; if we find a large factor we will find a + good sequence quickly, and therefore be able to prune (by decreasing + COST_LIMIT) the search. */ + + for (m = floor_log2 (t - 1); m >= 2; m--) + { + unsigned HOST_WIDE_INT d; + + d = ((unsigned HOST_WIDE_INT) 1 << m) + 1; + if (t % d == 0 && t > d) + { + cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]); + *alg_in = synth_mult (t / d, cost_limit - cost); + + cost += alg_in->cost; + if (cost < best_alg->cost) + { + struct algorithm *x; + x = alg_in, alg_in = best_alg, best_alg = x; + best_alg->log[best_alg->ops] = m; + best_alg->op[best_alg->ops++] = alg_add_factor; + best_alg->cost = cost_limit = cost; + } + } + + d = ((unsigned HOST_WIDE_INT) 1 << m) - 1; + if (t % d == 0 && t > d) + { + cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]); + *alg_in = synth_mult (t / d, cost_limit - cost); + + cost += alg_in->cost; + if (cost < best_alg->cost) + { + struct algorithm *x; + x = alg_in, alg_in = best_alg, best_alg = x; + best_alg->log[best_alg->ops] = m; + best_alg->op[best_alg->ops++] = alg_sub_factor; + best_alg->cost = cost_limit = cost; + } + } + } + + /* Try shift-and-add (load effective address) instructions, + i.e. do a*3, a*5, a*9. */ + if ((t & 1) != 0) + { + q = t - 1; + q = q & -q; + m = exact_log2 (q); + if (m >= 0) + { + cost = shiftadd_cost[m]; + *alg_in = synth_mult ((t - 1) >> m, cost_limit - cost); + + cost += alg_in->cost; + if (cost < best_alg->cost) + { + struct algorithm *x; + x = alg_in, alg_in = best_alg, best_alg = x; + best_alg->log[best_alg->ops] = m; + best_alg->op[best_alg->ops++] = alg_add_t2_m; + best_alg->cost = cost_limit = cost; + } + } + + q = t + 1; + q = q & -q; + m = exact_log2 (q); + if (m >= 0) + { + cost = shiftsub_cost[m]; + *alg_in = synth_mult ((t + 1) >> m, cost_limit - cost); + + cost += alg_in->cost; + if (cost < best_alg->cost) + { + struct algorithm *x; + x = alg_in, alg_in = best_alg, best_alg = x; + best_alg->log[best_alg->ops] = m; + best_alg->op[best_alg->ops++] = alg_sub_t2_m; + best_alg->cost = cost_limit = cost; + } + } + } + + /* If we are getting a too long sequence for `struct algorithm' + to record, store a fake cost to make this search fail. */ + if (best_alg->ops == MAX_BITS_PER_WORD) + best_alg->cost = cost_limit; + + return *best_alg; +} + +/* Perform a multiplication and return an rtx for the result. + MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); + TARGET is a suggestion for where to store the result (an rtx). + + We check specially for a constant integer as OP1. + If you want this check for OP0 as well, then before calling + you should swap the two operands if OP0 would be constant. */ + +rtx +expand_mult (mode, op0, op1, target, unsignedp) + enum machine_mode mode; + register rtx op0, op1, target; + int unsignedp; +{ + rtx const_op1 = op1; + + /* If we are multiplying in DImode, it may still be a win + to try to work with shifts and adds. */ + if (GET_CODE (op1) == CONST_DOUBLE + && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT + && HOST_BITS_PER_INT <= BITS_PER_WORD) + { + if ((CONST_DOUBLE_HIGH (op1) == 0 && CONST_DOUBLE_LOW (op1) >= 0) + || (CONST_DOUBLE_HIGH (op1) == -1 && CONST_DOUBLE_LOW (op1) < 0)) + const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1)); + } + + /* We used to test optimize here, on the grounds that it's better to + produce a smaller program when -O is not used. + But this causes such a terrible slowdown sometimes + that it seems better to use synth_mult always. */ + + if (GET_CODE (const_op1) == CONST_INT && ! mult_is_very_cheap) + { + struct algorithm alg; + struct algorithm neg_alg; + int negate = 0; + HOST_WIDE_INT val = INTVAL (op1); + HOST_WIDE_INT val_so_far; + rtx insn; + + /* Try to do the computation two ways: multiply by the negative of OP1 + and then negate, or do the multiplication directly. The latter is + usually faster for positive numbers and the former for negative + numbers, but the opposite can be faster if the original value + has a factor of 2**m +/- 1, while the negated value does not or + vice versa. */ + + alg = synth_mult (val, mult_cost); + neg_alg = synth_mult (- val, + (alg.cost < mult_cost ? alg.cost : mult_cost) + - negate_cost); + + if (neg_alg.cost + negate_cost < alg.cost) + alg = neg_alg, negate = 1; + + if (alg.cost < mult_cost) + { + /* We found something cheaper than a multiply insn. */ + int opno; + rtx accum, tem; + + op0 = protect_from_queue (op0, 0); + + /* Avoid referencing memory over and over. + For speed, but also for correctness when mem is volatile. */ + if (GET_CODE (op0) == MEM) + op0 = force_reg (mode, op0); + + /* ACCUM starts out either as OP0 or as a zero, depending on + the first operation. */ + + if (alg.op[0] == alg_zero) + { + accum = copy_to_mode_reg (mode, const0_rtx); + val_so_far = 0; + } + else if (alg.op[0] == alg_m) + { + accum = copy_to_mode_reg (mode, op0); + val_so_far = 1; + } + else + abort (); + + for (opno = 1; opno < alg.ops; opno++) + { + int log = alg.log[opno]; + rtx shift_subtarget = preserve_subexpressions_p () ? 0 : accum; + rtx add_target = opno == alg.ops - 1 && target != 0 ? target : 0; + + switch (alg.op[opno]) + { + case alg_shift: + accum = expand_shift (LSHIFT_EXPR, mode, accum, + build_int_2 (log, 0), NULL_RTX, 0); + val_so_far <<= log; + break; + + case alg_add_t_m2: + tem = expand_shift (LSHIFT_EXPR, mode, op0, + build_int_2 (log, 0), NULL_RTX, 0); + accum = force_operand (gen_rtx (PLUS, mode, accum, tem), + add_target ? add_target : accum); + val_so_far += (HOST_WIDE_INT) 1 << log; + break; + + case alg_sub_t_m2: + tem = expand_shift (LSHIFT_EXPR, mode, op0, + build_int_2 (log, 0), NULL_RTX, 0); + accum = force_operand (gen_rtx (MINUS, mode, accum, tem), + add_target ? add_target : accum); + val_so_far -= (HOST_WIDE_INT) 1 << log; + break; + + case alg_add_t2_m: + accum = expand_shift (LSHIFT_EXPR, mode, accum, + build_int_2 (log, 0), accum, 0); + accum = force_operand (gen_rtx (PLUS, mode, accum, op0), + add_target ? add_target : accum); + val_so_far = (val_so_far << log) + 1; + break; + + case alg_sub_t2_m: + accum = expand_shift (LSHIFT_EXPR, mode, accum, + build_int_2 (log, 0), accum, 0); + accum = force_operand (gen_rtx (MINUS, mode, accum, op0), + add_target ? add_target : accum); + val_so_far = (val_so_far << log) - 1; + break; + + case alg_add_factor: + tem = expand_shift (LSHIFT_EXPR, mode, accum, + build_int_2 (log, 0), NULL_RTX, 0); + accum = force_operand (gen_rtx (PLUS, mode, accum, tem), + add_target ? add_target : accum); + val_so_far += val_so_far << log; + break; + + case alg_sub_factor: + tem = expand_shift (LSHIFT_EXPR, mode, accum, + build_int_2 (log, 0), NULL_RTX, 0); + accum = force_operand (gen_rtx (MINUS, mode, tem, accum), + add_target ? add_target : tem); + val_so_far = (val_so_far << log) - val_so_far; + break; + + default: + abort ();; + } + + /* Write a REG_EQUAL note on the last insn so that we can cse + multiplication sequences. */ + + insn = get_last_insn (); + REG_NOTES (insn) + = gen_rtx (EXPR_LIST, REG_EQUAL, + gen_rtx (MULT, mode, op0, GEN_INT (val_so_far)), + REG_NOTES (insn)); + } + + if (negate) + { + val_so_far = - val_so_far; + accum = expand_unop (mode, neg_optab, accum, target, 0); + } + + if (val != val_so_far) + abort (); + + return accum; + } + } + + /* This used to use umul_optab if unsigned, + but for non-widening multiply there is no difference + between signed and unsigned. */ + op0 = expand_binop (mode, smul_optab, + op0, op1, target, unsignedp, OPTAB_LIB_WIDEN); + if (op0 == 0) + abort (); + return op0; +} + +/* Emit the code to divide OP0 by OP1, putting the result in TARGET + if that is convenient, and returning where the result is. + You may request either the quotient or the remainder as the result; + specify REM_FLAG nonzero to get the remainder. + + CODE is the expression code for which kind of division this is; + it controls how rounding is done. MODE is the machine mode to use. + UNSIGNEDP nonzero means do unsigned division. */ + +/* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI + and then correct it by or'ing in missing high bits + if result of ANDI is nonzero. + For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result. + This could optimize to a bfexts instruction. + But C doesn't use these operations, so their optimizations are + left for later. */ + +rtx +expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp) + int rem_flag; + enum tree_code code; + enum machine_mode mode; + register rtx op0, op1, target; + int unsignedp; +{ + register rtx result = 0; + enum machine_mode compute_mode; + int log = -1; + int size; + int can_clobber_op0; + int mod_insn_no_good = 0; + rtx adjusted_op0 = op0; + optab optab1, optab2; + + /* We shouldn't be called with op1 == const1_rtx, but some of the + code below will malfunction if we are, so check here and handle + the special case if so. */ + if (op1 == const1_rtx) + return rem_flag ? const0_rtx : op0; + + /* Don't use the function value register as a target + since we have to read it as well as write it, + and function-inlining gets confused by this. */ + if (target && REG_P (target) && REG_FUNCTION_VALUE_P (target)) + target = 0; + + /* Don't clobber an operand while doing a multi-step calculation. */ + if (target) + if ((rem_flag && (reg_mentioned_p (target, op0) + || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM))) + || reg_mentioned_p (target, op1) + || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM)) + target = 0; + + can_clobber_op0 = (GET_CODE (op0) == REG && op0 == target); + + if (GET_CODE (op1) == CONST_INT) + log = exact_log2 (INTVAL (op1)); + + /* If log is >= 0, we are dividing by 2**log, and will do it by shifting, + which is really floor-division. Otherwise we will really do a divide, + and we assume that is trunc-division. + + We must correct the dividend by adding or subtracting something + based on the divisor, in order to do the kind of rounding specified + by CODE. The correction depends on what kind of rounding is actually + available, and that depends on whether we will shift or divide. + + In many of these cases it is possible to perform the operation by a + clever series of logical operations (shifts and/or exclusive-ors). + Although avoiding the jump has the advantage that it extends the basic + block and allows further optimization, the branch-free code is normally + at least one instruction longer in the (most common) case where the + dividend is non-negative. Performance measurements of the two + alternatives show that the branch-free code is slightly faster on the + IBM ROMP but slower on CISC processors (significantly slower on the + VAX). Accordingly, the jump code has been retained. + + On machines where the jump code is slower, the cost of a DIV or MOD + operation can be set small (less than twice that of an addition); in + that case, we pretend that we don't have a power of two and perform + a normal division or modulus operation. */ + + if ((code == TRUNC_MOD_EXPR || code == TRUNC_DIV_EXPR) + && ! unsignedp + && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap)) + log = -1; + + /* Get the mode in which to perform this computation. Normally it will + be MODE, but sometimes we can't do the desired operation in MODE. + If so, pick a wider mode in which we can do the operation. Convert + to that mode at the start to avoid repeated conversions. + + First see what operations we need. These depend on the expression + we are evaluating. (We assume that divxx3 insns exist under the + same conditions that modxx3 insns and that these insns don't normally + fail. If these assumptions are not correct, we may generate less + efficient code in some cases.) + + Then see if we find a mode in which we can open-code that operation + (either a division, modulus, or shift). Finally, check for the smallest + mode for which we can do the operation with a library call. */ + + optab1 = (log >= 0 ? (unsignedp ? lshr_optab : ashr_optab) + : (unsignedp ? udiv_optab : sdiv_optab)); + optab2 = (log >= 0 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab)); + + for (compute_mode = mode; compute_mode != VOIDmode; + compute_mode = GET_MODE_WIDER_MODE (compute_mode)) + if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing + || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing) + break; + + if (compute_mode == VOIDmode) + for (compute_mode = mode; compute_mode != VOIDmode; + compute_mode = GET_MODE_WIDER_MODE (compute_mode)) + if (optab1->handlers[(int) compute_mode].libfunc + || optab2->handlers[(int) compute_mode].libfunc) + break; + + /* If we still couldn't find a mode, use MODE; we'll probably abort in + expand_binop. */ + if (compute_mode == VOIDmode) + compute_mode = mode; + + size = GET_MODE_BITSIZE (compute_mode); + + /* Now convert to the best mode to use. Show we made a copy of OP0 + and hence we can clobber it (we cannot use a SUBREG to widen + something. */ + if (compute_mode != mode) + { + adjusted_op0 = op0 = convert_to_mode (compute_mode, op0, unsignedp); + can_clobber_op0 = 1; + op1 = convert_to_mode (compute_mode, op1, unsignedp); + } + + /* If we are computing the remainder and one of the operands is a volatile + MEM, copy it into a register. */ + + if (rem_flag && GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)) + adjusted_op0 = op0 = force_reg (compute_mode, op0), can_clobber_op0 = 1; + if (rem_flag && GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1)) + op1 = force_reg (compute_mode, op1); + + /* If we are computing the remainder, op0 will be needed later to calculate + X - Y * (X / Y), therefore cannot be clobbered. */ + if (rem_flag) + can_clobber_op0 = 0; + + if (target == 0 || GET_MODE (target) != compute_mode) + target = gen_reg_rtx (compute_mode); + + switch (code) + { + case TRUNC_MOD_EXPR: + case TRUNC_DIV_EXPR: + if (log >= 0 && ! unsignedp) + { + /* Here we need to add OP1-1 if OP0 is negative, 0 otherwise. + This can be computed without jumps by arithmetically shifting + OP0 right LOG-1 places and then shifting right logically + SIZE-LOG bits. The resulting value is unconditionally added + to OP0. */ + if (log == 1 || BRANCH_COST >= 3) + { + rtx temp = gen_reg_rtx (compute_mode); + if (! can_clobber_op0) + /* Copy op0 to a reg, to play safe, + since this is done in the other path. */ + op0 = force_reg (compute_mode, op0); + temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode); + temp = expand_shift (RSHIFT_EXPR, compute_mode, temp, + build_int_2 (log - 1, 0), NULL_RTX, 0); + temp = expand_shift (RSHIFT_EXPR, compute_mode, temp, + build_int_2 (size - log, 0), + temp, 1); + /* We supply 0 as the target to make a new pseudo + for the value; that helps loop.c optimize the result. */ + adjusted_op0 = expand_binop (compute_mode, add_optab, + adjusted_op0, temp, + 0, 0, OPTAB_LIB_WIDEN); + } + else + { + rtx label = gen_label_rtx (); + if (! can_clobber_op0) + { + adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, + compute_mode); + /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue + which will screw up mem refs for autoincrements. */ + op0 = force_reg (compute_mode, op0); + } + emit_cmp_insn (adjusted_op0, const0_rtx, GE, + NULL_RTX, compute_mode, 0, 0); + emit_jump_insn (gen_bge (label)); + expand_inc (adjusted_op0, plus_constant (op1, -1)); + emit_label (label); + } + mod_insn_no_good = 1; + } + break; + + case FLOOR_DIV_EXPR: + case FLOOR_MOD_EXPR: + if (log < 0 && ! unsignedp) + { + rtx label = gen_label_rtx (); + if (! can_clobber_op0) + { + adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, + compute_mode); + /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue + which will screw up mem refs for autoincrements. */ + op0 = force_reg (compute_mode, op0); + } + emit_cmp_insn (adjusted_op0, const0_rtx, GE, + NULL_RTX, compute_mode, 0, 0); + emit_jump_insn (gen_bge (label)); + expand_dec (adjusted_op0, op1); + expand_inc (adjusted_op0, const1_rtx); + emit_label (label); + mod_insn_no_good = 1; + } + break; + + case CEIL_DIV_EXPR: + case CEIL_MOD_EXPR: + if (! can_clobber_op0) + { + adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, + compute_mode); + /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue + which will screw up mem refs for autoincrements. */ + op0 = force_reg (compute_mode, op0); + } + if (log < 0) + { + rtx label = 0; + if (! unsignedp) + { + label = gen_label_rtx (); + emit_cmp_insn (adjusted_op0, const0_rtx, LE, + NULL_RTX, compute_mode, 0, 0); + emit_jump_insn (gen_ble (label)); + } + expand_inc (adjusted_op0, op1); + expand_dec (adjusted_op0, const1_rtx); + if (! unsignedp) + emit_label (label); + } + else + { + adjusted_op0 = expand_binop (compute_mode, add_optab, + adjusted_op0, plus_constant (op1, -1), + NULL_RTX, 0, OPTAB_LIB_WIDEN); + } + mod_insn_no_good = 1; + break; + + case ROUND_DIV_EXPR: + case ROUND_MOD_EXPR: + if (! can_clobber_op0) + { + adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, + compute_mode); + /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue + which will screw up mem refs for autoincrements. */ + op0 = force_reg (compute_mode, op0); + } + if (log < 0) + { + op1 = expand_shift (RSHIFT_EXPR, compute_mode, op1, + integer_one_node, NULL_RTX, 0); + if (! unsignedp) + { + if (BRANCH_COST >= 2) + { + /* Negate OP1 if OP0 < 0. Do this by computing a temporary + that has all bits equal to the sign bit and exclusive + or-ing it with OP1. */ + rtx temp = gen_reg_rtx (compute_mode); + temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode); + temp = expand_shift (RSHIFT_EXPR, compute_mode, temp, + build_int_2 (size - 1, 0), + NULL_RTX, 0); + op1 = expand_binop (compute_mode, xor_optab, op1, temp, op1, + unsignedp, OPTAB_LIB_WIDEN); + } + else + { + rtx label = gen_label_rtx (); + emit_cmp_insn (adjusted_op0, const0_rtx, GE, NULL_RTX, + compute_mode, 0, 0); + emit_jump_insn (gen_bge (label)); + expand_unop (compute_mode, neg_optab, op1, op1, 0); + emit_label (label); + } + } + expand_inc (adjusted_op0, op1); + } + else + { + op1 = GEN_INT (((HOST_WIDE_INT) 1 << log) / 2); + expand_inc (adjusted_op0, op1); + } + mod_insn_no_good = 1; + break; + } + + if (rem_flag && !mod_insn_no_good) + { + /* Try to produce the remainder directly */ + if (log >= 0) + result = expand_binop (compute_mode, and_optab, adjusted_op0, + GEN_INT (((HOST_WIDE_INT) 1 << log) - 1), + target, 1, OPTAB_LIB_WIDEN); + else + { + /* See if we can do remainder without a library call. */ + result = sign_expand_binop (mode, umod_optab, smod_optab, + adjusted_op0, op1, target, + unsignedp, OPTAB_WIDEN); + if (result == 0) + { + /* No luck there. Can we do remainder and divide at once + without a library call? */ + result = gen_reg_rtx (compute_mode); + if (! expand_twoval_binop (unsignedp + ? udivmod_optab : sdivmod_optab, + adjusted_op0, op1, + NULL_RTX, result, unsignedp)) + result = 0; + } + } + } + + if (result) + return gen_lowpart (mode, result); + + /* Produce the quotient. */ + if (log >= 0) + result = expand_shift (RSHIFT_EXPR, compute_mode, adjusted_op0, + build_int_2 (log, 0), target, unsignedp); + else if (rem_flag && !mod_insn_no_good) + /* If producing quotient in order to subtract for remainder, + and a remainder subroutine would be ok, + don't use a divide subroutine. */ + result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, + adjusted_op0, op1, NULL_RTX, unsignedp, + OPTAB_WIDEN); + else + { + /* Try a quotient insn, but not a library call. */ + result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, + adjusted_op0, op1, + rem_flag ? NULL_RTX : target, + unsignedp, OPTAB_WIDEN); + if (result == 0) + { + /* No luck there. Try a quotient-and-remainder insn, + keeping the quotient alone. */ + result = gen_reg_rtx (mode); + if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab, + adjusted_op0, op1, + result, NULL_RTX, unsignedp)) + result = 0; + } + + /* If still no luck, use a library call. */ + if (result == 0) + result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, + adjusted_op0, op1, + rem_flag ? NULL_RTX : target, + unsignedp, OPTAB_LIB_WIDEN); + } + + /* If we really want the remainder, get it by subtraction. */ + if (rem_flag) + { + if (result == 0) + /* No divide instruction either. Use library for remainder. */ + result = sign_expand_binop (compute_mode, umod_optab, smod_optab, + op0, op1, target, + unsignedp, OPTAB_LIB_WIDEN); + else + { + /* We divided. Now finish doing X - Y * (X / Y). */ + result = expand_mult (compute_mode, result, op1, target, unsignedp); + if (! result) abort (); + result = expand_binop (compute_mode, sub_optab, op0, + result, target, unsignedp, OPTAB_LIB_WIDEN); + } + } + + if (result == 0) + abort (); + + return gen_lowpart (mode, result); +} + +/* Return a tree node with data type TYPE, describing the value of X. + Usually this is an RTL_EXPR, if there is no obvious better choice. + X may be an expression, however we only support those expressions + generated by loop.c. */ + +tree +make_tree (type, x) + tree type; + rtx x; +{ + tree t; + + switch (GET_CODE (x)) + { + case CONST_INT: + t = build_int_2 (INTVAL (x), + ! TREE_UNSIGNED (type) && INTVAL (x) >= 0 ? 0 : -1); + TREE_TYPE (t) = type; + return t; + + case CONST_DOUBLE: + if (GET_MODE (x) == VOIDmode) + { + t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x)); + TREE_TYPE (t) = type; + } + else + { + REAL_VALUE_TYPE d; + + REAL_VALUE_FROM_CONST_DOUBLE (d, x); + t = build_real (type, d); + } + + return t; + + case PLUS: + return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)), + make_tree (type, XEXP (x, 1)))); + + case MINUS: + return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)), + make_tree (type, XEXP (x, 1)))); + + case NEG: + return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0)))); + + case MULT: + return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)), + make_tree (type, XEXP (x, 1)))); + + case ASHIFT: + return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)), + make_tree (type, XEXP (x, 1)))); + + case LSHIFTRT: + return fold (convert (type, + build (RSHIFT_EXPR, unsigned_type (type), + make_tree (unsigned_type (type), + XEXP (x, 0)), + make_tree (type, XEXP (x, 1))))); + + case ASHIFTRT: + return fold (convert (type, + build (RSHIFT_EXPR, signed_type (type), + make_tree (signed_type (type), XEXP (x, 0)), + make_tree (type, XEXP (x, 1))))); + + case DIV: + if (TREE_CODE (type) != REAL_TYPE) + t = signed_type (type); + else + t = type; + + return fold (convert (type, + build (TRUNC_DIV_EXPR, t, + make_tree (t, XEXP (x, 0)), + make_tree (t, XEXP (x, 1))))); + case UDIV: + t = unsigned_type (type); + return fold (convert (type, + build (TRUNC_DIV_EXPR, t, + make_tree (t, XEXP (x, 0)), + make_tree (t, XEXP (x, 1))))); + default: + t = make_node (RTL_EXPR); + TREE_TYPE (t) = type; + RTL_EXPR_RTL (t) = x; + /* There are no insns to be output + when this rtl_expr is used. */ + RTL_EXPR_SEQUENCE (t) = 0; + return t; + } +} + +/* Return an rtx representing the value of X * MULT + ADD. + TARGET is a suggestion for where to store the result (an rtx). + MODE is the machine mode for the computation. + X and MULT must have mode MODE. ADD may have a different mode. + So can X (defaults to same as MODE). + UNSIGNEDP is non-zero to do unsigned multiplication. + This may emit insns. */ + +rtx +expand_mult_add (x, target, mult, add, mode, unsignedp) + rtx x, target, mult, add; + enum machine_mode mode; + int unsignedp; +{ + tree type = type_for_mode (mode, unsignedp); + tree add_type = (GET_MODE (add) == VOIDmode + ? type : type_for_mode (GET_MODE (add), unsignedp)); + tree result = fold (build (PLUS_EXPR, type, + fold (build (MULT_EXPR, type, + make_tree (type, x), + make_tree (type, mult))), + make_tree (add_type, add))); + + return expand_expr (result, target, VOIDmode, 0); +} + +/* Compute the logical-and of OP0 and OP1, storing it in TARGET + and returning TARGET. + + If TARGET is 0, a pseudo-register or constant is returned. */ + +rtx +expand_and (op0, op1, target) + rtx op0, op1, target; +{ + enum machine_mode mode = VOIDmode; + rtx tem; + + if (GET_MODE (op0) != VOIDmode) + mode = GET_MODE (op0); + else if (GET_MODE (op1) != VOIDmode) + mode = GET_MODE (op1); + + if (mode != VOIDmode) + tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN); + else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT) + tem = GEN_INT (INTVAL (op0) & INTVAL (op1)); + else + abort (); + + if (target == 0) + target = tem; + else if (tem != target) + emit_move_insn (target, tem); + return target; +} + +/* Emit a store-flags instruction for comparison CODE on OP0 and OP1 + and storing in TARGET. Normally return TARGET. + Return 0 if that cannot be done. + + MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If + it is VOIDmode, they cannot both be CONST_INT. + + UNSIGNEDP is for the case where we have to widen the operands + to perform the operation. It says to use zero-extension. + + NORMALIZEP is 1 if we should convert the result to be either zero + or one one. Normalize is -1 if we should convert the result to be + either zero or -1. If NORMALIZEP is zero, the result will be left + "raw" out of the scc insn. */ + +rtx +emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep) + rtx target; + enum rtx_code code; + rtx op0, op1; + enum machine_mode mode; + int unsignedp; + int normalizep; +{ + rtx subtarget; + enum insn_code icode; + enum machine_mode compare_mode; + enum machine_mode target_mode = GET_MODE (target); + rtx tem; + rtx last = 0; + rtx pattern, comparison; + + if (mode == VOIDmode) + mode = GET_MODE (op0); + + /* If one operand is constant, make it the second one. Only do this + if the other operand is not constant as well. */ + + if ((CONSTANT_P (op0) && ! CONSTANT_P (op1)) + || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT)) + { + tem = op0; + op0 = op1; + op1 = tem; + code = swap_condition (code); + } + + /* For some comparisons with 1 and -1, we can convert this to + comparisons with zero. This will often produce more opportunities for + store-flag insns. */ + + switch (code) + { + case LT: + if (op1 == const1_rtx) + op1 = const0_rtx, code = LE; + break; + case LE: + if (op1 == constm1_rtx) + op1 = const0_rtx, code = LT; + break; + case GE: + if (op1 == const1_rtx) + op1 = const0_rtx, code = GT; + break; + case GT: + if (op1 == constm1_rtx) + op1 = const0_rtx, code = GE; + break; + case GEU: + if (op1 == const1_rtx) + op1 = const0_rtx, code = NE; + break; + case LTU: + if (op1 == const1_rtx) + op1 = const0_rtx, code = EQ; + break; + } + + /* From now on, we won't change CODE, so set ICODE now. */ + icode = setcc_gen_code[(int) code]; + + /* If this is A < 0 or A >= 0, we can do this by taking the ones + complement of A (for GE) and shifting the sign bit to the low bit. */ + if (op1 == const0_rtx && (code == LT || code == GE) + && GET_MODE_CLASS (mode) == MODE_INT + && (normalizep || STORE_FLAG_VALUE == 1 + || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && (STORE_FLAG_VALUE + == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))))) + { + subtarget = target; + + /* If the result is to be wider than OP0, it is best to convert it + first. If it is to be narrower, it is *incorrect* to convert it + first. */ + if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode)) + { + op0 = protect_from_queue (op0, 0); + op0 = convert_to_mode (target_mode, op0, 0); + mode = target_mode; + } + + if (target_mode != mode) + subtarget = 0; + + if (code == GE) + op0 = expand_unop (mode, one_cmpl_optab, op0, subtarget, 0); + + if (normalizep || STORE_FLAG_VALUE == 1) + /* If we are supposed to produce a 0/1 value, we want to do + a logical shift from the sign bit to the low-order bit; for + a -1/0 value, we do an arithmetic shift. */ + op0 = expand_shift (RSHIFT_EXPR, mode, op0, + size_int (GET_MODE_BITSIZE (mode) - 1), + subtarget, normalizep != -1); + + if (mode != target_mode) + op0 = convert_to_mode (target_mode, op0, 0); + + return op0; + } + + if (icode != CODE_FOR_nothing) + { + /* We think we may be able to do this with a scc insn. Emit the + comparison and then the scc insn. + + compare_from_rtx may call emit_queue, which would be deleted below + if the scc insn fails. So call it ourselves before setting LAST. */ + + emit_queue (); + last = get_last_insn (); + + comparison + = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0); + if (GET_CODE (comparison) == CONST_INT) + return (comparison == const0_rtx ? const0_rtx + : normalizep == 1 ? const1_rtx + : normalizep == -1 ? constm1_rtx + : const_true_rtx); + + /* If the code of COMPARISON doesn't match CODE, something is + wrong; we can no longer be sure that we have the operation. + We could handle this case, but it should not happen. */ + + if (GET_CODE (comparison) != code) + abort (); + + /* Get a reference to the target in the proper mode for this insn. */ + compare_mode = insn_operand_mode[(int) icode][0]; + subtarget = target; + if (preserve_subexpressions_p () + || ! (*insn_operand_predicate[(int) icode][0]) (subtarget, compare_mode)) + subtarget = gen_reg_rtx (compare_mode); + + pattern = GEN_FCN (icode) (subtarget); + if (pattern) + { + emit_insn (pattern); + + /* If we are converting to a wider mode, first convert to + TARGET_MODE, then normalize. This produces better combining + opportunities on machines that have a SIGN_EXTRACT when we are + testing a single bit. This mostly benefits the 68k. + + If STORE_FLAG_VALUE does not have the sign bit set when + interpreted in COMPARE_MODE, we can do this conversion as + unsigned, which is usually more efficient. */ + if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode)) + { + convert_move (target, subtarget, + (GET_MODE_BITSIZE (compare_mode) + <= HOST_BITS_PER_WIDE_INT) + && 0 == (STORE_FLAG_VALUE + & ((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (compare_mode) -1)))); + op0 = target; + compare_mode = target_mode; + } + else + op0 = subtarget; + + /* If we want to keep subexpressions around, don't reuse our + last target. */ + + if (preserve_subexpressions_p ()) + subtarget = 0; + + /* Now normalize to the proper value in COMPARE_MODE. Sometimes + we don't have to do anything. */ + if (normalizep == 0 || normalizep == STORE_FLAG_VALUE) + ; + else if (normalizep == - STORE_FLAG_VALUE) + op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0); + + /* We don't want to use STORE_FLAG_VALUE < 0 below since this + makes it hard to use a value of just the sign bit due to + ANSI integer constant typing rules. */ + else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT + && (STORE_FLAG_VALUE + & ((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (compare_mode) - 1)))) + op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0, + size_int (GET_MODE_BITSIZE (compare_mode) - 1), + subtarget, normalizep == 1); + else if (STORE_FLAG_VALUE & 1) + { + op0 = expand_and (op0, const1_rtx, subtarget); + if (normalizep == -1) + op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0); + } + else + abort (); + + /* If we were converting to a smaller mode, do the + conversion now. */ + if (target_mode != compare_mode) + { + convert_move (target, op0, 0); + return target; + } + else + return op0; + } + } + + if (last) + delete_insns_since (last); + + subtarget = target_mode == mode ? target : 0; + + /* If we reached here, we can't do this with a scc insn. However, there + are some comparisons that can be done directly. For example, if + this is an equality comparison of integers, we can try to exclusive-or + (or subtract) the two operands and use a recursive call to try the + comparison with zero. Don't do any of these cases if branches are + very cheap. */ + + if (BRANCH_COST > 0 + && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE) + && op1 != const0_rtx) + { + tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1, + OPTAB_WIDEN); + + if (tem == 0) + tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1, + OPTAB_WIDEN); + if (tem != 0) + tem = emit_store_flag (target, code, tem, const0_rtx, + mode, unsignedp, normalizep); + if (tem == 0) + delete_insns_since (last); + return tem; + } + + /* Some other cases we can do are EQ, NE, LE, and GT comparisons with + the constant zero. Reject all other comparisons at this point. Only + do LE and GT if branches are expensive since they are expensive on + 2-operand machines. */ + + if (BRANCH_COST == 0 + || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx + || (code != EQ && code != NE + && (BRANCH_COST <= 1 || (code != LE && code != GT)))) + return 0; + + /* See what we need to return. We can only return a 1, -1, or the + sign bit. */ + + if (normalizep == 0) + { + if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) + normalizep = STORE_FLAG_VALUE; + + else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && (STORE_FLAG_VALUE + == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))) + ; + else + return 0; + } + + /* Try to put the result of the comparison in the sign bit. Assume we can't + do the necessary operation below. */ + + tem = 0; + + /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has + the sign bit set. */ + + if (code == LE) + { + /* This is destructive, so SUBTARGET can't be OP0. */ + if (rtx_equal_p (subtarget, op0)) + subtarget = 0; + + tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0, + OPTAB_WIDEN); + if (tem) + tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0, + OPTAB_WIDEN); + } + + /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the + number of bits in the mode of OP0, minus one. */ + + if (code == GT) + { + if (rtx_equal_p (subtarget, op0)) + subtarget = 0; + + tem = expand_shift (RSHIFT_EXPR, mode, op0, + size_int (GET_MODE_BITSIZE (mode) - 1), + subtarget, 0); + tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0, + OPTAB_WIDEN); + } + + if (code == EQ || code == NE) + { + /* For EQ or NE, one way to do the comparison is to apply an operation + that converts the operand into a positive number if it is non-zero + or zero if it was originally zero. Then, for EQ, we subtract 1 and + for NE we negate. This puts the result in the sign bit. Then we + normalize with a shift, if needed. + + Two operations that can do the above actions are ABS and FFS, so try + them. If that doesn't work, and MODE is smaller than a full word, + we can use zero-extension to the wider mode (an unsigned conversion) + as the operation. */ + + if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + tem = expand_unop (mode, abs_optab, op0, subtarget, 1); + else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + tem = expand_unop (mode, ffs_optab, op0, subtarget, 1); + else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) + { + mode = word_mode; + op0 = protect_from_queue (op0, 0); + tem = convert_to_mode (mode, op0, 1); + } + + if (tem != 0) + { + if (code == EQ) + tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget, + 0, OPTAB_WIDEN); + else + tem = expand_unop (mode, neg_optab, tem, subtarget, 0); + } + + /* If we couldn't do it that way, for NE we can "or" the two's complement + of the value with itself. For EQ, we take the one's complement of + that "or", which is an extra insn, so we only handle EQ if branches + are expensive. */ + + if (tem == 0 && (code == NE || BRANCH_COST > 1)) + { + if (rtx_equal_p (subtarget, op0)) + subtarget = 0; + + tem = expand_unop (mode, neg_optab, op0, subtarget, 0); + tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0, + OPTAB_WIDEN); + + if (tem && code == EQ) + tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0); + } + } + + if (tem && normalizep) + tem = expand_shift (RSHIFT_EXPR, mode, tem, + size_int (GET_MODE_BITSIZE (mode) - 1), + tem, normalizep == 1); + + if (tem && GET_MODE (tem) != target_mode) + { + convert_move (target, tem, 0); + tem = target; + } + + if (tem == 0) + delete_insns_since (last); + + return tem; +} diff --git a/gnu/usr.bin/cc/lib/expr.c b/gnu/usr.bin/cc/lib/expr.c new file mode 100644 index 000000000000..d866d3c98efa --- /dev/null +++ b/gnu/usr.bin/cc/lib/expr.c @@ -0,0 +1,7994 @@ +/* Convert tree expression to rtl instructions, for GNU compiler. + Copyright (C) 1988, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include "rtl.h" +#include "tree.h" +#include "flags.h" +#include "function.h" +#include "insn-flags.h" +#include "insn-codes.h" +#include "expr.h" +#include "insn-config.h" +#include "recog.h" +#include "output.h" +#include "typeclass.h" + +#define CEIL(x,y) (((x) + (y) - 1) / (y)) + +/* Decide whether a function's arguments should be processed + from first to last or from last to first. + + They should if the stack and args grow in opposite directions, but + only if we have push insns. */ + +#ifdef PUSH_ROUNDING + +#if defined (STACK_GROWS_DOWNWARD) != defined (ARGS_GROW_DOWNARD) +#define PUSH_ARGS_REVERSED /* If it's last to first */ +#endif + +#endif + +#ifndef STACK_PUSH_CODE +#ifdef STACK_GROWS_DOWNWARD +#define STACK_PUSH_CODE PRE_DEC +#else +#define STACK_PUSH_CODE PRE_INC +#endif +#endif + +/* Like STACK_BOUNDARY but in units of bytes, not bits. */ +#define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT) + +/* If this is nonzero, we do not bother generating VOLATILE + around volatile memory references, and we are willing to + output indirect addresses. If cse is to follow, we reject + indirect addresses so a useful potential cse is generated; + if it is used only once, instruction combination will produce + the same indirect address eventually. */ +int cse_not_expected; + +/* Nonzero to generate code for all the subroutines within an + expression before generating the upper levels of the expression. + Nowadays this is never zero. */ +int do_preexpand_calls = 1; + +/* Number of units that we should eventually pop off the stack. + These are the arguments to function calls that have already returned. */ +int pending_stack_adjust; + +/* Nonzero means stack pops must not be deferred, and deferred stack + pops must not be output. It is nonzero inside a function call, + inside a conditional expression, inside a statement expression, + and in other cases as well. */ +int inhibit_defer_pop; + +/* A list of all cleanups which belong to the arguments of + function calls being expanded by expand_call. */ +tree cleanups_this_call; + +/* Nonzero means __builtin_saveregs has already been done in this function. + The value is the pseudoreg containing the value __builtin_saveregs + returned. */ +static rtx saveregs_value; + +/* Similarly for __builtin_apply_args. */ +static rtx apply_args_value; + +/* This structure is used by move_by_pieces to describe the move to + be performed. */ + +struct move_by_pieces +{ + rtx to; + rtx to_addr; + int autinc_to; + int explicit_inc_to; + rtx from; + rtx from_addr; + int autinc_from; + int explicit_inc_from; + int len; + int offset; + int reverse; +}; + +static rtx enqueue_insn PROTO((rtx, rtx)); +static int queued_subexp_p PROTO((rtx)); +static void init_queue PROTO((void)); +static void move_by_pieces PROTO((rtx, rtx, int, int)); +static int move_by_pieces_ninsns PROTO((unsigned int, int)); +static void move_by_pieces_1 PROTO((rtx (*) (), enum machine_mode, + struct move_by_pieces *)); +static void group_insns PROTO((rtx)); +static void store_constructor PROTO((tree, rtx)); +static rtx store_field PROTO((rtx, int, int, enum machine_mode, tree, + enum machine_mode, int, int, int)); +static tree save_noncopied_parts PROTO((tree, tree)); +static tree init_noncopied_parts PROTO((tree, tree)); +static int safe_from_p PROTO((rtx, tree)); +static int fixed_type_p PROTO((tree)); +static int get_pointer_alignment PROTO((tree, unsigned)); +static tree string_constant PROTO((tree, tree *)); +static tree c_strlen PROTO((tree)); +static rtx expand_builtin PROTO((tree, rtx, rtx, enum machine_mode, int)); +static int apply_args_size PROTO((void)); +static int apply_result_size PROTO((void)); +static rtx result_vector PROTO((int, rtx)); +static rtx expand_builtin_apply_args PROTO((void)); +static rtx expand_builtin_apply PROTO((rtx, rtx, rtx)); +static void expand_builtin_return PROTO((rtx)); +static rtx expand_increment PROTO((tree, int)); +static void preexpand_calls PROTO((tree)); +static void do_jump_by_parts_greater PROTO((tree, int, rtx, rtx)); +static void do_jump_by_parts_greater_rtx PROTO((enum machine_mode, int, rtx, rtx, rtx, rtx)); +static void do_jump_by_parts_equality PROTO((tree, rtx, rtx)); +static void do_jump_by_parts_equality_rtx PROTO((rtx, rtx, rtx)); +static void do_jump_for_compare PROTO((rtx, rtx, rtx)); +static rtx compare PROTO((tree, enum rtx_code, enum rtx_code)); +static rtx do_store_flag PROTO((tree, rtx, enum machine_mode, int)); + +/* Record for each mode whether we can move a register directly to or + from an object of that mode in memory. If we can't, we won't try + to use that mode directly when accessing a field of that mode. */ + +static char direct_load[NUM_MACHINE_MODES]; +static char direct_store[NUM_MACHINE_MODES]; + +/* MOVE_RATIO is the number of move instructions that is better than + a block move. */ + +#ifndef MOVE_RATIO +#if defined (HAVE_movstrqi) || defined (HAVE_movstrhi) || defined (HAVE_movstrsi) || defined (HAVE_movstrdi) || defined (HAVE_movstrti) +#define MOVE_RATIO 2 +#else +/* A value of around 6 would minimize code size; infinity would minimize + execution time. */ +#define MOVE_RATIO 15 +#endif +#endif + +/* This array records the insn_code of insns to perform block moves. */ +enum insn_code movstr_optab[NUM_MACHINE_MODES]; + +/* SLOW_UNALIGNED_ACCESS is non-zero if unaligned accesses are very slow. */ + +#ifndef SLOW_UNALIGNED_ACCESS +#define SLOW_UNALIGNED_ACCESS 0 +#endif + +/* Register mappings for target machines without register windows. */ +#ifndef INCOMING_REGNO +#define INCOMING_REGNO(OUT) (OUT) +#endif +#ifndef OUTGOING_REGNO +#define OUTGOING_REGNO(IN) (IN) +#endif + +/* This is run once per compilation to set up which modes can be used + directly in memory and to initialize the block move optab. */ + +void +init_expr_once () +{ + rtx insn, pat; + enum machine_mode mode; + /* Try indexing by frame ptr and try by stack ptr. + It is known that on the Convex the stack ptr isn't a valid index. + With luck, one or the other is valid on any machine. */ + rtx mem = gen_rtx (MEM, VOIDmode, stack_pointer_rtx); + rtx mem1 = gen_rtx (MEM, VOIDmode, frame_pointer_rtx); + + start_sequence (); + insn = emit_insn (gen_rtx (SET, 0, 0)); + pat = PATTERN (insn); + + for (mode = VOIDmode; (int) mode < NUM_MACHINE_MODES; + mode = (enum machine_mode) ((int) mode + 1)) + { + int regno; + rtx reg; + int num_clobbers; + + direct_load[(int) mode] = direct_store[(int) mode] = 0; + PUT_MODE (mem, mode); + PUT_MODE (mem1, mode); + + /* See if there is some register that can be used in this mode and + directly loaded or stored from memory. */ + + if (mode != VOIDmode && mode != BLKmode) + for (regno = 0; regno < FIRST_PSEUDO_REGISTER + && (direct_load[(int) mode] == 0 || direct_store[(int) mode] == 0); + regno++) + { + if (! HARD_REGNO_MODE_OK (regno, mode)) + continue; + + reg = gen_rtx (REG, mode, regno); + + SET_SRC (pat) = mem; + SET_DEST (pat) = reg; + if (recog (pat, insn, &num_clobbers) >= 0) + direct_load[(int) mode] = 1; + + SET_SRC (pat) = mem1; + SET_DEST (pat) = reg; + if (recog (pat, insn, &num_clobbers) >= 0) + direct_load[(int) mode] = 1; + + SET_SRC (pat) = reg; + SET_DEST (pat) = mem; + if (recog (pat, insn, &num_clobbers) >= 0) + direct_store[(int) mode] = 1; + + SET_SRC (pat) = reg; + SET_DEST (pat) = mem1; + if (recog (pat, insn, &num_clobbers) >= 0) + direct_store[(int) mode] = 1; + } + } + + end_sequence (); +} + +/* This is run at the start of compiling a function. */ + +void +init_expr () +{ + init_queue (); + + pending_stack_adjust = 0; + inhibit_defer_pop = 0; + cleanups_this_call = 0; + saveregs_value = 0; + apply_args_value = 0; + forced_labels = 0; +} + +/* Save all variables describing the current status into the structure *P. + This is used before starting a nested function. */ + +void +save_expr_status (p) + struct function *p; +{ + /* Instead of saving the postincrement queue, empty it. */ + emit_queue (); + + p->pending_stack_adjust = pending_stack_adjust; + p->inhibit_defer_pop = inhibit_defer_pop; + p->cleanups_this_call = cleanups_this_call; + p->saveregs_value = saveregs_value; + p->apply_args_value = apply_args_value; + p->forced_labels = forced_labels; + + pending_stack_adjust = 0; + inhibit_defer_pop = 0; + cleanups_this_call = 0; + saveregs_value = 0; + apply_args_value = 0; + forced_labels = 0; +} + +/* Restore all variables describing the current status from the structure *P. + This is used after a nested function. */ + +void +restore_expr_status (p) + struct function *p; +{ + pending_stack_adjust = p->pending_stack_adjust; + inhibit_defer_pop = p->inhibit_defer_pop; + cleanups_this_call = p->cleanups_this_call; + saveregs_value = p->saveregs_value; + apply_args_value = p->apply_args_value; + forced_labels = p->forced_labels; +} + +/* Manage the queue of increment instructions to be output + for POSTINCREMENT_EXPR expressions, etc. */ + +static rtx pending_chain; + +/* Queue up to increment (or change) VAR later. BODY says how: + BODY should be the same thing you would pass to emit_insn + to increment right away. It will go to emit_insn later on. + + The value is a QUEUED expression to be used in place of VAR + where you want to guarantee the pre-incrementation value of VAR. */ + +static rtx +enqueue_insn (var, body) + rtx var, body; +{ + pending_chain = gen_rtx (QUEUED, GET_MODE (var), + var, NULL_RTX, NULL_RTX, body, pending_chain); + return pending_chain; +} + +/* Use protect_from_queue to convert a QUEUED expression + into something that you can put immediately into an instruction. + If the queued incrementation has not happened yet, + protect_from_queue returns the variable itself. + If the incrementation has happened, protect_from_queue returns a temp + that contains a copy of the old value of the variable. + + Any time an rtx which might possibly be a QUEUED is to be put + into an instruction, it must be passed through protect_from_queue first. + QUEUED expressions are not meaningful in instructions. + + Do not pass a value through protect_from_queue and then hold + on to it for a while before putting it in an instruction! + If the queue is flushed in between, incorrect code will result. */ + +rtx +protect_from_queue (x, modify) + register rtx x; + int modify; +{ + register RTX_CODE code = GET_CODE (x); + +#if 0 /* A QUEUED can hang around after the queue is forced out. */ + /* Shortcut for most common case. */ + if (pending_chain == 0) + return x; +#endif + + if (code != QUEUED) + { + /* A special hack for read access to (MEM (QUEUED ...)) + to facilitate use of autoincrement. + Make a copy of the contents of the memory location + rather than a copy of the address, but not + if the value is of mode BLKmode. */ + if (code == MEM && GET_MODE (x) != BLKmode + && GET_CODE (XEXP (x, 0)) == QUEUED && !modify) + { + register rtx y = XEXP (x, 0); + XEXP (x, 0) = QUEUED_VAR (y); + if (QUEUED_INSN (y)) + { + register rtx temp = gen_reg_rtx (GET_MODE (x)); + emit_insn_before (gen_move_insn (temp, x), + QUEUED_INSN (y)); + return temp; + } + return x; + } + /* Otherwise, recursively protect the subexpressions of all + the kinds of rtx's that can contain a QUEUED. */ + if (code == MEM) + XEXP (x, 0) = protect_from_queue (XEXP (x, 0), 0); + else if (code == PLUS || code == MULT) + { + XEXP (x, 0) = protect_from_queue (XEXP (x, 0), 0); + XEXP (x, 1) = protect_from_queue (XEXP (x, 1), 0); + } + return x; + } + /* If the increment has not happened, use the variable itself. */ + if (QUEUED_INSN (x) == 0) + return QUEUED_VAR (x); + /* If the increment has happened and a pre-increment copy exists, + use that copy. */ + if (QUEUED_COPY (x) != 0) + return QUEUED_COPY (x); + /* The increment has happened but we haven't set up a pre-increment copy. + Set one up now, and use it. */ + QUEUED_COPY (x) = gen_reg_rtx (GET_MODE (QUEUED_VAR (x))); + emit_insn_before (gen_move_insn (QUEUED_COPY (x), QUEUED_VAR (x)), + QUEUED_INSN (x)); + return QUEUED_COPY (x); +} + +/* Return nonzero if X contains a QUEUED expression: + if it contains anything that will be altered by a queued increment. + We handle only combinations of MEM, PLUS, MINUS and MULT operators + since memory addresses generally contain only those. */ + +static int +queued_subexp_p (x) + rtx x; +{ + register enum rtx_code code = GET_CODE (x); + switch (code) + { + case QUEUED: + return 1; + case MEM: + return queued_subexp_p (XEXP (x, 0)); + case MULT: + case PLUS: + case MINUS: + return queued_subexp_p (XEXP (x, 0)) + || queued_subexp_p (XEXP (x, 1)); + } + return 0; +} + +/* Perform all the pending incrementations. */ + +void +emit_queue () +{ + register rtx p; + while (p = pending_chain) + { + QUEUED_INSN (p) = emit_insn (QUEUED_BODY (p)); + pending_chain = QUEUED_NEXT (p); + } +} + +static void +init_queue () +{ + if (pending_chain) + abort (); +} + +/* Copy data from FROM to TO, where the machine modes are not the same. + Both modes may be integer, or both may be floating. + UNSIGNEDP should be nonzero if FROM is an unsigned type. + This causes zero-extension instead of sign-extension. */ + +void +convert_move (to, from, unsignedp) + register rtx to, from; + int unsignedp; +{ + enum machine_mode to_mode = GET_MODE (to); + enum machine_mode from_mode = GET_MODE (from); + int to_real = GET_MODE_CLASS (to_mode) == MODE_FLOAT; + int from_real = GET_MODE_CLASS (from_mode) == MODE_FLOAT; + enum insn_code code; + rtx libcall; + + /* rtx code for making an equivalent value. */ + enum rtx_code equiv_code = (unsignedp ? ZERO_EXTEND : SIGN_EXTEND); + + to = protect_from_queue (to, 1); + from = protect_from_queue (from, 0); + + if (to_real != from_real) + abort (); + + /* If FROM is a SUBREG that indicates that we have already done at least + the required extension, strip it. We don't handle such SUBREGs as + TO here. */ + + if (GET_CODE (from) == SUBREG && SUBREG_PROMOTED_VAR_P (from) + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (from))) + >= GET_MODE_SIZE (to_mode)) + && SUBREG_PROMOTED_UNSIGNED_P (from) == unsignedp) + from = gen_lowpart (to_mode, from), from_mode = to_mode; + + if (GET_CODE (to) == SUBREG && SUBREG_PROMOTED_VAR_P (to)) + abort (); + + if (to_mode == from_mode + || (from_mode == VOIDmode && CONSTANT_P (from))) + { + emit_move_insn (to, from); + return; + } + + if (to_real) + { +#ifdef HAVE_extendqfhf2 + if (HAVE_extendqfsf2 && from_mode == QFmode && to_mode == HFmode) + { + emit_unop_insn (CODE_FOR_extendqfsf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extendqfsf2 + if (HAVE_extendqfsf2 && from_mode == QFmode && to_mode == SFmode) + { + emit_unop_insn (CODE_FOR_extendqfsf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extendqfdf2 + if (HAVE_extendqfdf2 && from_mode == QFmode && to_mode == DFmode) + { + emit_unop_insn (CODE_FOR_extendqfdf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extendqfxf2 + if (HAVE_extendqfxf2 && from_mode == QFmode && to_mode == XFmode) + { + emit_unop_insn (CODE_FOR_extendqfxf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extendqftf2 + if (HAVE_extendqftf2 && from_mode == QFmode && to_mode == TFmode) + { + emit_unop_insn (CODE_FOR_extendqftf2, to, from, UNKNOWN); + return; + } +#endif + +#ifdef HAVE_extendhfsf2 + if (HAVE_extendhfsf2 && from_mode == HFmode && to_mode == SFmode) + { + emit_unop_insn (CODE_FOR_extendhfsf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extendhfdf2 + if (HAVE_extendhfdf2 && from_mode == HFmode && to_mode == DFmode) + { + emit_unop_insn (CODE_FOR_extendhfdf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extendhfxf2 + if (HAVE_extendhfxf2 && from_mode == HFmode && to_mode == XFmode) + { + emit_unop_insn (CODE_FOR_extendhfxf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extendhftf2 + if (HAVE_extendhftf2 && from_mode == HFmode && to_mode == TFmode) + { + emit_unop_insn (CODE_FOR_extendhftf2, to, from, UNKNOWN); + return; + } +#endif + +#ifdef HAVE_extendsfdf2 + if (HAVE_extendsfdf2 && from_mode == SFmode && to_mode == DFmode) + { + emit_unop_insn (CODE_FOR_extendsfdf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extendsfxf2 + if (HAVE_extendsfxf2 && from_mode == SFmode && to_mode == XFmode) + { + emit_unop_insn (CODE_FOR_extendsfxf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extendsftf2 + if (HAVE_extendsftf2 && from_mode == SFmode && to_mode == TFmode) + { + emit_unop_insn (CODE_FOR_extendsftf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extenddfxf2 + if (HAVE_extenddfxf2 && from_mode == DFmode && to_mode == XFmode) + { + emit_unop_insn (CODE_FOR_extenddfxf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_extenddftf2 + if (HAVE_extenddftf2 && from_mode == DFmode && to_mode == TFmode) + { + emit_unop_insn (CODE_FOR_extenddftf2, to, from, UNKNOWN); + return; + } +#endif + +#ifdef HAVE_trunchfqf2 + if (HAVE_trunchfqf2 && from_mode == HFmode && to_mode == QFmode) + { + emit_unop_insn (CODE_FOR_trunchfqf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_truncsfqf2 + if (HAVE_truncsfqf2 && from_mode == SFmode && to_mode == QFmode) + { + emit_unop_insn (CODE_FOR_truncsfqf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_truncdfqf2 + if (HAVE_truncdfqf2 && from_mode == DFmode && to_mode == QFmode) + { + emit_unop_insn (CODE_FOR_truncdfqf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_truncxfqf2 + if (HAVE_truncxfqf2 && from_mode == XFmode && to_mode == QFmode) + { + emit_unop_insn (CODE_FOR_truncxfqf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_trunctfqf2 + if (HAVE_trunctfqf2 && from_mode == TFmode && to_mode == QFmode) + { + emit_unop_insn (CODE_FOR_trunctfqf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_truncsfhf2 + if (HAVE_truncsfhf2 && from_mode == SFmode && to_mode == HFmode) + { + emit_unop_insn (CODE_FOR_truncsfhf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_truncdfhf2 + if (HAVE_truncdfhf2 && from_mode == DFmode && to_mode == HFmode) + { + emit_unop_insn (CODE_FOR_truncdfhf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_truncxfhf2 + if (HAVE_truncxfhf2 && from_mode == XFmode && to_mode == HFmode) + { + emit_unop_insn (CODE_FOR_truncxfhf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_trunctfhf2 + if (HAVE_trunctfhf2 && from_mode == TFmode && to_mode == HFmode) + { + emit_unop_insn (CODE_FOR_trunctfhf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_truncdfsf2 + if (HAVE_truncdfsf2 && from_mode == DFmode && to_mode == SFmode) + { + emit_unop_insn (CODE_FOR_truncdfsf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_truncxfsf2 + if (HAVE_truncxfsf2 && from_mode == XFmode && to_mode == SFmode) + { + emit_unop_insn (CODE_FOR_truncxfsf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_trunctfsf2 + if (HAVE_trunctfsf2 && from_mode == TFmode && to_mode == SFmode) + { + emit_unop_insn (CODE_FOR_trunctfsf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_truncxfdf2 + if (HAVE_truncxfdf2 && from_mode == XFmode && to_mode == DFmode) + { + emit_unop_insn (CODE_FOR_truncxfdf2, to, from, UNKNOWN); + return; + } +#endif +#ifdef HAVE_trunctfdf2 + if (HAVE_trunctfdf2 && from_mode == TFmode && to_mode == DFmode) + { + emit_unop_insn (CODE_FOR_trunctfdf2, to, from, UNKNOWN); + return; + } +#endif + + libcall = (rtx) 0; + switch (from_mode) + { + case SFmode: + switch (to_mode) + { + case DFmode: + libcall = extendsfdf2_libfunc; + break; + + case XFmode: + libcall = extendsfxf2_libfunc; + break; + + case TFmode: + libcall = extendsftf2_libfunc; + break; + } + break; + + case DFmode: + switch (to_mode) + { + case SFmode: + libcall = truncdfsf2_libfunc; + break; + + case XFmode: + libcall = extenddfxf2_libfunc; + break; + + case TFmode: + libcall = extenddftf2_libfunc; + break; + } + break; + + case XFmode: + switch (to_mode) + { + case SFmode: + libcall = truncxfsf2_libfunc; + break; + + case DFmode: + libcall = truncxfdf2_libfunc; + break; + } + break; + + case TFmode: + switch (to_mode) + { + case SFmode: + libcall = trunctfsf2_libfunc; + break; + + case DFmode: + libcall = trunctfdf2_libfunc; + break; + } + break; + } + + if (libcall == (rtx) 0) + /* This conversion is not implemented yet. */ + abort (); + + emit_library_call (libcall, 1, to_mode, 1, from, from_mode); + emit_move_insn (to, hard_libcall_value (to_mode)); + return; + } + + /* Now both modes are integers. */ + + /* Handle expanding beyond a word. */ + if (GET_MODE_BITSIZE (from_mode) < GET_MODE_BITSIZE (to_mode) + && GET_MODE_BITSIZE (to_mode) > BITS_PER_WORD) + { + rtx insns; + rtx lowpart; + rtx fill_value; + rtx lowfrom; + int i; + enum machine_mode lowpart_mode; + int nwords = CEIL (GET_MODE_SIZE (to_mode), UNITS_PER_WORD); + + /* Try converting directly if the insn is supported. */ + if ((code = can_extend_p (to_mode, from_mode, unsignedp)) + != CODE_FOR_nothing) + { + /* If FROM is a SUBREG, put it into a register. Do this + so that we always generate the same set of insns for + better cse'ing; if an intermediate assignment occurred, + we won't be doing the operation directly on the SUBREG. */ + if (optimize > 0 && GET_CODE (from) == SUBREG) + from = force_reg (from_mode, from); + emit_unop_insn (code, to, from, equiv_code); + return; + } + /* Next, try converting via full word. */ + else if (GET_MODE_BITSIZE (from_mode) < BITS_PER_WORD + && ((code = can_extend_p (to_mode, word_mode, unsignedp)) + != CODE_FOR_nothing)) + { + convert_move (gen_lowpart (word_mode, to), from, unsignedp); + emit_unop_insn (code, to, + gen_lowpart (word_mode, to), equiv_code); + return; + } + + /* No special multiword conversion insn; do it by hand. */ + start_sequence (); + + /* Get a copy of FROM widened to a word, if necessary. */ + if (GET_MODE_BITSIZE (from_mode) < BITS_PER_WORD) + lowpart_mode = word_mode; + else + lowpart_mode = from_mode; + + lowfrom = convert_to_mode (lowpart_mode, from, unsignedp); + + lowpart = gen_lowpart (lowpart_mode, to); + emit_move_insn (lowpart, lowfrom); + + /* Compute the value to put in each remaining word. */ + if (unsignedp) + fill_value = const0_rtx; + else + { +#ifdef HAVE_slt + if (HAVE_slt + && insn_operand_mode[(int) CODE_FOR_slt][0] == word_mode + && STORE_FLAG_VALUE == -1) + { + emit_cmp_insn (lowfrom, const0_rtx, NE, NULL_RTX, + lowpart_mode, 0, 0); + fill_value = gen_reg_rtx (word_mode); + emit_insn (gen_slt (fill_value)); + } + else +#endif + { + fill_value + = expand_shift (RSHIFT_EXPR, lowpart_mode, lowfrom, + size_int (GET_MODE_BITSIZE (lowpart_mode) - 1), + NULL_RTX, 0); + fill_value = convert_to_mode (word_mode, fill_value, 1); + } + } + + /* Fill the remaining words. */ + for (i = GET_MODE_SIZE (lowpart_mode) / UNITS_PER_WORD; i < nwords; i++) + { + int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); + rtx subword = operand_subword (to, index, 1, to_mode); + + if (subword == 0) + abort (); + + if (fill_value != subword) + emit_move_insn (subword, fill_value); + } + + insns = get_insns (); + end_sequence (); + + emit_no_conflict_block (insns, to, from, NULL_RTX, + gen_rtx (equiv_code, to_mode, copy_rtx (from))); + return; + } + + /* Truncating multi-word to a word or less. */ + if (GET_MODE_BITSIZE (from_mode) > BITS_PER_WORD + && GET_MODE_BITSIZE (to_mode) <= BITS_PER_WORD) + { + convert_move (to, gen_lowpart (word_mode, from), 0); + return; + } + + /* Handle pointer conversion */ /* SPEE 900220 */ + if (to_mode == PSImode) + { + if (from_mode != SImode) + from = convert_to_mode (SImode, from, unsignedp); + +#ifdef HAVE_truncsipsi + if (HAVE_truncsipsi) + { + emit_unop_insn (CODE_FOR_truncsipsi, to, from, UNKNOWN); + return; + } +#endif /* HAVE_truncsipsi */ + abort (); + } + + if (from_mode == PSImode) + { + if (to_mode != SImode) + { + from = convert_to_mode (SImode, from, unsignedp); + from_mode = SImode; + } + else + { +#ifdef HAVE_extendpsisi + if (HAVE_extendpsisi) + { + emit_unop_insn (CODE_FOR_extendpsisi, to, from, UNKNOWN); + return; + } +#endif /* HAVE_extendpsisi */ + abort (); + } + } + + /* Now follow all the conversions between integers + no more than a word long. */ + + /* For truncation, usually we can just refer to FROM in a narrower mode. */ + if (GET_MODE_BITSIZE (to_mode) < GET_MODE_BITSIZE (from_mode) + && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (to_mode), + GET_MODE_BITSIZE (from_mode))) + { + if (!((GET_CODE (from) == MEM + && ! MEM_VOLATILE_P (from) + && direct_load[(int) to_mode] + && ! mode_dependent_address_p (XEXP (from, 0))) + || GET_CODE (from) == REG + || GET_CODE (from) == SUBREG)) + from = force_reg (from_mode, from); + emit_move_insn (to, gen_lowpart (to_mode, from)); + return; + } + + /* Handle extension. */ + if (GET_MODE_BITSIZE (to_mode) > GET_MODE_BITSIZE (from_mode)) + { + /* Convert directly if that works. */ + if ((code = can_extend_p (to_mode, from_mode, unsignedp)) + != CODE_FOR_nothing) + { + /* If FROM is a SUBREG, put it into a register. Do this + so that we always generate the same set of insns for + better cse'ing; if an intermediate assignment occurred, + we won't be doing the operation directly on the SUBREG. */ + if (optimize > 0 && GET_CODE (from) == SUBREG) + from = force_reg (from_mode, from); + emit_unop_insn (code, to, from, equiv_code); + return; + } + else + { + enum machine_mode intermediate; + + /* Search for a mode to convert via. */ + for (intermediate = from_mode; intermediate != VOIDmode; + intermediate = GET_MODE_WIDER_MODE (intermediate)) + if ((can_extend_p (to_mode, intermediate, unsignedp) + != CODE_FOR_nothing) + && (can_extend_p (intermediate, from_mode, unsignedp) + != CODE_FOR_nothing)) + { + convert_move (to, convert_to_mode (intermediate, from, + unsignedp), unsignedp); + return; + } + + /* No suitable intermediate mode. */ + abort (); + } + } + + /* Support special truncate insns for certain modes. */ + + if (from_mode == DImode && to_mode == SImode) + { +#ifdef HAVE_truncdisi2 + if (HAVE_truncdisi2) + { + emit_unop_insn (CODE_FOR_truncdisi2, to, from, UNKNOWN); + return; + } +#endif + convert_move (to, force_reg (from_mode, from), unsignedp); + return; + } + + if (from_mode == DImode && to_mode == HImode) + { +#ifdef HAVE_truncdihi2 + if (HAVE_truncdihi2) + { + emit_unop_insn (CODE_FOR_truncdihi2, to, from, UNKNOWN); + return; + } +#endif + convert_move (to, force_reg (from_mode, from), unsignedp); + return; + } + + if (from_mode == DImode && to_mode == QImode) + { +#ifdef HAVE_truncdiqi2 + if (HAVE_truncdiqi2) + { + emit_unop_insn (CODE_FOR_truncdiqi2, to, from, UNKNOWN); + return; + } +#endif + convert_move (to, force_reg (from_mode, from), unsignedp); + return; + } + + if (from_mode == SImode && to_mode == HImode) + { +#ifdef HAVE_truncsihi2 + if (HAVE_truncsihi2) + { + emit_unop_insn (CODE_FOR_truncsihi2, to, from, UNKNOWN); + return; + } +#endif + convert_move (to, force_reg (from_mode, from), unsignedp); + return; + } + + if (from_mode == SImode && to_mode == QImode) + { +#ifdef HAVE_truncsiqi2 + if (HAVE_truncsiqi2) + { + emit_unop_insn (CODE_FOR_truncsiqi2, to, from, UNKNOWN); + return; + } +#endif + convert_move (to, force_reg (from_mode, from), unsignedp); + return; + } + + if (from_mode == HImode && to_mode == QImode) + { +#ifdef HAVE_trunchiqi2 + if (HAVE_trunchiqi2) + { + emit_unop_insn (CODE_FOR_trunchiqi2, to, from, UNKNOWN); + return; + } +#endif + convert_move (to, force_reg (from_mode, from), unsignedp); + return; + } + + /* Handle truncation of volatile memrefs, and so on; + the things that couldn't be truncated directly, + and for which there was no special instruction. */ + if (GET_MODE_BITSIZE (to_mode) < GET_MODE_BITSIZE (from_mode)) + { + rtx temp = force_reg (to_mode, gen_lowpart (to_mode, from)); + emit_move_insn (to, temp); + return; + } + + /* Mode combination is not recognized. */ + abort (); +} + +/* Return an rtx for a value that would result + from converting X to mode MODE. + Both X and MODE may be floating, or both integer. + UNSIGNEDP is nonzero if X is an unsigned value. + This can be done by referring to a part of X in place + or by copying to a new temporary with conversion. + + This function *must not* call protect_from_queue + except when putting X into an insn (in which case convert_move does it). */ + +rtx +convert_to_mode (mode, x, unsignedp) + enum machine_mode mode; + rtx x; + int unsignedp; +{ + register rtx temp; + + /* If FROM is a SUBREG that indicates that we have already done at least + the required extension, strip it. */ + + if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x) + && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) >= GET_MODE_SIZE (mode) + && SUBREG_PROMOTED_UNSIGNED_P (x) == unsignedp) + x = gen_lowpart (mode, x); + + if (mode == GET_MODE (x)) + return x; + + /* There is one case that we must handle specially: If we are converting + a CONST_INT into a mode whose size is twice HOST_BITS_PER_WIDE_INT and + we are to interpret the constant as unsigned, gen_lowpart will do + the wrong if the constant appears negative. What we want to do is + make the high-order word of the constant zero, not all ones. */ + + if (unsignedp && GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT + && GET_CODE (x) == CONST_INT && INTVAL (x) < 0) + return immed_double_const (INTVAL (x), (HOST_WIDE_INT) 0, mode); + + /* We can do this with a gen_lowpart if both desired and current modes + are integer, and this is either a constant integer, a register, or a + non-volatile MEM. Except for the constant case, we must be narrowing + the operand. */ + + if (GET_CODE (x) == CONST_INT + || (GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT + && (GET_CODE (x) == CONST_DOUBLE + || (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (x)) + && ((GET_CODE (x) == MEM && ! MEM_VOLATILE_P (x)) + && direct_load[(int) mode] + || GET_CODE (x) == REG))))) + return gen_lowpart (mode, x); + + temp = gen_reg_rtx (mode); + convert_move (temp, x, unsignedp); + return temp; +} + +/* Generate several move instructions to copy LEN bytes + from block FROM to block TO. (These are MEM rtx's with BLKmode). + The caller must pass FROM and TO + through protect_from_queue before calling. + ALIGN (in bytes) is maximum alignment we can assume. */ + +static void +move_by_pieces (to, from, len, align) + rtx to, from; + int len, align; +{ + struct move_by_pieces data; + rtx to_addr = XEXP (to, 0), from_addr = XEXP (from, 0); + int max_size = MOVE_MAX + 1; + + data.offset = 0; + data.to_addr = to_addr; + data.from_addr = from_addr; + data.to = to; + data.from = from; + data.autinc_to + = (GET_CODE (to_addr) == PRE_INC || GET_CODE (to_addr) == PRE_DEC + || GET_CODE (to_addr) == POST_INC || GET_CODE (to_addr) == POST_DEC); + data.autinc_from + = (GET_CODE (from_addr) == PRE_INC || GET_CODE (from_addr) == PRE_DEC + || GET_CODE (from_addr) == POST_INC + || GET_CODE (from_addr) == POST_DEC); + + data.explicit_inc_from = 0; + data.explicit_inc_to = 0; + data.reverse + = (GET_CODE (to_addr) == PRE_DEC || GET_CODE (to_addr) == POST_DEC); + if (data.reverse) data.offset = len; + data.len = len; + + /* If copying requires more than two move insns, + copy addresses to registers (to make displacements shorter) + and use post-increment if available. */ + if (!(data.autinc_from && data.autinc_to) + && move_by_pieces_ninsns (len, align) > 2) + { +#ifdef HAVE_PRE_DECREMENT + if (data.reverse && ! data.autinc_from) + { + data.from_addr = copy_addr_to_reg (plus_constant (from_addr, len)); + data.autinc_from = 1; + data.explicit_inc_from = -1; + } +#endif +#ifdef HAVE_POST_INCREMENT + if (! data.autinc_from) + { + data.from_addr = copy_addr_to_reg (from_addr); + data.autinc_from = 1; + data.explicit_inc_from = 1; + } +#endif + if (!data.autinc_from && CONSTANT_P (from_addr)) + data.from_addr = copy_addr_to_reg (from_addr); +#ifdef HAVE_PRE_DECREMENT + if (data.reverse && ! data.autinc_to) + { + data.to_addr = copy_addr_to_reg (plus_constant (to_addr, len)); + data.autinc_to = 1; + data.explicit_inc_to = -1; + } +#endif +#ifdef HAVE_POST_INCREMENT + if (! data.reverse && ! data.autinc_to) + { + data.to_addr = copy_addr_to_reg (to_addr); + data.autinc_to = 1; + data.explicit_inc_to = 1; + } +#endif + if (!data.autinc_to && CONSTANT_P (to_addr)) + data.to_addr = copy_addr_to_reg (to_addr); + } + + if (! (STRICT_ALIGNMENT || SLOW_UNALIGNED_ACCESS) + || align > MOVE_MAX || align >= BIGGEST_ALIGNMENT / BITS_PER_UNIT) + align = MOVE_MAX; + + /* First move what we can in the largest integer mode, then go to + successively smaller modes. */ + + while (max_size > 1) + { + enum machine_mode mode = VOIDmode, tmode; + enum insn_code icode; + + for (tmode = GET_CLASS_NARROWEST_MODE (MODE_INT); + tmode != VOIDmode; tmode = GET_MODE_WIDER_MODE (tmode)) + if (GET_MODE_SIZE (tmode) < max_size) + mode = tmode; + + if (mode == VOIDmode) + break; + + icode = mov_optab->handlers[(int) mode].insn_code; + if (icode != CODE_FOR_nothing + && align >= MIN (BIGGEST_ALIGNMENT / BITS_PER_UNIT, + GET_MODE_SIZE (mode))) + move_by_pieces_1 (GEN_FCN (icode), mode, &data); + + max_size = GET_MODE_SIZE (mode); + } + + /* The code above should have handled everything. */ + if (data.len != 0) + abort (); +} + +/* Return number of insns required to move L bytes by pieces. + ALIGN (in bytes) is maximum alignment we can assume. */ + +static int +move_by_pieces_ninsns (l, align) + unsigned int l; + int align; +{ + register int n_insns = 0; + int max_size = MOVE_MAX + 1; + + if (! (STRICT_ALIGNMENT || SLOW_UNALIGNED_ACCESS) + || align > MOVE_MAX || align >= BIGGEST_ALIGNMENT / BITS_PER_UNIT) + align = MOVE_MAX; + + while (max_size > 1) + { + enum machine_mode mode = VOIDmode, tmode; + enum insn_code icode; + + for (tmode = GET_CLASS_NARROWEST_MODE (MODE_INT); + tmode != VOIDmode; tmode = GET_MODE_WIDER_MODE (tmode)) + if (GET_MODE_SIZE (tmode) < max_size) + mode = tmode; + + if (mode == VOIDmode) + break; + + icode = mov_optab->handlers[(int) mode].insn_code; + if (icode != CODE_FOR_nothing + && align >= MIN (BIGGEST_ALIGNMENT / BITS_PER_UNIT, + GET_MODE_SIZE (mode))) + n_insns += l / GET_MODE_SIZE (mode), l %= GET_MODE_SIZE (mode); + + max_size = GET_MODE_SIZE (mode); + } + + return n_insns; +} + +/* Subroutine of move_by_pieces. Move as many bytes as appropriate + with move instructions for mode MODE. GENFUN is the gen_... function + to make a move insn for that mode. DATA has all the other info. */ + +static void +move_by_pieces_1 (genfun, mode, data) + rtx (*genfun) (); + enum machine_mode mode; + struct move_by_pieces *data; +{ + register int size = GET_MODE_SIZE (mode); + register rtx to1, from1; + + while (data->len >= size) + { + if (data->reverse) data->offset -= size; + + to1 = (data->autinc_to + ? gen_rtx (MEM, mode, data->to_addr) + : change_address (data->to, mode, + plus_constant (data->to_addr, data->offset))); + from1 = + (data->autinc_from + ? gen_rtx (MEM, mode, data->from_addr) + : change_address (data->from, mode, + plus_constant (data->from_addr, data->offset))); + +#ifdef HAVE_PRE_DECREMENT + if (data->explicit_inc_to < 0) + emit_insn (gen_add2_insn (data->to_addr, GEN_INT (-size))); + if (data->explicit_inc_from < 0) + emit_insn (gen_add2_insn (data->from_addr, GEN_INT (-size))); +#endif + + emit_insn ((*genfun) (to1, from1)); +#ifdef HAVE_POST_INCREMENT + if (data->explicit_inc_to > 0) + emit_insn (gen_add2_insn (data->to_addr, GEN_INT (size))); + if (data->explicit_inc_from > 0) + emit_insn (gen_add2_insn (data->from_addr, GEN_INT (size))); +#endif + + if (! data->reverse) data->offset += size; + + data->len -= size; + } +} + +/* Emit code to move a block Y to a block X. + This may be done with string-move instructions, + with multiple scalar move instructions, or with a library call. + + Both X and Y must be MEM rtx's (perhaps inside VOLATILE) + with mode BLKmode. + SIZE is an rtx that says how long they are. + ALIGN is the maximum alignment we can assume they have, + measured in bytes. */ + +void +emit_block_move (x, y, size, align) + rtx x, y; + rtx size; + int align; +{ + if (GET_MODE (x) != BLKmode) + abort (); + + if (GET_MODE (y) != BLKmode) + abort (); + + x = protect_from_queue (x, 1); + y = protect_from_queue (y, 0); + size = protect_from_queue (size, 0); + + if (GET_CODE (x) != MEM) + abort (); + if (GET_CODE (y) != MEM) + abort (); + if (size == 0) + abort (); + + if (GET_CODE (size) == CONST_INT + && (move_by_pieces_ninsns (INTVAL (size), align) < MOVE_RATIO)) + move_by_pieces (x, y, INTVAL (size), align); + else + { + /* Try the most limited insn first, because there's no point + including more than one in the machine description unless + the more limited one has some advantage. */ + + rtx opalign = GEN_INT (align); + enum machine_mode mode; + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + { + enum insn_code code = movstr_optab[(int) mode]; + + if (code != CODE_FOR_nothing + /* We don't need MODE to be narrower than BITS_PER_HOST_WIDE_INT + here because if SIZE is less than the mode mask, as it is + returned by the macro, it will definitely be less than the + actual mode mask. */ + && (unsigned HOST_WIDE_INT) INTVAL (size) <= GET_MODE_MASK (mode) + && (insn_operand_predicate[(int) code][0] == 0 + || (*insn_operand_predicate[(int) code][0]) (x, BLKmode)) + && (insn_operand_predicate[(int) code][1] == 0 + || (*insn_operand_predicate[(int) code][1]) (y, BLKmode)) + && (insn_operand_predicate[(int) code][3] == 0 + || (*insn_operand_predicate[(int) code][3]) (opalign, + VOIDmode))) + { + rtx op2; + rtx last = get_last_insn (); + rtx pat; + + op2 = convert_to_mode (mode, size, 1); + if (insn_operand_predicate[(int) code][2] != 0 + && ! (*insn_operand_predicate[(int) code][2]) (op2, mode)) + op2 = copy_to_mode_reg (mode, op2); + + pat = GEN_FCN ((int) code) (x, y, op2, opalign); + if (pat) + { + emit_insn (pat); + return; + } + else + delete_insns_since (last); + } + } + +#ifdef TARGET_MEM_FUNCTIONS + emit_library_call (memcpy_libfunc, 0, + VOIDmode, 3, XEXP (x, 0), Pmode, + XEXP (y, 0), Pmode, + convert_to_mode (TYPE_MODE (sizetype), size, + TREE_UNSIGNED (sizetype)), + TYPE_MODE (sizetype)); +#else + emit_library_call (bcopy_libfunc, 0, + VOIDmode, 3, XEXP (y, 0), Pmode, + XEXP (x, 0), Pmode, + convert_to_mode (TYPE_MODE (sizetype), size, + TREE_UNSIGNED (sizetype)), + TYPE_MODE (sizetype)); +#endif + } +} + +/* Copy all or part of a value X into registers starting at REGNO. + The number of registers to be filled is NREGS. */ + +void +move_block_to_reg (regno, x, nregs, mode) + int regno; + rtx x; + int nregs; + enum machine_mode mode; +{ + int i; + rtx pat, last; + + if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x)) + x = validize_mem (force_const_mem (mode, x)); + + /* See if the machine can do this with a load multiple insn. */ +#ifdef HAVE_load_multiple + last = get_last_insn (); + pat = gen_load_multiple (gen_rtx (REG, word_mode, regno), x, + GEN_INT (nregs)); + if (pat) + { + emit_insn (pat); + return; + } + else + delete_insns_since (last); +#endif + + for (i = 0; i < nregs; i++) + emit_move_insn (gen_rtx (REG, word_mode, regno + i), + operand_subword_force (x, i, mode)); +} + +/* Copy all or part of a BLKmode value X out of registers starting at REGNO. + The number of registers to be filled is NREGS. */ + +void +move_block_from_reg (regno, x, nregs) + int regno; + rtx x; + int nregs; +{ + int i; + rtx pat, last; + + /* See if the machine can do this with a store multiple insn. */ +#ifdef HAVE_store_multiple + last = get_last_insn (); + pat = gen_store_multiple (x, gen_rtx (REG, word_mode, regno), + GEN_INT (nregs)); + if (pat) + { + emit_insn (pat); + return; + } + else + delete_insns_since (last); +#endif + + for (i = 0; i < nregs; i++) + { + rtx tem = operand_subword (x, i, 1, BLKmode); + + if (tem == 0) + abort (); + + emit_move_insn (tem, gen_rtx (REG, word_mode, regno + i)); + } +} + +/* Mark NREGS consecutive regs, starting at REGNO, as being live now. */ + +void +use_regs (regno, nregs) + int regno; + int nregs; +{ + int i; + + for (i = 0; i < nregs; i++) + emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, regno + i))); +} + +/* Mark the instructions since PREV as a libcall block. + Add REG_LIBCALL to PREV and add a REG_RETVAL to the most recent insn. */ + +static void +group_insns (prev) + rtx prev; +{ + rtx insn_first; + rtx insn_last; + + /* Find the instructions to mark */ + if (prev) + insn_first = NEXT_INSN (prev); + else + insn_first = get_insns (); + + insn_last = get_last_insn (); + + REG_NOTES (insn_last) = gen_rtx (INSN_LIST, REG_RETVAL, insn_first, + REG_NOTES (insn_last)); + + REG_NOTES (insn_first) = gen_rtx (INSN_LIST, REG_LIBCALL, insn_last, + REG_NOTES (insn_first)); +} + +/* Write zeros through the storage of OBJECT. + If OBJECT has BLKmode, SIZE is its length in bytes. */ + +void +clear_storage (object, size) + rtx object; + int size; +{ + if (GET_MODE (object) == BLKmode) + { +#ifdef TARGET_MEM_FUNCTIONS + emit_library_call (memset_libfunc, 0, + VOIDmode, 3, + XEXP (object, 0), Pmode, const0_rtx, Pmode, + GEN_INT (size), Pmode); +#else + emit_library_call (bzero_libfunc, 0, + VOIDmode, 2, + XEXP (object, 0), Pmode, + GEN_INT (size), Pmode); +#endif + } + else + emit_move_insn (object, const0_rtx); +} + +/* Generate code to copy Y into X. + Both Y and X must have the same mode, except that + Y can be a constant with VOIDmode. + This mode cannot be BLKmode; use emit_block_move for that. + + Return the last instruction emitted. */ + +rtx +emit_move_insn (x, y) + rtx x, y; +{ + enum machine_mode mode = GET_MODE (x); + enum machine_mode submode; + enum mode_class class = GET_MODE_CLASS (mode); + int i; + + x = protect_from_queue (x, 1); + y = protect_from_queue (y, 0); + + if (mode == BLKmode || (GET_MODE (y) != mode && GET_MODE (y) != VOIDmode)) + abort (); + + if (CONSTANT_P (y) && ! LEGITIMATE_CONSTANT_P (y)) + y = force_const_mem (mode, y); + + /* If X or Y are memory references, verify that their addresses are valid + for the machine. */ + if (GET_CODE (x) == MEM + && ((! memory_address_p (GET_MODE (x), XEXP (x, 0)) + && ! push_operand (x, GET_MODE (x))) + || (flag_force_addr + && CONSTANT_ADDRESS_P (XEXP (x, 0))))) + x = change_address (x, VOIDmode, XEXP (x, 0)); + + if (GET_CODE (y) == MEM + && (! memory_address_p (GET_MODE (y), XEXP (y, 0)) + || (flag_force_addr + && CONSTANT_ADDRESS_P (XEXP (y, 0))))) + y = change_address (y, VOIDmode, XEXP (y, 0)); + + if (mode == BLKmode) + abort (); + + return emit_move_insn_1 (x, y); +} + +/* Low level part of emit_move_insn. + Called just like emit_move_insn, but assumes X and Y + are basically valid. */ + +rtx +emit_move_insn_1 (x, y) + rtx x, y; +{ + enum machine_mode mode = GET_MODE (x); + enum machine_mode submode; + enum mode_class class = GET_MODE_CLASS (mode); + int i; + + if (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT) + submode = mode_for_size (GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT, + (class == MODE_COMPLEX_INT + ? MODE_INT : MODE_FLOAT), + 0); + + if (mov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + return + emit_insn (GEN_FCN (mov_optab->handlers[(int) mode].insn_code) (x, y)); + + /* Expand complex moves by moving real part and imag part, if possible. */ + else if ((class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT) + && submode != BLKmode + && (mov_optab->handlers[(int) submode].insn_code + != CODE_FOR_nothing)) + { + /* Don't split destination if it is a stack push. */ + int stack = push_operand (x, GET_MODE (x)); + rtx prev = get_last_insn (); + + /* Tell flow that the whole of the destination is being set. */ + if (GET_CODE (x) == REG) + emit_insn (gen_rtx (CLOBBER, VOIDmode, x)); + + /* If this is a stack, push the highpart first, so it + will be in the argument order. + + In that case, change_address is used only to convert + the mode, not to change the address. */ + emit_insn (GEN_FCN (mov_optab->handlers[(int) submode].insn_code) + ((stack ? change_address (x, submode, (rtx) 0) + : gen_highpart (submode, x)), + gen_highpart (submode, y))); + emit_insn (GEN_FCN (mov_optab->handlers[(int) submode].insn_code) + ((stack ? change_address (x, submode, (rtx) 0) + : gen_lowpart (submode, x)), + gen_lowpart (submode, y))); + + group_insns (prev); + + return get_last_insn (); + } + + /* This will handle any multi-word mode that lacks a move_insn pattern. + However, you will get better code if you define such patterns, + even if they must turn into multiple assembler instructions. */ + else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) + { + rtx last_insn = 0; + rtx prev_insn = get_last_insn (); + + for (i = 0; + i < (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; + i++) + { + rtx xpart = operand_subword (x, i, 1, mode); + rtx ypart = operand_subword (y, i, 1, mode); + + /* If we can't get a part of Y, put Y into memory if it is a + constant. Otherwise, force it into a register. If we still + can't get a part of Y, abort. */ + if (ypart == 0 && CONSTANT_P (y)) + { + y = force_const_mem (mode, y); + ypart = operand_subword (y, i, 1, mode); + } + else if (ypart == 0) + ypart = operand_subword_force (y, i, mode); + + if (xpart == 0 || ypart == 0) + abort (); + + last_insn = emit_move_insn (xpart, ypart); + } + /* Mark these insns as a libcall block. */ + group_insns (prev_insn); + + return last_insn; + } + else + abort (); +} + +/* Pushing data onto the stack. */ + +/* Push a block of length SIZE (perhaps variable) + and return an rtx to address the beginning of the block. + Note that it is not possible for the value returned to be a QUEUED. + The value may be virtual_outgoing_args_rtx. + + EXTRA is the number of bytes of padding to push in addition to SIZE. + BELOW nonzero means this padding comes at low addresses; + otherwise, the padding comes at high addresses. */ + +rtx +push_block (size, extra, below) + rtx size; + int extra, below; +{ + register rtx temp; + if (CONSTANT_P (size)) + anti_adjust_stack (plus_constant (size, extra)); + else if (GET_CODE (size) == REG && extra == 0) + anti_adjust_stack (size); + else + { + rtx temp = copy_to_mode_reg (Pmode, size); + if (extra != 0) + temp = expand_binop (Pmode, add_optab, temp, GEN_INT (extra), + temp, 0, OPTAB_LIB_WIDEN); + anti_adjust_stack (temp); + } + +#ifdef STACK_GROWS_DOWNWARD + temp = virtual_outgoing_args_rtx; + if (extra != 0 && below) + temp = plus_constant (temp, extra); +#else + if (GET_CODE (size) == CONST_INT) + temp = plus_constant (virtual_outgoing_args_rtx, + - INTVAL (size) - (below ? 0 : extra)); + else if (extra != 0 && !below) + temp = gen_rtx (PLUS, Pmode, virtual_outgoing_args_rtx, + negate_rtx (Pmode, plus_constant (size, extra))); + else + temp = gen_rtx (PLUS, Pmode, virtual_outgoing_args_rtx, + negate_rtx (Pmode, size)); +#endif + + return memory_address (GET_CLASS_NARROWEST_MODE (MODE_INT), temp); +} + +rtx +gen_push_operand () +{ + return gen_rtx (STACK_PUSH_CODE, Pmode, stack_pointer_rtx); +} + +/* Generate code to push X onto the stack, assuming it has mode MODE and + type TYPE. + MODE is redundant except when X is a CONST_INT (since they don't + carry mode info). + SIZE is an rtx for the size of data to be copied (in bytes), + needed only if X is BLKmode. + + ALIGN (in bytes) is maximum alignment we can assume. + + If PARTIAL and REG are both nonzero, then copy that many of the first + words of X into registers starting with REG, and push the rest of X. + The amount of space pushed is decreased by PARTIAL words, + rounded *down* to a multiple of PARM_BOUNDARY. + REG must be a hard register in this case. + If REG is zero but PARTIAL is not, take any all others actions for an + argument partially in registers, but do not actually load any + registers. + + EXTRA is the amount in bytes of extra space to leave next to this arg. + This is ignored if an argument block has already been allocated. + + On a machine that lacks real push insns, ARGS_ADDR is the address of + the bottom of the argument block for this call. We use indexing off there + to store the arg. On machines with push insns, ARGS_ADDR is 0 when a + argument block has not been preallocated. + + ARGS_SO_FAR is the size of args previously pushed for this call. */ + +void +emit_push_insn (x, mode, type, size, align, partial, reg, extra, + args_addr, args_so_far) + register rtx x; + enum machine_mode mode; + tree type; + rtx size; + int align; + int partial; + rtx reg; + int extra; + rtx args_addr; + rtx args_so_far; +{ + rtx xinner; + enum direction stack_direction +#ifdef STACK_GROWS_DOWNWARD + = downward; +#else + = upward; +#endif + + /* Decide where to pad the argument: `downward' for below, + `upward' for above, or `none' for don't pad it. + Default is below for small data on big-endian machines; else above. */ + enum direction where_pad = FUNCTION_ARG_PADDING (mode, type); + + /* Invert direction if stack is post-update. */ + if (STACK_PUSH_CODE == POST_INC || STACK_PUSH_CODE == POST_DEC) + if (where_pad != none) + where_pad = (where_pad == downward ? upward : downward); + + xinner = x = protect_from_queue (x, 0); + + if (mode == BLKmode) + { + /* Copy a block into the stack, entirely or partially. */ + + register rtx temp; + int used = partial * UNITS_PER_WORD; + int offset = used % (PARM_BOUNDARY / BITS_PER_UNIT); + int skip; + + if (size == 0) + abort (); + + used -= offset; + + /* USED is now the # of bytes we need not copy to the stack + because registers will take care of them. */ + + if (partial != 0) + xinner = change_address (xinner, BLKmode, + plus_constant (XEXP (xinner, 0), used)); + + /* If the partial register-part of the arg counts in its stack size, + skip the part of stack space corresponding to the registers. + Otherwise, start copying to the beginning of the stack space, + by setting SKIP to 0. */ +#ifndef REG_PARM_STACK_SPACE + skip = 0; +#else + skip = used; +#endif + +#ifdef PUSH_ROUNDING + /* Do it with several push insns if that doesn't take lots of insns + and if there is no difficulty with push insns that skip bytes + on the stack for alignment purposes. */ + if (args_addr == 0 + && GET_CODE (size) == CONST_INT + && skip == 0 + && (move_by_pieces_ninsns ((unsigned) INTVAL (size) - used, align) + < MOVE_RATIO) + /* Here we avoid the case of a structure whose weak alignment + forces many pushes of a small amount of data, + and such small pushes do rounding that causes trouble. */ + && ((! STRICT_ALIGNMENT && ! SLOW_UNALIGNED_ACCESS) + || align >= BIGGEST_ALIGNMENT / BITS_PER_UNIT + || PUSH_ROUNDING (align) == align) + && PUSH_ROUNDING (INTVAL (size)) == INTVAL (size)) + { + /* Push padding now if padding above and stack grows down, + or if padding below and stack grows up. + But if space already allocated, this has already been done. */ + if (extra && args_addr == 0 + && where_pad != none && where_pad != stack_direction) + anti_adjust_stack (GEN_INT (extra)); + + move_by_pieces (gen_rtx (MEM, BLKmode, gen_push_operand ()), xinner, + INTVAL (size) - used, align); + } + else +#endif /* PUSH_ROUNDING */ + { + /* Otherwise make space on the stack and copy the data + to the address of that space. */ + + /* Deduct words put into registers from the size we must copy. */ + if (partial != 0) + { + if (GET_CODE (size) == CONST_INT) + size = GEN_INT (INTVAL (size) - used); + else + size = expand_binop (GET_MODE (size), sub_optab, size, + GEN_INT (used), NULL_RTX, 0, + OPTAB_LIB_WIDEN); + } + + /* Get the address of the stack space. + In this case, we do not deal with EXTRA separately. + A single stack adjust will do. */ + if (! args_addr) + { + temp = push_block (size, extra, where_pad == downward); + extra = 0; + } + else if (GET_CODE (args_so_far) == CONST_INT) + temp = memory_address (BLKmode, + plus_constant (args_addr, + skip + INTVAL (args_so_far))); + else + temp = memory_address (BLKmode, + plus_constant (gen_rtx (PLUS, Pmode, + args_addr, args_so_far), + skip)); + + /* TEMP is the address of the block. Copy the data there. */ + if (GET_CODE (size) == CONST_INT + && (move_by_pieces_ninsns ((unsigned) INTVAL (size), align) + < MOVE_RATIO)) + { + move_by_pieces (gen_rtx (MEM, BLKmode, temp), xinner, + INTVAL (size), align); + goto ret; + } + /* Try the most limited insn first, because there's no point + including more than one in the machine description unless + the more limited one has some advantage. */ +#ifdef HAVE_movstrqi + if (HAVE_movstrqi + && GET_CODE (size) == CONST_INT + && ((unsigned) INTVAL (size) + < (1 << (GET_MODE_BITSIZE (QImode) - 1)))) + { + rtx pat = gen_movstrqi (gen_rtx (MEM, BLKmode, temp), + xinner, size, GEN_INT (align)); + if (pat != 0) + { + emit_insn (pat); + goto ret; + } + } +#endif +#ifdef HAVE_movstrhi + if (HAVE_movstrhi + && GET_CODE (size) == CONST_INT + && ((unsigned) INTVAL (size) + < (1 << (GET_MODE_BITSIZE (HImode) - 1)))) + { + rtx pat = gen_movstrhi (gen_rtx (MEM, BLKmode, temp), + xinner, size, GEN_INT (align)); + if (pat != 0) + { + emit_insn (pat); + goto ret; + } + } +#endif +#ifdef HAVE_movstrsi + if (HAVE_movstrsi) + { + rtx pat = gen_movstrsi (gen_rtx (MEM, BLKmode, temp), + xinner, size, GEN_INT (align)); + if (pat != 0) + { + emit_insn (pat); + goto ret; + } + } +#endif +#ifdef HAVE_movstrdi + if (HAVE_movstrdi) + { + rtx pat = gen_movstrdi (gen_rtx (MEM, BLKmode, temp), + xinner, size, GEN_INT (align)); + if (pat != 0) + { + emit_insn (pat); + goto ret; + } + } +#endif + +#ifndef ACCUMULATE_OUTGOING_ARGS + /* If the source is referenced relative to the stack pointer, + copy it to another register to stabilize it. We do not need + to do this if we know that we won't be changing sp. */ + + if (reg_mentioned_p (virtual_stack_dynamic_rtx, temp) + || reg_mentioned_p (virtual_outgoing_args_rtx, temp)) + temp = copy_to_reg (temp); +#endif + + /* Make inhibit_defer_pop nonzero around the library call + to force it to pop the bcopy-arguments right away. */ + NO_DEFER_POP; +#ifdef TARGET_MEM_FUNCTIONS + emit_library_call (memcpy_libfunc, 0, + VOIDmode, 3, temp, Pmode, XEXP (xinner, 0), Pmode, + convert_to_mode (TYPE_MODE (sizetype), + size, TREE_UNSIGNED (sizetype)), + TYPE_MODE (sizetype)); +#else + emit_library_call (bcopy_libfunc, 0, + VOIDmode, 3, XEXP (xinner, 0), Pmode, temp, Pmode, + convert_to_mode (TYPE_MODE (sizetype), + size, TREE_UNSIGNED (sizetype)), + TYPE_MODE (sizetype)); +#endif + OK_DEFER_POP; + } + } + else if (partial > 0) + { + /* Scalar partly in registers. */ + + int size = GET_MODE_SIZE (mode) / UNITS_PER_WORD; + int i; + int not_stack; + /* # words of start of argument + that we must make space for but need not store. */ + int offset = partial % (PARM_BOUNDARY / BITS_PER_WORD); + int args_offset = INTVAL (args_so_far); + int skip; + + /* Push padding now if padding above and stack grows down, + or if padding below and stack grows up. + But if space already allocated, this has already been done. */ + if (extra && args_addr == 0 + && where_pad != none && where_pad != stack_direction) + anti_adjust_stack (GEN_INT (extra)); + + /* If we make space by pushing it, we might as well push + the real data. Otherwise, we can leave OFFSET nonzero + and leave the space uninitialized. */ + if (args_addr == 0) + offset = 0; + + /* Now NOT_STACK gets the number of words that we don't need to + allocate on the stack. */ + not_stack = partial - offset; + + /* If the partial register-part of the arg counts in its stack size, + skip the part of stack space corresponding to the registers. + Otherwise, start copying to the beginning of the stack space, + by setting SKIP to 0. */ +#ifndef REG_PARM_STACK_SPACE + skip = 0; +#else + skip = not_stack; +#endif + + if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x)) + x = validize_mem (force_const_mem (mode, x)); + + /* If X is a hard register in a non-integer mode, copy it into a pseudo; + SUBREGs of such registers are not allowed. */ + if ((GET_CODE (x) == REG && REGNO (x) < FIRST_PSEUDO_REGISTER + && GET_MODE_CLASS (GET_MODE (x)) != MODE_INT)) + x = copy_to_reg (x); + + /* Loop over all the words allocated on the stack for this arg. */ + /* We can do it by words, because any scalar bigger than a word + has a size a multiple of a word. */ +#ifndef PUSH_ARGS_REVERSED + for (i = not_stack; i < size; i++) +#else + for (i = size - 1; i >= not_stack; i--) +#endif + if (i >= not_stack + offset) + emit_push_insn (operand_subword_force (x, i, mode), + word_mode, NULL_TREE, NULL_RTX, align, 0, NULL_RTX, + 0, args_addr, + GEN_INT (args_offset + ((i - not_stack + skip) + * UNITS_PER_WORD))); + } + else + { + rtx addr; + + /* Push padding now if padding above and stack grows down, + or if padding below and stack grows up. + But if space already allocated, this has already been done. */ + if (extra && args_addr == 0 + && where_pad != none && where_pad != stack_direction) + anti_adjust_stack (GEN_INT (extra)); + +#ifdef PUSH_ROUNDING + if (args_addr == 0) + addr = gen_push_operand (); + else +#endif + if (GET_CODE (args_so_far) == CONST_INT) + addr + = memory_address (mode, + plus_constant (args_addr, INTVAL (args_so_far))); + else + addr = memory_address (mode, gen_rtx (PLUS, Pmode, args_addr, + args_so_far)); + + emit_move_insn (gen_rtx (MEM, mode, addr), x); + } + + ret: + /* If part should go in registers, copy that part + into the appropriate registers. Do this now, at the end, + since mem-to-mem copies above may do function calls. */ + if (partial > 0 && reg != 0) + move_block_to_reg (REGNO (reg), x, partial, mode); + + if (extra && args_addr == 0 && where_pad == stack_direction) + anti_adjust_stack (GEN_INT (extra)); +} + +/* Expand an assignment that stores the value of FROM into TO. + If WANT_VALUE is nonzero, return an rtx for the value of TO. + (This may contain a QUEUED rtx.) + Otherwise, the returned value is not meaningful. + + SUGGEST_REG is no longer actually used. + It used to mean, copy the value through a register + and return that register, if that is possible. + But now we do this if WANT_VALUE. + + If the value stored is a constant, we return the constant. */ + +rtx +expand_assignment (to, from, want_value, suggest_reg) + tree to, from; + int want_value; + int suggest_reg; +{ + register rtx to_rtx = 0; + rtx result; + + /* Don't crash if the lhs of the assignment was erroneous. */ + + if (TREE_CODE (to) == ERROR_MARK) + return expand_expr (from, NULL_RTX, VOIDmode, 0); + + /* Assignment of a structure component needs special treatment + if the structure component's rtx is not simply a MEM. + Assignment of an array element at a constant index + has the same problem. */ + + if (TREE_CODE (to) == COMPONENT_REF + || TREE_CODE (to) == BIT_FIELD_REF + || (TREE_CODE (to) == ARRAY_REF + && TREE_CODE (TREE_OPERAND (to, 1)) == INTEGER_CST + && TREE_CODE (TYPE_SIZE (TREE_TYPE (to))) == INTEGER_CST)) + { + enum machine_mode mode1; + int bitsize; + int bitpos; + tree offset; + int unsignedp; + int volatilep = 0; + tree tem = get_inner_reference (to, &bitsize, &bitpos, &offset, + &mode1, &unsignedp, &volatilep); + + /* If we are going to use store_bit_field and extract_bit_field, + make sure to_rtx will be safe for multiple use. */ + + if (mode1 == VOIDmode && want_value) + tem = stabilize_reference (tem); + + to_rtx = expand_expr (tem, NULL_RTX, VOIDmode, 0); + if (offset != 0) + { + rtx offset_rtx = expand_expr (offset, NULL_RTX, VOIDmode, 0); + + if (GET_CODE (to_rtx) != MEM) + abort (); + to_rtx = change_address (to_rtx, VOIDmode, + gen_rtx (PLUS, Pmode, XEXP (to_rtx, 0), + force_reg (Pmode, offset_rtx))); + } + if (volatilep) + { + if (GET_CODE (to_rtx) == MEM) + MEM_VOLATILE_P (to_rtx) = 1; +#if 0 /* This was turned off because, when a field is volatile + in an object which is not volatile, the object may be in a register, + and then we would abort over here. */ + else + abort (); +#endif + } + + result = store_field (to_rtx, bitsize, bitpos, mode1, from, + (want_value + /* Spurious cast makes HPUX compiler happy. */ + ? (enum machine_mode) TYPE_MODE (TREE_TYPE (to)) + : VOIDmode), + unsignedp, + /* Required alignment of containing datum. */ + TYPE_ALIGN (TREE_TYPE (tem)) / BITS_PER_UNIT, + int_size_in_bytes (TREE_TYPE (tem))); + preserve_temp_slots (result); + free_temp_slots (); + + /* If we aren't returning a result, just pass on what expand_expr + returned; it was probably const0_rtx. Otherwise, convert RESULT + to the proper mode. */ + return (want_value ? convert_to_mode (TYPE_MODE (TREE_TYPE (to)), result, + TREE_UNSIGNED (TREE_TYPE (to))) + : result); + } + + /* Ordinary treatment. Expand TO to get a REG or MEM rtx. + Don't re-expand if it was expanded already (in COMPONENT_REF case). */ + + if (to_rtx == 0) + to_rtx = expand_expr (to, NULL_RTX, VOIDmode, 0); + + /* Don't move directly into a return register. */ + if (TREE_CODE (to) == RESULT_DECL && GET_CODE (to_rtx) == REG) + { + rtx temp = expand_expr (from, 0, GET_MODE (to_rtx), 0); + emit_move_insn (to_rtx, temp); + preserve_temp_slots (to_rtx); + free_temp_slots (); + return to_rtx; + } + + /* In case we are returning the contents of an object which overlaps + the place the value is being stored, use a safe function when copying + a value through a pointer into a structure value return block. */ + if (TREE_CODE (to) == RESULT_DECL && TREE_CODE (from) == INDIRECT_REF + && current_function_returns_struct + && !current_function_returns_pcc_struct) + { + rtx from_rtx = expand_expr (from, NULL_RTX, VOIDmode, 0); + rtx size = expr_size (from); + +#ifdef TARGET_MEM_FUNCTIONS + emit_library_call (memcpy_libfunc, 0, + VOIDmode, 3, XEXP (to_rtx, 0), Pmode, + XEXP (from_rtx, 0), Pmode, + convert_to_mode (TYPE_MODE (sizetype), + size, TREE_UNSIGNED (sizetype)), + TYPE_MODE (sizetype)); +#else + emit_library_call (bcopy_libfunc, 0, + VOIDmode, 3, XEXP (from_rtx, 0), Pmode, + XEXP (to_rtx, 0), Pmode, + convert_to_mode (TYPE_MODE (sizetype), + size, TREE_UNSIGNED (sizetype)), + TYPE_MODE (sizetype)); +#endif + + preserve_temp_slots (to_rtx); + free_temp_slots (); + return to_rtx; + } + + /* Compute FROM and store the value in the rtx we got. */ + + result = store_expr (from, to_rtx, want_value); + preserve_temp_slots (result); + free_temp_slots (); + return result; +} + +/* Generate code for computing expression EXP, + and storing the value into TARGET. + Returns TARGET or an equivalent value. + TARGET may contain a QUEUED rtx. + + If SUGGEST_REG is nonzero, copy the value through a register + and return that register, if that is possible. + + If the value stored is a constant, we return the constant. */ + +rtx +store_expr (exp, target, suggest_reg) + register tree exp; + register rtx target; + int suggest_reg; +{ + register rtx temp; + int dont_return_target = 0; + + if (TREE_CODE (exp) == COMPOUND_EXPR) + { + /* Perform first part of compound expression, then assign from second + part. */ + expand_expr (TREE_OPERAND (exp, 0), const0_rtx, VOIDmode, 0); + emit_queue (); + return store_expr (TREE_OPERAND (exp, 1), target, suggest_reg); + } + else if (TREE_CODE (exp) == COND_EXPR && GET_MODE (target) == BLKmode) + { + /* For conditional expression, get safe form of the target. Then + test the condition, doing the appropriate assignment on either + side. This avoids the creation of unnecessary temporaries. + For non-BLKmode, it is more efficient not to do this. */ + + rtx lab1 = gen_label_rtx (), lab2 = gen_label_rtx (); + + emit_queue (); + target = protect_from_queue (target, 1); + + NO_DEFER_POP; + jumpifnot (TREE_OPERAND (exp, 0), lab1); + store_expr (TREE_OPERAND (exp, 1), target, suggest_reg); + emit_queue (); + emit_jump_insn (gen_jump (lab2)); + emit_barrier (); + emit_label (lab1); + store_expr (TREE_OPERAND (exp, 2), target, suggest_reg); + emit_queue (); + emit_label (lab2); + OK_DEFER_POP; + return target; + } + else if (suggest_reg && GET_CODE (target) == MEM + && GET_MODE (target) != BLKmode) + /* If target is in memory and caller wants value in a register instead, + arrange that. Pass TARGET as target for expand_expr so that, + if EXP is another assignment, SUGGEST_REG will be nonzero for it. + We know expand_expr will not use the target in that case. */ + { + temp = expand_expr (exp, cse_not_expected ? NULL_RTX : target, + GET_MODE (target), 0); + if (GET_MODE (temp) != BLKmode && GET_MODE (temp) != VOIDmode) + temp = copy_to_reg (temp); + dont_return_target = 1; + } + else if (queued_subexp_p (target)) + /* If target contains a postincrement, it is not safe + to use as the returned value. It would access the wrong + place by the time the queued increment gets output. + So copy the value through a temporary and use that temp + as the result. */ + { + if (GET_MODE (target) != BLKmode && GET_MODE (target) != VOIDmode) + { + /* Expand EXP into a new pseudo. */ + temp = gen_reg_rtx (GET_MODE (target)); + temp = expand_expr (exp, temp, GET_MODE (target), 0); + } + else + temp = expand_expr (exp, NULL_RTX, GET_MODE (target), 0); + dont_return_target = 1; + } + else if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target)) + /* If this is an scalar in a register that is stored in a wider mode + than the declared mode, compute the result into its declared mode + and then convert to the wider mode. Our value is the computed + expression. */ + { + temp = expand_expr (exp, NULL_RTX, VOIDmode, 0); + convert_move (SUBREG_REG (target), temp, + SUBREG_PROMOTED_UNSIGNED_P (target)); + return temp; + } + else + { + temp = expand_expr (exp, target, GET_MODE (target), 0); + /* DO return TARGET if it's a specified hardware register. + expand_return relies on this. */ + if (!(target && GET_CODE (target) == REG + && REGNO (target) < FIRST_PSEUDO_REGISTER) + && CONSTANT_P (temp)) + dont_return_target = 1; + } + + /* If value was not generated in the target, store it there. + Convert the value to TARGET's type first if nec. */ + + if (temp != target && TREE_CODE (exp) != ERROR_MARK) + { + target = protect_from_queue (target, 1); + if (GET_MODE (temp) != GET_MODE (target) + && GET_MODE (temp) != VOIDmode) + { + int unsignedp = TREE_UNSIGNED (TREE_TYPE (exp)); + if (dont_return_target) + { + /* In this case, we will return TEMP, + so make sure it has the proper mode. + But don't forget to store the value into TARGET. */ + temp = convert_to_mode (GET_MODE (target), temp, unsignedp); + emit_move_insn (target, temp); + } + else + convert_move (target, temp, unsignedp); + } + + else if (GET_MODE (temp) == BLKmode && TREE_CODE (exp) == STRING_CST) + { + /* Handle copying a string constant into an array. + The string constant may be shorter than the array. + So copy just the string's actual length, and clear the rest. */ + rtx size; + + /* Get the size of the data type of the string, + which is actually the size of the target. */ + size = expr_size (exp); + if (GET_CODE (size) == CONST_INT + && INTVAL (size) < TREE_STRING_LENGTH (exp)) + emit_block_move (target, temp, size, + TYPE_ALIGN (TREE_TYPE (exp)) / BITS_PER_UNIT); + else + { + /* Compute the size of the data to copy from the string. */ + tree copy_size + = size_binop (MIN_EXPR, + size_binop (CEIL_DIV_EXPR, + TYPE_SIZE (TREE_TYPE (exp)), + size_int (BITS_PER_UNIT)), + convert (sizetype, + build_int_2 (TREE_STRING_LENGTH (exp), 0))); + rtx copy_size_rtx = expand_expr (copy_size, NULL_RTX, + VOIDmode, 0); + rtx label = 0; + + /* Copy that much. */ + emit_block_move (target, temp, copy_size_rtx, + TYPE_ALIGN (TREE_TYPE (exp)) / BITS_PER_UNIT); + + /* Figure out how much is left in TARGET + that we have to clear. */ + if (GET_CODE (copy_size_rtx) == CONST_INT) + { + temp = plus_constant (XEXP (target, 0), + TREE_STRING_LENGTH (exp)); + size = plus_constant (size, + - TREE_STRING_LENGTH (exp)); + } + else + { + enum machine_mode size_mode = Pmode; + + temp = force_reg (Pmode, XEXP (target, 0)); + temp = expand_binop (size_mode, add_optab, temp, + copy_size_rtx, NULL_RTX, 0, + OPTAB_LIB_WIDEN); + + size = expand_binop (size_mode, sub_optab, size, + copy_size_rtx, NULL_RTX, 0, + OPTAB_LIB_WIDEN); + + emit_cmp_insn (size, const0_rtx, LT, NULL_RTX, + GET_MODE (size), 0, 0); + label = gen_label_rtx (); + emit_jump_insn (gen_blt (label)); + } + + if (size != const0_rtx) + { +#ifdef TARGET_MEM_FUNCTIONS + emit_library_call (memset_libfunc, 0, VOIDmode, 3, + temp, Pmode, const0_rtx, Pmode, size, Pmode); +#else + emit_library_call (bzero_libfunc, 0, VOIDmode, 2, + temp, Pmode, size, Pmode); +#endif + } + if (label) + emit_label (label); + } + } + else if (GET_MODE (temp) == BLKmode) + emit_block_move (target, temp, expr_size (exp), + TYPE_ALIGN (TREE_TYPE (exp)) / BITS_PER_UNIT); + else + emit_move_insn (target, temp); + } + if (dont_return_target) + return temp; + return target; +} + +/* Store the value of constructor EXP into the rtx TARGET. + TARGET is either a REG or a MEM. */ + +static void +store_constructor (exp, target) + tree exp; + rtx target; +{ + tree type = TREE_TYPE (exp); + + /* We know our target cannot conflict, since safe_from_p has been called. */ +#if 0 + /* Don't try copying piece by piece into a hard register + since that is vulnerable to being clobbered by EXP. + Instead, construct in a pseudo register and then copy it all. */ + if (GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER) + { + rtx temp = gen_reg_rtx (GET_MODE (target)); + store_constructor (exp, temp); + emit_move_insn (target, temp); + return; + } +#endif + + if (TREE_CODE (type) == RECORD_TYPE || TREE_CODE (type) == UNION_TYPE) + { + register tree elt; + + /* Inform later passes that the whole union value is dead. */ + if (TREE_CODE (type) == UNION_TYPE) + emit_insn (gen_rtx (CLOBBER, VOIDmode, target)); + + /* If we are building a static constructor into a register, + set the initial value as zero so we can fold the value into + a constant. */ + else if (GET_CODE (target) == REG && TREE_STATIC (exp)) + emit_move_insn (target, const0_rtx); + + /* If the constructor has fewer fields than the structure, + clear the whole structure first. */ + else if (list_length (CONSTRUCTOR_ELTS (exp)) + != list_length (TYPE_FIELDS (type))) + clear_storage (target, int_size_in_bytes (type)); + else + /* Inform later passes that the old value is dead. */ + emit_insn (gen_rtx (CLOBBER, VOIDmode, target)); + + /* Store each element of the constructor into + the corresponding field of TARGET. */ + + for (elt = CONSTRUCTOR_ELTS (exp); elt; elt = TREE_CHAIN (elt)) + { + register tree field = TREE_PURPOSE (elt); + register enum machine_mode mode; + int bitsize; + int bitpos; + int unsignedp; + + /* Just ignore missing fields. + We cleared the whole structure, above, + if any fields are missing. */ + if (field == 0) + continue; + + bitsize = TREE_INT_CST_LOW (DECL_SIZE (field)); + unsignedp = TREE_UNSIGNED (field); + mode = DECL_MODE (field); + if (DECL_BIT_FIELD (field)) + mode = VOIDmode; + + if (TREE_CODE (DECL_FIELD_BITPOS (field)) != INTEGER_CST) + /* ??? This case remains to be written. */ + abort (); + + bitpos = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); + + store_field (target, bitsize, bitpos, mode, TREE_VALUE (elt), + /* The alignment of TARGET is + at least what its type requires. */ + VOIDmode, 0, + TYPE_ALIGN (type) / BITS_PER_UNIT, + int_size_in_bytes (type)); + } + } + else if (TREE_CODE (type) == ARRAY_TYPE) + { + register tree elt; + register int i; + tree domain = TYPE_DOMAIN (type); + HOST_WIDE_INT minelt = TREE_INT_CST_LOW (TYPE_MIN_VALUE (domain)); + HOST_WIDE_INT maxelt = TREE_INT_CST_LOW (TYPE_MAX_VALUE (domain)); + tree elttype = TREE_TYPE (type); + + /* If the constructor has fewer fields than the structure, + clear the whole structure first. Similarly if this this is + static constructor of a non-BLKmode object. */ + + if (list_length (CONSTRUCTOR_ELTS (exp)) < maxelt - minelt + 1 + || (GET_CODE (target) == REG && TREE_STATIC (exp))) + clear_storage (target, int_size_in_bytes (type)); + else + /* Inform later passes that the old value is dead. */ + emit_insn (gen_rtx (CLOBBER, VOIDmode, target)); + + /* Store each element of the constructor into + the corresponding element of TARGET, determined + by counting the elements. */ + for (elt = CONSTRUCTOR_ELTS (exp), i = 0; + elt; + elt = TREE_CHAIN (elt), i++) + { + register enum machine_mode mode; + int bitsize; + int bitpos; + int unsignedp; + + mode = TYPE_MODE (elttype); + bitsize = GET_MODE_BITSIZE (mode); + unsignedp = TREE_UNSIGNED (elttype); + + bitpos = (i * TREE_INT_CST_LOW (TYPE_SIZE (elttype))); + + store_field (target, bitsize, bitpos, mode, TREE_VALUE (elt), + /* The alignment of TARGET is + at least what its type requires. */ + VOIDmode, 0, + TYPE_ALIGN (type) / BITS_PER_UNIT, + int_size_in_bytes (type)); + } + } + + else + abort (); +} + +/* Store the value of EXP (an expression tree) + into a subfield of TARGET which has mode MODE and occupies + BITSIZE bits, starting BITPOS bits from the start of TARGET. + If MODE is VOIDmode, it means that we are storing into a bit-field. + + If VALUE_MODE is VOIDmode, return nothing in particular. + UNSIGNEDP is not used in this case. + + Otherwise, return an rtx for the value stored. This rtx + has mode VALUE_MODE if that is convenient to do. + In this case, UNSIGNEDP must be nonzero if the value is an unsigned type. + + ALIGN is the alignment that TARGET is known to have, measured in bytes. + TOTAL_SIZE is the size in bytes of the structure, or -1 if varying. */ + +static rtx +store_field (target, bitsize, bitpos, mode, exp, value_mode, + unsignedp, align, total_size) + rtx target; + int bitsize, bitpos; + enum machine_mode mode; + tree exp; + enum machine_mode value_mode; + int unsignedp; + int align; + int total_size; +{ + HOST_WIDE_INT width_mask = 0; + + if (bitsize < HOST_BITS_PER_WIDE_INT) + width_mask = ((HOST_WIDE_INT) 1 << bitsize) - 1; + + /* If we are storing into an unaligned field of an aligned union that is + in a register, we may have the mode of TARGET being an integer mode but + MODE == BLKmode. In that case, get an aligned object whose size and + alignment are the same as TARGET and store TARGET into it (we can avoid + the store if the field being stored is the entire width of TARGET). Then + call ourselves recursively to store the field into a BLKmode version of + that object. Finally, load from the object into TARGET. This is not + very efficient in general, but should only be slightly more expensive + than the otherwise-required unaligned accesses. Perhaps this can be + cleaned up later. */ + + if (mode == BLKmode + && (GET_CODE (target) == REG || GET_CODE (target) == SUBREG)) + { + rtx object = assign_stack_temp (GET_MODE (target), + GET_MODE_SIZE (GET_MODE (target)), 0); + rtx blk_object = copy_rtx (object); + + PUT_MODE (blk_object, BLKmode); + + if (bitsize != GET_MODE_BITSIZE (GET_MODE (target))) + emit_move_insn (object, target); + + store_field (blk_object, bitsize, bitpos, mode, exp, VOIDmode, 0, + align, total_size); + + emit_move_insn (target, object); + + return target; + } + + /* If the structure is in a register or if the component + is a bit field, we cannot use addressing to access it. + Use bit-field techniques or SUBREG to store in it. */ + + if (mode == VOIDmode + || (mode != BLKmode && ! direct_store[(int) mode]) + || GET_CODE (target) == REG + || GET_CODE (target) == SUBREG) + { + rtx temp = expand_expr (exp, NULL_RTX, VOIDmode, 0); + /* Store the value in the bitfield. */ + store_bit_field (target, bitsize, bitpos, mode, temp, align, total_size); + if (value_mode != VOIDmode) + { + /* The caller wants an rtx for the value. */ + /* If possible, avoid refetching from the bitfield itself. */ + if (width_mask != 0 + && ! (GET_CODE (target) == MEM && MEM_VOLATILE_P (target))) + { + tree count; + enum machine_mode tmode; + + if (unsignedp) + return expand_and (temp, GEN_INT (width_mask), NULL_RTX); + tmode = GET_MODE (temp); + if (tmode == VOIDmode) + tmode = value_mode; + count = build_int_2 (GET_MODE_BITSIZE (tmode) - bitsize, 0); + temp = expand_shift (LSHIFT_EXPR, tmode, temp, count, 0, 0); + return expand_shift (RSHIFT_EXPR, tmode, temp, count, 0, 0); + } + return extract_bit_field (target, bitsize, bitpos, unsignedp, + NULL_RTX, value_mode, 0, align, + total_size); + } + return const0_rtx; + } + else + { + rtx addr = XEXP (target, 0); + rtx to_rtx; + + /* If a value is wanted, it must be the lhs; + so make the address stable for multiple use. */ + + if (value_mode != VOIDmode && GET_CODE (addr) != REG + && ! CONSTANT_ADDRESS_P (addr) + /* A frame-pointer reference is already stable. */ + && ! (GET_CODE (addr) == PLUS + && GET_CODE (XEXP (addr, 1)) == CONST_INT + && (XEXP (addr, 0) == virtual_incoming_args_rtx + || XEXP (addr, 0) == virtual_stack_vars_rtx))) + addr = copy_to_reg (addr); + + /* Now build a reference to just the desired component. */ + + to_rtx = change_address (target, mode, + plus_constant (addr, (bitpos / BITS_PER_UNIT))); + MEM_IN_STRUCT_P (to_rtx) = 1; + + return store_expr (exp, to_rtx, value_mode != VOIDmode); + } +} + +/* Given an expression EXP that may be a COMPONENT_REF, a BIT_FIELD_REF, + or an ARRAY_REF, look for nested COMPONENT_REFs, BIT_FIELD_REFs, or + ARRAY_REFs and find the ultimate containing object, which we return. + + We set *PBITSIZE to the size in bits that we want, *PBITPOS to the + bit position, and *PUNSIGNEDP to the signedness of the field. + If the position of the field is variable, we store a tree + giving the variable offset (in units) in *POFFSET. + This offset is in addition to the bit position. + If the position is not variable, we store 0 in *POFFSET. + + If any of the extraction expressions is volatile, + we store 1 in *PVOLATILEP. Otherwise we don't change that. + + If the field is a bit-field, *PMODE is set to VOIDmode. Otherwise, it + is a mode that can be used to access the field. In that case, *PBITSIZE + is redundant. + + If the field describes a variable-sized object, *PMODE is set to + VOIDmode and *PBITSIZE is set to -1. An access cannot be made in + this case, but the address of the object can be found. */ + +tree +get_inner_reference (exp, pbitsize, pbitpos, poffset, pmode, + punsignedp, pvolatilep) + tree exp; + int *pbitsize; + int *pbitpos; + tree *poffset; + enum machine_mode *pmode; + int *punsignedp; + int *pvolatilep; +{ + tree size_tree = 0; + enum machine_mode mode = VOIDmode; + tree offset = integer_zero_node; + + if (TREE_CODE (exp) == COMPONENT_REF) + { + size_tree = DECL_SIZE (TREE_OPERAND (exp, 1)); + if (! DECL_BIT_FIELD (TREE_OPERAND (exp, 1))) + mode = DECL_MODE (TREE_OPERAND (exp, 1)); + *punsignedp = TREE_UNSIGNED (TREE_OPERAND (exp, 1)); + } + else if (TREE_CODE (exp) == BIT_FIELD_REF) + { + size_tree = TREE_OPERAND (exp, 1); + *punsignedp = TREE_UNSIGNED (exp); + } + else + { + mode = TYPE_MODE (TREE_TYPE (exp)); + *pbitsize = GET_MODE_BITSIZE (mode); + *punsignedp = TREE_UNSIGNED (TREE_TYPE (exp)); + } + + if (size_tree) + { + if (TREE_CODE (size_tree) != INTEGER_CST) + mode = BLKmode, *pbitsize = -1; + else + *pbitsize = TREE_INT_CST_LOW (size_tree); + } + + /* Compute cumulative bit-offset for nested component-refs and array-refs, + and find the ultimate containing object. */ + + *pbitpos = 0; + + while (1) + { + if (TREE_CODE (exp) == COMPONENT_REF || TREE_CODE (exp) == BIT_FIELD_REF) + { + tree pos = (TREE_CODE (exp) == COMPONENT_REF + ? DECL_FIELD_BITPOS (TREE_OPERAND (exp, 1)) + : TREE_OPERAND (exp, 2)); + + /* If this field hasn't been filled in yet, don't go + past it. This should only happen when folding expressions + made during type construction. */ + if (pos == 0) + break; + + if (TREE_CODE (pos) == PLUS_EXPR) + { + tree constant, var; + if (TREE_CODE (TREE_OPERAND (pos, 0)) == INTEGER_CST) + { + constant = TREE_OPERAND (pos, 0); + var = TREE_OPERAND (pos, 1); + } + else if (TREE_CODE (TREE_OPERAND (pos, 1)) == INTEGER_CST) + { + constant = TREE_OPERAND (pos, 1); + var = TREE_OPERAND (pos, 0); + } + else + abort (); + + *pbitpos += TREE_INT_CST_LOW (constant); + offset = size_binop (PLUS_EXPR, offset, + size_binop (FLOOR_DIV_EXPR, var, + size_int (BITS_PER_UNIT))); + } + else if (TREE_CODE (pos) == INTEGER_CST) + *pbitpos += TREE_INT_CST_LOW (pos); + else + { + /* Assume here that the offset is a multiple of a unit. + If not, there should be an explicitly added constant. */ + offset = size_binop (PLUS_EXPR, offset, + size_binop (FLOOR_DIV_EXPR, pos, + size_int (BITS_PER_UNIT))); + } + } + + else if (TREE_CODE (exp) == ARRAY_REF) + { + /* This code is based on the code in case ARRAY_REF in expand_expr + below. We assume here that the size of an array element is + always an integral multiple of BITS_PER_UNIT. */ + + tree index = TREE_OPERAND (exp, 1); + tree domain = TYPE_DOMAIN (TREE_TYPE (TREE_OPERAND (exp, 0))); + tree low_bound + = domain ? TYPE_MIN_VALUE (domain) : integer_zero_node; + tree index_type = TREE_TYPE (index); + + if (! integer_zerop (low_bound)) + index = fold (build (MINUS_EXPR, index_type, index, low_bound)); + + if (TYPE_PRECISION (index_type) != POINTER_SIZE) + { + index = convert (type_for_size (POINTER_SIZE, 0), index); + index_type = TREE_TYPE (index); + } + + index = fold (build (MULT_EXPR, index_type, index, + TYPE_SIZE (TREE_TYPE (exp)))); + + if (TREE_CODE (index) == INTEGER_CST + && TREE_INT_CST_HIGH (index) == 0) + *pbitpos += TREE_INT_CST_LOW (index); + else + offset = size_binop (PLUS_EXPR, offset, + size_binop (FLOOR_DIV_EXPR, index, + size_int (BITS_PER_UNIT))); + } + else if (TREE_CODE (exp) != NON_LVALUE_EXPR + && ! ((TREE_CODE (exp) == NOP_EXPR + || TREE_CODE (exp) == CONVERT_EXPR) + && (TYPE_MODE (TREE_TYPE (exp)) + == TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))))) + break; + + /* If any reference in the chain is volatile, the effect is volatile. */ + if (TREE_THIS_VOLATILE (exp)) + *pvolatilep = 1; + exp = TREE_OPERAND (exp, 0); + } + + /* If this was a bit-field, see if there is a mode that allows direct + access in case EXP is in memory. */ + if (mode == VOIDmode && *pbitsize != 0 && *pbitpos % *pbitsize == 0) + { + mode = mode_for_size (*pbitsize, MODE_INT, 0); + if (mode == BLKmode) + mode = VOIDmode; + } + + if (integer_zerop (offset)) + offset = 0; + + *pmode = mode; + *poffset = offset; +#if 0 + /* We aren't finished fixing the callers to really handle nonzero offset. */ + if (offset != 0) + abort (); +#endif + + return exp; +} + +/* Given an rtx VALUE that may contain additions and multiplications, + return an equivalent value that just refers to a register or memory. + This is done by generating instructions to perform the arithmetic + and returning a pseudo-register containing the value. + + The returned value may be a REG, SUBREG, MEM or constant. */ + +rtx +force_operand (value, target) + rtx value, target; +{ + register optab binoptab = 0; + /* Use a temporary to force order of execution of calls to + `force_operand'. */ + rtx tmp; + register rtx op2; + /* Use subtarget as the target for operand 0 of a binary operation. */ + register rtx subtarget = (target != 0 && GET_CODE (target) == REG ? target : 0); + + if (GET_CODE (value) == PLUS) + binoptab = add_optab; + else if (GET_CODE (value) == MINUS) + binoptab = sub_optab; + else if (GET_CODE (value) == MULT) + { + op2 = XEXP (value, 1); + if (!CONSTANT_P (op2) + && !(GET_CODE (op2) == REG && op2 != subtarget)) + subtarget = 0; + tmp = force_operand (XEXP (value, 0), subtarget); + return expand_mult (GET_MODE (value), tmp, + force_operand (op2, NULL_RTX), + target, 0); + } + + if (binoptab) + { + op2 = XEXP (value, 1); + if (!CONSTANT_P (op2) + && !(GET_CODE (op2) == REG && op2 != subtarget)) + subtarget = 0; + if (binoptab == sub_optab && GET_CODE (op2) == CONST_INT) + { + binoptab = add_optab; + op2 = negate_rtx (GET_MODE (value), op2); + } + + /* Check for an addition with OP2 a constant integer and our first + operand a PLUS of a virtual register and something else. In that + case, we want to emit the sum of the virtual register and the + constant first and then add the other value. This allows virtual + register instantiation to simply modify the constant rather than + creating another one around this addition. */ + if (binoptab == add_optab && GET_CODE (op2) == CONST_INT + && GET_CODE (XEXP (value, 0)) == PLUS + && GET_CODE (XEXP (XEXP (value, 0), 0)) == REG + && REGNO (XEXP (XEXP (value, 0), 0)) >= FIRST_VIRTUAL_REGISTER + && REGNO (XEXP (XEXP (value, 0), 0)) <= LAST_VIRTUAL_REGISTER) + { + rtx temp = expand_binop (GET_MODE (value), binoptab, + XEXP (XEXP (value, 0), 0), op2, + subtarget, 0, OPTAB_LIB_WIDEN); + return expand_binop (GET_MODE (value), binoptab, temp, + force_operand (XEXP (XEXP (value, 0), 1), 0), + target, 0, OPTAB_LIB_WIDEN); + } + + tmp = force_operand (XEXP (value, 0), subtarget); + return expand_binop (GET_MODE (value), binoptab, tmp, + force_operand (op2, NULL_RTX), + target, 0, OPTAB_LIB_WIDEN); + /* We give UNSIGNEDP = 0 to expand_binop + because the only operations we are expanding here are signed ones. */ + } + return value; +} + +/* Subroutine of expand_expr: + save the non-copied parts (LIST) of an expr (LHS), and return a list + which can restore these values to their previous values, + should something modify their storage. */ + +static tree +save_noncopied_parts (lhs, list) + tree lhs; + tree list; +{ + tree tail; + tree parts = 0; + + for (tail = list; tail; tail = TREE_CHAIN (tail)) + if (TREE_CODE (TREE_VALUE (tail)) == TREE_LIST) + parts = chainon (parts, save_noncopied_parts (lhs, TREE_VALUE (tail))); + else + { + tree part = TREE_VALUE (tail); + tree part_type = TREE_TYPE (part); + tree to_be_saved = build (COMPONENT_REF, part_type, lhs, part); + rtx target = assign_stack_temp (TYPE_MODE (part_type), + int_size_in_bytes (part_type), 0); + if (! memory_address_p (TYPE_MODE (part_type), XEXP (target, 0))) + target = change_address (target, TYPE_MODE (part_type), NULL_RTX); + parts = tree_cons (to_be_saved, + build (RTL_EXPR, part_type, NULL_TREE, + (tree) target), + parts); + store_expr (TREE_PURPOSE (parts), RTL_EXPR_RTL (TREE_VALUE (parts)), 0); + } + return parts; +} + +/* Subroutine of expand_expr: + record the non-copied parts (LIST) of an expr (LHS), and return a list + which specifies the initial values of these parts. */ + +static tree +init_noncopied_parts (lhs, list) + tree lhs; + tree list; +{ + tree tail; + tree parts = 0; + + for (tail = list; tail; tail = TREE_CHAIN (tail)) + if (TREE_CODE (TREE_VALUE (tail)) == TREE_LIST) + parts = chainon (parts, init_noncopied_parts (lhs, TREE_VALUE (tail))); + else + { + tree part = TREE_VALUE (tail); + tree part_type = TREE_TYPE (part); + tree to_be_initialized = build (COMPONENT_REF, part_type, lhs, part); + parts = tree_cons (TREE_PURPOSE (tail), to_be_initialized, parts); + } + return parts; +} + +/* Subroutine of expand_expr: return nonzero iff there is no way that + EXP can reference X, which is being modified. */ + +static int +safe_from_p (x, exp) + rtx x; + tree exp; +{ + rtx exp_rtl = 0; + int i, nops; + + if (x == 0) + return 1; + + /* If this is a subreg of a hard register, declare it unsafe, otherwise, + find the underlying pseudo. */ + if (GET_CODE (x) == SUBREG) + { + x = SUBREG_REG (x); + if (GET_CODE (x) == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) + return 0; + } + + /* If X is a location in the outgoing argument area, it is always safe. */ + if (GET_CODE (x) == MEM + && (XEXP (x, 0) == virtual_outgoing_args_rtx + || (GET_CODE (XEXP (x, 0)) == PLUS + && XEXP (XEXP (x, 0), 0) == virtual_outgoing_args_rtx))) + return 1; + + switch (TREE_CODE_CLASS (TREE_CODE (exp))) + { + case 'd': + exp_rtl = DECL_RTL (exp); + break; + + case 'c': + return 1; + + case 'x': + if (TREE_CODE (exp) == TREE_LIST) + return ((TREE_VALUE (exp) == 0 + || safe_from_p (x, TREE_VALUE (exp))) + && (TREE_CHAIN (exp) == 0 + || safe_from_p (x, TREE_CHAIN (exp)))); + else + return 0; + + case '1': + return safe_from_p (x, TREE_OPERAND (exp, 0)); + + case '2': + case '<': + return (safe_from_p (x, TREE_OPERAND (exp, 0)) + && safe_from_p (x, TREE_OPERAND (exp, 1))); + + case 'e': + case 'r': + /* Now do code-specific tests. EXP_RTL is set to any rtx we find in + the expression. If it is set, we conflict iff we are that rtx or + both are in memory. Otherwise, we check all operands of the + expression recursively. */ + + switch (TREE_CODE (exp)) + { + case ADDR_EXPR: + return staticp (TREE_OPERAND (exp, 0)); + + case INDIRECT_REF: + if (GET_CODE (x) == MEM) + return 0; + break; + + case CALL_EXPR: + exp_rtl = CALL_EXPR_RTL (exp); + if (exp_rtl == 0) + { + /* Assume that the call will clobber all hard registers and + all of memory. */ + if ((GET_CODE (x) == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) + || GET_CODE (x) == MEM) + return 0; + } + + break; + + case RTL_EXPR: + exp_rtl = RTL_EXPR_RTL (exp); + if (exp_rtl == 0) + /* We don't know what this can modify. */ + return 0; + + break; + + case WITH_CLEANUP_EXPR: + exp_rtl = RTL_EXPR_RTL (exp); + break; + + case SAVE_EXPR: + exp_rtl = SAVE_EXPR_RTL (exp); + break; + + case BIND_EXPR: + /* The only operand we look at is operand 1. The rest aren't + part of the expression. */ + return safe_from_p (x, TREE_OPERAND (exp, 1)); + + case METHOD_CALL_EXPR: + /* This takes a rtx argument, but shouldn't appear here. */ + abort (); + } + + /* If we have an rtx, we do not need to scan our operands. */ + if (exp_rtl) + break; + + nops = tree_code_length[(int) TREE_CODE (exp)]; + for (i = 0; i < nops; i++) + if (TREE_OPERAND (exp, i) != 0 + && ! safe_from_p (x, TREE_OPERAND (exp, i))) + return 0; + } + + /* If we have an rtl, find any enclosed object. Then see if we conflict + with it. */ + if (exp_rtl) + { + if (GET_CODE (exp_rtl) == SUBREG) + { + exp_rtl = SUBREG_REG (exp_rtl); + if (GET_CODE (exp_rtl) == REG + && REGNO (exp_rtl) < FIRST_PSEUDO_REGISTER) + return 0; + } + + /* If the rtl is X, then it is not safe. Otherwise, it is unless both + are memory and EXP is not readonly. */ + return ! (rtx_equal_p (x, exp_rtl) + || (GET_CODE (x) == MEM && GET_CODE (exp_rtl) == MEM + && ! TREE_READONLY (exp))); + } + + /* If we reach here, it is safe. */ + return 1; +} + +/* Subroutine of expand_expr: return nonzero iff EXP is an + expression whose type is statically determinable. */ + +static int +fixed_type_p (exp) + tree exp; +{ + if (TREE_CODE (exp) == PARM_DECL + || TREE_CODE (exp) == VAR_DECL + || TREE_CODE (exp) == CALL_EXPR || TREE_CODE (exp) == TARGET_EXPR + || TREE_CODE (exp) == COMPONENT_REF + || TREE_CODE (exp) == ARRAY_REF) + return 1; + return 0; +} + +/* expand_expr: generate code for computing expression EXP. + An rtx for the computed value is returned. The value is never null. + In the case of a void EXP, const0_rtx is returned. + + The value may be stored in TARGET if TARGET is nonzero. + TARGET is just a suggestion; callers must assume that + the rtx returned may not be the same as TARGET. + + If TARGET is CONST0_RTX, it means that the value will be ignored. + + If TMODE is not VOIDmode, it suggests generating the + result in mode TMODE. But this is done only when convenient. + Otherwise, TMODE is ignored and the value generated in its natural mode. + TMODE is just a suggestion; callers must assume that + the rtx returned may not have mode TMODE. + + EXPAND_CONST_ADDRESS says that it is okay to return a MEM + with a constant address even if that address is not normally legitimate. + EXPAND_INITIALIZER and EXPAND_SUM also have this effect. + + If MODIFIER is EXPAND_SUM then when EXP is an addition + we can return an rtx of the form (MULT (REG ...) (CONST_INT ...)) + or a nest of (PLUS ...) and (MINUS ...) where the terms are + products as above, or REG or MEM, or constant. + Ordinarily in such cases we would output mul or add instructions + and then return a pseudo reg containing the sum. + + EXPAND_INITIALIZER is much like EXPAND_SUM except that + it also marks a label as absolutely required (it can't be dead). + It also makes a ZERO_EXTEND or SIGN_EXTEND instead of emitting extend insns. + This is used for outputting expressions used in initializers. */ + +rtx +expand_expr (exp, target, tmode, modifier) + register tree exp; + rtx target; + enum machine_mode tmode; + enum expand_modifier modifier; +{ + register rtx op0, op1, temp; + tree type = TREE_TYPE (exp); + int unsignedp = TREE_UNSIGNED (type); + register enum machine_mode mode = TYPE_MODE (type); + register enum tree_code code = TREE_CODE (exp); + optab this_optab; + /* Use subtarget as the target for operand 0 of a binary operation. */ + rtx subtarget = (target != 0 && GET_CODE (target) == REG ? target : 0); + rtx original_target = target; + int ignore = target == const0_rtx; + tree context; + + /* Don't use hard regs as subtargets, because the combiner + can only handle pseudo regs. */ + if (subtarget && REGNO (subtarget) < FIRST_PSEUDO_REGISTER) + subtarget = 0; + /* Avoid subtargets inside loops, + since they hide some invariant expressions. */ + if (preserve_subexpressions_p ()) + subtarget = 0; + + if (ignore) target = 0, original_target = 0; + + /* If will do cse, generate all results into pseudo registers + since 1) that allows cse to find more things + and 2) otherwise cse could produce an insn the machine + cannot support. */ + + if (! cse_not_expected && mode != BLKmode && target + && (GET_CODE (target) != REG || REGNO (target) < FIRST_PSEUDO_REGISTER)) + target = subtarget; + + /* Ensure we reference a volatile object even if value is ignored. */ + if (ignore && TREE_THIS_VOLATILE (exp) + && TREE_CODE (exp) != FUNCTION_DECL + && mode != VOIDmode && mode != BLKmode) + { + target = gen_reg_rtx (mode); + temp = expand_expr (exp, target, VOIDmode, modifier); + if (temp != target) + emit_move_insn (target, temp); + return target; + } + + switch (code) + { + case LABEL_DECL: + { + tree function = decl_function_context (exp); + /* Handle using a label in a containing function. */ + if (function != current_function_decl && function != 0) + { + struct function *p = find_function_data (function); + /* Allocate in the memory associated with the function + that the label is in. */ + push_obstacks (p->function_obstack, + p->function_maybepermanent_obstack); + + p->forced_labels = gen_rtx (EXPR_LIST, VOIDmode, + label_rtx (exp), p->forced_labels); + pop_obstacks (); + } + else if (modifier == EXPAND_INITIALIZER) + forced_labels = gen_rtx (EXPR_LIST, VOIDmode, + label_rtx (exp), forced_labels); + temp = gen_rtx (MEM, FUNCTION_MODE, + gen_rtx (LABEL_REF, Pmode, label_rtx (exp))); + if (function != current_function_decl && function != 0) + LABEL_REF_NONLOCAL_P (XEXP (temp, 0)) = 1; + return temp; + } + + case PARM_DECL: + if (DECL_RTL (exp) == 0) + { + error_with_decl (exp, "prior parameter's size depends on `%s'"); + return CONST0_RTX (mode); + } + + case FUNCTION_DECL: + case VAR_DECL: + case RESULT_DECL: + if (DECL_RTL (exp) == 0) + abort (); + /* Ensure variable marked as used + even if it doesn't go through a parser. */ + TREE_USED (exp) = 1; + /* Handle variables inherited from containing functions. */ + context = decl_function_context (exp); + + /* We treat inline_function_decl as an alias for the current function + because that is the inline function whose vars, types, etc. + are being merged into the current function. + See expand_inline_function. */ + if (context != 0 && context != current_function_decl + && context != inline_function_decl + /* If var is static, we don't need a static chain to access it. */ + && ! (GET_CODE (DECL_RTL (exp)) == MEM + && CONSTANT_P (XEXP (DECL_RTL (exp), 0)))) + { + rtx addr; + + /* Mark as non-local and addressable. */ + DECL_NONLOCAL (exp) = 1; + mark_addressable (exp); + if (GET_CODE (DECL_RTL (exp)) != MEM) + abort (); + addr = XEXP (DECL_RTL (exp), 0); + if (GET_CODE (addr) == MEM) + addr = gen_rtx (MEM, Pmode, fix_lexical_addr (XEXP (addr, 0), exp)); + else + addr = fix_lexical_addr (addr, exp); + return change_address (DECL_RTL (exp), mode, addr); + } + + /* This is the case of an array whose size is to be determined + from its initializer, while the initializer is still being parsed. + See expand_decl. */ + if (GET_CODE (DECL_RTL (exp)) == MEM + && GET_CODE (XEXP (DECL_RTL (exp), 0)) == REG) + return change_address (DECL_RTL (exp), GET_MODE (DECL_RTL (exp)), + XEXP (DECL_RTL (exp), 0)); + if (GET_CODE (DECL_RTL (exp)) == MEM + && modifier != EXPAND_CONST_ADDRESS + && modifier != EXPAND_SUM + && modifier != EXPAND_INITIALIZER) + { + /* DECL_RTL probably contains a constant address. + On RISC machines where a constant address isn't valid, + make some insns to get that address into a register. */ + if (!memory_address_p (DECL_MODE (exp), XEXP (DECL_RTL (exp), 0)) + || (flag_force_addr + && CONSTANT_ADDRESS_P (XEXP (DECL_RTL (exp), 0)))) + return change_address (DECL_RTL (exp), VOIDmode, + copy_rtx (XEXP (DECL_RTL (exp), 0))); + } + + /* If the mode of DECL_RTL does not match that of the decl, it + must be a promoted value. We return a SUBREG of the wanted mode, + but mark it so that we know that it was already extended. */ + + if (GET_CODE (DECL_RTL (exp)) == REG + && GET_MODE (DECL_RTL (exp)) != mode) + { + enum machine_mode decl_mode = DECL_MODE (exp); + + /* Get the signedness used for this variable. Ensure we get the + same mode we got when the variable was declared. */ + + PROMOTE_MODE (decl_mode, unsignedp, type); + + if (decl_mode != GET_MODE (DECL_RTL (exp))) + abort (); + + temp = gen_rtx (SUBREG, mode, DECL_RTL (exp), 0); + SUBREG_PROMOTED_VAR_P (temp) = 1; + SUBREG_PROMOTED_UNSIGNED_P (temp) = unsignedp; + return temp; + } + + return DECL_RTL (exp); + + case INTEGER_CST: + return immed_double_const (TREE_INT_CST_LOW (exp), + TREE_INT_CST_HIGH (exp), + mode); + + case CONST_DECL: + return expand_expr (DECL_INITIAL (exp), target, VOIDmode, 0); + + case REAL_CST: + /* If optimized, generate immediate CONST_DOUBLE + which will be turned into memory by reload if necessary. + + We used to force a register so that loop.c could see it. But + this does not allow gen_* patterns to perform optimizations with + the constants. It also produces two insns in cases like "x = 1.0;". + On most machines, floating-point constants are not permitted in + many insns, so we'd end up copying it to a register in any case. + + Now, we do the copying in expand_binop, if appropriate. */ + return immed_real_const (exp); + + case COMPLEX_CST: + case STRING_CST: + if (! TREE_CST_RTL (exp)) + output_constant_def (exp); + + /* TREE_CST_RTL probably contains a constant address. + On RISC machines where a constant address isn't valid, + make some insns to get that address into a register. */ + if (GET_CODE (TREE_CST_RTL (exp)) == MEM + && modifier != EXPAND_CONST_ADDRESS + && modifier != EXPAND_INITIALIZER + && modifier != EXPAND_SUM + && !memory_address_p (mode, XEXP (TREE_CST_RTL (exp), 0))) + return change_address (TREE_CST_RTL (exp), VOIDmode, + copy_rtx (XEXP (TREE_CST_RTL (exp), 0))); + return TREE_CST_RTL (exp); + + case SAVE_EXPR: + context = decl_function_context (exp); + /* We treat inline_function_decl as an alias for the current function + because that is the inline function whose vars, types, etc. + are being merged into the current function. + See expand_inline_function. */ + if (context == current_function_decl || context == inline_function_decl) + context = 0; + + /* If this is non-local, handle it. */ + if (context) + { + temp = SAVE_EXPR_RTL (exp); + if (temp && GET_CODE (temp) == REG) + { + put_var_into_stack (exp); + temp = SAVE_EXPR_RTL (exp); + } + if (temp == 0 || GET_CODE (temp) != MEM) + abort (); + return change_address (temp, mode, + fix_lexical_addr (XEXP (temp, 0), exp)); + } + if (SAVE_EXPR_RTL (exp) == 0) + { + if (mode == BLKmode) + temp + = assign_stack_temp (mode, + int_size_in_bytes (TREE_TYPE (exp)), 0); + else + { + enum machine_mode var_mode = mode; + + if (TREE_CODE (type) == INTEGER_TYPE + || TREE_CODE (type) == ENUMERAL_TYPE + || TREE_CODE (type) == BOOLEAN_TYPE + || TREE_CODE (type) == CHAR_TYPE + || TREE_CODE (type) == REAL_TYPE + || TREE_CODE (type) == POINTER_TYPE + || TREE_CODE (type) == OFFSET_TYPE) + { + PROMOTE_MODE (var_mode, unsignedp, type); + } + + temp = gen_reg_rtx (var_mode); + } + + SAVE_EXPR_RTL (exp) = temp; + if (!optimize && GET_CODE (temp) == REG) + save_expr_regs = gen_rtx (EXPR_LIST, VOIDmode, temp, + save_expr_regs); + + /* If the mode of TEMP does not match that of the expression, it + must be a promoted value. We pass store_expr a SUBREG of the + wanted mode but mark it so that we know that it was already + extended. Note that `unsignedp' was modified above in + this case. */ + + if (GET_CODE (temp) == REG && GET_MODE (temp) != mode) + { + temp = gen_rtx (SUBREG, mode, SAVE_EXPR_RTL (exp), 0); + SUBREG_PROMOTED_VAR_P (temp) = 1; + SUBREG_PROMOTED_UNSIGNED_P (temp) = unsignedp; + } + + store_expr (TREE_OPERAND (exp, 0), temp, 0); + } + + /* If the mode of SAVE_EXPR_RTL does not match that of the expression, it + must be a promoted value. We return a SUBREG of the wanted mode, + but mark it so that we know that it was already extended. Note + that `unsignedp' was modified above in this case. */ + + if (GET_CODE (SAVE_EXPR_RTL (exp)) == REG + && GET_MODE (SAVE_EXPR_RTL (exp)) != mode) + { + temp = gen_rtx (SUBREG, mode, SAVE_EXPR_RTL (exp), 0); + SUBREG_PROMOTED_VAR_P (temp) = 1; + SUBREG_PROMOTED_UNSIGNED_P (temp) = unsignedp; + return temp; + } + + return SAVE_EXPR_RTL (exp); + + case EXIT_EXPR: + /* Exit the current loop if the body-expression is true. */ + { + rtx label = gen_label_rtx (); + do_jump (TREE_OPERAND (exp, 0), label, NULL_RTX); + expand_exit_loop (NULL_PTR); + emit_label (label); + } + return const0_rtx; + + case LOOP_EXPR: + expand_start_loop (1); + expand_expr_stmt (TREE_OPERAND (exp, 0)); + expand_end_loop (); + + return const0_rtx; + + case BIND_EXPR: + { + tree vars = TREE_OPERAND (exp, 0); + int vars_need_expansion = 0; + + /* Need to open a binding contour here because + if there are any cleanups they most be contained here. */ + expand_start_bindings (0); + + /* Mark the corresponding BLOCK for output in its proper place. */ + if (TREE_OPERAND (exp, 2) != 0 + && ! TREE_USED (TREE_OPERAND (exp, 2))) + insert_block (TREE_OPERAND (exp, 2)); + + /* If VARS have not yet been expanded, expand them now. */ + while (vars) + { + if (DECL_RTL (vars) == 0) + { + vars_need_expansion = 1; + expand_decl (vars); + } + expand_decl_init (vars); + vars = TREE_CHAIN (vars); + } + + temp = expand_expr (TREE_OPERAND (exp, 1), target, tmode, modifier); + + expand_end_bindings (TREE_OPERAND (exp, 0), 0, 0); + + return temp; + } + + case RTL_EXPR: + if (RTL_EXPR_SEQUENCE (exp) == const0_rtx) + abort (); + emit_insns (RTL_EXPR_SEQUENCE (exp)); + RTL_EXPR_SEQUENCE (exp) = const0_rtx; + return RTL_EXPR_RTL (exp); + + case CONSTRUCTOR: + /* All elts simple constants => refer to a constant in memory. But + if this is a non-BLKmode mode, let it store a field at a time + since that should make a CONST_INT or CONST_DOUBLE when we + fold. */ + if (TREE_STATIC (exp) && (mode == BLKmode || TREE_ADDRESSABLE (exp))) + { + rtx constructor = output_constant_def (exp); + if (modifier != EXPAND_CONST_ADDRESS + && modifier != EXPAND_INITIALIZER + && modifier != EXPAND_SUM + && !memory_address_p (GET_MODE (constructor), + XEXP (constructor, 0))) + constructor = change_address (constructor, VOIDmode, + XEXP (constructor, 0)); + return constructor; + } + + if (ignore) + { + tree elt; + for (elt = CONSTRUCTOR_ELTS (exp); elt; elt = TREE_CHAIN (elt)) + expand_expr (TREE_VALUE (elt), const0_rtx, VOIDmode, 0); + return const0_rtx; + } + else + { + if (target == 0 || ! safe_from_p (target, exp)) + { + if (mode != BLKmode && ! TREE_ADDRESSABLE (exp)) + target = gen_reg_rtx (mode); + else + { + enum tree_code c = TREE_CODE (type); + target + = assign_stack_temp (mode, int_size_in_bytes (type), 0); + if (c == RECORD_TYPE || c == UNION_TYPE + || c == QUAL_UNION_TYPE || c == ARRAY_TYPE) + MEM_IN_STRUCT_P (target) = 1; + } + } + store_constructor (exp, target); + return target; + } + + case INDIRECT_REF: + { + tree exp1 = TREE_OPERAND (exp, 0); + tree exp2; + + /* A SAVE_EXPR as the address in an INDIRECT_EXPR is generated + for *PTR += ANYTHING where PTR is put inside the SAVE_EXPR. + This code has the same general effect as simply doing + expand_expr on the save expr, except that the expression PTR + is computed for use as a memory address. This means different + code, suitable for indexing, may be generated. */ + if (TREE_CODE (exp1) == SAVE_EXPR + && SAVE_EXPR_RTL (exp1) == 0 + && TREE_CODE (exp2 = TREE_OPERAND (exp1, 0)) != ERROR_MARK + && TYPE_MODE (TREE_TYPE (exp1)) == Pmode + && TYPE_MODE (TREE_TYPE (exp2)) == Pmode) + { + temp = expand_expr (TREE_OPERAND (exp1, 0), NULL_RTX, + VOIDmode, EXPAND_SUM); + op0 = memory_address (mode, temp); + op0 = copy_all_regs (op0); + SAVE_EXPR_RTL (exp1) = op0; + } + else + { + op0 = expand_expr (exp1, NULL_RTX, VOIDmode, EXPAND_SUM); + op0 = memory_address (mode, op0); + } + + temp = gen_rtx (MEM, mode, op0); + /* If address was computed by addition, + mark this as an element of an aggregate. */ + if (TREE_CODE (TREE_OPERAND (exp, 0)) == PLUS_EXPR + || (TREE_CODE (TREE_OPERAND (exp, 0)) == SAVE_EXPR + && TREE_CODE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0)) == PLUS_EXPR) + || TREE_CODE (TREE_TYPE (exp)) == ARRAY_TYPE + || TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (exp)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (exp)) == QUAL_UNION_TYPE + || (TREE_CODE (exp1) == ADDR_EXPR + && (exp2 = TREE_OPERAND (exp1, 0)) + && (TREE_CODE (TREE_TYPE (exp2)) == ARRAY_TYPE + || TREE_CODE (TREE_TYPE (exp2)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (exp2)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (exp2)) == QUAL_UNION_TYPE))) + MEM_IN_STRUCT_P (temp) = 1; + MEM_VOLATILE_P (temp) = TREE_THIS_VOLATILE (exp); +#if 0 /* It is incorrect to set RTX_UNCHANGING_P here, because the fact that + a location is accessed through a pointer to const does not mean + that the value there can never change. */ + RTX_UNCHANGING_P (temp) = TREE_READONLY (exp); +#endif + return temp; + } + + case ARRAY_REF: + if (TREE_CODE (TREE_TYPE (TREE_OPERAND (exp, 0))) != ARRAY_TYPE) + abort (); + + { + tree array = TREE_OPERAND (exp, 0); + tree domain = TYPE_DOMAIN (TREE_TYPE (array)); + tree low_bound = domain ? TYPE_MIN_VALUE (domain) : integer_zero_node; + tree index = TREE_OPERAND (exp, 1); + tree index_type = TREE_TYPE (index); + int i; + + /* Optimize the special-case of a zero lower bound. */ + if (! integer_zerop (low_bound)) + index = fold (build (MINUS_EXPR, index_type, index, low_bound)); + + if (TREE_CODE (index) != INTEGER_CST + || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) + { + /* Nonconstant array index or nonconstant element size. + Generate the tree for *(&array+index) and expand that, + except do it in a language-independent way + and don't complain about non-lvalue arrays. + `mark_addressable' should already have been called + for any array for which this case will be reached. */ + + /* Don't forget the const or volatile flag from the array + element. */ + tree variant_type = build_type_variant (type, + TREE_READONLY (exp), + TREE_THIS_VOLATILE (exp)); + tree array_adr = build1 (ADDR_EXPR, + build_pointer_type (variant_type), array); + tree elt; + + /* Convert the integer argument to a type the same size as a + pointer so the multiply won't overflow spuriously. */ + if (TYPE_PRECISION (index_type) != POINTER_SIZE) + index = convert (type_for_size (POINTER_SIZE, 0), index); + + /* Don't think the address has side effects + just because the array does. + (In some cases the address might have side effects, + and we fail to record that fact here. However, it should not + matter, since expand_expr should not care.) */ + TREE_SIDE_EFFECTS (array_adr) = 0; + + elt = build1 (INDIRECT_REF, type, + fold (build (PLUS_EXPR, + TYPE_POINTER_TO (variant_type), + array_adr, + fold (build (MULT_EXPR, + TYPE_POINTER_TO (variant_type), + index, + size_in_bytes (type)))))); + + /* Volatility, etc., of new expression is same as old + expression. */ + TREE_SIDE_EFFECTS (elt) = TREE_SIDE_EFFECTS (exp); + TREE_THIS_VOLATILE (elt) = TREE_THIS_VOLATILE (exp); + TREE_READONLY (elt) = TREE_READONLY (exp); + + return expand_expr (elt, target, tmode, modifier); + } + + /* Fold an expression like: "foo"[2]. + This is not done in fold so it won't happen inside &. */ + + if (TREE_CODE (array) == STRING_CST + && TREE_CODE (index) == INTEGER_CST + && !TREE_INT_CST_HIGH (index) + && (i = TREE_INT_CST_LOW (index)) < TREE_STRING_LENGTH (array)) + { + if (TREE_TYPE (TREE_TYPE (array)) == integer_type_node) + { + exp = build_int_2 (((int *)TREE_STRING_POINTER (array))[i], 0); + TREE_TYPE (exp) = integer_type_node; + return expand_expr (exp, target, tmode, modifier); + } + if (TREE_TYPE (TREE_TYPE (array)) == char_type_node) + { + exp = build_int_2 (TREE_STRING_POINTER (array)[i], 0); + TREE_TYPE (exp) = integer_type_node; + return expand_expr (convert (TREE_TYPE (TREE_TYPE (array)), + exp), + target, tmode, modifier); + } + } + + /* If this is a constant index into a constant array, + just get the value from the array. Handle both the cases when + we have an explicit constructor and when our operand is a variable + that was declared const. */ + + if (TREE_CODE (array) == CONSTRUCTOR && ! TREE_SIDE_EFFECTS (array)) + { + if (TREE_CODE (index) == INTEGER_CST + && TREE_INT_CST_HIGH (index) == 0) + { + tree elem = CONSTRUCTOR_ELTS (TREE_OPERAND (exp, 0)); + + i = TREE_INT_CST_LOW (index); + while (elem && i--) + elem = TREE_CHAIN (elem); + if (elem) + return expand_expr (fold (TREE_VALUE (elem)), target, + tmode, modifier); + } + } + + else if (optimize >= 1 + && TREE_READONLY (array) && ! TREE_SIDE_EFFECTS (array) + && TREE_CODE (array) == VAR_DECL && DECL_INITIAL (array) + && TREE_CODE (DECL_INITIAL (array)) != ERROR_MARK) + { + if (TREE_CODE (index) == INTEGER_CST + && TREE_INT_CST_HIGH (index) == 0) + { + tree init = DECL_INITIAL (array); + + i = TREE_INT_CST_LOW (index); + if (TREE_CODE (init) == CONSTRUCTOR) + { + tree elem = CONSTRUCTOR_ELTS (init); + + while (elem && i--) + elem = TREE_CHAIN (elem); + if (elem) + return expand_expr (fold (TREE_VALUE (elem)), target, + tmode, modifier); + } + else if (TREE_CODE (init) == STRING_CST + && i < TREE_STRING_LENGTH (init)) + { + temp = GEN_INT (TREE_STRING_POINTER (init)[i]); + return convert_to_mode (mode, temp, 0); + } + } + } + } + + /* Treat array-ref with constant index as a component-ref. */ + + case COMPONENT_REF: + case BIT_FIELD_REF: + /* If the operand is a CONSTRUCTOR, we can just extract the + appropriate field if it is present. */ + if (code != ARRAY_REF + && TREE_CODE (TREE_OPERAND (exp, 0)) == CONSTRUCTOR) + { + tree elt; + + for (elt = CONSTRUCTOR_ELTS (TREE_OPERAND (exp, 0)); elt; + elt = TREE_CHAIN (elt)) + if (TREE_PURPOSE (elt) == TREE_OPERAND (exp, 1)) + return expand_expr (TREE_VALUE (elt), target, tmode, modifier); + } + + { + enum machine_mode mode1; + int bitsize; + int bitpos; + tree offset; + int volatilep = 0; + tree tem = get_inner_reference (exp, &bitsize, &bitpos, &offset, + &mode1, &unsignedp, &volatilep); + + /* If we got back the original object, something is wrong. Perhaps + we are evaluating an expression too early. In any event, don't + infinitely recurse. */ + if (tem == exp) + abort (); + + /* In some cases, we will be offsetting OP0's address by a constant. + So get it as a sum, if possible. If we will be using it + directly in an insn, we validate it. */ + op0 = expand_expr (tem, NULL_RTX, VOIDmode, EXPAND_SUM); + + /* If this is a constant, put it into a register if it is a + legitimate constant and memory if it isn't. */ + if (CONSTANT_P (op0)) + { + enum machine_mode mode = TYPE_MODE (TREE_TYPE (tem)); + if (mode != BLKmode && LEGITIMATE_CONSTANT_P (op0)) + op0 = force_reg (mode, op0); + else + op0 = validize_mem (force_const_mem (mode, op0)); + } + + if (offset != 0) + { + rtx offset_rtx = expand_expr (offset, NULL_RTX, VOIDmode, 0); + + if (GET_CODE (op0) != MEM) + abort (); + op0 = change_address (op0, VOIDmode, + gen_rtx (PLUS, Pmode, XEXP (op0, 0), + force_reg (Pmode, offset_rtx))); + } + + /* Don't forget about volatility even if this is a bitfield. */ + if (GET_CODE (op0) == MEM && volatilep && ! MEM_VOLATILE_P (op0)) + { + op0 = copy_rtx (op0); + MEM_VOLATILE_P (op0) = 1; + } + + if (mode1 == VOIDmode + || (mode1 != BLKmode && ! direct_load[(int) mode1] + && modifier != EXPAND_CONST_ADDRESS + && modifier != EXPAND_SUM && modifier != EXPAND_INITIALIZER) + || GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) + { + /* In cases where an aligned union has an unaligned object + as a field, we might be extracting a BLKmode value from + an integer-mode (e.g., SImode) object. Handle this case + by doing the extract into an object as wide as the field + (which we know to be the width of a basic mode), then + storing into memory, and changing the mode to BLKmode. */ + enum machine_mode ext_mode = mode; + + if (ext_mode == BLKmode) + ext_mode = mode_for_size (bitsize, MODE_INT, 1); + + if (ext_mode == BLKmode) + abort (); + + op0 = extract_bit_field (validize_mem (op0), bitsize, bitpos, + unsignedp, target, ext_mode, ext_mode, + TYPE_ALIGN (TREE_TYPE (tem)) / BITS_PER_UNIT, + int_size_in_bytes (TREE_TYPE (tem))); + if (mode == BLKmode) + { + rtx new = assign_stack_temp (ext_mode, + bitsize / BITS_PER_UNIT, 0); + + emit_move_insn (new, op0); + op0 = copy_rtx (new); + PUT_MODE (op0, BLKmode); + } + + return op0; + } + + /* Get a reference to just this component. */ + if (modifier == EXPAND_CONST_ADDRESS + || modifier == EXPAND_SUM || modifier == EXPAND_INITIALIZER) + op0 = gen_rtx (MEM, mode1, plus_constant (XEXP (op0, 0), + (bitpos / BITS_PER_UNIT))); + else + op0 = change_address (op0, mode1, + plus_constant (XEXP (op0, 0), + (bitpos / BITS_PER_UNIT))); + MEM_IN_STRUCT_P (op0) = 1; + MEM_VOLATILE_P (op0) |= volatilep; + if (mode == mode1 || mode1 == BLKmode || mode1 == tmode) + return op0; + if (target == 0) + target = gen_reg_rtx (tmode != VOIDmode ? tmode : mode); + convert_move (target, op0, unsignedp); + return target; + } + + case OFFSET_REF: + { + tree base = build1 (ADDR_EXPR, type, TREE_OPERAND (exp, 0)); + tree addr = build (PLUS_EXPR, type, base, TREE_OPERAND (exp, 1)); + op0 = expand_expr (addr, NULL_RTX, VOIDmode, EXPAND_SUM); + temp = gen_rtx (MEM, mode, memory_address (mode, op0)); + MEM_IN_STRUCT_P (temp) = 1; + MEM_VOLATILE_P (temp) = TREE_THIS_VOLATILE (exp); +#if 0 /* It is incorrect to set RTX_UNCHANGING_P here, because the fact that + a location is accessed through a pointer to const does not mean + that the value there can never change. */ + RTX_UNCHANGING_P (temp) = TREE_READONLY (exp); +#endif + return temp; + } + + /* Intended for a reference to a buffer of a file-object in Pascal. + But it's not certain that a special tree code will really be + necessary for these. INDIRECT_REF might work for them. */ + case BUFFER_REF: + abort (); + + /* IN_EXPR: Inlined pascal set IN expression. + + Algorithm: + rlo = set_low - (set_low%bits_per_word); + the_word = set [ (index - rlo)/bits_per_word ]; + bit_index = index % bits_per_word; + bitmask = 1 << bit_index; + return !!(the_word & bitmask); */ + case IN_EXPR: + preexpand_calls (exp); + { + tree set = TREE_OPERAND (exp, 0); + tree index = TREE_OPERAND (exp, 1); + tree set_type = TREE_TYPE (set); + + tree set_low_bound = TYPE_MIN_VALUE (TYPE_DOMAIN (set_type)); + tree set_high_bound = TYPE_MAX_VALUE (TYPE_DOMAIN (set_type)); + + rtx index_val; + rtx lo_r; + rtx hi_r; + rtx rlow; + rtx diff, quo, rem, addr, bit, result; + rtx setval, setaddr; + enum machine_mode index_mode = TYPE_MODE (TREE_TYPE (index)); + + if (target == 0) + target = gen_reg_rtx (mode); + + /* If domain is empty, answer is no. */ + if (tree_int_cst_lt (set_high_bound, set_low_bound)) + return const0_rtx; + + index_val = expand_expr (index, 0, VOIDmode, 0); + lo_r = expand_expr (set_low_bound, 0, VOIDmode, 0); + hi_r = expand_expr (set_high_bound, 0, VOIDmode, 0); + setval = expand_expr (set, 0, VOIDmode, 0); + setaddr = XEXP (setval, 0); + + /* Compare index against bounds, if they are constant. */ + if (GET_CODE (index_val) == CONST_INT + && GET_CODE (lo_r) == CONST_INT + && INTVAL (index_val) < INTVAL (lo_r)) + return const0_rtx; + + if (GET_CODE (index_val) == CONST_INT + && GET_CODE (hi_r) == CONST_INT + && INTVAL (hi_r) < INTVAL (index_val)) + return const0_rtx; + + /* If we get here, we have to generate the code for both cases + (in range and out of range). */ + + op0 = gen_label_rtx (); + op1 = gen_label_rtx (); + + if (! (GET_CODE (index_val) == CONST_INT + && GET_CODE (lo_r) == CONST_INT)) + { + emit_cmp_insn (index_val, lo_r, LT, NULL_RTX, + GET_MODE (index_val), 0, 0); + emit_jump_insn (gen_blt (op1)); + } + + if (! (GET_CODE (index_val) == CONST_INT + && GET_CODE (hi_r) == CONST_INT)) + { + emit_cmp_insn (index_val, hi_r, GT, NULL_RTX, + GET_MODE (index_val), 0, 0); + emit_jump_insn (gen_bgt (op1)); + } + + /* Calculate the element number of bit zero in the first word + of the set. */ + if (GET_CODE (lo_r) == CONST_INT) + rlow = GEN_INT (INTVAL (lo_r) + & ~ ((HOST_WIDE_INT) 1 << BITS_PER_UNIT)); + else + rlow = expand_binop (index_mode, and_optab, lo_r, + GEN_INT (~((HOST_WIDE_INT) 1 << BITS_PER_UNIT)), + NULL_RTX, 0, OPTAB_LIB_WIDEN); + + diff = expand_binop (index_mode, sub_optab, + index_val, rlow, NULL_RTX, 0, OPTAB_LIB_WIDEN); + + quo = expand_divmod (0, TRUNC_DIV_EXPR, index_mode, diff, + GEN_INT (BITS_PER_UNIT), NULL_RTX, 0); + rem = expand_divmod (1, TRUNC_MOD_EXPR, index_mode, index_val, + GEN_INT (BITS_PER_UNIT), NULL_RTX, 0); + addr = memory_address (byte_mode, + expand_binop (index_mode, add_optab, + diff, setaddr, NULL_RTX, 0, + OPTAB_LIB_WIDEN)); + /* Extract the bit we want to examine */ + bit = expand_shift (RSHIFT_EXPR, byte_mode, + gen_rtx (MEM, byte_mode, addr), + make_tree (TREE_TYPE (index), rem), + NULL_RTX, 1); + result = expand_binop (byte_mode, and_optab, bit, const1_rtx, + GET_MODE (target) == byte_mode ? target : 0, + 1, OPTAB_LIB_WIDEN); + + if (result != target) + convert_move (target, result, 1); + + /* Output the code to handle the out-of-range case. */ + emit_jump (op0); + emit_label (op1); + emit_move_insn (target, const0_rtx); + emit_label (op0); + return target; + } + + case WITH_CLEANUP_EXPR: + if (RTL_EXPR_RTL (exp) == 0) + { + RTL_EXPR_RTL (exp) + = expand_expr (TREE_OPERAND (exp, 0), target, tmode, modifier); + cleanups_this_call + = tree_cons (NULL_TREE, TREE_OPERAND (exp, 2), cleanups_this_call); + /* That's it for this cleanup. */ + TREE_OPERAND (exp, 2) = 0; + } + return RTL_EXPR_RTL (exp); + + case CALL_EXPR: + /* Check for a built-in function. */ + if (TREE_CODE (TREE_OPERAND (exp, 0)) == ADDR_EXPR + && TREE_CODE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0)) == FUNCTION_DECL + && DECL_BUILT_IN (TREE_OPERAND (TREE_OPERAND (exp, 0), 0))) + return expand_builtin (exp, target, subtarget, tmode, ignore); + /* If this call was expanded already by preexpand_calls, + just return the result we got. */ + if (CALL_EXPR_RTL (exp) != 0) + return CALL_EXPR_RTL (exp); + return expand_call (exp, target, ignore); + + case NON_LVALUE_EXPR: + case NOP_EXPR: + case CONVERT_EXPR: + case REFERENCE_EXPR: + if (TREE_CODE (type) == VOID_TYPE || ignore) + { + expand_expr (TREE_OPERAND (exp, 0), const0_rtx, VOIDmode, modifier); + return const0_rtx; + } + if (mode == TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))) + return expand_expr (TREE_OPERAND (exp, 0), target, VOIDmode, modifier); + if (TREE_CODE (type) == UNION_TYPE) + { + tree valtype = TREE_TYPE (TREE_OPERAND (exp, 0)); + if (target == 0) + { + if (mode == BLKmode) + { + if (TYPE_SIZE (type) == 0 + || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) + abort (); + target = assign_stack_temp (BLKmode, + (TREE_INT_CST_LOW (TYPE_SIZE (type)) + + BITS_PER_UNIT - 1) + / BITS_PER_UNIT, 0); + } + else + target = gen_reg_rtx (mode); + } + if (GET_CODE (target) == MEM) + /* Store data into beginning of memory target. */ + store_expr (TREE_OPERAND (exp, 0), + change_address (target, TYPE_MODE (valtype), 0), 0); + + else if (GET_CODE (target) == REG) + /* Store this field into a union of the proper type. */ + store_field (target, GET_MODE_BITSIZE (TYPE_MODE (valtype)), 0, + TYPE_MODE (valtype), TREE_OPERAND (exp, 0), + VOIDmode, 0, 1, + int_size_in_bytes (TREE_TYPE (TREE_OPERAND (exp, 0)))); + else + abort (); + + /* Return the entire union. */ + return target; + } + op0 = expand_expr (TREE_OPERAND (exp, 0), NULL_RTX, mode, 0); + if (GET_MODE (op0) == mode) + return op0; + /* If arg is a constant integer being extended from a narrower mode, + we must really truncate to get the extended bits right. Otherwise + (unsigned long) (unsigned char) ("\377"[0]) + would come out as ffffffff. */ + if (GET_MODE (op0) == VOIDmode + && (GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))) + < GET_MODE_BITSIZE (mode))) + { + /* MODE must be narrower than HOST_BITS_PER_INT. */ + int width = GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))); + + if (width < HOST_BITS_PER_WIDE_INT) + { + HOST_WIDE_INT val = (GET_CODE (op0) == CONST_INT ? INTVAL (op0) + : CONST_DOUBLE_LOW (op0)); + if (TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 0))) + || !(val & ((HOST_WIDE_INT) 1 << (width - 1)))) + val &= ((HOST_WIDE_INT) 1 << width) - 1; + else + val |= ~(((HOST_WIDE_INT) 1 << width) - 1); + + op0 = GEN_INT (val); + } + else + { + op0 = (simplify_unary_operation + ((TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 0))) + ? ZERO_EXTEND : SIGN_EXTEND), + mode, op0, + TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))))); + if (op0 == 0) + abort (); + } + } + if (GET_MODE (op0) == VOIDmode) + return op0; + if (modifier == EXPAND_INITIALIZER) + return gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, mode, op0); + if (flag_force_mem && GET_CODE (op0) == MEM) + op0 = copy_to_reg (op0); + + if (target == 0) + return convert_to_mode (mode, op0, TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 0)))); + else + convert_move (target, op0, TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 0)))); + return target; + + case PLUS_EXPR: + /* We come here from MINUS_EXPR when the second operand is a constant. */ + plus_expr: + this_optab = add_optab; + + /* If we are adding a constant, an RTL_EXPR that is sp, fp, or ap, and + something else, make sure we add the register to the constant and + then to the other thing. This case can occur during strength + reduction and doing it this way will produce better code if the + frame pointer or argument pointer is eliminated. + + fold-const.c will ensure that the constant is always in the inner + PLUS_EXPR, so the only case we need to do anything about is if + sp, ap, or fp is our second argument, in which case we must swap + the innermost first argument and our second argument. */ + + if (TREE_CODE (TREE_OPERAND (exp, 0)) == PLUS_EXPR + && TREE_CODE (TREE_OPERAND (TREE_OPERAND (exp, 0), 1)) == INTEGER_CST + && TREE_CODE (TREE_OPERAND (exp, 1)) == RTL_EXPR + && (RTL_EXPR_RTL (TREE_OPERAND (exp, 1)) == frame_pointer_rtx + || RTL_EXPR_RTL (TREE_OPERAND (exp, 1)) == stack_pointer_rtx + || RTL_EXPR_RTL (TREE_OPERAND (exp, 1)) == arg_pointer_rtx)) + { + tree t = TREE_OPERAND (exp, 1); + + TREE_OPERAND (exp, 1) = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); + TREE_OPERAND (TREE_OPERAND (exp, 0), 0) = t; + } + + /* If the result is to be Pmode and we are adding an integer to + something, we might be forming a constant. So try to use + plus_constant. If it produces a sum and we can't accept it, + use force_operand. This allows P = &ARR[const] to generate + efficient code on machines where a SYMBOL_REF is not a valid + address. + + If this is an EXPAND_SUM call, always return the sum. */ + if (TREE_CODE (TREE_OPERAND (exp, 0)) == INTEGER_CST + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && (modifier == EXPAND_SUM || modifier == EXPAND_INITIALIZER + || mode == Pmode)) + { + op1 = expand_expr (TREE_OPERAND (exp, 1), subtarget, VOIDmode, + EXPAND_SUM); + op1 = plus_constant (op1, TREE_INT_CST_LOW (TREE_OPERAND (exp, 0))); + if (modifier != EXPAND_SUM && modifier != EXPAND_INITIALIZER) + op1 = force_operand (op1, target); + return op1; + } + + else if (TREE_CODE (TREE_OPERAND (exp, 1)) == INTEGER_CST + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT + && (modifier == EXPAND_SUM || modifier == EXPAND_INITIALIZER + || mode == Pmode)) + { + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, + EXPAND_SUM); + op0 = plus_constant (op0, TREE_INT_CST_LOW (TREE_OPERAND (exp, 1))); + if (modifier != EXPAND_SUM && modifier != EXPAND_INITIALIZER) + op0 = force_operand (op0, target); + return op0; + } + + /* No sense saving up arithmetic to be done + if it's all in the wrong mode to form part of an address. + And force_operand won't know whether to sign-extend or + zero-extend. */ + if ((modifier != EXPAND_SUM && modifier != EXPAND_INITIALIZER) + || mode != Pmode) goto binop; + + preexpand_calls (exp); + if (! safe_from_p (subtarget, TREE_OPERAND (exp, 1))) + subtarget = 0; + + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, modifier); + op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, VOIDmode, modifier); + + /* Make sure any term that's a sum with a constant comes last. */ + if (GET_CODE (op0) == PLUS + && CONSTANT_P (XEXP (op0, 1))) + { + temp = op0; + op0 = op1; + op1 = temp; + } + /* If adding to a sum including a constant, + associate it to put the constant outside. */ + if (GET_CODE (op1) == PLUS + && CONSTANT_P (XEXP (op1, 1))) + { + rtx constant_term = const0_rtx; + + temp = simplify_binary_operation (PLUS, mode, XEXP (op1, 0), op0); + if (temp != 0) + op0 = temp; + /* Ensure that MULT comes first if there is one. */ + else if (GET_CODE (op0) == MULT) + op0 = gen_rtx (PLUS, mode, op0, XEXP (op1, 0)); + else + op0 = gen_rtx (PLUS, mode, XEXP (op1, 0), op0); + + /* Let's also eliminate constants from op0 if possible. */ + op0 = eliminate_constant_term (op0, &constant_term); + + /* CONSTANT_TERM and XEXP (op1, 1) are known to be constant, so + their sum should be a constant. Form it into OP1, since the + result we want will then be OP0 + OP1. */ + + temp = simplify_binary_operation (PLUS, mode, constant_term, + XEXP (op1, 1)); + if (temp != 0) + op1 = temp; + else + op1 = gen_rtx (PLUS, mode, constant_term, XEXP (op1, 1)); + } + + /* Put a constant term last and put a multiplication first. */ + if (CONSTANT_P (op0) || GET_CODE (op1) == MULT) + temp = op1, op1 = op0, op0 = temp; + + temp = simplify_binary_operation (PLUS, mode, op0, op1); + return temp ? temp : gen_rtx (PLUS, mode, op0, op1); + + case MINUS_EXPR: + /* Handle difference of two symbolic constants, + for the sake of an initializer. */ + if ((modifier == EXPAND_SUM || modifier == EXPAND_INITIALIZER) + && really_constant_p (TREE_OPERAND (exp, 0)) + && really_constant_p (TREE_OPERAND (exp, 1))) + { + rtx op0 = expand_expr (TREE_OPERAND (exp, 0), NULL_RTX, + VOIDmode, modifier); + rtx op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, + VOIDmode, modifier); + return gen_rtx (MINUS, mode, op0, op1); + } + /* Convert A - const to A + (-const). */ + if (TREE_CODE (TREE_OPERAND (exp, 1)) == INTEGER_CST) + { + exp = build (PLUS_EXPR, type, TREE_OPERAND (exp, 0), + fold (build1 (NEGATE_EXPR, type, + TREE_OPERAND (exp, 1)))); + goto plus_expr; + } + this_optab = sub_optab; + goto binop; + + case MULT_EXPR: + preexpand_calls (exp); + /* If first operand is constant, swap them. + Thus the following special case checks need only + check the second operand. */ + if (TREE_CODE (TREE_OPERAND (exp, 0)) == INTEGER_CST) + { + register tree t1 = TREE_OPERAND (exp, 0); + TREE_OPERAND (exp, 0) = TREE_OPERAND (exp, 1); + TREE_OPERAND (exp, 1) = t1; + } + + /* Attempt to return something suitable for generating an + indexed address, for machines that support that. */ + + if (modifier == EXPAND_SUM && mode == Pmode + && TREE_CODE (TREE_OPERAND (exp, 1)) == INTEGER_CST + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) + { + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, EXPAND_SUM); + + /* Apply distributive law if OP0 is x+c. */ + if (GET_CODE (op0) == PLUS + && GET_CODE (XEXP (op0, 1)) == CONST_INT) + return gen_rtx (PLUS, mode, + gen_rtx (MULT, mode, XEXP (op0, 0), + GEN_INT (TREE_INT_CST_LOW (TREE_OPERAND (exp, 1)))), + GEN_INT (TREE_INT_CST_LOW (TREE_OPERAND (exp, 1)) + * INTVAL (XEXP (op0, 1)))); + + if (GET_CODE (op0) != REG) + op0 = force_operand (op0, NULL_RTX); + if (GET_CODE (op0) != REG) + op0 = copy_to_mode_reg (mode, op0); + + return gen_rtx (MULT, mode, op0, + GEN_INT (TREE_INT_CST_LOW (TREE_OPERAND (exp, 1)))); + } + + if (! safe_from_p (subtarget, TREE_OPERAND (exp, 1))) + subtarget = 0; + + /* Check for multiplying things that have been extended + from a narrower type. If this machine supports multiplying + in that narrower type with a result in the desired type, + do it that way, and avoid the explicit type-conversion. */ + if (TREE_CODE (TREE_OPERAND (exp, 0)) == NOP_EXPR + && TREE_CODE (type) == INTEGER_TYPE + && (TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0))) + < TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (exp, 0)))) + && ((TREE_CODE (TREE_OPERAND (exp, 1)) == INTEGER_CST + && int_fits_type_p (TREE_OPERAND (exp, 1), + TREE_TYPE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0))) + /* Don't use a widening multiply if a shift will do. */ + && ((GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 1)))) + > HOST_BITS_PER_WIDE_INT) + || exact_log2 (TREE_INT_CST_LOW (TREE_OPERAND (exp, 1))) < 0)) + || + (TREE_CODE (TREE_OPERAND (exp, 1)) == NOP_EXPR + && (TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (exp, 1), 0))) + == + TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0)))) + /* If both operands are extended, they must either both + be zero-extended or both be sign-extended. */ + && (TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (exp, 1), 0))) + == + TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0))))))) + { + enum machine_mode innermode + = TYPE_MODE (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0))); + this_optab = (TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0))) + ? umul_widen_optab : smul_widen_optab); + if (mode == GET_MODE_WIDER_MODE (innermode) + && this_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + { + op0 = expand_expr (TREE_OPERAND (TREE_OPERAND (exp, 0), 0), + NULL_RTX, VOIDmode, 0); + if (TREE_CODE (TREE_OPERAND (exp, 1)) == INTEGER_CST) + op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, + VOIDmode, 0); + else + op1 = expand_expr (TREE_OPERAND (TREE_OPERAND (exp, 1), 0), + NULL_RTX, VOIDmode, 0); + goto binop2; + } + } + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, 0); + op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, VOIDmode, 0); + return expand_mult (mode, op0, op1, target, unsignedp); + + case TRUNC_DIV_EXPR: + case FLOOR_DIV_EXPR: + case CEIL_DIV_EXPR: + case ROUND_DIV_EXPR: + case EXACT_DIV_EXPR: + preexpand_calls (exp); + if (! safe_from_p (subtarget, TREE_OPERAND (exp, 1))) + subtarget = 0; + /* Possible optimization: compute the dividend with EXPAND_SUM + then if the divisor is constant can optimize the case + where some terms of the dividend have coeffs divisible by it. */ + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, 0); + op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, VOIDmode, 0); + return expand_divmod (0, code, mode, op0, op1, target, unsignedp); + + case RDIV_EXPR: + this_optab = flodiv_optab; + goto binop; + + case TRUNC_MOD_EXPR: + case FLOOR_MOD_EXPR: + case CEIL_MOD_EXPR: + case ROUND_MOD_EXPR: + preexpand_calls (exp); + if (! safe_from_p (subtarget, TREE_OPERAND (exp, 1))) + subtarget = 0; + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, 0); + op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, VOIDmode, 0); + return expand_divmod (1, code, mode, op0, op1, target, unsignedp); + + case FIX_ROUND_EXPR: + case FIX_FLOOR_EXPR: + case FIX_CEIL_EXPR: + abort (); /* Not used for C. */ + + case FIX_TRUNC_EXPR: + op0 = expand_expr (TREE_OPERAND (exp, 0), NULL_RTX, VOIDmode, 0); + if (target == 0) + target = gen_reg_rtx (mode); + expand_fix (target, op0, unsignedp); + return target; + + case FLOAT_EXPR: + op0 = expand_expr (TREE_OPERAND (exp, 0), NULL_RTX, VOIDmode, 0); + if (target == 0) + target = gen_reg_rtx (mode); + /* expand_float can't figure out what to do if FROM has VOIDmode. + So give it the correct mode. With -O, cse will optimize this. */ + if (GET_MODE (op0) == VOIDmode) + op0 = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))), + op0); + expand_float (target, op0, + TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 0)))); + return target; + + case NEGATE_EXPR: + op0 = expand_expr (TREE_OPERAND (exp, 0), target, VOIDmode, 0); + temp = expand_unop (mode, neg_optab, op0, target, 0); + if (temp == 0) + abort (); + return temp; + + case ABS_EXPR: + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, 0); + + /* Handle complex values specially. */ + { + enum machine_mode opmode + = TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))); + + if (GET_MODE_CLASS (opmode) == MODE_COMPLEX_INT + || GET_MODE_CLASS (opmode) == MODE_COMPLEX_FLOAT) + return expand_complex_abs (opmode, op0, target, unsignedp); + } + + /* Unsigned abs is simply the operand. Testing here means we don't + risk generating incorrect code below. */ + if (TREE_UNSIGNED (type)) + return op0; + + /* First try to do it with a special abs instruction. */ + temp = expand_unop (mode, abs_optab, op0, target, 0); + if (temp != 0) + return temp; + + /* If this machine has expensive jumps, we can do integer absolute + value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)), + where W is the width of MODE. */ + + if (GET_MODE_CLASS (mode) == MODE_INT && BRANCH_COST >= 2) + { + rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, + size_int (GET_MODE_BITSIZE (mode) - 1), + NULL_RTX, 0); + + temp = expand_binop (mode, xor_optab, extended, op0, target, 0, + OPTAB_LIB_WIDEN); + if (temp != 0) + temp = expand_binop (mode, sub_optab, temp, extended, target, 0, + OPTAB_LIB_WIDEN); + + if (temp != 0) + return temp; + } + + /* If that does not win, use conditional jump and negate. */ + target = original_target; + temp = gen_label_rtx (); + if (target == 0 || ! safe_from_p (target, TREE_OPERAND (exp, 0)) + || (GET_CODE (target) == REG + && REGNO (target) < FIRST_PSEUDO_REGISTER)) + target = gen_reg_rtx (mode); + emit_move_insn (target, op0); + emit_cmp_insn (target, + expand_expr (convert (type, integer_zero_node), + NULL_RTX, VOIDmode, 0), + GE, NULL_RTX, mode, 0, 0); + NO_DEFER_POP; + emit_jump_insn (gen_bge (temp)); + op0 = expand_unop (mode, neg_optab, target, target, 0); + if (op0 != target) + emit_move_insn (target, op0); + emit_label (temp); + OK_DEFER_POP; + return target; + + case MAX_EXPR: + case MIN_EXPR: + target = original_target; + if (target == 0 || ! safe_from_p (target, TREE_OPERAND (exp, 1)) + || (GET_CODE (target) == REG + && REGNO (target) < FIRST_PSEUDO_REGISTER)) + target = gen_reg_rtx (mode); + op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, VOIDmode, 0); + op0 = expand_expr (TREE_OPERAND (exp, 0), target, VOIDmode, 0); + + /* First try to do it with a special MIN or MAX instruction. + If that does not win, use a conditional jump to select the proper + value. */ + this_optab = (TREE_UNSIGNED (type) + ? (code == MIN_EXPR ? umin_optab : umax_optab) + : (code == MIN_EXPR ? smin_optab : smax_optab)); + + temp = expand_binop (mode, this_optab, op0, op1, target, unsignedp, + OPTAB_WIDEN); + if (temp != 0) + return temp; + + if (target != op0) + emit_move_insn (target, op0); + op0 = gen_label_rtx (); + /* If this mode is an integer too wide to compare properly, + compare word by word. Rely on cse to optimize constant cases. */ + if (GET_MODE_CLASS (mode) == MODE_INT + && !can_compare_p (mode)) + { + if (code == MAX_EXPR) + do_jump_by_parts_greater_rtx (mode, TREE_UNSIGNED (type), target, op1, NULL, op0); + else + do_jump_by_parts_greater_rtx (mode, TREE_UNSIGNED (type), op1, target, NULL, op0); + emit_move_insn (target, op1); + } + else + { + if (code == MAX_EXPR) + temp = (TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 1))) + ? compare_from_rtx (target, op1, GEU, 1, mode, NULL_RTX, 0) + : compare_from_rtx (target, op1, GE, 0, mode, NULL_RTX, 0)); + else + temp = (TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 1))) + ? compare_from_rtx (target, op1, LEU, 1, mode, NULL_RTX, 0) + : compare_from_rtx (target, op1, LE, 0, mode, NULL_RTX, 0)); + if (temp == const0_rtx) + emit_move_insn (target, op1); + else if (temp != const_true_rtx) + { + if (bcc_gen_fctn[(int) GET_CODE (temp)] != 0) + emit_jump_insn ((*bcc_gen_fctn[(int) GET_CODE (temp)]) (op0)); + else + abort (); + emit_move_insn (target, op1); + } + } + emit_label (op0); + return target; + +/* ??? Can optimize when the operand of this is a bitwise operation, + by using a different bitwise operation. */ + case BIT_NOT_EXPR: + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, 0); + temp = expand_unop (mode, one_cmpl_optab, op0, target, 1); + if (temp == 0) + abort (); + return temp; + + case FFS_EXPR: + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, 0); + temp = expand_unop (mode, ffs_optab, op0, target, 1); + if (temp == 0) + abort (); + return temp; + +/* ??? Can optimize bitwise operations with one arg constant. + Can optimize (a bitwise1 n) bitwise2 (a bitwise3 b) + and (a bitwise1 b) bitwise2 b (etc) + but that is probably not worth while. */ + +/* BIT_AND_EXPR is for bitwise anding. + TRUTH_AND_EXPR is for anding two boolean values + when we want in all cases to compute both of them. + In general it is fastest to do TRUTH_AND_EXPR by + computing both operands as actual zero-or-1 values + and then bitwise anding. In cases where there cannot + be any side effects, better code would be made by + treating TRUTH_AND_EXPR like TRUTH_ANDIF_EXPR; + but the question is how to recognize those cases. */ + + case TRUTH_AND_EXPR: + case BIT_AND_EXPR: + this_optab = and_optab; + goto binop; + +/* See comment above about TRUTH_AND_EXPR; it applies here too. */ + case TRUTH_OR_EXPR: + case BIT_IOR_EXPR: + this_optab = ior_optab; + goto binop; + + case TRUTH_XOR_EXPR: + case BIT_XOR_EXPR: + this_optab = xor_optab; + goto binop; + + case LSHIFT_EXPR: + case RSHIFT_EXPR: + case LROTATE_EXPR: + case RROTATE_EXPR: + preexpand_calls (exp); + if (! safe_from_p (subtarget, TREE_OPERAND (exp, 1))) + subtarget = 0; + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, 0); + return expand_shift (code, mode, op0, TREE_OPERAND (exp, 1), target, + unsignedp); + +/* Could determine the answer when only additive constants differ. + Also, the addition of one can be handled by changing the condition. */ + case LT_EXPR: + case LE_EXPR: + case GT_EXPR: + case GE_EXPR: + case EQ_EXPR: + case NE_EXPR: + preexpand_calls (exp); + temp = do_store_flag (exp, target, tmode != VOIDmode ? tmode : mode, 0); + if (temp != 0) + return temp; + /* For foo != 0, load foo, and if it is nonzero load 1 instead. */ + if (code == NE_EXPR && integer_zerop (TREE_OPERAND (exp, 1)) + && original_target + && GET_CODE (original_target) == REG + && (GET_MODE (original_target) + == TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))))) + { + temp = expand_expr (TREE_OPERAND (exp, 0), original_target, VOIDmode, 0); + if (temp != original_target) + temp = copy_to_reg (temp); + op1 = gen_label_rtx (); + emit_cmp_insn (temp, const0_rtx, EQ, NULL_RTX, + GET_MODE (temp), unsignedp, 0); + emit_jump_insn (gen_beq (op1)); + emit_move_insn (temp, const1_rtx); + emit_label (op1); + return temp; + } + /* If no set-flag instruction, must generate a conditional + store into a temporary variable. Drop through + and handle this like && and ||. */ + + case TRUTH_ANDIF_EXPR: + case TRUTH_ORIF_EXPR: + if (target == 0 || ! safe_from_p (target, exp) + /* Make sure we don't have a hard reg (such as function's return + value) live across basic blocks, if not optimizing. */ + || (!optimize && GET_CODE (target) == REG + && REGNO (target) < FIRST_PSEUDO_REGISTER)) + target = gen_reg_rtx (tmode != VOIDmode ? tmode : mode); + emit_clr_insn (target); + op1 = gen_label_rtx (); + jumpifnot (exp, op1); + emit_0_to_1_insn (target); + emit_label (op1); + return target; + + case TRUTH_NOT_EXPR: + op0 = expand_expr (TREE_OPERAND (exp, 0), target, VOIDmode, 0); + /* The parser is careful to generate TRUTH_NOT_EXPR + only with operands that are always zero or one. */ + temp = expand_binop (mode, xor_optab, op0, const1_rtx, + target, 1, OPTAB_LIB_WIDEN); + if (temp == 0) + abort (); + return temp; + + case COMPOUND_EXPR: + expand_expr (TREE_OPERAND (exp, 0), const0_rtx, VOIDmode, 0); + emit_queue (); + return expand_expr (TREE_OPERAND (exp, 1), + (ignore ? const0_rtx : target), + VOIDmode, 0); + + case COND_EXPR: + { + /* Note that COND_EXPRs whose type is a structure or union + are required to be constructed to contain assignments of + a temporary variable, so that we can evaluate them here + for side effect only. If type is void, we must do likewise. */ + + /* If an arm of the branch requires a cleanup, + only that cleanup is performed. */ + + tree singleton = 0; + tree binary_op = 0, unary_op = 0; + tree old_cleanups = cleanups_this_call; + cleanups_this_call = 0; + + /* If this is (A ? 1 : 0) and A is a condition, just evaluate it and + convert it to our mode, if necessary. */ + if (integer_onep (TREE_OPERAND (exp, 1)) + && integer_zerop (TREE_OPERAND (exp, 2)) + && TREE_CODE_CLASS (TREE_CODE (TREE_OPERAND (exp, 0))) == '<') + { + op0 = expand_expr (TREE_OPERAND (exp, 0), target, mode, modifier); + if (GET_MODE (op0) == mode) + return op0; + if (target == 0) + target = gen_reg_rtx (mode); + convert_move (target, op0, unsignedp); + return target; + } + + /* If we are not to produce a result, we have no target. Otherwise, + if a target was specified use it; it will not be used as an + intermediate target unless it is safe. If no target, use a + temporary. */ + + if (mode == VOIDmode || ignore) + temp = 0; + else if (original_target + && safe_from_p (original_target, TREE_OPERAND (exp, 0))) + temp = original_target; + else if (mode == BLKmode) + { + if (TYPE_SIZE (type) == 0 + || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) + abort (); + temp = assign_stack_temp (BLKmode, + (TREE_INT_CST_LOW (TYPE_SIZE (type)) + + BITS_PER_UNIT - 1) + / BITS_PER_UNIT, 0); + } + else + temp = gen_reg_rtx (mode); + + /* Check for X ? A + B : A. If we have this, we can copy + A to the output and conditionally add B. Similarly for unary + operations. Don't do this if X has side-effects because + those side effects might affect A or B and the "?" operation is + a sequence point in ANSI. (We test for side effects later.) */ + + if (TREE_CODE_CLASS (TREE_CODE (TREE_OPERAND (exp, 1))) == '2' + && operand_equal_p (TREE_OPERAND (exp, 2), + TREE_OPERAND (TREE_OPERAND (exp, 1), 0), 0)) + singleton = TREE_OPERAND (exp, 2), binary_op = TREE_OPERAND (exp, 1); + else if (TREE_CODE_CLASS (TREE_CODE (TREE_OPERAND (exp, 2))) == '2' + && operand_equal_p (TREE_OPERAND (exp, 1), + TREE_OPERAND (TREE_OPERAND (exp, 2), 0), 0)) + singleton = TREE_OPERAND (exp, 1), binary_op = TREE_OPERAND (exp, 2); + else if (TREE_CODE_CLASS (TREE_CODE (TREE_OPERAND (exp, 1))) == '1' + && operand_equal_p (TREE_OPERAND (exp, 2), + TREE_OPERAND (TREE_OPERAND (exp, 1), 0), 0)) + singleton = TREE_OPERAND (exp, 2), unary_op = TREE_OPERAND (exp, 1); + else if (TREE_CODE_CLASS (TREE_CODE (TREE_OPERAND (exp, 2))) == '1' + && operand_equal_p (TREE_OPERAND (exp, 1), + TREE_OPERAND (TREE_OPERAND (exp, 2), 0), 0)) + singleton = TREE_OPERAND (exp, 1), unary_op = TREE_OPERAND (exp, 2); + + /* If we had X ? A + 1 : A and we can do the test of X as a store-flag + operation, do this as A + (X != 0). Similarly for other simple + binary operators. */ + if (singleton && binary_op + && ! TREE_SIDE_EFFECTS (TREE_OPERAND (exp, 0)) + && (TREE_CODE (binary_op) == PLUS_EXPR + || TREE_CODE (binary_op) == MINUS_EXPR + || TREE_CODE (binary_op) == BIT_IOR_EXPR + || TREE_CODE (binary_op) == BIT_XOR_EXPR + || TREE_CODE (binary_op) == BIT_AND_EXPR) + && integer_onep (TREE_OPERAND (binary_op, 1)) + && TREE_CODE_CLASS (TREE_CODE (TREE_OPERAND (exp, 0))) == '<') + { + rtx result; + optab boptab = (TREE_CODE (binary_op) == PLUS_EXPR ? add_optab + : TREE_CODE (binary_op) == MINUS_EXPR ? sub_optab + : TREE_CODE (binary_op) == BIT_IOR_EXPR ? ior_optab + : TREE_CODE (binary_op) == BIT_XOR_EXPR ? xor_optab + : and_optab); + + /* If we had X ? A : A + 1, do this as A + (X == 0). + + We have to invert the truth value here and then put it + back later if do_store_flag fails. We cannot simply copy + TREE_OPERAND (exp, 0) to another variable and modify that + because invert_truthvalue can modify the tree pointed to + by its argument. */ + if (singleton == TREE_OPERAND (exp, 1)) + TREE_OPERAND (exp, 0) + = invert_truthvalue (TREE_OPERAND (exp, 0)); + + result = do_store_flag (TREE_OPERAND (exp, 0), + (safe_from_p (temp, singleton) + ? temp : NULL_RTX), + mode, BRANCH_COST <= 1); + + if (result) + { + op1 = expand_expr (singleton, NULL_RTX, VOIDmode, 0); + return expand_binop (mode, boptab, op1, result, temp, + unsignedp, OPTAB_LIB_WIDEN); + } + else if (singleton == TREE_OPERAND (exp, 1)) + TREE_OPERAND (exp, 0) + = invert_truthvalue (TREE_OPERAND (exp, 0)); + } + + NO_DEFER_POP; + op0 = gen_label_rtx (); + + if (singleton && ! TREE_SIDE_EFFECTS (TREE_OPERAND (exp, 0))) + { + if (temp != 0) + { + /* If the target conflicts with the other operand of the + binary op, we can't use it. Also, we can't use the target + if it is a hard register, because evaluating the condition + might clobber it. */ + if ((binary_op + && ! safe_from_p (temp, TREE_OPERAND (binary_op, 1))) + || (GET_CODE (temp) == REG + && REGNO (temp) < FIRST_PSEUDO_REGISTER)) + temp = gen_reg_rtx (mode); + store_expr (singleton, temp, 0); + } + else + expand_expr (singleton, + ignore ? const0_rtx : NULL_RTX, VOIDmode, 0); + if (cleanups_this_call) + { + sorry ("aggregate value in COND_EXPR"); + cleanups_this_call = 0; + } + if (singleton == TREE_OPERAND (exp, 1)) + jumpif (TREE_OPERAND (exp, 0), op0); + else + jumpifnot (TREE_OPERAND (exp, 0), op0); + + if (binary_op && temp == 0) + /* Just touch the other operand. */ + expand_expr (TREE_OPERAND (binary_op, 1), + ignore ? const0_rtx : NULL_RTX, VOIDmode, 0); + else if (binary_op) + store_expr (build (TREE_CODE (binary_op), type, + make_tree (type, temp), + TREE_OPERAND (binary_op, 1)), + temp, 0); + else + store_expr (build1 (TREE_CODE (unary_op), type, + make_tree (type, temp)), + temp, 0); + op1 = op0; + } +#if 0 + /* This is now done in jump.c and is better done there because it + produces shorter register lifetimes. */ + + /* Check for both possibilities either constants or variables + in registers (but not the same as the target!). If so, can + save branches by assigning one, branching, and assigning the + other. */ + else if (temp && GET_MODE (temp) != BLKmode + && (TREE_CONSTANT (TREE_OPERAND (exp, 1)) + || ((TREE_CODE (TREE_OPERAND (exp, 1)) == PARM_DECL + || TREE_CODE (TREE_OPERAND (exp, 1)) == VAR_DECL) + && DECL_RTL (TREE_OPERAND (exp, 1)) + && GET_CODE (DECL_RTL (TREE_OPERAND (exp, 1))) == REG + && DECL_RTL (TREE_OPERAND (exp, 1)) != temp)) + && (TREE_CONSTANT (TREE_OPERAND (exp, 2)) + || ((TREE_CODE (TREE_OPERAND (exp, 2)) == PARM_DECL + || TREE_CODE (TREE_OPERAND (exp, 2)) == VAR_DECL) + && DECL_RTL (TREE_OPERAND (exp, 2)) + && GET_CODE (DECL_RTL (TREE_OPERAND (exp, 2))) == REG + && DECL_RTL (TREE_OPERAND (exp, 2)) != temp))) + { + if (GET_CODE (temp) == REG && REGNO (temp) < FIRST_PSEUDO_REGISTER) + temp = gen_reg_rtx (mode); + store_expr (TREE_OPERAND (exp, 2), temp, 0); + jumpifnot (TREE_OPERAND (exp, 0), op0); + store_expr (TREE_OPERAND (exp, 1), temp, 0); + op1 = op0; + } +#endif + /* Check for A op 0 ? A : FOO and A op 0 ? FOO : A where OP is any + comparison operator. If we have one of these cases, set the + output to A, branch on A (cse will merge these two references), + then set the output to FOO. */ + else if (temp + && TREE_CODE_CLASS (TREE_CODE (TREE_OPERAND (exp, 0))) == '<' + && integer_zerop (TREE_OPERAND (TREE_OPERAND (exp, 0), 1)) + && operand_equal_p (TREE_OPERAND (TREE_OPERAND (exp, 0), 0), + TREE_OPERAND (exp, 1), 0) + && ! TREE_SIDE_EFFECTS (TREE_OPERAND (exp, 0)) + && safe_from_p (temp, TREE_OPERAND (exp, 2))) + { + if (GET_CODE (temp) == REG && REGNO (temp) < FIRST_PSEUDO_REGISTER) + temp = gen_reg_rtx (mode); + store_expr (TREE_OPERAND (exp, 1), temp, 0); + jumpif (TREE_OPERAND (exp, 0), op0); + store_expr (TREE_OPERAND (exp, 2), temp, 0); + op1 = op0; + } + else if (temp + && TREE_CODE_CLASS (TREE_CODE (TREE_OPERAND (exp, 0))) == '<' + && integer_zerop (TREE_OPERAND (TREE_OPERAND (exp, 0), 1)) + && operand_equal_p (TREE_OPERAND (TREE_OPERAND (exp, 0), 0), + TREE_OPERAND (exp, 2), 0) + && ! TREE_SIDE_EFFECTS (TREE_OPERAND (exp, 0)) + && safe_from_p (temp, TREE_OPERAND (exp, 1))) + { + if (GET_CODE (temp) == REG && REGNO (temp) < FIRST_PSEUDO_REGISTER) + temp = gen_reg_rtx (mode); + store_expr (TREE_OPERAND (exp, 2), temp, 0); + jumpifnot (TREE_OPERAND (exp, 0), op0); + store_expr (TREE_OPERAND (exp, 1), temp, 0); + op1 = op0; + } + else + { + op1 = gen_label_rtx (); + jumpifnot (TREE_OPERAND (exp, 0), op0); + if (temp != 0) + store_expr (TREE_OPERAND (exp, 1), temp, 0); + else + expand_expr (TREE_OPERAND (exp, 1), + ignore ? const0_rtx : NULL_RTX, VOIDmode, 0); + if (cleanups_this_call) + { + sorry ("aggregate value in COND_EXPR"); + cleanups_this_call = 0; + } + + emit_queue (); + emit_jump_insn (gen_jump (op1)); + emit_barrier (); + emit_label (op0); + if (temp != 0) + store_expr (TREE_OPERAND (exp, 2), temp, 0); + else + expand_expr (TREE_OPERAND (exp, 2), + ignore ? const0_rtx : NULL_RTX, VOIDmode, 0); + } + + if (cleanups_this_call) + { + sorry ("aggregate value in COND_EXPR"); + cleanups_this_call = 0; + } + + emit_queue (); + emit_label (op1); + OK_DEFER_POP; + cleanups_this_call = old_cleanups; + return temp; + } + + case TARGET_EXPR: + { + /* Something needs to be initialized, but we didn't know + where that thing was when building the tree. For example, + it could be the return value of a function, or a parameter + to a function which lays down in the stack, or a temporary + variable which must be passed by reference. + + We guarantee that the expression will either be constructed + or copied into our original target. */ + + tree slot = TREE_OPERAND (exp, 0); + tree exp1; + + if (TREE_CODE (slot) != VAR_DECL) + abort (); + + if (target == 0) + { + if (DECL_RTL (slot) != 0) + { + target = DECL_RTL (slot); + /* If we have already expanded the slot, so don't do + it again. (mrs) */ + if (TREE_OPERAND (exp, 1) == NULL_TREE) + return target; + } + else + { + target = assign_stack_temp (mode, int_size_in_bytes (type), 0); + /* All temp slots at this level must not conflict. */ + preserve_temp_slots (target); + DECL_RTL (slot) = target; + } + +#if 0 + /* I bet this needs to be done, and I bet that it needs to + be above, inside the else clause. The reason is + simple, how else is it going to get cleaned up? (mrs) + + The reason is probably did not work before, and was + commented out is because this was re-expanding already + expanded target_exprs (target == 0 and DECL_RTL (slot) + != 0) also cleaning them up many times as well. :-( */ + + /* Since SLOT is not known to the called function + to belong to its stack frame, we must build an explicit + cleanup. This case occurs when we must build up a reference + to pass the reference as an argument. In this case, + it is very likely that such a reference need not be + built here. */ + + if (TREE_OPERAND (exp, 2) == 0) + TREE_OPERAND (exp, 2) = maybe_build_cleanup (slot); + if (TREE_OPERAND (exp, 2)) + cleanups_this_call = tree_cons (NULL_TREE, TREE_OPERAND (exp, 2), + cleanups_this_call); +#endif + } + else + { + /* This case does occur, when expanding a parameter which + needs to be constructed on the stack. The target + is the actual stack address that we want to initialize. + The function we call will perform the cleanup in this case. */ + + /* If we have already assigned it space, use that space, + not target that we were passed in, as our target + parameter is only a hint. */ + if (DECL_RTL (slot) != 0) + { + target = DECL_RTL (slot); + /* If we have already expanded the slot, so don't do + it again. (mrs) */ + if (TREE_OPERAND (exp, 1) == NULL_TREE) + return target; + } + + DECL_RTL (slot) = target; + } + + exp1 = TREE_OPERAND (exp, 1); + /* Mark it as expanded. */ + TREE_OPERAND (exp, 1) = NULL_TREE; + + return expand_expr (exp1, target, tmode, modifier); + } + + case INIT_EXPR: + { + tree lhs = TREE_OPERAND (exp, 0); + tree rhs = TREE_OPERAND (exp, 1); + tree noncopied_parts = 0; + tree lhs_type = TREE_TYPE (lhs); + + temp = expand_assignment (lhs, rhs, ! ignore, original_target != 0); + if (TYPE_NONCOPIED_PARTS (lhs_type) != 0 && !fixed_type_p (rhs)) + noncopied_parts = init_noncopied_parts (stabilize_reference (lhs), + TYPE_NONCOPIED_PARTS (lhs_type)); + while (noncopied_parts != 0) + { + expand_assignment (TREE_VALUE (noncopied_parts), + TREE_PURPOSE (noncopied_parts), 0, 0); + noncopied_parts = TREE_CHAIN (noncopied_parts); + } + return temp; + } + + case MODIFY_EXPR: + { + /* If lhs is complex, expand calls in rhs before computing it. + That's so we don't compute a pointer and save it over a call. + If lhs is simple, compute it first so we can give it as a + target if the rhs is just a call. This avoids an extra temp and copy + and that prevents a partial-subsumption which makes bad code. + Actually we could treat component_ref's of vars like vars. */ + + tree lhs = TREE_OPERAND (exp, 0); + tree rhs = TREE_OPERAND (exp, 1); + tree noncopied_parts = 0; + tree lhs_type = TREE_TYPE (lhs); + + temp = 0; + + if (TREE_CODE (lhs) != VAR_DECL + && TREE_CODE (lhs) != RESULT_DECL + && TREE_CODE (lhs) != PARM_DECL) + preexpand_calls (exp); + + /* Check for |= or &= of a bitfield of size one into another bitfield + of size 1. In this case, (unless we need the result of the + assignment) we can do this more efficiently with a + test followed by an assignment, if necessary. + + ??? At this point, we can't get a BIT_FIELD_REF here. But if + things change so we do, this code should be enhanced to + support it. */ + if (ignore + && TREE_CODE (lhs) == COMPONENT_REF + && (TREE_CODE (rhs) == BIT_IOR_EXPR + || TREE_CODE (rhs) == BIT_AND_EXPR) + && TREE_OPERAND (rhs, 0) == lhs + && TREE_CODE (TREE_OPERAND (rhs, 1)) == COMPONENT_REF + && TREE_INT_CST_LOW (DECL_SIZE (TREE_OPERAND (lhs, 1))) == 1 + && TREE_INT_CST_LOW (DECL_SIZE (TREE_OPERAND (TREE_OPERAND (rhs, 1), 1))) == 1) + { + rtx label = gen_label_rtx (); + + do_jump (TREE_OPERAND (rhs, 1), + TREE_CODE (rhs) == BIT_IOR_EXPR ? label : 0, + TREE_CODE (rhs) == BIT_AND_EXPR ? label : 0); + expand_assignment (lhs, convert (TREE_TYPE (rhs), + (TREE_CODE (rhs) == BIT_IOR_EXPR + ? integer_one_node + : integer_zero_node)), + 0, 0); + do_pending_stack_adjust (); + emit_label (label); + return const0_rtx; + } + + if (TYPE_NONCOPIED_PARTS (lhs_type) != 0 + && ! (fixed_type_p (lhs) && fixed_type_p (rhs))) + noncopied_parts = save_noncopied_parts (stabilize_reference (lhs), + TYPE_NONCOPIED_PARTS (lhs_type)); + + temp = expand_assignment (lhs, rhs, ! ignore, original_target != 0); + while (noncopied_parts != 0) + { + expand_assignment (TREE_PURPOSE (noncopied_parts), + TREE_VALUE (noncopied_parts), 0, 0); + noncopied_parts = TREE_CHAIN (noncopied_parts); + } + return temp; + } + + case PREINCREMENT_EXPR: + case PREDECREMENT_EXPR: + return expand_increment (exp, 0); + + case POSTINCREMENT_EXPR: + case POSTDECREMENT_EXPR: + /* Faster to treat as pre-increment if result is not used. */ + return expand_increment (exp, ! ignore); + + case ADDR_EXPR: + /* Are we taking the address of a nested function? */ + if (TREE_CODE (TREE_OPERAND (exp, 0)) == FUNCTION_DECL + && decl_function_context (TREE_OPERAND (exp, 0)) != 0) + { + op0 = trampoline_address (TREE_OPERAND (exp, 0)); + op0 = force_operand (op0, target); + } + else + { + op0 = expand_expr (TREE_OPERAND (exp, 0), NULL_RTX, VOIDmode, + (modifier == EXPAND_INITIALIZER + ? modifier : EXPAND_CONST_ADDRESS)); + + /* We would like the object in memory. If it is a constant, + we can have it be statically allocated into memory. For + a non-constant (REG or SUBREG), we need to allocate some + memory and store the value into it. */ + + if (CONSTANT_P (op0)) + op0 = force_const_mem (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))), + op0); + + if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) + { + /* If this object is in a register, it must be not + be BLKmode. */ + tree inner_type = TREE_TYPE (TREE_OPERAND (exp, 0)); + enum machine_mode inner_mode = TYPE_MODE (inner_type); + rtx memloc + = assign_stack_temp (inner_mode, + int_size_in_bytes (inner_type), 1); + + emit_move_insn (memloc, op0); + op0 = memloc; + } + + if (GET_CODE (op0) != MEM) + abort (); + + if (modifier == EXPAND_SUM || modifier == EXPAND_INITIALIZER) + return XEXP (op0, 0); + op0 = force_operand (XEXP (op0, 0), target); + } + if (flag_force_addr && GET_CODE (op0) != REG) + return force_reg (Pmode, op0); + return op0; + + case ENTRY_VALUE_EXPR: + abort (); + + /* COMPLEX type for Extended Pascal & Fortran */ + case COMPLEX_EXPR: + { + enum machine_mode mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (exp))); + + rtx prev; + + /* Get the rtx code of the operands. */ + op0 = expand_expr (TREE_OPERAND (exp, 0), 0, VOIDmode, 0); + op1 = expand_expr (TREE_OPERAND (exp, 1), 0, VOIDmode, 0); + + if (! target) + target = gen_reg_rtx (TYPE_MODE (TREE_TYPE (exp))); + + prev = get_last_insn (); + + /* Tell flow that the whole of the destination is being set. */ + if (GET_CODE (target) == REG) + emit_insn (gen_rtx (CLOBBER, VOIDmode, target)); + + /* Move the real (op0) and imaginary (op1) parts to their location. */ + emit_move_insn (gen_realpart (mode, target), op0); + emit_move_insn (gen_imagpart (mode, target), op1); + + /* Complex construction should appear as a single unit. */ + group_insns (prev); + + return target; + } + + case REALPART_EXPR: + op0 = expand_expr (TREE_OPERAND (exp, 0), 0, VOIDmode, 0); + return gen_realpart (mode, op0); + + case IMAGPART_EXPR: + op0 = expand_expr (TREE_OPERAND (exp, 0), 0, VOIDmode, 0); + return gen_imagpart (mode, op0); + + case CONJ_EXPR: + { + enum machine_mode mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (exp))); + rtx imag_t; + rtx prev; + + op0 = expand_expr (TREE_OPERAND (exp, 0), 0, VOIDmode, 0); + + if (! target) + target = gen_reg_rtx (TYPE_MODE (TREE_TYPE (exp))); + + prev = get_last_insn (); + + /* Tell flow that the whole of the destination is being set. */ + if (GET_CODE (target) == REG) + emit_insn (gen_rtx (CLOBBER, VOIDmode, target)); + + /* Store the realpart and the negated imagpart to target. */ + emit_move_insn (gen_realpart (mode, target), gen_realpart (mode, op0)); + + imag_t = gen_imagpart (mode, target); + temp = expand_unop (mode, neg_optab, + gen_imagpart (mode, op0), imag_t, 0); + if (temp != imag_t) + emit_move_insn (imag_t, temp); + + /* Conjugate should appear as a single unit */ + group_insns (prev); + + return target; + } + + case ERROR_MARK: + op0 = CONST0_RTX (tmode); + if (op0 != 0) + return op0; + return const0_rtx; + + default: + return (*lang_expand_expr) (exp, target, tmode, modifier); + } + + /* Here to do an ordinary binary operator, generating an instruction + from the optab already placed in `this_optab'. */ + binop: + preexpand_calls (exp); + if (! safe_from_p (subtarget, TREE_OPERAND (exp, 1))) + subtarget = 0; + op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode, 0); + op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, VOIDmode, 0); + binop2: + temp = expand_binop (mode, this_optab, op0, op1, target, + unsignedp, OPTAB_LIB_WIDEN); + if (temp == 0) + abort (); + return temp; +} + +/* Return the alignment in bits of EXP, a pointer valued expression. + But don't return more than MAX_ALIGN no matter what. + The alignment returned is, by default, the alignment of the thing that + EXP points to (if it is not a POINTER_TYPE, 0 is returned). + + Otherwise, look at the expression to see if we can do better, i.e., if the + expression is actually pointing at an object whose alignment is tighter. */ + +static int +get_pointer_alignment (exp, max_align) + tree exp; + unsigned max_align; +{ + unsigned align, inner; + + if (TREE_CODE (TREE_TYPE (exp)) != POINTER_TYPE) + return 0; + + align = TYPE_ALIGN (TREE_TYPE (TREE_TYPE (exp))); + align = MIN (align, max_align); + + while (1) + { + switch (TREE_CODE (exp)) + { + case NOP_EXPR: + case CONVERT_EXPR: + case NON_LVALUE_EXPR: + exp = TREE_OPERAND (exp, 0); + if (TREE_CODE (TREE_TYPE (exp)) != POINTER_TYPE) + return align; + inner = TYPE_ALIGN (TREE_TYPE (TREE_TYPE (exp))); + inner = MIN (inner, max_align); + align = MAX (align, inner); + break; + + case PLUS_EXPR: + /* If sum of pointer + int, restrict our maximum alignment to that + imposed by the integer. If not, we can't do any better than + ALIGN. */ + if (TREE_CODE (TREE_OPERAND (exp, 1)) != INTEGER_CST) + return align; + + while (((TREE_INT_CST_LOW (TREE_OPERAND (exp, 1)) * BITS_PER_UNIT) + & (max_align - 1)) + != 0) + max_align >>= 1; + + exp = TREE_OPERAND (exp, 0); + break; + + case ADDR_EXPR: + /* See what we are pointing at and look at its alignment. */ + exp = TREE_OPERAND (exp, 0); + if (TREE_CODE (exp) == FUNCTION_DECL) + align = MAX (align, FUNCTION_BOUNDARY); + else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'd') + align = MAX (align, DECL_ALIGN (exp)); +#ifdef CONSTANT_ALIGNMENT + else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c') + align = CONSTANT_ALIGNMENT (exp, align); +#endif + return MIN (align, max_align); + + default: + return align; + } + } +} + +/* Return the tree node and offset if a given argument corresponds to + a string constant. */ + +static tree +string_constant (arg, ptr_offset) + tree arg; + tree *ptr_offset; +{ + STRIP_NOPS (arg); + + if (TREE_CODE (arg) == ADDR_EXPR + && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST) + { + *ptr_offset = integer_zero_node; + return TREE_OPERAND (arg, 0); + } + else if (TREE_CODE (arg) == PLUS_EXPR) + { + tree arg0 = TREE_OPERAND (arg, 0); + tree arg1 = TREE_OPERAND (arg, 1); + + STRIP_NOPS (arg0); + STRIP_NOPS (arg1); + + if (TREE_CODE (arg0) == ADDR_EXPR + && TREE_CODE (TREE_OPERAND (arg0, 0)) == STRING_CST) + { + *ptr_offset = arg1; + return TREE_OPERAND (arg0, 0); + } + else if (TREE_CODE (arg1) == ADDR_EXPR + && TREE_CODE (TREE_OPERAND (arg1, 0)) == STRING_CST) + { + *ptr_offset = arg0; + return TREE_OPERAND (arg1, 0); + } + } + + return 0; +} + +/* Compute the length of a C string. TREE_STRING_LENGTH is not the right + way, because it could contain a zero byte in the middle. + TREE_STRING_LENGTH is the size of the character array, not the string. + + Unfortunately, string_constant can't access the values of const char + arrays with initializers, so neither can we do so here. */ + +static tree +c_strlen (src) + tree src; +{ + tree offset_node; + int offset, max; + char *ptr; + + src = string_constant (src, &offset_node); + if (src == 0) + return 0; + max = TREE_STRING_LENGTH (src); + ptr = TREE_STRING_POINTER (src); + if (offset_node && TREE_CODE (offset_node) != INTEGER_CST) + { + /* If the string has an internal zero byte (e.g., "foo\0bar"), we can't + compute the offset to the following null if we don't know where to + start searching for it. */ + int i; + for (i = 0; i < max; i++) + if (ptr[i] == 0) + return 0; + /* We don't know the starting offset, but we do know that the string + has no internal zero bytes. We can assume that the offset falls + within the bounds of the string; otherwise, the programmer deserves + what he gets. Subtract the offset from the length of the string, + and return that. */ + /* This would perhaps not be valid if we were dealing with named + arrays in addition to literal string constants. */ + return size_binop (MINUS_EXPR, size_int (max), offset_node); + } + + /* We have a known offset into the string. Start searching there for + a null character. */ + if (offset_node == 0) + offset = 0; + else + { + /* Did we get a long long offset? If so, punt. */ + if (TREE_INT_CST_HIGH (offset_node) != 0) + return 0; + offset = TREE_INT_CST_LOW (offset_node); + } + /* If the offset is known to be out of bounds, warn, and call strlen at + runtime. */ + if (offset < 0 || offset > max) + { + warning ("offset outside bounds of constant string"); + return 0; + } + /* Use strlen to search for the first zero byte. Since any strings + constructed with build_string will have nulls appended, we win even + if we get handed something like (char[4])"abcd". + + Since OFFSET is our starting index into the string, no further + calculation is needed. */ + return size_int (strlen (ptr + offset)); +} + +/* Expand an expression EXP that calls a built-in function, + with result going to TARGET if that's convenient + (and in mode MODE if that's convenient). + SUBTARGET may be used as the target for computing one of EXP's operands. + IGNORE is nonzero if the value is to be ignored. */ + +static rtx +expand_builtin (exp, target, subtarget, mode, ignore) + tree exp; + rtx target; + rtx subtarget; + enum machine_mode mode; + int ignore; +{ + tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); + tree arglist = TREE_OPERAND (exp, 1); + rtx op0; + rtx lab1, insns; + enum machine_mode value_mode = TYPE_MODE (TREE_TYPE (exp)); + optab builtin_optab; + + switch (DECL_FUNCTION_CODE (fndecl)) + { + case BUILT_IN_ABS: + case BUILT_IN_LABS: + case BUILT_IN_FABS: + /* build_function_call changes these into ABS_EXPR. */ + abort (); + + case BUILT_IN_SIN: + case BUILT_IN_COS: + case BUILT_IN_FSQRT: + /* If not optimizing, call the library function. */ + if (! optimize) + break; + + if (arglist == 0 + /* Arg could be wrong type if user redeclared this fcn wrong. */ + || TREE_CODE (TREE_TYPE (TREE_VALUE (arglist))) != REAL_TYPE) + return CONST0_RTX (TYPE_MODE (TREE_TYPE (exp))); + + /* Stabilize and compute the argument. */ + if (TREE_CODE (TREE_VALUE (arglist)) != VAR_DECL + && TREE_CODE (TREE_VALUE (arglist)) != PARM_DECL) + { + exp = copy_node (exp); + arglist = copy_node (arglist); + TREE_OPERAND (exp, 1) = arglist; + TREE_VALUE (arglist) = save_expr (TREE_VALUE (arglist)); + } + op0 = expand_expr (TREE_VALUE (arglist), subtarget, VOIDmode, 0); + + /* Make a suitable register to place result in. */ + target = gen_reg_rtx (TYPE_MODE (TREE_TYPE (exp))); + + emit_queue (); + start_sequence (); + + switch (DECL_FUNCTION_CODE (fndecl)) + { + case BUILT_IN_SIN: + builtin_optab = sin_optab; break; + case BUILT_IN_COS: + builtin_optab = cos_optab; break; + case BUILT_IN_FSQRT: + builtin_optab = sqrt_optab; break; + default: + abort (); + } + + /* Compute into TARGET. + Set TARGET to wherever the result comes back. */ + target = expand_unop (TYPE_MODE (TREE_TYPE (TREE_VALUE (arglist))), + builtin_optab, op0, target, 0); + + /* If we were unable to expand via the builtin, stop the + sequence (without outputting the insns) and break, causing + a call the the library function. */ + if (target == 0) + { + end_sequence (); + break; + } + + /* Check the results by default. But if flag_fast_math is turned on, + then assume sqrt will always be called with valid arguments. */ + + if (! flag_fast_math) + { + /* Don't define the builtin FP instructions + if your machine is not IEEE. */ + if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT) + abort (); + + lab1 = gen_label_rtx (); + + /* Test the result; if it is NaN, set errno=EDOM because + the argument was not in the domain. */ + emit_cmp_insn (target, target, EQ, 0, GET_MODE (target), 0, 0); + emit_jump_insn (gen_beq (lab1)); + +#if TARGET_EDOM + { +#ifdef GEN_ERRNO_RTX + rtx errno_rtx = GEN_ERRNO_RTX; +#else + rtx errno_rtx + = gen_rtx (MEM, word_mode, gen_rtx (SYMBOL_REF, Pmode, "*errno")); +#endif + + emit_move_insn (errno_rtx, GEN_INT (TARGET_EDOM)); + } +#else + /* We can't set errno=EDOM directly; let the library call do it. + Pop the arguments right away in case the call gets deleted. */ + NO_DEFER_POP; + expand_call (exp, target, 0); + OK_DEFER_POP; +#endif + + emit_label (lab1); + } + + /* Output the entire sequence. */ + insns = get_insns (); + end_sequence (); + emit_insns (insns); + + return target; + + /* __builtin_apply_args returns block of memory allocated on + the stack into which is stored the arg pointer, structure + value address, static chain, and all the registers that might + possibly be used in performing a function call. The code is + moved to the start of the function so the incoming values are + saved. */ + case BUILT_IN_APPLY_ARGS: + /* Don't do __builtin_apply_args more than once in a function. + Save the result of the first call and reuse it. */ + if (apply_args_value != 0) + return apply_args_value; + { + /* When this function is called, it means that registers must be + saved on entry to this function. So we migrate the + call to the first insn of this function. */ + rtx temp; + rtx seq; + + start_sequence (); + temp = expand_builtin_apply_args (); + seq = get_insns (); + end_sequence (); + + apply_args_value = temp; + + /* Put the sequence after the NOTE that starts the function. + If this is inside a SEQUENCE, make the outer-level insn + chain current, so the code is placed at the start of the + function. */ + push_topmost_sequence (); + emit_insns_before (seq, NEXT_INSN (get_insns ())); + pop_topmost_sequence (); + return temp; + } + + /* __builtin_apply (FUNCTION, ARGUMENTS, ARGSIZE) invokes + FUNCTION with a copy of the parameters described by + ARGUMENTS, and ARGSIZE. It returns a block of memory + allocated on the stack into which is stored all the registers + that might possibly be used for returning the result of a + function. ARGUMENTS is the value returned by + __builtin_apply_args. ARGSIZE is the number of bytes of + arguments that must be copied. ??? How should this value be + computed? We'll also need a safe worst case value for varargs + functions. */ + case BUILT_IN_APPLY: + if (arglist == 0 + /* Arg could be non-pointer if user redeclared this fcn wrong. */ + || TREE_CODE (TREE_TYPE (TREE_VALUE (arglist))) != POINTER_TYPE + || TREE_CHAIN (arglist) == 0 + || TREE_CODE (TREE_TYPE (TREE_VALUE (TREE_CHAIN (arglist)))) != POINTER_TYPE + || TREE_CHAIN (TREE_CHAIN (arglist)) == 0 + || TREE_CODE (TREE_TYPE (TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))))) != INTEGER_TYPE) + return const0_rtx; + else + { + int i; + tree t; + rtx ops[3]; + + for (t = arglist, i = 0; t; t = TREE_CHAIN (t), i++) + ops[i] = expand_expr (TREE_VALUE (t), NULL_RTX, VOIDmode, 0); + + return expand_builtin_apply (ops[0], ops[1], ops[2]); + } + + /* __builtin_return (RESULT) causes the function to return the + value described by RESULT. RESULT is address of the block of + memory returned by __builtin_apply. */ + case BUILT_IN_RETURN: + if (arglist + /* Arg could be non-pointer if user redeclared this fcn wrong. */ + && TREE_CODE (TREE_TYPE (TREE_VALUE (arglist))) == POINTER_TYPE) + expand_builtin_return (expand_expr (TREE_VALUE (arglist), + NULL_RTX, VOIDmode, 0)); + return const0_rtx; + + case BUILT_IN_SAVEREGS: + /* Don't do __builtin_saveregs more than once in a function. + Save the result of the first call and reuse it. */ + if (saveregs_value != 0) + return saveregs_value; + { + /* When this function is called, it means that registers must be + saved on entry to this function. So we migrate the + call to the first insn of this function. */ + rtx temp; + rtx seq; + rtx valreg, saved_valreg; + + /* Now really call the function. `expand_call' does not call + expand_builtin, so there is no danger of infinite recursion here. */ + start_sequence (); + +#ifdef EXPAND_BUILTIN_SAVEREGS + /* Do whatever the machine needs done in this case. */ + temp = EXPAND_BUILTIN_SAVEREGS (arglist); +#else + /* The register where the function returns its value + is likely to have something else in it, such as an argument. + So preserve that register around the call. */ + if (value_mode != VOIDmode) + { + valreg = hard_libcall_value (value_mode); + saved_valreg = gen_reg_rtx (value_mode); + emit_move_insn (saved_valreg, valreg); + } + + /* Generate the call, putting the value in a pseudo. */ + temp = expand_call (exp, target, ignore); + + if (value_mode != VOIDmode) + emit_move_insn (valreg, saved_valreg); +#endif + + seq = get_insns (); + end_sequence (); + + saveregs_value = temp; + + /* Put the sequence after the NOTE that starts the function. + If this is inside a SEQUENCE, make the outer-level insn + chain current, so the code is placed at the start of the + function. */ + push_topmost_sequence (); + emit_insns_before (seq, NEXT_INSN (get_insns ())); + pop_topmost_sequence (); + return temp; + } + + /* __builtin_args_info (N) returns word N of the arg space info + for the current function. The number and meanings of words + is controlled by the definition of CUMULATIVE_ARGS. */ + case BUILT_IN_ARGS_INFO: + { + int nwords = sizeof (CUMULATIVE_ARGS) / sizeof (int); + int i; + int *word_ptr = (int *) ¤t_function_args_info; + tree type, elts, result; + + if (sizeof (CUMULATIVE_ARGS) % sizeof (int) != 0) + fatal ("CUMULATIVE_ARGS type defined badly; see %s, line %d", + __FILE__, __LINE__); + + if (arglist != 0) + { + tree arg = TREE_VALUE (arglist); + if (TREE_CODE (arg) != INTEGER_CST) + error ("argument of `__builtin_args_info' must be constant"); + else + { + int wordnum = TREE_INT_CST_LOW (arg); + + if (wordnum < 0 || wordnum >= nwords || TREE_INT_CST_HIGH (arg)) + error ("argument of `__builtin_args_info' out of range"); + else + return GEN_INT (word_ptr[wordnum]); + } + } + else + error ("missing argument in `__builtin_args_info'"); + + return const0_rtx; + +#if 0 + for (i = 0; i < nwords; i++) + elts = tree_cons (NULL_TREE, build_int_2 (word_ptr[i], 0)); + + type = build_array_type (integer_type_node, + build_index_type (build_int_2 (nwords, 0))); + result = build (CONSTRUCTOR, type, NULL_TREE, nreverse (elts)); + TREE_CONSTANT (result) = 1; + TREE_STATIC (result) = 1; + result = build (INDIRECT_REF, build_pointer_type (type), result); + TREE_CONSTANT (result) = 1; + return expand_expr (result, NULL_RTX, VOIDmode, 0); +#endif + } + + /* Return the address of the first anonymous stack arg. */ + case BUILT_IN_NEXT_ARG: + { + tree fntype = TREE_TYPE (current_function_decl); + if (!(TYPE_ARG_TYPES (fntype) != 0 + && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) + != void_type_node))) + { + error ("`va_start' used in function with fixed args"); + return const0_rtx; + } + } + + return expand_binop (Pmode, add_optab, + current_function_internal_arg_pointer, + current_function_arg_offset_rtx, + NULL_RTX, 0, OPTAB_LIB_WIDEN); + + case BUILT_IN_CLASSIFY_TYPE: + if (arglist != 0) + { + tree type = TREE_TYPE (TREE_VALUE (arglist)); + enum tree_code code = TREE_CODE (type); + if (code == VOID_TYPE) + return GEN_INT (void_type_class); + if (code == INTEGER_TYPE) + return GEN_INT (integer_type_class); + if (code == CHAR_TYPE) + return GEN_INT (char_type_class); + if (code == ENUMERAL_TYPE) + return GEN_INT (enumeral_type_class); + if (code == BOOLEAN_TYPE) + return GEN_INT (boolean_type_class); + if (code == POINTER_TYPE) + return GEN_INT (pointer_type_class); + if (code == REFERENCE_TYPE) + return GEN_INT (reference_type_class); + if (code == OFFSET_TYPE) + return GEN_INT (offset_type_class); + if (code == REAL_TYPE) + return GEN_INT (real_type_class); + if (code == COMPLEX_TYPE) + return GEN_INT (complex_type_class); + if (code == FUNCTION_TYPE) + return GEN_INT (function_type_class); + if (code == METHOD_TYPE) + return GEN_INT (method_type_class); + if (code == RECORD_TYPE) + return GEN_INT (record_type_class); + if (code == UNION_TYPE || code == QUAL_UNION_TYPE) + return GEN_INT (union_type_class); + if (code == ARRAY_TYPE) + return GEN_INT (array_type_class); + if (code == STRING_TYPE) + return GEN_INT (string_type_class); + if (code == SET_TYPE) + return GEN_INT (set_type_class); + if (code == FILE_TYPE) + return GEN_INT (file_type_class); + if (code == LANG_TYPE) + return GEN_INT (lang_type_class); + } + return GEN_INT (no_type_class); + + case BUILT_IN_CONSTANT_P: + if (arglist == 0) + return const0_rtx; + else + return (TREE_CODE_CLASS (TREE_CODE (TREE_VALUE (arglist))) == 'c' + ? const1_rtx : const0_rtx); + + case BUILT_IN_FRAME_ADDRESS: + /* The argument must be a nonnegative integer constant. + It counts the number of frames to scan up the stack. + The value is the address of that frame. */ + case BUILT_IN_RETURN_ADDRESS: + /* The argument must be a nonnegative integer constant. + It counts the number of frames to scan up the stack. + The value is the return address saved in that frame. */ + if (arglist == 0) + /* Warning about missing arg was already issued. */ + return const0_rtx; + else if (TREE_CODE (TREE_VALUE (arglist)) != INTEGER_CST) + { + error ("invalid arg to `__builtin_return_address'"); + return const0_rtx; + } + else if (tree_int_cst_lt (TREE_VALUE (arglist), integer_zero_node)) + { + error ("invalid arg to `__builtin_return_address'"); + return const0_rtx; + } + else + { + int count = TREE_INT_CST_LOW (TREE_VALUE (arglist)); + rtx tem = frame_pointer_rtx; + int i; + + /* Some machines need special handling before we can access arbitrary + frames. For example, on the sparc, we must first flush all + register windows to the stack. */ +#ifdef SETUP_FRAME_ADDRESSES + SETUP_FRAME_ADDRESSES (); +#endif + + /* On the sparc, the return address is not in the frame, it is + in a register. There is no way to access it off of the current + frame pointer, but it can be accessed off the previous frame + pointer by reading the value from the register window save + area. */ +#ifdef RETURN_ADDR_IN_PREVIOUS_FRAME + if (DECL_FUNCTION_CODE (fndecl) == BUILT_IN_RETURN_ADDRESS) + count--; +#endif + + /* Scan back COUNT frames to the specified frame. */ + for (i = 0; i < count; i++) + { + /* Assume the dynamic chain pointer is in the word that + the frame address points to, unless otherwise specified. */ +#ifdef DYNAMIC_CHAIN_ADDRESS + tem = DYNAMIC_CHAIN_ADDRESS (tem); +#endif + tem = memory_address (Pmode, tem); + tem = copy_to_reg (gen_rtx (MEM, Pmode, tem)); + } + + /* For __builtin_frame_address, return what we've got. */ + if (DECL_FUNCTION_CODE (fndecl) == BUILT_IN_FRAME_ADDRESS) + return tem; + + /* For __builtin_return_address, + Get the return address from that frame. */ +#ifdef RETURN_ADDR_RTX + return RETURN_ADDR_RTX (count, tem); +#else + tem = memory_address (Pmode, + plus_constant (tem, GET_MODE_SIZE (Pmode))); + return copy_to_reg (gen_rtx (MEM, Pmode, tem)); +#endif + } + + case BUILT_IN_ALLOCA: + if (arglist == 0 + /* Arg could be non-integer if user redeclared this fcn wrong. */ + || TREE_CODE (TREE_TYPE (TREE_VALUE (arglist))) != INTEGER_TYPE) + return const0_rtx; + current_function_calls_alloca = 1; + /* Compute the argument. */ + op0 = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0); + + /* Allocate the desired space. */ + target = allocate_dynamic_stack_space (op0, target, BITS_PER_UNIT); + + /* Record the new stack level for nonlocal gotos. */ + if (nonlocal_goto_handler_slot != 0) + emit_stack_save (SAVE_NONLOCAL, &nonlocal_goto_stack_level, NULL_RTX); + return target; + + case BUILT_IN_FFS: + /* If not optimizing, call the library function. */ + if (!optimize) + break; + + if (arglist == 0 + /* Arg could be non-integer if user redeclared this fcn wrong. */ + || TREE_CODE (TREE_TYPE (TREE_VALUE (arglist))) != INTEGER_TYPE) + return const0_rtx; + + /* Compute the argument. */ + op0 = expand_expr (TREE_VALUE (arglist), subtarget, VOIDmode, 0); + /* Compute ffs, into TARGET if possible. + Set TARGET to wherever the result comes back. */ + target = expand_unop (TYPE_MODE (TREE_TYPE (TREE_VALUE (arglist))), + ffs_optab, op0, target, 1); + if (target == 0) + abort (); + return target; + + case BUILT_IN_STRLEN: + /* If not optimizing, call the library function. */ + if (!optimize) + break; + + if (arglist == 0 + /* Arg could be non-pointer if user redeclared this fcn wrong. */ + || TREE_CODE (TREE_TYPE (TREE_VALUE (arglist))) != POINTER_TYPE) + return const0_rtx; + else + { + tree src = TREE_VALUE (arglist); + tree len = c_strlen (src); + + int align + = get_pointer_alignment (src, BIGGEST_ALIGNMENT) / BITS_PER_UNIT; + + rtx result, src_rtx, char_rtx; + enum machine_mode insn_mode = value_mode, char_mode; + enum insn_code icode; + + /* If the length is known, just return it. */ + if (len != 0) + return expand_expr (len, target, mode, 0); + + /* If SRC is not a pointer type, don't do this operation inline. */ + if (align == 0) + break; + + /* Call a function if we can't compute strlen in the right mode. */ + + while (insn_mode != VOIDmode) + { + icode = strlen_optab->handlers[(int) insn_mode].insn_code; + if (icode != CODE_FOR_nothing) + break; + + insn_mode = GET_MODE_WIDER_MODE (insn_mode); + } + if (insn_mode == VOIDmode) + break; + + /* Make a place to write the result of the instruction. */ + result = target; + if (! (result != 0 + && GET_CODE (result) == REG + && GET_MODE (result) == insn_mode + && REGNO (result) >= FIRST_PSEUDO_REGISTER)) + result = gen_reg_rtx (insn_mode); + + /* Make sure the operands are acceptable to the predicates. */ + + if (! (*insn_operand_predicate[(int)icode][0]) (result, insn_mode)) + result = gen_reg_rtx (insn_mode); + + src_rtx = memory_address (BLKmode, + expand_expr (src, NULL_RTX, Pmode, + EXPAND_NORMAL)); + if (! (*insn_operand_predicate[(int)icode][1]) (src_rtx, Pmode)) + src_rtx = copy_to_mode_reg (Pmode, src_rtx); + + char_rtx = const0_rtx; + char_mode = insn_operand_mode[(int)icode][2]; + if (! (*insn_operand_predicate[(int)icode][2]) (char_rtx, char_mode)) + char_rtx = copy_to_mode_reg (char_mode, char_rtx); + + emit_insn (GEN_FCN (icode) (result, + gen_rtx (MEM, BLKmode, src_rtx), + char_rtx, GEN_INT (align))); + + /* Return the value in the proper mode for this function. */ + if (GET_MODE (result) == value_mode) + return result; + else if (target != 0) + { + convert_move (target, result, 0); + return target; + } + else + return convert_to_mode (value_mode, result, 0); + } + + case BUILT_IN_STRCPY: + /* If not optimizing, call the library function. */ + if (!optimize) + break; + + if (arglist == 0 + /* Arg could be non-pointer if user redeclared this fcn wrong. */ + || TREE_CODE (TREE_TYPE (TREE_VALUE (arglist))) != POINTER_TYPE + || TREE_CHAIN (arglist) == 0 + || TREE_CODE (TREE_TYPE (TREE_VALUE (TREE_CHAIN (arglist)))) != POINTER_TYPE) + return const0_rtx; + else + { + tree len = c_strlen (TREE_VALUE (TREE_CHAIN (arglist))); + + if (len == 0) + break; + + len = size_binop (PLUS_EXPR, len, integer_one_node); + + chainon (arglist, build_tree_list (NULL_TREE, len)); + } + + /* Drops in. */ + case BUILT_IN_MEMCPY: + /* If not optimizing, call the library function. */ + if (!optimize) + break; + + if (arglist == 0 + /* Arg could be non-pointer if user redeclared this fcn wrong. */ + || TREE_CODE (TREE_TYPE (TREE_VALUE (arglist))) != POINTER_TYPE + || TREE_CHAIN (arglist) == 0 + || TREE_CODE (TREE_TYPE (TREE_VALUE (TREE_CHAIN (arglist)))) != POINTER_TYPE + || TREE_CHAIN (TREE_CHAIN (arglist)) == 0 + || TREE_CODE (TREE_TYPE (TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))))) != INTEGER_TYPE) + return const0_rtx; + else + { + tree dest = TREE_VALUE (arglist); + tree src = TREE_VALUE (TREE_CHAIN (arglist)); + tree len = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); + + int src_align + = get_pointer_alignment (src, BIGGEST_ALIGNMENT) / BITS_PER_UNIT; + int dest_align + = get_pointer_alignment (dest, BIGGEST_ALIGNMENT) / BITS_PER_UNIT; + rtx dest_rtx, dest_mem, src_mem; + + /* If either SRC or DEST is not a pointer type, don't do + this operation in-line. */ + if (src_align == 0 || dest_align == 0) + { + if (DECL_FUNCTION_CODE (fndecl) == BUILT_IN_STRCPY) + TREE_CHAIN (TREE_CHAIN (arglist)) = 0; + break; + } + + dest_rtx = expand_expr (dest, NULL_RTX, Pmode, EXPAND_NORMAL); + dest_mem = gen_rtx (MEM, BLKmode, + memory_address (BLKmode, dest_rtx)); + src_mem = gen_rtx (MEM, BLKmode, + memory_address (BLKmode, + expand_expr (src, NULL_RTX, + Pmode, + EXPAND_NORMAL))); + + /* Copy word part most expediently. */ + emit_block_move (dest_mem, src_mem, + expand_expr (len, NULL_RTX, VOIDmode, 0), + MIN (src_align, dest_align)); + return dest_rtx; + } + +/* These comparison functions need an instruction that returns an actual + index. An ordinary compare that just sets the condition codes + is not enough. */ +#ifdef HAVE_cmpstrsi + case BUILT_IN_STRCMP: + /* If not optimizing, call the library function. */ + if (!optimize) + break; + + if (arglist == 0 + /* Arg could be non-pointer if user redeclared this fcn wrong. */ + || TREE_CODE (TREE_TYPE (TREE_VALUE (arglist))) != POINTER_TYPE + || TREE_CHAIN (arglist) == 0 + || TREE_CODE (TREE_TYPE (TREE_VALUE (TREE_CHAIN (arglist)))) != POINTER_TYPE) + return const0_rtx; + else if (!HAVE_cmpstrsi) + break; + { + tree arg1 = TREE_VALUE (arglist); + tree arg2 = TREE_VALUE (TREE_CHAIN (arglist)); + tree offset; + tree len, len2; + + len = c_strlen (arg1); + if (len) + len = size_binop (PLUS_EXPR, integer_one_node, len); + len2 = c_strlen (arg2); + if (len2) + len2 = size_binop (PLUS_EXPR, integer_one_node, len2); + + /* If we don't have a constant length for the first, use the length + of the second, if we know it. We don't require a constant for + this case; some cost analysis could be done if both are available + but neither is constant. For now, assume they're equally cheap. + + If both strings have constant lengths, use the smaller. This + could arise if optimization results in strcpy being called with + two fixed strings, or if the code was machine-generated. We should + add some code to the `memcmp' handler below to deal with such + situations, someday. */ + if (!len || TREE_CODE (len) != INTEGER_CST) + { + if (len2) + len = len2; + else if (len == 0) + break; + } + else if (len2 && TREE_CODE (len2) == INTEGER_CST) + { + if (tree_int_cst_lt (len2, len)) + len = len2; + } + + chainon (arglist, build_tree_list (NULL_TREE, len)); + } + + /* Drops in. */ + case BUILT_IN_MEMCMP: + /* If not optimizing, call the library function. */ + if (!optimize) + break; + + if (arglist == 0 + /* Arg could be non-pointer if user redeclared this fcn wrong. */ + || TREE_CODE (TREE_TYPE (TREE_VALUE (arglist))) != POINTER_TYPE + || TREE_CHAIN (arglist) == 0 + || TREE_CODE (TREE_TYPE (TREE_VALUE (TREE_CHAIN (arglist)))) != POINTER_TYPE + || TREE_CHAIN (TREE_CHAIN (arglist)) == 0 + || TREE_CODE (TREE_TYPE (TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))))) != INTEGER_TYPE) + return const0_rtx; + else if (!HAVE_cmpstrsi) + break; + { + tree arg1 = TREE_VALUE (arglist); + tree arg2 = TREE_VALUE (TREE_CHAIN (arglist)); + tree len = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); + rtx result; + + int arg1_align + = get_pointer_alignment (arg1, BIGGEST_ALIGNMENT) / BITS_PER_UNIT; + int arg2_align + = get_pointer_alignment (arg2, BIGGEST_ALIGNMENT) / BITS_PER_UNIT; + enum machine_mode insn_mode + = insn_operand_mode[(int) CODE_FOR_cmpstrsi][0]; + + /* If we don't have POINTER_TYPE, call the function. */ + if (arg1_align == 0 || arg2_align == 0) + { + if (DECL_FUNCTION_CODE (fndecl) == BUILT_IN_STRCMP) + TREE_CHAIN (TREE_CHAIN (arglist)) = 0; + break; + } + + /* Make a place to write the result of the instruction. */ + result = target; + if (! (result != 0 + && GET_CODE (result) == REG && GET_MODE (result) == insn_mode + && REGNO (result) >= FIRST_PSEUDO_REGISTER)) + result = gen_reg_rtx (insn_mode); + + emit_insn (gen_cmpstrsi (result, + gen_rtx (MEM, BLKmode, + expand_expr (arg1, NULL_RTX, Pmode, + EXPAND_NORMAL)), + gen_rtx (MEM, BLKmode, + expand_expr (arg2, NULL_RTX, Pmode, + EXPAND_NORMAL)), + expand_expr (len, NULL_RTX, VOIDmode, 0), + GEN_INT (MIN (arg1_align, arg2_align)))); + + /* Return the value in the proper mode for this function. */ + mode = TYPE_MODE (TREE_TYPE (exp)); + if (GET_MODE (result) == mode) + return result; + else if (target != 0) + { + convert_move (target, result, 0); + return target; + } + else + return convert_to_mode (mode, result, 0); + } +#else + case BUILT_IN_STRCMP: + case BUILT_IN_MEMCMP: + break; +#endif + + default: /* just do library call, if unknown builtin */ + error ("built-in function `%s' not currently supported", + IDENTIFIER_POINTER (DECL_NAME (fndecl))); + } + + /* The switch statement above can drop through to cause the function + to be called normally. */ + + return expand_call (exp, target, ignore); +} + +/* Built-in functions to perform an untyped call and return. */ + +/* For each register that may be used for calling a function, this + gives a mode used to copy the register's value. VOIDmode indicates + the register is not used for calling a function. If the machine + has register windows, this gives only the outbound registers. + INCOMING_REGNO gives the corresponding inbound register. */ +static enum machine_mode apply_args_mode[FIRST_PSEUDO_REGISTER]; + +/* For each register that may be used for returning values, this gives + a mode used to copy the register's value. VOIDmode indicates the + register is not used for returning values. If the machine has + register windows, this gives only the outbound registers. + INCOMING_REGNO gives the corresponding inbound register. */ +static enum machine_mode apply_result_mode[FIRST_PSEUDO_REGISTER]; + +/* Return the size required for the block returned by __builtin_apply_args, + and initialize apply_args_mode. */ +static int +apply_args_size () +{ + static int size = -1; + int align, regno; + enum machine_mode mode; + + /* The values computed by this function never change. */ + if (size < 0) + { + /* The first value is the incoming arg-pointer. */ + size = GET_MODE_SIZE (Pmode); + + /* The second value is the structure value address unless this is + passed as an "invisible" first argument. */ + if (struct_value_rtx) + size += GET_MODE_SIZE (Pmode); + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (FUNCTION_ARG_REGNO_P (regno)) + { + /* Search for the proper mode for copying this register's + value. I'm not sure this is right, but it works so far. */ + enum machine_mode best_mode = VOIDmode; + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); + mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + if (HARD_REGNO_MODE_OK (regno, mode) + && HARD_REGNO_NREGS (regno, mode) == 1) + best_mode = mode; + + if (best_mode == VOIDmode) + for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); + mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + if (HARD_REGNO_MODE_OK (regno, mode) + && (mov_optab->handlers[(int) mode].insn_code + != CODE_FOR_nothing)) + best_mode = mode; + + mode = best_mode; + if (mode == VOIDmode) + abort (); + + align = GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT; + if (size % align != 0) + size = CEIL (size, align) * align; + size += GET_MODE_SIZE (mode); + apply_args_mode[regno] = mode; + } + else + apply_args_mode[regno] = VOIDmode; + } + return size; +} + +/* Return the size required for the block returned by __builtin_apply, + and initialize apply_result_mode. */ +static int +apply_result_size () +{ + static int size = -1; + int align, regno; + enum machine_mode mode; + + /* The values computed by this function never change. */ + if (size < 0) + { + size = 0; + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (FUNCTION_VALUE_REGNO_P (regno)) + { + /* Search for the proper mode for copying this register's + value. I'm not sure this is right, but it works so far. */ + enum machine_mode best_mode = VOIDmode; + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); + mode != TImode; + mode = GET_MODE_WIDER_MODE (mode)) + if (HARD_REGNO_MODE_OK (regno, mode)) + best_mode = mode; + + if (best_mode == VOIDmode) + for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); + mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + if (HARD_REGNO_MODE_OK (regno, mode) + && (mov_optab->handlers[(int) mode].insn_code + != CODE_FOR_nothing)) + best_mode = mode; + + mode = best_mode; + if (mode == VOIDmode) + abort (); + + align = GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT; + if (size % align != 0) + size = CEIL (size, align) * align; + size += GET_MODE_SIZE (mode); + apply_result_mode[regno] = mode; + } + else + apply_result_mode[regno] = VOIDmode; + + /* Allow targets that use untyped_call and untyped_return to override + the size so that machine-specific information can be stored here. */ +#ifdef APPLY_RESULT_SIZE + size = APPLY_RESULT_SIZE; +#endif + } + return size; +} + +#if defined (HAVE_untyped_call) || defined (HAVE_untyped_return) +/* Create a vector describing the result block RESULT. If SAVEP is true, + the result block is used to save the values; otherwise it is used to + restore the values. */ +static rtx +result_vector (savep, result) + int savep; + rtx result; +{ + int regno, size, align, nelts; + enum machine_mode mode; + rtx reg, mem; + rtx *savevec = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx)); + + size = nelts = 0; + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if ((mode = apply_result_mode[regno]) != VOIDmode) + { + align = GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT; + if (size % align != 0) + size = CEIL (size, align) * align; + reg = gen_rtx (REG, mode, savep ? INCOMING_REGNO (regno) : regno); + mem = change_address (result, mode, + plus_constant (XEXP (result, 0), size)); + savevec[nelts++] = (savep + ? gen_rtx (SET, VOIDmode, mem, reg) + : gen_rtx (SET, VOIDmode, reg, mem)); + size += GET_MODE_SIZE (mode); + } + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (nelts, savevec)); +} +#endif /* HAVE_untyped_call or HAVE_untyped_return */ + + +/* Save the state required to perform an untyped call with the same + arguments as were passed to the current function. */ +static rtx +expand_builtin_apply_args () +{ + rtx registers; + int size, align, regno; + enum machine_mode mode; + + /* Create a block where the arg-pointer, structure value address, + and argument registers can be saved. */ + registers = assign_stack_local (BLKmode, apply_args_size (), -1); + + /* Walk past the arg-pointer and structure value address. */ + size = GET_MODE_SIZE (Pmode); + if (struct_value_rtx) + size += GET_MODE_SIZE (Pmode); + + /* Save each register used in calling a function to the block. */ + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if ((mode = apply_args_mode[regno]) != VOIDmode) + { + align = GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT; + if (size % align != 0) + size = CEIL (size, align) * align; + emit_move_insn (change_address (registers, mode, + plus_constant (XEXP (registers, 0), + size)), + gen_rtx (REG, mode, INCOMING_REGNO (regno))); + size += GET_MODE_SIZE (mode); + } + + /* Save the arg pointer to the block. */ + emit_move_insn (change_address (registers, Pmode, XEXP (registers, 0)), + copy_to_reg (virtual_incoming_args_rtx)); + size = GET_MODE_SIZE (Pmode); + + /* Save the structure value address unless this is passed as an + "invisible" first argument. */ + if (struct_value_incoming_rtx) + { + emit_move_insn (change_address (registers, Pmode, + plus_constant (XEXP (registers, 0), + size)), + copy_to_reg (struct_value_incoming_rtx)); + size += GET_MODE_SIZE (Pmode); + } + + /* Return the address of the block. */ + return copy_addr_to_reg (XEXP (registers, 0)); +} + +/* Perform an untyped call and save the state required to perform an + untyped return of whatever value was returned by the given function. */ +static rtx +expand_builtin_apply (function, arguments, argsize) + rtx function, arguments, argsize; +{ + int size, align, regno; + enum machine_mode mode; + rtx incoming_args, result, reg, dest, call_insn; + rtx old_stack_level = 0; + rtx use_insns = 0; + + /* Create a block where the return registers can be saved. */ + result = assign_stack_local (BLKmode, apply_result_size (), -1); + + /* ??? The argsize value should be adjusted here. */ + + /* Fetch the arg pointer from the ARGUMENTS block. */ + incoming_args = gen_reg_rtx (Pmode); + emit_move_insn (incoming_args, + gen_rtx (MEM, Pmode, arguments)); +#ifndef STACK_GROWS_DOWNWARD + incoming_args = expand_binop (Pmode, add_optab, incoming_args, argsize, + incoming_args, 0, OPTAB_LIB_WIDEN); +#endif + + /* Perform postincrements before actually calling the function. */ + emit_queue (); + + /* Push a new argument block and copy the arguments. */ + do_pending_stack_adjust (); + emit_stack_save (SAVE_BLOCK, &old_stack_level, NULL_RTX); + + /* Push a block of memory onto the stack to store the memory arguments. + Save the address in a register, and copy the memory arguments. ??? I + haven't figured out how the calling convention macros effect this, + but it's likely that the source and/or destination addresses in + the block copy will need updating in machine specific ways. */ + dest = copy_addr_to_reg (push_block (argsize, 0, 0)); + emit_block_move (gen_rtx (MEM, BLKmode, dest), + gen_rtx (MEM, BLKmode, incoming_args), + argsize, + PARM_BOUNDARY / BITS_PER_UNIT); + + /* Refer to the argument block. */ + apply_args_size (); + arguments = gen_rtx (MEM, BLKmode, arguments); + + /* Walk past the arg-pointer and structure value address. */ + size = GET_MODE_SIZE (Pmode); + if (struct_value_rtx) + size += GET_MODE_SIZE (Pmode); + + /* Restore each of the registers previously saved. Make USE insns + for each of these registers for use in making the call. */ + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if ((mode = apply_args_mode[regno]) != VOIDmode) + { + align = GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT; + if (size % align != 0) + size = CEIL (size, align) * align; + reg = gen_rtx (REG, mode, regno); + emit_move_insn (reg, + change_address (arguments, mode, + plus_constant (XEXP (arguments, 0), + size))); + + push_to_sequence (use_insns); + emit_insn (gen_rtx (USE, VOIDmode, reg)); + use_insns = get_insns (); + end_sequence (); + size += GET_MODE_SIZE (mode); + } + + /* Restore the structure value address unless this is passed as an + "invisible" first argument. */ + size = GET_MODE_SIZE (Pmode); + if (struct_value_rtx) + { + rtx value = gen_reg_rtx (Pmode); + emit_move_insn (value, + change_address (arguments, Pmode, + plus_constant (XEXP (arguments, 0), + size))); + emit_move_insn (struct_value_rtx, value); + if (GET_CODE (struct_value_rtx) == REG) + { + push_to_sequence (use_insns); + emit_insn (gen_rtx (USE, VOIDmode, struct_value_rtx)); + use_insns = get_insns (); + end_sequence (); + } + size += GET_MODE_SIZE (Pmode); + } + + /* All arguments and registers used for the call are set up by now! */ + function = prepare_call_address (function, NULL_TREE, &use_insns); + + /* Ensure address is valid. SYMBOL_REF is already valid, so no need, + and we don't want to load it into a register as an optimization, + because prepare_call_address already did it if it should be done. */ + if (GET_CODE (function) != SYMBOL_REF) + function = memory_address (FUNCTION_MODE, function); + + /* Generate the actual call instruction and save the return value. */ +#ifdef HAVE_untyped_call + if (HAVE_untyped_call) + emit_call_insn (gen_untyped_call (gen_rtx (MEM, FUNCTION_MODE, function), + result, result_vector (1, result))); + else +#endif +#ifdef HAVE_call_value + if (HAVE_call_value) + { + rtx valreg = 0; + + /* Locate the unique return register. It is not possible to + express a call that sets more than one return register using + call_value; use untyped_call for that. In fact, untyped_call + only needs to save the return registers in the given block. */ + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if ((mode = apply_result_mode[regno]) != VOIDmode) + { + if (valreg) + abort (); /* HAVE_untyped_call required. */ + valreg = gen_rtx (REG, mode, regno); + } + + emit_call_insn (gen_call_value (valreg, + gen_rtx (MEM, FUNCTION_MODE, function), + const0_rtx, NULL_RTX, const0_rtx)); + + emit_move_insn (change_address (result, GET_MODE (valreg), + XEXP (result, 0)), + valreg); + } + else +#endif + abort (); + + /* Find the CALL insn we just emitted and write the USE insns before it. */ + for (call_insn = get_last_insn (); + call_insn && GET_CODE (call_insn) != CALL_INSN; + call_insn = PREV_INSN (call_insn)) + ; + + if (! call_insn) + abort (); + + /* Put the USE insns before the CALL. */ + emit_insns_before (use_insns, call_insn); + + /* Restore the stack. */ + emit_stack_restore (SAVE_BLOCK, old_stack_level, NULL_RTX); + + /* Return the address of the result block. */ + return copy_addr_to_reg (XEXP (result, 0)); +} + +/* Perform an untyped return. */ +static void +expand_builtin_return (result) + rtx result; +{ + int size, align, regno; + enum machine_mode mode; + rtx reg; + rtx use_insns = 0; + + apply_result_size (); + result = gen_rtx (MEM, BLKmode, result); + +#ifdef HAVE_untyped_return + if (HAVE_untyped_return) + { + emit_jump_insn (gen_untyped_return (result, result_vector (0, result))); + emit_barrier (); + return; + } +#endif + + /* Restore the return value and note that each value is used. */ + size = 0; + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if ((mode = apply_result_mode[regno]) != VOIDmode) + { + align = GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT; + if (size % align != 0) + size = CEIL (size, align) * align; + reg = gen_rtx (REG, mode, INCOMING_REGNO (regno)); + emit_move_insn (reg, + change_address (result, mode, + plus_constant (XEXP (result, 0), + size))); + + push_to_sequence (use_insns); + emit_insn (gen_rtx (USE, VOIDmode, reg)); + use_insns = get_insns (); + end_sequence (); + size += GET_MODE_SIZE (mode); + } + + /* Put the USE insns before the return. */ + emit_insns (use_insns); + + /* Return whatever values was restored by jumping directly to the end + of the function. */ + expand_null_return (); +} + +/* Expand code for a post- or pre- increment or decrement + and return the RTX for the result. + POST is 1 for postinc/decrements and 0 for preinc/decrements. */ + +static rtx +expand_increment (exp, post) + register tree exp; + int post; +{ + register rtx op0, op1; + register rtx temp, value; + register tree incremented = TREE_OPERAND (exp, 0); + optab this_optab = add_optab; + int icode; + enum machine_mode mode = TYPE_MODE (TREE_TYPE (exp)); + int op0_is_copy = 0; + + /* Stabilize any component ref that might need to be + evaluated more than once below. */ + if (!post + || TREE_CODE (incremented) == BIT_FIELD_REF + || (TREE_CODE (incremented) == COMPONENT_REF + && (TREE_CODE (TREE_OPERAND (incremented, 0)) != INDIRECT_REF + || DECL_BIT_FIELD (TREE_OPERAND (incremented, 1))))) + incremented = stabilize_reference (incremented); + + /* Compute the operands as RTX. + Note whether OP0 is the actual lvalue or a copy of it: + I believe it is a copy iff it is a register or subreg + and insns were generated in computing it. */ + + temp = get_last_insn (); + op0 = expand_expr (incremented, NULL_RTX, VOIDmode, 0); + + /* If OP0 is a SUBREG made for a promoted variable, we cannot increment + in place but intead must do sign- or zero-extension during assignment, + so we copy it into a new register and let the code below use it as + a copy. + + Note that we can safely modify this SUBREG since it is know not to be + shared (it was made by the expand_expr call above). */ + + if (GET_CODE (op0) == SUBREG && SUBREG_PROMOTED_VAR_P (op0)) + SUBREG_REG (op0) = copy_to_reg (SUBREG_REG (op0)); + + op0_is_copy = ((GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) + && temp != get_last_insn ()); + op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, VOIDmode, 0); + + /* Decide whether incrementing or decrementing. */ + if (TREE_CODE (exp) == POSTDECREMENT_EXPR + || TREE_CODE (exp) == PREDECREMENT_EXPR) + this_optab = sub_optab; + + /* If OP0 is not the actual lvalue, but rather a copy in a register, + then we cannot just increment OP0. We must therefore contrive to + increment the original value. Then, for postincrement, we can return + OP0 since it is a copy of the old value. For preincrement, we want + to always expand here, since this generates better or equivalent code. */ + if (!post || op0_is_copy) + { + /* This is the easiest way to increment the value wherever it is. + Problems with multiple evaluation of INCREMENTED are prevented + because either (1) it is a component_ref or preincrement, + in which case it was stabilized above, or (2) it is an array_ref + with constant index in an array in a register, which is + safe to reevaluate. */ + tree newexp = build ((this_optab == add_optab + ? PLUS_EXPR : MINUS_EXPR), + TREE_TYPE (exp), + incremented, + TREE_OPERAND (exp, 1)); + temp = expand_assignment (incremented, newexp, ! post, 0); + return post ? op0 : temp; + } + + /* Convert decrement by a constant into a negative increment. */ + if (this_optab == sub_optab + && GET_CODE (op1) == CONST_INT) + { + op1 = GEN_INT (- INTVAL (op1)); + this_optab = add_optab; + } + + if (post) + { + /* We have a true reference to the value in OP0. + If there is an insn to add or subtract in this mode, queue it. */ + +#if 0 /* Turned off to avoid making extra insn for indexed memref. */ + op0 = stabilize (op0); +#endif + + icode = (int) this_optab->handlers[(int) mode].insn_code; + if (icode != (int) CODE_FOR_nothing + /* Make sure that OP0 is valid for operands 0 and 1 + of the insn we want to queue. */ + && (*insn_operand_predicate[icode][0]) (op0, mode) + && (*insn_operand_predicate[icode][1]) (op0, mode)) + { + if (! (*insn_operand_predicate[icode][2]) (op1, mode)) + op1 = force_reg (mode, op1); + + return enqueue_insn (op0, GEN_FCN (icode) (op0, op0, op1)); + } + } + + /* Preincrement, or we can't increment with one simple insn. */ + if (post) + /* Save a copy of the value before inc or dec, to return it later. */ + temp = value = copy_to_reg (op0); + else + /* Arrange to return the incremented value. */ + /* Copy the rtx because expand_binop will protect from the queue, + and the results of that would be invalid for us to return + if our caller does emit_queue before using our result. */ + temp = copy_rtx (value = op0); + + /* Increment however we can. */ + op1 = expand_binop (mode, this_optab, value, op1, op0, + TREE_UNSIGNED (TREE_TYPE (exp)), OPTAB_LIB_WIDEN); + /* Make sure the value is stored into OP0. */ + if (op1 != op0) + emit_move_insn (op0, op1); + + return temp; +} + +/* Expand all function calls contained within EXP, innermost ones first. + But don't look within expressions that have sequence points. + For each CALL_EXPR, record the rtx for its value + in the CALL_EXPR_RTL field. */ + +static void +preexpand_calls (exp) + tree exp; +{ + register int nops, i; + int type = TREE_CODE_CLASS (TREE_CODE (exp)); + + if (! do_preexpand_calls) + return; + + /* Only expressions and references can contain calls. */ + + if (type != 'e' && type != '<' && type != '1' && type != '2' && type != 'r') + return; + + switch (TREE_CODE (exp)) + { + case CALL_EXPR: + /* Do nothing if already expanded. */ + if (CALL_EXPR_RTL (exp) != 0) + return; + + /* Do nothing to built-in functions. */ + if (TREE_CODE (TREE_OPERAND (exp, 0)) != ADDR_EXPR + || TREE_CODE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0)) != FUNCTION_DECL + || ! DECL_BUILT_IN (TREE_OPERAND (TREE_OPERAND (exp, 0), 0))) + CALL_EXPR_RTL (exp) = expand_call (exp, NULL_RTX, 0); + return; + + case COMPOUND_EXPR: + case COND_EXPR: + case TRUTH_ANDIF_EXPR: + case TRUTH_ORIF_EXPR: + /* If we find one of these, then we can be sure + the adjust will be done for it (since it makes jumps). + Do it now, so that if this is inside an argument + of a function, we don't get the stack adjustment + after some other args have already been pushed. */ + do_pending_stack_adjust (); + return; + + case BLOCK: + case RTL_EXPR: + case WITH_CLEANUP_EXPR: + return; + + case SAVE_EXPR: + if (SAVE_EXPR_RTL (exp) != 0) + return; + } + + nops = tree_code_length[(int) TREE_CODE (exp)]; + for (i = 0; i < nops; i++) + if (TREE_OPERAND (exp, i) != 0) + { + type = TREE_CODE_CLASS (TREE_CODE (TREE_OPERAND (exp, i))); + if (type == 'e' || type == '<' || type == '1' || type == '2' + || type == 'r') + preexpand_calls (TREE_OPERAND (exp, i)); + } +} + +/* At the start of a function, record that we have no previously-pushed + arguments waiting to be popped. */ + +void +init_pending_stack_adjust () +{ + pending_stack_adjust = 0; +} + +/* When exiting from function, if safe, clear out any pending stack adjust + so the adjustment won't get done. */ + +void +clear_pending_stack_adjust () +{ +#ifdef EXIT_IGNORE_STACK + if (! flag_omit_frame_pointer && EXIT_IGNORE_STACK + && ! (DECL_INLINE (current_function_decl) && ! flag_no_inline) + && ! flag_inline_functions) + pending_stack_adjust = 0; +#endif +} + +/* Pop any previously-pushed arguments that have not been popped yet. */ + +void +do_pending_stack_adjust () +{ + if (inhibit_defer_pop == 0) + { + if (pending_stack_adjust != 0) + adjust_stack (GEN_INT (pending_stack_adjust)); + pending_stack_adjust = 0; + } +} + +/* Expand all cleanups up to OLD_CLEANUPS. + Needed here, and also for language-dependent calls. */ + +void +expand_cleanups_to (old_cleanups) + tree old_cleanups; +{ + while (cleanups_this_call != old_cleanups) + { + expand_expr (TREE_VALUE (cleanups_this_call), NULL_RTX, VOIDmode, 0); + cleanups_this_call = TREE_CHAIN (cleanups_this_call); + } +} + +/* Expand conditional expressions. */ + +/* Generate code to evaluate EXP and jump to LABEL if the value is zero. + LABEL is an rtx of code CODE_LABEL, in this function and all the + functions here. */ + +void +jumpifnot (exp, label) + tree exp; + rtx label; +{ + do_jump (exp, label, NULL_RTX); +} + +/* Generate code to evaluate EXP and jump to LABEL if the value is nonzero. */ + +void +jumpif (exp, label) + tree exp; + rtx label; +{ + do_jump (exp, NULL_RTX, label); +} + +/* Generate code to evaluate EXP and jump to IF_FALSE_LABEL if + the result is zero, or IF_TRUE_LABEL if the result is one. + Either of IF_FALSE_LABEL and IF_TRUE_LABEL may be zero, + meaning fall through in that case. + + do_jump always does any pending stack adjust except when it does not + actually perform a jump. An example where there is no jump + is when EXP is `(foo (), 0)' and IF_FALSE_LABEL is null. + + This function is responsible for optimizing cases such as + &&, || and comparison operators in EXP. */ + +void +do_jump (exp, if_false_label, if_true_label) + tree exp; + rtx if_false_label, if_true_label; +{ + register enum tree_code code = TREE_CODE (exp); + /* Some cases need to create a label to jump to + in order to properly fall through. + These cases set DROP_THROUGH_LABEL nonzero. */ + rtx drop_through_label = 0; + rtx temp; + rtx comparison = 0; + int i; + tree type; + + emit_queue (); + + switch (code) + { + case ERROR_MARK: + break; + + case INTEGER_CST: + temp = integer_zerop (exp) ? if_false_label : if_true_label; + if (temp) + emit_jump (temp); + break; + +#if 0 + /* This is not true with #pragma weak */ + case ADDR_EXPR: + /* The address of something can never be zero. */ + if (if_true_label) + emit_jump (if_true_label); + break; +#endif + + case NOP_EXPR: + if (TREE_CODE (TREE_OPERAND (exp, 0)) == COMPONENT_REF + || TREE_CODE (TREE_OPERAND (exp, 0)) == BIT_FIELD_REF + || TREE_CODE (TREE_OPERAND (exp, 0)) == ARRAY_REF) + goto normal; + case CONVERT_EXPR: + /* If we are narrowing the operand, we have to do the compare in the + narrower mode. */ + if ((TYPE_PRECISION (TREE_TYPE (exp)) + < TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (exp, 0))))) + goto normal; + case NON_LVALUE_EXPR: + case REFERENCE_EXPR: + case ABS_EXPR: + case NEGATE_EXPR: + case LROTATE_EXPR: + case RROTATE_EXPR: + /* These cannot change zero->non-zero or vice versa. */ + do_jump (TREE_OPERAND (exp, 0), if_false_label, if_true_label); + break; + +#if 0 + /* This is never less insns than evaluating the PLUS_EXPR followed by + a test and can be longer if the test is eliminated. */ + case PLUS_EXPR: + /* Reduce to minus. */ + exp = build (MINUS_EXPR, TREE_TYPE (exp), + TREE_OPERAND (exp, 0), + fold (build1 (NEGATE_EXPR, TREE_TYPE (TREE_OPERAND (exp, 1)), + TREE_OPERAND (exp, 1)))); + /* Process as MINUS. */ +#endif + + case MINUS_EXPR: + /* Non-zero iff operands of minus differ. */ + comparison = compare (build (NE_EXPR, TREE_TYPE (exp), + TREE_OPERAND (exp, 0), + TREE_OPERAND (exp, 1)), + NE, NE); + break; + + case BIT_AND_EXPR: + /* If we are AND'ing with a small constant, do this comparison in the + smallest type that fits. If the machine doesn't have comparisons + that small, it will be converted back to the wider comparison. + This helps if we are testing the sign bit of a narrower object. + combine can't do this for us because it can't know whether a + ZERO_EXTRACT or a compare in a smaller mode exists, but we do. */ + + if (! SLOW_BYTE_ACCESS + && TREE_CODE (TREE_OPERAND (exp, 1)) == INTEGER_CST + && TYPE_PRECISION (TREE_TYPE (exp)) <= HOST_BITS_PER_WIDE_INT + && (i = floor_log2 (TREE_INT_CST_LOW (TREE_OPERAND (exp, 1)))) >= 0 + && (type = type_for_size (i + 1, 1)) != 0 + && TYPE_PRECISION (type) < TYPE_PRECISION (TREE_TYPE (exp)) + && (cmp_optab->handlers[(int) TYPE_MODE (type)].insn_code + != CODE_FOR_nothing)) + { + do_jump (convert (type, exp), if_false_label, if_true_label); + break; + } + goto normal; + + case TRUTH_NOT_EXPR: + do_jump (TREE_OPERAND (exp, 0), if_true_label, if_false_label); + break; + + case TRUTH_ANDIF_EXPR: + if (if_false_label == 0) + if_false_label = drop_through_label = gen_label_rtx (); + do_jump (TREE_OPERAND (exp, 0), if_false_label, NULL_RTX); + do_jump (TREE_OPERAND (exp, 1), if_false_label, if_true_label); + break; + + case TRUTH_ORIF_EXPR: + if (if_true_label == 0) + if_true_label = drop_through_label = gen_label_rtx (); + do_jump (TREE_OPERAND (exp, 0), NULL_RTX, if_true_label); + do_jump (TREE_OPERAND (exp, 1), if_false_label, if_true_label); + break; + + case COMPOUND_EXPR: + expand_expr (TREE_OPERAND (exp, 0), const0_rtx, VOIDmode, 0); + free_temp_slots (); + emit_queue (); + do_pending_stack_adjust (); + do_jump (TREE_OPERAND (exp, 1), if_false_label, if_true_label); + break; + + case COMPONENT_REF: + case BIT_FIELD_REF: + case ARRAY_REF: + { + int bitsize, bitpos, unsignedp; + enum machine_mode mode; + tree type; + tree offset; + int volatilep = 0; + + /* Get description of this reference. We don't actually care + about the underlying object here. */ + get_inner_reference (exp, &bitsize, &bitpos, &offset, + &mode, &unsignedp, &volatilep); + + type = type_for_size (bitsize, unsignedp); + if (! SLOW_BYTE_ACCESS + && type != 0 && bitsize >= 0 + && TYPE_PRECISION (type) < TYPE_PRECISION (TREE_TYPE (exp)) + && (cmp_optab->handlers[(int) TYPE_MODE (type)].insn_code + != CODE_FOR_nothing)) + { + do_jump (convert (type, exp), if_false_label, if_true_label); + break; + } + goto normal; + } + + case COND_EXPR: + /* Do (a ? 1 : 0) and (a ? 0 : 1) as special cases. */ + if (integer_onep (TREE_OPERAND (exp, 1)) + && integer_zerop (TREE_OPERAND (exp, 2))) + do_jump (TREE_OPERAND (exp, 0), if_false_label, if_true_label); + + else if (integer_zerop (TREE_OPERAND (exp, 1)) + && integer_onep (TREE_OPERAND (exp, 2))) + do_jump (TREE_OPERAND (exp, 0), if_true_label, if_false_label); + + else + { + register rtx label1 = gen_label_rtx (); + drop_through_label = gen_label_rtx (); + do_jump (TREE_OPERAND (exp, 0), label1, NULL_RTX); + /* Now the THEN-expression. */ + do_jump (TREE_OPERAND (exp, 1), + if_false_label ? if_false_label : drop_through_label, + if_true_label ? if_true_label : drop_through_label); + /* In case the do_jump just above never jumps. */ + do_pending_stack_adjust (); + emit_label (label1); + /* Now the ELSE-expression. */ + do_jump (TREE_OPERAND (exp, 2), + if_false_label ? if_false_label : drop_through_label, + if_true_label ? if_true_label : drop_through_label); + } + break; + + case EQ_EXPR: + if (integer_zerop (TREE_OPERAND (exp, 1))) + do_jump (TREE_OPERAND (exp, 0), if_true_label, if_false_label); + else if ((GET_MODE_CLASS (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))) + == MODE_INT) + && + !can_compare_p (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))))) + do_jump_by_parts_equality (exp, if_false_label, if_true_label); + else + comparison = compare (exp, EQ, EQ); + break; + + case NE_EXPR: + if (integer_zerop (TREE_OPERAND (exp, 1))) + do_jump (TREE_OPERAND (exp, 0), if_false_label, if_true_label); + else if ((GET_MODE_CLASS (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))) + == MODE_INT) + && + !can_compare_p (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))))) + do_jump_by_parts_equality (exp, if_true_label, if_false_label); + else + comparison = compare (exp, NE, NE); + break; + + case LT_EXPR: + if ((GET_MODE_CLASS (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))) + == MODE_INT) + && !can_compare_p (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))))) + do_jump_by_parts_greater (exp, 1, if_false_label, if_true_label); + else + comparison = compare (exp, LT, LTU); + break; + + case LE_EXPR: + if ((GET_MODE_CLASS (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))) + == MODE_INT) + && !can_compare_p (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))))) + do_jump_by_parts_greater (exp, 0, if_true_label, if_false_label); + else + comparison = compare (exp, LE, LEU); + break; + + case GT_EXPR: + if ((GET_MODE_CLASS (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))) + == MODE_INT) + && !can_compare_p (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))))) + do_jump_by_parts_greater (exp, 0, if_false_label, if_true_label); + else + comparison = compare (exp, GT, GTU); + break; + + case GE_EXPR: + if ((GET_MODE_CLASS (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))) + == MODE_INT) + && !can_compare_p (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))))) + do_jump_by_parts_greater (exp, 1, if_true_label, if_false_label); + else + comparison = compare (exp, GE, GEU); + break; + + default: + normal: + temp = expand_expr (exp, NULL_RTX, VOIDmode, 0); +#if 0 + /* This is not needed any more and causes poor code since it causes + comparisons and tests from non-SI objects to have different code + sequences. */ + /* Copy to register to avoid generating bad insns by cse + from (set (mem ...) (arithop)) (set (cc0) (mem ...)). */ + if (!cse_not_expected && GET_CODE (temp) == MEM) + temp = copy_to_reg (temp); +#endif + do_pending_stack_adjust (); + if (GET_CODE (temp) == CONST_INT) + comparison = (temp == const0_rtx ? const0_rtx : const_true_rtx); + else if (GET_CODE (temp) == LABEL_REF) + comparison = const_true_rtx; + else if (GET_MODE_CLASS (GET_MODE (temp)) == MODE_INT + && !can_compare_p (GET_MODE (temp))) + /* Note swapping the labels gives us not-equal. */ + do_jump_by_parts_equality_rtx (temp, if_true_label, if_false_label); + else if (GET_MODE (temp) != VOIDmode) + comparison = compare_from_rtx (temp, CONST0_RTX (GET_MODE (temp)), + NE, TREE_UNSIGNED (TREE_TYPE (exp)), + GET_MODE (temp), NULL_RTX, 0); + else + abort (); + } + + /* Do any postincrements in the expression that was tested. */ + emit_queue (); + + /* If COMPARISON is nonzero here, it is an rtx that can be substituted + straight into a conditional jump instruction as the jump condition. + Otherwise, all the work has been done already. */ + + if (comparison == const_true_rtx) + { + if (if_true_label) + emit_jump (if_true_label); + } + else if (comparison == const0_rtx) + { + if (if_false_label) + emit_jump (if_false_label); + } + else if (comparison) + do_jump_for_compare (comparison, if_false_label, if_true_label); + + free_temp_slots (); + + if (drop_through_label) + { + /* If do_jump produces code that might be jumped around, + do any stack adjusts from that code, before the place + where control merges in. */ + do_pending_stack_adjust (); + emit_label (drop_through_label); + } +} + +/* Given a comparison expression EXP for values too wide to be compared + with one insn, test the comparison and jump to the appropriate label. + The code of EXP is ignored; we always test GT if SWAP is 0, + and LT if SWAP is 1. */ + +static void +do_jump_by_parts_greater (exp, swap, if_false_label, if_true_label) + tree exp; + int swap; + rtx if_false_label, if_true_label; +{ + rtx op0 = expand_expr (TREE_OPERAND (exp, swap), NULL_RTX, VOIDmode, 0); + rtx op1 = expand_expr (TREE_OPERAND (exp, !swap), NULL_RTX, VOIDmode, 0); + enum machine_mode mode = TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))); + int nwords = (GET_MODE_SIZE (mode) / UNITS_PER_WORD); + rtx drop_through_label = 0; + int unsignedp = TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 0))); + int i; + + if (! if_true_label || ! if_false_label) + drop_through_label = gen_label_rtx (); + if (! if_true_label) + if_true_label = drop_through_label; + if (! if_false_label) + if_false_label = drop_through_label; + + /* Compare a word at a time, high order first. */ + for (i = 0; i < nwords; i++) + { + rtx comp; + rtx op0_word, op1_word; + + if (WORDS_BIG_ENDIAN) + { + op0_word = operand_subword_force (op0, i, mode); + op1_word = operand_subword_force (op1, i, mode); + } + else + { + op0_word = operand_subword_force (op0, nwords - 1 - i, mode); + op1_word = operand_subword_force (op1, nwords - 1 - i, mode); + } + + /* All but high-order word must be compared as unsigned. */ + comp = compare_from_rtx (op0_word, op1_word, + (unsignedp || i > 0) ? GTU : GT, + unsignedp, word_mode, NULL_RTX, 0); + if (comp == const_true_rtx) + emit_jump (if_true_label); + else if (comp != const0_rtx) + do_jump_for_compare (comp, NULL_RTX, if_true_label); + + /* Consider lower words only if these are equal. */ + comp = compare_from_rtx (op0_word, op1_word, NE, unsignedp, word_mode, + NULL_RTX, 0); + if (comp == const_true_rtx) + emit_jump (if_false_label); + else if (comp != const0_rtx) + do_jump_for_compare (comp, NULL_RTX, if_false_label); + } + + if (if_false_label) + emit_jump (if_false_label); + if (drop_through_label) + emit_label (drop_through_label); +} + +/* Compare OP0 with OP1, word at a time, in mode MODE. + UNSIGNEDP says to do unsigned comparison. + Jump to IF_TRUE_LABEL if OP0 is greater, IF_FALSE_LABEL otherwise. */ + +static void +do_jump_by_parts_greater_rtx (mode, unsignedp, op0, op1, if_false_label, if_true_label) + enum machine_mode mode; + int unsignedp; + rtx op0, op1; + rtx if_false_label, if_true_label; +{ + int nwords = (GET_MODE_SIZE (mode) / UNITS_PER_WORD); + rtx drop_through_label = 0; + int i; + + if (! if_true_label || ! if_false_label) + drop_through_label = gen_label_rtx (); + if (! if_true_label) + if_true_label = drop_through_label; + if (! if_false_label) + if_false_label = drop_through_label; + + /* Compare a word at a time, high order first. */ + for (i = 0; i < nwords; i++) + { + rtx comp; + rtx op0_word, op1_word; + + if (WORDS_BIG_ENDIAN) + { + op0_word = operand_subword_force (op0, i, mode); + op1_word = operand_subword_force (op1, i, mode); + } + else + { + op0_word = operand_subword_force (op0, nwords - 1 - i, mode); + op1_word = operand_subword_force (op1, nwords - 1 - i, mode); + } + + /* All but high-order word must be compared as unsigned. */ + comp = compare_from_rtx (op0_word, op1_word, + (unsignedp || i > 0) ? GTU : GT, + unsignedp, word_mode, NULL_RTX, 0); + if (comp == const_true_rtx) + emit_jump (if_true_label); + else if (comp != const0_rtx) + do_jump_for_compare (comp, NULL_RTX, if_true_label); + + /* Consider lower words only if these are equal. */ + comp = compare_from_rtx (op0_word, op1_word, NE, unsignedp, word_mode, + NULL_RTX, 0); + if (comp == const_true_rtx) + emit_jump (if_false_label); + else if (comp != const0_rtx) + do_jump_for_compare (comp, NULL_RTX, if_false_label); + } + + if (if_false_label) + emit_jump (if_false_label); + if (drop_through_label) + emit_label (drop_through_label); +} + +/* Given an EQ_EXPR expression EXP for values too wide to be compared + with one insn, test the comparison and jump to the appropriate label. */ + +static void +do_jump_by_parts_equality (exp, if_false_label, if_true_label) + tree exp; + rtx if_false_label, if_true_label; +{ + rtx op0 = expand_expr (TREE_OPERAND (exp, 0), NULL_RTX, VOIDmode, 0); + rtx op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, VOIDmode, 0); + enum machine_mode mode = TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))); + int nwords = (GET_MODE_SIZE (mode) / UNITS_PER_WORD); + int i; + rtx drop_through_label = 0; + + if (! if_false_label) + drop_through_label = if_false_label = gen_label_rtx (); + + for (i = 0; i < nwords; i++) + { + rtx comp = compare_from_rtx (operand_subword_force (op0, i, mode), + operand_subword_force (op1, i, mode), + EQ, TREE_UNSIGNED (TREE_TYPE (exp)), + word_mode, NULL_RTX, 0); + if (comp == const_true_rtx) + emit_jump (if_false_label); + else if (comp != const0_rtx) + do_jump_for_compare (comp, if_false_label, NULL_RTX); + } + + if (if_true_label) + emit_jump (if_true_label); + if (drop_through_label) + emit_label (drop_through_label); +} + +/* Jump according to whether OP0 is 0. + We assume that OP0 has an integer mode that is too wide + for the available compare insns. */ + +static void +do_jump_by_parts_equality_rtx (op0, if_false_label, if_true_label) + rtx op0; + rtx if_false_label, if_true_label; +{ + int nwords = GET_MODE_SIZE (GET_MODE (op0)) / UNITS_PER_WORD; + int i; + rtx drop_through_label = 0; + + if (! if_false_label) + drop_through_label = if_false_label = gen_label_rtx (); + + for (i = 0; i < nwords; i++) + { + rtx comp = compare_from_rtx (operand_subword_force (op0, i, + GET_MODE (op0)), + const0_rtx, EQ, 1, word_mode, NULL_RTX, 0); + if (comp == const_true_rtx) + emit_jump (if_false_label); + else if (comp != const0_rtx) + do_jump_for_compare (comp, if_false_label, NULL_RTX); + } + + if (if_true_label) + emit_jump (if_true_label); + if (drop_through_label) + emit_label (drop_through_label); +} + +/* Given a comparison expression in rtl form, output conditional branches to + IF_TRUE_LABEL, IF_FALSE_LABEL, or both. */ + +static void +do_jump_for_compare (comparison, if_false_label, if_true_label) + rtx comparison, if_false_label, if_true_label; +{ + if (if_true_label) + { + if (bcc_gen_fctn[(int) GET_CODE (comparison)] != 0) + emit_jump_insn ((*bcc_gen_fctn[(int) GET_CODE (comparison)]) (if_true_label)); + else + abort (); + + if (if_false_label) + emit_jump (if_false_label); + } + else if (if_false_label) + { + rtx insn; + rtx prev = PREV_INSN (get_last_insn ()); + rtx branch = 0; + + /* Output the branch with the opposite condition. Then try to invert + what is generated. If more than one insn is a branch, or if the + branch is not the last insn written, abort. If we can't invert + the branch, emit make a true label, redirect this jump to that, + emit a jump to the false label and define the true label. */ + + if (bcc_gen_fctn[(int) GET_CODE (comparison)] != 0) + emit_jump_insn ((*bcc_gen_fctn[(int) GET_CODE (comparison)]) (if_false_label)); + else + abort (); + + /* Here we get the insn before what was just emitted. + On some machines, emitting the branch can discard + the previous compare insn and emit a replacement. */ + if (prev == 0) + /* If there's only one preceding insn... */ + insn = get_insns (); + else + insn = NEXT_INSN (prev); + + for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == JUMP_INSN) + { + if (branch) + abort (); + branch = insn; + } + + if (branch != get_last_insn ()) + abort (); + + if (! invert_jump (branch, if_false_label)) + { + if_true_label = gen_label_rtx (); + redirect_jump (branch, if_true_label); + emit_jump (if_false_label); + emit_label (if_true_label); + } + } +} + +/* Generate code for a comparison expression EXP + (including code to compute the values to be compared) + and set (CC0) according to the result. + SIGNED_CODE should be the rtx operation for this comparison for + signed data; UNSIGNED_CODE, likewise for use if data is unsigned. + + We force a stack adjustment unless there are currently + things pushed on the stack that aren't yet used. */ + +static rtx +compare (exp, signed_code, unsigned_code) + register tree exp; + enum rtx_code signed_code, unsigned_code; +{ + register rtx op0 + = expand_expr (TREE_OPERAND (exp, 0), NULL_RTX, VOIDmode, 0); + register rtx op1 + = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, VOIDmode, 0); + register tree type = TREE_TYPE (TREE_OPERAND (exp, 0)); + register enum machine_mode mode = TYPE_MODE (type); + int unsignedp = TREE_UNSIGNED (type); + enum rtx_code code = unsignedp ? unsigned_code : signed_code; + + return compare_from_rtx (op0, op1, code, unsignedp, mode, + ((mode == BLKmode) + ? expr_size (TREE_OPERAND (exp, 0)) : NULL_RTX), + TYPE_ALIGN (TREE_TYPE (exp)) / BITS_PER_UNIT); +} + +/* Like compare but expects the values to compare as two rtx's. + The decision as to signed or unsigned comparison must be made by the caller. + + If MODE is BLKmode, SIZE is an RTX giving the size of the objects being + compared. + + If ALIGN is non-zero, it is the alignment of this type; if zero, the + size of MODE should be used. */ + +rtx +compare_from_rtx (op0, op1, code, unsignedp, mode, size, align) + register rtx op0, op1; + enum rtx_code code; + int unsignedp; + enum machine_mode mode; + rtx size; + int align; +{ + rtx tem; + + /* If one operand is constant, make it the second one. Only do this + if the other operand is not constant as well. */ + + if ((CONSTANT_P (op0) && ! CONSTANT_P (op1)) + || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT)) + { + tem = op0; + op0 = op1; + op1 = tem; + code = swap_condition (code); + } + + if (flag_force_mem) + { + op0 = force_not_mem (op0); + op1 = force_not_mem (op1); + } + + do_pending_stack_adjust (); + + if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT + && (tem = simplify_relational_operation (code, mode, op0, op1)) != 0) + return tem; + +#if 0 + /* There's no need to do this now that combine.c can eliminate lots of + sign extensions. This can be less efficient in certain cases on other + machines. */ + + /* If this is a signed equality comparison, we can do it as an + unsigned comparison since zero-extension is cheaper than sign + extension and comparisons with zero are done as unsigned. This is + the case even on machines that can do fast sign extension, since + zero-extension is easier to combine with other operations than + sign-extension is. If we are comparing against a constant, we must + convert it to what it would look like unsigned. */ + if ((code == EQ || code == NE) && ! unsignedp + && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT) + { + if (GET_CODE (op1) == CONST_INT + && (INTVAL (op1) & GET_MODE_MASK (GET_MODE (op0))) != INTVAL (op1)) + op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (GET_MODE (op0))); + unsignedp = 1; + } +#endif + + emit_cmp_insn (op0, op1, code, size, mode, unsignedp, align); + + return gen_rtx (code, VOIDmode, cc0_rtx, const0_rtx); +} + +/* Generate code to calculate EXP using a store-flag instruction + and return an rtx for the result. EXP is either a comparison + or a TRUTH_NOT_EXPR whose operand is a comparison. + + If TARGET is nonzero, store the result there if convenient. + + If ONLY_CHEAP is non-zero, only do this if it is likely to be very + cheap. + + Return zero if there is no suitable set-flag instruction + available on this machine. + + Once expand_expr has been called on the arguments of the comparison, + we are committed to doing the store flag, since it is not safe to + re-evaluate the expression. We emit the store-flag insn by calling + emit_store_flag, but only expand the arguments if we have a reason + to believe that emit_store_flag will be successful. If we think that + it will, but it isn't, we have to simulate the store-flag with a + set/jump/set sequence. */ + +static rtx +do_store_flag (exp, target, mode, only_cheap) + tree exp; + rtx target; + enum machine_mode mode; + int only_cheap; +{ + enum rtx_code code; + tree arg0, arg1, type; + tree tem; + enum machine_mode operand_mode; + int invert = 0; + int unsignedp; + rtx op0, op1; + enum insn_code icode; + rtx subtarget = target; + rtx result, label, pattern, jump_pat; + + /* If this is a TRUTH_NOT_EXPR, set a flag indicating we must invert the + result at the end. We can't simply invert the test since it would + have already been inverted if it were valid. This case occurs for + some floating-point comparisons. */ + + if (TREE_CODE (exp) == TRUTH_NOT_EXPR) + invert = 1, exp = TREE_OPERAND (exp, 0); + + arg0 = TREE_OPERAND (exp, 0); + arg1 = TREE_OPERAND (exp, 1); + type = TREE_TYPE (arg0); + operand_mode = TYPE_MODE (type); + unsignedp = TREE_UNSIGNED (type); + + /* We won't bother with BLKmode store-flag operations because it would mean + passing a lot of information to emit_store_flag. */ + if (operand_mode == BLKmode) + return 0; + + STRIP_NOPS (arg0); + STRIP_NOPS (arg1); + + /* Get the rtx comparison code to use. We know that EXP is a comparison + operation of some type. Some comparisons against 1 and -1 can be + converted to comparisons with zero. Do so here so that the tests + below will be aware that we have a comparison with zero. These + tests will not catch constants in the first operand, but constants + are rarely passed as the first operand. */ + + switch (TREE_CODE (exp)) + { + case EQ_EXPR: + code = EQ; + break; + case NE_EXPR: + code = NE; + break; + case LT_EXPR: + if (integer_onep (arg1)) + arg1 = integer_zero_node, code = unsignedp ? LEU : LE; + else + code = unsignedp ? LTU : LT; + break; + case LE_EXPR: + if (! unsignedp && integer_all_onesp (arg1)) + arg1 = integer_zero_node, code = LT; + else + code = unsignedp ? LEU : LE; + break; + case GT_EXPR: + if (! unsignedp && integer_all_onesp (arg1)) + arg1 = integer_zero_node, code = GE; + else + code = unsignedp ? GTU : GT; + break; + case GE_EXPR: + if (integer_onep (arg1)) + arg1 = integer_zero_node, code = unsignedp ? GTU : GT; + else + code = unsignedp ? GEU : GE; + break; + default: + abort (); + } + + /* Put a constant second. */ + if (TREE_CODE (arg0) == REAL_CST || TREE_CODE (arg0) == INTEGER_CST) + { + tem = arg0; arg0 = arg1; arg1 = tem; + code = swap_condition (code); + } + + /* If this is an equality or inequality test of a single bit, we can + do this by shifting the bit being tested to the low-order bit and + masking the result with the constant 1. If the condition was EQ, + we xor it with 1. This does not require an scc insn and is faster + than an scc insn even if we have it. */ + + if ((code == NE || code == EQ) + && TREE_CODE (arg0) == BIT_AND_EXPR && integer_zerop (arg1) + && integer_pow2p (TREE_OPERAND (arg0, 1)) + && TYPE_PRECISION (type) <= HOST_BITS_PER_WIDE_INT) + { + int bitnum = exact_log2 (INTVAL (expand_expr (TREE_OPERAND (arg0, 1), + NULL_RTX, VOIDmode, 0))); + + if (subtarget == 0 || GET_CODE (subtarget) != REG + || GET_MODE (subtarget) != operand_mode + || ! safe_from_p (subtarget, TREE_OPERAND (arg0, 0))) + subtarget = 0; + + op0 = expand_expr (TREE_OPERAND (arg0, 0), subtarget, VOIDmode, 0); + + if (bitnum != 0) + op0 = expand_shift (RSHIFT_EXPR, GET_MODE (op0), op0, + size_int (bitnum), target, 1); + + if (GET_MODE (op0) != mode) + op0 = convert_to_mode (mode, op0, 1); + + if (bitnum != TYPE_PRECISION (type) - 1) + op0 = expand_and (op0, const1_rtx, target); + + if ((code == EQ && ! invert) || (code == NE && invert)) + op0 = expand_binop (mode, xor_optab, op0, const1_rtx, target, 0, + OPTAB_LIB_WIDEN); + + return op0; + } + + /* Now see if we are likely to be able to do this. Return if not. */ + if (! can_compare_p (operand_mode)) + return 0; + icode = setcc_gen_code[(int) code]; + if (icode == CODE_FOR_nothing + || (only_cheap && insn_operand_mode[(int) icode][0] != mode)) + { + /* We can only do this if it is one of the special cases that + can be handled without an scc insn. */ + if ((code == LT && integer_zerop (arg1)) + || (! only_cheap && code == GE && integer_zerop (arg1))) + ; + else if (BRANCH_COST >= 0 + && ! only_cheap && (code == NE || code == EQ) + && TREE_CODE (type) != REAL_TYPE + && ((abs_optab->handlers[(int) operand_mode].insn_code + != CODE_FOR_nothing) + || (ffs_optab->handlers[(int) operand_mode].insn_code + != CODE_FOR_nothing))) + ; + else + return 0; + } + + preexpand_calls (exp); + if (subtarget == 0 || GET_CODE (subtarget) != REG + || GET_MODE (subtarget) != operand_mode + || ! safe_from_p (subtarget, arg1)) + subtarget = 0; + + op0 = expand_expr (arg0, subtarget, VOIDmode, 0); + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + + if (target == 0) + target = gen_reg_rtx (mode); + + /* Pass copies of OP0 and OP1 in case they contain a QUEUED. This is safe + because, if the emit_store_flag does anything it will succeed and + OP0 and OP1 will not be used subsequently. */ + + result = emit_store_flag (target, code, + queued_subexp_p (op0) ? copy_rtx (op0) : op0, + queued_subexp_p (op1) ? copy_rtx (op1) : op1, + operand_mode, unsignedp, 1); + + if (result) + { + if (invert) + result = expand_binop (mode, xor_optab, result, const1_rtx, + result, 0, OPTAB_LIB_WIDEN); + return result; + } + + /* If this failed, we have to do this with set/compare/jump/set code. */ + if (target == 0 || GET_CODE (target) != REG + || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1)) + target = gen_reg_rtx (GET_MODE (target)); + + emit_move_insn (target, invert ? const0_rtx : const1_rtx); + result = compare_from_rtx (op0, op1, code, unsignedp, + operand_mode, NULL_RTX, 0); + if (GET_CODE (result) == CONST_INT) + return (((result == const0_rtx && ! invert) + || (result != const0_rtx && invert)) + ? const0_rtx : const1_rtx); + + label = gen_label_rtx (); + if (bcc_gen_fctn[(int) code] == 0) + abort (); + + emit_jump_insn ((*bcc_gen_fctn[(int) code]) (label)); + emit_move_insn (target, invert ? const1_rtx : const0_rtx); + emit_label (label); + + return target; +} + +/* Generate a tablejump instruction (used for switch statements). */ + +#ifdef HAVE_tablejump + +/* INDEX is the value being switched on, with the lowest value + in the table already subtracted. + MODE is its expected mode (needed if INDEX is constant). + RANGE is the length of the jump table. + TABLE_LABEL is a CODE_LABEL rtx for the table itself. + + DEFAULT_LABEL is a CODE_LABEL rtx to jump to if the + index value is out of range. */ + +void +do_tablejump (index, mode, range, table_label, default_label) + rtx index, range, table_label, default_label; + enum machine_mode mode; +{ + register rtx temp, vector; + + /* Do an unsigned comparison (in the proper mode) between the index + expression and the value which represents the length of the range. + Since we just finished subtracting the lower bound of the range + from the index expression, this comparison allows us to simultaneously + check that the original index expression value is both greater than + or equal to the minimum value of the range and less than or equal to + the maximum value of the range. */ + + emit_cmp_insn (range, index, LTU, NULL_RTX, mode, 1, 0); + emit_jump_insn (gen_bltu (default_label)); + + /* If index is in range, it must fit in Pmode. + Convert to Pmode so we can index with it. */ + if (mode != Pmode) + index = convert_to_mode (Pmode, index, 1); + + /* If flag_force_addr were to affect this address + it could interfere with the tricky assumptions made + about addresses that contain label-refs, + which may be valid only very near the tablejump itself. */ + /* ??? The only correct use of CASE_VECTOR_MODE is the one inside the + GET_MODE_SIZE, because this indicates how large insns are. The other + uses should all be Pmode, because they are addresses. This code + could fail if addresses and insns are not the same size. */ + index = memory_address_noforce + (CASE_VECTOR_MODE, + gen_rtx (PLUS, Pmode, + gen_rtx (MULT, Pmode, index, + GEN_INT (GET_MODE_SIZE (CASE_VECTOR_MODE))), + gen_rtx (LABEL_REF, Pmode, table_label))); + temp = gen_reg_rtx (CASE_VECTOR_MODE); + vector = gen_rtx (MEM, CASE_VECTOR_MODE, index); + RTX_UNCHANGING_P (vector) = 1; + convert_move (temp, vector, 0); + + emit_jump_insn (gen_tablejump (temp, table_label)); + +#ifndef CASE_VECTOR_PC_RELATIVE + /* If we are generating PIC code or if the table is PC-relative, the + table and JUMP_INSN must be adjacent, so don't output a BARRIER. */ + if (! flag_pic) + emit_barrier (); +#endif +} + +#endif /* HAVE_tablejump */ diff --git a/gnu/usr.bin/cc/lib/expr.h b/gnu/usr.bin/cc/lib/expr.h new file mode 100644 index 000000000000..972c62cbf6b6 --- /dev/null +++ b/gnu/usr.bin/cc/lib/expr.h @@ -0,0 +1,812 @@ +/* Definitions for code generation pass of GNU compiler. + Copyright (C) 1987, 1991, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#ifndef __STDC__ +#ifndef const +#define const +#endif +#endif + +/* The default branch cost is 1. */ +#ifndef BRANCH_COST +#define BRANCH_COST 1 +#endif + +/* The default is that we do not promote the mode of an object. */ +#ifndef PROMOTE_MODE +#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) +#endif + +/* Macros to access the slots of a QUEUED rtx. + Here rather than in rtl.h because only the expansion pass + should ever encounter a QUEUED. */ + +/* The variable for which an increment is queued. */ +#define QUEUED_VAR(P) XEXP (P, 0) +/* If the increment has been emitted, this is the insn + that does the increment. It is zero before the increment is emitted. */ +#define QUEUED_INSN(P) XEXP (P, 1) +/* If a pre-increment copy has been generated, this is the copy + (it is a temporary reg). Zero if no copy made yet. */ +#define QUEUED_COPY(P) XEXP (P, 2) +/* This is the body to use for the insn to do the increment. + It is used to emit the increment. */ +#define QUEUED_BODY(P) XEXP (P, 3) +/* Next QUEUED in the queue. */ +#define QUEUED_NEXT(P) XEXP (P, 4) + +/* This is the 4th arg to `expand_expr'. + EXPAND_SUM means it is ok to return a PLUS rtx or MULT rtx. + EXPAND_INITIALIZER is similar but also record any labels on forced_labels. + EXPAND_CONST_ADDRESS means it is ok to return a MEM whose address + is a constant that is not a legitimate address. */ +enum expand_modifier {EXPAND_NORMAL, EXPAND_SUM, + EXPAND_CONST_ADDRESS, EXPAND_INITIALIZER}; + +/* List of labels that must never be deleted. */ +extern rtx forced_labels; + +/* List (chain of EXPR_LISTs) of pseudo-regs of SAVE_EXPRs. + So we can mark them all live at the end of the function, if stupid. */ +extern rtx save_expr_regs; + +extern int current_function_calls_alloca; +extern int current_function_outgoing_args_size; + +/* This is the offset from the arg pointer to the place where the first + anonymous arg can be found, if there is one. */ +extern rtx current_function_arg_offset_rtx; + +/* This is nonzero if the current function uses the constant pool. */ +extern int current_function_uses_const_pool; + +/* This is nonzero if the current function uses pic_offset_table_rtx. */ +extern int current_function_uses_pic_offset_table; + +/* The arg pointer hard register, or the pseudo into which it was copied. */ +extern rtx current_function_internal_arg_pointer; + +/* Nonzero means stack pops must not be deferred, and deferred stack + pops must not be output. It is nonzero inside a function call, + inside a conditional expression, inside a statement expression, + and in other cases as well. */ +extern int inhibit_defer_pop; + +/* Number of function calls seen so far in current function. */ + +extern int function_call_count; + +/* RTX for stack slot that holds the current handler for nonlocal gotos. + Zero when function does not have nonlocal labels. */ + +extern rtx nonlocal_goto_handler_slot; + +/* RTX for stack slot that holds the stack pointer value to restore + for a nonlocal goto. + Zero when function does not have nonlocal labels. */ + +extern rtx nonlocal_goto_stack_level; + +/* List (chain of TREE_LIST) of LABEL_DECLs for all nonlocal labels + (labels to which there can be nonlocal gotos from nested functions) + in this function. */ + +#ifdef TREE_CODE /* Don't lose if tree.h not included. */ +extern tree nonlocal_labels; +#endif + +#define NO_DEFER_POP (inhibit_defer_pop += 1) +#define OK_DEFER_POP (inhibit_defer_pop -= 1) + +/* Number of units that we should eventually pop off the stack. + These are the arguments to function calls that have already returned. */ +extern int pending_stack_adjust; + +/* A list of all cleanups which belong to the arguments of + function calls being expanded by expand_call. */ +#ifdef TREE_CODE /* Don't lose if tree.h not included. */ +extern tree cleanups_this_call; +#endif + +#ifdef TREE_CODE /* Don't lose if tree.h not included. */ +/* Structure to record the size of a sequence of arguments + as the sum of a tree-expression and a constant. */ + +struct args_size +{ + int constant; + tree var; +}; +#endif + +/* Add the value of the tree INC to the `struct args_size' TO. */ + +#define ADD_PARM_SIZE(TO, INC) \ +{ tree inc = (INC); \ + if (TREE_CODE (inc) == INTEGER_CST) \ + (TO).constant += TREE_INT_CST_LOW (inc); \ + else if ((TO).var == 0) \ + (TO).var = inc; \ + else \ + (TO).var = size_binop (PLUS_EXPR, (TO).var, inc); } + +#define SUB_PARM_SIZE(TO, DEC) \ +{ tree dec = (DEC); \ + if (TREE_CODE (dec) == INTEGER_CST) \ + (TO).constant -= TREE_INT_CST_LOW (dec); \ + else if ((TO).var == 0) \ + (TO).var = size_binop (MINUS_EXPR, integer_zero_node, dec); \ + else \ + (TO).var = size_binop (MINUS_EXPR, (TO).var, dec); } + +/* Convert the implicit sum in a `struct args_size' into an rtx. */ +#define ARGS_SIZE_RTX(SIZE) \ +((SIZE).var == 0 ? GEN_INT ((SIZE).constant) \ + : expand_expr (size_binop (PLUS_EXPR, (SIZE).var, \ + size_int ((SIZE).constant)), \ + NULL_RTX, VOIDmode, 0)) + +/* Convert the implicit sum in a `struct args_size' into a tree. */ +#define ARGS_SIZE_TREE(SIZE) \ +((SIZE).var == 0 ? size_int ((SIZE).constant) \ + : size_binop (PLUS_EXPR, (SIZE).var, size_int ((SIZE).constant))) + +/* Supply a default definition for FUNCTION_ARG_PADDING: + usually pad upward, but pad short args downward on + big-endian machines. */ + +enum direction {none, upward, downward}; /* Value has this type. */ + +#ifndef FUNCTION_ARG_PADDING +#if BYTES_BIG_ENDIAN +#define FUNCTION_ARG_PADDING(MODE, TYPE) \ + (((MODE) == BLKmode \ + ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ + && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT)) \ + : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY) \ + ? downward : upward) +#else +#define FUNCTION_ARG_PADDING(MODE, TYPE) upward +#endif +#endif + +/* Supply a default definition for FUNCTION_ARG_BOUNDARY. Normally, we let + FUNCTION_ARG_PADDING, which also pads the length, handle any needed + alignment. */ + +#ifndef FUNCTION_ARG_BOUNDARY +#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) PARM_BOUNDARY +#endif + +/* Nonzero if we do not know how to pass TYPE solely in registers. + We cannot do so in the following cases: + + - if the type has variable size + - if the type is marked as addressable (it is required to be constructed + into the stack) + - if the padding and mode of the type is such that a copy into a register + would put it into the wrong part of the register. + + Which padding can't be supported depends on the byte endianness. + + A value in a register is implicitly padded at the most significant end. + On a big-endian machine, that is the lower end in memory. + So a value padded in memory at the upper end can't go in a register. + For a little-endian machine, the reverse is true. */ + +#if BYTES_BIG_ENDIAN +#define MUST_PASS_IN_STACK_BAD_PADDING upward +#else +#define MUST_PASS_IN_STACK_BAD_PADDING downward +#endif + +#define MUST_PASS_IN_STACK(MODE,TYPE) \ + ((TYPE) != 0 \ + && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ + || TREE_ADDRESSABLE (TYPE) \ + || ((MODE) == BLKmode \ + && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ + && 0 == (int_size_in_bytes (TYPE) \ + % (PARM_BOUNDARY / BITS_PER_UNIT))) \ + && (FUNCTION_ARG_PADDING (MODE, TYPE) \ + == MUST_PASS_IN_STACK_BAD_PADDING)))) + +/* Nonzero if type TYPE should be returned in memory. + Most machines can use the following default definition. */ + +#ifndef RETURN_IN_MEMORY +#define RETURN_IN_MEMORY(TYPE) (TYPE_MODE (TYPE) == BLKmode) +#endif + +/* Optabs are tables saying how to generate insn bodies + for various machine modes and numbers of operands. + Each optab applies to one operation. + For example, add_optab applies to addition. + + The insn_code slot is the enum insn_code that says how to + generate an insn for this operation on a particular machine mode. + It is CODE_FOR_nothing if there is no such insn on the target machine. + + The `lib_call' slot is the name of the library function that + can be used to perform the operation. + + A few optabs, such as move_optab and cmp_optab, are used + by special code. */ + +/* Everything that uses expr.h needs to define enum insn_code + but we don't list it in the Makefile dependencies just for that. */ +#include "insn-codes.h" + +typedef struct optab +{ + enum rtx_code code; + struct { + enum insn_code insn_code; + rtx libfunc; + } handlers [NUM_MACHINE_MODES]; +} * optab; + +/* Given an enum insn_code, access the function to construct + the body of that kind of insn. */ +#ifdef FUNCTION_CONVERSION_BUG +/* Some compilers fail to convert a function properly to a + pointer-to-function when used as an argument. + So produce the pointer-to-function directly. + Luckily, these compilers seem to work properly when you + call the pointer-to-function. */ +#define GEN_FCN(CODE) (insn_gen_function[(int) (CODE)]) +#else +#define GEN_FCN(CODE) (*insn_gen_function[(int) (CODE)]) +#endif + +extern rtx (*const insn_gen_function[]) (); + +extern optab add_optab; +extern optab sub_optab; +extern optab smul_optab; /* Signed and floating-point multiply */ +extern optab smul_widen_optab; /* Signed multiply with result + one machine mode wider than args */ +extern optab umul_widen_optab; +extern optab sdiv_optab; /* Signed divide */ +extern optab sdivmod_optab; /* Signed divide-and-remainder in one */ +extern optab udiv_optab; +extern optab udivmod_optab; +extern optab smod_optab; /* Signed remainder */ +extern optab umod_optab; +extern optab flodiv_optab; /* Optab for floating divide. */ +extern optab ftrunc_optab; /* Convert float to integer in float fmt */ +extern optab and_optab; /* Logical and */ +extern optab ior_optab; /* Logical or */ +extern optab xor_optab; /* Logical xor */ +extern optab ashl_optab; /* Arithmetic shift left */ +extern optab ashr_optab; /* Arithmetic shift right */ +extern optab lshl_optab; /* Logical shift left */ +extern optab lshr_optab; /* Logical shift right */ +extern optab rotl_optab; /* Rotate left */ +extern optab rotr_optab; /* Rotate right */ +extern optab smin_optab; /* Signed and floating-point minimum value */ +extern optab smax_optab; /* Signed and floating-point maximum value */ +extern optab umin_optab; /* Unsigned minimum value */ +extern optab umax_optab; /* Unsigned maximum value */ + +extern optab mov_optab; /* Move instruction. */ +extern optab movstrict_optab; /* Move, preserving high part of register. */ + +extern optab cmp_optab; /* Compare insn; two operands. */ +extern optab tst_optab; /* tst insn; compare one operand against 0 */ + +/* Unary operations */ +extern optab neg_optab; /* Negation */ +extern optab abs_optab; /* Abs value */ +extern optab one_cmpl_optab; /* Bitwise not */ +extern optab ffs_optab; /* Find first bit set */ +extern optab sqrt_optab; /* Square root */ +extern optab sin_optab; /* Sine */ +extern optab cos_optab; /* Cosine */ +extern optab strlen_optab; /* String length */ + +/* Tables of patterns for extending one integer mode to another. */ +extern enum insn_code extendtab[MAX_MACHINE_MODE][MAX_MACHINE_MODE][2]; + +/* Tables of patterns for converting between fixed and floating point. */ +extern enum insn_code fixtab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2]; +extern enum insn_code fixtrunctab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2]; +extern enum insn_code floattab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2]; + +/* Passed to expand_binop and expand_unop to say which options to try to use + if the requested operation can't be open-coded on the requisite mode. + Either OPTAB_LIB or OPTAB_LIB_WIDEN says try using a library call. + Either OPTAB_WIDEN or OPTAB_LIB_WIDEN says try using a wider mode. + OPTAB_MUST_WIDEN says try widening and don't try anything else. */ + +enum optab_methods +{ + OPTAB_DIRECT, + OPTAB_LIB, + OPTAB_WIDEN, + OPTAB_LIB_WIDEN, + OPTAB_MUST_WIDEN +}; + +/* SYMBOL_REF rtx's for the library functions that are called + implicitly and not via optabs. */ + +extern rtx extendsfdf2_libfunc; +extern rtx extendsfxf2_libfunc; +extern rtx extendsftf2_libfunc; +extern rtx extenddfxf2_libfunc; +extern rtx extenddftf2_libfunc; + +extern rtx truncdfsf2_libfunc; +extern rtx truncxfsf2_libfunc; +extern rtx trunctfsf2_libfunc; +extern rtx truncxfdf2_libfunc; +extern rtx trunctfdf2_libfunc; + +extern rtx memcpy_libfunc; +extern rtx bcopy_libfunc; +extern rtx memcmp_libfunc; +extern rtx bcmp_libfunc; +extern rtx memset_libfunc; +extern rtx bzero_libfunc; + +extern rtx eqsf2_libfunc; +extern rtx nesf2_libfunc; +extern rtx gtsf2_libfunc; +extern rtx gesf2_libfunc; +extern rtx ltsf2_libfunc; +extern rtx lesf2_libfunc; + +extern rtx eqdf2_libfunc; +extern rtx nedf2_libfunc; +extern rtx gtdf2_libfunc; +extern rtx gedf2_libfunc; +extern rtx ltdf2_libfunc; +extern rtx ledf2_libfunc; + +extern rtx eqxf2_libfunc; +extern rtx nexf2_libfunc; +extern rtx gtxf2_libfunc; +extern rtx gexf2_libfunc; +extern rtx ltxf2_libfunc; +extern rtx lexf2_libfunc; + +extern rtx eqtf2_libfunc; +extern rtx netf2_libfunc; +extern rtx gttf2_libfunc; +extern rtx getf2_libfunc; +extern rtx lttf2_libfunc; +extern rtx letf2_libfunc; + +extern rtx floatsisf_libfunc; +extern rtx floatdisf_libfunc; +extern rtx floattisf_libfunc; + +extern rtx floatsidf_libfunc; +extern rtx floatdidf_libfunc; +extern rtx floattidf_libfunc; + +extern rtx floatsixf_libfunc; +extern rtx floatdixf_libfunc; +extern rtx floattixf_libfunc; + +extern rtx floatsitf_libfunc; +extern rtx floatditf_libfunc; +extern rtx floattitf_libfunc; + +extern rtx fixsfsi_libfunc; +extern rtx fixsfdi_libfunc; +extern rtx fixsfti_libfunc; + +extern rtx fixdfsi_libfunc; +extern rtx fixdfdi_libfunc; +extern rtx fixdfti_libfunc; + +extern rtx fixxfsi_libfunc; +extern rtx fixxfdi_libfunc; +extern rtx fixxfti_libfunc; + +extern rtx fixtfsi_libfunc; +extern rtx fixtfdi_libfunc; +extern rtx fixtfti_libfunc; + +extern rtx fixunssfsi_libfunc; +extern rtx fixunssfdi_libfunc; +extern rtx fixunssfti_libfunc; + +extern rtx fixunsdfsi_libfunc; +extern rtx fixunsdfdi_libfunc; +extern rtx fixunsdfti_libfunc; + +extern rtx fixunsxfsi_libfunc; +extern rtx fixunsxfdi_libfunc; +extern rtx fixunsxfti_libfunc; + +extern rtx fixunstfsi_libfunc; +extern rtx fixunstfdi_libfunc; +extern rtx fixunstfti_libfunc; + +typedef rtx (*rtxfun) (); + +/* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) + gives the gen_function to make a branch to test that condition. */ + +extern rtxfun bcc_gen_fctn[NUM_RTX_CODE]; + +/* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) + gives the insn code to make a store-condition insn + to test that condition. */ + +extern enum insn_code setcc_gen_code[NUM_RTX_CODE]; + +/* This array records the insn_code of insns to perform block moves. */ +extern enum insn_code movstr_optab[NUM_MACHINE_MODES]; + +/* Define functions given in optabs.c. */ + +/* Expand a binary operation given optab and rtx operands. */ +extern rtx expand_binop PROTO((enum machine_mode, optab, rtx, rtx, rtx, + int, enum optab_methods)); + +/* Expand a binary operation with both signed and unsigned forms. */ +extern rtx sign_expand_binop PROTO((enum machine_mode, optab, optab, rtx, + rtx, rtx, int, enum optab_methods)); + +/* Generate code to perform an operation on two operands with two results. */ +extern int expand_twoval_binop PROTO((optab, rtx, rtx, rtx, rtx, int)); + +/* Expand a unary arithmetic operation given optab rtx operand. */ +extern rtx expand_unop PROTO((enum machine_mode, optab, rtx, rtx, int)); + +/* Expand the complex absolute value operation. */ +extern rtx expand_complex_abs PROTO((enum machine_mode, rtx, rtx, int)); + +/* Generate an instruction with a given INSN_CODE with an output and + an input. */ +extern void emit_unop_insn PROTO((int, rtx, rtx, enum rtx_code)); + +/* Emit code to perform a series of operations on a multi-word quantity, one + word at a time. */ +extern rtx emit_no_conflict_block PROTO((rtx, rtx, rtx, rtx, rtx)); + +/* Emit code to make a call to a constant function or a library call. */ +extern void emit_libcall_block PROTO((rtx, rtx, rtx, rtx)); + +/* Emit one rtl instruction to store zero in specified rtx. */ +extern void emit_clr_insn PROTO((rtx)); + +/* Emit one rtl insn to store 1 in specified rtx assuming it contains 0. */ +extern void emit_0_to_1_insn PROTO((rtx)); + +/* Emit one rtl insn to compare two rtx's. */ +extern void emit_cmp_insn PROTO((rtx, rtx, enum rtx_code, rtx, + enum machine_mode, int, int)); + +/* Nonzero if a compare of mode MODE can be done straightforwardly + (without splitting it into pieces). */ +extern int can_compare_p PROTO((enum machine_mode)); + +/* Generate code to indirectly jump to a location given in the rtx LOC. */ +extern void emit_indirect_jump PROTO((rtx)); + +/* Create but don't emit one rtl instruction to add one rtx into another. + Modes must match; operands must meet the operation's predicates. + Likewise for subtraction and for just copying. + These do not call protect_from_queue; caller must do so. */ +extern rtx gen_add2_insn PROTO((rtx, rtx)); +extern rtx gen_sub2_insn PROTO((rtx, rtx)); +extern rtx gen_move_insn PROTO((rtx, rtx)); +extern int have_add2_insn PROTO((enum machine_mode)); +extern int have_sub2_insn PROTO((enum machine_mode)); + +/* Return the INSN_CODE to use for an extend operation. */ +extern enum insn_code can_extend_p PROTO((enum machine_mode, + enum machine_mode, int)); + +/* Generate the body of an insn to extend Y (with mode MFROM) + into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ +extern rtx gen_extend_insn PROTO((rtx, rtx, enum machine_mode, + enum machine_mode, int)); + +/* Initialize the tables that control conversion between fixed and + floating values. */ +extern void init_fixtab PROTO((void)); +extern void init_floattab PROTO((void)); + +/* Generate code for a FLOAT_EXPR. */ +extern void expand_float PROTO((rtx, rtx, int)); + +/* Generate code for a FIX_EXPR. */ +extern void expand_fix PROTO((rtx, rtx, int)); + +/* Call this once to initialize the contents of the optabs + appropriately for the current target machine. */ +extern void init_optabs PROTO((void)); + +/* Functions from expmed.c: */ + +/* Arguments MODE, RTX: return an rtx for the negation of that value. + May emit insns. */ +extern rtx negate_rtx PROTO((enum machine_mode, rtx)); + +/* Expand a logical AND operation. */ +extern rtx expand_and PROTO((rtx, rtx, rtx)); + +/* Emit a store-flag operation. */ +extern rtx emit_store_flag PROTO((rtx, enum rtx_code, rtx, rtx, + enum machine_mode, int, int)); + +/* Functions from loop.c: */ + +/* Given a JUMP_INSN, return a description of the test being made. */ +extern rtx get_condition PROTO((rtx, rtx *)); + +/* Functions from expr.c: */ + +/* This is run once per compilation to set up which modes can be used + directly in memory and to initialize the block move optab. */ +extern void init_expr_once PROTO((void)); + +/* This is run at the start of compiling a function. */ +extern void init_expr PROTO((void)); + +/* Use protect_from_queue to convert a QUEUED expression + into something that you can put immediately into an instruction. */ +extern rtx protect_from_queue PROTO((rtx, int)); + +/* Perform all the pending incrementations. */ +extern void emit_queue PROTO((void)); + +/* Emit some rtl insns to move data between rtx's, converting machine modes. + Both modes must be floating or both fixed. */ +extern void convert_move PROTO((rtx, rtx, int)); + +/* Convert an rtx to specified machine mode and return the result. */ +extern rtx convert_to_mode PROTO((enum machine_mode, rtx, int)); + +/* Emit code to move a block Y to a block X. */ +extern void emit_block_move PROTO((rtx, rtx, rtx, int)); + +/* Copy all or part of a value X into registers starting at REGNO. + The number of registers to be filled is NREGS. */ +extern void move_block_to_reg PROTO((int, rtx, int, enum machine_mode)); + +/* Copy all or part of a BLKmode value X out of registers starting at REGNO. + The number of registers to be filled is NREGS. */ +extern void move_block_from_reg PROTO((int, rtx, int)); + +/* Mark NREGS consecutive regs, starting at REGNO, as being live now. */ +extern void use_regs PROTO((int, int)); + +/* Write zeros through the storage of OBJECT. + If OBJECT has BLKmode, SIZE is its length in bytes. */ +extern void clear_storage PROTO((rtx, int)); + +/* Emit insns to set X from Y. */ +extern rtx emit_move_insn PROTO((rtx, rtx)); + +/* Emit insns to set X from Y, with no frills. */ +extern rtx emit_move_insn_1 PROTO ((rtx, rtx)); + +/* Push a block of length SIZE (perhaps variable) + and return an rtx to address the beginning of the block. */ +extern rtx push_block PROTO((rtx, int, int)); + +/* Make an operand to push someting on the stack. */ +extern rtx gen_push_operand PROTO((void)); + +#ifdef TREE_CODE +/* Generate code to push something onto the stack, given its mode and type. */ +extern void emit_push_insn PROTO((rtx, enum machine_mode, tree, rtx, int, + int, rtx, int, rtx, rtx)); + +/* Emit library call. These cannot have accurate prototypes since they have + a variable number of args. */ +extern void emit_library_call (); +extern void emit_library_call_value (); + +/* Expand an assignment that stores the value of FROM into TO. */ +extern rtx expand_assignment PROTO((tree, tree, int, int)); + +/* Generate code for computing expression EXP, + and storing the value into TARGET. + If SUGGEST_REG is nonzero, copy the value through a register + and return that register, if that is possible. */ +extern rtx store_expr PROTO((tree, rtx, int)); +#endif + +/* Given an rtx that may include add and multiply operations, + generate them as insns and return a pseudo-reg containing the value. + Useful after calling expand_expr with 1 as sum_ok. */ +extern rtx force_operand PROTO((rtx, rtx)); + +#ifdef TREE_CODE +/* Generate code for computing expression EXP. + An rtx for the computed value is returned. The value is never null. + In the case of a void EXP, const0_rtx is returned. */ +extern rtx expand_expr PROTO((tree, rtx, enum machine_mode, + enum expand_modifier)); +#endif + +/* At the start of a function, record that we have no previously-pushed + arguments waiting to be popped. */ +extern void init_pending_stack_adjust PROTO((void)); + +/* When exiting from function, if safe, clear out any pending stack adjust + so the adjustment won't get done. */ +extern void clear_pending_stack_adjust PROTO((void)); + +/* Pop any previously-pushed arguments that have not been popped yet. */ +extern void do_pending_stack_adjust PROTO((void)); + +#ifdef TREE_CODE +/* Expand all cleanups up to OLD_CLEANUPS. */ +extern void expand_cleanups_to PROTO((tree)); + +/* Generate code to evaluate EXP and jump to LABEL if the value is zero. */ +extern void jumpifnot PROTO((tree, rtx)); + +/* Generate code to evaluate EXP and jump to LABEL if the value is nonzero. */ +extern void jumpif PROTO((tree, rtx)); + +/* Generate code to evaluate EXP and jump to IF_FALSE_LABEL if + the result is zero, or IF_TRUE_LABEL if the result is one. */ +extern void do_jump PROTO((tree, rtx, rtx)); +#endif + +/* Generate rtl to compare two rtx's, will call emit_cmp_insn. */ +extern rtx compare_from_rtx PROTO((rtx, rtx, enum rtx_code, int, + enum machine_mode, rtx, int)); + +/* Generate a tablejump instruction (used for switch statements). */ +extern void do_tablejump PROTO((rtx, enum machine_mode, rtx, rtx, rtx)); + +#ifdef TREE_CODE +/* rtl.h and tree.h were included. */ +/* Return an rtx for the size in bytes of the value of an expr. */ +extern rtx expr_size PROTO((tree)); + +extern rtx lookup_static_chain PROTO((tree)); + +/* Convert a stack slot address ADDR valid in function FNDECL + into an address valid in this function (using a static chain). */ +extern rtx fix_lexical_addr PROTO((rtx, tree)); + +/* Return the address of the trampoline for entering nested fn FUNCTION. */ +extern rtx trampoline_address PROTO((tree)); + +/* Return an rtx that refers to the value returned by a function + in its original home. This becomes invalid if any more code is emitted. */ +extern rtx hard_function_value PROTO((tree, tree)); + +extern rtx prepare_call_address PROTO((rtx, tree, rtx *)); + +extern rtx expand_call PROTO((tree, rtx, int)); + +extern rtx expand_shift PROTO((enum tree_code, enum machine_mode, rtx, tree, rtx, int)); +extern rtx expand_divmod PROTO((int, enum tree_code, enum machine_mode, rtx, rtx, rtx, int)); +extern void locate_and_pad_parm PROTO((enum machine_mode, tree, int, tree, struct args_size *, struct args_size *, struct args_size *)); +extern rtx expand_inline_function PROTO((tree, tree, rtx, int, tree, rtx)); +/* Return the CODE_LABEL rtx for a LABEL_DECL, creating it if necessary. */ +extern rtx label_rtx PROTO((tree)); +#endif + +/* Indicate how an input argument register was promoted. */ +extern rtx promoted_input_arg PROTO((int, enum machine_mode *, int *)); + +/* Return an rtx like arg but sans any constant terms. + Returns the original rtx if it has no constant terms. + The constant terms are added and stored via a second arg. */ +extern rtx eliminate_constant_term PROTO((rtx, rtx *)); + +/* Convert arg to a valid memory address for specified machine mode, + by emitting insns to perform arithmetic if nec. */ +extern rtx memory_address PROTO((enum machine_mode, rtx)); + +/* Like `memory_address' but pretent `flag_force_addr' is 0. */ +extern rtx memory_address_noforce PROTO((enum machine_mode, rtx)); + +/* Return a memory reference like MEMREF, but with its mode changed + to MODE and its address changed to ADDR. + (VOIDmode means don't change the mode. + NULL for ADDR means don't change the address.) */ +extern rtx change_address PROTO((rtx, enum machine_mode, rtx)); + +/* Return a memory reference like MEMREF, but which is known to have a + valid address. */ + +extern rtx validize_mem PROTO((rtx)); + +/* Assemble the static constant template for function entry trampolines. */ +extern rtx assemble_trampoline_template PROTO((void)); + +/* Return 1 if two rtx's are equivalent in structure and elements. */ +extern int rtx_equal_p PROTO((rtx, rtx)); + +/* Given rtx, return new rtx whose address won't be affected by + any side effects. It has been copied to a new temporary reg. */ +extern rtx stabilize PROTO((rtx)); + +/* Given an rtx, copy all regs it refers to into new temps + and return a modified copy that refers to the new temps. */ +extern rtx copy_all_regs PROTO((rtx)); + +/* Copy given rtx to a new temp reg and return that. */ +extern rtx copy_to_reg PROTO((rtx)); + +/* Like copy_to_reg but always make the reg Pmode. */ +extern rtx copy_addr_to_reg PROTO((rtx)); + +/* Like copy_to_reg but always make the reg the specified mode MODE. */ +extern rtx copy_to_mode_reg PROTO((enum machine_mode, rtx)); + +/* Copy given rtx to given temp reg and return that. */ +extern rtx copy_to_suggested_reg PROTO((rtx, rtx, enum machine_mode)); + +/* Copy a value to a register if it isn't already a register. + Args are mode (in case value is a constant) and the value. */ +extern rtx force_reg PROTO((enum machine_mode, rtx)); + +/* Return given rtx, copied into a new temp reg if it was in memory. */ +extern rtx force_not_mem PROTO((rtx)); + +/* Remove some bytes from the stack. An rtx says how many. */ +extern void adjust_stack PROTO((rtx)); + +/* Add some bytes to the stack. An rtx says how many. */ +extern void anti_adjust_stack PROTO((rtx)); + +/* This enum is used for the following two functions. */ +enum save_level {SAVE_BLOCK, SAVE_FUNCTION, SAVE_NONLOCAL}; + +/* Save the stack pointer at the specified level. */ +extern void emit_stack_save PROTO((enum save_level, rtx *, rtx)); + +/* Restore the stack pointer from a save area of the specified level. */ +extern void emit_stack_restore PROTO((enum save_level, rtx, rtx)); + +/* Allocate some space on the stack dynamically and return its address. An rtx + says how many bytes. */ +extern rtx allocate_dynamic_stack_space PROTO((rtx, rtx, int)); + +/* Emit code to copy function value to a new temp reg and return that reg. */ +extern rtx function_value (); + +/* Return an rtx that refers to the value returned by a library call + in its original home. This becomes invalid if any more code is emitted. */ +extern rtx hard_libcall_value PROTO((enum machine_mode)); + +/* Given an rtx, return an rtx for a value rounded up to a multiple + of STACK_BOUNDARY / BITS_PER_UNIT. */ +extern rtx round_push PROTO((rtx)); + +extern void emit_block_move PROTO((rtx, rtx, rtx, int)); + +extern rtx store_bit_field PROTO((rtx, int, int, enum machine_mode, rtx, int, int)); +extern rtx extract_bit_field PROTO((rtx, int, int, int, rtx, enum machine_mode, enum machine_mode, int, int)); +extern rtx expand_mult PROTO((enum machine_mode, rtx, rtx, rtx, int)); +extern rtx expand_mult_add PROTO((rtx, rtx, rtx, rtx,enum machine_mode, int)); + +extern rtx assemble_static_space PROTO((int)); + +/* Hook called by expand_expr for language-specific tree codes. + It is up to the language front end to install a hook + if it has any such codes that expand_expr needs to know about. */ +extern rtx (*lang_expand_expr) (); diff --git a/gnu/usr.bin/cc/lib/final.c b/gnu/usr.bin/cc/lib/final.c new file mode 100644 index 000000000000..9773fa8e2870 --- /dev/null +++ b/gnu/usr.bin/cc/lib/final.c @@ -0,0 +1,2740 @@ +/* Convert RTL to assembler code and output it, for GNU compiler. + Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This is the final pass of the compiler. + It looks at the rtl code for a function and outputs assembler code. + + Call `final_start_function' to output the assembler code for function entry, + `final' to output assembler code for some RTL code, + `final_end_function' to output assembler code for function exit. + If a function is compiled in several pieces, each piece is + output separately with `final'. + + Some optimizations are also done at this level. + Move instructions that were made unnecessary by good register allocation + are detected and omitted from the output. (Though most of these + are removed by the last jump pass.) + + Instructions to set the condition codes are omitted when it can be + seen that the condition codes already had the desired values. + + In some cases it is sufficient if the inherited condition codes + have related values, but this may require the following insn + (the one that tests the condition codes) to be modified. + + The code for the function prologue and epilogue are generated + directly as assembler code by the macros FUNCTION_PROLOGUE and + FUNCTION_EPILOGUE. Those instructions never exist as rtl. */ + +#include "config.h" +#include "gvarargs.h" +#include "rtl.h" +#include "regs.h" +#include "insn-config.h" +#include "insn-flags.h" +#include "insn-attr.h" +#include "insn-codes.h" +#include "recog.h" +#include "conditions.h" +#include "flags.h" +#include "real.h" +#include "hard-reg-set.h" +#include "defaults.h" + +#include + +#include "output.h" + +/* Get N_SLINE and N_SOL from stab.h if we can expect the file to exist. */ +#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) +#if defined (USG) || defined (NO_STAB_H) +#include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */ +#else +#include /* On BSD, use the system's stab.h. */ +#endif /* not USG */ +#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ + +#ifdef XCOFF_DEBUGGING_INFO +#include "xcoffout.h" +#endif + +/* .stabd code for line number. */ +#ifndef N_SLINE +#define N_SLINE 0x44 +#endif + +/* .stabs code for included file name. */ +#ifndef N_SOL +#define N_SOL 0x84 +#endif + +#ifndef INT_TYPE_SIZE +#define INT_TYPE_SIZE BITS_PER_WORD +#endif + +/* If we aren't using cc0, CC_STATUS_INIT shouldn't exist. So define a + null default for it to save conditionalization later. */ +#ifndef CC_STATUS_INIT +#define CC_STATUS_INIT +#endif + +/* How to start an assembler comment. */ +#ifndef ASM_COMMENT_START +#define ASM_COMMENT_START ";#" +#endif + +rtx peephole (); +void output_asm_insn (); +rtx alter_subreg (); +static int alter_cond (); +void output_asm_label (); +static void output_operand (); +void output_address (); +void output_addr_const (); +static void output_source_line (); +rtx final_scan_insn (); +void profile_function (); +static void profile_after_prologue (); + +#ifdef HAVE_ATTR_length +static int asm_insn_count (); +#endif + +/* Nonzero means this function is a leaf function, with no function calls. + This variable exists to be examined in FUNCTION_PROLOGUE + and FUNCTION_EPILOGUE. Always zero, unless set by some action. */ +int leaf_function; + +int leaf_function_p (); + +#ifdef LEAF_REGISTERS +int only_leaf_regs_used (); +static void leaf_renumber_regs (); +void leaf_renumber_regs_insn (); +#endif + +/* Last insn processed by final_scan_insn. */ +static rtx debug_insn = 0; + +/* Line number of last NOTE. */ +static int last_linenum; + +/* Number of basic blocks seen so far; + used if profile_block_flag is set. */ +static int count_basic_blocks; + +/* Nonzero while outputting an `asm' with operands. + This means that inconsistencies are the user's fault, so don't abort. + The precise value is the insn being output, to pass to error_for_asm. */ +static rtx this_is_asm_operands; + +/* Number of operands of this insn, for an `asm' with operands. */ +static int insn_noperands; + +/* Compare optimization flag. */ + +static rtx last_ignored_compare = 0; + +/* Flag indicating this insn is the start of a new basic block. */ + +static int new_block = 1; + +/* All the symbol-blocks (levels of scoping) in the compilation + are assigned sequence numbers in order of appearance of the + beginnings of the symbol-blocks. Both final and dbxout do this, + and assume that they will both give the same number to each block. + Final uses these sequence numbers to generate assembler label names + LBBnnn and LBEnnn for the beginning and end of the symbol-block. + Dbxout uses the sequence numbers to generate references to the same labels + from the dbx debugging information. + + Sdb records this level at the beginning of each function, + in order to find the current level when recursing down declarations. + It outputs the block beginning and endings + at the point in the asm file where the blocks would begin and end. */ + +int next_block_index; + +/* Assign a unique number to each insn that is output. + This can be used to generate unique local labels. */ + +static int insn_counter = 0; + +#ifdef HAVE_cc0 +/* This variable contains machine-dependent flags (defined in tm.h) + set and examined by output routines + that describe how to interpret the condition codes properly. */ + +CC_STATUS cc_status; + +/* During output of an insn, this contains a copy of cc_status + from before the insn. */ + +CC_STATUS cc_prev_status; +#endif + +/* Indexed by hardware reg number, is 1 if that register is ever + used in the current function. + + In life_analysis, or in stupid_life_analysis, this is set + up to record the hard regs used explicitly. Reload adds + in the hard regs used for holding pseudo regs. Final uses + it to generate the code in the function prologue and epilogue + to save and restore registers as needed. */ + +char regs_ever_live[FIRST_PSEUDO_REGISTER]; + +/* Nonzero means current function must be given a frame pointer. + Set in stmt.c if anything is allocated on the stack there. + Set in reload1.c if anything is allocated on the stack there. */ + +int frame_pointer_needed; + +/* Assign unique numbers to labels generated for profiling. */ + +int profile_label_no; + +/* Length so far allocated in PENDING_BLOCKS. */ + +static int max_block_depth; + +/* Stack of sequence numbers of symbol-blocks of which we have seen the + beginning but not yet the end. Sequence numbers are assigned at + the beginning; this stack allows us to find the sequence number + of a block that is ending. */ + +static int *pending_blocks; + +/* Number of elements currently in use in PENDING_BLOCKS. */ + +static int block_depth; + +/* Nonzero if have enabled APP processing of our assembler output. */ + +static int app_on; + +/* If we are outputting an insn sequence, this contains the sequence rtx. + Zero otherwise. */ + +rtx final_sequence; + +/* Indexed by line number, nonzero if there is a note for that line. */ + +static char *line_note_exists; + +/* Initialize data in final at the beginning of a compilation. */ + +void +init_final (filename) + char *filename; +{ + next_block_index = 2; + app_on = 0; + max_block_depth = 20; + pending_blocks = (int *) xmalloc (20 * sizeof *pending_blocks); + final_sequence = 0; +} + +/* Called at end of source file, + to output the block-profiling table for this entire compilation. */ + +void +end_final (filename) + char *filename; +{ + int i; + + if (profile_block_flag) + { + char name[12]; + + data_section (); + + /* Output the main header, of 6 words: + 0: 1 if this file's initialized, else 0. + 1: address of file name. + 2: address of table of counts. + 4: number of counts in the table. + 5: always 0, for compatibility with Sun. + 6: extra word added by GNU: address of address table + which contains addresses of basic blocks, + in parallel with the table of counts. */ + ASM_OUTPUT_ALIGN (asm_out_file, + exact_log2 (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); + + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LPBX", 0); + assemble_integer (const0_rtx, UNITS_PER_WORD, 1); + ASM_GENERATE_INTERNAL_LABEL (name, "LPBX", 1); + assemble_integer (gen_rtx (SYMBOL_REF, Pmode, name), UNITS_PER_WORD, 1); + ASM_GENERATE_INTERNAL_LABEL (name, "LPBX", 2); + assemble_integer (gen_rtx (SYMBOL_REF, Pmode, name), UNITS_PER_WORD, 1); + assemble_integer (GEN_INT (count_basic_blocks), UNITS_PER_WORD, 1); + assemble_integer (const0_rtx, UNITS_PER_WORD, 1); + ASM_GENERATE_INTERNAL_LABEL (name, "LPBX", 3); + assemble_integer (gen_rtx (SYMBOL_REF, Pmode, name), UNITS_PER_WORD, 1); + + /* Output the file name. */ + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LPBX", 1); + { + int len = strlen (filename); + char *data_file = (char *) alloca (len + 3); + strcpy (data_file, filename); + strip_off_ending (data_file, len); + strcat (data_file, ".d"); + assemble_string (data_file, strlen (data_file) + 1); + } + + /* Realign data section. */ + ASM_OUTPUT_ALIGN (asm_out_file, + exact_log2 (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); + + /* Make space for the table of counts. */ + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LPBX", 2); + if (count_basic_blocks != 0) + assemble_zeros (INT_TYPE_SIZE / BITS_PER_UNIT * count_basic_blocks); + + /* Output the table of addresses. */ + readonly_data_section (); + /* Realign in new section */ + ASM_OUTPUT_ALIGN (asm_out_file, + floor_log2 (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LPBX", 3); + for (i = 0; i < count_basic_blocks; i++) + { + char name[12]; + ASM_GENERATE_INTERNAL_LABEL (name, "LPB", i); + assemble_integer (gen_rtx (SYMBOL_REF, Pmode, name), + UNITS_PER_WORD, 1); + } + + /* End with the address of the table of addresses, + so we can find it easily, as the last word in the file's text. */ + ASM_GENERATE_INTERNAL_LABEL (name, "LPBX", 3); + assemble_integer (gen_rtx (SYMBOL_REF, Pmode, name), UNITS_PER_WORD, 1); + } +} + +/* Enable APP processing of subsequent output. + Used before the output from an `asm' statement. */ + +void +app_enable () +{ + if (! app_on) + { + fprintf (asm_out_file, ASM_APP_ON); + app_on = 1; + } +} + +/* Enable APP processing of subsequent output. + Called from varasm.c before most kinds of output. */ + +void +app_disable () +{ + if (app_on) + { + fprintf (asm_out_file, ASM_APP_OFF); + app_on = 0; + } +} + +/* Return the number of slots filled in the current + delayed branch sequence (we don't count the insn needing the + delay slot). Zero if not in a delayed branch sequence. */ + +#ifdef DELAY_SLOTS +int +dbr_sequence_length () +{ + if (final_sequence != 0) + return XVECLEN (final_sequence, 0) - 1; + else + return 0; +} +#endif + +/* The next two pages contain routines used to compute the length of an insn + and to shorten branches. */ + +/* Arrays for insn lengths, and addresses. The latter is referenced by + `insn_current_length'. */ + +static short *insn_lengths; +int *insn_addresses; + +/* Address of insn being processed. Used by `insn_current_length'. */ +int insn_current_address; + +/* Indicate the branch shortening hasn't yet been done. */ + +void +init_insn_lengths () +{ + insn_lengths = 0; +} + +/* Obtain the current length of an insn. If branch shortening has been done, + get its actual length. Otherwise, get its maximum length. */ + +int +get_attr_length (insn) + rtx insn; +{ +#ifdef HAVE_ATTR_length + rtx body; + int i; + int length = 0; + + if (insn_lengths) + return insn_lengths[INSN_UID (insn)]; + else + switch (GET_CODE (insn)) + { + case NOTE: + case BARRIER: + case CODE_LABEL: + return 0; + + case CALL_INSN: + length = insn_default_length (insn); + break; + + case JUMP_INSN: + body = PATTERN (insn); + if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) + { + /* This only takes room if jump tables go into the text section. */ +#if !defined(READONLY_DATA_SECTION) || defined(JUMP_TABLES_IN_TEXT_SECTION) + length = (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC) + * GET_MODE_SIZE (GET_MODE (body))); + + /* Be pessimistic and assume worst-case alignment. */ + length += (GET_MODE_SIZE (GET_MODE (body)) - 1); +#else + return 0; +#endif + } + else + length = insn_default_length (insn); + break; + + case INSN: + body = PATTERN (insn); + if (GET_CODE (body) == USE || GET_CODE (body) == CLOBBER) + return 0; + + else if (GET_CODE (body) == ASM_INPUT || asm_noperands (body) >= 0) + length = asm_insn_count (insn) * insn_default_length (insn); + else if (GET_CODE (body) == SEQUENCE) + for (i = 0; i < XVECLEN (body, 0); i++) + length += get_attr_length (XVECEXP (body, 0, i)); + else + length = insn_default_length (insn); + } + +#ifdef ADJUST_INSN_LENGTH + ADJUST_INSN_LENGTH (insn, length); +#endif + return length; +#else /* not HAVE_ATTR_length */ + return 0; +#endif /* not HAVE_ATTR_length */ +} + +/* Make a pass over all insns and compute their actual lengths by shortening + any branches of variable length if possible. */ + +/* Give a default value for the lowest address in a function. */ + +#ifndef FIRST_INSN_ADDRESS +#define FIRST_INSN_ADDRESS 0 +#endif + +void +shorten_branches (first) + rtx first; +{ +#ifdef HAVE_ATTR_length + rtx insn; + int something_changed = 1; + int max_uid = 0; + char *varying_length; + rtx body; + int uid; + + /* Compute maximum UID and allocate arrays. */ + for (insn = first; insn; insn = NEXT_INSN (insn)) + if (INSN_UID (insn) > max_uid) + max_uid = INSN_UID (insn); + + max_uid++; + insn_lengths = (short *) oballoc (max_uid * sizeof (short)); + insn_addresses = (int *) oballoc (max_uid * sizeof (int)); + varying_length = (char *) oballoc (max_uid * sizeof (char)); + + /* Compute initial lengths, addresses, and varying flags for each insn. */ + for (insn_current_address = FIRST_INSN_ADDRESS, insn = first; + insn != 0; + insn_current_address += insn_lengths[uid], insn = NEXT_INSN (insn)) + { + uid = INSN_UID (insn); + insn_addresses[uid] = insn_current_address; + insn_lengths[uid] = 0; + varying_length[uid] = 0; + + if (GET_CODE (insn) == NOTE || GET_CODE (insn) == BARRIER + || GET_CODE (insn) == CODE_LABEL) + continue; + + body = PATTERN (insn); + if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) + { + /* This only takes room if read-only data goes into the text + section. */ +#if !defined(READONLY_DATA_SECTION) || defined(JUMP_TABLES_IN_TEXT_SECTION) + int unitsize = GET_MODE_SIZE (GET_MODE (body)); + + insn_lengths[uid] = (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC) + * GET_MODE_SIZE (GET_MODE (body))); + + /* Account for possible alignment. */ + insn_lengths[uid] + += unitsize - (insn_current_address & (unitsize - 1)); +#else + ; +#endif + } + else if (asm_noperands (body) >= 0) + insn_lengths[uid] = asm_insn_count (body) * insn_default_length (insn); + else if (GET_CODE (body) == SEQUENCE) + { + int i; + int const_delay_slots; +#ifdef DELAY_SLOTS + const_delay_slots = const_num_delay_slots (XVECEXP (body, 0, 0)); +#else + const_delay_slots = 0; +#endif + /* Inside a delay slot sequence, we do not do any branch shortening + if the shortening could change the number of delay slots + of the branch. */ + for (i = 0; i < XVECLEN (body, 0); i++) + { + rtx inner_insn = XVECEXP (body, 0, i); + int inner_uid = INSN_UID (inner_insn); + int inner_length; + + if (asm_noperands (PATTERN (XVECEXP (body, 0, i))) >= 0) + inner_length = (asm_insn_count (PATTERN (inner_insn)) + * insn_default_length (inner_insn)); + else + inner_length = insn_default_length (inner_insn); + + insn_lengths[inner_uid] = inner_length; + if (const_delay_slots) + { + if ((varying_length[inner_uid] + = insn_variable_length_p (inner_insn)) != 0) + varying_length[uid] = 1; + insn_addresses[inner_uid] = (insn_current_address + + insn_lengths[uid]); + } + else + varying_length[inner_uid] = 0; + insn_lengths[uid] += inner_length; + } + } + else if (GET_CODE (body) != USE && GET_CODE (body) != CLOBBER) + { + insn_lengths[uid] = insn_default_length (insn); + varying_length[uid] = insn_variable_length_p (insn); + } + + /* If needed, do any adjustment. */ +#ifdef ADJUST_INSN_LENGTH + ADJUST_INSN_LENGTH (insn, insn_lengths[uid]); +#endif + } + + /* Now loop over all the insns finding varying length insns. For each, + get the current insn length. If it has changed, reflect the change. + When nothing changes for a full pass, we are done. */ + + while (something_changed) + { + something_changed = 0; + for (insn_current_address = FIRST_INSN_ADDRESS, insn = first; + insn != 0; + insn = NEXT_INSN (insn)) + { + int new_length; + int tmp_length; + + uid = INSN_UID (insn); + insn_addresses[uid] = insn_current_address; + if (! varying_length[uid]) + { + insn_current_address += insn_lengths[uid]; + continue; + } + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) + { + int i; + + body = PATTERN (insn); + new_length = 0; + for (i = 0; i < XVECLEN (body, 0); i++) + { + rtx inner_insn = XVECEXP (body, 0, i); + int inner_uid = INSN_UID (inner_insn); + int inner_length; + + insn_addresses[inner_uid] = insn_current_address; + + /* insn_current_length returns 0 for insns with a + non-varying length. */ + if (! varying_length[inner_uid]) + inner_length = insn_lengths[inner_uid]; + else + inner_length = insn_current_length (inner_insn); + + if (inner_length != insn_lengths[inner_uid]) + { + insn_lengths[inner_uid] = inner_length; + something_changed = 1; + } + insn_current_address += insn_lengths[inner_uid]; + new_length += inner_length; + } + } + else + { + new_length = insn_current_length (insn); + insn_current_address += new_length; + } + +#ifdef SHORTEN_WITH_ADJUST_INSN_LENGTH +#ifdef ADJUST_INSN_LENGTH + /* If needed, do any adjustment. */ + tmp_length = new_length; + ADJUST_INSN_LENGTH (insn, new_length); + insn_current_address += (new_length - tmp_length); +#endif +#endif + + if (new_length != insn_lengths[uid]) + { + insn_lengths[uid] = new_length; + something_changed = 1; + } + } + } +#endif /* HAVE_ATTR_length */ +} + +#ifdef HAVE_ATTR_length +/* Given the body of an INSN known to be generated by an ASM statement, return + the number of machine instructions likely to be generated for this insn. + This is used to compute its length. */ + +static int +asm_insn_count (body) + rtx body; +{ + char *template; + int count = 1; + + for (template = decode_asm_operands (body, NULL_PTR, NULL_PTR, + NULL_PTR, NULL_PTR); + *template; template++) + if (*template == ';' || *template == '\n') + count++; + + return count; +} +#endif + +/* Output assembler code for the start of a function, + and initialize some of the variables in this file + for the new function. The label for the function and associated + assembler pseudo-ops have already been output in `assemble_start_function'. + + FIRST is the first insn of the rtl for the function being compiled. + FILE is the file to write assembler code to. + OPTIMIZE is nonzero if we should eliminate redundant + test and compare insns. */ + +void +final_start_function (first, file, optimize) + rtx first; + FILE *file; + int optimize; +{ + block_depth = 0; + + this_is_asm_operands = 0; + +#ifdef NON_SAVING_SETJMP + /* A function that calls setjmp should save and restore all the + call-saved registers on a system where longjmp clobbers them. */ + if (NON_SAVING_SETJMP && current_function_calls_setjmp) + { + int i; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (!call_used_regs[i] && !call_fixed_regs[i]) + regs_ever_live[i] = 1; + } +#endif + + /* Initial line number is supposed to be output + before the function's prologue and label + so that the function's address will not appear to be + in the last statement of the preceding function. */ + if (NOTE_LINE_NUMBER (first) != NOTE_INSN_DELETED) + { + if (write_symbols == SDB_DEBUG) + /* For sdb, let's not, but say we did. + We need to set last_linenum for sdbout_function_begin, + but we can't have an actual line number before the .bf symbol. + (sdb_begin_function_line is not set, + and other compilers don't do it.) */ + last_linenum = NOTE_LINE_NUMBER (first); +#ifdef XCOFF_DEBUGGING_INFO + else if (write_symbols == XCOFF_DEBUG) + { + last_linenum = NOTE_LINE_NUMBER (first); + xcoffout_output_first_source_line (file, last_linenum); + } +#endif + else + output_source_line (file, first); + } + +#ifdef LEAF_REG_REMAP + if (leaf_function) + leaf_renumber_regs (first); +#endif + + /* The Sun386i and perhaps other machines don't work right + if the profiling code comes after the prologue. */ +#ifdef PROFILE_BEFORE_PROLOGUE + if (profile_flag) + profile_function (file); +#endif /* PROFILE_BEFORE_PROLOGUE */ + +#ifdef FUNCTION_PROLOGUE + /* First output the function prologue: code to set up the stack frame. */ + FUNCTION_PROLOGUE (file, get_frame_size ()); +#endif + +#if defined (SDB_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) + if (write_symbols == SDB_DEBUG || write_symbols == XCOFF_DEBUG) + next_block_index = 1; +#endif + + /* If the machine represents the prologue as RTL, the profiling code must + be emitted when NOTE_INSN_PROLOGUE_END is scanned. */ +#ifdef HAVE_prologue + if (! HAVE_prologue) +#endif + profile_after_prologue (file); + + profile_label_no++; +} + +static void +profile_after_prologue (file) + FILE *file; +{ +#ifdef FUNCTION_BLOCK_PROFILER + if (profile_block_flag) + { + FUNCTION_BLOCK_PROFILER (file, profile_label_no); + } +#endif /* FUNCTION_BLOCK_PROFILER */ + +#ifndef PROFILE_BEFORE_PROLOGUE + if (profile_flag) + profile_function (file); +#endif /* not PROFILE_BEFORE_PROLOGUE */ +} + +void +profile_function (file) + FILE *file; +{ + int align = MIN (BIGGEST_ALIGNMENT, INT_TYPE_SIZE); + int sval = current_function_returns_struct; + int cxt = current_function_needs_context; + + data_section (); + ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT)); + ASM_OUTPUT_INTERNAL_LABEL (file, "LP", profile_label_no); + assemble_integer (const0_rtx, UNITS_PER_WORD, 1); + + text_section (); + +#ifdef STRUCT_VALUE_INCOMING_REGNUM + if (sval) + ASM_OUTPUT_REG_PUSH (file, STRUCT_VALUE_INCOMING_REGNUM); +#else +#ifdef STRUCT_VALUE_REGNUM + if (sval) + ASM_OUTPUT_REG_PUSH (file, STRUCT_VALUE_REGNUM); +#endif +#endif + +#if 0 +#ifdef STATIC_CHAIN_INCOMING_REGNUM + if (cxt) + ASM_OUTPUT_REG_PUSH (file, STATIC_CHAIN_INCOMING_REGNUM); +#else +#ifdef STATIC_CHAIN_REGNUM + if (cxt) + ASM_OUTPUT_REG_PUSH (file, STATIC_CHAIN_REGNUM); +#endif +#endif +#endif /* 0 */ + + FUNCTION_PROFILER (file, profile_label_no); + +#if 0 +#ifdef STATIC_CHAIN_INCOMING_REGNUM + if (cxt) + ASM_OUTPUT_REG_POP (file, STATIC_CHAIN_INCOMING_REGNUM); +#else +#ifdef STATIC_CHAIN_REGNUM + if (cxt) + ASM_OUTPUT_REG_POP (file, STATIC_CHAIN_REGNUM); +#endif +#endif +#endif /* 0 */ + +#ifdef STRUCT_VALUE_INCOMING_REGNUM + if (sval) + ASM_OUTPUT_REG_POP (file, STRUCT_VALUE_INCOMING_REGNUM); +#else +#ifdef STRUCT_VALUE_REGNUM + if (sval) + ASM_OUTPUT_REG_POP (file, STRUCT_VALUE_REGNUM); +#endif +#endif +} + +/* Output assembler code for the end of a function. + For clarity, args are same as those of `final_start_function' + even though not all of them are needed. */ + +void +final_end_function (first, file, optimize) + rtx first; + FILE *file; + int optimize; +{ + if (app_on) + { + fprintf (file, ASM_APP_OFF); + app_on = 0; + } + +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG) + sdbout_end_function (last_linenum); +#endif + +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG) + dwarfout_end_function (); +#endif + +#ifdef XCOFF_DEBUGGING_INFO + if (write_symbols == XCOFF_DEBUG) + xcoffout_end_function (file, last_linenum); +#endif + +#ifdef FUNCTION_EPILOGUE + /* Finally, output the function epilogue: + code to restore the stack frame and return to the caller. */ + FUNCTION_EPILOGUE (file, get_frame_size ()); +#endif + +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG) + sdbout_end_epilogue (); +#endif + +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG) + dwarfout_end_epilogue (); +#endif + +#ifdef XCOFF_DEBUGGING_INFO + if (write_symbols == XCOFF_DEBUG) + xcoffout_end_epilogue (file); +#endif + + /* If FUNCTION_EPILOGUE is not defined, then the function body + itself contains return instructions wherever needed. */ +} + +/* Output assembler code for some insns: all or part of a function. + For description of args, see `final_start_function', above. + + PRESCAN is 1 if we are not really outputting, + just scanning as if we were outputting. + Prescanning deletes and rearranges insns just like ordinary output. + PRESCAN is -2 if we are outputting after having prescanned. + In this case, don't try to delete or rearrange insns + because that has already been done. + Prescanning is done only on certain machines. */ + +void +final (first, file, optimize, prescan) + rtx first; + FILE *file; + int optimize; + int prescan; +{ + register rtx insn; + int max_line = 0; + + last_ignored_compare = 0; + new_block = 1; + + /* Make a map indicating which line numbers appear in this function. + When producing SDB debugging info, delete troublesome line number + notes from inlined functions in other files as well as duplicate + line number notes. */ +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG) + { + rtx last = 0; + for (insn = first; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) + { + if ((RTX_INTEGRATED_P (insn) + && strcmp (NOTE_SOURCE_FILE (insn), main_input_filename) != 0) + || (last != 0 + && NOTE_LINE_NUMBER (insn) == NOTE_LINE_NUMBER (last) + && NOTE_SOURCE_FILE (insn) == NOTE_SOURCE_FILE (last))) + { + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + continue; + } + last = insn; + if (NOTE_LINE_NUMBER (insn) > max_line) + max_line = NOTE_LINE_NUMBER (insn); + } + } + else +#endif + { + for (insn = first; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > max_line) + max_line = NOTE_LINE_NUMBER (insn); + } + + line_note_exists = (char *) oballoc (max_line + 1); + bzero (line_note_exists, max_line + 1); + + for (insn = first; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) + line_note_exists[NOTE_LINE_NUMBER (insn)] = 1; + + init_recog (); + + CC_STATUS_INIT; + + /* Output the insns. */ + for (insn = NEXT_INSN (first); insn;) + insn = final_scan_insn (insn, file, optimize, prescan, 0); + + /* Do basic-block profiling here + if the last insn was a conditional branch. */ + if (profile_block_flag && new_block) + { + new_block = 0; + /* Enable the table of basic-block use counts + to point at the code it applies to. */ + ASM_OUTPUT_INTERNAL_LABEL (file, "LPB", count_basic_blocks); + /* Before first insn of this basic block, increment the + count of times it was entered. */ +#ifdef BLOCK_PROFILER + BLOCK_PROFILER (file, count_basic_blocks); + CC_STATUS_INIT; +#endif + count_basic_blocks++; + } +} + +/* The final scan for one insn, INSN. + Args are same as in `final', except that INSN + is the insn being scanned. + Value returned is the next insn to be scanned. + + NOPEEPHOLES is the flag to disallow peephole processing (currently + used for within delayed branch sequence output). */ + +rtx +final_scan_insn (insn, file, optimize, prescan, nopeepholes) + rtx insn; + FILE *file; + int optimize; + int prescan; + int nopeepholes; +{ + register int i; + insn_counter++; + + /* Ignore deleted insns. These can occur when we split insns (due to a + template of "#") while not optimizing. */ + if (INSN_DELETED_P (insn)) + return NEXT_INSN (insn); + + switch (GET_CODE (insn)) + { + case NOTE: + if (prescan > 0) + break; + + /* Align the beginning of a loop, for higher speed + on certain machines. */ + + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG && optimize > 0) + { +#ifdef ASM_OUTPUT_LOOP_ALIGN + rtx next = next_nonnote_insn (insn); + if (next && GET_CODE (next) == CODE_LABEL) + { + ASM_OUTPUT_LOOP_ALIGN (asm_out_file); + } +#endif + break; + } + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) + break; + + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_PROLOGUE_END) + { +#ifdef FUNCTION_END_PROLOGUE + FUNCTION_END_PROLOGUE (file); +#endif + profile_after_prologue (file); + break; + } + +#ifdef FUNCTION_BEGIN_EPILOGUE + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_EPILOGUE_BEG) + { + FUNCTION_BEGIN_EPILOGUE (file); + break; + } +#endif + + if (write_symbols == NO_DEBUG) + break; + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_FUNCTION_BEG) + { +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG) + sdbout_begin_function (last_linenum); +#endif +#ifdef XCOFF_DEBUGGING_INFO + if (write_symbols == XCOFF_DEBUG) + xcoffout_begin_function (file, last_linenum); +#endif +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG) + dwarfout_begin_function (); +#endif + break; + } + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) + break; /* An insn that was "deleted" */ + if (app_on) + { + fprintf (file, ASM_APP_OFF); + app_on = 0; + } + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG + && (debug_info_level == DINFO_LEVEL_NORMAL + || debug_info_level == DINFO_LEVEL_VERBOSE +#ifdef DWARF_DEBUGGING_INFO + || write_symbols == DWARF_DEBUG +#endif + ) + ) + { + /* Beginning of a symbol-block. Assign it a sequence number + and push the number onto the stack PENDING_BLOCKS. */ + + if (block_depth == max_block_depth) + { + /* PENDING_BLOCKS is full; make it longer. */ + max_block_depth *= 2; + pending_blocks + = (int *) xrealloc (pending_blocks, + max_block_depth * sizeof (int)); + } + pending_blocks[block_depth++] = next_block_index; + + /* Output debugging info about the symbol-block beginning. */ + +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG) + sdbout_begin_block (file, last_linenum, next_block_index); +#endif +#ifdef XCOFF_DEBUGGING_INFO + if (write_symbols == XCOFF_DEBUG) + xcoffout_begin_block (file, last_linenum, next_block_index); +#endif +#ifdef DBX_DEBUGGING_INFO + if (write_symbols == DBX_DEBUG) + ASM_OUTPUT_INTERNAL_LABEL (file, "LBB", next_block_index); +#endif +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG && block_depth > 1) + dwarfout_begin_block (next_block_index); +#endif + + next_block_index++; + } + else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END + && (debug_info_level == DINFO_LEVEL_NORMAL + || debug_info_level == DINFO_LEVEL_VERBOSE +#ifdef DWARF_DEBUGGING_INFO + || write_symbols == DWARF_DEBUG +#endif + ) + ) + { + /* End of a symbol-block. Pop its sequence number off + PENDING_BLOCKS and output debugging info based on that. */ + + --block_depth; + +#ifdef XCOFF_DEBUGGING_INFO + if (write_symbols == XCOFF_DEBUG && block_depth >= 0) + xcoffout_end_block (file, last_linenum, pending_blocks[block_depth]); +#endif +#ifdef DBX_DEBUGGING_INFO + if (write_symbols == DBX_DEBUG && block_depth >= 0) + ASM_OUTPUT_INTERNAL_LABEL (file, "LBE", + pending_blocks[block_depth]); +#endif +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG && block_depth >= 0) + sdbout_end_block (file, last_linenum); +#endif +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG && block_depth >= 1) + dwarfout_end_block (pending_blocks[block_depth]); +#endif + } + else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL + && (debug_info_level == DINFO_LEVEL_NORMAL + || debug_info_level == DINFO_LEVEL_VERBOSE)) + { +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG) + dwarfout_label (insn); +#endif + } + else if (NOTE_LINE_NUMBER (insn) > 0) + /* This note is a line-number. */ + { + register rtx note; + +#if 0 /* This is what we used to do. */ + output_source_line (file, insn); +#endif + int note_after = 0; + + /* If there is anything real after this note, + output it. If another line note follows, omit this one. */ + for (note = NEXT_INSN (insn); note; note = NEXT_INSN (note)) + { + if (GET_CODE (note) != NOTE && GET_CODE (note) != CODE_LABEL) + break; + /* These types of notes can be significant + so make sure the preceding line number stays. */ + else if (GET_CODE (note) == NOTE + && (NOTE_LINE_NUMBER (note) == NOTE_INSN_BLOCK_BEG + || NOTE_LINE_NUMBER (note) == NOTE_INSN_BLOCK_END + || NOTE_LINE_NUMBER (note) == NOTE_INSN_FUNCTION_BEG)) + break; + else if (GET_CODE (note) == NOTE && NOTE_LINE_NUMBER (note) > 0) + { + /* Another line note follows; we can delete this note + if no intervening line numbers have notes elsewhere. */ + int num; + for (num = NOTE_LINE_NUMBER (insn) + 1; + num < NOTE_LINE_NUMBER (note); + num++) + if (line_note_exists[num]) + break; + + if (num >= NOTE_LINE_NUMBER (note)) + note_after = 1; + break; + } + } + + /* Output this line note + if it is the first or the last line note in a row. */ + if (!note_after) + output_source_line (file, insn); + } + break; + + case BARRIER: +#ifdef ASM_OUTPUT_ALIGN_CODE + /* Don't litter the assembler output with needless alignments. A + BARRIER will be placed at the end of every function if HAVE_epilogue + is true. */ + if (NEXT_INSN (insn)) + ASM_OUTPUT_ALIGN_CODE (file); +#endif + break; + + case CODE_LABEL: + CC_STATUS_INIT; + if (prescan > 0) + break; + new_block = 1; +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG && LABEL_NAME (insn)) + sdbout_label (insn); +#endif +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG && LABEL_NAME (insn)) + dwarfout_label (insn); +#endif + if (app_on) + { + fprintf (file, ASM_APP_OFF); + app_on = 0; + } + if (NEXT_INSN (insn) != 0 + && GET_CODE (NEXT_INSN (insn)) == JUMP_INSN) + { + rtx nextbody = PATTERN (NEXT_INSN (insn)); + + /* If this label is followed by a jump-table, + make sure we put the label in the read-only section. Also + possibly write the label and jump table together. */ + + if (GET_CODE (nextbody) == ADDR_VEC + || GET_CODE (nextbody) == ADDR_DIFF_VEC) + { +#ifndef JUMP_TABLES_IN_TEXT_SECTION + readonly_data_section (); +#ifdef READONLY_DATA_SECTION + ASM_OUTPUT_ALIGN (file, + exact_log2 (BIGGEST_ALIGNMENT + / BITS_PER_UNIT)); +#endif /* READONLY_DATA_SECTION */ +#else /* JUMP_TABLES_IN_TEXT_SECTION */ + text_section (); +#endif /* JUMP_TABLES_IN_TEXT_SECTION */ +#ifdef ASM_OUTPUT_CASE_LABEL + ASM_OUTPUT_CASE_LABEL (file, "L", CODE_LABEL_NUMBER (insn), + NEXT_INSN (insn)); +#else + ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (insn)); +#endif + break; + } + } + + ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (insn)); + break; + + default: + { + register rtx body = PATTERN (insn); + int insn_code_number; + char *template; + rtx note; + + /* An INSN, JUMP_INSN or CALL_INSN. + First check for special kinds that recog doesn't recognize. */ + + if (GET_CODE (body) == USE /* These are just declarations */ + || GET_CODE (body) == CLOBBER) + break; + +#ifdef HAVE_cc0 + /* If there is a REG_CC_SETTER note on this insn, it means that + the setting of the condition code was done in the delay slot + of the insn that branched here. So recover the cc status + from the insn that set it. */ + + note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); + if (note) + { + NOTICE_UPDATE_CC (PATTERN (XEXP (note, 0)), XEXP (note, 0)); + cc_prev_status = cc_status; + } +#endif + + /* Detect insns that are really jump-tables + and output them as such. */ + + if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) + { + register int vlen, idx; + + if (prescan > 0) + break; + + if (app_on) + { + fprintf (file, ASM_APP_OFF); + app_on = 0; + } + + vlen = XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC); + for (idx = 0; idx < vlen; idx++) + { + if (GET_CODE (body) == ADDR_VEC) + { +#ifdef ASM_OUTPUT_ADDR_VEC_ELT + ASM_OUTPUT_ADDR_VEC_ELT + (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); +#else + abort (); +#endif + } + else + { +#ifdef ASM_OUTPUT_ADDR_DIFF_ELT + ASM_OUTPUT_ADDR_DIFF_ELT + (file, + CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), + CODE_LABEL_NUMBER (XEXP (XEXP (body, 0), 0))); +#else + abort (); +#endif + } + } +#ifdef ASM_OUTPUT_CASE_END + ASM_OUTPUT_CASE_END (file, + CODE_LABEL_NUMBER (PREV_INSN (insn)), + insn); +#endif + + text_section (); + + break; + } + + /* Do basic-block profiling when we reach a new block. + Done here to avoid jump tables. */ + if (profile_block_flag && new_block) + { + new_block = 0; + /* Enable the table of basic-block use counts + to point at the code it applies to. */ + ASM_OUTPUT_INTERNAL_LABEL (file, "LPB", count_basic_blocks); + /* Before first insn of this basic block, increment the + count of times it was entered. */ +#ifdef BLOCK_PROFILER + BLOCK_PROFILER (file, count_basic_blocks); + CC_STATUS_INIT; +#endif + count_basic_blocks++; + } + + if (GET_CODE (body) == ASM_INPUT) + { + /* There's no telling what that did to the condition codes. */ + CC_STATUS_INIT; + if (prescan > 0) + break; + if (! app_on) + { + fprintf (file, ASM_APP_ON); + app_on = 1; + } + fprintf (asm_out_file, "\t%s\n", XSTR (body, 0)); + break; + } + + /* Detect `asm' construct with operands. */ + if (asm_noperands (body) >= 0) + { + int noperands = asm_noperands (body); + rtx *ops; + char *string; + + /* There's no telling what that did to the condition codes. */ + CC_STATUS_INIT; + if (prescan > 0) + break; + + /* alloca won't do here, since only return from `final' + would free it. */ + if (noperands > 0) + ops = (rtx *) xmalloc (noperands * sizeof (rtx)); + + if (! app_on) + { + fprintf (file, ASM_APP_ON); + app_on = 1; + } + + /* Get out the operand values. */ + string = decode_asm_operands (body, ops, NULL_PTR, + NULL_PTR, NULL_PTR); + /* Inhibit aborts on what would otherwise be compiler bugs. */ + insn_noperands = noperands; + this_is_asm_operands = insn; + /* Output the insn using them. */ + output_asm_insn (string, ops); + this_is_asm_operands = 0; + if (noperands > 0) + free (ops); + break; + } + + if (prescan <= 0 && app_on) + { + fprintf (file, ASM_APP_OFF); + app_on = 0; + } + + if (GET_CODE (body) == SEQUENCE) + { + /* A delayed-branch sequence */ + register int i; + rtx next; + + if (prescan > 0) + break; + final_sequence = body; + + /* The first insn in this SEQUENCE might be a JUMP_INSN that will + force the restoration of a comparison that was previously + thought unnecessary. If that happens, cancel this sequence + and cause that insn to be restored. */ + + next = final_scan_insn (XVECEXP (body, 0, 0), file, 0, prescan, 1); + if (next != XVECEXP (body, 0, 1)) + { + final_sequence = 0; + return next; + } + + for (i = 1; i < XVECLEN (body, 0); i++) + final_scan_insn (XVECEXP (body, 0, i), file, 0, prescan, 1); +#ifdef DBR_OUTPUT_SEQEND + DBR_OUTPUT_SEQEND (file); +#endif + final_sequence = 0; + + /* If the insn requiring the delay slot was a CALL_INSN, the + insns in the delay slot are actually executed before the + called function. Hence we don't preserve any CC-setting + actions in these insns and the CC must be marked as being + clobbered by the function. */ + if (GET_CODE (XVECEXP (body, 0, 0)) == CALL_INSN) + CC_STATUS_INIT; + + /* Following a conditional branch sequence, we have a new basic + block. */ + if (profile_block_flag) + { + rtx insn = XVECEXP (body, 0, 0); + rtx body = PATTERN (insn); + + if ((GET_CODE (insn) == JUMP_INSN && GET_CODE (body) == SET + && GET_CODE (SET_SRC (body)) != LABEL_REF) + || (GET_CODE (insn) == JUMP_INSN + && GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) != LABEL_REF)) + new_block = 1; + } + break; + } + + /* We have a real machine instruction as rtl. */ + + body = PATTERN (insn); + +#ifdef HAVE_cc0 + /* Check for redundant test and compare instructions + (when the condition codes are already set up as desired). + This is done only when optimizing; if not optimizing, + it should be possible for the user to alter a variable + with the debugger in between statements + and the next statement should reexamine the variable + to compute the condition codes. */ + + if (optimize + && GET_CODE (body) == SET + && GET_CODE (SET_DEST (body)) == CC0 + && insn != last_ignored_compare) + { + if (GET_CODE (SET_SRC (body)) == SUBREG) + SET_SRC (body) = alter_subreg (SET_SRC (body)); + else if (GET_CODE (SET_SRC (body)) == COMPARE) + { + if (GET_CODE (XEXP (SET_SRC (body), 0)) == SUBREG) + XEXP (SET_SRC (body), 0) + = alter_subreg (XEXP (SET_SRC (body), 0)); + if (GET_CODE (XEXP (SET_SRC (body), 1)) == SUBREG) + XEXP (SET_SRC (body), 1) + = alter_subreg (XEXP (SET_SRC (body), 1)); + } + if ((cc_status.value1 != 0 + && rtx_equal_p (SET_SRC (body), cc_status.value1)) + || (cc_status.value2 != 0 + && rtx_equal_p (SET_SRC (body), cc_status.value2))) + { + /* Don't delete insn if it has an addressing side-effect. */ + if (! FIND_REG_INC_NOTE (insn, 0) + /* or if anything in it is volatile. */ + && ! volatile_refs_p (PATTERN (insn))) + { + /* We don't really delete the insn; just ignore it. */ + last_ignored_compare = insn; + break; + } + } + } +#endif + + /* Following a conditional branch, we have a new basic block. + But if we are inside a sequence, the new block starts after the + last insn of the sequence. */ + if (profile_block_flag && final_sequence == 0 + && ((GET_CODE (insn) == JUMP_INSN && GET_CODE (body) == SET + && GET_CODE (SET_SRC (body)) != LABEL_REF) + || (GET_CODE (insn) == JUMP_INSN && GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) != LABEL_REF))) + new_block = 1; + +#ifndef STACK_REGS + /* Don't bother outputting obvious no-ops, even without -O. + This optimization is fast and doesn't interfere with debugging. + Don't do this if the insn is in a delay slot, since this + will cause an improper number of delay insns to be written. */ + if (final_sequence == 0 + && prescan >= 0 + && GET_CODE (insn) == INSN && GET_CODE (body) == SET + && GET_CODE (SET_SRC (body)) == REG + && GET_CODE (SET_DEST (body)) == REG + && REGNO (SET_SRC (body)) == REGNO (SET_DEST (body))) + break; +#endif + +#ifdef HAVE_cc0 + /* If this is a conditional branch, maybe modify it + if the cc's are in a nonstandard state + so that it accomplishes the same thing that it would + do straightforwardly if the cc's were set up normally. */ + + if (cc_status.flags != 0 + && GET_CODE (insn) == JUMP_INSN + && GET_CODE (body) == SET + && SET_DEST (body) == pc_rtx + && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE + /* This is done during prescan; it is not done again + in final scan when prescan has been done. */ + && prescan >= 0) + { + /* This function may alter the contents of its argument + and clear some of the cc_status.flags bits. + It may also return 1 meaning condition now always true + or -1 meaning condition now always false + or 2 meaning condition nontrivial but altered. */ + register int result = alter_cond (XEXP (SET_SRC (body), 0)); + /* If condition now has fixed value, replace the IF_THEN_ELSE + with its then-operand or its else-operand. */ + if (result == 1) + SET_SRC (body) = XEXP (SET_SRC (body), 1); + if (result == -1) + SET_SRC (body) = XEXP (SET_SRC (body), 2); + + /* The jump is now either unconditional or a no-op. + If it has become a no-op, don't try to output it. + (It would not be recognized.) */ + if (SET_SRC (body) == pc_rtx) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + break; + } + else if (GET_CODE (SET_SRC (body)) == RETURN) + /* Replace (set (pc) (return)) with (return). */ + PATTERN (insn) = body = SET_SRC (body); + + /* Rerecognize the instruction if it has changed. */ + if (result != 0) + INSN_CODE (insn) = -1; + } + + /* Make same adjustments to instructions that examine the + condition codes without jumping (if this machine has them). */ + + if (cc_status.flags != 0 + && GET_CODE (body) == SET) + { + switch (GET_CODE (SET_SRC (body))) + { + case GTU: + case GT: + case LTU: + case LT: + case GEU: + case GE: + case LEU: + case LE: + case EQ: + case NE: + { + register int result; + if (XEXP (SET_SRC (body), 0) != cc0_rtx) + break; + result = alter_cond (SET_SRC (body)); + if (result == 1) + validate_change (insn, &SET_SRC (body), const_true_rtx, 0); + else if (result == -1) + validate_change (insn, &SET_SRC (body), const0_rtx, 0); + else if (result == 2) + INSN_CODE (insn) = -1; + } + } + } +#endif + + /* Do machine-specific peephole optimizations if desired. */ + + if (optimize && !flag_no_peephole && !nopeepholes) + { + rtx next = peephole (insn); + /* When peepholing, if there were notes within the peephole, + emit them before the peephole. */ + if (next != 0 && next != NEXT_INSN (insn)) + { + rtx prev = PREV_INSN (insn); + rtx note; + + for (note = NEXT_INSN (insn); note != next; + note = NEXT_INSN (note)) + final_scan_insn (note, file, optimize, prescan, nopeepholes); + + /* In case this is prescan, put the notes + in proper position for later rescan. */ + note = NEXT_INSN (insn); + PREV_INSN (note) = prev; + NEXT_INSN (prev) = note; + NEXT_INSN (PREV_INSN (next)) = insn; + PREV_INSN (insn) = PREV_INSN (next); + NEXT_INSN (insn) = next; + PREV_INSN (next) = insn; + } + + /* PEEPHOLE might have changed this. */ + body = PATTERN (insn); + } + + /* Try to recognize the instruction. + If successful, verify that the operands satisfy the + constraints for the instruction. Crash if they don't, + since `reload' should have changed them so that they do. */ + + insn_code_number = recog_memoized (insn); + insn_extract (insn); + for (i = 0; i < insn_n_operands[insn_code_number]; i++) + { + if (GET_CODE (recog_operand[i]) == SUBREG) + recog_operand[i] = alter_subreg (recog_operand[i]); + } + + for (i = 0; i < insn_n_dups[insn_code_number]; i++) + { + if (GET_CODE (*recog_dup_loc[i]) == SUBREG) + *recog_dup_loc[i] = alter_subreg (*recog_dup_loc[i]); + } + +#ifdef REGISTER_CONSTRAINTS + if (! constrain_operands (insn_code_number, 1)) + fatal_insn_not_found (insn); +#endif + + /* Some target machines need to prescan each insn before + it is output. */ + +#ifdef FINAL_PRESCAN_INSN + FINAL_PRESCAN_INSN (insn, recog_operand, + insn_n_operands[insn_code_number]); +#endif + +#ifdef HAVE_cc0 + cc_prev_status = cc_status; + + /* Update `cc_status' for this instruction. + The instruction's output routine may change it further. + If the output routine for a jump insn needs to depend + on the cc status, it should look at cc_prev_status. */ + + NOTICE_UPDATE_CC (body, insn); +#endif + + debug_insn = insn; + + /* If the proper template needs to be chosen by some C code, + run that code and get the real template. */ + + template = insn_template[insn_code_number]; + if (template == 0) + { + template = (*insn_outfun[insn_code_number]) (recog_operand, insn); + + /* If the C code returns 0, it means that it is a jump insn + which follows a deleted test insn, and that test insn + needs to be reinserted. */ + if (template == 0) + { + if (prev_nonnote_insn (insn) != last_ignored_compare) + abort (); + new_block = 0; + return prev_nonnote_insn (insn); + } + } + + /* If the template is the string "#", it means that this insn must + be split. */ + if (template[0] == '#' && template[1] == '\0') + { + rtx new = try_split (body, insn, 0); + + /* If we didn't split the insn, go away. */ + if (new == insn && PATTERN (new) == body) + abort (); + + new_block = 0; + return new; + } + + if (prescan > 0) + break; + + /* Output assembler code from the template. */ + + output_asm_insn (template, recog_operand); + +#if 0 + /* It's not at all clear why we did this and doing so interferes + with tests we'd like to do to use REG_WAS_0 notes, so let's try + with this out. */ + + /* Mark this insn as having been output. */ + INSN_DELETED_P (insn) = 1; +#endif + + debug_insn = 0; + } + } + return NEXT_INSN (insn); +} + +/* Output debugging info to the assembler file FILE + based on the NOTE-insn INSN, assumed to be a line number. */ + +static void +output_source_line (file, insn) + FILE *file; + rtx insn; +{ + char ltext_label_name[100]; + register char *filename = NOTE_SOURCE_FILE (insn); + + last_linenum = NOTE_LINE_NUMBER (insn); + + if (write_symbols != NO_DEBUG) + { +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG +#if 0 /* People like having line numbers even in wrong file! */ + /* COFF can't handle multiple source files--lose, lose. */ + && !strcmp (filename, main_input_filename) +#endif + /* COFF relative line numbers must be positive. */ + && last_linenum > sdb_begin_function_line) + { +#ifdef ASM_OUTPUT_SOURCE_LINE + ASM_OUTPUT_SOURCE_LINE (file, last_linenum); +#else + fprintf (file, "\t.ln\t%d\n", + ((sdb_begin_function_line > -1) + ? last_linenum - sdb_begin_function_line : 1)); +#endif + } +#endif + +#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) + if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) + dbxout_source_line (file, filename, NOTE_LINE_NUMBER (insn)); +#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ + +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG) + dwarfout_line (filename, NOTE_LINE_NUMBER (insn)); +#endif + } +} + +/* If X is a SUBREG, replace it with a REG or a MEM, + based on the thing it is a subreg of. */ + +rtx +alter_subreg (x) + register rtx x; +{ + register rtx y = SUBREG_REG (x); + if (GET_CODE (y) == SUBREG) + y = alter_subreg (y); + + if (GET_CODE (y) == REG) + { + /* If the containing reg really gets a hard reg, so do we. */ + PUT_CODE (x, REG); + REGNO (x) = REGNO (y) + SUBREG_WORD (x); + } + else if (GET_CODE (y) == MEM) + { + register int offset = SUBREG_WORD (x) * UNITS_PER_WORD; +#if BYTES_BIG_ENDIAN + offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))) + - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (y)))); +#endif + PUT_CODE (x, MEM); + MEM_VOLATILE_P (x) = MEM_VOLATILE_P (y); + XEXP (x, 0) = plus_constant (XEXP (y, 0), offset); + } + + return x; +} + +/* Do alter_subreg on all the SUBREGs contained in X. */ + +static rtx +walk_alter_subreg (x) + rtx x; +{ + switch (GET_CODE (x)) + { + case PLUS: + case MULT: + XEXP (x, 0) = walk_alter_subreg (XEXP (x, 0)); + XEXP (x, 1) = walk_alter_subreg (XEXP (x, 1)); + break; + + case MEM: + XEXP (x, 0) = walk_alter_subreg (XEXP (x, 0)); + break; + + case SUBREG: + return alter_subreg (x); + } + + return x; +} + +#ifdef HAVE_cc0 + +/* Given BODY, the body of a jump instruction, alter the jump condition + as required by the bits that are set in cc_status.flags. + Not all of the bits there can be handled at this level in all cases. + + The value is normally 0. + 1 means that the condition has become always true. + -1 means that the condition has become always false. + 2 means that COND has been altered. */ + +static int +alter_cond (cond) + register rtx cond; +{ + int value = 0; + + if (cc_status.flags & CC_REVERSED) + { + value = 2; + PUT_CODE (cond, swap_condition (GET_CODE (cond))); + } + + if (cc_status.flags & CC_INVERTED) + { + value = 2; + PUT_CODE (cond, reverse_condition (GET_CODE (cond))); + } + + if (cc_status.flags & CC_NOT_POSITIVE) + switch (GET_CODE (cond)) + { + case LE: + case LEU: + case GEU: + /* Jump becomes unconditional. */ + return 1; + + case GT: + case GTU: + case LTU: + /* Jump becomes no-op. */ + return -1; + + case GE: + PUT_CODE (cond, EQ); + value = 2; + break; + + case LT: + PUT_CODE (cond, NE); + value = 2; + break; + } + + if (cc_status.flags & CC_NOT_NEGATIVE) + switch (GET_CODE (cond)) + { + case GE: + case GEU: + /* Jump becomes unconditional. */ + return 1; + + case LT: + case LTU: + /* Jump becomes no-op. */ + return -1; + + case LE: + case LEU: + PUT_CODE (cond, EQ); + value = 2; + break; + + case GT: + case GTU: + PUT_CODE (cond, NE); + value = 2; + break; + } + + if (cc_status.flags & CC_NO_OVERFLOW) + switch (GET_CODE (cond)) + { + case GEU: + /* Jump becomes unconditional. */ + return 1; + + case LEU: + PUT_CODE (cond, EQ); + value = 2; + break; + + case GTU: + PUT_CODE (cond, NE); + value = 2; + break; + + case LTU: + /* Jump becomes no-op. */ + return -1; + } + + if (cc_status.flags & (CC_Z_IN_NOT_N | CC_Z_IN_N)) + switch (GET_CODE (cond)) + { + case LE: + case LEU: + case GE: + case GEU: + case LT: + case LTU: + case GT: + case GTU: + abort (); + + case NE: + PUT_CODE (cond, cc_status.flags & CC_Z_IN_N ? GE : LT); + value = 2; + break; + + case EQ: + PUT_CODE (cond, cc_status.flags & CC_Z_IN_N ? LT : GE); + value = 2; + break; + } + + if (cc_status.flags & CC_NOT_SIGNED) + /* The flags are valid if signed condition operators are converted + to unsigned. */ + switch (GET_CODE (cond)) + { + case LE: + PUT_CODE (cond, LEU); + value = 2; + break; + + case LT: + PUT_CODE (cond, LTU); + value = 2; + break; + + case GT: + PUT_CODE (cond, GTU); + value = 2; + break; + + case GE: + PUT_CODE (cond, GEU); + value = 2; + break; + } + + return value; +} +#endif + +/* Report inconsistency between the assembler template and the operands. + In an `asm', it's the user's fault; otherwise, the compiler's fault. */ + +void +output_operand_lossage (str) + char *str; +{ + if (this_is_asm_operands) + error_for_asm (this_is_asm_operands, "invalid `asm': %s", str); + else + abort (); +} + +/* Output of assembler code from a template, and its subroutines. */ + +/* Output text from TEMPLATE to the assembler output file, + obeying %-directions to substitute operands taken from + the vector OPERANDS. + + %N (for N a digit) means print operand N in usual manner. + %lN means require operand N to be a CODE_LABEL or LABEL_REF + and print the label name with no punctuation. + %cN means require operand N to be a constant + and print the constant expression with no punctuation. + %aN means expect operand N to be a memory address + (not a memory reference!) and print a reference + to that address. + %nN means expect operand N to be a constant + and print a constant expression for minus the value + of the operand, with no other punctuation. */ + +void +output_asm_insn (template, operands) + char *template; + rtx *operands; +{ + register char *p; + register int c; + + /* An insn may return a null string template + in a case where no assembler code is needed. */ + if (*template == 0) + return; + + p = template; + putc ('\t', asm_out_file); + +#ifdef ASM_OUTPUT_OPCODE + ASM_OUTPUT_OPCODE (asm_out_file, p); +#endif + + while (c = *p++) + { +#ifdef ASM_OUTPUT_OPCODE + if (c == '\n') + { + putc (c, asm_out_file); + while ((c = *p) == '\t') + { + putc (c, asm_out_file); + p++; + } + ASM_OUTPUT_OPCODE (asm_out_file, p); + } + else +#endif + if (c != '%') + putc (c, asm_out_file); + else + { + /* %% outputs a single %. */ + if (*p == '%') + { + p++; + putc (c, asm_out_file); + } + /* %= outputs a number which is unique to each insn in the entire + compilation. This is useful for making local labels that are + referred to more than once in a given insn. */ + else if (*p == '=') + { + p++; + fprintf (asm_out_file, "%d", insn_counter); + } + /* % followed by a letter and some digits + outputs an operand in a special way depending on the letter. + Letters `acln' are implemented directly. + Other letters are passed to `output_operand' so that + the PRINT_OPERAND macro can define them. */ + else if ((*p >= 'a' && *p <= 'z') + || (*p >= 'A' && *p <= 'Z')) + { + int letter = *p++; + c = atoi (p); + + if (! (*p >= '0' && *p <= '9')) + output_operand_lossage ("operand number missing after %-letter"); + else if (this_is_asm_operands && c >= (unsigned) insn_noperands) + output_operand_lossage ("operand number out of range"); + else if (letter == 'l') + output_asm_label (operands[c]); + else if (letter == 'a') + output_address (operands[c]); + else if (letter == 'c') + { + if (CONSTANT_ADDRESS_P (operands[c])) + output_addr_const (asm_out_file, operands[c]); + else + output_operand (operands[c], 'c'); + } + else if (letter == 'n') + { + if (GET_CODE (operands[c]) == CONST_INT) + fprintf (asm_out_file, +#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT + "%d", +#else + "%ld", +#endif + - INTVAL (operands[c])); + else + { + putc ('-', asm_out_file); + output_addr_const (asm_out_file, operands[c]); + } + } + else + output_operand (operands[c], letter); + + while ((c = *p) >= '0' && c <= '9') p++; + } + /* % followed by a digit outputs an operand the default way. */ + else if (*p >= '0' && *p <= '9') + { + c = atoi (p); + if (this_is_asm_operands && c >= (unsigned) insn_noperands) + output_operand_lossage ("operand number out of range"); + else + output_operand (operands[c], 0); + while ((c = *p) >= '0' && c <= '9') p++; + } + /* % followed by punctuation: output something for that + punctuation character alone, with no operand. + The PRINT_OPERAND macro decides what is actually done. */ +#ifdef PRINT_OPERAND_PUNCT_VALID_P + else if (PRINT_OPERAND_PUNCT_VALID_P (*p)) + output_operand (NULL_RTX, *p++); +#endif + else + output_operand_lossage ("invalid %%-code"); + } + } + + if (flag_print_asm_name) + { + /* Annotate the assembly with a comment describing the pattern and + alternative used. */ + if (debug_insn) + { + register int num = INSN_CODE (debug_insn); + fprintf (asm_out_file, " %s %d %s", + ASM_COMMENT_START, INSN_UID (debug_insn), insn_name[num]); + if (insn_n_alternatives[num] > 1) + fprintf (asm_out_file, "/%d", which_alternative + 1); + + /* Clear this so only the first assembler insn + of any rtl insn will get the special comment for -dp. */ + debug_insn = 0; + } + } + + putc ('\n', asm_out_file); +} + +/* Output a LABEL_REF, or a bare CODE_LABEL, as an assembler symbol. */ + +void +output_asm_label (x) + rtx x; +{ + char buf[256]; + + if (GET_CODE (x) == LABEL_REF) + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0))); + else if (GET_CODE (x) == CODE_LABEL) + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); + else + output_operand_lossage ("`%l' operand isn't a label"); + + assemble_name (asm_out_file, buf); +} + +/* Print operand X using machine-dependent assembler syntax. + The macro PRINT_OPERAND is defined just to control this function. + CODE is a non-digit that preceded the operand-number in the % spec, + such as 'z' if the spec was `%z3'. CODE is 0 if there was no char + between the % and the digits. + When CODE is a non-letter, X is 0. + + The meanings of the letters are machine-dependent and controlled + by PRINT_OPERAND. */ + +static void +output_operand (x, code) + rtx x; + int code; +{ + if (x && GET_CODE (x) == SUBREG) + x = alter_subreg (x); + + /* If X is a pseudo-register, abort now rather than writing trash to the + assembler file. */ + + if (x && GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER) + abort (); + + PRINT_OPERAND (asm_out_file, x, code); +} + +/* Print a memory reference operand for address X + using machine-dependent assembler syntax. + The macro PRINT_OPERAND_ADDRESS exists just to control this function. */ + +void +output_address (x) + rtx x; +{ + walk_alter_subreg (x); + PRINT_OPERAND_ADDRESS (asm_out_file, x); +} + +/* Print an integer constant expression in assembler syntax. + Addition and subtraction are the only arithmetic + that may appear in these expressions. */ + +void +output_addr_const (file, x) + FILE *file; + rtx x; +{ + char buf[256]; + + restart: + switch (GET_CODE (x)) + { + case PC: + if (flag_pic) + putc ('.', file); + else + abort (); + break; + + case SYMBOL_REF: + assemble_name (file, XSTR (x, 0)); + break; + + case LABEL_REF: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0))); + assemble_name (file, buf); + break; + + case CODE_LABEL: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); + assemble_name (file, buf); + break; + + case CONST_INT: + fprintf (file, +#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT + "%d", +#else + "%ld", +#endif + INTVAL (x)); + break; + + case CONST: + /* This used to output parentheses around the expression, + but that does not work on the 386 (either ATT or BSD assembler). */ + output_addr_const (file, XEXP (x, 0)); + break; + + case CONST_DOUBLE: + if (GET_MODE (x) == VOIDmode) + { + /* We can use %d if the number is one word and positive. */ + if (CONST_DOUBLE_HIGH (x)) + fprintf (file, +#if HOST_BITS_PER_WIDE_INT == 64 +#if HOST_BITS_PER_WIDE_INT != HOST_BITS_PER_INT + "0x%lx%016lx", +#else + "0x%x%016x", +#endif +#else +#if HOST_BITS_PER_WIDE_INT != HOST_BITS_PER_INT + "0x%lx%08lx", +#else + "0x%x%08x", +#endif +#endif + CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x)); + else if (CONST_DOUBLE_LOW (x) < 0) + fprintf (file, +#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT + "0x%x", +#else + "0x%lx", +#endif + CONST_DOUBLE_LOW (x)); + else + fprintf (file, +#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT + "%d", +#else + "%ld", +#endif + CONST_DOUBLE_LOW (x)); + } + else + /* We can't handle floating point constants; + PRINT_OPERAND must handle them. */ + output_operand_lossage ("floating constant misused"); + break; + + case PLUS: + /* Some assemblers need integer constants to appear last (eg masm). */ + if (GET_CODE (XEXP (x, 0)) == CONST_INT) + { + output_addr_const (file, XEXP (x, 1)); + if (INTVAL (XEXP (x, 0)) >= 0) + fprintf (file, "+"); + output_addr_const (file, XEXP (x, 0)); + } + else + { + output_addr_const (file, XEXP (x, 0)); + if (INTVAL (XEXP (x, 1)) >= 0) + fprintf (file, "+"); + output_addr_const (file, XEXP (x, 1)); + } + break; + + case MINUS: + /* Avoid outputting things like x-x or x+5-x, + since some assemblers can't handle that. */ + x = simplify_subtraction (x); + if (GET_CODE (x) != MINUS) + goto restart; + + output_addr_const (file, XEXP (x, 0)); + fprintf (file, "-"); + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) < 0) + { + fprintf (file, ASM_OPEN_PAREN); + output_addr_const (file, XEXP (x, 1)); + fprintf (file, ASM_CLOSE_PAREN); + } + else + output_addr_const (file, XEXP (x, 1)); + break; + + case ZERO_EXTEND: + case SIGN_EXTEND: + output_addr_const (file, XEXP (x, 0)); + break; + + default: + output_operand_lossage ("invalid expression as operand"); + } +} + +/* A poor man's fprintf, with the added features of %I, %R, %L, and %U. + %R prints the value of REGISTER_PREFIX. + %L prints the value of LOCAL_LABEL_PREFIX. + %U prints the value of USER_LABEL_PREFIX. + %I prints the value of IMMEDIATE_PREFIX. + %O runs ASM_OUTPUT_OPCODE to transform what follows in the string. + Also supported are %d, %x, %s, %e, %f, %g and %%. */ + +void +asm_fprintf (va_alist) + va_dcl +{ + va_list argptr; + FILE *file; + char buf[10]; + char *p, *q, c; + + va_start (argptr); + + file = va_arg (argptr, FILE *); + p = va_arg (argptr, char *); + buf[0] = '%'; + + while (c = *p++) + switch (c) + { + case '%': + c = *p++; + q = &buf[1]; + while ((c >= '0' && c <= '9') || c == '.') + { + *q++ = c; + c = *p++; + } + switch (c) + { + case '%': + fprintf (file, "%%"); + break; + + case 'd': case 'i': case 'u': + case 'x': case 'p': case 'X': + case 'o': + *q++ = c; + *q = 0; + fprintf (file, buf, va_arg (argptr, int)); + break; + + case 'e': + case 'f': + case 'g': + *q++ = c; + *q = 0; + fprintf (file, buf, va_arg (argptr, double)); + break; + + case 's': + *q++ = c; + *q = 0; + fprintf (file, buf, va_arg (argptr, char *)); + break; + + case 'O': +#ifdef ASM_OUTPUT_OPCODE + ASM_OUTPUT_OPCODE (asm_out_file, p); +#endif + break; + + case 'R': +#ifdef REGISTER_PREFIX + fprintf (file, "%s", REGISTER_PREFIX); +#endif + break; + + case 'I': +#ifdef IMMEDIATE_PREFIX + fprintf (file, "%s", IMMEDIATE_PREFIX); +#endif + break; + + case 'L': +#ifdef LOCAL_LABEL_PREFIX + fprintf (file, "%s", LOCAL_LABEL_PREFIX); +#endif + break; + + case 'U': +#ifdef USER_LABEL_PREFIX + fprintf (file, "%s", USER_LABEL_PREFIX); +#endif + break; + + default: + abort (); + } + break; + + default: + fputc (c, file); + } +} + +/* Split up a CONST_DOUBLE or integer constant rtx + into two rtx's for single words, + storing in *FIRST the word that comes first in memory in the target + and in *SECOND the other. */ + +void +split_double (value, first, second) + rtx value; + rtx *first, *second; +{ + if (GET_CODE (value) == CONST_INT) + { + /* The rule for using CONST_INT for a wider mode + is that we regard the value as signed. + So sign-extend it. */ + rtx high = (INTVAL (value) < 0 ? constm1_rtx : const0_rtx); +#if WORDS_BIG_ENDIAN + *first = high; + *second = value; +#else + *first = value; + *second = high; +#endif + } + else if (GET_CODE (value) != CONST_DOUBLE) + { +#if WORDS_BIG_ENDIAN + *first = const0_rtx; + *second = value; +#else + *first = value; + *second = const0_rtx; +#endif + } + else if (GET_MODE (value) == VOIDmode + /* This is the old way we did CONST_DOUBLE integers. */ + || GET_MODE_CLASS (GET_MODE (value)) == MODE_INT) + { + /* In an integer, the words are defined as most and least significant. + So order them by the target's convention. */ +#if WORDS_BIG_ENDIAN + *first = GEN_INT (CONST_DOUBLE_HIGH (value)); + *second = GEN_INT (CONST_DOUBLE_LOW (value)); +#else + *first = GEN_INT (CONST_DOUBLE_LOW (value)); + *second = GEN_INT (CONST_DOUBLE_HIGH (value)); +#endif + } + else + { +#ifdef REAL_ARITHMETIC + REAL_VALUE_TYPE r; HOST_WIDE_INT l[2]; + REAL_VALUE_FROM_CONST_DOUBLE (r, value); + REAL_VALUE_TO_TARGET_DOUBLE (r, l); + *first = GEN_INT (l[0]); + *second = GEN_INT (l[1]); +#else + if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT + || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) + && ! flag_pretend_float) + abort (); + +#if defined (HOST_WORDS_BIG_ENDIAN) == WORDS_BIG_ENDIAN + /* Host and target agree => no need to swap. */ + *first = GEN_INT (CONST_DOUBLE_LOW (value)); + *second = GEN_INT (CONST_DOUBLE_HIGH (value)); +#else + *second = GEN_INT (CONST_DOUBLE_LOW (value)); + *first = GEN_INT (CONST_DOUBLE_HIGH (value)); +#endif +#endif /* no REAL_ARITHMETIC */ + } +} + +/* Return nonzero if this function has no function calls. */ + +int +leaf_function_p () +{ + rtx insn; + + if (profile_flag || profile_block_flag) + return 0; + + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == CALL_INSN) + return 0; + if (GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == SEQUENCE + && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN) + return 0; + } + for (insn = current_function_epilogue_delay_list; insn; insn = XEXP (insn, 1)) + { + if (GET_CODE (XEXP (insn, 0)) == CALL_INSN) + return 0; + if (GET_CODE (XEXP (insn, 0)) == INSN + && GET_CODE (PATTERN (XEXP (insn, 0))) == SEQUENCE + && GET_CODE (XVECEXP (PATTERN (XEXP (insn, 0)), 0, 0)) == CALL_INSN) + return 0; + } + + return 1; +} + +/* On some machines, a function with no call insns + can run faster if it doesn't create its own register window. + When output, the leaf function should use only the "output" + registers. Ordinarily, the function would be compiled to use + the "input" registers to find its arguments; it is a candidate + for leaf treatment if it uses only the "input" registers. + Leaf function treatment means renumbering so the function + uses the "output" registers instead. */ + +#ifdef LEAF_REGISTERS + +static char permitted_reg_in_leaf_functions[] = LEAF_REGISTERS; + +/* Return 1 if this function uses only the registers that can be + safely renumbered. */ + +int +only_leaf_regs_used () +{ + int i; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + if ((regs_ever_live[i] || global_regs[i]) + && ! permitted_reg_in_leaf_functions[i]) + return 0; + } + return 1; +} + +/* Scan all instructions and renumber all registers into those + available in leaf functions. */ + +static void +leaf_renumber_regs (first) + rtx first; +{ + rtx insn; + + /* Renumber only the actual patterns. + The reg-notes can contain frame pointer refs, + and renumbering them could crash, and should not be needed. */ + for (insn = first; insn; insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + leaf_renumber_regs_insn (PATTERN (insn)); + for (insn = current_function_epilogue_delay_list; insn; insn = XEXP (insn, 1)) + if (GET_RTX_CLASS (GET_CODE (XEXP (insn, 0))) == 'i') + leaf_renumber_regs_insn (PATTERN (XEXP (insn, 0))); +} + +/* Scan IN_RTX and its subexpressions, and renumber all regs into those + available in leaf functions. */ + +void +leaf_renumber_regs_insn (in_rtx) + register rtx in_rtx; +{ + register int i, j; + register char *format_ptr; + + if (in_rtx == 0) + return; + + /* Renumber all input-registers into output-registers. + renumbered_regs would be 1 for an output-register; + they */ + + if (GET_CODE (in_rtx) == REG) + { + int newreg; + + /* Don't renumber the same reg twice. */ + if (in_rtx->used) + return; + + newreg = REGNO (in_rtx); + /* Don't try to renumber pseudo regs. It is possible for a pseudo reg + to reach here as part of a REG_NOTE. */ + if (newreg >= FIRST_PSEUDO_REGISTER) + { + in_rtx->used = 1; + return; + } + newreg = LEAF_REG_REMAP (newreg); + if (newreg < 0) + abort (); + regs_ever_live[REGNO (in_rtx)] = 0; + regs_ever_live[newreg] = 1; + REGNO (in_rtx) = newreg; + in_rtx->used = 1; + } + + if (GET_RTX_CLASS (GET_CODE (in_rtx)) == 'i') + { + /* Inside a SEQUENCE, we find insns. + Renumber just the patterns of these insns, + just as we do for the top-level insns. */ + leaf_renumber_regs_insn (PATTERN (in_rtx)); + return; + } + + format_ptr = GET_RTX_FORMAT (GET_CODE (in_rtx)); + + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (in_rtx)); i++) + switch (*format_ptr++) + { + case 'e': + leaf_renumber_regs_insn (XEXP (in_rtx, i)); + break; + + case 'E': + if (NULL != XVEC (in_rtx, i)) + { + for (j = 0; j < XVECLEN (in_rtx, i); j++) + leaf_renumber_regs_insn (XVECEXP (in_rtx, i, j)); + } + break; + + case 'S': + case 's': + case '0': + case 'i': + case 'w': + case 'n': + case 'u': + break; + + default: + abort (); + } +} +#endif diff --git a/gnu/usr.bin/cc/lib/flags.h b/gnu/usr.bin/cc/lib/flags.h new file mode 100644 index 000000000000..22bd1f04f819 --- /dev/null +++ b/gnu/usr.bin/cc/lib/flags.h @@ -0,0 +1,344 @@ +/* Compilation switch flag definitions for GNU CC. + Copyright (C) 1987, 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Name of the input .c file being compiled. */ +extern char *main_input_filename; + +enum debug_info_type +{ + NO_DEBUG, /* Write no debug info. */ + DBX_DEBUG, /* Write BSD .stabs for DBX (using dbxout.c). */ + SDB_DEBUG, /* Write COFF for (old) SDB (using sdbout.c). */ + DWARF_DEBUG, /* Write Dwarf debug info (using dwarfout.c). */ + XCOFF_DEBUG /* Write IBM/Xcoff debug info (using dbxout.c). */ +}; + +/* Specify which kind of debugging info to generate. */ +extern enum debug_info_type write_symbols; + +enum debug_info_level +{ + DINFO_LEVEL_NONE, /* Write no debugging info. */ + DINFO_LEVEL_TERSE, /* Write minimal info to support tracebacks only. */ + DINFO_LEVEL_NORMAL, /* Write info for all declarations (and line table). */ + DINFO_LEVEL_VERBOSE /* Write normal info plus #define/#undef info. */ +}; + +/* Specify how much debugging info to generate. */ +extern enum debug_info_level debug_info_level; + +/* Nonzero means use GNU-only extensions in the generated symbolic + debugging information. */ +extern int use_gnu_debug_info_extensions; + +/* Nonzero means do optimizations. -opt. */ + +extern int optimize; + +/* Nonzero means do stupid register allocation. -noreg. + Currently, this is 1 if `optimize' is 0. */ + +extern int obey_regdecls; + +/* Don't print functions as they are compiled and don't print + times taken by the various passes. -quiet. */ + +extern int quiet_flag; + +/* Don't print warning messages. -w. */ + +extern int inhibit_warnings; + +/* Do print extra warnings (such as for uninitialized variables). -W. */ + +extern int extra_warnings; + +/* Nonzero to warn about unused local variables. */ + +extern int warn_unused; + +/* Nonzero means warn if inline function is too large. */ + +extern int warn_inline; + +/* Nonzero to warn about variables used before they are initialized. */ + +extern int warn_uninitialized; + +/* Nonzero means warn about all declarations which shadow others. */ + +extern int warn_shadow; + +/* Warn if a switch on an enum fails to have a case for every enum value. */ + +extern int warn_switch; + +/* Nonzero means warn about function definitions that default the return type + or that use a null return and have a return-type other than void. */ + +extern int warn_return_type; + +/* Nonzero means warn about pointer casts that increase the required + alignment of the target type (and might therefore lead to a crash + due to a misaligned access). */ + +extern int warn_cast_align; + +/* Nonzero means warn that dbx info for template class methods isn't fully + supported yet. */ + +extern int warn_template_debugging; + +/* Nonzero means warn about any identifiers that match in the first N + characters. The value N is in `id_clash_len'. */ + +extern int warn_id_clash; +extern int id_clash_len; + +/* Warn if a function returns an aggregate, + since there are often incompatible calling conventions for doing this. */ + +extern int warn_aggregate_return; + +/* Nonzero if generating code to do profiling. */ + +extern int profile_flag; + +/* Nonzero if generating code to do profiling on the basis of basic blocks. */ + +extern int profile_block_flag; + +/* Nonzero for -pedantic switch: warn about anything + that standard C forbids. */ + +extern int pedantic; + +/* Temporarily suppress certain warnings. + This is set while reading code from a system header file. */ + +extern int in_system_header; + +/* Nonzero for -dp: annotate the assembly with a comment describing the + pattern and alternative used. */ + +extern int flag_print_asm_name; + +/* Now the symbols that are set with `-f' switches. */ + +/* Nonzero means `char' should be signed. */ + +extern int flag_signed_char; + +/* Nonzero means give an enum type only as many bytes as it needs. */ + +extern int flag_short_enums; + +/* Nonzero for -fcaller-saves: allocate values in regs that need to + be saved across function calls, if that produces overall better code. + Optional now, so people can test it. */ + +extern int flag_caller_saves; + +/* Nonzero for -fpcc-struct-return: return values the same way PCC does. */ + +extern int flag_pcc_struct_return; + +/* Nonzero for -fforce-mem: load memory value into a register + before arithmetic on it. This makes better cse but slower compilation. */ + +extern int flag_force_mem; + +/* Nonzero for -fforce-addr: load memory address into a register before + reference to memory. This makes better cse but slower compilation. */ + +extern int flag_force_addr; + +/* Nonzero for -fdefer-pop: don't pop args after each function call; + instead save them up to pop many calls' args with one insns. */ + +extern int flag_defer_pop; + +/* Nonzero for -ffloat-store: don't allocate floats and doubles + in extended-precision registers. */ + +extern int flag_float_store; + +/* Nonzero enables strength-reduction in loop.c. */ + +extern int flag_strength_reduce; + +/* Nonzero enables loop unrolling in unroll.c. Only loops for which the + number of iterations can be calculated at compile-time (UNROLL_COMPLETELY, + UNROLL_MODULO) or at run-time (preconditioned to be UNROLL_MODULO) are + unrolled. */ + +extern int flag_unroll_loops; + +/* Nonzero enables loop unrolling in unroll.c. All loops are unrolled. + This is generally not a win. */ + +extern int flag_unroll_all_loops; + +/* Nonzero for -fcse-follow-jumps: + have cse follow jumps to do a more extensive job. */ + +extern int flag_cse_follow_jumps; + +/* Nonzero for -fcse-skip-blocks: + have cse follow a branch around a block. */ + +extern int flag_cse_skip_blocks; + +/* Nonzero for -fexpensive-optimizations: + perform miscellaneous relatively-expensive optimizations. */ +extern int flag_expensive_optimizations; + +/* Nonzero for -fwritable-strings: + store string constants in data segment and don't uniquize them. */ + +extern int flag_writable_strings; + +/* Nonzero means don't put addresses of constant functions in registers. + Used for compiling the Unix kernel, where strange substitutions are + done on the assembly output. */ + +extern int flag_no_function_cse; + +/* Nonzero for -fomit-frame-pointer: + don't make a frame pointer in simple functions that don't require one. */ + +extern int flag_omit_frame_pointer; + +/* Nonzero to inhibit use of define_optimization peephole opts. */ + +extern int flag_no_peephole; + +/* Nonzero means all references through pointers are volatile. */ + +extern int flag_volatile; + +/* Nonzero means treat all global and extern variables as global. */ + +extern int flag_volatile_global; + +/* Nonzero allows GCC to violate some IEEE or ANSI rules regarding math + operations in the interest of optimization. For example it allows + GCC to assume arguments to sqrt are nonnegative numbers, allowing + faster code for sqrt to be generated. */ + +extern int flag_fast_math; + +/* Nonzero means make functions that look like good inline candidates + go inline. */ + +extern int flag_inline_functions; + +/* Nonzero for -fkeep-inline-functions: even if we make a function + go inline everywhere, keep its definition around for debugging + purposes. */ + +extern int flag_keep_inline_functions; + +/* Nonzero means that functions declared `inline' will be treated + as `static'. Prevents generation of zillions of copies of unused + static inline functions; instead, `inlines' are written out + only when actually used. Used in conjunction with -g. Also + does the right thing with #pragma interface. */ + +extern int flag_no_inline; + +/* Nonzero if we are only using compiler to check syntax errors. */ + +extern int flag_syntax_only; + +/* Nonzero means we should save auxiliary info into a .X file. */ + +extern int flag_gen_aux_info; + +/* Nonzero means make the text shared if supported. */ + +extern int flag_shared_data; + +/* flag_schedule_insns means schedule insns within basic blocks (before + local_alloc). + flag_schedule_insns_after_reload means schedule insns after + global_alloc. */ + +extern int flag_schedule_insns; +extern int flag_schedule_insns_after_reload; + +/* Nonzero means put things in delayed-branch slots if supported. */ + +extern int flag_delayed_branch; + +/* Nonzero means pretend it is OK to examine bits of target floats, + even if that isn't true. The resulting code will have incorrect constants, + but the same series of instructions that the native compiler would make. */ + +extern int flag_pretend_float; + +/* Nonzero means change certain warnings into errors. + Usually these are warnings about failure to conform to some standard. */ + +extern int flag_pedantic_errors; + +/* Nonzero means generate position-independent code. + This is not fully implemented yet. */ + +extern int flag_pic; + +/* Nonzero means place uninitialized global data in the bss section. */ + +extern int flag_no_common; + +/* -finhibit-size-directive inhibits output of .size for ELF. + This is used only for compiling crtstuff.c, + and it may be extended to other effects + needed for crtstuff.c on other systems. */ +extern int flag_inhibit_size_directive; + +/* -fverbose-asm causes extra commentary information to be produced in + the generated assembly code (to make it more readable). This option + is generally only of use to those who actually need to read the + generated assembly code (perhaps while debugging the compiler itself). */ + +extern int flag_verbose_asm; + +/* -fgnu-linker specifies use of the GNU linker for initializations. + -fno-gnu-linker says that collect will be used. */ +extern int flag_gnu_linker; + +/* Other basic status info about current function. */ + +/* Nonzero means current function must be given a frame pointer. + Set in stmt.c if anything is allocated on the stack there. + Set in reload1.c if anything is allocated on the stack there. */ + +extern int frame_pointer_needed; + +/* Set nonzero if jump_optimize finds that control falls through + at the end of the function. */ + +extern int can_reach_end; + +/* Nonzero if function being compiled receives nonlocal gotos + from nested functions. */ + +extern int current_function_has_nonlocal_label; + diff --git a/gnu/usr.bin/cc/lib/flow.c b/gnu/usr.bin/cc/lib/flow.c new file mode 100644 index 000000000000..a5cc47612b03 --- /dev/null +++ b/gnu/usr.bin/cc/lib/flow.c @@ -0,0 +1,2674 @@ +/* Data flow analysis for GNU compiler. + Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This file contains the data flow analysis pass of the compiler. + It computes data flow information + which tells combine_instructions which insns to consider combining + and controls register allocation. + + Additional data flow information that is too bulky to record + is generated during the analysis, and is used at that time to + create autoincrement and autodecrement addressing. + + The first step is dividing the function into basic blocks. + find_basic_blocks does this. Then life_analysis determines + where each register is live and where it is dead. + + ** find_basic_blocks ** + + find_basic_blocks divides the current function's rtl + into basic blocks. It records the beginnings and ends of the + basic blocks in the vectors basic_block_head and basic_block_end, + and the number of blocks in n_basic_blocks. + + find_basic_blocks also finds any unreachable loops + and deletes them. + + ** life_analysis ** + + life_analysis is called immediately after find_basic_blocks. + It uses the basic block information to determine where each + hard or pseudo register is live. + + ** live-register info ** + + The information about where each register is live is in two parts: + the REG_NOTES of insns, and the vector basic_block_live_at_start. + + basic_block_live_at_start has an element for each basic block, + and the element is a bit-vector with a bit for each hard or pseudo + register. The bit is 1 if the register is live at the beginning + of the basic block. + + Two types of elements can be added to an insn's REG_NOTES. + A REG_DEAD note is added to an insn's REG_NOTES for any register + that meets both of two conditions: The value in the register is not + needed in subsequent insns and the insn does not replace the value in + the register (in the case of multi-word hard registers, the value in + each register must be replaced by the insn to avoid a REG_DEAD note). + + In the vast majority of cases, an object in a REG_DEAD note will be + used somewhere in the insn. The (rare) exception to this is if an + insn uses a multi-word hard register and only some of the registers are + needed in subsequent insns. In that case, REG_DEAD notes will be + provided for those hard registers that are not subsequently needed. + Partial REG_DEAD notes of this type do not occur when an insn sets + only some of the hard registers used in such a multi-word operand; + omitting REG_DEAD notes for objects stored in an insn is optional and + the desire to do so does not justify the complexity of the partial + REG_DEAD notes. + + REG_UNUSED notes are added for each register that is set by the insn + but is unused subsequently (if every register set by the insn is unused + and the insn does not reference memory or have some other side-effect, + the insn is deleted instead). If only part of a multi-word hard + register is used in a subsequent insn, REG_UNUSED notes are made for + the parts that will not be used. + + To determine which registers are live after any insn, one can + start from the beginning of the basic block and scan insns, noting + which registers are set by each insn and which die there. + + ** Other actions of life_analysis ** + + life_analysis sets up the LOG_LINKS fields of insns because the + information needed to do so is readily available. + + life_analysis deletes insns whose only effect is to store a value + that is never used. + + life_analysis notices cases where a reference to a register as + a memory address can be combined with a preceding or following + incrementation or decrementation of the register. The separate + instruction to increment or decrement is deleted and the address + is changed to a POST_INC or similar rtx. + + Each time an incrementing or decrementing address is created, + a REG_INC element is added to the insn's REG_NOTES list. + + life_analysis fills in certain vectors containing information about + register usage: reg_n_refs, reg_n_deaths, reg_n_sets, reg_live_length, + reg_n_calls_crosses and reg_basic_block. */ + +#include +#include "config.h" +#include "rtl.h" +#include "basic-block.h" +#include "insn-config.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "flags.h" +#include "output.h" + +#include "obstack.h" +#define obstack_chunk_alloc xmalloc +#define obstack_chunk_free free + +/* List of labels that must never be deleted. */ +extern rtx forced_labels; + +/* Get the basic block number of an insn. + This info should not be expected to remain available + after the end of life_analysis. */ + +/* This is the limit of the allocated space in the following two arrays. */ + +static int max_uid_for_flow; + +#define BLOCK_NUM(INSN) uid_block_number[INSN_UID (INSN)] + +/* This is where the BLOCK_NUM values are really stored. + This is set up by find_basic_blocks and used there and in life_analysis, + and then freed. */ + +static int *uid_block_number; + +/* INSN_VOLATILE (insn) is 1 if the insn refers to anything volatile. */ + +#define INSN_VOLATILE(INSN) uid_volatile[INSN_UID (INSN)] +static char *uid_volatile; + +/* Number of basic blocks in the current function. */ + +int n_basic_blocks; + +/* Maximum register number used in this function, plus one. */ + +int max_regno; + +/* Maximum number of SCRATCH rtx's used in any basic block of this function. */ + +int max_scratch; + +/* Number of SCRATCH rtx's in the current block. */ + +static int num_scratch; + +/* Indexed by n, gives number of basic block that (REG n) is used in. + If the value is REG_BLOCK_GLOBAL (-2), + it means (REG n) is used in more than one basic block. + REG_BLOCK_UNKNOWN (-1) means it hasn't been seen yet so we don't know. + This information remains valid for the rest of the compilation + of the current function; it is used to control register allocation. */ + +int *reg_basic_block; + +/* Indexed by n, gives number of times (REG n) is used or set, each + weighted by its loop-depth. + This information remains valid for the rest of the compilation + of the current function; it is used to control register allocation. */ + +int *reg_n_refs; + +/* Indexed by N, gives number of places register N dies. + This information remains valid for the rest of the compilation + of the current function; it is used to control register allocation. */ + +short *reg_n_deaths; + +/* Indexed by N, gives 1 if that reg is live across any CALL_INSNs. + This information remains valid for the rest of the compilation + of the current function; it is used to control register allocation. */ + +int *reg_n_calls_crossed; + +/* Total number of instructions at which (REG n) is live. + The larger this is, the less priority (REG n) gets for + allocation in a real register. + This information remains valid for the rest of the compilation + of the current function; it is used to control register allocation. + + local-alloc.c may alter this number to change the priority. + + Negative values are special. + -1 is used to mark a pseudo reg which has a constant or memory equivalent + and is used infrequently enough that it should not get a hard register. + -2 is used to mark a pseudo reg for a parameter, when a frame pointer + is not required. global.c makes an allocno for this but does + not try to assign a hard register to it. */ + +int *reg_live_length; + +/* Element N is the next insn that uses (hard or pseudo) register number N + within the current basic block; or zero, if there is no such insn. + This is valid only during the final backward scan in propagate_block. */ + +static rtx *reg_next_use; + +/* Size of a regset for the current function, + in (1) bytes and (2) elements. */ + +int regset_bytes; +int regset_size; + +/* Element N is first insn in basic block N. + This info lasts until we finish compiling the function. */ + +rtx *basic_block_head; + +/* Element N is last insn in basic block N. + This info lasts until we finish compiling the function. */ + +rtx *basic_block_end; + +/* Element N is a regset describing the registers live + at the start of basic block N. + This info lasts until we finish compiling the function. */ + +regset *basic_block_live_at_start; + +/* Regset of regs live when calls to `setjmp'-like functions happen. */ + +regset regs_live_at_setjmp; + +/* List made of EXPR_LIST rtx's which gives pairs of pseudo registers + that have to go in the same hard reg. + The first two regs in the list are a pair, and the next two + are another pair, etc. */ +rtx regs_may_share; + +/* Element N is nonzero if control can drop into basic block N + from the preceding basic block. Freed after life_analysis. */ + +static char *basic_block_drops_in; + +/* Element N is depth within loops of the last insn in basic block number N. + Freed after life_analysis. */ + +static short *basic_block_loop_depth; + +/* Element N nonzero if basic block N can actually be reached. + Vector exists only during find_basic_blocks. */ + +static char *block_live_static; + +/* Depth within loops of basic block being scanned for lifetime analysis, + plus one. This is the weight attached to references to registers. */ + +static int loop_depth; + +/* During propagate_block, this is non-zero if the value of CC0 is live. */ + +static int cc0_live; + +/* During propagate_block, this contains the last MEM stored into. It + is used to eliminate consecutive stores to the same location. */ + +static rtx last_mem_set; + +/* Set of registers that may be eliminable. These are handled specially + in updating regs_ever_live. */ + +static HARD_REG_SET elim_reg_set; + +/* Forward declarations */ +static void find_basic_blocks (); +static void life_analysis (); +static void mark_label_ref (); +void allocate_for_life_analysis (); /* Used also in stupid_life_analysis */ +static void init_regset_vector (); +static void propagate_block (); +static void mark_set_regs (); +static void mark_used_regs (); +static int insn_dead_p (); +static int libcall_dead_p (); +static int try_pre_increment (); +static int try_pre_increment_1 (); +static rtx find_use_as_address (); +void dump_flow_info (); + +/* Find basic blocks of the current function and perform data flow analysis. + F is the first insn of the function and NREGS the number of register numbers + in use. */ + +void +flow_analysis (f, nregs, file) + rtx f; + int nregs; + FILE *file; +{ + register rtx insn; + register int i; + rtx nonlocal_label_list = nonlocal_label_rtx_list (); + +#ifdef ELIMINABLE_REGS + static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; +#endif + + /* Record which registers will be eliminated. We use this in + mark_used_regs. */ + + CLEAR_HARD_REG_SET (elim_reg_set); + +#ifdef ELIMINABLE_REGS + for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++) + SET_HARD_REG_BIT (elim_reg_set, eliminables[i].from); +#else + SET_HARD_REG_BIT (elim_reg_set, FRAME_POINTER_REGNUM); +#endif + + /* Count the basic blocks. Also find maximum insn uid value used. */ + + { + register RTX_CODE prev_code = JUMP_INSN; + register RTX_CODE code; + + max_uid_for_flow = 0; + + for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) + { + code = GET_CODE (insn); + if (INSN_UID (insn) > max_uid_for_flow) + max_uid_for_flow = INSN_UID (insn); + if (code == CODE_LABEL + || (GET_RTX_CLASS (code) == 'i' + && (prev_code == JUMP_INSN + || (prev_code == CALL_INSN + && nonlocal_label_list != 0) + || prev_code == BARRIER))) + i++; + if (code != NOTE) + prev_code = code; + } + } + +#ifdef AUTO_INC_DEC + /* Leave space for insns we make in some cases for auto-inc. These cases + are rare, so we don't need too much space. */ + max_uid_for_flow += max_uid_for_flow / 10; +#endif + + /* Allocate some tables that last till end of compiling this function + and some needed only in find_basic_blocks and life_analysis. */ + + n_basic_blocks = i; + basic_block_head = (rtx *) oballoc (n_basic_blocks * sizeof (rtx)); + basic_block_end = (rtx *) oballoc (n_basic_blocks * sizeof (rtx)); + basic_block_drops_in = (char *) alloca (n_basic_blocks); + basic_block_loop_depth = (short *) alloca (n_basic_blocks * sizeof (short)); + uid_block_number + = (int *) alloca ((max_uid_for_flow + 1) * sizeof (int)); + uid_volatile = (char *) alloca (max_uid_for_flow + 1); + bzero (uid_volatile, max_uid_for_flow + 1); + + find_basic_blocks (f, nonlocal_label_list); + life_analysis (f, nregs); + if (file) + dump_flow_info (file); + + basic_block_drops_in = 0; + uid_block_number = 0; + basic_block_loop_depth = 0; +} + +/* Find all basic blocks of the function whose first insn is F. + Store the correct data in the tables that describe the basic blocks, + set up the chains of references for each CODE_LABEL, and + delete any entire basic blocks that cannot be reached. + + NONLOCAL_LABEL_LIST is the same local variable from flow_analysis. */ + +static void +find_basic_blocks (f, nonlocal_label_list) + rtx f, nonlocal_label_list; +{ + register rtx insn; + register int i; + register char *block_live = (char *) alloca (n_basic_blocks); + register char *block_marked = (char *) alloca (n_basic_blocks); + /* List of label_refs to all labels whose addresses are taken + and used as data. */ + rtx label_value_list = 0; + + block_live_static = block_live; + bzero (block_live, n_basic_blocks); + bzero (block_marked, n_basic_blocks); + + /* Initialize with just block 0 reachable and no blocks marked. */ + if (n_basic_blocks > 0) + block_live[0] = 1; + + /* Initialize the ref chain of each label to 0. */ + /* Record where all the blocks start and end and their depth in loops. */ + /* For each insn, record the block it is in. */ + /* Also mark as reachable any blocks headed by labels that + must not be deleted. */ + + { + register RTX_CODE prev_code = JUMP_INSN; + register RTX_CODE code; + int depth = 1; + + for (insn = f, i = -1; insn; insn = NEXT_INSN (insn)) + { + code = GET_CODE (insn); + if (code == NOTE) + { + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) + depth++; + else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) + depth--; + } + /* A basic block starts at label, or after something that can jump. */ + else if (code == CODE_LABEL + || (GET_RTX_CLASS (code) == 'i' + && (prev_code == JUMP_INSN + || (prev_code == CALL_INSN + && nonlocal_label_list != 0) + || prev_code == BARRIER))) + { + basic_block_head[++i] = insn; + basic_block_end[i] = insn; + basic_block_loop_depth[i] = depth; + if (code == CODE_LABEL) + { + LABEL_REFS (insn) = insn; + /* Any label that cannot be deleted + is considered to start a reachable block. */ + if (LABEL_PRESERVE_P (insn)) + block_live[i] = 1; + } + } + else if (GET_RTX_CLASS (code) == 'i') + { + basic_block_end[i] = insn; + basic_block_loop_depth[i] = depth; + } + + /* Make a list of all labels referred to other than by jumps. */ + if (code == INSN || code == CALL_INSN) + { + rtx note = find_reg_note (insn, REG_LABEL, NULL_RTX); + if (note != 0) + label_value_list = gen_rtx (EXPR_LIST, VOIDmode, XEXP (note, 0), + label_value_list); + } + + BLOCK_NUM (insn) = i; + + /* Don't separate a CALL_INSN from following CLOBBER insns. This is + a kludge that will go away when each CALL_INSN records its + USE and CLOBBERs. */ + + if (code != NOTE + && ! (prev_code == CALL_INSN && code == INSN + && GET_CODE (PATTERN (insn)) == CLOBBER)) + prev_code = code; + } + if (i + 1 != n_basic_blocks) + abort (); + } + + /* Don't delete the labels (in this function) + that are referenced by non-jump instructions. */ + { + register rtx x; + for (x = label_value_list; x; x = XEXP (x, 1)) + if (! LABEL_REF_NONLOCAL_P (x)) + block_live[BLOCK_NUM (XEXP (x, 0))] = 1; + } + + /* Record which basic blocks control can drop in to. */ + + { + register int i; + for (i = 0; i < n_basic_blocks; i++) + { + register rtx insn = PREV_INSN (basic_block_head[i]); + /* TEMP1 is used to avoid a bug in Sequent's compiler. */ + register int temp1; + while (insn && GET_CODE (insn) == NOTE) + insn = PREV_INSN (insn); + temp1 = insn && GET_CODE (insn) != BARRIER; + basic_block_drops_in[i] = temp1; + } + } + + /* Now find which basic blocks can actually be reached + and put all jump insns' LABEL_REFS onto the ref-chains + of their target labels. */ + + if (n_basic_blocks > 0) + { + int something_marked = 1; + + /* Find all indirect jump insns and mark them as possibly jumping + to all the labels whose addresses are explicitly used. + This is because, when there are computed gotos, + we can't tell which labels they jump to, of all the possibilities. */ + + for (insn = f; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == JUMP_INSN + && GET_CODE (PATTERN (insn)) == SET + && SET_DEST (PATTERN (insn)) == pc_rtx + && (GET_CODE (SET_SRC (PATTERN (insn))) == REG + || GET_CODE (SET_SRC (PATTERN (insn))) == MEM)) + { + rtx x; + for (x = label_value_list; x; x = XEXP (x, 1)) + mark_label_ref (gen_rtx (LABEL_REF, VOIDmode, XEXP (x, 0)), + insn, 0); + for (x = forced_labels; x; x = XEXP (x, 1)) + mark_label_ref (gen_rtx (LABEL_REF, VOIDmode, XEXP (x, 0)), + insn, 0); + } + + /* Find all call insns and mark them as possibly jumping + to all the nonlocal goto handler labels. */ + + for (insn = f; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == CALL_INSN) + { + rtx x; + for (x = nonlocal_label_list; x; x = XEXP (x, 1)) + /* Don't try marking labels that + were deleted as unreferenced. */ + if (GET_CODE (XEXP (x, 0)) == CODE_LABEL) + mark_label_ref (gen_rtx (LABEL_REF, VOIDmode, XEXP (x, 0)), + insn, 0); + /* ??? This could be made smarter: + in some cases it's possible to tell that certain + calls will not do a nonlocal goto. + + For example, if the nested functions that do the + nonlocal gotos do not have their addresses taken, then + only calls to those functions or to other nested + functions that use them could possibly do nonlocal + gotos. */ + } + + /* Pass over all blocks, marking each block that is reachable + and has not yet been marked. + Keep doing this until, in one pass, no blocks have been marked. + Then blocks_live and blocks_marked are identical and correct. + In addition, all jumps actually reachable have been marked. */ + + while (something_marked) + { + something_marked = 0; + for (i = 0; i < n_basic_blocks; i++) + if (block_live[i] && !block_marked[i]) + { + block_marked[i] = 1; + something_marked = 1; + if (i + 1 < n_basic_blocks && basic_block_drops_in[i + 1]) + block_live[i + 1] = 1; + insn = basic_block_end[i]; + if (GET_CODE (insn) == JUMP_INSN) + mark_label_ref (PATTERN (insn), insn, 0); + } + } + + /* Now delete the code for any basic blocks that can't be reached. + They can occur because jump_optimize does not recognize + unreachable loops as unreachable. */ + + for (i = 0; i < n_basic_blocks; i++) + if (!block_live[i]) + { + insn = basic_block_head[i]; + while (1) + { + if (GET_CODE (insn) == BARRIER) + abort (); + if (GET_CODE (insn) != NOTE) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + if (insn == basic_block_end[i]) + { + /* BARRIERs are between basic blocks, not part of one. + Delete a BARRIER if the preceding jump is deleted. + We cannot alter a BARRIER into a NOTE + because it is too short; but we can really delete + it because it is not part of a basic block. */ + if (NEXT_INSN (insn) != 0 + && GET_CODE (NEXT_INSN (insn)) == BARRIER) + delete_insn (NEXT_INSN (insn)); + break; + } + insn = NEXT_INSN (insn); + } + /* Each time we delete some basic blocks, + see if there is a jump around them that is + being turned into a no-op. If so, delete it. */ + + if (block_live[i - 1]) + { + register int j; + for (j = i; j < n_basic_blocks; j++) + if (block_live[j]) + { + rtx label; + insn = basic_block_end[i - 1]; + if (GET_CODE (insn) == JUMP_INSN + /* An unconditional jump is the only possibility + we must check for, since a conditional one + would make these blocks live. */ + && simplejump_p (insn) + && (label = XEXP (SET_SRC (PATTERN (insn)), 0), 1) + && INSN_UID (label) != 0 + && BLOCK_NUM (label) == j) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + if (GET_CODE (NEXT_INSN (insn)) != BARRIER) + abort (); + delete_insn (NEXT_INSN (insn)); + } + break; + } + } + } + } +} + +/* Check expression X for label references; + if one is found, add INSN to the label's chain of references. + + CHECKDUP means check for and avoid creating duplicate references + from the same insn. Such duplicates do no serious harm but + can slow life analysis. CHECKDUP is set only when duplicates + are likely. */ + +static void +mark_label_ref (x, insn, checkdup) + rtx x, insn; + int checkdup; +{ + register RTX_CODE code; + register int i; + register char *fmt; + + /* We can be called with NULL when scanning label_value_list. */ + if (x == 0) + return; + + code = GET_CODE (x); + if (code == LABEL_REF) + { + register rtx label = XEXP (x, 0); + register rtx y; + if (GET_CODE (label) != CODE_LABEL) + abort (); + /* If the label was never emitted, this insn is junk, + but avoid a crash trying to refer to BLOCK_NUM (label). + This can happen as a result of a syntax error + and a diagnostic has already been printed. */ + if (INSN_UID (label) == 0) + return; + CONTAINING_INSN (x) = insn; + /* if CHECKDUP is set, check for duplicate ref from same insn + and don't insert. */ + if (checkdup) + for (y = LABEL_REFS (label); y != label; y = LABEL_NEXTREF (y)) + if (CONTAINING_INSN (y) == insn) + return; + LABEL_NEXTREF (x) = LABEL_REFS (label); + LABEL_REFS (label) = x; + block_live_static[BLOCK_NUM (label)] = 1; + return; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + mark_label_ref (XEXP (x, i), insn, 0); + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + mark_label_ref (XVECEXP (x, i, j), insn, 1); + } + } +} + +/* Determine which registers are live at the start of each + basic block of the function whose first insn is F. + NREGS is the number of registers used in F. + We allocate the vector basic_block_live_at_start + and the regsets that it points to, and fill them with the data. + regset_size and regset_bytes are also set here. */ + +static void +life_analysis (f, nregs) + rtx f; + int nregs; +{ + register regset tem; + int first_pass; + int changed; + /* For each basic block, a bitmask of regs + live on exit from the block. */ + regset *basic_block_live_at_end; + /* For each basic block, a bitmask of regs + live on entry to a successor-block of this block. + If this does not match basic_block_live_at_end, + that must be updated, and the block must be rescanned. */ + regset *basic_block_new_live_at_end; + /* For each basic block, a bitmask of regs + whose liveness at the end of the basic block + can make a difference in which regs are live on entry to the block. + These are the regs that are set within the basic block, + possibly excluding those that are used after they are set. */ + regset *basic_block_significant; + register int i; + rtx insn; + + struct obstack flow_obstack; + + gcc_obstack_init (&flow_obstack); + + max_regno = nregs; + + bzero (regs_ever_live, sizeof regs_ever_live); + + /* Allocate and zero out many data structures + that will record the data from lifetime analysis. */ + + allocate_for_life_analysis (); + + reg_next_use = (rtx *) alloca (nregs * sizeof (rtx)); + bzero (reg_next_use, nregs * sizeof (rtx)); + + /* Set up several regset-vectors used internally within this function. + Their meanings are documented above, with their declarations. */ + + basic_block_live_at_end = (regset *) alloca (n_basic_blocks * sizeof (regset)); + /* Don't use alloca since that leads to a crash rather than an error message + if there isn't enough space. + Don't use oballoc since we may need to allocate other things during + this function on the temporary obstack. */ + tem = (regset) obstack_alloc (&flow_obstack, n_basic_blocks * regset_bytes); + bzero (tem, n_basic_blocks * regset_bytes); + init_regset_vector (basic_block_live_at_end, tem, n_basic_blocks, regset_bytes); + + basic_block_new_live_at_end = (regset *) alloca (n_basic_blocks * sizeof (regset)); + tem = (regset) obstack_alloc (&flow_obstack, n_basic_blocks * regset_bytes); + bzero (tem, n_basic_blocks * regset_bytes); + init_regset_vector (basic_block_new_live_at_end, tem, n_basic_blocks, regset_bytes); + + basic_block_significant = (regset *) alloca (n_basic_blocks * sizeof (regset)); + tem = (regset) obstack_alloc (&flow_obstack, n_basic_blocks * regset_bytes); + bzero (tem, n_basic_blocks * regset_bytes); + init_regset_vector (basic_block_significant, tem, n_basic_blocks, regset_bytes); + + /* Record which insns refer to any volatile memory + or for any reason can't be deleted just because they are dead stores. + Also, delete any insns that copy a register to itself. */ + + for (insn = f; insn; insn = NEXT_INSN (insn)) + { + enum rtx_code code1 = GET_CODE (insn); + if (code1 == CALL_INSN) + INSN_VOLATILE (insn) = 1; + else if (code1 == INSN || code1 == JUMP_INSN) + { + /* Delete (in effect) any obvious no-op moves. */ + if (GET_CODE (PATTERN (insn)) == SET + && GET_CODE (SET_DEST (PATTERN (insn))) == REG + && GET_CODE (SET_SRC (PATTERN (insn))) == REG + && REGNO (SET_DEST (PATTERN (insn))) == + REGNO (SET_SRC (PATTERN (insn))) + /* Insns carrying these notes are useful later on. */ + && ! find_reg_note (insn, REG_EQUAL, NULL_RTX)) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + else if (GET_CODE (PATTERN (insn)) == PARALLEL) + { + /* If nothing but SETs of registers to themselves, + this insn can also be deleted. */ + for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) + { + rtx tem = XVECEXP (PATTERN (insn), 0, i); + + if (GET_CODE (tem) == USE + || GET_CODE (tem) == CLOBBER) + continue; + + if (GET_CODE (tem) != SET + || GET_CODE (SET_DEST (tem)) != REG + || GET_CODE (SET_SRC (tem)) != REG + || REGNO (SET_DEST (tem)) != REGNO (SET_SRC (tem))) + break; + } + + if (i == XVECLEN (PATTERN (insn), 0) + /* Insns carrying these notes are useful later on. */ + && ! find_reg_note (insn, REG_EQUAL, NULL_RTX)) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + else + INSN_VOLATILE (insn) = volatile_refs_p (PATTERN (insn)); + } + else if (GET_CODE (PATTERN (insn)) != USE) + INSN_VOLATILE (insn) = volatile_refs_p (PATTERN (insn)); + /* A SET that makes space on the stack cannot be dead. + (Such SETs occur only for allocating variable-size data, + so they will always have a PLUS or MINUS according to the + direction of stack growth.) + Even if this function never uses this stack pointer value, + signal handlers do! */ + else if (code1 == INSN && GET_CODE (PATTERN (insn)) == SET + && SET_DEST (PATTERN (insn)) == stack_pointer_rtx +#ifdef STACK_GROWS_DOWNWARD + && GET_CODE (SET_SRC (PATTERN (insn))) == MINUS +#else + && GET_CODE (SET_SRC (PATTERN (insn))) == PLUS +#endif + && XEXP (SET_SRC (PATTERN (insn)), 0) == stack_pointer_rtx) + INSN_VOLATILE (insn) = 1; + } + } + + if (n_basic_blocks > 0) +#ifdef EXIT_IGNORE_STACK + if (! EXIT_IGNORE_STACK + || (! FRAME_POINTER_REQUIRED && flag_omit_frame_pointer)) +#endif + { + /* If exiting needs the right stack value, + consider the stack pointer live at the end of the function. */ + basic_block_live_at_end[n_basic_blocks - 1] + [STACK_POINTER_REGNUM / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << (STACK_POINTER_REGNUM % REGSET_ELT_BITS); + basic_block_new_live_at_end[n_basic_blocks - 1] + [STACK_POINTER_REGNUM / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << (STACK_POINTER_REGNUM % REGSET_ELT_BITS); + } + + /* Mark the frame pointer is needed at the end of the function. If + we end up eliminating it, it will be removed from the live list + of each basic block by reload. */ + + if (n_basic_blocks > 0) + { + basic_block_live_at_end[n_basic_blocks - 1] + [FRAME_POINTER_REGNUM / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << (FRAME_POINTER_REGNUM % REGSET_ELT_BITS); + basic_block_new_live_at_end[n_basic_blocks - 1] + [FRAME_POINTER_REGNUM / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << (FRAME_POINTER_REGNUM % REGSET_ELT_BITS); + } + + /* Mark all global registers as being live at the end of the function + since they may be referenced by our caller. */ + + if (n_basic_blocks > 0) + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (global_regs[i]) + { + basic_block_live_at_end[n_basic_blocks - 1] + [i / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS); + basic_block_new_live_at_end[n_basic_blocks - 1] + [i / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS); + } + + /* Propagate life info through the basic blocks + around the graph of basic blocks. + + This is a relaxation process: each time a new register + is live at the end of the basic block, we must scan the block + to determine which registers are, as a consequence, live at the beginning + of that block. These registers must then be marked live at the ends + of all the blocks that can transfer control to that block. + The process continues until it reaches a fixed point. */ + + first_pass = 1; + changed = 1; + while (changed) + { + changed = 0; + for (i = n_basic_blocks - 1; i >= 0; i--) + { + int consider = first_pass; + int must_rescan = first_pass; + register int j; + + if (!first_pass) + { + /* Set CONSIDER if this block needs thinking about at all + (that is, if the regs live now at the end of it + are not the same as were live at the end of it when + we last thought about it). + Set must_rescan if it needs to be thought about + instruction by instruction (that is, if any additional + reg that is live at the end now but was not live there before + is one of the significant regs of this basic block). */ + + for (j = 0; j < regset_size; j++) + { + register REGSET_ELT_TYPE x + = (basic_block_new_live_at_end[i][j] + & ~basic_block_live_at_end[i][j]); + if (x) + consider = 1; + if (x & basic_block_significant[i][j]) + { + must_rescan = 1; + consider = 1; + break; + } + } + + if (! consider) + continue; + } + + /* The live_at_start of this block may be changing, + so another pass will be required after this one. */ + changed = 1; + + if (! must_rescan) + { + /* No complete rescan needed; + just record those variables newly known live at end + as live at start as well. */ + for (j = 0; j < regset_size; j++) + { + register REGSET_ELT_TYPE x + = (basic_block_new_live_at_end[i][j] + & ~basic_block_live_at_end[i][j]); + basic_block_live_at_start[i][j] |= x; + basic_block_live_at_end[i][j] |= x; + } + } + else + { + /* Update the basic_block_live_at_start + by propagation backwards through the block. */ + bcopy (basic_block_new_live_at_end[i], + basic_block_live_at_end[i], regset_bytes); + bcopy (basic_block_live_at_end[i], + basic_block_live_at_start[i], regset_bytes); + propagate_block (basic_block_live_at_start[i], + basic_block_head[i], basic_block_end[i], 0, + first_pass ? basic_block_significant[i] + : (regset) 0, + i); + } + + { + register rtx jump, head; + /* Update the basic_block_new_live_at_end's of the block + that falls through into this one (if any). */ + head = basic_block_head[i]; + jump = PREV_INSN (head); + if (basic_block_drops_in[i]) + { + register int from_block = BLOCK_NUM (jump); + register int j; + for (j = 0; j < regset_size; j++) + basic_block_new_live_at_end[from_block][j] + |= basic_block_live_at_start[i][j]; + } + /* Update the basic_block_new_live_at_end's of + all the blocks that jump to this one. */ + if (GET_CODE (head) == CODE_LABEL) + for (jump = LABEL_REFS (head); + jump != head; + jump = LABEL_NEXTREF (jump)) + { + register int from_block = BLOCK_NUM (CONTAINING_INSN (jump)); + register int j; + for (j = 0; j < regset_size; j++) + basic_block_new_live_at_end[from_block][j] + |= basic_block_live_at_start[i][j]; + } + } +#ifdef USE_C_ALLOCA + alloca (0); +#endif + } + first_pass = 0; + } + + /* The only pseudos that are live at the beginning of the function are + those that were not set anywhere in the function. local-alloc doesn't + know how to handle these correctly, so mark them as not local to any + one basic block. */ + + if (n_basic_blocks > 0) + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (basic_block_live_at_start[0][i / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS))) + reg_basic_block[i] = REG_BLOCK_GLOBAL; + + /* Now the life information is accurate. + Make one more pass over each basic block + to delete dead stores, create autoincrement addressing + and record how many times each register is used, is set, or dies. + + To save time, we operate directly in basic_block_live_at_end[i], + thus destroying it (in fact, converting it into a copy of + basic_block_live_at_start[i]). This is ok now because + basic_block_live_at_end[i] is no longer used past this point. */ + + max_scratch = 0; + + for (i = 0; i < n_basic_blocks; i++) + { + propagate_block (basic_block_live_at_end[i], + basic_block_head[i], basic_block_end[i], 1, + (regset) 0, i); +#ifdef USE_C_ALLOCA + alloca (0); +#endif + } + +#if 0 + /* Something live during a setjmp should not be put in a register + on certain machines which restore regs from stack frames + rather than from the jmpbuf. + But we don't need to do this for the user's variables, since + ANSI says only volatile variables need this. */ +#ifdef LONGJMP_RESTORE_FROM_STACK + for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) + if (regs_live_at_setjmp[i / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)) + && regno_reg_rtx[i] != 0 && ! REG_USERVAR_P (regno_reg_rtx[i])) + { + reg_live_length[i] = -1; + reg_basic_block[i] = -1; + } +#endif +#endif + + /* We have a problem with any pseudoreg that + lives across the setjmp. ANSI says that if a + user variable does not change in value + between the setjmp and the longjmp, then the longjmp preserves it. + This includes longjmp from a place where the pseudo appears dead. + (In principle, the value still exists if it is in scope.) + If the pseudo goes in a hard reg, some other value may occupy + that hard reg where this pseudo is dead, thus clobbering the pseudo. + Conclusion: such a pseudo must not go in a hard reg. */ + for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) + if ((regs_live_at_setjmp[i / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS))) + && regno_reg_rtx[i] != 0) + { + reg_live_length[i] = -1; + reg_basic_block[i] = -1; + } + + obstack_free (&flow_obstack, NULL_PTR); +} + +/* Subroutines of life analysis. */ + +/* Allocate the permanent data structures that represent the results + of life analysis. Not static since used also for stupid life analysis. */ + +void +allocate_for_life_analysis () +{ + register int i; + register regset tem; + + regset_size = ((max_regno + REGSET_ELT_BITS - 1) / REGSET_ELT_BITS); + regset_bytes = regset_size * sizeof (*(regset)0); + + reg_n_refs = (int *) oballoc (max_regno * sizeof (int)); + bzero (reg_n_refs, max_regno * sizeof (int)); + + reg_n_sets = (short *) oballoc (max_regno * sizeof (short)); + bzero (reg_n_sets, max_regno * sizeof (short)); + + reg_n_deaths = (short *) oballoc (max_regno * sizeof (short)); + bzero (reg_n_deaths, max_regno * sizeof (short)); + + reg_live_length = (int *) oballoc (max_regno * sizeof (int)); + bzero (reg_live_length, max_regno * sizeof (int)); + + reg_n_calls_crossed = (int *) oballoc (max_regno * sizeof (int)); + bzero (reg_n_calls_crossed, max_regno * sizeof (int)); + + reg_basic_block = (int *) oballoc (max_regno * sizeof (int)); + for (i = 0; i < max_regno; i++) + reg_basic_block[i] = REG_BLOCK_UNKNOWN; + + basic_block_live_at_start = (regset *) oballoc (n_basic_blocks * sizeof (regset)); + tem = (regset) oballoc (n_basic_blocks * regset_bytes); + bzero (tem, n_basic_blocks * regset_bytes); + init_regset_vector (basic_block_live_at_start, tem, n_basic_blocks, regset_bytes); + + regs_live_at_setjmp = (regset) oballoc (regset_bytes); + bzero (regs_live_at_setjmp, regset_bytes); +} + +/* Make each element of VECTOR point at a regset, + taking the space for all those regsets from SPACE. + SPACE is of type regset, but it is really as long as NELTS regsets. + BYTES_PER_ELT is the number of bytes in one regset. */ + +static void +init_regset_vector (vector, space, nelts, bytes_per_elt) + regset *vector; + regset space; + int nelts; + int bytes_per_elt; +{ + register int i; + register regset p = space; + + for (i = 0; i < nelts; i++) + { + vector[i] = p; + p += bytes_per_elt / sizeof (*p); + } +} + +/* Compute the registers live at the beginning of a basic block + from those live at the end. + + When called, OLD contains those live at the end. + On return, it contains those live at the beginning. + FIRST and LAST are the first and last insns of the basic block. + + FINAL is nonzero if we are doing the final pass which is not + for computing the life info (since that has already been done) + but for acting on it. On this pass, we delete dead stores, + set up the logical links and dead-variables lists of instructions, + and merge instructions for autoincrement and autodecrement addresses. + + SIGNIFICANT is nonzero only the first time for each basic block. + If it is nonzero, it points to a regset in which we store + a 1 for each register that is set within the block. + + BNUM is the number of the basic block. */ + +static void +propagate_block (old, first, last, final, significant, bnum) + register regset old; + rtx first; + rtx last; + int final; + regset significant; + int bnum; +{ + register rtx insn; + rtx prev; + regset live; + regset dead; + + /* The following variables are used only if FINAL is nonzero. */ + /* This vector gets one element for each reg that has been live + at any point in the basic block that has been scanned so far. + SOMETIMES_MAX says how many elements are in use so far. + In each element, OFFSET is the byte-number within a regset + for the register described by the element, and BIT is a mask + for that register's bit within the byte. */ + register struct sometimes { short offset; short bit; } *regs_sometimes_live; + int sometimes_max = 0; + /* This regset has 1 for each reg that we have seen live so far. + It and REGS_SOMETIMES_LIVE are updated together. */ + regset maxlive; + + /* The loop depth may change in the middle of a basic block. Since we + scan from end to beginning, we start with the depth at the end of the + current basic block, and adjust as we pass ends and starts of loops. */ + loop_depth = basic_block_loop_depth[bnum]; + + dead = (regset) alloca (regset_bytes); + live = (regset) alloca (regset_bytes); + + cc0_live = 0; + last_mem_set = 0; + + /* Include any notes at the end of the block in the scan. + This is in case the block ends with a call to setjmp. */ + + while (NEXT_INSN (last) != 0 && GET_CODE (NEXT_INSN (last)) == NOTE) + { + /* Look for loop boundaries, we are going forward here. */ + last = NEXT_INSN (last); + if (NOTE_LINE_NUMBER (last) == NOTE_INSN_LOOP_BEG) + loop_depth++; + else if (NOTE_LINE_NUMBER (last) == NOTE_INSN_LOOP_END) + loop_depth--; + } + + if (final) + { + register int i, offset; + REGSET_ELT_TYPE bit; + + num_scratch = 0; + maxlive = (regset) alloca (regset_bytes); + bcopy (old, maxlive, regset_bytes); + regs_sometimes_live + = (struct sometimes *) alloca (max_regno * sizeof (struct sometimes)); + + /* Process the regs live at the end of the block. + Enter them in MAXLIVE and REGS_SOMETIMES_LIVE. + Also mark them as not local to any one basic block. */ + + for (offset = 0, i = 0; offset < regset_size; offset++) + for (bit = 1; bit; bit <<= 1, i++) + { + if (i == max_regno) + break; + if (old[offset] & bit) + { + reg_basic_block[i] = REG_BLOCK_GLOBAL; + regs_sometimes_live[sometimes_max].offset = offset; + regs_sometimes_live[sometimes_max].bit = i % REGSET_ELT_BITS; + sometimes_max++; + } + } + } + + /* Scan the block an insn at a time from end to beginning. */ + + for (insn = last; ; insn = prev) + { + prev = PREV_INSN (insn); + + /* Look for loop boundaries, remembering that we are going backwards. */ + if (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) + loop_depth++; + else if (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) + loop_depth--; + + /* If we have LOOP_DEPTH == 0, there has been a bookkeeping error. + Abort now rather than setting register status incorrectly. */ + if (loop_depth == 0) + abort (); + + /* If this is a call to `setjmp' et al, + warn if any non-volatile datum is live. */ + + if (final && GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP) + { + int i; + for (i = 0; i < regset_size; i++) + regs_live_at_setjmp[i] |= old[i]; + } + + /* Update the life-status of regs for this insn. + First DEAD gets which regs are set in this insn + then LIVE gets which regs are used in this insn. + Then the regs live before the insn + are those live after, with DEAD regs turned off, + and then LIVE regs turned on. */ + + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + register int i; + rtx note = find_reg_note (insn, REG_RETVAL, NULL_RTX); + int insn_is_dead + = (insn_dead_p (PATTERN (insn), old, 0) + /* Don't delete something that refers to volatile storage! */ + && ! INSN_VOLATILE (insn)); + int libcall_is_dead + = (insn_is_dead && note != 0 + && libcall_dead_p (PATTERN (insn), old, note, insn)); + + /* If an instruction consists of just dead store(s) on final pass, + "delete" it by turning it into a NOTE of type NOTE_INSN_DELETED. + We could really delete it with delete_insn, but that + can cause trouble for first or last insn in a basic block. */ + if (final && insn_is_dead) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + + /* CC0 is now known to be dead. Either this insn used it, + in which case it doesn't anymore, or clobbered it, + so the next insn can't use it. */ + cc0_live = 0; + + /* If this insn is copying the return value from a library call, + delete the entire library call. */ + if (libcall_is_dead) + { + rtx first = XEXP (note, 0); + rtx p = insn; + while (INSN_DELETED_P (first)) + first = NEXT_INSN (first); + while (p != first) + { + p = PREV_INSN (p); + PUT_CODE (p, NOTE); + NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (p) = 0; + } + } + goto flushed; + } + + for (i = 0; i < regset_size; i++) + { + dead[i] = 0; /* Faster than bzero here */ + live[i] = 0; /* since regset_size is usually small */ + } + + /* See if this is an increment or decrement that can be + merged into a following memory address. */ +#ifdef AUTO_INC_DEC + { + register rtx x = PATTERN (insn); + /* Does this instruction increment or decrement a register? */ + if (final && GET_CODE (x) == SET + && GET_CODE (SET_DEST (x)) == REG + && (GET_CODE (SET_SRC (x)) == PLUS + || GET_CODE (SET_SRC (x)) == MINUS) + && XEXP (SET_SRC (x), 0) == SET_DEST (x) + && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT + /* Ok, look for a following memory ref we can combine with. + If one is found, change the memory ref to a PRE_INC + or PRE_DEC, cancel this insn, and return 1. + Return 0 if nothing has been done. */ + && try_pre_increment_1 (insn)) + goto flushed; + } +#endif /* AUTO_INC_DEC */ + + /* If this is not the final pass, and this insn is copying the + value of a library call and it's dead, don't scan the + insns that perform the library call, so that the call's + arguments are not marked live. */ + if (libcall_is_dead) + { + /* Mark the dest reg as `significant'. */ + mark_set_regs (old, dead, PATTERN (insn), NULL_RTX, significant); + + insn = XEXP (note, 0); + prev = PREV_INSN (insn); + } + else if (GET_CODE (PATTERN (insn)) == SET + && SET_DEST (PATTERN (insn)) == stack_pointer_rtx + && GET_CODE (SET_SRC (PATTERN (insn))) == PLUS + && XEXP (SET_SRC (PATTERN (insn)), 0) == stack_pointer_rtx + && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT) + /* We have an insn to pop a constant amount off the stack. + (Such insns use PLUS regardless of the direction of the stack, + and any insn to adjust the stack by a constant is always a pop.) + These insns, if not dead stores, have no effect on life. */ + ; + else + { + /* LIVE gets the regs used in INSN; + DEAD gets those set by it. Dead insns don't make anything + live. */ + + mark_set_regs (old, dead, PATTERN (insn), + final ? insn : NULL_RTX, significant); + + /* If an insn doesn't use CC0, it becomes dead since we + assume that every insn clobbers it. So show it dead here; + mark_used_regs will set it live if it is referenced. */ + cc0_live = 0; + + if (! insn_is_dead) + mark_used_regs (old, live, PATTERN (insn), final, insn); + + /* Sometimes we may have inserted something before INSN (such as + a move) when we make an auto-inc. So ensure we will scan + those insns. */ +#ifdef AUTO_INC_DEC + prev = PREV_INSN (insn); +#endif + + if (! insn_is_dead && GET_CODE (insn) == CALL_INSN) + { + register int i; + + /* Each call clobbers all call-clobbered regs that are not + global. Note that the function-value reg is a + call-clobbered reg, and mark_set_regs has already had + a chance to handle it. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (call_used_regs[i] && ! global_regs[i]) + dead[i / REGSET_ELT_BITS] + |= ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)); + + /* The stack ptr is used (honorarily) by a CALL insn. */ + live[STACK_POINTER_REGNUM / REGSET_ELT_BITS] + |= ((REGSET_ELT_TYPE) 1 + << (STACK_POINTER_REGNUM % REGSET_ELT_BITS)); + + /* Calls may also reference any of the global registers, + so they are made live. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (global_regs[i]) + live[i / REGSET_ELT_BITS] + |= ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)); + + /* Calls also clobber memory. */ + last_mem_set = 0; + } + + /* Update OLD for the registers used or set. */ + for (i = 0; i < regset_size; i++) + { + old[i] &= ~dead[i]; + old[i] |= live[i]; + } + + if (GET_CODE (insn) == CALL_INSN && final) + { + /* Any regs live at the time of a call instruction + must not go in a register clobbered by calls. + Find all regs now live and record this for them. */ + + register struct sometimes *p = regs_sometimes_live; + + for (i = 0; i < sometimes_max; i++, p++) + if (old[p->offset] & ((REGSET_ELT_TYPE) 1 << p->bit)) + reg_n_calls_crossed[p->offset * REGSET_ELT_BITS + p->bit]+= 1; + } + } + + /* On final pass, add any additional sometimes-live regs + into MAXLIVE and REGS_SOMETIMES_LIVE. + Also update counts of how many insns each reg is live at. */ + + if (final) + { + for (i = 0; i < regset_size; i++) + { + register REGSET_ELT_TYPE diff = live[i] & ~maxlive[i]; + + if (diff) + { + register int regno; + maxlive[i] |= diff; + for (regno = 0; diff && regno < REGSET_ELT_BITS; regno++) + if (diff & ((REGSET_ELT_TYPE) 1 << regno)) + { + regs_sometimes_live[sometimes_max].offset = i; + regs_sometimes_live[sometimes_max].bit = regno; + diff &= ~ ((REGSET_ELT_TYPE) 1 << regno); + sometimes_max++; + } + } + } + + { + register struct sometimes *p = regs_sometimes_live; + for (i = 0; i < sometimes_max; i++, p++) + { + if (old[p->offset] & ((REGSET_ELT_TYPE) 1 << p->bit)) + reg_live_length[p->offset * REGSET_ELT_BITS + p->bit]++; + } + } + } + } + flushed: ; + if (insn == first) + break; + } + + if (num_scratch > max_scratch) + max_scratch = num_scratch; +} + +/* Return 1 if X (the body of an insn, or part of it) is just dead stores + (SET expressions whose destinations are registers dead after the insn). + NEEDED is the regset that says which regs are alive after the insn. + + Unless CALL_OK is non-zero, an insn is needed if it contains a CALL. */ + +static int +insn_dead_p (x, needed, call_ok) + rtx x; + regset needed; + int call_ok; +{ + register RTX_CODE code = GET_CODE (x); + /* If setting something that's a reg or part of one, + see if that register's altered value will be live. */ + + if (code == SET) + { + register rtx r = SET_DEST (x); + /* A SET that is a subroutine call cannot be dead. */ + if (! call_ok && GET_CODE (SET_SRC (x)) == CALL) + return 0; + +#ifdef HAVE_cc0 + if (GET_CODE (r) == CC0) + return ! cc0_live; +#endif + + if (GET_CODE (r) == MEM && last_mem_set && ! MEM_VOLATILE_P (r) + && rtx_equal_p (r, last_mem_set)) + return 1; + + while (GET_CODE (r) == SUBREG + || GET_CODE (r) == STRICT_LOW_PART + || GET_CODE (r) == ZERO_EXTRACT + || GET_CODE (r) == SIGN_EXTRACT) + r = SUBREG_REG (r); + + if (GET_CODE (r) == REG) + { + register int regno = REGNO (r); + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + + /* Don't delete insns to set global regs. */ + if ((regno < FIRST_PSEUDO_REGISTER && global_regs[regno]) + /* Make sure insns to set frame pointer aren't deleted. */ + || regno == FRAME_POINTER_REGNUM +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + /* Make sure insns to set arg pointer are never deleted + (if the arg pointer isn't fixed, there will be a USE for + it, so we can treat it normally). */ + || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) +#endif + || (needed[offset] & bit) != 0) + return 0; + + /* If this is a hard register, verify that subsequent words are + not needed. */ + if (regno < FIRST_PSEUDO_REGISTER) + { + int n = HARD_REGNO_NREGS (regno, GET_MODE (r)); + + while (--n > 0) + if ((needed[(regno + n) / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 + << ((regno + n) % REGSET_ELT_BITS))) != 0) + return 0; + } + + return 1; + } + } + /* If performing several activities, + insn is dead if each activity is individually dead. + Also, CLOBBERs and USEs can be ignored; a CLOBBER or USE + that's inside a PARALLEL doesn't make the insn worth keeping. */ + else if (code == PARALLEL) + { + register int i = XVECLEN (x, 0); + for (i--; i >= 0; i--) + { + rtx elt = XVECEXP (x, 0, i); + if (!insn_dead_p (elt, needed, call_ok) + && GET_CODE (elt) != CLOBBER + && GET_CODE (elt) != USE) + return 0; + } + return 1; + } + /* We do not check CLOBBER or USE here. + An insn consisting of just a CLOBBER or just a USE + should not be deleted. */ + return 0; +} + +/* If X is the pattern of the last insn in a libcall, and assuming X is dead, + return 1 if the entire library call is dead. + This is true if X copies a register (hard or pseudo) + and if the hard return reg of the call insn is dead. + (The caller should have tested the destination of X already for death.) + + If this insn doesn't just copy a register, then we don't + have an ordinary libcall. In that case, cse could not have + managed to substitute the source for the dest later on, + so we can assume the libcall is dead. + + NEEDED is the bit vector of pseudoregs live before this insn. + NOTE is the REG_RETVAL note of the insn. INSN is the insn itself. */ + +static int +libcall_dead_p (x, needed, note, insn) + rtx x; + regset needed; + rtx note; + rtx insn; +{ + register RTX_CODE code = GET_CODE (x); + + if (code == SET) + { + register rtx r = SET_SRC (x); + if (GET_CODE (r) == REG) + { + rtx call = XEXP (note, 0); + register int i; + + /* Find the call insn. */ + while (call != insn && GET_CODE (call) != CALL_INSN) + call = NEXT_INSN (call); + + /* If there is none, do nothing special, + since ordinary death handling can understand these insns. */ + if (call == insn) + return 0; + + /* See if the hard reg holding the value is dead. + If this is a PARALLEL, find the call within it. */ + call = PATTERN (call); + if (GET_CODE (call) == PARALLEL) + { + for (i = XVECLEN (call, 0) - 1; i >= 0; i--) + if (GET_CODE (XVECEXP (call, 0, i)) == SET + && GET_CODE (SET_SRC (XVECEXP (call, 0, i))) == CALL) + break; + + if (i < 0) + abort (); + + call = XVECEXP (call, 0, i); + } + + return insn_dead_p (call, needed, 1); + } + } + return 1; +} + +/* Return 1 if register REGNO was used before it was set. + In other words, if it is live at function entry. + Don't count global regster variables, though. */ + +int +regno_uninitialized (regno) + int regno; +{ + if (n_basic_blocks == 0 + || (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])) + return 0; + + return (basic_block_live_at_start[0][regno / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))); +} + +/* 1 if register REGNO was alive at a place where `setjmp' was called + and was set more than once or is an argument. + Such regs may be clobbered by `longjmp'. */ + +int +regno_clobbered_at_setjmp (regno) + int regno; +{ + if (n_basic_blocks == 0) + return 0; + + return ((reg_n_sets[regno] > 1 + || (basic_block_live_at_start[0][regno / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS)))) + && (regs_live_at_setjmp[regno / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS)))); +} + +/* Process the registers that are set within X. + Their bits are set to 1 in the regset DEAD, + because they are dead prior to this insn. + + If INSN is nonzero, it is the insn being processed + and the fact that it is nonzero implies this is the FINAL pass + in propagate_block. In this case, various info about register + usage is stored, LOG_LINKS fields of insns are set up. */ + +static void mark_set_1 (); + +static void +mark_set_regs (needed, dead, x, insn, significant) + regset needed; + regset dead; + rtx x; + rtx insn; + regset significant; +{ + register RTX_CODE code = GET_CODE (x); + + if (code == SET || code == CLOBBER) + mark_set_1 (needed, dead, x, insn, significant); + else if (code == PARALLEL) + { + register int i; + for (i = XVECLEN (x, 0) - 1; i >= 0; i--) + { + code = GET_CODE (XVECEXP (x, 0, i)); + if (code == SET || code == CLOBBER) + mark_set_1 (needed, dead, XVECEXP (x, 0, i), insn, significant); + } + } +} + +/* Process a single SET rtx, X. */ + +static void +mark_set_1 (needed, dead, x, insn, significant) + regset needed; + regset dead; + rtx x; + rtx insn; + regset significant; +{ + register int regno; + register rtx reg = SET_DEST (x); + + /* Modifying just one hardware register of a multi-reg value + or just a byte field of a register + does not mean the value from before this insn is now dead. + But it does mean liveness of that register at the end of the block + is significant. + + Within mark_set_1, however, we treat it as if the register is + indeed modified. mark_used_regs will, however, also treat this + register as being used. Thus, we treat these insns as setting a + new value for the register as a function of its old value. This + cases LOG_LINKS to be made appropriately and this will help combine. */ + + while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT + || GET_CODE (reg) == SIGN_EXTRACT + || GET_CODE (reg) == STRICT_LOW_PART) + reg = XEXP (reg, 0); + + /* If we are writing into memory or into a register mentioned in the + address of the last thing stored into memory, show we don't know + what the last store was. If we are writing memory, save the address + unless it is volatile. */ + if (GET_CODE (reg) == MEM + || (GET_CODE (reg) == REG + && last_mem_set != 0 && reg_overlap_mentioned_p (reg, last_mem_set))) + last_mem_set = 0; + + if (GET_CODE (reg) == MEM && ! side_effects_p (reg) + /* There are no REG_INC notes for SP, so we can't assume we'll see + everything that invalidates it. To be safe, don't eliminate any + stores though SP; none of them should be redundant anyway. */ + && ! reg_mentioned_p (stack_pointer_rtx, reg)) + last_mem_set = reg; + + if (GET_CODE (reg) == REG + && (regno = REGNO (reg), regno != FRAME_POINTER_REGNUM) +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) +#endif + && ! (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])) + /* && regno != STACK_POINTER_REGNUM) -- let's try without this. */ + { + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + REGSET_ELT_TYPE all_needed = (needed[offset] & bit); + REGSET_ELT_TYPE some_needed = (needed[offset] & bit); + + /* Mark it as a significant register for this basic block. */ + if (significant) + significant[offset] |= bit; + + /* Mark it as as dead before this insn. */ + dead[offset] |= bit; + + /* A hard reg in a wide mode may really be multiple registers. + If so, mark all of them just like the first. */ + if (regno < FIRST_PSEUDO_REGISTER) + { + int n; + + /* Nothing below is needed for the stack pointer; get out asap. + Eg, log links aren't needed, since combine won't use them. */ + if (regno == STACK_POINTER_REGNUM) + return; + + n = HARD_REGNO_NREGS (regno, GET_MODE (reg)); + while (--n > 0) + { + if (significant) + significant[(regno + n) / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << ((regno + n) % REGSET_ELT_BITS); + dead[(regno + n) / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << ((regno + n) % REGSET_ELT_BITS); + some_needed + |= (needed[(regno + n) / REGSET_ELT_BITS] + & (REGSET_ELT_TYPE) 1 << ((regno + n) % REGSET_ELT_BITS)); + all_needed + &= (needed[(regno + n) / REGSET_ELT_BITS] + & (REGSET_ELT_TYPE) 1 << ((regno + n) % REGSET_ELT_BITS)); + } + } + /* Additional data to record if this is the final pass. */ + if (insn) + { + register rtx y = reg_next_use[regno]; + register int blocknum = BLOCK_NUM (insn); + + /* The next use is no longer "next", since a store intervenes. */ + reg_next_use[regno] = 0; + + /* If this is a hard reg, record this function uses the reg. */ + + if (regno < FIRST_PSEUDO_REGISTER) + { + register int i; + int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg)); + + for (i = regno; i < endregno; i++) + { + regs_ever_live[i] = 1; + reg_n_sets[i]++; + } + } + else + { + /* Keep track of which basic blocks each reg appears in. */ + + if (reg_basic_block[regno] == REG_BLOCK_UNKNOWN) + reg_basic_block[regno] = blocknum; + else if (reg_basic_block[regno] != blocknum) + reg_basic_block[regno] = REG_BLOCK_GLOBAL; + + /* Count (weighted) references, stores, etc. This counts a + register twice if it is modified, but that is correct. */ + reg_n_sets[regno]++; + + reg_n_refs[regno] += loop_depth; + + /* The insns where a reg is live are normally counted + elsewhere, but we want the count to include the insn + where the reg is set, and the normal counting mechanism + would not count it. */ + reg_live_length[regno]++; + } + + if (all_needed) + { + /* Make a logical link from the next following insn + that uses this register, back to this insn. + The following insns have already been processed. + + We don't build a LOG_LINK for hard registers containing + in ASM_OPERANDs. If these registers get replaced, + we might wind up changing the semantics of the insn, + even if reload can make what appear to be valid assignments + later. */ + if (y && (BLOCK_NUM (y) == blocknum) + && (regno >= FIRST_PSEUDO_REGISTER + || asm_noperands (PATTERN (y)) < 0)) + LOG_LINKS (y) + = gen_rtx (INSN_LIST, VOIDmode, insn, LOG_LINKS (y)); + } + else if (! some_needed) + { + /* Note that dead stores have already been deleted when possible + If we get here, we have found a dead store that cannot + be eliminated (because the same insn does something useful). + Indicate this by marking the reg being set as dying here. */ + REG_NOTES (insn) + = gen_rtx (EXPR_LIST, REG_UNUSED, reg, REG_NOTES (insn)); + reg_n_deaths[REGNO (reg)]++; + } + else + { + /* This is a case where we have a multi-word hard register + and some, but not all, of the words of the register are + needed in subsequent insns. Write REG_UNUSED notes + for those parts that were not needed. This case should + be rare. */ + + int i; + + for (i = HARD_REGNO_NREGS (regno, GET_MODE (reg)) - 1; + i >= 0; i--) + if ((needed[(regno + i) / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 + << ((regno + i) % REGSET_ELT_BITS))) == 0) + REG_NOTES (insn) + = gen_rtx (EXPR_LIST, REG_UNUSED, + gen_rtx (REG, word_mode, regno + i), + REG_NOTES (insn)); + } + } + } + else if (GET_CODE (reg) == REG) + reg_next_use[regno] = 0; + + /* If this is the last pass and this is a SCRATCH, show it will be dying + here and count it. */ + else if (GET_CODE (reg) == SCRATCH && insn != 0) + { + REG_NOTES (insn) + = gen_rtx (EXPR_LIST, REG_UNUSED, reg, REG_NOTES (insn)); + num_scratch++; + } +} + +#ifdef AUTO_INC_DEC + +/* X is a MEM found in INSN. See if we can convert it into an auto-increment + reference. */ + +static void +find_auto_inc (needed, x, insn) + regset needed; + rtx x; + rtx insn; +{ + rtx addr = XEXP (x, 0); + int offset = 0; + + /* Here we detect use of an index register which might be good for + postincrement, postdecrement, preincrement, or predecrement. */ + + if (GET_CODE (addr) == PLUS && GET_CODE (XEXP (addr, 1)) == CONST_INT) + offset = INTVAL (XEXP (addr, 1)), addr = XEXP (addr, 0); + + if (GET_CODE (addr) == REG) + { + register rtx y; + register int size = GET_MODE_SIZE (GET_MODE (x)); + rtx use; + rtx incr; + int regno = REGNO (addr); + + /* Is the next use an increment that might make auto-increment? */ + incr = reg_next_use[regno]; + if (incr && GET_CODE (PATTERN (incr)) == SET + && BLOCK_NUM (incr) == BLOCK_NUM (insn) + /* Can't add side effects to jumps; if reg is spilled and + reloaded, there's no way to store back the altered value. */ + && GET_CODE (insn) != JUMP_INSN + && (y = SET_SRC (PATTERN (incr)), GET_CODE (y) == PLUS) + && XEXP (y, 0) == addr + && GET_CODE (XEXP (y, 1)) == CONST_INT + && (0 +#ifdef HAVE_POST_INCREMENT + || (INTVAL (XEXP (y, 1)) == size && offset == 0) +#endif +#ifdef HAVE_POST_DECREMENT + || (INTVAL (XEXP (y, 1)) == - size && offset == 0) +#endif +#ifdef HAVE_PRE_INCREMENT + || (INTVAL (XEXP (y, 1)) == size && offset == size) +#endif +#ifdef HAVE_PRE_DECREMENT + || (INTVAL (XEXP (y, 1)) == - size && offset == - size) +#endif + ) + /* Make sure this reg appears only once in this insn. */ + && (use = find_use_as_address (PATTERN (insn), addr, offset), + use != 0 && use != (rtx) 1)) + { + int win = 0; + rtx q = SET_DEST (PATTERN (incr)); + + if (dead_or_set_p (incr, addr)) + win = 1; + else if (GET_CODE (q) == REG && ! reg_used_between_p (q, insn, incr)) + { + /* We have *p followed by q = p+size. + Both p and q must be live afterward, + and q must be dead before. + Change it to q = p, ...*q..., q = q+size. + Then fall into the usual case. */ + rtx insns, temp; + + start_sequence (); + emit_move_insn (q, addr); + insns = get_insns (); + end_sequence (); + + /* If anything in INSNS have UID's that don't fit within the + extra space we allocate earlier, we can't make this auto-inc. + This should never happen. */ + for (temp = insns; temp; temp = NEXT_INSN (temp)) + { + if (INSN_UID (temp) > max_uid_for_flow) + return; + BLOCK_NUM (temp) = BLOCK_NUM (insn); + } + + emit_insns_before (insns, insn); + + if (basic_block_head[BLOCK_NUM (insn)] == insn) + basic_block_head[BLOCK_NUM (insn)] = insns; + + XEXP (x, 0) = q; + XEXP (y, 0) = q; + + /* INCR will become a NOTE and INSN won't contain a + use of ADDR. If a use of ADDR was just placed in + the insn before INSN, make that the next use. + Otherwise, invalidate it. */ + if (GET_CODE (PREV_INSN (insn)) == INSN + && GET_CODE (PATTERN (PREV_INSN (insn))) == SET + && SET_SRC (PATTERN (PREV_INSN (insn))) == addr) + reg_next_use[regno] = PREV_INSN (insn); + else + reg_next_use[regno] = 0; + + addr = q; + regno = REGNO (q); + win = 1; + + /* REGNO is now used in INCR which is below INSN, but + it previously wasn't live here. If we don't mark + it as needed, we'll put a REG_DEAD note for it + on this insn, which is incorrect. */ + needed[regno / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + + /* If there are any calls between INSN and INCR, show + that REGNO now crosses them. */ + for (temp = insn; temp != incr; temp = NEXT_INSN (temp)) + if (GET_CODE (temp) == CALL_INSN) + reg_n_calls_crossed[regno]++; + } + + if (win) + { + /* We have found a suitable auto-increment: do POST_INC around + the register here, and patch out the increment instruction + that follows. */ + XEXP (x, 0) = gen_rtx ((INTVAL (XEXP (y, 1)) == size + ? (offset ? PRE_INC : POST_INC) + : (offset ? PRE_DEC : POST_DEC)), + Pmode, addr); + + /* Record that this insn has an implicit side effect. */ + REG_NOTES (insn) + = gen_rtx (EXPR_LIST, REG_INC, addr, REG_NOTES (insn)); + + /* Modify the old increment-insn to simply copy + the already-incremented value of our register. */ + SET_SRC (PATTERN (incr)) = addr; + /* Indicate insn must be re-recognized. */ + INSN_CODE (incr) = -1; + + /* If that makes it a no-op (copying the register into itself) + then delete it so it won't appear to be a "use" and a "set" + of this register. */ + if (SET_DEST (PATTERN (incr)) == addr) + { + PUT_CODE (incr, NOTE); + NOTE_LINE_NUMBER (incr) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (incr) = 0; + } + + if (regno >= FIRST_PSEUDO_REGISTER) + { + /* Count an extra reference to the reg. When a reg is + incremented, spilling it is worse, so we want to make + that less likely. */ + reg_n_refs[regno] += loop_depth; + /* Count the increment as a setting of the register, + even though it isn't a SET in rtl. */ + reg_n_sets[regno]++; + } + } + } + } +} +#endif /* AUTO_INC_DEC */ + +/* Scan expression X and store a 1-bit in LIVE for each reg it uses. + This is done assuming the registers needed from X + are those that have 1-bits in NEEDED. + + On the final pass, FINAL is 1. This means try for autoincrement + and count the uses and deaths of each pseudo-reg. + + INSN is the containing instruction. If INSN is dead, this function is not + called. */ + +static void +mark_used_regs (needed, live, x, final, insn) + regset needed; + regset live; + rtx x; + rtx insn; + int final; +{ + register RTX_CODE code; + register int regno; + int i; + + retry: + code = GET_CODE (x); + switch (code) + { + case LABEL_REF: + case SYMBOL_REF: + case CONST_INT: + case CONST: + case CONST_DOUBLE: + case PC: + case CLOBBER: + case ADDR_VEC: + case ADDR_DIFF_VEC: + case ASM_INPUT: + return; + +#ifdef HAVE_cc0 + case CC0: + cc0_live = 1; + return; +#endif + + case MEM: + /* Invalidate the data for the last MEM stored. We could do this only + if the addresses conflict, but this doesn't seem worthwhile. */ + last_mem_set = 0; + +#ifdef AUTO_INC_DEC + if (final) + find_auto_inc (needed, x, insn); +#endif + break; + + case REG: + /* See a register other than being set + => mark it as needed. */ + + regno = REGNO (x); + { + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + REGSET_ELT_TYPE all_needed = needed[offset] & bit; + REGSET_ELT_TYPE some_needed = needed[offset] & bit; + + live[offset] |= bit; + /* A hard reg in a wide mode may really be multiple registers. + If so, mark all of them just like the first. */ + if (regno < FIRST_PSEUDO_REGISTER) + { + int n; + + /* For stack ptr or fixed arg pointer, + nothing below can be necessary, so waste no more time. */ + if (regno == STACK_POINTER_REGNUM +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) +#endif + || regno == FRAME_POINTER_REGNUM) + { + /* If this is a register we are going to try to eliminate, + don't mark it live here. If we are successful in + eliminating it, it need not be live unless it is used for + pseudos, in which case it will have been set live when + it was allocated to the pseudos. If the register will not + be eliminated, reload will set it live at that point. */ + + if (! TEST_HARD_REG_BIT (elim_reg_set, regno)) + regs_ever_live[regno] = 1; + return; + } + /* No death notes for global register variables; + their values are live after this function exits. */ + if (global_regs[regno]) + { + if (final) + reg_next_use[regno] = insn; + return; + } + + n = HARD_REGNO_NREGS (regno, GET_MODE (x)); + while (--n > 0) + { + live[(regno + n) / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << ((regno + n) % REGSET_ELT_BITS); + some_needed + |= (needed[(regno + n) / REGSET_ELT_BITS] + & (REGSET_ELT_TYPE) 1 << ((regno + n) % REGSET_ELT_BITS)); + all_needed + &= (needed[(regno + n) / REGSET_ELT_BITS] + & (REGSET_ELT_TYPE) 1 << ((regno + n) % REGSET_ELT_BITS)); + } + } + if (final) + { + /* Record where each reg is used, so when the reg + is set we know the next insn that uses it. */ + + reg_next_use[regno] = insn; + + if (regno < FIRST_PSEUDO_REGISTER) + { + /* If a hard reg is being used, + record that this function does use it. */ + + i = HARD_REGNO_NREGS (regno, GET_MODE (x)); + if (i == 0) + i = 1; + do + regs_ever_live[regno + --i] = 1; + while (i > 0); + } + else + { + /* Keep track of which basic block each reg appears in. */ + + register int blocknum = BLOCK_NUM (insn); + + if (reg_basic_block[regno] == REG_BLOCK_UNKNOWN) + reg_basic_block[regno] = blocknum; + else if (reg_basic_block[regno] != blocknum) + reg_basic_block[regno] = REG_BLOCK_GLOBAL; + + /* Count (weighted) number of uses of each reg. */ + + reg_n_refs[regno] += loop_depth; + } + + /* Record and count the insns in which a reg dies. + If it is used in this insn and was dead below the insn + then it dies in this insn. If it was set in this insn, + we do not make a REG_DEAD note; likewise if we already + made such a note. */ + + if (! all_needed + && ! dead_or_set_p (insn, x) +#if 0 + && (regno >= FIRST_PSEUDO_REGISTER || ! fixed_regs[regno]) +#endif + ) + { + /* If none of the words in X is needed, make a REG_DEAD + note. Otherwise, we must make partial REG_DEAD notes. */ + if (! some_needed) + { + REG_NOTES (insn) + = gen_rtx (EXPR_LIST, REG_DEAD, x, REG_NOTES (insn)); + reg_n_deaths[regno]++; + } + else + { + int i; + + /* Don't make a REG_DEAD note for a part of a register + that is set in the insn. */ + + for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1; + i >= 0; i--) + if ((needed[(regno + i) / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 + << ((regno + i) % REGSET_ELT_BITS))) == 0 + && ! dead_or_set_regno_p (insn, regno + i)) + REG_NOTES (insn) + = gen_rtx (EXPR_LIST, REG_DEAD, + gen_rtx (REG, word_mode, regno + i), + REG_NOTES (insn)); + } + } + } + } + return; + + case SET: + { + register rtx testreg = SET_DEST (x); + int mark_dest = 0; + + /* If storing into MEM, don't show it as being used. But do + show the address as being used. */ + if (GET_CODE (testreg) == MEM) + { +#ifdef AUTO_INC_DEC + if (final) + find_auto_inc (needed, testreg, insn); +#endif + mark_used_regs (needed, live, XEXP (testreg, 0), final, insn); + mark_used_regs (needed, live, SET_SRC (x), final, insn); + return; + } + + /* Storing in STRICT_LOW_PART is like storing in a reg + in that this SET might be dead, so ignore it in TESTREG. + but in some other ways it is like using the reg. + + Storing in a SUBREG or a bit field is like storing the entire + register in that if the register's value is not used + then this SET is not needed. */ + while (GET_CODE (testreg) == STRICT_LOW_PART + || GET_CODE (testreg) == ZERO_EXTRACT + || GET_CODE (testreg) == SIGN_EXTRACT + || GET_CODE (testreg) == SUBREG) + { + /* Modifying a single register in an alternate mode + does not use any of the old value. But these other + ways of storing in a register do use the old value. */ + if (GET_CODE (testreg) == SUBREG + && !(REG_SIZE (SUBREG_REG (testreg)) > REG_SIZE (testreg))) + ; + else + mark_dest = 1; + + testreg = XEXP (testreg, 0); + } + + /* If this is a store into a register, + recursively scan the value being stored. */ + + if (GET_CODE (testreg) == REG + && (regno = REGNO (testreg), regno != FRAME_POINTER_REGNUM) +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) +#endif + ) + /* We used to exclude global_regs here, but that seems wrong. + Storing in them is like storing in mem. */ + { + mark_used_regs (needed, live, SET_SRC (x), final, insn); + if (mark_dest) + mark_used_regs (needed, live, SET_DEST (x), final, insn); + return; + } + } + break; + + case RETURN: + /* If exiting needs the right stack value, consider this insn as + using the stack pointer. In any event, consider it as using + all global registers. */ + +#ifdef EXIT_IGNORE_STACK + if (! EXIT_IGNORE_STACK + || (! FRAME_POINTER_REQUIRED && flag_omit_frame_pointer)) +#endif + live[STACK_POINTER_REGNUM / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << (STACK_POINTER_REGNUM % REGSET_ELT_BITS); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (global_regs[i]) + live[i / REGSET_ELT_BITS] + |= (REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS); + break; + } + + /* Recursively scan the operands of this expression. */ + + { + register char *fmt = GET_RTX_FORMAT (code); + register int i; + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + { + /* Tail recursive case: save a function call level. */ + if (i == 0) + { + x = XEXP (x, 0); + goto retry; + } + mark_used_regs (needed, live, XEXP (x, i), final, insn); + } + else if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + mark_used_regs (needed, live, XVECEXP (x, i, j), final, insn); + } + } + } +} + +#ifdef AUTO_INC_DEC + +static int +try_pre_increment_1 (insn) + rtx insn; +{ + /* Find the next use of this reg. If in same basic block, + make it do pre-increment or pre-decrement if appropriate. */ + rtx x = PATTERN (insn); + HOST_WIDE_INT amount = ((GET_CODE (SET_SRC (x)) == PLUS ? 1 : -1) + * INTVAL (XEXP (SET_SRC (x), 1))); + int regno = REGNO (SET_DEST (x)); + rtx y = reg_next_use[regno]; + if (y != 0 + && BLOCK_NUM (y) == BLOCK_NUM (insn) + && try_pre_increment (y, SET_DEST (PATTERN (insn)), + amount)) + { + /* We have found a suitable auto-increment + and already changed insn Y to do it. + So flush this increment-instruction. */ + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + /* Count a reference to this reg for the increment + insn we are deleting. When a reg is incremented. + spilling it is worse, so we want to make that + less likely. */ + if (regno >= FIRST_PSEUDO_REGISTER) + { + reg_n_refs[regno] += loop_depth; + reg_n_sets[regno]++; + } + return 1; + } + return 0; +} + +/* Try to change INSN so that it does pre-increment or pre-decrement + addressing on register REG in order to add AMOUNT to REG. + AMOUNT is negative for pre-decrement. + Returns 1 if the change could be made. + This checks all about the validity of the result of modifying INSN. */ + +static int +try_pre_increment (insn, reg, amount) + rtx insn, reg; + HOST_WIDE_INT amount; +{ + register rtx use; + + /* Nonzero if we can try to make a pre-increment or pre-decrement. + For example, addl $4,r1; movl (r1),... can become movl +(r1),... */ + int pre_ok = 0; + /* Nonzero if we can try to make a post-increment or post-decrement. + For example, addl $4,r1; movl -4(r1),... can become movl (r1)+,... + It is possible for both PRE_OK and POST_OK to be nonzero if the machine + supports both pre-inc and post-inc, or both pre-dec and post-dec. */ + int post_ok = 0; + + /* Nonzero if the opportunity actually requires post-inc or post-dec. */ + int do_post = 0; + + /* From the sign of increment, see which possibilities are conceivable + on this target machine. */ +#ifdef HAVE_PRE_INCREMENT + if (amount > 0) + pre_ok = 1; +#endif +#ifdef HAVE_POST_INCREMENT + if (amount > 0) + post_ok = 1; +#endif + +#ifdef HAVE_PRE_DECREMENT + if (amount < 0) + pre_ok = 1; +#endif +#ifdef HAVE_POST_DECREMENT + if (amount < 0) + post_ok = 1; +#endif + + if (! (pre_ok || post_ok)) + return 0; + + /* It is not safe to add a side effect to a jump insn + because if the incremented register is spilled and must be reloaded + there would be no way to store the incremented value back in memory. */ + + if (GET_CODE (insn) == JUMP_INSN) + return 0; + + use = 0; + if (pre_ok) + use = find_use_as_address (PATTERN (insn), reg, 0); + if (post_ok && (use == 0 || use == (rtx) 1)) + { + use = find_use_as_address (PATTERN (insn), reg, -amount); + do_post = 1; + } + + if (use == 0 || use == (rtx) 1) + return 0; + + if (GET_MODE_SIZE (GET_MODE (use)) != (amount > 0 ? amount : - amount)) + return 0; + + XEXP (use, 0) = gen_rtx (amount > 0 + ? (do_post ? POST_INC : PRE_INC) + : (do_post ? POST_DEC : PRE_DEC), + Pmode, reg); + + /* Record that this insn now has an implicit side effect on X. */ + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, reg, REG_NOTES (insn)); + return 1; +} + +#endif /* AUTO_INC_DEC */ + +/* Find the place in the rtx X where REG is used as a memory address. + Return the MEM rtx that so uses it. + If PLUSCONST is nonzero, search instead for a memory address equivalent to + (plus REG (const_int PLUSCONST)). + + If such an address does not appear, return 0. + If REG appears more than once, or is used other than in such an address, + return (rtx)1. */ + +static rtx +find_use_as_address (x, reg, plusconst) + register rtx x; + rtx reg; + int plusconst; +{ + enum rtx_code code = GET_CODE (x); + char *fmt = GET_RTX_FORMAT (code); + register int i; + register rtx value = 0; + register rtx tem; + + if (code == MEM && XEXP (x, 0) == reg && plusconst == 0) + return x; + + if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS + && XEXP (XEXP (x, 0), 0) == reg + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (x, 0), 1)) == plusconst) + return x; + + if (code == SIGN_EXTRACT || code == ZERO_EXTRACT) + { + /* If REG occurs inside a MEM used in a bit-field reference, + that is unacceptable. */ + if (find_use_as_address (XEXP (x, 0), reg, 0) != 0) + return (rtx) (HOST_WIDE_INT) 1; + } + + if (x == reg) + return (rtx) (HOST_WIDE_INT) 1; + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + { + tem = find_use_as_address (XEXP (x, i), reg, plusconst); + if (value == 0) + value = tem; + else if (tem != 0) + return (rtx) (HOST_WIDE_INT) 1; + } + if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + { + tem = find_use_as_address (XVECEXP (x, i, j), reg, plusconst); + if (value == 0) + value = tem; + else if (tem != 0) + return (rtx) (HOST_WIDE_INT) 1; + } + } + } + + return value; +} + +/* Write information about registers and basic blocks into FILE. + This is part of making a debugging dump. */ + +void +dump_flow_info (file) + FILE *file; +{ + register int i; + static char *reg_class_names[] = REG_CLASS_NAMES; + + fprintf (file, "%d registers.\n", max_regno); + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (reg_n_refs[i]) + { + enum reg_class class, altclass; + fprintf (file, "\nRegister %d used %d times across %d insns", + i, reg_n_refs[i], reg_live_length[i]); + if (reg_basic_block[i] >= 0) + fprintf (file, " in block %d", reg_basic_block[i]); + if (reg_n_deaths[i] != 1) + fprintf (file, "; dies in %d places", reg_n_deaths[i]); + if (reg_n_calls_crossed[i] == 1) + fprintf (file, "; crosses 1 call"); + else if (reg_n_calls_crossed[i]) + fprintf (file, "; crosses %d calls", reg_n_calls_crossed[i]); + if (PSEUDO_REGNO_BYTES (i) != UNITS_PER_WORD) + fprintf (file, "; %d bytes", PSEUDO_REGNO_BYTES (i)); + class = reg_preferred_class (i); + altclass = reg_alternate_class (i); + if (class != GENERAL_REGS || altclass != ALL_REGS) + { + if (altclass == ALL_REGS || class == ALL_REGS) + fprintf (file, "; pref %s", reg_class_names[(int) class]); + else if (altclass == NO_REGS) + fprintf (file, "; %s or none", reg_class_names[(int) class]); + else + fprintf (file, "; pref %s, else %s", + reg_class_names[(int) class], + reg_class_names[(int) altclass]); + } + if (REGNO_POINTER_FLAG (i)) + fprintf (file, "; pointer"); + fprintf (file, ".\n"); + } + fprintf (file, "\n%d basic blocks.\n", n_basic_blocks); + for (i = 0; i < n_basic_blocks; i++) + { + register rtx head, jump; + register int regno; + fprintf (file, "\nBasic block %d: first insn %d, last %d.\n", + i, + INSN_UID (basic_block_head[i]), + INSN_UID (basic_block_end[i])); + /* The control flow graph's storage is freed + now when flow_analysis returns. + Don't try to print it if it is gone. */ + if (basic_block_drops_in) + { + fprintf (file, "Reached from blocks: "); + head = basic_block_head[i]; + if (GET_CODE (head) == CODE_LABEL) + for (jump = LABEL_REFS (head); + jump != head; + jump = LABEL_NEXTREF (jump)) + { + register int from_block = BLOCK_NUM (CONTAINING_INSN (jump)); + fprintf (file, " %d", from_block); + } + if (basic_block_drops_in[i]) + fprintf (file, " previous"); + } + fprintf (file, "\nRegisters live at start:"); + for (regno = 0; regno < max_regno; regno++) + { + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + if (basic_block_live_at_start[i][offset] & bit) + fprintf (file, " %d", regno); + } + fprintf (file, "\n"); + } + fprintf (file, "\n"); +} diff --git a/gnu/usr.bin/cc/lib/fold-const.c b/gnu/usr.bin/cc/lib/fold-const.c new file mode 100644 index 000000000000..6570ac2a62d5 --- /dev/null +++ b/gnu/usr.bin/cc/lib/fold-const.c @@ -0,0 +1,4479 @@ +/* Fold a constant sub-tree into a single node for C-compiler + Copyright (C) 1987, 1988, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/*@@ Fix lossage on folding division of big integers. */ + +/*@@ This file should be rewritten to use an arbitrary precision + @@ representation for "struct tree_int_cst" and "struct tree_real_cst". + @@ Perhaps the routines could also be used for bc/dc, and made a lib. + @@ The routines that translate from the ap rep should + @@ warn if precision et. al. is lost. + @@ This would also make life easier when this technology is used + @@ for cross-compilers. */ + + +/* The entry points in this file are fold, size_int and size_binop. + + fold takes a tree as argument and returns a simplified tree. + + size_binop takes a tree code for an arithmetic operation + and two operands that are trees, and produces a tree for the + result, assuming the type comes from `sizetype'. + + size_int takes an integer value, and creates a tree constant + with type from `sizetype'. */ + +#include +#include +#include "config.h" +#include "flags.h" +#include "tree.h" + +/* Handle floating overflow for `const_binop'. */ +static jmp_buf float_error; + +void lshift_double (); +void rshift_double (); +void lrotate_double (); +void rrotate_double (); +static tree const_binop (); + +#ifndef BRANCH_COST +#define BRANCH_COST 1 +#endif + +/* Yield nonzero if a signed left shift of A by B bits overflows. */ +#define left_shift_overflows(a, b) ((a) != ((a) << (b)) >> (b)) + +/* Suppose A1 + B1 = SUM1, using 2's complement arithmetic ignoring overflow. + Suppose A, B and SUM have the same respective signs as A1, B1, and SUM1. + Then this yields nonzero if overflow occurred during the addition. + Overflow occurs if A and B have the same sign, but A and SUM differ in sign. + Use `^' to test whether signs differ, and `< 0' to isolate the sign. */ +#define overflow_sum_sign(a, b, sum) ((~((a) ^ (b)) & ((a) ^ (sum))) < 0) + +/* To do constant folding on INTEGER_CST nodes requires two-word arithmetic. + We do that by representing the two-word integer as MAX_SHORTS shorts, + with only 8 bits stored in each short, as a positive number. */ + +/* Unpack a two-word integer into MAX_SHORTS shorts. + LOW and HI are the integer, as two `HOST_WIDE_INT' pieces. + SHORTS points to the array of shorts. */ + +static void +encode (shorts, low, hi) + short *shorts; + HOST_WIDE_INT low, hi; +{ + register int i; + + for (i = 0; i < MAX_SHORTS / 2; i++) + { + shorts[i] = (low >> (i * 8)) & 0xff; + shorts[i + MAX_SHORTS / 2] = (hi >> (i * 8) & 0xff); + } +} + +/* Pack an array of MAX_SHORTS shorts into a two-word integer. + SHORTS points to the array of shorts. + The integer is stored into *LOW and *HI as two `HOST_WIDE_INT' pieces. */ + +static void +decode (shorts, low, hi) + short *shorts; + HOST_WIDE_INT *low, *hi; +{ + register int i; + HOST_WIDE_INT lv = 0, hv = 0; + + for (i = 0; i < MAX_SHORTS / 2; i++) + { + lv |= (HOST_WIDE_INT) shorts[i] << (i * 8); + hv |= (HOST_WIDE_INT) shorts[i + MAX_SHORTS / 2] << (i * 8); + } + + *low = lv, *hi = hv; +} + +/* Make the integer constant T valid for its type + by setting to 0 or 1 all the bits in the constant + that don't belong in the type. + Yield 1 if a signed overflow occurs, 0 otherwise. + If OVERFLOW is nonzero, a signed overflow has already occurred + in calculating T, so propagate it. */ + +int +force_fit_type (t, overflow) + tree t; + int overflow; +{ + HOST_WIDE_INT low, high; + register int prec; + + if (TREE_CODE (t) != INTEGER_CST) + return overflow; + + low = TREE_INT_CST_LOW (t); + high = TREE_INT_CST_HIGH (t); + + if (TREE_CODE (TREE_TYPE (t)) == POINTER_TYPE) + prec = POINTER_SIZE; + else + prec = TYPE_PRECISION (TREE_TYPE (t)); + + /* First clear all bits that are beyond the type's precision. */ + + if (prec == 2 * HOST_BITS_PER_WIDE_INT) + ; + else if (prec > HOST_BITS_PER_WIDE_INT) + { + TREE_INT_CST_HIGH (t) + &= ~((HOST_WIDE_INT) (-1) << (prec - HOST_BITS_PER_WIDE_INT)); + } + else + { + TREE_INT_CST_HIGH (t) = 0; + if (prec < HOST_BITS_PER_WIDE_INT) + TREE_INT_CST_LOW (t) &= ~((HOST_WIDE_INT) (-1) << prec); + } + + /* Unsigned types do not suffer sign extension or overflow. */ + if (TREE_UNSIGNED (TREE_TYPE (t))) + return 0; + + /* If the value's sign bit is set, extend the sign. */ + if (prec != 2 * HOST_BITS_PER_WIDE_INT + && (prec > HOST_BITS_PER_WIDE_INT + ? (TREE_INT_CST_HIGH (t) + & ((HOST_WIDE_INT) 1 << (prec - HOST_BITS_PER_WIDE_INT - 1))) + : TREE_INT_CST_LOW (t) & ((HOST_WIDE_INT) 1 << (prec - 1)))) + { + /* Value is negative: + set to 1 all the bits that are outside this type's precision. */ + if (prec > HOST_BITS_PER_WIDE_INT) + { + TREE_INT_CST_HIGH (t) + |= ((HOST_WIDE_INT) (-1) << (prec - HOST_BITS_PER_WIDE_INT)); + } + else + { + TREE_INT_CST_HIGH (t) = -1; + if (prec < HOST_BITS_PER_WIDE_INT) + TREE_INT_CST_LOW (t) |= ((HOST_WIDE_INT) (-1) << prec); + } + } + + /* Yield nonzero if signed overflow occurred. */ + return + ((overflow | (low ^ TREE_INT_CST_LOW (t)) | (high ^ TREE_INT_CST_HIGH (t))) + != 0); +} + +/* Add two doubleword integers with doubleword result. + Each argument is given as two `HOST_WIDE_INT' pieces. + One argument is L1 and H1; the other, L2 and H2. + The value is stored as two `HOST_WIDE_INT' pieces in *LV and *HV. + We use the 8-shorts representation internally. */ + +int +add_double (l1, h1, l2, h2, lv, hv) + HOST_WIDE_INT l1, h1, l2, h2; + HOST_WIDE_INT *lv, *hv; +{ + short arg1[MAX_SHORTS]; + short arg2[MAX_SHORTS]; + register int carry = 0; + register int i; + + encode (arg1, l1, h1); + encode (arg2, l2, h2); + + for (i = 0; i < MAX_SHORTS; i++) + { + carry += arg1[i] + arg2[i]; + arg1[i] = carry & 0xff; + carry >>= 8; + } + + decode (arg1, lv, hv); + return overflow_sum_sign (h1, h2, *hv); +} + +/* Negate a doubleword integer with doubleword result. + Return nonzero if the operation overflows, assuming it's signed. + The argument is given as two `HOST_WIDE_INT' pieces in L1 and H1. + The value is stored as two `HOST_WIDE_INT' pieces in *LV and *HV. + We use the 8-shorts representation internally. */ + +int +neg_double (l1, h1, lv, hv) + HOST_WIDE_INT l1, h1; + HOST_WIDE_INT *lv, *hv; +{ + if (l1 == 0) + { + *lv = 0; + *hv = - h1; + return (*hv & h1) < 0; + } + else + { + *lv = - l1; + *hv = ~ h1; + return 0; + } +} + +/* Multiply two doubleword integers with doubleword result. + Return nonzero if the operation overflows, assuming it's signed. + Each argument is given as two `HOST_WIDE_INT' pieces. + One argument is L1 and H1; the other, L2 and H2. + The value is stored as two `HOST_WIDE_INT' pieces in *LV and *HV. + We use the 8-shorts representation internally. */ + +int +mul_double (l1, h1, l2, h2, lv, hv) + HOST_WIDE_INT l1, h1, l2, h2; + HOST_WIDE_INT *lv, *hv; +{ + short arg1[MAX_SHORTS]; + short arg2[MAX_SHORTS]; + short prod[MAX_SHORTS * 2]; + register int carry = 0; + register int i, j, k; + HOST_WIDE_INT toplow, tophigh, neglow, neghigh; + + /* These cases are used extensively, arising from pointer combinations. */ + if (h2 == 0) + { + if (l2 == 2) + { + int overflow = left_shift_overflows (h1, 1); + unsigned HOST_WIDE_INT temp = l1 + l1; + *hv = (h1 << 1) + (temp < l1); + *lv = temp; + return overflow; + } + if (l2 == 4) + { + int overflow = left_shift_overflows (h1, 2); + unsigned HOST_WIDE_INT temp = l1 + l1; + h1 = (h1 << 2) + ((temp < l1) << 1); + l1 = temp; + temp += temp; + h1 += (temp < l1); + *lv = temp; + *hv = h1; + return overflow; + } + if (l2 == 8) + { + int overflow = left_shift_overflows (h1, 3); + unsigned HOST_WIDE_INT temp = l1 + l1; + h1 = (h1 << 3) + ((temp < l1) << 2); + l1 = temp; + temp += temp; + h1 += (temp < l1) << 1; + l1 = temp; + temp += temp; + h1 += (temp < l1); + *lv = temp; + *hv = h1; + return overflow; + } + } + + encode (arg1, l1, h1); + encode (arg2, l2, h2); + + bzero (prod, sizeof prod); + + for (i = 0; i < MAX_SHORTS; i++) + for (j = 0; j < MAX_SHORTS; j++) + { + k = i + j; + carry = arg1[i] * arg2[j]; + while (carry) + { + carry += prod[k]; + prod[k] = carry & 0xff; + carry >>= 8; + k++; + } + } + + decode (prod, lv, hv); /* This ignores + prod[MAX_SHORTS] -> prod[MAX_SHORTS*2-1] */ + + /* Check for overflow by calculating the top half of the answer in full; + it should agree with the low half's sign bit. */ + decode (prod+MAX_SHORTS, &toplow, &tophigh); + if (h1 < 0) + { + neg_double (l2, h2, &neglow, &neghigh); + add_double (neglow, neghigh, toplow, tophigh, &toplow, &tophigh); + } + if (h2 < 0) + { + neg_double (l1, h1, &neglow, &neghigh); + add_double (neglow, neghigh, toplow, tophigh, &toplow, &tophigh); + } + return (*hv < 0 ? ~(toplow & tophigh) : toplow | tophigh) != 0; +} + +/* Shift the doubleword integer in L1, H1 left by COUNT places + keeping only PREC bits of result. + Shift right if COUNT is negative. + ARITH nonzero specifies arithmetic shifting; otherwise use logical shift. + Store the value as two `HOST_WIDE_INT' pieces in *LV and *HV. */ + +void +lshift_double (l1, h1, count, prec, lv, hv, arith) + HOST_WIDE_INT l1, h1; + int count, prec; + HOST_WIDE_INT *lv, *hv; + int arith; +{ + short arg1[MAX_SHORTS]; + register int i; + register int carry; + + if (count < 0) + { + rshift_double (l1, h1, - count, prec, lv, hv, arith); + return; + } + + encode (arg1, l1, h1); + + if (count > prec) + count = prec; + + while (count > 0) + { + carry = 0; + for (i = 0; i < MAX_SHORTS; i++) + { + carry += arg1[i] << 1; + arg1[i] = carry & 0xff; + carry >>= 8; + } + count--; + } + + decode (arg1, lv, hv); +} + +/* Shift the doubleword integer in L1, H1 right by COUNT places + keeping only PREC bits of result. COUNT must be positive. + ARITH nonzero specifies arithmetic shifting; otherwise use logical shift. + Store the value as two `HOST_WIDE_INT' pieces in *LV and *HV. */ + +void +rshift_double (l1, h1, count, prec, lv, hv, arith) + HOST_WIDE_INT l1, h1, count, prec; + HOST_WIDE_INT *lv, *hv; + int arith; +{ + short arg1[MAX_SHORTS]; + register int i; + register int carry; + + encode (arg1, l1, h1); + + if (count > prec) + count = prec; + + while (count > 0) + { + carry = arith && arg1[7] >> 7; + for (i = MAX_SHORTS - 1; i >= 0; i--) + { + carry <<= 8; + carry += arg1[i]; + arg1[i] = (carry >> 1) & 0xff; + } + count--; + } + + decode (arg1, lv, hv); +} + +/* Rotate the doubldword integer in L1, H1 left by COUNT places + keeping only PREC bits of result. + Rotate right if COUNT is negative. + Store the value as two `HOST_WIDE_INT' pieces in *LV and *HV. */ + +void +lrotate_double (l1, h1, count, prec, lv, hv) + HOST_WIDE_INT l1, h1, count, prec; + HOST_WIDE_INT *lv, *hv; +{ + short arg1[MAX_SHORTS]; + register int i; + register int carry; + + if (count < 0) + { + rrotate_double (l1, h1, - count, prec, lv, hv); + return; + } + + encode (arg1, l1, h1); + + if (count > prec) + count = prec; + + carry = arg1[MAX_SHORTS - 1] >> 7; + while (count > 0) + { + for (i = 0; i < MAX_SHORTS; i++) + { + carry += arg1[i] << 1; + arg1[i] = carry & 0xff; + carry >>= 8; + } + count--; + } + + decode (arg1, lv, hv); +} + +/* Rotate the doubleword integer in L1, H1 left by COUNT places + keeping only PREC bits of result. COUNT must be positive. + Store the value as two `HOST_WIDE_INT' pieces in *LV and *HV. */ + +void +rrotate_double (l1, h1, count, prec, lv, hv) + HOST_WIDE_INT l1, h1, count, prec; + HOST_WIDE_INT *lv, *hv; +{ + short arg1[MAX_SHORTS]; + register int i; + register int carry; + + encode (arg1, l1, h1); + + if (count > prec) + count = prec; + + carry = arg1[0] & 1; + while (count > 0) + { + for (i = MAX_SHORTS - 1; i >= 0; i--) + { + carry <<= 8; + carry += arg1[i]; + arg1[i] = (carry >> 1) & 0xff; + } + count--; + } + + decode (arg1, lv, hv); +} + +/* Divide doubleword integer LNUM, HNUM by doubleword integer LDEN, HDEN + for a quotient (stored in *LQUO, *HQUO) and remainder (in *LREM, *HREM). + CODE is a tree code for a kind of division, one of + TRUNC_DIV_EXPR, FLOOR_DIV_EXPR, CEIL_DIV_EXPR, ROUND_DIV_EXPR + or EXACT_DIV_EXPR + It controls how the quotient is rounded to a integer. + Return nonzero if the operation overflows. + UNS nonzero says do unsigned division. */ + +static int +div_and_round_double (code, uns, + lnum_orig, hnum_orig, lden_orig, hden_orig, + lquo, hquo, lrem, hrem) + enum tree_code code; + int uns; + HOST_WIDE_INT lnum_orig, hnum_orig; /* num == numerator == dividend */ + HOST_WIDE_INT lden_orig, hden_orig; /* den == denominator == divisor */ + HOST_WIDE_INT *lquo, *hquo, *lrem, *hrem; +{ + int quo_neg = 0; + short num[MAX_SHORTS + 1]; /* extra element for scaling. */ + short den[MAX_SHORTS], quo[MAX_SHORTS]; + register int i, j, work; + register int carry = 0; + HOST_WIDE_INT lnum = lnum_orig; + HOST_WIDE_INT hnum = hnum_orig; + HOST_WIDE_INT lden = lden_orig; + HOST_WIDE_INT hden = hden_orig; + int overflow = 0; + + if ((hden == 0) && (lden == 0)) + abort (); + + /* calculate quotient sign and convert operands to unsigned. */ + if (!uns) + { + if (hnum < 0) + { + quo_neg = ~ quo_neg; + /* (minimum integer) / (-1) is the only overflow case. */ + if (neg_double (lnum, hnum, &lnum, &hnum) && (lden & hden) == -1) + overflow = 1; + } + if (hden < 0) + { + quo_neg = ~ quo_neg; + neg_double (lden, hden, &lden, &hden); + } + } + + if (hnum == 0 && hden == 0) + { /* single precision */ + *hquo = *hrem = 0; + /* This unsigned division rounds toward zero. */ + *lquo = lnum / (unsigned HOST_WIDE_INT) lden; + goto finish_up; + } + + if (hnum == 0) + { /* trivial case: dividend < divisor */ + /* hden != 0 already checked. */ + *hquo = *lquo = 0; + *hrem = hnum; + *lrem = lnum; + goto finish_up; + } + + bzero (quo, sizeof quo); + + bzero (num, sizeof num); /* to zero 9th element */ + bzero (den, sizeof den); + + encode (num, lnum, hnum); + encode (den, lden, hden); + + /* This code requires more than just hden == 0. + We also have to require that we don't need more than three bytes + to hold CARRY. If we ever did need four bytes to hold it, we + would lose part of it when computing WORK on the next round. */ + if (hden == 0 && (((unsigned HOST_WIDE_INT) lden << 8) >> 8) == lden) + { /* simpler algorithm */ + /* hnum != 0 already checked. */ + for (i = MAX_SHORTS - 1; i >= 0; i--) + { + work = num[i] + (carry << 8); + quo[i] = work / (unsigned HOST_WIDE_INT) lden; + carry = work % (unsigned HOST_WIDE_INT) lden; + } + } + else { /* full double precision, + with thanks to Don Knuth's + "Seminumerical Algorithms". */ +#define BASE 256 + int quo_est, scale, num_hi_sig, den_hi_sig, quo_hi_sig; + + /* Find the highest non-zero divisor digit. */ + for (i = MAX_SHORTS - 1; ; i--) + if (den[i] != 0) { + den_hi_sig = i; + break; + } + for (i = MAX_SHORTS - 1; ; i--) + if (num[i] != 0) { + num_hi_sig = i; + break; + } + quo_hi_sig = num_hi_sig - den_hi_sig + 1; + + /* Insure that the first digit of the divisor is at least BASE/2. + This is required by the quotient digit estimation algorithm. */ + + scale = BASE / (den[den_hi_sig] + 1); + if (scale > 1) { /* scale divisor and dividend */ + carry = 0; + for (i = 0; i <= MAX_SHORTS - 1; i++) { + work = (num[i] * scale) + carry; + num[i] = work & 0xff; + carry = work >> 8; + if (num[i] != 0) num_hi_sig = i; + } + carry = 0; + for (i = 0; i <= MAX_SHORTS - 1; i++) { + work = (den[i] * scale) + carry; + den[i] = work & 0xff; + carry = work >> 8; + if (den[i] != 0) den_hi_sig = i; + } + } + + /* Main loop */ + for (i = quo_hi_sig; i > 0; i--) { + /* guess the next quotient digit, quo_est, by dividing the first + two remaining dividend digits by the high order quotient digit. + quo_est is never low and is at most 2 high. */ + + int num_hi; /* index of highest remaining dividend digit */ + + num_hi = i + den_hi_sig; + + work = (num[num_hi] * BASE) + (num_hi > 0 ? num[num_hi - 1] : 0); + if (num[num_hi] != den[den_hi_sig]) { + quo_est = work / den[den_hi_sig]; + } + else { + quo_est = BASE - 1; + } + + /* refine quo_est so it's usually correct, and at most one high. */ + while ((den[den_hi_sig - 1] * quo_est) + > (((work - (quo_est * den[den_hi_sig])) * BASE) + + ((num_hi - 1) > 0 ? num[num_hi - 2] : 0))) + quo_est--; + + /* Try QUO_EST as the quotient digit, by multiplying the + divisor by QUO_EST and subtracting from the remaining dividend. + Keep in mind that QUO_EST is the I - 1st digit. */ + + carry = 0; + + for (j = 0; j <= den_hi_sig; j++) + { + int digit; + + work = num[i + j - 1] - (quo_est * den[j]) + carry; + digit = work & 0xff; + carry = work >> 8; + if (digit < 0) + { + digit += BASE; + carry--; + } + num[i + j - 1] = digit; + } + + /* if quo_est was high by one, then num[i] went negative and + we need to correct things. */ + + if (num[num_hi] < 0) + { + quo_est--; + carry = 0; /* add divisor back in */ + for (j = 0; j <= den_hi_sig; j++) + { + work = num[i + j - 1] + den[j] + carry; + if (work > BASE) + { + work -= BASE; + carry = 1; + } + else + { + carry = 0; + } + num[i + j - 1] = work; + } + num [num_hi] += carry; + } + + /* store the quotient digit. */ + quo[i - 1] = quo_est; + } + } + + decode (quo, lquo, hquo); + + finish_up: + /* if result is negative, make it so. */ + if (quo_neg) + neg_double (*lquo, *hquo, lquo, hquo); + + /* compute trial remainder: rem = num - (quo * den) */ + mul_double (*lquo, *hquo, lden_orig, hden_orig, lrem, hrem); + neg_double (*lrem, *hrem, lrem, hrem); + add_double (lnum_orig, hnum_orig, *lrem, *hrem, lrem, hrem); + + switch (code) + { + case TRUNC_DIV_EXPR: + case TRUNC_MOD_EXPR: /* round toward zero */ + case EXACT_DIV_EXPR: /* for this one, it shouldn't matter */ + return overflow; + + case FLOOR_DIV_EXPR: + case FLOOR_MOD_EXPR: /* round toward negative infinity */ + if (quo_neg && (*lrem != 0 || *hrem != 0)) /* ratio < 0 && rem != 0 */ + { + /* quo = quo - 1; */ + add_double (*lquo, *hquo, (HOST_WIDE_INT) -1, (HOST_WIDE_INT) -1, + lquo, hquo); + } + else return overflow; + break; + + case CEIL_DIV_EXPR: + case CEIL_MOD_EXPR: /* round toward positive infinity */ + if (!quo_neg && (*lrem != 0 || *hrem != 0)) /* ratio > 0 && rem != 0 */ + { + add_double (*lquo, *hquo, (HOST_WIDE_INT) 1, (HOST_WIDE_INT) 0, + lquo, hquo); + } + else return overflow; + break; + + case ROUND_DIV_EXPR: + case ROUND_MOD_EXPR: /* round to closest integer */ + { + HOST_WIDE_INT labs_rem = *lrem, habs_rem = *hrem; + HOST_WIDE_INT labs_den = lden, habs_den = hden, ltwice, htwice; + + /* get absolute values */ + if (*hrem < 0) neg_double (*lrem, *hrem, &labs_rem, &habs_rem); + if (hden < 0) neg_double (lden, hden, &labs_den, &habs_den); + + /* if (2 * abs (lrem) >= abs (lden)) */ + mul_double ((HOST_WIDE_INT) 2, (HOST_WIDE_INT) 0, + labs_rem, habs_rem, <wice, &htwice); + if (((unsigned HOST_WIDE_INT) habs_den + < (unsigned HOST_WIDE_INT) htwice) + || (((unsigned HOST_WIDE_INT) habs_den + == (unsigned HOST_WIDE_INT) htwice) + && ((HOST_WIDE_INT unsigned) labs_den + < (unsigned HOST_WIDE_INT) ltwice))) + { + if (*hquo < 0) + /* quo = quo - 1; */ + add_double (*lquo, *hquo, + (HOST_WIDE_INT) -1, (HOST_WIDE_INT) -1, lquo, hquo); + else + /* quo = quo + 1; */ + add_double (*lquo, *hquo, (HOST_WIDE_INT) 1, (HOST_WIDE_INT) 0, + lquo, hquo); + } + else return overflow; + } + break; + + default: + abort (); + } + + /* compute true remainder: rem = num - (quo * den) */ + mul_double (*lquo, *hquo, lden_orig, hden_orig, lrem, hrem); + neg_double (*lrem, *hrem, lrem, hrem); + add_double (lnum_orig, hnum_orig, *lrem, *hrem, lrem, hrem); + return overflow; +} + +#ifndef REAL_ARITHMETIC +/* Effectively truncate a real value to represent + the nearest possible value in a narrower mode. + The result is actually represented in the same data type as the argument, + but its value is usually different. */ + +REAL_VALUE_TYPE +real_value_truncate (mode, arg) + enum machine_mode mode; + REAL_VALUE_TYPE arg; +{ +#ifdef __STDC__ + /* Make sure the value is actually stored in memory before we turn off + the handler. */ + volatile +#endif + REAL_VALUE_TYPE value; + jmp_buf handler, old_handler; + int handled; + + if (setjmp (handler)) + { + error ("floating overflow"); + return dconst0; + } + handled = push_float_handler (handler, old_handler); + value = REAL_VALUE_TRUNCATE (mode, arg); + pop_float_handler (handled, old_handler); + return value; +} + +#if TARGET_FLOAT_FORMAT == IEEE_FLOAT_FORMAT + +/* Check for infinity in an IEEE double precision number. */ + +int +target_isinf (x) + REAL_VALUE_TYPE x; +{ + /* The IEEE 64-bit double format. */ + union { + REAL_VALUE_TYPE d; + struct { + unsigned sign : 1; + unsigned exponent : 11; + unsigned mantissa1 : 20; + unsigned mantissa2; + } little_endian; + struct { + unsigned mantissa2; + unsigned mantissa1 : 20; + unsigned exponent : 11; + unsigned sign : 1; + } big_endian; + } u; + + u.d = dconstm1; + if (u.big_endian.sign == 1) + { + u.d = x; + return (u.big_endian.exponent == 2047 + && u.big_endian.mantissa1 == 0 + && u.big_endian.mantissa2 == 0); + } + else + { + u.d = x; + return (u.little_endian.exponent == 2047 + && u.little_endian.mantissa1 == 0 + && u.little_endian.mantissa2 == 0); + } +} + +/* Check whether an IEEE double precision number is a NaN. */ + +int +target_isnan (x) + REAL_VALUE_TYPE x; +{ + /* The IEEE 64-bit double format. */ + union { + REAL_VALUE_TYPE d; + struct { + unsigned sign : 1; + unsigned exponent : 11; + unsigned mantissa1 : 20; + unsigned mantissa2; + } little_endian; + struct { + unsigned mantissa2; + unsigned mantissa1 : 20; + unsigned exponent : 11; + unsigned sign : 1; + } big_endian; + } u; + + u.d = dconstm1; + if (u.big_endian.sign == 1) + { + u.d = x; + return (u.big_endian.exponent == 2047 + && (u.big_endian.mantissa1 != 0 + || u.big_endian.mantissa2 != 0)); + } + else + { + u.d = x; + return (u.little_endian.exponent == 2047 + && (u.little_endian.mantissa1 != 0 + || u.little_endian.mantissa2 != 0)); + } +} + +/* Check for a negative IEEE double precision number. */ + +int +target_negative (x) + REAL_VALUE_TYPE x; +{ + /* The IEEE 64-bit double format. */ + union { + REAL_VALUE_TYPE d; + struct { + unsigned sign : 1; + unsigned exponent : 11; + unsigned mantissa1 : 20; + unsigned mantissa2; + } little_endian; + struct { + unsigned mantissa2; + unsigned mantissa1 : 20; + unsigned exponent : 11; + unsigned sign : 1; + } big_endian; + } u; + + u.d = dconstm1; + if (u.big_endian.sign == 1) + { + u.d = x; + return u.big_endian.sign; + } + else + { + u.d = x; + return u.little_endian.sign; + } +} +#else /* Target not IEEE */ + +/* Let's assume other float formats don't have infinity. + (This can be overridden by redefining REAL_VALUE_ISINF.) */ + +target_isinf (x) + REAL_VALUE_TYPE x; +{ + return 0; +} + +/* Let's assume other float formats don't have NaNs. + (This can be overridden by redefining REAL_VALUE_ISNAN.) */ + +target_isnan (x) + REAL_VALUE_TYPE x; +{ + return 0; +} + +/* Let's assume other float formats don't have minus zero. + (This can be overridden by redefining REAL_VALUE_NEGATIVE.) */ + +target_negative (x) + REAL_VALUE_TYPE x; +{ + return x < 0; +} +#endif /* Target not IEEE */ +#endif /* no REAL_ARITHMETIC */ + +/* Split a tree IN into a constant and a variable part + that could be combined with CODE to make IN. + CODE must be a commutative arithmetic operation. + Store the constant part into *CONP and the variable in &VARP. + Return 1 if this was done; zero means the tree IN did not decompose + this way. + + If CODE is PLUS_EXPR we also split trees that use MINUS_EXPR. + Therefore, we must tell the caller whether the variable part + was subtracted. We do this by storing 1 or -1 into *VARSIGNP. + The value stored is the coefficient for the variable term. + The constant term we return should always be added; + we negate it if necessary. */ + +static int +split_tree (in, code, varp, conp, varsignp) + tree in; + enum tree_code code; + tree *varp, *conp; + int *varsignp; +{ + register tree outtype = TREE_TYPE (in); + *varp = 0; + *conp = 0; + + /* Strip any conversions that don't change the machine mode. */ + while ((TREE_CODE (in) == NOP_EXPR + || TREE_CODE (in) == CONVERT_EXPR) + && (TYPE_MODE (TREE_TYPE (in)) + == TYPE_MODE (TREE_TYPE (TREE_OPERAND (in, 0))))) + in = TREE_OPERAND (in, 0); + + if (TREE_CODE (in) == code + || (! FLOAT_TYPE_P (TREE_TYPE (in)) + /* We can associate addition and subtraction together + (even though the C standard doesn't say so) + for integers because the value is not affected. + For reals, the value might be affected, so we can't. */ + && ((code == PLUS_EXPR && TREE_CODE (in) == MINUS_EXPR) + || (code == MINUS_EXPR && TREE_CODE (in) == PLUS_EXPR)))) + { + enum tree_code code = TREE_CODE (TREE_OPERAND (in, 0)); + if (code == INTEGER_CST) + { + *conp = TREE_OPERAND (in, 0); + *varp = TREE_OPERAND (in, 1); + if (TYPE_MODE (TREE_TYPE (*varp)) != TYPE_MODE (outtype) + && TREE_TYPE (*varp) != outtype) + *varp = convert (outtype, *varp); + *varsignp = (TREE_CODE (in) == MINUS_EXPR) ? -1 : 1; + return 1; + } + if (TREE_CONSTANT (TREE_OPERAND (in, 1))) + { + *conp = TREE_OPERAND (in, 1); + *varp = TREE_OPERAND (in, 0); + *varsignp = 1; + if (TYPE_MODE (TREE_TYPE (*varp)) != TYPE_MODE (outtype) + && TREE_TYPE (*varp) != outtype) + *varp = convert (outtype, *varp); + if (TREE_CODE (in) == MINUS_EXPR) + { + /* If operation is subtraction and constant is second, + must negate it to get an additive constant. + And this cannot be done unless it is a manifest constant. + It could also be the address of a static variable. + We cannot negate that, so give up. */ + if (TREE_CODE (*conp) == INTEGER_CST) + /* Subtracting from integer_zero_node loses for long long. */ + *conp = fold (build1 (NEGATE_EXPR, TREE_TYPE (*conp), *conp)); + else + return 0; + } + return 1; + } + if (TREE_CONSTANT (TREE_OPERAND (in, 0))) + { + *conp = TREE_OPERAND (in, 0); + *varp = TREE_OPERAND (in, 1); + if (TYPE_MODE (TREE_TYPE (*varp)) != TYPE_MODE (outtype) + && TREE_TYPE (*varp) != outtype) + *varp = convert (outtype, *varp); + *varsignp = (TREE_CODE (in) == MINUS_EXPR) ? -1 : 1; + return 1; + } + } + return 0; +} + +/* Combine two constants NUM and ARG2 under operation CODE + to produce a new constant. + We assume ARG1 and ARG2 have the same data type, + or at least are the same kind of constant and the same machine mode. + + If NOTRUNC is nonzero, do not truncate the result to fit the data type. */ + +static tree +const_binop (code, arg1, arg2, notrunc) + enum tree_code code; + register tree arg1, arg2; + int notrunc; +{ + if (TREE_CODE (arg1) == INTEGER_CST) + { + register HOST_WIDE_INT int1l = TREE_INT_CST_LOW (arg1); + register HOST_WIDE_INT int1h = TREE_INT_CST_HIGH (arg1); + HOST_WIDE_INT int2l = TREE_INT_CST_LOW (arg2); + HOST_WIDE_INT int2h = TREE_INT_CST_HIGH (arg2); + HOST_WIDE_INT low, hi; + HOST_WIDE_INT garbagel, garbageh; + register tree t; + int uns = TREE_UNSIGNED (TREE_TYPE (arg1)); + int overflow = 0; + + switch (code) + { + case BIT_IOR_EXPR: + t = build_int_2 (int1l | int2l, int1h | int2h); + break; + + case BIT_XOR_EXPR: + t = build_int_2 (int1l ^ int2l, int1h ^ int2h); + break; + + case BIT_AND_EXPR: + t = build_int_2 (int1l & int2l, int1h & int2h); + break; + + case BIT_ANDTC_EXPR: + t = build_int_2 (int1l & ~int2l, int1h & ~int2h); + break; + + case RSHIFT_EXPR: + int2l = - int2l; + case LSHIFT_EXPR: + /* It's unclear from the C standard whether shifts can overflow. + The following code ignores overflow; perhaps a C standard + interpretation ruling is needed. */ + lshift_double (int1l, int1h, int2l, + TYPE_PRECISION (TREE_TYPE (arg1)), + &low, &hi, + !uns); + t = build_int_2 (low, hi); + TREE_TYPE (t) = TREE_TYPE (arg1); + if (!notrunc) + force_fit_type (t, 0); + TREE_CONSTANT_OVERFLOW (t) + = TREE_CONSTANT_OVERFLOW (arg1) | TREE_CONSTANT_OVERFLOW (arg2); + return t; + + case RROTATE_EXPR: + int2l = - int2l; + case LROTATE_EXPR: + lrotate_double (int1l, int1h, int2l, + TYPE_PRECISION (TREE_TYPE (arg1)), + &low, &hi); + t = build_int_2 (low, hi); + break; + + case PLUS_EXPR: + if (int1h == 0) + { + int2l += int1l; + if ((unsigned HOST_WIDE_INT) int2l < int1l) + { + hi = int2h++; + overflow = int2h < hi; + } + t = build_int_2 (int2l, int2h); + break; + } + if (int2h == 0) + { + int1l += int2l; + if ((unsigned HOST_WIDE_INT) int1l < int2l) + { + hi = int1h++; + overflow = int1h < hi; + } + t = build_int_2 (int1l, int1h); + break; + } + overflow = add_double (int1l, int1h, int2l, int2h, &low, &hi); + t = build_int_2 (low, hi); + break; + + case MINUS_EXPR: + if (int2h == 0 && int2l == 0) + { + t = build_int_2 (int1l, int1h); + break; + } + neg_double (int2l, int2h, &low, &hi); + add_double (int1l, int1h, low, hi, &low, &hi); + overflow = overflow_sum_sign (hi, int2h, int1h); + t = build_int_2 (low, hi); + break; + + case MULT_EXPR: + /* Optimize simple cases. */ + if (int1h == 0) + { + unsigned HOST_WIDE_INT temp; + + switch (int1l) + { + case 0: + t = build_int_2 (0, 0); + goto got_it; + case 1: + t = build_int_2 (int2l, int2h); + goto got_it; + case 2: + overflow = left_shift_overflows (int2h, 1); + temp = int2l + int2l; + int2h = (int2h << 1) + (temp < int2l); + t = build_int_2 (temp, int2h); + goto got_it; +#if 0 /* This code can lose carries. */ + case 3: + temp = int2l + int2l + int2l; + int2h = int2h * 3 + (temp < int2l); + t = build_int_2 (temp, int2h); + goto got_it; +#endif + case 4: + overflow = left_shift_overflows (int2h, 2); + temp = int2l + int2l; + int2h = (int2h << 2) + ((temp < int2l) << 1); + int2l = temp; + temp += temp; + int2h += (temp < int2l); + t = build_int_2 (temp, int2h); + goto got_it; + case 8: + overflow = left_shift_overflows (int2h, 3); + temp = int2l + int2l; + int2h = (int2h << 3) + ((temp < int2l) << 2); + int2l = temp; + temp += temp; + int2h += (temp < int2l) << 1; + int2l = temp; + temp += temp; + int2h += (temp < int2l); + t = build_int_2 (temp, int2h); + goto got_it; + default: + break; + } + } + + if (int2h == 0) + { + if (int2l == 0) + { + t = build_int_2 (0, 0); + break; + } + if (int2l == 1) + { + t = build_int_2 (int1l, int1h); + break; + } + } + + overflow = mul_double (int1l, int1h, int2l, int2h, &low, &hi); + t = build_int_2 (low, hi); + break; + + case TRUNC_DIV_EXPR: + case FLOOR_DIV_EXPR: case CEIL_DIV_EXPR: + case EXACT_DIV_EXPR: + /* This is a shortcut for a common special case. + It reduces the number of tree nodes generated + and saves time. */ + if (int2h == 0 && int2l > 0 + && TREE_TYPE (arg1) == sizetype + && int1h == 0 && int1l >= 0) + { + if (code == CEIL_DIV_EXPR) + int1l += int2l-1; + return size_int (int1l / int2l); + } + case ROUND_DIV_EXPR: + if (int2h == 0 && int2l == 1) + { + t = build_int_2 (int1l, int1h); + break; + } + if (int1l == int2l && int1h == int2h) + { + if ((int1l | int1h) == 0) + abort (); + t = build_int_2 (1, 0); + break; + } + overflow = div_and_round_double (code, uns, + int1l, int1h, int2l, int2h, + &low, &hi, &garbagel, &garbageh); + t = build_int_2 (low, hi); + break; + + case TRUNC_MOD_EXPR: case ROUND_MOD_EXPR: + case FLOOR_MOD_EXPR: case CEIL_MOD_EXPR: + overflow = div_and_round_double (code, uns, + int1l, int1h, int2l, int2h, + &garbagel, &garbageh, &low, &hi); + t = build_int_2 (low, hi); + break; + + case MIN_EXPR: + case MAX_EXPR: + if (uns) + { + low = (((unsigned HOST_WIDE_INT) int1h + < (unsigned HOST_WIDE_INT) int2h) + || (((unsigned HOST_WIDE_INT) int1h + == (unsigned HOST_WIDE_INT) int2h) + && ((unsigned HOST_WIDE_INT) int1l + < (unsigned HOST_WIDE_INT) int2l))); + } + else + { + low = ((int1h < int2h) + || ((int1h == int2h) + && ((unsigned HOST_WIDE_INT) int1l + < (unsigned HOST_WIDE_INT) int2l))); + } + if (low == (code == MIN_EXPR)) + t = build_int_2 (int1l, int1h); + else + t = build_int_2 (int2l, int2h); + break; + + default: + abort (); + } + got_it: + TREE_TYPE (t) = TREE_TYPE (arg1); + TREE_CONSTANT_OVERFLOW (t) + = ((notrunc ? !uns && overflow : force_fit_type (t, overflow)) + | TREE_CONSTANT_OVERFLOW (arg1) + | TREE_CONSTANT_OVERFLOW (arg2)); + return t; + } +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + if (TREE_CODE (arg1) == REAL_CST) + { + REAL_VALUE_TYPE d1; + REAL_VALUE_TYPE d2; + REAL_VALUE_TYPE value; + tree t; + + d1 = TREE_REAL_CST (arg1); + d2 = TREE_REAL_CST (arg2); + if (setjmp (float_error)) + { + pedwarn ("floating overflow in constant expression"); + return build (code, TREE_TYPE (arg1), arg1, arg2); + } + set_float_handler (float_error); + +#ifdef REAL_ARITHMETIC + REAL_ARITHMETIC (value, code, d1, d2); +#else + switch (code) + { + case PLUS_EXPR: + value = d1 + d2; + break; + + case MINUS_EXPR: + value = d1 - d2; + break; + + case MULT_EXPR: + value = d1 * d2; + break; + + case RDIV_EXPR: +#ifndef REAL_INFINITY + if (d2 == 0) + abort (); +#endif + + value = d1 / d2; + break; + + case MIN_EXPR: + value = MIN (d1, d2); + break; + + case MAX_EXPR: + value = MAX (d1, d2); + break; + + default: + abort (); + } +#endif /* no REAL_ARITHMETIC */ + t = build_real (TREE_TYPE (arg1), + real_value_truncate (TYPE_MODE (TREE_TYPE (arg1)), value)); + set_float_handler (NULL_PTR); + return t; + } +#endif /* not REAL_IS_NOT_DOUBLE, or REAL_ARITHMETIC */ + if (TREE_CODE (arg1) == COMPLEX_CST) + { + register tree r1 = TREE_REALPART (arg1); + register tree i1 = TREE_IMAGPART (arg1); + register tree r2 = TREE_REALPART (arg2); + register tree i2 = TREE_IMAGPART (arg2); + register tree t; + + switch (code) + { + case PLUS_EXPR: + t = build_complex (const_binop (PLUS_EXPR, r1, r2, notrunc), + const_binop (PLUS_EXPR, i1, i2, notrunc)); + break; + + case MINUS_EXPR: + t = build_complex (const_binop (MINUS_EXPR, r1, r2, notrunc), + const_binop (MINUS_EXPR, i1, i2, notrunc)); + break; + + case MULT_EXPR: + t = build_complex (const_binop (MINUS_EXPR, + const_binop (MULT_EXPR, + r1, r2, notrunc), + const_binop (MULT_EXPR, + i1, i2, notrunc), + notrunc), + const_binop (PLUS_EXPR, + const_binop (MULT_EXPR, + r1, i2, notrunc), + const_binop (MULT_EXPR, + i1, r2, notrunc), + notrunc)); + break; + + case RDIV_EXPR: + { + register tree magsquared + = const_binop (PLUS_EXPR, + const_binop (MULT_EXPR, r2, r2, notrunc), + const_binop (MULT_EXPR, i2, i2, notrunc), + notrunc); + t = build_complex (const_binop (RDIV_EXPR, + const_binop (PLUS_EXPR, + const_binop (MULT_EXPR, r1, r2, notrunc), + const_binop (MULT_EXPR, i1, i2, notrunc), + notrunc), + magsquared, notrunc), + const_binop (RDIV_EXPR, + const_binop (MINUS_EXPR, + const_binop (MULT_EXPR, i1, r2, notrunc), + const_binop (MULT_EXPR, r1, i2, notrunc), + notrunc), + magsquared, notrunc)); + } + break; + + default: + abort (); + } + TREE_TYPE (t) = TREE_TYPE (arg1); + return t; + } + return 0; +} + +/* Return an INTEGER_CST with value V and type from `sizetype'. */ + +tree +size_int (number) + unsigned int number; +{ + register tree t; + /* Type-size nodes already made for small sizes. */ + static tree size_table[2*HOST_BITS_PER_WIDE_INT + 1]; + + if (number < 2*HOST_BITS_PER_WIDE_INT + 1 + && size_table[number] != 0) + return size_table[number]; + if (number < 2*HOST_BITS_PER_WIDE_INT + 1) + { + push_obstacks_nochange (); + /* Make this a permanent node. */ + end_temporary_allocation (); + t = build_int_2 (number, 0); + TREE_TYPE (t) = sizetype; + size_table[number] = t; + pop_obstacks (); + } + else + { + t = build_int_2 (number, 0); + TREE_TYPE (t) = sizetype; + } + return t; +} + +/* Combine operands OP1 and OP2 with arithmetic operation CODE. + CODE is a tree code. Data type is taken from `sizetype', + If the operands are constant, so is the result. */ + +tree +size_binop (code, arg0, arg1) + enum tree_code code; + tree arg0, arg1; +{ + /* Handle the special case of two integer constants faster. */ + if (TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST) + { + /* And some specific cases even faster than that. */ + if (code == PLUS_EXPR + && TREE_INT_CST_LOW (arg0) == 0 + && TREE_INT_CST_HIGH (arg0) == 0) + return arg1; + if (code == MINUS_EXPR + && TREE_INT_CST_LOW (arg1) == 0 + && TREE_INT_CST_HIGH (arg1) == 0) + return arg0; + if (code == MULT_EXPR + && TREE_INT_CST_LOW (arg0) == 1 + && TREE_INT_CST_HIGH (arg0) == 0) + return arg1; + /* Handle general case of two integer constants. */ + return const_binop (code, arg0, arg1, 1); + } + + if (arg0 == error_mark_node || arg1 == error_mark_node) + return error_mark_node; + + return fold (build (code, sizetype, arg0, arg1)); +} + +/* Given T, a tree representing type conversion of ARG1, a constant, + return a constant tree representing the result of conversion. */ + +static tree +fold_convert (t, arg1) + register tree t; + register tree arg1; +{ + register tree type = TREE_TYPE (t); + + if (TREE_CODE (type) == POINTER_TYPE || INTEGRAL_TYPE_P (type)) + { + if (TREE_CODE (arg1) == INTEGER_CST) + { + /* Given an integer constant, make new constant with new type, + appropriately sign-extended or truncated. */ + t = build_int_2 (TREE_INT_CST_LOW (arg1), + TREE_INT_CST_HIGH (arg1)); + TREE_TYPE (t) = type; + /* Indicate an overflow if (1) ARG1 already overflowed, + or (2) ARG1 is a too-large unsigned value and T is signed, + or (3) force_fit_type indicates an overflow. + force_fit_type can't detect (2), since it sees only T's type. */ + TREE_CONSTANT_OVERFLOW (t) = + (TREE_CONSTANT_OVERFLOW (arg1) + | (TREE_INT_CST_HIGH (arg1) < 0 + & TREE_UNSIGNED (type) < TREE_UNSIGNED (TREE_TYPE (arg1))) + | force_fit_type (t, 0)); + } +#if !defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + else if (TREE_CODE (arg1) == REAL_CST) + { + REAL_VALUE_TYPE l, x, u; + + l = real_value_from_int_cst (TYPE_MIN_VALUE (type)); + x = TREE_REAL_CST (arg1); + u = real_value_from_int_cst (TYPE_MAX_VALUE (type)); + + /* See if X will be in range after truncation towards 0. + To compensate for truncation, move the bounds away from 0, + but reject if X exactly equals the adjusted bounds. */ +#ifdef REAL_ARITHMETIC + REAL_ARITHMETIC (l, MINUS_EXPR, l, dconst1); + REAL_ARITHMETIC (u, PLUS_EXPR, u, dconst1); +#else + l--; + u++; +#endif + if (! (REAL_VALUES_LESS (l, x) && REAL_VALUES_LESS (x, u))) + { + pedwarn ("real constant out of range for integer conversion"); + return t; + } +#ifndef REAL_ARITHMETIC + { + REAL_VALUE_TYPE d; + HOST_WIDE_INT low, high; + HOST_WIDE_INT half_word + = (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2); + + d = TREE_REAL_CST (arg1); + if (d < 0) + d = -d; + + high = (HOST_WIDE_INT) (d / half_word / half_word); + d -= (REAL_VALUE_TYPE) high * half_word * half_word; + if (d >= (REAL_VALUE_TYPE) half_word * half_word / 2) + { + low = d - (REAL_VALUE_TYPE) half_word * half_word / 2; + low |= (HOST_WIDE_INT) -1 << (HOST_BITS_PER_WIDE_INT - 1); + } + else + low = (HOST_WIDE_INT) d; + if (TREE_REAL_CST (arg1) < 0) + neg_double (low, high, &low, &high); + t = build_int_2 (low, high); + } +#else + { + HOST_WIDE_INT low, high; + REAL_VALUE_TO_INT (&low, &high, (TREE_REAL_CST (arg1))); + t = build_int_2 (low, high); + } +#endif + TREE_TYPE (t) = type; + force_fit_type (t, 0); + } +#endif /* not REAL_IS_NOT_DOUBLE, or REAL_ARITHMETIC */ + TREE_TYPE (t) = type; + } + else if (TREE_CODE (type) == REAL_TYPE) + { +#if !defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + if (TREE_CODE (arg1) == INTEGER_CST) + return build_real_from_int_cst (type, arg1); +#endif /* not REAL_IS_NOT_DOUBLE, or REAL_ARITHMETIC */ + if (TREE_CODE (arg1) == REAL_CST) + { + if (setjmp (float_error)) + { + pedwarn ("floating overflow in constant expression"); + return t; + } + set_float_handler (float_error); + + t = build_real (type, real_value_truncate (TYPE_MODE (type), + TREE_REAL_CST (arg1))); + set_float_handler (NULL_PTR); + return t; + } + } + TREE_CONSTANT (t) = 1; + return t; +} + +/* Return an expr equal to X but certainly not valid as an lvalue. + Also make sure it is not valid as an null pointer constant. */ + +tree +non_lvalue (x) + tree x; +{ + tree result; + + /* These things are certainly not lvalues. */ + if (TREE_CODE (x) == NON_LVALUE_EXPR + || TREE_CODE (x) == INTEGER_CST + || TREE_CODE (x) == REAL_CST + || TREE_CODE (x) == STRING_CST + || TREE_CODE (x) == ADDR_EXPR) + { + if (TREE_CODE (x) == INTEGER_CST && integer_zerop (x)) + { + /* Use NOP_EXPR instead of NON_LVALUE_EXPR + so convert_for_assignment won't strip it. + This is so this 0 won't be treated as a null pointer constant. */ + result = build1 (NOP_EXPR, TREE_TYPE (x), x); + TREE_CONSTANT (result) = TREE_CONSTANT (x); + return result; + } + return x; + } + + result = build1 (NON_LVALUE_EXPR, TREE_TYPE (x), x); + TREE_CONSTANT (result) = TREE_CONSTANT (x); + return result; +} + +/* Given a tree comparison code, return the code that is the logical inverse + of the given code. It is not safe to do this for floating-point + comparisons, except for NE_EXPR and EQ_EXPR. */ + +static enum tree_code +invert_tree_comparison (code) + enum tree_code code; +{ + switch (code) + { + case EQ_EXPR: + return NE_EXPR; + case NE_EXPR: + return EQ_EXPR; + case GT_EXPR: + return LE_EXPR; + case GE_EXPR: + return LT_EXPR; + case LT_EXPR: + return GE_EXPR; + case LE_EXPR: + return GT_EXPR; + default: + abort (); + } +} + +/* Similar, but return the comparison that results if the operands are + swapped. This is safe for floating-point. */ + +static enum tree_code +swap_tree_comparison (code) + enum tree_code code; +{ + switch (code) + { + case EQ_EXPR: + case NE_EXPR: + return code; + case GT_EXPR: + return LT_EXPR; + case GE_EXPR: + return LE_EXPR; + case LT_EXPR: + return GT_EXPR; + case LE_EXPR: + return GE_EXPR; + default: + abort (); + } +} + +/* Return nonzero if two operands are necessarily equal. + If ONLY_CONST is non-zero, only return non-zero for constants. + This function tests whether the operands are indistinguishable; + it does not test whether they are equal using C's == operation. + The distinction is important for IEEE floating point, because + (1) -0.0 and 0.0 are distinguishable, but -0.0==0.0, and + (2) two NaNs may be indistinguishable, but NaN!=NaN. */ + +int +operand_equal_p (arg0, arg1, only_const) + tree arg0, arg1; + int only_const; +{ + /* If both types don't have the same signedness, then we can't consider + them equal. We must check this before the STRIP_NOPS calls + because they may change the signedness of the arguments. */ + if (TREE_UNSIGNED (TREE_TYPE (arg0)) != TREE_UNSIGNED (TREE_TYPE (arg1))) + return 0; + + STRIP_NOPS (arg0); + STRIP_NOPS (arg1); + + /* If ARG0 and ARG1 are the same SAVE_EXPR, they are necessarily equal. + We don't care about side effects in that case because the SAVE_EXPR + takes care of that for us. */ + if (TREE_CODE (arg0) == SAVE_EXPR && arg0 == arg1) + return ! only_const; + + if (TREE_SIDE_EFFECTS (arg0) || TREE_SIDE_EFFECTS (arg1)) + return 0; + + if (TREE_CODE (arg0) == TREE_CODE (arg1) + && TREE_CODE (arg0) == ADDR_EXPR + && TREE_OPERAND (arg0, 0) == TREE_OPERAND (arg1, 0)) + return 1; + + if (TREE_CODE (arg0) == TREE_CODE (arg1) + && TREE_CODE (arg0) == INTEGER_CST + && TREE_INT_CST_LOW (arg0) == TREE_INT_CST_LOW (arg1) + && TREE_INT_CST_HIGH (arg0) == TREE_INT_CST_HIGH (arg1)) + return 1; + + /* Detect when real constants are equal. */ + if (TREE_CODE (arg0) == TREE_CODE (arg1) + && TREE_CODE (arg0) == REAL_CST) + return !bcmp (&TREE_REAL_CST (arg0), &TREE_REAL_CST (arg1), + sizeof (REAL_VALUE_TYPE)); + + if (only_const) + return 0; + + if (arg0 == arg1) + return 1; + + if (TREE_CODE (arg0) != TREE_CODE (arg1)) + return 0; + /* This is needed for conversions and for COMPONENT_REF. + Might as well play it safe and always test this. */ + if (TYPE_MODE (TREE_TYPE (arg0)) != TYPE_MODE (TREE_TYPE (arg1))) + return 0; + + switch (TREE_CODE_CLASS (TREE_CODE (arg0))) + { + case '1': + /* Two conversions are equal only if signedness and modes match. */ + if ((TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == CONVERT_EXPR) + && (TREE_UNSIGNED (TREE_TYPE (arg0)) + != TREE_UNSIGNED (TREE_TYPE (arg1)))) + return 0; + + return operand_equal_p (TREE_OPERAND (arg0, 0), + TREE_OPERAND (arg1, 0), 0); + + case '<': + case '2': + return (operand_equal_p (TREE_OPERAND (arg0, 0), + TREE_OPERAND (arg1, 0), 0) + && operand_equal_p (TREE_OPERAND (arg0, 1), + TREE_OPERAND (arg1, 1), 0)); + + case 'r': + switch (TREE_CODE (arg0)) + { + case INDIRECT_REF: + return operand_equal_p (TREE_OPERAND (arg0, 0), + TREE_OPERAND (arg1, 0), 0); + + case COMPONENT_REF: + case ARRAY_REF: + return (operand_equal_p (TREE_OPERAND (arg0, 0), + TREE_OPERAND (arg1, 0), 0) + && operand_equal_p (TREE_OPERAND (arg0, 1), + TREE_OPERAND (arg1, 1), 0)); + + case BIT_FIELD_REF: + return (operand_equal_p (TREE_OPERAND (arg0, 0), + TREE_OPERAND (arg1, 0), 0) + && operand_equal_p (TREE_OPERAND (arg0, 1), + TREE_OPERAND (arg1, 1), 0) + && operand_equal_p (TREE_OPERAND (arg0, 2), + TREE_OPERAND (arg1, 2), 0)); + } + break; + } + + return 0; +} + +/* Similar to operand_equal_p, but see if ARG0 might have been made by + shorten_compare from ARG1 when ARG1 was being compared with OTHER. + + When in doubt, return 0. */ + +static int +operand_equal_for_comparison_p (arg0, arg1, other) + tree arg0, arg1; + tree other; +{ + int unsignedp1, unsignedpo; + tree primarg1, primother; + int correct_width; + + if (operand_equal_p (arg0, arg1, 0)) + return 1; + + if (! INTEGRAL_TYPE_P (TREE_TYPE (arg0))) + return 0; + + /* Duplicate what shorten_compare does to ARG1 and see if that gives the + actual comparison operand, ARG0. + + First throw away any conversions to wider types + already present in the operands. */ + + primarg1 = get_narrower (arg1, &unsignedp1); + primother = get_narrower (other, &unsignedpo); + + correct_width = TYPE_PRECISION (TREE_TYPE (arg1)); + if (unsignedp1 == unsignedpo + && TYPE_PRECISION (TREE_TYPE (primarg1)) < correct_width + && TYPE_PRECISION (TREE_TYPE (primother)) < correct_width) + { + tree type = TREE_TYPE (arg0); + + /* Make sure shorter operand is extended the right way + to match the longer operand. */ + primarg1 = convert (signed_or_unsigned_type (unsignedp1, + TREE_TYPE (primarg1)), + primarg1); + + if (operand_equal_p (arg0, convert (type, primarg1), 0)) + return 1; + } + + return 0; +} + +/* See if ARG is an expression that is either a comparison or is performing + arithmetic on comparisons. The comparisons must only be comparing + two different values, which will be stored in *CVAL1 and *CVAL2; if + they are non-zero it means that some operands have already been found. + No variables may be used anywhere else in the expression except in the + comparisons. + + If this is true, return 1. Otherwise, return zero. */ + +static int +twoval_comparison_p (arg, cval1, cval2) + tree arg; + tree *cval1, *cval2; +{ + enum tree_code code = TREE_CODE (arg); + char class = TREE_CODE_CLASS (code); + + /* We can handle some of the 'e' cases here. */ + if (class == 'e' + && (code == TRUTH_NOT_EXPR + || (code == SAVE_EXPR && SAVE_EXPR_RTL (arg) == 0))) + class = '1'; + else if (class == 'e' + && (code == TRUTH_ANDIF_EXPR || code == TRUTH_ORIF_EXPR + || code == COMPOUND_EXPR)) + class = '2'; + + switch (class) + { + case '1': + return twoval_comparison_p (TREE_OPERAND (arg, 0), cval1, cval2); + + case '2': + return (twoval_comparison_p (TREE_OPERAND (arg, 0), cval1, cval2) + && twoval_comparison_p (TREE_OPERAND (arg, 1), cval1, cval2)); + + case 'c': + return 1; + + case 'e': + if (code == COND_EXPR) + return (twoval_comparison_p (TREE_OPERAND (arg, 0), cval1, cval2) + && twoval_comparison_p (TREE_OPERAND (arg, 1), cval1, cval2) + && twoval_comparison_p (TREE_OPERAND (arg, 2), + cval1, cval2)); + return 0; + + case '<': + /* First see if we can handle the first operand, then the second. For + the second operand, we know *CVAL1 can't be zero. It must be that + one side of the comparison is each of the values; test for the + case where this isn't true by failing if the two operands + are the same. */ + + if (operand_equal_p (TREE_OPERAND (arg, 0), + TREE_OPERAND (arg, 1), 0)) + return 0; + + if (*cval1 == 0) + *cval1 = TREE_OPERAND (arg, 0); + else if (operand_equal_p (*cval1, TREE_OPERAND (arg, 0), 0)) + ; + else if (*cval2 == 0) + *cval2 = TREE_OPERAND (arg, 0); + else if (operand_equal_p (*cval2, TREE_OPERAND (arg, 0), 0)) + ; + else + return 0; + + if (operand_equal_p (*cval1, TREE_OPERAND (arg, 1), 0)) + ; + else if (*cval2 == 0) + *cval2 = TREE_OPERAND (arg, 1); + else if (operand_equal_p (*cval2, TREE_OPERAND (arg, 1), 0)) + ; + else + return 0; + + return 1; + } + + return 0; +} + +/* ARG is a tree that is known to contain just arithmetic operations and + comparisons. Evaluate the operations in the tree substituting NEW0 for + any occurrence of OLD0 as an operand of a comparison and likewise for + NEW1 and OLD1. */ + +static tree +eval_subst (arg, old0, new0, old1, new1) + tree arg; + tree old0, new0, old1, new1; +{ + tree type = TREE_TYPE (arg); + enum tree_code code = TREE_CODE (arg); + char class = TREE_CODE_CLASS (code); + + /* We can handle some of the 'e' cases here. */ + if (class == 'e' && code == TRUTH_NOT_EXPR) + class = '1'; + else if (class == 'e' + && (code == TRUTH_ANDIF_EXPR || code == TRUTH_ORIF_EXPR)) + class = '2'; + + switch (class) + { + case '1': + return fold (build1 (code, type, + eval_subst (TREE_OPERAND (arg, 0), + old0, new0, old1, new1))); + + case '2': + return fold (build (code, type, + eval_subst (TREE_OPERAND (arg, 0), + old0, new0, old1, new1), + eval_subst (TREE_OPERAND (arg, 1), + old0, new0, old1, new1))); + + case 'e': + switch (code) + { + case SAVE_EXPR: + return eval_subst (TREE_OPERAND (arg, 0), old0, new0, old1, new1); + + case COMPOUND_EXPR: + return eval_subst (TREE_OPERAND (arg, 1), old0, new0, old1, new1); + + case COND_EXPR: + return fold (build (code, type, + eval_subst (TREE_OPERAND (arg, 0), + old0, new0, old1, new1), + eval_subst (TREE_OPERAND (arg, 1), + old0, new0, old1, new1), + eval_subst (TREE_OPERAND (arg, 2), + old0, new0, old1, new1))); + } + + case '<': + { + tree arg0 = TREE_OPERAND (arg, 0); + tree arg1 = TREE_OPERAND (arg, 1); + + /* We need to check both for exact equality and tree equality. The + former will be true if the operand has a side-effect. In that + case, we know the operand occurred exactly once. */ + + if (arg0 == old0 || operand_equal_p (arg0, old0, 0)) + arg0 = new0; + else if (arg0 == old1 || operand_equal_p (arg0, old1, 0)) + arg0 = new1; + + if (arg1 == old0 || operand_equal_p (arg1, old0, 0)) + arg1 = new0; + else if (arg1 == old1 || operand_equal_p (arg1, old1, 0)) + arg1 = new1; + + return fold (build (code, type, arg0, arg1)); + } + } + + return arg; +} + +/* Return a tree for the case when the result of an expression is RESULT + converted to TYPE and OMITTED was previously an operand of the expression + but is now not needed (e.g., we folded OMITTED * 0). + + If OMITTED has side effects, we must evaluate it. Otherwise, just do + the conversion of RESULT to TYPE. */ + +static tree +omit_one_operand (type, result, omitted) + tree type, result, omitted; +{ + tree t = convert (type, result); + + if (TREE_SIDE_EFFECTS (omitted)) + return build (COMPOUND_EXPR, type, omitted, t); + + return non_lvalue (t); +} + +/* Return a simplified tree node for the truth-negation of ARG. This + never alters ARG itself. We assume that ARG is an operation that + returns a truth value (0 or 1). */ + +tree +invert_truthvalue (arg) + tree arg; +{ + tree type = TREE_TYPE (arg); + enum tree_code code = TREE_CODE (arg); + + /* If this is a comparison, we can simply invert it, except for + floating-point non-equality comparisons, in which case we just + enclose a TRUTH_NOT_EXPR around what we have. */ + + if (TREE_CODE_CLASS (code) == '<') + { + if (FLOAT_TYPE_P (TREE_TYPE (TREE_OPERAND (arg, 0))) + && code != NE_EXPR && code != EQ_EXPR) + return build1 (TRUTH_NOT_EXPR, type, arg); + else + return build (invert_tree_comparison (code), type, + TREE_OPERAND (arg, 0), TREE_OPERAND (arg, 1)); + } + + switch (code) + { + case INTEGER_CST: + return convert (type, build_int_2 (TREE_INT_CST_LOW (arg) == 0 + && TREE_INT_CST_HIGH (arg) == 0, 0)); + + case TRUTH_AND_EXPR: + return build (TRUTH_OR_EXPR, type, + invert_truthvalue (TREE_OPERAND (arg, 0)), + invert_truthvalue (TREE_OPERAND (arg, 1))); + + case TRUTH_OR_EXPR: + return build (TRUTH_AND_EXPR, type, + invert_truthvalue (TREE_OPERAND (arg, 0)), + invert_truthvalue (TREE_OPERAND (arg, 1))); + + case TRUTH_XOR_EXPR: + /* Here we can invert either operand. We invert the first operand + unless the second operand is a TRUTH_NOT_EXPR in which case our + result is the XOR of the first operand with the inside of the + negation of the second operand. */ + + if (TREE_CODE (TREE_OPERAND (arg, 1)) == TRUTH_NOT_EXPR) + return build (TRUTH_XOR_EXPR, type, TREE_OPERAND (arg, 0), + TREE_OPERAND (TREE_OPERAND (arg, 1), 0)); + else + return build (TRUTH_XOR_EXPR, type, + invert_truthvalue (TREE_OPERAND (arg, 0)), + TREE_OPERAND (arg, 1)); + + case TRUTH_ANDIF_EXPR: + return build (TRUTH_ORIF_EXPR, type, + invert_truthvalue (TREE_OPERAND (arg, 0)), + invert_truthvalue (TREE_OPERAND (arg, 1))); + + case TRUTH_ORIF_EXPR: + return build (TRUTH_ANDIF_EXPR, type, + invert_truthvalue (TREE_OPERAND (arg, 0)), + invert_truthvalue (TREE_OPERAND (arg, 1))); + + case TRUTH_NOT_EXPR: + return TREE_OPERAND (arg, 0); + + case COND_EXPR: + return build (COND_EXPR, type, TREE_OPERAND (arg, 0), + invert_truthvalue (TREE_OPERAND (arg, 1)), + invert_truthvalue (TREE_OPERAND (arg, 2))); + + case COMPOUND_EXPR: + return build (COMPOUND_EXPR, type, TREE_OPERAND (arg, 0), + invert_truthvalue (TREE_OPERAND (arg, 1))); + + case NON_LVALUE_EXPR: + return invert_truthvalue (TREE_OPERAND (arg, 0)); + + case NOP_EXPR: + case CONVERT_EXPR: + case FLOAT_EXPR: + return build1 (TREE_CODE (arg), type, + invert_truthvalue (TREE_OPERAND (arg, 0))); + + case BIT_AND_EXPR: + if (! integer_onep (TREE_OPERAND (arg, 1))) + abort (); + return build (EQ_EXPR, type, arg, convert (type, integer_zero_node)); + } + + abort (); +} + +/* Given a bit-wise operation CODE applied to ARG0 and ARG1, see if both + operands are another bit-wise operation with a common input. If so, + distribute the bit operations to save an operation and possibly two if + constants are involved. For example, convert + (A | B) & (A | C) into A | (B & C) + Further simplification will occur if B and C are constants. + + If this optimization cannot be done, 0 will be returned. */ + +static tree +distribute_bit_expr (code, type, arg0, arg1) + enum tree_code code; + tree type; + tree arg0, arg1; +{ + tree common; + tree left, right; + + if (TREE_CODE (arg0) != TREE_CODE (arg1) + || TREE_CODE (arg0) == code + || (TREE_CODE (arg0) != BIT_AND_EXPR + && TREE_CODE (arg0) != BIT_IOR_EXPR)) + return 0; + + if (operand_equal_p (TREE_OPERAND (arg0, 0), TREE_OPERAND (arg1, 0), 0)) + { + common = TREE_OPERAND (arg0, 0); + left = TREE_OPERAND (arg0, 1); + right = TREE_OPERAND (arg1, 1); + } + else if (operand_equal_p (TREE_OPERAND (arg0, 0), TREE_OPERAND (arg1, 1), 0)) + { + common = TREE_OPERAND (arg0, 0); + left = TREE_OPERAND (arg0, 1); + right = TREE_OPERAND (arg1, 0); + } + else if (operand_equal_p (TREE_OPERAND (arg0, 1), TREE_OPERAND (arg1, 0), 0)) + { + common = TREE_OPERAND (arg0, 1); + left = TREE_OPERAND (arg0, 0); + right = TREE_OPERAND (arg1, 1); + } + else if (operand_equal_p (TREE_OPERAND (arg0, 1), TREE_OPERAND (arg1, 1), 0)) + { + common = TREE_OPERAND (arg0, 1); + left = TREE_OPERAND (arg0, 0); + right = TREE_OPERAND (arg1, 0); + } + else + return 0; + + return fold (build (TREE_CODE (arg0), type, common, + fold (build (code, type, left, right)))); +} + +/* Return a BIT_FIELD_REF of type TYPE to refer to BITSIZE bits of INNER + starting at BITPOS. The field is unsigned if UNSIGNEDP is non-zero. */ + +static tree +make_bit_field_ref (inner, type, bitsize, bitpos, unsignedp) + tree inner; + tree type; + int bitsize, bitpos; + int unsignedp; +{ + tree result = build (BIT_FIELD_REF, type, inner, + size_int (bitsize), size_int (bitpos)); + + TREE_UNSIGNED (result) = unsignedp; + + return result; +} + +/* Optimize a bit-field compare. + + There are two cases: First is a compare against a constant and the + second is a comparison of two items where the fields are at the same + bit position relative to the start of a chunk (byte, halfword, word) + large enough to contain it. In these cases we can avoid the shift + implicit in bitfield extractions. + + For constants, we emit a compare of the shifted constant with the + BIT_AND_EXPR of a mask and a byte, halfword, or word of the operand being + compared. For two fields at the same position, we do the ANDs with the + similar mask and compare the result of the ANDs. + + CODE is the comparison code, known to be either NE_EXPR or EQ_EXPR. + COMPARE_TYPE is the type of the comparison, and LHS and RHS + are the left and right operands of the comparison, respectively. + + If the optimization described above can be done, we return the resulting + tree. Otherwise we return zero. */ + +static tree +optimize_bit_field_compare (code, compare_type, lhs, rhs) + enum tree_code code; + tree compare_type; + tree lhs, rhs; +{ + int lbitpos, lbitsize, rbitpos, rbitsize; + int lnbitpos, lnbitsize, rnbitpos, rnbitsize; + tree type = TREE_TYPE (lhs); + tree signed_type, unsigned_type; + int const_p = TREE_CODE (rhs) == INTEGER_CST; + enum machine_mode lmode, rmode, lnmode, rnmode; + int lunsignedp, runsignedp; + int lvolatilep = 0, rvolatilep = 0; + tree linner, rinner; + tree mask; + tree offset; + + /* Get all the information about the extractions being done. If the bit size + if the same as the size of the underlying object, we aren't doing an + extraction at all and so can do nothing. */ + linner = get_inner_reference (lhs, &lbitsize, &lbitpos, &offset, &lmode, + &lunsignedp, &lvolatilep); + if (lbitsize == GET_MODE_BITSIZE (lmode) || lbitsize < 0 + || offset != 0) + return 0; + + if (!const_p) + { + /* If this is not a constant, we can only do something if bit positions, + sizes, and signedness are the same. */ + rinner = get_inner_reference (rhs, &rbitsize, &rbitpos, &offset, + &rmode, &runsignedp, &rvolatilep); + + if (lbitpos != rbitpos || lbitsize != rbitsize + || lunsignedp != runsignedp || offset != 0) + return 0; + } + + /* See if we can find a mode to refer to this field. We should be able to, + but fail if we can't. */ + lnmode = get_best_mode (lbitsize, lbitpos, + TYPE_ALIGN (TREE_TYPE (linner)), word_mode, + lvolatilep); + if (lnmode == VOIDmode) + return 0; + + /* Set signed and unsigned types of the precision of this mode for the + shifts below. */ + signed_type = type_for_mode (lnmode, 0); + unsigned_type = type_for_mode (lnmode, 1); + + if (! const_p) + { + rnmode = get_best_mode (rbitsize, rbitpos, + TYPE_ALIGN (TREE_TYPE (rinner)), word_mode, + rvolatilep); + if (rnmode == VOIDmode) + return 0; + } + + /* Compute the bit position and size for the new reference and our offset + within it. If the new reference is the same size as the original, we + won't optimize anything, so return zero. */ + lnbitsize = GET_MODE_BITSIZE (lnmode); + lnbitpos = lbitpos & ~ (lnbitsize - 1); + lbitpos -= lnbitpos; + if (lnbitsize == lbitsize) + return 0; + + if (! const_p) + { + rnbitsize = GET_MODE_BITSIZE (rnmode); + rnbitpos = rbitpos & ~ (rnbitsize - 1); + rbitpos -= rnbitpos; + if (rnbitsize == rbitsize) + return 0; + } + +#if BYTES_BIG_ENDIAN + lbitpos = lnbitsize - lbitsize - lbitpos; +#endif + + /* Make the mask to be used against the extracted field. */ + mask = build_int_2 (~0, ~0); + TREE_TYPE (mask) = unsigned_type; + force_fit_type (mask, 0); + mask = convert (unsigned_type, mask); + mask = const_binop (LSHIFT_EXPR, mask, size_int (lnbitsize - lbitsize), 0); + mask = const_binop (RSHIFT_EXPR, mask, + size_int (lnbitsize - lbitsize - lbitpos), 0); + + if (! const_p) + /* If not comparing with constant, just rework the comparison + and return. */ + return build (code, compare_type, + build (BIT_AND_EXPR, unsigned_type, + make_bit_field_ref (linner, unsigned_type, + lnbitsize, lnbitpos, 1), + mask), + build (BIT_AND_EXPR, unsigned_type, + make_bit_field_ref (rinner, unsigned_type, + rnbitsize, rnbitpos, 1), + mask)); + + /* Otherwise, we are handling the constant case. See if the constant is too + big for the field. Warn and return a tree of for 0 (false) if so. We do + this not only for its own sake, but to avoid having to test for this + error case below. If we didn't, we might generate wrong code. + + For unsigned fields, the constant shifted right by the field length should + be all zero. For signed fields, the high-order bits should agree with + the sign bit. */ + + if (lunsignedp) + { + if (! integer_zerop (const_binop (RSHIFT_EXPR, + convert (unsigned_type, rhs), + size_int (lbitsize), 0))) + { + warning ("comparison is always %s due to width of bitfield", + code == NE_EXPR ? "one" : "zero"); + return convert (compare_type, + (code == NE_EXPR + ? integer_one_node : integer_zero_node)); + } + } + else + { + tree tem = const_binop (RSHIFT_EXPR, convert (signed_type, rhs), + size_int (lbitsize - 1), 0); + if (! integer_zerop (tem) && ! integer_all_onesp (tem)) + { + warning ("comparison is always %s due to width of bitfield", + code == NE_EXPR ? "one" : "zero"); + return convert (compare_type, + (code == NE_EXPR + ? integer_one_node : integer_zero_node)); + } + } + + /* Single-bit compares should always be against zero. */ + if (lbitsize == 1 && ! integer_zerop (rhs)) + { + code = code == EQ_EXPR ? NE_EXPR : EQ_EXPR; + rhs = convert (type, integer_zero_node); + } + + /* Make a new bitfield reference, shift the constant over the + appropriate number of bits and mask it with the computed mask + (in case this was a signed field). If we changed it, make a new one. */ + lhs = make_bit_field_ref (linner, unsigned_type, lnbitsize, lnbitpos, 1); + + rhs = fold (const_binop (BIT_AND_EXPR, + const_binop (LSHIFT_EXPR, + convert (unsigned_type, rhs), + size_int (lbitpos), 0), + mask, 0)); + + return build (code, compare_type, + build (BIT_AND_EXPR, unsigned_type, lhs, mask), + rhs); +} + +/* Subroutine for fold_truthop: decode a field reference. + + If EXP is a comparison reference, we return the innermost reference. + + *PBITSIZE is set to the number of bits in the reference, *PBITPOS is + set to the starting bit number. + + If the innermost field can be completely contained in a mode-sized + unit, *PMODE is set to that mode. Otherwise, it is set to VOIDmode. + + *PVOLATILEP is set to 1 if the any expression encountered is volatile; + otherwise it is not changed. + + *PUNSIGNEDP is set to the signedness of the field. + + *PMASK is set to the mask used. This is either contained in a + BIT_AND_EXPR or derived from the width of the field. + + Return 0 if this is not a component reference or is one that we can't + do anything with. */ + +static tree +decode_field_reference (exp, pbitsize, pbitpos, pmode, punsignedp, + pvolatilep, pmask) + tree exp; + int *pbitsize, *pbitpos; + enum machine_mode *pmode; + int *punsignedp, *pvolatilep; + tree *pmask; +{ + tree mask = 0; + tree inner; + tree offset; + + /* All the optimizations using this function assume integer fields. + There are problems with FP fields since the type_for_size call + below can fail for, e.g., XFmode. */ + if (! INTEGRAL_TYPE_P (TREE_TYPE (exp))) + return 0; + + STRIP_NOPS (exp); + + if (TREE_CODE (exp) == BIT_AND_EXPR) + { + mask = TREE_OPERAND (exp, 1); + exp = TREE_OPERAND (exp, 0); + STRIP_NOPS (exp); STRIP_NOPS (mask); + if (TREE_CODE (mask) != INTEGER_CST) + return 0; + } + + if (TREE_CODE (exp) != COMPONENT_REF && TREE_CODE (exp) != ARRAY_REF + && TREE_CODE (exp) != BIT_FIELD_REF) + return 0; + + inner = get_inner_reference (exp, pbitsize, pbitpos, &offset, pmode, + punsignedp, pvolatilep); + if (*pbitsize < 0 || offset != 0) + return 0; + + if (mask == 0) + { + tree unsigned_type = type_for_size (*pbitsize, 1); + int precision = TYPE_PRECISION (unsigned_type); + + mask = build_int_2 (~0, ~0); + TREE_TYPE (mask) = unsigned_type; + force_fit_type (mask, 0); + mask = const_binop (LSHIFT_EXPR, mask, size_int (precision - *pbitsize), 0); + mask = const_binop (RSHIFT_EXPR, mask, size_int (precision - *pbitsize), 0); + } + + *pmask = mask; + return inner; +} + +/* Return non-zero if MASK represents a mask of SIZE ones in the low-order + bit positions. */ + +static int +all_ones_mask_p (mask, size) + tree mask; + int size; +{ + tree type = TREE_TYPE (mask); + int precision = TYPE_PRECISION (type); + tree tmask; + + tmask = build_int_2 (~0, ~0); + TREE_TYPE (tmask) = signed_type (type); + force_fit_type (tmask, 0); + return + operand_equal_p (mask, + const_binop (RSHIFT_EXPR, + const_binop (LSHIFT_EXPR, tmask, + size_int (precision - size), 0), + size_int (precision - size), 0), + 0); +} + +/* Subroutine for fold_truthop: determine if an operand is simple enough + to be evaluated unconditionally. */ + +#ifdef __GNUC__ +__inline +#endif +static int +simple_operand_p (exp) + tree exp; +{ + /* Strip any conversions that don't change the machine mode. */ + while ((TREE_CODE (exp) == NOP_EXPR + || TREE_CODE (exp) == CONVERT_EXPR) + && (TYPE_MODE (TREE_TYPE (exp)) + == TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))))) + exp = TREE_OPERAND (exp, 0); + + return (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c' + || (TREE_CODE_CLASS (TREE_CODE (exp)) == 'd' + && ! TREE_ADDRESSABLE (exp) + && ! TREE_THIS_VOLATILE (exp) + && ! DECL_NONLOCAL (exp) + /* Don't regard global variables as simple. They may be + allocated in ways unknown to the compiler (shared memory, + #pragma weak, etc). */ + && ! TREE_PUBLIC (exp) + && ! DECL_EXTERNAL (exp) + /* Loading a static variable is unduly expensive, but global + registers aren't expensive. */ + && (! TREE_STATIC (exp) || DECL_REGISTER (exp)))); +} + +/* Subroutine for fold_truthop: try to optimize a range test. + + For example, "i >= 2 && i =< 9" can be done as "(unsigned) (i - 2) <= 7". + + JCODE is the logical combination of the two terms. It is TRUTH_AND_EXPR + (representing TRUTH_ANDIF_EXPR and TRUTH_AND_EXPR) or TRUTH_OR_EXPR + (representing TRUTH_ORIF_EXPR and TRUTH_OR_EXPR). TYPE is the type of + the result. + + VAR is the value being tested. LO_CODE and HI_CODE are the comparison + operators comparing VAR to LO_CST and HI_CST. LO_CST is known to be no + larger than HI_CST (they may be equal). + + We return the simplified tree or 0 if no optimization is possible. */ + +tree +range_test (jcode, type, lo_code, hi_code, var, lo_cst, hi_cst) + enum tree_code jcode, lo_code, hi_code; + tree type, var, lo_cst, hi_cst; +{ + tree utype; + enum tree_code rcode; + + /* See if this is a range test and normalize the constant terms. */ + + if (jcode == TRUTH_AND_EXPR) + { + switch (lo_code) + { + case NE_EXPR: + /* See if we have VAR != CST && VAR != CST+1. */ + if (! (hi_code == NE_EXPR + && TREE_INT_CST_LOW (hi_cst) - TREE_INT_CST_LOW (lo_cst) == 1 + && tree_int_cst_equal (integer_one_node, + const_binop (MINUS_EXPR, + hi_cst, lo_cst, 0)))) + return 0; + + rcode = GT_EXPR; + break; + + case GT_EXPR: + case GE_EXPR: + if (hi_code == LT_EXPR) + hi_cst = const_binop (MINUS_EXPR, hi_cst, integer_one_node, 0); + else if (hi_code != LE_EXPR) + return 0; + + if (lo_code == GT_EXPR) + lo_cst = const_binop (PLUS_EXPR, lo_cst, integer_one_node, 0); + + /* We now have VAR >= LO_CST && VAR <= HI_CST. */ + rcode = LE_EXPR; + break; + + default: + return 0; + } + } + else + { + switch (lo_code) + { + case EQ_EXPR: + /* See if we have VAR == CST || VAR == CST+1. */ + if (! (hi_code == EQ_EXPR + && TREE_INT_CST_LOW (hi_cst) - TREE_INT_CST_LOW (lo_cst) == 1 + && tree_int_cst_equal (integer_one_node, + const_binop (MINUS_EXPR, + hi_cst, lo_cst, 0)))) + return 0; + + rcode = LE_EXPR; + break; + + case LE_EXPR: + case LT_EXPR: + if (hi_code == GE_EXPR) + hi_cst = const_binop (MINUS_EXPR, hi_cst, integer_one_node, 0); + else if (hi_code != GT_EXPR) + return 0; + + if (lo_code == LE_EXPR) + lo_cst = const_binop (PLUS_EXPR, lo_cst, integer_one_node, 0); + + /* We now have VAR < LO_CST || VAR > HI_CST. */ + rcode = GT_EXPR; + break; + + default: + return 0; + } + } + + /* When normalizing, it is possible to both increment the smaller constant + and decrement the larger constant. See if they are still ordered. */ + if (tree_int_cst_lt (hi_cst, lo_cst)) + return 0; + + /* Fail if VAR isn't an integer. */ + utype = TREE_TYPE (var); + if (! INTEGRAL_TYPE_P (utype)) + return 0; + + /* The range test is invalid if subtracting the two constants results + in overflow. This can happen in traditional mode. */ + if (! int_fits_type_p (hi_cst, TREE_TYPE (var)) + || ! int_fits_type_p (lo_cst, TREE_TYPE (var))) + return 0; + + if (! TREE_UNSIGNED (utype)) + { + utype = unsigned_type (utype); + var = convert (utype, var); + lo_cst = convert (utype, lo_cst); + hi_cst = convert (utype, hi_cst); + } + + return fold (convert (type, + build (rcode, utype, + build (MINUS_EXPR, utype, var, lo_cst), + const_binop (MINUS_EXPR, hi_cst, lo_cst, 0)))); +} + +/* Find ways of folding logical expressions of LHS and RHS: + Try to merge two comparisons to the same innermost item. + Look for range tests like "ch >= '0' && ch <= '9'". + Look for combinations of simple terms on machines with expensive branches + and evaluate the RHS unconditionally. + + For example, if we have p->a == 2 && p->b == 4 and we can make an + object large enough to span both A and B, we can do this with a comparison + against the object ANDed with the a mask. + + If we have p->a == q->a && p->b == q->b, we may be able to use bit masking + operations to do this with one comparison. + + We check for both normal comparisons and the BIT_AND_EXPRs made this by + function and the one above. + + CODE is the logical operation being done. It can be TRUTH_ANDIF_EXPR, + TRUTH_AND_EXPR, TRUTH_ORIF_EXPR, or TRUTH_OR_EXPR. + + TRUTH_TYPE is the type of the logical operand and LHS and RHS are its + two operands. + + We return the simplified tree or 0 if no optimization is possible. */ + +static tree +fold_truthop (code, truth_type, lhs, rhs) + enum tree_code code; + tree truth_type, lhs, rhs; +{ + /* If this is the "or" of two comparisons, we can do something if we + the comparisons are NE_EXPR. If this is the "and", we can do something + if the comparisons are EQ_EXPR. I.e., + (a->b == 2 && a->c == 4) can become (a->new == NEW). + + WANTED_CODE is this operation code. For single bit fields, we can + convert EQ_EXPR to NE_EXPR so we need not reject the "wrong" + comparison for one-bit fields. */ + + enum tree_code wanted_code; + enum tree_code lcode, rcode; + tree ll_arg, lr_arg, rl_arg, rr_arg; + tree ll_inner, lr_inner, rl_inner, rr_inner; + int ll_bitsize, ll_bitpos, lr_bitsize, lr_bitpos; + int rl_bitsize, rl_bitpos, rr_bitsize, rr_bitpos; + int xll_bitpos, xlr_bitpos, xrl_bitpos, xrr_bitpos; + int lnbitsize, lnbitpos, rnbitsize, rnbitpos; + int ll_unsignedp, lr_unsignedp, rl_unsignedp, rr_unsignedp; + enum machine_mode ll_mode, lr_mode, rl_mode, rr_mode; + enum machine_mode lnmode, rnmode; + tree ll_mask, lr_mask, rl_mask, rr_mask; + tree l_const, r_const; + tree type, result; + int first_bit, end_bit; + int volatilep; + + /* Start by getting the comparison codes and seeing if this looks like + a range test. Fail if anything is volatile. */ + + if (TREE_SIDE_EFFECTS (lhs) + || TREE_SIDE_EFFECTS (rhs)) + return 0; + + lcode = TREE_CODE (lhs); + rcode = TREE_CODE (rhs); + + if (TREE_CODE_CLASS (lcode) != '<' + || TREE_CODE_CLASS (rcode) != '<') + return 0; + + code = ((code == TRUTH_AND_EXPR || code == TRUTH_ANDIF_EXPR) + ? TRUTH_AND_EXPR : TRUTH_OR_EXPR); + + ll_arg = TREE_OPERAND (lhs, 0); + lr_arg = TREE_OPERAND (lhs, 1); + rl_arg = TREE_OPERAND (rhs, 0); + rr_arg = TREE_OPERAND (rhs, 1); + + if (TREE_CODE (lr_arg) == INTEGER_CST + && TREE_CODE (rr_arg) == INTEGER_CST + && operand_equal_p (ll_arg, rl_arg, 0)) + { + if (tree_int_cst_lt (lr_arg, rr_arg)) + result = range_test (code, truth_type, lcode, rcode, + ll_arg, lr_arg, rr_arg); + else + result = range_test (code, truth_type, rcode, lcode, + ll_arg, rr_arg, lr_arg); + + /* If this isn't a range test, it also isn't a comparison that + can be merged. However, it wins to evaluate the RHS unconditionally + on machines with expensive branches. */ + + if (result == 0 && BRANCH_COST >= 2) + { + if (TREE_CODE (ll_arg) != VAR_DECL + && TREE_CODE (ll_arg) != PARM_DECL) + { + /* Avoid evaluating the variable part twice. */ + ll_arg = save_expr (ll_arg); + lhs = build (lcode, TREE_TYPE (lhs), ll_arg, lr_arg); + rhs = build (rcode, TREE_TYPE (rhs), ll_arg, rr_arg); + } + return build (code, truth_type, lhs, rhs); + } + return result; + } + + /* If the RHS can be evaluated unconditionally and its operands are + simple, it wins to evaluate the RHS unconditionally on machines + with expensive branches. In this case, this isn't a comparison + that can be merged. */ + + /* @@ I'm not sure it wins on the m88110 to do this if the comparisons + are with zero (tmw). */ + + if (BRANCH_COST >= 2 + && INTEGRAL_TYPE_P (TREE_TYPE (rhs)) + && simple_operand_p (rl_arg) + && simple_operand_p (rr_arg)) + return build (code, truth_type, lhs, rhs); + + /* See if the comparisons can be merged. Then get all the parameters for + each side. */ + + if ((lcode != EQ_EXPR && lcode != NE_EXPR) + || (rcode != EQ_EXPR && rcode != NE_EXPR)) + return 0; + + volatilep = 0; + ll_inner = decode_field_reference (ll_arg, + &ll_bitsize, &ll_bitpos, &ll_mode, + &ll_unsignedp, &volatilep, &ll_mask); + lr_inner = decode_field_reference (lr_arg, + &lr_bitsize, &lr_bitpos, &lr_mode, + &lr_unsignedp, &volatilep, &lr_mask); + rl_inner = decode_field_reference (rl_arg, + &rl_bitsize, &rl_bitpos, &rl_mode, + &rl_unsignedp, &volatilep, &rl_mask); + rr_inner = decode_field_reference (rr_arg, + &rr_bitsize, &rr_bitpos, &rr_mode, + &rr_unsignedp, &volatilep, &rr_mask); + + /* It must be true that the inner operation on the lhs of each + comparison must be the same if we are to be able to do anything. + Then see if we have constants. If not, the same must be true for + the rhs's. */ + if (volatilep || ll_inner == 0 || rl_inner == 0 + || ! operand_equal_p (ll_inner, rl_inner, 0)) + return 0; + + if (TREE_CODE (lr_arg) == INTEGER_CST + && TREE_CODE (rr_arg) == INTEGER_CST) + l_const = lr_arg, r_const = rr_arg; + else if (lr_inner == 0 || rr_inner == 0 + || ! operand_equal_p (lr_inner, rr_inner, 0)) + return 0; + else + l_const = r_const = 0; + + /* If either comparison code is not correct for our logical operation, + fail. However, we can convert a one-bit comparison against zero into + the opposite comparison against that bit being set in the field. */ + + wanted_code = (code == TRUTH_AND_EXPR ? EQ_EXPR : NE_EXPR); + if (lcode != wanted_code) + { + if (l_const && integer_zerop (l_const) && integer_pow2p (ll_mask)) + l_const = ll_mask; + else + return 0; + } + + if (rcode != wanted_code) + { + if (r_const && integer_zerop (r_const) && integer_pow2p (rl_mask)) + r_const = rl_mask; + else + return 0; + } + + /* See if we can find a mode that contains both fields being compared on + the left. If we can't, fail. Otherwise, update all constants and masks + to be relative to a field of that size. */ + first_bit = MIN (ll_bitpos, rl_bitpos); + end_bit = MAX (ll_bitpos + ll_bitsize, rl_bitpos + rl_bitsize); + lnmode = get_best_mode (end_bit - first_bit, first_bit, + TYPE_ALIGN (TREE_TYPE (ll_inner)), word_mode, + volatilep); + if (lnmode == VOIDmode) + return 0; + + lnbitsize = GET_MODE_BITSIZE (lnmode); + lnbitpos = first_bit & ~ (lnbitsize - 1); + type = type_for_size (lnbitsize, 1); + xll_bitpos = ll_bitpos - lnbitpos, xrl_bitpos = rl_bitpos - lnbitpos; + +#if BYTES_BIG_ENDIAN + xll_bitpos = lnbitsize - xll_bitpos - ll_bitsize; + xrl_bitpos = lnbitsize - xrl_bitpos - rl_bitsize; +#endif + + ll_mask = const_binop (LSHIFT_EXPR, convert (type, ll_mask), + size_int (xll_bitpos), 0); + rl_mask = const_binop (LSHIFT_EXPR, convert (type, rl_mask), + size_int (xrl_bitpos), 0); + + /* Make sure the constants are interpreted as unsigned, so we + don't have sign bits outside the range of their type. */ + + if (l_const) + { + l_const = convert (unsigned_type (TREE_TYPE (l_const)), l_const); + l_const = const_binop (LSHIFT_EXPR, convert (type, l_const), + size_int (xll_bitpos), 0); + } + if (r_const) + { + r_const = convert (unsigned_type (TREE_TYPE (r_const)), r_const); + r_const = const_binop (LSHIFT_EXPR, convert (type, r_const), + size_int (xrl_bitpos), 0); + } + + /* If the right sides are not constant, do the same for it. Also, + disallow this optimization if a size or signedness mismatch occurs + between the left and right sides. */ + if (l_const == 0) + { + if (ll_bitsize != lr_bitsize || rl_bitsize != rr_bitsize + || ll_unsignedp != lr_unsignedp || rl_unsignedp != rr_unsignedp + /* Make sure the two fields on the right + correspond to the left without being swapped. */ + || ll_bitpos - rl_bitpos != lr_bitpos - rr_bitpos) + return 0; + + first_bit = MIN (lr_bitpos, rr_bitpos); + end_bit = MAX (lr_bitpos + lr_bitsize, rr_bitpos + rr_bitsize); + rnmode = get_best_mode (end_bit - first_bit, first_bit, + TYPE_ALIGN (TREE_TYPE (lr_inner)), word_mode, + volatilep); + if (rnmode == VOIDmode) + return 0; + + rnbitsize = GET_MODE_BITSIZE (rnmode); + rnbitpos = first_bit & ~ (rnbitsize - 1); + xlr_bitpos = lr_bitpos - rnbitpos, xrr_bitpos = rr_bitpos - rnbitpos; + +#if BYTES_BIG_ENDIAN + xlr_bitpos = rnbitsize - xlr_bitpos - lr_bitsize; + xrr_bitpos = rnbitsize - xrr_bitpos - rr_bitsize; +#endif + + lr_mask = const_binop (LSHIFT_EXPR, convert (type, lr_mask), + size_int (xlr_bitpos), 0); + rr_mask = const_binop (LSHIFT_EXPR, convert (type, rr_mask), + size_int (xrr_bitpos), 0); + + /* Make a mask that corresponds to both fields being compared. + Do this for both items being compared. If the masks agree, + we can do this by masking both and comparing the masked + results. */ + ll_mask = const_binop (BIT_IOR_EXPR, ll_mask, rl_mask, 0); + lr_mask = const_binop (BIT_IOR_EXPR, lr_mask, rr_mask, 0); + if (operand_equal_p (ll_mask, lr_mask, 0) && lnbitsize == rnbitsize) + { + lhs = make_bit_field_ref (ll_inner, type, lnbitsize, lnbitpos, + ll_unsignedp || rl_unsignedp); + rhs = make_bit_field_ref (lr_inner, type, rnbitsize, rnbitpos, + lr_unsignedp || rr_unsignedp); + if (! all_ones_mask_p (ll_mask, lnbitsize)) + { + lhs = build (BIT_AND_EXPR, type, lhs, ll_mask); + rhs = build (BIT_AND_EXPR, type, rhs, ll_mask); + } + return build (wanted_code, truth_type, lhs, rhs); + } + + /* There is still another way we can do something: If both pairs of + fields being compared are adjacent, we may be able to make a wider + field containing them both. */ + if ((ll_bitsize + ll_bitpos == rl_bitpos + && lr_bitsize + lr_bitpos == rr_bitpos) + || (ll_bitpos == rl_bitpos + rl_bitsize + && lr_bitpos == rr_bitpos + rr_bitsize)) + return build (wanted_code, truth_type, + make_bit_field_ref (ll_inner, type, + ll_bitsize + rl_bitsize, + MIN (ll_bitpos, rl_bitpos), + ll_unsignedp), + make_bit_field_ref (lr_inner, type, + lr_bitsize + rr_bitsize, + MIN (lr_bitpos, rr_bitpos), + lr_unsignedp)); + + return 0; + } + + /* Handle the case of comparisons with constants. If there is something in + common between the masks, those bits of the constants must be the same. + If not, the condition is always false. Test for this to avoid generating + incorrect code below. */ + result = const_binop (BIT_AND_EXPR, ll_mask, rl_mask, 0); + if (! integer_zerop (result) + && simple_cst_equal (const_binop (BIT_AND_EXPR, result, l_const, 0), + const_binop (BIT_AND_EXPR, result, r_const, 0)) != 1) + { + if (wanted_code == NE_EXPR) + { + warning ("`or' of unmatched not-equal tests is always 1"); + return convert (truth_type, integer_one_node); + } + else + { + warning ("`and' of mutually exclusive equal-tests is always zero"); + return convert (truth_type, integer_zero_node); + } + } + + /* Construct the expression we will return. First get the component + reference we will make. Unless the mask is all ones the width of + that field, perform the mask operation. Then compare with the + merged constant. */ + result = make_bit_field_ref (ll_inner, type, lnbitsize, lnbitpos, + ll_unsignedp || rl_unsignedp); + + ll_mask = const_binop (BIT_IOR_EXPR, ll_mask, rl_mask, 0); + if (! all_ones_mask_p (ll_mask, lnbitsize)) + result = build (BIT_AND_EXPR, type, result, ll_mask); + + return build (wanted_code, truth_type, result, + const_binop (BIT_IOR_EXPR, l_const, r_const, 0)); +} + +/* Perform constant folding and related simplification of EXPR. + The related simplifications include x*1 => x, x*0 => 0, etc., + and application of the associative law. + NOP_EXPR conversions may be removed freely (as long as we + are careful not to change the C type of the overall expression) + We cannot simplify through a CONVERT_EXPR, FIX_EXPR or FLOAT_EXPR, + but we can constant-fold them if they have constant operands. */ + +tree +fold (expr) + tree expr; +{ + register tree t = expr; + tree t1 = NULL_TREE; + tree tem; + tree type = TREE_TYPE (expr); + register tree arg0, arg1; + register enum tree_code code = TREE_CODE (t); + register int kind; + int invert; + + /* WINS will be nonzero when the switch is done + if all operands are constant. */ + + int wins = 1; + + /* Return right away if already constant. */ + if (TREE_CONSTANT (t)) + { + if (code == CONST_DECL) + return DECL_INITIAL (t); + return t; + } + + kind = TREE_CODE_CLASS (code); + if (code == NOP_EXPR || code == FLOAT_EXPR || code == CONVERT_EXPR) + { + tree subop; + + /* Special case for conversion ops that can have fixed point args. */ + arg0 = TREE_OPERAND (t, 0); + + /* Don't use STRIP_NOPS, because signedness of argument type matters. */ + if (arg0 != 0) + STRIP_TYPE_NOPS (arg0); + + if (arg0 != 0 && TREE_CODE (arg0) == COMPLEX_CST) + subop = TREE_REALPART (arg0); + else + subop = arg0; + + if (subop != 0 && TREE_CODE (subop) != INTEGER_CST +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + && TREE_CODE (subop) != REAL_CST +#endif /* not REAL_IS_NOT_DOUBLE, or REAL_ARITHMETIC */ + ) + /* Note that TREE_CONSTANT isn't enough: + static var addresses are constant but we can't + do arithmetic on them. */ + wins = 0; + } + else if (kind == 'e' || kind == '<' + || kind == '1' || kind == '2' || kind == 'r') + { + register int len = tree_code_length[(int) code]; + register int i; + for (i = 0; i < len; i++) + { + tree op = TREE_OPERAND (t, i); + tree subop; + + if (op == 0) + continue; /* Valid for CALL_EXPR, at least. */ + + if (kind == '<' || code == RSHIFT_EXPR) + { + /* Signedness matters here. Perhaps we can refine this + later. */ + STRIP_TYPE_NOPS (op); + } + else + { + /* Strip any conversions that don't change the mode. */ + STRIP_NOPS (op); + } + + if (TREE_CODE (op) == COMPLEX_CST) + subop = TREE_REALPART (op); + else + subop = op; + + if (TREE_CODE (subop) != INTEGER_CST +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + && TREE_CODE (subop) != REAL_CST +#endif /* not REAL_IS_NOT_DOUBLE, or REAL_ARITHMETIC */ + ) + /* Note that TREE_CONSTANT isn't enough: + static var addresses are constant but we can't + do arithmetic on them. */ + wins = 0; + + if (i == 0) + arg0 = op; + else if (i == 1) + arg1 = op; + } + } + + /* If this is a commutative operation, and ARG0 is a constant, move it + to ARG1 to reduce the number of tests below. */ + if ((code == PLUS_EXPR || code == MULT_EXPR || code == MIN_EXPR + || code == MAX_EXPR || code == BIT_IOR_EXPR || code == BIT_XOR_EXPR + || code == BIT_AND_EXPR) + && (TREE_CODE (arg0) == INTEGER_CST || TREE_CODE (arg0) == REAL_CST)) + { + tem = arg0; arg0 = arg1; arg1 = tem; + + tem = TREE_OPERAND (t, 0); TREE_OPERAND (t, 0) = TREE_OPERAND (t, 1); + TREE_OPERAND (t, 1) = tem; + } + + /* Now WINS is set as described above, + ARG0 is the first operand of EXPR, + and ARG1 is the second operand (if it has more than one operand). + + First check for cases where an arithmetic operation is applied to a + compound, conditional, or comparison operation. Push the arithmetic + operation inside the compound or conditional to see if any folding + can then be done. Convert comparison to conditional for this purpose. + The also optimizes non-constant cases that used to be done in + expand_expr. */ + if (TREE_CODE_CLASS (code) == '1') + { + if (TREE_CODE (arg0) == COMPOUND_EXPR) + return build (COMPOUND_EXPR, type, TREE_OPERAND (arg0, 0), + fold (build1 (code, type, TREE_OPERAND (arg0, 1)))); + else if (TREE_CODE (arg0) == COND_EXPR) + { + t = fold (build (COND_EXPR, type, TREE_OPERAND (arg0, 0), + fold (build1 (code, type, TREE_OPERAND (arg0, 1))), + fold (build1 (code, type, TREE_OPERAND (arg0, 2))))); + + /* If this was a conversion, and all we did was to move into + inside the COND_EXPR, bring it back out. Then return so we + don't get into an infinite recursion loop taking the conversion + out and then back in. */ + + if ((code == NOP_EXPR || code == CONVERT_EXPR + || code == NON_LVALUE_EXPR) + && TREE_CODE (t) == COND_EXPR + && TREE_CODE (TREE_OPERAND (t, 1)) == code + && TREE_CODE (TREE_OPERAND (t, 2)) == code + && (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (t, 1), 0)) + == TREE_TYPE (TREE_OPERAND (TREE_OPERAND (t, 2), 0)))) + t = build1 (code, type, + build (COND_EXPR, + TREE_TYPE (TREE_OPERAND (TREE_OPERAND (t, 1), 0)), + TREE_OPERAND (t, 0), + TREE_OPERAND (TREE_OPERAND (t, 1), 0), + TREE_OPERAND (TREE_OPERAND (t, 2), 0))); + return t; + } + else if (TREE_CODE_CLASS (TREE_CODE (arg0)) == '<') + return fold (build (COND_EXPR, type, arg0, + fold (build1 (code, type, integer_one_node)), + fold (build1 (code, type, integer_zero_node)))); + } + else if (TREE_CODE_CLASS (code) == '2') + { + if (TREE_CODE (arg1) == COMPOUND_EXPR) + return build (COMPOUND_EXPR, type, TREE_OPERAND (arg1, 0), + fold (build (code, type, arg0, TREE_OPERAND (arg1, 1)))); + else if (TREE_CODE (arg1) == COND_EXPR + || TREE_CODE_CLASS (TREE_CODE (arg1)) == '<') + { + tree test, true_value, false_value; + + if (TREE_CODE (arg1) == COND_EXPR) + { + test = TREE_OPERAND (arg1, 0); + true_value = TREE_OPERAND (arg1, 1); + false_value = TREE_OPERAND (arg1, 2); + } + else + { + test = arg1; + true_value = integer_one_node; + false_value = integer_zero_node; + } + + if (TREE_CODE (arg0) != VAR_DECL && TREE_CODE (arg0) != PARM_DECL) + arg0 = save_expr (arg0); + test = fold (build (COND_EXPR, type, test, + fold (build (code, type, arg0, true_value)), + fold (build (code, type, arg0, false_value)))); + if (TREE_CODE (arg0) == SAVE_EXPR) + return build (COMPOUND_EXPR, type, + convert (void_type_node, arg0), test); + else + return convert (type, test); + } + + else if (TREE_CODE (arg0) == COMPOUND_EXPR) + return build (COMPOUND_EXPR, type, TREE_OPERAND (arg0, 0), + fold (build (code, type, TREE_OPERAND (arg0, 1), arg1))); + else if (TREE_CODE (arg0) == COND_EXPR + || TREE_CODE_CLASS (TREE_CODE (arg0)) == '<') + { + tree test, true_value, false_value; + + if (TREE_CODE (arg0) == COND_EXPR) + { + test = TREE_OPERAND (arg0, 0); + true_value = TREE_OPERAND (arg0, 1); + false_value = TREE_OPERAND (arg0, 2); + } + else + { + test = arg0; + true_value = integer_one_node; + false_value = integer_zero_node; + } + + if (TREE_CODE (arg1) != VAR_DECL && TREE_CODE (arg1) != PARM_DECL) + arg1 = save_expr (arg1); + test = fold (build (COND_EXPR, type, test, + fold (build (code, type, true_value, arg1)), + fold (build (code, type, false_value, arg1)))); + if (TREE_CODE (arg1) == SAVE_EXPR) + return build (COMPOUND_EXPR, type, + convert (void_type_node, arg1), test); + else + return convert (type, test); + } + } + else if (TREE_CODE_CLASS (code) == '<' + && TREE_CODE (arg0) == COMPOUND_EXPR) + return build (COMPOUND_EXPR, type, TREE_OPERAND (arg0, 0), + fold (build (code, type, TREE_OPERAND (arg0, 1), arg1))); + else if (TREE_CODE_CLASS (code) == '<' + && TREE_CODE (arg1) == COMPOUND_EXPR) + return build (COMPOUND_EXPR, type, TREE_OPERAND (arg1, 0), + fold (build (code, type, arg0, TREE_OPERAND (arg1, 1)))); + + switch (code) + { + case INTEGER_CST: + case REAL_CST: + case STRING_CST: + case COMPLEX_CST: + case CONSTRUCTOR: + return t; + + case CONST_DECL: + return fold (DECL_INITIAL (t)); + + case NOP_EXPR: + case FLOAT_EXPR: + case CONVERT_EXPR: + case FIX_TRUNC_EXPR: + /* Other kinds of FIX are not handled properly by fold_convert. */ + /* Two conversions in a row are not needed unless: + - the intermediate type is narrower than both initial and final, or + - the intermediate type and innermost type differ in signedness, + and the outermost type is wider than the intermediate, or + - the initial type is a pointer type and the precisions of the + intermediate and final types differ, or + - the final type is a pointer type and the precisions of the + initial and intermediate types differ. */ + if ((TREE_CODE (TREE_OPERAND (t, 0)) == NOP_EXPR + || TREE_CODE (TREE_OPERAND (t, 0)) == CONVERT_EXPR) + && (TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (t, 0))) + > TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (t, 0), 0))) + || + TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (t, 0))) + > TYPE_PRECISION (TREE_TYPE (t))) + && ! ((TREE_CODE (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (t, 0), 0))) + == INTEGER_TYPE) + && (TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0))) + == INTEGER_TYPE) + && (TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (t, 0))) + != TREE_UNSIGNED (TREE_OPERAND (TREE_OPERAND (t, 0), 0))) + && (TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (t, 0))) + < TYPE_PRECISION (TREE_TYPE (t)))) + && ((TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (t, 0))) + && (TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (t, 0))) + > TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (t, 0), 0))))) + == + (TREE_UNSIGNED (TREE_TYPE (t)) + && (TYPE_PRECISION (TREE_TYPE (t)) + > TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (t, 0)))))) + && ! ((TREE_CODE (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (t, 0), 0))) + == POINTER_TYPE) + && (TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (t, 0))) + != TYPE_PRECISION (TREE_TYPE (t)))) + && ! (TREE_CODE (TREE_TYPE (t)) == POINTER_TYPE + && (TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (TREE_OPERAND (t, 0), 0))) + != TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (t, 0)))))) + return convert (TREE_TYPE (t), TREE_OPERAND (TREE_OPERAND (t, 0), 0)); + + if (TREE_CODE (TREE_OPERAND (t, 0)) == MODIFY_EXPR + && TREE_CONSTANT (TREE_OPERAND (TREE_OPERAND (t, 0), 1)) + /* Detect assigning a bitfield. */ + && !(TREE_CODE (TREE_OPERAND (TREE_OPERAND (t, 0), 0)) == COMPONENT_REF + && DECL_BIT_FIELD (TREE_OPERAND (TREE_OPERAND (TREE_OPERAND (t, 0), 0), 1)))) + { + /* Don't leave an assignment inside a conversion + unless assigning a bitfield. */ + tree prev = TREE_OPERAND (t, 0); + TREE_OPERAND (t, 0) = TREE_OPERAND (prev, 1); + /* First do the assignment, then return converted constant. */ + t = build (COMPOUND_EXPR, TREE_TYPE (t), prev, fold (t)); + TREE_USED (t) = 1; + return t; + } + if (!wins) + { + TREE_CONSTANT (t) = TREE_CONSTANT (arg0); + return t; + } + return fold_convert (t, arg0); + +#if 0 /* This loses on &"foo"[0]. */ + case ARRAY_REF: + { + int i; + + /* Fold an expression like: "foo"[2] */ + if (TREE_CODE (arg0) == STRING_CST + && TREE_CODE (arg1) == INTEGER_CST + && !TREE_INT_CST_HIGH (arg1) + && (i = TREE_INT_CST_LOW (arg1)) < TREE_STRING_LENGTH (arg0)) + { + t = build_int_2 (TREE_STRING_POINTER (arg0)[i], 0); + TREE_TYPE (t) = TREE_TYPE (TREE_TYPE (arg0)); + force_fit_type (t, 0); + } + } + return t; +#endif /* 0 */ + + case RANGE_EXPR: + TREE_CONSTANT (t) = wins; + return t; + + case NEGATE_EXPR: + if (wins) + { + if (TREE_CODE (arg0) == INTEGER_CST) + { + HOST_WIDE_INT low, high; + int overflow = neg_double (TREE_INT_CST_LOW (arg0), + TREE_INT_CST_HIGH (arg0), + &low, &high); + t = build_int_2 (low, high); + TREE_TYPE (t) = type; + TREE_CONSTANT_OVERFLOW (t) + = (TREE_CONSTANT_OVERFLOW (arg0) + | force_fit_type (t, overflow)); + } + else if (TREE_CODE (arg0) == REAL_CST) + t = build_real (type, REAL_VALUE_NEGATE (TREE_REAL_CST (arg0))); + TREE_TYPE (t) = type; + } + else if (TREE_CODE (arg0) == NEGATE_EXPR) + return TREE_OPERAND (arg0, 0); + + /* Convert - (a - b) to (b - a) for non-floating-point. */ + else if (TREE_CODE (arg0) == MINUS_EXPR && ! FLOAT_TYPE_P (type)) + return build (MINUS_EXPR, type, TREE_OPERAND (arg0, 1), + TREE_OPERAND (arg0, 0)); + + return t; + + case ABS_EXPR: + if (wins) + { + if (TREE_CODE (arg0) == INTEGER_CST) + { + if (! TREE_UNSIGNED (type) + && TREE_INT_CST_HIGH (arg0) < 0) + { + HOST_WIDE_INT low, high; + int overflow = neg_double (TREE_INT_CST_LOW (arg0), + TREE_INT_CST_HIGH (arg0), + &low, &high); + t = build_int_2 (low, high); + TREE_TYPE (t) = type; + TREE_CONSTANT_OVERFLOW (t) + = (TREE_CONSTANT_OVERFLOW (arg0) + | force_fit_type (t, overflow)); + } + } + else if (TREE_CODE (arg0) == REAL_CST) + { + if (REAL_VALUE_NEGATIVE (TREE_REAL_CST (arg0))) + t = build_real (type, + REAL_VALUE_NEGATE (TREE_REAL_CST (arg0))); + } + TREE_TYPE (t) = type; + } + else if (TREE_CODE (arg0) == ABS_EXPR || TREE_CODE (arg0) == NEGATE_EXPR) + return build1 (ABS_EXPR, type, TREE_OPERAND (arg0, 0)); + return t; + + case BIT_NOT_EXPR: + if (wins) + { + if (TREE_CODE (arg0) == INTEGER_CST) + t = build_int_2 (~ TREE_INT_CST_LOW (arg0), + ~ TREE_INT_CST_HIGH (arg0)); + TREE_TYPE (t) = type; + force_fit_type (t, 0); + TREE_CONSTANT_OVERFLOW (t) = TREE_CONSTANT_OVERFLOW (arg0); + } + else if (TREE_CODE (arg0) == BIT_NOT_EXPR) + return TREE_OPERAND (arg0, 0); + return t; + + case PLUS_EXPR: + /* A + (-B) -> A - B */ + if (TREE_CODE (arg1) == NEGATE_EXPR) + return fold (build (MINUS_EXPR, type, arg0, TREE_OPERAND (arg1, 0))); + else if (! FLOAT_TYPE_P (type)) + { + if (integer_zerop (arg1)) + return non_lvalue (convert (type, arg0)); + + /* If we are adding two BIT_AND_EXPR's, both of which are and'ing + with a constant, and the two constants have no bits in common, + we should treat this as a BIT_IOR_EXPR since this may produce more + simplifications. */ + if (TREE_CODE (arg0) == BIT_AND_EXPR + && TREE_CODE (arg1) == BIT_AND_EXPR + && TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST + && TREE_CODE (TREE_OPERAND (arg1, 1)) == INTEGER_CST + && integer_zerop (const_binop (BIT_AND_EXPR, + TREE_OPERAND (arg0, 1), + TREE_OPERAND (arg1, 1), 0))) + { + code = BIT_IOR_EXPR; + goto bit_ior; + } + } + /* In IEEE floating point, x+0 may not equal x. */ + else if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + && real_zerop (arg1)) + return non_lvalue (convert (type, arg0)); + associate: + /* In most languages, can't associate operations on floats + through parentheses. Rather than remember where the parentheses + were, we don't associate floats at all. It shouldn't matter much. */ + if (FLOAT_TYPE_P (type)) + goto binary; + /* The varsign == -1 cases happen only for addition and subtraction. + It says that the arg that was split was really CON minus VAR. + The rest of the code applies to all associative operations. */ + if (!wins) + { + tree var, con; + int varsign; + + if (split_tree (arg0, code, &var, &con, &varsign)) + { + if (varsign == -1) + { + /* EXPR is (CON-VAR) +- ARG1. */ + /* If it is + and VAR==ARG1, return just CONST. */ + if (code == PLUS_EXPR && operand_equal_p (var, arg1, 0)) + return convert (TREE_TYPE (t), con); + + /* If ARG0 is a constant, don't change things around; + instead keep all the constant computations together. */ + + if (TREE_CONSTANT (arg0)) + return t; + + /* Otherwise return (CON +- ARG1) - VAR. */ + TREE_SET_CODE (t, MINUS_EXPR); + TREE_OPERAND (t, 1) = var; + TREE_OPERAND (t, 0) + = fold (build (code, TREE_TYPE (t), con, arg1)); + } + else + { + /* EXPR is (VAR+CON) +- ARG1. */ + /* If it is - and VAR==ARG1, return just CONST. */ + if (code == MINUS_EXPR && operand_equal_p (var, arg1, 0)) + return convert (TREE_TYPE (t), con); + + /* If ARG0 is a constant, don't change things around; + instead keep all the constant computations together. */ + + if (TREE_CONSTANT (arg0)) + return t; + + /* Otherwise return VAR +- (ARG1 +- CON). */ + TREE_OPERAND (t, 1) = tem + = fold (build (code, TREE_TYPE (t), arg1, con)); + TREE_OPERAND (t, 0) = var; + if (integer_zerop (tem) + && (code == PLUS_EXPR || code == MINUS_EXPR)) + return convert (type, var); + /* If we have x +/- (c - d) [c an explicit integer] + change it to x -/+ (d - c) since if d is relocatable + then the latter can be a single immediate insn + and the former cannot. */ + if (TREE_CODE (tem) == MINUS_EXPR + && TREE_CODE (TREE_OPERAND (tem, 0)) == INTEGER_CST) + { + tree tem1 = TREE_OPERAND (tem, 1); + TREE_OPERAND (tem, 1) = TREE_OPERAND (tem, 0); + TREE_OPERAND (tem, 0) = tem1; + TREE_SET_CODE (t, + (code == PLUS_EXPR ? MINUS_EXPR : PLUS_EXPR)); + } + } + return t; + } + + if (split_tree (arg1, code, &var, &con, &varsign)) + { + /* EXPR is ARG0 +- (CON +- VAR). */ + if (TREE_CODE (t) == MINUS_EXPR + && operand_equal_p (var, arg0, 0)) + { + /* If VAR and ARG0 cancel, return just CON or -CON. */ + if (code == PLUS_EXPR) + return convert (TREE_TYPE (t), con); + return fold (build1 (NEGATE_EXPR, TREE_TYPE (t), + convert (TREE_TYPE (t), con))); + } + if (TREE_CONSTANT (arg1)) + return t; + if (varsign == -1) + TREE_SET_CODE (t, + (code == PLUS_EXPR ? MINUS_EXPR : PLUS_EXPR)); + TREE_OPERAND (t, 0) + = fold (build (code, TREE_TYPE (t), arg0, con)); + TREE_OPERAND (t, 1) = var; + if (integer_zerop (TREE_OPERAND (t, 0)) + && TREE_CODE (t) == PLUS_EXPR) + return convert (TREE_TYPE (t), var); + return t; + } + } + binary: +#if defined (REAL_IS_NOT_DOUBLE) && ! defined (REAL_ARITHMETIC) + if (TREE_CODE (arg1) == REAL_CST) + return t; +#endif /* REAL_IS_NOT_DOUBLE, and no REAL_ARITHMETIC */ + if (wins) + t1 = const_binop (code, arg0, arg1, 0); + if (t1 != NULL_TREE) + { + /* The return value should always have + the same type as the original expression. */ + TREE_TYPE (t1) = TREE_TYPE (t); + return t1; + } + return t; + + case MINUS_EXPR: + if (! FLOAT_TYPE_P (type)) + { + if (! wins && integer_zerop (arg0)) + return build1 (NEGATE_EXPR, type, arg1); + if (integer_zerop (arg1)) + return non_lvalue (convert (type, arg0)); + } + /* Convert A - (-B) to A + B. */ + else if (TREE_CODE (arg1) == NEGATE_EXPR) + return fold (build (PLUS_EXPR, type, arg0, TREE_OPERAND (arg1, 0))); + else if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT) + { + /* Except with IEEE floating point, 0-x equals -x. */ + if (! wins && real_zerop (arg0)) + return build1 (NEGATE_EXPR, type, arg1); + /* Except with IEEE floating point, x-0 equals x. */ + if (real_zerop (arg1)) + return non_lvalue (convert (type, arg0)); + + /* Fold &x - &x. This can happen from &x.foo - &x. + This is unsafe for certain floats even in non-IEEE formats. + In IEEE, it is unsafe because it does wrong for NaNs. + Also note that operand_equal_p is always false if an operand + is volatile. */ + + if (operand_equal_p (arg0, arg1, FLOAT_TYPE_P (type))) + return convert (type, integer_zero_node); + } + goto associate; + + case MULT_EXPR: + if (! FLOAT_TYPE_P (type)) + { + if (integer_zerop (arg1)) + return omit_one_operand (type, arg1, arg0); + if (integer_onep (arg1)) + return non_lvalue (convert (type, arg0)); + + /* (a * (1 << b)) is (a << b) */ + if (TREE_CODE (arg1) == LSHIFT_EXPR + && integer_onep (TREE_OPERAND (arg1, 0))) + return fold (build (LSHIFT_EXPR, type, arg0, + TREE_OPERAND (arg1, 1))); + if (TREE_CODE (arg0) == LSHIFT_EXPR + && integer_onep (TREE_OPERAND (arg0, 0))) + return fold (build (LSHIFT_EXPR, type, arg1, + TREE_OPERAND (arg0, 1))); + } + else + { + /* x*0 is 0, except for IEEE floating point. */ + if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + && real_zerop (arg1)) + return omit_one_operand (type, arg1, arg0); + /* In IEEE floating point, x*1 is not equivalent to x for snans. + However, ANSI says we can drop signals, + so we can do this anyway. */ + if (real_onep (arg1)) + return non_lvalue (convert (type, arg0)); + /* x*2 is x+x */ + if (! wins && real_twop (arg1)) + { + tree arg = save_expr (arg0); + return build (PLUS_EXPR, type, arg, arg); + } + } + goto associate; + + case BIT_IOR_EXPR: + bit_ior: + if (integer_all_onesp (arg1)) + return omit_one_operand (type, arg1, arg0); + if (integer_zerop (arg1)) + return non_lvalue (convert (type, arg0)); + t1 = distribute_bit_expr (code, type, arg0, arg1); + if (t1 != NULL_TREE) + return t1; + + /* (a << C1) | (a >> C2) if A is unsigned and C1+C2 is the size of A + is a rotate of A by C1 bits. */ + + if ((TREE_CODE (arg0) == RSHIFT_EXPR + || TREE_CODE (arg0) == LSHIFT_EXPR) + && (TREE_CODE (arg1) == RSHIFT_EXPR + || TREE_CODE (arg1) == LSHIFT_EXPR) + && TREE_CODE (arg0) != TREE_CODE (arg1) + && operand_equal_p (TREE_OPERAND (arg0, 0), TREE_OPERAND (arg1,0), 0) + && TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (arg0, 0))) + && TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST + && TREE_CODE (TREE_OPERAND (arg1, 1)) == INTEGER_CST + && TREE_INT_CST_HIGH (TREE_OPERAND (arg0, 1)) == 0 + && TREE_INT_CST_HIGH (TREE_OPERAND (arg1, 1)) == 0 + && ((TREE_INT_CST_LOW (TREE_OPERAND (arg0, 1)) + + TREE_INT_CST_LOW (TREE_OPERAND (arg1, 1))) + == TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (arg0, 0))))) + return build (LROTATE_EXPR, type, TREE_OPERAND (arg0, 0), + TREE_CODE (arg0) == LSHIFT_EXPR + ? TREE_OPERAND (arg0, 1) : TREE_OPERAND (arg1, 1)); + + goto associate; + + case BIT_XOR_EXPR: + if (integer_zerop (arg1)) + return non_lvalue (convert (type, arg0)); + if (integer_all_onesp (arg1)) + return fold (build1 (BIT_NOT_EXPR, type, arg0)); + goto associate; + + case BIT_AND_EXPR: + bit_and: + if (integer_all_onesp (arg1)) + return non_lvalue (convert (type, arg0)); + if (integer_zerop (arg1)) + return omit_one_operand (type, arg1, arg0); + t1 = distribute_bit_expr (code, type, arg0, arg1); + if (t1 != NULL_TREE) + return t1; + /* Simplify ((int)c & 0x377) into (int)c, if c is unsigned char. */ + if (TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == NOP_EXPR + && TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (arg1, 0)))) + { + int prec = TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (arg1, 0))); + if (prec < BITS_PER_WORD && prec < HOST_BITS_PER_WIDE_INT + && (~TREE_INT_CST_LOW (arg0) + & (((HOST_WIDE_INT) 1 << prec) - 1)) == 0) + return build1 (NOP_EXPR, type, TREE_OPERAND (arg1, 0)); + } + if (TREE_CODE (arg1) == INTEGER_CST && TREE_CODE (arg0) == NOP_EXPR + && TREE_UNSIGNED (TREE_TYPE (TREE_OPERAND (arg0, 0)))) + { + int prec = TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (arg0, 0))); + if (prec < BITS_PER_WORD && prec < HOST_BITS_PER_WIDE_INT + && (~TREE_INT_CST_LOW (arg1) + & (((HOST_WIDE_INT) 1 << prec) - 1)) == 0) + return build1 (NOP_EXPR, type, TREE_OPERAND (arg0, 0)); + } + goto associate; + + case BIT_ANDTC_EXPR: + if (integer_all_onesp (arg0)) + return non_lvalue (convert (type, arg1)); + if (integer_zerop (arg0)) + return omit_one_operand (type, arg0, arg1); + if (TREE_CODE (arg1) == INTEGER_CST) + { + arg1 = fold (build1 (BIT_NOT_EXPR, type, arg1)); + code = BIT_AND_EXPR; + goto bit_and; + } + goto binary; + + case TRUNC_DIV_EXPR: + case ROUND_DIV_EXPR: + case FLOOR_DIV_EXPR: + case CEIL_DIV_EXPR: + case EXACT_DIV_EXPR: + case RDIV_EXPR: + if (integer_onep (arg1)) + return non_lvalue (convert (type, arg0)); + if (integer_zerop (arg1)) + return t; + + /* If we have ((a * C1) / C2) and C1 % C2 == 0, we can replace this with + (a * (C1/C2). Also look for when we have a SAVE_EXPR in + between. */ + if (TREE_CODE (arg1) == INTEGER_CST + && TREE_INT_CST_LOW (arg1) > 0 && TREE_INT_CST_HIGH (arg1) == 0 + && TREE_CODE (arg0) == MULT_EXPR + && TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST + && TREE_INT_CST_LOW (TREE_OPERAND (arg0, 1)) > 0 + && TREE_INT_CST_HIGH (TREE_OPERAND (arg0, 1)) == 0 + && 0 == (TREE_INT_CST_LOW (TREE_OPERAND (arg0, 1)) + % TREE_INT_CST_LOW (arg1))) + { + tree new_op + = build_int_2 (TREE_INT_CST_LOW (TREE_OPERAND (arg0, 1)) + / TREE_INT_CST_LOW (arg1), 0); + + TREE_TYPE (new_op) = type; + return build (MULT_EXPR, type, TREE_OPERAND (arg0, 0), new_op); + } + + else if (TREE_CODE (arg1) == INTEGER_CST + && TREE_INT_CST_LOW (arg1) > 0 && TREE_INT_CST_HIGH (arg1) == 0 + && TREE_CODE (arg0) == SAVE_EXPR + && TREE_CODE (TREE_OPERAND (arg0, 0)) == MULT_EXPR + && (TREE_CODE (TREE_OPERAND (TREE_OPERAND (arg0, 0), 1)) + == INTEGER_CST) + && (TREE_INT_CST_LOW (TREE_OPERAND (TREE_OPERAND (arg0, 0), 1)) + > 0) + && (TREE_INT_CST_HIGH (TREE_OPERAND (TREE_OPERAND (arg0, 0), 1)) + == 0) + && (TREE_INT_CST_LOW (TREE_OPERAND (TREE_OPERAND (arg0, 0), 1)) + % TREE_INT_CST_LOW (arg1)) == 0) + { + tree new_op + = build_int_2 (TREE_INT_CST_LOW (TREE_OPERAND (TREE_OPERAND (arg0, 0), 1)) + / TREE_INT_CST_LOW (arg1), 0); + + TREE_TYPE (new_op) = type; + return build (MULT_EXPR, type, + TREE_OPERAND (TREE_OPERAND (arg0, 0), 0), new_op); + } + +#if !defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) +#ifndef REAL_INFINITY + if (TREE_CODE (arg1) == REAL_CST + && real_zerop (arg1)) + return t; +#endif +#endif /* not REAL_IS_NOT_DOUBLE, or REAL_ARITHMETIC */ + + goto binary; + + case CEIL_MOD_EXPR: + case FLOOR_MOD_EXPR: + case ROUND_MOD_EXPR: + case TRUNC_MOD_EXPR: + if (integer_onep (arg1)) + return omit_one_operand (type, integer_zero_node, arg0); + if (integer_zerop (arg1)) + return t; + goto binary; + + case LSHIFT_EXPR: + case RSHIFT_EXPR: + case LROTATE_EXPR: + case RROTATE_EXPR: + if (integer_zerop (arg1)) + return non_lvalue (convert (type, arg0)); + /* Since negative shift count is not well-defined, + don't try to compute it in the compiler. */ + if (tree_int_cst_lt (arg1, integer_zero_node)) + return t; + goto binary; + + case MIN_EXPR: + if (operand_equal_p (arg0, arg1, 0)) + return arg0; + if (INTEGRAL_TYPE_P (type) + && operand_equal_p (arg1, TYPE_MIN_VALUE (type), 1)) + return omit_one_operand (type, arg1, arg0); + goto associate; + + case MAX_EXPR: + if (operand_equal_p (arg0, arg1, 0)) + return arg0; + if (INTEGRAL_TYPE_P (type) + && operand_equal_p (arg1, TYPE_MAX_VALUE (type), 1)) + return omit_one_operand (type, arg1, arg0); + goto associate; + + case TRUTH_NOT_EXPR: + /* Note that the operand of this must be an int + and its values must be 0 or 1. + ("true" is a fixed value perhaps depending on the language, + but we don't handle values other than 1 correctly yet.) */ + return invert_truthvalue (arg0); + + case TRUTH_ANDIF_EXPR: + /* Note that the operands of this must be ints + and their values must be 0 or 1. + ("true" is a fixed value perhaps depending on the language.) */ + /* If first arg is constant zero, return it. */ + if (integer_zerop (arg0)) + return arg0; + case TRUTH_AND_EXPR: + /* If either arg is constant true, drop it. */ + if (TREE_CODE (arg0) == INTEGER_CST && ! integer_zerop (arg0)) + return non_lvalue (arg1); + if (TREE_CODE (arg1) == INTEGER_CST && ! integer_zerop (arg1)) + return non_lvalue (arg0); + /* If second arg is constant zero, result is zero, but first arg + must be evaluated. */ + if (integer_zerop (arg1)) + return omit_one_operand (type, arg1, arg0); + + truth_andor: + /* Check for the possibility of merging component references. If our + lhs is another similar operation, try to merge its rhs with our + rhs. Then try to merge our lhs and rhs. */ + if (optimize) + { + if (TREE_CODE (arg0) == code) + { + tem = fold_truthop (code, type, + TREE_OPERAND (arg0, 1), arg1); + if (tem) + return fold (build (code, type, TREE_OPERAND (arg0, 0), tem)); + } + + tem = fold_truthop (code, type, arg0, arg1); + if (tem) + return tem; + } + return t; + + case TRUTH_ORIF_EXPR: + /* Note that the operands of this must be ints + and their values must be 0 or true. + ("true" is a fixed value perhaps depending on the language.) */ + /* If first arg is constant true, return it. */ + if (TREE_CODE (arg0) == INTEGER_CST && ! integer_zerop (arg0)) + return arg0; + case TRUTH_OR_EXPR: + /* If either arg is constant zero, drop it. */ + if (TREE_CODE (arg0) == INTEGER_CST && integer_zerop (arg0)) + return non_lvalue (arg1); + if (TREE_CODE (arg1) == INTEGER_CST && integer_zerop (arg1)) + return non_lvalue (arg0); + /* If second arg is constant true, result is true, but we must + evaluate first arg. */ + if (TREE_CODE (arg1) == INTEGER_CST && ! integer_zerop (arg1)) + return omit_one_operand (type, arg1, arg0); + goto truth_andor; + + case TRUTH_XOR_EXPR: + /* If either arg is constant zero, drop it. */ + if (integer_zerop (arg0)) + return non_lvalue (arg1); + if (integer_zerop (arg1)) + return non_lvalue (arg0); + /* If either arg is constant true, this is a logical inversion. */ + if (integer_onep (arg0)) + return non_lvalue (invert_truthvalue (arg1)); + if (integer_onep (arg1)) + return non_lvalue (invert_truthvalue (arg0)); + break; + + case EQ_EXPR: + case NE_EXPR: + case LT_EXPR: + case GT_EXPR: + case LE_EXPR: + case GE_EXPR: + /* If one arg is a constant integer, put it last. */ + if (TREE_CODE (arg0) == INTEGER_CST + && TREE_CODE (arg1) != INTEGER_CST) + { + TREE_OPERAND (t, 0) = arg1; + TREE_OPERAND (t, 1) = arg0; + arg0 = TREE_OPERAND (t, 0); + arg1 = TREE_OPERAND (t, 1); + code = swap_tree_comparison (code); + TREE_SET_CODE (t, code); + } + + /* Convert foo++ == CONST into ++foo == CONST + INCR. + First, see if one arg is constant; find the constant arg + and the other one. */ + { + tree constop = 0, varop; + tree *constoploc; + + if (TREE_CONSTANT (arg1)) + constoploc = &TREE_OPERAND (t, 1), constop = arg1, varop = arg0; + if (TREE_CONSTANT (arg0)) + constoploc = &TREE_OPERAND (t, 0), constop = arg0, varop = arg1; + + if (constop && TREE_CODE (varop) == POSTINCREMENT_EXPR) + { + /* This optimization is invalid for ordered comparisons + if CONST+INCR overflows or if foo+incr might overflow. + This optimization is invalid for floating point due to rounding. + For pointer types we assume overflow doesn't happen. */ + if (TREE_CODE (TREE_TYPE (varop)) == POINTER_TYPE + || (! FLOAT_TYPE_P (TREE_TYPE (varop)) + && (code == EQ_EXPR || code == NE_EXPR))) + { + tree newconst + = fold (build (PLUS_EXPR, TREE_TYPE (varop), + constop, TREE_OPERAND (varop, 1))); + TREE_SET_CODE (varop, PREINCREMENT_EXPR); + *constoploc = newconst; + return t; + } + } + else if (constop && TREE_CODE (varop) == POSTDECREMENT_EXPR) + { + if (TREE_CODE (TREE_TYPE (varop)) == POINTER_TYPE + || (! FLOAT_TYPE_P (TREE_TYPE (varop)) + && (code == EQ_EXPR || code == NE_EXPR))) + { + tree newconst + = fold (build (MINUS_EXPR, TREE_TYPE (varop), + constop, TREE_OPERAND (varop, 1))); + TREE_SET_CODE (varop, PREDECREMENT_EXPR); + *constoploc = newconst; + return t; + } + } + } + + /* Change X >= CST to X > (CST - 1) if CST is positive. */ + if (TREE_CODE (arg1) == INTEGER_CST + && TREE_CODE (arg0) != INTEGER_CST + && ! tree_int_cst_lt (arg1, integer_one_node)) + { + switch (TREE_CODE (t)) + { + case GE_EXPR: + code = GT_EXPR; + TREE_SET_CODE (t, code); + arg1 = const_binop (MINUS_EXPR, arg1, integer_one_node, 0); + TREE_OPERAND (t, 1) = arg1; + break; + + case LT_EXPR: + code = LE_EXPR; + TREE_SET_CODE (t, code); + arg1 = const_binop (MINUS_EXPR, arg1, integer_one_node, 0); + TREE_OPERAND (t, 1) = arg1; + } + } + + /* If this is an EQ or NE comparison with zero and ARG0 is + (1 << foo) & bar, convert it to (bar >> foo) & 1. Both require + two operations, but the latter can be done in one less insn + one machine that have only two-operand insns or on which a + constant cannot be the first operand. */ + if (integer_zerop (arg1) && (code == EQ_EXPR || code == NE_EXPR) + && TREE_CODE (arg0) == BIT_AND_EXPR) + { + if (TREE_CODE (TREE_OPERAND (arg0, 0)) == LSHIFT_EXPR + && integer_onep (TREE_OPERAND (TREE_OPERAND (arg0, 0), 0))) + return + fold (build (code, type, + build (BIT_AND_EXPR, TREE_TYPE (arg0), + build (RSHIFT_EXPR, + TREE_TYPE (TREE_OPERAND (arg0, 0)), + TREE_OPERAND (arg0, 1), + TREE_OPERAND (TREE_OPERAND (arg0, 0), 1)), + convert (TREE_TYPE (arg0), + integer_one_node)), + arg1)); + else if (TREE_CODE (TREE_OPERAND (arg0, 1)) == LSHIFT_EXPR + && integer_onep (TREE_OPERAND (TREE_OPERAND (arg0, 1), 0))) + return + fold (build (code, type, + build (BIT_AND_EXPR, TREE_TYPE (arg0), + build (RSHIFT_EXPR, + TREE_TYPE (TREE_OPERAND (arg0, 1)), + TREE_OPERAND (arg0, 0), + TREE_OPERAND (TREE_OPERAND (arg0, 1), 1)), + convert (TREE_TYPE (arg0), + integer_one_node)), + arg1)); + } + + /* If this is an NE comparison of zero with an AND of one, remove the + comparison since the AND will give the correct value. */ + if (code == NE_EXPR && integer_zerop (arg1) + && TREE_CODE (arg0) == BIT_AND_EXPR + && integer_onep (TREE_OPERAND (arg0, 1))) + return convert (type, arg0); + + /* If we have (A & C) == C where C is a power of 2, convert this into + (A & C) != 0. Similarly for NE_EXPR. */ + if ((code == EQ_EXPR || code == NE_EXPR) + && TREE_CODE (arg0) == BIT_AND_EXPR + && integer_pow2p (TREE_OPERAND (arg0, 1)) + && operand_equal_p (TREE_OPERAND (arg0, 1), arg1, 0)) + return build (code == EQ_EXPR ? NE_EXPR : EQ_EXPR, type, + arg0, integer_zero_node); + + /* Simplify comparison of something with itself. (For IEEE + floating-point, we can only do some of these simplifications.) */ + if (operand_equal_p (arg0, arg1, 0)) + { + switch (code) + { + case EQ_EXPR: + case GE_EXPR: + case LE_EXPR: + if (INTEGRAL_TYPE_P (TREE_TYPE (arg0))) + { + t = build_int_2 (1, 0); + TREE_TYPE (t) = type; + return t; + } + code = EQ_EXPR; + TREE_SET_CODE (t, code); + break; + + case NE_EXPR: + /* For NE, we can only do this simplification if integer. */ + if (! INTEGRAL_TYPE_P (TREE_TYPE (arg0))) + break; + /* ... fall through ... */ + case GT_EXPR: + case LT_EXPR: + t = build_int_2 (0, 0); + TREE_TYPE (t) = type; + return t; + } + } + + /* An unsigned comparison against 0 can be simplified. */ + if (integer_zerop (arg1) + && (INTEGRAL_TYPE_P (TREE_TYPE (arg1)) + || TREE_CODE (TREE_TYPE (arg1)) == POINTER_TYPE) + && TREE_UNSIGNED (TREE_TYPE (arg1))) + { + switch (TREE_CODE (t)) + { + case GT_EXPR: + code = NE_EXPR; + TREE_SET_CODE (t, NE_EXPR); + break; + case LE_EXPR: + code = EQ_EXPR; + TREE_SET_CODE (t, EQ_EXPR); + break; + case GE_EXPR: + return omit_one_operand (integer_type_node, + integer_one_node, arg0); + case LT_EXPR: + return omit_one_operand (integer_type_node, + integer_zero_node, arg0); + } + } + + /* If we are comparing an expression that just has comparisons + of two integer values, arithmetic expressions of those comparisons, + and constants, we can simplify it. There are only three cases + to check: the two values can either be equal, the first can be + greater, or the second can be greater. Fold the expression for + those three values. Since each value must be 0 or 1, we have + eight possibilities, each of which corresponds to the constant 0 + or 1 or one of the six possible comparisons. + + This handles common cases like (a > b) == 0 but also handles + expressions like ((x > y) - (y > x)) > 0, which supposedly + occur in macroized code. */ + + if (TREE_CODE (arg1) == INTEGER_CST && TREE_CODE (arg0) != INTEGER_CST) + { + tree cval1 = 0, cval2 = 0; + + if (twoval_comparison_p (arg0, &cval1, &cval2) + /* Don't handle degenerate cases here; they should already + have been handled anyway. */ + && cval1 != 0 && cval2 != 0 + && ! (TREE_CONSTANT (cval1) && TREE_CONSTANT (cval2)) + && TREE_TYPE (cval1) == TREE_TYPE (cval2) + && INTEGRAL_TYPE_P (TREE_TYPE (cval1)) + && ! operand_equal_p (TYPE_MIN_VALUE (TREE_TYPE (cval1)), + TYPE_MAX_VALUE (TREE_TYPE (cval2)), 0)) + { + tree maxval = TYPE_MAX_VALUE (TREE_TYPE (cval1)); + tree minval = TYPE_MIN_VALUE (TREE_TYPE (cval1)); + + /* We can't just pass T to eval_subst in case cval1 or cval2 + was the same as ARG1. */ + + tree high_result + = fold (build (code, type, + eval_subst (arg0, cval1, maxval, cval2, minval), + arg1)); + tree equal_result + = fold (build (code, type, + eval_subst (arg0, cval1, maxval, cval2, maxval), + arg1)); + tree low_result + = fold (build (code, type, + eval_subst (arg0, cval1, minval, cval2, maxval), + arg1)); + + /* All three of these results should be 0 or 1. Confirm they + are. Then use those values to select the proper code + to use. */ + + if ((integer_zerop (high_result) + || integer_onep (high_result)) + && (integer_zerop (equal_result) + || integer_onep (equal_result)) + && (integer_zerop (low_result) + || integer_onep (low_result))) + { + /* Make a 3-bit mask with the high-order bit being the + value for `>', the next for '=', and the low for '<'. */ + switch ((integer_onep (high_result) * 4) + + (integer_onep (equal_result) * 2) + + integer_onep (low_result)) + { + case 0: + /* Always false. */ + return omit_one_operand (type, integer_zero_node, arg0); + case 1: + code = LT_EXPR; + break; + case 2: + code = EQ_EXPR; + break; + case 3: + code = LE_EXPR; + break; + case 4: + code = GT_EXPR; + break; + case 5: + code = NE_EXPR; + break; + case 6: + code = GE_EXPR; + break; + case 7: + /* Always true. */ + return omit_one_operand (type, integer_one_node, arg0); + } + + return fold (build (code, type, cval1, cval2)); + } + } + } + + /* If this is a comparison of a field, we may be able to simplify it. */ + if ((TREE_CODE (arg0) == COMPONENT_REF + || TREE_CODE (arg0) == BIT_FIELD_REF) + && (code == EQ_EXPR || code == NE_EXPR) + /* Handle the constant case even without -O + to make sure the warnings are given. */ + && (optimize || TREE_CODE (arg1) == INTEGER_CST)) + { + t1 = optimize_bit_field_compare (code, type, arg0, arg1); + return t1 ? t1 : t; + } + + /* From here on, the only cases we handle are when the result is + known to be a constant. + + To compute GT, swap the arguments and do LT. + To compute GE, do LT and invert the result. + To compute LE, swap the arguments, do LT and invert the result. + To compute NE, do EQ and invert the result. + + Therefore, the code below must handle only EQ and LT. */ + + if (code == LE_EXPR || code == GT_EXPR) + { + tem = arg0, arg0 = arg1, arg1 = tem; + code = swap_tree_comparison (code); + } + + /* Note that it is safe to invert for real values here because we + will check below in the one case that it matters. */ + + invert = 0; + if (code == NE_EXPR || code == GE_EXPR) + { + invert = 1; + code = invert_tree_comparison (code); + } + + /* Compute a result for LT or EQ if args permit; + otherwise return T. */ + if (TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST) + { + if (code == EQ_EXPR) + t1 = build_int_2 ((TREE_INT_CST_LOW (arg0) + == TREE_INT_CST_LOW (arg1)) + && (TREE_INT_CST_HIGH (arg0) + == TREE_INT_CST_HIGH (arg1)), + 0); + else + t1 = build_int_2 ((TREE_UNSIGNED (TREE_TYPE (arg0)) + ? INT_CST_LT_UNSIGNED (arg0, arg1) + : INT_CST_LT (arg0, arg1)), + 0); + } + + /* Assume a nonexplicit constant cannot equal an explicit one, + since such code would be undefined anyway. + Exception: on sysvr4, using #pragma weak, + a label can come out as 0. */ + else if (TREE_CODE (arg1) == INTEGER_CST + && !integer_zerop (arg1) + && TREE_CONSTANT (arg0) + && TREE_CODE (arg0) == ADDR_EXPR + && code == EQ_EXPR) + t1 = build_int_2 (0, 0); + + /* Two real constants can be compared explicitly. */ + else if (TREE_CODE (arg0) == REAL_CST && TREE_CODE (arg1) == REAL_CST) + { + /* If either operand is a NaN, the result is false with two + exceptions: First, an NE_EXPR is true on NaNs, but that case + is already handled correctly since we will be inverting the + result for NE_EXPR. Second, if we had inverted a LE_EXPR + or a GE_EXPR into a LT_EXPR, we must return true so that it + will be inverted into false. */ + + if (REAL_VALUE_ISNAN (TREE_REAL_CST (arg0)) + || REAL_VALUE_ISNAN (TREE_REAL_CST (arg1))) + t1 = build_int_2 (invert && code == LT_EXPR, 0); + + else if (code == EQ_EXPR) + t1 = build_int_2 (REAL_VALUES_EQUAL (TREE_REAL_CST (arg0), + TREE_REAL_CST (arg1)), + 0); + else + t1 = build_int_2 (REAL_VALUES_LESS (TREE_REAL_CST (arg0), + TREE_REAL_CST (arg1)), + 0); + } + + if (t1 == NULL_TREE) + return t; + + if (invert) + TREE_INT_CST_LOW (t1) ^= 1; + + TREE_TYPE (t1) = type; + return t1; + + case COND_EXPR: + if (TREE_CODE (arg0) == INTEGER_CST) + return TREE_OPERAND (t, (integer_zerop (arg0) ? 2 : 1)); + else if (operand_equal_p (arg1, TREE_OPERAND (expr, 2), 0)) + return omit_one_operand (type, arg1, arg0); + + /* If the second operand is zero, invert the comparison and swap + the second and third operands. Likewise if the second operand + is constant and the third is not or if the third operand is + equivalent to the first operand of the comparison. */ + + if (integer_zerop (arg1) + || (TREE_CONSTANT (arg1) && ! TREE_CONSTANT (TREE_OPERAND (t, 2))) + || (TREE_CODE_CLASS (TREE_CODE (arg0)) == '<' + && operand_equal_for_comparison_p (TREE_OPERAND (arg0, 0), + TREE_OPERAND (t, 2), + TREE_OPERAND (arg0, 1)))) + { + /* See if this can be inverted. If it can't, possibly because + it was a floating-point inequality comparison, don't do + anything. */ + tem = invert_truthvalue (arg0); + + if (TREE_CODE (tem) != TRUTH_NOT_EXPR) + { + arg0 = TREE_OPERAND (t, 0) = tem; + TREE_OPERAND (t, 1) = TREE_OPERAND (t, 2); + TREE_OPERAND (t, 2) = arg1; + arg1 = TREE_OPERAND (t, 1); + } + } + + /* If we have A op B ? A : C, we may be able to convert this to a + simpler expression, depending on the operation and the values + of B and C. IEEE floating point prevents this though, + because A or B might be -0.0 or a NaN. */ + + if (TREE_CODE_CLASS (TREE_CODE (arg0)) == '<' + && (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + || ! FLOAT_TYPE_P (TREE_TYPE (TREE_OPERAND (arg0, 0)))) + && operand_equal_for_comparison_p (TREE_OPERAND (arg0, 0), + arg1, TREE_OPERAND (arg0, 1))) + { + tree arg2 = TREE_OPERAND (t, 2); + enum tree_code comp_code = TREE_CODE (arg0); + + /* If we have A op 0 ? A : -A, this is A, -A, abs (A), or abs (-A), + depending on the comparison operation. */ + if (integer_zerop (TREE_OPERAND (arg0, 1)) + && TREE_CODE (arg2) == NEGATE_EXPR + && operand_equal_p (TREE_OPERAND (arg2, 0), arg1, 0)) + switch (comp_code) + { + case EQ_EXPR: + return fold (build1 (NEGATE_EXPR, type, arg1)); + case NE_EXPR: + return convert (type, arg1); + case GE_EXPR: + case GT_EXPR: + return fold (build1 (ABS_EXPR, type, arg1)); + case LE_EXPR: + case LT_EXPR: + return fold (build1 (NEGATE_EXPR, type, + fold (build1 (ABS_EXPR, type, arg1)))); + } + + /* If this is A != 0 ? A : 0, this is simply A. For ==, it is + always zero. */ + + if (integer_zerop (TREE_OPERAND (arg0, 1)) && integer_zerop (arg2)) + { + if (comp_code == NE_EXPR) + return convert (type, arg1); + else if (comp_code == EQ_EXPR) + return convert (type, integer_zero_node); + } + + /* If this is A op B ? A : B, this is either A, B, min (A, B), + or max (A, B), depending on the operation. */ + + if (operand_equal_for_comparison_p (TREE_OPERAND (arg0, 1), + arg2, TREE_OPERAND (arg0, 0))) + switch (comp_code) + { + case EQ_EXPR: + return convert (type, arg2); + case NE_EXPR: + return convert (type, arg1); + case LE_EXPR: + case LT_EXPR: + return fold (build (MIN_EXPR, type, arg1, arg2)); + case GE_EXPR: + case GT_EXPR: + return fold (build (MAX_EXPR, type, arg1, arg2)); + } + + /* If this is A op C1 ? A : C2 with C1 and C2 constant integers, + we might still be able to simplify this. For example, + if C1 is one less or one more than C2, this might have started + out as a MIN or MAX and been transformed by this function. + Only good for INTEGER_TYPEs, because we need TYPE_MAX_VALUE. */ + + if (INTEGRAL_TYPE_P (type) + && TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST + && TREE_CODE (arg2) == INTEGER_CST) + switch (comp_code) + { + case EQ_EXPR: + /* We can replace A with C1 in this case. */ + arg1 = TREE_OPERAND (t, 1) + = convert (type, TREE_OPERAND (arg0, 1)); + break; + + case LT_EXPR: + /* If C1 is C2 + 1, this is min(A, C2). */ + if (! operand_equal_p (arg2, TYPE_MAX_VALUE (type), 1) + && operand_equal_p (TREE_OPERAND (arg0, 1), + const_binop (PLUS_EXPR, arg2, + integer_one_node, 0), 1)) + return fold (build (MIN_EXPR, type, arg1, arg2)); + break; + + case LE_EXPR: + /* If C1 is C2 - 1, this is min(A, C2). */ + if (! operand_equal_p (arg2, TYPE_MIN_VALUE (type), 1) + && operand_equal_p (TREE_OPERAND (arg0, 1), + const_binop (MINUS_EXPR, arg2, + integer_one_node, 0), 1)) + return fold (build (MIN_EXPR, type, arg1, arg2)); + break; + + case GT_EXPR: + /* If C1 is C2 - 1, this is max(A, C2). */ + if (! operand_equal_p (arg2, TYPE_MIN_VALUE (type), 1) + && operand_equal_p (TREE_OPERAND (arg0, 1), + const_binop (MINUS_EXPR, arg2, + integer_one_node, 0), 1)) + return fold (build (MAX_EXPR, type, arg1, arg2)); + break; + + case GE_EXPR: + /* If C1 is C2 + 1, this is max(A, C2). */ + if (! operand_equal_p (arg2, TYPE_MAX_VALUE (type), 1) + && operand_equal_p (TREE_OPERAND (arg0, 1), + const_binop (PLUS_EXPR, arg2, + integer_one_node, 0), 1)) + return fold (build (MAX_EXPR, type, arg1, arg2)); + break; + } + } + + /* Convert A ? 1 : 0 to simply A. */ + if (integer_onep (TREE_OPERAND (t, 1)) + && integer_zerop (TREE_OPERAND (t, 2)) + /* If we try to convert TREE_OPERAND (t, 0) to our type, the + call to fold will try to move the conversion inside + a COND, which will recurse. In that case, the COND_EXPR + is probably the best choice, so leave it alone. */ + && type == TREE_TYPE (arg0)) + return arg0; + + + /* Look for expressions of the form A & 2 ? 2 : 0. The result of this + operation is simply A & 2. */ + + if (integer_zerop (TREE_OPERAND (t, 2)) + && TREE_CODE (arg0) == NE_EXPR + && integer_zerop (TREE_OPERAND (arg0, 1)) + && integer_pow2p (arg1) + && TREE_CODE (TREE_OPERAND (arg0, 0)) == BIT_AND_EXPR + && operand_equal_p (TREE_OPERAND (TREE_OPERAND (arg0, 0), 1), + arg1, 1)) + return convert (type, TREE_OPERAND (arg0, 0)); + + return t; + + case COMPOUND_EXPR: + /* When pedantic, a compound expression can be neither an lvalue + nor an integer constant expression. */ + if (TREE_SIDE_EFFECTS (arg0) || pedantic) + return t; + /* Don't let (0, 0) be null pointer constant. */ + if (integer_zerop (arg1)) + return non_lvalue (arg1); + return arg1; + + case COMPLEX_EXPR: + if (wins) + return build_complex (arg0, arg1); + return t; + + case REALPART_EXPR: + if (TREE_CODE (TREE_TYPE (arg0)) != COMPLEX_TYPE) + return t; + else if (TREE_CODE (arg0) == COMPLEX_EXPR) + return omit_one_operand (type, TREE_OPERAND (arg0, 0), + TREE_OPERAND (arg0, 1)); + else if (TREE_CODE (arg0) == COMPLEX_CST) + return TREE_REALPART (arg0); + else if (TREE_CODE (arg0) == PLUS_EXPR || TREE_CODE (arg0) == MINUS_EXPR) + return fold (build (TREE_CODE (arg0), type, + fold (build1 (REALPART_EXPR, type, + TREE_OPERAND (arg0, 0))), + fold (build1 (REALPART_EXPR, + type, TREE_OPERAND (arg0, 1))))); + return t; + + case IMAGPART_EXPR: + if (TREE_CODE (TREE_TYPE (arg0)) != COMPLEX_TYPE) + return convert (type, integer_zero_node); + else if (TREE_CODE (arg0) == COMPLEX_EXPR) + return omit_one_operand (type, TREE_OPERAND (arg0, 1), + TREE_OPERAND (arg0, 0)); + else if (TREE_CODE (arg0) == COMPLEX_CST) + return TREE_IMAGPART (arg0); + else if (TREE_CODE (arg0) == PLUS_EXPR || TREE_CODE (arg0) == MINUS_EXPR) + return fold (build (TREE_CODE (arg0), type, + fold (build1 (IMAGPART_EXPR, type, + TREE_OPERAND (arg0, 0))), + fold (build1 (IMAGPART_EXPR, type, + TREE_OPERAND (arg0, 1))))); + return t; + + default: + return t; + } /* switch (code) */ +} diff --git a/gnu/usr.bin/cc/lib/function.c b/gnu/usr.bin/cc/lib/function.c new file mode 100644 index 000000000000..f9d851713f42 --- /dev/null +++ b/gnu/usr.bin/cc/lib/function.c @@ -0,0 +1,4913 @@ +/* Expands front end tree to back end RTL for GNU C-Compiler + Copyright (C) 1987, 88, 89, 91, 92, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This file handles the generation of rtl code from tree structure + at the level of the function as a whole. + It creates the rtl expressions for parameters and auto variables + and has full responsibility for allocating stack slots. + + `expand_function_start' is called at the beginning of a function, + before the function body is parsed, and `expand_function_end' is + called after parsing the body. + + Call `assign_stack_local' to allocate a stack slot for a local variable. + This is usually done during the RTL generation for the function body, + but it can also be done in the reload pass when a pseudo-register does + not get a hard register. + + Call `put_var_into_stack' when you learn, belatedly, that a variable + previously given a pseudo-register must in fact go in the stack. + This function changes the DECL_RTL to be a stack slot instead of a reg + then scans all the RTL instructions so far generated to correct them. */ + +#include "config.h" + +#include + +#include "rtl.h" +#include "tree.h" +#include "flags.h" +#include "function.h" +#include "insn-flags.h" +#include "expr.h" +#include "insn-codes.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "insn-config.h" +#include "recog.h" +#include "output.h" +#include "basic-block.h" + +/* Round a value to the lowest integer less than it that is a multiple of + the required alignment. Avoid using division in case the value is + negative. Assume the alignment is a power of two. */ +#define FLOOR_ROUND(VALUE,ALIGN) ((VALUE) & ~((ALIGN) - 1)) + +/* Similar, but round to the next highest integer that meets the + alignment. */ +#define CEIL_ROUND(VALUE,ALIGN) (((VALUE) + (ALIGN) - 1) & ~((ALIGN)- 1)) + +/* NEED_SEPARATE_AP means that we cannot derive ap from the value of fp + during rtl generation. If they are different register numbers, this is + always true. It may also be true if + FIRST_PARM_OFFSET - STARTING_FRAME_OFFSET is not a constant during rtl + generation. See fix_lexical_addr for details. */ + +#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM +#define NEED_SEPARATE_AP +#endif + +/* Number of bytes of args popped by function being compiled on its return. + Zero if no bytes are to be popped. + May affect compilation of return insn or of function epilogue. */ + +int current_function_pops_args; + +/* Nonzero if function being compiled needs to be given an address + where the value should be stored. */ + +int current_function_returns_struct; + +/* Nonzero if function being compiled needs to + return the address of where it has put a structure value. */ + +int current_function_returns_pcc_struct; + +/* Nonzero if function being compiled needs to be passed a static chain. */ + +int current_function_needs_context; + +/* Nonzero if function being compiled can call setjmp. */ + +int current_function_calls_setjmp; + +/* Nonzero if function being compiled can call longjmp. */ + +int current_function_calls_longjmp; + +/* Nonzero if function being compiled receives nonlocal gotos + from nested functions. */ + +int current_function_has_nonlocal_label; + +/* Nonzero if function being compiled contains nested functions. */ + +int current_function_contains_functions; + +/* Nonzero if function being compiled can call alloca, + either as a subroutine or builtin. */ + +int current_function_calls_alloca; + +/* Nonzero if the current function returns a pointer type */ + +int current_function_returns_pointer; + +/* If some insns can be deferred to the delay slots of the epilogue, the + delay list for them is recorded here. */ + +rtx current_function_epilogue_delay_list; + +/* If function's args have a fixed size, this is that size, in bytes. + Otherwise, it is -1. + May affect compilation of return insn or of function epilogue. */ + +int current_function_args_size; + +/* # bytes the prologue should push and pretend that the caller pushed them. + The prologue must do this, but only if parms can be passed in registers. */ + +int current_function_pretend_args_size; + +/* # of bytes of outgoing arguments required to be pushed by the prologue. + If this is non-zero, it means that ACCUMULATE_OUTGOING_ARGS was defined + and no stack adjusts will be done on function calls. */ + +int current_function_outgoing_args_size; + +/* This is the offset from the arg pointer to the place where the first + anonymous arg can be found, if there is one. */ + +rtx current_function_arg_offset_rtx; + +/* Nonzero if current function uses varargs.h or equivalent. + Zero for functions that use stdarg.h. */ + +int current_function_varargs; + +/* Quantities of various kinds of registers + used for the current function's args. */ + +CUMULATIVE_ARGS current_function_args_info; + +/* Name of function now being compiled. */ + +char *current_function_name; + +/* If non-zero, an RTL expression for that location at which the current + function returns its result. Always equal to + DECL_RTL (DECL_RESULT (current_function_decl)), but provided + independently of the tree structures. */ + +rtx current_function_return_rtx; + +/* Nonzero if the current function uses the constant pool. */ + +int current_function_uses_const_pool; + +/* Nonzero if the current function uses pic_offset_table_rtx. */ +int current_function_uses_pic_offset_table; + +/* The arg pointer hard register, or the pseudo into which it was copied. */ +rtx current_function_internal_arg_pointer; + +/* The FUNCTION_DECL for an inline function currently being expanded. */ +tree inline_function_decl; + +/* Number of function calls seen so far in current function. */ + +int function_call_count; + +/* List (chain of TREE_LIST) of LABEL_DECLs for all nonlocal labels + (labels to which there can be nonlocal gotos from nested functions) + in this function. */ + +tree nonlocal_labels; + +/* RTX for stack slot that holds the current handler for nonlocal gotos. + Zero when function does not have nonlocal labels. */ + +rtx nonlocal_goto_handler_slot; + +/* RTX for stack slot that holds the stack pointer value to restore + for a nonlocal goto. + Zero when function does not have nonlocal labels. */ + +rtx nonlocal_goto_stack_level; + +/* Label that will go on parm cleanup code, if any. + Jumping to this label runs cleanup code for parameters, if + such code must be run. Following this code is the logical return label. */ + +rtx cleanup_label; + +/* Label that will go on function epilogue. + Jumping to this label serves as a "return" instruction + on machines which require execution of the epilogue on all returns. */ + +rtx return_label; + +/* List (chain of EXPR_LISTs) of pseudo-regs of SAVE_EXPRs. + So we can mark them all live at the end of the function, if nonopt. */ +rtx save_expr_regs; + +/* List (chain of EXPR_LISTs) of all stack slots in this function. + Made for the sake of unshare_all_rtl. */ +rtx stack_slot_list; + +/* Chain of all RTL_EXPRs that have insns in them. */ +tree rtl_expr_chain; + +/* Label to jump back to for tail recursion, or 0 if we have + not yet needed one for this function. */ +rtx tail_recursion_label; + +/* Place after which to insert the tail_recursion_label if we need one. */ +rtx tail_recursion_reentry; + +/* Location at which to save the argument pointer if it will need to be + referenced. There are two cases where this is done: if nonlocal gotos + exist, or if vars stored at an offset from the argument pointer will be + needed by inner routines. */ + +rtx arg_pointer_save_area; + +/* Offset to end of allocated area of stack frame. + If stack grows down, this is the address of the last stack slot allocated. + If stack grows up, this is the address for the next slot. */ +int frame_offset; + +/* List (chain of TREE_LISTs) of static chains for containing functions. + Each link has a FUNCTION_DECL in the TREE_PURPOSE and a reg rtx + in an RTL_EXPR in the TREE_VALUE. */ +static tree context_display; + +/* List (chain of TREE_LISTs) of trampolines for nested functions. + The trampoline sets up the static chain and jumps to the function. + We supply the trampoline's address when the function's address is requested. + + Each link has a FUNCTION_DECL in the TREE_PURPOSE and a reg rtx + in an RTL_EXPR in the TREE_VALUE. */ +static tree trampoline_list; + +/* Insn after which register parms and SAVE_EXPRs are born, if nonopt. */ +static rtx parm_birth_insn; + +#if 0 +/* Nonzero if a stack slot has been generated whose address is not + actually valid. It means that the generated rtl must all be scanned + to detect and correct the invalid addresses where they occur. */ +static int invalid_stack_slot; +#endif + +/* Last insn of those whose job was to put parms into their nominal homes. */ +static rtx last_parm_insn; + +/* 1 + last pseudo register number used for loading a copy + of a parameter of this function. */ +static int max_parm_reg; + +/* Vector indexed by REGNO, containing location on stack in which + to put the parm which is nominally in pseudo register REGNO, + if we discover that that parm must go in the stack. */ +static rtx *parm_reg_stack_loc; + +#if 0 /* Turned off because 0 seems to work just as well. */ +/* Cleanup lists are required for binding levels regardless of whether + that binding level has cleanups or not. This node serves as the + cleanup list whenever an empty list is required. */ +static tree empty_cleanup_list; +#endif + +/* Nonzero once virtual register instantiation has been done. + assign_stack_local uses frame_pointer_rtx when this is nonzero. */ +static int virtuals_instantiated; + +/* Nonzero if we need to distinguish between the return value of this function + and the return value of a function called by this function. This helps + integrate.c */ + +extern int rtx_equal_function_value_matters; + +void fixup_gotos (); + +static tree round_down (); +static rtx round_trampoline_addr (); +static rtx fixup_stack_1 (); +static void fixup_var_refs (); +static void fixup_var_refs_insns (); +static void fixup_var_refs_1 (); +static void optimize_bit_field (); +static void instantiate_decls (); +static void instantiate_decls_1 (); +static void instantiate_decl (); +static int instantiate_virtual_regs_1 (); +static rtx fixup_memory_subreg (); +static rtx walk_fixup_memory_subreg (); + +/* In order to evaluate some expressions, such as function calls returning + structures in memory, we need to temporarily allocate stack locations. + We record each allocated temporary in the following structure. + + Associated with each temporary slot is a nesting level. When we pop up + one level, all temporaries associated with the previous level are freed. + Normally, all temporaries are freed after the execution of the statement + in which they were created. However, if we are inside a ({...}) grouping, + the result may be in a temporary and hence must be preserved. If the + result could be in a temporary, we preserve it if we can determine which + one it is in. If we cannot determine which temporary may contain the + result, all temporaries are preserved. A temporary is preserved by + pretending it was allocated at the previous nesting level. + + Automatic variables are also assigned temporary slots, at the nesting + level where they are defined. They are marked a "kept" so that + free_temp_slots will not free them. */ + +struct temp_slot +{ + /* Points to next temporary slot. */ + struct temp_slot *next; + /* The rtx to used to reference the slot. */ + rtx slot; + /* The size, in units, of the slot. */ + int size; + /* Non-zero if this temporary is currently in use. */ + char in_use; + /* Nesting level at which this slot is being used. */ + int level; + /* Non-zero if this should survive a call to free_temp_slots. */ + int keep; +}; + +/* List of all temporaries allocated, both available and in use. */ + +struct temp_slot *temp_slots; + +/* Current nesting level for temporaries. */ + +int temp_slot_level; + +/* Pointer to chain of `struct function' for containing functions. */ +struct function *outer_function_chain; + +/* Given a function decl for a containing function, + return the `struct function' for it. */ + +struct function * +find_function_data (decl) + tree decl; +{ + struct function *p; + for (p = outer_function_chain; p; p = p->next) + if (p->decl == decl) + return p; + abort (); +} + +/* Save the current context for compilation of a nested function. + This is called from language-specific code. + The caller is responsible for saving any language-specific status, + since this function knows only about language-independent variables. */ + +void +push_function_context () +{ + struct function *p = (struct function *) xmalloc (sizeof (struct function)); + + p->next = outer_function_chain; + outer_function_chain = p; + + p->name = current_function_name; + p->decl = current_function_decl; + p->pops_args = current_function_pops_args; + p->returns_struct = current_function_returns_struct; + p->returns_pcc_struct = current_function_returns_pcc_struct; + p->needs_context = current_function_needs_context; + p->calls_setjmp = current_function_calls_setjmp; + p->calls_longjmp = current_function_calls_longjmp; + p->calls_alloca = current_function_calls_alloca; + p->has_nonlocal_label = current_function_has_nonlocal_label; + p->args_size = current_function_args_size; + p->pretend_args_size = current_function_pretend_args_size; + p->arg_offset_rtx = current_function_arg_offset_rtx; + p->uses_const_pool = current_function_uses_const_pool; + p->uses_pic_offset_table = current_function_uses_pic_offset_table; + p->internal_arg_pointer = current_function_internal_arg_pointer; + p->max_parm_reg = max_parm_reg; + p->parm_reg_stack_loc = parm_reg_stack_loc; + p->outgoing_args_size = current_function_outgoing_args_size; + p->return_rtx = current_function_return_rtx; + p->nonlocal_goto_handler_slot = nonlocal_goto_handler_slot; + p->nonlocal_goto_stack_level = nonlocal_goto_stack_level; + p->nonlocal_labels = nonlocal_labels; + p->cleanup_label = cleanup_label; + p->return_label = return_label; + p->save_expr_regs = save_expr_regs; + p->stack_slot_list = stack_slot_list; + p->parm_birth_insn = parm_birth_insn; + p->frame_offset = frame_offset; + p->tail_recursion_label = tail_recursion_label; + p->tail_recursion_reentry = tail_recursion_reentry; + p->arg_pointer_save_area = arg_pointer_save_area; + p->rtl_expr_chain = rtl_expr_chain; + p->last_parm_insn = last_parm_insn; + p->context_display = context_display; + p->trampoline_list = trampoline_list; + p->function_call_count = function_call_count; + p->temp_slots = temp_slots; + p->temp_slot_level = temp_slot_level; + p->fixup_var_refs_queue = 0; + p->epilogue_delay_list = current_function_epilogue_delay_list; + + save_tree_status (p); + save_storage_status (p); + save_emit_status (p); + init_emit (); + save_expr_status (p); + save_stmt_status (p); + save_varasm_status (p); +} + +/* Restore the last saved context, at the end of a nested function. + This function is called from language-specific code. */ + +void +pop_function_context () +{ + struct function *p = outer_function_chain; + + outer_function_chain = p->next; + + current_function_name = p->name; + current_function_decl = p->decl; + current_function_pops_args = p->pops_args; + current_function_returns_struct = p->returns_struct; + current_function_returns_pcc_struct = p->returns_pcc_struct; + current_function_needs_context = p->needs_context; + current_function_calls_setjmp = p->calls_setjmp; + current_function_calls_longjmp = p->calls_longjmp; + current_function_calls_alloca = p->calls_alloca; + current_function_has_nonlocal_label = p->has_nonlocal_label; + current_function_contains_functions = 1; + current_function_args_size = p->args_size; + current_function_pretend_args_size = p->pretend_args_size; + current_function_arg_offset_rtx = p->arg_offset_rtx; + current_function_uses_const_pool = p->uses_const_pool; + current_function_uses_pic_offset_table = p->uses_pic_offset_table; + current_function_internal_arg_pointer = p->internal_arg_pointer; + max_parm_reg = p->max_parm_reg; + parm_reg_stack_loc = p->parm_reg_stack_loc; + current_function_outgoing_args_size = p->outgoing_args_size; + current_function_return_rtx = p->return_rtx; + nonlocal_goto_handler_slot = p->nonlocal_goto_handler_slot; + nonlocal_goto_stack_level = p->nonlocal_goto_stack_level; + nonlocal_labels = p->nonlocal_labels; + cleanup_label = p->cleanup_label; + return_label = p->return_label; + save_expr_regs = p->save_expr_regs; + stack_slot_list = p->stack_slot_list; + parm_birth_insn = p->parm_birth_insn; + frame_offset = p->frame_offset; + tail_recursion_label = p->tail_recursion_label; + tail_recursion_reentry = p->tail_recursion_reentry; + arg_pointer_save_area = p->arg_pointer_save_area; + rtl_expr_chain = p->rtl_expr_chain; + last_parm_insn = p->last_parm_insn; + context_display = p->context_display; + trampoline_list = p->trampoline_list; + function_call_count = p->function_call_count; + temp_slots = p->temp_slots; + temp_slot_level = p->temp_slot_level; + current_function_epilogue_delay_list = p->epilogue_delay_list; + + restore_tree_status (p); + restore_storage_status (p); + restore_expr_status (p); + restore_emit_status (p); + restore_stmt_status (p); + restore_varasm_status (p); + + /* Finish doing put_var_into_stack for any of our variables + which became addressable during the nested function. */ + { + struct var_refs_queue *queue = p->fixup_var_refs_queue; + for (; queue; queue = queue->next) + fixup_var_refs (queue->modified, queue->promoted_mode, queue->unsignedp); + } + + free (p); + + /* Reset variables that have known state during rtx generation. */ + rtx_equal_function_value_matters = 1; + virtuals_instantiated = 0; +} + +/* Allocate fixed slots in the stack frame of the current function. */ + +/* Return size needed for stack frame based on slots so far allocated. + This size counts from zero. It is not rounded to STACK_BOUNDARY; + the caller may have to do that. */ + +int +get_frame_size () +{ +#ifdef FRAME_GROWS_DOWNWARD + return -frame_offset; +#else + return frame_offset; +#endif +} + +/* Allocate a stack slot of SIZE bytes and return a MEM rtx for it + with machine mode MODE. + + ALIGN controls the amount of alignment for the address of the slot: + 0 means according to MODE, + -1 means use BIGGEST_ALIGNMENT and round size to multiple of that, + positive specifies alignment boundary in bits. + + We do not round to stack_boundary here. */ + +rtx +assign_stack_local (mode, size, align) + enum machine_mode mode; + int size; + int align; +{ + register rtx x, addr; + int bigend_correction = 0; + int alignment; + + if (align == 0) + { + alignment = GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT; + if (mode == BLKmode) + alignment = BIGGEST_ALIGNMENT / BITS_PER_UNIT; + } + else if (align == -1) + { + alignment = BIGGEST_ALIGNMENT / BITS_PER_UNIT; + size = CEIL_ROUND (size, alignment); + } + else + alignment = align / BITS_PER_UNIT; + + /* Round frame offset to that alignment. + We must be careful here, since FRAME_OFFSET might be negative and + division with a negative dividend isn't as well defined as we might + like. So we instead assume that ALIGNMENT is a power of two and + use logical operations which are unambiguous. */ +#ifdef FRAME_GROWS_DOWNWARD + frame_offset = FLOOR_ROUND (frame_offset, alignment); +#else + frame_offset = CEIL_ROUND (frame_offset, alignment); +#endif + + /* On a big-endian machine, if we are allocating more space than we will use, + use the least significant bytes of those that are allocated. */ +#if BYTES_BIG_ENDIAN + if (mode != BLKmode) + bigend_correction = size - GET_MODE_SIZE (mode); +#endif + +#ifdef FRAME_GROWS_DOWNWARD + frame_offset -= size; +#endif + + /* If we have already instantiated virtual registers, return the actual + address relative to the frame pointer. */ + if (virtuals_instantiated) + addr = plus_constant (frame_pointer_rtx, + (frame_offset + bigend_correction + + STARTING_FRAME_OFFSET)); + else + addr = plus_constant (virtual_stack_vars_rtx, + frame_offset + bigend_correction); + +#ifndef FRAME_GROWS_DOWNWARD + frame_offset += size; +#endif + + x = gen_rtx (MEM, mode, addr); + + stack_slot_list = gen_rtx (EXPR_LIST, VOIDmode, x, stack_slot_list); + + return x; +} + +/* Assign a stack slot in a containing function. + First three arguments are same as in preceding function. + The last argument specifies the function to allocate in. */ + +rtx +assign_outer_stack_local (mode, size, align, function) + enum machine_mode mode; + int size; + int align; + struct function *function; +{ + register rtx x, addr; + int bigend_correction = 0; + int alignment; + + /* Allocate in the memory associated with the function in whose frame + we are assigning. */ + push_obstacks (function->function_obstack, + function->function_maybepermanent_obstack); + + if (align == 0) + { + alignment = GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT; + if (mode == BLKmode) + alignment = BIGGEST_ALIGNMENT / BITS_PER_UNIT; + } + else if (align == -1) + { + alignment = BIGGEST_ALIGNMENT / BITS_PER_UNIT; + size = CEIL_ROUND (size, alignment); + } + else + alignment = align / BITS_PER_UNIT; + + /* Round frame offset to that alignment. */ +#ifdef FRAME_GROWS_DOWNWARD + function->frame_offset = FLOOR_ROUND (function->frame_offset, alignment); +#else + function->frame_offset = CEIL_ROUND (function->frame_offset, alignment); +#endif + + /* On a big-endian machine, if we are allocating more space than we will use, + use the least significant bytes of those that are allocated. */ +#if BYTES_BIG_ENDIAN + if (mode != BLKmode) + bigend_correction = size - GET_MODE_SIZE (mode); +#endif + +#ifdef FRAME_GROWS_DOWNWARD + function->frame_offset -= size; +#endif + addr = plus_constant (virtual_stack_vars_rtx, + function->frame_offset + bigend_correction); +#ifndef FRAME_GROWS_DOWNWARD + function->frame_offset += size; +#endif + + x = gen_rtx (MEM, mode, addr); + + function->stack_slot_list + = gen_rtx (EXPR_LIST, VOIDmode, x, function->stack_slot_list); + + pop_obstacks (); + + return x; +} + +/* Allocate a temporary stack slot and record it for possible later + reuse. + + MODE is the machine mode to be given to the returned rtx. + + SIZE is the size in units of the space required. We do no rounding here + since assign_stack_local will do any required rounding. + + KEEP is non-zero if this slot is to be retained after a call to + free_temp_slots. Automatic variables for a block are allocated with this + flag. */ + +rtx +assign_stack_temp (mode, size, keep) + enum machine_mode mode; + int size; + int keep; +{ + struct temp_slot *p, *best_p = 0; + + /* First try to find an available, already-allocated temporary that is the + exact size we require. */ + for (p = temp_slots; p; p = p->next) + if (p->size == size && GET_MODE (p->slot) == mode && ! p->in_use) + break; + + /* If we didn't find, one, try one that is larger than what we want. We + find the smallest such. */ + if (p == 0) + for (p = temp_slots; p; p = p->next) + if (p->size > size && GET_MODE (p->slot) == mode && ! p->in_use + && (best_p == 0 || best_p->size > p->size)) + best_p = p; + + /* Make our best, if any, the one to use. */ + if (best_p) + p = best_p; + + /* If we still didn't find one, make a new temporary. */ + if (p == 0) + { + p = (struct temp_slot *) oballoc (sizeof (struct temp_slot)); + p->size = size; + /* If the temp slot mode doesn't indicate the alignment, + use the largest possible, so no one will be disappointed. */ + p->slot = assign_stack_local (mode, size, mode == BLKmode ? -1 : 0); + p->next = temp_slots; + temp_slots = p; + } + + p->in_use = 1; + p->level = temp_slot_level; + p->keep = keep; + return p->slot; +} + +/* If X could be a reference to a temporary slot, mark that slot as belonging + to the to one level higher. If X matched one of our slots, just mark that + one. Otherwise, we can't easily predict which it is, so upgrade all of + them. Kept slots need not be touched. + + This is called when an ({...}) construct occurs and a statement + returns a value in memory. */ + +void +preserve_temp_slots (x) + rtx x; +{ + struct temp_slot *p; + + /* If X is not in memory or is at a constant address, it cannot be in + a temporary slot. */ + if (x == 0 || GET_CODE (x) != MEM || CONSTANT_P (XEXP (x, 0))) + return; + + /* First see if we can find a match. */ + for (p = temp_slots; p; p = p->next) + if (p->in_use && x == p->slot) + { + p->level--; + return; + } + + /* Otherwise, preserve all non-kept slots at this level. */ + for (p = temp_slots; p; p = p->next) + if (p->in_use && p->level == temp_slot_level && ! p->keep) + p->level--; +} + +/* Free all temporaries used so far. This is normally called at the end + of generating code for a statement. */ + +void +free_temp_slots () +{ + struct temp_slot *p; + + for (p = temp_slots; p; p = p->next) + if (p->in_use && p->level == temp_slot_level && ! p->keep) + p->in_use = 0; +} + +/* Push deeper into the nesting level for stack temporaries. */ + +void +push_temp_slots () +{ + /* For GNU C++, we must allow a sequence to be emitted anywhere in + the level where the sequence was started. By not changing levels + when the compiler is inside a sequence, the temporaries for the + sequence and the temporaries will not unwittingly conflict with + the temporaries for other sequences and/or code at that level. */ + if (in_sequence_p ()) + return; + + temp_slot_level++; +} + +/* Pop a temporary nesting level. All slots in use in the current level + are freed. */ + +void +pop_temp_slots () +{ + struct temp_slot *p; + + /* See comment in push_temp_slots about why we don't change levels + in sequences. */ + if (in_sequence_p ()) + return; + + for (p = temp_slots; p; p = p->next) + if (p->in_use && p->level == temp_slot_level) + p->in_use = 0; + + temp_slot_level--; +} + +/* Retroactively move an auto variable from a register to a stack slot. + This is done when an address-reference to the variable is seen. */ + +void +put_var_into_stack (decl) + tree decl; +{ + register rtx reg; + register rtx new = 0; + enum machine_mode promoted_mode, decl_mode; + struct function *function = 0; + tree context = decl_function_context (decl); + + /* Get the current rtl used for this object and it's original mode. */ + reg = TREE_CODE (decl) == SAVE_EXPR ? SAVE_EXPR_RTL (decl) : DECL_RTL (decl); + + /* No need to do anything if decl has no rtx yet + since in that case caller is setting TREE_ADDRESSABLE + and a stack slot will be assigned when the rtl is made. */ + if (reg == 0) + return; + + /* Get the declared mode for this object. */ + decl_mode = (TREE_CODE (decl) == SAVE_EXPR ? TYPE_MODE (TREE_TYPE (decl)) + : DECL_MODE (decl)); + /* Get the mode it's actually stored in. */ + promoted_mode = GET_MODE (reg); + + /* If this variable comes from an outer function, + find that function's saved context. */ + if (context != current_function_decl) + for (function = outer_function_chain; function; function = function->next) + if (function->decl == context) + break; + + /* If this is a variable-size object with a pseudo to address it, + put that pseudo into the stack, if the var is nonlocal. */ + if (DECL_NONLOCAL (decl) + && GET_CODE (reg) == MEM + && GET_CODE (XEXP (reg, 0)) == REG + && REGNO (XEXP (reg, 0)) > LAST_VIRTUAL_REGISTER) + { + reg = XEXP (reg, 0); + decl_mode = promoted_mode = GET_MODE (reg); + } + + if (GET_CODE (reg) != REG) + return; + + if (function) + { + if (REGNO (reg) < function->max_parm_reg) + new = function->parm_reg_stack_loc[REGNO (reg)]; + if (new == 0) + new = assign_outer_stack_local (decl_mode, GET_MODE_SIZE (decl_mode), + 0, function); + } + else + { + if (REGNO (reg) < max_parm_reg) + new = parm_reg_stack_loc[REGNO (reg)]; + if (new == 0) + new = assign_stack_local (decl_mode, GET_MODE_SIZE (decl_mode), 0); + } + + XEXP (reg, 0) = XEXP (new, 0); + /* `volatil' bit means one thing for MEMs, another entirely for REGs. */ + REG_USERVAR_P (reg) = 0; + PUT_CODE (reg, MEM); + PUT_MODE (reg, decl_mode); + + /* If this is a memory ref that contains aggregate components, + mark it as such for cse and loop optimize. */ + MEM_IN_STRUCT_P (reg) + = (TREE_CODE (TREE_TYPE (decl)) == ARRAY_TYPE + || TREE_CODE (TREE_TYPE (decl)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (decl)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (decl)) == QUAL_UNION_TYPE); + + /* Now make sure that all refs to the variable, previously made + when it was a register, are fixed up to be valid again. */ + if (function) + { + struct var_refs_queue *temp; + + /* Variable is inherited; fix it up when we get back to its function. */ + push_obstacks (function->function_obstack, + function->function_maybepermanent_obstack); + temp + = (struct var_refs_queue *) oballoc (sizeof (struct var_refs_queue)); + temp->modified = reg; + temp->promoted_mode = promoted_mode; + temp->unsignedp = TREE_UNSIGNED (TREE_TYPE (decl)); + temp->next = function->fixup_var_refs_queue; + function->fixup_var_refs_queue = temp; + pop_obstacks (); + } + else + /* Variable is local; fix it up now. */ + fixup_var_refs (reg, promoted_mode, TREE_UNSIGNED (TREE_TYPE (decl))); +} + +static void +fixup_var_refs (var, promoted_mode, unsignedp) + rtx var; + enum machine_mode promoted_mode; + int unsignedp; +{ + tree pending; + rtx first_insn = get_insns (); + struct sequence_stack *stack = sequence_stack; + tree rtl_exps = rtl_expr_chain; + + /* Must scan all insns for stack-refs that exceed the limit. */ + fixup_var_refs_insns (var, promoted_mode, unsignedp, first_insn, stack == 0); + + /* Scan all pending sequences too. */ + for (; stack; stack = stack->next) + { + push_to_sequence (stack->first); + fixup_var_refs_insns (var, promoted_mode, unsignedp, + stack->first, stack->next != 0); + /* Update remembered end of sequence + in case we added an insn at the end. */ + stack->last = get_last_insn (); + end_sequence (); + } + + /* Scan all waiting RTL_EXPRs too. */ + for (pending = rtl_exps; pending; pending = TREE_CHAIN (pending)) + { + rtx seq = RTL_EXPR_SEQUENCE (TREE_VALUE (pending)); + if (seq != const0_rtx && seq != 0) + { + push_to_sequence (seq); + fixup_var_refs_insns (var, promoted_mode, unsignedp, seq, 0); + end_sequence (); + } + } +} + +/* This structure is used by the following two functions to record MEMs or + pseudos used to replace VAR, any SUBREGs of VAR, and any MEMs containing + VAR as an address. We need to maintain this list in case two operands of + an insn were required to match; in that case we must ensure we use the + same replacement. */ + +struct fixup_replacement +{ + rtx old; + rtx new; + struct fixup_replacement *next; +}; + +/* REPLACEMENTS is a pointer to a list of the above structures and X is + some part of an insn. Return a struct fixup_replacement whose OLD + value is equal to X. Allocate a new structure if no such entry exists. */ + +static struct fixup_replacement * +find_fixup_replacement (replacements, x) + struct fixup_replacement **replacements; + rtx x; +{ + struct fixup_replacement *p; + + /* See if we have already replaced this. */ + for (p = *replacements; p && p->old != x; p = p->next) + ; + + if (p == 0) + { + p = (struct fixup_replacement *) oballoc (sizeof (struct fixup_replacement)); + p->old = x; + p->new = 0; + p->next = *replacements; + *replacements = p; + } + + return p; +} + +/* Scan the insn-chain starting with INSN for refs to VAR + and fix them up. TOPLEVEL is nonzero if this chain is the + main chain of insns for the current function. */ + +static void +fixup_var_refs_insns (var, promoted_mode, unsignedp, insn, toplevel) + rtx var; + enum machine_mode promoted_mode; + int unsignedp; + rtx insn; + int toplevel; +{ + rtx call_dest = 0; + + while (insn) + { + rtx next = NEXT_INSN (insn); + rtx note; + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + /* The insn to load VAR from a home in the arglist + is now a no-op. When we see it, just delete it. */ + if (toplevel + && GET_CODE (PATTERN (insn)) == SET + && SET_DEST (PATTERN (insn)) == var + /* If this represents the result of an insn group, + don't delete the insn. */ + && find_reg_note (insn, REG_RETVAL, NULL_RTX) == 0 + && rtx_equal_p (SET_SRC (PATTERN (insn)), var)) + { + /* In unoptimized compilation, we shouldn't call delete_insn + except in jump.c doing warnings. */ + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + if (insn == last_parm_insn) + last_parm_insn = PREV_INSN (next); + } + else + { + struct fixup_replacement *replacements = 0; + rtx next_insn = NEXT_INSN (insn); + +#ifdef SMALL_REGISTER_CLASSES + /* If the insn that copies the results of a CALL_INSN + into a pseudo now references VAR, we have to use an + intermediate pseudo since we want the life of the + return value register to be only a single insn. + + If we don't use an intermediate pseudo, such things as + address computations to make the address of VAR valid + if it is not can be placed beween the CALL_INSN and INSN. + + To make sure this doesn't happen, we record the destination + of the CALL_INSN and see if the next insn uses both that + and VAR. */ + + if (call_dest != 0 && GET_CODE (insn) == INSN + && reg_mentioned_p (var, PATTERN (insn)) + && reg_mentioned_p (call_dest, PATTERN (insn))) + { + rtx temp = gen_reg_rtx (GET_MODE (call_dest)); + + emit_insn_before (gen_move_insn (temp, call_dest), insn); + + PATTERN (insn) = replace_rtx (PATTERN (insn), + call_dest, temp); + } + + if (GET_CODE (insn) == CALL_INSN + && GET_CODE (PATTERN (insn)) == SET) + call_dest = SET_DEST (PATTERN (insn)); + else if (GET_CODE (insn) == CALL_INSN + && GET_CODE (PATTERN (insn)) == PARALLEL + && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) + call_dest = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); + else + call_dest = 0; +#endif + + /* See if we have to do anything to INSN now that VAR is in + memory. If it needs to be loaded into a pseudo, use a single + pseudo for the entire insn in case there is a MATCH_DUP + between two operands. We pass a pointer to the head of + a list of struct fixup_replacements. If fixup_var_refs_1 + needs to allocate pseudos or replacement MEMs (for SUBREGs), + it will record them in this list. + + If it allocated a pseudo for any replacement, we copy into + it here. */ + + fixup_var_refs_1 (var, promoted_mode, &PATTERN (insn), insn, + &replacements); + + /* If this is last_parm_insn, and any instructions were output + after it to fix it up, then we must set last_parm_insn to + the last such instruction emitted. */ + if (insn == last_parm_insn) + last_parm_insn = PREV_INSN (next_insn); + + while (replacements) + { + if (GET_CODE (replacements->new) == REG) + { + rtx insert_before; + rtx seq; + + /* OLD might be a (subreg (mem)). */ + if (GET_CODE (replacements->old) == SUBREG) + replacements->old + = fixup_memory_subreg (replacements->old, insn, 0); + else + replacements->old + = fixup_stack_1 (replacements->old, insn); + + /* We can not separate USE insns from the CALL_INSN + that they belong to. If this is a CALL_INSN, insert + the move insn before the USE insns preceding it + instead of immediately before the insn. */ + if (GET_CODE (insn) == CALL_INSN) + { + insert_before = insn; + while (GET_CODE (PREV_INSN (insert_before)) == INSN + && GET_CODE (PATTERN (PREV_INSN (insert_before))) == USE) + insert_before = PREV_INSN (insert_before); + } + else + insert_before = insn; + + /* If we are changing the mode, do a conversion. + This might be wasteful, but combine.c will + eliminate much of the waste. */ + + if (GET_MODE (replacements->new) + != GET_MODE (replacements->old)) + { + start_sequence (); + convert_move (replacements->new, + replacements->old, unsignedp); + seq = gen_sequence (); + end_sequence (); + } + else + seq = gen_move_insn (replacements->new, + replacements->old); + + emit_insn_before (seq, insert_before); + } + + replacements = replacements->next; + } + } + + /* Also fix up any invalid exprs in the REG_NOTES of this insn. + But don't touch other insns referred to by reg-notes; + we will get them elsewhere. */ + for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) + if (GET_CODE (note) != INSN_LIST) + XEXP (note, 0) + = walk_fixup_memory_subreg (XEXP (note, 0), insn, 1); + } + insn = next; + } +} + +/* VAR is a MEM that used to be a pseudo register with mode PROMOTED_MODE. + See if the rtx expression at *LOC in INSN needs to be changed. + + REPLACEMENTS is a pointer to a list head that starts out zero, but may + contain a list of original rtx's and replacements. If we find that we need + to modify this insn by replacing a memory reference with a pseudo or by + making a new MEM to implement a SUBREG, we consult that list to see if + we have already chosen a replacement. If none has already been allocated, + we allocate it and update the list. fixup_var_refs_insns will copy VAR + or the SUBREG, as appropriate, to the pseudo. */ + +static void +fixup_var_refs_1 (var, promoted_mode, loc, insn, replacements) + register rtx var; + enum machine_mode promoted_mode; + register rtx *loc; + rtx insn; + struct fixup_replacement **replacements; +{ + register int i; + register rtx x = *loc; + RTX_CODE code = GET_CODE (x); + register char *fmt; + register rtx tem, tem1; + struct fixup_replacement *replacement; + + switch (code) + { + case MEM: + if (var == x) + { + /* If we already have a replacement, use it. Otherwise, + try to fix up this address in case it is invalid. */ + + replacement = find_fixup_replacement (replacements, var); + if (replacement->new) + { + *loc = replacement->new; + return; + } + + *loc = replacement->new = x = fixup_stack_1 (x, insn); + + /* Unless we are forcing memory to register or we changed the mode, + we can leave things the way they are if the insn is valid. */ + + INSN_CODE (insn) = -1; + if (! flag_force_mem && GET_MODE (x) == promoted_mode + && recog_memoized (insn) >= 0) + return; + + *loc = replacement->new = gen_reg_rtx (promoted_mode); + return; + } + + /* If X contains VAR, we need to unshare it here so that we update + each occurrence separately. But all identical MEMs in one insn + must be replaced with the same rtx because of the possibility of + MATCH_DUPs. */ + + if (reg_mentioned_p (var, x)) + { + replacement = find_fixup_replacement (replacements, x); + if (replacement->new == 0) + replacement->new = copy_most_rtx (x, var); + + *loc = x = replacement->new; + } + break; + + case REG: + case CC0: + case PC: + case CONST_INT: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + case CONST_DOUBLE: + return; + + case SIGN_EXTRACT: + case ZERO_EXTRACT: + /* Note that in some cases those types of expressions are altered + by optimize_bit_field, and do not survive to get here. */ + if (XEXP (x, 0) == var + || (GET_CODE (XEXP (x, 0)) == SUBREG + && SUBREG_REG (XEXP (x, 0)) == var)) + { + /* Get TEM as a valid MEM in the mode presently in the insn. + + We don't worry about the possibility of MATCH_DUP here; it + is highly unlikely and would be tricky to handle. */ + + tem = XEXP (x, 0); + if (GET_CODE (tem) == SUBREG) + tem = fixup_memory_subreg (tem, insn, 1); + tem = fixup_stack_1 (tem, insn); + + /* Unless we want to load from memory, get TEM into the proper mode + for an extract from memory. This can only be done if the + extract is at a constant position and length. */ + + if (! flag_force_mem && GET_CODE (XEXP (x, 1)) == CONST_INT + && GET_CODE (XEXP (x, 2)) == CONST_INT + && ! mode_dependent_address_p (XEXP (tem, 0)) + && ! MEM_VOLATILE_P (tem)) + { + enum machine_mode wanted_mode = VOIDmode; + enum machine_mode is_mode = GET_MODE (tem); + int width = INTVAL (XEXP (x, 1)); + int pos = INTVAL (XEXP (x, 2)); + +#ifdef HAVE_extzv + if (GET_CODE (x) == ZERO_EXTRACT) + wanted_mode = insn_operand_mode[(int) CODE_FOR_extzv][1]; +#endif +#ifdef HAVE_extv + if (GET_CODE (x) == SIGN_EXTRACT) + wanted_mode = insn_operand_mode[(int) CODE_FOR_extv][1]; +#endif + /* If we have a narrower mode, we can do something. */ + if (wanted_mode != VOIDmode + && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode)) + { + int offset = pos / BITS_PER_UNIT; + rtx old_pos = XEXP (x, 2); + rtx newmem; + + /* If the bytes and bits are counted differently, we + must adjust the offset. */ +#if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN + offset = (GET_MODE_SIZE (is_mode) + - GET_MODE_SIZE (wanted_mode) - offset); +#endif + + pos %= GET_MODE_BITSIZE (wanted_mode); + + newmem = gen_rtx (MEM, wanted_mode, + plus_constant (XEXP (tem, 0), offset)); + RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (tem); + MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (tem); + MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (tem); + + /* Make the change and see if the insn remains valid. */ + INSN_CODE (insn) = -1; + XEXP (x, 0) = newmem; + XEXP (x, 2) = GEN_INT (pos); + + if (recog_memoized (insn) >= 0) + return; + + /* Otherwise, restore old position. XEXP (x, 0) will be + restored later. */ + XEXP (x, 2) = old_pos; + } + } + + /* If we get here, the bitfield extract insn can't accept a memory + reference. Copy the input into a register. */ + + tem1 = gen_reg_rtx (GET_MODE (tem)); + emit_insn_before (gen_move_insn (tem1, tem), insn); + XEXP (x, 0) = tem1; + return; + } + break; + + case SUBREG: + if (SUBREG_REG (x) == var) + { + /* If this is a special SUBREG made because VAR was promoted + from a wider mode, replace it with VAR and call ourself + recursively, this time saying that the object previously + had its current mode (by virtue of the SUBREG). */ + + if (SUBREG_PROMOTED_VAR_P (x)) + { + *loc = var; + fixup_var_refs_1 (var, GET_MODE (var), loc, insn, replacements); + return; + } + + /* If this SUBREG makes VAR wider, it has become a paradoxical + SUBREG with VAR in memory, but these aren't allowed at this + stage of the compilation. So load VAR into a pseudo and take + a SUBREG of that pseudo. */ + if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (var))) + { + replacement = find_fixup_replacement (replacements, var); + if (replacement->new == 0) + replacement->new = gen_reg_rtx (GET_MODE (var)); + SUBREG_REG (x) = replacement->new; + return; + } + + /* See if we have already found a replacement for this SUBREG. + If so, use it. Otherwise, make a MEM and see if the insn + is recognized. If not, or if we should force MEM into a register, + make a pseudo for this SUBREG. */ + replacement = find_fixup_replacement (replacements, x); + if (replacement->new) + { + *loc = replacement->new; + return; + } + + replacement->new = *loc = fixup_memory_subreg (x, insn, 0); + + INSN_CODE (insn) = -1; + if (! flag_force_mem && recog_memoized (insn) >= 0) + return; + + *loc = replacement->new = gen_reg_rtx (GET_MODE (x)); + return; + } + break; + + case SET: + /* First do special simplification of bit-field references. */ + if (GET_CODE (SET_DEST (x)) == SIGN_EXTRACT + || GET_CODE (SET_DEST (x)) == ZERO_EXTRACT) + optimize_bit_field (x, insn, 0); + if (GET_CODE (SET_SRC (x)) == SIGN_EXTRACT + || GET_CODE (SET_SRC (x)) == ZERO_EXTRACT) + optimize_bit_field (x, insn, NULL_PTR); + + /* If SET_DEST is now a paradoxical SUBREG, put the result of this + insn into a pseudo and store the low part of the pseudo into VAR. */ + if (GET_CODE (SET_DEST (x)) == SUBREG + && SUBREG_REG (SET_DEST (x)) == var + && (GET_MODE_SIZE (GET_MODE (SET_DEST (x))) + > GET_MODE_SIZE (GET_MODE (var)))) + { + SET_DEST (x) = tem = gen_reg_rtx (GET_MODE (SET_DEST (x))); + emit_insn_after (gen_move_insn (var, gen_lowpart (GET_MODE (var), + tem)), + insn); + break; + } + + { + rtx dest = SET_DEST (x); + rtx src = SET_SRC (x); + rtx outerdest = dest; + + while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART + || GET_CODE (dest) == SIGN_EXTRACT + || GET_CODE (dest) == ZERO_EXTRACT) + dest = XEXP (dest, 0); + + if (GET_CODE (src) == SUBREG) + src = XEXP (src, 0); + + /* If VAR does not appear at the top level of the SET + just scan the lower levels of the tree. */ + + if (src != var && dest != var) + break; + + /* We will need to rerecognize this insn. */ + INSN_CODE (insn) = -1; + +#ifdef HAVE_insv + if (GET_CODE (outerdest) == ZERO_EXTRACT && dest == var) + { + /* Since this case will return, ensure we fixup all the + operands here. */ + fixup_var_refs_1 (var, promoted_mode, &XEXP (outerdest, 1), + insn, replacements); + fixup_var_refs_1 (var, promoted_mode, &XEXP (outerdest, 2), + insn, replacements); + fixup_var_refs_1 (var, promoted_mode, &SET_SRC (x), + insn, replacements); + + tem = XEXP (outerdest, 0); + + /* Clean up (SUBREG:SI (MEM:mode ...) 0) + that may appear inside a ZERO_EXTRACT. + This was legitimate when the MEM was a REG. */ + if (GET_CODE (tem) == SUBREG + && SUBREG_REG (tem) == var) + tem = fixup_memory_subreg (tem, insn, 1); + else + tem = fixup_stack_1 (tem, insn); + + if (GET_CODE (XEXP (outerdest, 1)) == CONST_INT + && GET_CODE (XEXP (outerdest, 2)) == CONST_INT + && ! mode_dependent_address_p (XEXP (tem, 0)) + && ! MEM_VOLATILE_P (tem)) + { + enum machine_mode wanted_mode + = insn_operand_mode[(int) CODE_FOR_insv][0]; + enum machine_mode is_mode = GET_MODE (tem); + int width = INTVAL (XEXP (outerdest, 1)); + int pos = INTVAL (XEXP (outerdest, 2)); + + /* If we have a narrower mode, we can do something. */ + if (GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode)) + { + int offset = pos / BITS_PER_UNIT; + rtx old_pos = XEXP (outerdest, 2); + rtx newmem; + +#if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN + offset = (GET_MODE_SIZE (is_mode) + - GET_MODE_SIZE (wanted_mode) - offset); +#endif + + pos %= GET_MODE_BITSIZE (wanted_mode); + + newmem = gen_rtx (MEM, wanted_mode, + plus_constant (XEXP (tem, 0), offset)); + RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (tem); + MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (tem); + MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (tem); + + /* Make the change and see if the insn remains valid. */ + INSN_CODE (insn) = -1; + XEXP (outerdest, 0) = newmem; + XEXP (outerdest, 2) = GEN_INT (pos); + + if (recog_memoized (insn) >= 0) + return; + + /* Otherwise, restore old position. XEXP (x, 0) will be + restored later. */ + XEXP (outerdest, 2) = old_pos; + } + } + + /* If we get here, the bit-field store doesn't allow memory + or isn't located at a constant position. Load the value into + a register, do the store, and put it back into memory. */ + + tem1 = gen_reg_rtx (GET_MODE (tem)); + emit_insn_before (gen_move_insn (tem1, tem), insn); + emit_insn_after (gen_move_insn (tem, tem1), insn); + XEXP (outerdest, 0) = tem1; + return; + } +#endif + + /* STRICT_LOW_PART is a no-op on memory references + and it can cause combinations to be unrecognizable, + so eliminate it. */ + + if (dest == var && GET_CODE (SET_DEST (x)) == STRICT_LOW_PART) + SET_DEST (x) = XEXP (SET_DEST (x), 0); + + /* A valid insn to copy VAR into or out of a register + must be left alone, to avoid an infinite loop here. + If the reference to VAR is by a subreg, fix that up, + since SUBREG is not valid for a memref. + Also fix up the address of the stack slot. + + Note that we must not try to recognize the insn until + after we know that we have valid addresses and no + (subreg (mem ...) ...) constructs, since these interfere + with determining the validity of the insn. */ + + if ((SET_SRC (x) == var + || (GET_CODE (SET_SRC (x)) == SUBREG + && SUBREG_REG (SET_SRC (x)) == var)) + && (GET_CODE (SET_DEST (x)) == REG + || (GET_CODE (SET_DEST (x)) == SUBREG + && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)) + && x == single_set (PATTERN (insn))) + { + rtx pat; + + replacement = find_fixup_replacement (replacements, SET_SRC (x)); + if (replacement->new) + SET_SRC (x) = replacement->new; + else if (GET_CODE (SET_SRC (x)) == SUBREG) + SET_SRC (x) = replacement->new + = fixup_memory_subreg (SET_SRC (x), insn, 0); + else + SET_SRC (x) = replacement->new + = fixup_stack_1 (SET_SRC (x), insn); + + if (recog_memoized (insn) >= 0) + return; + + /* INSN is not valid, but we know that we want to + copy SET_SRC (x) to SET_DEST (x) in some way. So + we generate the move and see whether it requires more + than one insn. If it does, we emit those insns and + delete INSN. Otherwise, we an just replace the pattern + of INSN; we have already verified above that INSN has + no other function that to do X. */ + + pat = gen_move_insn (SET_DEST (x), SET_SRC (x)); + if (GET_CODE (pat) == SEQUENCE) + { + emit_insn_after (pat, insn); + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + else + PATTERN (insn) = pat; + + return; + } + + if ((SET_DEST (x) == var + || (GET_CODE (SET_DEST (x)) == SUBREG + && SUBREG_REG (SET_DEST (x)) == var)) + && (GET_CODE (SET_SRC (x)) == REG + || (GET_CODE (SET_SRC (x)) == SUBREG + && GET_CODE (SUBREG_REG (SET_SRC (x))) == REG)) + && x == single_set (PATTERN (insn))) + { + rtx pat; + + if (GET_CODE (SET_DEST (x)) == SUBREG) + SET_DEST (x) = fixup_memory_subreg (SET_DEST (x), insn, 0); + else + SET_DEST (x) = fixup_stack_1 (SET_DEST (x), insn); + + if (recog_memoized (insn) >= 0) + return; + + pat = gen_move_insn (SET_DEST (x), SET_SRC (x)); + if (GET_CODE (pat) == SEQUENCE) + { + emit_insn_after (pat, insn); + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + else + PATTERN (insn) = pat; + + return; + } + + /* Otherwise, storing into VAR must be handled specially + by storing into a temporary and copying that into VAR + with a new insn after this one. Note that this case + will be used when storing into a promoted scalar since + the insn will now have different modes on the input + and output and hence will be invalid (except for the case + of setting it to a constant, which does not need any + change if it is valid). We generate extra code in that case, + but combine.c will eliminate it. */ + + if (dest == var) + { + rtx temp; + rtx fixeddest = SET_DEST (x); + + /* STRICT_LOW_PART can be discarded, around a MEM. */ + if (GET_CODE (fixeddest) == STRICT_LOW_PART) + fixeddest = XEXP (fixeddest, 0); + /* Convert (SUBREG (MEM)) to a MEM in a changed mode. */ + if (GET_CODE (fixeddest) == SUBREG) + fixeddest = fixup_memory_subreg (fixeddest, insn, 0); + else + fixeddest = fixup_stack_1 (fixeddest, insn); + + temp = gen_reg_rtx (GET_MODE (SET_SRC (x)) == VOIDmode + ? GET_MODE (fixeddest) + : GET_MODE (SET_SRC (x))); + + emit_insn_after (gen_move_insn (fixeddest, + gen_lowpart (GET_MODE (fixeddest), + temp)), + insn); + + SET_DEST (x) = temp; + } + } + } + + /* Nothing special about this RTX; fix its operands. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + fixup_var_refs_1 (var, promoted_mode, &XEXP (x, i), insn, replacements); + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + fixup_var_refs_1 (var, promoted_mode, &XVECEXP (x, i, j), + insn, replacements); + } + } +} + +/* Given X, an rtx of the form (SUBREG:m1 (MEM:m2 addr)), + return an rtx (MEM:m1 newaddr) which is equivalent. + If any insns must be emitted to compute NEWADDR, put them before INSN. + + UNCRITICAL nonzero means accept paradoxical subregs. + This is used for subregs found inside of ZERO_EXTRACTs and in REG_NOTES. */ + +static rtx +fixup_memory_subreg (x, insn, uncritical) + rtx x; + rtx insn; + int uncritical; +{ + int offset = SUBREG_WORD (x) * UNITS_PER_WORD; + rtx addr = XEXP (SUBREG_REG (x), 0); + enum machine_mode mode = GET_MODE (x); + rtx saved, result; + + /* Paradoxical SUBREGs are usually invalid during RTL generation. */ + if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) + && ! uncritical) + abort (); + +#if BYTES_BIG_ENDIAN + offset += (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) + - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); +#endif + addr = plus_constant (addr, offset); + if (!flag_force_addr && memory_address_p (mode, addr)) + /* Shortcut if no insns need be emitted. */ + return change_address (SUBREG_REG (x), mode, addr); + start_sequence (); + result = change_address (SUBREG_REG (x), mode, addr); + emit_insn_before (gen_sequence (), insn); + end_sequence (); + return result; +} + +/* Do fixup_memory_subreg on all (SUBREG (MEM ...) ...) contained in X. + Replace subexpressions of X in place. + If X itself is a (SUBREG (MEM ...) ...), return the replacement expression. + Otherwise return X, with its contents possibly altered. + + If any insns must be emitted to compute NEWADDR, put them before INSN. + + UNCRITICAL is as in fixup_memory_subreg. */ + +static rtx +walk_fixup_memory_subreg (x, insn, uncritical) + register rtx x; + rtx insn; + int uncritical; +{ + register enum rtx_code code; + register char *fmt; + register int i; + + if (x == 0) + return 0; + + code = GET_CODE (x); + + if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM) + return fixup_memory_subreg (x, insn, uncritical); + + /* Nothing special about this RTX; fix its operands. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + XEXP (x, i) = walk_fixup_memory_subreg (XEXP (x, i), insn, uncritical); + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + XVECEXP (x, i, j) + = walk_fixup_memory_subreg (XVECEXP (x, i, j), insn, uncritical); + } + } + return x; +} + +#if 0 +/* Fix up any references to stack slots that are invalid memory addresses + because they exceed the maximum range of a displacement. */ + +void +fixup_stack_slots () +{ + register rtx insn; + + /* Did we generate a stack slot that is out of range + or otherwise has an invalid address? */ + if (invalid_stack_slot) + { + /* Yes. Must scan all insns for stack-refs that exceed the limit. */ + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN + || GET_CODE (insn) == JUMP_INSN) + fixup_stack_1 (PATTERN (insn), insn); + } +} +#endif + +/* For each memory ref within X, if it refers to a stack slot + with an out of range displacement, put the address in a temp register + (emitting new insns before INSN to load these registers) + and alter the memory ref to use that register. + Replace each such MEM rtx with a copy, to avoid clobberage. */ + +static rtx +fixup_stack_1 (x, insn) + rtx x; + rtx insn; +{ + register int i; + register RTX_CODE code = GET_CODE (x); + register char *fmt; + + if (code == MEM) + { + register rtx ad = XEXP (x, 0); + /* If we have address of a stack slot but it's not valid + (displacement is too large), compute the sum in a register. */ + if (GET_CODE (ad) == PLUS + && GET_CODE (XEXP (ad, 0)) == REG + && REGNO (XEXP (ad, 0)) >= FIRST_VIRTUAL_REGISTER + && REGNO (XEXP (ad, 0)) <= LAST_VIRTUAL_REGISTER + && GET_CODE (XEXP (ad, 1)) == CONST_INT) + { + rtx temp, seq; + if (memory_address_p (GET_MODE (x), ad)) + return x; + + start_sequence (); + temp = copy_to_reg (ad); + seq = gen_sequence (); + end_sequence (); + emit_insn_before (seq, insn); + return change_address (x, VOIDmode, temp); + } + return x; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + XEXP (x, i) = fixup_stack_1 (XEXP (x, i), insn); + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + XVECEXP (x, i, j) = fixup_stack_1 (XVECEXP (x, i, j), insn); + } + } + return x; +} + +/* Optimization: a bit-field instruction whose field + happens to be a byte or halfword in memory + can be changed to a move instruction. + + We call here when INSN is an insn to examine or store into a bit-field. + BODY is the SET-rtx to be altered. + + EQUIV_MEM is the table `reg_equiv_mem' if that is available; else 0. + (Currently this is called only from function.c, and EQUIV_MEM + is always 0.) */ + +static void +optimize_bit_field (body, insn, equiv_mem) + rtx body; + rtx insn; + rtx *equiv_mem; +{ + register rtx bitfield; + int destflag; + rtx seq = 0; + enum machine_mode mode; + + if (GET_CODE (SET_DEST (body)) == SIGN_EXTRACT + || GET_CODE (SET_DEST (body)) == ZERO_EXTRACT) + bitfield = SET_DEST (body), destflag = 1; + else + bitfield = SET_SRC (body), destflag = 0; + + /* First check that the field being stored has constant size and position + and is in fact a byte or halfword suitably aligned. */ + + if (GET_CODE (XEXP (bitfield, 1)) == CONST_INT + && GET_CODE (XEXP (bitfield, 2)) == CONST_INT + && ((mode = mode_for_size (INTVAL (XEXP (bitfield, 1)), MODE_INT, 1)) + != BLKmode) + && INTVAL (XEXP (bitfield, 2)) % INTVAL (XEXP (bitfield, 1)) == 0) + { + register rtx memref = 0; + + /* Now check that the containing word is memory, not a register, + and that it is safe to change the machine mode. */ + + if (GET_CODE (XEXP (bitfield, 0)) == MEM) + memref = XEXP (bitfield, 0); + else if (GET_CODE (XEXP (bitfield, 0)) == REG + && equiv_mem != 0) + memref = equiv_mem[REGNO (XEXP (bitfield, 0))]; + else if (GET_CODE (XEXP (bitfield, 0)) == SUBREG + && GET_CODE (SUBREG_REG (XEXP (bitfield, 0))) == MEM) + memref = SUBREG_REG (XEXP (bitfield, 0)); + else if (GET_CODE (XEXP (bitfield, 0)) == SUBREG + && equiv_mem != 0 + && GET_CODE (SUBREG_REG (XEXP (bitfield, 0))) == REG) + memref = equiv_mem[REGNO (SUBREG_REG (XEXP (bitfield, 0)))]; + + if (memref + && ! mode_dependent_address_p (XEXP (memref, 0)) + && ! MEM_VOLATILE_P (memref)) + { + /* Now adjust the address, first for any subreg'ing + that we are now getting rid of, + and then for which byte of the word is wanted. */ + + register int offset = INTVAL (XEXP (bitfield, 2)); + /* Adjust OFFSET to count bits from low-address byte. */ +#if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN + offset = (GET_MODE_BITSIZE (GET_MODE (XEXP (bitfield, 0))) + - offset - INTVAL (XEXP (bitfield, 1))); +#endif + /* Adjust OFFSET to count bytes from low-address byte. */ + offset /= BITS_PER_UNIT; + if (GET_CODE (XEXP (bitfield, 0)) == SUBREG) + { + offset += SUBREG_WORD (XEXP (bitfield, 0)) * UNITS_PER_WORD; +#if BYTES_BIG_ENDIAN + offset -= (MIN (UNITS_PER_WORD, + GET_MODE_SIZE (GET_MODE (XEXP (bitfield, 0)))) + - MIN (UNITS_PER_WORD, + GET_MODE_SIZE (GET_MODE (memref)))); +#endif + } + + memref = change_address (memref, mode, + plus_constant (XEXP (memref, 0), offset)); + + /* Store this memory reference where + we found the bit field reference. */ + + if (destflag) + { + validate_change (insn, &SET_DEST (body), memref, 1); + if (! CONSTANT_ADDRESS_P (SET_SRC (body))) + { + rtx src = SET_SRC (body); + while (GET_CODE (src) == SUBREG + && SUBREG_WORD (src) == 0) + src = SUBREG_REG (src); + if (GET_MODE (src) != GET_MODE (memref)) + src = gen_lowpart (GET_MODE (memref), SET_SRC (body)); + validate_change (insn, &SET_SRC (body), src, 1); + } + else if (GET_MODE (SET_SRC (body)) != VOIDmode + && GET_MODE (SET_SRC (body)) != GET_MODE (memref)) + /* This shouldn't happen because anything that didn't have + one of these modes should have got converted explicitly + and then referenced through a subreg. + This is so because the original bit-field was + handled by agg_mode and so its tree structure had + the same mode that memref now has. */ + abort (); + } + else + { + rtx dest = SET_DEST (body); + + while (GET_CODE (dest) == SUBREG + && SUBREG_WORD (dest) == 0) + dest = SUBREG_REG (dest); + + validate_change (insn, &SET_DEST (body), dest, 1); + + if (GET_MODE (dest) == GET_MODE (memref)) + validate_change (insn, &SET_SRC (body), memref, 1); + else + { + /* Convert the mem ref to the destination mode. */ + rtx newreg = gen_reg_rtx (GET_MODE (dest)); + + start_sequence (); + convert_move (newreg, memref, + GET_CODE (SET_SRC (body)) == ZERO_EXTRACT); + seq = get_insns (); + end_sequence (); + + validate_change (insn, &SET_SRC (body), newreg, 1); + } + } + + /* See if we can convert this extraction or insertion into + a simple move insn. We might not be able to do so if this + was, for example, part of a PARALLEL. + + If we succeed, write out any needed conversions. If we fail, + it is hard to guess why we failed, so don't do anything + special; just let the optimization be suppressed. */ + + if (apply_change_group () && seq) + emit_insns_before (seq, insn); + } + } +} + +/* These routines are responsible for converting virtual register references + to the actual hard register references once RTL generation is complete. + + The following four variables are used for communication between the + routines. They contain the offsets of the virtual registers from their + respective hard registers. */ + +static int in_arg_offset; +static int var_offset; +static int dynamic_offset; +static int out_arg_offset; + +/* In most machines, the stack pointer register is equivalent to the bottom + of the stack. */ + +#ifndef STACK_POINTER_OFFSET +#define STACK_POINTER_OFFSET 0 +#endif + +/* If not defined, pick an appropriate default for the offset of dynamically + allocated memory depending on the value of ACCUMULATE_OUTGOING_ARGS, + REG_PARM_STACK_SPACE, and OUTGOING_REG_PARM_STACK_SPACE. */ + +#ifndef STACK_DYNAMIC_OFFSET + +#ifdef ACCUMULATE_OUTGOING_ARGS +/* The bottom of the stack points to the actual arguments. If + REG_PARM_STACK_SPACE is defined, this includes the space for the register + parameters. However, if OUTGOING_REG_PARM_STACK space is not defined, + stack space for register parameters is not pushed by the caller, but + rather part of the fixed stack areas and hence not included in + `current_function_outgoing_args_size'. Nevertheless, we must allow + for it when allocating stack dynamic objects. */ + +#if defined(REG_PARM_STACK_SPACE) && ! defined(OUTGOING_REG_PARM_STACK_SPACE) +#define STACK_DYNAMIC_OFFSET(FNDECL) \ +(current_function_outgoing_args_size \ + + REG_PARM_STACK_SPACE (FNDECL) + (STACK_POINTER_OFFSET)) + +#else +#define STACK_DYNAMIC_OFFSET(FNDECL) \ +(current_function_outgoing_args_size + (STACK_POINTER_OFFSET)) +#endif + +#else +#define STACK_DYNAMIC_OFFSET(FNDECL) STACK_POINTER_OFFSET +#endif +#endif + +/* Pass through the INSNS of function FNDECL and convert virtual register + references to hard register references. */ + +void +instantiate_virtual_regs (fndecl, insns) + tree fndecl; + rtx insns; +{ + rtx insn; + + /* Compute the offsets to use for this function. */ + in_arg_offset = FIRST_PARM_OFFSET (fndecl); + var_offset = STARTING_FRAME_OFFSET; + dynamic_offset = STACK_DYNAMIC_OFFSET (fndecl); + out_arg_offset = STACK_POINTER_OFFSET; + + /* Scan all variables and parameters of this function. For each that is + in memory, instantiate all virtual registers if the result is a valid + address. If not, we do it later. That will handle most uses of virtual + regs on many machines. */ + instantiate_decls (fndecl, 1); + + /* Initialize recognition, indicating that volatile is OK. */ + init_recog (); + + /* Scan through all the insns, instantiating every virtual register still + present. */ + for (insn = insns; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN + || GET_CODE (insn) == CALL_INSN) + { + instantiate_virtual_regs_1 (&PATTERN (insn), insn, 1); + instantiate_virtual_regs_1 (®_NOTES (insn), NULL_RTX, 0); + } + + /* Now instantiate the remaining register equivalences for debugging info. + These will not be valid addresses. */ + instantiate_decls (fndecl, 0); + + /* Indicate that, from now on, assign_stack_local should use + frame_pointer_rtx. */ + virtuals_instantiated = 1; +} + +/* Scan all decls in FNDECL (both variables and parameters) and instantiate + all virtual registers in their DECL_RTL's. + + If VALID_ONLY, do this only if the resulting address is still valid. + Otherwise, always do it. */ + +static void +instantiate_decls (fndecl, valid_only) + tree fndecl; + int valid_only; +{ + tree decl; + + if (DECL_INLINE (fndecl)) + /* When compiling an inline function, the obstack used for + rtl allocation is the maybepermanent_obstack. Calling + `resume_temporary_allocation' switches us back to that + obstack while we process this function's parameters. */ + resume_temporary_allocation (); + + /* Process all parameters of the function. */ + for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl)) + { + instantiate_decl (DECL_RTL (decl), int_size_in_bytes (TREE_TYPE (decl)), + valid_only); + instantiate_decl (DECL_INCOMING_RTL (decl), + int_size_in_bytes (TREE_TYPE (decl)), valid_only); + } + + /* Now process all variables defined in the function or its subblocks. */ + instantiate_decls_1 (DECL_INITIAL (fndecl), valid_only); + + if (DECL_INLINE (fndecl)) + { + /* Save all rtl allocated for this function by raising the + high-water mark on the maybepermanent_obstack. */ + preserve_data (); + /* All further rtl allocation is now done in the current_obstack. */ + rtl_in_current_obstack (); + } +} + +/* Subroutine of instantiate_decls: Process all decls in the given + BLOCK node and all its subblocks. */ + +static void +instantiate_decls_1 (let, valid_only) + tree let; + int valid_only; +{ + tree t; + + for (t = BLOCK_VARS (let); t; t = TREE_CHAIN (t)) + instantiate_decl (DECL_RTL (t), int_size_in_bytes (TREE_TYPE (t)), + valid_only); + + /* Process all subblocks. */ + for (t = BLOCK_SUBBLOCKS (let); t; t = TREE_CHAIN (t)) + instantiate_decls_1 (t, valid_only); +} + +/* Subroutine of the preceding procedures: Given RTL representing a + decl and the size of the object, do any instantiation required. + + If VALID_ONLY is non-zero, it means that the RTL should only be + changed if the new address is valid. */ + +static void +instantiate_decl (x, size, valid_only) + rtx x; + int size; + int valid_only; +{ + enum machine_mode mode; + rtx addr; + + /* If this is not a MEM, no need to do anything. Similarly if the + address is a constant or a register that is not a virtual register. */ + + if (x == 0 || GET_CODE (x) != MEM) + return; + + addr = XEXP (x, 0); + if (CONSTANT_P (addr) + || (GET_CODE (addr) == REG + && (REGNO (addr) < FIRST_VIRTUAL_REGISTER + || REGNO (addr) > LAST_VIRTUAL_REGISTER))) + return; + + /* If we should only do this if the address is valid, copy the address. + We need to do this so we can undo any changes that might make the + address invalid. This copy is unfortunate, but probably can't be + avoided. */ + + if (valid_only) + addr = copy_rtx (addr); + + instantiate_virtual_regs_1 (&addr, NULL_RTX, 0); + + if (! valid_only) + return; + + /* Now verify that the resulting address is valid for every integer or + floating-point mode up to and including SIZE bytes long. We do this + since the object might be accessed in any mode and frame addresses + are shared. */ + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); + mode != VOIDmode && GET_MODE_SIZE (mode) <= size; + mode = GET_MODE_WIDER_MODE (mode)) + if (! memory_address_p (mode, addr)) + return; + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); + mode != VOIDmode && GET_MODE_SIZE (mode) <= size; + mode = GET_MODE_WIDER_MODE (mode)) + if (! memory_address_p (mode, addr)) + return; + + /* Otherwise, put back the address, now that we have updated it and we + know it is valid. */ + + XEXP (x, 0) = addr; +} + +/* Given a pointer to a piece of rtx and an optional pointer to the + containing object, instantiate any virtual registers present in it. + + If EXTRA_INSNS, we always do the replacement and generate + any extra insns before OBJECT. If it zero, we do nothing if replacement + is not valid. + + Return 1 if we either had nothing to do or if we were able to do the + needed replacement. Return 0 otherwise; we only return zero if + EXTRA_INSNS is zero. + + We first try some simple transformations to avoid the creation of extra + pseudos. */ + +static int +instantiate_virtual_regs_1 (loc, object, extra_insns) + rtx *loc; + rtx object; + int extra_insns; +{ + rtx x; + RTX_CODE code; + rtx new = 0; + int offset; + rtx temp; + rtx seq; + int i, j; + char *fmt; + + /* Re-start here to avoid recursion in common cases. */ + restart: + + x = *loc; + if (x == 0) + return 1; + + code = GET_CODE (x); + + /* Check for some special cases. */ + switch (code) + { + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case CODE_LABEL: + case PC: + case CC0: + case ASM_INPUT: + case ADDR_VEC: + case ADDR_DIFF_VEC: + case RETURN: + return 1; + + case SET: + /* We are allowed to set the virtual registers. This means that + that the actual register should receive the source minus the + appropriate offset. This is used, for example, in the handling + of non-local gotos. */ + if (SET_DEST (x) == virtual_incoming_args_rtx) + new = arg_pointer_rtx, offset = - in_arg_offset; + else if (SET_DEST (x) == virtual_stack_vars_rtx) + new = frame_pointer_rtx, offset = - var_offset; + else if (SET_DEST (x) == virtual_stack_dynamic_rtx) + new = stack_pointer_rtx, offset = - dynamic_offset; + else if (SET_DEST (x) == virtual_outgoing_args_rtx) + new = stack_pointer_rtx, offset = - out_arg_offset; + + if (new) + { + /* The only valid sources here are PLUS or REG. Just do + the simplest possible thing to handle them. */ + if (GET_CODE (SET_SRC (x)) != REG + && GET_CODE (SET_SRC (x)) != PLUS) + abort (); + + start_sequence (); + if (GET_CODE (SET_SRC (x)) != REG) + temp = force_operand (SET_SRC (x), NULL_RTX); + else + temp = SET_SRC (x); + temp = force_operand (plus_constant (temp, offset), NULL_RTX); + seq = get_insns (); + end_sequence (); + + emit_insns_before (seq, object); + SET_DEST (x) = new; + + if (!validate_change (object, &SET_SRC (x), temp, 0) + || ! extra_insns) + abort (); + + return 1; + } + + instantiate_virtual_regs_1 (&SET_DEST (x), object, extra_insns); + loc = &SET_SRC (x); + goto restart; + + case PLUS: + /* Handle special case of virtual register plus constant. */ + if (CONSTANT_P (XEXP (x, 1))) + { + rtx old; + + /* Check for (plus (plus VIRT foo) (const_int)) first. */ + if (GET_CODE (XEXP (x, 0)) == PLUS) + { + rtx inner = XEXP (XEXP (x, 0), 0); + + if (inner == virtual_incoming_args_rtx) + new = arg_pointer_rtx, offset = in_arg_offset; + else if (inner == virtual_stack_vars_rtx) + new = frame_pointer_rtx, offset = var_offset; + else if (inner == virtual_stack_dynamic_rtx) + new = stack_pointer_rtx, offset = dynamic_offset; + else if (inner == virtual_outgoing_args_rtx) + new = stack_pointer_rtx, offset = out_arg_offset; + else + { + loc = &XEXP (x, 0); + goto restart; + } + + instantiate_virtual_regs_1 (&XEXP (XEXP (x, 0), 1), object, + extra_insns); + new = gen_rtx (PLUS, Pmode, new, XEXP (XEXP (x, 0), 1)); + } + + else if (XEXP (x, 0) == virtual_incoming_args_rtx) + new = arg_pointer_rtx, offset = in_arg_offset; + else if (XEXP (x, 0) == virtual_stack_vars_rtx) + new = frame_pointer_rtx, offset = var_offset; + else if (XEXP (x, 0) == virtual_stack_dynamic_rtx) + new = stack_pointer_rtx, offset = dynamic_offset; + else if (XEXP (x, 0) == virtual_outgoing_args_rtx) + new = stack_pointer_rtx, offset = out_arg_offset; + else + { + /* We know the second operand is a constant. Unless the + first operand is a REG (which has been already checked), + it needs to be checked. */ + if (GET_CODE (XEXP (x, 0)) != REG) + { + loc = &XEXP (x, 0); + goto restart; + } + return 1; + } + + old = XEXP (x, 0); + XEXP (x, 0) = new; + new = plus_constant (XEXP (x, 1), offset); + + /* If the new constant is zero, try to replace the sum with its + first operand. */ + if (new == const0_rtx + && validate_change (object, loc, XEXP (x, 0), 0)) + return 1; + + /* Next try to replace constant with new one. */ + if (!validate_change (object, &XEXP (x, 1), new, 0)) + { + if (! extra_insns) + { + XEXP (x, 0) = old; + return 0; + } + + /* Otherwise copy the new constant into a register and replace + constant with that register. */ + temp = gen_reg_rtx (Pmode); + if (validate_change (object, &XEXP (x, 1), temp, 0)) + emit_insn_before (gen_move_insn (temp, new), object); + else + { + /* If that didn't work, replace this expression with a + register containing the sum. */ + + new = gen_rtx (PLUS, Pmode, XEXP (x, 0), new); + XEXP (x, 0) = old; + + start_sequence (); + temp = force_operand (new, NULL_RTX); + seq = get_insns (); + end_sequence (); + + emit_insns_before (seq, object); + if (! validate_change (object, loc, temp, 0) + && ! validate_replace_rtx (x, temp, object)) + abort (); + } + } + + return 1; + } + + /* Fall through to generic two-operand expression case. */ + case EXPR_LIST: + case CALL: + case COMPARE: + case MINUS: + case MULT: + case DIV: case UDIV: + case MOD: case UMOD: + case AND: case IOR: case XOR: + case LSHIFT: case ASHIFT: case ROTATE: + case ASHIFTRT: case LSHIFTRT: case ROTATERT: + case NE: case EQ: + case GE: case GT: case GEU: case GTU: + case LE: case LT: case LEU: case LTU: + if (XEXP (x, 1) && ! CONSTANT_P (XEXP (x, 1))) + instantiate_virtual_regs_1 (&XEXP (x, 1), object, extra_insns); + loc = &XEXP (x, 0); + goto restart; + + case MEM: + /* Most cases of MEM that convert to valid addresses have already been + handled by our scan of regno_reg_rtx. The only special handling we + need here is to make a copy of the rtx to ensure it isn't being + shared if we have to change it to a pseudo. + + If the rtx is a simple reference to an address via a virtual register, + it can potentially be shared. In such cases, first try to make it + a valid address, which can also be shared. Otherwise, copy it and + proceed normally. + + First check for common cases that need no processing. These are + usually due to instantiation already being done on a previous instance + of a shared rtx. */ + + temp = XEXP (x, 0); + if (CONSTANT_ADDRESS_P (temp) +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + || temp == arg_pointer_rtx +#endif + || temp == frame_pointer_rtx) + return 1; + + if (GET_CODE (temp) == PLUS + && CONSTANT_ADDRESS_P (XEXP (temp, 1)) + && (XEXP (temp, 0) == frame_pointer_rtx +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + || XEXP (temp, 0) == arg_pointer_rtx +#endif + )) + return 1; + + if (temp == virtual_stack_vars_rtx + || temp == virtual_incoming_args_rtx + || (GET_CODE (temp) == PLUS + && CONSTANT_ADDRESS_P (XEXP (temp, 1)) + && (XEXP (temp, 0) == virtual_stack_vars_rtx + || XEXP (temp, 0) == virtual_incoming_args_rtx))) + { + /* This MEM may be shared. If the substitution can be done without + the need to generate new pseudos, we want to do it in place + so all copies of the shared rtx benefit. The call below will + only make substitutions if the resulting address is still + valid. + + Note that we cannot pass X as the object in the recursive call + since the insn being processed may not allow all valid + addresses. However, if we were not passed on object, we can + only modify X without copying it if X will have a valid + address. + + ??? Also note that this can still lose if OBJECT is an insn that + has less restrictions on an address that some other insn. + In that case, we will modify the shared address. This case + doesn't seem very likely, though. */ + + if (instantiate_virtual_regs_1 (&XEXP (x, 0), + object ? object : x, 0)) + return 1; + + /* Otherwise make a copy and process that copy. We copy the entire + RTL expression since it might be a PLUS which could also be + shared. */ + *loc = x = copy_rtx (x); + } + + /* Fall through to generic unary operation case. */ + case USE: + case CLOBBER: + case SUBREG: + case STRICT_LOW_PART: + case NEG: case NOT: + case PRE_DEC: case PRE_INC: case POST_DEC: case POST_INC: + case SIGN_EXTEND: case ZERO_EXTEND: + case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: + case FLOAT: case FIX: + case UNSIGNED_FIX: case UNSIGNED_FLOAT: + case ABS: + case SQRT: + case FFS: + /* These case either have just one operand or we know that we need not + check the rest of the operands. */ + loc = &XEXP (x, 0); + goto restart; + + case REG: + /* Try to replace with a PLUS. If that doesn't work, compute the sum + in front of this insn and substitute the temporary. */ + if (x == virtual_incoming_args_rtx) + new = arg_pointer_rtx, offset = in_arg_offset; + else if (x == virtual_stack_vars_rtx) + new = frame_pointer_rtx, offset = var_offset; + else if (x == virtual_stack_dynamic_rtx) + new = stack_pointer_rtx, offset = dynamic_offset; + else if (x == virtual_outgoing_args_rtx) + new = stack_pointer_rtx, offset = out_arg_offset; + + if (new) + { + temp = plus_constant (new, offset); + if (!validate_change (object, loc, temp, 0)) + { + if (! extra_insns) + return 0; + + start_sequence (); + temp = force_operand (temp, NULL_RTX); + seq = get_insns (); + end_sequence (); + + emit_insns_before (seq, object); + if (! validate_change (object, loc, temp, 0) + && ! validate_replace_rtx (x, temp, object)) + abort (); + } + } + + return 1; + } + + /* Scan all subexpressions. */ + fmt = GET_RTX_FORMAT (code); + for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) + if (*fmt == 'e') + { + if (!instantiate_virtual_regs_1 (&XEXP (x, i), object, extra_insns)) + return 0; + } + else if (*fmt == 'E') + for (j = 0; j < XVECLEN (x, i); j++) + if (! instantiate_virtual_regs_1 (&XVECEXP (x, i, j), object, + extra_insns)) + return 0; + + return 1; +} + +/* Optimization: assuming this function does not receive nonlocal gotos, + delete the handlers for such, as well as the insns to establish + and disestablish them. */ + +static void +delete_handlers () +{ + rtx insn; + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + { + /* Delete the handler by turning off the flag that would + prevent jump_optimize from deleting it. + Also permit deletion of the nonlocal labels themselves + if nothing local refers to them. */ + if (GET_CODE (insn) == CODE_LABEL) + LABEL_PRESERVE_P (insn) = 0; + if (GET_CODE (insn) == INSN + && ((nonlocal_goto_handler_slot != 0 + && reg_mentioned_p (nonlocal_goto_handler_slot, PATTERN (insn))) + || (nonlocal_goto_stack_level != 0 + && reg_mentioned_p (nonlocal_goto_stack_level, + PATTERN (insn))))) + delete_insn (insn); + } +} + +/* Return a list (chain of EXPR_LIST nodes) for the nonlocal labels + of the current function. */ + +rtx +nonlocal_label_rtx_list () +{ + tree t; + rtx x = 0; + + for (t = nonlocal_labels; t; t = TREE_CHAIN (t)) + x = gen_rtx (EXPR_LIST, VOIDmode, label_rtx (TREE_VALUE (t)), x); + + return x; +} + +/* Output a USE for any register use in RTL. + This is used with -noreg to mark the extent of lifespan + of any registers used in a user-visible variable's DECL_RTL. */ + +void +use_variable (rtl) + rtx rtl; +{ + if (GET_CODE (rtl) == REG) + /* This is a register variable. */ + emit_insn (gen_rtx (USE, VOIDmode, rtl)); + else if (GET_CODE (rtl) == MEM + && GET_CODE (XEXP (rtl, 0)) == REG + && (REGNO (XEXP (rtl, 0)) < FIRST_VIRTUAL_REGISTER + || REGNO (XEXP (rtl, 0)) > LAST_VIRTUAL_REGISTER) + && XEXP (rtl, 0) != current_function_internal_arg_pointer) + /* This is a variable-sized structure. */ + emit_insn (gen_rtx (USE, VOIDmode, XEXP (rtl, 0))); +} + +/* Like use_variable except that it outputs the USEs after INSN + instead of at the end of the insn-chain. */ + +void +use_variable_after (rtl, insn) + rtx rtl, insn; +{ + if (GET_CODE (rtl) == REG) + /* This is a register variable. */ + emit_insn_after (gen_rtx (USE, VOIDmode, rtl), insn); + else if (GET_CODE (rtl) == MEM + && GET_CODE (XEXP (rtl, 0)) == REG + && (REGNO (XEXP (rtl, 0)) < FIRST_VIRTUAL_REGISTER + || REGNO (XEXP (rtl, 0)) > LAST_VIRTUAL_REGISTER) + && XEXP (rtl, 0) != current_function_internal_arg_pointer) + /* This is a variable-sized structure. */ + emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (rtl, 0)), insn); +} + +int +max_parm_reg_num () +{ + return max_parm_reg; +} + +/* Return the first insn following those generated by `assign_parms'. */ + +rtx +get_first_nonparm_insn () +{ + if (last_parm_insn) + return NEXT_INSN (last_parm_insn); + return get_insns (); +} + +/* Return the first NOTE_INSN_BLOCK_BEG note in the function. + Crash if there is none. */ + +rtx +get_first_block_beg () +{ + register rtx searcher; + register rtx insn = get_first_nonparm_insn (); + + for (searcher = insn; searcher; searcher = NEXT_INSN (searcher)) + if (GET_CODE (searcher) == NOTE + && NOTE_LINE_NUMBER (searcher) == NOTE_INSN_BLOCK_BEG) + return searcher; + + abort (); /* Invalid call to this function. (See comments above.) */ + return NULL_RTX; +} + +/* Return 1 if EXP returns an aggregate value, for which an address + must be passed to the function or returned by the function. */ + +int +aggregate_value_p (exp) + tree exp; +{ + int i, regno, nregs; + rtx reg; + if (RETURN_IN_MEMORY (TREE_TYPE (exp))) + return 1; + if (flag_pcc_struct_return + && (TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (exp)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (exp)) == QUAL_UNION_TYPE)) + return 1; + /* Make sure we have suitable call-clobbered regs to return + the value in; if not, we must return it in memory. */ + reg = hard_function_value (TREE_TYPE (exp), 0); + regno = REGNO (reg); + nregs = HARD_REGNO_NREGS (regno, TYPE_MODE (TREE_TYPE (exp))); + for (i = 0; i < nregs; i++) + if (! call_used_regs[regno + i]) + return 1; + return 0; +} + +/* Assign RTL expressions to the function's parameters. + This may involve copying them into registers and using + those registers as the RTL for them. + + If SECOND_TIME is non-zero it means that this function is being + called a second time. This is done by integrate.c when a function's + compilation is deferred. We need to come back here in case the + FUNCTION_ARG macro computes items needed for the rest of the compilation + (such as changing which registers are fixed or caller-saved). But suppress + writing any insns or setting DECL_RTL of anything in this case. */ + +void +assign_parms (fndecl, second_time) + tree fndecl; + int second_time; +{ + register tree parm; + register rtx entry_parm = 0; + register rtx stack_parm = 0; + CUMULATIVE_ARGS args_so_far; + enum machine_mode promoted_mode, passed_mode, nominal_mode; + int unsignedp; + /* Total space needed so far for args on the stack, + given as a constant and a tree-expression. */ + struct args_size stack_args_size; + tree fntype = TREE_TYPE (fndecl); + tree fnargs = DECL_ARGUMENTS (fndecl); + /* This is used for the arg pointer when referring to stack args. */ + rtx internal_arg_pointer; + /* This is a dummy PARM_DECL that we used for the function result if + the function returns a structure. */ + tree function_result_decl = 0; + int nparmregs = list_length (fnargs) + LAST_VIRTUAL_REGISTER + 1; + int varargs_setup = 0; + rtx conversion_insns = 0; + /* FUNCTION_ARG may look at this variable. Since this is not + expanding a call it will always be zero in this function. */ + int current_call_is_indirect = 0; + + /* Nonzero if the last arg is named `__builtin_va_alist', + which is used on some machines for old-fashioned non-ANSI varargs.h; + this should be stuck onto the stack as if it had arrived there. */ + int vararg + = (fnargs + && (parm = tree_last (fnargs)) != 0 + && DECL_NAME (parm) + && (! strcmp (IDENTIFIER_POINTER (DECL_NAME (parm)), + "__builtin_va_alist"))); + + /* Nonzero if function takes extra anonymous args. + This means the last named arg must be on the stack + right before the anonymous ones. */ + int stdarg + = (TYPE_ARG_TYPES (fntype) != 0 + && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) + != void_type_node)); + + /* If the reg that the virtual arg pointer will be translated into is + not a fixed reg or is the stack pointer, make a copy of the virtual + arg pointer, and address parms via the copy. The frame pointer is + considered fixed even though it is not marked as such. + + The second time through, simply use ap to avoid generating rtx. */ + + if ((ARG_POINTER_REGNUM == STACK_POINTER_REGNUM + || ! (fixed_regs[ARG_POINTER_REGNUM] + || ARG_POINTER_REGNUM == FRAME_POINTER_REGNUM)) + && ! second_time) + internal_arg_pointer = copy_to_reg (virtual_incoming_args_rtx); + else + internal_arg_pointer = virtual_incoming_args_rtx; + current_function_internal_arg_pointer = internal_arg_pointer; + + stack_args_size.constant = 0; + stack_args_size.var = 0; + + /* If struct value address is treated as the first argument, make it so. */ + if (aggregate_value_p (DECL_RESULT (fndecl)) + && ! current_function_returns_pcc_struct + && struct_value_incoming_rtx == 0) + { + tree type = build_pointer_type (fntype); + + function_result_decl = build_decl (PARM_DECL, NULL_TREE, type); + + DECL_ARG_TYPE (function_result_decl) = type; + TREE_CHAIN (function_result_decl) = fnargs; + fnargs = function_result_decl; + } + + parm_reg_stack_loc = (rtx *) oballoc (nparmregs * sizeof (rtx)); + bzero (parm_reg_stack_loc, nparmregs * sizeof (rtx)); + +#ifdef INIT_CUMULATIVE_INCOMING_ARGS + INIT_CUMULATIVE_INCOMING_ARGS (args_so_far, fntype, NULL_RTX); +#else + INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX); +#endif + + /* We haven't yet found an argument that we must push and pretend the + caller did. */ + current_function_pretend_args_size = 0; + + for (parm = fnargs; parm; parm = TREE_CHAIN (parm)) + { + int aggregate + = (TREE_CODE (TREE_TYPE (parm)) == ARRAY_TYPE + || TREE_CODE (TREE_TYPE (parm)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (parm)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (parm)) == QUAL_UNION_TYPE); + struct args_size stack_offset; + struct args_size arg_size; + int passed_pointer = 0; + tree passed_type = DECL_ARG_TYPE (parm); + + /* Set LAST_NAMED if this is last named arg before some + anonymous args. We treat it as if it were anonymous too. */ + int last_named = ((TREE_CHAIN (parm) == 0 + || DECL_NAME (TREE_CHAIN (parm)) == 0) + && (vararg || stdarg)); + + if (TREE_TYPE (parm) == error_mark_node + /* This can happen after weird syntax errors + or if an enum type is defined among the parms. */ + || TREE_CODE (parm) != PARM_DECL + || passed_type == NULL) + { + DECL_INCOMING_RTL (parm) = DECL_RTL (parm) = gen_rtx (MEM, BLKmode, + const0_rtx); + TREE_USED (parm) = 1; + continue; + } + + /* For varargs.h function, save info about regs and stack space + used by the individual args, not including the va_alist arg. */ + if (vararg && last_named) + current_function_args_info = args_so_far; + + /* Find mode of arg as it is passed, and mode of arg + as it should be during execution of this function. */ + passed_mode = TYPE_MODE (passed_type); + nominal_mode = TYPE_MODE (TREE_TYPE (parm)); + + /* If the parm's mode is VOID, its value doesn't matter, + and avoid the usual things like emit_move_insn that could crash. */ + if (nominal_mode == VOIDmode) + { + DECL_INCOMING_RTL (parm) = DECL_RTL (parm) = const0_rtx; + continue; + } + +#ifdef FUNCTION_ARG_PASS_BY_REFERENCE + /* See if this arg was passed by invisible reference. */ + if (FUNCTION_ARG_PASS_BY_REFERENCE (args_so_far, passed_mode, + passed_type, ! last_named)) + { + passed_type = build_pointer_type (passed_type); + passed_pointer = 1; + passed_mode = nominal_mode = Pmode; + } +#endif + + promoted_mode = passed_mode; + +#ifdef PROMOTE_FUNCTION_ARGS + /* Compute the mode in which the arg is actually extended to. */ + if (TREE_CODE (passed_type) == INTEGER_TYPE + || TREE_CODE (passed_type) == ENUMERAL_TYPE + || TREE_CODE (passed_type) == BOOLEAN_TYPE + || TREE_CODE (passed_type) == CHAR_TYPE + || TREE_CODE (passed_type) == REAL_TYPE + || TREE_CODE (passed_type) == POINTER_TYPE + || TREE_CODE (passed_type) == OFFSET_TYPE) + { + unsignedp = TREE_UNSIGNED (passed_type); + PROMOTE_MODE (promoted_mode, unsignedp, passed_type); + } +#endif + + /* Let machine desc say which reg (if any) the parm arrives in. + 0 means it arrives on the stack. */ +#ifdef FUNCTION_INCOMING_ARG + entry_parm = FUNCTION_INCOMING_ARG (args_so_far, promoted_mode, + passed_type, ! last_named); +#else + entry_parm = FUNCTION_ARG (args_so_far, promoted_mode, + passed_type, ! last_named); +#endif + + if (entry_parm) + passed_mode = promoted_mode; + +#ifdef SETUP_INCOMING_VARARGS + /* If this is the last named parameter, do any required setup for + varargs or stdargs. We need to know about the case of this being an + addressable type, in which case we skip the registers it + would have arrived in. + + For stdargs, LAST_NAMED will be set for two parameters, the one that + is actually the last named, and the dummy parameter. We only + want to do this action once. + + Also, indicate when RTL generation is to be suppressed. */ + if (last_named && !varargs_setup) + { + SETUP_INCOMING_VARARGS (args_so_far, passed_mode, passed_type, + current_function_pretend_args_size, + second_time); + varargs_setup = 1; + } +#endif + + /* Determine parm's home in the stack, + in case it arrives in the stack or we should pretend it did. + + Compute the stack position and rtx where the argument arrives + and its size. + + There is one complexity here: If this was a parameter that would + have been passed in registers, but wasn't only because it is + __builtin_va_alist, we want locate_and_pad_parm to treat it as if + it came in a register so that REG_PARM_STACK_SPACE isn't skipped. + In this case, we call FUNCTION_ARG with NAMED set to 1 instead of + 0 as it was the previous time. */ + + locate_and_pad_parm (passed_mode, passed_type, +#ifdef STACK_PARMS_IN_REG_PARM_AREA + 1, +#else +#ifdef FUNCTION_INCOMING_ARG + FUNCTION_INCOMING_ARG (args_so_far, passed_mode, + passed_type, + (! last_named + || varargs_setup)) != 0, +#else + FUNCTION_ARG (args_so_far, passed_mode, + passed_type, + ! last_named || varargs_setup) != 0, +#endif +#endif + fndecl, &stack_args_size, &stack_offset, &arg_size); + + if (! second_time) + { + rtx offset_rtx = ARGS_SIZE_RTX (stack_offset); + + if (offset_rtx == const0_rtx) + stack_parm = gen_rtx (MEM, passed_mode, internal_arg_pointer); + else + stack_parm = gen_rtx (MEM, passed_mode, + gen_rtx (PLUS, Pmode, + internal_arg_pointer, offset_rtx)); + + /* If this is a memory ref that contains aggregate components, + mark it as such for cse and loop optimize. */ + MEM_IN_STRUCT_P (stack_parm) = aggregate; + } + + /* If this parameter was passed both in registers and in the stack, + use the copy on the stack. */ + if (MUST_PASS_IN_STACK (passed_mode, passed_type)) + entry_parm = 0; + +#ifdef FUNCTION_ARG_PARTIAL_NREGS + /* If this parm was passed part in regs and part in memory, + pretend it arrived entirely in memory + by pushing the register-part onto the stack. + + In the special case of a DImode or DFmode that is split, + we could put it together in a pseudoreg directly, + but for now that's not worth bothering with. */ + + if (entry_parm) + { + int nregs = FUNCTION_ARG_PARTIAL_NREGS (args_so_far, passed_mode, + passed_type, ! last_named); + + if (nregs > 0) + { + current_function_pretend_args_size + = (((nregs * UNITS_PER_WORD) + (PARM_BOUNDARY / BITS_PER_UNIT) - 1) + / (PARM_BOUNDARY / BITS_PER_UNIT) + * (PARM_BOUNDARY / BITS_PER_UNIT)); + + if (! second_time) + move_block_from_reg (REGNO (entry_parm), + validize_mem (stack_parm), nregs); + entry_parm = stack_parm; + } + } +#endif + + /* If we didn't decide this parm came in a register, + by default it came on the stack. */ + if (entry_parm == 0) + entry_parm = stack_parm; + + /* Record permanently how this parm was passed. */ + if (! second_time) + DECL_INCOMING_RTL (parm) = entry_parm; + + /* If there is actually space on the stack for this parm, + count it in stack_args_size; otherwise set stack_parm to 0 + to indicate there is no preallocated stack slot for the parm. */ + + if (entry_parm == stack_parm +#if defined (REG_PARM_STACK_SPACE) && ! defined (MAYBE_REG_PARM_STACK_SPACE) + /* On some machines, even if a parm value arrives in a register + there is still an (uninitialized) stack slot allocated for it. + + ??? When MAYBE_REG_PARM_STACK_SPACE is defined, we can't tell + whether this parameter already has a stack slot allocated, + because an arg block exists only if current_function_args_size + is larger than some threshhold, and we haven't calculated that + yet. So, for now, we just assume that stack slots never exist + in this case. */ + || REG_PARM_STACK_SPACE (fndecl) > 0 +#endif + ) + { + stack_args_size.constant += arg_size.constant; + if (arg_size.var) + ADD_PARM_SIZE (stack_args_size, arg_size.var); + } + else + /* No stack slot was pushed for this parm. */ + stack_parm = 0; + + /* Update info on where next arg arrives in registers. */ + + FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, + passed_type, ! last_named); + + /* If this is our second time through, we are done with this parm. */ + if (second_time) + continue; + + /* If we can't trust the parm stack slot to be aligned enough + for its ultimate type, don't use that slot after entry. + We'll make another stack slot, if we need one. */ + { + int thisparm_boundary + = FUNCTION_ARG_BOUNDARY (passed_mode, passed_type); + + if (GET_MODE_ALIGNMENT (nominal_mode) > thisparm_boundary) + stack_parm = 0; + } + + /* Now adjust STACK_PARM to the mode and precise location + where this parameter should live during execution, + if we discover that it must live in the stack during execution. + To make debuggers happier on big-endian machines, we store + the value in the last bytes of the space available. */ + + if (nominal_mode != BLKmode && nominal_mode != passed_mode + && stack_parm != 0) + { + rtx offset_rtx; + +#if BYTES_BIG_ENDIAN + if (GET_MODE_SIZE (nominal_mode) < UNITS_PER_WORD) + stack_offset.constant += (GET_MODE_SIZE (passed_mode) + - GET_MODE_SIZE (nominal_mode)); +#endif + + offset_rtx = ARGS_SIZE_RTX (stack_offset); + if (offset_rtx == const0_rtx) + stack_parm = gen_rtx (MEM, nominal_mode, internal_arg_pointer); + else + stack_parm = gen_rtx (MEM, nominal_mode, + gen_rtx (PLUS, Pmode, + internal_arg_pointer, offset_rtx)); + + /* If this is a memory ref that contains aggregate components, + mark it as such for cse and loop optimize. */ + MEM_IN_STRUCT_P (stack_parm) = aggregate; + } + + /* ENTRY_PARM is an RTX for the parameter as it arrives, + in the mode in which it arrives. + STACK_PARM is an RTX for a stack slot where the parameter can live + during the function (in case we want to put it there). + STACK_PARM is 0 if no stack slot was pushed for it. + + Now output code if necessary to convert ENTRY_PARM to + the type in which this function declares it, + and store that result in an appropriate place, + which may be a pseudo reg, may be STACK_PARM, + or may be a local stack slot if STACK_PARM is 0. + + Set DECL_RTL to that place. */ + + if (nominal_mode == BLKmode) + { + /* If a BLKmode arrives in registers, copy it to a stack slot. */ + if (GET_CODE (entry_parm) == REG) + { + int size_stored = CEIL_ROUND (int_size_in_bytes (TREE_TYPE (parm)), + UNITS_PER_WORD); + + /* Note that we will be storing an integral number of words. + So we have to be careful to ensure that we allocate an + integral number of words. We do this below in the + assign_stack_local if space was not allocated in the argument + list. If it was, this will not work if PARM_BOUNDARY is not + a multiple of BITS_PER_WORD. It isn't clear how to fix this + if it becomes a problem. */ + + if (stack_parm == 0) + { + stack_parm + = assign_stack_local (GET_MODE (entry_parm), size_stored, 0); + /* If this is a memory ref that contains aggregate components, + mark it as such for cse and loop optimize. */ + MEM_IN_STRUCT_P (stack_parm) = aggregate; + } + + else if (PARM_BOUNDARY % BITS_PER_WORD != 0) + abort (); + + move_block_from_reg (REGNO (entry_parm), + validize_mem (stack_parm), + size_stored / UNITS_PER_WORD); + } + DECL_RTL (parm) = stack_parm; + } + else if (! ((obey_regdecls && ! DECL_REGISTER (parm) + && ! DECL_INLINE (fndecl)) + /* layout_decl may set this. */ + || TREE_ADDRESSABLE (parm) + || TREE_SIDE_EFFECTS (parm) + /* If -ffloat-store specified, don't put explicit + float variables into registers. */ + || (flag_float_store + && TREE_CODE (TREE_TYPE (parm)) == REAL_TYPE)) + /* Always assign pseudo to structure return or item passed + by invisible reference. */ + || passed_pointer || parm == function_result_decl) + { + /* Store the parm in a pseudoregister during the function, but we + may need to do it in a wider mode. */ + + register rtx parmreg; + + unsignedp = TREE_UNSIGNED (TREE_TYPE (parm)); + if (TREE_CODE (TREE_TYPE (parm)) == INTEGER_TYPE + || TREE_CODE (TREE_TYPE (parm)) == ENUMERAL_TYPE + || TREE_CODE (TREE_TYPE (parm)) == BOOLEAN_TYPE + || TREE_CODE (TREE_TYPE (parm)) == CHAR_TYPE + || TREE_CODE (TREE_TYPE (parm)) == REAL_TYPE + || TREE_CODE (TREE_TYPE (parm)) == POINTER_TYPE + || TREE_CODE (TREE_TYPE (parm)) == OFFSET_TYPE) + { + PROMOTE_MODE (nominal_mode, unsignedp, TREE_TYPE (parm)); + } + + parmreg = gen_reg_rtx (nominal_mode); + REG_USERVAR_P (parmreg) = 1; + + /* If this was an item that we received a pointer to, set DECL_RTL + appropriately. */ + if (passed_pointer) + { + DECL_RTL (parm) = gen_rtx (MEM, TYPE_MODE (TREE_TYPE (passed_type)), parmreg); + MEM_IN_STRUCT_P (DECL_RTL (parm)) = aggregate; + } + else + DECL_RTL (parm) = parmreg; + + /* Copy the value into the register. */ + if (GET_MODE (parmreg) != GET_MODE (entry_parm)) + { + /* If ENTRY_PARM is a hard register, it might be in a register + not valid for operating in its mode (e.g., an odd-numbered + register for a DFmode). In that case, moves are the only + thing valid, so we can't do a convert from there. This + occurs when the calling sequence allow such misaligned + usages. + + In addition, the conversion may involve a call, which could + clobber parameters which haven't been copied to pseudo + registers yet. Therefore, we must first copy the parm to + a pseudo reg here, and save the conversion until after all + parameters have been moved. */ + + rtx tempreg = gen_reg_rtx (GET_MODE (entry_parm)); + + emit_move_insn (tempreg, validize_mem (entry_parm)); + + push_to_sequence (conversion_insns); + convert_move (parmreg, tempreg, unsignedp); + conversion_insns = get_insns (); + end_sequence (); + } + else + emit_move_insn (parmreg, validize_mem (entry_parm)); + + /* If we were passed a pointer but the actual value + can safely live in a register, put it in one. */ + if (passed_pointer && TYPE_MODE (TREE_TYPE (parm)) != BLKmode + && ! ((obey_regdecls && ! DECL_REGISTER (parm) + && ! DECL_INLINE (fndecl)) + /* layout_decl may set this. */ + || TREE_ADDRESSABLE (parm) + || TREE_SIDE_EFFECTS (parm) + /* If -ffloat-store specified, don't put explicit + float variables into registers. */ + || (flag_float_store + && TREE_CODE (TREE_TYPE (parm)) == REAL_TYPE))) + { + /* We can't use nominal_mode, because it will have been set to + Pmode above. We must use the actual mode of the parm. */ + parmreg = gen_reg_rtx (TYPE_MODE (TREE_TYPE (parm))); + emit_move_insn (parmreg, DECL_RTL (parm)); + DECL_RTL (parm) = parmreg; + } +#ifdef FUNCTION_ARG_CALLEE_COPIES + /* If we are passed an arg by reference and it is our responsibility + to make a copy, do it now. + PASSED_TYPE and PASSED mode now refer to the pointer, not the + original argument, so we must recreate them in the call to + FUNCTION_ARG_CALLEE_COPIES. */ + /* ??? Later add code to handle the case that if the argument isn't + modified, don't do the copy. */ + + else if (passed_pointer + && FUNCTION_ARG_CALLEE_COPIES (args_so_far, + TYPE_MODE (DECL_ARG_TYPE (parm)), + DECL_ARG_TYPE (parm), + ! last_named)) + { + rtx copy; + tree type = DECL_ARG_TYPE (parm); + + /* This sequence may involve a library call perhaps clobbering + registers that haven't been copied to pseudos yet. */ + + push_to_sequence (conversion_insns); + + if (TYPE_SIZE (type) == 0 + || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) + { + /* This is a variable sized object. */ + /* ??? Can we use expr_size here? */ + rtx size_rtx = expand_expr (size_in_bytes (type), NULL_RTX, + TYPE_MODE (sizetype), 0); + + copy = gen_rtx (MEM, BLKmode, + allocate_dynamic_stack_space (size_rtx, NULL_RTX, + TYPE_ALIGN (type))); + } + else + { + int size = int_size_in_bytes (type); + copy = assign_stack_temp (TYPE_MODE (type), size, 1); + } + + store_expr (parm, copy, 0); + emit_move_insn (parmreg, XEXP (copy, 0)); + conversion_insns = get_insns (); + end_sequence (); + } +#endif /* FUNCTION_ARG_CALLEE_COPIES */ + + /* In any case, record the parm's desired stack location + in case we later discover it must live in the stack. */ + if (REGNO (parmreg) >= nparmregs) + { + rtx *new; + nparmregs = REGNO (parmreg) + 5; + new = (rtx *) oballoc (nparmregs * sizeof (rtx)); + bcopy (parm_reg_stack_loc, new, nparmregs * sizeof (rtx)); + parm_reg_stack_loc = new; + } + parm_reg_stack_loc[REGNO (parmreg)] = stack_parm; + + /* Mark the register as eliminable if we did no conversion + and it was copied from memory at a fixed offset, + and the arg pointer was not copied to a pseudo-reg. + If the arg pointer is a pseudo reg or the offset formed + an invalid address, such memory-equivalences + as we make here would screw up life analysis for it. */ + if (nominal_mode == passed_mode + && GET_CODE (entry_parm) == MEM + && entry_parm == stack_parm + && stack_offset.var == 0 + && reg_mentioned_p (virtual_incoming_args_rtx, + XEXP (entry_parm, 0))) + REG_NOTES (get_last_insn ()) + = gen_rtx (EXPR_LIST, REG_EQUIV, + entry_parm, REG_NOTES (get_last_insn ())); + + /* For pointer data type, suggest pointer register. */ + if (TREE_CODE (TREE_TYPE (parm)) == POINTER_TYPE) + mark_reg_pointer (parmreg); + } + else + { + /* Value must be stored in the stack slot STACK_PARM + during function execution. */ + + if (passed_mode != nominal_mode) + { + /* Conversion is required. */ + rtx tempreg = gen_reg_rtx (GET_MODE (entry_parm)); + + emit_move_insn (tempreg, validize_mem (entry_parm)); + + push_to_sequence (conversion_insns); + entry_parm = convert_to_mode (nominal_mode, tempreg, + TREE_UNSIGNED (TREE_TYPE (parm))); + conversion_insns = get_insns (); + end_sequence (); + } + + if (entry_parm != stack_parm) + { + if (stack_parm == 0) + { + stack_parm + = assign_stack_local (GET_MODE (entry_parm), + GET_MODE_SIZE (GET_MODE (entry_parm)), 0); + /* If this is a memory ref that contains aggregate components, + mark it as such for cse and loop optimize. */ + MEM_IN_STRUCT_P (stack_parm) = aggregate; + } + + if (passed_mode != nominal_mode) + { + push_to_sequence (conversion_insns); + emit_move_insn (validize_mem (stack_parm), + validize_mem (entry_parm)); + conversion_insns = get_insns (); + end_sequence (); + } + else + emit_move_insn (validize_mem (stack_parm), + validize_mem (entry_parm)); + } + + DECL_RTL (parm) = stack_parm; + } + + /* If this "parameter" was the place where we are receiving the + function's incoming structure pointer, set up the result. */ + if (parm == function_result_decl) + DECL_RTL (DECL_RESULT (fndecl)) + = gen_rtx (MEM, DECL_MODE (DECL_RESULT (fndecl)), DECL_RTL (parm)); + + if (TREE_THIS_VOLATILE (parm)) + MEM_VOLATILE_P (DECL_RTL (parm)) = 1; + if (TREE_READONLY (parm)) + RTX_UNCHANGING_P (DECL_RTL (parm)) = 1; + } + + /* Output all parameter conversion instructions (possibly including calls) + now that all parameters have been copied out of hard registers. */ + emit_insns (conversion_insns); + + max_parm_reg = max_reg_num (); + last_parm_insn = get_last_insn (); + + current_function_args_size = stack_args_size.constant; + + /* Adjust function incoming argument size for alignment and + minimum length. */ + +#ifdef REG_PARM_STACK_SPACE +#ifndef MAYBE_REG_PARM_STACK_SPACE + current_function_args_size = MAX (current_function_args_size, + REG_PARM_STACK_SPACE (fndecl)); +#endif +#endif + +#ifdef STACK_BOUNDARY +#define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT) + + current_function_args_size + = ((current_function_args_size + STACK_BYTES - 1) + / STACK_BYTES) * STACK_BYTES; +#endif + +#ifdef ARGS_GROW_DOWNWARD + current_function_arg_offset_rtx + = (stack_args_size.var == 0 ? GEN_INT (-stack_args_size.constant) + : expand_expr (size_binop (MINUS_EXPR, stack_args_size.var, + size_int (-stack_args_size.constant)), + NULL_RTX, VOIDmode, 0)); +#else + current_function_arg_offset_rtx = ARGS_SIZE_RTX (stack_args_size); +#endif + + /* See how many bytes, if any, of its args a function should try to pop + on return. */ + + current_function_pops_args = RETURN_POPS_ARGS (TREE_TYPE (fndecl), + current_function_args_size); + + /* For stdarg.h function, save info about regs and stack space + used by the named args. */ + + if (stdarg) + current_function_args_info = args_so_far; + + /* Set the rtx used for the function return value. Put this in its + own variable so any optimizers that need this information don't have + to include tree.h. Do this here so it gets done when an inlined + function gets output. */ + + current_function_return_rtx = DECL_RTL (DECL_RESULT (fndecl)); +} + +/* Indicate whether REGNO is an incoming argument to the current function + that was promoted to a wider mode. If so, return the RTX for the + register (to get its mode). PMODE and PUNSIGNEDP are set to the mode + that REGNO is promoted from and whether the promotion was signed or + unsigned. */ + +#ifdef PROMOTE_FUNCTION_ARGS + +rtx +promoted_input_arg (regno, pmode, punsignedp) + int regno; + enum machine_mode *pmode; + int *punsignedp; +{ + tree arg; + + for (arg = DECL_ARGUMENTS (current_function_decl); arg; + arg = TREE_CHAIN (arg)) + if (GET_CODE (DECL_INCOMING_RTL (arg)) == REG + && REGNO (DECL_INCOMING_RTL (arg)) == regno + && (TREE_CODE (TREE_TYPE (arg)) == INTEGER_TYPE + || TREE_CODE (TREE_TYPE (arg)) == ENUMERAL_TYPE + || TREE_CODE (TREE_TYPE (arg)) == BOOLEAN_TYPE + || TREE_CODE (TREE_TYPE (arg)) == CHAR_TYPE + || TREE_CODE (TREE_TYPE (arg)) == REAL_TYPE + || TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE + || TREE_CODE (TREE_TYPE (arg)) == OFFSET_TYPE)) + { + enum machine_mode mode = TYPE_MODE (TREE_TYPE (arg)); + int unsignedp = TREE_UNSIGNED (TREE_TYPE (arg)); + + PROMOTE_MODE (mode, unsignedp, TREE_TYPE (arg)); + if (mode == GET_MODE (DECL_INCOMING_RTL (arg)) + && mode != DECL_MODE (arg)) + { + *pmode = DECL_MODE (arg); + *punsignedp = unsignedp; + return DECL_INCOMING_RTL (arg); + } + } + + return 0; +} + +#endif + +/* Compute the size and offset from the start of the stacked arguments for a + parm passed in mode PASSED_MODE and with type TYPE. + + INITIAL_OFFSET_PTR points to the current offset into the stacked + arguments. + + The starting offset and size for this parm are returned in *OFFSET_PTR + and *ARG_SIZE_PTR, respectively. + + IN_REGS is non-zero if the argument will be passed in registers. It will + never be set if REG_PARM_STACK_SPACE is not defined. + + FNDECL is the function in which the argument was defined. + + There are two types of rounding that are done. The first, controlled by + FUNCTION_ARG_BOUNDARY, forces the offset from the start of the argument + list to be aligned to the specific boundary (in bits). This rounding + affects the initial and starting offsets, but not the argument size. + + The second, controlled by FUNCTION_ARG_PADDING and PARM_BOUNDARY, + optionally rounds the size of the parm to PARM_BOUNDARY. The + initial offset is not affected by this rounding, while the size always + is and the starting offset may be. */ + +/* offset_ptr will be negative for ARGS_GROW_DOWNWARD case; + initial_offset_ptr is positive because locate_and_pad_parm's + callers pass in the total size of args so far as + initial_offset_ptr. arg_size_ptr is always positive.*/ + +static void pad_to_arg_alignment (), pad_below (); + +void +locate_and_pad_parm (passed_mode, type, in_regs, fndecl, + initial_offset_ptr, offset_ptr, arg_size_ptr) + enum machine_mode passed_mode; + tree type; + int in_regs; + tree fndecl; + struct args_size *initial_offset_ptr; + struct args_size *offset_ptr; + struct args_size *arg_size_ptr; +{ + tree sizetree + = type ? size_in_bytes (type) : size_int (GET_MODE_SIZE (passed_mode)); + enum direction where_pad = FUNCTION_ARG_PADDING (passed_mode, type); + int boundary = FUNCTION_ARG_BOUNDARY (passed_mode, type); + int boundary_in_bytes = boundary / BITS_PER_UNIT; + int reg_parm_stack_space = 0; + +#ifdef REG_PARM_STACK_SPACE + /* If we have found a stack parm before we reach the end of the + area reserved for registers, skip that area. */ + if (! in_regs) + { +#ifdef MAYBE_REG_PARM_STACK_SPACE + reg_parm_stack_space = MAYBE_REG_PARM_STACK_SPACE; +#else + reg_parm_stack_space = REG_PARM_STACK_SPACE (fndecl); +#endif + if (reg_parm_stack_space > 0) + { + if (initial_offset_ptr->var) + { + initial_offset_ptr->var + = size_binop (MAX_EXPR, ARGS_SIZE_TREE (*initial_offset_ptr), + size_int (reg_parm_stack_space)); + initial_offset_ptr->constant = 0; + } + else if (initial_offset_ptr->constant < reg_parm_stack_space) + initial_offset_ptr->constant = reg_parm_stack_space; + } + } +#endif /* REG_PARM_STACK_SPACE */ + + arg_size_ptr->var = 0; + arg_size_ptr->constant = 0; + +#ifdef ARGS_GROW_DOWNWARD + if (initial_offset_ptr->var) + { + offset_ptr->constant = 0; + offset_ptr->var = size_binop (MINUS_EXPR, integer_zero_node, + initial_offset_ptr->var); + } + else + { + offset_ptr->constant = - initial_offset_ptr->constant; + offset_ptr->var = 0; + } + if (where_pad == upward + && (TREE_CODE (sizetree) != INTEGER_CST + || ((TREE_INT_CST_LOW (sizetree) * BITS_PER_UNIT) % PARM_BOUNDARY))) + sizetree = round_up (sizetree, PARM_BOUNDARY / BITS_PER_UNIT); + SUB_PARM_SIZE (*offset_ptr, sizetree); + if (where_pad != downward) + pad_to_arg_alignment (offset_ptr, boundary); + if (initial_offset_ptr->var) + { + arg_size_ptr->var = size_binop (MINUS_EXPR, + size_binop (MINUS_EXPR, + integer_zero_node, + initial_offset_ptr->var), + offset_ptr->var); + } + else + { + arg_size_ptr->constant = (- initial_offset_ptr->constant - + offset_ptr->constant); + } +/* ADD_PARM_SIZE (*arg_size_ptr, sizetree); */ + if (where_pad == downward) + pad_below (arg_size_ptr, passed_mode, sizetree); +#else /* !ARGS_GROW_DOWNWARD */ + pad_to_arg_alignment (initial_offset_ptr, boundary); + *offset_ptr = *initial_offset_ptr; + if (where_pad == downward) + pad_below (offset_ptr, passed_mode, sizetree); + +#ifdef PUSH_ROUNDING + if (passed_mode != BLKmode) + sizetree = size_int (PUSH_ROUNDING (TREE_INT_CST_LOW (sizetree))); +#endif + + if (where_pad != none + && (TREE_CODE (sizetree) != INTEGER_CST + || ((TREE_INT_CST_LOW (sizetree) * BITS_PER_UNIT) % PARM_BOUNDARY))) + sizetree = round_up (sizetree, PARM_BOUNDARY / BITS_PER_UNIT); + + ADD_PARM_SIZE (*arg_size_ptr, sizetree); +#endif /* ARGS_GROW_DOWNWARD */ +} + +/* Round the stack offset in *OFFSET_PTR up to a multiple of BOUNDARY. + BOUNDARY is measured in bits, but must be a multiple of a storage unit. */ + +static void +pad_to_arg_alignment (offset_ptr, boundary) + struct args_size *offset_ptr; + int boundary; +{ + int boundary_in_bytes = boundary / BITS_PER_UNIT; + + if (boundary > BITS_PER_UNIT) + { + if (offset_ptr->var) + { + offset_ptr->var = +#ifdef ARGS_GROW_DOWNWARD + round_down +#else + round_up +#endif + (ARGS_SIZE_TREE (*offset_ptr), + boundary / BITS_PER_UNIT); + offset_ptr->constant = 0; /*?*/ + } + else + offset_ptr->constant = +#ifdef ARGS_GROW_DOWNWARD + FLOOR_ROUND (offset_ptr->constant, boundary_in_bytes); +#else + CEIL_ROUND (offset_ptr->constant, boundary_in_bytes); +#endif + } +} + +static void +pad_below (offset_ptr, passed_mode, sizetree) + struct args_size *offset_ptr; + enum machine_mode passed_mode; + tree sizetree; +{ + if (passed_mode != BLKmode) + { + if (GET_MODE_BITSIZE (passed_mode) % PARM_BOUNDARY) + offset_ptr->constant + += (((GET_MODE_BITSIZE (passed_mode) + PARM_BOUNDARY - 1) + / PARM_BOUNDARY * PARM_BOUNDARY / BITS_PER_UNIT) + - GET_MODE_SIZE (passed_mode)); + } + else + { + if (TREE_CODE (sizetree) != INTEGER_CST + || (TREE_INT_CST_LOW (sizetree) * BITS_PER_UNIT) % PARM_BOUNDARY) + { + /* Round the size up to multiple of PARM_BOUNDARY bits. */ + tree s2 = round_up (sizetree, PARM_BOUNDARY / BITS_PER_UNIT); + /* Add it in. */ + ADD_PARM_SIZE (*offset_ptr, s2); + SUB_PARM_SIZE (*offset_ptr, sizetree); + } + } +} + +static tree +round_down (value, divisor) + tree value; + int divisor; +{ + return size_binop (MULT_EXPR, + size_binop (FLOOR_DIV_EXPR, value, size_int (divisor)), + size_int (divisor)); +} + +/* Walk the tree of blocks describing the binding levels within a function + and warn about uninitialized variables. + This is done after calling flow_analysis and before global_alloc + clobbers the pseudo-regs to hard regs. */ + +void +uninitialized_vars_warning (block) + tree block; +{ + register tree decl, sub; + for (decl = BLOCK_VARS (block); decl; decl = TREE_CHAIN (decl)) + { + if (TREE_CODE (decl) == VAR_DECL + /* These warnings are unreliable for and aggregates + because assigning the fields one by one can fail to convince + flow.c that the entire aggregate was initialized. + Unions are troublesome because members may be shorter. */ + && TREE_CODE (TREE_TYPE (decl)) != RECORD_TYPE + && TREE_CODE (TREE_TYPE (decl)) != UNION_TYPE + && TREE_CODE (TREE_TYPE (decl)) != QUAL_UNION_TYPE + && TREE_CODE (TREE_TYPE (decl)) != ARRAY_TYPE + && DECL_RTL (decl) != 0 + && GET_CODE (DECL_RTL (decl)) == REG + && regno_uninitialized (REGNO (DECL_RTL (decl)))) + warning_with_decl (decl, + "`%s' may be used uninitialized in this function"); + if (TREE_CODE (decl) == VAR_DECL + && DECL_RTL (decl) != 0 + && GET_CODE (DECL_RTL (decl)) == REG + && regno_clobbered_at_setjmp (REGNO (DECL_RTL (decl)))) + warning_with_decl (decl, + "variable `%s' may be clobbered by `longjmp' or `vfork'"); + } + for (sub = BLOCK_SUBBLOCKS (block); sub; sub = TREE_CHAIN (sub)) + uninitialized_vars_warning (sub); +} + +/* Do the appropriate part of uninitialized_vars_warning + but for arguments instead of local variables. */ + +void +setjmp_args_warning (block) + tree block; +{ + register tree decl; + for (decl = DECL_ARGUMENTS (current_function_decl); + decl; decl = TREE_CHAIN (decl)) + if (DECL_RTL (decl) != 0 + && GET_CODE (DECL_RTL (decl)) == REG + && regno_clobbered_at_setjmp (REGNO (DECL_RTL (decl)))) + warning_with_decl (decl, "argument `%s' may be clobbered by `longjmp' or `vfork'"); +} + +/* If this function call setjmp, put all vars into the stack + unless they were declared `register'. */ + +void +setjmp_protect (block) + tree block; +{ + register tree decl, sub; + for (decl = BLOCK_VARS (block); decl; decl = TREE_CHAIN (decl)) + if ((TREE_CODE (decl) == VAR_DECL + || TREE_CODE (decl) == PARM_DECL) + && DECL_RTL (decl) != 0 + && GET_CODE (DECL_RTL (decl)) == REG + /* If this variable came from an inline function, it must be + that it's life doesn't overlap the setjmp. If there was a + setjmp in the function, it would already be in memory. We + must exclude such variable because their DECL_RTL might be + set to strange things such as virtual_stack_vars_rtx. */ + && ! DECL_FROM_INLINE (decl) + && ( +#ifdef NON_SAVING_SETJMP + /* If longjmp doesn't restore the registers, + don't put anything in them. */ + NON_SAVING_SETJMP + || +#endif + ! DECL_REGISTER (decl))) + put_var_into_stack (decl); + for (sub = BLOCK_SUBBLOCKS (block); sub; sub = TREE_CHAIN (sub)) + setjmp_protect (sub); +} + +/* Like the previous function, but for args instead of local variables. */ + +void +setjmp_protect_args () +{ + register tree decl, sub; + for (decl = DECL_ARGUMENTS (current_function_decl); + decl; decl = TREE_CHAIN (decl)) + if ((TREE_CODE (decl) == VAR_DECL + || TREE_CODE (decl) == PARM_DECL) + && DECL_RTL (decl) != 0 + && GET_CODE (DECL_RTL (decl)) == REG + && ( + /* If longjmp doesn't restore the registers, + don't put anything in them. */ +#ifdef NON_SAVING_SETJMP + NON_SAVING_SETJMP + || +#endif + ! DECL_REGISTER (decl))) + put_var_into_stack (decl); +} + +/* Return the context-pointer register corresponding to DECL, + or 0 if it does not need one. */ + +rtx +lookup_static_chain (decl) + tree decl; +{ + tree context = decl_function_context (decl); + tree link; + + if (context == 0) + return 0; + + /* We treat inline_function_decl as an alias for the current function + because that is the inline function whose vars, types, etc. + are being merged into the current function. + See expand_inline_function. */ + if (context == current_function_decl || context == inline_function_decl) + return virtual_stack_vars_rtx; + + for (link = context_display; link; link = TREE_CHAIN (link)) + if (TREE_PURPOSE (link) == context) + return RTL_EXPR_RTL (TREE_VALUE (link)); + + abort (); +} + +/* Convert a stack slot address ADDR for variable VAR + (from a containing function) + into an address valid in this function (using a static chain). */ + +rtx +fix_lexical_addr (addr, var) + rtx addr; + tree var; +{ + rtx basereg; + int displacement; + tree context = decl_function_context (var); + struct function *fp; + rtx base = 0; + + /* If this is the present function, we need not do anything. */ + if (context == current_function_decl || context == inline_function_decl) + return addr; + + for (fp = outer_function_chain; fp; fp = fp->next) + if (fp->decl == context) + break; + + if (fp == 0) + abort (); + + /* Decode given address as base reg plus displacement. */ + if (GET_CODE (addr) == REG) + basereg = addr, displacement = 0; + else if (GET_CODE (addr) == PLUS && GET_CODE (XEXP (addr, 1)) == CONST_INT) + basereg = XEXP (addr, 0), displacement = INTVAL (XEXP (addr, 1)); + else + abort (); + + /* We accept vars reached via the containing function's + incoming arg pointer and via its stack variables pointer. */ + if (basereg == fp->internal_arg_pointer) + { + /* If reached via arg pointer, get the arg pointer value + out of that function's stack frame. + + There are two cases: If a separate ap is needed, allocate a + slot in the outer function for it and dereference it that way. + This is correct even if the real ap is actually a pseudo. + Otherwise, just adjust the offset from the frame pointer to + compensate. */ + +#ifdef NEED_SEPARATE_AP + rtx addr; + + if (fp->arg_pointer_save_area == 0) + fp->arg_pointer_save_area + = assign_outer_stack_local (Pmode, GET_MODE_SIZE (Pmode), 0, fp); + + addr = fix_lexical_addr (XEXP (fp->arg_pointer_save_area, 0), var); + addr = memory_address (Pmode, addr); + + base = copy_to_reg (gen_rtx (MEM, Pmode, addr)); +#else + displacement += (FIRST_PARM_OFFSET (context) - STARTING_FRAME_OFFSET); + base = lookup_static_chain (var); +#endif + } + + else if (basereg == virtual_stack_vars_rtx) + { + /* This is the same code as lookup_static_chain, duplicated here to + avoid an extra call to decl_function_context. */ + tree link; + + for (link = context_display; link; link = TREE_CHAIN (link)) + if (TREE_PURPOSE (link) == context) + { + base = RTL_EXPR_RTL (TREE_VALUE (link)); + break; + } + } + + if (base == 0) + abort (); + + /* Use same offset, relative to appropriate static chain or argument + pointer. */ + return plus_constant (base, displacement); +} + +/* Return the address of the trampoline for entering nested fn FUNCTION. + If necessary, allocate a trampoline (in the stack frame) + and emit rtl to initialize its contents (at entry to this function). */ + +rtx +trampoline_address (function) + tree function; +{ + tree link; + tree rtlexp; + rtx tramp; + struct function *fp; + tree fn_context; + + /* Find an existing trampoline and return it. */ + for (link = trampoline_list; link; link = TREE_CHAIN (link)) + if (TREE_PURPOSE (link) == function) + return XEXP (RTL_EXPR_RTL (TREE_VALUE (link)), 0); + for (fp = outer_function_chain; fp; fp = fp->next) + for (link = fp->trampoline_list; link; link = TREE_CHAIN (link)) + if (TREE_PURPOSE (link) == function) + { + tramp = fix_lexical_addr (XEXP (RTL_EXPR_RTL (TREE_VALUE (link)), 0), + function); + return round_trampoline_addr (tramp); + } + + /* None exists; we must make one. */ + + /* Find the `struct function' for the function containing FUNCTION. */ + fp = 0; + fn_context = decl_function_context (function); + if (fn_context != current_function_decl) + for (fp = outer_function_chain; fp; fp = fp->next) + if (fp->decl == fn_context) + break; + + /* Allocate run-time space for this trampoline + (usually in the defining function's stack frame). */ +#ifdef ALLOCATE_TRAMPOLINE + tramp = ALLOCATE_TRAMPOLINE (fp); +#else + /* If rounding needed, allocate extra space + to ensure we have TRAMPOLINE_SIZE bytes left after rounding up. */ +#ifdef TRAMPOLINE_ALIGNMENT +#define TRAMPOLINE_REAL_SIZE (TRAMPOLINE_SIZE + TRAMPOLINE_ALIGNMENT - 1) +#else +#define TRAMPOLINE_REAL_SIZE (TRAMPOLINE_SIZE) +#endif + if (fp != 0) + tramp = assign_outer_stack_local (BLKmode, TRAMPOLINE_REAL_SIZE, 0, fp); + else + tramp = assign_stack_local (BLKmode, TRAMPOLINE_REAL_SIZE, 0); +#endif + + /* Record the trampoline for reuse and note it for later initialization + by expand_function_end. */ + if (fp != 0) + { + push_obstacks (fp->current_obstack, fp->function_maybepermanent_obstack); + rtlexp = make_node (RTL_EXPR); + RTL_EXPR_RTL (rtlexp) = tramp; + fp->trampoline_list = tree_cons (function, rtlexp, fp->trampoline_list); + pop_obstacks (); + } + else + { + /* Make the RTL_EXPR node temporary, not momentary, so that the + trampoline_list doesn't become garbage. */ + int momentary = suspend_momentary (); + rtlexp = make_node (RTL_EXPR); + resume_momentary (momentary); + + RTL_EXPR_RTL (rtlexp) = tramp; + trampoline_list = tree_cons (function, rtlexp, trampoline_list); + } + + tramp = fix_lexical_addr (XEXP (tramp, 0), function); + return round_trampoline_addr (tramp); +} + +/* Given a trampoline address, + round it to multiple of TRAMPOLINE_ALIGNMENT. */ + +static rtx +round_trampoline_addr (tramp) + rtx tramp; +{ +#ifdef TRAMPOLINE_ALIGNMENT + /* Round address up to desired boundary. */ + rtx temp = gen_reg_rtx (Pmode); + temp = expand_binop (Pmode, add_optab, tramp, + GEN_INT (TRAMPOLINE_ALIGNMENT - 1), + temp, 0, OPTAB_LIB_WIDEN); + tramp = expand_binop (Pmode, and_optab, temp, + GEN_INT (- TRAMPOLINE_ALIGNMENT), + temp, 0, OPTAB_LIB_WIDEN); +#endif + return tramp; +} + +/* The functions identify_blocks and reorder_blocks provide a way to + reorder the tree of BLOCK nodes, for optimizers that reshuffle or + duplicate portions of the RTL code. Call identify_blocks before + changing the RTL, and call reorder_blocks after. */ + +static int all_blocks (); +static tree blocks_nreverse (); + +/* Put all this function's BLOCK nodes into a vector, and return it. + Also store in each NOTE for the beginning or end of a block + the index of that block in the vector. + The arguments are TOP_BLOCK, the top-level block of the function, + and INSNS, the insn chain of the function. */ + +tree * +identify_blocks (top_block, insns) + tree top_block; + rtx insns; +{ + int n_blocks; + tree *block_vector; + int *block_stack; + int depth = 0; + int next_block_number = 0; + int current_block_number = 0; + rtx insn; + + if (top_block == 0) + return 0; + + n_blocks = all_blocks (top_block, 0); + block_vector = (tree *) xmalloc (n_blocks * sizeof (tree)); + block_stack = (int *) alloca (n_blocks * sizeof (int)); + + all_blocks (top_block, block_vector); + + for (insn = insns; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == NOTE) + { + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG) + { + block_stack[depth++] = current_block_number; + current_block_number = next_block_number; + NOTE_BLOCK_NUMBER (insn) = next_block_number++; + } + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) + { + current_block_number = block_stack[--depth]; + NOTE_BLOCK_NUMBER (insn) = current_block_number; + } + } + + return block_vector; +} + +/* Given BLOCK_VECTOR which was returned by identify_blocks, + and a revised instruction chain, rebuild the tree structure + of BLOCK nodes to correspond to the new order of RTL. + The new block tree is inserted below TOP_BLOCK. + Returns the current top-level block. */ + +tree +reorder_blocks (block_vector, top_block, insns) + tree *block_vector; + tree top_block; + rtx insns; +{ + tree current_block = top_block; + rtx insn; + + if (block_vector == 0) + return top_block; + + /* Prune the old tree away, so that it doesn't get in the way. */ + BLOCK_SUBBLOCKS (current_block) = 0; + + for (insn = insns; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == NOTE) + { + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG) + { + tree block = block_vector[NOTE_BLOCK_NUMBER (insn)]; + /* If we have seen this block before, copy it. */ + if (TREE_ASM_WRITTEN (block)) + block = copy_node (block); + BLOCK_SUBBLOCKS (block) = 0; + TREE_ASM_WRITTEN (block) = 1; + BLOCK_SUPERCONTEXT (block) = current_block; + BLOCK_CHAIN (block) = BLOCK_SUBBLOCKS (current_block); + BLOCK_SUBBLOCKS (current_block) = block; + current_block = block; + NOTE_SOURCE_FILE (insn) = 0; + } + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) + { + BLOCK_SUBBLOCKS (current_block) + = blocks_nreverse (BLOCK_SUBBLOCKS (current_block)); + current_block = BLOCK_SUPERCONTEXT (current_block); + NOTE_SOURCE_FILE (insn) = 0; + } + } + + return current_block; +} + +/* Reverse the order of elements in the chain T of blocks, + and return the new head of the chain (old last element). */ + +static tree +blocks_nreverse (t) + tree t; +{ + register tree prev = 0, decl, next; + for (decl = t; decl; decl = next) + { + next = BLOCK_CHAIN (decl); + BLOCK_CHAIN (decl) = prev; + prev = decl; + } + return prev; +} + +/* Count the subblocks of BLOCK, and list them all into the vector VECTOR. + Also clear TREE_ASM_WRITTEN in all blocks. */ + +static int +all_blocks (block, vector) + tree block; + tree *vector; +{ + int n_blocks = 1; + tree subblocks; + + TREE_ASM_WRITTEN (block) = 0; + /* Record this block. */ + if (vector) + vector[0] = block; + + /* Record the subblocks, and their subblocks. */ + for (subblocks = BLOCK_SUBBLOCKS (block); + subblocks; subblocks = BLOCK_CHAIN (subblocks)) + n_blocks += all_blocks (subblocks, vector ? vector + n_blocks : 0); + + return n_blocks; +} + +/* Generate RTL for the start of the function SUBR (a FUNCTION_DECL tree node) + and initialize static variables for generating RTL for the statements + of the function. */ + +void +init_function_start (subr, filename, line) + tree subr; + char *filename; + int line; +{ + char *junk; + + init_stmt_for_function (); + + cse_not_expected = ! optimize; + + /* Caller save not needed yet. */ + caller_save_needed = 0; + + /* No stack slots have been made yet. */ + stack_slot_list = 0; + + /* There is no stack slot for handling nonlocal gotos. */ + nonlocal_goto_handler_slot = 0; + nonlocal_goto_stack_level = 0; + + /* No labels have been declared for nonlocal use. */ + nonlocal_labels = 0; + + /* No function calls so far in this function. */ + function_call_count = 0; + + /* No parm regs have been allocated. + (This is important for output_inline_function.) */ + max_parm_reg = LAST_VIRTUAL_REGISTER + 1; + + /* Initialize the RTL mechanism. */ + init_emit (); + + /* Initialize the queue of pending postincrement and postdecrements, + and some other info in expr.c. */ + init_expr (); + + /* We haven't done register allocation yet. */ + reg_renumber = 0; + + init_const_rtx_hash_table (); + + current_function_name = (*decl_printable_name) (subr, &junk); + + /* Nonzero if this is a nested function that uses a static chain. */ + + current_function_needs_context + = (decl_function_context (current_function_decl) != 0); + + /* Set if a call to setjmp is seen. */ + current_function_calls_setjmp = 0; + + /* Set if a call to longjmp is seen. */ + current_function_calls_longjmp = 0; + + current_function_calls_alloca = 0; + current_function_has_nonlocal_label = 0; + current_function_contains_functions = 0; + + current_function_returns_pcc_struct = 0; + current_function_returns_struct = 0; + current_function_epilogue_delay_list = 0; + current_function_uses_const_pool = 0; + current_function_uses_pic_offset_table = 0; + + /* We have not yet needed to make a label to jump to for tail-recursion. */ + tail_recursion_label = 0; + + /* We haven't had a need to make a save area for ap yet. */ + + arg_pointer_save_area = 0; + + /* No stack slots allocated yet. */ + frame_offset = 0; + + /* No SAVE_EXPRs in this function yet. */ + save_expr_regs = 0; + + /* No RTL_EXPRs in this function yet. */ + rtl_expr_chain = 0; + + /* We have not allocated any temporaries yet. */ + temp_slots = 0; + temp_slot_level = 0; + + /* Within function body, compute a type's size as soon it is laid out. */ + immediate_size_expand++; + + init_pending_stack_adjust (); + inhibit_defer_pop = 0; + + current_function_outgoing_args_size = 0; + + /* Initialize the insn lengths. */ + init_insn_lengths (); + + /* Prevent ever trying to delete the first instruction of a function. + Also tell final how to output a linenum before the function prologue. */ + emit_line_note (filename, line); + + /* Make sure first insn is a note even if we don't want linenums. + This makes sure the first insn will never be deleted. + Also, final expects a note to appear there. */ + emit_note (NULL_PTR, NOTE_INSN_DELETED); + + /* Set flags used by final.c. */ + if (aggregate_value_p (DECL_RESULT (subr))) + { +#ifdef PCC_STATIC_STRUCT_RETURN + current_function_returns_pcc_struct = 1; +#endif + current_function_returns_struct = 1; + } + + /* Warn if this value is an aggregate type, + regardless of which calling convention we are using for it. */ + if (warn_aggregate_return + && (TREE_CODE (TREE_TYPE (DECL_RESULT (subr))) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (DECL_RESULT (subr))) == UNION_TYPE + || TREE_CODE (TREE_TYPE (DECL_RESULT (subr))) == QUAL_UNION_TYPE + || TREE_CODE (TREE_TYPE (DECL_RESULT (subr))) == ARRAY_TYPE)) + warning ("function returns an aggregate"); + + current_function_returns_pointer + = (TREE_CODE (TREE_TYPE (DECL_RESULT (subr))) == POINTER_TYPE); + + /* Indicate that we need to distinguish between the return value of the + present function and the return value of a function being called. */ + rtx_equal_function_value_matters = 1; + + /* Indicate that we have not instantiated virtual registers yet. */ + virtuals_instantiated = 0; + + /* Indicate we have no need of a frame pointer yet. */ + frame_pointer_needed = 0; + + /* By default assume not varargs. */ + current_function_varargs = 0; +} + +/* Indicate that the current function uses extra args + not explicitly mentioned in the argument list in any fashion. */ + +void +mark_varargs () +{ + current_function_varargs = 1; +} + +/* Expand a call to __main at the beginning of a possible main function. */ + +void +expand_main_function () +{ +#if !defined (INIT_SECTION_ASM_OP) || defined (INVOKE__main) + emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__main"), 0, + VOIDmode, 0); +#endif /* not INIT_SECTION_ASM_OP or INVOKE__main */ +} + +/* Start the RTL for a new function, and set variables used for + emitting RTL. + SUBR is the FUNCTION_DECL node. + PARMS_HAVE_CLEANUPS is nonzero if there are cleanups associated with + the function's parameters, which must be run at any return statement. */ + +void +expand_function_start (subr, parms_have_cleanups) + tree subr; + int parms_have_cleanups; +{ + register int i; + tree tem; + rtx last_ptr; + + /* Make sure volatile mem refs aren't considered + valid operands of arithmetic insns. */ + init_recog_no_volatile (); + + /* If function gets a static chain arg, store it in the stack frame. + Do this first, so it gets the first stack slot offset. */ + if (current_function_needs_context) + { + last_ptr = assign_stack_local (Pmode, GET_MODE_SIZE (Pmode), 0); + emit_move_insn (last_ptr, static_chain_incoming_rtx); + } + + /* If the parameters of this function need cleaning up, get a label + for the beginning of the code which executes those cleanups. This must + be done before doing anything with return_label. */ + if (parms_have_cleanups) + cleanup_label = gen_label_rtx (); + else + cleanup_label = 0; + + /* Make the label for return statements to jump to, if this machine + does not have a one-instruction return and uses an epilogue, + or if it returns a structure, or if it has parm cleanups. */ +#ifdef HAVE_return + if (cleanup_label == 0 && HAVE_return + && ! current_function_returns_pcc_struct + && ! (current_function_returns_struct && ! optimize)) + return_label = 0; + else + return_label = gen_label_rtx (); +#else + return_label = gen_label_rtx (); +#endif + + /* Initialize rtx used to return the value. */ + /* Do this before assign_parms so that we copy the struct value address + before any library calls that assign parms might generate. */ + + /* Decide whether to return the value in memory or in a register. */ + if (aggregate_value_p (DECL_RESULT (subr))) + { + /* Returning something that won't go in a register. */ + register rtx value_address; + +#ifdef PCC_STATIC_STRUCT_RETURN + if (current_function_returns_pcc_struct) + { + int size = int_size_in_bytes (TREE_TYPE (DECL_RESULT (subr))); + value_address = assemble_static_space (size); + } + else +#endif + { + /* Expect to be passed the address of a place to store the value. + If it is passed as an argument, assign_parms will take care of + it. */ + if (struct_value_incoming_rtx) + { + value_address = gen_reg_rtx (Pmode); + emit_move_insn (value_address, struct_value_incoming_rtx); + } + } + if (value_address) + DECL_RTL (DECL_RESULT (subr)) + = gen_rtx (MEM, DECL_MODE (DECL_RESULT (subr)), + value_address); + } + else if (DECL_MODE (DECL_RESULT (subr)) == VOIDmode) + /* If return mode is void, this decl rtl should not be used. */ + DECL_RTL (DECL_RESULT (subr)) = 0; + else if (parms_have_cleanups) + { + /* If function will end with cleanup code for parms, + compute the return values into a pseudo reg, + which we will copy into the true return register + after the cleanups are done. */ + + enum machine_mode mode = DECL_MODE (DECL_RESULT (subr)); +#ifdef PROMOTE_FUNCTION_RETURN + tree type = TREE_TYPE (DECL_RESULT (subr)); + int unsignedp = TREE_UNSIGNED (type); + + if (TREE_CODE (type) == INTEGER_TYPE || TREE_CODE (type) == ENUMERAL_TYPE + || TREE_CODE (type) == BOOLEAN_TYPE || TREE_CODE (type) == CHAR_TYPE + || TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == POINTER_TYPE + || TREE_CODE (type) == OFFSET_TYPE) + { + PROMOTE_MODE (mode, unsignedp, type); + } +#endif + + DECL_RTL (DECL_RESULT (subr)) = gen_reg_rtx (mode); + } + else + /* Scalar, returned in a register. */ + { +#ifdef FUNCTION_OUTGOING_VALUE + DECL_RTL (DECL_RESULT (subr)) + = FUNCTION_OUTGOING_VALUE (TREE_TYPE (DECL_RESULT (subr)), subr); +#else + DECL_RTL (DECL_RESULT (subr)) + = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (subr)), subr); +#endif + + /* Mark this reg as the function's return value. */ + if (GET_CODE (DECL_RTL (DECL_RESULT (subr))) == REG) + { + REG_FUNCTION_VALUE_P (DECL_RTL (DECL_RESULT (subr))) = 1; + /* Needed because we may need to move this to memory + in case it's a named return value whose address is taken. */ + DECL_REGISTER (DECL_RESULT (subr)) = 1; + } + } + + /* Initialize rtx for parameters and local variables. + In some cases this requires emitting insns. */ + + assign_parms (subr, 0); + + /* The following was moved from init_function_start. + The move is supposed to make sdb output more accurate. */ + /* Indicate the beginning of the function body, + as opposed to parm setup. */ + emit_note (NULL_PTR, NOTE_INSN_FUNCTION_BEG); + + /* If doing stupid allocation, mark parms as born here. */ + + if (GET_CODE (get_last_insn ()) != NOTE) + emit_note (NULL_PTR, NOTE_INSN_DELETED); + parm_birth_insn = get_last_insn (); + + if (obey_regdecls) + { + for (i = LAST_VIRTUAL_REGISTER + 1; i < max_parm_reg; i++) + use_variable (regno_reg_rtx[i]); + + if (current_function_internal_arg_pointer != virtual_incoming_args_rtx) + use_variable (current_function_internal_arg_pointer); + } + + /* Fetch static chain values for containing functions. */ + tem = decl_function_context (current_function_decl); + /* If not doing stupid register allocation, then start off with the static + chain pointer in a pseudo register. Otherwise, we use the stack + address that was generated above. */ + if (tem && ! obey_regdecls) + last_ptr = copy_to_reg (static_chain_incoming_rtx); + context_display = 0; + while (tem) + { + tree rtlexp = make_node (RTL_EXPR); + + RTL_EXPR_RTL (rtlexp) = last_ptr; + context_display = tree_cons (tem, rtlexp, context_display); + tem = decl_function_context (tem); + if (tem == 0) + break; + /* Chain thru stack frames, assuming pointer to next lexical frame + is found at the place we always store it. */ +#ifdef FRAME_GROWS_DOWNWARD + last_ptr = plus_constant (last_ptr, - GET_MODE_SIZE (Pmode)); +#endif + last_ptr = copy_to_reg (gen_rtx (MEM, Pmode, + memory_address (Pmode, last_ptr))); + } + + /* After the display initializations is where the tail-recursion label + should go, if we end up needing one. Ensure we have a NOTE here + since some things (like trampolines) get placed before this. */ + tail_recursion_reentry = emit_note (NULL_PTR, NOTE_INSN_DELETED); + + /* Evaluate now the sizes of any types declared among the arguments. */ + for (tem = nreverse (get_pending_sizes ()); tem; tem = TREE_CHAIN (tem)) + expand_expr (TREE_VALUE (tem), const0_rtx, VOIDmode, 0); + + /* Make sure there is a line number after the function entry setup code. */ + force_next_line_note (); +} + +/* Generate RTL for the end of the current function. + FILENAME and LINE are the current position in the source file. */ + +/* It is up to language-specific callers to do cleanups for parameters. */ + +void +expand_function_end (filename, line) + char *filename; + int line; +{ + register int i; + tree link; + + static rtx initial_trampoline; + +#ifdef NON_SAVING_SETJMP + /* Don't put any variables in registers if we call setjmp + on a machine that fails to restore the registers. */ + if (NON_SAVING_SETJMP && current_function_calls_setjmp) + { + setjmp_protect (DECL_INITIAL (current_function_decl)); + setjmp_protect_args (); + } +#endif + + /* Save the argument pointer if a save area was made for it. */ + if (arg_pointer_save_area) + { + rtx x = gen_move_insn (arg_pointer_save_area, virtual_incoming_args_rtx); + emit_insn_before (x, tail_recursion_reentry); + } + + /* Initialize any trampolines required by this function. */ + for (link = trampoline_list; link; link = TREE_CHAIN (link)) + { + tree function = TREE_PURPOSE (link); + rtx context = lookup_static_chain (function); + rtx tramp = RTL_EXPR_RTL (TREE_VALUE (link)); + rtx seq; + + /* First make sure this compilation has a template for + initializing trampolines. */ + if (initial_trampoline == 0) + { + end_temporary_allocation (); + initial_trampoline + = gen_rtx (MEM, BLKmode, assemble_trampoline_template ()); + resume_temporary_allocation (); + } + + /* Generate insns to initialize the trampoline. */ + start_sequence (); + tramp = change_address (initial_trampoline, BLKmode, + round_trampoline_addr (XEXP (tramp, 0))); + emit_block_move (tramp, initial_trampoline, GEN_INT (TRAMPOLINE_SIZE), + FUNCTION_BOUNDARY / BITS_PER_UNIT); + INITIALIZE_TRAMPOLINE (XEXP (tramp, 0), + XEXP (DECL_RTL (function), 0), context); + seq = get_insns (); + end_sequence (); + + /* Put those insns at entry to the containing function (this one). */ + emit_insns_before (seq, tail_recursion_reentry); + } + /* Clear the trampoline_list for the next function. */ + trampoline_list = 0; + +#if 0 /* I think unused parms are legitimate enough. */ + /* Warn about unused parms. */ + if (warn_unused) + { + rtx decl; + + for (decl = DECL_ARGUMENTS (current_function_decl); + decl; decl = TREE_CHAIN (decl)) + if (! TREE_USED (decl) && TREE_CODE (decl) == VAR_DECL) + warning_with_decl (decl, "unused parameter `%s'"); + } +#endif + + /* Delete handlers for nonlocal gotos if nothing uses them. */ + if (nonlocal_goto_handler_slot != 0 && !current_function_has_nonlocal_label) + delete_handlers (); + + /* End any sequences that failed to be closed due to syntax errors. */ + while (in_sequence_p ()) + end_sequence (); + + /* Outside function body, can't compute type's actual size + until next function's body starts. */ + immediate_size_expand--; + + /* If doing stupid register allocation, + mark register parms as dying here. */ + + if (obey_regdecls) + { + rtx tem; + for (i = LAST_VIRTUAL_REGISTER + 1; i < max_parm_reg; i++) + use_variable (regno_reg_rtx[i]); + + /* Likewise for the regs of all the SAVE_EXPRs in the function. */ + + for (tem = save_expr_regs; tem; tem = XEXP (tem, 1)) + { + use_variable (XEXP (tem, 0)); + use_variable_after (XEXP (tem, 0), parm_birth_insn); + } + + if (current_function_internal_arg_pointer != virtual_incoming_args_rtx) + use_variable (current_function_internal_arg_pointer); + } + + clear_pending_stack_adjust (); + do_pending_stack_adjust (); + + /* Mark the end of the function body. + If control reaches this insn, the function can drop through + without returning a value. */ + emit_note (NULL_PTR, NOTE_INSN_FUNCTION_END); + + /* Output a linenumber for the end of the function. + SDB depends on this. */ + emit_line_note_force (filename, line); + + /* Output the label for the actual return from the function, + if one is expected. This happens either because a function epilogue + is used instead of a return instruction, or because a return was done + with a goto in order to run local cleanups, or because of pcc-style + structure returning. */ + + if (return_label) + emit_label (return_label); + + /* If we had calls to alloca, and this machine needs + an accurate stack pointer to exit the function, + insert some code to save and restore the stack pointer. */ +#ifdef EXIT_IGNORE_STACK + if (! EXIT_IGNORE_STACK) +#endif + if (current_function_calls_alloca) + { + rtx tem = 0; + + emit_stack_save (SAVE_FUNCTION, &tem, parm_birth_insn); + emit_stack_restore (SAVE_FUNCTION, tem, NULL_RTX); + } + + /* If scalar return value was computed in a pseudo-reg, + copy that to the hard return register. */ + if (DECL_RTL (DECL_RESULT (current_function_decl)) != 0 + && GET_CODE (DECL_RTL (DECL_RESULT (current_function_decl))) == REG + && (REGNO (DECL_RTL (DECL_RESULT (current_function_decl))) + >= FIRST_PSEUDO_REGISTER)) + { + rtx real_decl_result; + +#ifdef FUNCTION_OUTGOING_VALUE + real_decl_result + = FUNCTION_OUTGOING_VALUE (TREE_TYPE (DECL_RESULT (current_function_decl)), + current_function_decl); +#else + real_decl_result + = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (current_function_decl)), + current_function_decl); +#endif + REG_FUNCTION_VALUE_P (real_decl_result) = 1; + emit_move_insn (real_decl_result, + DECL_RTL (DECL_RESULT (current_function_decl))); + emit_insn (gen_rtx (USE, VOIDmode, real_decl_result)); + } + + /* If returning a structure, arrange to return the address of the value + in a place where debuggers expect to find it. + + If returning a structure PCC style, + the caller also depends on this value. + And current_function_returns_pcc_struct is not necessarily set. */ + if (current_function_returns_struct + || current_function_returns_pcc_struct) + { + rtx value_address = XEXP (DECL_RTL (DECL_RESULT (current_function_decl)), 0); + tree type = TREE_TYPE (DECL_RESULT (current_function_decl)); +#ifdef FUNCTION_OUTGOING_VALUE + rtx outgoing + = FUNCTION_OUTGOING_VALUE (build_pointer_type (type), + current_function_decl); +#else + rtx outgoing + = FUNCTION_VALUE (build_pointer_type (type), + current_function_decl); +#endif + + /* Mark this as a function return value so integrate will delete the + assignment and USE below when inlining this function. */ + REG_FUNCTION_VALUE_P (outgoing) = 1; + + emit_move_insn (outgoing, value_address); + use_variable (outgoing); + } + + /* Output a return insn if we are using one. + Otherwise, let the rtl chain end here, to drop through + into the epilogue. */ + +#ifdef HAVE_return + if (HAVE_return) + { + emit_jump_insn (gen_return ()); + emit_barrier (); + } +#endif + + /* Fix up any gotos that jumped out to the outermost + binding level of the function. + Must follow emitting RETURN_LABEL. */ + + /* If you have any cleanups to do at this point, + and they need to create temporary variables, + then you will lose. */ + fixup_gotos (NULL_PTR, NULL_RTX, NULL_TREE, get_insns (), 0); +} + +/* These arrays record the INSN_UIDs of the prologue and epilogue insns. */ + +static int *prologue; +static int *epilogue; + +/* Create an array that records the INSN_UIDs of INSNS (either a sequence + or a single insn). */ + +static int * +record_insns (insns) + rtx insns; +{ + int *vec; + + if (GET_CODE (insns) == SEQUENCE) + { + int len = XVECLEN (insns, 0); + vec = (int *) oballoc ((len + 1) * sizeof (int)); + vec[len] = 0; + while (--len >= 0) + vec[len] = INSN_UID (XVECEXP (insns, 0, len)); + } + else + { + vec = (int *) oballoc (2 * sizeof (int)); + vec[0] = INSN_UID (insns); + vec[1] = 0; + } + return vec; +} + +/* Determine how many INSN_UIDs in VEC are part of INSN. */ + +static int +contains (insn, vec) + rtx insn; + int *vec; +{ + register int i, j; + + if (GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == SEQUENCE) + { + int count = 0; + for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) + for (j = 0; vec[j]; j++) + if (INSN_UID (XVECEXP (PATTERN (insn), 0, i)) == vec[j]) + count++; + return count; + } + else + { + for (j = 0; vec[j]; j++) + if (INSN_UID (insn) == vec[j]) + return 1; + } + return 0; +} + +/* Generate the prologe and epilogue RTL if the machine supports it. Thread + this into place with notes indicating where the prologue ends and where + the epilogue begins. Update the basic block information when possible. */ + +void +thread_prologue_and_epilogue_insns (f) + rtx f; +{ +#ifdef HAVE_prologue + if (HAVE_prologue) + { + rtx head, seq, insn; + + /* The first insn (a NOTE_INSN_DELETED) is followed by zero or more + prologue insns and a NOTE_INSN_PROLOGUE_END. */ + emit_note_after (NOTE_INSN_PROLOGUE_END, f); + seq = gen_prologue (); + head = emit_insn_after (seq, f); + + /* Include the new prologue insns in the first block. Ignore them + if they form a basic block unto themselves. */ + if (basic_block_head && n_basic_blocks + && GET_CODE (basic_block_head[0]) != CODE_LABEL) + basic_block_head[0] = NEXT_INSN (f); + + /* Retain a map of the prologue insns. */ + prologue = record_insns (GET_CODE (seq) == SEQUENCE ? seq : head); + } + else +#endif + prologue = 0; + +#ifdef HAVE_epilogue + if (HAVE_epilogue) + { + rtx insn = get_last_insn (); + rtx prev = prev_nonnote_insn (insn); + + /* If we end with a BARRIER, we don't need an epilogue. */ + if (! (prev && GET_CODE (prev) == BARRIER)) + { + rtx tail, seq; + + /* The last basic block ends with a NOTE_INSN_EPILOGUE_BEG, + the epilogue insns (this must include the jump insn that + returns), USE insns ad the end of a function, and a BARRIER. */ + + emit_barrier_after (insn); + + /* Place the epilogue before the USE insns at the end of a + function. */ + while (prev + && GET_CODE (prev) == INSN + && GET_CODE (PATTERN (prev)) == USE) + { + insn = PREV_INSN (prev); + prev = prev_nonnote_insn (prev); + } + + seq = gen_epilogue (); + tail = emit_jump_insn_after (seq, insn); + emit_note_after (NOTE_INSN_EPILOGUE_BEG, insn); + + /* Include the new epilogue insns in the last block. Ignore + them if they form a basic block unto themselves. */ + if (basic_block_end && n_basic_blocks + && GET_CODE (basic_block_end[n_basic_blocks - 1]) != JUMP_INSN) + basic_block_end[n_basic_blocks - 1] = tail; + + /* Retain a map of the epilogue insns. */ + epilogue = record_insns (GET_CODE (seq) == SEQUENCE ? seq : tail); + return; + } + } +#endif + epilogue = 0; +} + +/* Reposition the prologue-end and epilogue-begin notes after instruction + scheduling and delayed branch scheduling. */ + +void +reposition_prologue_and_epilogue_notes (f) + rtx f; +{ +#if defined (HAVE_prologue) || defined (HAVE_epilogue) + /* Reposition the prologue and epilogue notes. */ + if (n_basic_blocks) + { + rtx next, prev; + int len; + + if (prologue) + { + register rtx insn, note = 0; + + /* Scan from the beginning until we reach the last prologue insn. + We apparently can't depend on basic_block_{head,end} after + reorg has run. */ + for (len = 0; prologue[len]; len++) + ; + for (insn = f; len && insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == NOTE) + { + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_PROLOGUE_END) + note = insn; + } + else if ((len -= contains (insn, prologue)) == 0) + { + /* Find the prologue-end note if we haven't already, and + move it to just after the last prologue insn. */ + if (note == 0) + { + for (note = insn; note = NEXT_INSN (note);) + if (GET_CODE (note) == NOTE + && NOTE_LINE_NUMBER (note) == NOTE_INSN_PROLOGUE_END) + break; + } + next = NEXT_INSN (note); + prev = PREV_INSN (note); + if (prev) + NEXT_INSN (prev) = next; + if (next) + PREV_INSN (next) = prev; + add_insn_after (note, insn); + } + } + } + + if (epilogue) + { + register rtx insn, note = 0; + + /* Scan from the end until we reach the first epilogue insn. + We apparently can't depend on basic_block_{head,end} after + reorg has run. */ + for (len = 0; epilogue[len]; len++) + ; + for (insn = get_last_insn (); len && insn; insn = PREV_INSN (insn)) + { + if (GET_CODE (insn) == NOTE) + { + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_EPILOGUE_BEG) + note = insn; + } + else if ((len -= contains (insn, epilogue)) == 0) + { + /* Find the epilogue-begin note if we haven't already, and + move it to just before the first epilogue insn. */ + if (note == 0) + { + for (note = insn; note = PREV_INSN (note);) + if (GET_CODE (note) == NOTE + && NOTE_LINE_NUMBER (note) == NOTE_INSN_EPILOGUE_BEG) + break; + } + next = NEXT_INSN (note); + prev = PREV_INSN (note); + if (prev) + NEXT_INSN (prev) = next; + if (next) + PREV_INSN (next) = prev; + add_insn_after (note, PREV_INSN (insn)); + } + } + } + } +#endif /* HAVE_prologue or HAVE_epilogue */ +} diff --git a/gnu/usr.bin/cc/lib/function.h b/gnu/usr.bin/cc/lib/function.h new file mode 100644 index 000000000000..209e44a93f9b --- /dev/null +++ b/gnu/usr.bin/cc/lib/function.h @@ -0,0 +1,203 @@ +/* Structure for saving state for a nested function. + Copyright (C) 1989, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#ifndef NULL_TREE +#define tree int * +#endif +#ifndef GET_CODE +#define rtx int * +#endif + +struct var_refs_queue + { + rtx modified; + enum machine_mode promoted_mode; + int unsignedp; + struct var_refs_queue *next; + }; + +/* Stack of pending (incomplete) sequences saved by `start_sequence'. + Each element describes one pending sequence. + The main insn-chain is saved in the last element of the chain, + unless the chain is empty. */ + +struct sequence_stack +{ + /* First and last insns in the chain of the saved sequence. */ + rtx first, last; + struct sequence_stack *next; +}; + +extern struct sequence_stack *sequence_stack; + +/* This structure can save all the important global and static variables + describing the status of the current function. */ + +struct function +{ + struct function *next; + + /* For function.c. */ + char *name; + tree decl; + int pops_args; + int returns_struct; + int returns_pcc_struct; + int needs_context; + int calls_setjmp; + int calls_longjmp; + int calls_alloca; + int has_nonlocal_label; + rtx nonlocal_goto_handler_slot; + rtx nonlocal_goto_stack_level; + tree nonlocal_labels; + int args_size; + int pretend_args_size; + rtx arg_offset_rtx; + int max_parm_reg; + rtx *parm_reg_stack_loc; + int outgoing_args_size; + rtx return_rtx; + rtx cleanup_label; + rtx return_label; + rtx save_expr_regs; + rtx stack_slot_list; + rtx parm_birth_insn; + int frame_offset; + rtx tail_recursion_label; + rtx tail_recursion_reentry; + rtx internal_arg_pointer; + rtx arg_pointer_save_area; + tree rtl_expr_chain; + rtx last_parm_insn; + tree context_display; + tree trampoline_list; + int function_call_count; + struct temp_slot *temp_slots; + int temp_slot_level; + /* This slot is initialized as 0 and is added to + during the nested function. */ + struct var_refs_queue *fixup_var_refs_queue; + + /* For stmt.c */ + struct nesting *block_stack; + struct nesting *stack_block_stack; + struct nesting *cond_stack; + struct nesting *loop_stack; + struct nesting *case_stack; + struct nesting *nesting_stack; + int nesting_depth; + int block_start_count; + tree last_expr_type; + rtx last_expr_value; + int expr_stmts_for_value; + char *emit_filename; + int emit_lineno; + struct goto_fixup *goto_fixup_chain; + + /* For expr.c. */ + int pending_stack_adjust; + int inhibit_defer_pop; + tree cleanups_this_call; + rtx saveregs_value; + rtx apply_args_value; + rtx forced_labels; + + /* For emit-rtl.c. */ + int reg_rtx_no; + int first_label_num; + rtx first_insn; + rtx last_insn; + struct sequence_stack *sequence_stack; + int cur_insn_uid; + int last_linenum; + char *last_filename; + char *regno_pointer_flag; + int regno_pointer_flag_length; + rtx *regno_reg_rtx; + + /* For stor-layout.c. */ + tree permanent_type_chain; + tree temporary_type_chain; + tree permanent_type_end; + tree temporary_type_end; + tree pending_sizes; + int immediate_size_expand; + + /* For tree.c. */ + int all_types_permanent; + struct momentary_level *momentary_stack; + char *maybepermanent_firstobj; + char *temporary_firstobj; + char *momentary_firstobj; + struct obstack *current_obstack; + struct obstack *function_obstack; + struct obstack *function_maybepermanent_obstack; + struct obstack *expression_obstack; + struct obstack *saveable_obstack; + struct obstack *rtl_obstack; + + /* For integrate.c. */ + int uses_const_pool; + + /* For md files. */ + int uses_pic_offset_table; + + /* For reorg. */ + rtx epilogue_delay_list; + + /* For varasm. */ + struct constant_descriptor **const_rtx_hash_table; + struct pool_sym **const_rtx_sym_hash_table; + struct pool_constant *first_pool, *last_pool; + int pool_offset; +}; + +/* The FUNCTION_DECL for an inline function currently being expanded. */ +extern tree inline_function_decl; + +/* Label that will go on function epilogue. + Jumping to this label serves as a "return" instruction + on machines which require execution of the epilogue on all returns. */ +extern rtx return_label; + +/* List (chain of EXPR_LISTs) of all stack slots in this function. + Made for the sake of unshare_all_rtl. */ +extern rtx stack_slot_list; + +/* Given a function decl for a containing function, + return the `struct function' for it. */ +struct function *find_function_data PROTO((tree)); + +/* Pointer to chain of `struct function' for containing functions. */ +extern struct function *outer_function_chain; + +/* Put all this function's BLOCK nodes into a vector and return it. + Also store in each NOTE for the beginning or end of a block + the index of that block in the vector. */ +tree *identify_blocks PROTO((tree, rtx)); + +#ifdef rtx +#undef rtx +#endif + +#ifdef tree +#undef tree +#endif diff --git a/gnu/usr.bin/cc/lib/gbl-ctors.h b/gnu/usr.bin/cc/lib/gbl-ctors.h new file mode 100644 index 000000000000..13048cefe454 --- /dev/null +++ b/gnu/usr.bin/cc/lib/gbl-ctors.h @@ -0,0 +1,80 @@ +/* Definitions relating to the special __do_global_init function used + for getting g++ file-scope static objects constructed. This file + will get included either by libgcc2.c (for systems that don't support + a .init section) or by crtstuff.c (for those that do). + + Written by Ron Guilmette (rfg@ncd.com) + +Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* This file contains definitions and declarations of things + relating to the normal start-up-time invocation of C++ + file-scope static object constructors. These declarations + and definitions are used by *both* libgcc2.c and by crtstuff.c. + + Note that this file should only be compiled with GCC. +*/ + +#ifdef HAVE_ATEXIT +extern void atexit (void (*) (void)); +#define ON_EXIT(FUNC,ARG) atexit ((FUNC)) +#else +#ifdef sun +extern void on_exit (void*, void*); +#define ON_EXIT(FUNC,ARG) on_exit ((FUNC), (ARG)) +#endif +#endif + +/* Declare a pointer to void function type. */ + +typedef void (*func_ptr) (void); + +/* Declare the set of symbols use as begin and end markers for the lists + of global object constructors and global object destructors. */ + +extern func_ptr __CTOR_LIST__[]; +extern func_ptr __DTOR_LIST__[]; + +/* Declare the routine which need to get invoked at program exit time. */ + +extern void __do_global_dtors (); + +/* Define a macro with the code which needs to be executed at program + start-up time. This macro is used in two places in crtstuff.c (for + systems which support a .init section) and in one place in libgcc2.c + (for those system which do *not* support a .init section). For all + three places where this code might appear, it must be identical, so + we define it once here as a macro to avoid various instances getting + out-of-sync with one another. */ + +/* The first word may or may not contain the number of pointers in the table. + In all cases, the table is null-terminated. + We ignore the first word and scan up to the null. */ + +/* Some systems use a different strategy for finding the ctors. + For example, svr3. */ +#ifndef DO_GLOBAL_CTORS_BODY +#define DO_GLOBAL_CTORS_BODY \ +do { \ + func_ptr *p; \ + for (p = __CTOR_LIST__ + 1; *p; ) \ + (*p++) (); \ +} while (0) +#endif + diff --git a/gnu/usr.bin/cc/lib/getpwd.c b/gnu/usr.bin/cc/lib/getpwd.c new file mode 100644 index 000000000000..922a9edb1123 --- /dev/null +++ b/gnu/usr.bin/cc/lib/getpwd.c @@ -0,0 +1,94 @@ +/* getpwd.c - get the working directory */ + +#include "config.h" + +#include +#include +#include + +#ifndef errno +extern int errno; +#endif + +/* Virtually every UN*X system now in common use (except for pre-4.3-tahoe + BSD systems) now provides getcwd as called for by POSIX. Allow for + the few exceptions to the general rule here. */ + +#if !(defined (POSIX) || defined (USG) || defined (VMS)) +#include +extern char *getwd (); +#define getcwd(buf,len) getwd(buf) +#define GUESSPATHLEN (MAXPATHLEN + 1) +#else /* (defined (USG) || defined (VMS)) */ +extern char *getcwd (); +/* We actually use this as a starting point, not a limit. */ +#define GUESSPATHLEN 100 +#endif /* (defined (USG) || defined (VMS)) */ + +char *getenv (); +char *xmalloc (); + +#ifndef VMS + +/* Get the working directory. Use the PWD environment variable if it's + set correctly, since this is faster and gives more uniform answers + to the user. Yield the working directory if successful; otherwise, + yield 0 and set errno. */ + +char * +getpwd () +{ + static char *pwd; + static int failure_errno; + + char *p = pwd; + size_t s; + struct stat dotstat, pwdstat; + + if (!p && !(errno = failure_errno)) + { + if (! ((p = getenv ("PWD")) != 0 + && *p == '/' + && stat (p, &pwdstat) == 0 + && stat (".", &dotstat) == 0 + && dotstat.st_ino == pwdstat.st_ino + && dotstat.st_dev == pwdstat.st_dev)) + + /* The shortcut didn't work. Try the slow, ``sure'' way. */ + for (s = GUESSPATHLEN; ! getcwd (p = xmalloc (s), s); s *= 2) + { + int e = errno; + free (p); +#ifdef ERANGE + if (e != ERANGE) +#endif + { + errno = failure_errno = e; + p = 0; + break; + } + } + + /* Cache the result. This assumes that the program does + not invoke chdir between calls to getpwd. */ + pwd = p; + } + return p; +} + +#else /* VMS */ + +#ifndef MAXPATHLEN +#define MAXPATHLEN 255 +#endif + +char * +getpwd () +{ + static char *pwd = 0; + + if (!pwd) pwd = getcwd (xmalloc (MAXPATHLEN+1), MAXPATHLEN+1); + return pwd; +} + +#endif /* VMS */ diff --git a/gnu/usr.bin/cc/lib/glimits.h b/gnu/usr.bin/cc/lib/glimits.h new file mode 100644 index 000000000000..9b4df3d73d85 --- /dev/null +++ b/gnu/usr.bin/cc/lib/glimits.h @@ -0,0 +1,83 @@ +#ifndef _LIMITS_H___ +#ifndef _MACH_MACHLIMITS_H_ + +/* _MACH_MACHLIMITS_H_ is used on OSF/1. */ +#define _LIMITS_H___ +#define _MACH_MACHLIMITS_H_ + +/* Number of bits in a `char'. */ +#undef CHAR_BIT +#define CHAR_BIT 8 + +/* No multibyte characters supported yet. */ +#undef MB_LEN_MAX +#define MB_LEN_MAX 1 + +/* Minimum and maximum values a `signed char' can hold. */ +#undef SCHAR_MIN +#define SCHAR_MIN (-128) +#undef SCHAR_MAX +#define SCHAR_MAX 127 + +/* Maximum value an `unsigned char' can hold. (Minimum is 0). */ +#undef UCHAR_MAX +#define UCHAR_MAX 255 + +/* Minimum and maximum values a `char' can hold. */ +#ifdef __CHAR_UNSIGNED__ +#undef CHAR_MIN +#define CHAR_MIN 0 +#undef CHAR_MAX +#define CHAR_MAX 255 +#else +#undef CHAR_MIN +#define CHAR_MIN (-128) +#undef CHAR_MAX +#define CHAR_MAX 127 +#endif + +/* Minimum and maximum values a `signed short int' can hold. */ +#undef SHRT_MIN +#define SHRT_MIN (-32768) +#undef SHRT_MAX +#define SHRT_MAX 32767 + +/* Maximum value an `unsigned short int' can hold. (Minimum is 0). */ +#undef USHRT_MAX +#define USHRT_MAX 65535 + +/* Minimum and maximum values a `signed int' can hold. */ +#undef INT_MIN +#define INT_MIN (-INT_MAX-1) +#undef INT_MAX +#define INT_MAX 2147483647 + +/* Maximum value an `unsigned int' can hold. (Minimum is 0). */ +#undef UINT_MAX +#define UINT_MAX 4294967295U + +/* Minimum and maximum values a `signed long int' can hold. + (Same as `int'). */ +#undef LONG_MIN +#define LONG_MIN (-LONG_MAX-1) +#undef LONG_MAX +#define LONG_MAX 2147483647L + +/* Maximum value an `unsigned long int' can hold. (Minimum is 0). */ +#undef ULONG_MAX +#define ULONG_MAX 4294967295UL + +#if defined (__GNU_LIBRARY__) ? defined (__USE_GNU) : !defined (__STRICT_ANSI__) +/* Minimum and maximum values a `signed long long int' can hold. */ +#undef LONG_LONG_MIN +#define LONG_LONG_MIN (-LONG_LONG_MAX-1) +#undef LONG_LONG_MAX +#define LONG_LONG_MAX 9223372036854775807LL + +/* Maximum value an `unsigned long long int' can hold. (Minimum is 0). */ +#undef ULONG_LONG_MAX +#define ULONG_LONG_MAX 18446744073709551615ULL +#endif + +#endif /* _MACH_MACHLIMITS_H_ */ +#endif /* _LIMITS_H___ */ diff --git a/gnu/usr.bin/cc/lib/global.c b/gnu/usr.bin/cc/lib/global.c new file mode 100644 index 000000000000..967526e3c30a --- /dev/null +++ b/gnu/usr.bin/cc/lib/global.c @@ -0,0 +1,1660 @@ +/* Allocate registers for pseudo-registers that span basic blocks. + Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include +#include "config.h" +#include "rtl.h" +#include "flags.h" +#include "basic-block.h" +#include "hard-reg-set.h" +#include "regs.h" +#include "insn-config.h" +#include "output.h" + +/* This pass of the compiler performs global register allocation. + It assigns hard register numbers to all the pseudo registers + that were not handled in local_alloc. Assignments are recorded + in the vector reg_renumber, not by changing the rtl code. + (Such changes are made by final). The entry point is + the function global_alloc. + + After allocation is complete, the reload pass is run as a subroutine + of this pass, so that when a pseudo reg loses its hard reg due to + spilling it is possible to make a second attempt to find a hard + reg for it. The reload pass is independent in other respects + and it is run even when stupid register allocation is in use. + + 1. count the pseudo-registers still needing allocation + and assign allocation-numbers (allocnos) to them. + Set up tables reg_allocno and allocno_reg to map + reg numbers to allocnos and vice versa. + max_allocno gets the number of allocnos in use. + + 2. Allocate a max_allocno by max_allocno conflict bit matrix and clear it. + Allocate a max_allocno by FIRST_PSEUDO_REGISTER conflict matrix + for conflicts between allocnos and explicit hard register use + (which includes use of pseudo-registers allocated by local_alloc). + + 3. for each basic block + walk forward through the block, recording which + unallocated registers and which hardware registers are live. + Build the conflict matrix between the unallocated registers + and another of unallocated registers versus hardware registers. + Also record the preferred hardware registers + for each unallocated one. + + 4. Sort a table of the allocnos into order of + desirability of the variables. + + 5. Allocate the variables in that order; each if possible into + a preferred register, else into another register. */ + +/* Number of pseudo-registers still requiring allocation + (not allocated by local_allocate). */ + +static int max_allocno; + +/* Indexed by (pseudo) reg number, gives the allocno, or -1 + for pseudo registers already allocated by local_allocate. */ + +static int *reg_allocno; + +/* Indexed by allocno, gives the reg number. */ + +static int *allocno_reg; + +/* A vector of the integers from 0 to max_allocno-1, + sorted in the order of first-to-be-allocated first. */ + +static int *allocno_order; + +/* Indexed by an allocno, gives the number of consecutive + hard registers needed by that pseudo reg. */ + +static int *allocno_size; + +/* Indexed by (pseudo) reg number, gives the number of another + lower-numbered pseudo reg which can share a hard reg with this pseudo + *even if the two pseudos would otherwise appear to conflict*. */ + +static int *reg_may_share; + +/* Define the number of bits in each element of `conflicts' and what + type that element has. We use the largest integer format on the + host machine. */ + +#define INT_BITS HOST_BITS_PER_WIDE_INT +#define INT_TYPE HOST_WIDE_INT + +/* max_allocno by max_allocno array of bits, + recording whether two allocno's conflict (can't go in the same + hardware register). + + `conflicts' is not symmetric; a conflict between allocno's i and j + is recorded either in element i,j or in element j,i. */ + +static INT_TYPE *conflicts; + +/* Number of ints require to hold max_allocno bits. + This is the length of a row in `conflicts'. */ + +static int allocno_row_words; + +/* Two macros to test or store 1 in an element of `conflicts'. */ + +#define CONFLICTP(I, J) \ + (conflicts[(I) * allocno_row_words + (J) / INT_BITS] \ + & ((INT_TYPE) 1 << ((J) % INT_BITS))) + +#define SET_CONFLICT(I, J) \ + (conflicts[(I) * allocno_row_words + (J) / INT_BITS] \ + |= ((INT_TYPE) 1 << ((J) % INT_BITS))) + +/* Set of hard regs currently live (during scan of all insns). */ + +static HARD_REG_SET hard_regs_live; + +/* Indexed by N, set of hard regs conflicting with allocno N. */ + +static HARD_REG_SET *hard_reg_conflicts; + +/* Indexed by N, set of hard regs preferred by allocno N. + This is used to make allocnos go into regs that are copied to or from them, + when possible, to reduce register shuffling. */ + +static HARD_REG_SET *hard_reg_preferences; + +/* Similar, but just counts register preferences made in simple copy + operations, rather than arithmetic. These are given priority because + we can always eliminate an insn by using these, but using a register + in the above list won't always eliminate an insn. */ + +static HARD_REG_SET *hard_reg_copy_preferences; + +/* Similar to hard_reg_preferences, but includes bits for subsequent + registers when an allocno is multi-word. The above variable is used for + allocation while this is used to build reg_someone_prefers, below. */ + +static HARD_REG_SET *hard_reg_full_preferences; + +/* Indexed by N, set of hard registers that some later allocno has a + preference for. */ + +static HARD_REG_SET *regs_someone_prefers; + +/* Set of registers that global-alloc isn't supposed to use. */ + +static HARD_REG_SET no_global_alloc_regs; + +/* Set of registers used so far. */ + +static HARD_REG_SET regs_used_so_far; + +/* Number of calls crossed by each allocno. */ + +static int *allocno_calls_crossed; + +/* Number of refs (weighted) to each allocno. */ + +static int *allocno_n_refs; + +/* Guess at live length of each allocno. + This is actually the max of the live lengths of the regs. */ + +static int *allocno_live_length; + +/* Number of refs (weighted) to each hard reg, as used by local alloc. + It is zero for a reg that contains global pseudos or is explicitly used. */ + +static int local_reg_n_refs[FIRST_PSEUDO_REGISTER]; + +/* Guess at live length of each hard reg, as used by local alloc. + This is actually the sum of the live lengths of the specific regs. */ + +static int local_reg_live_length[FIRST_PSEUDO_REGISTER]; + +/* Test a bit in TABLE, a vector of HARD_REG_SETs, + for vector element I, and hard register number J. */ + +#define REGBITP(TABLE, I, J) TEST_HARD_REG_BIT (TABLE[I], J) + +/* Set to 1 a bit in a vector of HARD_REG_SETs. Works like REGBITP. */ + +#define SET_REGBIT(TABLE, I, J) SET_HARD_REG_BIT (TABLE[I], J) + +/* Bit mask for allocnos live at current point in the scan. */ + +static INT_TYPE *allocnos_live; + +/* Test, set or clear bit number I in allocnos_live, + a bit vector indexed by allocno. */ + +#define ALLOCNO_LIVE_P(I) \ + (allocnos_live[(I) / INT_BITS] & ((INT_TYPE) 1 << ((I) % INT_BITS))) + +#define SET_ALLOCNO_LIVE(I) \ + (allocnos_live[(I) / INT_BITS] |= ((INT_TYPE) 1 << ((I) % INT_BITS))) + +#define CLEAR_ALLOCNO_LIVE(I) \ + (allocnos_live[(I) / INT_BITS] &= ~((INT_TYPE) 1 << ((I) % INT_BITS))) + +/* This is turned off because it doesn't work right for DImode. + (And it is only used for DImode, so the other cases are worthless.) + The problem is that it isn't true that there is NO possibility of conflict; + only that there is no conflict if the two pseudos get the exact same regs. + If they were allocated with a partial overlap, there would be a conflict. + We can't safely turn off the conflict unless we have another way to + prevent the partial overlap. + + Idea: change hard_reg_conflicts so that instead of recording which + hard regs the allocno may not overlap, it records where the allocno + may not start. Change both where it is used and where it is updated. + Then there is a way to record that (reg:DI 108) may start at 10 + but not at 9 or 11. There is still the question of how to record + this semi-conflict between two pseudos. */ +#if 0 +/* Reg pairs for which conflict after the current insn + is inhibited by a REG_NO_CONFLICT note. + If the table gets full, we ignore any other notes--that is conservative. */ +#define NUM_NO_CONFLICT_PAIRS 4 +/* Number of pairs in use in this insn. */ +int n_no_conflict_pairs; +static struct { int allocno1, allocno2;} + no_conflict_pairs[NUM_NO_CONFLICT_PAIRS]; +#endif /* 0 */ + +/* Record all regs that are set in any one insn. + Communication from mark_reg_{store,clobber} and global_conflicts. */ + +static rtx *regs_set; +static int n_regs_set; + +/* All register that can be eliminated. */ + +static HARD_REG_SET eliminable_regset; + +static int allocno_compare (); +static void mark_reg_store (); +static void mark_reg_clobber (); +static void mark_reg_conflicts (); +static void mark_reg_live_nc (); +static void mark_reg_death (); +static void dump_conflicts (); +void dump_global_regs (); +static void find_reg (); +static void global_conflicts (); +static void expand_preferences (); +static void prune_preferences (); +static void record_conflicts (); +static void set_preference (); + +/* Perform allocation of pseudo-registers not allocated by local_alloc. + FILE is a file to output debugging information on, + or zero if such output is not desired. + + Return value is nonzero if reload failed + and we must not do any more for this function. */ + +int +global_alloc (file) + FILE *file; +{ +#ifdef ELIMINABLE_REGS + static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; +#endif + register int i; + rtx x; + + max_allocno = 0; + + /* A machine may have certain hard registers that + are safe to use only within a basic block. */ + + CLEAR_HARD_REG_SET (no_global_alloc_regs); +#ifdef OVERLAPPING_REGNO_P + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (OVERLAPPING_REGNO_P (i)) + SET_HARD_REG_BIT (no_global_alloc_regs, i); +#endif + + /* Build the regset of all eliminable registers and show we can't use those + that we already know won't be eliminated. */ +#ifdef ELIMINABLE_REGS + for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++) + { + SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); + + if (! CAN_ELIMINATE (eliminables[i].from, eliminables[i].to) + || (eliminables[i].from == FRAME_POINTER_REGNUM + && (! flag_omit_frame_pointer || FRAME_POINTER_REQUIRED))) + SET_HARD_REG_BIT (no_global_alloc_regs, eliminables[i].from); + } +#else + SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); + + /* If we know we will definitely not be eliminating the frame pointer, + don't allocate it. */ + if (! flag_omit_frame_pointer || FRAME_POINTER_REQUIRED) + SET_HARD_REG_BIT (no_global_alloc_regs, FRAME_POINTER_REGNUM); +#endif + + /* Track which registers have already been used. Start with registers + explicitly in the rtl, then registers allocated by local register + allocation. */ + + CLEAR_HARD_REG_SET (regs_used_so_far); +#ifdef LEAF_REGISTERS + /* If we are doing the leaf function optimization, and this is a leaf + function, it means that the registers that take work to save are those + that need a register window. So prefer the ones that can be used in + a leaf function. */ + { + char *cheap_regs; + static char leaf_regs[] = LEAF_REGISTERS; + + if (only_leaf_regs_used () && leaf_function_p ()) + cheap_regs = leaf_regs; + else + cheap_regs = call_used_regs; + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (regs_ever_live[i] || cheap_regs[i]) + SET_HARD_REG_BIT (regs_used_so_far, i); + } +#else + /* We consider registers that do not have to be saved over calls as if + they were already used since there is no cost in using them. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (regs_ever_live[i] || call_used_regs[i]) + SET_HARD_REG_BIT (regs_used_so_far, i); +#endif + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (reg_renumber[i] >= 0) + SET_HARD_REG_BIT (regs_used_so_far, reg_renumber[i]); + + /* Establish mappings from register number to allocation number + and vice versa. In the process, count the allocnos. */ + + reg_allocno = (int *) alloca (max_regno * sizeof (int)); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + reg_allocno[i] = -1; + + /* Initialize the shared-hard-reg mapping + from the list of pairs that may share. */ + reg_may_share = (int *) alloca (max_regno * sizeof (int)); + bzero (reg_may_share, max_regno * sizeof (int)); + for (x = regs_may_share; x; x = XEXP (XEXP (x, 1), 1)) + { + int r1 = REGNO (XEXP (x, 0)); + int r2 = REGNO (XEXP (XEXP (x, 1), 0)); + if (r1 > r2) + reg_may_share[r1] = r2; + else + reg_may_share[r2] = r1; + } + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + /* Note that reg_live_length[i] < 0 indicates a "constant" reg + that we are supposed to refrain from putting in a hard reg. + -2 means do make an allocno but don't allocate it. */ + if (reg_n_refs[i] != 0 && reg_renumber[i] < 0 && reg_live_length[i] != -1 + /* Don't allocate pseudos that cross calls, + if this function receives a nonlocal goto. */ + && (! current_function_has_nonlocal_label + || reg_n_calls_crossed[i] == 0)) + { + if (reg_may_share[i] && reg_allocno[reg_may_share[i]] >= 0) + reg_allocno[i] = reg_allocno[reg_may_share[i]]; + else + reg_allocno[i] = max_allocno++; + if (reg_live_length[i] == 0) + abort (); + } + else + reg_allocno[i] = -1; + + allocno_reg = (int *) alloca (max_allocno * sizeof (int)); + allocno_size = (int *) alloca (max_allocno * sizeof (int)); + allocno_calls_crossed = (int *) alloca (max_allocno * sizeof (int)); + allocno_n_refs = (int *) alloca (max_allocno * sizeof (int)); + allocno_live_length = (int *) alloca (max_allocno * sizeof (int)); + bzero (allocno_size, max_allocno * sizeof (int)); + bzero (allocno_calls_crossed, max_allocno * sizeof (int)); + bzero (allocno_n_refs, max_allocno * sizeof (int)); + bzero (allocno_live_length, max_allocno * sizeof (int)); + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (reg_allocno[i] >= 0) + { + int allocno = reg_allocno[i]; + allocno_reg[allocno] = i; + allocno_size[allocno] = PSEUDO_REGNO_SIZE (i); + allocno_calls_crossed[allocno] += reg_n_calls_crossed[i]; + allocno_n_refs[allocno] += reg_n_refs[i]; + if (allocno_live_length[allocno] < reg_live_length[i]) + allocno_live_length[allocno] = reg_live_length[i]; + } + + /* Calculate amount of usage of each hard reg by pseudos + allocated by local-alloc. This is to see if we want to + override it. */ + bzero (local_reg_live_length, sizeof local_reg_live_length); + bzero (local_reg_n_refs, sizeof local_reg_n_refs); + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (reg_allocno[i] < 0 && reg_renumber[i] >= 0) + { + int regno = reg_renumber[i]; + int endregno = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i)); + int j; + + for (j = regno; j < endregno; j++) + { + local_reg_n_refs[j] += reg_n_refs[i]; + local_reg_live_length[j] += reg_live_length[i]; + } + } + + /* We can't override local-alloc for a reg used not just by local-alloc. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (regs_ever_live[i]) + local_reg_n_refs[i] = 0; + + /* Allocate the space for the conflict and preference tables and + initialize them. */ + + hard_reg_conflicts + = (HARD_REG_SET *) alloca (max_allocno * sizeof (HARD_REG_SET)); + bzero (hard_reg_conflicts, max_allocno * sizeof (HARD_REG_SET)); + + hard_reg_preferences + = (HARD_REG_SET *) alloca (max_allocno * sizeof (HARD_REG_SET)); + bzero (hard_reg_preferences, max_allocno * sizeof (HARD_REG_SET)); + + hard_reg_copy_preferences + = (HARD_REG_SET *) alloca (max_allocno * sizeof (HARD_REG_SET)); + bzero (hard_reg_copy_preferences, max_allocno * sizeof (HARD_REG_SET)); + + hard_reg_full_preferences + = (HARD_REG_SET *) alloca (max_allocno * sizeof (HARD_REG_SET)); + bzero (hard_reg_full_preferences, max_allocno * sizeof (HARD_REG_SET)); + + regs_someone_prefers + = (HARD_REG_SET *) alloca (max_allocno * sizeof (HARD_REG_SET)); + bzero (regs_someone_prefers, max_allocno * sizeof (HARD_REG_SET)); + + allocno_row_words = (max_allocno + INT_BITS - 1) / INT_BITS; + + conflicts = (INT_TYPE *) alloca (max_allocno * allocno_row_words + * sizeof (INT_TYPE)); + bzero (conflicts, max_allocno * allocno_row_words + * sizeof (INT_TYPE)); + + allocnos_live = (INT_TYPE *) alloca (allocno_row_words * sizeof (INT_TYPE)); + + /* If there is work to be done (at least one reg to allocate), + perform global conflict analysis and allocate the regs. */ + + if (max_allocno > 0) + { + /* Scan all the insns and compute the conflicts among allocnos + and between allocnos and hard regs. */ + + global_conflicts (); + + /* Eliminate conflicts between pseudos and eliminable registers. If + the register is not eliminated, the pseudo won't really be able to + live in the eliminable register, so the conflict doesn't matter. + If we do eliminate the register, the conflict will no longer exist. + So in either case, we can ignore the conflict. Likewise for + preferences. */ + + for (i = 0; i < max_allocno; i++) + { + AND_COMPL_HARD_REG_SET (hard_reg_conflicts[i], eliminable_regset); + AND_COMPL_HARD_REG_SET (hard_reg_copy_preferences[i], + eliminable_regset); + AND_COMPL_HARD_REG_SET (hard_reg_preferences[i], eliminable_regset); + } + + /* Try to expand the preferences by merging them between allocnos. */ + + expand_preferences (); + + /* Determine the order to allocate the remaining pseudo registers. */ + + allocno_order = (int *) alloca (max_allocno * sizeof (int)); + for (i = 0; i < max_allocno; i++) + allocno_order[i] = i; + + /* Default the size to 1, since allocno_compare uses it to divide by. + Also convert allocno_live_length of zero to -1. A length of zero + can occur when all the registers for that allocno have reg_live_length + equal to -2. In this case, we want to make an allocno, but not + allocate it. So avoid the divide-by-zero and set it to a low + priority. */ + + for (i = 0; i < max_allocno; i++) + { + if (allocno_size[i] == 0) + allocno_size[i] = 1; + if (allocno_live_length[i] == 0) + allocno_live_length[i] = -1; + } + + qsort (allocno_order, max_allocno, sizeof (int), allocno_compare); + + prune_preferences (); + + if (file) + dump_conflicts (file); + + /* Try allocating them, one by one, in that order, + except for parameters marked with reg_live_length[regno] == -2. */ + + for (i = 0; i < max_allocno; i++) + if (reg_live_length[allocno_reg[allocno_order[i]]] >= 0) + { + /* If we have more than one register class, + first try allocating in the class that is cheapest + for this pseudo-reg. If that fails, try any reg. */ + if (N_REG_CLASSES > 1) + { + find_reg (allocno_order[i], HARD_CONST (0), 0, 0, 0); + if (reg_renumber[allocno_reg[allocno_order[i]]] >= 0) + continue; + } + if (reg_alternate_class (allocno_reg[allocno_order[i]]) != NO_REGS) + find_reg (allocno_order[i], HARD_CONST (0), 1, 0, 0); + } + } + + /* Do the reloads now while the allocno data still exist, so that we can + try to assign new hard regs to any pseudo regs that are spilled. */ + +#if 0 /* We need to eliminate regs even if there is no rtl code, + for the sake of debugging information. */ + if (n_basic_blocks > 0) +#endif + return reload (get_insns (), 1, file); +} + +/* Sort predicate for ordering the allocnos. + Returns -1 (1) if *v1 should be allocated before (after) *v2. */ + +static int +allocno_compare (v1, v2) + int *v1, *v2; +{ + /* Note that the quotient will never be bigger than + the value of floor_log2 times the maximum number of + times a register can occur in one insn (surely less than 100). + Multiplying this by 10000 can't overflow. */ + register int pri1 + = (((double) (floor_log2 (allocno_n_refs[*v1]) * allocno_n_refs[*v1]) + / (allocno_live_length[*v1] * allocno_size[*v1])) + * 10000); + register int pri2 + = (((double) (floor_log2 (allocno_n_refs[*v2]) * allocno_n_refs[*v2]) + / (allocno_live_length[*v2] * allocno_size[*v2])) + * 10000); + if (pri2 - pri1) + return pri2 - pri1; + + /* If regs are equally good, sort by allocno, + so that the results of qsort leave nothing to chance. */ + return *v1 - *v2; +} + +/* Scan the rtl code and record all conflicts and register preferences in the + conflict matrices and preference tables. */ + +static void +global_conflicts () +{ + register int b, i; + register rtx insn; + short *block_start_allocnos; + + /* Make a vector that mark_reg_{store,clobber} will store in. */ + regs_set = (rtx *) alloca (max_parallel * sizeof (rtx) * 2); + + block_start_allocnos = (short *) alloca (max_allocno * sizeof (short)); + + for (b = 0; b < n_basic_blocks; b++) + { + bzero (allocnos_live, allocno_row_words * sizeof (INT_TYPE)); + + /* Initialize table of registers currently live + to the state at the beginning of this basic block. + This also marks the conflicts among them. + + For pseudo-regs, there is only one bit for each one + no matter how many hard regs it occupies. + This is ok; we know the size from PSEUDO_REGNO_SIZE. + For explicit hard regs, we cannot know the size that way + since one hard reg can be used with various sizes. + Therefore, we must require that all the hard regs + implicitly live as part of a multi-word hard reg + are explicitly marked in basic_block_live_at_start. */ + + { + register int offset; + REGSET_ELT_TYPE bit; + register regset old = basic_block_live_at_start[b]; + int ax = 0; + +#ifdef HARD_REG_SET + hard_regs_live = old[0]; +#else + COPY_HARD_REG_SET (hard_regs_live, old); +#endif + for (offset = 0, i = 0; offset < regset_size; offset++) + if (old[offset] == 0) + i += REGSET_ELT_BITS; + else + for (bit = 1; bit; bit <<= 1, i++) + { + if (i >= max_regno) + break; + if (old[offset] & bit) + { + register int a = reg_allocno[i]; + if (a >= 0) + { + SET_ALLOCNO_LIVE (a); + block_start_allocnos[ax++] = a; + } + else if ((a = reg_renumber[i]) >= 0) + mark_reg_live_nc (a, PSEUDO_REGNO_MODE (i)); + } + } + + /* Record that each allocno now live conflicts with each other + allocno now live, and with each hard reg now live. */ + + record_conflicts (block_start_allocnos, ax); + } + + insn = basic_block_head[b]; + + /* Scan the code of this basic block, noting which allocnos + and hard regs are born or die. When one is born, + record a conflict with all others currently live. */ + + while (1) + { + register RTX_CODE code = GET_CODE (insn); + register rtx link; + + /* Make regs_set an empty set. */ + + n_regs_set = 0; + + if (code == INSN || code == CALL_INSN || code == JUMP_INSN) + { + int i = 0; + +#if 0 + for (link = REG_NOTES (insn); + link && i < NUM_NO_CONFLICT_PAIRS; + link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_NO_CONFLICT) + { + no_conflict_pairs[i].allocno1 + = reg_allocno[REGNO (SET_DEST (PATTERN (insn)))]; + no_conflict_pairs[i].allocno2 + = reg_allocno[REGNO (XEXP (link, 0))]; + i++; + } +#endif /* 0 */ + + /* Mark any registers clobbered by INSN as live, + so they conflict with the inputs. */ + + note_stores (PATTERN (insn), mark_reg_clobber); + + /* Mark any registers dead after INSN as dead now. */ + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_DEAD) + mark_reg_death (XEXP (link, 0)); + + /* Mark any registers set in INSN as live, + and mark them as conflicting with all other live regs. + Clobbers are processed again, so they conflict with + the registers that are set. */ + + note_stores (PATTERN (insn), mark_reg_store); + +#ifdef AUTO_INC_DEC + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_INC) + mark_reg_store (XEXP (link, 0), NULL_RTX); +#endif + + /* If INSN has multiple outputs, then any reg that dies here + and is used inside of an output + must conflict with the other outputs. */ + + if (GET_CODE (PATTERN (insn)) == PARALLEL && !single_set (insn)) + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_DEAD) + { + int used_in_output = 0; + int i; + rtx reg = XEXP (link, 0); + + for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) + { + rtx set = XVECEXP (PATTERN (insn), 0, i); + if (GET_CODE (set) == SET + && GET_CODE (SET_DEST (set)) != REG + && !rtx_equal_p (reg, SET_DEST (set)) + && reg_overlap_mentioned_p (reg, SET_DEST (set))) + used_in_output = 1; + } + if (used_in_output) + mark_reg_conflicts (reg); + } + + /* Mark any registers set in INSN and then never used. */ + + while (n_regs_set > 0) + if (find_regno_note (insn, REG_UNUSED, + REGNO (regs_set[--n_regs_set]))) + mark_reg_death (regs_set[n_regs_set]); + } + + if (insn == basic_block_end[b]) + break; + insn = NEXT_INSN (insn); + } + } +} +/* Expand the preference information by looking for cases where one allocno + dies in an insn that sets an allocno. If those two allocnos don't conflict, + merge any preferences between those allocnos. */ + +static void +expand_preferences () +{ + rtx insn; + rtx link; + rtx set; + + /* We only try to handle the most common cases here. Most of the cases + where this wins are reg-reg copies. */ + + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && (set = single_set (insn)) != 0 + && GET_CODE (SET_DEST (set)) == REG + && reg_allocno[REGNO (SET_DEST (set))] >= 0) + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_DEAD + && GET_CODE (XEXP (link, 0)) == REG + && reg_allocno[REGNO (XEXP (link, 0))] >= 0 + && ! CONFLICTP (reg_allocno[REGNO (SET_DEST (set))], + reg_allocno[REGNO (XEXP (link, 0))]) + && ! CONFLICTP (reg_allocno[REGNO (XEXP (link, 0))], + reg_allocno[REGNO (SET_DEST (set))])) + { + int a1 = reg_allocno[REGNO (SET_DEST (set))]; + int a2 = reg_allocno[REGNO (XEXP (link, 0))]; + + if (XEXP (link, 0) == SET_SRC (set)) + { + IOR_HARD_REG_SET (hard_reg_copy_preferences[a1], + hard_reg_copy_preferences[a2]); + IOR_HARD_REG_SET (hard_reg_copy_preferences[a2], + hard_reg_copy_preferences[a1]); + } + + IOR_HARD_REG_SET (hard_reg_preferences[a1], + hard_reg_preferences[a2]); + IOR_HARD_REG_SET (hard_reg_preferences[a2], + hard_reg_preferences[a1]); + IOR_HARD_REG_SET (hard_reg_full_preferences[a1], + hard_reg_full_preferences[a2]); + IOR_HARD_REG_SET (hard_reg_full_preferences[a2], + hard_reg_full_preferences[a1]); + } +} + +/* Prune the preferences for global registers to exclude registers that cannot + be used. + + Compute `regs_someone_prefers', which is a bitmask of the hard registers + that are preferred by conflicting registers of lower priority. If possible, + we will avoid using these registers. */ + +static void +prune_preferences () +{ + int i, j; + int allocno; + + /* Scan least most important to most important. + For each allocno, remove from preferences registers that cannot be used, + either because of conflicts or register type. Then compute all registers + preferred by each lower-priority register that conflicts. */ + + for (i = max_allocno - 1; i >= 0; i--) + { + HARD_REG_SET temp; + + allocno = allocno_order[i]; + COPY_HARD_REG_SET (temp, hard_reg_conflicts[allocno]); + + if (allocno_calls_crossed[allocno] == 0) + IOR_HARD_REG_SET (temp, fixed_reg_set); + else + IOR_HARD_REG_SET (temp, call_used_reg_set); + + IOR_COMPL_HARD_REG_SET + (temp, + reg_class_contents[(int) reg_preferred_class (allocno_reg[allocno])]); + + AND_COMPL_HARD_REG_SET (hard_reg_preferences[allocno], temp); + AND_COMPL_HARD_REG_SET (hard_reg_copy_preferences[allocno], temp); + AND_COMPL_HARD_REG_SET (hard_reg_full_preferences[allocno], temp); + + CLEAR_HARD_REG_SET (regs_someone_prefers[allocno]); + + /* Merge in the preferences of lower-priority registers (they have + already been pruned). If we also prefer some of those registers, + don't exclude them unless we are of a smaller size (in which case + we want to give the lower-priority allocno the first chance for + these registers). */ + for (j = i + 1; j < max_allocno; j++) + if (CONFLICTP (allocno, allocno_order[j])) + { + COPY_HARD_REG_SET (temp, + hard_reg_full_preferences[allocno_order[j]]); + if (allocno_size[allocno_order[j]] <= allocno_size[allocno]) + AND_COMPL_HARD_REG_SET (temp, + hard_reg_full_preferences[allocno]); + + IOR_HARD_REG_SET (regs_someone_prefers[allocno], temp); + } + } +} + +/* Assign a hard register to ALLOCNO; look for one that is the beginning + of a long enough stretch of hard regs none of which conflicts with ALLOCNO. + The registers marked in PREFREGS are tried first. + + LOSERS, if non-zero, is a HARD_REG_SET indicating registers that cannot + be used for this allocation. + + If ALT_REGS_P is zero, consider only the preferred class of ALLOCNO's reg. + Otherwise ignore that preferred class and use the alternate class. + + If ACCEPT_CALL_CLOBBERED is nonzero, accept a call-clobbered hard reg that + will have to be saved and restored at calls. + + RETRYING is nonzero if this is called from retry_global_alloc. + + If we find one, record it in reg_renumber. + If not, do nothing. */ + +static void +find_reg (allocno, losers, alt_regs_p, accept_call_clobbered, retrying) + int allocno; + HARD_REG_SET losers; + int alt_regs_p; + int accept_call_clobbered; + int retrying; +{ + register int i, best_reg, pass; +#ifdef HARD_REG_SET + register /* Declare it register if it's a scalar. */ +#endif + HARD_REG_SET used, used1, used2; + + enum reg_class class = (alt_regs_p + ? reg_alternate_class (allocno_reg[allocno]) + : reg_preferred_class (allocno_reg[allocno])); + enum machine_mode mode = PSEUDO_REGNO_MODE (allocno_reg[allocno]); + + if (accept_call_clobbered) + COPY_HARD_REG_SET (used1, call_fixed_reg_set); + else if (allocno_calls_crossed[allocno] == 0) + COPY_HARD_REG_SET (used1, fixed_reg_set); + else + COPY_HARD_REG_SET (used1, call_used_reg_set); + + /* Some registers should not be allocated in global-alloc. */ + IOR_HARD_REG_SET (used1, no_global_alloc_regs); + if (losers) + IOR_HARD_REG_SET (used1, losers); + + IOR_COMPL_HARD_REG_SET (used1, reg_class_contents[(int) class]); + COPY_HARD_REG_SET (used2, used1); + + IOR_HARD_REG_SET (used1, hard_reg_conflicts[allocno]); + + /* Try each hard reg to see if it fits. Do this in two passes. + In the first pass, skip registers that are preferred by some other pseudo + to give it a better chance of getting one of those registers. Only if + we can't get a register when excluding those do we take one of them. + However, we never allocate a register for the first time in pass 0. */ + + COPY_HARD_REG_SET (used, used1); + IOR_COMPL_HARD_REG_SET (used, regs_used_so_far); + IOR_HARD_REG_SET (used, regs_someone_prefers[allocno]); + + best_reg = -1; + for (i = FIRST_PSEUDO_REGISTER, pass = 0; + pass <= 1 && i >= FIRST_PSEUDO_REGISTER; + pass++) + { + if (pass == 1) + COPY_HARD_REG_SET (used, used1); + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { +#ifdef REG_ALLOC_ORDER + int regno = reg_alloc_order[i]; +#else + int regno = i; +#endif + if (! TEST_HARD_REG_BIT (used, regno) + && HARD_REGNO_MODE_OK (regno, mode)) + { + register int j; + register int lim = regno + HARD_REGNO_NREGS (regno, mode); + for (j = regno + 1; + (j < lim + && ! TEST_HARD_REG_BIT (used, j)); + j++); + if (j == lim) + { + best_reg = regno; + break; + } +#ifndef REG_ALLOC_ORDER + i = j; /* Skip starting points we know will lose */ +#endif + } + } + } + + /* See if there is a preferred register with the same class as the register + we allocated above. Making this restriction prevents register + preferencing from creating worse register allocation. + + Remove from the preferred registers and conflicting registers. Note that + additional conflicts may have been added after `prune_preferences' was + called. + + First do this for those register with copy preferences, then all + preferred registers. */ + + AND_COMPL_HARD_REG_SET (hard_reg_copy_preferences[allocno], used); + GO_IF_HARD_REG_SUBSET (hard_reg_copy_preferences[allocno], + reg_class_contents[(int) NO_REGS], no_copy_prefs); + + if (best_reg >= 0) + { + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (TEST_HARD_REG_BIT (hard_reg_copy_preferences[allocno], i) + && HARD_REGNO_MODE_OK (i, mode) + && (REGNO_REG_CLASS (i) == REGNO_REG_CLASS (best_reg) + || reg_class_subset_p (REGNO_REG_CLASS (i), + REGNO_REG_CLASS (best_reg)) + || reg_class_subset_p (REGNO_REG_CLASS (best_reg), + REGNO_REG_CLASS (i)))) + { + register int j; + register int lim = i + HARD_REGNO_NREGS (i, mode); + for (j = i + 1; + (j < lim + && ! TEST_HARD_REG_BIT (used, j) + && (REGNO_REG_CLASS (j) + == REGNO_REG_CLASS (best_reg + (j - i)) + || reg_class_subset_p (REGNO_REG_CLASS (j), + REGNO_REG_CLASS (best_reg + (j - i))) + || reg_class_subset_p (REGNO_REG_CLASS (best_reg + (j - i)), + REGNO_REG_CLASS (j)))); + j++); + if (j == lim) + { + best_reg = i; + goto no_prefs; + } + } + } + no_copy_prefs: + + AND_COMPL_HARD_REG_SET (hard_reg_preferences[allocno], used); + GO_IF_HARD_REG_SUBSET (hard_reg_preferences[allocno], + reg_class_contents[(int) NO_REGS], no_prefs); + + if (best_reg >= 0) + { + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (TEST_HARD_REG_BIT (hard_reg_preferences[allocno], i) + && HARD_REGNO_MODE_OK (i, mode) + && (REGNO_REG_CLASS (i) == REGNO_REG_CLASS (best_reg) + || reg_class_subset_p (REGNO_REG_CLASS (i), + REGNO_REG_CLASS (best_reg)) + || reg_class_subset_p (REGNO_REG_CLASS (best_reg), + REGNO_REG_CLASS (i)))) + { + register int j; + register int lim = i + HARD_REGNO_NREGS (i, mode); + for (j = i + 1; + (j < lim + && ! TEST_HARD_REG_BIT (used, j) + && (REGNO_REG_CLASS (j) + == REGNO_REG_CLASS (best_reg + (j - i)) + || reg_class_subset_p (REGNO_REG_CLASS (j), + REGNO_REG_CLASS (best_reg + (j - i))) + || reg_class_subset_p (REGNO_REG_CLASS (best_reg + (j - i)), + REGNO_REG_CLASS (j)))); + j++); + if (j == lim) + { + best_reg = i; + break; + } + } + } + no_prefs: + + /* If we haven't succeeded yet, try with caller-saves. + We need not check to see if the current function has nonlocal + labels because we don't put any pseudos that are live over calls in + registers in that case. */ + + if (flag_caller_saves && best_reg < 0) + { + /* Did not find a register. If it would be profitable to + allocate a call-clobbered register and save and restore it + around calls, do that. */ + if (! accept_call_clobbered + && allocno_calls_crossed[allocno] != 0 + && CALLER_SAVE_PROFITABLE (allocno_n_refs[allocno], + allocno_calls_crossed[allocno])) + { + find_reg (allocno, losers, alt_regs_p, 1, retrying); + if (reg_renumber[allocno_reg[allocno]] >= 0) + { + caller_save_needed = 1; + return; + } + } + } + + /* If we haven't succeeded yet, + see if some hard reg that conflicts with us + was utilized poorly by local-alloc. + If so, kick out the regs that were put there by local-alloc + so we can use it instead. */ + if (best_reg < 0 && !retrying + /* Let's not bother with multi-reg allocnos. */ + && allocno_size[allocno] == 1) + { + /* Count from the end, to find the least-used ones first. */ + for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) + if (local_reg_n_refs[i] != 0 + /* Don't use a reg no good for this pseudo. */ + && ! TEST_HARD_REG_BIT (used2, i) + && HARD_REGNO_MODE_OK (i, mode) + && ((double) local_reg_n_refs[i] / local_reg_live_length[i] + < ((double) allocno_n_refs[allocno] + / allocno_live_length[allocno]))) + { + /* Hard reg I was used less in total by local regs + than it would be used by this one allocno! */ + int k; + for (k = 0; k < max_regno; k++) + if (reg_renumber[k] >= 0) + { + int regno = reg_renumber[k]; + int endregno + = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (k)); + + if (i >= regno && i < endregno) + reg_renumber[k] = -1; + } + + best_reg = i; + break; + } + } + + /* Did we find a register? */ + + if (best_reg >= 0) + { + register int lim, j; + HARD_REG_SET this_reg; + + /* Yes. Record it as the hard register of this pseudo-reg. */ + reg_renumber[allocno_reg[allocno]] = best_reg; + /* Also of any pseudo-regs that share with it. */ + if (reg_may_share[allocno_reg[allocno]]) + for (j = FIRST_PSEUDO_REGISTER; j < max_regno; j++) + if (reg_allocno[j] == allocno) + reg_renumber[j] = best_reg; + + /* Make a set of the hard regs being allocated. */ + CLEAR_HARD_REG_SET (this_reg); + lim = best_reg + HARD_REGNO_NREGS (best_reg, mode); + for (j = best_reg; j < lim; j++) + { + SET_HARD_REG_BIT (this_reg, j); + SET_HARD_REG_BIT (regs_used_so_far, j); + /* This is no longer a reg used just by local regs. */ + local_reg_n_refs[j] = 0; + } + /* For each other pseudo-reg conflicting with this one, + mark it as conflicting with the hard regs this one occupies. */ + lim = allocno; + for (j = 0; j < max_allocno; j++) + if (CONFLICTP (lim, j) || CONFLICTP (j, lim)) + { + IOR_HARD_REG_SET (hard_reg_conflicts[j], this_reg); + } + } +} + +/* Called from `reload' to look for a hard reg to put pseudo reg REGNO in. + Perhaps it had previously seemed not worth a hard reg, + or perhaps its old hard reg has been commandeered for reloads. + FORBIDDEN_REGS indicates certain hard regs that may not be used, even if + they do not appear to be allocated. + If FORBIDDEN_REGS is zero, no regs are forbidden. */ + +void +retry_global_alloc (regno, forbidden_regs) + int regno; + HARD_REG_SET forbidden_regs; +{ + int allocno = reg_allocno[regno]; + if (allocno >= 0) + { + /* If we have more than one register class, + first try allocating in the class that is cheapest + for this pseudo-reg. If that fails, try any reg. */ + if (N_REG_CLASSES > 1) + find_reg (allocno, forbidden_regs, 0, 0, 1); + if (reg_renumber[regno] < 0 + && reg_alternate_class (regno) != NO_REGS) + find_reg (allocno, forbidden_regs, 1, 0, 1); + + /* If we found a register, modify the RTL for the register to + show the hard register, and mark that register live. */ + if (reg_renumber[regno] >= 0) + { + REGNO (regno_reg_rtx[regno]) = reg_renumber[regno]; + mark_home_live (regno); + } + } +} + +/* Record a conflict between register REGNO + and everything currently live. + REGNO must not be a pseudo reg that was allocated + by local_alloc; such numbers must be translated through + reg_renumber before calling here. */ + +static void +record_one_conflict (regno) + int regno; +{ + register int j; + + if (regno < FIRST_PSEUDO_REGISTER) + /* When a hard register becomes live, + record conflicts with live pseudo regs. */ + for (j = 0; j < max_allocno; j++) + { + if (ALLOCNO_LIVE_P (j)) + SET_HARD_REG_BIT (hard_reg_conflicts[j], regno); + } + else + /* When a pseudo-register becomes live, + record conflicts first with hard regs, + then with other pseudo regs. */ + { + register int ialloc = reg_allocno[regno]; + register int ialloc_prod = ialloc * allocno_row_words; + IOR_HARD_REG_SET (hard_reg_conflicts[ialloc], hard_regs_live); + for (j = allocno_row_words - 1; j >= 0; j--) + { +#if 0 + int k; + for (k = 0; k < n_no_conflict_pairs; k++) + if (! ((j == no_conflict_pairs[k].allocno1 + && ialloc == no_conflict_pairs[k].allocno2) + || + (j == no_conflict_pairs[k].allocno2 + && ialloc == no_conflict_pairs[k].allocno1))) +#endif /* 0 */ + conflicts[ialloc_prod + j] |= allocnos_live[j]; + } + } +} + +/* Record all allocnos currently live as conflicting + with each other and with all hard regs currently live. + ALLOCNO_VEC is a vector of LEN allocnos, all allocnos that + are currently live. Their bits are also flagged in allocnos_live. */ + +static void +record_conflicts (allocno_vec, len) + register short *allocno_vec; + register int len; +{ + register int allocno; + register int j; + register int ialloc_prod; + + while (--len >= 0) + { + allocno = allocno_vec[len]; + ialloc_prod = allocno * allocno_row_words; + IOR_HARD_REG_SET (hard_reg_conflicts[allocno], hard_regs_live); + for (j = allocno_row_words - 1; j >= 0; j--) + conflicts[ialloc_prod + j] |= allocnos_live[j]; + } +} + +/* Handle the case where REG is set by the insn being scanned, + during the forward scan to accumulate conflicts. + Store a 1 in regs_live or allocnos_live for this register, record how many + consecutive hardware registers it actually needs, + and record a conflict with all other registers already live. + + Note that even if REG does not remain alive after this insn, + we must mark it here as live, to ensure a conflict between + REG and any other regs set in this insn that really do live. + This is because those other regs could be considered after this. + + REG might actually be something other than a register; + if so, we do nothing. + + SETTER is 0 if this register was modified by an auto-increment (i.e., + a REG_INC note was found for it). + + CLOBBERs are processed here by calling mark_reg_clobber. */ + +static void +mark_reg_store (orig_reg, setter) + rtx orig_reg, setter; +{ + register int regno; + register rtx reg = orig_reg; + + /* WORD is which word of a multi-register group is being stored. + For the case where the store is actually into a SUBREG of REG. + Except we don't use it; I believe the entire REG needs to be + made live. */ + int word = 0; + + if (GET_CODE (reg) == SUBREG) + { + word = SUBREG_WORD (reg); + reg = SUBREG_REG (reg); + } + + if (GET_CODE (reg) != REG) + return; + + if (setter && GET_CODE (setter) == CLOBBER) + { + /* A clobber of a register should be processed here too. */ + mark_reg_clobber (orig_reg, setter); + return; + } + + regs_set[n_regs_set++] = reg; + + if (setter) + set_preference (reg, SET_SRC (setter)); + + regno = REGNO (reg); + + if (reg_renumber[regno] >= 0) + regno = reg_renumber[regno] /* + word */; + + /* Either this is one of the max_allocno pseudo regs not allocated, + or it is or has a hardware reg. First handle the pseudo-regs. */ + if (regno >= FIRST_PSEUDO_REGISTER) + { + if (reg_allocno[regno] >= 0) + { + SET_ALLOCNO_LIVE (reg_allocno[regno]); + record_one_conflict (regno); + } + } + /* Handle hardware regs (and pseudos allocated to hard regs). */ + else if (! fixed_regs[regno]) + { + register int last = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg)); + while (regno < last) + { + record_one_conflict (regno); + SET_HARD_REG_BIT (hard_regs_live, regno); + regno++; + } + } +} + +/* Like mark_reg_set except notice just CLOBBERs; ignore SETs. */ + +static void +mark_reg_clobber (reg, setter) + rtx reg, setter; +{ + register int regno; + + /* WORD is which word of a multi-register group is being stored. + For the case where the store is actually into a SUBREG of REG. + Except we don't use it; I believe the entire REG needs to be + made live. */ + int word = 0; + + if (GET_CODE (setter) != CLOBBER) + return; + + if (GET_CODE (reg) == SUBREG) + { + word = SUBREG_WORD (reg); + reg = SUBREG_REG (reg); + } + + if (GET_CODE (reg) != REG) + return; + + regs_set[n_regs_set++] = reg; + + regno = REGNO (reg); + + if (reg_renumber[regno] >= 0) + regno = reg_renumber[regno] /* + word */; + + /* Either this is one of the max_allocno pseudo regs not allocated, + or it is or has a hardware reg. First handle the pseudo-regs. */ + if (regno >= FIRST_PSEUDO_REGISTER) + { + if (reg_allocno[regno] >= 0) + { + SET_ALLOCNO_LIVE (reg_allocno[regno]); + record_one_conflict (regno); + } + } + /* Handle hardware regs (and pseudos allocated to hard regs). */ + else if (! fixed_regs[regno]) + { + register int last = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg)); + while (regno < last) + { + record_one_conflict (regno); + SET_HARD_REG_BIT (hard_regs_live, regno); + regno++; + } + } +} + +/* Record that REG has conflicts with all the regs currently live. + Do not mark REG itself as live. */ + +static void +mark_reg_conflicts (reg) + rtx reg; +{ + register int regno; + + if (GET_CODE (reg) == SUBREG) + reg = SUBREG_REG (reg); + + if (GET_CODE (reg) != REG) + return; + + regno = REGNO (reg); + + if (reg_renumber[regno] >= 0) + regno = reg_renumber[regno]; + + /* Either this is one of the max_allocno pseudo regs not allocated, + or it is or has a hardware reg. First handle the pseudo-regs. */ + if (regno >= FIRST_PSEUDO_REGISTER) + { + if (reg_allocno[regno] >= 0) + record_one_conflict (regno); + } + /* Handle hardware regs (and pseudos allocated to hard regs). */ + else if (! fixed_regs[regno]) + { + register int last = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg)); + while (regno < last) + { + record_one_conflict (regno); + regno++; + } + } +} + +/* Mark REG as being dead (following the insn being scanned now). + Store a 0 in regs_live or allocnos_live for this register. */ + +static void +mark_reg_death (reg) + rtx reg; +{ + register int regno = REGNO (reg); + + /* For pseudo reg, see if it has been assigned a hardware reg. */ + if (reg_renumber[regno] >= 0) + regno = reg_renumber[regno]; + + /* Either this is one of the max_allocno pseudo regs not allocated, + or it is a hardware reg. First handle the pseudo-regs. */ + if (regno >= FIRST_PSEUDO_REGISTER) + { + if (reg_allocno[regno] >= 0) + CLEAR_ALLOCNO_LIVE (reg_allocno[regno]); + } + /* Handle hardware regs (and pseudos allocated to hard regs). */ + else if (! fixed_regs[regno]) + { + /* Pseudo regs already assigned hardware regs are treated + almost the same as explicit hardware regs. */ + register int last = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg)); + while (regno < last) + { + CLEAR_HARD_REG_BIT (hard_regs_live, regno); + regno++; + } + } +} + +/* Mark hard reg REGNO as currently live, assuming machine mode MODE + for the value stored in it. MODE determines how many consecutive + registers are actually in use. Do not record conflicts; + it is assumed that the caller will do that. */ + +static void +mark_reg_live_nc (regno, mode) + register int regno; + enum machine_mode mode; +{ + register int last = regno + HARD_REGNO_NREGS (regno, mode); + while (regno < last) + { + SET_HARD_REG_BIT (hard_regs_live, regno); + regno++; + } +} + +/* Try to set a preference for an allocno to a hard register. + We are passed DEST and SRC which are the operands of a SET. It is known + that SRC is a register. If SRC or the first operand of SRC is a register, + try to set a preference. If one of the two is a hard register and the other + is a pseudo-register, mark the preference. + + Note that we are not as aggressive as local-alloc in trying to tie a + pseudo-register to a hard register. */ + +static void +set_preference (dest, src) + rtx dest, src; +{ + int src_regno, dest_regno; + /* Amount to add to the hard regno for SRC, or subtract from that for DEST, + to compensate for subregs in SRC or DEST. */ + int offset = 0; + int i; + int copy = 1; + + if (GET_RTX_FORMAT (GET_CODE (src))[0] == 'e') + src = XEXP (src, 0), copy = 0; + + /* Get the reg number for both SRC and DEST. + If neither is a reg, give up. */ + + if (GET_CODE (src) == REG) + src_regno = REGNO (src); + else if (GET_CODE (src) == SUBREG && GET_CODE (SUBREG_REG (src)) == REG) + { + src_regno = REGNO (SUBREG_REG (src)); + offset += SUBREG_WORD (src); + } + else + return; + + if (GET_CODE (dest) == REG) + dest_regno = REGNO (dest); + else if (GET_CODE (dest) == SUBREG && GET_CODE (SUBREG_REG (dest)) == REG) + { + dest_regno = REGNO (SUBREG_REG (dest)); + offset -= SUBREG_WORD (dest); + } + else + return; + + /* Convert either or both to hard reg numbers. */ + + if (reg_renumber[src_regno] >= 0) + src_regno = reg_renumber[src_regno]; + + if (reg_renumber[dest_regno] >= 0) + dest_regno = reg_renumber[dest_regno]; + + /* Now if one is a hard reg and the other is a global pseudo + then give the other a preference. */ + + if (dest_regno < FIRST_PSEUDO_REGISTER && src_regno >= FIRST_PSEUDO_REGISTER + && reg_allocno[src_regno] >= 0) + { + dest_regno -= offset; + if (dest_regno >= 0 && dest_regno < FIRST_PSEUDO_REGISTER) + { + if (copy) + SET_REGBIT (hard_reg_copy_preferences, + reg_allocno[src_regno], dest_regno); + + SET_REGBIT (hard_reg_preferences, + reg_allocno[src_regno], dest_regno); + for (i = dest_regno; + i < dest_regno + HARD_REGNO_NREGS (dest_regno, GET_MODE (dest)); + i++) + SET_REGBIT (hard_reg_full_preferences, reg_allocno[src_regno], i); + } + } + + if (src_regno < FIRST_PSEUDO_REGISTER && dest_regno >= FIRST_PSEUDO_REGISTER + && reg_allocno[dest_regno] >= 0) + { + src_regno += offset; + if (src_regno >= 0 && src_regno < FIRST_PSEUDO_REGISTER) + { + if (copy) + SET_REGBIT (hard_reg_copy_preferences, + reg_allocno[dest_regno], src_regno); + + SET_REGBIT (hard_reg_preferences, + reg_allocno[dest_regno], src_regno); + for (i = src_regno; + i < src_regno + HARD_REGNO_NREGS (src_regno, GET_MODE (src)); + i++) + SET_REGBIT (hard_reg_full_preferences, reg_allocno[dest_regno], i); + } + } +} + +/* Indicate that hard register number FROM was eliminated and replaced with + an offset from hard register number TO. The status of hard registers live + at the start of a basic block is updated by replacing a use of FROM with + a use of TO. */ + +void +mark_elimination (from, to) + int from, to; +{ + int i; + + for (i = 0; i < n_basic_blocks; i++) + if ((basic_block_live_at_start[i][from / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 << (from % REGSET_ELT_BITS))) != 0) + { + basic_block_live_at_start[i][from / REGSET_ELT_BITS] + &= ~ ((REGSET_ELT_TYPE) 1 << (from % REGSET_ELT_BITS)); + basic_block_live_at_start[i][to / REGSET_ELT_BITS] + |= ((REGSET_ELT_TYPE) 1 << (to % REGSET_ELT_BITS)); + } +} + +/* Print debugging trace information if -greg switch is given, + showing the information on which the allocation decisions are based. */ + +static void +dump_conflicts (file) + FILE *file; +{ + register int i; + register int has_preferences; + fprintf (file, ";; %d regs to allocate:", max_allocno); + for (i = 0; i < max_allocno; i++) + { + int j; + fprintf (file, " %d", allocno_reg[allocno_order[i]]); + for (j = 0; j < max_regno; j++) + if (reg_allocno[j] == allocno_order[i] + && j != allocno_reg[allocno_order[i]]) + fprintf (file, "+%d", j); + if (allocno_size[allocno_order[i]] != 1) + fprintf (file, " (%d)", allocno_size[allocno_order[i]]); + } + fprintf (file, "\n"); + + for (i = 0; i < max_allocno; i++) + { + register int j; + fprintf (file, ";; %d conflicts:", allocno_reg[i]); + for (j = 0; j < max_allocno; j++) + if (CONFLICTP (i, j) || CONFLICTP (j, i)) + fprintf (file, " %d", allocno_reg[j]); + for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) + if (TEST_HARD_REG_BIT (hard_reg_conflicts[i], j)) + fprintf (file, " %d", j); + fprintf (file, "\n"); + + has_preferences = 0; + for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) + if (TEST_HARD_REG_BIT (hard_reg_preferences[i], j)) + has_preferences = 1; + + if (! has_preferences) + continue; + fprintf (file, ";; %d preferences:", allocno_reg[i]); + for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) + if (TEST_HARD_REG_BIT (hard_reg_preferences[i], j)) + fprintf (file, " %d", j); + fprintf (file, "\n"); + } + fprintf (file, "\n"); +} + +void +dump_global_regs (file) + FILE *file; +{ + register int i, j; + + fprintf (file, ";; Register dispositions:\n"); + for (i = FIRST_PSEUDO_REGISTER, j = 0; i < max_regno; i++) + if (reg_renumber[i] >= 0) + { + fprintf (file, "%d in %d ", i, reg_renumber[i]); + if (++j % 6 == 0) + fprintf (file, "\n"); + } + + fprintf (file, "\n\n;; Hard regs used: "); + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (regs_ever_live[i]) + fprintf (file, " %d", i); + fprintf (file, "\n\n"); +} diff --git a/gnu/usr.bin/cc/lib/gstddef.h b/gnu/usr.bin/cc/lib/gstddef.h new file mode 100644 index 000000000000..f1939e33fff1 --- /dev/null +++ b/gnu/usr.bin/cc/lib/gstddef.h @@ -0,0 +1,217 @@ +#ifndef _STDDEF_H +#ifndef _STDDEF_H_ +#ifndef _ANSI_STDDEF_H + +/* Any one of these symbols __need_* means that GNU libc + wants us just to define one data type. So don't define + the symbols that indicate this file's entire job has been done. */ +#if (!defined(__need_wchar_t) && !defined(__need_size_t) \ + && !defined(__need_ptrdiff_t) && !defined(__need_NULL)) +#define _STDDEF_H +#define _STDDEF_H_ +/* snaroff@next.com says the NeXT needs this. */ +#define _ANSI_STDDEF_H +#endif + +#ifndef __sys_stdtypes_h +/* This avoids lossage on SunOS but only if stdtypes.h comes first. + There's no way to win with the other order! Sun lossage. */ + +/* On 4.3bsd-net2, make sure ansi.h is included, so we have + one less case to deal with in the following. */ +#if defined (__BSD_NET2__) || defined (____386BSD____) +#include +#endif + +/* In 4.3bsd-net2, machine/ansi.h defines these symbols, which are + defined if the corresponding type is *not* defined. */ +#ifdef _ANSI_H_ +#ifndef _SIZE_T_ +#define _SIZE_T +#endif +#ifndef _PTRDIFF_T_ +#define _PTRDIFF_T +#endif +#ifndef _WCHAR_T_ +#define _WCHAR_T +#endif +/* Undef _FOO_T_ if we are supposed to define foo_t. */ +#if defined (__need_ptrdiff_t) || defined (_STDDEF_H_) +#undef _PTRDIFF_T_ +#endif +#if defined (__need_size_t) || defined (_STDDEF_H_) +#undef _SIZE_T_ +#endif +#if defined (__need_wchar_t) || defined (_STDDEF_H_) +#undef _WCHAR_T_ +#endif +#endif /* _ANSI_H_ */ + +/* Sequent's header files use _PTRDIFF_T_ in some conflicting way. + Just ignore it. */ +#if defined (__sequent__) && defined (_PTRDIFF_T_) +#undef _PTRDIFF_T_ +#endif + +/* In case nobody has defined these types, but we aren't running under + GCC 2.00, make sure that __PTRDIFF_TYPE__, __SIZE__TYPE__, and + __WCHAR_TYPE__ have reasonable values. This can happen if the + parts of GCC is compiled by an older compiler, that actually + include gstddef.h, such as collect2. */ + +/* Signed type of difference of two pointers. */ + +/* Define this type if we are doing the whole job, + or if we want this type in particular. */ +#if defined (_STDDEF_H) || defined (__need_ptrdiff_t) +#ifndef _PTRDIFF_T /* in case has defined it. */ +#ifndef _T_PTRDIFF_ +#ifndef _T_PTRDIFF +#ifndef __PTRDIFF_T +#ifndef _PTRDIFF_T_ +#ifndef ___int_ptrdiff_t_h +#ifndef _GCC_PTRDIFF_T +#define _PTRDIFF_T +#define _T_PTRDIFF_ +#define _T_PTRDIFF +#define __PTRDIFF_T +#define _PTRDIFF_T_ +#define ___int_ptrdiff_t_h +#define _GCC_PTRDIFF_T +#ifndef __PTRDIFF_TYPE__ +#define __PTRDIFF_TYPE__ long int +#endif +typedef __PTRDIFF_TYPE__ ptrdiff_t; +#endif /* _GCC_PTRDIFF_T */ +#endif /* ___int_ptrdiff_t_h */ +#endif /* _PTRDIFF_T_ */ +#endif /* __PTRDIFF_T */ +#endif /* _T_PTRDIFF */ +#endif /* _T_PTRDIFF_ */ +#endif /* _PTRDIFF_T */ + +/* If this symbol has done its job, get rid of it. */ +#undef __need_ptrdiff_t + +#endif /* _STDDEF_H or __need_ptrdiff_t. */ + +/* Unsigned type of `sizeof' something. */ + +/* Define this type if we are doing the whole job, + or if we want this type in particular. */ +#if defined (_STDDEF_H) || defined (__need_size_t) +#ifndef _SIZE_T /* in case has defined it. */ +#ifndef _SYS_SIZE_T_H +#ifndef _T_SIZE_ +#ifndef _T_SIZE +#ifndef __SIZE_T +#ifndef _SIZE_T_ +#ifndef ___int_size_t_h +#ifndef _GCC_SIZE_T +#ifndef _SIZET_ +#define _SIZE_T +#define _SYS_SIZE_T_H +#define _T_SIZE_ +#define _T_SIZE +#define __SIZE_T +#define _SIZE_T_ +#define ___int_size_t_h +#define _GCC_SIZE_T +#define _SIZET_ +#ifndef __SIZE_TYPE__ +#define __SIZE_TYPE__ long unsigned int +#endif +#if !(defined (__GNUG__) && defined (size_t)) +typedef __SIZE_TYPE__ size_t; +#endif /* !(defined (__GNUG__) && defined (size_t)) */ +#endif /* _SIZET_ */ +#endif /* _GCC_SIZE_T */ +#endif /* ___int_size_t_h */ +#endif /* _SIZE_T_ */ +#endif /* __SIZE_T */ +#endif /* _T_SIZE */ +#endif /* _T_SIZE_ */ +#endif /* _SYS_SIZE_T_H */ +#endif /* _SIZE_T */ +#undef __need_size_t +#endif /* _STDDEF_H or __need_size_t. */ + + +/* Wide character type. + Locale-writers should change this as necessary to + be big enough to hold unique values not between 0 and 127, + and not (wchar_t) -1, for each defined multibyte character. */ + +/* Define this type if we are doing the whole job, + or if we want this type in particular. */ +#if defined (_STDDEF_H) || defined (__need_wchar_t) +#ifndef _WCHAR_T +#ifndef _T_WCHAR_ +#ifndef _T_WCHAR +#ifndef __WCHAR_T +#ifndef _WCHAR_T_ +#ifndef ___int_wchar_t_h +#ifndef _GCC_WCHAR_T +#define _WCHAR_T +#define _T_WCHAR_ +#define _T_WCHAR +#define __WCHAR_T +#define _WCHAR_T_ +#define ___int_wchar_t_h +#define _GCC_WCHAR_T +#ifndef __WCHAR_TYPE__ +#define __WCHAR_TYPE__ int +#endif +#ifdef __GNUG__ +/* In C++, wchar_t is a distinct basic type, + and we can expect __wchar_t to be defined by cc1plus. */ +typedef __wchar_t wchar_t; +#else +/* In C, cpp tells us which type to make an alias for. */ +typedef __WCHAR_TYPE__ wchar_t; +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#undef __need_wchar_t +#endif /* _STDDEF_H or __need_wchar_t. */ + +/* In 4.3bsd-net2, leave these undefined to indicate that size_t, etc. + are already defined. */ +#ifdef _ANSI_H_ +#ifdef _GCC_PTRDIFF_T +#undef _PTRDIFF_T_ +#endif +#ifdef _GCC_SIZE_T +#undef _SIZE_T_ +#endif +#ifdef _GCC_WCHAR_T +#undef _WCHAR_T_ +#endif +#endif /* _ANSI_H_ */ + +#endif /* __sys_stdtypes_h */ + +/* A null pointer constant. */ + +#if defined (_STDDEF_H) || defined (__need_NULL) +#undef NULL /* in case has defined it. */ +#define NULL ((void *)0) +#endif /* NULL not defined and or need NULL. */ +#undef __need_NULL + +#ifdef _STDDEF_H + +/* Offset of member MEMBER in a struct of type TYPE. */ + +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +#endif /* _STDDEF_H was defined this time */ + +#endif /* _ANSI_STDDEF_H was not defined before */ +#endif /* _STDDEF_H_ was not defined before */ +#endif /* _STDDEF_H was not defined before */ diff --git a/gnu/usr.bin/cc/lib/gvarargs.h b/gnu/usr.bin/cc/lib/gvarargs.h new file mode 100644 index 000000000000..d0ebba2bb445 --- /dev/null +++ b/gnu/usr.bin/cc/lib/gvarargs.h @@ -0,0 +1,169 @@ +#ifndef __GNUC__ +/* Use the system's macros with the system's compiler. */ +#include +#else +/* Record that this is varargs.h; this turns off stdarg.h. */ + +#ifndef _VARARGS_H +#define _VARARGS_H + +#ifdef __sparc__ +#include +#else +#ifdef __spur__ +#include +#else +#ifdef __mips__ +#include +#else +#ifdef __i860__ +#include +#else +#ifdef __pyr__ +#include +#else +#ifdef __clipper__ +#include +#else +#ifdef __m88k__ +#include +#else +#if defined(__hppa__) || defined(hp800) +#include +#else +#ifdef __i960__ +#include +#else +#ifdef __alpha__ +#include +#else + +#ifdef __NeXT__ + +/* On Next, erase any vestiges of stdarg.h. */ + +#ifdef _ANSI_STDARG_H_ +#define _VA_LIST_ +#endif +#define _ANSI_STDARG_H_ + +#undef va_alist +#undef va_dcl +#undef va_list +#undef va_start +#undef va_end +#undef __va_rounded_size +#undef va_arg +#endif /* __NeXT__ */ + +/* In GCC version 2, we want an ellipsis at the end of the declaration + of the argument list. GCC version 1 can't parse it. */ + +#if __GNUC__ > 1 +#define __va_ellipsis ... +#else +#define __va_ellipsis +#endif + +/* These macros implement traditional (non-ANSI) varargs + for GNU C. */ + +#define va_alist __builtin_va_alist +/* The ... causes current_function_varargs to be set in cc1. */ +#define va_dcl int __builtin_va_alist; __va_ellipsis + +/* Define __gnuc_va_list, just as in gstdarg.h. */ + +#ifndef __GNUC_VA_LIST +#define __GNUC_VA_LIST +#if defined(__svr4__) || defined(_AIX) || defined(_M_UNIX) +typedef char *__gnuc_va_list; +#else +typedef void *__gnuc_va_list; +#endif +#endif + +#define va_start(AP) AP=(char *) &__builtin_va_alist + +#define va_end(AP) + +#define __va_rounded_size(TYPE) \ + (((sizeof (TYPE) + sizeof (int) - 1) / sizeof (int)) * sizeof (int)) + +#if defined (__arm__) || defined (__i386__) || defined (__ns32000__) || defined (__vax__) +/* This is for little-endian machines; small args are padded upward. */ +#define va_arg(AP, TYPE) \ + (AP = (__gnuc_va_list) ((char *) (AP) + __va_rounded_size (TYPE)), \ + *((TYPE *) (void *) ((char *) (AP) - __va_rounded_size (TYPE)))) +#else /* big-endian */ +/* This is for big-endian machines; small args are padded downward. */ +#define va_arg(AP, TYPE) \ + (AP = (__gnuc_va_list) ((char *) (AP) + __va_rounded_size (TYPE)), \ + *((TYPE *) (void *) ((char *) (AP) - ((sizeof (TYPE) < 4 \ + ? sizeof (TYPE) \ + : __va_rounded_size (TYPE)))))) +#endif /* big-endian */ + +#endif /* not alpha */ +#endif /* not i960 */ +#endif /* not hppa */ +#endif /* not m88k */ +#endif /* not clipper */ +#endif /* not pyr */ +#endif /* not i860 */ +#endif /* not mips */ +#endif /* not spur */ +#endif /* not sparc */ +#endif /* not _VARARGS_H */ + +/* Define va_list from __gnuc_va_list. */ + +#ifdef _HIDDEN_VA_LIST /* On OSF1, this means varargs.h is "half-loaded". */ +#undef _VA_LIST +#endif + +#ifdef __svr4__ +/* SVR4.2 uses _VA_LIST for an internal alias for va_list, + so we must avoid testing it and setting it here. + SVR4 uses _VA_LIST as a flag in stdarg.h, but we should + have no conflict with that. */ +#ifndef _VA_LIST_ +#define _VA_LIST_ +#ifdef __i860__ +#ifndef _VA_LIST +#define _VA_LIST va_list +#endif +#endif /* __i860__ */ +typedef __gnuc_va_list va_list; +#endif /* _VA_LIST_ */ + +#else /* not __svr4__ */ + +/* The macro _VA_LIST_ is the same thing used by this file in Ultrix. + But on BSD NET2 we must not test or define or undef it. + (Note that the comments in NET 2's ansi.h + are incorrect for _VA_LIST_--see stdio.h!) */ +#if !defined (_VA_LIST_) || defined (__BSD_NET2__) || defined (____386BSD____) +/* The macro _VA_LIST is used in SCO Unix 3.2. */ +#ifndef _VA_LIST +/* The macro _VA_LIST_T_H is used in the Bull dpx2 */ +#ifndef _VA_LIST_T_H +#define _VA_LIST_T_H +#if !(defined (__BSD_NET2__) || defined (____386BSD____)) +#define _VA_LIST_ +#endif +#define _VA_LIST +typedef __gnuc_va_list va_list; +#endif /* not _VA_LIST_T_H */ +#endif /* not _VA_LIST */ +#endif /* not _VA_LIST_ */ + +#endif /* not __svr4__ */ + +/* The next BSD release (if there is one) wants this symbol to be + undefined instead of _VA_LIST_. */ +#ifdef _BSD_VA_LIST +#undef _BSD_VA_LIST +#endif + +#endif /* __GNUC__ */ diff --git a/gnu/usr.bin/cc/lib/hard-reg-set.h b/gnu/usr.bin/cc/lib/hard-reg-set.h new file mode 100644 index 000000000000..1c3342a1c115 --- /dev/null +++ b/gnu/usr.bin/cc/lib/hard-reg-set.h @@ -0,0 +1,267 @@ +/* Sets (bit vectors) of hard registers, and operations on them. + Copyright (C) 1987, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* Define the type of a set of hard registers. */ + +/* If HARD_REG_SET is a macro, its definition is a scalar type + that has enough bits for all the target machine's hard registers. + Otherwise, it is a typedef for a suitable array of HOST_WIDE_INTs, + and HARD_REG_SET_LONGS is how many. + + Note that lots of code assumes that the first part of a regset is + the same format as a HARD_REG_SET. To help make sure this is true, + we only try the widest integer mode (HOST_WIDE_INT) instead of all the + smaller types. This only loses if there are a very few registers and + then only in the few cases where we have an array of HARD_REG_SETs, + so it isn't worth making this as complex as it used to be. */ + +#if FIRST_PSEUDO_REGISTER <= HOST_BITS_PER_WIDE_INT +#define HARD_REG_SET HOST_WIDE_INT + +#else + +#define HARD_REG_SET_LONGS \ + ((FIRST_PSEUDO_REGISTER + HOST_BITS_PER_WIDE_INT - 1) \ + / HOST_BITS_PER_WIDE_INT) +typedef HOST_WIDE_INT HARD_REG_SET[HARD_REG_SET_LONGS]; + +#endif + +/* HARD_CONST is used to cast a constant to a HARD_REG_SET + if that is a scalar wider than an integer. */ + +#ifdef HARD_REG_SET +#define HARD_CONST(X) ((HARD_REG_SET) (X)) +#else +#define HARD_CONST(X) (X) +#endif + +/* Define macros SET_HARD_REG_BIT, CLEAR_HARD_REG_BIT and TEST_HARD_REG_BIT + to set, clear or test one bit in a hard reg set of type HARD_REG_SET. + All three take two arguments: the set and the register number. + + In the case where sets are arrays of longs, the first argument + is actually a pointer to a long. + + Define two macros for initializing a set: + CLEAR_HARD_REG_SET and SET_HARD_REG_SET. + These take just one argument. + + Also define macros for copying hard reg sets: + COPY_HARD_REG_SET and COMPL_HARD_REG_SET. + These take two arguments TO and FROM; they read from FROM + and store into TO. COMPL_HARD_REG_SET complements each bit. + + Also define macros for combining hard reg sets: + IOR_HARD_REG_SET and AND_HARD_REG_SET. + These take two arguments TO and FROM; they read from FROM + and combine bitwise into TO. Define also two variants + IOR_COMPL_HARD_REG_SET and AND_COMPL_HARD_REG_SET + which use the complement of the set FROM. + + Also define GO_IF_HARD_REG_SUBSET (X, Y, TO): + if X is a subset of Y, go to TO. +*/ + +#ifdef HARD_REG_SET + +#define SET_HARD_REG_BIT(SET, BIT) \ + ((SET) |= HARD_CONST (1) << (BIT)) +#define CLEAR_HARD_REG_BIT(SET, BIT) \ + ((SET) &= ~(HARD_CONST (1) << (BIT))) +#define TEST_HARD_REG_BIT(SET, BIT) \ + ((SET) & (HARD_CONST (1) << (BIT))) + +#define CLEAR_HARD_REG_SET(TO) ((TO) = HARD_CONST (0)) +#define SET_HARD_REG_SET(TO) ((TO) = HARD_CONST (-1)) + +#define COPY_HARD_REG_SET(TO, FROM) ((TO) = (FROM)) +#define COMPL_HARD_REG_SET(TO, FROM) ((TO) = ~(FROM)) + +#define IOR_HARD_REG_SET(TO, FROM) ((TO) |= (FROM)) +#define IOR_COMPL_HARD_REG_SET(TO, FROM) ((TO) |= ~ (FROM)) +#define AND_HARD_REG_SET(TO, FROM) ((TO) &= (FROM)) +#define AND_COMPL_HARD_REG_SET(TO, FROM) ((TO) &= ~ (FROM)) + +#define GO_IF_HARD_REG_SUBSET(X,Y,TO) if (HARD_CONST (0) == ((X) & ~(Y))) goto TO + +#define GO_IF_HARD_REG_EQUAL(X,Y,TO) if ((X) == (Y)) goto TO +#else + +#define UHOST_BITS_PER_WIDE_INT ((unsigned) HOST_BITS_PER_WIDE_INT) + +#define SET_HARD_REG_BIT(SET, BIT) \ + ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \ + |= (HOST_WIDE_INT) 1 << ((BIT) % UHOST_BITS_PER_WIDE_INT)) + +#define CLEAR_HARD_REG_BIT(SET, BIT) \ + ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \ + &= ~((HOST_WIDE_INT) 1 << ((BIT) % UHOST_BITS_PER_WIDE_INT))) + +#define TEST_HARD_REG_BIT(SET, BIT) \ + ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \ + & ((HOST_WIDE_INT) 1 << ((BIT) % UHOST_BITS_PER_WIDE_INT))) + +#define CLEAR_HARD_REG_SET(TO) \ +do { register HOST_WIDE_INT *scan_tp_ = (TO); \ + register int i; \ + for (i = 0; i < HARD_REG_SET_LONGS; i++) \ + *scan_tp_++ = 0; } while (0) + +#define SET_HARD_REG_SET(TO) \ +do { register HOST_WIDE_INT *scan_tp_ = (TO); \ + register int i; \ + for (i = 0; i < HARD_REG_SET_LONGS; i++) \ + *scan_tp_++ = -1; } while (0) + +#define COPY_HARD_REG_SET(TO, FROM) \ +do { register HOST_WIDE_INT *scan_tp_ = (TO), *scan_fp_ = (FROM); \ + register int i; \ + for (i = 0; i < HARD_REG_SET_LONGS; i++) \ + *scan_tp_++ = *scan_fp_++; } while (0) + +#define COMPL_HARD_REG_SET(TO, FROM) \ +do { register HOST_WIDE_INT *scan_tp_ = (TO), *scan_fp_ = (FROM); \ + register int i; \ + for (i = 0; i < HARD_REG_SET_LONGS; i++) \ + *scan_tp_++ = ~ *scan_fp_++; } while (0) + +#define AND_HARD_REG_SET(TO, FROM) \ +do { register HOST_WIDE_INT *scan_tp_ = (TO), *scan_fp_ = (FROM); \ + register int i; \ + for (i = 0; i < HARD_REG_SET_LONGS; i++) \ + *scan_tp_++ &= *scan_fp_++; } while (0) + +#define AND_COMPL_HARD_REG_SET(TO, FROM) \ +do { register HOST_WIDE_INT *scan_tp_ = (TO), *scan_fp_ = (FROM); \ + register int i; \ + for (i = 0; i < HARD_REG_SET_LONGS; i++) \ + *scan_tp_++ &= ~ *scan_fp_++; } while (0) + +#define IOR_HARD_REG_SET(TO, FROM) \ +do { register HOST_WIDE_INT *scan_tp_ = (TO), *scan_fp_ = (FROM); \ + register int i; \ + for (i = 0; i < HARD_REG_SET_LONGS; i++) \ + *scan_tp_++ |= *scan_fp_++; } while (0) + +#define IOR_COMPL_HARD_REG_SET(TO, FROM) \ +do { register HOST_WIDE_INT *scan_tp_ = (TO), *scan_fp_ = (FROM); \ + register int i; \ + for (i = 0; i < HARD_REG_SET_LONGS; i++) \ + *scan_tp_++ |= ~ *scan_fp_++; } while (0) + +#define GO_IF_HARD_REG_SUBSET(X,Y,TO) \ +do { register HOST_WIDE_INT *scan_xp_ = (X), *scan_yp_ = (Y); \ + register int i; \ + for (i = 0; i < HARD_REG_SET_LONGS; i++) \ + if (0 != (*scan_xp_++ & ~*scan_yp_++)) break; \ + if (i == HARD_REG_SET_LONGS) goto TO; } while (0) + +#define GO_IF_HARD_REG_EQUAL(X,Y,TO) \ +do { register HOST_WIDE_INT *scan_xp_ = (X), *scan_yp_ = (Y); \ + register int i; \ + for (i = 0; i < HARD_REG_SET_LONGS; i++) \ + if (*scan_xp_++ != ~*scan_yp_++)) break; \ + if (i == HARD_REG_SET_LONGS) goto TO; } while (0) + +#endif + +/* Define some standard sets of registers. */ + +/* Indexed by hard register number, contains 1 for registers + that are fixed use (stack pointer, pc, frame pointer, etc.). + These are the registers that cannot be used to allocate + a pseudo reg whose life does not cross calls. */ + +extern char fixed_regs[FIRST_PSEUDO_REGISTER]; + +/* The same info as a HARD_REG_SET. */ + +extern HARD_REG_SET fixed_reg_set; + +/* Indexed by hard register number, contains 1 for registers + that are fixed use or are clobbered by function calls. + These are the registers that cannot be used to allocate + a pseudo reg whose life crosses calls. */ + +extern char call_used_regs[FIRST_PSEUDO_REGISTER]; + +/* The same info as a HARD_REG_SET. */ + +extern HARD_REG_SET call_used_reg_set; + +/* Indexed by hard register number, contains 1 for registers that are + fixed use -- i.e. in fixed_regs -- or a function value return register + or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the + registers that cannot hold quantities across calls even if we are + willing to save and restore them. */ + +extern char call_fixed_regs[FIRST_PSEUDO_REGISTER]; + +/* The same info as a HARD_REG_SET. */ + +extern HARD_REG_SET call_fixed_reg_set; + +/* Indexed by hard register number, contains 1 for registers + that are being used for global register decls. + These must be exempt from ordinary flow analysis + and are also considered fixed. */ + +extern char global_regs[FIRST_PSEUDO_REGISTER]; + +/* Table of register numbers in the order in which to try to use them. */ + +#ifdef REG_ALLOC_ORDER /* Avoid undef symbol in certain broken linkers. */ +extern int reg_alloc_order[FIRST_PSEUDO_REGISTER]; +#endif + +/* For each reg class, a HARD_REG_SET saying which registers are in it. */ + +extern HARD_REG_SET reg_class_contents[]; + +/* For each reg class, number of regs it contains. */ + +extern int reg_class_size[N_REG_CLASSES]; + +/* For each reg class, table listing all the containing classes. */ + +extern enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; + +/* For each reg class, table listing all the classes contained in it. */ + +extern enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; + +/* For each pair of reg classes, + a largest reg class contained in their union. */ + +extern enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; + +/* For each pair of reg classes, + the smallest reg class that contains their union. */ + +extern enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; + +/* Number of non-fixed registers. */ + +extern int n_non_fixed_regs; + +/* Vector indexed by hardware reg giving its name. */ + +extern char *reg_names[FIRST_PSEUDO_REGISTER]; diff --git a/gnu/usr.bin/cc/lib/i386/bsd.h b/gnu/usr.bin/cc/lib/i386/bsd.h new file mode 100644 index 000000000000..164290c5a5bb --- /dev/null +++ b/gnu/usr.bin/cc/lib/i386/bsd.h @@ -0,0 +1,132 @@ +/* Definitions for BSD assembler syntax for Intel 386 + (actually AT&T syntax for insns and operands, + adapted to BSD conventions for symbol names and debugging.) + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Include common aspects of all 386 Unix assemblers. */ +#include "i386/unix.h" + +/* Use the Sequent Symmetry assembler syntax. */ + +#define TARGET_VERSION fprintf (stderr, " (80386, BSD syntax)"); + +/* Define the syntax of pseudo-ops, labels and comments. */ + +/* Prefix for internally generated assembler labels. If we aren't using + underscores, we are using prefix `.'s to identify labels that should + be ignored, as in `i386/gas.h' --karl@cs.umb.edu */ +#ifdef NO_UNDERSCORES +#define LPREFIX ".L" +#else +#define LPREFIX "L" +#endif /* not NO_UNDERSCORES */ + +/* Assembler pseudos to introduce constants of various size. */ + +#define ASM_BYTE_OP "\t.byte" +#define ASM_SHORT "\t.word" +#define ASM_LONG "\t.long" +#define ASM_DOUBLE "\t.double" + +/* Output at beginning of assembler file. + ??? I am skeptical of this -- RMS. */ + +#define ASM_FILE_START(FILE) \ + fprintf (FILE, "\t.file\t\"%s\"\n", dump_base_name); + +/* This was suggested, but it shouldn't be right for DBX output. -- RMS + #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) */ + + +/* Define the syntax of labels and symbol definitions/declarations. */ + +/* This is how to output an assembler line + that says to advance the location counter by SIZE bytes. */ + +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.space %u\n", (SIZE)) + +/* Define the syntax of labels and symbol definitions/declarations. */ + +/* This says how to output an assembler line + to define a global common symbol. */ + +#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".comm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* This says how to output an assembler line + to define a local common symbol. */ + +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".lcomm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", (LOG)) + +/* This is how to store into the string BUF + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#ifdef NO_UNDERSCORES +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER)) +#else +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), "*%s%d", (PREFIX), (NUMBER)) +#endif + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#ifdef NO_UNDERSCORES +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".%s%d:\n", PREFIX, NUM) +#else +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, "%s%d:\n", PREFIX, NUM) +#endif + +/* This is how to output a reference to a user-level label named NAME. */ + +#ifdef NO_UNDERSCORES +#define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "%s", NAME) +#else +#define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME) +#endif /* not NO_UNDERSCORES */ + +/* Sequent has some changes in the format of DBX symbols. */ +#define DBX_NO_XREFS 1 + +/* Don't split DBX symbols into continuations. */ +#define DBX_CONTIN_LENGTH 0 + +/* This is how to output an assembler line defining a `double' constant. */ + +#undef ASM_OUTPUT_DOUBLE +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + fprintf (FILE, "\t.double 0d%.20e\n", (VALUE)) diff --git a/gnu/usr.bin/cc/lib/i386/gas.h b/gnu/usr.bin/cc/lib/i386/gas.h new file mode 100644 index 000000000000..4821a895c5d5 --- /dev/null +++ b/gnu/usr.bin/cc/lib/i386/gas.h @@ -0,0 +1,158 @@ +/* Definitions for Intel 386 running system V with gnu tools + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Note that i386/seq-gas.h is a GAS configuration that does not use this + file. */ + +#include "i386/i386.h" + +#ifndef YES_UNDERSCORES +/* Define this now, because i386/bsd.h tests it. */ +#define NO_UNDERSCORES +#endif + +/* Use the bsd assembler syntax. */ +/* we need to do this because gas is really a bsd style assembler, + * and so doesn't work well this these att-isms: + * + * ASM_OUTPUT_SKIP is .set .,.+N, which isn't implemented in gas + * ASM_OUTPUT_LOCAL is done with .set .,.+N, but that can't be + * used to define bss static space + * + * Next is the question of whether to uses underscores. RMS didn't + * like this idea at first, but since it is now obvious that we + * need this separate tm file for use with gas, at least to get + * dbx debugging info, I think we should also switch to underscores. + * We can keep i386v for real att style output, and the few + * people who want both form will have to compile twice. + */ + +#include "i386/bsd.h" + +/* these come from i386/bsd.h, but are specific to sequent */ +#undef DBX_NO_XREFS +#undef DBX_CONTIN_LENGTH + +/* Ask for COFF symbols. */ + +#define SDB_DEBUGGING_INFO + +/* Specify predefined symbols in preprocessor. */ + +#define CPP_PREDEFINES "-Dunix -Di386" +#define CPP_SPEC "%{posix:-D_POSIX_SOURCE}" + +/* Allow #sccs in preprocessor. */ + +#define SCCS_DIRECTIVE + +/* Output #ident as a .ident. */ + +#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME); + +/* Implicit library calls should use memcpy, not bcopy, etc. */ + +#define TARGET_MEM_FUNCTIONS + +#if 0 /* People say gas uses the log as the arg to .align. */ +/* When using gas, .align N aligns to an N-byte boundary. */ + +#undef ASM_OUTPUT_ALIGN +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) +#endif + +/* Align labels, etc. at 4-byte boundaries. + For the 486, align to 16-byte boundary for sake of cache. */ + +#undef ASM_OUTPUT_ALIGN_CODE +#define ASM_OUTPUT_ALIGN_CODE(FILE) \ + fprintf ((FILE), "\t.align %d,0x90\n", \ + TARGET_486 ? 4 : 2); /* Use log of 16 or log of 4 as arg. */ + +/* Align start of loop at 4-byte boundary. */ + +#undef ASM_OUTPUT_LOOP_ALIGN +#define ASM_OUTPUT_LOOP_ALIGN(FILE) \ + fprintf ((FILE), "\t.align 2,0x90\n"); /* Use log of 4 as arg. */ + +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + fprintf (FILE, "\t.file\t\"%s\"\n", dump_base_name); + +/* A C statement or statements which output an assembler instruction + opcode to the stdio stream STREAM. The macro-operand PTR is a + variable of type `char *' which points to the opcode name in its + "internal" form--the form that is written in the machine description. + + GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic. + So use `repe' instead. */ + +#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ +{ \ + if ((PTR)[0] == 'r' \ + && (PTR)[1] == 'e' \ + && (PTR)[2] == 'p') \ + { \ + if ((PTR)[3] == 'z') \ + { \ + fprintf (STREAM, "repe"); \ + (PTR) += 4; \ + } \ + else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \ + { \ + fprintf (STREAM, "repne"); \ + (PTR) += 5; \ + } \ + } \ +} + +/* Define macro used to output shift-double opcodes when the shift + count is in %cl. Some assemblers require %cl as an argument; + some don't. + + GAS requires the %cl argument, so override i386/unix.h. */ + +#undef AS3_SHIFT_DOUBLE +#define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) + +/* Print opcodes the way that GAS expects them. */ +#define GAS_MNEMONICS 1 + +#ifdef NO_UNDERSCORES /* If user-symbols don't have underscores, + then it must take more than `L' to identify + a label that should be ignored. */ + +/* This is how to store into the string BUF + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), ".%s%d", (PREFIX), (NUMBER)) + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".%s%d:\n", PREFIX, NUM) + +#endif /* NO_UNDERSCORES */ diff --git a/gnu/usr.bin/cc/lib/i386/gstabs.h b/gnu/usr.bin/cc/lib/i386/gstabs.h new file mode 100644 index 000000000000..5f0ae348f158 --- /dev/null +++ b/gnu/usr.bin/cc/lib/i386/gstabs.h @@ -0,0 +1,9 @@ +#include "i386/gas.h" + +/* We do not want to output SDB debugging information. */ + +#undef SDB_DEBUGGING_INFO + +/* We want to output DBX debugging information. */ + +#define DBX_DEBUGGING_INFO diff --git a/gnu/usr.bin/cc/lib/i386/i386.h b/gnu/usr.bin/cc/lib/i386/i386.h new file mode 100644 index 000000000000..fa8f0b5b26b4 --- /dev/null +++ b/gnu/usr.bin/cc/lib/i386/i386.h @@ -0,0 +1,1591 @@ +/* Definitions of target machine for GNU compiler for Intel 80386. + Copyright (C) 1988, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* The purpose of this file is to define the characteristics of the i386, + independent of assembler syntax or operating system. + + Three other files build on this one to describe a specific assembler syntax: + bsd386.h, att386.h, and sun386.h. + + The actual tm.h file for a particular system should include + this file, and then the file for the appropriate assembler syntax. + + Many macros that specify assembler syntax are omitted entirely from + this file because they really belong in the files for particular + assemblers. These include AS1, AS2, AS3, RP, IP, LPREFIX, L_SIZE, + PUT_OP_SIZE, USE_STAR, ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, + PRINT_B_I_S, and many that start with ASM_ or end in ASM_OP. */ + +/* Names to predefine in the preprocessor for this target machine. */ + +#define I386 1 + +/* Stubs for half-pic support if not OSF/1 reference platform. */ + +#ifndef HALF_PIC_P +#define HALF_PIC_P() 0 +#define HALF_PIC_NUMBER_PTRS 0 +#define HALF_PIC_NUMBER_REFS 0 +#define HALF_PIC_ENCODE(DECL) +#define HALF_PIC_DECLARE(NAME) +#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.") +#define HALF_PIC_ADDRESS_P(X) 0 +#define HALF_PIC_PTR(X) X +#define HALF_PIC_FINISH(STREAM) +#endif + +/* Run-time compilation parameters selecting different hardware subsets. */ + +extern int target_flags; + +/* Macros used in the machine description to test the flags. */ + +/* configure can arrage to make this 2, to force a 486. */ +#ifndef TARGET_CPU_DEFAULT +#define TARGET_CPU_DEFAULT 0 +#endif + +/* Compile 80387 insns for floating point (not library calls). */ +#define TARGET_80387 (target_flags & 1) +/* Compile code for an i486. */ +#define TARGET_486 (target_flags & 2) +/* Compile using ret insn that pops args. + This will not work unless you use prototypes at least + for all functions that can take varying numbers of args. */ +#define TARGET_RTD (target_flags & 8) +/* Compile passing first two args in regs 0 and 1. + This exists only to test compiler features that will + be needed for RISC chips. It is not usable + and is not intended to be usable on this cpu. */ +#define TARGET_REGPARM (target_flags & 020) + +/* Put uninitialized locals into bss, not data. + Meaningful only on svr3. */ +#define TARGET_SVR3_SHLIB (target_flags & 040) + +/* Use IEEE floating point comparisons. These handle correctly the cases + where the result of a comparison is unordered. Normally SIGFPE is + generated in such cases, in which case this isn't needed. */ +#define TARGET_IEEE_FP (target_flags & 0100) + +/* Functions that return a floating point value may return that value + in the 387 FPU or in 386 integer registers. If set, this flag causes + the 387 to be used, which is compatible with most calling conventions. */ +#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & 0200) + +/* Macro to define tables used to set the flags. + This is a list in braces of pairs in braces, + each pair being { "NAME", VALUE } + where VALUE is the bits to set or minus the bits to clear. + An empty string NAME is used to identify the default VALUE. */ + +#define TARGET_SWITCHES \ + { { "80387", 1}, \ + { "no-80387", -1}, \ + { "soft-float", -1}, \ + { "no-soft-float", 1}, \ + { "486", 2}, \ + { "no-486", -2}, \ + { "386", -2}, \ + { "rtd", 8}, \ + { "no-rtd", -8}, \ + { "regparm", 020}, \ + { "no-regparm", -020}, \ + { "svr3-shlib", 040}, \ + { "no-svr3-shlib", -040}, \ + { "ieee-fp", 0100}, \ + { "no-ieee-fp", -0100}, \ + { "fp-ret-in-387", 0200}, \ + { "no-fp-ret-in-387", -0200}, \ + SUBTARGET_SWITCHES \ + { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}} + +/* This is meant to be redefined in the host dependent files */ +#define SUBTARGET_SWITCHES + + +/* target machine storage layout */ + +/* Define this if most significant byte of a word is the lowest numbered. */ +/* That is true on the 80386. */ + +#define BITS_BIG_ENDIAN 0 + +/* Define this if most significant byte of a word is the lowest numbered. */ +/* That is not true on the 80386. */ +#define BYTES_BIG_ENDIAN 0 + +/* Define this if most significant word of a multiword number is the lowest + numbered. */ +/* Not true for 80386 */ +#define WORDS_BIG_ENDIAN 0 + +/* number of bits in an addressable storage unit */ +#define BITS_PER_UNIT 8 + +/* Width in bits of a "word", which is the contents of a machine register. + Note that this is not necessarily the width of data type `int'; + if using 16-bit ints on a 80386, this would still be 32. + But on a machine with 16-bit registers, this would be 16. */ +#define BITS_PER_WORD 32 + +/* Width of a word, in units (bytes). */ +#define UNITS_PER_WORD 4 + +/* Width in bits of a pointer. + See also the macro `Pmode' defined below. */ +#define POINTER_SIZE 32 + +/* Allocation boundary (in *bits*) for storing arguments in argument list. */ +#define PARM_BOUNDARY 32 + +/* Boundary (in *bits*) on which stack pointer should be aligned. */ +#define STACK_BOUNDARY 32 + +/* Allocation boundary (in *bits*) for the code of a function. + For i486, we get better performance by aligning to a cache + line (i.e. 16 byte) boundary. */ +#define FUNCTION_BOUNDARY (TARGET_486 ? 128 : 32) + +/* Alignment of field after `int : 0' in a structure. */ + +#define EMPTY_FIELD_BOUNDARY 32 + +/* Minimum size in bits of the largest boundary to which any + and all fundamental data types supported by the hardware + might need to be aligned. No data type wants to be aligned + rounder than this. The i386 supports 64-bit floating point + quantities, but these can be aligned on any 32-bit boundary. */ +#define BIGGEST_ALIGNMENT 32 + +/* Set this non-zero if move instructions will actually fail to work + when given unaligned data. */ +#define STRICT_ALIGNMENT 0 + +/* If bit field type is int, don't let it cross an int, + and give entire struct the alignment of an int. */ +/* Required on the 386 since it doesn't have bitfield insns. */ +#define PCC_BITFIELD_TYPE_MATTERS 1 + +/* Align loop starts for optimal branching. */ +#define ASM_OUTPUT_LOOP_ALIGN(FILE) \ + ASM_OUTPUT_ALIGN (FILE, 2) + +/* This is how to align an instruction for optimal branching. + On i486 we'll get better performance by aligning on a + cache line (i.e. 16 byte) boundary. */ +#define ASM_OUTPUT_ALIGN_CODE(FILE) \ + ASM_OUTPUT_ALIGN ((FILE), (TARGET_486 ? 4 : 2)) + +/* Standard register usage. */ + +/* This processor has special stack-like registers. See reg-stack.c + for details. */ + +#define STACK_REGS + +/* Number of actual hardware registers. + The hardware registers are assigned numbers for the compiler + from 0 to just below FIRST_PSEUDO_REGISTER. + All registers that the compiler knows about must be given numbers, + even those that are not normally considered general registers. + + In the 80386 we give the 8 general purpose registers the numbers 0-7. + We number the floating point registers 8-15. + Note that registers 0-7 can be accessed as a short or int, + while only 0-3 may be used with byte `mov' instructions. + + Reg 16 does not correspond to any hardware register, but instead + appears in the RTL as an argument pointer prior to reload, and is + eliminated during reloading in favor of either the stack or frame + pointer. */ + +#define FIRST_PSEUDO_REGISTER 17 + +/* 1 for registers that have pervasive standard uses + and are not available for the register allocator. + On the 80386, the stack pointer is such, as is the arg pointer. */ +#define FIXED_REGISTERS \ +/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ +{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 } + +/* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ + +#define CALL_USED_REGISTERS \ +/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ +{ 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } + +/* Macro to conditionally modify fixed_regs/call_used_regs. */ +#define CONDITIONAL_REGISTER_USAGE \ + { \ + if (flag_pic) \ + { \ + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + } \ + if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ + { \ + int i; \ + HARD_REG_SET x; \ + COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ + if (TEST_HARD_REG_BIT (x, i)) \ + fixed_regs[i] = call_used_regs[i] = 1; \ + } \ + } + +/* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. + + Actually there are no two word move instructions for consecutive + registers. And only registers 0-3 may have mov byte instructions + applied to them. + */ + +#define HARD_REGNO_NREGS(REGNO, MODE) \ + (FP_REGNO_P (REGNO) ? 1 \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. + On the 80386, the first 4 cpu registers can hold any mode + while the floating point registers may hold only floating point. + Make it clear that the fp regs could not hold a 16-byte float. */ + +/* The casts to int placate a compiler on a microvax, + for cross-compiler testing. */ + +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ + ((REGNO) < 2 ? 1 \ + : (REGNO) < 4 ? 1 \ + : FP_REGNO_P ((REGNO)) \ + ? (((int) GET_MODE_CLASS (MODE) == (int) MODE_FLOAT \ + || (int) GET_MODE_CLASS (MODE) == (int) MODE_COMPLEX_FLOAT) \ + && GET_MODE_UNIT_SIZE (MODE) <= 12) \ + : (int) (MODE) != (int) QImode) + +/* Value is 1 if it is a good idea to tie two pseudo registers + when one has mode MODE1 and one has mode MODE2. + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, + for any hard reg, then this must be 0 for correct output. */ + +#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) + +/* A C expression returning the cost of moving data from a register of class + CLASS1 to one of CLASS2. + + On the i386, copying between floating-point and fixed-point + registers is expensive. */ + +#define REGISTER_MOVE_COST(CLASS1, CLASS2) \ + (((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ + || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) ? 10 \ + : 2) + +/* Specify the registers used for certain standard purposes. + The values of these macros are register numbers. */ + +/* on the 386 the pc register is %eip, and is not usable as a general + register. The ordinary mov instructions won't work */ +/* #define PC_REGNUM */ + +/* Register to use for pushing function arguments. */ +#define STACK_POINTER_REGNUM 7 + +/* Base register for access to local variables of the function. */ +#define FRAME_POINTER_REGNUM 6 + +/* First floating point reg */ +#define FIRST_FLOAT_REG 8 + +/* First & last stack-like regs */ +#define FIRST_STACK_REG FIRST_FLOAT_REG +#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) + +/* Value should be nonzero if functions must have frame pointers. + Zero means the frame pointer need not be set up (and parms + may be accessed via the stack pointer) in functions that seem suitable. + This is computed in `reload', in reload1.c. */ +#define FRAME_POINTER_REQUIRED 0 + +/* Base register for access to arguments of the function. */ +#define ARG_POINTER_REGNUM 16 + +/* Register in which static-chain is passed to a function. */ +#define STATIC_CHAIN_REGNUM 2 + +/* Register to hold the addressing base for position independent + code access to data items. */ +#define PIC_OFFSET_TABLE_REGNUM 3 + +/* Register in which address to store a structure value + arrives in the function. On the 386, the prologue + copies this from the stack to register %eax. */ +#define STRUCT_VALUE_INCOMING 0 + +/* Place in which caller passes the structure value address. + 0 means push the value on the stack like an argument. */ +#define STRUCT_VALUE 0 + +/* Define the classes of registers for register constraints in the + machine description. Also define ranges of constants. + + One of the classes must always be named ALL_REGS and include all hard regs. + If there is more than one class, another class must be named NO_REGS + and contain no registers. + + The name GENERAL_REGS must be the name of a class (or an alias for + another name such as ALL_REGS). This is the class of registers + that is allowed by "g" or "r" in a register constraint. + Also, registers outside this class are allocated only when + instructions express preferences for them. + + The classes must be numbered in nondecreasing order; that is, + a larger-numbered class must never be contained completely + in a smaller-numbered class. + + For any two classes, it is very desirable that there be another + class that represents their union. + + It might seem that class BREG is unnecessary, since no useful 386 + opcode needs reg %ebx. But some systems pass args to the OS in ebx, + and the "b" register constraint is useful in asms for syscalls. */ + +enum reg_class +{ + NO_REGS, + AREG, DREG, CREG, BREG, + Q_REGS, /* %eax %ebx %ecx %edx */ + SIREG, DIREG, + INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ + GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ + FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ + FLOAT_REGS, + ALL_REGS, LIM_REG_CLASSES +}; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +#define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS)) + +/* Give names of register classes as strings for dump file. */ + +#define REG_CLASS_NAMES \ +{ "NO_REGS", \ + "AREG", "DREG", "CREG", "BREG", \ + "Q_REGS", \ + "SIREG", "DIREG", \ + "INDEX_REGS", \ + "GENERAL_REGS", \ + "FP_TOP_REG", "FP_SECOND_REG", \ + "FLOAT_REGS", \ + "ALL_REGS" } + +/* Define which registers fit in which classes. + This is an initializer for a vector of HARD_REG_SET + of length N_REG_CLASSES. */ + +#define REG_CLASS_CONTENTS \ +{ 0, \ + 0x1, 0x2, 0x4, 0x8, /* AREG, DREG, CREG, BREG */ \ + 0xf, /* Q_REGS */ \ + 0x10, 0x20, /* SIREG, DIREG */ \ + 0x1007f, /* INDEX_REGS */ \ + 0x100ff, /* GENERAL_REGS */ \ + 0x0100, 0x0200, /* FP_TOP_REG, FP_SECOND_REG */ \ + 0xff00, /* FLOAT_REGS */ \ + 0x1ffff } + +/* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + +extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; +#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) + +/* When defined, the compiler allows registers explicitly used in the + rtl to be used as spill registers but prevents the compiler from + extending the lifetime of these registers. */ + +#define SMALL_REGISTER_CLASSES + +#define QI_REG_P(X) \ + (REG_P (X) && REGNO (X) < 4) +#define NON_QI_REG_P(X) \ + (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) + +#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) +#define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) + +#define STACK_REG_P(xop) (REG_P (xop) && \ + REGNO (xop) >= FIRST_STACK_REG && \ + REGNO (xop) <= LAST_STACK_REG) + +#define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop)) + +#define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG) + +/* Try to maintain the accuracy of the death notes for regs satisfying the + following. Important for stack like regs, to know when to pop. */ + +/* #define PRESERVE_DEATH_INFO_REGNO_P(x) FP_REGNO_P(x) */ + +/* 1 if register REGNO can magically overlap other regs. + Note that nonzero values work only in very special circumstances. */ + +/* #define OVERLAPPING_REGNO_P(REGNO) FP_REGNO_P (REGNO) */ + +/* The class value for index registers, and the one for base regs. */ + +#define INDEX_REG_CLASS INDEX_REGS +#define BASE_REG_CLASS GENERAL_REGS + +/* Get reg_class from a letter such as appears in the machine description. */ + +#define REG_CLASS_FROM_LETTER(C) \ + ((C) == 'r' ? GENERAL_REGS : \ + (C) == 'q' ? Q_REGS : \ + (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ + ? FLOAT_REGS \ + : NO_REGS) : \ + (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ + ? FP_TOP_REG \ + : NO_REGS) : \ + (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ + ? FP_SECOND_REG \ + : NO_REGS) : \ + (C) == 'a' ? AREG : \ + (C) == 'b' ? BREG : \ + (C) == 'c' ? CREG : \ + (C) == 'd' ? DREG : \ + (C) == 'D' ? DIREG : \ + (C) == 'S' ? SIREG : NO_REGS) + +/* The letters I, J, K, L and M in a register constraint string + can be used to stand for particular ranges of immediate operands. + This macro defines what the ranges are. + C is the letter, and VALUE is a constant value. + Return 1 if VALUE is in the range specified by C. + + I is for non-DImode shifts. + J is for DImode shifts. + K and L are for an `andsi' optimization. + M is for shifts that can be executed by the "lea" opcode. + */ + +#define CONST_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 : \ + (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 : \ + (C) == 'K' ? (VALUE) == 0xff : \ + (C) == 'L' ? (VALUE) == 0xffff : \ + (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 : \ + 0) + +/* Similar, but for floating constants, and defining letters G and H. + Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if + TARGET_387 isn't set, because the stack register converter may need to + load 0.0 into the function value register. */ + +#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'G' ? standard_80387_constant_p (VALUE) : 0) + +/* Place additional restrictions on the register class to use when it + is necessary to be able to hold a value of mode MODE in a reload + register for which class CLASS would ordinarily be used. */ + +#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ + ((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \ + ? Q_REGS : (CLASS)) + +/* Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. + On the 80386 series, we prevent floating constants from being + reloaded into floating registers (since no move-insn can do that) + and we ensure that QImodes aren't reloaded into the esi or edi reg. */ + +/* Put float CONST_DOUBLE in the constant pool instead of fp regs. + QImode must go into class Q_REGS. + Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and + movdf to do mem-to-mem moves through integer regs. */ + +#define PREFERRED_RELOAD_CLASS(X,CLASS) \ + (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode ? NO_REGS \ + : GET_MODE (X) == QImode && ! reg_class_subset_p (CLASS, Q_REGS) ? Q_REGS \ + : ((CLASS) == ALL_REGS \ + && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) ? GENERAL_REGS \ + : (CLASS)) + +/* If we are copying between general and FP registers, we need a memory + location. */ + +#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ + ((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ + || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) + +/* Return the maximum number of consecutive registers + needed to represent mode MODE in a register of class CLASS. */ +/* On the 80386, this is the size of MODE in words, + except in the FP regs, where a single reg is always enough. */ +#define CLASS_MAX_NREGS(CLASS, MODE) \ + (FLOAT_CLASS_P (CLASS) ? 1 : \ + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +/* Stack layout; function entry, exit and calling. */ + +/* Define this if pushing a word on the stack + makes the stack pointer a smaller address. */ +#define STACK_GROWS_DOWNWARD + +/* Define this if the nominal address of the stack frame + is at the high-address end of the local variables; + that is, each additional local variable allocated + goes at a more negative offset in the frame. */ +#define FRAME_GROWS_DOWNWARD + +/* Offset within stack frame to start allocating local variables at. + If FRAME_GROWS_DOWNWARD, this is the offset to the END of the + first local allocated. Otherwise, it is the offset to the BEGINNING + of the first local allocated. */ +#define STARTING_FRAME_OFFSET 0 + +/* If we generate an insn to push BYTES bytes, + this says how many the stack pointer really advances by. + On 386 pushw decrements by exactly 2 no matter what the position was. + On the 386 there is no pushb; we use pushw instead, and this + has the effect of rounding up to 2. */ + +#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2)) + +/* Offset of first parameter from the argument pointer register value. */ +#define FIRST_PARM_OFFSET(FNDECL) 0 + +/* Value is the number of bytes of arguments automatically + popped when returning from a subroutine call. + FUNTYPE is the data type of the function (as a tree), + or for a library call it is an identifier node for the subroutine name. + SIZE is the number of bytes of arguments passed on the stack. + + On the 80386, the RTD insn may be used to pop them if the number + of args is fixed, but if the number is variable then the caller + must pop them all. RTD can't be used for library calls now + because the library is compiled with the Unix compiler. + Use of RTD is a selectable option, since it is incompatible with + standard Unix calling sequences. If the option is not selected, + the caller must always pop the args. */ + +#define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ + (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \ + : (TARGET_RTD \ + && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ + || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ + == void_type_node))) ? (SIZE) \ + : (aggregate_value_p (FUNTYPE)) ? GET_MODE_SIZE (Pmode) : 0) + +/* Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ +#define FUNCTION_VALUE(VALTYPE, FUNC) \ + gen_rtx (REG, TYPE_MODE (VALTYPE), \ + VALUE_REGNO (TYPE_MODE (VALTYPE))) + +/* Define how to find the value returned by a library function + assuming the value has mode MODE. */ + +#define LIBCALL_VALUE(MODE) \ + gen_rtx (REG, MODE, VALUE_REGNO (MODE)) + +/* Define the size of the result block used for communication between + untyped_call and untyped_return. The block contains a DImode value + followed by the block used by fnsave and frstor. */ + +#define APPLY_RESULT_SIZE (8+108) + +/* 1 if N is a possible register number for function argument passing. + On the 80386, no registers are used in this way. + *NOTE* -mregparm does not work. + It exists only to test register calling conventions. */ + +#define FUNCTION_ARG_REGNO_P(N) 0 + +/* Define a data type for recording info about an argument list + during the scan of that argument list. This data type should + hold all necessary information about the function itself + and about the args processed so far, enough to enable macros + such as FUNCTION_ARG to determine where the next arg should go. + + On the 80386, this is a single integer, which is a number of bytes + of arguments scanned so far. */ + +#define CUMULATIVE_ARGS int + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. + + On the 80386, the offset starts at 0. */ + +#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ + ((CUM) = 0) + +/* Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + (TYPE is null for libcalls where that information may not be available.) */ + +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ + ((CUM) += ((MODE) != BLKmode \ + ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ + : (int_size_in_bytes (TYPE) + 3) & ~3)) + +/* Define where to put the arguments to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). */ + + +/* On the 80386 all args are pushed, except if -mregparm is specified + then the first two words of arguments are passed in EAX, EDX. + *NOTE* -mregparm does not work. + It exists only to test register calling conventions. */ + +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ +((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0) + +/* For an arg passed partly in registers and partly in memory, + this is the number of registers used. + For args passed entirely in registers or entirely in memory, zero. */ + + +#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ +((TARGET_REGPARM && (CUM) < 8 \ + && 8 < ((CUM) + ((MODE) == BLKmode \ + ? int_size_in_bytes (TYPE) \ + : GET_MODE_SIZE (MODE)))) \ + ? 2 - (CUM) / 4 : 0) + +/* This macro generates the assembly code for function entry. + FILE is a stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. + Refer to the array `regs_ever_live' to determine which registers + to save; `regs_ever_live[I]' is nonzero if register number I + is ever used in the function. This macro is responsible for + knowing which registers should not be saved even if used. */ + +#define FUNCTION_PROLOGUE(FILE, SIZE) \ + function_prologue (FILE, SIZE) + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ + LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall *_mcount@GOT(%%ebx)\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall _mcount\n"); \ + } \ +} + +/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, + the stack pointer does not matter. The value is tested only in + functions that have frame pointers. + No definition is equivalent to always zero. */ +/* Note on the 386 it might be more efficient not to define this since + we have to restore it ourselves from the frame pointer, in order to + use pop */ + +#define EXIT_IGNORE_STACK 1 + +/* This macro generates the assembly code for function exit, + on machines that need it. If FUNCTION_EPILOGUE is not defined + then individual return instructions are generated for each + return statement. Args are same as for FUNCTION_PROLOGUE. + + The function epilogue should not depend on the current stack pointer! + It should use the frame pointer only. This is mandatory because + of alloca; we also take advantage of it to omit stack adjustments + before returning. + + If the last non-note insn in the function is a BARRIER, then there + is no need to emit a function prologue, because control does not fall + off the end. This happens if the function ends in an "exit" call, or + if a `return' insn is emitted directly into the function. */ + +#define FUNCTION_EPILOGUE(FILE, SIZE) \ +do { \ + rtx last = get_last_insn (); \ + if (last && GET_CODE (last) == NOTE) \ + last = prev_nonnote_insn (last); \ + if (! last || GET_CODE (last) != BARRIER) \ + function_epilogue (FILE, SIZE); \ +} while (0) + +/* Output assembler code for a block containing the constant parts + of a trampoline, leaving space for the variable parts. */ + +/* On the 386, the trampoline contains three instructions: + mov #STATIC,ecx + mov #FUNCTION,eax + jmp @eax */ +#define TRAMPOLINE_TEMPLATE(FILE) \ +{ \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb9)); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb8)); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xff)); \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xe0)); \ +} + +/* Length in units of the trampoline for entering a nested function. */ + +#define TRAMPOLINE_SIZE 12 + +/* Emit RTL insns to initialize the variable parts of a trampoline. + FNADDR is an RTX for the address of the function's pure code. + CXT is an RTX for the static chain value for the function. */ + +#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ +{ \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 1)), CXT); \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 6)), FNADDR); \ +} + +/* Definitions for register eliminations. + + This is an array of structures. Each structure initializes one pair + of eliminable registers. The "from" register number is given first, + followed by "to". Eliminations of the same "from" register are listed + in order of preference. + + We have two registers that can be eliminated on the i386. First, the + frame pointer register can often be eliminated in favor of the stack + pointer register. Secondly, the argument pointer register can always be + eliminated; it is replaced with either the stack or frame pointer. */ + +#define ELIMINABLE_REGS \ +{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ + { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} + +/* Given FROM and TO register numbers, say whether this elimination is allowed. + Frame pointer elimination is automatically handled. + + For the i386, if frame pointer elimination is being done, we would like to + convert ap into sp, not fp. + + All other eliminations are valid. */ + +#define CAN_ELIMINATE(FROM, TO) \ + ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ + ? ! frame_pointer_needed \ + : 1) + +/* Define the offset between two registers, one to be eliminated, and the other + its replacement, at the start of a routine. */ + +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ +{ \ + if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ + (OFFSET) = 8; /* Skip saved PC and previous frame pointer */ \ + else \ + { \ + int regno; \ + int offset = 0; \ + \ + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ + if ((regs_ever_live[regno] && ! call_used_regs[regno]) \ + || (current_function_uses_pic_offset_table \ + && regno == PIC_OFFSET_TABLE_REGNUM)) \ + offset += 4; \ + \ + (OFFSET) = offset + get_frame_size (); \ + \ + if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ + (OFFSET) += 4; /* Skip saved PC */ \ + } \ +} + +/* Addressing modes, and classification of registers for them. */ + +/* #define HAVE_POST_INCREMENT */ +/* #define HAVE_POST_DECREMENT */ + +/* #define HAVE_PRE_DECREMENT */ +/* #define HAVE_PRE_INCREMENT */ + +/* Macros to check register numbers against specific register classes. */ + +/* These assume that REGNO is a hard or pseudo reg number. + They give nonzero only if REGNO is a hard reg of the suitable class + or a pseudo reg currently allocated to a suitable hard reg. + Since they use reg_renumber, they are safe only once reg_renumber + has been allocated, which happens in local-alloc.c. */ + +#define REGNO_OK_FOR_INDEX_P(REGNO) \ + ((REGNO) < STACK_POINTER_REGNUM \ + || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM) + +#define REGNO_OK_FOR_BASE_P(REGNO) \ + ((REGNO) <= STACK_POINTER_REGNUM \ + || (REGNO) == ARG_POINTER_REGNUM \ + || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM) + +#define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4) +#define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5) + +/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx + and check its validity for a certain class. + We have two alternate definitions for each of them. + The usual definition accepts all pseudo regs; the other rejects + them unless they have been allocated suitable hard regs. + The symbol REG_OK_STRICT causes the latter definition to be used. + + Most source files want to accept pseudo regs in the hope that + they will get allocated to the class that the insn wants them to be in. + Source files for reload pass need to be strict. + After reload, it makes no difference, since pseudo regs have + been eliminated by then. */ + +#ifndef REG_OK_STRICT + +/* Nonzero if X is a hard reg that can be used as an index or if + it is a pseudo reg. */ + +#define REG_OK_FOR_INDEX_P(X) \ + (REGNO (X) < STACK_POINTER_REGNUM \ + || REGNO (X) >= FIRST_PSEUDO_REGISTER) + +/* Nonzero if X is a hard reg that can be used as a base reg + of if it is a pseudo reg. */ + /* ?wfs */ + +#define REG_OK_FOR_BASE_P(X) \ + (REGNO (X) <= STACK_POINTER_REGNUM \ + || REGNO (X) == ARG_POINTER_REGNUM \ + || REGNO(X) >= FIRST_PSEUDO_REGISTER) + +#define REG_OK_FOR_STRREG_P(X) \ + (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER) + +#else + +/* Nonzero if X is a hard reg that can be used as an index. */ +#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) +/* Nonzero if X is a hard reg that can be used as a base reg. */ +#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) +#define REG_OK_FOR_STRREG_P(X) \ + (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X))) + +#endif + +/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, + except for CONSTANT_ADDRESS_P which is usually machine-independent. + + See legitimize_pic_address in i386.c for details as to what + constitutes a legitimate address when -fpic is used. */ + +#define MAX_REGS_PER_ADDRESS 2 + +#define CONSTANT_ADDRESS_P(X) \ + (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ + || GET_CODE (X) == HIGH) + +/* Nonzero if the constant value X is a legitimate general operand. + It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_CONSTANT_P(X) 1 + +#define GO_IF_INDEXABLE_BASE(X, ADDR) \ + if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR + +#define LEGITIMATE_INDEX_REG_P(X) \ + (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) + +/* Return 1 if X is an index or an index times a scale. */ + +#define LEGITIMATE_INDEX_P(X) \ + (LEGITIMATE_INDEX_REG_P (X) \ + || (GET_CODE (X) == MULT \ + && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ + && GET_CODE (XEXP (X, 1)) == CONST_INT \ + && (INTVAL (XEXP (X, 1)) == 2 \ + || INTVAL (XEXP (X, 1)) == 4 \ + || INTVAL (XEXP (X, 1)) == 8))) + +/* Go to ADDR if X is an index term, a base reg, or a sum of those. */ + +#define GO_IF_INDEXING(X, ADDR) \ +{ if (LEGITIMATE_INDEX_P (X)) goto ADDR; \ + GO_IF_INDEXABLE_BASE (X, ADDR); \ + if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ + { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ + if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ + { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } + +/* We used to allow this, but it isn't ever used. + || ((GET_CODE (X) == POST_DEC || GET_CODE (X) == POST_INC) \ + && REG_P (XEXP (X, 0)) \ + && REG_OK_FOR_STRREG_P (XEXP (X, 0))) \ +*/ + +#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +{ \ + if (CONSTANT_ADDRESS_P (X) \ + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ + goto ADDR; \ + GO_IF_INDEXING (X, ADDR); \ + if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ + { \ + rtx x0 = XEXP (X, 0); \ + if (! flag_pic || ! SYMBOLIC_CONST (XEXP (X, 1))) \ + { GO_IF_INDEXING (x0, ADDR); } \ + else if (x0 == pic_offset_table_rtx) \ + goto ADDR; \ + else if (GET_CODE (x0) == PLUS) \ + { \ + if (XEXP (x0, 0) == pic_offset_table_rtx) \ + { GO_IF_INDEXABLE_BASE (XEXP (x0, 1), ADDR); } \ + if (XEXP (x0, 1) == pic_offset_table_rtx) \ + { GO_IF_INDEXABLE_BASE (XEXP (x0, 0), ADDR); } \ + } \ + } \ +} + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was called. + In some cases it is useful to look at this to decide what needs to be done. + + MODE and WIN are passed so that this macro can use + GO_IF_LEGITIMATE_ADDRESS. + + It is always safe for this macro to do nothing. It exists to recognize + opportunities to optimize the output. + + For the 80386, we handle X+REG by loading X into a register R and + using R+REG. R will go in a general reg and indexing will be used. + However, if REG is a broken-out memory address or multiplication, + nothing needs to be done because REG can certainly go in a general reg. + + When -fpic is used, special handling is needed for symbolic references. + See comments by legitimize_pic_address in i386.c for details. */ + +#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ +{ extern rtx legitimize_pic_address (); \ + int ch = (X) != (OLDX); \ + if (flag_pic && SYMBOLIC_CONST (X)) \ + { \ + (X) = legitimize_pic_address (X, 0); \ + if (memory_address_p (MODE, X)) \ + goto WIN; \ + } \ + if (GET_CODE (X) == PLUS) \ + { if (GET_CODE (XEXP (X, 0)) == MULT) \ + ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \ + if (GET_CODE (XEXP (X, 1)) == MULT) \ + ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \ + if (ch && GET_CODE (XEXP (X, 1)) == REG \ + && GET_CODE (XEXP (X, 0)) == REG) \ + goto WIN; \ + if (flag_pic && SYMBOLIC_CONST (XEXP (X, 1))) \ + ch = 1, (X) = legitimize_pic_address (X, 0); \ + if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ + if (GET_CODE (XEXP (X, 0)) == REG) \ + { register rtx temp = gen_reg_rtx (Pmode); \ + register rtx val = force_operand (XEXP (X, 1), temp); \ + if (val != temp) emit_move_insn (temp, val); \ + XEXP (X, 1) = temp; \ + goto WIN; } \ + else if (GET_CODE (XEXP (X, 1)) == REG) \ + { register rtx temp = gen_reg_rtx (Pmode); \ + register rtx val = force_operand (XEXP (X, 0), temp); \ + if (val != temp) emit_move_insn (temp, val); \ + XEXP (X, 0) = temp; \ + goto WIN; }}} + +/* Nonzero if the constant value X is a legitimate general operand + when generating PIC code. It is given that flag_pic is on and + that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_PIC_OPERAND_P(X) \ + (! SYMBOLIC_CONST (X) \ + || (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))) + +#define SYMBOLIC_CONST(X) \ +(GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == LABEL_REF \ + || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) + +/* Go to LABEL if ADDR (a legitimate address expression) + has an effect that depends on the machine mode it is used for. + On the 80386, only postdecrement and postincrement address depend thus + (the amount of decrement or increment being the length of the operand). */ +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ + if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL + +/* Define this macro if references to a symbol must be treated + differently depending on something about the variable or + function named by the symbol (such as what section it is in). + + On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol + so that we may access it directly in the GOT. */ + +#define ENCODE_SECTION_INFO(DECL) \ +do \ + { \ + if (flag_pic) \ + { \ + rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ + ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ + SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ + = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ + || ! TREE_PUBLIC (DECL)); \ + } \ + } \ +while (0) + +/* Initialize data used by insn expanders. This is called from + init_emit, once for each function, before code is generated. + For 386, clear stack slot assignments remembered from previous + functions. */ + +#define INIT_EXPANDERS clear_386_stack_locals () + +/* Specify the machine mode that this machine uses + for the index in the tablejump instruction. */ +#define CASE_VECTOR_MODE Pmode + +/* Define this if the tablejump instruction expects the table + to contain offsets from the address of the table. + Do not define this if the table should contain absolute addresses. */ +/* #define CASE_VECTOR_PC_RELATIVE */ + +/* Specify the tree operation to be used to convert reals to integers. + This should be changed to take advantage of fist --wfs ?? + */ +#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR + +/* This is the kind of divide that is easiest to do in the general case. */ +#define EASY_DIV_EXPR TRUNC_DIV_EXPR + +/* Define this as 1 if `char' should by default be signed; else as 0. */ +#define DEFAULT_SIGNED_CHAR 1 + +/* Max number of bytes we can move from memory to memory + in one reasonably fast instruction. */ +#define MOVE_MAX 4 + +/* MOVE_RATIO is the number of move instructions that is better than a + block move. Make this large on i386, since the block move is very + inefficient with small blocks, and the hard register needs of the + block move require much reload work. */ +#define MOVE_RATIO 5 + +/* Define this if zero-extension is slow (more than one real instruction). */ +/* #define SLOW_ZERO_EXTEND */ + +/* Nonzero if access to memory by bytes is slow and undesirable. */ +#define SLOW_BYTE_ACCESS 0 + +/* Define if shifts truncate the shift count + which implies one can omit a sign-extension or zero-extension + of a shift count. */ +/* One i386, shifts do truncate the count. But bit opcodes don't. */ + +/* #define SHIFT_COUNT_TRUNCATED */ + +/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +/* We assume that the store-condition-codes instructions store 0 for false + and some other value for true. This is the value stored for true. */ + +#define STORE_FLAG_VALUE 1 + +/* When a prototype says `char' or `short', really pass an `int'. + (The 386 can't easily push less than an int.) */ + +#define PROMOTE_PROTOTYPES + +/* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. */ +#define Pmode SImode + +/* A function address in a call instruction + is a byte address (for indexing purposes) + so give the MEM rtx a byte's mode. */ +#define FUNCTION_MODE QImode + +/* Define this if addresses of constant functions + shouldn't be put through pseudo regs where they can be cse'd. + Desirable on the 386 because a CALL with a constant address is + not much slower than one with a register address. */ +#define NO_FUNCTION_CSE + +/* Provide the costs of a rtl expression. This is in the body of a + switch on CODE. */ + +#define RTX_COSTS(X,CODE,OUTER_CODE) \ + case MULT: \ + return COSTS_N_INSNS (10); \ + case DIV: \ + case UDIV: \ + case MOD: \ + case UMOD: \ + return COSTS_N_INSNS (40); \ + case PLUS: \ + if (GET_CODE (XEXP (X, 0)) == REG \ + && GET_CODE (XEXP (X, 1)) == CONST_INT) \ + return 1; \ + break; + + +/* Compute the cost of computing a constant rtl expression RTX + whose rtx-code is CODE. The body of this macro is a portion + of a switch statement. If the code is computed here, + return it with a return statement. Otherwise, break from the switch. */ + +#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ + case CONST_INT: \ + case CONST: \ + case LABEL_REF: \ + case SYMBOL_REF: \ + return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 0; \ + case CONST_DOUBLE: \ + { \ + int code; \ + if (GET_MODE (RTX) == VOIDmode) \ + return 2; \ + code = standard_80387_constant_p (RTX); \ + return code == 1 ? 0 : \ + code == 2 ? 1 : \ + 2; \ + } + +/* Compute the cost of an address. This is meant to approximate the size + and/or execution delay of an insn using that address. If the cost is + approximated by the RTL complexity, including CONST_COSTS above, as + is usually the case for CISC machines, this macro should not be defined. + For aggressively RISCy machines, only one insn format is allowed, so + this macro should be a constant. The value of this macro only matters + for valid addresses. + + For i386, it is better to use a complex address than let gcc copy + the address into a reg and make a new pseudo. But not if the address + requires to two regs - that would mean more pseudos with longer + lifetimes. */ + +#define ADDRESS_COST(RTX) \ + ((CONSTANT_P (RTX) \ + || (GET_CODE (RTX) == PLUS && CONSTANT_P (XEXP (RTX, 1)) \ + && REG_P (XEXP (RTX, 0)))) ? 0 \ + : REG_P (RTX) ? 1 \ + : 2) + +/* Add any extra modes needed to represent the condition code. + + For the i386, we need separate modes when floating-point equality + comparisons are being done. */ + +#define EXTRA_CC_MODES CCFPEQmode + +/* Define the names for the modes specified above. */ +#define EXTRA_CC_NAMES "CCFPEQ" + +/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, + return the mode to be used for the comparison. + + For floating-point equality comparisons, CCFPEQmode should be used. + VOIDmode should be used in all other cases. */ + +#define SELECT_CC_MODE(OP,X,Y) \ + (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + && ((OP) == EQ || (OP) == NE) ? CCFPEQmode : VOIDmode) + +/* Define the information needed to generate branch and scc insns. This is + stored from the compare operation. Note that we can't use "rtx" here + since it hasn't been defined! */ + +extern struct rtx_def *i386_compare_op0, *i386_compare_op1; +extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); + +/* Tell final.c how to eliminate redundant test instructions. */ + +/* Here we define machine-dependent flags and fields in cc_status + (see `conditions.h'). */ + +/* Set if the cc value is actually in the 80387, so a floating point + conditional branch must be output. */ +#define CC_IN_80387 04000 + +/* Set if the CC value was stored in a nonstandard way, so that + the state of equality is indicated by zero in the carry bit. */ +#define CC_Z_IN_NOT_C 010000 + +/* Store in cc_status the expressions + that the condition codes will describe + after execution of an instruction whose pattern is EXP. + Do not alter them if the instruction would not alter the cc's. */ + +#define NOTICE_UPDATE_CC(EXP, INSN) \ + notice_update_cc((EXP)) + +/* Output a signed jump insn. Use template NORMAL ordinarily, or + FLOAT following a floating point comparison. + Use NO_OV following an arithmetic insn that set the cc's + before a test insn that was deleted. + NO_OV may be zero, meaning final should reinsert the test insn + because the jump cannot be handled properly without it. */ + +#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ +{ \ + if (cc_prev_status.flags & CC_IN_80387) \ + return FLOAT; \ + if (cc_prev_status.flags & CC_NO_OVERFLOW) \ + return NO_OV; \ + return NORMAL; \ +} + +/* Control the assembler format that we output, to the extent + this does not vary between assemblers. */ + +/* How to refer to registers in assembler output. + This sequence is indexed by compiler's hard-register-number (see above). */ + +/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" + For non floating point regs, the following are the HImode names. + + For float regs, the stack top is sometimes referred to as "%st(0)" + instead of just "%st". PRINT_REG handles this with the "y" code. */ + +#define HI_REGISTER_NAMES \ +{"ax","dx","cx","bx","si","di","bp","sp", \ + "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","" } + +#define REGISTER_NAMES HI_REGISTER_NAMES + +/* Table of additional register names to use in user input. */ + +#define ADDITIONAL_REGISTER_NAMES \ +{ "eax", 0, "edx", 1, "ecx", 2, "ebx", 3, \ + "esi", 4, "edi", 5, "ebp", 6, "esp", 7, \ + "al", 0, "dl", 1, "cl", 2, "bl", 3, \ + "ah", 0, "dh", 1, "ch", 2, "bh", 3 } + +/* Note we are omitting these since currently I don't know how +to get gcc to use these, since they want the same but different +number as al, and ax. +*/ + +/* note the last four are not really qi_registers, but + the md will have to never output movb into one of them + only a movw . There is no movb into the last four regs */ + +#define QI_REGISTER_NAMES \ +{"al", "dl", "cl", "bl", "si", "di", "bp", "sp",} + +/* These parallel the array above, and can be used to access bits 8:15 + of regs 0 through 3. */ + +#define QI_HIGH_REGISTER_NAMES \ +{"ah", "dh", "ch", "bh", } + +/* How to renumber registers for dbx and gdb. */ + +/* {0,2,1,3,6,7,4,5,12,13,14,15,16,17} */ +#define DBX_REGISTER_NUMBER(n) \ +((n) == 0 ? 0 : \ + (n) == 1 ? 2 : \ + (n) == 2 ? 1 : \ + (n) == 3 ? 3 : \ + (n) == 4 ? 6 : \ + (n) == 5 ? 7 : \ + (n) == 6 ? 4 : \ + (n) == 7 ? 5 : \ + (n) + 4) + +/* This is how to output the definition of a user-level label named NAME, + such as the label on a static function or variable NAME. */ + +#define ASM_OUTPUT_LABEL(FILE,NAME) \ + (assemble_name (FILE, NAME), fputs (":\n", FILE)) + +/* This is how to output an assembler line defining a `double' constant. */ + +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + fprintf (FILE, "%s %.22e\n", ASM_DOUBLE, (VALUE)) + + +/* This is how to output an assembler line defining a `float' constant. */ + +#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ +do { union { float f; long l;} tem; \ + tem.f = (VALUE); \ + fprintf((FILE), "%s 0x%x\n", ASM_LONG, tem.l); \ + } while (0) + + +/* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable named NAME. + LABELNO is an integer which is different for each call. */ + +#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ +( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ + sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) + + + +/* This is how to output an assembler line defining an `int' constant. */ + +#define ASM_OUTPUT_INT(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_LONG), \ + output_addr_const (FILE,(VALUE)), \ + putc('\n',FILE)) + +/* Likewise for `char' and `short' constants. */ +/* is this supposed to do align too?? */ + +#define ASM_OUTPUT_SHORT(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_SHORT), \ + output_addr_const (FILE,(VALUE)), \ + putc('\n',FILE)) + +/* +#define ASM_OUTPUT_SHORT(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_BYTE_OP), \ + output_addr_const (FILE,(VALUE)), \ + fputs (",", FILE), \ + output_addr_const (FILE,(VALUE)), \ + fputs (" >> 8\n",FILE)) +*/ + + +#define ASM_OUTPUT_CHAR(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_BYTE_OP), \ + output_addr_const (FILE, (VALUE)), \ + putc ('\n', FILE)) + +/* This is how to output an assembler line for a numeric constant byte. */ + +#define ASM_OUTPUT_BYTE(FILE,VALUE) \ + fprintf ((FILE), "%s 0x%x\n", ASM_BYTE_OP, (VALUE)) + +/* This is how to output an insn to push a register on the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + fprintf (FILE, "\tpushl e%s\n", reg_names[REGNO]) + +/* This is how to output an insn to pop a register from the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + fprintf (FILE, "\tpopl e%s\n", reg_names[REGNO]) + +/* This is how to output an element of a case-vector that is absolute. + */ + +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ + fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE) + +/* This is how to output an element of a case-vector that is relative. + We don't use these on the 386 yet, because the ATT assembler can't do + forward reference the differences. + */ + +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.word %s%d-%s%d\n",LPREFIX, VALUE,LPREFIX, REL) + +/* Define the parentheses used to group arithmetic operations + in assembler code. */ + +#define ASM_OPEN_PAREN "" +#define ASM_CLOSE_PAREN "" + +/* Define results of standard character escape sequences. */ +#define TARGET_BELL 007 +#define TARGET_BS 010 +#define TARGET_TAB 011 +#define TARGET_NEWLINE 012 +#define TARGET_VT 013 +#define TARGET_FF 014 +#define TARGET_CR 015 + +/* Print operand X (an rtx) in assembler syntax to file FILE. + CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. + The CODE z takes the size of operand from the following digit, and + outputs b,w,or l respectively. + + On the 80386, we use several such letters: + f -- float insn (print a CONST_DOUBLE as a float rather than in hex). + L,W,B,Q,S -- print the opcode suffix for specified size of operand. + R -- print the prefix for register names. + z -- print the opcode suffix for the size of the current operand. + * -- print a star (in certain assembler syntax) + w -- print the operand as if it's a "word" (HImode) even if it isn't. + b -- print the operand as if it's a byte (QImode) even if it isn't. + c -- don't print special prefixes before constant operands. */ + +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ + ((CODE) == '*') + +/* Print the name of a register based on its machine mode and number. + If CODE is 'w', pretend the mode is HImode. + If CODE is 'b', pretend the mode is QImode. + If CODE is 'k', pretend the mode is SImode. + If CODE is 'h', pretend the reg is the `high' byte register. + If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ + +extern char *hi_reg_name[]; +extern char *qi_reg_name[]; +extern char *qi_high_reg_name[]; + +#define PRINT_REG(X, CODE, FILE) \ + do { if (REGNO (X) == ARG_POINTER_REGNUM) \ + abort (); \ + fprintf (FILE, "%s", RP); \ + switch ((CODE == 'w' ? 2 \ + : CODE == 'b' ? 1 \ + : CODE == 'k' ? 4 \ + : CODE == 'y' ? 3 \ + : CODE == 'h' ? 0 \ + : GET_MODE_SIZE (GET_MODE (X)))) \ + { \ + case 3: \ + if (STACK_TOP_P (X)) \ + { \ + fputs ("st(0)", FILE); \ + break; \ + } \ + case 4: \ + case 8: \ + if (! FP_REG_P (X)) fputs ("e", FILE); \ + case 2: \ + fputs (hi_reg_name[REGNO (X)], FILE); \ + break; \ + case 1: \ + fputs (qi_reg_name[REGNO (X)], FILE); \ + break; \ + case 0: \ + fputs (qi_high_reg_name[REGNO (X)], FILE); \ + break; \ + } \ + } while (0) + +#define PRINT_OPERAND(FILE, X, CODE) \ + print_operand (FILE, X, CODE) + +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ + print_operand_address (FILE, ADDR) + +/* Print the name of a register for based on its machine mode and number. + This macro is used to print debugging output. + This macro is different from PRINT_REG in that it may be used in + programs that are not linked with aux-output.o. */ + +#define DEBUG_PRINT_REG(X, CODE, FILE) \ + do { static char *hi_name[] = HI_REGISTER_NAMES; \ + static char *qi_name[] = QI_REGISTER_NAMES; \ + fprintf (FILE, "%d %s", REGNO (X), RP); \ + if (REGNO (X) == ARG_POINTER_REGNUM) \ + { fputs ("argp", FILE); break; } \ + if (STACK_TOP_P (X)) \ + { fputs ("st(0)", FILE); break; } \ + switch (GET_MODE_SIZE (GET_MODE (X))) \ + { \ + case 8: \ + case 4: \ + if (! FP_REG_P (X)) fputs ("e", FILE); \ + case 2: \ + fputs (hi_name[REGNO (X)], FILE); \ + break; \ + case 1: \ + fputs (qi_name[REGNO (X)], FILE); \ + break; \ + } \ + } while (0) + +/* Output the prefix for an immediate operand, or for an offset operand. */ +#define PRINT_IMMED_PREFIX(FILE) fputs (IP, (FILE)) +#define PRINT_OFFSET_PREFIX(FILE) fputs (IP, (FILE)) + +/* Routines in libgcc that return floats must return them in an fp reg, + just as other functions do which return such values. + These macros make that happen. */ + +#define FLOAT_VALUE_TYPE float +#define INTIFY(FLOATVAL) FLOATVAL + +/* Nonzero if INSN magically clobbers register REGNO. */ + +/* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) \ + (FP_REGNO_P (REGNO) \ + && (GET_CODE (INSN) == JUMP_INSN || GET_CODE (INSN) == BARRIER)) +*/ + +/* a letter which is not needed by the normal asm syntax, which + we can use for operand syntax in the extended asm */ + +#define ASM_OPERAND_LETTER '#' + +#define RET return "" +#define AT_SP(mode) (gen_rtx (MEM, (mode), stack_pointer_rtx)) + +/* +Local variables: +version-control: t +End: +*/ diff --git a/gnu/usr.bin/cc/lib/i386/perform.h b/gnu/usr.bin/cc/lib/i386/perform.h new file mode 100644 index 000000000000..c1a417071cae --- /dev/null +++ b/gnu/usr.bin/cc/lib/i386/perform.h @@ -0,0 +1,93 @@ +/* Definitions for AT&T assembler syntax for the Intel 80386. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Defines to be able to build libgcc.a with GCC. */ + +/* It might seem that these are not important, since gcc 2 will never + call libgcc for these functions. But programs might be linked with + code compiled by gcc 1, and then these will be used. */ + +/* The arg names used to be a and b, but `a' appears inside strings + and that confuses non-ANSI cpp. */ + +#define perform_udivsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + \ + dx = 0; \ + ax = arg0; \ + asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \ + return ax; \ +} + +#define perform_divsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + \ + ax = arg0; \ + asm ("cltd\n\tidivl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1)); \ + return ax; \ +} + +#define perform_umodsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + \ + dx = 0; \ + ax = arg0; \ + asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \ + return dx; \ +} + +#define perform_modsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + \ + ax = arg0; \ + asm ("cltd\n\tidivl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1)); \ + return dx; \ +} + +#define perform_fixdfsi(arg0) \ +{ \ + auto unsigned short ostatus; \ + auto unsigned short nstatus; \ + auto int ret; \ + auto double tmp; \ + \ + &ostatus; /* guarantee these land in memory */ \ + &nstatus; \ + &ret; \ + &tmp; \ + \ + asm volatile ("fnstcw %0" : "=m" (ostatus)); \ + nstatus = ostatus | 0x0c00; \ + asm volatile ("fldcw %0" : /* no outputs */ : "m" (nstatus)); \ + tmp = arg0; \ + asm volatile ("fldl %0" : /* no outputs */ : "m" (tmp)); \ + asm volatile ("fistpl %0" : "=m" (ret)); \ + asm volatile ("fldcw %0" : /* no outputs */ : "m" (ostatus)); \ + \ + return ret; \ +} + diff --git a/gnu/usr.bin/cc/lib/i386/unix.h b/gnu/usr.bin/cc/lib/i386/unix.h new file mode 100644 index 000000000000..7209176d191e --- /dev/null +++ b/gnu/usr.bin/cc/lib/i386/unix.h @@ -0,0 +1,145 @@ +/* Definitions for Unix assembler syntax for the Intel 80386. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* This file defines the aspects of assembler syntax + that are the same for all the i386 Unix systems + (though they may differ in non-Unix systems). */ + +/* Define some concatenation macros to concatenate an opcode + and one, two or three operands. In other assembler syntaxes + they may alter the order of ther operands. */ + +/* Note that the other files fail to use these + in some of the places where they should. */ + +#ifdef __STDC__ +#define AS2(a,b,c) #a " " #b "," #c +#define AS3(a,b,c,d) #a " " #b "," #c "," #d +#define AS1(a,b) #a " " #b +#else +#define AS1(a,b) "a b" +#define AS2(a,b,c) "a b,c" +#define AS3(a,b,c,d) "a b,c,d" +#endif + +/* Define macro used to output shift-double opcodes when the shift + count is in %cl. Some assemblers require %cl as an argument; + some don't. This macro controls what to do: by default, don't + print %cl. */ +#define AS3_SHIFT_DOUBLE(a,b,c,d) AS2 (a,c,d) + +/* Output the size-letter for an opcode. + CODE is the letter used in an operand spec (L, B, W, S or Q). + CH is the corresponding lower case letter + (except if CODE is `Q' then CH is `l', unless GAS_MNEMONICS). */ +#define PUT_OP_SIZE(CODE,CH,FILE) putc (CH,(FILE)) + +/* Opcode suffix for fullword insn. */ +#define L_SIZE "l" + +/* Prefix for register names in this syntax. */ +#define RP "%" + +/* Prefix for immediate operands in this syntax. */ +#define IP "$" + +/* Indirect call instructions should use `*'. */ +#define USE_STAR 1 + +/* Prefix for a memory-operand X. */ +#define PRINT_PTR(X, FILE) + +/* Delimiters that surround base reg and index reg. */ +#define ADDR_BEG(FILE) putc('(', (FILE)) +#define ADDR_END(FILE) putc(')', (FILE)) + +/* Print an index register (whose rtx is IREG). */ +#define PRINT_IREG(FILE,IREG) \ + do \ + { fputs (",", (FILE)); PRINT_REG ((IREG), 0, (FILE)); } \ + while (0) + +/* Print an index scale factor SCALE. */ +#define PRINT_SCALE(FILE,SCALE) \ + if ((SCALE) != 1) fprintf ((FILE), ",%d", (SCALE)) + +/* Print a base/index combination. + BREG is the base reg rtx, IREG is the index reg rtx, + and SCALE is the index scale factor (an integer). */ + +#define PRINT_B_I_S(BREG,IREG,SCALE,FILE) \ + { ADDR_BEG (FILE); \ + if (BREG) PRINT_REG ((BREG), 0, (FILE)); \ + if ((IREG) != 0) \ + { PRINT_IREG ((FILE), (IREG)); \ + PRINT_SCALE ((FILE), (SCALE)); } \ + ADDR_END (FILE); } + +/* Define the syntax of pseudo-ops, labels and comments. */ + +/* String containing the assembler's comment-starter. */ + +#define ASM_COMMENT_START "/" +#define COMMENT_BEGIN "/" + +/* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + +#define ASM_APP_ON "/APP\n" + +/* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + +#define ASM_APP_OFF "/NO_APP\n" + +/* Output before read-only data. */ + +#define TEXT_SECTION_ASM_OP ".text" + +/* Output before writable (initialized) data. */ + +#define DATA_SECTION_ASM_OP ".data" + +/* Output before writable (uninitialized) data. */ + +#define BSS_SECTION_ASM_OP ".bss" + +/* This is how to output a command to make the user-level label named NAME + defined for reference from other files. */ + +#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ + (fputs (".globl ", FILE), assemble_name (FILE, NAME), fputs ("\n", FILE)) + +/* By default, target has a 80387, uses IEEE compatible arithmetic, + and returns float values in the 387, ie, + (TARGET_80387 | TARGET_IEEE_FP | TARGET_FLOAT_RETURNS_IN_80387) */ + +#define TARGET_DEFAULT 0301 + +/* Floating-point return values come in the FP register. */ + +#define VALUE_REGNO(MODE) \ + (GET_MODE_CLASS (MODE) == MODE_FLOAT \ + && TARGET_FLOAT_RETURNS_IN_80387 ? FIRST_FLOAT_REG : 0) + +/* 1 if N is a possible register number for a function value. */ + +#define FUNCTION_VALUE_REGNO_P(N) \ + ((N) == 0 || ((N)== FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)) + diff --git a/gnu/usr.bin/cc/lib/input.h b/gnu/usr.bin/cc/lib/input.h new file mode 100644 index 000000000000..39590e2eb5e3 --- /dev/null +++ b/gnu/usr.bin/cc/lib/input.h @@ -0,0 +1,46 @@ +/* Declarations for variables relating to reading the source file. + Used by parsers, lexical analyzers, and error message routines. + + Copyright (C) 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Source file current line is coming from. */ +extern char *input_filename; + +/* Top-level source file. */ +extern char *main_input_filename; + +/* Line number in current source file. */ +extern int lineno; + +/* Stream for reading from input file. */ +extern FILE *finput; + +struct file_stack + { + char *name; + struct file_stack *next; + int line; + }; + +/* Stack of currently pending input files. + The line member is not accurate for the innermost file on the stack. */ +extern struct file_stack *input_file_stack; + +/* Incremented on each change to input_file_stack. */ +extern int input_file_stack_tick; diff --git a/gnu/usr.bin/cc/lib/insn-attr.h b/gnu/usr.bin/cc/lib/insn-attr.h new file mode 100644 index 000000000000..5fe9a2f80012 --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-attr.h @@ -0,0 +1,19 @@ +/* Generated automatically by the program `genattr' +from the machine description file `md'. */ + +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif +#define HAVE_ATTR_alternative +#define get_attr_alternative(insn) which_alternative + +#define ATTR_FLAG_forward 0x1 +#define ATTR_FLAG_backward 0x2 +#define ATTR_FLAG_likely 0x4 +#define ATTR_FLAG_very_likely 0x8 +#define ATTR_FLAG_unlikely 0x10 +#define ATTR_FLAG_very_unlikely 0x20 diff --git a/gnu/usr.bin/cc/lib/insn-attrtab.c b/gnu/usr.bin/cc/lib/insn-attrtab.c new file mode 100644 index 000000000000..0e86d1f4c35a --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-attrtab.c @@ -0,0 +1,14 @@ +/* Generated automatically by the program `genattrtab' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "recog.h" +#include "regs.h" +#include "real.h" +#include "output.h" +#include "insn-attr.h" + +#define operands recog_operand + diff --git a/gnu/usr.bin/cc/lib/insn-codes.h b/gnu/usr.bin/cc/lib/insn-codes.h new file mode 100644 index 000000000000..59b4e98d5199 --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-codes.h @@ -0,0 +1,174 @@ +/* Generated automatically by the program `gencodes' +from the machine description file `md'. */ + +#ifndef MAX_INSN_CODE + +enum insn_code { + CODE_FOR_tstsi_1 = 0, + CODE_FOR_tstsi = 1, + CODE_FOR_tsthi_1 = 2, + CODE_FOR_tsthi = 3, + CODE_FOR_tstqi_1 = 4, + CODE_FOR_tstqi = 5, + CODE_FOR_tstsf_cc = 6, + CODE_FOR_tstsf = 7, + CODE_FOR_tstdf_cc = 8, + CODE_FOR_tstdf = 9, + CODE_FOR_cmpsi_1 = 10, + CODE_FOR_cmpsi = 11, + CODE_FOR_cmphi_1 = 12, + CODE_FOR_cmphi = 13, + CODE_FOR_cmpqi_1 = 14, + CODE_FOR_cmpqi = 15, + CODE_FOR_cmpsf_cc_1 = 22, + CODE_FOR_cmpdf = 26, + CODE_FOR_cmpsf = 27, + CODE_FOR_cmpdf_cc = 28, + CODE_FOR_cmpdf_ccfpeq = 29, + CODE_FOR_cmpsf_cc = 30, + CODE_FOR_cmpsf_ccfpeq = 31, + CODE_FOR_movsi = 37, + CODE_FOR_movhi = 40, + CODE_FOR_movstricthi = 41, + CODE_FOR_movqi = 43, + CODE_FOR_movstrictqi = 44, + CODE_FOR_movsf = 46, + CODE_FOR_swapdf = 48, + CODE_FOR_movdf = 49, + CODE_FOR_movdi = 51, + CODE_FOR_zero_extendhisi2 = 52, + CODE_FOR_zero_extendqihi2 = 53, + CODE_FOR_zero_extendqisi2 = 54, + CODE_FOR_zero_extendsidi2 = 55, + CODE_FOR_extendsidi2 = 56, + CODE_FOR_extendhisi2 = 57, + CODE_FOR_extendqihi2 = 58, + CODE_FOR_extendqisi2 = 59, + CODE_FOR_extendsfdf2 = 60, + CODE_FOR_truncdfsf2 = 61, + CODE_FOR_fixuns_truncdfsi2 = 63, + CODE_FOR_fixuns_truncsfsi2 = 64, + CODE_FOR_fix_truncdfdi2 = 65, + CODE_FOR_fix_truncsfdi2 = 66, + CODE_FOR_fix_truncdfsi2 = 69, + CODE_FOR_fix_truncsfsi2 = 70, + CODE_FOR_floatsisf2 = 73, + CODE_FOR_floatdisf2 = 74, + CODE_FOR_floatsidf2 = 75, + CODE_FOR_floatdidf2 = 76, + CODE_FOR_adddi3 = 81, + CODE_FOR_addsi3 = 82, + CODE_FOR_addhi3 = 83, + CODE_FOR_addqi3 = 84, + CODE_FOR_adddf3 = 86, + CODE_FOR_addsf3 = 87, + CODE_FOR_subdi3 = 88, + CODE_FOR_subsi3 = 89, + CODE_FOR_subhi3 = 90, + CODE_FOR_subqi3 = 91, + CODE_FOR_subdf3 = 92, + CODE_FOR_subsf3 = 93, + CODE_FOR_mulhi3 = 95, + CODE_FOR_mulsi3 = 97, + CODE_FOR_muldf3 = 99, + CODE_FOR_mulsf3 = 100, + CODE_FOR_divqi3 = 101, + CODE_FOR_udivqi3 = 102, + CODE_FOR_divdf3 = 103, + CODE_FOR_divsf3 = 104, + CODE_FOR_divmodsi4 = 105, + CODE_FOR_divmodhi4 = 106, + CODE_FOR_udivmodsi4 = 107, + CODE_FOR_udivmodhi4 = 108, + CODE_FOR_andsi3 = 109, + CODE_FOR_andhi3 = 110, + CODE_FOR_andqi3 = 111, + CODE_FOR_iorsi3 = 112, + CODE_FOR_iorhi3 = 113, + CODE_FOR_iorqi3 = 114, + CODE_FOR_xorsi3 = 115, + CODE_FOR_xorhi3 = 116, + CODE_FOR_xorqi3 = 117, + CODE_FOR_negdi2 = 118, + CODE_FOR_negsi2 = 119, + CODE_FOR_neghi2 = 120, + CODE_FOR_negqi2 = 121, + CODE_FOR_negsf2 = 122, + CODE_FOR_negdf2 = 123, + CODE_FOR_abssf2 = 125, + CODE_FOR_absdf2 = 126, + CODE_FOR_sqrtsf2 = 128, + CODE_FOR_sqrtdf2 = 129, + CODE_FOR_sindf2 = 131, + CODE_FOR_sinsf2 = 132, + CODE_FOR_cosdf2 = 134, + CODE_FOR_cossf2 = 135, + CODE_FOR_one_cmplsi2 = 137, + CODE_FOR_one_cmplhi2 = 138, + CODE_FOR_one_cmplqi2 = 139, + CODE_FOR_ashldi3 = 140, + CODE_FOR_ashldi3_const_int = 141, + CODE_FOR_ashldi3_non_const_int = 142, + CODE_FOR_ashlsi3 = 143, + CODE_FOR_ashlhi3 = 144, + CODE_FOR_ashlqi3 = 145, + CODE_FOR_ashrdi3 = 146, + CODE_FOR_ashrdi3_const_int = 147, + CODE_FOR_ashrdi3_non_const_int = 148, + CODE_FOR_ashrsi3 = 149, + CODE_FOR_ashrhi3 = 150, + CODE_FOR_ashrqi3 = 151, + CODE_FOR_lshrdi3 = 152, + CODE_FOR_lshrdi3_const_int = 153, + CODE_FOR_lshrdi3_non_const_int = 154, + CODE_FOR_lshrsi3 = 155, + CODE_FOR_lshrhi3 = 156, + CODE_FOR_lshrqi3 = 157, + CODE_FOR_rotlsi3 = 158, + CODE_FOR_rotlhi3 = 159, + CODE_FOR_rotlqi3 = 160, + CODE_FOR_rotrsi3 = 161, + CODE_FOR_rotrhi3 = 162, + CODE_FOR_rotrqi3 = 163, + CODE_FOR_seq = 170, + CODE_FOR_sne = 172, + CODE_FOR_sgt = 174, + CODE_FOR_sgtu = 176, + CODE_FOR_slt = 178, + CODE_FOR_sltu = 180, + CODE_FOR_sge = 182, + CODE_FOR_sgeu = 184, + CODE_FOR_sle = 186, + CODE_FOR_sleu = 188, + CODE_FOR_beq = 190, + CODE_FOR_bne = 192, + CODE_FOR_bgt = 194, + CODE_FOR_bgtu = 196, + CODE_FOR_blt = 198, + CODE_FOR_bltu = 200, + CODE_FOR_bge = 202, + CODE_FOR_bgeu = 204, + CODE_FOR_ble = 206, + CODE_FOR_bleu = 208, + CODE_FOR_jump = 220, + CODE_FOR_indirect_jump = 221, + CODE_FOR_casesi = 222, + CODE_FOR_tablejump = 224, + CODE_FOR_call_pop = 225, + CODE_FOR_call = 228, + CODE_FOR_call_value_pop = 231, + CODE_FOR_call_value = 234, + CODE_FOR_untyped_call = 237, + CODE_FOR_untyped_return = 240, + CODE_FOR_update_return = 241, + CODE_FOR_return = 242, + CODE_FOR_nop = 243, + CODE_FOR_movstrsi = 244, + CODE_FOR_cmpstrsi = 246, + CODE_FOR_ffssi2 = 249, + CODE_FOR_ffshi2 = 251, + CODE_FOR_strlensi = 261, + CODE_FOR_nothing }; + +#define MAX_INSN_CODE ((int) CODE_FOR_nothing) +#endif /* MAX_INSN_CODE */ diff --git a/gnu/usr.bin/cc/lib/insn-config.h b/gnu/usr.bin/cc/lib/insn-config.h new file mode 100644 index 000000000000..7dba8866f62f --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-config.h @@ -0,0 +1,12 @@ +/* Generated automatically by the program `genconfig' +from the machine description file `md'. */ + + +#define MAX_RECOG_OPERANDS 10 + +#define MAX_DUP_OPERANDS 3 +#ifndef MAX_INSNS_PER_SPLIT +#define MAX_INSNS_PER_SPLIT 1 +#endif +#define REGISTER_CONSTRAINTS +#define HAVE_cc0 diff --git a/gnu/usr.bin/cc/lib/insn-emit.c b/gnu/usr.bin/cc/lib/insn-emit.c new file mode 100644 index 000000000000..8a8d9bd4f80b --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-emit.c @@ -0,0 +1,2708 @@ +/* Generated automatically by the program `genemit' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "expr.h" +#include "real.h" +#include "output.h" +#include "insn-config.h" + +#include "insn-flags.h" + +#include "insn-codes.h" + +extern char *insn_operand_constraint[][MAX_RECOG_OPERANDS]; + +extern rtx recog_operand[]; +#define operands emit_operand + +#define FAIL goto _fail + +#define DONE goto _done + +rtx +gen_tstsi_1 (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tstsi (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + i386_compare_gen = gen_tstsi_1; + i386_compare_op0 = operands[0]; + DONE; +} + operand0 = operands[0]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, operand0)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tsthi_1 (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tsthi (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + i386_compare_gen = gen_tsthi_1; + i386_compare_op0 = operands[0]; + DONE; +} + operand0 = operands[0]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, operand0)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tstqi_1 (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tstqi (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + i386_compare_gen = gen_tstqi_1; + i386_compare_op0 = operands[0]; + DONE; +} + operand0 = operands[0]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, operand0)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tstsf_cc (operand0) + rtx operand0; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, operand0), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)))); +} + +rtx +gen_tstsf (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + i386_compare_gen = gen_tstsf_cc; + i386_compare_op0 = operands[0]; + DONE; +} + operand0 = operands[0]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, operand0), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tstdf_cc (operand0) + rtx operand0; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, operand0), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)))); +} + +rtx +gen_tstdf (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + i386_compare_gen = gen_tstdf_cc; + i386_compare_op0 = operands[0]; + DONE; +} + operand0 = operands[0]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, operand0), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpsi_1 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmpsi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + operands[0] = force_reg (SImode, operands[0]); + + i386_compare_gen = gen_cmpsi_1; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmphi_1 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmphi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + operands[0] = force_reg (HImode, operands[0]); + + i386_compare_gen = gen_cmphi_1; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpqi_1 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmpqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + operands[0] = force_reg (QImode, operands[0]); + + i386_compare_gen = gen_cmpqi_1; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpsf_cc_1 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (GET_CODE (operand2), VOIDmode, + operand0, + operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)))); +} + +rtx +gen_cmpdf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + i386_compare_gen = gen_cmpdf_cc; + i386_compare_gen_eq = gen_cmpdf_ccfpeq; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpsf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + i386_compare_gen = gen_cmpsf_cc; + i386_compare_gen_eq = gen_cmpsf_ccfpeq; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpdf_cc (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)))); +} + +rtx +gen_cmpdf_ccfpeq (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (! register_operand (operands[1], DFmode)) + operands[1] = copy_to_mode_reg (DFmode, operands[1]); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, CCFPEQmode, operand0, operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpsf_cc (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)))); +} + +rtx +gen_cmpsf_ccfpeq (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (! register_operand (operands[1], SFmode)) + operands[1] = copy_to_mode_reg (SFmode, operands[1]); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, CCFPEQmode, operand0, operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_movsi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + extern int flag_pic; + + if (flag_pic && SYMBOLIC_CONST (operands[1])) + emit_pic_move (operands, SImode); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_movhi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movstricthi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand0), operand1); +} + +rtx +gen_movqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movstrictqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand0), operand1); +} + +rtx +gen_movsf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_swapdf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, operand1), + gen_rtx (SET, VOIDmode, operand1, operand0))); +} + +rtx +gen_movdf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movdi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_zero_extendhisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, SImode, operand1)); +} + +rtx +gen_zero_extendqihi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, HImode, operand1)); +} + +rtx +gen_zero_extendqisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, SImode, operand1)); +} + +rtx +gen_zero_extendsidi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, DImode, operand1)); +} + +rtx +gen_extendsidi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, DImode, operand1)); +} + +rtx +gen_extendhisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, SImode, operand1)); +} + +rtx +gen_extendqihi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, HImode, operand1)); +} + +rtx +gen_extendqisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, SImode, operand1)); +} + +rtx +gen_extendsfdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_EXTEND, DFmode, operand1)); +} + +rtx +gen_truncdfsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[2] = (rtx) assign_386_stack_local (SFmode, 0); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_TRUNCATE, SFmode, operand1)), + gen_rtx (CLOBBER, VOIDmode, operand2)))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fixuns_truncdfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operand4; + rtx operand5; + rtx operand6; + rtx operands[7]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[2] = gen_reg_rtx (DImode); + operands[3] = gen_lowpart (SImode, operands[2]); + operands[4] = gen_reg_rtx (DFmode); + operands[5] = (rtx) assign_386_stack_local (SImode, 0); + operands[6] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + operand6 = operands[6]; + emit_insn (gen_rtx (SET, VOIDmode, operand4, operand1)); + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, + gen_rtx (SET, VOIDmode, operand2, gen_rtx (FIX, DImode, gen_rtx (FIX, DFmode, operand4))), + gen_rtx (CLOBBER, VOIDmode, operand4), + gen_rtx (CLOBBER, VOIDmode, operand5), + gen_rtx (CLOBBER, VOIDmode, operand6), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + emit_insn (gen_rtx (SET, VOIDmode, operand0, operand3)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fixuns_truncsfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operand4; + rtx operand5; + rtx operand6; + rtx operands[7]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[2] = gen_reg_rtx (DImode); + operands[3] = gen_lowpart (SImode, operands[2]); + operands[4] = gen_reg_rtx (SFmode); + operands[5] = (rtx) assign_386_stack_local (SImode, 0); + operands[6] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + operand6 = operands[6]; + emit_insn (gen_rtx (SET, VOIDmode, operand4, operand1)); + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, + gen_rtx (SET, VOIDmode, operand2, gen_rtx (FIX, DImode, gen_rtx (FIX, SFmode, operand4))), + gen_rtx (CLOBBER, VOIDmode, operand4), + gen_rtx (CLOBBER, VOIDmode, operand5), + gen_rtx (CLOBBER, VOIDmode, operand6), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + emit_insn (gen_rtx (SET, VOIDmode, operand0, operand3)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fix_truncdfdi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operand4; + rtx operands[5]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[1] = copy_to_mode_reg (DFmode, operands[1]); + operands[2] = gen_reg_rtx (DFmode); + operands[3] = (rtx) assign_386_stack_local (SImode, 0); + operands[4] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + emit_insn (gen_rtx (SET, VOIDmode, operand2, operand1)); + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, DImode, gen_rtx (FIX, DFmode, operand2))), + gen_rtx (CLOBBER, VOIDmode, operand2), + gen_rtx (CLOBBER, VOIDmode, operand3), + gen_rtx (CLOBBER, VOIDmode, operand4), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fix_truncsfdi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operand4; + rtx operands[5]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[1] = copy_to_mode_reg (SFmode, operands[1]); + operands[2] = gen_reg_rtx (SFmode); + operands[3] = (rtx) assign_386_stack_local (SImode, 0); + operands[4] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + emit_insn (gen_rtx (SET, VOIDmode, operand2, operand1)); + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, DImode, gen_rtx (FIX, SFmode, operand2))), + gen_rtx (CLOBBER, VOIDmode, operand2), + gen_rtx (CLOBBER, VOIDmode, operand3), + gen_rtx (CLOBBER, VOIDmode, operand4), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fix_truncdfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[2] = (rtx) assign_386_stack_local (SImode, 0); + operands[3] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (4, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, gen_rtx (FIX, DFmode, operand1))), + gen_rtx (CLOBBER, VOIDmode, operand2), + gen_rtx (CLOBBER, VOIDmode, operand3), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fix_truncsfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[2] = (rtx) assign_386_stack_local (SImode, 0); + operands[3] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (4, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, gen_rtx (FIX, SFmode, operand1))), + gen_rtx (CLOBBER, VOIDmode, operand2), + gen_rtx (CLOBBER, VOIDmode, operand3), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_floatsisf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, SFmode, operand1)); +} + +rtx +gen_floatdisf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, SFmode, operand1)); +} + +rtx +gen_floatsidf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, DFmode, operand1)); +} + +rtx +gen_floatdidf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, DFmode, operand1)); +} + +rtx +gen_adddi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, DImode, operand1, operand2)); +} + +rtx +gen_addsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SImode, operand1, operand2)); +} + +rtx +gen_addhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, HImode, operand1, operand2)); +} + +rtx +gen_addqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, QImode, operand1, operand2)); +} + +rtx +gen_adddf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, DFmode, operand1, operand2)); +} + +rtx +gen_addsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SFmode, operand1, operand2)); +} + +rtx +gen_subdi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, DImode, operand1, operand2)); +} + +rtx +gen_subsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, SImode, operand1, operand2)); +} + +rtx +gen_subhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, HImode, operand1, operand2)); +} + +rtx +gen_subqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, QImode, operand1, operand2)); +} + +rtx +gen_subdf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, DFmode, operand1, operand2)); +} + +rtx +gen_subsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, SFmode, operand1, operand2)); +} + +rtx +gen_mulhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SImode, operand1, operand2)); +} + +rtx +gen_mulsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SImode, operand1, operand2)); +} + +rtx +gen_muldf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, DFmode, operand1, operand2)); +} + +rtx +gen_mulsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SFmode, operand1, operand2)); +} + +rtx +gen_divqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, QImode, operand1, operand2)); +} + +rtx +gen_udivqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, QImode, operand1, operand2)); +} + +rtx +gen_divdf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, DFmode, operand1, operand2)); +} + +rtx +gen_divsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, SFmode, operand1, operand2)); +} + +rtx +gen_divmodsi4 (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, SImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, operand3, gen_rtx (MOD, SImode, operand1, operand2)))); +} + +rtx +gen_divmodhi4 (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, HImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, operand3, gen_rtx (MOD, HImode, operand1, operand2)))); +} + +rtx +gen_udivmodsi4 (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, SImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, operand3, gen_rtx (UMOD, SImode, operand1, operand2)))); +} + +rtx +gen_udivmodhi4 (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, HImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, operand3, gen_rtx (UMOD, HImode, operand1, operand2)))); +} + +rtx +gen_andsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, SImode, operand1, operand2)); +} + +rtx +gen_andhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, HImode, operand1, operand2)); +} + +rtx +gen_andqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, QImode, operand1, operand2)); +} + +rtx +gen_iorsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, SImode, operand1, operand2)); +} + +rtx +gen_iorhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, HImode, operand1, operand2)); +} + +rtx +gen_iorqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, QImode, operand1, operand2)); +} + +rtx +gen_xorsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, SImode, operand1, operand2)); +} + +rtx +gen_xorhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, HImode, operand1, operand2)); +} + +rtx +gen_xorqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, QImode, operand1, operand2)); +} + +rtx +gen_negdi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, DImode, operand1)); +} + +rtx +gen_negsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, SImode, operand1)); +} + +rtx +gen_neghi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, HImode, operand1)); +} + +rtx +gen_negqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, QImode, operand1)); +} + +rtx +gen_negsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, SFmode, operand1)); +} + +rtx +gen_negdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, DFmode, operand1)); +} + +rtx +gen_abssf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, SFmode, operand1)); +} + +rtx +gen_absdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, DFmode, operand1)); +} + +rtx +gen_sqrtsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SQRT, SFmode, operand1)); +} + +rtx +gen_sqrtdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SQRT, DFmode, operand1)); +} + +rtx +gen_sindf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSPEC, DFmode, gen_rtvec (1, + operand1), 1)); +} + +rtx +gen_sinsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSPEC, SFmode, gen_rtvec (1, + operand1), 1)); +} + +rtx +gen_cosdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSPEC, DFmode, gen_rtvec (1, + operand1), 2)); +} + +rtx +gen_cossf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSPEC, SFmode, gen_rtvec (1, + operand1), 2)); +} + +rtx +gen_one_cmplsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, SImode, operand1)); +} + +rtx +gen_one_cmplhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, HImode, operand1)); +} + +rtx +gen_one_cmplqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, QImode, operand1)); +} + +rtx +gen_ashldi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT + || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) + { + operands[2] = copy_to_mode_reg (QImode, operands[2]); + emit_insn (gen_ashldi3_non_const_int (operands[0], operands[1], + operands[2])); + } + else + emit_insn (gen_ashldi3_const_int (operands[0], operands[1], operands[2])); + + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, DImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ashldi3_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, DImode, operand1, operand2)); +} + +rtx +gen_ashldi3_non_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, DImode, operand1, operand2)), + gen_rtx (CLOBBER, VOIDmode, operand2))); +} + +rtx +gen_ashlsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, SImode, operand1, operand2)); +} + +rtx +gen_ashlhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, HImode, operand1, operand2)); +} + +rtx +gen_ashlqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, QImode, operand1, operand2)); +} + +rtx +gen_ashrdi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT + || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) + { + operands[2] = copy_to_mode_reg (QImode, operands[2]); + emit_insn (gen_ashrdi3_non_const_int (operands[0], operands[1], + operands[2])); + } + else + emit_insn (gen_ashrdi3_const_int (operands[0], operands[1], operands[2])); + + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, DImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ashrdi3_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, DImode, operand1, operand2)); +} + +rtx +gen_ashrdi3_non_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, DImode, operand1, operand2)), + gen_rtx (CLOBBER, VOIDmode, operand2))); +} + +rtx +gen_ashrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, SImode, operand1, operand2)); +} + +rtx +gen_ashrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, HImode, operand1, operand2)); +} + +rtx +gen_ashrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, QImode, operand1, operand2)); +} + +rtx +gen_lshrdi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT + || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) + { + operands[2] = copy_to_mode_reg (QImode, operands[2]); + emit_insn (gen_lshrdi3_non_const_int (operands[0], operands[1], + operands[2])); + } + else + emit_insn (gen_lshrdi3_const_int (operands[0], operands[1], operands[2])); + + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, DImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_lshrdi3_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, DImode, operand1, operand2)); +} + +rtx +gen_lshrdi3_non_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, DImode, operand1, operand2)), + gen_rtx (CLOBBER, VOIDmode, operand2))); +} + +rtx +gen_lshrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, SImode, operand1, operand2)); +} + +rtx +gen_lshrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, HImode, operand1, operand2)); +} + +rtx +gen_lshrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, QImode, operand1, operand2)); +} + +rtx +gen_rotlsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, SImode, operand1, operand2)); +} + +rtx +gen_rotlhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, HImode, operand1, operand2)); +} + +rtx +gen_rotlqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, QImode, operand1, operand2)); +} + +rtx +gen_rotrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, SImode, operand1, operand2)); +} + +rtx +gen_rotrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, HImode, operand1, operand2)); +} + +rtx +gen_rotrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, QImode, operand1, operand2)); +} + +rtx +gen_seq (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (EQ, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sne (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (NE, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sgt (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (GT, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sgtu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (GTU, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_slt (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LT, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sltu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LTU, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sge (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (GE, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sgeu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (GEU, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sle (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LE, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sleu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LEU, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_beq (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (EQ, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bne (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (NE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bgt (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GT, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bgtu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GTU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_blt (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LT, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bltu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LTU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bge (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bgeu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GEU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ble (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bleu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LEU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_jump (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (LABEL_REF, VOIDmode, operand0)); +} + +rtx +gen_indirect_jump (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, operand0); +} + +rtx +gen_casesi (operand0, operand1, operand2, operand3, operand4) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; + rtx operand4; +{ + rtx operand5; + rtx operands[6]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + operands[4] = operand4; + +{ + operands[5] = gen_reg_rtx (SImode); + current_function_uses_pic_offset_table = 1; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + emit_insn (gen_rtx (SET, VOIDmode, operand5, gen_rtx (MINUS, SImode, operand0, operand1))); + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, CCmode, operand5, operand2))); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GTU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand4), pc_rtx))); + emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (MINUS, SImode, gen_rtx (REG, SImode, 3), gen_rtx (MEM, SImode, gen_rtx (PLUS, SImode, gen_rtx (MULT, SImode, operand5, GEN_INT (4)), gen_rtx (LABEL_REF, VOIDmode, operand3))))), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tablejump (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, pc_rtx, operand0), + gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, operand1)))); +} + +rtx +gen_call_pop (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[0], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[0], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[0], QImode)) + operands[0] + = change_address (operands[0], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit_call_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (CALL, VOIDmode, operand0, operand1), + gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 7), gen_rtx (PLUS, SImode, gen_rtx (REG, SImode, 7), operand3))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_call (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[0], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[0], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[0], QImode)) + operands[0] + = change_address (operands[0], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_call_insn (gen_rtx (CALL, VOIDmode, operand0, operand1)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_call_value_pop (operand0, operand1, operand2, operand3, operand4) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; + rtx operand4; +{ + rtx operands[5]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + operands[4] = operand4; + +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[1], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[1], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[1], QImode)) + operands[1] + = change_address (operands[1], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + emit_call_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (CALL, VOIDmode, operand1, operand2)), + gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 7), gen_rtx (PLUS, SImode, gen_rtx (REG, SImode, 7), operand4))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_call_value (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[1], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[1], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[1], QImode)) + operands[1] + = change_address (operands[1], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_call_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (CALL, VOIDmode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_untyped_call (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[0], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[0], 0) = force_reg (Pmode, addr); + + operands[1] = change_address (operands[1], DImode, XEXP (operands[1], 0)); + if (! expander_call_insn_operand (operands[1], QImode)) + operands[1] + = change_address (operands[1], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_call_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (3, + gen_rtx (CALL, VOIDmode, operand0, const0_rtx), + operand1, + operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_untyped_return (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + rtx valreg1 = gen_rtx (REG, SImode, 0); + rtx valreg2 = gen_rtx (REG, SImode, 1); + rtx result = operands[0]; + + /* Restore the FPU state. */ + emit_insn (gen_update_return (change_address (result, SImode, + plus_constant (XEXP (result, 0), + 8)))); + + /* Reload the function value registers. */ + emit_move_insn (valreg1, change_address (result, SImode, XEXP (result, 0))); + emit_move_insn (valreg2, + change_address (result, SImode, + plus_constant (XEXP (result, 0), 4))); + + /* Put USE insns before the return. */ + emit_insn (gen_rtx (USE, VOIDmode, valreg1)); + emit_insn (gen_rtx (USE, VOIDmode, valreg2)); + + /* Construct the return. */ + expand_null_return (); + + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand0); + emit (operand1); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_update_return (operand0) + rtx operand0; +{ + return gen_rtx (UNSPEC, SImode, gen_rtvec (1, + operand0), 0); +} + +rtx +gen_return () +{ + return gen_rtx (RETURN, VOIDmode); +} + +rtx +gen_nop () +{ + return const0_rtx; +} + +rtx +gen_movstrsi (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + rtx operand4; + rtx operand5; + rtx operand6; + rtx operands[7]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + +{ + rtx addr0, addr1; + + if (GET_CODE (operands[2]) != CONST_INT) + FAIL; + + addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); + addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); + + operands[5] = addr0; + operands[6] = addr1; + + operands[0] = gen_rtx (MEM, BLKmode, addr0); + operands[1] = gen_rtx (MEM, BLKmode, addr1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + operand6 = operands[6]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (6, + gen_rtx (SET, VOIDmode, operand0, operand1), + gen_rtx (USE, VOIDmode, operand2), + gen_rtx (USE, VOIDmode, operand3), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)), + gen_rtx (CLOBBER, VOIDmode, operand5), + gen_rtx (CLOBBER, VOIDmode, operand6)))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpstrsi (operand0, operand1, operand2, operand3, operand4) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; + rtx operand4; +{ + rtx operand5; + rtx operand6; + rtx operands[7]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + operands[4] = operand4; + +{ + rtx addr1, addr2; + + addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); + addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0)); + operands[3] = copy_to_mode_reg (SImode, operands[3]); + + operands[5] = addr1; + operands[6] = addr2; + + operands[1] = gen_rtx (MEM, BLKmode, addr1); + operands[2] = gen_rtx (MEM, BLKmode, addr2); + +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + operand6 = operands[6]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (6, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (COMPARE, SImode, operand1, operand2)), + gen_rtx (USE, VOIDmode, operand3), + gen_rtx (USE, VOIDmode, operand4), + gen_rtx (CLOBBER, VOIDmode, operand5), + gen_rtx (CLOBBER, VOIDmode, operand6), + gen_rtx (CLOBBER, VOIDmode, operand3)))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ffssi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; +operands[3] = gen_reg_rtx (SImode); + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand3, gen_rtx (PLUS, SImode, gen_rtx (FFS, SImode, operand1), constm1_rtx)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SImode, operand3, const1_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ffshi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; +operands[3] = gen_reg_rtx (HImode); + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand3, gen_rtx (PLUS, HImode, gen_rtx (FFS, HImode, operand1), constm1_rtx)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0))))); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, HImode, operand3, const1_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_strlensi (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + rtx operand4; + rtx operand5; + rtx operands[6]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + +{ + operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); + operands[4] = gen_reg_rtx (SImode); + operands[5] = gen_reg_rtx (SImode); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand4, gen_rtx (UNSPEC, SImode, gen_rtvec (3, + gen_rtx (MEM, BLKmode, operand1), + operand2, + operand3), 0)), + gen_rtx (CLOBBER, VOIDmode, operand1)))); + emit_insn (gen_rtx (SET, VOIDmode, operand5, gen_rtx (NOT, SImode, operand4))); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, SImode, operand5, const1_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + + + +void +add_clobbers (pattern, insn_code_number) + rtx pattern; + int insn_code_number; +{ + int i; + + switch (insn_code_number) + { + case 250: + case 223: + XVECEXP (pattern, 0, 1) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)); + break; + + case 72: + case 71: + XVECEXP (pattern, 0, 3) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)); + break; + + case 68: + case 67: + XVECEXP (pattern, 0, 4) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)); + break; + + case 252: + case 25: + case 24: + case 23: + case 22: + case 21: + case 20: + case 19: + case 18: + case 17: + case 16: + case 8: + case 6: + XVECEXP (pattern, 0, 1) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)); + break; + + default: + abort (); + } +} + +void +init_mov_optab () +{ +#ifdef HAVE_movccfpeq + if (HAVE_movccfpeq) + mov_optab->handlers[(int) CCFPEQmode].insn_code = CODE_FOR_movccfpeq; +#endif +} diff --git a/gnu/usr.bin/cc/lib/insn-extract.c b/gnu/usr.bin/cc/lib/insn-extract.c new file mode 100644 index 000000000000..f645b830af87 --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-extract.c @@ -0,0 +1,505 @@ +/* Generated automatically by the program `genextract' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" + +static rtx junk; +extern rtx recog_operand[]; +extern rtx *recog_operand_loc[]; +extern rtx *recog_dup_loc[]; +extern char recog_dup_num[]; +extern +#ifdef __GNUC__ +__volatile__ +#endif +void fatal_insn_not_found (); + +void +insn_extract (insn) + rtx insn; +{ + register rtx *ro = recog_operand; + register rtx **ro_loc = recog_operand_loc; + rtx pat = PATTERN (insn); + switch (INSN_CODE (insn)) + { + case -1: + fatal_insn_not_found (insn); + + case 262: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0, 0), 0)); + ro[2] = *(ro_loc[2] = &XVECEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0, 1)); + ro[3] = *(ro_loc[3] = &XVECEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0, 2)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 1; + break; + + case 260: + case 257: + case 256: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (pat, 1)); + break; + + case 259: + case 255: + case 254: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (pat, 1)); + break; + + case 258: + case 253: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (pat, 1)); + break; + + case 252: + case 250: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 248: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 2), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 5), 0); + recog_dup_num[0] = 2; + recog_dup_loc[1] = &XEXP (XVECEXP (pat, 0, 4), 0); + recog_dup_num[1] = 1; + recog_dup_loc[2] = &XEXP (XVECEXP (pat, 0, 3), 0); + recog_dup_num[2] = 0; + break; + + case 247: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + ro[4] = *(ro_loc[4] = &XEXP (XVECEXP (pat, 0, 2), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 5), 0); + recog_dup_num[0] = 3; + recog_dup_loc[1] = &XEXP (XVECEXP (pat, 0, 4), 0); + recog_dup_num[1] = 2; + recog_dup_loc[2] = &XEXP (XVECEXP (pat, 0, 3), 0); + recog_dup_num[2] = 1; + break; + + case 245: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 2), 0)); + ro[4] = *(ro_loc[4] = &XEXP (XVECEXP (pat, 0, 3), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 5), 0); + recog_dup_num[0] = 1; + recog_dup_loc[1] = &XEXP (XVECEXP (pat, 0, 4), 0); + recog_dup_num[1] = 0; + break; + + case 243: + case 242: + break; + + case 241: + ro[0] = *(ro_loc[0] = &XVECEXP (pat, 0, 0)); + break; + + case 239: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)); + ro[1] = *(ro_loc[1] = &XVECEXP (pat, 0, 1)); + ro[2] = *(ro_loc[2] = &XVECEXP (pat, 0, 2)); + break; + + case 238: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XVECEXP (pat, 0, 1)); + ro[2] = *(ro_loc[2] = &XVECEXP (pat, 0, 2)); + break; + + case 236: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 233: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[3] = const0_rtx; + ro_loc[3] = &junk; + ro[4] = *(ro_loc[4] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1)); + break; + + case 232: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[3] = const0_rtx; + ro_loc[3] = &junk; + ro[4] = *(ro_loc[4] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1)); + break; + + case 227: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[2] = const0_rtx; + ro_loc[2] = &junk; + ro[3] = *(ro_loc[3] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1)); + break; + + case 226: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[2] = const0_rtx; + ro_loc[2] = &junk; + ro[3] = *(ro_loc[3] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1)); + break; + + case 224: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0)); + break; + + case 223: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 220: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + break; + + case 219: + case 218: + case 217: + case 216: + case 215: + case 214: + case 213: + case 212: + case 211: + case 210: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 2), 0)); + break; + + case 209: + case 207: + case 205: + case 203: + case 201: + case 199: + case 197: + case 195: + case 193: + case 191: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + break; + + case 189: + case 187: + case 185: + case 183: + case 181: + case 179: + case 177: + case 175: + case 173: + case 171: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + break; + + case 169: + case 168: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 2)); + break; + + case 167: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 2)); + break; + + case 166: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 1)); + break; + + case 165: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 164: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = const0_rtx; + ro_loc[1] = &junk; + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 0), 2)); + ro[3] = *(ro_loc[3] = &XEXP (pat, 1)); + break; + + case 154: + case 148: + case 142: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 2; + break; + + case 136: + case 133: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (XEXP (pat, 1), 0, 0), 0)); + break; + + case 135: + case 134: + case 132: + case 131: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XVECEXP (XEXP (pat, 1), 0, 0)); + break; + + case 130: + case 127: + case 124: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + break; + + case 108: + case 107: + case 106: + case 105: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + recog_dup_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0); + recog_dup_num[0] = 1; + recog_dup_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1); + recog_dup_num[1] = 2; + break; + + case 98: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + break; + + case 235: + case 163: + case 162: + case 161: + case 160: + case 159: + case 158: + case 157: + case 156: + case 155: + case 153: + case 151: + case 150: + case 149: + case 147: + case 145: + case 144: + case 143: + case 141: + case 117: + case 116: + case 115: + case 114: + case 113: + case 112: + case 111: + case 110: + case 109: + case 102: + case 101: + case 97: + case 96: + case 95: + case 94: + case 91: + case 90: + case 89: + case 88: + case 84: + case 83: + case 82: + case 81: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 72: + case 71: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 2), 0)); + ro[4] = *(ro_loc[4] = &XEXP (XVECEXP (pat, 0, 3), 0)); + break; + + case 68: + case 67: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 2), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 3), 0)); + ro[4] = *(ro_loc[4] = &XEXP (XVECEXP (pat, 0, 4), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 1; + break; + + case 62: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 139: + case 138: + case 137: + case 129: + case 128: + case 126: + case 125: + case 123: + case 122: + case 121: + case 120: + case 119: + case 118: + case 80: + case 79: + case 78: + case 77: + case 60: + case 59: + case 58: + case 57: + case 56: + case 55: + case 54: + case 53: + case 52: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + break; + + case 48: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 0), 1)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 1; + recog_dup_loc[1] = &XEXP (XVECEXP (pat, 0, 1), 1); + recog_dup_num[1] = 0; + break; + + case 230: + case 44: + case 41: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (pat, 1)); + break; + + case 229: + case 85: + case 51: + case 50: + case 49: + case 47: + case 46: + case 45: + case 43: + case 42: + case 40: + case 39: + case 38: + case 36: + case 35: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (pat, 1)); + break; + + case 25: + case 21: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 24: + case 20: + case 18: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 23: + case 19: + case 17: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 22: + case 16: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 34: + case 33: + case 32: + case 14: + case 12: + case 10: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 8: + case 6: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 221: + case 4: + case 2: + case 0: + ro[0] = *(ro_loc[0] = &XEXP (pat, 1)); + break; + + default: + abort (); + } +} diff --git a/gnu/usr.bin/cc/lib/insn-flags.h b/gnu/usr.bin/cc/lib/insn-flags.h new file mode 100644 index 000000000000..4ffa0df4757e --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-flags.h @@ -0,0 +1,522 @@ +/* Generated automatically by the program `genflags' +from the machine description file `md'. */ + +#define HAVE_tstsi_1 1 +#define HAVE_tstsi 1 +#define HAVE_tsthi_1 1 +#define HAVE_tsthi 1 +#define HAVE_tstqi_1 1 +#define HAVE_tstqi 1 +#define HAVE_tstsf_cc (TARGET_80387 && ! TARGET_IEEE_FP) +#define HAVE_tstsf (TARGET_80387 && ! TARGET_IEEE_FP) +#define HAVE_tstdf_cc (TARGET_80387 && ! TARGET_IEEE_FP) +#define HAVE_tstdf (TARGET_80387 && ! TARGET_IEEE_FP) +#define HAVE_cmpsi_1 (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) +#define HAVE_cmpsi 1 +#define HAVE_cmphi_1 (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) +#define HAVE_cmphi 1 +#define HAVE_cmpqi_1 (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) +#define HAVE_cmpqi 1 +#define HAVE_cmpsf_cc_1 (TARGET_80387 \ + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)) +#define HAVE_cmpdf (TARGET_80387) +#define HAVE_cmpsf (TARGET_80387) +#define HAVE_cmpdf_cc (TARGET_80387) +#define HAVE_cmpdf_ccfpeq (TARGET_80387) +#define HAVE_cmpsf_cc (TARGET_80387) +#define HAVE_cmpsf_ccfpeq (TARGET_80387) +#define HAVE_movsi 1 +#define HAVE_movhi 1 +#define HAVE_movstricthi 1 +#define HAVE_movqi 1 +#define HAVE_movstrictqi 1 +#define HAVE_movsf 1 +#define HAVE_swapdf 1 +#define HAVE_movdf 1 +#define HAVE_movdi 1 +#define HAVE_zero_extendhisi2 1 +#define HAVE_zero_extendqihi2 1 +#define HAVE_zero_extendqisi2 1 +#define HAVE_zero_extendsidi2 1 +#define HAVE_extendsidi2 1 +#define HAVE_extendhisi2 1 +#define HAVE_extendqihi2 1 +#define HAVE_extendqisi2 1 +#define HAVE_extendsfdf2 (TARGET_80387) +#define HAVE_truncdfsf2 (TARGET_80387) +#define HAVE_fixuns_truncdfsi2 (TARGET_80387) +#define HAVE_fixuns_truncsfsi2 (TARGET_80387) +#define HAVE_fix_truncdfdi2 (TARGET_80387) +#define HAVE_fix_truncsfdi2 (TARGET_80387) +#define HAVE_fix_truncdfsi2 (TARGET_80387) +#define HAVE_fix_truncsfsi2 (TARGET_80387) +#define HAVE_floatsisf2 (TARGET_80387) +#define HAVE_floatdisf2 (TARGET_80387) +#define HAVE_floatsidf2 (TARGET_80387) +#define HAVE_floatdidf2 (TARGET_80387) +#define HAVE_adddi3 1 +#define HAVE_addsi3 1 +#define HAVE_addhi3 1 +#define HAVE_addqi3 1 +#define HAVE_adddf3 (TARGET_80387) +#define HAVE_addsf3 (TARGET_80387) +#define HAVE_subdi3 1 +#define HAVE_subsi3 1 +#define HAVE_subhi3 1 +#define HAVE_subqi3 1 +#define HAVE_subdf3 (TARGET_80387) +#define HAVE_subsf3 (TARGET_80387) +#define HAVE_mulhi3 1 +#define HAVE_mulsi3 1 +#define HAVE_muldf3 (TARGET_80387) +#define HAVE_mulsf3 (TARGET_80387) +#define HAVE_divqi3 1 +#define HAVE_udivqi3 1 +#define HAVE_divdf3 (TARGET_80387) +#define HAVE_divsf3 (TARGET_80387) +#define HAVE_divmodsi4 1 +#define HAVE_divmodhi4 1 +#define HAVE_udivmodsi4 1 +#define HAVE_udivmodhi4 1 +#define HAVE_andsi3 1 +#define HAVE_andhi3 1 +#define HAVE_andqi3 1 +#define HAVE_iorsi3 1 +#define HAVE_iorhi3 1 +#define HAVE_iorqi3 1 +#define HAVE_xorsi3 1 +#define HAVE_xorhi3 1 +#define HAVE_xorqi3 1 +#define HAVE_negdi2 1 +#define HAVE_negsi2 1 +#define HAVE_neghi2 1 +#define HAVE_negqi2 1 +#define HAVE_negsf2 (TARGET_80387) +#define HAVE_negdf2 (TARGET_80387) +#define HAVE_abssf2 (TARGET_80387) +#define HAVE_absdf2 (TARGET_80387) +/* XXX missing emulator instructions. + Use NOFPU to prevent them being generated on non-fpu machines. +*/ +#ifdef NOFPU +#define HAVE_sqrtdf2 0 +#define HAVE_sqrtsf2 0 +#define HAVE_sindf2 0 +#define HAVE_sinsf2 0 +#define HAVE_cosdf2 0 +#define HAVE_cossf2 0 +#else /* Have a fpu */ +#define HAVE_sqrtdf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_sqrtsf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_sindf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_sinsf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_cosdf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_cossf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#endif +#define HAVE_one_cmplsi2 1 +#define HAVE_one_cmplhi2 1 +#define HAVE_one_cmplqi2 1 +#define HAVE_ashldi3 1 +#define HAVE_ashldi3_const_int 1 +#define HAVE_ashldi3_non_const_int 1 +#define HAVE_ashlsi3 1 +#define HAVE_ashlhi3 1 +#define HAVE_ashlqi3 1 +#define HAVE_ashrdi3 1 +#define HAVE_ashrdi3_const_int 1 +#define HAVE_ashrdi3_non_const_int 1 +#define HAVE_ashrsi3 1 +#define HAVE_ashrhi3 1 +#define HAVE_ashrqi3 1 +#define HAVE_lshrdi3 1 +#define HAVE_lshrdi3_const_int 1 +#define HAVE_lshrdi3_non_const_int 1 +#define HAVE_lshrsi3 1 +#define HAVE_lshrhi3 1 +#define HAVE_lshrqi3 1 +#define HAVE_rotlsi3 1 +#define HAVE_rotlhi3 1 +#define HAVE_rotlqi3 1 +#define HAVE_rotrsi3 1 +#define HAVE_rotrhi3 1 +#define HAVE_rotrqi3 1 +#define HAVE_seq 1 +#define HAVE_sne 1 +#define HAVE_sgt 1 +#define HAVE_sgtu 1 +#define HAVE_slt 1 +#define HAVE_sltu 1 +#define HAVE_sge 1 +#define HAVE_sgeu 1 +#define HAVE_sle 1 +#define HAVE_sleu 1 +#define HAVE_beq 1 +#define HAVE_bne 1 +#define HAVE_bgt 1 +#define HAVE_bgtu 1 +#define HAVE_blt 1 +#define HAVE_bltu 1 +#define HAVE_bge 1 +#define HAVE_bgeu 1 +#define HAVE_ble 1 +#define HAVE_bleu 1 +#define HAVE_jump 1 +#define HAVE_indirect_jump 1 +#define HAVE_casesi (flag_pic) +#define HAVE_tablejump 1 +#define HAVE_call_pop 1 +#define HAVE_call 1 +#define HAVE_call_value_pop 1 +#define HAVE_call_value 1 +#define HAVE_untyped_call 1 +#define HAVE_untyped_return 1 +#define HAVE_update_return 1 +#define HAVE_return (simple_386_epilogue ()) +#define HAVE_nop 1 +#define HAVE_movstrsi 1 +#define HAVE_cmpstrsi 1 +#define HAVE_ffssi2 1 +#define HAVE_ffshi2 1 +#define HAVE_strlensi 1 + +#ifndef NO_MD_PROTOTYPES +extern rtx gen_tstsi_1 PROTO((rtx)); +extern rtx gen_tstsi PROTO((rtx)); +extern rtx gen_tsthi_1 PROTO((rtx)); +extern rtx gen_tsthi PROTO((rtx)); +extern rtx gen_tstqi_1 PROTO((rtx)); +extern rtx gen_tstqi PROTO((rtx)); +extern rtx gen_tstsf_cc PROTO((rtx)); +extern rtx gen_tstsf PROTO((rtx)); +extern rtx gen_tstdf_cc PROTO((rtx)); +extern rtx gen_tstdf PROTO((rtx)); +extern rtx gen_cmpsi_1 PROTO((rtx, rtx)); +extern rtx gen_cmpsi PROTO((rtx, rtx)); +extern rtx gen_cmphi_1 PROTO((rtx, rtx)); +extern rtx gen_cmphi PROTO((rtx, rtx)); +extern rtx gen_cmpqi_1 PROTO((rtx, rtx)); +extern rtx gen_cmpqi PROTO((rtx, rtx)); +extern rtx gen_cmpsf_cc_1 PROTO((rtx, rtx, rtx)); +extern rtx gen_cmpdf PROTO((rtx, rtx)); +extern rtx gen_cmpsf PROTO((rtx, rtx)); +extern rtx gen_cmpdf_cc PROTO((rtx, rtx)); +extern rtx gen_cmpdf_ccfpeq PROTO((rtx, rtx)); +extern rtx gen_cmpsf_cc PROTO((rtx, rtx)); +extern rtx gen_cmpsf_ccfpeq PROTO((rtx, rtx)); +extern rtx gen_movsi PROTO((rtx, rtx)); +extern rtx gen_movhi PROTO((rtx, rtx)); +extern rtx gen_movstricthi PROTO((rtx, rtx)); +extern rtx gen_movqi PROTO((rtx, rtx)); +extern rtx gen_movstrictqi PROTO((rtx, rtx)); +extern rtx gen_movsf PROTO((rtx, rtx)); +extern rtx gen_swapdf PROTO((rtx, rtx)); +extern rtx gen_movdf PROTO((rtx, rtx)); +extern rtx gen_movdi PROTO((rtx, rtx)); +extern rtx gen_zero_extendhisi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendqihi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendqisi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendsidi2 PROTO((rtx, rtx)); +extern rtx gen_extendsidi2 PROTO((rtx, rtx)); +extern rtx gen_extendhisi2 PROTO((rtx, rtx)); +extern rtx gen_extendqihi2 PROTO((rtx, rtx)); +extern rtx gen_extendqisi2 PROTO((rtx, rtx)); +extern rtx gen_extendsfdf2 PROTO((rtx, rtx)); +extern rtx gen_truncdfsf2 PROTO((rtx, rtx)); +extern rtx gen_fixuns_truncdfsi2 PROTO((rtx, rtx)); +extern rtx gen_fixuns_truncsfsi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncdfdi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncsfdi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncdfsi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncsfsi2 PROTO((rtx, rtx)); +extern rtx gen_floatsisf2 PROTO((rtx, rtx)); +extern rtx gen_floatdisf2 PROTO((rtx, rtx)); +extern rtx gen_floatsidf2 PROTO((rtx, rtx)); +extern rtx gen_floatdidf2 PROTO((rtx, rtx)); +extern rtx gen_adddi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_adddf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subdi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subdf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_muldf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_udivqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divdf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divmodsi4 PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_divmodhi4 PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_udivmodsi4 PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_udivmodhi4 PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_andsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_andhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_andqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_negdi2 PROTO((rtx, rtx)); +extern rtx gen_negsi2 PROTO((rtx, rtx)); +extern rtx gen_neghi2 PROTO((rtx, rtx)); +extern rtx gen_negqi2 PROTO((rtx, rtx)); +extern rtx gen_negsf2 PROTO((rtx, rtx)); +extern rtx gen_negdf2 PROTO((rtx, rtx)); +extern rtx gen_abssf2 PROTO((rtx, rtx)); +extern rtx gen_absdf2 PROTO((rtx, rtx)); +extern rtx gen_sqrtsf2 PROTO((rtx, rtx)); +extern rtx gen_sqrtdf2 PROTO((rtx, rtx)); +extern rtx gen_sindf2 PROTO((rtx, rtx)); +extern rtx gen_sinsf2 PROTO((rtx, rtx)); +extern rtx gen_cosdf2 PROTO((rtx, rtx)); +extern rtx gen_cossf2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplsi2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplhi2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplqi2 PROTO((rtx, rtx)); +extern rtx gen_ashldi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashldi3_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_ashldi3_non_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_ashlsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashlhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashlqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrdi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrdi3_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrdi3_non_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrdi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrdi3_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrdi3_non_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_seq PROTO((rtx)); +extern rtx gen_sne PROTO((rtx)); +extern rtx gen_sgt PROTO((rtx)); +extern rtx gen_sgtu PROTO((rtx)); +extern rtx gen_slt PROTO((rtx)); +extern rtx gen_sltu PROTO((rtx)); +extern rtx gen_sge PROTO((rtx)); +extern rtx gen_sgeu PROTO((rtx)); +extern rtx gen_sle PROTO((rtx)); +extern rtx gen_sleu PROTO((rtx)); +extern rtx gen_beq PROTO((rtx)); +extern rtx gen_bne PROTO((rtx)); +extern rtx gen_bgt PROTO((rtx)); +extern rtx gen_bgtu PROTO((rtx)); +extern rtx gen_blt PROTO((rtx)); +extern rtx gen_bltu PROTO((rtx)); +extern rtx gen_bge PROTO((rtx)); +extern rtx gen_bgeu PROTO((rtx)); +extern rtx gen_ble PROTO((rtx)); +extern rtx gen_bleu PROTO((rtx)); +extern rtx gen_jump PROTO((rtx)); +extern rtx gen_indirect_jump PROTO((rtx)); +extern rtx gen_casesi PROTO((rtx, rtx, rtx, rtx, rtx)); +extern rtx gen_tablejump PROTO((rtx, rtx)); +extern rtx gen_untyped_call PROTO((rtx, rtx, rtx)); +extern rtx gen_untyped_return PROTO((rtx, rtx)); +extern rtx gen_update_return PROTO((rtx)); +extern rtx gen_return PROTO((void)); +extern rtx gen_nop PROTO((void)); +extern rtx gen_movstrsi PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_cmpstrsi PROTO((rtx, rtx, rtx, rtx, rtx)); +extern rtx gen_ffssi2 PROTO((rtx, rtx)); +extern rtx gen_ffshi2 PROTO((rtx, rtx)); +extern rtx gen_strlensi PROTO((rtx, rtx, rtx, rtx)); + +#ifdef MD_CALL_PROTOTYPES +extern rtx gen_call_pop PROTO((rtx, rtx, rtx)); +extern rtx gen_call PROTO((rtx, rtx)); +extern rtx gen_call_value_pop PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_call_value PROTO((rtx, rtx, rtx)); + +#else /* !MD_CALL_PROTOTYPES */ +extern rtx gen_call_pop (); +extern rtx gen_call (); +extern rtx gen_call_value_pop (); +extern rtx gen_call_value (); +#endif /* !MD_CALL_PROTOTYPES */ + +#else /* NO_MD_PROTOTYPES */ +extern rtx gen_tstsi_1 (); +extern rtx gen_tstsi (); +extern rtx gen_tsthi_1 (); +extern rtx gen_tsthi (); +extern rtx gen_tstqi_1 (); +extern rtx gen_tstqi (); +extern rtx gen_tstsf_cc (); +extern rtx gen_tstsf (); +extern rtx gen_tstdf_cc (); +extern rtx gen_tstdf (); +extern rtx gen_cmpsi_1 (); +extern rtx gen_cmpsi (); +extern rtx gen_cmphi_1 (); +extern rtx gen_cmphi (); +extern rtx gen_cmpqi_1 (); +extern rtx gen_cmpqi (); +extern rtx gen_cmpsf_cc_1 (); +extern rtx gen_cmpdf (); +extern rtx gen_cmpsf (); +extern rtx gen_cmpdf_cc (); +extern rtx gen_cmpdf_ccfpeq (); +extern rtx gen_cmpsf_cc (); +extern rtx gen_cmpsf_ccfpeq (); +extern rtx gen_movsi (); +extern rtx gen_movhi (); +extern rtx gen_movstricthi (); +extern rtx gen_movqi (); +extern rtx gen_movstrictqi (); +extern rtx gen_movsf (); +extern rtx gen_swapdf (); +extern rtx gen_movdf (); +extern rtx gen_movdi (); +extern rtx gen_zero_extendhisi2 (); +extern rtx gen_zero_extendqihi2 (); +extern rtx gen_zero_extendqisi2 (); +extern rtx gen_zero_extendsidi2 (); +extern rtx gen_extendsidi2 (); +extern rtx gen_extendhisi2 (); +extern rtx gen_extendqihi2 (); +extern rtx gen_extendqisi2 (); +extern rtx gen_extendsfdf2 (); +extern rtx gen_truncdfsf2 (); +extern rtx gen_fixuns_truncdfsi2 (); +extern rtx gen_fixuns_truncsfsi2 (); +extern rtx gen_fix_truncdfdi2 (); +extern rtx gen_fix_truncsfdi2 (); +extern rtx gen_fix_truncdfsi2 (); +extern rtx gen_fix_truncsfsi2 (); +extern rtx gen_floatsisf2 (); +extern rtx gen_floatdisf2 (); +extern rtx gen_floatsidf2 (); +extern rtx gen_floatdidf2 (); +extern rtx gen_adddi3 (); +extern rtx gen_addsi3 (); +extern rtx gen_addhi3 (); +extern rtx gen_addqi3 (); +extern rtx gen_adddf3 (); +extern rtx gen_addsf3 (); +extern rtx gen_subdi3 (); +extern rtx gen_subsi3 (); +extern rtx gen_subhi3 (); +extern rtx gen_subqi3 (); +extern rtx gen_subdf3 (); +extern rtx gen_subsf3 (); +extern rtx gen_mulhi3 (); +extern rtx gen_mulsi3 (); +extern rtx gen_muldf3 (); +extern rtx gen_mulsf3 (); +extern rtx gen_divqi3 (); +extern rtx gen_udivqi3 (); +extern rtx gen_divdf3 (); +extern rtx gen_divsf3 (); +extern rtx gen_divmodsi4 (); +extern rtx gen_divmodhi4 (); +extern rtx gen_udivmodsi4 (); +extern rtx gen_udivmodhi4 (); +extern rtx gen_andsi3 (); +extern rtx gen_andhi3 (); +extern rtx gen_andqi3 (); +extern rtx gen_iorsi3 (); +extern rtx gen_iorhi3 (); +extern rtx gen_iorqi3 (); +extern rtx gen_xorsi3 (); +extern rtx gen_xorhi3 (); +extern rtx gen_xorqi3 (); +extern rtx gen_negdi2 (); +extern rtx gen_negsi2 (); +extern rtx gen_neghi2 (); +extern rtx gen_negqi2 (); +extern rtx gen_negsf2 (); +extern rtx gen_negdf2 (); +extern rtx gen_abssf2 (); +extern rtx gen_absdf2 (); +extern rtx gen_sqrtsf2 (); +extern rtx gen_sqrtdf2 (); +extern rtx gen_sindf2 (); +extern rtx gen_sinsf2 (); +extern rtx gen_cosdf2 (); +extern rtx gen_cossf2 (); +extern rtx gen_one_cmplsi2 (); +extern rtx gen_one_cmplhi2 (); +extern rtx gen_one_cmplqi2 (); +extern rtx gen_ashldi3 (); +extern rtx gen_ashldi3_const_int (); +extern rtx gen_ashldi3_non_const_int (); +extern rtx gen_ashlsi3 (); +extern rtx gen_ashlhi3 (); +extern rtx gen_ashlqi3 (); +extern rtx gen_ashrdi3 (); +extern rtx gen_ashrdi3_const_int (); +extern rtx gen_ashrdi3_non_const_int (); +extern rtx gen_ashrsi3 (); +extern rtx gen_ashrhi3 (); +extern rtx gen_ashrqi3 (); +extern rtx gen_lshrdi3 (); +extern rtx gen_lshrdi3_const_int (); +extern rtx gen_lshrdi3_non_const_int (); +extern rtx gen_lshrsi3 (); +extern rtx gen_lshrhi3 (); +extern rtx gen_lshrqi3 (); +extern rtx gen_rotlsi3 (); +extern rtx gen_rotlhi3 (); +extern rtx gen_rotlqi3 (); +extern rtx gen_rotrsi3 (); +extern rtx gen_rotrhi3 (); +extern rtx gen_rotrqi3 (); +extern rtx gen_seq (); +extern rtx gen_sne (); +extern rtx gen_sgt (); +extern rtx gen_sgtu (); +extern rtx gen_slt (); +extern rtx gen_sltu (); +extern rtx gen_sge (); +extern rtx gen_sgeu (); +extern rtx gen_sle (); +extern rtx gen_sleu (); +extern rtx gen_beq (); +extern rtx gen_bne (); +extern rtx gen_bgt (); +extern rtx gen_bgtu (); +extern rtx gen_blt (); +extern rtx gen_bltu (); +extern rtx gen_bge (); +extern rtx gen_bgeu (); +extern rtx gen_ble (); +extern rtx gen_bleu (); +extern rtx gen_jump (); +extern rtx gen_indirect_jump (); +extern rtx gen_casesi (); +extern rtx gen_tablejump (); +extern rtx gen_untyped_call (); +extern rtx gen_untyped_return (); +extern rtx gen_update_return (); +extern rtx gen_return (); +extern rtx gen_nop (); +extern rtx gen_movstrsi (); +extern rtx gen_cmpstrsi (); +extern rtx gen_ffssi2 (); +extern rtx gen_ffshi2 (); +extern rtx gen_strlensi (); +extern rtx gen_call_pop (); +extern rtx gen_call (); +extern rtx gen_call_value_pop (); +extern rtx gen_call_value (); +#endif /* NO_MD_PROTOTYPES */ diff --git a/gnu/usr.bin/cc/lib/insn-opinit.c b/gnu/usr.bin/cc/lib/insn-opinit.c new file mode 100644 index 000000000000..7959ae5fb1c9 --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-opinit.c @@ -0,0 +1,179 @@ +/* Generated automatically by the program `genopinit' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "flags.h" +#include "insn-flags.h" +#include "insn-codes.h" +#include "insn-config.h" +#include "recog.h" +#include "expr.h" +#include "reload.h" + +void +init_all_optabs () +{ + tst_optab->handlers[(int) SImode].insn_code = CODE_FOR_tstsi; + tst_optab->handlers[(int) HImode].insn_code = CODE_FOR_tsthi; + tst_optab->handlers[(int) QImode].insn_code = CODE_FOR_tstqi; + if (HAVE_tstsf) + tst_optab->handlers[(int) SFmode].insn_code = CODE_FOR_tstsf; + if (HAVE_tstdf) + tst_optab->handlers[(int) DFmode].insn_code = CODE_FOR_tstdf; + cmp_optab->handlers[(int) SImode].insn_code = CODE_FOR_cmpsi; + cmp_optab->handlers[(int) HImode].insn_code = CODE_FOR_cmphi; + cmp_optab->handlers[(int) QImode].insn_code = CODE_FOR_cmpqi; + if (HAVE_cmpdf) + cmp_optab->handlers[(int) DFmode].insn_code = CODE_FOR_cmpdf; + if (HAVE_cmpsf) + cmp_optab->handlers[(int) SFmode].insn_code = CODE_FOR_cmpsf; + mov_optab->handlers[(int) SImode].insn_code = CODE_FOR_movsi; + mov_optab->handlers[(int) HImode].insn_code = CODE_FOR_movhi; + movstrict_optab->handlers[(int) HImode].insn_code = CODE_FOR_movstricthi; + mov_optab->handlers[(int) QImode].insn_code = CODE_FOR_movqi; + movstrict_optab->handlers[(int) QImode].insn_code = CODE_FOR_movstrictqi; + mov_optab->handlers[(int) SFmode].insn_code = CODE_FOR_movsf; + mov_optab->handlers[(int) DFmode].insn_code = CODE_FOR_movdf; + mov_optab->handlers[(int) DImode].insn_code = CODE_FOR_movdi; + extendtab[(int) SImode][(int) HImode][1] = CODE_FOR_zero_extendhisi2; + extendtab[(int) HImode][(int) QImode][1] = CODE_FOR_zero_extendqihi2; + extendtab[(int) SImode][(int) QImode][1] = CODE_FOR_zero_extendqisi2; + extendtab[(int) DImode][(int) SImode][1] = CODE_FOR_zero_extendsidi2; + extendtab[(int) DImode][(int) SImode][0] = CODE_FOR_extendsidi2; + extendtab[(int) SImode][(int) HImode][0] = CODE_FOR_extendhisi2; + extendtab[(int) HImode][(int) QImode][0] = CODE_FOR_extendqihi2; + extendtab[(int) SImode][(int) QImode][0] = CODE_FOR_extendqisi2; + if (HAVE_extendsfdf2) + extendtab[(int) DFmode][(int) SFmode][0] = CODE_FOR_extendsfdf2; + if (HAVE_fixuns_truncdfsi2) + fixtrunctab[(int) DFmode][(int) SImode][1] = CODE_FOR_fixuns_truncdfsi2; + if (HAVE_fixuns_truncsfsi2) + fixtrunctab[(int) SFmode][(int) SImode][1] = CODE_FOR_fixuns_truncsfsi2; + if (HAVE_fix_truncdfdi2) + fixtrunctab[(int) DFmode][(int) DImode][0] = CODE_FOR_fix_truncdfdi2; + if (HAVE_fix_truncsfdi2) + fixtrunctab[(int) SFmode][(int) DImode][0] = CODE_FOR_fix_truncsfdi2; + if (HAVE_fix_truncdfsi2) + fixtrunctab[(int) DFmode][(int) SImode][0] = CODE_FOR_fix_truncdfsi2; + if (HAVE_fix_truncsfsi2) + fixtrunctab[(int) SFmode][(int) SImode][0] = CODE_FOR_fix_truncsfsi2; + if (HAVE_floatsisf2) + floattab[(int) SFmode][(int) SImode][0] = CODE_FOR_floatsisf2; + if (HAVE_floatdisf2) + floattab[(int) SFmode][(int) DImode][0] = CODE_FOR_floatdisf2; + if (HAVE_floatsidf2) + floattab[(int) DFmode][(int) SImode][0] = CODE_FOR_floatsidf2; + if (HAVE_floatdidf2) + floattab[(int) DFmode][(int) DImode][0] = CODE_FOR_floatdidf2; + add_optab->handlers[(int) DImode].insn_code = CODE_FOR_adddi3; + add_optab->handlers[(int) SImode].insn_code = CODE_FOR_addsi3; + add_optab->handlers[(int) HImode].insn_code = CODE_FOR_addhi3; + add_optab->handlers[(int) QImode].insn_code = CODE_FOR_addqi3; + if (HAVE_adddf3) + add_optab->handlers[(int) DFmode].insn_code = CODE_FOR_adddf3; + if (HAVE_addsf3) + add_optab->handlers[(int) SFmode].insn_code = CODE_FOR_addsf3; + sub_optab->handlers[(int) DImode].insn_code = CODE_FOR_subdi3; + sub_optab->handlers[(int) SImode].insn_code = CODE_FOR_subsi3; + sub_optab->handlers[(int) HImode].insn_code = CODE_FOR_subhi3; + sub_optab->handlers[(int) QImode].insn_code = CODE_FOR_subqi3; + if (HAVE_subdf3) + sub_optab->handlers[(int) DFmode].insn_code = CODE_FOR_subdf3; + if (HAVE_subsf3) + sub_optab->handlers[(int) SFmode].insn_code = CODE_FOR_subsf3; + smul_optab->handlers[(int) HImode].insn_code = CODE_FOR_mulhi3; + smul_optab->handlers[(int) SImode].insn_code = CODE_FOR_mulsi3; + if (HAVE_muldf3) + smul_optab->handlers[(int) DFmode].insn_code = CODE_FOR_muldf3; + if (HAVE_mulsf3) + smul_optab->handlers[(int) SFmode].insn_code = CODE_FOR_mulsf3; + sdiv_optab->handlers[(int) QImode].insn_code = CODE_FOR_divqi3; + udiv_optab->handlers[(int) QImode].insn_code = CODE_FOR_udivqi3; + if (HAVE_divdf3) + flodiv_optab->handlers[(int) DFmode].insn_code = CODE_FOR_divdf3; + if (HAVE_divsf3) + flodiv_optab->handlers[(int) SFmode].insn_code = CODE_FOR_divsf3; + sdivmod_optab->handlers[(int) SImode].insn_code = CODE_FOR_divmodsi4; + sdivmod_optab->handlers[(int) HImode].insn_code = CODE_FOR_divmodhi4; + udivmod_optab->handlers[(int) SImode].insn_code = CODE_FOR_udivmodsi4; + udivmod_optab->handlers[(int) HImode].insn_code = CODE_FOR_udivmodhi4; + and_optab->handlers[(int) SImode].insn_code = CODE_FOR_andsi3; + and_optab->handlers[(int) HImode].insn_code = CODE_FOR_andhi3; + and_optab->handlers[(int) QImode].insn_code = CODE_FOR_andqi3; + ior_optab->handlers[(int) SImode].insn_code = CODE_FOR_iorsi3; + ior_optab->handlers[(int) HImode].insn_code = CODE_FOR_iorhi3; + ior_optab->handlers[(int) QImode].insn_code = CODE_FOR_iorqi3; + xor_optab->handlers[(int) SImode].insn_code = CODE_FOR_xorsi3; + xor_optab->handlers[(int) HImode].insn_code = CODE_FOR_xorhi3; + xor_optab->handlers[(int) QImode].insn_code = CODE_FOR_xorqi3; + neg_optab->handlers[(int) DImode].insn_code = CODE_FOR_negdi2; + neg_optab->handlers[(int) SImode].insn_code = CODE_FOR_negsi2; + neg_optab->handlers[(int) HImode].insn_code = CODE_FOR_neghi2; + neg_optab->handlers[(int) QImode].insn_code = CODE_FOR_negqi2; + if (HAVE_negsf2) + neg_optab->handlers[(int) SFmode].insn_code = CODE_FOR_negsf2; + if (HAVE_negdf2) + neg_optab->handlers[(int) DFmode].insn_code = CODE_FOR_negdf2; + if (HAVE_abssf2) + abs_optab->handlers[(int) SFmode].insn_code = CODE_FOR_abssf2; + if (HAVE_absdf2) + abs_optab->handlers[(int) DFmode].insn_code = CODE_FOR_absdf2; + if (HAVE_sqrtsf2) + sqrt_optab->handlers[(int) SFmode].insn_code = CODE_FOR_sqrtsf2; + if (HAVE_sqrtdf2) + sqrt_optab->handlers[(int) DFmode].insn_code = CODE_FOR_sqrtdf2; + if (HAVE_sindf2) + sin_optab->handlers[(int) DFmode].insn_code = CODE_FOR_sindf2; + if (HAVE_sinsf2) + sin_optab->handlers[(int) SFmode].insn_code = CODE_FOR_sinsf2; + if (HAVE_cosdf2) + cos_optab->handlers[(int) DFmode].insn_code = CODE_FOR_cosdf2; + if (HAVE_cossf2) + cos_optab->handlers[(int) SFmode].insn_code = CODE_FOR_cossf2; + one_cmpl_optab->handlers[(int) SImode].insn_code = CODE_FOR_one_cmplsi2; + one_cmpl_optab->handlers[(int) HImode].insn_code = CODE_FOR_one_cmplhi2; + one_cmpl_optab->handlers[(int) QImode].insn_code = CODE_FOR_one_cmplqi2; + ashl_optab->handlers[(int) DImode].insn_code = CODE_FOR_ashldi3; + ashl_optab->handlers[(int) SImode].insn_code = CODE_FOR_ashlsi3; + ashl_optab->handlers[(int) HImode].insn_code = CODE_FOR_ashlhi3; + ashl_optab->handlers[(int) QImode].insn_code = CODE_FOR_ashlqi3; + ashr_optab->handlers[(int) DImode].insn_code = CODE_FOR_ashrdi3; + ashr_optab->handlers[(int) SImode].insn_code = CODE_FOR_ashrsi3; + ashr_optab->handlers[(int) HImode].insn_code = CODE_FOR_ashrhi3; + ashr_optab->handlers[(int) QImode].insn_code = CODE_FOR_ashrqi3; + lshr_optab->handlers[(int) DImode].insn_code = CODE_FOR_lshrdi3; + lshr_optab->handlers[(int) SImode].insn_code = CODE_FOR_lshrsi3; + lshr_optab->handlers[(int) HImode].insn_code = CODE_FOR_lshrhi3; + lshr_optab->handlers[(int) QImode].insn_code = CODE_FOR_lshrqi3; + rotl_optab->handlers[(int) SImode].insn_code = CODE_FOR_rotlsi3; + rotl_optab->handlers[(int) HImode].insn_code = CODE_FOR_rotlhi3; + rotl_optab->handlers[(int) QImode].insn_code = CODE_FOR_rotlqi3; + rotr_optab->handlers[(int) SImode].insn_code = CODE_FOR_rotrsi3; + rotr_optab->handlers[(int) HImode].insn_code = CODE_FOR_rotrhi3; + rotr_optab->handlers[(int) QImode].insn_code = CODE_FOR_rotrqi3; + setcc_gen_code[(int) EQ] = CODE_FOR_seq; + setcc_gen_code[(int) NE] = CODE_FOR_sne; + setcc_gen_code[(int) GT] = CODE_FOR_sgt; + setcc_gen_code[(int) GTU] = CODE_FOR_sgtu; + setcc_gen_code[(int) LT] = CODE_FOR_slt; + setcc_gen_code[(int) LTU] = CODE_FOR_sltu; + setcc_gen_code[(int) GE] = CODE_FOR_sge; + setcc_gen_code[(int) GEU] = CODE_FOR_sgeu; + setcc_gen_code[(int) LE] = CODE_FOR_sle; + setcc_gen_code[(int) LEU] = CODE_FOR_sleu; + bcc_gen_fctn[(int) EQ] = gen_beq; + bcc_gen_fctn[(int) NE] = gen_bne; + bcc_gen_fctn[(int) GT] = gen_bgt; + bcc_gen_fctn[(int) GTU] = gen_bgtu; + bcc_gen_fctn[(int) LT] = gen_blt; + bcc_gen_fctn[(int) LTU] = gen_bltu; + bcc_gen_fctn[(int) GE] = gen_bge; + bcc_gen_fctn[(int) GEU] = gen_bgeu; + bcc_gen_fctn[(int) LE] = gen_ble; + bcc_gen_fctn[(int) LEU] = gen_bleu; + movstr_optab[(int) SImode] = CODE_FOR_movstrsi; + ffs_optab->handlers[(int) SImode].insn_code = CODE_FOR_ffssi2; + ffs_optab->handlers[(int) HImode].insn_code = CODE_FOR_ffshi2; + strlen_optab->handlers[(int) SImode].insn_code = CODE_FOR_strlensi; +} diff --git a/gnu/usr.bin/cc/lib/insn-output.c b/gnu/usr.bin/cc/lib/insn-output.c new file mode 100644 index 000000000000..c39c4ffcc106 --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-output.c @@ -0,0 +1,5899 @@ +/* Generated automatically by the program `genoutput' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" + +#include "conditions.h" +#include "insn-flags.h" +#include "insn-attr.h" + +#include "insn-codes.h" + +#include "recog.h" + +#include +#include "output.h" + +static char * +output_0 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0])) + return AS2 (test%L0,%0,%0); + + operands[1] = const0_rtx; + return AS2 (cmp%L0,%1,%0); +} +} + +static char * +output_2 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0])) + return AS2 (test%W0,%0,%0); + + operands[1] = const0_rtx; + return AS2 (cmp%W0,%1,%0); +} +} + +static char * +output_4 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0])) + return AS2 (test%B0,%0,%0); + + operands[1] = const0_rtx; + return AS2 (cmp%B0,%1,%0); +} +} + +static char * +output_6 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (! STACK_TOP_P (operands[0])) + abort (); + + output_asm_insn ("ftst", operands); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp,%y0), operands); + + return (char *) output_fp_cc0_set (insn); +} +} + +static char * +output_8 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (! STACK_TOP_P (operands[0])) + abort (); + + output_asm_insn ("ftst", operands); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp,%y0), operands); + + return (char *) output_fp_cc0_set (insn); +} +} + +static char * +output_10 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) + { + cc_status.flags |= CC_REVERSED; + return AS2 (cmp%L0,%0,%1); + } + return AS2 (cmp%L0,%1,%0); +} +} + +static char * +output_12 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) + { + cc_status.flags |= CC_REVERSED; + return AS2 (cmp%W0,%0,%1); + } + return AS2 (cmp%W0,%1,%0); +} +} + +static char * +output_14 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) + { + cc_status.flags |= CC_REVERSED; + return AS2 (cmp%B0,%0,%1); + } + return AS2 (cmp%B0,%1,%0); +} +} + +static char * +output_16 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_17 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_18 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_19 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_20 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_21 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_22 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_23 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_24 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_25 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_32 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + /* For small integers, we may actually use testb. */ + if (GET_CODE (operands[1]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) + && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) + { + /* We may set the sign bit spuriously. */ + + if ((INTVAL (operands[1]) & ~0xff) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((INTVAL (operands[1]) & ~0xff00) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (INTVAL (operands[1]) >> 8); + + if (QI_REG_P (operands[0])) + return AS2 (test%B0,%1,%h0); + else + { + operands[0] = adj_offsettable_operand (operands[0], 1); + return AS2 (test%B0,%1,%b0); + } + } + + if (GET_CODE (operands[0]) == MEM + && (INTVAL (operands[1]) & ~0xff0000) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (INTVAL (operands[1]) >> 16); + operands[0] = adj_offsettable_operand (operands[0], 2); + return AS2 (test%B0,%1,%b0); + } + + if (GET_CODE (operands[0]) == MEM + && (INTVAL (operands[1]) & ~0xff000000) == 0) + { + operands[1] = GEN_INT ((INTVAL (operands[1]) >> 24) & 0xff); + operands[0] = adj_offsettable_operand (operands[0], 3); + return AS2 (test%B0,%1,%b0); + } + } + + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%L0,%1,%0); + + return AS2 (test%L1,%0,%1); +} +} + +static char * +output_33 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) + && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) + { + if ((INTVAL (operands[1]) & 0xff00) == 0) + { + /* ??? This might not be necessary. */ + if (INTVAL (operands[1]) & 0xffff0000) + operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); + + /* We may set the sign bit spuriously. */ + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((INTVAL (operands[1]) & 0xff) == 0) + { + operands[1] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0xff); + + if (QI_REG_P (operands[0])) + return AS2 (test%B0,%1,%h0); + else + { + operands[0] = adj_offsettable_operand (operands[0], 1); + return AS2 (test%B0,%1,%b0); + } + } + } + + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%W0,%1,%0); + + return AS2 (test%W1,%0,%1); +} +} + +static char * +output_34 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%B0,%1,%0); + + return AS2 (test%B1,%0,%1); +} +} + +static char * +output_38 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%L0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%L0,%0); + + return AS2 (mov%L0,%1,%0); +} +} + +static char * +output_40 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx link; + if (REG_P (operands[0]) && operands[1] == const0_rtx) + return AS2 (xor%L0,%k0,%k0); + + if (REG_P (operands[0]) && operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%L0,%k0); + + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return AS2 (mov%L0,%k1,%k0); + else if (CONSTANT_P (operands[1])) + return AS2 (mov%L0,%1,%k0); + } + + return AS2 (mov%W0,%1,%0); +} +} + +static char * +output_41 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%W0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%W0,%0); + + return AS2 (mov%W0,%1,%0); +} +} + +static char * +output_42 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); + return AS1 (push%W0,%1); +} +} + +static char * +output_43 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%B0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%B0,%0); + + /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */ + if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) + return (AS2 (mov%L0,%k1,%k0)); + + return (AS2 (mov%B0,%1,%0)); +} +} + +static char * +output_44 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%B0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%B0,%0); + + /* If mov%B0 isn't allowed for one of these regs, use mov%W0. */ + if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) + { + abort (); + return (AS2 (mov%L0,%k1,%k0)); + } + + return AS2 (mov%B0,%1,%0); +} +} + +static char * +output_45 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (STACK_REG_P (operands[1])) + { + rtx xops[3]; + + if (! STACK_TOP_P (operands[1])) + abort (); + + xops[0] = AT_SP (SFmode); + xops[1] = GEN_INT (4); + xops[2] = stack_pointer_rtx; + + output_asm_insn (AS2 (sub%L2,%1,%2), xops); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp%S0,%0), xops); + else + output_asm_insn (AS1 (fst%S0,%0), xops); + RET; + } + return AS1 (push%L1,%1); +} +} + +static char * +output_46 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + /* First handle a `pop' insn or a `fld %st(0)' */ + + if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp,%y0); + else + return AS1 (fld,%y0); + } + + /* Handle a transfer between the 387 and a 386 register */ + + if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + /* Handle other kinds of writes from the 387 */ + + if (STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp%z0,%y0); + else + return AS1 (fst%z0,%y0); + } + + /* Handle other kinds of reads to the 387 */ + + if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) + return (char *) output_move_const_single (operands); + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + /* Handle all SFmode moves not involving the 387 */ + + return (char *) singlemove_string (operands); +} +} + +static char * +output_47 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (STACK_REG_P (operands[1])) + { + rtx xops[3]; + + xops[0] = AT_SP (SFmode); + xops[1] = GEN_INT (8); + xops[2] = stack_pointer_rtx; + + output_asm_insn (AS2 (sub%L2,%1,%2), xops); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp%Q0,%0), xops); + else + output_asm_insn (AS1 (fst%Q0,%0), xops); + + RET; + } + else + return (char *) output_move_double (operands); +} +} + +static char * +output_48 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (STACK_TOP_P (operands[0])) + return AS1 (fxch,%1); + else + return AS1 (fxch,%0); +} +} + +static char * +output_49 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + /* First handle a `pop' insn or a `fld %st(0)' */ + + if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp,%y0); + else + return AS1 (fld,%y0); + } + + /* Handle a transfer between the 387 and a 386 register */ + + if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + /* Handle other kinds of writes from the 387 */ + + if (STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp%z0,%y0); + else + return AS1 (fst%z0,%y0); + } + + /* Handle other kinds of reads to the 387 */ + + if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) + return (char *) output_move_const_single (operands); + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + /* Handle all DFmode moves not involving the 387 */ + + return (char *) output_move_double (operands); +} +} + +static char * +output_50 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + return (char *) output_move_double (operands); +} +} + +static char * +output_51 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + return (char *) output_move_double (operands); +} +} + +static char * +output_52 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if ((TARGET_486 || REGNO (operands[0]) == 0) + && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xffff); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + +#ifdef INTEL_SYNTAX + return AS2 (movzx,%1,%0); +#else + return AS2 (movz%W0%L0,%1,%0); +#endif +} +} + +static char * +output_53 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if ((TARGET_486 || REGNO (operands[0]) == 0) + && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xff); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + +#ifdef INTEL_SYNTAX + return AS2 (movzx,%1,%0); +#else + return AS2 (movz%B0%W0,%1,%0); +#endif +} +} + +static char * +output_54 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if ((TARGET_486 || REGNO (operands[0]) == 0) + && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xff); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + +#ifdef INTEL_SYNTAX + return AS2 (movzx,%1,%0); +#else + return AS2 (movz%B0%L0,%1,%0); +#endif +} +} + +static char * +output_55 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return AS2 (xor%L0,%0,%0); +} +} + +static char * +output_56 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REGNO (operands[0]) == 0) + { + /* This used to be cwtl, but that extends HI to SI somehow. */ +#ifdef INTEL_SYNTAX + return "cdq"; +#else + return "cltd"; +#endif + } + + operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + output_asm_insn (AS2 (mov%L0,%0,%1), operands); + + operands[0] = GEN_INT (31); + return AS2 (sar%L1,%0,%1); +} +} + +static char * +output_57 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REGNO (operands[0]) == 0 + && REG_P (operands[1]) && REGNO (operands[1]) == 0) +#ifdef INTEL_SYNTAX + return "cwde"; +#else + return "cwtl"; +#endif + +#ifdef INTEL_SYNTAX + return AS2 (movsx,%1,%0); +#else + return AS2 (movs%W0%L0,%1,%0); +#endif +} +} + +static char * +output_58 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REGNO (operands[0]) == 0 + && REG_P (operands[1]) && REGNO (operands[1]) == 0) + return "cbtw"; + +#ifdef INTEL_SYNTAX + return AS2 (movsx,%1,%0); +#else + return AS2 (movs%B0%W0,%1,%0); +#endif +} +} + +static char * +output_59 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef INTEL_SYNTAX + return AS2 (movsx,%1,%0); +#else + return AS2 (movs%B0%L0,%1,%0); +#endif +} +} + +static char * +output_60 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + return AS1 (fstp%z0,%y0); + else + return AS1 (fst%z0,%y0); + } + + abort (); +} +} + +static char * +output_62 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + return AS1 (fstp%z0,%0); + else + return AS1 (fst%z0,%0); + } + else if (STACK_TOP_P (operands[0])) + { + output_asm_insn (AS1 (fstp%z2,%y2), operands); + return AS1 (fld%z2,%y2); + } + else + abort (); +} +} + +static char * +output_67 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_fix_trunc (insn, operands); +} + +static char * +output_68 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_fix_trunc (insn, operands); +} + +static char * +output_71 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_fix_trunc (insn, operands); +} + +static char * +output_72 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_fix_trunc (insn, operands); +} + +static char * +output_77 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +} +} + +static char * +output_78 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +} +} + +static char * +output_79 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +} +} + +static char * +output_80 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +} +} + +static char * +output_81 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx low[3], high[3]; + + CC_STATUS_INIT; + + split_di (operands, 3, low, high); + + if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) + { + output_asm_insn (AS2 (add%L0,%2,%0), low); + output_asm_insn (AS2 (adc%L0,%2,%0), high); + } + else + output_asm_insn (AS2 (add%L0,%2,%0), high); + RET; +} +} + +static char * +output_82 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) + { + if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) + return AS2 (add%L0,%1,%0); + + if (! TARGET_486 || ! REG_P (operands[2])) + { + CC_STATUS_INIT; + + if (operands[2] == stack_pointer_rtx) + { + rtx temp; + + temp = operands[1]; + operands[1] = operands[2]; + operands[2] = temp; + } + if (operands[2] != stack_pointer_rtx) + { + operands[1] = SET_SRC (PATTERN (insn)); + return AS2 (lea%L0,%a1,%0); + } + } + + output_asm_insn (AS2 (mov%L0,%1,%0), operands); + } + + if (operands[2] == const1_rtx) + return AS1 (inc%L0,%0); + + if (operands[2] == constm1_rtx) + return AS1 (dec%L0,%0); + + return AS2 (add%L0,%2,%0); +} +} + +static char * +output_83 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (operands[2] == const1_rtx) + return AS1 (inc%W0,%0); + + if (operands[2] == constm1_rtx) + return AS1 (dec%W0,%0); + + return AS2 (add%W0,%2,%0); +} +} + +static char * +output_84 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (operands[2] == const1_rtx) + return AS1 (inc%B0,%0); + + if (operands[2] == constm1_rtx) + return AS1 (dec%B0,%0); + + return AS2 (add%B0,%2,%0); +} +} + +static char * +output_85 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + /* Adding a constant to a register is faster with an add. */ + /* ??? can this ever happen? */ + if (GET_CODE (operands[1]) == PLUS + && GET_CODE (XEXP (operands[1], 1)) == CONST_INT + && rtx_equal_p (operands[0], XEXP (operands[1], 0))) + { + operands[1] = XEXP (operands[1], 1); + + if (operands[1] == const1_rtx) + return AS1 (inc%L0,%0); + + if (operands[1] == constm1_rtx) + return AS1 (dec%L0,%0); + + return AS2 (add%L0,%1,%0); + } + return AS2 (lea%L0,%a1,%0); +} +} + +static char * +output_88 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx low[3], high[3]; + + CC_STATUS_INIT; + + split_di (operands, 3, low, high); + + if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) + { + output_asm_insn (AS2 (sub%L0,%2,%0), low); + output_asm_insn (AS2 (sbb%L0,%2,%0), high); + } + else + output_asm_insn (AS2 (sub%L0,%2,%0), high); + + RET; +} +} + +static char * +output_89 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (sub%L0,%2,%0); +} + +static char * +output_90 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (sub%W0,%2,%0); +} + +static char * +output_91 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (sub%B0,%2,%0); +} + +static char * +output_94 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (imul%W0,%2,%0); +} + +static char * +output_95 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == REG + && REGNO (operands[1]) == REGNO (operands[0]) + && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) + /* Assembler has weird restrictions. */ + return AS2 (imul%W0,%2,%0); + return AS3 (imul%W0,%2,%1,%0); +} +} + +static char * +output_96 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (imul%L0,%2,%0); +} + +static char * +output_97 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == REG + && REGNO (operands[1]) == REGNO (operands[0]) + && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) + /* Assembler has weird restrictions. */ + return AS2 (imul%L0,%2,%0); + return AS3 (imul%L0,%2,%1,%0); +} +} + +static char * +output_105 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef INTEL_SYNTAX + output_asm_insn ("cdq", operands); +#else + output_asm_insn ("cltd", operands); +#endif + return AS1 (idiv%L0,%2); +} +} + +static char * +output_107 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + output_asm_insn (AS2 (xor%L3,%3,%3), operands); + return AS1 (div%L0,%2); +} +} + +static char * +output_108 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + output_asm_insn (AS2 (xor%W0,%3,%3), operands); + return AS1 (div%W0,%2); +} +} + +static char * +output_109 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if (INTVAL (operands[2]) == 0xffff && REG_P (operands[0]) + && (! REG_P (operands[1]) + || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) + && (! TARGET_486 || ! rtx_equal_p (operands[0], operands[1]))) + { + /* ??? tege: Should forget CC_STATUS only if we clobber a + remembered operand. Fix that later. */ + CC_STATUS_INIT; +#ifdef INTEL_SYNTAX + return AS2 (movzx,%w1,%0); +#else + return AS2 (movz%W0%L0,%w1,%0); +#endif + } + + if (INTVAL (operands[2]) == 0xff && REG_P (operands[0]) + && !(REG_P (operands[1]) && NON_QI_REG_P (operands[1])) + && (! REG_P (operands[1]) + || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) + && (! TARGET_486 || ! rtx_equal_p (operands[0], operands[1]))) + { + /* ??? tege: Should forget CC_STATUS only if we clobber a + remembered operand. Fix that later. */ + CC_STATUS_INIT; +#ifdef INTEL_SYNTAX + return AS2 (movzx,%b1,%0); +#else + return AS2 (movz%B0%L0,%b1,%0); +#endif + } + + if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xffffff00) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%b0); + } + + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); + return AS2 (and%B0,%2,%b0); + } + + if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff00) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xffff00ff) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%h0); + } + + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + return AS2 (and%B0,%2,%h0); + } + + if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) == 0xffff0000) + { + operands[2] = const0_rtx; + return AS2 (mov%W0,%2,%w0); + } + } + + return AS2 (and%L0,%2,%0); +} +} + +static char * +output_110 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + /* Can we ignore the upper byte? */ + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & 0xff00) == 0xff00) + { + CC_STATUS_INIT; + + if ((INTVAL (operands[2]) & 0xff) == 0) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%b0); + } + + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); + return AS2 (and%B0,%2,%b0); + } + + /* Can we ignore the lower byte? */ + /* ??? what about offsettable memory references? */ + if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & 0xff) == 0xff) + { + CC_STATUS_INIT; + + if ((INTVAL (operands[2]) & 0xff00) == 0) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%h0); + } + + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + return AS2 (and%B0,%2,%h0); + } + } + + return AS2 (and%W0,%2,%0); +} +} + +static char * +output_111 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (and%B0,%2,%0); +} + +static char * +output_112 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & ~0xff) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%b0); + + return AS2 (or%B0,%2,%b0); + } + + if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT (INTVAL (operands[2]) >> 8); + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%h0); + + return AS2 (or%B0,%2,%h0); + } + } + + return AS2 (or%L0,%2,%0); +} +} + +static char * +output_113 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + /* Can we ignore the upper byte? */ + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & 0xff00) == 0) + { + CC_STATUS_INIT; + if (INTVAL (operands[2]) & 0xffff0000) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%b0); + + return AS2 (or%B0,%2,%b0); + } + + /* Can we ignore the lower byte? */ + /* ??? what about offsettable memory references? */ + if (QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%h0); + + return AS2 (or%B0,%2,%h0); + } + } + + return AS2 (or%W0,%2,%0); +} +} + +static char * +output_114 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (or%B0,%2,%0); +} + +static char * +output_115 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & ~0xff) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%b0); + + return AS2 (xor%B0,%2,%b0); + } + + if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT (INTVAL (operands[2]) >> 8); + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%h0); + + return AS2 (xor%B0,%2,%h0); + } + } + + return AS2 (xor%L0,%2,%0); +} +} + +static char * +output_116 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + /* Can we ignore the upper byte? */ + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & 0xff00) == 0) + { + CC_STATUS_INIT; + if (INTVAL (operands[2]) & 0xffff0000) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%b0); + + return AS2 (xor%B0,%2,%b0); + } + + /* Can we ignore the lower byte? */ + /* ??? what about offsettable memory references? */ + if (QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%h0); + + return AS2 (xor%B0,%2,%h0); + } + } + + return AS2 (xor%W0,%2,%0); +} +} + +static char * +output_117 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (xor%B0,%2,%0); +} + +static char * +output_118 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = const0_rtx; + xops[1] = high[0]; + + output_asm_insn (AS1 (neg%L0,%0), low); + output_asm_insn (AS2 (adc%L1,%0,%1), xops); + output_asm_insn (AS1 (neg%L0,%0), high); + RET; +} +} + +static char * +output_141 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + if (INTVAL (xops[0]) > 31) + { + output_asm_insn (AS2 (mov%L3,%2,%3), xops); /* Fast shift by 32 */ + output_asm_insn (AS2 (xor%L2,%2,%2), xops); + + if (INTVAL (xops[0]) > 32) + { + xops[0] = GEN_INT (INTVAL (xops[0]) - 32); + output_asm_insn (AS2 (sal%L3,%0,%3), xops); /* Remaining shift */ + } + } + else + { + output_asm_insn (AS3 (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + } + RET; +} +} + +static char * +output_142 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ + + output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + + xops[1] = GEN_INT (7); /* shift count & 1 */ + + output_asm_insn (AS2 (shr%B0,%1,%0), xops); + + output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + + RET; +} +} + +static char * +output_143 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) + { + if (TARGET_486 && INTVAL (operands[2]) == 1) + { + output_asm_insn (AS2 (mov%L0,%1,%0), operands); + return AS2 (add%L0,%1,%0); + } + else + { + CC_STATUS_INIT; + + if (operands[1] == stack_pointer_rtx) + { + output_asm_insn (AS2 (mov%L0,%1,%0), operands); + operands[1] = operands[0]; + } + operands[1] = gen_rtx (MULT, SImode, operands[1], + GEN_INT (1 << INTVAL (operands[2]))); + return AS2 (lea%L0,%a1,%0); + } + } + + if (REG_P (operands[2])) + return AS2 (sal%L0,%b2,%0); + + if (REG_P (operands[0]) && operands[2] == const1_rtx) + return AS2 (add%L0,%0,%0); + + return AS2 (sal%L0,%2,%0); +} +} + +static char * +output_144 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (sal%W0,%b2,%0); + + if (REG_P (operands[0]) && operands[2] == const1_rtx) + return AS2 (add%W0,%0,%0); + + return AS2 (sal%W0,%2,%0); +} +} + +static char * +output_145 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (sal%B0,%b2,%0); + + if (REG_P (operands[0]) && operands[2] == const1_rtx) + return AS2 (add%B0,%0,%0); + + return AS2 (sal%B0,%2,%0); +} +} + +static char * +output_147 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + if (INTVAL (xops[0]) > 31) + { + xops[1] = GEN_INT (31); + output_asm_insn (AS2 (mov%L2,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */ + + if (INTVAL (xops[0]) > 32) + { + xops[0] = GEN_INT (INTVAL (xops[0]) - 32); + output_asm_insn (AS2 (sar%L2,%0,%2), xops); /* Remaining shift */ + } + } + else + { + output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + } + + RET; +} +} + +static char * +output_148 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + + xops[1] = GEN_INT (7); /* shift count & 1 */ + + output_asm_insn (AS2 (shr%B0,%1,%0), xops); + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + + RET; +} +} + +static char * +output_149 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (sar%L0,%b2,%0); + else + return AS2 (sar%L0,%2,%0); +} +} + +static char * +output_150 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (sar%W0,%b2,%0); + else + return AS2 (sar%W0,%2,%0); +} +} + +static char * +output_151 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (sar%B0,%b2,%0); + else + return AS2 (sar%B0,%2,%0); +} +} + +static char * +output_153 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + if (INTVAL (xops[0]) > 31) + { + output_asm_insn (AS2 (mov%L2,%3,%2), xops); /* Fast shift by 32 */ + output_asm_insn (AS2 (xor%L3,%3,%3), xops); + + if (INTVAL (xops[0]) > 32) + { + xops[0] = GEN_INT (INTVAL (xops[0]) - 32); + output_asm_insn (AS2 (shr%L2,%0,%2), xops); /* Remaining shift */ + } + } + else + { + output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + } + + RET; +} +} + +static char * +output_154 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + + xops[1] = GEN_INT (7); /* shift count & 1 */ + + output_asm_insn (AS2 (shr%B0,%1,%0), xops); + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + + RET; +} +} + +static char * +output_155 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (shr%L0,%b2,%0); + else + return AS2 (shr%L0,%2,%1); +} +} + +static char * +output_156 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (shr%W0,%b2,%0); + else + return AS2 (shr%W0,%2,%0); +} +} + +static char * +output_157 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (shr%B0,%b2,%0); + else + return AS2 (shr%B0,%2,%0); +} +} + +static char * +output_158 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (rol%L0,%b2,%0); + else + return AS2 (rol%L0,%2,%0); +} +} + +static char * +output_159 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (rol%W0,%b2,%0); + else + return AS2 (rol%W0,%2,%0); +} +} + +static char * +output_160 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (rol%B0,%b2,%0); + else + return AS2 (rol%B0,%2,%0); +} +} + +static char * +output_161 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (ror%L0,%b2,%0); + else + return AS2 (ror%L0,%2,%0); +} +} + +static char * +output_162 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (ror%W0,%b2,%0); + else + return AS2 (ror%W0,%2,%0); +} +} + +static char * +output_163 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (ror%B0,%b2,%0); + else + return AS2 (ror%B0,%2,%0); +} +} + +static char * +output_164 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + if (INTVAL (operands[3]) == 1) + return AS2 (bts%L0,%2,%0); + else + return AS2 (btr%L0,%2,%0); +} +} + +static char * +output_165 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + return AS2 (btc%L0,%1,%0); +} +} + +static char * +output_166 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + return AS2 (btc%L0,%2,%0); +} +} + +static char * +output_167 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags |= CC_Z_IN_NOT_C; + return AS2 (bt%L0,%1,%0); +} +} + +static char * +output_168 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + unsigned int mask; + + mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]); + operands[1] = GEN_INT (mask); + + if (QI_REG_P (operands[0])) + { + if ((mask & ~0xff) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((mask & ~0xff00) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 8); + return AS2 (test%B0,%1,%h0); + } + } + + return AS2 (test%L0,%1,%0); +} +} + +static char * +output_169 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + unsigned int mask; + + mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]); + operands[1] = GEN_INT (mask); + + if (! REG_P (operands[0]) || QI_REG_P (operands[0])) + { + if ((mask & ~0xff) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((mask & ~0xff00) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 8); + + if (QI_REG_P (operands[0])) + return AS2 (test%B0,%1,%h0); + else + { + operands[0] = adj_offsettable_operand (operands[0], 1); + return AS2 (test%B0,%1,%b0); + } + } + + if (GET_CODE (operands[0]) == MEM && (mask & ~0xff0000) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 16); + operands[0] = adj_offsettable_operand (operands[0], 2); + return AS2 (test%B0,%1,%b0); + } + + if (GET_CODE (operands[0]) == MEM && (mask & ~0xff000000) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 24); + operands[0] = adj_offsettable_operand (operands[0], 3); + return AS2 (test%B0,%1,%b0); + } + } + + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%L0,%1,%0); + + return AS2 (test%L1,%0,%1); +} +} + +static char * +output_171 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return AS1 (setnb,%0); + else + return AS1 (sete,%0); +} +} + +static char * +output_173 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return AS1 (setb,%0); + else + return AS1 (setne,%0); +} + +} + +static char * +output_175 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (sete,%0); + + OUTPUT_JUMP ("setg %0", "seta %0", NULL_PTR); +} +} + +static char * +output_177 (operands, insn) + rtx *operands; + rtx insn; +{ + return "seta %0"; +} + +static char * +output_179 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (sete,%0); + + OUTPUT_JUMP ("setl %0", "setb %0", "sets %0"); +} +} + +static char * +output_181 (operands, insn) + rtx *operands; + rtx insn; +{ + return "setb %0"; +} + +static char * +output_183 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (sete,%0); + + OUTPUT_JUMP ("setge %0", "setae %0", "setns %0"); +} +} + +static char * +output_185 (operands, insn) + rtx *operands; + rtx insn; +{ + return "setae %0"; +} + +static char * +output_187 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (setb,%0); + + OUTPUT_JUMP ("setle %0", "setbe %0", NULL_PTR); +} +} + +static char * +output_189 (operands, insn) + rtx *operands; + rtx insn; +{ + return "setbe %0"; +} + +static char * +output_191 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return "jnc %l0"; + else + return "je %l0"; +} +} + +static char * +output_193 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return "jc %l0"; + else + return "jne %l0"; +} +} + +static char * +output_195 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (je,%l0); + + OUTPUT_JUMP ("jg %l0", "ja %l0", NULL_PTR); +} +} + +static char * +output_199 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (je,%l0); + + OUTPUT_JUMP ("jl %l0", "jb %l0", "js %l0"); +} +} + +static char * +output_203 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (je,%l0); + + OUTPUT_JUMP ("jge %l0", "jae %l0", "jns %l0"); +} +} + +static char * +output_207 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jb,%l0); + + OUTPUT_JUMP ("jle %l0", "jbe %l0", NULL_PTR); +} +} + +static char * +output_210 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return "jc %l0"; + else + return "jne %l0"; +} +} + +static char * +output_211 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return "jnc %l0"; + else + return "je %l0"; +} +} + +static char * +output_212 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jne,%l0); + + OUTPUT_JUMP ("jle %l0", "jbe %l0", NULL_PTR); +} +} + +static char * +output_214 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jne,%l0); + + OUTPUT_JUMP ("jge %l0", "jae %l0", "jns %l0"); +} +} + +static char * +output_216 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jne,%l0); + + OUTPUT_JUMP ("jl %l0", "jb %l0", "js %l0"); +} +} + +static char * +output_218 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jae,%l0); + + OUTPUT_JUMP ("jg %l0", "ja %l0", NULL_PTR); +} +} + +static char * +output_221 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + return AS1 (jmp,%*%0); +} +} + +static char * +output_223 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4]; + + xops[0] = operands[0]; + xops[1] = operands[1]; + xops[2] = operands[2]; + xops[3] = pic_offset_table_rtx; + + output_asm_insn (AS2 (mov%L2,%3,%2), xops); + output_asm_insn ("sub%L2 %l1@GOTOFF(%3,%0,4),%2", xops); + output_asm_insn (AS1 (jmp,%*%2), xops); + ASM_OUTPUT_ALIGN_CODE (asm_out_file); + RET; +} +} + +static char * +output_224 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + return AS1 (jmp,%*%0); +} +} + +static char * +output_226 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) + { + operands[0] = XEXP (operands[0], 0); + return AS1 (call,%*%0); + } + else + return AS1 (call,%P0); +} +} + +static char * +output_229 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) + { + operands[0] = XEXP (operands[0], 0); + return AS1 (call,%*%0); + } + else + return AS1 (call,%P0); +} +} + +static char * +output_232 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) + { + operands[1] = XEXP (operands[1], 0); + output_asm_insn (AS1 (call,%*%1), operands); + } + else + output_asm_insn (AS1 (call,%P1), operands); + + RET; +} +} + +static char * +output_235 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) + { + operands[1] = XEXP (operands[1], 0); + output_asm_insn (AS1 (call,%*%1), operands); + } + else + output_asm_insn (AS1 (call,%P1), operands); + + RET; +} +} + +static char * +output_238 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx addr = operands[1]; + + if (GET_CODE (operands[0]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) + { + operands[0] = XEXP (operands[0], 0); + output_asm_insn (AS1 (call,%*%0), operands); + } + else + output_asm_insn (AS1 (call,%P0), operands); + + operands[2] = gen_rtx (REG, SImode, 0); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[2] = gen_rtx (REG, SImode, 1); + operands[1] = adj_offsettable_operand (addr, 4); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[1] = adj_offsettable_operand (addr, 8); + return AS1 (fnsave,%1); +} +} + +static char * +output_239 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx addr = operands[1]; + + output_asm_insn (AS1 (call,%P0), operands); + + operands[2] = gen_rtx (REG, SImode, 0); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[2] = gen_rtx (REG, SImode, 1); + operands[1] = adj_offsettable_operand (addr, 4); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[1] = adj_offsettable_operand (addr, 8); + return AS1 (fnsave,%1); +} +} + +static char * +output_242 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + function_epilogue (asm_out_file, get_frame_size ()); + RET; +} +} + +static char * +output_245 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2]; + + output_asm_insn ("cld", operands); + if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) & ~0x03) + { + xops[0] = GEN_INT ((INTVAL (operands[2]) >> 2) & 0x3fffffff); + xops[1] = operands[4]; + + output_asm_insn (AS2 (mov%L1,%0,%1), xops); +#ifdef INTEL_SYNTAX + output_asm_insn ("rep movsd", xops); +#else + output_asm_insn ("rep\n\tmovsl", xops); +#endif + } + if (INTVAL (operands[2]) & 0x02) + output_asm_insn ("movsw", operands); + if (INTVAL (operands[2]) & 0x01) + output_asm_insn ("movsb", operands); + } + else + abort (); + RET; +} +} + +static char * +output_247 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], label; + + label = gen_label_rtx (); + + output_asm_insn ("cld", operands); + output_asm_insn (AS2 (xor%L0,%0,%0), operands); + output_asm_insn ("repz\n\tcmps%B2", operands); + output_asm_insn ("je %l0", &label); + + xops[0] = operands[0]; + xops[1] = gen_rtx (MEM, QImode, + gen_rtx (PLUS, SImode, operands[1], constm1_rtx)); + xops[2] = gen_rtx (MEM, QImode, + gen_rtx (PLUS, SImode, operands[2], constm1_rtx)); + xops[3] = operands[3]; + + output_asm_insn (AS2 (movz%B1%L0,%1,%0), xops); + output_asm_insn (AS2 (movz%B2%L3,%2,%3), xops); + + output_asm_insn (AS2 (sub%L0,%3,%0), xops); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (label)); + RET; +} +} + +static char * +output_248 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2]; + + cc_status.flags |= CC_NOT_SIGNED; + + xops[0] = gen_rtx (REG, QImode, 0); + xops[1] = CONST0_RTX (QImode); + + output_asm_insn ("cld", operands); + output_asm_insn (AS2 (test%B0,%1,%0), xops); + return "repz\n\tcmps%B2"; +} +} + +static char * +output_250 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2]; + + xops[0] = const1_rtx; + xops[1] = operands[1]; + output_asm_insn (AS2 (bsf%L1,%1,%0), operands); + output_asm_insn (AS2 (cmp%L1,%0,%1), xops); + output_asm_insn (AS2 (sbb%L0,%2,%2), operands); + output_asm_insn (AS2 (or%L0,%2,%0), operands); + return ""; +} +} + +static char * +output_252 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2]; + + xops[0] = const1_rtx; + xops[1] = operands[1]; + output_asm_insn (AS2 (bsf%W1,%1,%0), operands); + output_asm_insn (AS2 (cmp%W1,%0,%1), xops); + output_asm_insn (AS2 (sbb%W0,%2,%2), operands); + output_asm_insn (AS2 (or%W0,%2,%0), operands); + return ""; +} +} + +static char * +output_253 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_254 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_255 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_256 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_257 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_258 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_259 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_260 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_262 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2]; + + xops[0] = operands[0]; + xops[1] = constm1_rtx; + output_asm_insn ("cld", operands); + output_asm_insn (AS2 (mov%L0,%1,%0), xops); + return "repnz\n\tscas%B2"; +} +} + +char * const insn_template[] = + { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "push%L0 %1", + "push%L0 %1", + 0, + 0, + "push%W0 %1", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "mul%B0 %2", + 0, + 0, + "idiv%B0 %2", + "div%B0 %2", + 0, + 0, + 0, + "cwtd\n\tidiv%W0 %2", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "neg%L0 %0", + "neg%W0 %0", + "neg%B0 %0", + "fchs", + "fchs", + "fchs", + "fabs", + "fabs", + "fabs", + "fsqrt", + "fsqrt", + "fsqrt", + "fsin", + "fsin", + "fsin", + "fcos", + "fcos", + "fcos", + "not%L0 %0", + "not%W0 %0", + "not%B0 %0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "ja %l0", + 0, + 0, + 0, + "jb %l0", + 0, + 0, + 0, + "jae %l0", + 0, + 0, + 0, + "jbe %l0", + 0, + 0, + 0, + "jbe %l0", + 0, + "jae %l0", + 0, + "jb %l0", + 0, + "ja %l0", + "jmp %l0", + 0, + 0, + 0, + 0, + 0, + 0, + "call %P0", + 0, + 0, + "call %P0", + 0, + 0, + "call %P1", + 0, + 0, + "call %P1", + 0, + 0, + 0, + 0, + "frstor %0", + 0, + "nop", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + }; + +char *(*const insn_outfun[])() = + { + output_0, + 0, + output_2, + 0, + output_4, + 0, + output_6, + 0, + output_8, + 0, + output_10, + 0, + output_12, + 0, + output_14, + 0, + output_16, + output_17, + output_18, + output_19, + output_20, + output_21, + output_22, + output_23, + output_24, + output_25, + 0, + 0, + 0, + 0, + 0, + 0, + output_32, + output_33, + output_34, + 0, + 0, + 0, + output_38, + 0, + output_40, + output_41, + output_42, + output_43, + output_44, + output_45, + output_46, + output_47, + output_48, + output_49, + output_50, + output_51, + output_52, + output_53, + output_54, + output_55, + output_56, + output_57, + output_58, + output_59, + output_60, + 0, + output_62, + 0, + 0, + 0, + 0, + output_67, + output_68, + 0, + 0, + output_71, + output_72, + 0, + 0, + 0, + 0, + output_77, + output_78, + output_79, + output_80, + output_81, + output_82, + output_83, + output_84, + output_85, + 0, + 0, + output_88, + output_89, + output_90, + output_91, + 0, + 0, + output_94, + output_95, + output_96, + output_97, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_105, + 0, + output_107, + output_108, + output_109, + output_110, + output_111, + output_112, + output_113, + output_114, + output_115, + output_116, + output_117, + output_118, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_141, + output_142, + output_143, + output_144, + output_145, + 0, + output_147, + output_148, + output_149, + output_150, + output_151, + 0, + output_153, + output_154, + output_155, + output_156, + output_157, + output_158, + output_159, + output_160, + output_161, + output_162, + output_163, + output_164, + output_165, + output_166, + output_167, + output_168, + output_169, + 0, + output_171, + 0, + output_173, + 0, + output_175, + 0, + output_177, + 0, + output_179, + 0, + output_181, + 0, + output_183, + 0, + output_185, + 0, + output_187, + 0, + output_189, + 0, + output_191, + 0, + output_193, + 0, + output_195, + 0, + 0, + 0, + output_199, + 0, + 0, + 0, + output_203, + 0, + 0, + 0, + output_207, + 0, + 0, + output_210, + output_211, + output_212, + 0, + output_214, + 0, + output_216, + 0, + output_218, + 0, + 0, + output_221, + 0, + output_223, + output_224, + 0, + output_226, + 0, + 0, + output_229, + 0, + 0, + output_232, + 0, + 0, + output_235, + 0, + 0, + output_238, + output_239, + 0, + 0, + output_242, + 0, + 0, + output_245, + 0, + output_247, + output_248, + 0, + output_250, + 0, + output_252, + output_253, + output_254, + output_255, + output_256, + output_257, + output_258, + output_259, + output_260, + 0, + output_262, + }; + +rtx (*const insn_gen_function[]) () = + { + gen_tstsi_1, + gen_tstsi, + gen_tsthi_1, + gen_tsthi, + gen_tstqi_1, + gen_tstqi, + gen_tstsf_cc, + gen_tstsf, + gen_tstdf_cc, + gen_tstdf, + gen_cmpsi_1, + gen_cmpsi, + gen_cmphi_1, + gen_cmphi, + gen_cmpqi_1, + gen_cmpqi, + 0, + 0, + 0, + 0, + 0, + 0, + gen_cmpsf_cc_1, + 0, + 0, + 0, + gen_cmpdf, + gen_cmpsf, + gen_cmpdf_cc, + gen_cmpdf_ccfpeq, + gen_cmpsf_cc, + gen_cmpsf_ccfpeq, + 0, + 0, + 0, + 0, + 0, + gen_movsi, + 0, + 0, + gen_movhi, + gen_movstricthi, + 0, + gen_movqi, + gen_movstrictqi, + 0, + gen_movsf, + 0, + gen_swapdf, + gen_movdf, + 0, + gen_movdi, + gen_zero_extendhisi2, + gen_zero_extendqihi2, + gen_zero_extendqisi2, + gen_zero_extendsidi2, + gen_extendsidi2, + gen_extendhisi2, + gen_extendqihi2, + gen_extendqisi2, + gen_extendsfdf2, + gen_truncdfsf2, + 0, + gen_fixuns_truncdfsi2, + gen_fixuns_truncsfsi2, + gen_fix_truncdfdi2, + gen_fix_truncsfdi2, + 0, + 0, + gen_fix_truncdfsi2, + gen_fix_truncsfsi2, + 0, + 0, + gen_floatsisf2, + gen_floatdisf2, + gen_floatsidf2, + gen_floatdidf2, + 0, + 0, + 0, + 0, + gen_adddi3, + gen_addsi3, + gen_addhi3, + gen_addqi3, + 0, + gen_adddf3, + gen_addsf3, + gen_subdi3, + gen_subsi3, + gen_subhi3, + gen_subqi3, + gen_subdf3, + gen_subsf3, + 0, + gen_mulhi3, + 0, + gen_mulsi3, + 0, + gen_muldf3, + gen_mulsf3, + gen_divqi3, + gen_udivqi3, + gen_divdf3, + gen_divsf3, + gen_divmodsi4, + gen_divmodhi4, + gen_udivmodsi4, + gen_udivmodhi4, + gen_andsi3, + gen_andhi3, + gen_andqi3, + gen_iorsi3, + gen_iorhi3, + gen_iorqi3, + gen_xorsi3, + gen_xorhi3, + gen_xorqi3, + gen_negdi2, + gen_negsi2, + gen_neghi2, + gen_negqi2, + gen_negsf2, + gen_negdf2, + 0, + gen_abssf2, + gen_absdf2, + 0, + gen_sqrtsf2, + gen_sqrtdf2, + 0, + gen_sindf2, + gen_sinsf2, + 0, + gen_cosdf2, + gen_cossf2, + 0, + gen_one_cmplsi2, + gen_one_cmplhi2, + gen_one_cmplqi2, + gen_ashldi3, + gen_ashldi3_const_int, + gen_ashldi3_non_const_int, + gen_ashlsi3, + gen_ashlhi3, + gen_ashlqi3, + gen_ashrdi3, + gen_ashrdi3_const_int, + gen_ashrdi3_non_const_int, + gen_ashrsi3, + gen_ashrhi3, + gen_ashrqi3, + gen_lshrdi3, + gen_lshrdi3_const_int, + gen_lshrdi3_non_const_int, + gen_lshrsi3, + gen_lshrhi3, + gen_lshrqi3, + gen_rotlsi3, + gen_rotlhi3, + gen_rotlqi3, + gen_rotrsi3, + gen_rotrhi3, + gen_rotrqi3, + 0, + 0, + 0, + 0, + 0, + 0, + gen_seq, + 0, + gen_sne, + 0, + gen_sgt, + 0, + gen_sgtu, + 0, + gen_slt, + 0, + gen_sltu, + 0, + gen_sge, + 0, + gen_sgeu, + 0, + gen_sle, + 0, + gen_sleu, + 0, + gen_beq, + 0, + gen_bne, + 0, + gen_bgt, + 0, + gen_bgtu, + 0, + gen_blt, + 0, + gen_bltu, + 0, + gen_bge, + 0, + gen_bgeu, + 0, + gen_ble, + 0, + gen_bleu, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_jump, + gen_indirect_jump, + gen_casesi, + 0, + gen_tablejump, + gen_call_pop, + 0, + 0, + gen_call, + 0, + 0, + gen_call_value_pop, + 0, + 0, + gen_call_value, + 0, + 0, + gen_untyped_call, + 0, + 0, + gen_untyped_return, + gen_update_return, + gen_return, + gen_nop, + gen_movstrsi, + 0, + gen_cmpstrsi, + 0, + 0, + gen_ffssi2, + 0, + gen_ffshi2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_strlensi, + 0, + }; + +char *insn_name[] = + { + "tstsi_1", + "tstsi", + "tsthi_1", + "tsthi", + "tstqi_1", + "tstqi", + "tstsf_cc", + "tstsf", + "tstdf_cc", + "tstdf", + "cmpsi_1", + "cmpsi", + "cmphi_1", + "cmphi", + "cmpqi_1", + "cmpqi", + "cmpqi+1", + "cmpqi+2", + "cmpqi+3", + "cmpsf_cc_1-3", + "cmpsf_cc_1-2", + "cmpsf_cc_1-1", + "cmpsf_cc_1", + "cmpsf_cc_1+1", + "cmpsf_cc_1+2", + "cmpdf-1", + "cmpdf", + "cmpsf", + "cmpdf_cc", + "cmpdf_ccfpeq", + "cmpsf_cc", + "cmpsf_ccfpeq", + "cmpsf_ccfpeq+1", + "cmpsf_ccfpeq+2", + "cmpsf_ccfpeq+3", + "movsi-2", + "movsi-1", + "movsi", + "movsi+1", + "movhi-1", + "movhi", + "movstricthi", + "movstricthi+1", + "movqi", + "movstrictqi", + "movstrictqi+1", + "movsf", + "movsf+1", + "swapdf", + "movdf", + "movdf+1", + "movdi", + "zero_extendhisi2", + "zero_extendqihi2", + "zero_extendqisi2", + "zero_extendsidi2", + "extendsidi2", + "extendhisi2", + "extendqihi2", + "extendqisi2", + "extendsfdf2", + "truncdfsf2", + "truncdfsf2+1", + "fixuns_truncdfsi2", + "fixuns_truncsfsi2", + "fix_truncdfdi2", + "fix_truncsfdi2", + "fix_truncsfdi2+1", + "fix_truncdfsi2-1", + "fix_truncdfsi2", + "fix_truncsfsi2", + "fix_truncsfsi2+1", + "floatsisf2-1", + "floatsisf2", + "floatdisf2", + "floatsidf2", + "floatdidf2", + "floatdidf2+1", + "floatdidf2+2", + "adddi3-2", + "adddi3-1", + "adddi3", + "addsi3", + "addhi3", + "addqi3", + "addqi3+1", + "adddf3", + "addsf3", + "subdi3", + "subsi3", + "subhi3", + "subqi3", + "subdf3", + "subsf3", + "subsf3+1", + "mulhi3", + "mulhi3+1", + "mulsi3", + "mulsi3+1", + "muldf3", + "mulsf3", + "divqi3", + "udivqi3", + "divdf3", + "divsf3", + "divmodsi4", + "divmodhi4", + "udivmodsi4", + "udivmodhi4", + "andsi3", + "andhi3", + "andqi3", + "iorsi3", + "iorhi3", + "iorqi3", + "xorsi3", + "xorhi3", + "xorqi3", + "negdi2", + "negsi2", + "neghi2", + "negqi2", + "negsf2", + "negdf2", + "negdf2+1", + "abssf2", + "absdf2", + "absdf2+1", + "sqrtsf2", + "sqrtdf2", + "sqrtdf2+1", + "sindf2", + "sinsf2", + "sinsf2+1", + "cosdf2", + "cossf2", + "cossf2+1", + "one_cmplsi2", + "one_cmplhi2", + "one_cmplqi2", + "ashldi3", + "ashldi3_const_int", + "ashldi3_non_const_int", + "ashlsi3", + "ashlhi3", + "ashlqi3", + "ashrdi3", + "ashrdi3_const_int", + "ashrdi3_non_const_int", + "ashrsi3", + "ashrhi3", + "ashrqi3", + "lshrdi3", + "lshrdi3_const_int", + "lshrdi3_non_const_int", + "lshrsi3", + "lshrhi3", + "lshrqi3", + "rotlsi3", + "rotlhi3", + "rotlqi3", + "rotrsi3", + "rotrhi3", + "rotrqi3", + "rotrqi3+1", + "rotrqi3+2", + "rotrqi3+3", + "seq-3", + "seq-2", + "seq-1", + "seq", + "seq+1", + "sne", + "sne+1", + "sgt", + "sgt+1", + "sgtu", + "sgtu+1", + "slt", + "slt+1", + "sltu", + "sltu+1", + "sge", + "sge+1", + "sgeu", + "sgeu+1", + "sle", + "sle+1", + "sleu", + "sleu+1", + "beq", + "beq+1", + "bne", + "bne+1", + "bgt", + "bgt+1", + "bgtu", + "bgtu+1", + "blt", + "blt+1", + "bltu", + "bltu+1", + "bge", + "bge+1", + "bgeu", + "bgeu+1", + "ble", + "ble+1", + "bleu", + "bleu+1", + "bleu+2", + "bleu+3", + "bleu+4", + "bleu+5", + "bleu+6", + "jump-5", + "jump-4", + "jump-3", + "jump-2", + "jump-1", + "jump", + "indirect_jump", + "casesi", + "casesi+1", + "tablejump", + "call_pop", + "call_pop+1", + "call-1", + "call", + "call+1", + "call_value_pop-1", + "call_value_pop", + "call_value_pop+1", + "call_value-1", + "call_value", + "call_value+1", + "untyped_call-1", + "untyped_call", + "untyped_call+1", + "untyped_return-1", + "untyped_return", + "update_return", + "return", + "nop", + "movstrsi", + "movstrsi+1", + "cmpstrsi", + "cmpstrsi+1", + "ffssi2-1", + "ffssi2", + "ffssi2+1", + "ffshi2", + "ffshi2+1", + "ffshi2+2", + "ffshi2+3", + "ffshi2+4", + "ffshi2+5", + "strlensi-4", + "strlensi-3", + "strlensi-2", + "strlensi-1", + "strlensi", + "strlensi+1", + }; +char **insn_name_ptr = insn_name; + +const int insn_n_operands[] = + { + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 4, + 4, + 4, + 4, + 4, + 3, + 4, + 4, + 4, + 3, + 2, + 2, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 3, + 8, + 8, + 6, + 6, + 5, + 5, + 5, + 5, + 5, + 5, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 3, + 3, + 3, + 3, + 2, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 4, + 4, + 4, + 4, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 4, + 3, + 3, + 2, + 3, + 3, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 7, + 3, + 1, + 4, + 4, + 4, + 2, + 2, + 2, + 5, + 5, + 5, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 1, + 0, + 0, + 5, + 5, + 5, + 5, + 4, + 3, + 3, + 3, + 3, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + }; + +const int insn_n_dups[] = + { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 7, + 7, + 5, + 5, + 1, + 1, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 2, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 2, + 3, + 3, + 3, + 2, + 0, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 5, + 1, + }; + +char *const insn_operand_constraint[][MAX_RECOG_OPERANDS] = + { + { "rm", }, + { "", }, + { "rm", }, + { "", }, + { "qm", }, + { "", }, + { "f", "=a", }, + { "", "", }, + { "f", "=a", }, + { "", "", }, + { "mr,r", "ri,mr", }, + { "", "", }, + { "mr,r", "ri,mr", }, + { "", "", }, + { "q,mq", "qm,nq", }, + { "", "", }, + { "f,fm", "fm,f", "", "=a,a", }, + { "f", "rm", "", "=a", }, + { "rm", "f", "", "=a", }, + { "f", "fm", "", "=a", }, + { "fm", "f", "", "=a", }, + { "f", "f", "=a", }, + { "f,fm", "fm,f", "", "=a,a", }, + { "f", "rm", "", "=a", }, + { "rm", "f", "", "=a", }, + { "f", "f", "=a", }, + { "", "", }, + { "", "", }, + { "", "", "", }, + { "", "", "", }, + { "", "", "", }, + { "", "", "", }, + { "%ro", "ri", }, + { "%ro", "ri", }, + { "%qm", "qi", }, + { "=<", "g", }, + { "=<", "ri", }, + { "", "", }, + { "=g,r", "ri,m", }, + { "=<", "g", }, + { "=g,r", "ri,m", }, + { "+g,r", "ri,m", }, + { "=<", "q", }, + { "=q,*r,qm", "*g,q,qn", }, + { "+q,qm", "*g,qn", }, + { "=<,<", "gF,f", }, + { "=*rfm,*rf,f,!*rm", "*rf,*rfm,fG,fF", }, + { "=<,<", "gF,f", }, + { "f", "f", }, + { "=*rfm,*rf,f,!*rm", "*rf,*rfm,fG,fF", }, + { "=<", "roiF", }, + { "=r,rm", "m,riF", }, + { "=r", "rm", }, + { "=r", "qm", }, + { "=r", "qm", }, + { "=r", "0", }, + { "=r", "0", }, + { "=r", "rm", }, + { "=r", "qm", }, + { "=r", "qm", }, + { "=fm,f", "f,fm", }, + { "", "", }, + { "=f,m", "0,f", "m,m", }, + { "", "", "", "", "", "", "", "", }, + { "", "", "", "", "", "", "", "", }, + { "", "", "", "", "", "", }, + { "", "", "", "", "", "", }, + { "=rm", "f", "m", "m", "=&q", }, + { "=rm", "f", "m", "m", "=&q", }, + { "", "", "", "", "", }, + { "", "", "", "", "", }, + { "=rm", "f", "m", "m", "=&q", }, + { "=rm", "f", "m", "m", "=&q", }, + { "", "", }, + { "", "", }, + { "", "", }, + { "", "", }, + { "=f", "rm", }, + { "=f", "rm", }, + { "=f", "rm", }, + { "=f", "rm", }, + { "=&r,ro", "%0,0", "o,riF", }, + { "=?r,rm,r", "%r,0,0", "ri,ri,rm", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=qm,q", "%0,0", "qn,qmn", }, + { "=r", "p", }, + { "", "", "", }, + { "", "", "", }, + { "=&r,ro", "0,0", "o,riF", }, + { "=rm,r", "0,0", "ri,rm", }, + { "=rm,r", "0,0", "ri,rm", }, + { "=qm,q", "0,0", "qn,qmn", }, + { "", "", "", }, + { "", "", "", }, + { "=r", "%0", "r", }, + { "=r,r", "%0,rm", "g,i", }, + { "=r", "%0", "r", }, + { "=r,r", "%0,rm", "g,i", }, + { "=a", "%0", "qm", }, + { "", "", "", }, + { "", "", "", }, + { "=a", "0", "qm", }, + { "=a", "0", "qm", }, + { "", "", "", }, + { "", "", "", }, + { "=a", "0", "rm", "=&d", }, + { "=a", "0", "rm", "=&d", }, + { "=a", "0", "rm", "=&d", }, + { "=a", "0", "rm", "=&d", }, + { "=r,r,rm,r", "%rm,qm,0,0", "L,K,ri,rm", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=qm,q", "%0,0", "qn,qmn", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=qm,q", "%0,0", "qn,qmn", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=qm,q", "%0,0", "qn,qm", }, + { "=&ro", "0", }, + { "=rm", "0", }, + { "=rm", "0", }, + { "=qm", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=rm", "0", }, + { "=rm", "0", }, + { "=qm", "0", }, + { "", "", "", }, + { "=&r", "0", "J", }, + { "=&r", "0", "c", }, + { "=r,rm", "r,0", "M,cI", }, + { "=rm", "0", "cI", }, + { "=qm", "0", "cI", }, + { "", "", "", }, + { "=&r", "0", "J", }, + { "=&r", "0", "c", }, + { "=rm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=qm", "0", "cI", }, + { "", "", "", }, + { "=&r", "0", "J", }, + { "=&r", "0", "c", }, + { "=rm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=qm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=qm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=qm", "0", "cI", }, + { "+rm", "", "r", "n", }, + { "=rm", "r", "0", }, + { "=rm", "0", "r", }, + { "r", "r", }, + { "r", "n", "n", }, + { "rm", "n", "n", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { "rm", }, + { "", "", "", "", "", "", "", }, + { "r", "", "=&r", }, + { "rm", }, + { "", "", "", "", }, + { "m", "g", "", "i", }, + { "", "g", "", "i", }, + { "", "", }, + { "m", "g", }, + { "", "g", }, + { "", "", "", "", "", }, + { "=rf", "m", "g", "", "i", }, + { "=rf", "", "g", "", "i", }, + { "", "", "", }, + { "=rf", "m", "g", }, + { "=rf", "", "g", }, + { "", "", "", }, + { "m", "o", "", }, + { "", "o", "", }, + { "", "", }, + { "m", }, + { 0 }, + { 0 }, + { "", "", "", "", "", }, + { "D", "S", "n", "i", "=&c", }, + { "", "", "", "", "", }, + { "=&r", "S", "D", "c", "i", }, + { "S", "D", "c", "i", }, + { "", "", "", }, + { "=&r", "rm", "=r", }, + { "", "", "", }, + { "=&r", "rm", "=r", }, + { "=f,f", "0,fm", "fm,0", "", }, + { "=f", "rm", "0", "", }, + { "=f,f", "fm,0", "0,f", "", }, + { "=f", "0", "rm", "", }, + { "=f,f", "0,f", "fm,0", "", }, + { "=f,f", "0,fm", "fm,0", "", }, + { "=f", "rm", "0", "", }, + { "=f", "0", "rm", "", }, + { "", "", "", "", }, + { "=&c", "D", "a", "i", }, + }; + +const enum machine_mode insn_operand_mode[][MAX_RECOG_OPERANDS] = + { + { SImode, }, + { SImode, }, + { HImode, }, + { HImode, }, + { QImode, }, + { QImode, }, + { SFmode, HImode, }, + { SFmode, HImode, }, + { DFmode, HImode, }, + { DFmode, HImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { DFmode, DFmode, VOIDmode, HImode, }, + { DFmode, SImode, VOIDmode, HImode, }, + { SImode, DFmode, VOIDmode, HImode, }, + { DFmode, SFmode, VOIDmode, HImode, }, + { SFmode, DFmode, VOIDmode, HImode, }, + { DFmode, DFmode, HImode, }, + { SFmode, SFmode, VOIDmode, HImode, }, + { SFmode, SImode, VOIDmode, HImode, }, + { SImode, SFmode, VOIDmode, HImode, }, + { SFmode, SFmode, HImode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, HImode, }, + { DFmode, DFmode, HImode, }, + { SFmode, SFmode, HImode, }, + { SFmode, SFmode, HImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { SFmode, SFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { DFmode, DFmode, }, + { DFmode, DFmode, }, + { DImode, DImode, }, + { DImode, DImode, }, + { SImode, HImode, }, + { HImode, QImode, }, + { SImode, QImode, }, + { DImode, SImode, }, + { DImode, SImode, }, + { SImode, HImode, }, + { HImode, QImode, }, + { SImode, QImode, }, + { DFmode, SFmode, }, + { SFmode, DFmode, }, + { SFmode, DFmode, SFmode, }, + { SImode, DFmode, VOIDmode, VOIDmode, VOIDmode, VOIDmode, VOIDmode, SImode, }, + { SImode, SFmode, VOIDmode, VOIDmode, VOIDmode, VOIDmode, VOIDmode, SImode, }, + { DImode, DFmode, VOIDmode, VOIDmode, VOIDmode, SImode, }, + { DImode, SFmode, VOIDmode, VOIDmode, VOIDmode, SImode, }, + { DImode, DFmode, SImode, SImode, SImode, }, + { DImode, SFmode, SImode, SImode, SImode, }, + { SImode, DFmode, VOIDmode, VOIDmode, SImode, }, + { SImode, SFmode, VOIDmode, VOIDmode, SImode, }, + { SImode, DFmode, SImode, SImode, SImode, }, + { SImode, SFmode, SImode, SImode, SImode, }, + { SFmode, SImode, }, + { SFmode, DImode, }, + { DFmode, SImode, }, + { DFmode, DImode, }, + { DFmode, DImode, }, + { SFmode, DImode, }, + { DFmode, SImode, }, + { SFmode, SImode, }, + { DImode, DImode, DImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { DImode, DImode, DImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, HImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, QImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { QImode, HImode, QImode, }, + { QImode, HImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { SImode, SImode, SImode, SImode, }, + { HImode, HImode, HImode, HImode, }, + { SImode, SImode, SImode, SImode, }, + { HImode, HImode, HImode, HImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { DImode, DImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { DFmode, SFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { DFmode, SFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { DFmode, SFmode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { DFmode, SFmode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { DFmode, SFmode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, VOIDmode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, }, + { SImode, SImode, SImode, }, + { QImode, SImode, SImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { SImode, }, + { SImode, SImode, SImode, VOIDmode, VOIDmode, VOIDmode, SImode, }, + { SImode, VOIDmode, SImode, }, + { SImode, }, + { QImode, SImode, VOIDmode, SImode, }, + { QImode, SImode, VOIDmode, SImode, }, + { SImode, SImode, VOIDmode, SImode, }, + { QImode, SImode, }, + { QImode, SImode, }, + { SImode, SImode, }, + { VOIDmode, QImode, SImode, VOIDmode, SImode, }, + { VOIDmode, QImode, SImode, VOIDmode, SImode, }, + { VOIDmode, SImode, SImode, VOIDmode, SImode, }, + { VOIDmode, QImode, SImode, }, + { VOIDmode, QImode, SImode, }, + { VOIDmode, SImode, SImode, }, + { QImode, BLKmode, VOIDmode, }, + { QImode, DImode, VOIDmode, }, + { SImode, DImode, VOIDmode, }, + { BLKmode, VOIDmode, }, + { SImode, }, + { VOIDmode }, + { VOIDmode }, + { BLKmode, BLKmode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, SImode, }, + { SImode, BLKmode, BLKmode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, HImode, }, + { DFmode, DFmode, DFmode, DFmode, }, + { DFmode, SImode, DFmode, DFmode, }, + { DFmode, SFmode, DFmode, DFmode, }, + { DFmode, DFmode, SImode, DFmode, }, + { DFmode, DFmode, SFmode, DFmode, }, + { SFmode, SFmode, SFmode, SFmode, }, + { SFmode, SImode, SFmode, SFmode, }, + { SFmode, SFmode, SImode, SFmode, }, + { SImode, BLKmode, QImode, SImode, }, + { SImode, SImode, QImode, SImode, }, + }; + +const char insn_operand_strict_low[][MAX_RECOG_OPERANDS] = + { + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 1, 0, }, + { 0, 0, }, + { 0, 0, }, + { 1, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0, }, + { 0, 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, }, + { 0 }, + { 0 }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + }; + +extern int nonimmediate_operand (); +extern int register_operand (); +extern int scratch_operand (); +extern int general_operand (); +extern int VOIDmode_compare_op (); +extern int push_operand (); +extern int memory_operand (); +extern int address_operand (); +extern int nonmemory_operand (); +extern int const_int_operand (); +extern int indirect_operand (); +extern int immediate_operand (); +extern int call_insn_operand (); +extern int symbolic_operand (); +extern int binary_387_op (); + +int (*const insn_operand_predicate[][MAX_RECOG_OPERANDS])() = + { + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { register_operand, scratch_operand, }, + { register_operand, scratch_operand, }, + { register_operand, scratch_operand, }, + { register_operand, scratch_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, nonimmediate_operand, VOIDmode_compare_op, scratch_operand, }, + { register_operand, nonimmediate_operand, VOIDmode_compare_op, scratch_operand, }, + { nonimmediate_operand, register_operand, VOIDmode_compare_op, scratch_operand, }, + { register_operand, nonimmediate_operand, VOIDmode_compare_op, scratch_operand, }, + { nonimmediate_operand, register_operand, VOIDmode_compare_op, scratch_operand, }, + { register_operand, register_operand, scratch_operand, }, + { nonimmediate_operand, nonimmediate_operand, VOIDmode_compare_op, scratch_operand, }, + { register_operand, nonimmediate_operand, VOIDmode_compare_op, scratch_operand, }, + { nonimmediate_operand, register_operand, VOIDmode_compare_op, scratch_operand, }, + { register_operand, register_operand, scratch_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, register_operand, scratch_operand, }, + { register_operand, register_operand, scratch_operand, }, + { register_operand, register_operand, scratch_operand, }, + { register_operand, register_operand, scratch_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { register_operand, register_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, general_operand, }, + { nonimmediate_operand, register_operand, }, + { nonimmediate_operand, register_operand, memory_operand, }, + { general_operand, register_operand, 0, 0, 0, 0, 0, scratch_operand, }, + { general_operand, register_operand, 0, 0, 0, 0, 0, scratch_operand, }, + { general_operand, register_operand, 0, 0, 0, scratch_operand, }, + { general_operand, register_operand, 0, 0, 0, scratch_operand, }, + { general_operand, register_operand, memory_operand, memory_operand, scratch_operand, }, + { general_operand, register_operand, memory_operand, memory_operand, scratch_operand, }, + { general_operand, register_operand, 0, 0, scratch_operand, }, + { general_operand, register_operand, 0, 0, scratch_operand, }, + { general_operand, register_operand, memory_operand, memory_operand, scratch_operand, }, + { general_operand, register_operand, memory_operand, memory_operand, scratch_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { register_operand, address_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, register_operand, general_operand, register_operand, }, + { register_operand, register_operand, general_operand, register_operand, }, + { register_operand, register_operand, general_operand, register_operand, }, + { register_operand, register_operand, general_operand, register_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { register_operand, register_operand, nonmemory_operand, }, + { register_operand, register_operand, const_int_operand, }, + { register_operand, register_operand, register_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { register_operand, register_operand, nonmemory_operand, }, + { register_operand, register_operand, const_int_operand, }, + { register_operand, register_operand, register_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { register_operand, register_operand, nonmemory_operand, }, + { register_operand, register_operand, const_int_operand, }, + { register_operand, register_operand, register_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, 0, general_operand, const_int_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, const_int_operand, const_int_operand, }, + { general_operand, const_int_operand, const_int_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { general_operand, }, + { general_operand, general_operand, general_operand, 0, 0, 0, scratch_operand, }, + { register_operand, 0, scratch_operand, }, + { general_operand, }, + { indirect_operand, general_operand, 0, immediate_operand, }, + { call_insn_operand, general_operand, 0, immediate_operand, }, + { symbolic_operand, general_operand, 0, immediate_operand, }, + { indirect_operand, general_operand, }, + { call_insn_operand, general_operand, }, + { symbolic_operand, general_operand, }, + { 0, indirect_operand, general_operand, 0, immediate_operand, }, + { 0, call_insn_operand, general_operand, 0, immediate_operand, }, + { 0, symbolic_operand, general_operand, 0, immediate_operand, }, + { 0, indirect_operand, general_operand, }, + { 0, call_insn_operand, general_operand, }, + { 0, symbolic_operand, general_operand, }, + { indirect_operand, memory_operand, 0, }, + { call_insn_operand, memory_operand, 0, }, + { symbolic_operand, memory_operand, 0, }, + { memory_operand, 0, }, + { memory_operand, }, + { 0 }, + { 0 }, + { memory_operand, memory_operand, const_int_operand, const_int_operand, scratch_operand, }, + { address_operand, address_operand, const_int_operand, immediate_operand, scratch_operand, }, + { general_operand, general_operand, general_operand, general_operand, immediate_operand, }, + { general_operand, address_operand, address_operand, register_operand, immediate_operand, }, + { address_operand, address_operand, register_operand, immediate_operand, }, + { general_operand, general_operand, scratch_operand, }, + { register_operand, general_operand, scratch_operand, }, + { general_operand, general_operand, scratch_operand, }, + { register_operand, general_operand, scratch_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, general_operand, register_operand, immediate_operand, }, + { register_operand, address_operand, register_operand, immediate_operand, }, + }; + +const int insn_n_alternatives[] = + { + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 2, + 0, + 2, + 0, + 2, + 0, + 2, + 1, + 1, + 1, + 1, + 1, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 0, + 2, + 1, + 2, + 2, + 1, + 3, + 2, + 2, + 4, + 2, + 1, + 4, + 1, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 0, + 2, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 2, + 3, + 2, + 2, + 1, + 0, + 0, + 2, + 2, + 2, + 2, + 0, + 0, + 1, + 2, + 1, + 2, + 1, + 0, + 0, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 1, + 4, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 2, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 1, + 0, + 1, + 2, + 1, + 2, + 1, + 2, + 2, + 1, + 1, + 0, + 1, + }; diff --git a/gnu/usr.bin/cc/lib/insn-peep.c b/gnu/usr.bin/cc/lib/insn-peep.c new file mode 100644 index 000000000000..37136c4333d0 --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-peep.c @@ -0,0 +1,28 @@ +/* Generated automatically by the program `genpeep' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "output.h" +#include "real.h" + +extern rtx peep_operand[]; + +#define operands peep_operand + +rtx +peephole (ins1) + rtx ins1; +{ + rtx insn, x, pat; + int i; + + if (NEXT_INSN (ins1) + && GET_CODE (NEXT_INSN (ins1)) == BARRIER) + return 0; + + return 0; +} + +rtx peep_operand[2]; diff --git a/gnu/usr.bin/cc/lib/insn-recog.c b/gnu/usr.bin/cc/lib/insn-recog.c new file mode 100644 index 000000000000..bca21b305fe8 --- /dev/null +++ b/gnu/usr.bin/cc/lib/insn-recog.c @@ -0,0 +1,6158 @@ +/* Generated automatically by the program `genrecog' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "recog.h" +#include "real.h" +#include "output.h" +#include "flags.h" + + +/* `recog' contains a decision tree + that recognizes whether the rtx X0 is a valid instruction. + + recog returns -1 if the rtx is not valid. + If the rtx is valid, recog returns a nonnegative number + which is the insn code number for the pattern that matched. + This is the same as the order in the machine description of + the entry that matched. This number can be used as an index into + entry that matched. This number can be used as an index into various + insn_* tables, such as insn_templates, insn_outfun, and insn_n_operands + (found in insn-output.c). + + The third argument to recog is an optional pointer to an int. + If present, recog will accept a pattern if it matches except for + missing CLOBBER expressions at the end. In that case, the value + pointed to by the optional pointer will be set to the number of + CLOBBERs that need to be added (it should be initialized to zero by + the caller). If it is set nonzero, the caller should allocate a + PARALLEL of the appropriate size, copy the initial entries, and call + add_clobbers (found in insn-emit.c) to fill in the CLOBBERs.*/ + +rtx recog_operand[MAX_RECOG_OPERANDS]; + +rtx *recog_operand_loc[MAX_RECOG_OPERANDS]; + +rtx *recog_dup_loc[MAX_DUP_OPERANDS]; + +char recog_dup_num[MAX_DUP_OPERANDS]; + +#define operands recog_operand + +int +recog_1 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SImode: + if (nonimmediate_operand (x1, SImode)) + { + ro[0] = x1; + return 0; + } + break; + case HImode: + if (nonimmediate_operand (x1, HImode)) + { + ro[0] = x1; + return 2; + } + break; + case QImode: + if (nonimmediate_operand (x1, QImode)) + { + ro[0] = x1; + return 4; + } + break; + case SFmode: + if (pnum_clobbers != 0 && register_operand (x1, SFmode)) + { + ro[0] = x1; + if (TARGET_80387 && ! TARGET_IEEE_FP) + { + *pnum_clobbers = 1; + return 6; + } + } + break; + case DFmode: + if (pnum_clobbers != 0 && register_operand (x1, DFmode)) + { + ro[0] = x1; + if (TARGET_80387 && ! TARGET_IEEE_FP) + { + *pnum_clobbers = 1; + return 8; + } + } + } + switch (GET_CODE (x1)) + { + case COMPARE: + goto L30; + case ZERO_EXTRACT: + goto L813; + } + L52: + if (VOIDmode_compare_op (x1, VOIDmode)) + { + ro[2] = x1; + goto L82; + } + L125: + switch (GET_MODE (x1)) + { + case CCFPEQmode: + switch (GET_CODE (x1)) + { + case COMPARE: + goto L126; + } + break; + case SImode: + switch (GET_CODE (x1)) + { + case AND: + goto L187; + } + break; + case HImode: + switch (GET_CODE (x1)) + { + case AND: + goto L192; + } + break; + case QImode: + if (GET_CODE (x1) == AND && 1) + goto L197; + } + goto ret0; + + L30: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[0] = x2; + goto L31; + } + break; + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[0] = x2; + goto L36; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[0] = x2; + goto L41; + } + } + goto L52; + + L31: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return 10; + } + goto L52; + + L36: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return 12; + } + goto L52; + + L41: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return 14; + } + goto L52; + + L813: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (register_operand (x2, SImode)) + { + ro[0] = x2; + goto L814; + } + break; + case QImode: + if (general_operand (x2, QImode)) + { + ro[0] = x2; + goto L826; + } + } + goto L52; + + L814: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) != CONST_INT) + { + goto L52; + } + if (XWINT (x2, 0) == 1 && 1) + goto L815; + L820: + ro[1] = x2; + goto L821; + + L815: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + if (GET_CODE (operands[1]) != CONST_INT) + return 167; + } + x2 = XEXP (x1, 1); + goto L820; + + L821: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + return 168; + } + goto L52; + + L826: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[1] = x2; + goto L827; + } + goto L52; + + L827: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + if (GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])) + return 169; + } + goto L52; + + L82: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DFmode: + switch (GET_CODE (x2)) + { + case FLOAT: + goto L83; + case FLOAT_EXTEND: + goto L113; + case SUBREG: + case REG: + case MEM: + if (nonimmediate_operand (x2, DFmode)) + { + ro[0] = x2; + goto L54; + } + } + L67: + if (register_operand (x2, DFmode)) + { + ro[0] = x2; + goto L68; + } + break; + case SFmode: + if (GET_CODE (x2) == FLOAT && 1) + goto L169; + if (nonimmediate_operand (x2, SFmode)) + { + ro[0] = x2; + goto L140; + } + L153: + if (register_operand (x2, SFmode)) + { + ro[0] = x2; + goto L154; + } + } + goto L125; + + L83: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, SImode)) + { + ro[0] = x3; + goto L84; + } + goto L125; + + L84: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && register_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 18; + } + } + goto L125; + + L113: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, SFmode)) + { + ro[0] = x3; + goto L114; + } + goto L125; + + L114: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && register_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 20; + } + } + goto L125; + + L54: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && nonimmediate_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)) + { + *pnum_clobbers = 1; + return 16; + } + } + x2 = XEXP (x1, 0); + goto L67; + + L68: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != DFmode) + { + goto L125; + } + switch (GET_CODE (x2)) + { + case FLOAT: + goto L69; + case FLOAT_EXTEND: + goto L99; + } + goto L125; + + L69: + x3 = XEXP (x2, 0); + if (pnum_clobbers != 0 && nonimmediate_operand (x3, SImode)) + { + ro[1] = x3; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 17; + } + } + goto L125; + + L99: + x3 = XEXP (x2, 0); + if (pnum_clobbers != 0 && nonimmediate_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 19; + } + } + goto L125; + + L169: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, SImode)) + { + ro[0] = x3; + goto L170; + } + goto L125; + + L170: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && register_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 24; + } + } + goto L125; + + L140: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && nonimmediate_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)) + { + *pnum_clobbers = 1; + return 22; + } + } + x2 = XEXP (x1, 0); + goto L153; + + L154: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SFmode && GET_CODE (x2) == FLOAT && 1) + goto L155; + goto L125; + + L155: + x3 = XEXP (x2, 0); + if (pnum_clobbers != 0 && nonimmediate_operand (x3, SImode)) + { + ro[1] = x3; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 23; + } + } + goto L125; + + L126: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DFmode: + if (register_operand (x2, DFmode)) + { + ro[0] = x2; + goto L127; + } + break; + case SFmode: + if (register_operand (x2, SFmode)) + { + ro[0] = x2; + goto L183; + } + } + goto ret0; + + L127: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && register_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 21; + } + } + goto ret0; + + L183: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && register_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 25; + } + } + goto ret0; + + L187: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L188; + } + goto ret0; + + L188: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 32; + } + goto ret0; + + L192: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[0] = x2; + goto L193; + } + goto ret0; + + L193: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 33; + } + goto ret0; + + L197: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[0] = x2; + goto L198; + } + goto ret0; + + L198: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 34; + } + goto ret0; + ret0: return -1; +} + +int +recog_2 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 1); + x2 = XEXP (x1, 0); + switch (GET_CODE (x2)) + { + case EQ: + goto L882; + case NE: + goto L891; + case GT: + goto L900; + case GTU: + goto L909; + case LT: + goto L918; + case LTU: + goto L927; + case GE: + goto L936; + case GEU: + goto L945; + case LE: + goto L954; + case LEU: + goto L963; + } + goto ret0; + + L882: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L883; + goto ret0; + + L883: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L884; + goto ret0; + + L884: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L885; + case PC: + goto L975; + } + goto ret0; + + L885: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L886; + + L886: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 191; + goto ret0; + + L975: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L976; + goto ret0; + + L976: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 210; + + L891: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L892; + goto ret0; + + L892: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L893; + goto ret0; + + L893: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L894; + case PC: + goto L984; + } + goto ret0; + + L894: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L895; + + L895: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 193; + goto ret0; + + L984: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L985; + goto ret0; + + L985: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 211; + + L900: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L901; + goto ret0; + + L901: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L902; + goto ret0; + + L902: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L903; + case PC: + goto L993; + } + goto ret0; + + L903: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L904; + + L904: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 195; + goto ret0; + + L993: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L994; + goto ret0; + + L994: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 212; + + L909: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L910; + goto ret0; + + L910: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L911; + goto ret0; + + L911: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L912; + case PC: + goto L1002; + } + goto ret0; + + L912: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L913; + + L913: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 197; + goto ret0; + + L1002: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1003; + goto ret0; + + L1003: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 213; + + L918: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L919; + goto ret0; + + L919: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L920; + goto ret0; + + L920: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L921; + case PC: + goto L1011; + } + goto ret0; + + L921: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L922; + + L922: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 199; + goto ret0; + + L1011: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1012; + goto ret0; + + L1012: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 214; + + L927: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L928; + goto ret0; + + L928: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L929; + goto ret0; + + L929: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L930; + case PC: + goto L1020; + } + goto ret0; + + L930: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L931; + + L931: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 201; + goto ret0; + + L1020: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1021; + goto ret0; + + L1021: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 215; + + L936: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L937; + goto ret0; + + L937: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L938; + goto ret0; + + L938: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L939; + case PC: + goto L1029; + } + goto ret0; + + L939: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L940; + + L940: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 203; + goto ret0; + + L1029: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1030; + goto ret0; + + L1030: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 216; + + L945: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L946; + goto ret0; + + L946: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L947; + goto ret0; + + L947: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L948; + case PC: + goto L1038; + } + goto ret0; + + L948: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L949; + + L949: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 205; + goto ret0; + + L1038: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1039; + goto ret0; + + L1039: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 217; + + L954: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L955; + goto ret0; + + L955: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L956; + goto ret0; + + L956: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L957; + case PC: + goto L1047; + } + goto ret0; + + L957: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L958; + + L958: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 207; + goto ret0; + + L1047: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1048; + goto ret0; + + L1048: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 218; + + L963: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L964; + goto ret0; + + L964: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L965; + goto ret0; + + L965: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L966; + case PC: + goto L1056; + } + goto ret0; + + L966: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L967; + + L967: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 209; + goto ret0; + + L1056: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1057; + goto ret0; + + L1057: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 219; + ret0: return -1; +} + +int +recog_3 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 0); + switch (GET_MODE (x1)) + { + case SImode: + switch (GET_CODE (x1)) + { + case MEM: + if (push_operand (x1, SImode)) + { + ro[0] = x1; + goto L201; + } + break; + case ZERO_EXTRACT: + goto L792; + } + L208: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + goto L257; + } + L431: + if (register_operand (x1, SImode)) + { + ro[0] = x1; + goto L432; + } + L439: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + goto L440; + } + break; + case HImode: + if (GET_CODE (x1) == MEM && push_operand (x1, HImode)) + { + ro[0] = x1; + goto L212; + } + L214: + if (general_operand (x1, HImode)) + { + ro[0] = x1; + goto L261; + } + break; + case QImode: + if (GET_CODE (x1) == MEM && push_operand (x1, QImode)) + { + ro[0] = x1; + goto L222; + } + L224: + if (general_operand (x1, QImode)) + { + ro[0] = x1; + goto L427; + } + L829: + if (register_operand (x1, QImode)) + { + ro[0] = x1; + goto L830; + } + break; + case SFmode: + if (GET_CODE (x1) == MEM && push_operand (x1, SFmode)) + { + ro[0] = x1; + goto L232; + } + L234: + if (general_operand (x1, SFmode)) + { + ro[0] = x1; + goto L235; + } + L399: + if (register_operand (x1, SFmode)) + { + ro[0] = x1; + goto L400; + } + break; + case DFmode: + if (GET_CODE (x1) == MEM && push_operand (x1, DFmode)) + { + ro[0] = x1; + goto L238; + } + L247: + if (general_operand (x1, DFmode)) + { + ro[0] = x1; + goto L289; + } + L395: + if (register_operand (x1, DFmode)) + { + ro[0] = x1; + goto L396; + } + break; + case DImode: + if (GET_CODE (x1) == MEM && push_operand (x1, DImode)) + { + ro[0] = x1; + goto L251; + } + L253: + if (general_operand (x1, DImode)) + { + ro[0] = x1; + goto L412; + } + L268: + if (register_operand (x1, DImode)) + { + ro[0] = x1; + goto L269; + } + } + switch (GET_CODE (x1)) + { + case CC0: + goto L2; + case STRICT_LOW_PART: + goto L218; + case PC: + goto L1081; + } + L1147: + ro[0] = x1; + goto L1148; + L1236: + switch (GET_MODE (x1)) + { + case SImode: + if (register_operand (x1, SImode)) + { + ro[0] = x1; + goto L1237; + } + break; + case HImode: + if (register_operand (x1, HImode)) + { + ro[0] = x1; + goto L1252; + } + break; + case DFmode: + if (register_operand (x1, DFmode)) + { + ro[0] = x1; + goto L1258; + } + break; + case SFmode: + if (register_operand (x1, SFmode)) + { + ro[0] = x1; + goto L1287; + } + } + goto ret0; + + L201: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + goto L205; + x1 = XEXP (x0, 0); + goto L208; + + L205: + ro[1] = x1; + if (! TARGET_486) + return 35; + L206: + ro[1] = x1; + if (TARGET_486) + return 36; + x1 = XEXP (x0, 0); + goto L208; + + L792: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && general_operand (x2, SImode)) + { + ro[0] = x2; + goto L793; + } + goto L1147; + + L793: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 1 && 1) + goto L794; + goto L1147; + + L794: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L795; + } + goto L1147; + + L795: + x1 = XEXP (x0, 1); + if (GET_CODE (x1) == CONST_INT && 1) + { + ro[3] = x1; + if (! TARGET_486 && GET_CODE (operands[2]) != CONST_INT) + return 164; + } + x1 = XEXP (x0, 0); + goto L1147; + + L257: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SImode: + switch (GET_CODE (x1)) + { + case ZERO_EXTEND: + goto L258; + case SIGN_EXTEND: + goto L278; + case PLUS: + goto L418; + } + } + if (general_operand (x1, SImode)) + { + ro[1] = x1; + return 38; + } + x1 = XEXP (x0, 0); + goto L431; + + L258: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[1] = x2; + return 52; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 54; + } + } + x1 = XEXP (x0, 0); + goto L431; + + L278: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[1] = x2; + return 57; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 59; + } + } + x1 = XEXP (x0, 0); + goto L431; + + L418: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L419; + } + x1 = XEXP (x0, 0); + goto L431; + + L419: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 82; + } + x1 = XEXP (x0, 0); + goto L431; + + L432: + x1 = XEXP (x0, 1); + if (address_operand (x1, QImode)) + { + ro[1] = x1; + return 85; + } + x1 = XEXP (x0, 0); + goto L439; + + L440: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != SImode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + switch (GET_CODE (x1)) + { + case MINUS: + goto L441; + case MULT: + goto L468; + case AND: + goto L541; + case IOR: + goto L556; + case XOR: + goto L799; + case NEG: + goto L590; + case NOT: + goto L667; + case ASHIFT: + goto L692; + case ASHIFTRT: + goto L720; + case LSHIFTRT: + goto L748; + case ROTATE: + goto L763; + case ROTATERT: + goto L778; + } + x1 = XEXP (x0, 0); + goto L1147; + + L441: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L442; + } + x1 = XEXP (x0, 0); + goto L1147; + + L442: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 89; + } + x1 = XEXP (x0, 0); + goto L1147; + + L468: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L469; + } + x1 = XEXP (x0, 0); + goto L1147; + + L469: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + goto L475; + x1 = XEXP (x0, 0); + goto L1147; + + L475: + ro[2] = x2; + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80) + return 96; + L476: + ro[2] = x2; + return 97; + + L541: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L542; + } + x1 = XEXP (x0, 0); + goto L1147; + + L542: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 109; + } + x1 = XEXP (x0, 0); + goto L1147; + + L556: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L557; + } + x1 = XEXP (x0, 0); + goto L1147; + + L557: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 112; + } + x1 = XEXP (x0, 0); + goto L1147; + + L799: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == ASHIFT && 1) + goto L800; + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L807; + } + x1 = XEXP (x0, 0); + goto L1147; + + L800: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 1 && 1) + goto L801; + x1 = XEXP (x0, 0); + goto L1147; + + L801: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L802; + } + x1 = XEXP (x0, 0); + goto L1147; + + L802: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + if (! TARGET_486 && GET_CODE (operands[1]) != CONST_INT) + return 165; + } + x1 = XEXP (x0, 0); + goto L1147; + + L807: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == ASHIFT && 1) + goto L808; + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 115; + } + x1 = XEXP (x0, 0); + goto L1147; + + L808: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 1 && 1) + goto L809; + x1 = XEXP (x0, 0); + goto L1147; + + L809: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + if (! TARGET_486 && GET_CODE (operands[2]) != CONST_INT) + return 166; + } + x1 = XEXP (x0, 0); + goto L1147; + + L590: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 119; + } + x1 = XEXP (x0, 0); + goto L1147; + + L667: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 137; + } + x1 = XEXP (x0, 0); + goto L1147; + + L692: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L693; + } + x1 = XEXP (x0, 0); + goto L1147; + + L693: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, SImode)) + { + ro[2] = x2; + return 143; + } + x1 = XEXP (x0, 0); + goto L1147; + + L720: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L721; + } + x1 = XEXP (x0, 0); + goto L1147; + + L721: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, SImode)) + { + ro[2] = x2; + return 149; + } + x1 = XEXP (x0, 0); + goto L1147; + + L748: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L749; + } + x1 = XEXP (x0, 0); + goto L1147; + + L749: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, SImode)) + { + ro[2] = x2; + return 155; + } + x1 = XEXP (x0, 0); + goto L1147; + + L763: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L764; + } + x1 = XEXP (x0, 0); + goto L1147; + + L764: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, SImode)) + { + ro[2] = x2; + return 158; + } + x1 = XEXP (x0, 0); + goto L1147; + + L778: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L779; + } + x1 = XEXP (x0, 0); + goto L1147; + + L779: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, SImode)) + { + ro[2] = x2; + return 161; + } + x1 = XEXP (x0, 0); + goto L1147; + + L212: + x1 = XEXP (x0, 1); + if (general_operand (x1, HImode)) + { + ro[1] = x1; + return 39; + } + x1 = XEXP (x0, 0); + goto L214; + + L261: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case HImode: + switch (GET_CODE (x1)) + { + case ZERO_EXTEND: + goto L262; + case SIGN_EXTEND: + goto L282; + case PLUS: + goto L423; + case MINUS: + goto L446; + case AND: + goto L546; + case IOR: + goto L561; + case XOR: + goto L576; + case NEG: + goto L594; + case NOT: + goto L671; + case ASHIFT: + goto L697; + case ASHIFTRT: + goto L725; + case LSHIFTRT: + goto L753; + case ROTATE: + goto L768; + case ROTATERT: + goto L783; + } + break; + case SImode: + if (GET_CODE (x1) == MULT && 1) + goto L480; + } + if (general_operand (x1, HImode)) + { + ro[1] = x1; + return 40; + } + x1 = XEXP (x0, 0); + goto L1147; + + L262: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 53; + } + x1 = XEXP (x0, 0); + goto L1147; + + L282: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 58; + } + x1 = XEXP (x0, 0); + goto L1147; + + L423: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L424; + } + x1 = XEXP (x0, 0); + goto L1147; + + L424: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 83; + } + x1 = XEXP (x0, 0); + goto L1147; + + L446: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L447; + } + x1 = XEXP (x0, 0); + goto L1147; + + L447: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 90; + } + x1 = XEXP (x0, 0); + goto L1147; + + L546: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L547; + } + x1 = XEXP (x0, 0); + goto L1147; + + L547: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 110; + } + x1 = XEXP (x0, 0); + goto L1147; + + L561: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L562; + } + x1 = XEXP (x0, 0); + goto L1147; + + L562: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 113; + } + x1 = XEXP (x0, 0); + goto L1147; + + L576: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L577; + } + x1 = XEXP (x0, 0); + goto L1147; + + L577: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 116; + } + x1 = XEXP (x0, 0); + goto L1147; + + L594: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 120; + } + x1 = XEXP (x0, 0); + goto L1147; + + L671: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 138; + } + x1 = XEXP (x0, 0); + goto L1147; + + L697: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L698; + } + x1 = XEXP (x0, 0); + goto L1147; + + L698: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, HImode)) + { + ro[2] = x2; + return 144; + } + x1 = XEXP (x0, 0); + goto L1147; + + L725: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L726; + } + x1 = XEXP (x0, 0); + goto L1147; + + L726: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, HImode)) + { + ro[2] = x2; + return 150; + } + x1 = XEXP (x0, 0); + goto L1147; + + L753: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L754; + } + x1 = XEXP (x0, 0); + goto L1147; + + L754: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, HImode)) + { + ro[2] = x2; + return 156; + } + x1 = XEXP (x0, 0); + goto L1147; + + L768: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L769; + } + x1 = XEXP (x0, 0); + goto L1147; + + L769: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, HImode)) + { + ro[2] = x2; + return 159; + } + x1 = XEXP (x0, 0); + goto L1147; + + L783: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L784; + } + x1 = XEXP (x0, 0); + goto L1147; + + L784: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, HImode)) + { + ro[2] = x2; + return 162; + } + x1 = XEXP (x0, 0); + goto L1147; + + L480: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == ZERO_EXTEND && 1) + goto L481; + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L457; + } + x1 = XEXP (x0, 0); + goto L1147; + + L481: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, QImode)) + { + ro[1] = x3; + goto L482; + } + x1 = XEXP (x0, 0); + goto L1147; + + L482: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == ZERO_EXTEND && 1) + goto L483; + x1 = XEXP (x0, 0); + goto L1147; + + L483: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, QImode)) + { + ro[2] = x3; + return 98; + } + x1 = XEXP (x0, 0); + goto L1147; + + L457: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + goto L463; + x1 = XEXP (x0, 0); + goto L1147; + + L463: + ro[2] = x2; + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80) + return 94; + L464: + ro[2] = x2; + return 95; + + L222: + x1 = XEXP (x0, 1); + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 42; + } + x1 = XEXP (x0, 0); + goto L224; + + L427: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case QImode: + switch (GET_CODE (x1)) + { + case PLUS: + goto L428; + case MINUS: + goto L451; + case DIV: + goto L487; + case UDIV: + goto L492; + case AND: + goto L551; + case IOR: + goto L566; + case XOR: + goto L581; + case NEG: + goto L598; + case NOT: + goto L675; + case ASHIFT: + goto L702; + case ASHIFTRT: + goto L730; + case LSHIFTRT: + goto L758; + case ROTATE: + goto L773; + case ROTATERT: + goto L788; + } + } + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 43; + } + x1 = XEXP (x0, 0); + goto L829; + + L428: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L429; + } + x1 = XEXP (x0, 0); + goto L829; + + L429: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 84; + } + x1 = XEXP (x0, 0); + goto L829; + + L451: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L452; + } + x1 = XEXP (x0, 0); + goto L829; + + L452: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 91; + } + x1 = XEXP (x0, 0); + goto L829; + + L487: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L488; + } + x1 = XEXP (x0, 0); + goto L829; + + L488: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 101; + } + x1 = XEXP (x0, 0); + goto L829; + + L492: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L493; + } + x1 = XEXP (x0, 0); + goto L829; + + L493: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 102; + } + x1 = XEXP (x0, 0); + goto L829; + + L551: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L552; + } + x1 = XEXP (x0, 0); + goto L829; + + L552: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 111; + } + x1 = XEXP (x0, 0); + goto L829; + + L566: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L567; + } + x1 = XEXP (x0, 0); + goto L829; + + L567: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 114; + } + x1 = XEXP (x0, 0); + goto L829; + + L581: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L582; + } + x1 = XEXP (x0, 0); + goto L829; + + L582: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 117; + } + x1 = XEXP (x0, 0); + goto L829; + + L598: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 121; + } + x1 = XEXP (x0, 0); + goto L829; + + L675: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 139; + } + x1 = XEXP (x0, 0); + goto L829; + + L702: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L703; + } + x1 = XEXP (x0, 0); + goto L829; + + L703: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, QImode)) + { + ro[2] = x2; + return 145; + } + x1 = XEXP (x0, 0); + goto L829; + + L730: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L731; + } + x1 = XEXP (x0, 0); + goto L829; + + L731: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, QImode)) + { + ro[2] = x2; + return 151; + } + x1 = XEXP (x0, 0); + goto L829; + + L758: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L759; + } + x1 = XEXP (x0, 0); + goto L829; + + L759: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, QImode)) + { + ro[2] = x2; + return 157; + } + x1 = XEXP (x0, 0); + goto L829; + + L773: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L774; + } + x1 = XEXP (x0, 0); + goto L829; + + L774: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, QImode)) + { + ro[2] = x2; + return 160; + } + x1 = XEXP (x0, 0); + goto L829; + + L788: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L789; + } + x1 = XEXP (x0, 0); + goto L829; + + L789: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, QImode)) + { + ro[2] = x2; + return 163; + } + x1 = XEXP (x0, 0); + goto L829; + + L830: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != QImode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + switch (GET_CODE (x1)) + { + case EQ: + goto L831; + case NE: + goto L836; + case GT: + goto L841; + case GTU: + goto L846; + case LT: + goto L851; + case LTU: + goto L856; + case GE: + goto L861; + case GEU: + goto L866; + case LE: + goto L871; + case LEU: + goto L876; + } + x1 = XEXP (x0, 0); + goto L1147; + + L831: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L832; + x1 = XEXP (x0, 0); + goto L1147; + + L832: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 171; + x1 = XEXP (x0, 0); + goto L1147; + + L836: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L837; + x1 = XEXP (x0, 0); + goto L1147; + + L837: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 173; + x1 = XEXP (x0, 0); + goto L1147; + + L841: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L842; + x1 = XEXP (x0, 0); + goto L1147; + + L842: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 175; + x1 = XEXP (x0, 0); + goto L1147; + + L846: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L847; + x1 = XEXP (x0, 0); + goto L1147; + + L847: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 177; + x1 = XEXP (x0, 0); + goto L1147; + + L851: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L852; + x1 = XEXP (x0, 0); + goto L1147; + + L852: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 179; + x1 = XEXP (x0, 0); + goto L1147; + + L856: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L857; + x1 = XEXP (x0, 0); + goto L1147; + + L857: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 181; + x1 = XEXP (x0, 0); + goto L1147; + + L861: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L862; + x1 = XEXP (x0, 0); + goto L1147; + + L862: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 183; + x1 = XEXP (x0, 0); + goto L1147; + + L866: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L867; + x1 = XEXP (x0, 0); + goto L1147; + + L867: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 185; + x1 = XEXP (x0, 0); + goto L1147; + + L871: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L872; + x1 = XEXP (x0, 0); + goto L1147; + + L872: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 187; + x1 = XEXP (x0, 0); + goto L1147; + + L876: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L877; + x1 = XEXP (x0, 0); + goto L1147; + + L877: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 189; + x1 = XEXP (x0, 0); + goto L1147; + + L232: + x1 = XEXP (x0, 1); + if (general_operand (x1, SFmode)) + { + ro[1] = x1; + return 45; + } + x1 = XEXP (x0, 0); + goto L234; + + L235: + x1 = XEXP (x0, 1); + if (general_operand (x1, SFmode)) + { + ro[1] = x1; + return 46; + } + x1 = XEXP (x0, 0); + goto L399; + + L400: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != SFmode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + switch (GET_CODE (x1)) + { + case FLOAT: + goto L401; + case NEG: + goto L602; + case ABS: + goto L615; + case SQRT: + goto L628; + case UNSPEC: + if (XINT (x1, 1) == 1 && XVECLEN (x1, 0) == 1 && 1) + goto L645; + if (XINT (x1, 1) == 2 && XVECLEN (x1, 0) == 1 && 1) + goto L658; + } + x1 = XEXP (x0, 0); + goto L1147; + + L401: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DImode: + if (nonimmediate_operand (x2, DImode)) + { + ro[1] = x2; + if (TARGET_80387) + return 78; + } + break; + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[1] = x2; + if (TARGET_80387) + return 80; + } + } + x1 = XEXP (x0, 0); + goto L1147; + + L602: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387) + return 122; + } + x1 = XEXP (x0, 0); + goto L1147; + + L615: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387) + return 125; + } + x1 = XEXP (x0, 0); + goto L1147; + + L628: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 128; + } + x1 = XEXP (x0, 0); + goto L1147; + + L645: + x2 = XVECEXP (x1, 0, 0); + if (register_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 132; + } + x1 = XEXP (x0, 0); + goto L1147; + + L658: + x2 = XVECEXP (x1, 0, 0); + if (register_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 135; + } + x1 = XEXP (x0, 0); + goto L1147; + + L238: + x1 = XEXP (x0, 1); + if (general_operand (x1, DFmode)) + { + ro[1] = x1; + return 47; + } + x1 = XEXP (x0, 0); + goto L247; + + L289: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == DFmode && GET_CODE (x1) == FLOAT_EXTEND && 1) + goto L290; + if (general_operand (x1, DFmode)) + { + ro[1] = x1; + return 49; + } + x1 = XEXP (x0, 0); + goto L395; + + L290: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387) + return 60; + } + x1 = XEXP (x0, 0); + goto L395; + + L396: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != DFmode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + switch (GET_CODE (x1)) + { + case FLOAT: + goto L397; + case NEG: + goto L610; + case ABS: + goto L623; + case SQRT: + goto L636; + case UNSPEC: + if (XINT (x1, 1) == 1 && XVECLEN (x1, 0) == 1 && 1) + goto L649; + if (XINT (x1, 1) == 2 && XVECLEN (x1, 0) == 1 && 1) + goto L662; + } + x1 = XEXP (x0, 0); + goto L1147; + + L397: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DImode: + if (nonimmediate_operand (x2, DImode)) + { + ro[1] = x2; + if (TARGET_80387) + return 77; + } + break; + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[1] = x2; + if (TARGET_80387) + return 79; + } + } + x1 = XEXP (x0, 0); + goto L1147; + + L610: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == FLOAT_EXTEND && 1) + goto L611; + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387) + return 123; + } + x1 = XEXP (x0, 0); + goto L1147; + + L611: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387) + return 124; + } + x1 = XEXP (x0, 0); + goto L1147; + + L623: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == FLOAT_EXTEND && 1) + goto L624; + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387) + return 126; + } + x1 = XEXP (x0, 0); + goto L1147; + + L624: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387) + return 127; + } + x1 = XEXP (x0, 0); + goto L1147; + + L636: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == FLOAT_EXTEND && 1) + goto L637; + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 129; + } + x1 = XEXP (x0, 0); + goto L1147; + + L637: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 130; + } + x1 = XEXP (x0, 0); + goto L1147; + + L649: + x2 = XVECEXP (x1, 0, 0); + if (GET_MODE (x2) != DFmode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + if (GET_CODE (x2) == FLOAT_EXTEND && 1) + goto L650; + if (register_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 131; + } + x1 = XEXP (x0, 0); + goto L1147; + + L650: + x3 = XEXP (x2, 0); + if (register_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 133; + } + x1 = XEXP (x0, 0); + goto L1147; + + L662: + x2 = XVECEXP (x1, 0, 0); + if (GET_MODE (x2) != DFmode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + if (GET_CODE (x2) == FLOAT_EXTEND && 1) + goto L663; + if (register_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 134; + } + x1 = XEXP (x0, 0); + goto L1147; + + L663: + x3 = XEXP (x2, 0); + if (register_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 136; + } + x1 = XEXP (x0, 0); + goto L1147; + + L251: + x1 = XEXP (x0, 1); + if (general_operand (x1, DImode)) + { + ro[1] = x1; + return 50; + } + x1 = XEXP (x0, 0); + goto L253; + + L412: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case DImode: + switch (GET_CODE (x1)) + { + case PLUS: + goto L413; + case MINUS: + goto L436; + case NEG: + goto L586; + } + } + if (general_operand (x1, DImode)) + { + ro[1] = x1; + return 51; + } + x1 = XEXP (x0, 0); + goto L268; + + L413: + x2 = XEXP (x1, 0); + if (general_operand (x2, DImode)) + { + ro[1] = x2; + goto L414; + } + x1 = XEXP (x0, 0); + goto L268; + + L414: + x2 = XEXP (x1, 1); + if (general_operand (x2, DImode)) + { + ro[2] = x2; + return 81; + } + x1 = XEXP (x0, 0); + goto L268; + + L436: + x2 = XEXP (x1, 0); + if (general_operand (x2, DImode)) + { + ro[1] = x2; + goto L437; + } + x1 = XEXP (x0, 0); + goto L268; + + L437: + x2 = XEXP (x1, 1); + if (general_operand (x2, DImode)) + { + ro[2] = x2; + return 88; + } + x1 = XEXP (x0, 0); + goto L268; + + L586: + x2 = XEXP (x1, 0); + if (general_operand (x2, DImode)) + { + ro[1] = x2; + return 118; + } + x1 = XEXP (x0, 0); + goto L268; + + L269: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != DImode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + switch (GET_CODE (x1)) + { + case ZERO_EXTEND: + goto L270; + case SIGN_EXTEND: + goto L274; + case ASHIFT: + goto L679; + case ASHIFTRT: + goto L707; + case LSHIFTRT: + goto L735; + } + x1 = XEXP (x0, 0); + goto L1147; + + L270: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[1] = x2; + return 55; + } + x1 = XEXP (x0, 0); + goto L1147; + + L274: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[1] = x2; + return 56; + } + x1 = XEXP (x0, 0); + goto L1147; + + L679: + x2 = XEXP (x1, 0); + if (register_operand (x2, DImode)) + { + ro[1] = x2; + goto L680; + } + x1 = XEXP (x0, 0); + goto L1147; + + L680: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + return 141; + } + x1 = XEXP (x0, 0); + goto L1147; + + L707: + x2 = XEXP (x1, 0); + if (register_operand (x2, DImode)) + { + ro[1] = x2; + goto L708; + } + x1 = XEXP (x0, 0); + goto L1147; + + L708: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + return 147; + } + x1 = XEXP (x0, 0); + goto L1147; + + L735: + x2 = XEXP (x1, 0); + if (register_operand (x2, DImode)) + { + ro[1] = x2; + goto L736; + } + x1 = XEXP (x0, 0); + goto L1147; + + L736: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + return 153; + } + x1 = XEXP (x0, 0); + goto L1147; + L2: + tem = recog_1 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L1147; + + L218: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (general_operand (x2, HImode)) + { + ro[0] = x2; + goto L219; + } + break; + case QImode: + if (general_operand (x2, QImode)) + { + ro[0] = x2; + goto L229; + } + } + goto L1147; + + L219: + x1 = XEXP (x0, 1); + if (general_operand (x1, HImode)) + { + ro[1] = x1; + return 41; + } + x1 = XEXP (x0, 0); + goto L1147; + + L229: + x1 = XEXP (x0, 1); + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 44; + } + x1 = XEXP (x0, 0); + goto L1147; + + L1081: + x1 = XEXP (x0, 1); + switch (GET_CODE (x1)) + { + case MINUS: + if (GET_MODE (x1) == SImode && 1) + goto L1082; + break; + case IF_THEN_ELSE: + goto L881; + case LABEL_REF: + goto L1061; + } + L1064: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + return 221; + } + x1 = XEXP (x0, 0); + goto L1147; + + L1082: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 3 && 1) + goto L1083; + x1 = XEXP (x0, 0); + goto L1147; + + L1083: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == MEM && 1) + goto L1084; + x1 = XEXP (x0, 0); + goto L1147; + + L1084: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == PLUS && 1) + goto L1085; + x1 = XEXP (x0, 0); + goto L1147; + + L1085: + x4 = XEXP (x3, 0); + if (GET_MODE (x4) == SImode && GET_CODE (x4) == MULT && 1) + goto L1086; + x1 = XEXP (x0, 0); + goto L1147; + + L1086: + x5 = XEXP (x4, 0); + if (register_operand (x5, SImode)) + { + ro[0] = x5; + goto L1087; + } + x1 = XEXP (x0, 0); + goto L1147; + + L1087: + x5 = XEXP (x4, 1); + if (GET_CODE (x5) == CONST_INT && XWINT (x5, 0) == 4 && 1) + goto L1088; + x1 = XEXP (x0, 0); + goto L1147; + + L1088: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == LABEL_REF && 1) + goto L1089; + x1 = XEXP (x0, 0); + goto L1147; + + L1089: + x5 = XEXP (x4, 0); + if (pnum_clobbers != 0 && 1) + { + ro[1] = x5; + *pnum_clobbers = 1; + return 223; + } + x1 = XEXP (x0, 0); + goto L1147; + L881: + tem = recog_2 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L1147; + + L1061: + x2 = XEXP (x1, 0); + ro[0] = x2; + return 220; + + L1148: + x1 = XEXP (x0, 1); + if (GET_CODE (x1) == CALL && 1) + goto L1149; + x1 = XEXP (x0, 0); + goto L1236; + + L1149: + x2 = XEXP (x1, 0); + if (call_insn_operand (x2, QImode)) + { + ro[1] = x2; + goto L1150; + } + L1154: + if (GET_MODE (x2) == QImode && GET_CODE (x2) == MEM && 1) + goto L1155; + x1 = XEXP (x0, 0); + goto L1236; + + L1150: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 235; + } + x2 = XEXP (x1, 0); + goto L1154; + + L1155: + x3 = XEXP (x2, 0); + if (symbolic_operand (x3, SImode)) + { + ro[1] = x3; + goto L1156; + } + x1 = XEXP (x0, 0); + goto L1236; + + L1156: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + if (!HALF_PIC_P ()) + return 236; + } + x1 = XEXP (x0, 0); + goto L1236; + + L1237: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == SImode && GET_CODE (x1) == PLUS && 1) + goto L1238; + goto ret0; + + L1238: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == FFS && 1) + goto L1239; + goto ret0; + + L1239: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L1240; + } + goto ret0; + + L1240: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == -1 && pnum_clobbers != 0 && 1) + { + *pnum_clobbers = 1; + return 250; + } + goto ret0; + + L1252: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == HImode && GET_CODE (x1) == PLUS && 1) + goto L1253; + goto ret0; + + L1253: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == FFS && 1) + goto L1254; + goto ret0; + + L1254: + x3 = XEXP (x2, 0); + if (general_operand (x3, HImode)) + { + ro[1] = x3; + goto L1255; + } + goto ret0; + + L1255: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == -1 && pnum_clobbers != 0 && 1) + { + *pnum_clobbers = 1; + return 252; + } + goto ret0; + + L1258: + x1 = XEXP (x0, 1); + if (binary_387_op (x1, DFmode)) + { + ro[3] = x1; + goto L1264; + } + goto ret0; + + L1264: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DFmode: + switch (GET_CODE (x2)) + { + case FLOAT: + goto L1265; + case FLOAT_EXTEND: + goto L1271; + case SUBREG: + case REG: + case MEM: + if (nonimmediate_operand (x2, DFmode)) + { + ro[1] = x2; + goto L1260; + } + } + } + L1276: + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L1277; + } + goto ret0; + + L1265: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L1266; + } + goto ret0; + + L1266: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 254; + } + goto ret0; + + L1271: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + goto L1272; + } + goto ret0; + + L1272: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 255; + } + goto ret0; + + L1260: + x2 = XEXP (x1, 1); + if (nonimmediate_operand (x2, DFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 253; + } + x2 = XEXP (x1, 0); + goto L1276; + + L1277: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != DFmode) + goto ret0; + switch (GET_CODE (x2)) + { + case FLOAT: + goto L1278; + case FLOAT_EXTEND: + goto L1284; + } + goto ret0; + + L1278: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + if (TARGET_80387) + return 256; + } + goto ret0; + + L1284: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[2] = x3; + if (TARGET_80387) + return 257; + } + goto ret0; + + L1287: + x1 = XEXP (x0, 1); + if (binary_387_op (x1, SFmode)) + { + ro[3] = x1; + goto L1293; + } + goto ret0; + + L1293: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SFmode: + if (GET_CODE (x2) == FLOAT && 1) + goto L1294; + if (nonimmediate_operand (x2, SFmode)) + { + ro[1] = x2; + goto L1289; + } + } + L1299: + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L1300; + } + goto ret0; + + L1294: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L1295; + } + goto ret0; + + L1295: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 259; + } + goto ret0; + + L1289: + x2 = XEXP (x1, 1); + if (nonimmediate_operand (x2, SFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 258; + } + x2 = XEXP (x1, 0); + goto L1299; + + L1300: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SFmode && GET_CODE (x2) == FLOAT && 1) + goto L1301; + goto ret0; + + L1301: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + if (TARGET_80387) + return 260; + } + goto ret0; + ret0: return -1; +} + +int +recog_4 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + switch (GET_MODE (x2)) + { + case SFmode: + if (register_operand (x2, SFmode)) + { + ro[0] = x2; + goto L13; + } + break; + case DFmode: + if (register_operand (x2, DFmode)) + { + ro[0] = x2; + goto L22; + } + } + L45: + if (VOIDmode_compare_op (x2, VOIDmode)) + { + ro[2] = x2; + goto L74; + } + L118: + if (GET_MODE (x2) == CCFPEQmode && GET_CODE (x2) == COMPARE && 1) + goto L119; + goto ret0; + + L13: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L14; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L45; + + L14: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[1] = x2; + if (TARGET_80387 && ! TARGET_IEEE_FP) + return 6; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L45; + + L22: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L23; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L45; + + L23: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[1] = x2; + if (TARGET_80387 && ! TARGET_IEEE_FP) + return 8; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L45; + + L74: + x3 = XEXP (x2, 0); + switch (GET_MODE (x3)) + { + case DFmode: + switch (GET_CODE (x3)) + { + case FLOAT: + goto L75; + case FLOAT_EXTEND: + goto L105; + case SUBREG: + case REG: + case MEM: + if (nonimmediate_operand (x3, DFmode)) + { + ro[0] = x3; + goto L47; + } + } + L59: + if (register_operand (x3, DFmode)) + { + ro[0] = x3; + goto L60; + } + break; + case SFmode: + if (GET_CODE (x3) == FLOAT && 1) + goto L161; + if (nonimmediate_operand (x3, SFmode)) + { + ro[0] = x3; + goto L133; + } + L145: + if (register_operand (x3, SFmode)) + { + ro[0] = x3; + goto L146; + } + } + goto L118; + + L75: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SImode)) + { + ro[0] = x4; + goto L76; + } + goto L118; + + L76: + x3 = XEXP (x2, 1); + if (register_operand (x3, DFmode)) + { + ro[1] = x3; + goto L77; + } + goto L118; + + L77: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L78; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L78: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 18; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L105: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SFmode)) + { + ro[0] = x4; + goto L106; + } + goto L118; + + L106: + x3 = XEXP (x2, 1); + if (register_operand (x3, DFmode)) + { + ro[1] = x3; + goto L107; + } + goto L118; + + L107: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L108; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L108: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 20; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L47: + x3 = XEXP (x2, 1); + if (nonimmediate_operand (x3, DFmode)) + { + ro[1] = x3; + goto L48; + } + x3 = XEXP (x2, 0); + goto L59; + + L48: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L49; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L59; + + L49: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)) + return 16; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L59; + + L60: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) != DFmode) + { + goto L118; + } + switch (GET_CODE (x3)) + { + case FLOAT: + goto L61; + case FLOAT_EXTEND: + goto L91; + } + goto L118; + + L61: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SImode)) + { + ro[1] = x4; + goto L62; + } + goto L118; + + L62: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L63; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L63: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 17; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L91: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SFmode)) + { + ro[1] = x4; + goto L92; + } + goto L118; + + L92: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L93; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L93: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 19; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L161: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SImode)) + { + ro[0] = x4; + goto L162; + } + goto L118; + + L162: + x3 = XEXP (x2, 1); + if (register_operand (x3, SFmode)) + { + ro[1] = x3; + goto L163; + } + goto L118; + + L163: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L164; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L164: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 24; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L133: + x3 = XEXP (x2, 1); + if (nonimmediate_operand (x3, SFmode)) + { + ro[1] = x3; + goto L134; + } + x3 = XEXP (x2, 0); + goto L145; + + L134: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L135; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L145; + + L135: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)) + return 22; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L145; + + L146: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) == SFmode && GET_CODE (x3) == FLOAT && 1) + goto L147; + goto L118; + + L147: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SImode)) + { + ro[1] = x4; + goto L148; + } + goto L118; + + L148: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L149; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L149: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 23; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L119: + x3 = XEXP (x2, 0); + switch (GET_MODE (x3)) + { + case DFmode: + if (register_operand (x3, DFmode)) + { + ro[0] = x3; + goto L120; + } + break; + case SFmode: + if (register_operand (x3, SFmode)) + { + ro[0] = x3; + goto L176; + } + } + goto ret0; + + L120: + x3 = XEXP (x2, 1); + if (register_operand (x3, DFmode)) + { + ro[1] = x3; + goto L121; + } + goto ret0; + + L121: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L122; + goto ret0; + + L122: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[2] = x2; + if (TARGET_80387) + return 21; + } + goto ret0; + + L176: + x3 = XEXP (x2, 1); + if (register_operand (x3, SFmode)) + { + ro[1] = x3; + goto L177; + } + goto ret0; + + L177: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L178; + goto ret0; + + L178: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[2] = x2; + if (TARGET_80387) + return 25; + } + goto ret0; + ret0: return -1; +} + +int +recog_5 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DFmode: + if (register_operand (x2, DFmode)) + { + ro[0] = x2; + goto L242; + } + break; + case SFmode: + if (nonimmediate_operand (x2, SFmode)) + { + ro[0] = x2; + goto L294; + } + break; + case SImode: + if (register_operand (x2, SImode)) + { + ro[0] = x2; + goto L497; + } + break; + case HImode: + if (register_operand (x2, HImode)) + { + ro[0] = x2; + goto L508; + } + break; + case DImode: + if (register_operand (x2, DImode)) + { + ro[0] = x2; + goto L684; + } + } + switch (GET_CODE (x2)) + { + case CC0: + goto L12; + case PC: + goto L1068; + } + L1125: + ro[0] = x2; + goto L1126; + L1228: + switch (GET_MODE (x2)) + { + case SImode: + if (register_operand (x2, SImode)) + { + ro[0] = x2; + goto L1229; + } + break; + case HImode: + if (register_operand (x2, HImode)) + { + ro[0] = x2; + goto L1244; + } + } + goto ret0; + + L242: + x2 = XEXP (x1, 1); + if (register_operand (x2, DFmode)) + { + ro[1] = x2; + goto L243; + } + x2 = XEXP (x1, 0); + goto L1125; + + L243: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L244; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L244: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L245; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L245: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 48; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L294: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SFmode && GET_CODE (x2) == FLOAT_TRUNCATE && 1) + goto L295; + x2 = XEXP (x1, 0); + goto L1125; + + L295: + x3 = XEXP (x2, 0); + if (register_operand (x3, DFmode)) + { + ro[1] = x3; + goto L296; + } + x2 = XEXP (x1, 0); + goto L1125; + + L296: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L297; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L297: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 62; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L497: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != SImode) + { + x2 = XEXP (x1, 0); + goto L1125; + } + switch (GET_CODE (x2)) + { + case DIV: + goto L498; + case UDIV: + goto L520; + } + x2 = XEXP (x1, 0); + goto L1125; + + L498: + x3 = XEXP (x2, 0); + if (register_operand (x3, SImode)) + { + ro[1] = x3; + goto L499; + } + x2 = XEXP (x1, 0); + goto L1125; + + L499: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + goto L500; + } + x2 = XEXP (x1, 0); + goto L1125; + + L500: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L501; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L501: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[3] = x2; + goto L502; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L502: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == MOD && 1) + goto L503; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L503: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L504; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L504: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[2]) && 1) + return 105; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L520: + x3 = XEXP (x2, 0); + if (register_operand (x3, SImode)) + { + ro[1] = x3; + goto L521; + } + x2 = XEXP (x1, 0); + goto L1125; + + L521: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + goto L522; + } + x2 = XEXP (x1, 0); + goto L1125; + + L522: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L523; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L523: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[3] = x2; + goto L524; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L524: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == UMOD && 1) + goto L525; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L525: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L526; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L526: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[2]) && 1) + return 107; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L508: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != HImode) + { + x2 = XEXP (x1, 0); + goto L1125; + } + switch (GET_CODE (x2)) + { + case DIV: + goto L509; + case UDIV: + goto L531; + } + x2 = XEXP (x1, 0); + goto L1125; + + L509: + x3 = XEXP (x2, 0); + if (register_operand (x3, HImode)) + { + ro[1] = x3; + goto L510; + } + x2 = XEXP (x1, 0); + goto L1125; + + L510: + x3 = XEXP (x2, 1); + if (general_operand (x3, HImode)) + { + ro[2] = x3; + goto L511; + } + x2 = XEXP (x1, 0); + goto L1125; + + L511: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L512; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L512: + x2 = XEXP (x1, 0); + if (register_operand (x2, HImode)) + { + ro[3] = x2; + goto L513; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L513: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == MOD && 1) + goto L514; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L514: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L515; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L515: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[2]) && 1) + return 106; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L531: + x3 = XEXP (x2, 0); + if (register_operand (x3, HImode)) + { + ro[1] = x3; + goto L532; + } + x2 = XEXP (x1, 0); + goto L1125; + + L532: + x3 = XEXP (x2, 1); + if (general_operand (x3, HImode)) + { + ro[2] = x3; + goto L533; + } + x2 = XEXP (x1, 0); + goto L1125; + + L533: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L534; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L534: + x2 = XEXP (x1, 0); + if (register_operand (x2, HImode)) + { + ro[3] = x2; + goto L535; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L535: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == UMOD && 1) + goto L536; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L536: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L537; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L537: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[2]) && 1) + return 108; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L684: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != DImode) + { + x2 = XEXP (x1, 0); + goto L1125; + } + switch (GET_CODE (x2)) + { + case ASHIFT: + goto L685; + case ASHIFTRT: + goto L713; + case LSHIFTRT: + goto L741; + } + x2 = XEXP (x1, 0); + goto L1125; + + L685: + x3 = XEXP (x2, 0); + if (register_operand (x3, DImode)) + { + ro[1] = x3; + goto L686; + } + x2 = XEXP (x1, 0); + goto L1125; + + L686: + x3 = XEXP (x2, 1); + if (register_operand (x3, QImode)) + { + ro[2] = x3; + goto L687; + } + x2 = XEXP (x1, 0); + goto L1125; + + L687: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L688; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L688: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[2]) && 1) + return 142; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L713: + x3 = XEXP (x2, 0); + if (register_operand (x3, DImode)) + { + ro[1] = x3; + goto L714; + } + x2 = XEXP (x1, 0); + goto L1125; + + L714: + x3 = XEXP (x2, 1); + if (register_operand (x3, QImode)) + { + ro[2] = x3; + goto L715; + } + x2 = XEXP (x1, 0); + goto L1125; + + L715: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L716; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L716: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[2]) && 1) + return 148; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L741: + x3 = XEXP (x2, 0); + if (register_operand (x3, DImode)) + { + ro[1] = x3; + goto L742; + } + x2 = XEXP (x1, 0); + goto L1125; + + L742: + x3 = XEXP (x2, 1); + if (register_operand (x3, QImode)) + { + ro[2] = x3; + goto L743; + } + x2 = XEXP (x1, 0); + goto L1125; + + L743: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L744; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L744: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[2]) && 1) + return 154; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + L12: + tem = recog_4 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x2 = XEXP (x1, 0); + goto L1125; + + L1068: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == MINUS && 1) + goto L1069; + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L1094; + } + x2 = XEXP (x1, 0); + goto L1125; + + L1069: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == REG && XINT (x3, 0) == 3 && 1) + goto L1070; + x2 = XEXP (x1, 0); + goto L1125; + + L1070: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == MEM && 1) + goto L1071; + x2 = XEXP (x1, 0); + goto L1125; + + L1071: + x4 = XEXP (x3, 0); + if (GET_MODE (x4) == SImode && GET_CODE (x4) == PLUS && 1) + goto L1072; + x2 = XEXP (x1, 0); + goto L1125; + + L1072: + x5 = XEXP (x4, 0); + if (GET_MODE (x5) == SImode && GET_CODE (x5) == MULT && 1) + goto L1073; + x2 = XEXP (x1, 0); + goto L1125; + + L1073: + x6 = XEXP (x5, 0); + if (register_operand (x6, SImode)) + { + ro[0] = x6; + goto L1074; + } + x2 = XEXP (x1, 0); + goto L1125; + + L1074: + x6 = XEXP (x5, 1); + if (GET_CODE (x6) == CONST_INT && XWINT (x6, 0) == 4 && 1) + goto L1075; + x2 = XEXP (x1, 0); + goto L1125; + + L1075: + x5 = XEXP (x4, 1); + if (GET_CODE (x5) == LABEL_REF && 1) + goto L1076; + x2 = XEXP (x1, 0); + goto L1125; + + L1076: + x6 = XEXP (x5, 0); + ro[1] = x6; + goto L1077; + + L1077: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1078; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L1078: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[2] = x2; + return 223; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L1094: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1095; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L1095: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1096; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L1096: + x3 = XEXP (x2, 0); + ro[1] = x3; + return 224; + + L1126: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CALL && 1) + goto L1138; + x2 = XEXP (x1, 0); + goto L1228; + + L1138: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == QImode && GET_CODE (x3) == MEM && 1) + goto L1139; + L1127: + if (call_insn_operand (x3, QImode)) + { + ro[1] = x3; + goto L1128; + } + x2 = XEXP (x1, 0); + goto L1228; + + L1139: + x4 = XEXP (x3, 0); + if (symbolic_operand (x4, SImode)) + { + ro[1] = x4; + goto L1140; + } + goto L1127; + + L1140: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + goto L1141; + } + x3 = XEXP (x2, 0); + goto L1127; + + L1141: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1142; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L1127; + + L1142: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 7 && 1) + goto L1143; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L1127; + + L1143: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == PLUS && 1) + goto L1144; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L1127; + + L1144: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == REG && XINT (x3, 0) == 7 && 1) + goto L1145; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L1127; + + L1145: + x3 = XEXP (x2, 1); + if (immediate_operand (x3, SImode)) + { + ro[4] = x3; + if (!HALF_PIC_P ()) + return 233; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L1127; + + L1128: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + goto L1129; + } + x2 = XEXP (x1, 0); + goto L1228; + + L1129: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1130; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1228; + + L1130: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 7 && 1) + goto L1131; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1228; + + L1131: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == PLUS && 1) + goto L1132; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1228; + + L1132: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == REG && XINT (x3, 0) == 7 && 1) + goto L1133; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1228; + + L1133: + x3 = XEXP (x2, 1); + if (immediate_operand (x3, SImode)) + { + ro[4] = x3; + return 232; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1228; + + L1229: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != SImode) + goto ret0; + switch (GET_CODE (x2)) + { + case PLUS: + goto L1230; + case UNSPEC: + if (XINT (x2, 1) == 0 && XVECLEN (x2, 0) == 3 && 1) + goto L1306; + } + goto ret0; + + L1230: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == FFS && 1) + goto L1231; + goto ret0; + + L1231: + x4 = XEXP (x3, 0); + if (general_operand (x4, SImode)) + { + ro[1] = x4; + goto L1232; + } + goto ret0; + + L1232: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == -1 && 1) + goto L1233; + goto ret0; + + L1233: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1234; + goto ret0; + + L1234: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[2] = x2; + return 250; + } + goto ret0; + + L1306: + x3 = XVECEXP (x2, 0, 0); + if (GET_MODE (x3) == BLKmode && GET_CODE (x3) == MEM && 1) + goto L1307; + goto ret0; + + L1307: + x4 = XEXP (x3, 0); + if (address_operand (x4, SImode)) + { + ro[1] = x4; + goto L1308; + } + goto ret0; + + L1308: + x3 = XVECEXP (x2, 0, 1); + if (register_operand (x3, QImode)) + { + ro[2] = x3; + goto L1309; + } + goto ret0; + + L1309: + x3 = XVECEXP (x2, 0, 2); + if (immediate_operand (x3, SImode)) + { + ro[3] = x3; + goto L1310; + } + goto ret0; + + L1310: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1311; + goto ret0; + + L1311: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + return 262; + goto ret0; + + L1244: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == PLUS && 1) + goto L1245; + goto ret0; + + L1245: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == HImode && GET_CODE (x3) == FFS && 1) + goto L1246; + goto ret0; + + L1246: + x4 = XEXP (x3, 0); + if (general_operand (x4, HImode)) + { + ro[1] = x4; + goto L1247; + } + goto ret0; + + L1247: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == -1 && 1) + goto L1248; + goto ret0; + + L1248: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1249; + goto ret0; + + L1249: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[2] = x2; + return 252; + } + goto ret0; + ret0: return -1; +} + +int +recog (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + L1170: + switch (GET_CODE (x0)) + { + case UNSPEC: + if (GET_MODE (x0) == SImode && XINT (x0, 1) == 0 && XVECLEN (x0, 0) == 1 && 1) + goto L1171; + break; + case SET: + goto L200; + case PARALLEL: + if (XVECLEN (x0, 0) == 2 && 1) + goto L10; + if (XVECLEN (x0, 0) == 5 && 1) + goto L299; + if (XVECLEN (x0, 0) == 4 && 1) + goto L313; + if (XVECLEN (x0, 0) == 3 && 1) + goto L363; + if (XVECLEN (x0, 0) == 6 && 1) + goto L1175; + break; + case CALL: + goto L1117; + case RETURN: + if (simple_386_epilogue ()) + return 242; + break; + case CONST_INT: + if (XWINT (x0, 0) == 0 && 1) + return 243; + } + goto ret0; + + L1171: + x1 = XVECEXP (x0, 0, 0); + if (memory_operand (x1, SImode)) + { + ro[0] = x1; + return 241; + } + goto ret0; + L200: + return recog_3 (x0, insn, pnum_clobbers); + + L10: + x1 = XVECEXP (x0, 0, 0); + switch (GET_CODE (x1)) + { + case SET: + goto L241; + case CALL: + goto L1108; + } + goto ret0; + L241: + return recog_5 (x0, insn, pnum_clobbers); + + L1108: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == QImode && GET_CODE (x2) == MEM && 1) + goto L1109; + L1099: + if (call_insn_operand (x2, QImode)) + { + ro[0] = x2; + goto L1100; + } + goto ret0; + + L1109: + x3 = XEXP (x2, 0); + if (symbolic_operand (x3, SImode)) + { + ro[0] = x3; + goto L1110; + } + goto L1099; + + L1110: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L1111; + } + x2 = XEXP (x1, 0); + goto L1099; + + L1111: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1112; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1099; + + L1112: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 7 && 1) + goto L1113; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1099; + + L1113: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == PLUS && 1) + goto L1114; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1099; + + L1114: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == REG && XINT (x3, 0) == 7 && 1) + goto L1115; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1099; + + L1115: + x3 = XEXP (x2, 1); + if (immediate_operand (x3, SImode)) + { + ro[3] = x3; + if (!HALF_PIC_P ()) + return 227; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1099; + + L1100: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L1101; + } + goto ret0; + + L1101: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1102; + goto ret0; + + L1102: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 7 && 1) + goto L1103; + goto ret0; + + L1103: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == PLUS && 1) + goto L1104; + goto ret0; + + L1104: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == REG && XINT (x3, 0) == 7 && 1) + goto L1105; + goto ret0; + + L1105: + x3 = XEXP (x2, 1); + if (immediate_operand (x3, SImode)) + { + ro[3] = x3; + return 226; + } + goto ret0; + + L299: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == SET && 1) + goto L300; + goto ret0; + + L300: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DImode && general_operand (x2, DImode)) + { + ro[0] = x2; + goto L301; + } + goto ret0; + + L301: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == DImode && GET_CODE (x2) == FIX && 1) + goto L302; + goto ret0; + + L302: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) != FIX) + goto ret0; + switch (GET_MODE (x3)) + { + case DFmode: + goto L303; + case SFmode: + goto L329; + } + goto ret0; + + L303: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L304; + } + goto ret0; + + L304: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L305; + goto ret0; + + L305: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L306; + goto ret0; + + L306: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L307; + goto ret0; + + L307: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L308; + } + goto ret0; + + L308: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L309; + goto ret0; + + L309: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[3] = x2; + goto L310; + } + goto ret0; + + L310: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L311; + goto ret0; + + L311: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[4] = x2; + if (TARGET_80387) + return 67; + } + goto ret0; + + L329: + x4 = XEXP (x3, 0); + if (register_operand (x4, SFmode)) + { + ro[1] = x4; + goto L330; + } + goto ret0; + + L330: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L331; + goto ret0; + + L331: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L332; + goto ret0; + + L332: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L333; + goto ret0; + + L333: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L334; + } + goto ret0; + + L334: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L335; + goto ret0; + + L335: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[3] = x2; + goto L336; + } + goto ret0; + + L336: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L337; + goto ret0; + + L337: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[4] = x2; + if (TARGET_80387) + return 68; + } + goto ret0; + + L313: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == SET && 1) + goto L314; + goto ret0; + + L314: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DImode: + if (general_operand (x2, DImode)) + { + ro[0] = x2; + goto L315; + } + break; + case SImode: + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L353; + } + } + goto ret0; + + L315: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == DImode && GET_CODE (x2) == FIX && 1) + goto L316; + goto ret0; + + L316: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) != FIX) + goto ret0; + switch (GET_MODE (x3)) + { + case DFmode: + goto L317; + case SFmode: + goto L343; + } + goto ret0; + + L317: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L318; + } + goto ret0; + + L318: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L319; + goto ret0; + + L319: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L320; + goto ret0; + + L320: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L321; + goto ret0; + + L321: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L322; + } + goto ret0; + + L322: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L323; + goto ret0; + + L323: + x2 = XEXP (x1, 0); + if (pnum_clobbers != 0 && memory_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 67; + } + } + goto ret0; + + L343: + x4 = XEXP (x3, 0); + if (register_operand (x4, SFmode)) + { + ro[1] = x4; + goto L344; + } + goto ret0; + + L344: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L345; + goto ret0; + + L345: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L346; + goto ret0; + + L346: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L347; + goto ret0; + + L347: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L348; + } + goto ret0; + + L348: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L349; + goto ret0; + + L349: + x2 = XEXP (x1, 0); + if (pnum_clobbers != 0 && memory_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 68; + } + } + goto ret0; + + L353: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == FIX && 1) + goto L354; + goto ret0; + + L354: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) != FIX) + goto ret0; + switch (GET_MODE (x3)) + { + case DFmode: + goto L355; + case SFmode: + goto L377; + } + goto ret0; + + L355: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L356; + } + goto ret0; + + L356: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L357; + goto ret0; + + L357: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L358; + } + goto ret0; + + L358: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L359; + goto ret0; + + L359: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[3] = x2; + goto L360; + } + goto ret0; + + L360: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L361; + goto ret0; + + L361: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[4] = x2; + if (TARGET_80387) + return 71; + } + goto ret0; + + L377: + x4 = XEXP (x3, 0); + if (register_operand (x4, SFmode)) + { + ro[1] = x4; + goto L378; + } + goto ret0; + + L378: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L379; + goto ret0; + + L379: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L380; + } + goto ret0; + + L380: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L381; + goto ret0; + + L381: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[3] = x2; + goto L382; + } + goto ret0; + + L382: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L383; + goto ret0; + + L383: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[4] = x2; + if (TARGET_80387) + return 72; + } + goto ret0; + + L363: + x1 = XVECEXP (x0, 0, 0); + switch (GET_CODE (x1)) + { + case SET: + goto L364; + case CALL: + goto L1165; + } + goto ret0; + + L364: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && general_operand (x2, SImode)) + { + ro[0] = x2; + goto L365; + } + goto ret0; + + L365: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == FIX && 1) + goto L366; + goto ret0; + + L366: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) != FIX) + goto ret0; + switch (GET_MODE (x3)) + { + case DFmode: + goto L367; + case SFmode: + goto L389; + } + goto ret0; + + L367: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L368; + } + goto ret0; + + L368: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L369; + goto ret0; + + L369: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L370; + } + goto ret0; + + L370: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L371; + goto ret0; + + L371: + x2 = XEXP (x1, 0); + if (pnum_clobbers != 0 && memory_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 71; + } + } + goto ret0; + + L389: + x4 = XEXP (x3, 0); + if (register_operand (x4, SFmode)) + { + ro[1] = x4; + goto L390; + } + goto ret0; + + L390: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L391; + goto ret0; + + L391: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L392; + } + goto ret0; + + L392: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L393; + goto ret0; + + L393: + x2 = XEXP (x1, 0); + if (pnum_clobbers != 0 && memory_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 72; + } + } + goto ret0; + + L1165: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == QImode && GET_CODE (x2) == MEM && 1) + goto L1166; + L1159: + if (call_insn_operand (x2, QImode)) + { + ro[0] = x2; + goto L1160; + } + goto ret0; + + L1166: + x3 = XEXP (x2, 0); + if (symbolic_operand (x3, SImode)) + { + ro[0] = x3; + goto L1167; + } + goto L1159; + + L1167: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + goto L1168; + x2 = XEXP (x1, 0); + goto L1159; + + L1168: + x1 = XVECEXP (x0, 0, 1); + if (memory_operand (x1, DImode)) + { + ro[1] = x1; + goto L1169; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1159; + + L1169: + x1 = XVECEXP (x0, 0, 2); + ro[2] = x1; + if (!HALF_PIC_P ()) + return 239; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1159; + + L1160: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + goto L1161; + goto ret0; + + L1161: + x1 = XVECEXP (x0, 0, 1); + if (memory_operand (x1, DImode)) + { + ro[1] = x1; + goto L1162; + } + goto ret0; + + L1162: + x1 = XVECEXP (x0, 0, 2); + ro[2] = x1; + return 238; + + L1175: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == SET && 1) + goto L1176; + goto ret0; + + L1176: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case BLKmode: + if (GET_CODE (x2) == MEM && 1) + goto L1177; + break; + case SImode: + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L1193; + } + } + if (GET_CODE (x2) == CC0 && 1) + goto L1211; + goto ret0; + + L1177: + x3 = XEXP (x2, 0); + if (address_operand (x3, SImode)) + { + ro[0] = x3; + goto L1178; + } + goto ret0; + + L1178: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == BLKmode && GET_CODE (x2) == MEM && 1) + goto L1179; + goto ret0; + + L1179: + x3 = XEXP (x2, 0); + if (address_operand (x3, SImode)) + { + ro[1] = x3; + goto L1180; + } + goto ret0; + + L1180: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1181; + goto ret0; + + L1181: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + goto L1182; + } + goto ret0; + + L1182: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == USE && 1) + goto L1183; + goto ret0; + + L1183: + x2 = XEXP (x1, 0); + if (immediate_operand (x2, SImode)) + { + ro[3] = x2; + goto L1184; + } + goto ret0; + + L1184: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1185; + goto ret0; + + L1185: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[4] = x2; + goto L1186; + } + goto ret0; + + L1186: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1187; + goto ret0; + + L1187: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1188; + goto ret0; + + L1188: + x1 = XVECEXP (x0, 0, 5); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1189; + goto ret0; + + L1189: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + return 245; + goto ret0; + + L1193: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == COMPARE && 1) + goto L1194; + goto ret0; + + L1194: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == BLKmode && GET_CODE (x3) == MEM && 1) + goto L1195; + goto ret0; + + L1195: + x4 = XEXP (x3, 0); + if (address_operand (x4, SImode)) + { + ro[1] = x4; + goto L1196; + } + goto ret0; + + L1196: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) == BLKmode && GET_CODE (x3) == MEM && 1) + goto L1197; + goto ret0; + + L1197: + x4 = XEXP (x3, 0); + if (address_operand (x4, SImode)) + { + ro[2] = x4; + goto L1198; + } + goto ret0; + + L1198: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1199; + goto ret0; + + L1199: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[3] = x2; + goto L1200; + } + goto ret0; + + L1200: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == USE && 1) + goto L1201; + goto ret0; + + L1201: + x2 = XEXP (x1, 0); + if (immediate_operand (x2, SImode)) + { + ro[4] = x2; + goto L1202; + } + goto ret0; + + L1202: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1203; + goto ret0; + + L1203: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L1204; + goto ret0; + + L1204: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1205; + goto ret0; + + L1205: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[2]) && 1) + goto L1206; + goto ret0; + + L1206: + x1 = XVECEXP (x0, 0, 5); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1207; + goto ret0; + + L1207: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[3]) && 1) + return 247; + goto ret0; + + L1211: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == COMPARE && 1) + goto L1212; + goto ret0; + + L1212: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == BLKmode && GET_CODE (x3) == MEM && 1) + goto L1213; + goto ret0; + + L1213: + x4 = XEXP (x3, 0); + if (address_operand (x4, SImode)) + { + ro[0] = x4; + goto L1214; + } + goto ret0; + + L1214: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) == BLKmode && GET_CODE (x3) == MEM && 1) + goto L1215; + goto ret0; + + L1215: + x4 = XEXP (x3, 0); + if (address_operand (x4, SImode)) + { + ro[1] = x4; + goto L1216; + } + goto ret0; + + L1216: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1217; + goto ret0; + + L1217: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[2] = x2; + goto L1218; + } + goto ret0; + + L1218: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == USE && 1) + goto L1219; + goto ret0; + + L1219: + x2 = XEXP (x1, 0); + if (immediate_operand (x2, SImode)) + { + ro[3] = x2; + goto L1220; + } + goto ret0; + + L1220: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1221; + goto ret0; + + L1221: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1222; + goto ret0; + + L1222: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1223; + goto ret0; + + L1223: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L1224; + goto ret0; + + L1224: + x1 = XVECEXP (x0, 0, 5); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1225; + goto ret0; + + L1225: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[2]) && 1) + return 248; + goto ret0; + + L1117: + x1 = XEXP (x0, 0); + if (call_insn_operand (x1, QImode)) + { + ro[0] = x1; + goto L1118; + } + L1120: + if (GET_MODE (x1) == QImode && GET_CODE (x1) == MEM && 1) + goto L1121; + goto ret0; + + L1118: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + { + ro[1] = x1; + return 229; + } + x1 = XEXP (x0, 0); + goto L1120; + + L1121: + x2 = XEXP (x1, 0); + if (symbolic_operand (x2, SImode)) + { + ro[0] = x2; + goto L1122; + } + goto ret0; + + L1122: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + { + ro[1] = x1; + if (!HALF_PIC_P ()) + return 230; + } + goto ret0; + ret0: return -1; +} + +rtx +split_insns (x0, insn) + register rtx x0; + rtx insn; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + rtx tem; + + goto ret0; + ret0: return 0; +} + diff --git a/gnu/usr.bin/cc/lib/integrate.c b/gnu/usr.bin/cc/lib/integrate.c new file mode 100644 index 000000000000..73d839baff67 --- /dev/null +++ b/gnu/usr.bin/cc/lib/integrate.c @@ -0,0 +1,2902 @@ +/* Procedure integration for GNU CC. + Copyright (C) 1988, 1991, 1993 Free Software Foundation, Inc. + Contributed by Michael Tiemann (tiemann@cygnus.com) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include + +#include "config.h" +#include "rtl.h" +#include "tree.h" +#include "flags.h" +#include "insn-config.h" +#include "insn-flags.h" +#include "expr.h" +#include "output.h" +#include "integrate.h" +#include "real.h" +#include "function.h" + +#include "obstack.h" +#define obstack_chunk_alloc xmalloc +#define obstack_chunk_free free + +extern struct obstack *function_maybepermanent_obstack; + +extern tree pushdecl (); +extern tree poplevel (); + +/* Similar, but round to the next highest integer that meets the + alignment. */ +#define CEIL_ROUND(VALUE,ALIGN) (((VALUE) + (ALIGN) - 1) & ~((ALIGN)- 1)) + +/* Default max number of insns a function can have and still be inline. + This is overridden on RISC machines. */ +#ifndef INTEGRATE_THRESHOLD +#define INTEGRATE_THRESHOLD(DECL) \ + (8 * (8 + list_length (DECL_ARGUMENTS (DECL)))) +#endif + +/* Save any constant pool constants in an insn. */ +static void save_constants (); + +/* Note when parameter registers are the destination of a SET. */ +static void note_modified_parmregs (); + +/* Copy an rtx for save_for_inline_copying. */ +static rtx copy_for_inline (); + +/* Make copies of MEMs in DECL_RTLs. */ +static void copy_decl_rtls (); + +static tree copy_decl_tree (); +static tree copy_decl_list (); + +static void integrate_parm_decls (); +static void integrate_decl_tree (); + +static void subst_constants (); + +/* Zero if the current function (whose FUNCTION_DECL is FNDECL) + is safe and reasonable to integrate into other functions. + Nonzero means value is a warning message with a single %s + for the function's name. */ + +char * +function_cannot_inline_p (fndecl) + register tree fndecl; +{ + register rtx insn; + tree last = tree_last (TYPE_ARG_TYPES (TREE_TYPE (fndecl))); + int max_insns = INTEGRATE_THRESHOLD (fndecl); + register int ninsns = 0; + register tree parms; + + /* No inlines with varargs. `grokdeclarator' gives a warning + message about that if `inline' is specified. This code + it put in to catch the volunteers. */ + if ((last && TREE_VALUE (last) != void_type_node) + || (DECL_ARGUMENTS (fndecl) && DECL_NAME (DECL_ARGUMENTS (fndecl)) + && ! strcmp (IDENTIFIER_POINTER (DECL_NAME (DECL_ARGUMENTS (fndecl))), + "__builtin_va_alist"))) + return "varargs function cannot be inline"; + + if (current_function_calls_alloca) + return "function using alloca cannot be inline"; + + if (current_function_contains_functions) + return "function with nested functions cannot be inline"; + + /* This restriction may be eliminated sometime soon. But for now, don't + worry about remapping the static chain. */ + if (current_function_needs_context) + return "nested function cannot be inline"; + + /* If its not even close, don't even look. */ + if (!DECL_INLINE (fndecl) && get_max_uid () > 3 * max_insns) + return "function too large to be inline"; + +#if 0 + /* Large stacks are OK now that inlined functions can share them. */ + /* Don't inline functions with large stack usage, + since they can make other recursive functions burn up stack. */ + if (!DECL_INLINE (fndecl) && get_frame_size () > 100) + return "function stack frame for inlining"; +#endif + +#if 0 + /* Don't inline functions which do not specify a function prototype and + have BLKmode argument or take the address of a parameter. */ + for (parms = DECL_ARGUMENTS (fndecl); parms; parms = TREE_CHAIN (parms)) + { + if (TYPE_MODE (TREE_TYPE (parms)) == BLKmode) + TREE_ADDRESSABLE (parms) = 1; + if (last == NULL_TREE && TREE_ADDRESSABLE (parms)) + return "no prototype, and parameter address used; cannot be inline"; + } +#endif + + /* We can't inline functions that return structures + the old-fashioned PCC way, copying into a static block. */ + if (current_function_returns_pcc_struct) + return "inline functions not supported for this return value type"; + + /* We can't inline functions that return structures of varying size. */ + if (int_size_in_bytes (TREE_TYPE (TREE_TYPE (fndecl))) < 0) + return "function with varying-size return value cannot be inline"; + + /* Cannot inline a function with a varying size argument. */ + for (parms = DECL_ARGUMENTS (fndecl); parms; parms = TREE_CHAIN (parms)) + if (int_size_in_bytes (TREE_TYPE (parms)) < 0) + return "function with varying-size parameter cannot be inline"; + + if (!DECL_INLINE (fndecl) && get_max_uid () > max_insns) + { + for (ninsns = 0, insn = get_first_nonparm_insn (); insn && ninsns < max_insns; + insn = NEXT_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + ninsns++; + } + + if (ninsns >= max_insns) + return "function too large to be inline"; + } + + /* We cannot inline this function if forced_labels is non-zero. This + implies that a label in this function was used as an initializer. + Because labels can not be duplicated, all labels in the function + will be renamed when it is inlined. However, there is no way to find + and fix all variables initialized with addresses of labels in this + function, hence inlining is impossible. */ + + if (forced_labels) + return "function with label addresses used in initializers cannot inline"; + + return 0; +} + +/* Variables used within save_for_inline. */ + +/* Mapping from old pseudo-register to new pseudo-registers. + The first element of this map is reg_map[FIRST_PSEUDO_REGISTER]. + It is allocated in `save_for_inline' and `expand_inline_function', + and deallocated on exit from each of those routines. */ +static rtx *reg_map; + +/* Mapping from old code-labels to new code-labels. + The first element of this map is label_map[min_labelno]. + It is allocated in `save_for_inline' and `expand_inline_function', + and deallocated on exit from each of those routines. */ +static rtx *label_map; + +/* Mapping from old insn uid's to copied insns. + It is allocated in `save_for_inline' and `expand_inline_function', + and deallocated on exit from each of those routines. */ +static rtx *insn_map; + +/* Map pseudo reg number into the PARM_DECL for the parm living in the reg. + Zero for a reg that isn't a parm's home. + Only reg numbers less than max_parm_reg are mapped here. */ +static tree *parmdecl_map; + +/* Keep track of first pseudo-register beyond those that are parms. */ +static int max_parm_reg; + +/* When an insn is being copied by copy_for_inline, + this is nonzero if we have copied an ASM_OPERANDS. + In that case, it is the original input-operand vector. */ +static rtvec orig_asm_operands_vector; + +/* When an insn is being copied by copy_for_inline, + this is nonzero if we have copied an ASM_OPERANDS. + In that case, it is the copied input-operand vector. */ +static rtvec copy_asm_operands_vector; + +/* Likewise, this is the copied constraints vector. */ +static rtvec copy_asm_constraints_vector; + +/* In save_for_inline, nonzero if past the parm-initialization insns. */ +static int in_nonparm_insns; + +/* Subroutine for `save_for_inline{copying,nocopy}'. Performs initialization + needed to save FNDECL's insns and info for future inline expansion. */ + +static rtx +initialize_for_inline (fndecl, min_labelno, max_labelno, max_reg, copy) + tree fndecl; + int min_labelno; + int max_labelno; + int max_reg; + int copy; +{ + int function_flags, i; + rtvec arg_vector; + tree parms; + + /* Compute the values of any flags we must restore when inlining this. */ + + function_flags + = (current_function_calls_alloca * FUNCTION_FLAGS_CALLS_ALLOCA + + current_function_calls_setjmp * FUNCTION_FLAGS_CALLS_SETJMP + + current_function_calls_longjmp * FUNCTION_FLAGS_CALLS_LONGJMP + + current_function_returns_struct * FUNCTION_FLAGS_RETURNS_STRUCT + + current_function_returns_pcc_struct * FUNCTION_FLAGS_RETURNS_PCC_STRUCT + + current_function_needs_context * FUNCTION_FLAGS_NEEDS_CONTEXT + + current_function_has_nonlocal_label * FUNCTION_FLAGS_HAS_NONLOCAL_LABEL + + current_function_returns_pointer * FUNCTION_FLAGS_RETURNS_POINTER + + current_function_uses_const_pool * FUNCTION_FLAGS_USES_CONST_POOL + + current_function_uses_pic_offset_table * FUNCTION_FLAGS_USES_PIC_OFFSET_TABLE); + + /* Clear out PARMDECL_MAP. It was allocated in the caller's frame. */ + bzero (parmdecl_map, max_parm_reg * sizeof (tree)); + arg_vector = rtvec_alloc (list_length (DECL_ARGUMENTS (fndecl))); + + for (parms = DECL_ARGUMENTS (fndecl), i = 0; + parms; + parms = TREE_CHAIN (parms), i++) + { + rtx p = DECL_RTL (parms); + + if (GET_CODE (p) == MEM && copy) + { + /* Copy the rtl so that modifications of the addresses + later in compilation won't affect this arg_vector. + Virtual register instantiation can screw the address + of the rtl. */ + rtx new = copy_rtx (p); + + /* Don't leave the old copy anywhere in this decl. */ + if (DECL_RTL (parms) == DECL_INCOMING_RTL (parms) + || (GET_CODE (DECL_RTL (parms)) == MEM + && GET_CODE (DECL_INCOMING_RTL (parms)) == MEM + && (XEXP (DECL_RTL (parms), 0) + == XEXP (DECL_INCOMING_RTL (parms), 0)))) + DECL_INCOMING_RTL (parms) = new; + DECL_RTL (parms) = new; + } + + RTVEC_ELT (arg_vector, i) = p; + + if (GET_CODE (p) == REG) + parmdecl_map[REGNO (p)] = parms; + /* This flag is cleared later + if the function ever modifies the value of the parm. */ + TREE_READONLY (parms) = 1; + } + + /* Assume we start out in the insns that set up the parameters. */ + in_nonparm_insns = 0; + + /* The list of DECL_SAVED_INSNS, starts off with a header which + contains the following information: + + the first insn of the function (not including the insns that copy + parameters into registers). + the first parameter insn of the function, + the first label used by that function, + the last label used by that function, + the highest register number used for parameters, + the total number of registers used, + the size of the incoming stack area for parameters, + the number of bytes popped on return, + the stack slot list, + some flags that are used to restore compiler globals, + the value of current_function_outgoing_args_size, + the original argument vector, + and the original DECL_INITIAL. */ + + return gen_inline_header_rtx (NULL_RTX, NULL_RTX, min_labelno, max_labelno, + max_parm_reg, max_reg, + current_function_args_size, + current_function_pops_args, + stack_slot_list, function_flags, + current_function_outgoing_args_size, + arg_vector, (rtx) DECL_INITIAL (fndecl)); +} + +/* Subroutine for `save_for_inline{copying,nocopy}'. Finishes up the + things that must be done to make FNDECL expandable as an inline function. + HEAD contains the chain of insns to which FNDECL will expand. */ + +static void +finish_inline (fndecl, head) + tree fndecl; + rtx head; +{ + NEXT_INSN (head) = get_first_nonparm_insn (); + FIRST_PARM_INSN (head) = get_insns (); + DECL_SAVED_INSNS (fndecl) = head; + DECL_FRAME_SIZE (fndecl) = get_frame_size (); + DECL_INLINE (fndecl) = 1; +} + +/* Adjust the BLOCK_END_NOTE pointers in a given copied DECL tree so that + they all point to the new (copied) rtxs. */ + +static void +adjust_copied_decl_tree (block) + register tree block; +{ + register tree subblock; + register rtx original_end; + + original_end = BLOCK_END_NOTE (block); + if (original_end) + { + BLOCK_END_NOTE (block) = (rtx) NOTE_SOURCE_FILE (original_end); + NOTE_SOURCE_FILE (original_end) = 0; + } + + /* Process all subblocks. */ + for (subblock = BLOCK_SUBBLOCKS (block); + subblock; + subblock = TREE_CHAIN (subblock)) + adjust_copied_decl_tree (subblock); +} + +/* Make the insns and PARM_DECLs of the current function permanent + and record other information in DECL_SAVED_INSNS to allow inlining + of this function in subsequent calls. + + This function is called when we are going to immediately compile + the insns for FNDECL. The insns in maybepermanent_obstack cannot be + modified by the compilation process, so we copy all of them to + new storage and consider the new insns to be the insn chain to be + compiled. Our caller (rest_of_compilation) saves the original + DECL_INITIAL and DECL_ARGUMENTS; here we copy them. */ + +void +save_for_inline_copying (fndecl) + tree fndecl; +{ + rtx first_insn, last_insn, insn; + rtx head, copy; + int max_labelno, min_labelno, i, len; + int max_reg; + int max_uid; + rtx first_nonparm_insn; + + /* Make and emit a return-label if we have not already done so. + Do this before recording the bounds on label numbers. */ + + if (return_label == 0) + { + return_label = gen_label_rtx (); + emit_label (return_label); + } + + /* Get some bounds on the labels and registers used. */ + + max_labelno = max_label_num (); + min_labelno = get_first_label_num (); + max_reg = max_reg_num (); + + /* Set up PARMDECL_MAP which maps pseudo-reg number to its PARM_DECL. + Later we set TREE_READONLY to 0 if the parm is modified inside the fn. + Also set up ARG_VECTOR, which holds the unmodified DECL_RTX values + for the parms, prior to elimination of virtual registers. + These values are needed for substituting parms properly. */ + + max_parm_reg = max_parm_reg_num (); + parmdecl_map = (tree *) alloca (max_parm_reg * sizeof (tree)); + + head = initialize_for_inline (fndecl, min_labelno, max_labelno, max_reg, 1); + + if (current_function_uses_const_pool) + { + /* Replace any constant pool references with the actual constant. We + will put the constants back in the copy made below. */ + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + save_constants (&PATTERN (insn)); + if (REG_NOTES (insn)) + save_constants (®_NOTES (insn)); + } + + /* Clear out the constant pool so that we can recreate it with the + copied constants below. */ + init_const_rtx_hash_table (); + clear_const_double_mem (); + } + + max_uid = INSN_UID (head); + + /* We have now allocated all that needs to be allocated permanently + on the rtx obstack. Set our high-water mark, so that we + can free the rest of this when the time comes. */ + + preserve_data (); + + /* Copy the chain insns of this function. + Install the copied chain as the insns of this function, + for continued compilation; + the original chain is recorded as the DECL_SAVED_INSNS + for inlining future calls. */ + + /* If there are insns that copy parms from the stack into pseudo registers, + those insns are not copied. `expand_inline_function' must + emit the correct code to handle such things. */ + + insn = get_insns (); + if (GET_CODE (insn) != NOTE) + abort (); + first_insn = rtx_alloc (NOTE); + NOTE_SOURCE_FILE (first_insn) = NOTE_SOURCE_FILE (insn); + NOTE_LINE_NUMBER (first_insn) = NOTE_LINE_NUMBER (insn); + INSN_UID (first_insn) = INSN_UID (insn); + PREV_INSN (first_insn) = NULL; + NEXT_INSN (first_insn) = NULL; + last_insn = first_insn; + + /* Each pseudo-reg in the old insn chain must have a unique rtx in the copy. + Make these new rtx's now, and install them in regno_reg_rtx, so they + will be the official pseudo-reg rtx's for the rest of compilation. */ + + reg_map = (rtx *) alloca ((max_reg + 1) * sizeof (rtx)); + + len = sizeof (struct rtx_def) + (GET_RTX_LENGTH (REG) - 1) * sizeof (rtunion); + for (i = max_reg - 1; i > LAST_VIRTUAL_REGISTER; i--) + reg_map[i] = (rtx)obstack_copy (function_maybepermanent_obstack, + regno_reg_rtx[i], len); + + bcopy (reg_map + LAST_VIRTUAL_REGISTER + 1, + regno_reg_rtx + LAST_VIRTUAL_REGISTER + 1, + (max_reg - (LAST_VIRTUAL_REGISTER + 1)) * sizeof (rtx)); + + /* Likewise each label rtx must have a unique rtx as its copy. */ + + label_map = (rtx *)alloca ((max_labelno - min_labelno) * sizeof (rtx)); + label_map -= min_labelno; + + for (i = min_labelno; i < max_labelno; i++) + label_map[i] = gen_label_rtx (); + + /* Record the mapping of old insns to copied insns. */ + + insn_map = (rtx *) alloca (max_uid * sizeof (rtx)); + bzero (insn_map, max_uid * sizeof (rtx)); + + /* Get the insn which signals the end of parameter setup code. */ + first_nonparm_insn = get_first_nonparm_insn (); + + /* Copy any entries in regno_reg_rtx or DECL_RTLs that reference MEM + (the former occurs when a variable has its address taken) + since these may be shared and can be changed by virtual + register instantiation. DECL_RTL values for our arguments + have already been copied by initialize_for_inline. */ + for (i = LAST_VIRTUAL_REGISTER + 1; i < max_reg; i++) + if (GET_CODE (regno_reg_rtx[i]) == MEM) + XEXP (regno_reg_rtx[i], 0) + = copy_for_inline (XEXP (regno_reg_rtx[i], 0)); + + /* Copy the tree of subblocks of the function, and the decls in them. + We will use the copy for compiling this function, then restore the original + subblocks and decls for use when inlining this function. + + Several parts of the compiler modify BLOCK trees. In particular, + instantiate_virtual_regs will instantiate any virtual regs + mentioned in the DECL_RTLs of the decls, and loop + unrolling will replicate any BLOCK trees inside an unrolled loop. + + The modified subblocks or DECL_RTLs would be incorrect for the original rtl + which we will use for inlining. The rtl might even contain pseudoregs + whose space has been freed. */ + + DECL_INITIAL (fndecl) = copy_decl_tree (DECL_INITIAL (fndecl)); + DECL_ARGUMENTS (fndecl) = copy_decl_list (DECL_ARGUMENTS (fndecl)); + + /* Now copy each DECL_RTL which is a MEM, + so it is safe to modify their addresses. */ + copy_decl_rtls (DECL_INITIAL (fndecl)); + + /* The fndecl node acts as its own progenitor, so mark it as such. */ + DECL_ABSTRACT_ORIGIN (fndecl) = fndecl; + + /* Now copy the chain of insns. Do this twice. The first copy the insn + itself and its body. The second time copy of REG_NOTES. This is because + a REG_NOTE may have a forward pointer to another insn. */ + + for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn)) + { + orig_asm_operands_vector = 0; + + if (insn == first_nonparm_insn) + in_nonparm_insns = 1; + + switch (GET_CODE (insn)) + { + case NOTE: + /* No need to keep these. */ + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) + continue; + + copy = rtx_alloc (NOTE); + NOTE_LINE_NUMBER (copy) = NOTE_LINE_NUMBER (insn); + if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_BLOCK_END) + NOTE_SOURCE_FILE (copy) = NOTE_SOURCE_FILE (insn); + else + { + NOTE_SOURCE_FILE (insn) = (char *) copy; + NOTE_SOURCE_FILE (copy) = 0; + } + break; + + case INSN: + case CALL_INSN: + case JUMP_INSN: + copy = rtx_alloc (GET_CODE (insn)); + PATTERN (copy) = copy_for_inline (PATTERN (insn)); + INSN_CODE (copy) = -1; + LOG_LINKS (copy) = NULL; + RTX_INTEGRATED_P (copy) = RTX_INTEGRATED_P (insn); + break; + + case CODE_LABEL: + copy = label_map[CODE_LABEL_NUMBER (insn)]; + LABEL_NAME (copy) = LABEL_NAME (insn); + break; + + case BARRIER: + copy = rtx_alloc (BARRIER); + break; + + default: + abort (); + } + INSN_UID (copy) = INSN_UID (insn); + insn_map[INSN_UID (insn)] = copy; + NEXT_INSN (last_insn) = copy; + PREV_INSN (copy) = last_insn; + last_insn = copy; + } + + adjust_copied_decl_tree (DECL_INITIAL (fndecl)); + + /* Now copy the REG_NOTES. */ + for (insn = NEXT_INSN (get_insns ()); insn; insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && insn_map[INSN_UID(insn)]) + REG_NOTES (insn_map[INSN_UID (insn)]) + = copy_for_inline (REG_NOTES (insn)); + + NEXT_INSN (last_insn) = NULL; + + finish_inline (fndecl, head); + + set_new_first_and_last_insn (first_insn, last_insn); +} + +/* Return a copy of a chain of nodes, chained through the TREE_CHAIN field. + For example, this can copy a list made of TREE_LIST nodes. While copying, + for each node copied which doesn't already have is DECL_ABSTRACT_ORIGIN + set to some non-zero value, set the DECL_ABSTRACT_ORIGIN of the copy to + point to the corresponding (abstract) original node. */ + +static tree +copy_decl_list (list) + tree list; +{ + tree head; + register tree prev, next; + + if (list == 0) + return 0; + + head = prev = copy_node (list); + if (DECL_ABSTRACT_ORIGIN (head) == NULL_TREE) + DECL_ABSTRACT_ORIGIN (head) = list; + next = TREE_CHAIN (list); + while (next) + { + register tree copy; + + copy = copy_node (next); + if (DECL_ABSTRACT_ORIGIN (copy) == NULL_TREE) + DECL_ABSTRACT_ORIGIN (copy) = next; + TREE_CHAIN (prev) = copy; + prev = copy; + next = TREE_CHAIN (next); + } + return head; +} + +/* Make a copy of the entire tree of blocks BLOCK, and return it. */ + +static tree +copy_decl_tree (block) + tree block; +{ + tree t, vars, subblocks; + + vars = copy_decl_list (BLOCK_VARS (block)); + subblocks = 0; + + /* Process all subblocks. */ + for (t = BLOCK_SUBBLOCKS (block); t; t = TREE_CHAIN (t)) + { + tree copy = copy_decl_tree (t); + TREE_CHAIN (copy) = subblocks; + subblocks = copy; + } + + t = copy_node (block); + BLOCK_VARS (t) = vars; + BLOCK_SUBBLOCKS (t) = nreverse (subblocks); + /* If the BLOCK being cloned is already marked as having been instantiated + from something else, then leave that `origin' marking alone. Elsewise, + mark the clone as having originated from the BLOCK we are cloning. */ + if (BLOCK_ABSTRACT_ORIGIN (t) == NULL_TREE) + BLOCK_ABSTRACT_ORIGIN (t) = block; + return t; +} + +/* Copy DECL_RTLs in all decls in the given BLOCK node. */ + +static void +copy_decl_rtls (block) + tree block; +{ + tree t; + + for (t = BLOCK_VARS (block); t; t = TREE_CHAIN (t)) + if (DECL_RTL (t) && GET_CODE (DECL_RTL (t)) == MEM) + DECL_RTL (t) = copy_for_inline (DECL_RTL (t)); + + /* Process all subblocks. */ + for (t = BLOCK_SUBBLOCKS (block); t; t = TREE_CHAIN (t)) + copy_decl_rtls (t); +} + +/* Make the insns and PARM_DECLs of the current function permanent + and record other information in DECL_SAVED_INSNS to allow inlining + of this function in subsequent calls. + + This routine need not copy any insns because we are not going + to immediately compile the insns in the insn chain. There + are two cases when we would compile the insns for FNDECL: + (1) when FNDECL is expanded inline, and (2) when FNDECL needs to + be output at the end of other compilation, because somebody took + its address. In the first case, the insns of FNDECL are copied + as it is expanded inline, so FNDECL's saved insns are not + modified. In the second case, FNDECL is used for the last time, + so modifying the rtl is not a problem. + + ??? Actually, we do not verify that FNDECL is not inline expanded + by other functions which must also be written down at the end + of compilation. We could set flag_no_inline to nonzero when + the time comes to write down such functions. */ + +void +save_for_inline_nocopy (fndecl) + tree fndecl; +{ + rtx insn; + rtx head, copy; + tree parms; + int max_labelno, min_labelno, i, len; + int max_reg; + int max_uid; + rtx first_nonparm_insn; + int function_flags; + + /* Set up PARMDECL_MAP which maps pseudo-reg number to its PARM_DECL. + Later we set TREE_READONLY to 0 if the parm is modified inside the fn. + Also set up ARG_VECTOR, which holds the unmodified DECL_RTX values + for the parms, prior to elimination of virtual registers. + These values are needed for substituting parms properly. */ + + max_parm_reg = max_parm_reg_num (); + parmdecl_map = (tree *) alloca (max_parm_reg * sizeof (tree)); + + /* Make and emit a return-label if we have not already done so. */ + + if (return_label == 0) + { + return_label = gen_label_rtx (); + emit_label (return_label); + } + + head = initialize_for_inline (fndecl, get_first_label_num (), + max_label_num (), max_reg_num (), 0); + + /* If there are insns that copy parms from the stack into pseudo registers, + those insns are not copied. `expand_inline_function' must + emit the correct code to handle such things. */ + + insn = get_insns (); + if (GET_CODE (insn) != NOTE) + abort (); + + /* Get the insn which signals the end of parameter setup code. */ + first_nonparm_insn = get_first_nonparm_insn (); + + /* Now just scan the chain of insns to see what happens to our + PARM_DECLs. If a PARM_DECL is used but never modified, we + can substitute its rtl directly when expanding inline (and + perform constant folding when its incoming value is constant). + Otherwise, we have to copy its value into a new register and track + the new register's life. */ + + for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn)) + { + if (insn == first_nonparm_insn) + in_nonparm_insns = 1; + + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + if (current_function_uses_const_pool) + { + /* Replace any constant pool references with the actual constant. + We will put the constant back if we need to write the + function out after all. */ + save_constants (&PATTERN (insn)); + if (REG_NOTES (insn)) + save_constants (®_NOTES (insn)); + } + + /* Record what interesting things happen to our parameters. */ + note_stores (PATTERN (insn), note_modified_parmregs); + } + } + + /* We have now allocated all that needs to be allocated permanently + on the rtx obstack. Set our high-water mark, so that we + can free the rest of this when the time comes. */ + + preserve_data (); + + finish_inline (fndecl, head); +} + +/* Given PX, a pointer into an insn, search for references to the constant + pool. Replace each with a CONST that has the mode of the original + constant, contains the constant, and has RTX_INTEGRATED_P set. + Similarly, constant pool addresses not enclosed in a MEM are replaced + with an ADDRESS rtx which also gives the constant, mode, and has + RTX_INTEGRATED_P set. */ + +static void +save_constants (px) + rtx *px; +{ + rtx x; + int i, j; + + again: + x = *px; + + /* If this is a CONST_DOUBLE, don't try to fix things up in + CONST_DOUBLE_MEM, because this is an infinite recursion. */ + if (GET_CODE (x) == CONST_DOUBLE) + return; + else if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (x,0))) + { + enum machine_mode const_mode = get_pool_mode (XEXP (x, 0)); + rtx new = gen_rtx (CONST, const_mode, get_pool_constant (XEXP (x, 0))); + RTX_INTEGRATED_P (new) = 1; + + /* If the MEM was in a different mode than the constant (perhaps we + were only looking at the low-order part), surround it with a + SUBREG so we can save both modes. */ + + if (GET_MODE (x) != const_mode) + { + new = gen_rtx (SUBREG, GET_MODE (x), new, 0); + RTX_INTEGRATED_P (new) = 1; + } + + *px = new; + save_constants (&XEXP (*px, 0)); + } + else if (GET_CODE (x) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (x)) + { + *px = gen_rtx (ADDRESS, get_pool_mode (x), get_pool_constant (x)); + save_constants (&XEXP (*px, 0)); + RTX_INTEGRATED_P (*px) = 1; + } + + else + { + char *fmt = GET_RTX_FORMAT (GET_CODE (x)); + int len = GET_RTX_LENGTH (GET_CODE (x)); + + for (i = len-1; i >= 0; i--) + { + switch (fmt[i]) + { + case 'E': + for (j = 0; j < XVECLEN (x, i); j++) + save_constants (&XVECEXP (x, i, j)); + break; + + case 'e': + if (XEXP (x, i) == 0) + continue; + if (i == 0) + { + /* Hack tail-recursion here. */ + px = &XEXP (x, 0); + goto again; + } + save_constants (&XEXP (x, i)); + break; + } + } + } +} + +/* Note whether a parameter is modified or not. */ + +static void +note_modified_parmregs (reg, x) + rtx reg; + rtx x; +{ + if (GET_CODE (reg) == REG && in_nonparm_insns + && REGNO (reg) < max_parm_reg + && REGNO (reg) >= FIRST_PSEUDO_REGISTER + && parmdecl_map[REGNO (reg)] != 0) + TREE_READONLY (parmdecl_map[REGNO (reg)]) = 0; +} + +/* Copy the rtx ORIG recursively, replacing pseudo-regs and labels + according to `reg_map' and `label_map'. The original rtl insns + will be saved for inlining; this is used to make a copy + which is used to finish compiling the inline function itself. + + If we find a "saved" constant pool entry, one which was replaced with + the value of the constant, convert it back to a constant pool entry. + Since the pool wasn't touched, this should simply restore the old + address. + + All other kinds of rtx are copied except those that can never be + changed during compilation. */ + +static rtx +copy_for_inline (orig) + rtx orig; +{ + register rtx x = orig; + register int i; + register enum rtx_code code; + register char *format_ptr; + + if (x == 0) + return x; + + code = GET_CODE (x); + + /* These types may be freely shared. */ + + switch (code) + { + case QUEUED: + case CONST_INT: + case SYMBOL_REF: + case PC: + case CC0: + return x; + + case CONST_DOUBLE: + /* We have to make a new CONST_DOUBLE to ensure that we account for + it correctly. Using the old CONST_DOUBLE_MEM data is wrong. */ + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) + { + REAL_VALUE_TYPE d; + + REAL_VALUE_FROM_CONST_DOUBLE (d, x); + return immed_real_const_1 (d, GET_MODE (x)); + } + else + return immed_double_const (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x), + VOIDmode); + + case CONST: + /* Get constant pool entry for constant in the pool. */ + if (RTX_INTEGRATED_P (x)) + return validize_mem (force_const_mem (GET_MODE (x), + copy_for_inline (XEXP (x, 0)))); + break; + + case SUBREG: + /* Get constant pool entry, but access in different mode. */ + if (RTX_INTEGRATED_P (x)) + { + rtx new + = force_const_mem (GET_MODE (SUBREG_REG (x)), + copy_for_inline (XEXP (SUBREG_REG (x), 0))); + + PUT_MODE (new, GET_MODE (x)); + return validize_mem (new); + } + break; + + case ADDRESS: + /* If not special for constant pool error. Else get constant pool + address. */ + if (! RTX_INTEGRATED_P (x)) + abort (); + + return XEXP (force_const_mem (GET_MODE (x), + copy_for_inline (XEXP (x, 0))), 0); + + case ASM_OPERANDS: + /* If a single asm insn contains multiple output operands + then it contains multiple ASM_OPERANDS rtx's that share operand 3. + We must make sure that the copied insn continues to share it. */ + if (orig_asm_operands_vector == XVEC (orig, 3)) + { + x = rtx_alloc (ASM_OPERANDS); + XSTR (x, 0) = XSTR (orig, 0); + XSTR (x, 1) = XSTR (orig, 1); + XINT (x, 2) = XINT (orig, 2); + XVEC (x, 3) = copy_asm_operands_vector; + XVEC (x, 4) = copy_asm_constraints_vector; + XSTR (x, 5) = XSTR (orig, 5); + XINT (x, 6) = XINT (orig, 6); + return x; + } + break; + + case MEM: + /* A MEM is usually allowed to be shared if its address is constant + or is a constant plus one of the special registers. + + We do not allow sharing of addresses that are either a special + register or the sum of a constant and a special register because + it is possible for unshare_all_rtl to copy the address, into memory + that won't be saved. Although the MEM can safely be shared, and + won't be copied there, the address itself cannot be shared, and may + need to be copied. + + There are also two exceptions with constants: The first is if the + constant is a LABEL_REF or the sum of the LABEL_REF + and an integer. This case can happen if we have an inline + function that supplies a constant operand to the call of another + inline function that uses it in a switch statement. In this case, + we will be replacing the LABEL_REF, so we have to replace this MEM + as well. + + The second case is if we have a (const (plus (address ..) ...)). + In that case we need to put back the address of the constant pool + entry. */ + + if (CONSTANT_ADDRESS_P (XEXP (x, 0)) + && GET_CODE (XEXP (x, 0)) != LABEL_REF + && ! (GET_CODE (XEXP (x, 0)) == CONST + && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS + && ((GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) + == LABEL_REF) + || (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) + == ADDRESS))))) + return x; + break; + + case LABEL_REF: + { + /* Must point to the new insn. */ + return gen_rtx (LABEL_REF, GET_MODE (orig), + label_map[CODE_LABEL_NUMBER (XEXP (orig, 0))]); + } + + case REG: + if (REGNO (x) > LAST_VIRTUAL_REGISTER) + return reg_map [REGNO (x)]; + else + return x; + + case SET: + /* If a parm that gets modified lives in a pseudo-reg, + clear its TREE_READONLY to prevent certain optimizations. */ + { + rtx dest = SET_DEST (x); + + while (GET_CODE (dest) == STRICT_LOW_PART + || GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == SUBREG) + dest = XEXP (dest, 0); + + if (GET_CODE (dest) == REG + && REGNO (dest) < max_parm_reg + && REGNO (dest) >= FIRST_PSEUDO_REGISTER + && parmdecl_map[REGNO (dest)] != 0 + /* The insn to load an arg pseudo from a stack slot + does not count as modifying it. */ + && in_nonparm_insns) + TREE_READONLY (parmdecl_map[REGNO (dest)]) = 0; + } + break; + +#if 0 /* This is a good idea, but here is the wrong place for it. */ + /* Arrange that CONST_INTs always appear as the second operand + if they appear, and that `frame_pointer_rtx' or `arg_pointer_rtx' + always appear as the first. */ + case PLUS: + if (GET_CODE (XEXP (x, 0)) == CONST_INT + || (XEXP (x, 1) == frame_pointer_rtx + || (ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM + && XEXP (x, 1) == arg_pointer_rtx))) + { + rtx t = XEXP (x, 0); + XEXP (x, 0) = XEXP (x, 1); + XEXP (x, 1) = t; + } + break; +#endif + } + + /* Replace this rtx with a copy of itself. */ + + x = rtx_alloc (code); + bcopy (orig, x, (sizeof (*x) - sizeof (x->fld) + + sizeof (x->fld[0]) * GET_RTX_LENGTH (code))); + + /* Now scan the subexpressions recursively. + We can store any replaced subexpressions directly into X + since we know X is not shared! Any vectors in X + must be copied if X was copied. */ + + format_ptr = GET_RTX_FORMAT (code); + + for (i = 0; i < GET_RTX_LENGTH (code); i++) + { + switch (*format_ptr++) + { + case 'e': + XEXP (x, i) = copy_for_inline (XEXP (x, i)); + break; + + case 'u': + /* Change any references to old-insns to point to the + corresponding copied insns. */ + XEXP (x, i) = insn_map[INSN_UID (XEXP (x, i))]; + break; + + case 'E': + if (XVEC (x, i) != NULL && XVECLEN (x, i) != 0) + { + register int j; + + XVEC (x, i) = gen_rtvec_v (XVECLEN (x, i), &XVECEXP (x, i, 0)); + for (j = 0; j < XVECLEN (x, i); j++) + XVECEXP (x, i, j) + = copy_for_inline (XVECEXP (x, i, j)); + } + break; + } + } + + if (code == ASM_OPERANDS && orig_asm_operands_vector == 0) + { + orig_asm_operands_vector = XVEC (orig, 3); + copy_asm_operands_vector = XVEC (x, 3); + copy_asm_constraints_vector = XVEC (x, 4); + } + + return x; +} + +/* Unfortunately, we need a global copy of const_equiv map for communication + with a function called from note_stores. Be *very* careful that this + is used properly in the presence of recursion. */ + +rtx *global_const_equiv_map; + +#define FIXED_BASE_PLUS_P(X) \ + (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == CONST_INT \ + && GET_CODE (XEXP (X, 0)) == REG \ + && REGNO (XEXP (X, 0)) >= FIRST_VIRTUAL_REGISTER \ + && REGNO (XEXP (X, 0)) <= LAST_VIRTUAL_REGISTER) + +/* Integrate the procedure defined by FNDECL. Note that this function + may wind up calling itself. Since the static variables are not + reentrant, we do not assign them until after the possibility + of recursion is eliminated. + + If IGNORE is nonzero, do not produce a value. + Otherwise store the value in TARGET if it is nonzero and that is convenient. + + Value is: + (rtx)-1 if we could not substitute the function + 0 if we substituted it and it does not produce a value + else an rtx for where the value is stored. */ + +rtx +expand_inline_function (fndecl, parms, target, ignore, type, structure_value_addr) + tree fndecl, parms; + rtx target; + int ignore; + tree type; + rtx structure_value_addr; +{ + tree formal, actual, block; + rtx header = DECL_SAVED_INSNS (fndecl); + rtx insns = FIRST_FUNCTION_INSN (header); + rtx parm_insns = FIRST_PARM_INSN (header); + tree *arg_trees; + rtx *arg_vals; + rtx insn; + int max_regno; + register int i; + int min_labelno = FIRST_LABELNO (header); + int max_labelno = LAST_LABELNO (header); + int nargs; + rtx local_return_label = 0; + rtx loc; + rtx temp; + struct inline_remap *map; + rtx cc0_insn = 0; + rtvec arg_vector = ORIGINAL_ARG_VECTOR (header); + + /* Allow for equivalences of the pseudos we make for virtual fp and ap. */ + max_regno = MAX_REGNUM (header) + 3; + if (max_regno < FIRST_PSEUDO_REGISTER) + abort (); + + nargs = list_length (DECL_ARGUMENTS (fndecl)); + + /* We expect PARMS to have the right length; don't crash if not. */ + if (list_length (parms) != nargs) + return (rtx) (HOST_WIDE_INT) -1; + /* Also check that the parms type match. Since the appropriate + conversions or default promotions have already been applied, + the machine modes should match exactly. */ + for (formal = DECL_ARGUMENTS (fndecl), + actual = parms; + formal; + formal = TREE_CHAIN (formal), + actual = TREE_CHAIN (actual)) + { + tree arg = TREE_VALUE (actual); + enum machine_mode mode = TYPE_MODE (DECL_ARG_TYPE (formal)); + if (mode != TYPE_MODE (TREE_TYPE (arg))) + return (rtx) (HOST_WIDE_INT) -1; + /* If they are block mode, the types should match exactly. + They don't match exactly if TREE_TYPE (FORMAL) == ERROR_MARK_NODE, + which could happen if the parameter has incomplete type. */ + if (mode == BLKmode && TREE_TYPE (arg) != TREE_TYPE (formal)) + return (rtx) (HOST_WIDE_INT) -1; + } + + /* Make a binding contour to keep inline cleanups called at + outer function-scope level from looking like they are shadowing + parameter declarations. */ + pushlevel (0); + + /* Make a fresh binding contour that we can easily remove. */ + pushlevel (0); + expand_start_bindings (0); + if (GET_CODE (parm_insns) == NOTE + && NOTE_LINE_NUMBER (parm_insns) > 0) + { + rtx note = emit_note (NOTE_SOURCE_FILE (parm_insns), + NOTE_LINE_NUMBER (parm_insns)); + if (note) + RTX_INTEGRATED_P (note) = 1; + } + + /* Expand the function arguments. Do this first so that any + new registers get created before we allocate the maps. */ + + arg_vals = (rtx *) alloca (nargs * sizeof (rtx)); + arg_trees = (tree *) alloca (nargs * sizeof (tree)); + + for (formal = DECL_ARGUMENTS (fndecl), actual = parms, i = 0; + formal; + formal = TREE_CHAIN (formal), actual = TREE_CHAIN (actual), i++) + { + /* Actual parameter, converted to the type of the argument within the + function. */ + tree arg = convert (TREE_TYPE (formal), TREE_VALUE (actual)); + /* Mode of the variable used within the function. */ + enum machine_mode mode = TYPE_MODE (TREE_TYPE (formal)); + /* Where parameter is located in the function. */ + rtx copy; + + /* Make sure this formal has some correspondence in the users code + * before emitting any line notes for it. */ + if (DECL_SOURCE_LINE (formal)) + { + rtx note = emit_note (DECL_SOURCE_FILE (formal), + DECL_SOURCE_LINE (formal)); + if (note) + RTX_INTEGRATED_P (note) = 1; + } + + arg_trees[i] = arg; + loc = RTVEC_ELT (arg_vector, i); + + /* If this is an object passed by invisible reference, we copy the + object into a stack slot and save its address. If this will go + into memory, we do nothing now. Otherwise, we just expand the + argument. */ + if (GET_CODE (loc) == MEM && GET_CODE (XEXP (loc, 0)) == REG + && REGNO (XEXP (loc, 0)) > LAST_VIRTUAL_REGISTER) + { + rtx stack_slot + = assign_stack_temp (TYPE_MODE (TREE_TYPE (arg)), + int_size_in_bytes (TREE_TYPE (arg)), 1); + + store_expr (arg, stack_slot, 0); + + arg_vals[i] = XEXP (stack_slot, 0); + } + else if (GET_CODE (loc) != MEM) + { + if (GET_MODE (loc) != TYPE_MODE (TREE_TYPE (arg))) + /* The mode if LOC and ARG can differ if LOC was a variable + that had its mode promoted via PROMOTED_MODE. */ + arg_vals[i] = convert_to_mode (GET_MODE (loc), + expand_expr (arg, NULL_RTX, mode, + EXPAND_SUM), + TREE_UNSIGNED (TREE_TYPE (formal))); + else + arg_vals[i] = expand_expr (arg, NULL_RTX, mode, EXPAND_SUM); + } + else + arg_vals[i] = 0; + + if (arg_vals[i] != 0 + && (! TREE_READONLY (formal) + /* If the parameter is not read-only, copy our argument through + a register. Also, we cannot use ARG_VALS[I] if it overlaps + TARGET in any way. In the inline function, they will likely + be two different pseudos, and `safe_from_p' will make all + sorts of smart assumptions about their not conflicting. + But if ARG_VALS[I] overlaps TARGET, these assumptions are + wrong, so put ARG_VALS[I] into a fresh register. */ + || (target != 0 + && (GET_CODE (arg_vals[i]) == REG + || GET_CODE (arg_vals[i]) == SUBREG + || GET_CODE (arg_vals[i]) == MEM) + && reg_overlap_mentioned_p (arg_vals[i], target)) + /* ??? We must always copy a SUBREG into a REG, because it might + get substituted into an address, and not all ports correctly + handle SUBREGs in addresses. */ + || (GET_CODE (arg_vals[i]) == SUBREG))) + arg_vals[i] = copy_to_mode_reg (GET_MODE (loc), arg_vals[i]); + } + + /* Allocate the structures we use to remap things. */ + + map = (struct inline_remap *) alloca (sizeof (struct inline_remap)); + map->fndecl = fndecl; + + map->reg_map = (rtx *) alloca (max_regno * sizeof (rtx)); + bzero (map->reg_map, max_regno * sizeof (rtx)); + + map->label_map = (rtx *)alloca ((max_labelno - min_labelno) * sizeof (rtx)); + map->label_map -= min_labelno; + + map->insn_map = (rtx *) alloca (INSN_UID (header) * sizeof (rtx)); + bzero (map->insn_map, INSN_UID (header) * sizeof (rtx)); + map->min_insnno = 0; + map->max_insnno = INSN_UID (header); + + map->integrating = 1; + + /* const_equiv_map maps pseudos in our routine to constants, so it needs to + be large enough for all our pseudos. This is the number we are currently + using plus the number in the called routine, plus 15 for each arg, + five to compute the virtual frame pointer, and five for the return value. + This should be enough for most cases. We do not reference entries + outside the range of the map. + + ??? These numbers are quite arbitrary and were obtained by + experimentation. At some point, we should try to allocate the + table after all the parameters are set up so we an more accurately + estimate the number of pseudos we will need. */ + + map->const_equiv_map_size + = max_reg_num () + (max_regno - FIRST_PSEUDO_REGISTER) + 15 * nargs + 10; + + map->const_equiv_map + = (rtx *)alloca (map->const_equiv_map_size * sizeof (rtx)); + bzero (map->const_equiv_map, map->const_equiv_map_size * sizeof (rtx)); + + map->const_age_map + = (unsigned *)alloca (map->const_equiv_map_size * sizeof (unsigned)); + bzero (map->const_age_map, map->const_equiv_map_size * sizeof (unsigned)); + map->const_age = 0; + + /* Record the current insn in case we have to set up pointers to frame + and argument memory blocks. */ + map->insns_at_start = get_last_insn (); + + /* Update the outgoing argument size to allow for those in the inlined + function. */ + if (OUTGOING_ARGS_SIZE (header) > current_function_outgoing_args_size) + current_function_outgoing_args_size = OUTGOING_ARGS_SIZE (header); + + /* If the inline function needs to make PIC references, that means + that this function's PIC offset table must be used. */ + if (FUNCTION_FLAGS (header) & FUNCTION_FLAGS_USES_PIC_OFFSET_TABLE) + current_function_uses_pic_offset_table = 1; + + /* Process each argument. For each, set up things so that the function's + reference to the argument will refer to the argument being passed. + We only replace REG with REG here. Any simplifications are done + via const_equiv_map. + + We make two passes: In the first, we deal with parameters that will + be placed into registers, since we need to ensure that the allocated + register number fits in const_equiv_map. Then we store all non-register + parameters into their memory location. */ + + for (i = 0; i < nargs; i++) + { + rtx copy = arg_vals[i]; + + loc = RTVEC_ELT (arg_vector, i); + + /* There are three cases, each handled separately. */ + if (GET_CODE (loc) == MEM && GET_CODE (XEXP (loc, 0)) == REG + && REGNO (XEXP (loc, 0)) > LAST_VIRTUAL_REGISTER) + { + /* This must be an object passed by invisible reference (it could + also be a variable-sized object, but we forbid inlining functions + with variable-sized arguments). COPY is the address of the + actual value (this computation will cause it to be copied). We + map that address for the register, noting the actual address as + an equivalent in case it can be substituted into the insns. */ + + if (GET_CODE (copy) != REG) + { + temp = copy_addr_to_reg (copy); + if (CONSTANT_P (copy) || FIXED_BASE_PLUS_P (copy)) + { + map->const_equiv_map[REGNO (temp)] = copy; + map->const_age_map[REGNO (temp)] = CONST_AGE_PARM; + } + copy = temp; + } + map->reg_map[REGNO (XEXP (loc, 0))] = copy; + } + else if (GET_CODE (loc) == MEM) + { + /* This is the case of a parameter that lives in memory. + It will live in the block we allocate in the called routine's + frame that simulates the incoming argument area. Do nothing + now; we will call store_expr later. */ + ; + } + else if (GET_CODE (loc) == REG) + { + /* This is the good case where the parameter is in a register. + If it is read-only and our argument is a constant, set up the + constant equivalence. + + If LOC is REG_USERVAR_P, the usual case, COPY must also have + that flag set if it is a register. */ + + if ((GET_CODE (copy) != REG && GET_CODE (copy) != SUBREG) + || (GET_CODE (copy) == REG && REG_USERVAR_P (loc) + && ! REG_USERVAR_P (copy))) + { + temp = copy_to_mode_reg (GET_MODE (loc), copy); + REG_USERVAR_P (temp) = REG_USERVAR_P (loc); + if (CONSTANT_P (copy) || FIXED_BASE_PLUS_P (copy)) + { + map->const_equiv_map[REGNO (temp)] = copy; + map->const_age_map[REGNO (temp)] = CONST_AGE_PARM; + } + copy = temp; + } + map->reg_map[REGNO (loc)] = copy; + } + else + abort (); + + /* Free any temporaries we made setting up this parameter. */ + free_temp_slots (); + } + + /* Now do the parameters that will be placed in memory. */ + + for (formal = DECL_ARGUMENTS (fndecl), i = 0; + formal; formal = TREE_CHAIN (formal), i++) + { + rtx copy = arg_vals[i]; + + loc = RTVEC_ELT (arg_vector, i); + + if (GET_CODE (loc) == MEM + /* Exclude case handled above. */ + && ! (GET_CODE (XEXP (loc, 0)) == REG + && REGNO (XEXP (loc, 0)) > LAST_VIRTUAL_REGISTER)) + { + rtx note = emit_note (DECL_SOURCE_FILE (formal), + DECL_SOURCE_LINE (formal)); + if (note) + RTX_INTEGRATED_P (note) = 1; + + /* Compute the address in the area we reserved and store the + value there. */ + temp = copy_rtx_and_substitute (loc, map); + subst_constants (&temp, NULL_RTX, map); + apply_change_group (); + if (! memory_address_p (GET_MODE (temp), XEXP (temp, 0))) + temp = change_address (temp, VOIDmode, XEXP (temp, 0)); + store_expr (arg_trees[i], temp, 0); + + /* Free any temporaries we made setting up this parameter. */ + free_temp_slots (); + } + } + + /* Deal with the places that the function puts its result. + We are driven by what is placed into DECL_RESULT. + + Initially, we assume that we don't have anything special handling for + REG_FUNCTION_RETURN_VALUE_P. */ + + map->inline_target = 0; + loc = DECL_RTL (DECL_RESULT (fndecl)); + if (TYPE_MODE (type) == VOIDmode) + /* There is no return value to worry about. */ + ; + else if (GET_CODE (loc) == MEM) + { + if (! structure_value_addr || ! aggregate_value_p (DECL_RESULT (fndecl))) + abort (); + + /* Pass the function the address in which to return a structure value. + Note that a constructor can cause someone to call us with + STRUCTURE_VALUE_ADDR, but the initialization takes place + via the first parameter, rather than the struct return address. + + We have two cases: If the address is a simple register indirect, + use the mapping mechanism to point that register to our structure + return address. Otherwise, store the structure return value into + the place that it will be referenced from. */ + + if (GET_CODE (XEXP (loc, 0)) == REG) + { + temp = force_reg (Pmode, structure_value_addr); + map->reg_map[REGNO (XEXP (loc, 0))] = temp; + if (CONSTANT_P (structure_value_addr) + || (GET_CODE (structure_value_addr) == PLUS + && XEXP (structure_value_addr, 0) == virtual_stack_vars_rtx + && GET_CODE (XEXP (structure_value_addr, 1)) == CONST_INT)) + { + map->const_equiv_map[REGNO (temp)] = structure_value_addr; + map->const_age_map[REGNO (temp)] = CONST_AGE_PARM; + } + } + else + { + temp = copy_rtx_and_substitute (loc, map); + subst_constants (&temp, NULL_RTX, map); + apply_change_group (); + emit_move_insn (temp, structure_value_addr); + } + } + else if (ignore) + /* We will ignore the result value, so don't look at its structure. + Note that preparations for an aggregate return value + do need to be made (above) even if it will be ignored. */ + ; + else if (GET_CODE (loc) == REG) + { + /* The function returns an object in a register and we use the return + value. Set up our target for remapping. */ + + /* Machine mode function was declared to return. */ + enum machine_mode departing_mode = TYPE_MODE (type); + /* (Possibly wider) machine mode it actually computes + (for the sake of callers that fail to declare it right). */ + enum machine_mode arriving_mode + = TYPE_MODE (TREE_TYPE (DECL_RESULT (fndecl))); + rtx reg_to_map; + + /* Don't use MEMs as direct targets because on some machines + substituting a MEM for a REG makes invalid insns. + Let the combiner substitute the MEM if that is valid. */ + if (target == 0 || GET_CODE (target) != REG + || GET_MODE (target) != departing_mode) + target = gen_reg_rtx (departing_mode); + + /* If function's value was promoted before return, + avoid machine mode mismatch when we substitute INLINE_TARGET. + But TARGET is what we will return to the caller. */ + if (arriving_mode != departing_mode) + reg_to_map = gen_rtx (SUBREG, arriving_mode, target, 0); + else + reg_to_map = target; + + /* Usually, the result value is the machine's return register. + Sometimes it may be a pseudo. Handle both cases. */ + if (REG_FUNCTION_VALUE_P (loc)) + map->inline_target = reg_to_map; + else + map->reg_map[REGNO (loc)] = reg_to_map; + } + + /* Make new label equivalences for the labels in the called function. */ + for (i = min_labelno; i < max_labelno; i++) + map->label_map[i] = gen_label_rtx (); + + /* Perform postincrements before actually calling the function. */ + emit_queue (); + + /* Clean up stack so that variables might have smaller offsets. */ + do_pending_stack_adjust (); + + /* Save a copy of the location of const_equiv_map for mark_stores, called + via note_stores. */ + global_const_equiv_map = map->const_equiv_map; + + /* Now copy the insns one by one. Do this in two passes, first the insns and + then their REG_NOTES, just like save_for_inline. */ + + /* This loop is very similar to the loop in copy_loop_body in unroll.c. */ + + for (insn = insns; insn; insn = NEXT_INSN (insn)) + { + rtx copy, pattern; + + map->orig_asm_operands_vector = 0; + + switch (GET_CODE (insn)) + { + case INSN: + pattern = PATTERN (insn); + copy = 0; + if (GET_CODE (pattern) == USE + && GET_CODE (XEXP (pattern, 0)) == REG + && REG_FUNCTION_VALUE_P (XEXP (pattern, 0))) + /* The (USE (REG n)) at return from the function should + be ignored since we are changing (REG n) into + inline_target. */ + break; + + /* Ignore setting a function value that we don't want to use. */ + if (map->inline_target == 0 + && GET_CODE (pattern) == SET + && GET_CODE (SET_DEST (pattern)) == REG + && REG_FUNCTION_VALUE_P (SET_DEST (pattern))) + { + if (volatile_refs_p (SET_SRC (pattern))) + { + /* If we must not delete the source, + load it into a new temporary. */ + copy = emit_insn (copy_rtx_and_substitute (pattern, map)); + SET_DEST (PATTERN (copy)) + = gen_reg_rtx (GET_MODE (SET_DEST (PATTERN (copy)))); + } + else + break; + } + else + copy = emit_insn (copy_rtx_and_substitute (pattern, map)); + /* REG_NOTES will be copied later. */ + +#ifdef HAVE_cc0 + /* If this insn is setting CC0, it may need to look at + the insn that uses CC0 to see what type of insn it is. + In that case, the call to recog via validate_change will + fail. So don't substitute constants here. Instead, + do it when we emit the following insn. + + For example, see the pyr.md file. That machine has signed and + unsigned compares. The compare patterns must check the + following branch insn to see which what kind of compare to + emit. + + If the previous insn set CC0, substitute constants on it as + well. */ + if (sets_cc0_p (PATTERN (copy)) != 0) + cc0_insn = copy; + else + { + if (cc0_insn) + try_constants (cc0_insn, map); + cc0_insn = 0; + try_constants (copy, map); + } +#else + try_constants (copy, map); +#endif + break; + + case JUMP_INSN: + if (GET_CODE (PATTERN (insn)) == RETURN) + { + if (local_return_label == 0) + local_return_label = gen_label_rtx (); + pattern = gen_jump (local_return_label); + } + else + pattern = copy_rtx_and_substitute (PATTERN (insn), map); + + copy = emit_jump_insn (pattern); + +#ifdef HAVE_cc0 + if (cc0_insn) + try_constants (cc0_insn, map); + cc0_insn = 0; +#endif + try_constants (copy, map); + + /* If this used to be a conditional jump insn but whose branch + direction is now know, we must do something special. */ + if (condjump_p (insn) && ! simplejump_p (insn) && map->last_pc_value) + { +#ifdef HAVE_cc0 + /* The previous insn set cc0 for us. So delete it. */ + delete_insn (PREV_INSN (copy)); +#endif + + /* If this is now a no-op, delete it. */ + if (map->last_pc_value == pc_rtx) + { + delete_insn (copy); + copy = 0; + } + else + /* Otherwise, this is unconditional jump so we must put a + BARRIER after it. We could do some dead code elimination + here, but jump.c will do it just as well. */ + emit_barrier (); + } + break; + + case CALL_INSN: + pattern = copy_rtx_and_substitute (PATTERN (insn), map); + copy = emit_call_insn (pattern); + +#ifdef HAVE_cc0 + if (cc0_insn) + try_constants (cc0_insn, map); + cc0_insn = 0; +#endif + try_constants (copy, map); + + /* Be lazy and assume CALL_INSNs clobber all hard registers. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + map->const_equiv_map[i] = 0; + break; + + case CODE_LABEL: + copy = emit_label (map->label_map[CODE_LABEL_NUMBER (insn)]); + LABEL_NAME (copy) = LABEL_NAME (insn); + map->const_age++; + break; + + case BARRIER: + copy = emit_barrier (); + break; + + case NOTE: + /* It is important to discard function-end and function-beg notes, + so we have only one of each in the current function. + Also, NOTE_INSN_DELETED notes aren't useful (save_for_inline + deleted these in the copy used for continuing compilation, + not the copy used for inlining). */ + if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_FUNCTION_END + && NOTE_LINE_NUMBER (insn) != NOTE_INSN_FUNCTION_BEG + && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED) + copy = emit_note (NOTE_SOURCE_FILE (insn), NOTE_LINE_NUMBER (insn)); + else + copy = 0; + break; + + default: + abort (); + break; + } + + if (copy) + RTX_INTEGRATED_P (copy) = 1; + + map->insn_map[INSN_UID (insn)] = copy; + } + + /* Now copy the REG_NOTES. Increment const_age, so that only constants + from parameters can be substituted in. These are the only ones that + are valid across the entire function. */ + map->const_age++; + for (insn = insns; insn; insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && map->insn_map[INSN_UID (insn)] + && REG_NOTES (insn)) + { + rtx tem = copy_rtx_and_substitute (REG_NOTES (insn), map); + /* We must also do subst_constants, in case one of our parameters + has const type and constant value. */ + subst_constants (&tem, NULL_RTX, map); + apply_change_group (); + REG_NOTES (map->insn_map[INSN_UID (insn)]) = tem; + } + + if (local_return_label) + emit_label (local_return_label); + + /* Make copies of the decls of the symbols in the inline function, so that + the copies of the variables get declared in the current function. Set + up things so that lookup_static_chain knows that to interpret registers + in SAVE_EXPRs for TYPE_SIZEs as local. */ + + inline_function_decl = fndecl; + integrate_parm_decls (DECL_ARGUMENTS (fndecl), map, arg_vector); + integrate_decl_tree ((tree) ORIGINAL_DECL_INITIAL (header), 0, map); + inline_function_decl = 0; + + /* End the scope containing the copied formal parameter variables + and copied LABEL_DECLs. */ + + expand_end_bindings (getdecls (), 1, 1); + block = poplevel (1, 1, 0); + BLOCK_ABSTRACT_ORIGIN (block) = (DECL_ABSTRACT_ORIGIN (fndecl) == NULL + ? fndecl : DECL_ABSTRACT_ORIGIN (fndecl)); + poplevel (0, 0, 0); + emit_line_note (input_filename, lineno); + + if (structure_value_addr) + { + target = gen_rtx (MEM, TYPE_MODE (type), + memory_address (TYPE_MODE (type), structure_value_addr)); + MEM_IN_STRUCT_P (target) = 1; + } + return target; +} + +/* Given a chain of PARM_DECLs, ARGS, copy each decl into a VAR_DECL, + push all of those decls and give each one the corresponding home. */ + +static void +integrate_parm_decls (args, map, arg_vector) + tree args; + struct inline_remap *map; + rtvec arg_vector; +{ + register tree tail; + register int i; + + for (tail = args, i = 0; tail; tail = TREE_CHAIN (tail), i++) + { + register tree decl = build_decl (VAR_DECL, DECL_NAME (tail), + TREE_TYPE (tail)); + rtx new_decl_rtl + = copy_rtx_and_substitute (RTVEC_ELT (arg_vector, i), map); + + DECL_ARG_TYPE (decl) = DECL_ARG_TYPE (tail); + /* We really should be setting DECL_INCOMING_RTL to something reasonable + here, but that's going to require some more work. */ + /* DECL_INCOMING_RTL (decl) = ?; */ + /* These args would always appear unused, if not for this. */ + TREE_USED (decl) = 1; + /* Prevent warning for shadowing with these. */ + DECL_ABSTRACT_ORIGIN (decl) = tail; + pushdecl (decl); + /* Fully instantiate the address with the equivalent form so that the + debugging information contains the actual register, instead of the + virtual register. Do this by not passing an insn to + subst_constants. */ + subst_constants (&new_decl_rtl, NULL_RTX, map); + apply_change_group (); + DECL_RTL (decl) = new_decl_rtl; + } +} + +/* Given a BLOCK node LET, push decls and levels so as to construct in the + current function a tree of contexts isomorphic to the one that is given. + + LEVEL indicates how far down into the BLOCK tree is the node we are + currently traversing. It is always zero except for recursive calls. + + MAP, if nonzero, is a pointer to an inline_remap map which indicates how + registers used in the DECL_RTL field should be remapped. If it is zero, + no mapping is necessary. */ + +static void +integrate_decl_tree (let, level, map) + tree let; + int level; + struct inline_remap *map; +{ + tree t, node; + + if (level > 0) + pushlevel (0); + + for (t = BLOCK_VARS (let); t; t = TREE_CHAIN (t)) + { + tree d = build_decl (TREE_CODE (t), DECL_NAME (t), TREE_TYPE (t)); + DECL_SOURCE_LINE (d) = DECL_SOURCE_LINE (t); + DECL_SOURCE_FILE (d) = DECL_SOURCE_FILE (t); + if (DECL_RTL (t) != 0) + { + DECL_RTL (d) = copy_rtx_and_substitute (DECL_RTL (t), map); + /* Fully instantiate the address with the equivalent form so that the + debugging information contains the actual register, instead of the + virtual register. Do this by not passing an insn to + subst_constants. */ + subst_constants (&DECL_RTL (d), NULL_RTX, map); + apply_change_group (); + } + else if (DECL_RTL (t)) + DECL_RTL (d) = copy_rtx (DECL_RTL (t)); + DECL_EXTERNAL (d) = DECL_EXTERNAL (t); + TREE_STATIC (d) = TREE_STATIC (t); + TREE_PUBLIC (d) = TREE_PUBLIC (t); + TREE_CONSTANT (d) = TREE_CONSTANT (t); + TREE_ADDRESSABLE (d) = TREE_ADDRESSABLE (t); + TREE_READONLY (d) = TREE_READONLY (t); + TREE_SIDE_EFFECTS (d) = TREE_SIDE_EFFECTS (t); + /* These args would always appear unused, if not for this. */ + TREE_USED (d) = 1; + /* Prevent warning for shadowing with these. */ + DECL_ABSTRACT_ORIGIN (d) = t; + pushdecl (d); + } + + for (t = BLOCK_SUBBLOCKS (let); t; t = TREE_CHAIN (t)) + integrate_decl_tree (t, level + 1, map); + + if (level > 0) + { + node = poplevel (1, 0, 0); + if (node) + { + TREE_USED (node) = TREE_USED (let); + BLOCK_ABSTRACT_ORIGIN (node) = let; + } + } +} + +/* Create a new copy of an rtx. + Recursively copies the operands of the rtx, + except for those few rtx codes that are sharable. + + We always return an rtx that is similar to that incoming rtx, with the + exception of possibly changing a REG to a SUBREG or vice versa. No + rtl is ever emitted. + + Handle constants that need to be placed in the constant pool by + calling `force_const_mem'. */ + +rtx +copy_rtx_and_substitute (orig, map) + register rtx orig; + struct inline_remap *map; +{ + register rtx copy, temp; + register int i, j; + register RTX_CODE code; + register enum machine_mode mode; + register char *format_ptr; + int regno; + + if (orig == 0) + return 0; + + code = GET_CODE (orig); + mode = GET_MODE (orig); + + switch (code) + { + case REG: + /* If the stack pointer register shows up, it must be part of + stack-adjustments (*not* because we eliminated the frame pointer!). + Small hard registers are returned as-is. Pseudo-registers + go through their `reg_map'. */ + regno = REGNO (orig); + if (regno <= LAST_VIRTUAL_REGISTER) + { + /* Some hard registers are also mapped, + but others are not translated. */ + if (map->reg_map[regno] != 0) + return map->reg_map[regno]; + + /* If this is the virtual frame pointer, make space in current + function's stack frame for the stack frame of the inline function. + + Copy the address of this area into a pseudo. Map + virtual_stack_vars_rtx to this pseudo and set up a constant + equivalence for it to be the address. This will substitute the + address into insns where it can be substituted and use the new + pseudo where it can't. */ + if (regno == VIRTUAL_STACK_VARS_REGNUM) + { + rtx loc, seq; + int size = DECL_FRAME_SIZE (map->fndecl); + int rounded; + + start_sequence (); + loc = assign_stack_temp (BLKmode, size, 1); + loc = XEXP (loc, 0); +#ifdef FRAME_GROWS_DOWNWARD + /* In this case, virtual_stack_vars_rtx points to one byte + higher than the top of the frame area. So compute the offset + to one byte higher than our substitute frame. + Keep the fake frame pointer aligned like a real one. */ + rounded = CEIL_ROUND (size, BIGGEST_ALIGNMENT / BITS_PER_UNIT); + loc = plus_constant (loc, rounded); +#endif + map->reg_map[regno] = temp + = force_reg (Pmode, force_operand (loc, NULL_RTX)); + map->const_equiv_map[REGNO (temp)] = loc; + map->const_age_map[REGNO (temp)] = CONST_AGE_PARM; + + seq = gen_sequence (); + end_sequence (); + emit_insn_after (seq, map->insns_at_start); + return temp; + } + else if (regno == VIRTUAL_INCOMING_ARGS_REGNUM) + { + /* Do the same for a block to contain any arguments referenced + in memory. */ + rtx loc, seq; + int size = FUNCTION_ARGS_SIZE (DECL_SAVED_INSNS (map->fndecl)); + + start_sequence (); + loc = assign_stack_temp (BLKmode, size, 1); + loc = XEXP (loc, 0); + /* When arguments grow downward, the virtual incoming + args pointer points to the top of the argument block, + so the remapped location better do the same. */ +#ifdef ARGS_GROW_DOWNWARD + loc = plus_constant (loc, size); +#endif + map->reg_map[regno] = temp + = force_reg (Pmode, force_operand (loc, NULL_RTX)); + map->const_equiv_map[REGNO (temp)] = loc; + map->const_age_map[REGNO (temp)] = CONST_AGE_PARM; + + seq = gen_sequence (); + end_sequence (); + emit_insn_after (seq, map->insns_at_start); + return temp; + } + else if (REG_FUNCTION_VALUE_P (orig)) + { + /* This is a reference to the function return value. If + the function doesn't have a return value, error. If the + mode doesn't agree, make a SUBREG. */ + if (map->inline_target == 0) + /* Must be unrolling loops or replicating code if we + reach here, so return the register unchanged. */ + return orig; + else if (mode != GET_MODE (map->inline_target)) + return gen_lowpart (mode, map->inline_target); + else + return map->inline_target; + } + return orig; + } + if (map->reg_map[regno] == NULL) + { + map->reg_map[regno] = gen_reg_rtx (mode); + REG_USERVAR_P (map->reg_map[regno]) = REG_USERVAR_P (orig); + REG_LOOP_TEST_P (map->reg_map[regno]) = REG_LOOP_TEST_P (orig); + RTX_UNCHANGING_P (map->reg_map[regno]) = RTX_UNCHANGING_P (orig); + /* A reg with REG_FUNCTION_VALUE_P true will never reach here. */ + } + return map->reg_map[regno]; + + case SUBREG: + copy = copy_rtx_and_substitute (SUBREG_REG (orig), map); + /* SUBREG is ordinary, but don't make nested SUBREGs. */ + if (GET_CODE (copy) == SUBREG) + return gen_rtx (SUBREG, GET_MODE (orig), SUBREG_REG (copy), + SUBREG_WORD (orig) + SUBREG_WORD (copy)); + else + return gen_rtx (SUBREG, GET_MODE (orig), copy, + SUBREG_WORD (orig)); + + case USE: + case CLOBBER: + /* USE and CLOBBER are ordinary, but we convert (use (subreg foo)) + to (use foo) if the original insn didn't have a subreg. + Removing the subreg distorts the VAX movstrhi pattern + by changing the mode of an operand. */ + copy = copy_rtx_and_substitute (XEXP (orig, 0), map); + if (GET_CODE (copy) == SUBREG && GET_CODE (XEXP (orig, 0)) != SUBREG) + copy = SUBREG_REG (copy); + return gen_rtx (code, VOIDmode, copy); + + case CODE_LABEL: + LABEL_PRESERVE_P (map->label_map[CODE_LABEL_NUMBER (orig)]) + = LABEL_PRESERVE_P (orig); + return map->label_map[CODE_LABEL_NUMBER (orig)]; + + case LABEL_REF: + copy = rtx_alloc (LABEL_REF); + PUT_MODE (copy, mode); + XEXP (copy, 0) = map->label_map[CODE_LABEL_NUMBER (XEXP (orig, 0))]; + LABEL_OUTSIDE_LOOP_P (copy) = LABEL_OUTSIDE_LOOP_P (orig); + return copy; + + case PC: + case CC0: + case CONST_INT: + return orig; + + case SYMBOL_REF: + /* Symbols which represent the address of a label stored in the constant + pool must be modified to point to a constant pool entry for the + remapped label. Otherwise, symbols are returned unchanged. */ + if (CONSTANT_POOL_ADDRESS_P (orig)) + { + rtx constant = get_pool_constant (orig); + if (GET_CODE (constant) == LABEL_REF) + { + copy = rtx_alloc (LABEL_REF); + PUT_MODE (copy, mode); + XEXP (copy, 0) + = map->label_map[CODE_LABEL_NUMBER (XEXP (constant, 0))]; + LABEL_OUTSIDE_LOOP_P (copy) = LABEL_OUTSIDE_LOOP_P (orig); + copy = force_const_mem (Pmode, copy); + return XEXP (copy, 0); + } + } + return orig; + + case CONST_DOUBLE: + /* We have to make a new copy of this CONST_DOUBLE because don't want + to use the old value of CONST_DOUBLE_MEM. Also, this may be a + duplicate of a CONST_DOUBLE we have already seen. */ + if (GET_MODE_CLASS (GET_MODE (orig)) == MODE_FLOAT) + { + REAL_VALUE_TYPE d; + + REAL_VALUE_FROM_CONST_DOUBLE (d, orig); + return immed_real_const_1 (d, GET_MODE (orig)); + } + else + return immed_double_const (CONST_DOUBLE_LOW (orig), + CONST_DOUBLE_HIGH (orig), VOIDmode); + + case CONST: + /* Make new constant pool entry for a constant + that was in the pool of the inline function. */ + if (RTX_INTEGRATED_P (orig)) + { + /* If this was an address of a constant pool entry that itself + had to be placed in the constant pool, it might not be a + valid address. So the recursive call below might turn it + into a register. In that case, it isn't a constant any + more, so return it. This has the potential of changing a + MEM into a REG, but we'll assume that it safe. */ + temp = copy_rtx_and_substitute (XEXP (orig, 0), map); + if (! CONSTANT_P (temp)) + return temp; + return validize_mem (force_const_mem (GET_MODE (orig), temp)); + } + break; + + case ADDRESS: + /* If from constant pool address, make new constant pool entry and + return its address. */ + if (! RTX_INTEGRATED_P (orig)) + abort (); + + temp = force_const_mem (GET_MODE (orig), + copy_rtx_and_substitute (XEXP (orig, 0), map)); + +#if 0 + /* Legitimizing the address here is incorrect. + + The only ADDRESS rtx's that can reach here are ones created by + save_constants. Hence the operand of the ADDRESS is always legal + in this position of the instruction, since the original rtx without + the ADDRESS was legal. + + The reason we don't legitimize the address here is that on the + Sparc, the caller may have a (high ...) surrounding this ADDRESS. + This code forces the operand of the address to a register, which + fails because we can not take the HIGH part of a register. + + Also, change_address may create new registers. These registers + will not have valid reg_map entries. This can cause try_constants() + to fail because assumes that all registers in the rtx have valid + reg_map entries, and it may end up replacing one of these new + registers with junk. */ + + if (! memory_address_p (GET_MODE (temp), XEXP (temp, 0))) + temp = change_address (temp, GET_MODE (temp), XEXP (temp, 0)); +#endif + + return XEXP (temp, 0); + + case ASM_OPERANDS: + /* If a single asm insn contains multiple output operands + then it contains multiple ASM_OPERANDS rtx's that share operand 3. + We must make sure that the copied insn continues to share it. */ + if (map->orig_asm_operands_vector == XVEC (orig, 3)) + { + copy = rtx_alloc (ASM_OPERANDS); + XSTR (copy, 0) = XSTR (orig, 0); + XSTR (copy, 1) = XSTR (orig, 1); + XINT (copy, 2) = XINT (orig, 2); + XVEC (copy, 3) = map->copy_asm_operands_vector; + XVEC (copy, 4) = map->copy_asm_constraints_vector; + XSTR (copy, 5) = XSTR (orig, 5); + XINT (copy, 6) = XINT (orig, 6); + return copy; + } + break; + + case CALL: + /* This is given special treatment because the first + operand of a CALL is a (MEM ...) which may get + forced into a register for cse. This is undesirable + if function-address cse isn't wanted or if we won't do cse. */ +#ifndef NO_FUNCTION_CSE + if (! (optimize && ! flag_no_function_cse)) +#endif + return gen_rtx (CALL, GET_MODE (orig), + gen_rtx (MEM, GET_MODE (XEXP (orig, 0)), + copy_rtx_and_substitute (XEXP (XEXP (orig, 0), 0), map)), + copy_rtx_and_substitute (XEXP (orig, 1), map)); + break; + +#if 0 + /* Must be ifdefed out for loop unrolling to work. */ + case RETURN: + abort (); +#endif + + case SET: + /* If this is setting fp or ap, it means that we have a nonlocal goto. + Don't alter that. + If the nonlocal goto is into the current function, + this will result in unnecessarily bad code, but should work. */ + if (SET_DEST (orig) == virtual_stack_vars_rtx + || SET_DEST (orig) == virtual_incoming_args_rtx) + return gen_rtx (SET, VOIDmode, SET_DEST (orig), + copy_rtx_and_substitute (SET_SRC (orig), map)); + break; + + case MEM: + copy = rtx_alloc (MEM); + PUT_MODE (copy, mode); + XEXP (copy, 0) = copy_rtx_and_substitute (XEXP (orig, 0), map); + MEM_IN_STRUCT_P (copy) = MEM_IN_STRUCT_P (orig); + MEM_VOLATILE_P (copy) = MEM_VOLATILE_P (orig); + + /* If doing function inlining, this MEM might not be const in the + function that it is being inlined into, and thus may not be + unchanging after function inlining. Constant pool references are + handled elsewhere, so this doesn't lose RTX_UNCHANGING_P bits + for them. */ + if (! map->integrating) + RTX_UNCHANGING_P (copy) = RTX_UNCHANGING_P (orig); + + return copy; + } + + copy = rtx_alloc (code); + PUT_MODE (copy, mode); + copy->in_struct = orig->in_struct; + copy->volatil = orig->volatil; + copy->unchanging = orig->unchanging; + + format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); + + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) + { + switch (*format_ptr++) + { + case '0': + break; + + case 'e': + XEXP (copy, i) = copy_rtx_and_substitute (XEXP (orig, i), map); + break; + + case 'u': + /* Change any references to old-insns to point to the + corresponding copied insns. */ + XEXP (copy, i) = map->insn_map[INSN_UID (XEXP (orig, i))]; + break; + + case 'E': + XVEC (copy, i) = XVEC (orig, i); + if (XVEC (orig, i) != NULL && XVECLEN (orig, i) != 0) + { + XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); + for (j = 0; j < XVECLEN (copy, i); j++) + XVECEXP (copy, i, j) + = copy_rtx_and_substitute (XVECEXP (orig, i, j), map); + } + break; + + case 'w': + XWINT (copy, i) = XWINT (orig, i); + break; + + case 'i': + XINT (copy, i) = XINT (orig, i); + break; + + case 's': + XSTR (copy, i) = XSTR (orig, i); + break; + + default: + abort (); + } + } + + if (code == ASM_OPERANDS && map->orig_asm_operands_vector == 0) + { + map->orig_asm_operands_vector = XVEC (orig, 3); + map->copy_asm_operands_vector = XVEC (copy, 3); + map->copy_asm_constraints_vector = XVEC (copy, 4); + } + + return copy; +} + +/* Substitute known constant values into INSN, if that is valid. */ + +void +try_constants (insn, map) + rtx insn; + struct inline_remap *map; +{ + int i; + + map->num_sets = 0; + subst_constants (&PATTERN (insn), insn, map); + + /* Apply the changes if they are valid; otherwise discard them. */ + apply_change_group (); + + /* Show we don't know the value of anything stored or clobbered. */ + note_stores (PATTERN (insn), mark_stores); + map->last_pc_value = 0; +#ifdef HAVE_cc0 + map->last_cc0_value = 0; +#endif + + /* Set up any constant equivalences made in this insn. */ + for (i = 0; i < map->num_sets; i++) + { + if (GET_CODE (map->equiv_sets[i].dest) == REG) + { + int regno = REGNO (map->equiv_sets[i].dest); + + if (map->const_equiv_map[regno] == 0 + /* Following clause is a hack to make case work where GNU C++ + reassigns a variable to make cse work right. */ + || ! rtx_equal_p (map->const_equiv_map[regno], + map->equiv_sets[i].equiv)) + { + map->const_equiv_map[regno] = map->equiv_sets[i].equiv; + map->const_age_map[regno] = map->const_age; + } + } + else if (map->equiv_sets[i].dest == pc_rtx) + map->last_pc_value = map->equiv_sets[i].equiv; +#ifdef HAVE_cc0 + else if (map->equiv_sets[i].dest == cc0_rtx) + map->last_cc0_value = map->equiv_sets[i].equiv; +#endif + } +} + +/* Substitute known constants for pseudo regs in the contents of LOC, + which are part of INSN. + If INSN is zero, the substitution should always be done (this is used to + update DECL_RTL). + These changes are taken out by try_constants if the result is not valid. + + Note that we are more concerned with determining when the result of a SET + is a constant, for further propagation, than actually inserting constants + into insns; cse will do the latter task better. + + This function is also used to adjust address of items previously addressed + via the virtual stack variable or virtual incoming arguments registers. */ + +static void +subst_constants (loc, insn, map) + rtx *loc; + rtx insn; + struct inline_remap *map; +{ + rtx x = *loc; + register int i; + register enum rtx_code code; + register char *format_ptr; + int num_changes = num_validated_changes (); + rtx new = 0; + enum machine_mode op0_mode; + + code = GET_CODE (x); + + switch (code) + { + case PC: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CONST: + case LABEL_REF: + case ADDRESS: + return; + +#ifdef HAVE_cc0 + case CC0: + validate_change (insn, loc, map->last_cc0_value, 1); + return; +#endif + + case USE: + case CLOBBER: + /* The only thing we can do with a USE or CLOBBER is possibly do + some substitutions in a MEM within it. */ + if (GET_CODE (XEXP (x, 0)) == MEM) + subst_constants (&XEXP (XEXP (x, 0), 0), insn, map); + return; + + case REG: + /* Substitute for parms and known constants. Don't replace + hard regs used as user variables with constants. */ + { + int regno = REGNO (x); + + if (! (regno < FIRST_PSEUDO_REGISTER && REG_USERVAR_P (x)) + && regno < map->const_equiv_map_size + && map->const_equiv_map[regno] != 0 + && map->const_age_map[regno] >= map->const_age) + validate_change (insn, loc, map->const_equiv_map[regno], 1); + return; + } + + case SUBREG: + /* SUBREG applied to something other than a reg + should be treated as ordinary, since that must + be a special hack and we don't know how to treat it specially. + Consider for example mulsidi3 in m68k.md. + Ordinary SUBREG of a REG needs this special treatment. */ + if (GET_CODE (SUBREG_REG (x)) == REG) + { + rtx inner = SUBREG_REG (x); + rtx new = 0; + + /* We can't call subst_constants on &SUBREG_REG (x) because any + constant or SUBREG wouldn't be valid inside our SUBEG. Instead, + see what is inside, try to form the new SUBREG and see if that is + valid. We handle two cases: extracting a full word in an + integral mode and extracting the low part. */ + subst_constants (&inner, NULL_RTX, map); + + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT + && GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD + && GET_MODE (SUBREG_REG (x)) != VOIDmode) + new = operand_subword (inner, SUBREG_WORD (x), 0, + GET_MODE (SUBREG_REG (x))); + + if (new == 0 && subreg_lowpart_p (x)) + new = gen_lowpart_common (GET_MODE (x), inner); + + if (new) + validate_change (insn, loc, new, 1); + + return; + } + break; + + case MEM: + subst_constants (&XEXP (x, 0), insn, map); + + /* If a memory address got spoiled, change it back. */ + if (insn != 0 && num_validated_changes () != num_changes + && !memory_address_p (GET_MODE (x), XEXP (x, 0))) + cancel_changes (num_changes); + return; + + case SET: + { + /* Substitute constants in our source, and in any arguments to a + complex (e..g, ZERO_EXTRACT) destination, but not in the destination + itself. */ + rtx *dest_loc = &SET_DEST (x); + rtx dest = *dest_loc; + rtx src, tem; + + subst_constants (&SET_SRC (x), insn, map); + src = SET_SRC (x); + + while (GET_CODE (*dest_loc) == ZERO_EXTRACT + /* By convention, we always use ZERO_EXTRACT in the dest. */ +/* || GET_CODE (*dest_loc) == SIGN_EXTRACT */ + || GET_CODE (*dest_loc) == SUBREG + || GET_CODE (*dest_loc) == STRICT_LOW_PART) + { + if (GET_CODE (*dest_loc) == ZERO_EXTRACT) + { + subst_constants (&XEXP (*dest_loc, 1), insn, map); + subst_constants (&XEXP (*dest_loc, 2), insn, map); + } + dest_loc = &XEXP (*dest_loc, 0); + } + + /* Do substitute in the address of a destination in memory. */ + if (GET_CODE (*dest_loc) == MEM) + subst_constants (&XEXP (*dest_loc, 0), insn, map); + + /* Check for the case of DEST a SUBREG, both it and the underlying + register are less than one word, and the SUBREG has the wider mode. + In the case, we are really setting the underlying register to the + source converted to the mode of DEST. So indicate that. */ + if (GET_CODE (dest) == SUBREG + && GET_MODE_SIZE (GET_MODE (dest)) <= UNITS_PER_WORD + && GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) <= UNITS_PER_WORD + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) + <= GET_MODE_SIZE (GET_MODE (dest))) + && (tem = gen_lowpart_if_possible (GET_MODE (SUBREG_REG (dest)), + src))) + src = tem, dest = SUBREG_REG (dest); + + /* If storing a recognizable value save it for later recording. */ + if ((map->num_sets < MAX_RECOG_OPERANDS) + && (CONSTANT_P (src) + || (GET_CODE (src) == PLUS + && GET_CODE (XEXP (src, 0)) == REG + && REGNO (XEXP (src, 0)) >= FIRST_VIRTUAL_REGISTER + && REGNO (XEXP (src, 0)) <= LAST_VIRTUAL_REGISTER + && CONSTANT_P (XEXP (src, 1))) + || GET_CODE (src) == COMPARE +#ifdef HAVE_cc0 + || dest == cc0_rtx +#endif + || (dest == pc_rtx + && (src == pc_rtx || GET_CODE (src) == RETURN + || GET_CODE (src) == LABEL_REF)))) + { + /* Normally, this copy won't do anything. But, if SRC is a COMPARE + it will cause us to save the COMPARE with any constants + substituted, which is what we want for later. */ + map->equiv_sets[map->num_sets].equiv = copy_rtx (src); + map->equiv_sets[map->num_sets++].dest = dest; + } + + return; + } + } + + format_ptr = GET_RTX_FORMAT (code); + + /* If the first operand is an expression, save its mode for later. */ + if (*format_ptr == 'e') + op0_mode = GET_MODE (XEXP (x, 0)); + + for (i = 0; i < GET_RTX_LENGTH (code); i++) + { + switch (*format_ptr++) + { + case '0': + break; + + case 'e': + if (XEXP (x, i)) + subst_constants (&XEXP (x, i), insn, map); + break; + + case 'u': + case 'i': + case 's': + case 'w': + break; + + case 'E': + if (XVEC (x, i) != NULL && XVECLEN (x, i) != 0) + { + int j; + for (j = 0; j < XVECLEN (x, i); j++) + subst_constants (&XVECEXP (x, i, j), insn, map); + } + break; + + default: + abort (); + } + } + + /* If this is a commutative operation, move a constant to the second + operand unless the second operand is already a CONST_INT. */ + if ((GET_RTX_CLASS (code) == 'c' || code == NE || code == EQ) + && CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT) + { + rtx tem = XEXP (x, 0); + validate_change (insn, &XEXP (x, 0), XEXP (x, 1), 1); + validate_change (insn, &XEXP (x, 1), tem, 1); + } + + /* Simplify the expression in case we put in some constants. */ + switch (GET_RTX_CLASS (code)) + { + case '1': + new = simplify_unary_operation (code, GET_MODE (x), + XEXP (x, 0), op0_mode); + break; + + case '<': + { + enum machine_mode op_mode = GET_MODE (XEXP (x, 0)); + if (op_mode == VOIDmode) + op_mode = GET_MODE (XEXP (x, 1)); + new = simplify_relational_operation (code, op_mode, + XEXP (x, 0), XEXP (x, 1)); +#ifdef FLOAT_STORE_FLAG_VALUE + if (new != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) + new = ((new == const0_rtx) ? CONST0_RTX (GET_MODE (x)) + : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x))); +#endif + break; + } + + case '2': + case 'c': + new = simplify_binary_operation (code, GET_MODE (x), + XEXP (x, 0), XEXP (x, 1)); + break; + + case 'b': + case '3': + new = simplify_ternary_operation (code, GET_MODE (x), op0_mode, + XEXP (x, 0), XEXP (x, 1), XEXP (x, 2)); + break; + } + + if (new) + validate_change (insn, loc, new, 1); +} + +/* Show that register modified no longer contain known constants. We are + called from note_stores with parts of the new insn. */ + +void +mark_stores (dest, x) + rtx dest; + rtx x; +{ + int regno = -1; + enum machine_mode mode; + + /* DEST is always the innermost thing set, except in the case of + SUBREGs of hard registers. */ + + if (GET_CODE (dest) == REG) + regno = REGNO (dest), mode = GET_MODE (dest); + else if (GET_CODE (dest) == SUBREG && GET_CODE (SUBREG_REG (dest)) == REG) + { + regno = REGNO (SUBREG_REG (dest)) + SUBREG_WORD (dest); + mode = GET_MODE (SUBREG_REG (dest)); + } + + if (regno >= 0) + { + int last_reg = (regno >= FIRST_PSEUDO_REGISTER ? regno + : regno + HARD_REGNO_NREGS (regno, mode) - 1); + int i; + + for (i = regno; i <= last_reg; i++) + global_const_equiv_map[i] = 0; + } +} + +/* If any CONST expressions with RTX_INTEGRATED_P are present in the rtx + pointed to by PX, they represent constants in the constant pool. + Replace these with a new memory reference obtained from force_const_mem. + Similarly, ADDRESS expressions with RTX_INTEGRATED_P represent the + address of a constant pool entry. Replace them with the address of + a new constant pool entry obtained from force_const_mem. */ + +static void +restore_constants (px) + rtx *px; +{ + rtx x = *px; + int i, j; + char *fmt; + + if (x == 0) + return; + + if (GET_CODE (x) == CONST_DOUBLE) + { + /* We have to make a new CONST_DOUBLE to ensure that we account for + it correctly. Using the old CONST_DOUBLE_MEM data is wrong. */ + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) + { + REAL_VALUE_TYPE d; + + REAL_VALUE_FROM_CONST_DOUBLE (d, x); + *px = immed_real_const_1 (d, GET_MODE (x)); + } + else + *px = immed_double_const (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x), + VOIDmode); + } + + else if (RTX_INTEGRATED_P (x) && GET_CODE (x) == CONST) + { + restore_constants (&XEXP (x, 0)); + *px = validize_mem (force_const_mem (GET_MODE (x), XEXP (x, 0))); + } + else if (RTX_INTEGRATED_P (x) && GET_CODE (x) == SUBREG) + { + /* This must be (subreg/i:M1 (const/i:M2 ...) 0). */ + rtx new = XEXP (SUBREG_REG (x), 0); + + restore_constants (&new); + new = force_const_mem (GET_MODE (SUBREG_REG (x)), new); + PUT_MODE (new, GET_MODE (x)); + *px = validize_mem (new); + } + else if (RTX_INTEGRATED_P (x) && GET_CODE (x) == ADDRESS) + { + restore_constants (&XEXP (x, 0)); + *px = XEXP (force_const_mem (GET_MODE (x), XEXP (x, 0)), 0); + } + else + { + fmt = GET_RTX_FORMAT (GET_CODE (x)); + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) + { + switch (*fmt++) + { + case 'E': + for (j = 0; j < XVECLEN (x, i); j++) + restore_constants (&XVECEXP (x, i, j)); + break; + + case 'e': + restore_constants (&XEXP (x, i)); + break; + } + } + } +} + +/* Given a pointer to some BLOCK node, if the BLOCK_ABSTRACT_ORIGIN for the + given BLOCK node is NULL, set the BLOCK_ABSTRACT_ORIGIN for the node so + that it points to the node itself, thus indicating that the node is its + own (abstract) origin. Additionally, if the BLOCK_ABSTRACT_ORIGIN for + the given node is NULL, recursively descend the decl/block tree which + it is the root of, and for each other ..._DECL or BLOCK node contained + therein whose DECL_ABSTRACT_ORIGINs or BLOCK_ABSTRACT_ORIGINs are also + still NULL, set *their* DECL_ABSTRACT_ORIGIN or BLOCK_ABSTRACT_ORIGIN + values to point to themselves. */ + +static void set_decl_origin_self (); + +static void +set_block_origin_self (stmt) + register tree stmt; +{ + if (BLOCK_ABSTRACT_ORIGIN (stmt) == NULL_TREE) + { + BLOCK_ABSTRACT_ORIGIN (stmt) = stmt; + + { + register tree local_decl; + + for (local_decl = BLOCK_VARS (stmt); + local_decl != NULL_TREE; + local_decl = TREE_CHAIN (local_decl)) + set_decl_origin_self (local_decl); /* Potential recursion. */ + } + + { + register tree subblock; + + for (subblock = BLOCK_SUBBLOCKS (stmt); + subblock != NULL_TREE; + subblock = BLOCK_CHAIN (subblock)) + set_block_origin_self (subblock); /* Recurse. */ + } + } +} + +/* Given a pointer to some ..._DECL node, if the DECL_ABSTRACT_ORIGIN for + the given ..._DECL node is NULL, set the DECL_ABSTRACT_ORIGIN for the + node to so that it points to the node itself, thus indicating that the + node represents its own (abstract) origin. Additionally, if the + DECL_ABSTRACT_ORIGIN for the given node is NULL, recursively descend + the decl/block tree of which the given node is the root of, and for + each other ..._DECL or BLOCK node contained therein whose + DECL_ABSTRACT_ORIGINs or BLOCK_ABSTRACT_ORIGINs are also still NULL, + set *their* DECL_ABSTRACT_ORIGIN or BLOCK_ABSTRACT_ORIGIN values to + point to themselves. */ + +static void +set_decl_origin_self (decl) + register tree decl; +{ + if (DECL_ABSTRACT_ORIGIN (decl) == NULL_TREE) + { + DECL_ABSTRACT_ORIGIN (decl) = decl; + if (TREE_CODE (decl) == FUNCTION_DECL) + { + register tree arg; + + for (arg = DECL_ARGUMENTS (decl); arg; arg = TREE_CHAIN (arg)) + DECL_ABSTRACT_ORIGIN (arg) = arg; + if (DECL_INITIAL (decl) != NULL_TREE) + set_block_origin_self (DECL_INITIAL (decl)); + } + } +} + +/* Given a pointer to some BLOCK node, and a boolean value to set the + "abstract" flags to, set that value into the BLOCK_ABSTRACT flag for + the given block, and for all local decls and all local sub-blocks + (recursively) which are contained therein. */ + +void set_decl_abstract_flags (); + +static void +set_block_abstract_flags (stmt, setting) + register tree stmt; + register int setting; +{ + BLOCK_ABSTRACT (stmt) = setting; + + { + register tree local_decl; + + for (local_decl = BLOCK_VARS (stmt); + local_decl != NULL_TREE; + local_decl = TREE_CHAIN (local_decl)) + set_decl_abstract_flags (local_decl, setting); + } + + { + register tree subblock; + + for (subblock = BLOCK_SUBBLOCKS (stmt); + subblock != NULL_TREE; + subblock = BLOCK_CHAIN (subblock)) + set_block_abstract_flags (subblock, setting); + } +} + +/* Given a pointer to some ..._DECL node, and a boolean value to set the + "abstract" flags to, set that value into the DECL_ABSTRACT flag for the + given decl, and (in the case where the decl is a FUNCTION_DECL) also + set the abstract flags for all of the parameters, local vars, local + blocks and sub-blocks (recursively) to the same setting. */ + +void +set_decl_abstract_flags (decl, setting) + register tree decl; + register int setting; +{ + DECL_ABSTRACT (decl) = setting; + if (TREE_CODE (decl) == FUNCTION_DECL) + { + register tree arg; + + for (arg = DECL_ARGUMENTS (decl); arg; arg = TREE_CHAIN (arg)) + DECL_ABSTRACT (arg) = setting; + if (DECL_INITIAL (decl) != NULL_TREE) + set_block_abstract_flags (DECL_INITIAL (decl), setting); + } +} + +/* Output the assembly language code for the function FNDECL + from its DECL_SAVED_INSNS. Used for inline functions that are output + at end of compilation instead of where they came in the source. */ + +void +output_inline_function (fndecl) + tree fndecl; +{ + rtx head = DECL_SAVED_INSNS (fndecl); + rtx last; + + temporary_allocation (); + + current_function_decl = fndecl; + + /* This call is only used to initialize global variables. */ + init_function_start (fndecl, "lossage", 1); + + /* Redo parameter determinations in case the FUNCTION_... + macros took machine-specific actions that need to be redone. */ + assign_parms (fndecl, 1); + + /* Set stack frame size. */ + assign_stack_local (BLKmode, DECL_FRAME_SIZE (fndecl), 0); + + restore_reg_data (FIRST_PARM_INSN (head)); + + stack_slot_list = STACK_SLOT_LIST (head); + + if (FUNCTION_FLAGS (head) & FUNCTION_FLAGS_CALLS_ALLOCA) + current_function_calls_alloca = 1; + + if (FUNCTION_FLAGS (head) & FUNCTION_FLAGS_CALLS_SETJMP) + current_function_calls_setjmp = 1; + + if (FUNCTION_FLAGS (head) & FUNCTION_FLAGS_CALLS_LONGJMP) + current_function_calls_longjmp = 1; + + if (FUNCTION_FLAGS (head) & FUNCTION_FLAGS_RETURNS_STRUCT) + current_function_returns_struct = 1; + + if (FUNCTION_FLAGS (head) & FUNCTION_FLAGS_RETURNS_PCC_STRUCT) + current_function_returns_pcc_struct = 1; + + if (FUNCTION_FLAGS (head) & FUNCTION_FLAGS_NEEDS_CONTEXT) + current_function_needs_context = 1; + + if (FUNCTION_FLAGS (head) & FUNCTION_FLAGS_HAS_NONLOCAL_LABEL) + current_function_has_nonlocal_label = 1; + + if (FUNCTION_FLAGS (head) & FUNCTION_FLAGS_RETURNS_POINTER) + current_function_returns_pointer = 1; + + if (FUNCTION_FLAGS (head) & FUNCTION_FLAGS_USES_CONST_POOL) + current_function_uses_const_pool = 1; + + if (FUNCTION_FLAGS (head) & FUNCTION_FLAGS_USES_PIC_OFFSET_TABLE) + current_function_uses_pic_offset_table = 1; + + current_function_outgoing_args_size = OUTGOING_ARGS_SIZE (head); + current_function_pops_args = POPS_ARGS (head); + + /* There is no need to output a return label again. */ + return_label = 0; + + expand_function_end (DECL_SOURCE_FILE (fndecl), DECL_SOURCE_LINE (fndecl)); + + /* Find last insn and rebuild the constant pool. */ + for (last = FIRST_PARM_INSN (head); + NEXT_INSN (last); last = NEXT_INSN (last)) + { + if (GET_RTX_CLASS (GET_CODE (last)) == 'i') + { + restore_constants (&PATTERN (last)); + restore_constants (®_NOTES (last)); + } + } + + set_new_first_and_last_insn (FIRST_PARM_INSN (head), last); + set_new_first_and_last_label_num (FIRST_LABELNO (head), LAST_LABELNO (head)); + + /* We must have already output DWARF debugging information for the + original (abstract) inline function declaration/definition, so + we want to make sure that the debugging information we generate + for this special instance of the inline function refers back to + the information we already generated. To make sure that happens, + we simply have to set the DECL_ABSTRACT_ORIGIN for the function + node (and for all of the local ..._DECL nodes which are its children) + so that they all point to themselves. */ + + set_decl_origin_self (fndecl); + + /* Compile this function all the way down to assembly code. */ + rest_of_compilation (fndecl); + + current_function_decl = 0; + + permanent_allocation (); +} diff --git a/gnu/usr.bin/cc/lib/integrate.h b/gnu/usr.bin/cc/lib/integrate.h new file mode 100644 index 000000000000..5e776dd3a90d --- /dev/null +++ b/gnu/usr.bin/cc/lib/integrate.h @@ -0,0 +1,120 @@ +/* Function integration definitions for GNU C-Compiler + Copyright (C) 1990 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* This structure is used to remap objects in the function being inlined to + those belonging to the calling function. It is passed by + expand_inline_function to its children. + + This structure is also used when unrolling loops and otherwise + replicating code, although not all fields are needed in this case; + only those fields needed by copy_rtx_and_substitute() and its children + are used. + + This structure is used instead of static variables because + expand_inline_function may be called recursively via expand_expr. */ + +struct inline_remap +{ + /* True if we are doing function integration, false otherwise. + Used to control whether RTX_UNCHANGING bits are copied by + copy_rtx_and_substitute. */ + int integrating; + /* Definition of function be inlined. */ + union tree_node *fndecl; + /* Place to put insns needed at start of function. */ + rtx insns_at_start; + /* Mapping from old registers to new registers. + It is allocated and deallocated in `expand_inline_function' */ + rtx *reg_map; + /* Mapping from old code-labels to new code-labels. + The first element of this map is label_map[min_labelno]. */ + rtx *label_map; + /* Mapping from old insn uid's to copied insns. The first element + of this map is insn_map[min_insnno]; the last element is + insn_map[max_insnno]. We keep the bounds here for when the map + only covers a partial range of insns (such as loop unrolling or + code replication). */ + rtx *insn_map; + int min_insnno, max_insnno; + + /* Map pseudo reg number in calling function to equivalent constant. We + cannot in general substitute constants into parameter pseudo registers, + since some machine descriptions (many RISCs) won't always handle + the resulting insns. So if an incoming parameter has a constant + equivalent, we record it here, and if the resulting insn is + recognizable, we go with it. + + We also use this mechanism to convert references to incoming arguments + and stacked variables. copy_rtx_and_substitute will replace the virtual + incoming argument and virtual stacked variables registers with new + pseudos that contain pointers into the replacement area allocated for + this inline instance. These pseudos are then marked as being equivalent + to the appropriate address and substituted if valid. */ + rtx *const_equiv_map; + /* Number of entries in const_equiv_map and const_arg_map. */ + int const_equiv_map_size; + /* This is incremented for each new basic block. + It is used to store in const_age_map to record the domain of validity + of each entry in const_equiv_map. + A value of -1 indicates an entry for a reg which is a parm. + All other values are "positive". */ +#define CONST_AGE_PARM (-1) + unsigned int const_age; + /* In parallel with const_equiv_map, record the valid age for each entry. + The entry is invalid if its age is less than const_age. */ + unsigned int *const_age_map; + /* Target of the inline function being expanded, or NULL if none. */ + rtx inline_target; + /* When an insn is being copied by copy_rtx_and_substitute, + this is nonzero if we have copied an ASM_OPERANDS. + In that case, it is the original input-operand vector. */ + rtvec orig_asm_operands_vector; + /* When an insn is being copied by copy_rtx_and_substitute, + this is nonzero if we have copied an ASM_OPERANDS. + In that case, it is the copied input-operand vector. */ + rtvec copy_asm_operands_vector; + /* Likewise, this is the copied constraints vector. */ + rtvec copy_asm_constraints_vector; + + /* The next few fields are used for subst_constants to record the SETs + that it saw. */ + int num_sets; + struct equiv_table + { + rtx dest; + rtx equiv; + } equiv_sets[MAX_RECOG_OPERANDS]; + /* Record the last thing assigned to pc. This is used for folded + conditional branch insns. */ + rtx last_pc_value; +#ifdef HAVE_cc0 + /* Record the last thing assigned to cc0. */ + rtx last_cc0_value; +#endif +}; + +/* Return a copy of an rtx (as needed), substituting pseudo-register, + labels, and frame-pointer offsets as necessary. */ +extern rtx copy_rtx_and_substitute PROTO((rtx, struct inline_remap *)); + +extern void try_constants PROTO((rtx, struct inline_remap *)); + +extern void mark_stores PROTO((rtx, rtx)); + +extern rtx *global_const_equiv_map; diff --git a/gnu/usr.bin/cc/lib/jump.c b/gnu/usr.bin/cc/lib/jump.c new file mode 100644 index 000000000000..c5da32a4aa7e --- /dev/null +++ b/gnu/usr.bin/cc/lib/jump.c @@ -0,0 +1,4235 @@ +/* Optimize jump instructions, for GNU compiler. + Copyright (C) 1987, 1988, 1989, 1991, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This is the jump-optimization pass of the compiler. + It is run two or three times: once before cse, sometimes once after cse, + and once after reload (before final). + + jump_optimize deletes unreachable code and labels that are not used. + It also deletes jumps that jump to the following insn, + and simplifies jumps around unconditional jumps and jumps + to unconditional jumps. + + Each CODE_LABEL has a count of the times it is used + stored in the LABEL_NUSES internal field, and each JUMP_INSN + has one label that it refers to stored in the + JUMP_LABEL internal field. With this we can detect labels that + become unused because of the deletion of all the jumps that + formerly used them. The JUMP_LABEL info is sometimes looked + at by later passes. + + Optionally, cross-jumping can be done. Currently it is done + only the last time (when after reload and before final). + In fact, the code for cross-jumping now assumes that register + allocation has been done, since it uses `rtx_renumbered_equal_p'. + + Jump optimization is done after cse when cse's constant-propagation + causes jumps to become unconditional or to be deleted. + + Unreachable loops are not detected here, because the labels + have references and the insns appear reachable from the labels. + find_basic_blocks in flow.c finds and deletes such loops. + + The subroutines delete_insn, redirect_jump, and invert_jump are used + from other passes as well. */ + +#include "config.h" +#include "rtl.h" +#include "flags.h" +#include "hard-reg-set.h" +#include "regs.h" +#include "expr.h" +#include "insn-config.h" +#include "insn-flags.h" +#include "real.h" + +/* ??? Eventually must record somehow the labels used by jumps + from nested functions. */ +/* Pre-record the next or previous real insn for each label? + No, this pass is very fast anyway. */ +/* Condense consecutive labels? + This would make life analysis faster, maybe. */ +/* Optimize jump y; x: ... y: jumpif... x? + Don't know if it is worth bothering with. */ +/* Optimize two cases of conditional jump to conditional jump? + This can never delete any instruction or make anything dead, + or even change what is live at any point. + So perhaps let combiner do it. */ + +/* Vector indexed by uid. + For each CODE_LABEL, index by its uid to get first unconditional jump + that jumps to the label. + For each JUMP_INSN, index by its uid to get the next unconditional jump + that jumps to the same label. + Element 0 is the start of a chain of all return insns. + (It is safe to use element 0 because insn uid 0 is not used. */ + +static rtx *jump_chain; + +/* List of labels referred to from initializers. + These can never be deleted. */ +rtx forced_labels; + +/* Maximum index in jump_chain. */ + +static int max_jump_chain; + +/* Set nonzero by jump_optimize if control can fall through + to the end of the function. */ +int can_reach_end; + +/* Indicates whether death notes are significant in cross jump analysis. + Normally they are not significant, because of A and B jump to C, + and R dies in A, it must die in B. But this might not be true after + stack register conversion, and we must compare death notes in that + case. */ + +static int cross_jump_death_matters = 0; + +static int duplicate_loop_exit_test (); +void redirect_tablejump (); +static int delete_labelref_insn (); +static void mark_jump_label (); +void delete_jump (); +void delete_computation (); +static void delete_from_jump_chain (); +static int tension_vector_labels (); +static void find_cross_jump (); +static void do_cross_jump (); +static int jump_back_p (); + +extern rtx gen_jump (); + +/* Delete no-op jumps and optimize jumps to jumps + and jumps around jumps. + Delete unused labels and unreachable code. + + If CROSS_JUMP is 1, detect matching code + before a jump and its destination and unify them. + If CROSS_JUMP is 2, do cross-jumping, but pay attention to death notes. + + If NOOP_MOVES is nonzero, delete no-op move insns. + + If AFTER_REGSCAN is nonzero, then this jump pass is being run immediately + after regscan, and it is safe to use regno_first_uid and regno_last_uid. + + If `optimize' is zero, don't change any code, + just determine whether control drops off the end of the function. + This case occurs when we have -W and not -O. + It works because `delete_insn' checks the value of `optimize' + and refrains from actually deleting when that is 0. */ + +void +jump_optimize (f, cross_jump, noop_moves, after_regscan) + rtx f; + int cross_jump; + int noop_moves; + int after_regscan; +{ + register rtx insn, next; + int changed; + int first = 1; + int max_uid = 0; + rtx last_insn; + + cross_jump_death_matters = (cross_jump == 2); + + /* Initialize LABEL_NUSES and JUMP_LABEL fields. */ + + for (insn = f; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == CODE_LABEL) + LABEL_NUSES (insn) = (LABEL_PRESERVE_P (insn) != 0); + else if (GET_CODE (insn) == JUMP_INSN) + JUMP_LABEL (insn) = 0; + if (INSN_UID (insn) > max_uid) + max_uid = INSN_UID (insn); + } + + max_uid++; + + /* Delete insns following barriers, up to next label. */ + + for (insn = f; insn;) + { + if (GET_CODE (insn) == BARRIER) + { + insn = NEXT_INSN (insn); + while (insn != 0 && GET_CODE (insn) != CODE_LABEL) + { + if (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) != NOTE_INSN_FUNCTION_END) + insn = NEXT_INSN (insn); + else + insn = delete_insn (insn); + } + /* INSN is now the code_label. */ + } + else + insn = NEXT_INSN (insn); + } + + /* Leave some extra room for labels and duplicate exit test insns + we make. */ + max_jump_chain = max_uid * 14 / 10; + jump_chain = (rtx *) alloca (max_jump_chain * sizeof (rtx)); + bzero (jump_chain, max_jump_chain * sizeof (rtx)); + + /* Mark the label each jump jumps to. + Combine consecutive labels, and count uses of labels. + + For each label, make a chain (using `jump_chain') + of all the *unconditional* jumps that jump to it; + also make a chain of all returns. */ + + for (insn = f; insn; insn = NEXT_INSN (insn)) + if ((GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == INSN + || GET_CODE (insn) == CALL_INSN) + && ! INSN_DELETED_P (insn)) + { + mark_jump_label (PATTERN (insn), insn, cross_jump); + if (GET_CODE (insn) == JUMP_INSN) + { + if (JUMP_LABEL (insn) != 0 && simplejump_p (insn)) + { + jump_chain[INSN_UID (insn)] + = jump_chain[INSN_UID (JUMP_LABEL (insn))]; + jump_chain[INSN_UID (JUMP_LABEL (insn))] = insn; + } + if (GET_CODE (PATTERN (insn)) == RETURN) + { + jump_chain[INSN_UID (insn)] = jump_chain[0]; + jump_chain[0] = insn; + } + } + } + + /* Keep track of labels used from static data; + they cannot ever be deleted. */ + + for (insn = forced_labels; insn; insn = XEXP (insn, 1)) + LABEL_NUSES (XEXP (insn, 0))++; + + /* Delete all labels already not referenced. + Also find the last insn. */ + + last_insn = 0; + for (insn = f; insn; ) + { + if (GET_CODE (insn) == CODE_LABEL && LABEL_NUSES (insn) == 0) + insn = delete_insn (insn); + else + { + last_insn = insn; + insn = NEXT_INSN (insn); + } + } + + if (!optimize) + { + /* See if there is still a NOTE_INSN_FUNCTION_END in this function. + If so record that this function can drop off the end. */ + + insn = last_insn; + { + int n_labels = 1; + while (insn + /* One label can follow the end-note: the return label. */ + && ((GET_CODE (insn) == CODE_LABEL && n_labels-- > 0) + /* Ordinary insns can follow it if returning a structure. */ + || GET_CODE (insn) == INSN + /* If machine uses explicit RETURN insns, no epilogue, + then one of them follows the note. */ + || (GET_CODE (insn) == JUMP_INSN + && GET_CODE (PATTERN (insn)) == RETURN) + /* Other kinds of notes can follow also. */ + || (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) != NOTE_INSN_FUNCTION_END))) + insn = PREV_INSN (insn); + } + + /* Report if control can fall through at the end of the function. */ + if (insn && GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_FUNCTION_END + && ! INSN_DELETED_P (insn)) + can_reach_end = 1; + + /* Zero the "deleted" flag of all the "deleted" insns. */ + for (insn = f; insn; insn = NEXT_INSN (insn)) + INSN_DELETED_P (insn) = 0; + return; + } + +#ifdef HAVE_return + if (HAVE_return) + { + /* If we fall through to the epilogue, see if we can insert a RETURN insn + in front of it. If the machine allows it at this point (we might be + after reload for a leaf routine), it will improve optimization for it + to be there. */ + insn = get_last_insn (); + while (insn && GET_CODE (insn) == NOTE) + insn = PREV_INSN (insn); + + if (insn && GET_CODE (insn) != BARRIER) + { + emit_jump_insn (gen_return ()); + emit_barrier (); + } + } +#endif + + if (noop_moves) + for (insn = f; insn; ) + { + next = NEXT_INSN (insn); + + if (GET_CODE (insn) == INSN) + { + register rtx body = PATTERN (insn); + +/* Combine stack_adjusts with following push_insns. */ +#ifdef PUSH_ROUNDING + if (GET_CODE (body) == SET + && SET_DEST (body) == stack_pointer_rtx + && GET_CODE (SET_SRC (body)) == PLUS + && XEXP (SET_SRC (body), 0) == stack_pointer_rtx + && GET_CODE (XEXP (SET_SRC (body), 1)) == CONST_INT + && INTVAL (XEXP (SET_SRC (body), 1)) > 0) + { + rtx p; + rtx stack_adjust_insn = insn; + int stack_adjust_amount = INTVAL (XEXP (SET_SRC (body), 1)); + int total_pushed = 0; + int pushes = 0; + + /* Find all successive push insns. */ + p = insn; + /* Don't convert more than three pushes; + that starts adding too many displaced addresses + and the whole thing starts becoming a losing + proposition. */ + while (pushes < 3) + { + rtx pbody, dest; + p = next_nonnote_insn (p); + if (p == 0 || GET_CODE (p) != INSN) + break; + pbody = PATTERN (p); + if (GET_CODE (pbody) != SET) + break; + dest = SET_DEST (pbody); + /* Allow a no-op move between the adjust and the push. */ + if (GET_CODE (dest) == REG + && GET_CODE (SET_SRC (pbody)) == REG + && REGNO (dest) == REGNO (SET_SRC (pbody))) + continue; + if (! (GET_CODE (dest) == MEM + && GET_CODE (XEXP (dest, 0)) == POST_INC + && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx)) + break; + pushes++; + if (total_pushed + GET_MODE_SIZE (GET_MODE (SET_DEST (pbody))) + > stack_adjust_amount) + break; + total_pushed += GET_MODE_SIZE (GET_MODE (SET_DEST (pbody))); + } + + /* Discard the amount pushed from the stack adjust; + maybe eliminate it entirely. */ + if (total_pushed >= stack_adjust_amount) + { + delete_insn (stack_adjust_insn); + total_pushed = stack_adjust_amount; + } + else + XEXP (SET_SRC (PATTERN (stack_adjust_insn)), 1) + = GEN_INT (stack_adjust_amount - total_pushed); + + /* Change the appropriate push insns to ordinary stores. */ + p = insn; + while (total_pushed > 0) + { + rtx pbody, dest; + p = next_nonnote_insn (p); + if (GET_CODE (p) != INSN) + break; + pbody = PATTERN (p); + if (GET_CODE (pbody) == SET) + break; + dest = SET_DEST (pbody); + if (! (GET_CODE (dest) == MEM + && GET_CODE (XEXP (dest, 0)) == POST_INC + && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx)) + break; + total_pushed -= GET_MODE_SIZE (GET_MODE (SET_DEST (pbody))); + /* If this push doesn't fully fit in the space + of the stack adjust that we deleted, + make another stack adjust here for what we + didn't use up. There should be peepholes + to recognize the resulting sequence of insns. */ + if (total_pushed < 0) + { + emit_insn_before (gen_add2_insn (stack_pointer_rtx, + GEN_INT (- total_pushed)), + p); + break; + } + XEXP (dest, 0) + = plus_constant (stack_pointer_rtx, total_pushed); + } + } +#endif + + /* Detect and delete no-op move instructions + resulting from not allocating a parameter in a register. */ + + if (GET_CODE (body) == SET + && (SET_DEST (body) == SET_SRC (body) + || (GET_CODE (SET_DEST (body)) == MEM + && GET_CODE (SET_SRC (body)) == MEM + && rtx_equal_p (SET_SRC (body), SET_DEST (body)))) + && ! (GET_CODE (SET_DEST (body)) == MEM + && MEM_VOLATILE_P (SET_DEST (body))) + && ! (GET_CODE (SET_SRC (body)) == MEM + && MEM_VOLATILE_P (SET_SRC (body)))) + delete_insn (insn); + + /* Detect and ignore no-op move instructions + resulting from smart or fortuitous register allocation. */ + + else if (GET_CODE (body) == SET) + { + int sreg = true_regnum (SET_SRC (body)); + int dreg = true_regnum (SET_DEST (body)); + + if (sreg == dreg && sreg >= 0) + delete_insn (insn); + else if (sreg >= 0 && dreg >= 0) + { + rtx trial; + rtx tem = find_equiv_reg (NULL_RTX, insn, 0, + sreg, NULL_PTR, dreg, + GET_MODE (SET_SRC (body))); + +#ifdef PRESERVE_DEATH_INFO_REGNO_P + /* Deleting insn could lose a death-note for SREG or DREG + so don't do it if final needs accurate death-notes. */ + if (! PRESERVE_DEATH_INFO_REGNO_P (sreg) + && ! PRESERVE_DEATH_INFO_REGNO_P (dreg)) +#endif + { + /* DREG may have been the target of a REG_DEAD note in + the insn which makes INSN redundant. If so, reorg + would still think it is dead. So search for such a + note and delete it if we find it. */ + for (trial = prev_nonnote_insn (insn); + trial && GET_CODE (trial) != CODE_LABEL; + trial = prev_nonnote_insn (trial)) + if (find_regno_note (trial, REG_DEAD, dreg)) + { + remove_death (dreg, trial); + break; + } + + if (tem != 0 + && GET_MODE (tem) == GET_MODE (SET_DEST (body))) + delete_insn (insn); + } + } + else if (dreg >= 0 && CONSTANT_P (SET_SRC (body)) + && find_equiv_reg (SET_SRC (body), insn, 0, dreg, + NULL_PTR, 0, + GET_MODE (SET_DEST (body)))) + { + /* This handles the case where we have two consecutive + assignments of the same constant to pseudos that didn't + get a hard reg. Each SET from the constant will be + converted into a SET of the spill register and an + output reload will be made following it. This produces + two loads of the same constant into the same spill + register. */ + + rtx in_insn = insn; + + /* Look back for a death note for the first reg. + If there is one, it is no longer accurate. */ + while (in_insn && GET_CODE (in_insn) != CODE_LABEL) + { + if ((GET_CODE (in_insn) == INSN + || GET_CODE (in_insn) == JUMP_INSN) + && find_regno_note (in_insn, REG_DEAD, dreg)) + { + remove_death (dreg, in_insn); + break; + } + in_insn = PREV_INSN (in_insn); + } + + /* Delete the second load of the value. */ + delete_insn (insn); + } + } + else if (GET_CODE (body) == PARALLEL) + { + /* If each part is a set between two identical registers or + a USE or CLOBBER, delete the insn. */ + int i, sreg, dreg; + rtx tem; + + for (i = XVECLEN (body, 0) - 1; i >= 0; i--) + { + tem = XVECEXP (body, 0, i); + if (GET_CODE (tem) == USE || GET_CODE (tem) == CLOBBER) + continue; + + if (GET_CODE (tem) != SET + || (sreg = true_regnum (SET_SRC (tem))) < 0 + || (dreg = true_regnum (SET_DEST (tem))) < 0 + || dreg != sreg) + break; + } + + if (i < 0) + delete_insn (insn); + } +#if !BYTES_BIG_ENDIAN /* Not worth the hair to detect this + in the big-endian case. */ + /* Also delete insns to store bit fields if they are no-ops. */ + else if (GET_CODE (body) == SET + && GET_CODE (SET_DEST (body)) == ZERO_EXTRACT + && XEXP (SET_DEST (body), 2) == const0_rtx + && XEXP (SET_DEST (body), 0) == SET_SRC (body) + && ! (GET_CODE (SET_SRC (body)) == MEM + && MEM_VOLATILE_P (SET_SRC (body)))) + delete_insn (insn); +#endif /* not BYTES_BIG_ENDIAN */ + } + insn = next; + } + + /* If we haven't yet gotten to reload and we have just run regscan, + delete any insn that sets a register that isn't used elsewhere. + This helps some of the optimizations below by having less insns + being jumped around. */ + + if (! reload_completed && after_regscan) + for (insn = f; insn; insn = next) + { + rtx set = single_set (insn); + + next = NEXT_INSN (insn); + + if (set && GET_CODE (SET_DEST (set)) == REG + && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER + && regno_first_uid[REGNO (SET_DEST (set))] == INSN_UID (insn) + && regno_last_uid[REGNO (SET_DEST (set))] == INSN_UID (insn) + && ! side_effects_p (SET_SRC (set))) + delete_insn (insn); + } + + /* Now iterate optimizing jumps until nothing changes over one pass. */ + changed = 1; + while (changed) + { + changed = 0; + + for (insn = f; insn; insn = next) + { + rtx reallabelprev; + rtx temp, temp1, temp2, temp3, temp4, temp5, temp6; + rtx nlabel; + int this_is_simplejump, this_is_condjump, reversep; +#if 0 + /* If NOT the first iteration, if this is the last jump pass + (just before final), do the special peephole optimizations. + Avoiding the first iteration gives ordinary jump opts + a chance to work before peephole opts. */ + + if (reload_completed && !first && !flag_no_peephole) + if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) + peephole (insn); +#endif + + /* That could have deleted some insns after INSN, so check now + what the following insn is. */ + + next = NEXT_INSN (insn); + + /* See if this is a NOTE_INSN_LOOP_BEG followed by an unconditional + jump. Try to optimize by duplicating the loop exit test if so. + This is only safe immediately after regscan, because it uses + the values of regno_first_uid and regno_last_uid. */ + if (after_regscan && GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG + && (temp1 = next_nonnote_insn (insn)) != 0 + && simplejump_p (temp1)) + { + temp = PREV_INSN (insn); + if (duplicate_loop_exit_test (insn)) + { + changed = 1; + next = NEXT_INSN (temp); + continue; + } + } + + if (GET_CODE (insn) != JUMP_INSN) + continue; + + this_is_simplejump = simplejump_p (insn); + this_is_condjump = condjump_p (insn); + + /* Tension the labels in dispatch tables. */ + + if (GET_CODE (PATTERN (insn)) == ADDR_VEC) + changed |= tension_vector_labels (PATTERN (insn), 0); + if (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) + changed |= tension_vector_labels (PATTERN (insn), 1); + + /* If a dispatch table always goes to the same place, + get rid of it and replace the insn that uses it. */ + + if (GET_CODE (PATTERN (insn)) == ADDR_VEC + || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) + { + int i; + rtx pat = PATTERN (insn); + int diff_vec_p = GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC; + int len = XVECLEN (pat, diff_vec_p); + rtx dispatch = prev_real_insn (insn); + + for (i = 0; i < len; i++) + if (XEXP (XVECEXP (pat, diff_vec_p, i), 0) + != XEXP (XVECEXP (pat, diff_vec_p, 0), 0)) + break; + if (i == len + && dispatch != 0 + && GET_CODE (dispatch) == JUMP_INSN + && JUMP_LABEL (dispatch) != 0 + /* Don't mess with a casesi insn. */ + && !(GET_CODE (PATTERN (dispatch)) == SET + && (GET_CODE (SET_SRC (PATTERN (dispatch))) + == IF_THEN_ELSE)) + && next_real_insn (JUMP_LABEL (dispatch)) == insn) + { + redirect_tablejump (dispatch, + XEXP (XVECEXP (pat, diff_vec_p, 0), 0)); + changed = 1; + } + } + + reallabelprev = prev_active_insn (JUMP_LABEL (insn)); + + /* If a jump references the end of the function, try to turn + it into a RETURN insn, possibly a conditional one. */ + if (JUMP_LABEL (insn) + && next_active_insn (JUMP_LABEL (insn)) == 0) + changed |= redirect_jump (insn, NULL_RTX); + + /* Detect jump to following insn. */ + if (reallabelprev == insn && condjump_p (insn)) + { + delete_jump (insn); + changed = 1; + continue; + } + + /* If we have an unconditional jump preceded by a USE, try to put + the USE before the target and jump there. This simplifies many + of the optimizations below since we don't have to worry about + dealing with these USE insns. We only do this if the label + being branch to already has the identical USE or if code + never falls through to that label. */ + + if (this_is_simplejump + && (temp = prev_nonnote_insn (insn)) != 0 + && GET_CODE (temp) == INSN && GET_CODE (PATTERN (temp)) == USE + && (temp1 = prev_nonnote_insn (JUMP_LABEL (insn))) != 0 + && (GET_CODE (temp1) == BARRIER + || (GET_CODE (temp1) == INSN + && rtx_equal_p (PATTERN (temp), PATTERN (temp1))))) + { + if (GET_CODE (temp1) == BARRIER) + { + emit_insn_after (PATTERN (temp), temp1); + temp1 = NEXT_INSN (temp1); + } + + delete_insn (temp); + redirect_jump (insn, get_label_before (temp1)); + reallabelprev = prev_real_insn (temp1); + changed = 1; + } + + /* Simplify if (...) x = a; else x = b; by converting it + to x = b; if (...) x = a; + if B is sufficiently simple, the test doesn't involve X, + and nothing in the test modifies B or X. + + If we have small register classes, we also can't do this if X + is a hard register. + + If the "x = b;" insn has any REG_NOTES, we don't do this because + of the possibility that we are running after CSE and there is a + REG_EQUAL note that is only valid if the branch has already been + taken. If we move the insn with the REG_EQUAL note, we may + fold the comparison to always be false in a later CSE pass. + (We could also delete the REG_NOTES when moving the insn, but it + seems simpler to not move it.) An exception is that we can move + the insn if the only note is a REG_EQUAL or REG_EQUIV whose + value is the same as "b". + + INSN is the branch over the `else' part. + + We set: + + TEMP to the jump insn preceding "x = a;" + TEMP1 to X + TEMP2 to the insn that sets "x = b;" + TEMP3 to the insn that sets "x = a;" + TEMP4 to the set of "x = b"; */ + + if (this_is_simplejump + && (temp3 = prev_active_insn (insn)) != 0 + && GET_CODE (temp3) == INSN + && (temp4 = single_set (temp3)) != 0 + && GET_CODE (temp1 = SET_DEST (temp4)) == REG +#ifdef SMALL_REGISTER_CLASSES + && REGNO (temp1) >= FIRST_PSEUDO_REGISTER +#endif + && (temp2 = next_active_insn (insn)) != 0 + && GET_CODE (temp2) == INSN + && (temp4 = single_set (temp2)) != 0 + && rtx_equal_p (SET_DEST (temp4), temp1) + && (GET_CODE (SET_SRC (temp4)) == REG + || GET_CODE (SET_SRC (temp4)) == SUBREG + || CONSTANT_P (SET_SRC (temp4))) + && (REG_NOTES (temp2) == 0 + || ((REG_NOTE_KIND (REG_NOTES (temp2)) == REG_EQUAL + || REG_NOTE_KIND (REG_NOTES (temp2)) == REG_EQUIV) + && XEXP (REG_NOTES (temp2), 1) == 0 + && rtx_equal_p (XEXP (REG_NOTES (temp2), 0), + SET_SRC (temp4)))) + && (temp = prev_active_insn (temp3)) != 0 + && condjump_p (temp) && ! simplejump_p (temp) + /* TEMP must skip over the "x = a;" insn */ + && prev_real_insn (JUMP_LABEL (temp)) == insn + && no_labels_between_p (insn, JUMP_LABEL (temp)) + /* There must be no other entries to the "x = b;" insn. */ + && no_labels_between_p (JUMP_LABEL (temp), temp2) + /* INSN must either branch to the insn after TEMP2 or the insn + after TEMP2 must branch to the same place as INSN. */ + && (reallabelprev == temp2 + || ((temp5 = next_active_insn (temp2)) != 0 + && simplejump_p (temp5) + && JUMP_LABEL (temp5) == JUMP_LABEL (insn)))) + { + /* The test expression, X, may be a complicated test with + multiple branches. See if we can find all the uses of + the label that TEMP branches to without hitting a CALL_INSN + or a jump to somewhere else. */ + rtx target = JUMP_LABEL (temp); + int nuses = LABEL_NUSES (target); + rtx p, q; + + /* Set P to the first jump insn that goes around "x = a;". */ + for (p = temp; nuses && p; p = prev_nonnote_insn (p)) + { + if (GET_CODE (p) == JUMP_INSN) + { + if (condjump_p (p) && ! simplejump_p (p) + && JUMP_LABEL (p) == target) + { + nuses--; + if (nuses == 0) + break; + } + else + break; + } + else if (GET_CODE (p) == CALL_INSN) + break; + } + +#ifdef HAVE_cc0 + /* We cannot insert anything between a set of cc and its use + so if P uses cc0, we must back up to the previous insn. */ + q = prev_nonnote_insn (p); + if (q && GET_RTX_CLASS (GET_CODE (q)) == 'i' + && sets_cc0_p (PATTERN (q))) + p = q; +#endif + + if (p) + p = PREV_INSN (p); + + /* If we found all the uses and there was no data conflict, we + can move the assignment unless we can branch into the middle + from somewhere. */ + if (nuses == 0 && p + && no_labels_between_p (p, insn) + && ! reg_referenced_between_p (temp1, p, NEXT_INSN (temp3)) + && ! reg_set_between_p (temp1, p, temp3) + && (GET_CODE (SET_SRC (temp4)) == CONST_INT + || ! reg_set_between_p (SET_SRC (temp4), p, temp2))) + { + emit_insn_after_with_line_notes (PATTERN (temp2), p, temp2); + delete_insn (temp2); + + /* Set NEXT to an insn that we know won't go away. */ + next = next_active_insn (insn); + + /* Delete the jump around the set. Note that we must do + this before we redirect the test jumps so that it won't + delete the code immediately following the assignment + we moved (which might be a jump). */ + + delete_insn (insn); + + /* We either have two consecutive labels or a jump to + a jump, so adjust all the JUMP_INSNs to branch to where + INSN branches to. */ + for (p = NEXT_INSN (p); p != next; p = NEXT_INSN (p)) + if (GET_CODE (p) == JUMP_INSN) + redirect_jump (p, target); + + changed = 1; + continue; + } + } + +#ifndef HAVE_cc0 + /* If we have if (...) x = exp; and branches are expensive, + EXP is a single insn, does not have any side effects, cannot + trap, and is not too costly, convert this to + t = exp; if (...) x = t; + + Don't do this when we have CC0 because it is unlikely to help + and we'd need to worry about where to place the new insn and + the potential for conflicts. We also can't do this when we have + notes on the insn for the same reason as above. + + We set: + + TEMP to the "x = exp;" insn. + TEMP1 to the single set in the "x = exp; insn. + TEMP2 to "x". */ + + if (! reload_completed + && this_is_condjump && ! this_is_simplejump + && BRANCH_COST >= 3 + && (temp = next_nonnote_insn (insn)) != 0 + && GET_CODE (temp) == INSN + && REG_NOTES (temp) == 0 + && (reallabelprev == temp + || ((temp2 = next_active_insn (temp)) != 0 + && simplejump_p (temp2) + && JUMP_LABEL (temp2) == JUMP_LABEL (insn))) + && (temp1 = single_set (temp)) != 0 + && (temp2 = SET_DEST (temp1), GET_CODE (temp2) == REG) + && GET_MODE_CLASS (GET_MODE (temp2)) == MODE_INT +#ifdef SMALL_REGISTER_CLASSES + && REGNO (temp2) >= FIRST_PSEUDO_REGISTER +#endif + && GET_CODE (SET_SRC (temp1)) != REG + && GET_CODE (SET_SRC (temp1)) != SUBREG + && GET_CODE (SET_SRC (temp1)) != CONST_INT + && ! side_effects_p (SET_SRC (temp1)) + && ! may_trap_p (SET_SRC (temp1)) + && rtx_cost (SET_SRC (temp1)) < 10) + { + rtx new = gen_reg_rtx (GET_MODE (temp2)); + + if (validate_change (temp, &SET_DEST (temp1), new, 0)) + { + next = emit_insn_after (gen_move_insn (temp2, new), insn); + emit_insn_after_with_line_notes (PATTERN (temp), + PREV_INSN (insn), temp); + delete_insn (temp); + } + } + + /* Similarly, if it takes two insns to compute EXP but they + have the same destination. Here TEMP3 will be the second + insn and TEMP4 the SET from that insn. */ + + if (! reload_completed + && this_is_condjump && ! this_is_simplejump + && BRANCH_COST >= 4 + && (temp = next_nonnote_insn (insn)) != 0 + && GET_CODE (temp) == INSN + && REG_NOTES (temp) == 0 + && (temp3 = next_nonnote_insn (temp)) != 0 + && GET_CODE (temp3) == INSN + && REG_NOTES (temp3) == 0 + && (reallabelprev == temp3 + || ((temp2 = next_active_insn (temp3)) != 0 + && simplejump_p (temp2) + && JUMP_LABEL (temp2) == JUMP_LABEL (insn))) + && (temp1 = single_set (temp)) != 0 + && (temp2 = SET_DEST (temp1), GET_CODE (temp2) == REG) + && GET_MODE_CLASS (GET_MODE (temp2)) == MODE_INT +#ifdef SMALL_REGISTER_CLASSES + && REGNO (temp2) >= FIRST_PSEUDO_REGISTER +#endif + && ! side_effects_p (SET_SRC (temp1)) + && ! may_trap_p (SET_SRC (temp1)) + && rtx_cost (SET_SRC (temp1)) < 10 + && (temp4 = single_set (temp3)) != 0 + && rtx_equal_p (SET_DEST (temp4), temp2) + && ! side_effects_p (SET_SRC (temp4)) + && ! may_trap_p (SET_SRC (temp4)) + && rtx_cost (SET_SRC (temp4)) < 10) + { + rtx new = gen_reg_rtx (GET_MODE (temp2)); + + if (validate_change (temp, &SET_DEST (temp1), new, 0)) + { + next = emit_insn_after (gen_move_insn (temp2, new), insn); + emit_insn_after_with_line_notes (PATTERN (temp), + PREV_INSN (insn), temp); + emit_insn_after_with_line_notes + (replace_rtx (PATTERN (temp3), temp2, new), + PREV_INSN (insn), temp3); + delete_insn (temp); + delete_insn (temp3); + } + } + + /* Finally, handle the case where two insns are used to + compute EXP but a temporary register is used. Here we must + ensure that the temporary register is not used anywhere else. */ + + if (! reload_completed + && after_regscan + && this_is_condjump && ! this_is_simplejump + && BRANCH_COST >= 4 + && (temp = next_nonnote_insn (insn)) != 0 + && GET_CODE (temp) == INSN + && REG_NOTES (temp) == 0 + && (temp3 = next_nonnote_insn (temp)) != 0 + && GET_CODE (temp3) == INSN + && REG_NOTES (temp3) == 0 + && (reallabelprev == temp3 + || ((temp2 = next_active_insn (temp3)) != 0 + && simplejump_p (temp2) + && JUMP_LABEL (temp2) == JUMP_LABEL (insn))) + && (temp1 = single_set (temp)) != 0 + && (temp5 = SET_DEST (temp1), GET_CODE (temp5) == REG) + && REGNO (temp5) >= FIRST_PSEUDO_REGISTER + && regno_first_uid[REGNO (temp5)] == INSN_UID (temp) + && regno_last_uid[REGNO (temp5)] == INSN_UID (temp3) + && ! side_effects_p (SET_SRC (temp1)) + && ! may_trap_p (SET_SRC (temp1)) + && rtx_cost (SET_SRC (temp1)) < 10 + && (temp4 = single_set (temp3)) != 0 + && (temp2 = SET_DEST (temp4), GET_CODE (temp2) == REG) + && GET_MODE_CLASS (GET_MODE (temp2)) == MODE_INT +#ifdef SMALL_REGISTER_CLASSES + && REGNO (temp2) >= FIRST_PSEUDO_REGISTER +#endif + && rtx_equal_p (SET_DEST (temp4), temp2) + && ! side_effects_p (SET_SRC (temp4)) + && ! may_trap_p (SET_SRC (temp4)) + && rtx_cost (SET_SRC (temp4)) < 10) + { + rtx new = gen_reg_rtx (GET_MODE (temp2)); + + if (validate_change (temp3, &SET_DEST (temp4), new, 0)) + { + next = emit_insn_after (gen_move_insn (temp2, new), insn); + emit_insn_after_with_line_notes (PATTERN (temp), + PREV_INSN (insn), temp); + emit_insn_after_with_line_notes (PATTERN (temp3), + PREV_INSN (insn), temp3); + delete_insn (temp); + delete_insn (temp3); + } + } +#endif /* HAVE_cc0 */ + + /* We deal with four cases: + + 1) x = a; if (...) x = b; and either A or B is zero, + 2) if (...) x = 0; and jumps are expensive, + 3) x = a; if (...) x = b; and A and B are constants where all the + set bits in A are also set in B and jumps are expensive, and + 4) x = a; if (...) x = b; and A and B non-zero, and jumps are + more expensive. + 5) if (...) x = b; if jumps are even more expensive. + + In each of these try to use a store-flag insn to avoid the jump. + (If the jump would be faster, the machine should not have + defined the scc insns!). These cases are often made by the + previous optimization. + + INSN here is the jump around the store. We set: + + TEMP to the "x = b;" insn. + TEMP1 to X. + TEMP2 to B (const0_rtx in the second case). + TEMP3 to A (X in the second case). + TEMP4 to the condition being tested. + TEMP5 to the earliest insn used to find the condition. */ + + if (/* We can't do this after reload has completed. */ + ! reload_completed + && this_is_condjump && ! this_is_simplejump + /* Set TEMP to the "x = b;" insn. */ + && (temp = next_nonnote_insn (insn)) != 0 + && GET_CODE (temp) == INSN + && GET_CODE (PATTERN (temp)) == SET + && GET_CODE (temp1 = SET_DEST (PATTERN (temp))) == REG +#ifdef SMALL_REGISTER_CLASSES + && REGNO (temp1) >= FIRST_PSEUDO_REGISTER +#endif + && GET_MODE_CLASS (GET_MODE (temp1)) == MODE_INT + && (GET_CODE (temp2 = SET_SRC (PATTERN (temp))) == REG + || GET_CODE (temp2) == SUBREG + || GET_CODE (temp2) == CONST_INT) + /* Allow either form, but prefer the former if both apply. + There is no point in using the old value of TEMP1 if + it is a register, since cse will alias them. It can + lose if the old value were a hard register since CSE + won't replace hard registers. */ + && (((temp3 = reg_set_last (temp1, insn)) != 0 + && GET_CODE (temp3) == CONST_INT) + /* Make the latter case look like x = x; if (...) x = 0; */ + || (temp3 = temp1, + ((BRANCH_COST >= 2 + && temp2 == const0_rtx) +#ifdef HAVE_conditional_move + || 1 +#endif + || BRANCH_COST >= 3))) + /* INSN must either branch to the insn after TEMP or the insn + after TEMP must branch to the same place as INSN. */ + && (reallabelprev == temp + || ((temp4 = next_active_insn (temp)) != 0 + && simplejump_p (temp4) + && JUMP_LABEL (temp4) == JUMP_LABEL (insn))) + && (temp4 = get_condition (insn, &temp5)) != 0 + /* We must be comparing objects whose modes imply the size. + We could handle BLKmode if (1) emit_store_flag could + and (2) we could find the size reliably. */ + && GET_MODE (XEXP (temp4, 0)) != BLKmode + + /* If B is zero, OK; if A is zero, can only do (1) if we + can reverse the condition. See if (3) applies possibly + by reversing the condition. Prefer reversing to (4) when + branches are very expensive. */ + && ((reversep = 0, temp2 == const0_rtx) + || (temp3 == const0_rtx + && (reversep = can_reverse_comparison_p (temp4, insn))) + || (BRANCH_COST >= 2 + && GET_CODE (temp2) == CONST_INT + && GET_CODE (temp3) == CONST_INT + && ((INTVAL (temp2) & INTVAL (temp3)) == INTVAL (temp2) + || ((INTVAL (temp2) & INTVAL (temp3)) == INTVAL (temp3) + && (reversep = can_reverse_comparison_p (temp4, + insn))))) +#ifdef HAVE_conditional_move + || 1 +#endif + || BRANCH_COST >= 3) +#ifdef HAVE_cc0 + /* If the previous insn sets CC0 and something else, we can't + do this since we are going to delete that insn. */ + + && ! ((temp6 = prev_nonnote_insn (insn)) != 0 + && GET_CODE (temp6) == INSN + && (sets_cc0_p (PATTERN (temp6)) == -1 + || (sets_cc0_p (PATTERN (temp6)) == 1 + && FIND_REG_INC_NOTE (temp6, NULL_RTX)))) +#endif + ) + { + enum rtx_code code = GET_CODE (temp4); + rtx uval, cval, var = temp1; + int normalizep; + rtx target; + + /* If necessary, reverse the condition. */ + if (reversep) + code = reverse_condition (code), uval = temp2, cval = temp3; + else + uval = temp3, cval = temp2; + + /* See if we can do this with a store-flag insn. */ + start_sequence (); + + /* If CVAL is non-zero, normalize to -1. Otherwise, + if UVAL is the constant 1, it is best to just compute + the result directly. If UVAL is constant and STORE_FLAG_VALUE + includes all of its bits, it is best to compute the flag + value unnormalized and `and' it with UVAL. Otherwise, + normalize to -1 and `and' with UVAL. */ + normalizep = (cval != const0_rtx ? -1 + : (uval == const1_rtx ? 1 + : (GET_CODE (uval) == CONST_INT + && (INTVAL (uval) & ~STORE_FLAG_VALUE) == 0) + ? 0 : -1)); + + /* We will be putting the store-flag insn immediately in + front of the comparison that was originally being done, + so we know all the variables in TEMP4 will be valid. + However, this might be in front of the assignment of + A to VAR. If it is, it would clobber the store-flag + we will be emitting. + + Therefore, emit into a temporary which will be copied to + VAR immediately after TEMP. */ + + target = emit_store_flag (gen_reg_rtx (GET_MODE (var)), code, + XEXP (temp4, 0), XEXP (temp4, 1), + VOIDmode, + (code == LTU || code == LEU + || code == GEU || code == GTU), + normalizep); + if (target) + { + rtx before = insn; + rtx seq; + + /* Put the store-flag insns in front of the first insn + used to compute the condition to ensure that we + use the same values of them as the current + comparison. However, the remainder of the insns we + generate will be placed directly in front of the + jump insn, in case any of the pseudos we use + are modified earlier. */ + + seq = get_insns (); + end_sequence (); + + emit_insns_before (seq, temp5); + + start_sequence (); + + /* Both CVAL and UVAL are non-zero. */ + if (cval != const0_rtx && uval != const0_rtx) + { + rtx tem1, tem2; + + tem1 = expand_and (uval, target, NULL_RTX); + if (GET_CODE (cval) == CONST_INT + && GET_CODE (uval) == CONST_INT + && (INTVAL (cval) & INTVAL (uval)) == INTVAL (cval)) + tem2 = cval; + else + { + tem2 = expand_unop (GET_MODE (var), one_cmpl_optab, + target, NULL_RTX, 0); + tem2 = expand_and (cval, tem2, + (GET_CODE (tem2) == REG + ? tem2 : 0)); + } + + /* If we usually make new pseudos, do so here. This + turns out to help machines that have conditional + move insns. */ + + if (flag_expensive_optimizations) + target = 0; + + target = expand_binop (GET_MODE (var), ior_optab, + tem1, tem2, target, + 1, OPTAB_WIDEN); + } + else if (normalizep != 1) + target = expand_and (uval, target, + (GET_CODE (target) == REG + && ! preserve_subexpressions_p () + ? target : NULL_RTX)); + + emit_move_insn (var, target); + seq = get_insns (); + end_sequence (); + +#ifdef HAVE_cc0 + /* If INSN uses CC0, we must not separate it from the + insn that sets cc0. */ + + if (reg_mentioned_p (cc0_rtx, PATTERN (before))) + before = prev_nonnote_insn (before); +#endif + + emit_insns_before (seq, before); + + delete_insn (temp); + next = NEXT_INSN (insn); + + delete_jump (insn); + changed = 1; + continue; + } + else + end_sequence (); + } + + /* If branches are expensive, convert + if (foo) bar++; to bar += (foo != 0); + and similarly for "bar--;" + + INSN is the conditional branch around the arithmetic. We set: + + TEMP is the arithmetic insn. + TEMP1 is the SET doing the arithmetic. + TEMP2 is the operand being incremented or decremented. + TEMP3 to the condition being tested. + TEMP4 to the earliest insn used to find the condition. */ + + if ((BRANCH_COST >= 2 +#ifdef HAVE_incscc + || HAVE_incscc +#endif +#ifdef HAVE_decscc + || HAVE_decscc +#endif + ) + && ! reload_completed + && this_is_condjump && ! this_is_simplejump + && (temp = next_nonnote_insn (insn)) != 0 + && (temp1 = single_set (temp)) != 0 + && (temp2 = SET_DEST (temp1), + GET_MODE_CLASS (GET_MODE (temp2)) == MODE_INT) + && GET_CODE (SET_SRC (temp1)) == PLUS + && (XEXP (SET_SRC (temp1), 1) == const1_rtx + || XEXP (SET_SRC (temp1), 1) == constm1_rtx) + && rtx_equal_p (temp2, XEXP (SET_SRC (temp1), 0)) + /* INSN must either branch to the insn after TEMP or the insn + after TEMP must branch to the same place as INSN. */ + && (reallabelprev == temp + || ((temp3 = next_active_insn (temp)) != 0 + && simplejump_p (temp3) + && JUMP_LABEL (temp3) == JUMP_LABEL (insn))) + && (temp3 = get_condition (insn, &temp4)) != 0 + /* We must be comparing objects whose modes imply the size. + We could handle BLKmode if (1) emit_store_flag could + and (2) we could find the size reliably. */ + && GET_MODE (XEXP (temp3, 0)) != BLKmode + && can_reverse_comparison_p (temp3, insn)) + { + rtx temp6, target = 0, seq, init_insn = 0, init = temp2; + enum rtx_code code = reverse_condition (GET_CODE (temp3)); + + start_sequence (); + + /* It must be the case that TEMP2 is not modified in the range + [TEMP4, INSN). The one exception we make is if the insn + before INSN sets TEMP2 to something which is also unchanged + in that range. In that case, we can move the initialization + into our sequence. */ + + if ((temp5 = prev_active_insn (insn)) != 0 + && GET_CODE (temp5) == INSN + && (temp6 = single_set (temp5)) != 0 + && rtx_equal_p (temp2, SET_DEST (temp6)) + && (CONSTANT_P (SET_SRC (temp6)) + || GET_CODE (SET_SRC (temp6)) == REG + || GET_CODE (SET_SRC (temp6)) == SUBREG)) + { + emit_insn (PATTERN (temp5)); + init_insn = temp5; + init = SET_SRC (temp6); + } + + if (CONSTANT_P (init) + || ! reg_set_between_p (init, PREV_INSN (temp4), insn)) + target = emit_store_flag (gen_reg_rtx (GET_MODE (temp2)), code, + XEXP (temp3, 0), XEXP (temp3, 1), + VOIDmode, + (code == LTU || code == LEU + || code == GTU || code == GEU), 1); + + /* If we can do the store-flag, do the addition or + subtraction. */ + + if (target) + target = expand_binop (GET_MODE (temp2), + (XEXP (SET_SRC (temp1), 1) == const1_rtx + ? add_optab : sub_optab), + temp2, target, temp2, 0, OPTAB_WIDEN); + + if (target != 0) + { + /* Put the result back in temp2 in case it isn't already. + Then replace the jump, possible a CC0-setting insn in + front of the jump, and TEMP, with the sequence we have + made. */ + + if (target != temp2) + emit_move_insn (temp2, target); + + seq = get_insns (); + end_sequence (); + + emit_insns_before (seq, temp4); + delete_insn (temp); + + if (init_insn) + delete_insn (init_insn); + + next = NEXT_INSN (insn); +#ifdef HAVE_cc0 + delete_insn (prev_nonnote_insn (insn)); +#endif + delete_insn (insn); + changed = 1; + continue; + } + else + end_sequence (); + } + + /* Simplify if (...) x = 1; else {...} if (x) ... + We recognize this case scanning backwards as well. + + TEMP is the assignment to x; + TEMP1 is the label at the head of the second if. */ + /* ?? This should call get_condition to find the values being + compared, instead of looking for a COMPARE insn when HAVE_cc0 + is not defined. This would allow it to work on the m88k. */ + /* ?? This optimization is only safe before cse is run if HAVE_cc0 + is not defined and the condition is tested by a separate compare + insn. This is because the code below assumes that the result + of the compare dies in the following branch. + + Not only that, but there might be other insns between the + compare and branch whose results are live. Those insns need + to be executed. + + A way to fix this is to move the insns at JUMP_LABEL (insn) + to before INSN. If we are running before flow, they will + be deleted if they aren't needed. But this doesn't work + well after flow. + + This is really a special-case of jump threading, anyway. The + right thing to do is to replace this and jump threading with + much simpler code in cse. + + This code has been turned off in the non-cc0 case in the + meantime. */ + +#ifdef HAVE_cc0 + else if (this_is_simplejump + /* Safe to skip USE and CLOBBER insns here + since they will not be deleted. */ + && (temp = prev_active_insn (insn)) + && no_labels_between_p (temp, insn) + && GET_CODE (temp) == INSN + && GET_CODE (PATTERN (temp)) == SET + && GET_CODE (SET_DEST (PATTERN (temp))) == REG + && CONSTANT_P (SET_SRC (PATTERN (temp))) + && (temp1 = next_active_insn (JUMP_LABEL (insn))) + /* If we find that the next value tested is `x' + (TEMP1 is the insn where this happens), win. */ + && GET_CODE (temp1) == INSN + && GET_CODE (PATTERN (temp1)) == SET +#ifdef HAVE_cc0 + /* Does temp1 `tst' the value of x? */ + && SET_SRC (PATTERN (temp1)) == SET_DEST (PATTERN (temp)) + && SET_DEST (PATTERN (temp1)) == cc0_rtx + && (temp1 = next_nonnote_insn (temp1)) +#else + /* Does temp1 compare the value of x against zero? */ + && GET_CODE (SET_SRC (PATTERN (temp1))) == COMPARE + && XEXP (SET_SRC (PATTERN (temp1)), 1) == const0_rtx + && (XEXP (SET_SRC (PATTERN (temp1)), 0) + == SET_DEST (PATTERN (temp))) + && GET_CODE (SET_DEST (PATTERN (temp1))) == REG + && (temp1 = find_next_ref (SET_DEST (PATTERN (temp1)), temp1)) +#endif + && condjump_p (temp1)) + { + /* Get the if_then_else from the condjump. */ + rtx choice = SET_SRC (PATTERN (temp1)); + if (GET_CODE (choice) == IF_THEN_ELSE) + { + enum rtx_code code = GET_CODE (XEXP (choice, 0)); + rtx val = SET_SRC (PATTERN (temp)); + rtx cond + = simplify_relational_operation (code, GET_MODE (SET_DEST (PATTERN (temp))), + val, const0_rtx); + rtx ultimate; + + if (cond == const_true_rtx) + ultimate = XEXP (choice, 1); + else if (cond == const0_rtx) + ultimate = XEXP (choice, 2); + else + ultimate = 0; + + if (ultimate == pc_rtx) + ultimate = get_label_after (temp1); + else if (ultimate && GET_CODE (ultimate) != RETURN) + ultimate = XEXP (ultimate, 0); + + if (ultimate) + changed |= redirect_jump (insn, ultimate); + } + } +#endif + +#if 0 + /* @@ This needs a bit of work before it will be right. + + Any type of comparison can be accepted for the first and + second compare. When rewriting the first jump, we must + compute the what conditions can reach label3, and use the + appropriate code. We can not simply reverse/swap the code + of the first jump. In some cases, the second jump must be + rewritten also. + + For example, + < == converts to > == + < != converts to == > + etc. + + If the code is written to only accept an '==' test for the second + compare, then all that needs to be done is to swap the condition + of the first branch. + + It is questionable whether we want this optimization anyways, + since if the user wrote code like this because he/she knew that + the jump to label1 is taken most of the time, then rewriting + this gives slower code. */ + /* @@ This should call get_condition to find the values being + compared, instead of looking for a COMPARE insn when HAVE_cc0 + is not defined. This would allow it to work on the m88k. */ + /* @@ This optimization is only safe before cse is run if HAVE_cc0 + is not defined and the condition is tested by a separate compare + insn. This is because the code below assumes that the result + of the compare dies in the following branch. */ + + /* Simplify test a ~= b + condjump label1; + test a == b + condjump label2; + jump label3; + label1: + + rewriting as + test a ~~= b + condjump label3 + test a == b + condjump label2 + label1: + + where ~= is an inequality, e.g. >, and ~~= is the swapped + inequality, e.g. <. + + We recognize this case scanning backwards. + + TEMP is the conditional jump to `label2'; + TEMP1 is the test for `a == b'; + TEMP2 is the conditional jump to `label1'; + TEMP3 is the test for `a ~= b'. */ + else if (this_is_simplejump + && (temp = prev_active_insn (insn)) + && no_labels_between_p (temp, insn) + && condjump_p (temp) + && (temp1 = prev_active_insn (temp)) + && no_labels_between_p (temp1, temp) + && GET_CODE (temp1) == INSN + && GET_CODE (PATTERN (temp1)) == SET +#ifdef HAVE_cc0 + && sets_cc0_p (PATTERN (temp1)) == 1 +#else + && GET_CODE (SET_SRC (PATTERN (temp1))) == COMPARE + && GET_CODE (SET_DEST (PATTERN (temp1))) == REG + && (temp == find_next_ref (SET_DEST (PATTERN (temp1)), temp1)) +#endif + && (temp2 = prev_active_insn (temp1)) + && no_labels_between_p (temp2, temp1) + && condjump_p (temp2) + && JUMP_LABEL (temp2) == next_nonnote_insn (NEXT_INSN (insn)) + && (temp3 = prev_active_insn (temp2)) + && no_labels_between_p (temp3, temp2) + && GET_CODE (PATTERN (temp3)) == SET + && rtx_equal_p (SET_DEST (PATTERN (temp3)), + SET_DEST (PATTERN (temp1))) + && rtx_equal_p (SET_SRC (PATTERN (temp1)), + SET_SRC (PATTERN (temp3))) + && ! inequality_comparisons_p (PATTERN (temp)) + && inequality_comparisons_p (PATTERN (temp2))) + { + rtx fallthrough_label = JUMP_LABEL (temp2); + + ++LABEL_NUSES (fallthrough_label); + if (swap_jump (temp2, JUMP_LABEL (insn))) + { + delete_insn (insn); + changed = 1; + } + + if (--LABEL_NUSES (fallthrough_label) == 0) + delete_insn (fallthrough_label); + } +#endif + /* Simplify if (...) {... x = 1;} if (x) ... + + We recognize this case backwards. + + TEMP is the test of `x'; + TEMP1 is the assignment to `x' at the end of the + previous statement. */ + /* @@ This should call get_condition to find the values being + compared, instead of looking for a COMPARE insn when HAVE_cc0 + is not defined. This would allow it to work on the m88k. */ + /* @@ This optimization is only safe before cse is run if HAVE_cc0 + is not defined and the condition is tested by a separate compare + insn. This is because the code below assumes that the result + of the compare dies in the following branch. */ + + /* ??? This has to be turned off. The problem is that the + unconditional jump might indirectly end up branching to the + label between TEMP1 and TEMP. We can't detect this, in general, + since it may become a jump to there after further optimizations. + If that jump is done, it will be deleted, so we will retry + this optimization in the next pass, thus an infinite loop. + + The present code prevents this by putting the jump after the + label, but this is not logically correct. */ +#if 0 + else if (this_is_condjump + /* Safe to skip USE and CLOBBER insns here + since they will not be deleted. */ + && (temp = prev_active_insn (insn)) + && no_labels_between_p (temp, insn) + && GET_CODE (temp) == INSN + && GET_CODE (PATTERN (temp)) == SET +#ifdef HAVE_cc0 + && sets_cc0_p (PATTERN (temp)) == 1 + && GET_CODE (SET_SRC (PATTERN (temp))) == REG +#else + /* Temp must be a compare insn, we can not accept a register + to register move here, since it may not be simply a + tst insn. */ + && GET_CODE (SET_SRC (PATTERN (temp))) == COMPARE + && XEXP (SET_SRC (PATTERN (temp)), 1) == const0_rtx + && GET_CODE (XEXP (SET_SRC (PATTERN (temp)), 0)) == REG + && GET_CODE (SET_DEST (PATTERN (temp))) == REG + && insn == find_next_ref (SET_DEST (PATTERN (temp)), temp) +#endif + /* May skip USE or CLOBBER insns here + for checking for opportunity, since we + take care of them later. */ + && (temp1 = prev_active_insn (temp)) + && GET_CODE (temp1) == INSN + && GET_CODE (PATTERN (temp1)) == SET +#ifdef HAVE_cc0 + && SET_SRC (PATTERN (temp)) == SET_DEST (PATTERN (temp1)) +#else + && (XEXP (SET_SRC (PATTERN (temp)), 0) + == SET_DEST (PATTERN (temp1))) +#endif + && CONSTANT_P (SET_SRC (PATTERN (temp1))) + /* If this isn't true, cse will do the job. */ + && ! no_labels_between_p (temp1, temp)) + { + /* Get the if_then_else from the condjump. */ + rtx choice = SET_SRC (PATTERN (insn)); + if (GET_CODE (choice) == IF_THEN_ELSE + && (GET_CODE (XEXP (choice, 0)) == EQ + || GET_CODE (XEXP (choice, 0)) == NE)) + { + int want_nonzero = (GET_CODE (XEXP (choice, 0)) == NE); + rtx last_insn; + rtx ultimate; + rtx p; + + /* Get the place that condjump will jump to + if it is reached from here. */ + if ((SET_SRC (PATTERN (temp1)) != const0_rtx) + == want_nonzero) + ultimate = XEXP (choice, 1); + else + ultimate = XEXP (choice, 2); + /* Get it as a CODE_LABEL. */ + if (ultimate == pc_rtx) + ultimate = get_label_after (insn); + else + /* Get the label out of the LABEL_REF. */ + ultimate = XEXP (ultimate, 0); + + /* Insert the jump immediately before TEMP, specifically + after the label that is between TEMP1 and TEMP. */ + last_insn = PREV_INSN (temp); + + /* If we would be branching to the next insn, the jump + would immediately be deleted and the re-inserted in + a subsequent pass over the code. So don't do anything + in that case. */ + if (next_active_insn (last_insn) + != next_active_insn (ultimate)) + { + emit_barrier_after (last_insn); + p = emit_jump_insn_after (gen_jump (ultimate), + last_insn); + JUMP_LABEL (p) = ultimate; + ++LABEL_NUSES (ultimate); + if (INSN_UID (ultimate) < max_jump_chain + && INSN_CODE (p) < max_jump_chain) + { + jump_chain[INSN_UID (p)] + = jump_chain[INSN_UID (ultimate)]; + jump_chain[INSN_UID (ultimate)] = p; + } + changed = 1; + continue; + } + } + } +#endif + /* Detect a conditional jump going to the same place + as an immediately following unconditional jump. */ + else if (this_is_condjump + && (temp = next_active_insn (insn)) != 0 + && simplejump_p (temp) + && (next_active_insn (JUMP_LABEL (insn)) + == next_active_insn (JUMP_LABEL (temp)))) + { + delete_jump (insn); + changed = 1; + continue; + } + /* Detect a conditional jump jumping over an unconditional jump. */ + + else if (this_is_condjump && ! this_is_simplejump + && reallabelprev != 0 + && GET_CODE (reallabelprev) == JUMP_INSN + && prev_active_insn (reallabelprev) == insn + && no_labels_between_p (insn, reallabelprev) + && simplejump_p (reallabelprev)) + { + /* When we invert the unconditional jump, we will be + decrementing the usage count of its old label. + Make sure that we don't delete it now because that + might cause the following code to be deleted. */ + rtx prev_uses = prev_nonnote_insn (reallabelprev); + rtx prev_label = JUMP_LABEL (insn); + + ++LABEL_NUSES (prev_label); + + if (invert_jump (insn, JUMP_LABEL (reallabelprev))) + { + /* It is very likely that if there are USE insns before + this jump, they hold REG_DEAD notes. These REG_DEAD + notes are no longer valid due to this optimization, + and will cause the life-analysis that following passes + (notably delayed-branch scheduling) to think that + these registers are dead when they are not. + + To prevent this trouble, we just remove the USE insns + from the insn chain. */ + + while (prev_uses && GET_CODE (prev_uses) == INSN + && GET_CODE (PATTERN (prev_uses)) == USE) + { + rtx useless = prev_uses; + prev_uses = prev_nonnote_insn (prev_uses); + delete_insn (useless); + } + + delete_insn (reallabelprev); + next = insn; + changed = 1; + } + + /* We can now safely delete the label if it is unreferenced + since the delete_insn above has deleted the BARRIER. */ + if (--LABEL_NUSES (prev_label) == 0) + delete_insn (prev_label); + continue; + } + else + { + /* Detect a jump to a jump. */ + + nlabel = follow_jumps (JUMP_LABEL (insn)); + if (nlabel != JUMP_LABEL (insn) + && redirect_jump (insn, nlabel)) + { + changed = 1; + next = insn; + } + + /* Look for if (foo) bar; else break; */ + /* The insns look like this: + insn = condjump label1; + ...range1 (some insns)... + jump label2; + label1: + ...range2 (some insns)... + jump somewhere unconditionally + label2: */ + { + rtx label1 = next_label (insn); + rtx range1end = label1 ? prev_active_insn (label1) : 0; + /* Don't do this optimization on the first round, so that + jump-around-a-jump gets simplified before we ask here + whether a jump is unconditional. + + Also don't do it when we are called after reload since + it will confuse reorg. */ + if (! first + && (reload_completed ? ! flag_delayed_branch : 1) + /* Make sure INSN is something we can invert. */ + && condjump_p (insn) + && label1 != 0 + && JUMP_LABEL (insn) == label1 + && LABEL_NUSES (label1) == 1 + && GET_CODE (range1end) == JUMP_INSN + && simplejump_p (range1end)) + { + rtx label2 = next_label (label1); + rtx range2end = label2 ? prev_active_insn (label2) : 0; + if (range1end != range2end + && JUMP_LABEL (range1end) == label2 + && GET_CODE (range2end) == JUMP_INSN + && GET_CODE (NEXT_INSN (range2end)) == BARRIER + /* Invert the jump condition, so we + still execute the same insns in each case. */ + && invert_jump (insn, label1)) + { + rtx range1beg = next_active_insn (insn); + rtx range2beg = next_active_insn (label1); + rtx range1after, range2after; + rtx range1before, range2before; + + /* Include in each range any line number before it. */ + while (PREV_INSN (range1beg) + && GET_CODE (PREV_INSN (range1beg)) == NOTE + && NOTE_LINE_NUMBER (PREV_INSN (range1beg)) > 0) + range1beg = PREV_INSN (range1beg); + + while (PREV_INSN (range2beg) + && GET_CODE (PREV_INSN (range2beg)) == NOTE + && NOTE_LINE_NUMBER (PREV_INSN (range2beg)) > 0) + range2beg = PREV_INSN (range2beg); + + /* Don't move NOTEs for blocks or loops; shift them + outside the ranges, where they'll stay put. */ + range1beg = squeeze_notes (range1beg, range1end); + range2beg = squeeze_notes (range2beg, range2end); + + /* Get current surrounds of the 2 ranges. */ + range1before = PREV_INSN (range1beg); + range2before = PREV_INSN (range2beg); + range1after = NEXT_INSN (range1end); + range2after = NEXT_INSN (range2end); + + /* Splice range2 where range1 was. */ + NEXT_INSN (range1before) = range2beg; + PREV_INSN (range2beg) = range1before; + NEXT_INSN (range2end) = range1after; + PREV_INSN (range1after) = range2end; + /* Splice range1 where range2 was. */ + NEXT_INSN (range2before) = range1beg; + PREV_INSN (range1beg) = range2before; + NEXT_INSN (range1end) = range2after; + PREV_INSN (range2after) = range1end; + changed = 1; + continue; + } + } + } + + /* Now that the jump has been tensioned, + try cross jumping: check for identical code + before the jump and before its target label. */ + + /* First, cross jumping of conditional jumps: */ + + if (cross_jump && condjump_p (insn)) + { + rtx newjpos, newlpos; + rtx x = prev_real_insn (JUMP_LABEL (insn)); + + /* A conditional jump may be crossjumped + only if the place it jumps to follows + an opposing jump that comes back here. */ + + if (x != 0 && ! jump_back_p (x, insn)) + /* We have no opposing jump; + cannot cross jump this insn. */ + x = 0; + + newjpos = 0; + /* TARGET is nonzero if it is ok to cross jump + to code before TARGET. If so, see if matches. */ + if (x != 0) + find_cross_jump (insn, x, 2, + &newjpos, &newlpos); + + if (newjpos != 0) + { + do_cross_jump (insn, newjpos, newlpos); + /* Make the old conditional jump + into an unconditional one. */ + SET_SRC (PATTERN (insn)) + = gen_rtx (LABEL_REF, VOIDmode, JUMP_LABEL (insn)); + INSN_CODE (insn) = -1; + emit_barrier_after (insn); + /* Add to jump_chain unless this is a new label + whose UID is too large. */ + if (INSN_UID (JUMP_LABEL (insn)) < max_jump_chain) + { + jump_chain[INSN_UID (insn)] + = jump_chain[INSN_UID (JUMP_LABEL (insn))]; + jump_chain[INSN_UID (JUMP_LABEL (insn))] = insn; + } + changed = 1; + next = insn; + } + } + + /* Cross jumping of unconditional jumps: + a few differences. */ + + if (cross_jump && simplejump_p (insn)) + { + rtx newjpos, newlpos; + rtx target; + + newjpos = 0; + + /* TARGET is nonzero if it is ok to cross jump + to code before TARGET. If so, see if matches. */ + find_cross_jump (insn, JUMP_LABEL (insn), 1, + &newjpos, &newlpos); + + /* If cannot cross jump to code before the label, + see if we can cross jump to another jump to + the same label. */ + /* Try each other jump to this label. */ + if (INSN_UID (JUMP_LABEL (insn)) < max_uid) + for (target = jump_chain[INSN_UID (JUMP_LABEL (insn))]; + target != 0 && newjpos == 0; + target = jump_chain[INSN_UID (target)]) + if (target != insn + && JUMP_LABEL (target) == JUMP_LABEL (insn) + /* Ignore TARGET if it's deleted. */ + && ! INSN_DELETED_P (target)) + find_cross_jump (insn, target, 2, + &newjpos, &newlpos); + + if (newjpos != 0) + { + do_cross_jump (insn, newjpos, newlpos); + changed = 1; + next = insn; + } + } + + /* This code was dead in the previous jump.c! */ + if (cross_jump && GET_CODE (PATTERN (insn)) == RETURN) + { + /* Return insns all "jump to the same place" + so we can cross-jump between any two of them. */ + + rtx newjpos, newlpos, target; + + newjpos = 0; + + /* If cannot cross jump to code before the label, + see if we can cross jump to another jump to + the same label. */ + /* Try each other jump to this label. */ + for (target = jump_chain[0]; + target != 0 && newjpos == 0; + target = jump_chain[INSN_UID (target)]) + if (target != insn + && ! INSN_DELETED_P (target) + && GET_CODE (PATTERN (target)) == RETURN) + find_cross_jump (insn, target, 2, + &newjpos, &newlpos); + + if (newjpos != 0) + { + do_cross_jump (insn, newjpos, newlpos); + changed = 1; + next = insn; + } + } + } + } + + first = 0; + } + + /* Delete extraneous line number notes. + Note that two consecutive notes for different lines are not really + extraneous. There should be some indication where that line belonged, + even if it became empty. */ + + { + rtx last_note = 0; + + for (insn = f; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) >= 0) + { + /* Delete this note if it is identical to previous note. */ + if (last_note + && NOTE_SOURCE_FILE (insn) == NOTE_SOURCE_FILE (last_note) + && NOTE_LINE_NUMBER (insn) == NOTE_LINE_NUMBER (last_note)) + { + delete_insn (insn); + continue; + } + + last_note = insn; + } + } + + /* See if there is still a NOTE_INSN_FUNCTION_END in this function. + If so, delete it, and record that this function can drop off the end. */ + + insn = last_insn; + { + int n_labels = 1; + while (insn + /* One label can follow the end-note: the return label. */ + && ((GET_CODE (insn) == CODE_LABEL && n_labels-- > 0) + /* Ordinary insns can follow it if returning a structure. */ + || GET_CODE (insn) == INSN + /* If machine uses explicit RETURN insns, no epilogue, + then one of them follows the note. */ + || (GET_CODE (insn) == JUMP_INSN + && GET_CODE (PATTERN (insn)) == RETURN) + /* Other kinds of notes can follow also. */ + || (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) != NOTE_INSN_FUNCTION_END))) + insn = PREV_INSN (insn); + } + + /* Report if control can fall through at the end of the function. */ + if (insn && GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_FUNCTION_END) + { + can_reach_end = 1; + delete_insn (insn); + } + + /* Show JUMP_CHAIN no longer valid. */ + jump_chain = 0; +} + +/* LOOP_START is a NOTE_INSN_LOOP_BEG note that is followed by an unconditional + jump. Assume that this unconditional jump is to the exit test code. If + the code is sufficiently simple, make a copy of it before INSN, + followed by a jump to the exit of the loop. Then delete the unconditional + jump after INSN. + + Note that it is possible we can get confused here if the jump immediately + after the loop start branches outside the loop but within an outer loop. + If we are near the exit of that loop, we will copy its exit test. This + will not generate incorrect code, but could suppress some optimizations. + However, such cases are degenerate loops anyway. + + Return 1 if we made the change, else 0. + + This is only safe immediately after a regscan pass because it uses the + values of regno_first_uid and regno_last_uid. */ + +static int +duplicate_loop_exit_test (loop_start) + rtx loop_start; +{ + rtx insn, set, p; + rtx copy, link; + int num_insns = 0; + rtx exitcode = NEXT_INSN (JUMP_LABEL (next_nonnote_insn (loop_start))); + rtx lastexit; + int max_reg = max_reg_num (); + rtx *reg_map = 0; + + /* Scan the exit code. We do not perform this optimization if any insn: + + is a CALL_INSN + is a CODE_LABEL + has a REG_RETVAL or REG_LIBCALL note (hard to adjust) + is a NOTE_INSN_LOOP_BEG because this means we have a nested loop + is a NOTE_INSN_BLOCK_{BEG,END} because duplicating these notes + are not valid + + Also, don't do this if the exit code is more than 20 insns. */ + + for (insn = exitcode; + insn + && ! (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END); + insn = NEXT_INSN (insn)) + { + switch (GET_CODE (insn)) + { + case CODE_LABEL: + case CALL_INSN: + return 0; + case NOTE: + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG + || NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG + || NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) + return 0; + break; + case JUMP_INSN: + case INSN: + if (++num_insns > 20 + || find_reg_note (insn, REG_RETVAL, NULL_RTX) + || find_reg_note (insn, REG_LIBCALL, NULL_RTX)) + return 0; + break; + } + } + + /* Unless INSN is zero, we can do the optimization. */ + if (insn == 0) + return 0; + + lastexit = insn; + + /* See if any insn sets a register only used in the loop exit code and + not a user variable. If so, replace it with a new register. */ + for (insn = exitcode; insn != lastexit; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == INSN + && (set = single_set (insn)) != 0 + && GET_CODE (SET_DEST (set)) == REG + && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER + && regno_first_uid[REGNO (SET_DEST (set))] == INSN_UID (insn)) + { + for (p = NEXT_INSN (insn); p != lastexit; p = NEXT_INSN (p)) + if (regno_last_uid[REGNO (SET_DEST (set))] == INSN_UID (p)) + break; + + if (p != lastexit) + { + /* We can do the replacement. Allocate reg_map if this is the + first replacement we found. */ + if (reg_map == 0) + { + reg_map = (rtx *) alloca (max_reg * sizeof (rtx)); + bzero (reg_map, max_reg * sizeof (rtx)); + } + + REG_LOOP_TEST_P (SET_DEST (set)) = 1; + + reg_map[REGNO (SET_DEST (set))] + = gen_reg_rtx (GET_MODE (SET_DEST (set))); + } + } + + /* Now copy each insn. */ + for (insn = exitcode; insn != lastexit; insn = NEXT_INSN (insn)) + switch (GET_CODE (insn)) + { + case BARRIER: + copy = emit_barrier_before (loop_start); + break; + case NOTE: + /* Only copy line-number notes. */ + if (NOTE_LINE_NUMBER (insn) >= 0) + { + copy = emit_note_before (NOTE_LINE_NUMBER (insn), loop_start); + NOTE_SOURCE_FILE (copy) = NOTE_SOURCE_FILE (insn); + } + break; + + case INSN: + copy = emit_insn_before (copy_rtx (PATTERN (insn)), loop_start); + if (reg_map) + replace_regs (PATTERN (copy), reg_map, max_reg, 1); + + mark_jump_label (PATTERN (copy), copy, 0); + + /* Copy all REG_NOTES except REG_LABEL since mark_jump_label will + make them. */ + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) != REG_LABEL) + REG_NOTES (copy) + = copy_rtx (gen_rtx (EXPR_LIST, REG_NOTE_KIND (link), + XEXP (link, 0), REG_NOTES (copy))); + if (reg_map && REG_NOTES (copy)) + replace_regs (REG_NOTES (copy), reg_map, max_reg, 1); + break; + + case JUMP_INSN: + copy = emit_jump_insn_before (copy_rtx (PATTERN (insn)), loop_start); + if (reg_map) + replace_regs (PATTERN (copy), reg_map, max_reg, 1); + mark_jump_label (PATTERN (copy), copy, 0); + if (REG_NOTES (insn)) + { + REG_NOTES (copy) = copy_rtx (REG_NOTES (insn)); + if (reg_map) + replace_regs (REG_NOTES (copy), reg_map, max_reg, 1); + } + + /* If this is a simple jump, add it to the jump chain. */ + + if (INSN_UID (copy) < max_jump_chain && JUMP_LABEL (copy) + && simplejump_p (copy)) + { + jump_chain[INSN_UID (copy)] + = jump_chain[INSN_UID (JUMP_LABEL (copy))]; + jump_chain[INSN_UID (JUMP_LABEL (copy))] = copy; + } + break; + + default: + abort (); + } + + /* Now clean up by emitting a jump to the end label and deleting the jump + at the start of the loop. */ + if (GET_CODE (copy) != BARRIER) + { + copy = emit_jump_insn_before (gen_jump (get_label_after (insn)), + loop_start); + mark_jump_label (PATTERN (copy), copy, 0); + if (INSN_UID (copy) < max_jump_chain + && INSN_UID (JUMP_LABEL (copy)) < max_jump_chain) + { + jump_chain[INSN_UID (copy)] + = jump_chain[INSN_UID (JUMP_LABEL (copy))]; + jump_chain[INSN_UID (JUMP_LABEL (copy))] = copy; + } + emit_barrier_before (loop_start); + } + + delete_insn (next_nonnote_insn (loop_start)); + + /* Mark the exit code as the virtual top of the converted loop. */ + emit_note_before (NOTE_INSN_LOOP_VTOP, exitcode); + + return 1; +} + +/* Move all block-beg, block-end, loop-beg, loop-cont, loop-vtop, and + loop-end notes between START and END out before START. Assume that + END is not such a note. START may be such a note. Returns the value + of the new starting insn, which may be different if the original start + was such a note. */ + +rtx +squeeze_notes (start, end) + rtx start, end; +{ + rtx insn; + rtx next; + + for (insn = start; insn != end; insn = next) + { + next = NEXT_INSN (insn); + if (GET_CODE (insn) == NOTE + && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END + || NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG + || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG + || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END + || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_CONT + || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_VTOP)) + { + if (insn == start) + start = next; + else + { + rtx prev = PREV_INSN (insn); + PREV_INSN (insn) = PREV_INSN (start); + NEXT_INSN (insn) = start; + NEXT_INSN (PREV_INSN (insn)) = insn; + PREV_INSN (NEXT_INSN (insn)) = insn; + NEXT_INSN (prev) = next; + PREV_INSN (next) = prev; + } + } + } + + return start; +} + +/* Compare the instructions before insn E1 with those before E2 + to find an opportunity for cross jumping. + (This means detecting identical sequences of insns followed by + jumps to the same place, or followed by a label and a jump + to that label, and replacing one with a jump to the other.) + + Assume E1 is a jump that jumps to label E2 + (that is not always true but it might as well be). + Find the longest possible equivalent sequences + and store the first insns of those sequences into *F1 and *F2. + Store zero there if no equivalent preceding instructions are found. + + We give up if we find a label in stream 1. + Actually we could transfer that label into stream 2. */ + +static void +find_cross_jump (e1, e2, minimum, f1, f2) + rtx e1, e2; + int minimum; + rtx *f1, *f2; +{ + register rtx i1 = e1, i2 = e2; + register rtx p1, p2; + int lose = 0; + + rtx last1 = 0, last2 = 0; + rtx afterlast1 = 0, afterlast2 = 0; + rtx prev1; + + *f1 = 0; + *f2 = 0; + + while (1) + { + i1 = prev_nonnote_insn (i1); + + i2 = PREV_INSN (i2); + while (i2 && (GET_CODE (i2) == NOTE || GET_CODE (i2) == CODE_LABEL)) + i2 = PREV_INSN (i2); + + if (i1 == 0) + break; + + /* Don't allow the range of insns preceding E1 or E2 + to include the other (E2 or E1). */ + if (i2 == e1 || i1 == e2) + break; + + /* If we will get to this code by jumping, those jumps will be + tensioned to go directly to the new label (before I2), + so this cross-jumping won't cost extra. So reduce the minimum. */ + if (GET_CODE (i1) == CODE_LABEL) + { + --minimum; + break; + } + + if (i2 == 0 || GET_CODE (i1) != GET_CODE (i2)) + break; + + p1 = PATTERN (i1); + p2 = PATTERN (i2); + +#ifdef STACK_REGS + /* If cross_jump_death_matters is not 0, the insn's mode + indicates whether or not the insn contains any stack-like + regs. */ + + if (cross_jump_death_matters && GET_MODE (i1) == QImode) + { + /* If register stack conversion has already been done, then + death notes must also be compared before it is certain that + the two instruction streams match. */ + + rtx note; + HARD_REG_SET i1_regset, i2_regset; + + CLEAR_HARD_REG_SET (i1_regset); + CLEAR_HARD_REG_SET (i2_regset); + + for (note = REG_NOTES (i1); note; note = XEXP (note, 1)) + if (REG_NOTE_KIND (note) == REG_DEAD + && STACK_REG_P (XEXP (note, 0))) + SET_HARD_REG_BIT (i1_regset, REGNO (XEXP (note, 0))); + + for (note = REG_NOTES (i2); note; note = XEXP (note, 1)) + if (REG_NOTE_KIND (note) == REG_DEAD + && STACK_REG_P (XEXP (note, 0))) + SET_HARD_REG_BIT (i2_regset, REGNO (XEXP (note, 0))); + + GO_IF_HARD_REG_EQUAL (i1_regset, i2_regset, done); + + lose = 1; + + done: + ; + } +#endif + + if (lose || GET_CODE (p1) != GET_CODE (p2) + || ! rtx_renumbered_equal_p (p1, p2)) + { + /* The following code helps take care of G++ cleanups. */ + rtx equiv1; + rtx equiv2; + + if (!lose && GET_CODE (p1) == GET_CODE (p2) + && ((equiv1 = find_reg_note (i1, REG_EQUAL, NULL_RTX)) != 0 + || (equiv1 = find_reg_note (i1, REG_EQUIV, NULL_RTX)) != 0) + && ((equiv2 = find_reg_note (i2, REG_EQUAL, NULL_RTX)) != 0 + || (equiv2 = find_reg_note (i2, REG_EQUIV, NULL_RTX)) != 0) + /* If the equivalences are not to a constant, they may + reference pseudos that no longer exist, so we can't + use them. */ + && CONSTANT_P (XEXP (equiv1, 0)) + && rtx_equal_p (XEXP (equiv1, 0), XEXP (equiv2, 0))) + { + rtx s1 = single_set (i1); + rtx s2 = single_set (i2); + if (s1 != 0 && s2 != 0 + && rtx_renumbered_equal_p (SET_DEST (s1), SET_DEST (s2))) + { + validate_change (i1, &SET_SRC (s1), XEXP (equiv1, 0), 1); + validate_change (i2, &SET_SRC (s2), XEXP (equiv2, 0), 1); + if (! rtx_renumbered_equal_p (p1, p2)) + cancel_changes (0); + else if (apply_change_group ()) + goto win; + } + } + + /* Insns fail to match; cross jumping is limited to the following + insns. */ + +#ifdef HAVE_cc0 + /* Don't allow the insn after a compare to be shared by + cross-jumping unless the compare is also shared. + Here, if either of these non-matching insns is a compare, + exclude the following insn from possible cross-jumping. */ + if (sets_cc0_p (p1) || sets_cc0_p (p2)) + last1 = afterlast1, last2 = afterlast2, ++minimum; +#endif + + /* If cross-jumping here will feed a jump-around-jump + optimization, this jump won't cost extra, so reduce + the minimum. */ + if (GET_CODE (i1) == JUMP_INSN + && JUMP_LABEL (i1) + && prev_real_insn (JUMP_LABEL (i1)) == e1) + --minimum; + break; + } + + win: + if (GET_CODE (p1) != USE && GET_CODE (p1) != CLOBBER) + { + /* Ok, this insn is potentially includable in a cross-jump here. */ + afterlast1 = last1, afterlast2 = last2; + last1 = i1, last2 = i2, --minimum; + } + } + + /* We have to be careful that we do not cross-jump into the middle of + USE-CALL_INSN-CLOBBER sequence. This sequence is used instead of + putting the USE and CLOBBERs inside the CALL_INSN. The delay slot + scheduler needs to know what registers are used and modified by the + CALL_INSN and needs the adjacent USE and CLOBBERs to do so. + + ??? At some point we should probably change this so that these are + part of the CALL_INSN. The way we are doing it now is a kludge that + is now causing trouble. */ + + if (last1 != 0 && GET_CODE (last1) == CALL_INSN + && (prev1 = prev_nonnote_insn (last1)) + && GET_CODE (prev1) == INSN + && GET_CODE (PATTERN (prev1)) == USE) + { + /* Remove this CALL_INSN from the range we can cross-jump. */ + last1 = next_real_insn (last1); + last2 = next_real_insn (last2); + + minimum++; + } + + /* Skip past CLOBBERS since they may be right after a CALL_INSN. It + isn't worth checking for the CALL_INSN. */ + while (last1 != 0 && GET_CODE (PATTERN (last1)) == CLOBBER) + last1 = next_real_insn (last1), last2 = next_real_insn (last2); + + if (minimum <= 0 && last1 != 0 && last1 != e1) + *f1 = last1, *f2 = last2; +} + +static void +do_cross_jump (insn, newjpos, newlpos) + rtx insn, newjpos, newlpos; +{ + /* Find an existing label at this point + or make a new one if there is none. */ + register rtx label = get_label_before (newlpos); + + /* Make the same jump insn jump to the new point. */ + if (GET_CODE (PATTERN (insn)) == RETURN) + { + /* Remove from jump chain of returns. */ + delete_from_jump_chain (insn); + /* Change the insn. */ + PATTERN (insn) = gen_jump (label); + INSN_CODE (insn) = -1; + JUMP_LABEL (insn) = label; + LABEL_NUSES (label)++; + /* Add to new the jump chain. */ + if (INSN_UID (label) < max_jump_chain + && INSN_UID (insn) < max_jump_chain) + { + jump_chain[INSN_UID (insn)] = jump_chain[INSN_UID (label)]; + jump_chain[INSN_UID (label)] = insn; + } + } + else + redirect_jump (insn, label); + + /* Delete the matching insns before the jump. Also, remove any REG_EQUAL + or REG_EQUIV note in the NEWLPOS stream that isn't also present in + the NEWJPOS stream. */ + + while (newjpos != insn) + { + rtx lnote; + + for (lnote = REG_NOTES (newlpos); lnote; lnote = XEXP (lnote, 1)) + if ((REG_NOTE_KIND (lnote) == REG_EQUAL + || REG_NOTE_KIND (lnote) == REG_EQUIV) + && ! find_reg_note (newjpos, REG_EQUAL, XEXP (lnote, 0)) + && ! find_reg_note (newjpos, REG_EQUIV, XEXP (lnote, 0))) + remove_note (newlpos, lnote); + + delete_insn (newjpos); + newjpos = next_real_insn (newjpos); + newlpos = next_real_insn (newlpos); + } +} + +/* Return the label before INSN, or put a new label there. */ + +rtx +get_label_before (insn) + rtx insn; +{ + rtx label; + + /* Find an existing label at this point + or make a new one if there is none. */ + label = prev_nonnote_insn (insn); + + if (label == 0 || GET_CODE (label) != CODE_LABEL) + { + rtx prev = PREV_INSN (insn); + + /* Don't put a label between a CALL_INSN and USE insns that precede + it. */ + + if (GET_CODE (insn) == CALL_INSN + || (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE + && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN)) + while (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == USE) + prev = PREV_INSN (prev); + + label = gen_label_rtx (); + emit_label_after (label, prev); + LABEL_NUSES (label) = 0; + } + return label; +} + +/* Return the label after INSN, or put a new label there. */ + +rtx +get_label_after (insn) + rtx insn; +{ + rtx label; + + /* Find an existing label at this point + or make a new one if there is none. */ + label = next_nonnote_insn (insn); + + if (label == 0 || GET_CODE (label) != CODE_LABEL) + { + /* Don't put a label between a CALL_INSN and CLOBBER insns + following it. */ + + if (GET_CODE (insn) == CALL_INSN + || (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE + && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN)) + while (GET_CODE (NEXT_INSN (insn)) == INSN + && GET_CODE (PATTERN (NEXT_INSN (insn))) == CLOBBER) + insn = NEXT_INSN (insn); + + label = gen_label_rtx (); + emit_label_after (label, insn); + LABEL_NUSES (label) = 0; + } + return label; +} + +/* Return 1 if INSN is a jump that jumps to right after TARGET + only on the condition that TARGET itself would drop through. + Assumes that TARGET is a conditional jump. */ + +static int +jump_back_p (insn, target) + rtx insn, target; +{ + rtx cinsn, ctarget; + enum rtx_code codei, codet; + + if (simplejump_p (insn) || ! condjump_p (insn) + || simplejump_p (target) + || target != prev_real_insn (JUMP_LABEL (insn))) + return 0; + + cinsn = XEXP (SET_SRC (PATTERN (insn)), 0); + ctarget = XEXP (SET_SRC (PATTERN (target)), 0); + + codei = GET_CODE (cinsn); + codet = GET_CODE (ctarget); + + if (XEXP (SET_SRC (PATTERN (insn)), 1) == pc_rtx) + { + if (! can_reverse_comparison_p (cinsn, insn)) + return 0; + codei = reverse_condition (codei); + } + + if (XEXP (SET_SRC (PATTERN (target)), 2) == pc_rtx) + { + if (! can_reverse_comparison_p (ctarget, target)) + return 0; + codet = reverse_condition (codet); + } + + return (codei == codet + && rtx_renumbered_equal_p (XEXP (cinsn, 0), XEXP (ctarget, 0)) + && rtx_renumbered_equal_p (XEXP (cinsn, 1), XEXP (ctarget, 1))); +} + +/* Given a comparison, COMPARISON, inside a conditional jump insn, INSN, + return non-zero if it is safe to reverse this comparison. It is if our + floating-point is not IEEE, if this is an NE or EQ comparison, or if + this is known to be an integer comparison. */ + +int +can_reverse_comparison_p (comparison, insn) + rtx comparison; + rtx insn; +{ + rtx arg0; + + /* If this is not actually a comparison, we can't reverse it. */ + if (GET_RTX_CLASS (GET_CODE (comparison)) != '<') + return 0; + + if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT + /* If this is an NE comparison, it is safe to reverse it to an EQ + comparison and vice versa, even for floating point. If no operands + are NaNs, the reversal is valid. If some operand is a NaN, EQ is + always false and NE is always true, so the reversal is also valid. */ + || GET_CODE (comparison) == NE + || GET_CODE (comparison) == EQ) + return 1; + + arg0 = XEXP (comparison, 0); + + /* Make sure ARG0 is one of the actual objects being compared. If we + can't do this, we can't be sure the comparison can be reversed. + + Handle cc0 and a MODE_CC register. */ + if ((GET_CODE (arg0) == REG && GET_MODE_CLASS (GET_MODE (arg0)) == MODE_CC) +#ifdef HAVE_cc0 + || arg0 == cc0_rtx +#endif + ) + { + rtx prev = prev_nonnote_insn (insn); + rtx set = single_set (prev); + + if (set == 0 || SET_DEST (set) != arg0) + return 0; + + arg0 = SET_SRC (set); + + if (GET_CODE (arg0) == COMPARE) + arg0 = XEXP (arg0, 0); + } + + /* We can reverse this if ARG0 is a CONST_INT or if its mode is + not VOIDmode and neither a MODE_CC nor MODE_FLOAT type. */ + return (GET_CODE (arg0) == CONST_INT + || (GET_MODE (arg0) != VOIDmode + && GET_MODE_CLASS (GET_MODE (arg0)) != MODE_CC + && GET_MODE_CLASS (GET_MODE (arg0)) != MODE_FLOAT)); +} + +/* Given an rtx-code for a comparison, return the code + for the negated comparison. + WATCH OUT! reverse_condition is not safe to use on a jump + that might be acting on the results of an IEEE floating point comparison, + because of the special treatment of non-signaling nans in comparisons. + Use can_reverse_comparison_p to be sure. */ + +enum rtx_code +reverse_condition (code) + enum rtx_code code; +{ + switch (code) + { + case EQ: + return NE; + + case NE: + return EQ; + + case GT: + return LE; + + case GE: + return LT; + + case LT: + return GE; + + case LE: + return GT; + + case GTU: + return LEU; + + case GEU: + return LTU; + + case LTU: + return GEU; + + case LEU: + return GTU; + + default: + abort (); + return UNKNOWN; + } +} + +/* Similar, but return the code when two operands of a comparison are swapped. + This IS safe for IEEE floating-point. */ + +enum rtx_code +swap_condition (code) + enum rtx_code code; +{ + switch (code) + { + case EQ: + case NE: + return code; + + case GT: + return LT; + + case GE: + return LE; + + case LT: + return GT; + + case LE: + return GE; + + case GTU: + return LTU; + + case GEU: + return LEU; + + case LTU: + return GTU; + + case LEU: + return GEU; + + default: + abort (); + return UNKNOWN; + } +} + +/* Given a comparison CODE, return the corresponding unsigned comparison. + If CODE is an equality comparison or already an unsigned comparison, + CODE is returned. */ + +enum rtx_code +unsigned_condition (code) + enum rtx_code code; +{ + switch (code) + { + case EQ: + case NE: + case GTU: + case GEU: + case LTU: + case LEU: + return code; + + case GT: + return GTU; + + case GE: + return GEU; + + case LT: + return LTU; + + case LE: + return LEU; + + default: + abort (); + } +} + +/* Similarly, return the signed version of a comparison. */ + +enum rtx_code +signed_condition (code) + enum rtx_code code; +{ + switch (code) + { + case EQ: + case NE: + case GT: + case GE: + case LT: + case LE: + return code; + + case GTU: + return GT; + + case GEU: + return GE; + + case LTU: + return LT; + + case LEU: + return LE; + + default: + abort (); + } +} + +/* Return non-zero if CODE1 is more strict than CODE2, i.e., if the + truth of CODE1 implies the truth of CODE2. */ + +int +comparison_dominates_p (code1, code2) + enum rtx_code code1, code2; +{ + if (code1 == code2) + return 1; + + switch (code1) + { + case EQ: + if (code2 == LE || code2 == LEU || code2 == GE || code2 == GEU) + return 1; + break; + + case LT: + if (code2 == LE) + return 1; + break; + + case GT: + if (code2 == GE) + return 1; + break; + + case LTU: + if (code2 == LEU) + return 1; + break; + + case GTU: + if (code2 == GEU) + return 1; + break; + } + + return 0; +} + +/* Return 1 if INSN is an unconditional jump and nothing else. */ + +int +simplejump_p (insn) + rtx insn; +{ + return (GET_CODE (insn) == JUMP_INSN + && GET_CODE (PATTERN (insn)) == SET + && GET_CODE (SET_DEST (PATTERN (insn))) == PC + && GET_CODE (SET_SRC (PATTERN (insn))) == LABEL_REF); +} + +/* Return nonzero if INSN is a (possibly) conditional jump + and nothing more. */ + +int +condjump_p (insn) + rtx insn; +{ + register rtx x = PATTERN (insn); + if (GET_CODE (x) != SET) + return 0; + if (GET_CODE (SET_DEST (x)) != PC) + return 0; + if (GET_CODE (SET_SRC (x)) == LABEL_REF) + return 1; + if (GET_CODE (SET_SRC (x)) != IF_THEN_ELSE) + return 0; + if (XEXP (SET_SRC (x), 2) == pc_rtx + && (GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF + || GET_CODE (XEXP (SET_SRC (x), 1)) == RETURN)) + return 1; + if (XEXP (SET_SRC (x), 1) == pc_rtx + && (GET_CODE (XEXP (SET_SRC (x), 2)) == LABEL_REF + || GET_CODE (XEXP (SET_SRC (x), 2)) == RETURN)) + return 1; + return 0; +} + +/* Return 1 if X is an RTX that does nothing but set the condition codes + and CLOBBER or USE registers. + Return -1 if X does explicitly set the condition codes, + but also does other things. */ + +int +sets_cc0_p (x) + rtx x; +{ +#ifdef HAVE_cc0 + if (GET_CODE (x) == SET && SET_DEST (x) == cc0_rtx) + return 1; + if (GET_CODE (x) == PARALLEL) + { + int i; + int sets_cc0 = 0; + int other_things = 0; + for (i = XVECLEN (x, 0) - 1; i >= 0; i--) + { + if (GET_CODE (XVECEXP (x, 0, i)) == SET + && SET_DEST (XVECEXP (x, 0, i)) == cc0_rtx) + sets_cc0 = 1; + else if (GET_CODE (XVECEXP (x, 0, i)) == SET) + other_things = 1; + } + return ! sets_cc0 ? 0 : other_things ? -1 : 1; + } + return 0; +#else + abort (); +#endif +} + +/* Follow any unconditional jump at LABEL; + return the ultimate label reached by any such chain of jumps. + If LABEL is not followed by a jump, return LABEL. + If the chain loops or we can't find end, return LABEL, + since that tells caller to avoid changing the insn. + + If RELOAD_COMPLETED is 0, we do not chain across a NOTE_INSN_LOOP_BEG or + a USE or CLOBBER. */ + +rtx +follow_jumps (label) + rtx label; +{ + register rtx insn; + register rtx next; + register rtx value = label; + register int depth; + + for (depth = 0; + (depth < 10 + && (insn = next_active_insn (value)) != 0 + && GET_CODE (insn) == JUMP_INSN + && (JUMP_LABEL (insn) != 0 || GET_CODE (PATTERN (insn)) == RETURN) + && (next = NEXT_INSN (insn)) + && GET_CODE (next) == BARRIER); + depth++) + { + /* Don't chain through the insn that jumps into a loop + from outside the loop, + since that would create multiple loop entry jumps + and prevent loop optimization. */ + rtx tem; + if (!reload_completed) + for (tem = value; tem != insn; tem = NEXT_INSN (tem)) + if (GET_CODE (tem) == NOTE + && NOTE_LINE_NUMBER (tem) == NOTE_INSN_LOOP_BEG) + return value; + + /* If we have found a cycle, make the insn jump to itself. */ + if (JUMP_LABEL (insn) == label) + return label; + value = JUMP_LABEL (insn); + } + if (depth == 10) + return label; + return value; +} + +/* Assuming that field IDX of X is a vector of label_refs, + replace each of them by the ultimate label reached by it. + Return nonzero if a change is made. + If IGNORE_LOOPS is 0, we do not chain across a NOTE_INSN_LOOP_BEG. */ + +static int +tension_vector_labels (x, idx) + register rtx x; + register int idx; +{ + int changed = 0; + register int i; + for (i = XVECLEN (x, idx) - 1; i >= 0; i--) + { + register rtx olabel = XEXP (XVECEXP (x, idx, i), 0); + register rtx nlabel = follow_jumps (olabel); + if (nlabel && nlabel != olabel) + { + XEXP (XVECEXP (x, idx, i), 0) = nlabel; + ++LABEL_NUSES (nlabel); + if (--LABEL_NUSES (olabel) == 0) + delete_insn (olabel); + changed = 1; + } + } + return changed; +} + +/* Find all CODE_LABELs referred to in X, and increment their use counts. + If INSN is a JUMP_INSN and there is at least one CODE_LABEL referenced + in INSN, then store one of them in JUMP_LABEL (INSN). + If INSN is an INSN or a CALL_INSN and there is at least one CODE_LABEL + referenced in INSN, add a REG_LABEL note containing that label to INSN. + Also, when there are consecutive labels, canonicalize on the last of them. + + Note that two labels separated by a loop-beginning note + must be kept distinct if we have not yet done loop-optimization, + because the gap between them is where loop-optimize + will want to move invariant code to. CROSS_JUMP tells us + that loop-optimization is done with. + + Once reload has completed (CROSS_JUMP non-zero), we need not consider + two labels distinct if they are separated by only USE or CLOBBER insns. */ + +static void +mark_jump_label (x, insn, cross_jump) + register rtx x; + rtx insn; + int cross_jump; +{ + register RTX_CODE code = GET_CODE (x); + register int i; + register char *fmt; + + switch (code) + { + case PC: + case CC0: + case REG: + case SUBREG: + case CONST_INT: + case SYMBOL_REF: + case CONST_DOUBLE: + case CLOBBER: + case CALL: + return; + + case MEM: + /* If this is a constant-pool reference, see if it is a label. */ + if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))) + mark_jump_label (get_pool_constant (XEXP (x, 0)), insn, cross_jump); + break; + + case LABEL_REF: + { + register rtx label = XEXP (x, 0); + register rtx next; + if (GET_CODE (label) != CODE_LABEL) + abort (); + /* Ignore references to labels of containing functions. */ + if (LABEL_REF_NONLOCAL_P (x)) + break; + /* If there are other labels following this one, + replace it with the last of the consecutive labels. */ + for (next = NEXT_INSN (label); next; next = NEXT_INSN (next)) + { + if (GET_CODE (next) == CODE_LABEL) + label = next; + else if (cross_jump && GET_CODE (next) == INSN + && (GET_CODE (PATTERN (next)) == USE + || GET_CODE (PATTERN (next)) == CLOBBER)) + continue; + else if (GET_CODE (next) != NOTE) + break; + else if (! cross_jump + && (NOTE_LINE_NUMBER (next) == NOTE_INSN_LOOP_BEG + || NOTE_LINE_NUMBER (next) == NOTE_INSN_FUNCTION_END)) + break; + } + XEXP (x, 0) = label; + ++LABEL_NUSES (label); + if (insn) + { + if (GET_CODE (insn) == JUMP_INSN) + JUMP_LABEL (insn) = label; + else if (! find_reg_note (insn, REG_LABEL, label)) + { + rtx next = next_real_insn (label); + /* Don't record labels that refer to dispatch tables. + This is not necessary, since the tablejump + references the same label. + And if we did record them, flow.c would make worse code. */ + if (next == 0 + || ! (GET_CODE (next) == JUMP_INSN + && (GET_CODE (PATTERN (next)) == ADDR_VEC + || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC))) + { + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL, label, + REG_NOTES (insn)); + /* Record in the note whether label is nonlocal. */ + LABEL_REF_NONLOCAL_P (REG_NOTES (insn)) + = LABEL_REF_NONLOCAL_P (x); + } + } + } + return; + } + + /* Do walk the labels in a vector, but not the first operand of an + ADDR_DIFF_VEC. Don't set the JUMP_LABEL of a vector. */ + case ADDR_VEC: + case ADDR_DIFF_VEC: + { + int eltnum = code == ADDR_DIFF_VEC ? 1 : 0; + + for (i = 0; i < XVECLEN (x, eltnum); i++) + mark_jump_label (XVECEXP (x, eltnum, i), NULL_RTX, cross_jump); + return; + } + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + mark_jump_label (XEXP (x, i), insn, cross_jump); + else if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + mark_jump_label (XVECEXP (x, i, j), insn, cross_jump); + } + } +} + +/* If all INSN does is set the pc, delete it, + and delete the insn that set the condition codes for it + if that's what the previous thing was. */ + +void +delete_jump (insn) + rtx insn; +{ + register rtx set = single_set (insn); + + if (set && GET_CODE (SET_DEST (set)) == PC) + delete_computation (insn); +} + +/* Delete INSN and recursively delete insns that compute values used only + by INSN. This uses the REG_DEAD notes computed during flow analysis. + If we are running before flow.c, we need do nothing since flow.c will + delete dead code. We also can't know if the registers being used are + dead or not at this point. + + Otherwise, look at all our REG_DEAD notes. If a previous insn does + nothing other than set a register that dies in this insn, we can delete + that insn as well. + + On machines with CC0, if CC0 is used in this insn, we may be able to + delete the insn that set it. */ + +void +delete_computation (insn) + rtx insn; +{ + rtx note, next; + +#ifdef HAVE_cc0 + if (reg_referenced_p (cc0_rtx, PATTERN (insn))) + { + rtx prev = prev_nonnote_insn (insn); + /* We assume that at this stage + CC's are always set explicitly + and always immediately before the jump that + will use them. So if the previous insn + exists to set the CC's, delete it + (unless it performs auto-increments, etc.). */ + if (prev && GET_CODE (prev) == INSN + && sets_cc0_p (PATTERN (prev))) + { + if (sets_cc0_p (PATTERN (prev)) > 0 + && !FIND_REG_INC_NOTE (prev, NULL_RTX)) + delete_computation (prev); + else + /* Otherwise, show that cc0 won't be used. */ + REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_UNUSED, + cc0_rtx, REG_NOTES (prev)); + } + } +#endif + + for (note = REG_NOTES (insn); note; note = next) + { + rtx our_prev; + + next = XEXP (note, 1); + + if (REG_NOTE_KIND (note) != REG_DEAD + /* Verify that the REG_NOTE is legitimate. */ + || GET_CODE (XEXP (note, 0)) != REG) + continue; + + for (our_prev = prev_nonnote_insn (insn); + our_prev && GET_CODE (our_prev) == INSN; + our_prev = prev_nonnote_insn (our_prev)) + { + /* If we reach a SEQUENCE, it is too complex to try to + do anything with it, so give up. */ + if (GET_CODE (PATTERN (our_prev)) == SEQUENCE) + break; + + if (GET_CODE (PATTERN (our_prev)) == USE + && GET_CODE (XEXP (PATTERN (our_prev), 0)) == INSN) + /* reorg creates USEs that look like this. We leave them + alone because reorg needs them for its own purposes. */ + break; + + if (reg_set_p (XEXP (note, 0), PATTERN (our_prev))) + { + if (FIND_REG_INC_NOTE (our_prev, NULL_RTX)) + break; + + if (GET_CODE (PATTERN (our_prev)) == PARALLEL) + { + /* If we find a SET of something else, we can't + delete the insn. */ + + int i; + + for (i = 0; i < XVECLEN (PATTERN (our_prev), 0); i++) + { + rtx part = XVECEXP (PATTERN (our_prev), 0, i); + + if (GET_CODE (part) == SET + && SET_DEST (part) != XEXP (note, 0)) + break; + } + + if (i == XVECLEN (PATTERN (our_prev), 0)) + delete_computation (our_prev); + } + else if (GET_CODE (PATTERN (our_prev)) == SET + && SET_DEST (PATTERN (our_prev)) == XEXP (note, 0)) + delete_computation (our_prev); + + break; + } + + /* If OUR_PREV references the register that dies here, it is an + additional use. Hence any prior SET isn't dead. However, this + insn becomes the new place for the REG_DEAD note. */ + if (reg_overlap_mentioned_p (XEXP (note, 0), + PATTERN (our_prev))) + { + XEXP (note, 1) = REG_NOTES (our_prev); + REG_NOTES (our_prev) = note; + break; + } + } + } + + delete_insn (insn); +} + +/* Delete insn INSN from the chain of insns and update label ref counts. + May delete some following insns as a consequence; may even delete + a label elsewhere and insns that follow it. + + Returns the first insn after INSN that was not deleted. */ + +rtx +delete_insn (insn) + register rtx insn; +{ + register rtx next = NEXT_INSN (insn); + register rtx prev = PREV_INSN (insn); + register int was_code_label = (GET_CODE (insn) == CODE_LABEL); + register int dont_really_delete = 0; + + while (next && INSN_DELETED_P (next)) + next = NEXT_INSN (next); + + /* This insn is already deleted => return first following nondeleted. */ + if (INSN_DELETED_P (insn)) + return next; + + /* Don't delete user-declared labels. Convert them to special NOTEs + instead. */ + if (was_code_label && LABEL_NAME (insn) != 0 + && optimize && ! dont_really_delete) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED_LABEL; + NOTE_SOURCE_FILE (insn) = 0; + dont_really_delete = 1; + } + else + /* Mark this insn as deleted. */ + INSN_DELETED_P (insn) = 1; + + /* If this is an unconditional jump, delete it from the jump chain. */ + if (simplejump_p (insn)) + delete_from_jump_chain (insn); + + /* If instruction is followed by a barrier, + delete the barrier too. */ + + if (next != 0 && GET_CODE (next) == BARRIER) + { + INSN_DELETED_P (next) = 1; + next = NEXT_INSN (next); + } + + /* Patch out INSN (and the barrier if any) */ + + if (optimize && ! dont_really_delete) + { + if (prev) + { + NEXT_INSN (prev) = next; + if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) + NEXT_INSN (XVECEXP (PATTERN (prev), 0, + XVECLEN (PATTERN (prev), 0) - 1)) = next; + } + + if (next) + { + PREV_INSN (next) = prev; + if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) + PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; + } + + if (prev && NEXT_INSN (prev) == 0) + set_last_insn (prev); + } + + /* If deleting a jump, decrement the count of the label, + and delete the label if it is now unused. */ + + if (GET_CODE (insn) == JUMP_INSN && JUMP_LABEL (insn)) + if (--LABEL_NUSES (JUMP_LABEL (insn)) == 0) + { + /* This can delete NEXT or PREV, + either directly if NEXT is JUMP_LABEL (INSN), + or indirectly through more levels of jumps. */ + delete_insn (JUMP_LABEL (insn)); + /* I feel a little doubtful about this loop, + but I see no clean and sure alternative way + to find the first insn after INSN that is not now deleted. + I hope this works. */ + while (next && INSN_DELETED_P (next)) + next = NEXT_INSN (next); + return next; + } + + while (prev && (INSN_DELETED_P (prev) || GET_CODE (prev) == NOTE)) + prev = PREV_INSN (prev); + + /* If INSN was a label and a dispatch table follows it, + delete the dispatch table. The tablejump must have gone already. + It isn't useful to fall through into a table. */ + + if (was_code_label + && NEXT_INSN (insn) != 0 + && GET_CODE (NEXT_INSN (insn)) == JUMP_INSN + && (GET_CODE (PATTERN (NEXT_INSN (insn))) == ADDR_VEC + || GET_CODE (PATTERN (NEXT_INSN (insn))) == ADDR_DIFF_VEC)) + next = delete_insn (NEXT_INSN (insn)); + + /* If INSN was a label, delete insns following it if now unreachable. */ + + if (was_code_label && prev && GET_CODE (prev) == BARRIER) + { + register RTX_CODE code; + while (next != 0 + && ((code = GET_CODE (next)) == INSN + || code == JUMP_INSN || code == CALL_INSN + || code == NOTE + || (code == CODE_LABEL && INSN_DELETED_P (next)))) + { + if (code == NOTE + && NOTE_LINE_NUMBER (next) != NOTE_INSN_FUNCTION_END) + next = NEXT_INSN (next); + /* Keep going past other deleted labels to delete what follows. */ + else if (code == CODE_LABEL && INSN_DELETED_P (next)) + next = NEXT_INSN (next); + else + /* Note: if this deletes a jump, it can cause more + deletion of unreachable code, after a different label. + As long as the value from this recursive call is correct, + this invocation functions correctly. */ + next = delete_insn (next); + } + } + + return next; +} + +/* Advance from INSN till reaching something not deleted + then return that. May return INSN itself. */ + +rtx +next_nondeleted_insn (insn) + rtx insn; +{ + while (INSN_DELETED_P (insn)) + insn = NEXT_INSN (insn); + return insn; +} + +/* Delete a range of insns from FROM to TO, inclusive. + This is for the sake of peephole optimization, so assume + that whatever these insns do will still be done by a new + peephole insn that will replace them. */ + +void +delete_for_peephole (from, to) + register rtx from, to; +{ + register rtx insn = from; + + while (1) + { + register rtx next = NEXT_INSN (insn); + register rtx prev = PREV_INSN (insn); + + if (GET_CODE (insn) != NOTE) + { + INSN_DELETED_P (insn) = 1; + + /* Patch this insn out of the chain. */ + /* We don't do this all at once, because we + must preserve all NOTEs. */ + if (prev) + NEXT_INSN (prev) = next; + + if (next) + PREV_INSN (next) = prev; + } + + if (insn == to) + break; + insn = next; + } + + /* Note that if TO is an unconditional jump + we *do not* delete the BARRIER that follows, + since the peephole that replaces this sequence + is also an unconditional jump in that case. */ +} + +/* Invert the condition of the jump JUMP, and make it jump + to label NLABEL instead of where it jumps now. */ + +int +invert_jump (jump, nlabel) + rtx jump, nlabel; +{ + register rtx olabel = JUMP_LABEL (jump); + + /* We have to either invert the condition and change the label or + do neither. Either operation could fail. We first try to invert + the jump. If that succeeds, we try changing the label. If that fails, + we invert the jump back to what it was. */ + + if (! invert_exp (PATTERN (jump), jump)) + return 0; + + if (redirect_jump (jump, nlabel)) + return 1; + + if (! invert_exp (PATTERN (jump), jump)) + /* This should just be putting it back the way it was. */ + abort (); + + return 0; +} + +/* Invert the jump condition of rtx X contained in jump insn, INSN. + + Return 1 if we can do so, 0 if we cannot find a way to do so that + matches a pattern. */ + +int +invert_exp (x, insn) + rtx x; + rtx insn; +{ + register RTX_CODE code; + register int i; + register char *fmt; + + code = GET_CODE (x); + + if (code == IF_THEN_ELSE) + { + register rtx comp = XEXP (x, 0); + register rtx tem; + + /* We can do this in two ways: The preferable way, which can only + be done if this is not an integer comparison, is to reverse + the comparison code. Otherwise, swap the THEN-part and ELSE-part + of the IF_THEN_ELSE. If we can't do either, fail. */ + + if (can_reverse_comparison_p (comp, insn) + && validate_change (insn, &XEXP (x, 0), + gen_rtx (reverse_condition (GET_CODE (comp)), + GET_MODE (comp), XEXP (comp, 0), + XEXP (comp, 1)), 0)) + return 1; + + tem = XEXP (x, 1); + validate_change (insn, &XEXP (x, 1), XEXP (x, 2), 1); + validate_change (insn, &XEXP (x, 2), tem, 1); + return apply_change_group (); + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + if (! invert_exp (XEXP (x, i), insn)) + return 0; + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + if (!invert_exp (XVECEXP (x, i, j), insn)) + return 0; + } + } + + return 1; +} + +/* Make jump JUMP jump to label NLABEL instead of where it jumps now. + If the old jump target label is unused as a result, + it and the code following it may be deleted. + + If NLABEL is zero, we are to turn the jump into a (possibly conditional) + RETURN insn. + + The return value will be 1 if the change was made, 0 if it wasn't (this + can only occur for NLABEL == 0). */ + +int +redirect_jump (jump, nlabel) + rtx jump, nlabel; +{ + register rtx olabel = JUMP_LABEL (jump); + + if (nlabel == olabel) + return 1; + + if (! redirect_exp (&PATTERN (jump), olabel, nlabel, jump)) + return 0; + + /* If this is an unconditional branch, delete it from the jump_chain of + OLABEL and add it to the jump_chain of NLABEL (assuming both labels + have UID's in range and JUMP_CHAIN is valid). */ + if (jump_chain && (simplejump_p (jump) + || GET_CODE (PATTERN (jump)) == RETURN)) + { + int label_index = nlabel ? INSN_UID (nlabel) : 0; + + delete_from_jump_chain (jump); + if (label_index < max_jump_chain + && INSN_UID (jump) < max_jump_chain) + { + jump_chain[INSN_UID (jump)] = jump_chain[label_index]; + jump_chain[label_index] = jump; + } + } + + JUMP_LABEL (jump) = nlabel; + if (nlabel) + ++LABEL_NUSES (nlabel); + + if (olabel && --LABEL_NUSES (olabel) == 0) + delete_insn (olabel); + + return 1; +} + +/* Delete the instruction JUMP from any jump chain it might be on. */ + +static void +delete_from_jump_chain (jump) + rtx jump; +{ + int index; + rtx olabel = JUMP_LABEL (jump); + + /* Handle unconditional jumps. */ + if (jump_chain && olabel != 0 + && INSN_UID (olabel) < max_jump_chain + && simplejump_p (jump)) + index = INSN_UID (olabel); + /* Handle return insns. */ + else if (jump_chain && GET_CODE (PATTERN (jump)) == RETURN) + index = 0; + else return; + + if (jump_chain[index] == jump) + jump_chain[index] = jump_chain[INSN_UID (jump)]; + else + { + rtx insn; + + for (insn = jump_chain[index]; + insn != 0; + insn = jump_chain[INSN_UID (insn)]) + if (jump_chain[INSN_UID (insn)] == jump) + { + jump_chain[INSN_UID (insn)] = jump_chain[INSN_UID (jump)]; + break; + } + } +} + +/* If NLABEL is nonzero, throughout the rtx at LOC, + alter (LABEL_REF OLABEL) to (LABEL_REF NLABEL). If OLABEL is + zero, alter (RETURN) to (LABEL_REF NLABEL). + + If NLABEL is zero, alter (LABEL_REF OLABEL) to (RETURN) and check + validity with validate_change. Convert (set (pc) (label_ref olabel)) + to (return). + + Return 0 if we found a change we would like to make but it is invalid. + Otherwise, return 1. */ + +int +redirect_exp (loc, olabel, nlabel, insn) + rtx *loc; + rtx olabel, nlabel; + rtx insn; +{ + register rtx x = *loc; + register RTX_CODE code = GET_CODE (x); + register int i; + register char *fmt; + + if (code == LABEL_REF) + { + if (XEXP (x, 0) == olabel) + { + if (nlabel) + XEXP (x, 0) = nlabel; + else + return validate_change (insn, loc, gen_rtx (RETURN, VOIDmode), 0); + return 1; + } + } + else if (code == RETURN && olabel == 0) + { + x = gen_rtx (LABEL_REF, VOIDmode, nlabel); + if (loc == &PATTERN (insn)) + x = gen_rtx (SET, VOIDmode, pc_rtx, x); + return validate_change (insn, loc, x, 0); + } + + if (code == SET && nlabel == 0 && SET_DEST (x) == pc_rtx + && GET_CODE (SET_SRC (x)) == LABEL_REF + && XEXP (SET_SRC (x), 0) == olabel) + return validate_change (insn, loc, gen_rtx (RETURN, VOIDmode), 0); + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + if (! redirect_exp (&XEXP (x, i), olabel, nlabel, insn)) + return 0; + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + if (! redirect_exp (&XVECEXP (x, i, j), olabel, nlabel, insn)) + return 0; + } + } + + return 1; +} + +/* Make jump JUMP jump to label NLABEL, assuming it used to be a tablejump. + + If the old jump target label (before the dispatch table) becomes unused, + it and the dispatch table may be deleted. In that case, find the insn + before the jump references that label and delete it and logical successors + too. */ + +void +redirect_tablejump (jump, nlabel) + rtx jump, nlabel; +{ + register rtx olabel = JUMP_LABEL (jump); + + /* Add this jump to the jump_chain of NLABEL. */ + if (jump_chain && INSN_UID (nlabel) < max_jump_chain + && INSN_UID (jump) < max_jump_chain) + { + jump_chain[INSN_UID (jump)] = jump_chain[INSN_UID (nlabel)]; + jump_chain[INSN_UID (nlabel)] = jump; + } + + PATTERN (jump) = gen_jump (nlabel); + JUMP_LABEL (jump) = nlabel; + ++LABEL_NUSES (nlabel); + INSN_CODE (jump) = -1; + + if (--LABEL_NUSES (olabel) == 0) + { + delete_labelref_insn (jump, olabel, 0); + delete_insn (olabel); + } +} + +/* Find the insn referencing LABEL that is a logical predecessor of INSN. + If we found one, delete it and then delete this insn if DELETE_THIS is + non-zero. Return non-zero if INSN or a predecessor references LABEL. */ + +static int +delete_labelref_insn (insn, label, delete_this) + rtx insn, label; + int delete_this; +{ + int deleted = 0; + rtx link; + + if (GET_CODE (insn) != NOTE + && reg_mentioned_p (label, PATTERN (insn))) + { + if (delete_this) + { + delete_insn (insn); + deleted = 1; + } + else + return 1; + } + + for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) + if (delete_labelref_insn (XEXP (link, 0), label, 1)) + { + if (delete_this) + { + delete_insn (insn); + deleted = 1; + } + else + return 1; + } + + return deleted; +} + +/* Like rtx_equal_p except that it considers two REGs as equal + if they renumber to the same value. */ + +int +rtx_renumbered_equal_p (x, y) + rtx x, y; +{ + register int i; + register RTX_CODE code = GET_CODE (x); + register char *fmt; + + if (x == y) + return 1; + if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)) + && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG + && GET_CODE (SUBREG_REG (y)) == REG))) + { + register int j; + + if (GET_MODE (x) != GET_MODE (y)) + return 0; + + /* If we haven't done any renumbering, don't + make any assumptions. */ + if (reg_renumber == 0) + return rtx_equal_p (x, y); + + if (code == SUBREG) + { + i = REGNO (SUBREG_REG (x)); + if (reg_renumber[i] >= 0) + i = reg_renumber[i]; + i += SUBREG_WORD (x); + } + else + { + i = REGNO (x); + if (reg_renumber[i] >= 0) + i = reg_renumber[i]; + } + if (GET_CODE (y) == SUBREG) + { + j = REGNO (SUBREG_REG (y)); + if (reg_renumber[j] >= 0) + j = reg_renumber[j]; + j += SUBREG_WORD (y); + } + else + { + j = REGNO (y); + if (reg_renumber[j] >= 0) + j = reg_renumber[j]; + } + return i == j; + } + /* Now we have disposed of all the cases + in which different rtx codes can match. */ + if (code != GET_CODE (y)) + return 0; + switch (code) + { + case PC: + case CC0: + case ADDR_VEC: + case ADDR_DIFF_VEC: + return 0; + + case CONST_INT: + return XINT (x, 0) == XINT (y, 0); + + case LABEL_REF: + /* We can't assume nonlocal labels have their following insns yet. */ + if (LABEL_REF_NONLOCAL_P (x) || LABEL_REF_NONLOCAL_P (y)) + return XEXP (x, 0) == XEXP (y, 0); + /* Two label-refs are equivalent if they point at labels + in the same position in the instruction stream. */ + return (next_real_insn (XEXP (x, 0)) + == next_real_insn (XEXP (y, 0))); + + case SYMBOL_REF: + return XSTR (x, 0) == XSTR (y, 0); + } + + /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ + + if (GET_MODE (x) != GET_MODE (y)) + return 0; + + /* Compare the elements. If any pair of corresponding elements + fail to match, return 0 for the whole things. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + register int j; + switch (fmt[i]) + { + case 'w': + if (XWINT (x, i) != XWINT (y, i)) + return 0; + break; + + case 'i': + if (XINT (x, i) != XINT (y, i)) + return 0; + break; + + case 's': + if (strcmp (XSTR (x, i), XSTR (y, i))) + return 0; + break; + + case 'e': + if (! rtx_renumbered_equal_p (XEXP (x, i), XEXP (y, i))) + return 0; + break; + + case 'u': + if (XEXP (x, i) != XEXP (y, i)) + return 0; + /* fall through. */ + case '0': + break; + + case 'E': + if (XVECLEN (x, i) != XVECLEN (y, i)) + return 0; + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + if (!rtx_renumbered_equal_p (XVECEXP (x, i, j), XVECEXP (y, i, j))) + return 0; + break; + + default: + abort (); + } + } + return 1; +} + +/* If X is a hard register or equivalent to one or a subregister of one, + return the hard register number. If X is a pseudo register that was not + assigned a hard register, return the pseudo register number. Otherwise, + return -1. Any rtx is valid for X. */ + +int +true_regnum (x) + rtx x; +{ + if (GET_CODE (x) == REG) + { + if (REGNO (x) >= FIRST_PSEUDO_REGISTER && reg_renumber[REGNO (x)] >= 0) + return reg_renumber[REGNO (x)]; + return REGNO (x); + } + if (GET_CODE (x) == SUBREG) + { + int base = true_regnum (SUBREG_REG (x)); + if (base >= 0 && base < FIRST_PSEUDO_REGISTER) + return SUBREG_WORD (x) + base; + } + return -1; +} + +/* Optimize code of the form: + + for (x = a[i]; x; ...) + ... + for (x = a[i]; x; ...) + ... + foo: + + Loop optimize will change the above code into + + if (x = a[i]) + for (;;) + { ...; if (! (x = ...)) break; } + if (x = a[i]) + for (;;) + { ...; if (! (x = ...)) break; } + foo: + + In general, if the first test fails, the program can branch + directly to `foo' and skip the second try which is doomed to fail. + We run this after loop optimization and before flow analysis. */ + +/* When comparing the insn patterns, we track the fact that different + pseudo-register numbers may have been used in each computation. + The following array stores an equivalence -- same_regs[I] == J means + that pseudo register I was used in the first set of tests in a context + where J was used in the second set. We also count the number of such + pending equivalences. If nonzero, the expressions really aren't the + same. */ + +static int *same_regs; + +static int num_same_regs; + +/* Track any registers modified between the target of the first jump and + the second jump. They never compare equal. */ + +static char *modified_regs; + +/* Record if memory was modified. */ + +static int modified_mem; + +/* Called via note_stores on each insn between the target of the first + branch and the second branch. It marks any changed registers. */ + +static void +mark_modified_reg (dest, x) + rtx dest; + rtx x; +{ + int regno, i; + + if (GET_CODE (dest) == SUBREG) + dest = SUBREG_REG (dest); + + if (GET_CODE (dest) == MEM) + modified_mem = 1; + + if (GET_CODE (dest) != REG) + return; + + regno = REGNO (dest); + if (regno >= FIRST_PSEUDO_REGISTER) + modified_regs[regno] = 1; + else + for (i = 0; i < HARD_REGNO_NREGS (regno, GET_MODE (dest)); i++) + modified_regs[regno + i] = 1; +} + +/* F is the first insn in the chain of insns. */ + +void +thread_jumps (f, max_reg, verbose) + rtx f; + int max_reg; + int verbose; +{ + /* Basic algorithm is to find a conditional branch, + the label it may branch to, and the branch after + that label. If the two branches test the same condition, + walk back from both branch paths until the insn patterns + differ, or code labels are hit. If we make it back to + the target of the first branch, then we know that the first branch + will either always succeed or always fail depending on the relative + senses of the two branches. So adjust the first branch accordingly + in this case. */ + + rtx label, b1, b2, t1, t2; + enum rtx_code code1, code2; + rtx b1op0, b1op1, b2op0, b2op1; + int changed = 1; + int i; + int *all_reset; + + /* Allocate register tables and quick-reset table. */ + modified_regs = (char *) alloca (max_reg * sizeof (char)); + same_regs = (int *) alloca (max_reg * sizeof (int)); + all_reset = (int *) alloca (max_reg * sizeof (int)); + for (i = 0; i < max_reg; i++) + all_reset[i] = -1; + + while (changed) + { + changed = 0; + + for (b1 = f; b1; b1 = NEXT_INSN (b1)) + { + /* Get to a candidate branch insn. */ + if (GET_CODE (b1) != JUMP_INSN + || ! condjump_p (b1) || simplejump_p (b1) + || JUMP_LABEL (b1) == 0) + continue; + + bzero (modified_regs, max_reg * sizeof (char)); + modified_mem = 0; + + bcopy (all_reset, same_regs, max_reg * sizeof (int)); + num_same_regs = 0; + + label = JUMP_LABEL (b1); + + /* Look for a branch after the target. Record any registers and + memory modified between the target and the branch. Stop when we + get to a label since we can't know what was changed there. */ + for (b2 = NEXT_INSN (label); b2; b2 = NEXT_INSN (b2)) + { + if (GET_CODE (b2) == CODE_LABEL) + break; + + else if (GET_CODE (b2) == JUMP_INSN) + { + /* If this is an unconditional jump and is the only use of + its target label, we can follow it. */ + if (simplejump_p (b2) + && JUMP_LABEL (b2) != 0 + && LABEL_NUSES (JUMP_LABEL (b2)) == 1) + { + b2 = JUMP_LABEL (b2); + continue; + } + else + break; + } + + if (GET_CODE (b2) != CALL_INSN && GET_CODE (b2) != INSN) + continue; + + if (GET_CODE (b2) == CALL_INSN) + { + modified_mem = 1; + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (call_used_regs[i] && ! fixed_regs[i] + && i != STACK_POINTER_REGNUM + && i != FRAME_POINTER_REGNUM + && i != ARG_POINTER_REGNUM) + modified_regs[i] = 1; + } + + note_stores (PATTERN (b2), mark_modified_reg); + } + + /* Check the next candidate branch insn from the label + of the first. */ + if (b2 == 0 + || GET_CODE (b2) != JUMP_INSN + || b2 == b1 + || ! condjump_p (b2) + || simplejump_p (b2)) + continue; + + /* Get the comparison codes and operands, reversing the + codes if appropriate. If we don't have comparison codes, + we can't do anything. */ + b1op0 = XEXP (XEXP (SET_SRC (PATTERN (b1)), 0), 0); + b1op1 = XEXP (XEXP (SET_SRC (PATTERN (b1)), 0), 1); + code1 = GET_CODE (XEXP (SET_SRC (PATTERN (b1)), 0)); + if (XEXP (SET_SRC (PATTERN (b1)), 1) == pc_rtx) + code1 = reverse_condition (code1); + + b2op0 = XEXP (XEXP (SET_SRC (PATTERN (b2)), 0), 0); + b2op1 = XEXP (XEXP (SET_SRC (PATTERN (b2)), 0), 1); + code2 = GET_CODE (XEXP (SET_SRC (PATTERN (b2)), 0)); + if (XEXP (SET_SRC (PATTERN (b2)), 1) == pc_rtx) + code2 = reverse_condition (code2); + + /* If they test the same things and knowing that B1 branches + tells us whether or not B2 branches, check if we + can thread the branch. */ + if (rtx_equal_for_thread_p (b1op0, b2op0, b2) + && rtx_equal_for_thread_p (b1op1, b2op1, b2) + && (comparison_dominates_p (code1, code2) + || comparison_dominates_p (code1, reverse_condition (code2)))) + { + t1 = prev_nonnote_insn (b1); + t2 = prev_nonnote_insn (b2); + + while (t1 != 0 && t2 != 0) + { + if (t1 == 0 || t2 == 0) + break; + + if (t2 == label) + { + /* We have reached the target of the first branch. + If there are no pending register equivalents, + we know that this branch will either always + succeed (if the senses of the two branches are + the same) or always fail (if not). */ + rtx new_label; + + if (num_same_regs != 0) + break; + + if (comparison_dominates_p (code1, code2)) + new_label = JUMP_LABEL (b2); + else + new_label = get_label_after (b2); + + if (JUMP_LABEL (b1) != new_label + && redirect_jump (b1, new_label)) + changed = 1; + break; + } + + /* If either of these is not a normal insn (it might be + a JUMP_INSN, CALL_INSN, or CODE_LABEL) we fail. (NOTEs + have already been skipped above.) Similarly, fail + if the insns are different. */ + if (GET_CODE (t1) != INSN || GET_CODE (t2) != INSN + || recog_memoized (t1) != recog_memoized (t2) + || ! rtx_equal_for_thread_p (PATTERN (t1), + PATTERN (t2), t2)) + break; + + t1 = prev_nonnote_insn (t1); + t2 = prev_nonnote_insn (t2); + } + } + } + } +} + +/* This is like RTX_EQUAL_P except that it knows about our handling of + possibly equivalent registers and knows to consider volatile and + modified objects as not equal. + + YINSN is the insn containing Y. */ + +int +rtx_equal_for_thread_p (x, y, yinsn) + rtx x, y; + rtx yinsn; +{ + register int i; + register int j; + register enum rtx_code code; + register char *fmt; + + code = GET_CODE (x); + /* Rtx's of different codes cannot be equal. */ + if (code != GET_CODE (y)) + return 0; + + /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. + (REG:SI x) and (REG:HI x) are NOT equivalent. */ + + if (GET_MODE (x) != GET_MODE (y)) + return 0; + + /* Handle special-cases first. */ + switch (code) + { + case REG: + if (REGNO (x) == REGNO (y) && ! modified_regs[REGNO (x)]) + return 1; + + /* If neither is user variable or hard register, check for possible + equivalence. */ + if (REG_USERVAR_P (x) || REG_USERVAR_P (y) + || REGNO (x) < FIRST_PSEUDO_REGISTER + || REGNO (y) < FIRST_PSEUDO_REGISTER) + return 0; + + if (same_regs[REGNO (x)] == -1) + { + same_regs[REGNO (x)] = REGNO (y); + num_same_regs++; + + /* If this is the first time we are seeing a register on the `Y' + side, see if it is the last use. If not, we can't thread the + jump, so mark it as not equivalent. */ + if (regno_last_uid[REGNO (y)] != INSN_UID (yinsn)) + return 0; + + return 1; + } + else + return (same_regs[REGNO (x)] == REGNO (y)); + + break; + + case MEM: + /* If memory modified or either volatile, not equivalent. + Else, check address. */ + if (modified_mem || MEM_VOLATILE_P (x) || MEM_VOLATILE_P (y)) + return 0; + + return rtx_equal_for_thread_p (XEXP (x, 0), XEXP (y, 0), yinsn); + + case ASM_INPUT: + if (MEM_VOLATILE_P (x) || MEM_VOLATILE_P (y)) + return 0; + + break; + + case SET: + /* Cancel a pending `same_regs' if setting equivalenced registers. + Then process source. */ + if (GET_CODE (SET_DEST (x)) == REG + && GET_CODE (SET_DEST (y)) == REG) + { + if (same_regs[REGNO (SET_DEST (x))] == REGNO (SET_DEST (y))) + { + same_regs[REGNO (SET_DEST (x))] = -1; + num_same_regs--; + } + else if (REGNO (SET_DEST (x)) != REGNO (SET_DEST (y))) + return 0; + } + else + if (rtx_equal_for_thread_p (SET_DEST (x), SET_DEST (y), yinsn) == 0) + return 0; + + return rtx_equal_for_thread_p (SET_SRC (x), SET_SRC (y), yinsn); + + case LABEL_REF: + return XEXP (x, 0) == XEXP (y, 0); + + case SYMBOL_REF: + return XSTR (x, 0) == XSTR (y, 0); + } + + if (x == y) + return 1; + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + switch (fmt[i]) + { + case 'w': + if (XWINT (x, i) != XWINT (y, i)) + return 0; + break; + + case 'n': + case 'i': + if (XINT (x, i) != XINT (y, i)) + return 0; + break; + + case 'V': + case 'E': + /* Two vectors must have the same length. */ + if (XVECLEN (x, i) != XVECLEN (y, i)) + return 0; + + /* And the corresponding elements must match. */ + for (j = 0; j < XVECLEN (x, i); j++) + if (rtx_equal_for_thread_p (XVECEXP (x, i, j), + XVECEXP (y, i, j), yinsn) == 0) + return 0; + break; + + case 'e': + if (rtx_equal_for_thread_p (XEXP (x, i), XEXP (y, i), yinsn) == 0) + return 0; + break; + + case 'S': + case 's': + if (strcmp (XSTR (x, i), XSTR (y, i))) + return 0; + break; + + case 'u': + /* These are just backpointers, so they don't matter. */ + break; + + case '0': + break; + + /* It is believed that rtx's at this level will never + contain anything but integers and other rtx's, + except for within LABEL_REFs and SYMBOL_REFs. */ + default: + abort (); + } + } + return 1; +} diff --git a/gnu/usr.bin/cc/lib/lib.mk b/gnu/usr.bin/cc/lib/lib.mk new file mode 100644 index 000000000000..88466c2ac222 --- /dev/null +++ b/gnu/usr.bin/cc/lib/lib.mk @@ -0,0 +1,196 @@ +# @(#)bsd.lib.mk 5.26 (Berkeley) 5/2/91 +# +# $Log: lib.mk,v $ +# Revision 1.2 1993/11/11 02:12:15 jkh +# Removed extra ld -x -r's that were gumming up the works (fix for now, +# may go shared later as soon as this is better tested). +# +# Revision 1.1 1993/08/05 02:15:32 paul +# Added lib.mk with lorder|tsort ripped out from library creation +# because tsort got stuck in a loop when setting HAVE_cossf2 to 0. +# +# Revision 1.7 1993/07/23 20:44:38 nate +# Fixed a boo-boo and made the NOMAN environment variable work correctly with +# both programs and libraries. +# +# Revision 1.6 1993/07/09 00:38:35 jkh +# Removed $History$ line from hell (no leading #). +# +# Revision 1.5 1993/07/08 12:17:07 paul +# Removed the core.* before disaster strikes. +# I removed core as well since it's pretty redundant. +# +# Revision 1.4 1993/07/07 21:42:45 nate +# Cleaned up header files and added core.* to clean directives +# +# Revision 1.3 1993/07/02 06:44:30 root +# New manual page system +# +# Revision 1.2 1993/06/17 02:01:11 rgrimes +# Make clean in src/lib/libc failed due to too many arguments to /bin/sh, +# this was fixed for make cleandir in the patchkit, this fixes it for +# make clean. +# + +.if exists(${.CURDIR}/../Makefile.inc) +.include "${.CURDIR}/../Makefile.inc" +.endif + +LIBDIR?= /usr/lib +LINTLIBDIR?= /usr/libdata/lint +LIBGRP?= bin +LIBOWN?= bin +LIBMODE?= 444 + +STRIP?= -s + +BINGRP?= bin +BINOWN?= bin +BINMODE?= 555 + +.MAIN: all + +# prefer .s to a .c, add .po, remove stuff not used in the BSD libraries +.SUFFIXES: .out .o .po .s .c .f .y .l + +.c.o: + ${CC} ${CFLAGS} -c ${.IMPSRC} +# @${LD} -x -r ${.TARGET} +# @mv a.out ${.TARGET} + +.c.po: + ${CC} -p ${CFLAGS} -c ${.IMPSRC} -o ${.TARGET} +# @${LD} -X -r ${.TARGET} +# @mv a.out ${.TARGET} + +.s.o: + ${CPP} -E ${CFLAGS:M-[ID]*} ${AINC} ${.IMPSRC} | \ + ${AS} -o ${.TARGET} +# @${LD} -x -r ${.TARGET} +# @mv a.out ${.TARGET} + +.s.po: + ${CPP} -E -DPROF ${CFLAGS:M-[ID]*} ${AINC} ${.IMPSRC} | \ + ${AS} -o ${.TARGET} +# @${LD} -X -r ${.TARGET} +# @mv a.out ${.TARGET} + +.if !defined(NOPROFILE) +_LIBS=lib${LIB}.a lib${LIB}_p.a +.else +_LIBS=lib${LIB}.a +.endif + +all: ${_LIBS} # llib-l${LIB}.ln + +OBJS+= ${SRCS:R:S/$/.o/g} + +lib${LIB}.a:: ${OBJS} + @echo building standard ${LIB} library + @rm -f lib${LIB}.a + @${AR} cTq lib${LIB}.a ${OBJS} + ranlib lib${LIB}.a + +POBJS+= ${OBJS:.o=.po} +lib${LIB}_p.a:: ${POBJS} + @echo building profiled ${LIB} library + @rm -f lib${LIB}_p.a + @${AR} cTq lib${LIB}_p.a `lorder ${POBJS} | tsort` ${LDADD} + ranlib lib${LIB}_p.a + +llib-l${LIB}.ln: ${SRCS} + ${LINT} -C${LIB} ${CFLAGS} ${.ALLSRC:M*.c} + +.if !target(clean) +clean: + rm -f a.out Errs errs mklog ${CLEANFILES} ${OBJS} \ + lib${LIB}.a llib-l${LIB}.ln + rm -f ${POBJS} profiled/*.o lib${LIB}_p.a +.endif + +.if !target(cleandir) +cleandir: + rm -f a.out Errs errs mklog ${CLEANFILES} ${OBJS} \ + lib${LIB}.a llib-l${LIB}.ln \ + ${.CURDIR}/tags .depend + rm -f ${POBJS} profiled/*.o lib${LIB}_p.a + cd ${.CURDIR}; rm -rf obj; +.endif + +.if !target(depend) +depend: .depend +.depend: ${SRCS} + mkdep ${CFLAGS:M-[ID+]*} ${AINC} ${.ALLSRC} + @(TMP=/tmp/_depend$$$$; \ + sed -e 's/^\([^\.]*\).o:/\1.o \1.po:/' < .depend > $$TMP; \ + mv $$TMP .depend) +.endif + +.if !target(install) +.if !target(beforeinstall) +beforeinstall: +.endif + +realinstall: beforeinstall + ranlib lib${LIB}.a + install ${COPY} -o ${LIBOWN} -g ${LIBGRP} -m ${LIBMODE} lib${LIB}.a \ + ${DESTDIR}${LIBDIR} + ${RANLIB} -t ${DESTDIR}${LIBDIR}/lib${LIB}.a +.if !defined(NOPROFILE) + ranlib lib${LIB}_p.a + install ${COPY} -o ${LIBOWN} -g ${LIBGRP} -m ${LIBMODE} \ + lib${LIB}_p.a ${DESTDIR}${LIBDIR} + ${RANLIB} -t ${DESTDIR}${LIBDIR}/lib${LIB}_p.a +.endif +# install ${COPY} -o ${LIBOWN} -g ${LIBGRP} -m ${LIBMODE} \ +# llib-l${LIB}.ln ${DESTDIR}${LINTLIBDIR} +.if defined(LINKS) && !empty(LINKS) + @set ${LINKS}; \ + while test $$# -ge 2; do \ + l=${DESTDIR}$$1; \ + shift; \ + t=${DESTDIR}$$1; \ + shift; \ + echo $$t -\> $$l; \ + rm -f $$t; \ + ln $$l $$t; \ + done; true +.endif + +install: afterinstall +.if !defined(NOMAN) +afterinstall: realinstall maninstall +.else +afterinstall: realinstall +.endif +.endif + +.if !target(lint) +lint: +.endif + +.if !target(tags) +tags: ${SRCS} + -cd ${.CURDIR}; ctags -f /dev/stdout ${.ALLSRC:M*.c} | \ + sed "s;\${.CURDIR}/;;" > tags +.endif + +.if !defined(NOMAN) +.include +.endif + +.if !target(obj) +.if defined(NOOBJ) +obj: +.else +obj: + @cd ${.CURDIR}; rm -rf obj; \ + here=`pwd`; dest=/usr/obj/`echo $$here | sed 's,/usr/src/,,'`; \ + echo "$$here -> $$dest"; ln -s $$dest obj; \ + if test -d /usr/obj -a ! -d $$dest; then \ + mkdir -p $$dest; \ + else \ + true; \ + fi; +.endif +.endif diff --git a/gnu/usr.bin/cc/lib/local-alloc.c b/gnu/usr.bin/cc/lib/local-alloc.c new file mode 100644 index 000000000000..6af09342524e --- /dev/null +++ b/gnu/usr.bin/cc/lib/local-alloc.c @@ -0,0 +1,2173 @@ +/* Allocate registers within a basic block, for GNU compiler. + Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* Allocation of hard register numbers to pseudo registers is done in + two passes. In this pass we consider only regs that are born and + die once within one basic block. We do this one basic block at a + time. Then the next pass allocates the registers that remain. + Two passes are used because this pass uses methods that work only + on linear code, but that do a better job than the general methods + used in global_alloc, and more quickly too. + + The assignments made are recorded in the vector reg_renumber + whose space is allocated here. The rtl code itself is not altered. + + We assign each instruction in the basic block a number + which is its order from the beginning of the block. + Then we can represent the lifetime of a pseudo register with + a pair of numbers, and check for conflicts easily. + We can record the availability of hard registers with a + HARD_REG_SET for each instruction. The HARD_REG_SET + contains 0 or 1 for each hard reg. + + To avoid register shuffling, we tie registers together when one + dies by being copied into another, or dies in an instruction that + does arithmetic to produce another. The tied registers are + allocated as one. Registers with different reg class preferences + can never be tied unless the class preferred by one is a subclass + of the one preferred by the other. + + Tying is represented with "quantity numbers". + A non-tied register is given a new quantity number. + Tied registers have the same quantity number. + + We have provision to exempt registers, even when they are contained + within the block, that can be tied to others that are not contained in it. + This is so that global_alloc could process them both and tie them then. + But this is currently disabled since tying in global_alloc is not + yet implemented. */ + +#include +#include "config.h" +#include "rtl.h" +#include "flags.h" +#include "basic-block.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "insn-config.h" +#include "recog.h" +#include "output.h" + +/* Pseudos allocated here cannot be reallocated by global.c if the hard + register is used as a spill register. So we don't allocate such pseudos + here if their preferred class is likely to be used by spills. + + On most machines, the appropriate test is if the class has one + register, so we default to that. */ + +#ifndef CLASS_LIKELY_SPILLED_P +#define CLASS_LIKELY_SPILLED_P(CLASS) (reg_class_size[(int) (CLASS)] == 1) +#endif + +/* Next quantity number available for allocation. */ + +static int next_qty; + +/* In all the following vectors indexed by quantity number. */ + +/* Element Q is the hard reg number chosen for quantity Q, + or -1 if none was found. */ + +static short *qty_phys_reg; + +/* We maintain two hard register sets that indicate suggested hard registers + for each quantity. The first, qty_phys_copy_sugg, contains hard registers + that are tied to the quantity by a simple copy. The second contains all + hard registers that are tied to the quantity via an arithmetic operation. + + The former register set is given priority for allocation. This tends to + eliminate copy insns. */ + +/* Element Q is a set of hard registers that are suggested for quantity Q by + copy insns. */ + +static HARD_REG_SET *qty_phys_copy_sugg; + +/* Element Q is a set of hard registers that are suggested for quantity Q by + arithmetic insns. */ + +static HARD_REG_SET *qty_phys_sugg; + +/* Element Q is non-zero if there is a suggested register in + qty_phys_copy_sugg. */ + +static char *qty_phys_has_copy_sugg; + +/* Element Q is non-zero if there is a suggested register in qty_phys_sugg. */ + +static char *qty_phys_has_sugg; + +/* Element Q is the number of refs to quantity Q. */ + +static int *qty_n_refs; + +/* Element Q is a reg class contained in (smaller than) the + preferred classes of all the pseudo regs that are tied in quantity Q. + This is the preferred class for allocating that quantity. */ + +static enum reg_class *qty_min_class; + +/* Insn number (counting from head of basic block) + where quantity Q was born. -1 if birth has not been recorded. */ + +static int *qty_birth; + +/* Insn number (counting from head of basic block) + where quantity Q died. Due to the way tying is done, + and the fact that we consider in this pass only regs that die but once, + a quantity can die only once. Each quantity's life span + is a set of consecutive insns. -1 if death has not been recorded. */ + +static int *qty_death; + +/* Number of words needed to hold the data in quantity Q. + This depends on its machine mode. It is used for these purposes: + 1. It is used in computing the relative importances of qtys, + which determines the order in which we look for regs for them. + 2. It is used in rules that prevent tying several registers of + different sizes in a way that is geometrically impossible + (see combine_regs). */ + +static int *qty_size; + +/* This holds the mode of the registers that are tied to qty Q, + or VOIDmode if registers with differing modes are tied together. */ + +static enum machine_mode *qty_mode; + +/* Number of times a reg tied to qty Q lives across a CALL_INSN. */ + +static int *qty_n_calls_crossed; + +/* Register class within which we allocate qty Q if we can't get + its preferred class. */ + +static enum reg_class *qty_alternate_class; + +/* Element Q is the SCRATCH expression for which this quantity is being + allocated or 0 if this quantity is allocating registers. */ + +static rtx *qty_scratch_rtx; + +/* Element Q is the register number of one pseudo register whose + reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This + register should be the head of the chain maintained in reg_next_in_qty. */ + +static int *qty_first_reg; + +/* If (REG N) has been assigned a quantity number, is a register number + of another register assigned the same quantity number, or -1 for the + end of the chain. qty_first_reg point to the head of this chain. */ + +static int *reg_next_in_qty; + +/* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg + if it is >= 0, + of -1 if this register cannot be allocated by local-alloc, + or -2 if not known yet. + + Note that if we see a use or death of pseudo register N with + reg_qty[N] == -2, register N must be local to the current block. If + it were used in more than one block, we would have reg_qty[N] == -1. + This relies on the fact that if reg_basic_block[N] is >= 0, register N + will not appear in any other block. We save a considerable number of + tests by exploiting this. + + If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not + be referenced. */ + +static int *reg_qty; + +/* The offset (in words) of register N within its quantity. + This can be nonzero if register N is SImode, and has been tied + to a subreg of a DImode register. */ + +static char *reg_offset; + +/* Vector of substitutions of register numbers, + used to map pseudo regs into hardware regs. + This is set up as a result of register allocation. + Element N is the hard reg assigned to pseudo reg N, + or is -1 if no hard reg was assigned. + If N is a hard reg number, element N is N. */ + +short *reg_renumber; + +/* Set of hard registers live at the current point in the scan + of the instructions in a basic block. */ + +static HARD_REG_SET regs_live; + +/* Each set of hard registers indicates registers live at a particular + point in the basic block. For N even, regs_live_at[N] says which + hard registers are needed *after* insn N/2 (i.e., they may not + conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. + + If an object is to conflict with the inputs of insn J but not the + outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, + if it is to conflict with the outputs of insn J but not the inputs of + insn J + 1, it is said to die at index J*2 + 1. */ + +static HARD_REG_SET *regs_live_at; + +/* Communicate local vars `insn_number' and `insn' + from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ +static int this_insn_number; +static rtx this_insn; + +static void block_alloc (); +static void update_equiv_regs (); +static int no_conflict_p (); +static int combine_regs (); +static void wipe_dead_reg (); +static int find_free_reg (); +static void reg_is_born (); +static void reg_is_set (); +static void mark_life (); +static void post_mark_life (); +static int qty_compare (); +static int qty_compare_1 (); +static int reg_meets_class_p (); +static void update_qty_class (); +static int requires_inout_p (); + +/* Allocate a new quantity (new within current basic block) + for register number REGNO which is born at index BIRTH + within the block. MODE and SIZE are info on reg REGNO. */ + +static void +alloc_qty (regno, mode, size, birth) + int regno; + enum machine_mode mode; + int size, birth; +{ + register int qty = next_qty++; + + reg_qty[regno] = qty; + reg_offset[regno] = 0; + reg_next_in_qty[regno] = -1; + + qty_first_reg[qty] = regno; + qty_size[qty] = size; + qty_mode[qty] = mode; + qty_birth[qty] = birth; + qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno]; + qty_min_class[qty] = reg_preferred_class (regno); + qty_alternate_class[qty] = reg_alternate_class (regno); + qty_n_refs[qty] = reg_n_refs[regno]; +} + +/* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx + used as operand N in INSN. We assume here that the SCRATCH is used in + a CLOBBER. */ + +static void +alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number) + rtx scratch; + int n; + rtx insn; + int insn_code_num, insn_number; +{ + register int qty; + enum reg_class class; + char *p, c; + int i; + +#ifdef REGISTER_CONSTRAINTS + /* If we haven't yet computed which alternative will be used, do so now. + Then set P to the constraints for that alternative. */ + if (which_alternative == -1) + if (! constrain_operands (insn_code_num, 0)) + return; + + for (p = insn_operand_constraint[insn_code_num][n], i = 0; + *p && i < which_alternative; p++) + if (*p == ',') + i++; + + /* Compute the class required for this SCRATCH. If we don't need a + register, the class will remain NO_REGS. If we guessed the alternative + number incorrectly, reload will fix things up for us. */ + + class = NO_REGS; + while ((c = *p++) != '\0' && c != ',') + switch (c) + { + case '=': case '+': case '?': + case '#': case '&': case '!': + case '*': case '%': + case '0': case '1': case '2': case '3': case '4': + case 'm': case '<': case '>': case 'V': case 'o': + case 'E': case 'F': case 'G': case 'H': + case 's': case 'i': case 'n': + case 'I': case 'J': case 'K': case 'L': + case 'M': case 'N': case 'O': case 'P': +#ifdef EXTRA_CONSTRAINT + case 'Q': case 'R': case 'S': case 'T': case 'U': +#endif + case 'p': + /* These don't say anything we care about. */ + break; + + case 'X': + /* We don't need to allocate this SCRATCH. */ + return; + + case 'g': case 'r': + class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; + break; + + default: + class + = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)]; + break; + } + + /* If CLASS has only a few registers, don't allocate the SCRATCH here since + it will prevent that register from being used as a spill register. + reload will do the allocation. */ + + if (class == NO_REGS || CLASS_LIKELY_SPILLED_P (class)) + return; + +#else /* REGISTER_CONSTRAINTS */ + + class = GENERAL_REGS; +#endif + + + qty = next_qty++; + + qty_first_reg[qty] = -1; + qty_scratch_rtx[qty] = scratch; + qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch)); + qty_mode[qty] = GET_MODE (scratch); + qty_birth[qty] = 2 * insn_number - 1; + qty_death[qty] = 2 * insn_number + 1; + qty_n_calls_crossed[qty] = 0; + qty_min_class[qty] = class; + qty_alternate_class[qty] = NO_REGS; + qty_n_refs[qty] = 1; +} + +/* Main entry point of this file. */ + +void +local_alloc () +{ + register int b, i; + int max_qty; + + /* Leaf functions and non-leaf functions have different needs. + If defined, let the machine say what kind of ordering we + should use. */ +#ifdef ORDER_REGS_FOR_LOCAL_ALLOC + ORDER_REGS_FOR_LOCAL_ALLOC; +#endif + + /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected + registers. */ + update_equiv_regs (); + + /* This sets the maximum number of quantities we can have. Quantity + numbers start at zero and we can have one for each pseudo plus the + number of SCRATCHes in the largest block, in the worst case. */ + max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch; + + /* Allocate vectors of temporary data. + See the declarations of these variables, above, + for what they mean. */ + + qty_phys_reg = (short *) alloca (max_qty * sizeof (short)); + qty_phys_copy_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET)); + qty_phys_has_copy_sugg = (char *) alloca (max_qty * sizeof (char)); + qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET)); + qty_phys_has_sugg = (char *) alloca (max_qty * sizeof (char)); + qty_birth = (int *) alloca (max_qty * sizeof (int)); + qty_death = (int *) alloca (max_qty * sizeof (int)); + qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx)); + qty_first_reg = (int *) alloca (max_qty * sizeof (int)); + qty_size = (int *) alloca (max_qty * sizeof (int)); + qty_mode = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode)); + qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int)); + qty_min_class = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class)); + qty_alternate_class = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class)); + qty_n_refs = (int *) alloca (max_qty * sizeof (int)); + + reg_qty = (int *) alloca (max_regno * sizeof (int)); + reg_offset = (char *) alloca (max_regno * sizeof (char)); + reg_next_in_qty = (int *) alloca (max_regno * sizeof (int)); + + reg_renumber = (short *) oballoc (max_regno * sizeof (short)); + for (i = 0; i < max_regno; i++) + reg_renumber[i] = -1; + + /* Determine which pseudo-registers can be allocated by local-alloc. + In general, these are the registers used only in a single block and + which only die once. However, if a register's preferred class has only + a few entries, don't allocate this register here unless it is preferred + or nothing since retry_global_alloc won't be able to move it to + GENERAL_REGS if a reload register of this class is needed. + + We need not be concerned with which block actually uses the register + since we will never see it outside that block. */ + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + { + if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1 + && (reg_alternate_class (i) == NO_REGS + || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i)))) + reg_qty[i] = -2; + else + reg_qty[i] = -1; + } + + /* Force loop below to initialize entire quantity array. */ + next_qty = max_qty; + + /* Allocate each block's local registers, block by block. */ + + for (b = 0; b < n_basic_blocks; b++) + { + /* NEXT_QTY indicates which elements of the `qty_...' + vectors might need to be initialized because they were used + for the previous block; it is set to the entire array before + block 0. Initialize those, with explicit loop if there are few, + else with bzero and bcopy. Do not initialize vectors that are + explicit set by `alloc_qty'. */ + + if (next_qty < 6) + { + for (i = 0; i < next_qty; i++) + { + qty_scratch_rtx[i] = 0; + CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); + qty_phys_has_copy_sugg[i] = 0; + CLEAR_HARD_REG_SET (qty_phys_sugg[i]); + qty_phys_has_sugg[i] = 0; + } + } + else + { +#define CLEAR(vector) \ + bzero ((vector), (sizeof (*(vector))) * next_qty); + + CLEAR (qty_scratch_rtx); + CLEAR (qty_phys_copy_sugg); + CLEAR (qty_phys_has_copy_sugg); + CLEAR (qty_phys_sugg); + CLEAR (qty_phys_has_sugg); + } + + next_qty = 0; + + block_alloc (b); +#ifdef USE_C_ALLOCA + alloca (0); +#endif + } +} + +/* Depth of loops we are in while in update_equiv_regs. */ +static int loop_depth; + +/* Used for communication between the following two functions: contains + a MEM that we wish to ensure remains unchanged. */ +static rtx equiv_mem; + +/* Set nonzero if EQUIV_MEM is modified. */ +static int equiv_mem_modified; + +/* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. + Called via note_stores. */ + +static void +validate_equiv_mem_from_store (dest, set) + rtx dest; + rtx set; +{ + if ((GET_CODE (dest) == REG + && reg_overlap_mentioned_p (dest, equiv_mem)) + || (GET_CODE (dest) == MEM + && true_dependence (dest, equiv_mem))) + equiv_mem_modified = 1; +} + +/* Verify that no store between START and the death of REG invalidates + MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, + by storing into an overlapping memory location, or with a non-const + CALL_INSN. + + Return 1 if MEMREF remains valid. */ + +static int +validate_equiv_mem (start, reg, memref) + rtx start; + rtx reg; + rtx memref; +{ + rtx insn; + rtx note; + + equiv_mem = memref; + equiv_mem_modified = 0; + + /* If the memory reference has side effects or is volatile, it isn't a + valid equivalence. */ + if (side_effects_p (memref)) + return 0; + + for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + continue; + + if (find_reg_note (insn, REG_DEAD, reg)) + return 1; + + if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref) + && ! CONST_CALL_P (insn)) + return 0; + + note_stores (PATTERN (insn), validate_equiv_mem_from_store); + + /* If a register mentioned in MEMREF is modified via an + auto-increment, we lose the equivalence. Do the same if one + dies; although we could extend the life, it doesn't seem worth + the trouble. */ + + for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) + if ((REG_NOTE_KIND (note) == REG_INC + || REG_NOTE_KIND (note) == REG_DEAD) + && GET_CODE (XEXP (note, 0)) == REG + && reg_overlap_mentioned_p (XEXP (note, 0), memref)) + return 0; + } + + return 0; +} + +/* TRUE if X references a memory location that would be affected by a store + to MEMREF. */ + +static int +memref_referenced_p (memref, x) + rtx x; + rtx memref; +{ + int i, j; + char *fmt; + enum rtx_code code = GET_CODE (x); + + switch (code) + { + case REG: + case CONST_INT: + case CONST: + case LABEL_REF: + case SYMBOL_REF: + case CONST_DOUBLE: + case PC: + case CC0: + case HIGH: + case LO_SUM: + return 0; + + case MEM: + if (true_dependence (memref, x)) + return 1; + break; + + case SET: + /* If we are setting a MEM, it doesn't count (its address does), but any + other SET_DEST that has a MEM in it is referencing the MEM. */ + if (GET_CODE (SET_DEST (x)) == MEM) + { + if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) + return 1; + } + else if (memref_referenced_p (memref, SET_DEST (x))) + return 1; + + return memref_referenced_p (memref, SET_SRC (x)); + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + switch (fmt[i]) + { + case 'e': + if (memref_referenced_p (memref, XEXP (x, i))) + return 1; + break; + case 'E': + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + if (memref_referenced_p (memref, XVECEXP (x, i, j))) + return 1; + break; + } + + return 0; +} + +/* TRUE if some insn in the range (START, END] references a memory location + that would be affected by a store to MEMREF. */ + +static int +memref_used_between_p (memref, start, end) + rtx memref; + rtx start; + rtx end; +{ + rtx insn; + + for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); + insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && memref_referenced_p (memref, PATTERN (insn))) + return 1; + + return 0; +} + +/* INSN is a copy from SRC to DEST, both registers, and SRC does not die + in INSN. + + Search forward to see if SRC dies before either it or DEST is modified, + but don't scan past the end of a basic block. If so, we can replace SRC + with DEST and let SRC die in INSN. + + This will reduce the number of registers live in that range and may enable + DEST to be tied to SRC, thus often saving one register in addition to a + register-register copy. */ + +static void +optimize_reg_copy_1 (insn, dest, src) + rtx insn; + rtx dest; + rtx src; +{ + rtx p, q; + rtx note; + rtx dest_death = 0; + int sregno = REGNO (src); + int dregno = REGNO (dest); + + if (sregno == dregno +#ifdef SMALL_REGISTER_CLASSES + /* We don't want to mess with hard regs if register classes are small. */ + || sregno < FIRST_PSEUDO_REGISTER || dregno < FIRST_PSEUDO_REGISTER +#endif + /* We don't see all updates to SP if they are in an auto-inc memory + reference, so we must disallow this optimization on them. */ + || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) + return; + + for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) + { + if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN + || (GET_CODE (p) == NOTE + && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG + || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) + break; + + if (GET_RTX_CLASS (GET_CODE (p)) != 'i') + continue; + + if (reg_set_p (src, p) || reg_set_p (dest, p) + /* Don't change a USE of a register. */ + || (GET_CODE (PATTERN (p)) == USE + && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) + break; + + /* See if all of SRC dies in P. This test is slightly more + conservative than it needs to be. */ + if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 + && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) + { + int failed = 0; + int length = 0; + int d_length = 0; + int n_calls = 0; + int d_n_calls = 0; + + /* We can do the optimization. Scan forward from INSN again, + replacing regs as we go. Set FAILED if a replacement can't + be done. In that case, we can't move the death note for SRC. + This should be rare. */ + + /* Set to stop at next insn. */ + for (q = next_real_insn (insn); + q != next_real_insn (p); + q = next_real_insn (q)) + { + if (reg_overlap_mentioned_p (src, PATTERN (q))) + { + /* If SRC is a hard register, we might miss some + overlapping registers with validate_replace_rtx, + so we would have to undo it. We can't if DEST is + present in the insn, so fail in that combination + of cases. */ + if (sregno < FIRST_PSEUDO_REGISTER + && reg_mentioned_p (dest, PATTERN (q))) + failed = 1; + + /* Replace all uses and make sure that the register + isn't still present. */ + else if (validate_replace_rtx (src, dest, q) + && (sregno >= FIRST_PSEUDO_REGISTER + || ! reg_overlap_mentioned_p (src, + PATTERN (q)))) + { + /* We assume that a register is used exactly once per + insn in the updates below. If this is not correct, + no great harm is done. */ + if (sregno >= FIRST_PSEUDO_REGISTER) + reg_n_refs[sregno] -= loop_depth; + if (dregno >= FIRST_PSEUDO_REGISTER) + reg_n_refs[dregno] += loop_depth; + } + else + { + validate_replace_rtx (dest, src, q); + failed = 1; + } + } + + /* Count the insns and CALL_INSNs passed. If we passed the + death note of DEST, show increased live length. */ + length++; + if (dest_death) + d_length++; + + if (GET_CODE (q) == CALL_INSN) + { + n_calls++; + if (dest_death) + d_n_calls++; + } + + /* If DEST dies here, remove the death note and save it for + later. Make sure ALL of DEST dies here; again, this is + overly conservative. */ + if (dest_death == 0 + && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0 + && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest)) + remove_note (q, dest_death); + } + + if (! failed) + { + if (sregno >= FIRST_PSEUDO_REGISTER) + { + reg_live_length[sregno] -= length; + reg_n_calls_crossed[sregno] -= n_calls; + } + + if (dregno >= FIRST_PSEUDO_REGISTER) + { + reg_live_length[dregno] += d_length; + reg_n_calls_crossed[dregno] += d_n_calls; + } + + /* Move death note of SRC from P to INSN. */ + remove_note (p, note); + XEXP (note, 1) = REG_NOTES (insn); + REG_NOTES (insn) = note; + } + + /* Put death note of DEST on P if we saw it die. */ + if (dest_death) + { + XEXP (dest_death, 1) = REG_NOTES (p); + REG_NOTES (p) = dest_death; + } + + return; + } + + /* If SRC is a hard register which is set or killed in some other + way, we can't do this optimization. */ + else if (sregno < FIRST_PSEUDO_REGISTER + && dead_or_set_p (p, src)) + break; + } +} + +/* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have + a sequence of insns that modify DEST followed by an insn that sets + SRC to DEST in which DEST dies, with no prior modification of DEST. + (There is no need to check if the insns in between actually modify + DEST. We should not have cases where DEST is not modified, but + the optimization is safe if no such modification is detected.) + In that case, we can replace all uses of DEST, starting with INSN and + ending with the set of SRC to DEST, with SRC. We do not do this + optimization if a CALL_INSN is crossed unless SRC already crosses a + call. + + It is assumed that DEST and SRC are pseudos; it is too complicated to do + this for hard registers since the substitutions we may make might fail. */ + +static void +optimize_reg_copy_2 (insn, dest, src) + rtx insn; + rtx dest; + rtx src; +{ + rtx p, q; + rtx set; + int sregno = REGNO (src); + int dregno = REGNO (dest); + + for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) + { + if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN + || (GET_CODE (p) == NOTE + && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG + || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) + break; + + if (GET_RTX_CLASS (GET_CODE (p)) != 'i') + continue; + + set = single_set (p); + if (set && SET_SRC (set) == dest && SET_DEST (set) == src + && find_reg_note (p, REG_DEAD, dest)) + { + /* We can do the optimization. Scan forward from INSN again, + replacing regs as we go. */ + + /* Set to stop at next insn. */ + for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) + if (GET_RTX_CLASS (GET_CODE (q)) == 'i') + { + if (reg_mentioned_p (dest, PATTERN (q))) + { + PATTERN (q) = replace_rtx (PATTERN (q), dest, src); + + /* We assume that a register is used exactly once per + insn in the updates below. If this is not correct, + no great harm is done. */ + reg_n_refs[dregno] -= loop_depth; + reg_n_refs[sregno] += loop_depth; + } + + + if (GET_CODE (q) == CALL_INSN) + { + reg_n_calls_crossed[dregno]--; + reg_n_calls_crossed[sregno]++; + } + } + + remove_note (p, find_reg_note (p, REG_DEAD, dest)); + reg_n_deaths[dregno]--; + remove_note (insn, find_reg_note (insn, REG_DEAD, src)); + reg_n_deaths[sregno]--; + return; + } + + if (reg_set_p (src, p) + || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0)) + break; + } +} + +/* Find registers that are equivalent to a single value throughout the + compilation (either because they can be referenced in memory or are set once + from a single constant). Lower their priority for a register. + + If such a register is only referenced once, try substituting its value + into the using insn. If it succeeds, we can eliminate the register + completely. */ + +static void +update_equiv_regs () +{ + rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *)); + rtx *reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *)); + rtx insn; + + bzero (reg_equiv_init_insn, max_regno * sizeof (rtx *)); + bzero (reg_equiv_replacement, max_regno * sizeof (rtx *)); + + init_alias_analysis (); + + loop_depth = 1; + + /* Scan the insns and find which registers have equivalences. Do this + in a separate scan of the insns because (due to -fcse-follow-jumps) + a register can be set below its use. */ + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + { + rtx note; + rtx set = single_set (insn); + rtx dest; + int regno; + + if (GET_CODE (insn) == NOTE) + { + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) + loop_depth++; + else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) + loop_depth--; + } + + /* If this insn contains more (or less) than a single SET, ignore it. */ + if (set == 0) + continue; + + dest = SET_DEST (set); + + /* If this sets a MEM to the contents of a REG that is only used + in a single basic block, see if the register is always equivalent + to that memory location and if moving the store from INSN to the + insn that set REG is safe. If so, put a REG_EQUIV note on the + initializing insn. */ + + if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG + && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER + && reg_basic_block[regno] >= 0 + && reg_equiv_init_insn[regno] != 0 + && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set), + dest) + && ! memref_used_between_p (SET_DEST (set), + reg_equiv_init_insn[regno], insn)) + REG_NOTES (reg_equiv_init_insn[regno]) + = gen_rtx (EXPR_LIST, REG_EQUIV, dest, + REG_NOTES (reg_equiv_init_insn[regno])); + + /* If this is a register-register copy where SRC is not dead, see if we + can optimize it. */ + if (flag_expensive_optimizations && GET_CODE (dest) == REG + && GET_CODE (SET_SRC (set)) == REG + && ! find_reg_note (insn, REG_DEAD, SET_SRC (set))) + optimize_reg_copy_1 (insn, dest, SET_SRC (set)); + + /* Similarly for a pseudo-pseudo copy when SRC is dead. */ + else if (flag_expensive_optimizations && GET_CODE (dest) == REG + && REGNO (dest) >= FIRST_PSEUDO_REGISTER + && GET_CODE (SET_SRC (set)) == REG + && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER + && find_reg_note (insn, REG_DEAD, SET_SRC (set))) + optimize_reg_copy_2 (insn, dest, SET_SRC (set)); + + /* Otherwise, we only handle the case of a pseudo register being set + once. */ + if (GET_CODE (dest) != REG + || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER + || reg_n_sets[regno] != 1) + continue; + + note = find_reg_note (insn, REG_EQUAL, NULL_RTX); + + /* Record this insn as initializing this register. */ + reg_equiv_init_insn[regno] = insn; + + /* If this register is known to be equal to a constant, record that + it is always equivalent to the constant. */ + if (note && CONSTANT_P (XEXP (note, 0))) + PUT_MODE (note, (enum machine_mode) REG_EQUIV); + + /* If this insn introduces a "constant" register, decrease the priority + of that register. Record this insn if the register is only used once + more and the equivalence value is the same as our source. + + The latter condition is checked for two reasons: First, it is an + indication that it may be more efficient to actually emit the insn + as written (if no registers are available, reload will substitute + the equivalence). Secondly, it avoids problems with any registers + dying in this insn whose death notes would be missed. + + If we don't have a REG_EQUIV note, see if this insn is loading + a register used only in one basic block from a MEM. If so, and the + MEM remains unchanged for the life of the register, add a REG_EQUIV + note. */ + + note = find_reg_note (insn, REG_EQUIV, NULL_RTX); + + if (note == 0 && reg_basic_block[regno] >= 0 + && GET_CODE (SET_SRC (set)) == MEM + && validate_equiv_mem (insn, dest, SET_SRC (set))) + REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set), + REG_NOTES (insn)); + + /* Don't mess with things live during setjmp. */ + if (note && reg_live_length[regno] >= 0) + { + int regno = REGNO (dest); + + /* Note that the statement below does not affect the priority + in local-alloc! */ + reg_live_length[regno] *= 2; + + /* If the register is referenced exactly twice, meaning it is set + once and used once, indicate that the reference may be replaced + by the equivalence we computed above. If the register is only + used in one basic block, this can't succeed or combine would + have done it. + + It would be nice to use "loop_depth * 2" in the compare + below. Unfortunately, LOOP_DEPTH need not be constant within + a basic block so this would be too complicated. + + This case normally occurs when a parameter is read from memory + and then used exactly once, not in a loop. */ + + if (reg_n_refs[regno] == 2 + && reg_basic_block[regno] < 0 + && rtx_equal_p (XEXP (note, 0), SET_SRC (set))) + reg_equiv_replacement[regno] = SET_SRC (set); + } + } + + /* Now scan all regs killed in an insn to see if any of them are registers + only used that once. If so, see if we can replace the reference with + the equivalent from. If we can, delete the initializing reference + and this register will go away. */ + for (insn = next_active_insn (get_insns ()); + insn; + insn = next_active_insn (insn)) + { + rtx link; + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_DEAD + /* Make sure this insn still refers to the register. */ + && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) + { + int regno = REGNO (XEXP (link, 0)); + + if (reg_equiv_replacement[regno] + && validate_replace_rtx (regno_reg_rtx[regno], + reg_equiv_replacement[regno], insn)) + { + rtx equiv_insn = reg_equiv_init_insn[regno]; + + remove_death (regno, insn); + reg_n_refs[regno] = 0; + PUT_CODE (equiv_insn, NOTE); + NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (equiv_insn) = 0; + } + } + } +} + +/* Allocate hard regs to the pseudo regs used only within block number B. + Only the pseudos that die but once can be handled. */ + +static void +block_alloc (b) + int b; +{ + register int i, q; + register rtx insn; + rtx note; + int insn_number = 0; + int insn_count = 0; + int max_uid = get_max_uid (); + int *qty_order; + int no_conflict_combined_regno = -1; + + /* Count the instructions in the basic block. */ + + insn = basic_block_end[b]; + while (1) + { + if (GET_CODE (insn) != NOTE) + if (++insn_count > max_uid) + abort (); + if (insn == basic_block_head[b]) + break; + insn = PREV_INSN (insn); + } + + /* +2 to leave room for a post_mark_life at the last insn and for + the birth of a CLOBBER in the first insn. */ + regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2) + * sizeof (HARD_REG_SET)); + bzero (regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET)); + + /* Initialize table of hardware registers currently live. */ + +#ifdef HARD_REG_SET + regs_live = *basic_block_live_at_start[b]; +#else + COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]); +#endif + + /* This loop scans the instructions of the basic block + and assigns quantities to registers. + It computes which registers to tie. */ + + insn = basic_block_head[b]; + while (1) + { + register rtx body = PATTERN (insn); + + if (GET_CODE (insn) != NOTE) + insn_number++; + + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + register rtx link, set; + register int win = 0; + register rtx r0, r1; + int combined_regno = -1; + int i; + int insn_code_number = recog_memoized (insn); + + this_insn_number = insn_number; + this_insn = insn; + + if (insn_code_number >= 0) + insn_extract (insn); + which_alternative = -1; + + /* Is this insn suitable for tying two registers? + If so, try doing that. + Suitable insns are those with at least two operands and where + operand 0 is an output that is a register that is not + earlyclobber. + + We can tie operand 0 with some operand that dies in this insn. + First look for operands that are required to be in the same + register as operand 0. If we find such, only try tying that + operand or one that can be put into that operand if the + operation is commutative. If we don't find an operand + that is required to be in the same register as operand 0, + we can tie with any operand. + + Subregs in place of regs are also ok. + + If tying is done, WIN is set nonzero. */ + + if (insn_code_number >= 0 +#ifdef REGISTER_CONSTRAINTS + && insn_n_operands[insn_code_number] > 1 + && insn_operand_constraint[insn_code_number][0][0] == '=' + && insn_operand_constraint[insn_code_number][0][1] != '&' +#else + && GET_CODE (PATTERN (insn)) == SET + && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0]) +#endif + ) + { +#ifdef REGISTER_CONSTRAINTS + int must_match_0 = -1; + + + for (i = 1; i < insn_n_operands[insn_code_number]; i++) + if (requires_inout_p + (insn_operand_constraint[insn_code_number][i])) + must_match_0 = i; +#endif + + r0 = recog_operand[0]; + for (i = 1; i < insn_n_operands[insn_code_number]; i++) + { +#ifdef REGISTER_CONSTRAINTS + /* Skip this operand if we found an operand that + must match operand 0 and this operand isn't it + and can't be made to be it by commutativity. */ + + if (must_match_0 >= 0 && i != must_match_0 + && ! (i == must_match_0 + 1 + && insn_operand_constraint[insn_code_number][i-1][0] == '%') + && ! (i == must_match_0 - 1 + && insn_operand_constraint[insn_code_number][i][0] == '%')) + continue; +#endif + + r1 = recog_operand[i]; + + /* If the operand is an address, find a register in it. + There may be more than one register, but we only try one + of them. */ + if ( +#ifdef REGISTER_CONSTRAINTS + insn_operand_constraint[insn_code_number][i][0] == 'p' +#else + insn_operand_address_p[insn_code_number][i] +#endif + ) + while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) + r1 = XEXP (r1, 0); + + if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG) + { + /* We have two priorities for hard register preferences. + If we have a move insn or an insn whose first input + can only be in the same register as the output, give + priority to an equivalence found from that insn. */ + int may_save_copy + = ((SET_DEST (body) == r0 && SET_SRC (body) == r1) +#ifdef REGISTER_CONSTRAINTS + || (r1 == recog_operand[i] && must_match_0 >= 0) +#endif + ); + + if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) + win = combine_regs (r1, r0, may_save_copy, + insn_number, insn, 0); + } + } + } + + /* Recognize an insn sequence with an ultimate result + which can safely overlap one of the inputs. + The sequence begins with a CLOBBER of its result, + and ends with an insn that copies the result to itself + and has a REG_EQUAL note for an equivalent formula. + That note indicates what the inputs are. + The result and the input can overlap if each insn in + the sequence either doesn't mention the input + or has a REG_NO_CONFLICT note to inhibit the conflict. + + We do the combining test at the CLOBBER so that the + destination register won't have had a quantity number + assigned, since that would prevent combining. */ + + if (GET_CODE (PATTERN (insn)) == CLOBBER + && (r0 = XEXP (PATTERN (insn), 0), + GET_CODE (r0) == REG) + && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0 + && XEXP (link, 0) != 0 + && GET_CODE (XEXP (link, 0)) == INSN + && (set = single_set (XEXP (link, 0))) != 0 + && SET_DEST (set) == r0 && SET_SRC (set) == r0 + && (note = find_reg_note (XEXP (link, 0), REG_EQUAL, + NULL_RTX)) != 0) + { + if (r1 = XEXP (note, 0), GET_CODE (r1) == REG + /* Check that we have such a sequence. */ + && no_conflict_p (insn, r0, r1)) + win = combine_regs (r1, r0, 1, insn_number, insn, 1); + else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e' + && (r1 = XEXP (XEXP (note, 0), 0), + GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) + && no_conflict_p (insn, r0, r1)) + win = combine_regs (r1, r0, 0, insn_number, insn, 1); + + /* Here we care if the operation to be computed is + commutative. */ + else if ((GET_CODE (XEXP (note, 0)) == EQ + || GET_CODE (XEXP (note, 0)) == NE + || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c') + && (r1 = XEXP (XEXP (note, 0), 1), + (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)) + && no_conflict_p (insn, r0, r1)) + win = combine_regs (r1, r0, 0, insn_number, insn, 1); + + /* If we did combine something, show the register number + in question so that we know to ignore its death. */ + if (win) + no_conflict_combined_regno = REGNO (r1); + } + + /* If registers were just tied, set COMBINED_REGNO + to the number of the register used in this insn + that was tied to the register set in this insn. + This register's qty should not be "killed". */ + + if (win) + { + while (GET_CODE (r1) == SUBREG) + r1 = SUBREG_REG (r1); + combined_regno = REGNO (r1); + } + + /* Mark the death of everything that dies in this instruction, + except for anything that was just combined. */ + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_DEAD + && GET_CODE (XEXP (link, 0)) == REG + && combined_regno != REGNO (XEXP (link, 0)) + && (no_conflict_combined_regno != REGNO (XEXP (link, 0)) + || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0)))) + wipe_dead_reg (XEXP (link, 0), 0); + + /* Allocate qty numbers for all registers local to this block + that are born (set) in this instruction. + A pseudo that already has a qty is not changed. */ + + note_stores (PATTERN (insn), reg_is_set); + + /* If anything is set in this insn and then unused, mark it as dying + after this insn, so it will conflict with our outputs. This + can't match with something that combined, and it doesn't matter + if it did. Do this after the calls to reg_is_set since these + die after, not during, the current insn. */ + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_UNUSED + && GET_CODE (XEXP (link, 0)) == REG) + wipe_dead_reg (XEXP (link, 0), 1); + +#ifndef SMALL_REGISTER_CLASSES + /* Allocate quantities for any SCRATCH operands of this insn. We + don't do this for machines with small register classes because + those machines can use registers explicitly mentioned in the + RTL as spill registers and our usage of hard registers + explicitly for SCRATCH operands will conflict. On those machines, + reload will allocate the SCRATCH. */ + + if (insn_code_number >= 0) + for (i = 0; i < insn_n_operands[insn_code_number]; i++) + if (GET_CODE (recog_operand[i]) == SCRATCH) + alloc_qty_for_scratch (recog_operand[i], i, insn, + insn_code_number, insn_number); +#endif + + /* If this is an insn that has a REG_RETVAL note pointing at a + CLOBBER insn, we have reached the end of a REG_NO_CONFLICT + block, so clear any register number that combined within it. */ + if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0 + && GET_CODE (XEXP (note, 0)) == INSN + && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER) + no_conflict_combined_regno = -1; + } + + /* Set the registers live after INSN_NUMBER. Note that we never + record the registers live before the block's first insn, since no + pseudos we care about are live before that insn. */ + + IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); + IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); + + if (insn == basic_block_end[b]) + break; + + insn = NEXT_INSN (insn); + } + + /* Now every register that is local to this basic block + should have been given a quantity, or else -1 meaning ignore it. + Every quantity should have a known birth and death. + + Order the qtys so we assign them registers in order of + decreasing length of life. Normally call qsort, but if we + have only a very small number of quantities, sort them ourselves. */ + + qty_order = (int *) alloca (next_qty * sizeof (int)); + for (i = 0; i < next_qty; i++) + qty_order[i] = i; + +#define EXCHANGE(I1, I2) \ + { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } + + switch (next_qty) + { + case 3: + /* Make qty_order[2] be the one to allocate last. */ + if (qty_compare (0, 1) > 0) + EXCHANGE (0, 1); + if (qty_compare (1, 2) > 0) + EXCHANGE (2, 1); + + /* ... Fall through ... */ + case 2: + /* Put the best one to allocate in qty_order[0]. */ + if (qty_compare (0, 1) > 0) + EXCHANGE (0, 1); + + /* ... Fall through ... */ + + case 1: + case 0: + /* Nothing to do here. */ + break; + + default: + qsort (qty_order, next_qty, sizeof (int), qty_compare_1); + } + + /* Try to put each quantity in a suggested physical register, if it has one. + This may cause registers to be allocated that otherwise wouldn't be, but + this seems acceptable in local allocation (unlike global allocation). */ + for (i = 0; i < next_qty; i++) + { + q = qty_order[i]; + if (qty_phys_has_sugg[q] || qty_phys_has_copy_sugg[q]) + qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q, + 0, 1, qty_birth[q], qty_death[q]); + else + qty_phys_reg[q] = -1; + } + + /* Now for each qty that is not a hardware register, + look for a hardware register to put it in. + First try the register class that is cheapest for this qty, + if there is more than one class. */ + + for (i = 0; i < next_qty; i++) + { + q = qty_order[i]; + if (qty_phys_reg[q] < 0) + { + if (N_REG_CLASSES > 1) + { + qty_phys_reg[q] = find_free_reg (qty_min_class[q], + qty_mode[q], q, 0, 0, + qty_birth[q], qty_death[q]); + if (qty_phys_reg[q] >= 0) + continue; + } + + if (qty_alternate_class[q] != NO_REGS) + qty_phys_reg[q] = find_free_reg (qty_alternate_class[q], + qty_mode[q], q, 0, 0, + qty_birth[q], qty_death[q]); + } + } + + /* Now propagate the register assignments + to the pseudo regs belonging to the qtys. */ + + for (q = 0; q < next_qty; q++) + if (qty_phys_reg[q] >= 0) + { + for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i]) + reg_renumber[i] = qty_phys_reg[q] + reg_offset[i]; + if (qty_scratch_rtx[q]) + { + PUT_CODE (qty_scratch_rtx[q], REG); + REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q]; + + for (i = HARD_REGNO_NREGS (qty_phys_reg[q], + GET_MODE (qty_scratch_rtx[q])) - 1; + i >= 0; i--) + regs_ever_live[qty_phys_reg[q] + i] = 1; + + /* Must clear the USED field, because it will have been set by + copy_rtx_if_shared, but the leaf_register code expects that + it is zero in all REG rtx. copy_rtx_if_shared does not set the + used bit for REGs, but does for SCRATCHes. */ + qty_scratch_rtx[q]->used = 0; + } + } +} + +/* Compare two quantities' priority for getting real registers. + We give shorter-lived quantities higher priority. + Quantities with more references are also preferred, as are quantities that + require multiple registers. This is the identical prioritization as + done by global-alloc. + + We used to give preference to registers with *longer* lives, but using + the same algorithm in both local- and global-alloc can speed up execution + of some programs by as much as a factor of three! */ + +static int +qty_compare (q1, q2) + int q1, q2; +{ + /* Note that the quotient will never be bigger than + the value of floor_log2 times the maximum number of + times a register can occur in one insn (surely less than 100). + Multiplying this by 10000 can't overflow. */ + register int pri1 + = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1]) + / ((qty_death[q1] - qty_birth[q1]) * qty_size[q1])) + * 10000); + register int pri2 + = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2]) + / ((qty_death[q2] - qty_birth[q2]) * qty_size[q2])) + * 10000); + return pri2 - pri1; +} + +static int +qty_compare_1 (q1, q2) + int *q1, *q2; +{ + register int tem; + + /* Note that the quotient will never be bigger than + the value of floor_log2 times the maximum number of + times a register can occur in one insn (surely less than 100). + Multiplying this by 10000 can't overflow. */ + register int pri1 + = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1]) + / ((qty_death[*q1] - qty_birth[*q1]) * qty_size[*q1])) + * 10000); + register int pri2 + = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2]) + / ((qty_death[*q2] - qty_birth[*q2]) * qty_size[*q2])) + * 10000); + + tem = pri2 - pri1; + if (tem != 0) return tem; + /* If qtys are equally good, sort by qty number, + so that the results of qsort leave nothing to chance. */ + return *q1 - *q2; +} + +/* Attempt to combine the two registers (rtx's) USEDREG and SETREG. + Returns 1 if have done so, or 0 if cannot. + + Combining registers means marking them as having the same quantity + and adjusting the offsets within the quantity if either of + them is a SUBREG). + + We don't actually combine a hard reg with a pseudo; instead + we just record the hard reg as the suggestion for the pseudo's quantity. + If we really combined them, we could lose if the pseudo lives + across an insn that clobbers the hard reg (eg, movstr). + + ALREADY_DEAD is non-zero if USEDREG is known to be dead even though + there is no REG_DEAD note on INSN. This occurs during the processing + of REG_NO_CONFLICT blocks. + + MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to + SETREG or if the input and output must share a register. + In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. + + There are elaborate checks for the validity of combining. */ + + +static int +combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead) + rtx usedreg, setreg; + int may_save_copy; + int insn_number; + rtx insn; + int already_dead; +{ + register int ureg, sreg; + register int offset = 0; + int usize, ssize; + register int sqty; + + /* Determine the numbers and sizes of registers being used. If a subreg + is present that does not change the entire register, don't consider + this a copy insn. */ + + while (GET_CODE (usedreg) == SUBREG) + { + if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD) + may_save_copy = 0; + offset += SUBREG_WORD (usedreg); + usedreg = SUBREG_REG (usedreg); + } + if (GET_CODE (usedreg) != REG) + return 0; + ureg = REGNO (usedreg); + usize = REG_SIZE (usedreg); + + while (GET_CODE (setreg) == SUBREG) + { + if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD) + may_save_copy = 0; + offset -= SUBREG_WORD (setreg); + setreg = SUBREG_REG (setreg); + } + if (GET_CODE (setreg) != REG) + return 0; + sreg = REGNO (setreg); + ssize = REG_SIZE (setreg); + + /* If UREG is a pseudo-register that hasn't already been assigned a + quantity number, it means that it is not local to this block or dies + more than once. In either event, we can't do anything with it. */ + if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) + /* Do not combine registers unless one fits within the other. */ + || (offset > 0 && usize + offset > ssize) + || (offset < 0 && usize + offset < ssize) + /* Do not combine with a smaller already-assigned object + if that smaller object is already combined with something bigger. */ + || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER + && usize < qty_size[reg_qty[ureg]]) + /* Can't combine if SREG is not a register we can allocate. */ + || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) + /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note. + These have already been taken care of. This probably wouldn't + combine anyway, but don't take any chances. */ + || (ureg >= FIRST_PSEUDO_REGISTER + && find_reg_note (insn, REG_NO_CONFLICT, usedreg)) + /* Don't tie something to itself. In most cases it would make no + difference, but it would screw up if the reg being tied to itself + also dies in this insn. */ + || ureg == sreg + /* Don't try to connect two different hardware registers. */ + || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) + /* Don't connect two different machine modes if they have different + implications as to which registers may be used. */ + || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) + return 0; + + /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in + qty_phys_sugg for the pseudo instead of tying them. + + Return "failure" so that the lifespan of UREG is terminated here; + that way the two lifespans will be disjoint and nothing will prevent + the pseudo reg from being given this hard reg. */ + + if (ureg < FIRST_PSEUDO_REGISTER) + { + /* Allocate a quantity number so we have a place to put our + suggestions. */ + if (reg_qty[sreg] == -2) + reg_is_born (setreg, 2 * insn_number); + + if (reg_qty[sreg] >= 0) + { + if (may_save_copy) + { + SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); + qty_phys_has_copy_sugg[reg_qty[sreg]] = 1; + } + else + { + SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); + qty_phys_has_sugg[reg_qty[sreg]] = 1; + } + } + return 0; + } + + /* Similarly for SREG a hard register and UREG a pseudo register. */ + + if (sreg < FIRST_PSEUDO_REGISTER) + { + if (may_save_copy) + { + SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); + qty_phys_has_copy_sugg[reg_qty[ureg]] = 1; + } + else + { + SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); + qty_phys_has_sugg[reg_qty[ureg]] = 1; + } + return 0; + } + + /* At this point we know that SREG and UREG are both pseudos. + Do nothing if SREG already has a quantity or is a register that we + don't allocate. */ + if (reg_qty[sreg] >= -1 + /* If we are not going to let any regs live across calls, + don't tie a call-crossing reg to a non-call-crossing reg. */ + || (current_function_has_nonlocal_label + && ((reg_n_calls_crossed[ureg] > 0) + != (reg_n_calls_crossed[sreg] > 0)))) + return 0; + + /* We don't already know about SREG, so tie it to UREG + if this is the last use of UREG, provided the classes they want + are compatible. */ + + if ((already_dead || find_regno_note (insn, REG_DEAD, ureg)) + && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]])) + { + /* Add SREG to UREG's quantity. */ + sqty = reg_qty[ureg]; + reg_qty[sreg] = sqty; + reg_offset[sreg] = reg_offset[ureg] + offset; + reg_next_in_qty[sreg] = qty_first_reg[sqty]; + qty_first_reg[sqty] = sreg; + + /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */ + update_qty_class (sqty, sreg); + + /* Update info about quantity SQTY. */ + qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg]; + qty_n_refs[sqty] += reg_n_refs[sreg]; + if (usize < ssize) + { + register int i; + + for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i]) + reg_offset[i] -= offset; + + qty_size[sqty] = ssize; + qty_mode[sqty] = GET_MODE (setreg); + } + } + else + return 0; + + return 1; +} + +/* Return 1 if the preferred class of REG allows it to be tied + to a quantity or register whose class is CLASS. + True if REG's reg class either contains or is contained in CLASS. */ + +static int +reg_meets_class_p (reg, class) + int reg; + enum reg_class class; +{ + register enum reg_class rclass = reg_preferred_class (reg); + return (reg_class_subset_p (rclass, class) + || reg_class_subset_p (class, rclass)); +} + +/* Return 1 if the two specified classes have registers in common. + If CALL_SAVED, then consider only call-saved registers. */ + +static int +reg_classes_overlap_p (c1, c2, call_saved) + register enum reg_class c1; + register enum reg_class c2; + int call_saved; +{ + HARD_REG_SET c; + int i; + + COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); + AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (TEST_HARD_REG_BIT (c, i) + && (! call_saved || ! call_used_regs[i])) + return 1; + + return 0; +} + +/* Update the class of QTY assuming that REG is being tied to it. */ + +static void +update_qty_class (qty, reg) + int qty; + int reg; +{ + enum reg_class rclass = reg_preferred_class (reg); + if (reg_class_subset_p (rclass, qty_min_class[qty])) + qty_min_class[qty] = rclass; + + rclass = reg_alternate_class (reg); + if (reg_class_subset_p (rclass, qty_alternate_class[qty])) + qty_alternate_class[qty] = rclass; +} + +/* Handle something which alters the value of an rtx REG. + + REG is whatever is set or clobbered. SETTER is the rtx that + is modifying the register. + + If it is not really a register, we do nothing. + The file-global variables `this_insn' and `this_insn_number' + carry info from `block_alloc'. */ + +static void +reg_is_set (reg, setter) + rtx reg; + rtx setter; +{ + /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of + a hard register. These may actually not exist any more. */ + + if (GET_CODE (reg) != SUBREG + && GET_CODE (reg) != REG) + return; + + /* Mark this register as being born. If it is used in a CLOBBER, mark + it as being born halfway between the previous insn and this insn so that + it conflicts with our inputs but not the outputs of the previous insn. */ + + reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); +} + +/* Handle beginning of the life of register REG. + BIRTH is the index at which this is happening. */ + +static void +reg_is_born (reg, birth) + rtx reg; + int birth; +{ + register int regno; + + if (GET_CODE (reg) == SUBREG) + regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg); + else + regno = REGNO (reg); + + if (regno < FIRST_PSEUDO_REGISTER) + { + mark_life (regno, GET_MODE (reg), 1); + + /* If the register was to have been born earlier that the present + insn, mark it as live where it is actually born. */ + if (birth < 2 * this_insn_number) + post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); + } + else + { + if (reg_qty[regno] == -2) + alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); + + /* If this register has a quantity number, show that it isn't dead. */ + if (reg_qty[regno] >= 0) + qty_death[reg_qty[regno]] = -1; + } +} + +/* Record the death of REG in the current insn. If OUTPUT_P is non-zero, + REG is an output that is dying (i.e., it is never used), otherwise it + is an input (the normal case). + If OUTPUT_P is 1, then we extend the life past the end of this insn. */ + +static void +wipe_dead_reg (reg, output_p) + register rtx reg; + int output_p; +{ + register int regno = REGNO (reg); + + /* If this insn has multiple results, + and the dead reg is used in one of the results, + extend its life to after this insn, + so it won't get allocated together with any other result of this insn. */ + if (GET_CODE (PATTERN (this_insn)) == PARALLEL + && !single_set (this_insn)) + { + int i; + for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) + { + rtx set = XVECEXP (PATTERN (this_insn), 0, i); + if (GET_CODE (set) == SET + && GET_CODE (SET_DEST (set)) != REG + && !rtx_equal_p (reg, SET_DEST (set)) + && reg_overlap_mentioned_p (reg, SET_DEST (set))) + output_p = 1; + } + } + + if (regno < FIRST_PSEUDO_REGISTER) + { + mark_life (regno, GET_MODE (reg), 0); + + /* If a hard register is dying as an output, mark it as in use at + the beginning of this insn (the above statement would cause this + not to happen). */ + if (output_p) + post_mark_life (regno, GET_MODE (reg), 1, + 2 * this_insn_number, 2 * this_insn_number+ 1); + } + + else if (reg_qty[regno] >= 0) + qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p; +} + +/* Find a block of SIZE words of hard regs in reg_class CLASS + that can hold something of machine-mode MODE + (but actually we test only the first of the block for holding MODE) + and still free between insn BORN_INDEX and insn DEAD_INDEX, + and return the number of the first of them. + Return -1 if such a block cannot be found. + If QTY crosses calls, insist on a register preserved by calls, + unless ACCEPT_CALL_CLOBBERED is nonzero. + + If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested + register is available. If not, return -1. */ + +static int +find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested, + born_index, dead_index) + enum reg_class class; + enum machine_mode mode; + int accept_call_clobbered; + int just_try_suggested; + int qty; + int born_index, dead_index; +{ + register int i, ins; +#ifdef HARD_REG_SET + register /* Declare it register if it's a scalar. */ +#endif + HARD_REG_SET used, first_used; +#ifdef ELIMINABLE_REGS + static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; +#endif + + /* Validate our parameters. */ + if (born_index < 0 || born_index > dead_index) + abort (); + + /* Don't let a pseudo live in a reg across a function call + if we might get a nonlocal goto. */ + if (current_function_has_nonlocal_label + && qty_n_calls_crossed[qty] > 0) + return -1; + + if (accept_call_clobbered) + COPY_HARD_REG_SET (used, call_fixed_reg_set); + else if (qty_n_calls_crossed[qty] == 0) + COPY_HARD_REG_SET (used, fixed_reg_set); + else + COPY_HARD_REG_SET (used, call_used_reg_set); + + for (ins = born_index; ins < dead_index; ins++) + IOR_HARD_REG_SET (used, regs_live_at[ins]); + + IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); + + /* Don't use the frame pointer reg in local-alloc even if + we may omit the frame pointer, because if we do that and then we + need a frame pointer, reload won't know how to move the pseudo + to another hard reg. It can move only regs made by global-alloc. + + This is true of any register that can be eliminated. */ +#ifdef ELIMINABLE_REGS + for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++) + SET_HARD_REG_BIT (used, eliminables[i].from); +#else + SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); +#endif + + /* Normally, the registers that can be used for the first register in + a multi-register quantity are the same as those that can be used for + subsequent registers. However, if just trying suggested registers, + restrict our consideration to them. If there are copy-suggested + register, try them. Otherwise, try the arithmetic-suggested + registers. */ + COPY_HARD_REG_SET (first_used, used); + + if (just_try_suggested) + { + if (qty_phys_has_copy_sugg[qty]) + IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]); + else + IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]); + } + + /* If all registers are excluded, we can't do anything. */ + GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail); + + /* If at least one would be suitable, test each hard reg. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { +#ifdef REG_ALLOC_ORDER + int regno = reg_alloc_order[i]; +#else + int regno = i; +#endif + if (! TEST_HARD_REG_BIT (first_used, regno) + && HARD_REGNO_MODE_OK (regno, mode)) + { + register int j; + register int size1 = HARD_REGNO_NREGS (regno, mode); + for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); + if (j == size1) + { + /* Mark that this register is in use between its birth and death + insns. */ + post_mark_life (regno, mode, 1, born_index, dead_index); + return regno; + } +#ifndef REG_ALLOC_ORDER + i += j; /* Skip starting points we know will lose */ +#endif + } + } + + fail: + + /* If we are just trying suggested register, we have just tried copy- + suggested registers, and there are arithmetic-suggested registers, + try them. */ + + /* If it would be profitable to allocate a call-clobbered register + and save and restore it around calls, do that. */ + if (just_try_suggested && qty_phys_has_copy_sugg[qty] + && qty_phys_has_sugg[qty]) + { + /* Don't try the copy-suggested regs again. */ + qty_phys_has_copy_sugg[qty] = 0; + return find_free_reg (class, mode, qty, accept_call_clobbered, 1, + born_index, dead_index); + } + + /* We need not check to see if the current function has nonlocal + labels because we don't put any pseudos that are live over calls in + registers in that case. */ + + if (! accept_call_clobbered + && flag_caller_saves + && ! just_try_suggested + && qty_n_calls_crossed[qty] != 0 + && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty])) + { + i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index); + if (i >= 0) + caller_save_needed = 1; + return i; + } + return -1; +} + +/* Mark that REGNO with machine-mode MODE is live starting from the current + insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE + is zero). */ + +static void +mark_life (regno, mode, life) + register int regno; + enum machine_mode mode; + int life; +{ + register int j = HARD_REGNO_NREGS (regno, mode); + if (life) + while (--j >= 0) + SET_HARD_REG_BIT (regs_live, regno + j); + else + while (--j >= 0) + CLEAR_HARD_REG_BIT (regs_live, regno + j); +} + +/* Mark register number REGNO (with machine-mode MODE) as live (if LIFE + is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) + to insn number DEATH (exclusive). */ + +static void +post_mark_life (regno, mode, life, birth, death) + register int regno, life, birth; + enum machine_mode mode; + int death; +{ + register int j = HARD_REGNO_NREGS (regno, mode); +#ifdef HARD_REG_SET + register /* Declare it register if it's a scalar. */ +#endif + HARD_REG_SET this_reg; + + CLEAR_HARD_REG_SET (this_reg); + while (--j >= 0) + SET_HARD_REG_BIT (this_reg, regno + j); + + if (life) + while (birth < death) + { + IOR_HARD_REG_SET (regs_live_at[birth], this_reg); + birth++; + } + else + while (birth < death) + { + AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); + birth++; + } +} + +/* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0 + is the register being clobbered, and R1 is a register being used in + the equivalent expression. + + If R1 dies in the block and has a REG_NO_CONFLICT note on every insn + in which it is used, return 1. + + Otherwise, return 0. */ + +static int +no_conflict_p (insn, r0, r1) + rtx insn, r0, r1; +{ + int ok = 0; + rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); + rtx p, last; + + /* If R1 is a hard register, return 0 since we handle this case + when we scan the insns that actually use it. */ + + if (note == 0 + || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER) + || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG + && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER)) + return 0; + + last = XEXP (note, 0); + + for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p)) + if (GET_RTX_CLASS (GET_CODE (p)) == 'i') + { + if (find_reg_note (p, REG_DEAD, r1)) + ok = 1; + + if (reg_mentioned_p (r1, PATTERN (p)) + && ! find_reg_note (p, REG_NO_CONFLICT, r1)) + return 0; + } + + return ok; +} + +#ifdef REGISTER_CONSTRAINTS + +/* Return 1 if the constraint string P indicates that the a the operand + must be equal to operand 0 and that no register is acceptable. */ + +static int +requires_inout_p (p) + char *p; +{ + char c; + int found_zero = 0; + + while (c = *p++) + switch (c) + { + case '0': + found_zero = 1; + break; + + case '=': case '+': case '?': + case '#': case '&': case '!': + case '*': case '%': case ',': + case '1': case '2': case '3': case '4': + case 'm': case '<': case '>': case 'V': case 'o': + case 'E': case 'F': case 'G': case 'H': + case 's': case 'i': case 'n': + case 'I': case 'J': case 'K': case 'L': + case 'M': case 'N': case 'O': case 'P': +#ifdef EXTRA_CONSTRAINT + case 'Q': case 'R': case 'S': case 'T': case 'U': +#endif + case 'X': + /* These don't say anything we care about. */ + break; + + case 'p': + case 'g': case 'r': + default: + /* These mean a register is allowed. Fail if so. */ + return 0; + } + + return found_zero; +} +#endif /* REGISTER_CONSTRAINTS */ + +void +dump_local_alloc (file) + FILE *file; +{ + register int i; + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (reg_renumber[i] != -1) + fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); +} diff --git a/gnu/usr.bin/cc/lib/longlong.h b/gnu/usr.bin/cc/lib/longlong.h new file mode 100644 index 000000000000..c594a1feb569 --- /dev/null +++ b/gnu/usr.bin/cc/lib/longlong.h @@ -0,0 +1,1004 @@ +/* longlong.h -- definitions for mixed size 32/64 bit arithmetic. + Copyright (C) 1991, 1992 Free Software Foundation, Inc. + + This definition file is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public + License as published by the Free Software Foundation; either + version 2, or (at your option) any later version. + + This definition file is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef SI_TYPE_SIZE +#define SI_TYPE_SIZE 32 +#endif + +#define __BITS4 (SI_TYPE_SIZE / 4) +#define __ll_B (1L << (SI_TYPE_SIZE / 2)) +#define __ll_lowpart(t) ((USItype) (t) % __ll_B) +#define __ll_highpart(t) ((USItype) (t) / __ll_B) + +/* Define auxiliary asm macros. + + 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) + multiplies two USItype integers MULTIPLER and MULTIPLICAND, + and generates a two-part USItype product in HIGH_PROD and + LOW_PROD. + + 2) __umulsidi3(a,b) multiplies two USItype integers A and B, + and returns a UDItype product. This is just a variant of umul_ppmm. + + 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, + denominator) divides a two-word unsigned integer, composed by the + integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and + places the quotient in QUOTIENT and the remainder in REMAINDER. + HIGH_NUMERATOR must be less than DENOMINATOR for correct operation. + If, in addition, the most significant bit of DENOMINATOR must be 1, + then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1. + + 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator, + denominator). Like udiv_qrnnd but the numbers are signed. The + quotient is rounded towards 0. + + 5) count_leading_zeros(count, x) counts the number of zero-bits from + the msb to the first non-zero bit. This is the number of steps X + needs to be shifted left to set the msb. Undefined for X == 0. + + 6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1, + high_addend_2, low_addend_2) adds two two-word unsigned integers, + composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and + LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and + LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is + lost. + + 7) sub_ddmmss(high_difference, low_difference, high_minuend, + low_minuend, high_subtrahend, low_subtrahend) subtracts two + two-word unsigned integers, composed by HIGH_MINUEND_1 and + LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2 + respectively. The result is placed in HIGH_DIFFERENCE and + LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere, + and is lost. + + If any of these macros are left undefined for a particular CPU, + C macros are used. */ + +/* The CPUs come in alphabetical order below. + + Please add support for more CPUs here, or improve the current support + for the CPUs below! + (E.g. WE32100, i960, IBM360.) */ + +#if defined (__GNUC__) && !defined (NO_ASM) + +/* We sometimes need to clobber "cc" with gcc2, but that would not be + understood by gcc1. Use cpp to avoid major code duplication. */ +#if __GNUC__ < 2 +#define __CLOBBER_CC +#define __AND_CLOBBER_CC +#else /* __GNUC__ >= 2 */ +#define __CLOBBER_CC : "cc" +#define __AND_CLOBBER_CC , "cc" +#endif /* __GNUC__ < 2 */ + +#if defined (__a29k__) || defined (___AM29K__) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("add %1,%4,%5 + addc %0,%2,%3" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "%r" ((USItype)(ah)), \ + "rI" ((USItype)(bh)), \ + "%r" ((USItype)(al)), \ + "rI" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("sub %1,%4,%5 + subc %0,%2,%3" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "r" ((USItype)(ah)), \ + "rI" ((USItype)(bh)), \ + "r" ((USItype)(al)), \ + "rI" ((USItype)(bl))) +#define umul_ppmm(xh, xl, m0, m1) \ + do { \ + USItype __m0 = (m0), __m1 = (m1); \ + __asm__ ("multiplu %0,%1,%2" \ + : "=r" ((USItype)(xl)) \ + : "r" (__m0), \ + "r" (__m1)); \ + __asm__ ("multmu %0,%1,%2" \ + : "=r" ((USItype)(xh)) \ + : "r" (__m0), \ + "r" (__m1)); \ + } while (0) +#define udiv_qrnnd(q, r, n1, n0, d) \ + __asm__ ("dividu %0,%3,%4" \ + : "=r" ((USItype)(q)), \ + "=q" ((USItype)(r)) \ + : "1" ((USItype)(n1)), \ + "r" ((USItype)(n0)), \ + "r" ((USItype)(d))) +#define count_leading_zeros(count, x) \ + __asm__ ("clz %0,%1" \ + : "=r" ((USItype)(count)) \ + : "r" ((USItype)(x))) +#endif /* __a29k__ */ + +#if defined (__arm__) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("adds %1,%4,%5 + adc %0,%2,%3" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "%r" ((USItype)(ah)), \ + "rI" ((USItype)(bh)), \ + "%r" ((USItype)(al)), \ + "rI" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("subs %1,%4,%5 + sbc %0,%2,%3" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "r" ((USItype)(ah)), \ + "rI" ((USItype)(bh)), \ + "r" ((USItype)(al)), \ + "rI" ((USItype)(bl))) +#endif /* __arm__ */ + +#if defined (__gmicro__) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("add.w %5,%1 + addx %3,%0" \ + : "=g" ((USItype)(sh)), \ + "=&g" ((USItype)(sl)) \ + : "%0" ((USItype)(ah)), \ + "g" ((USItype)(bh)), \ + "%1" ((USItype)(al)), \ + "g" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("sub.w %5,%1 + subx %3,%0" \ + : "=g" ((USItype)(sh)), \ + "=&g" ((USItype)(sl)) \ + : "0" ((USItype)(ah)), \ + "g" ((USItype)(bh)), \ + "1" ((USItype)(al)), \ + "g" ((USItype)(bl))) +#define umul_ppmm(ph, pl, m0, m1) \ + __asm__ ("mulx %3,%0,%1" \ + : "=g" ((USItype)(ph)), \ + "=r" ((USItype)(pl)) \ + : "%0" ((USItype)(m0)), \ + "g" ((USItype)(m1))) +#define udiv_qrnnd(q, r, nh, nl, d) \ + __asm__ ("divx %4,%0,%1" \ + : "=g" ((USItype)(q)), \ + "=r" ((USItype)(r)) \ + : "1" ((USItype)(nh)), \ + "0" ((USItype)(nl)), \ + "g" ((USItype)(d))) +#define count_leading_zeros(count, x) \ + __asm__ ("bsch/1 %1,%0" \ + : "=g" (count) \ + : "g" ((USItype)(x)), \ + "0" ((USItype)0)) +#endif + +#if defined (__hppa) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("add %4,%5,%1 + addc %2,%3,%0" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "%rM" ((USItype)(ah)), \ + "rM" ((USItype)(bh)), \ + "%rM" ((USItype)(al)), \ + "rM" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("sub %4,%5,%1 + subb %2,%3,%0" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "rM" ((USItype)(ah)), \ + "rM" ((USItype)(bh)), \ + "rM" ((USItype)(al)), \ + "rM" ((USItype)(bl))) +#if defined (_PA_RISC1_1) +#define umul_ppmm(w1, w0, u, v) \ + do { \ + union \ + { \ + UDItype __f; \ + struct {USItype __w1, __w0;} __w1w0; \ + } __t; \ + __asm__ ("xmpyu %1,%2,%0" \ + : "=x" (__t.__f) \ + : "x" ((USItype)(u)), \ + "x" ((USItype)(v))); \ + (w1) = __t.__w1w0.__w1; \ + (w0) = __t.__w1w0.__w0; \ + } while (0) +#define UMUL_TIME 8 +#else +#define UMUL_TIME 30 +#endif +#define UDIV_TIME 40 +#endif + +#if defined (__i386__) || defined (__i486__) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("addl %5,%1 + adcl %3,%0" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "%0" ((USItype)(ah)), \ + "g" ((USItype)(bh)), \ + "%1" ((USItype)(al)), \ + "g" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("subl %5,%1 + sbbl %3,%0" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "0" ((USItype)(ah)), \ + "g" ((USItype)(bh)), \ + "1" ((USItype)(al)), \ + "g" ((USItype)(bl))) +#define umul_ppmm(w1, w0, u, v) \ + __asm__ ("mull %3" \ + : "=a" ((USItype)(w0)), \ + "=d" ((USItype)(w1)) \ + : "%0" ((USItype)(u)), \ + "rm" ((USItype)(v))) +#define udiv_qrnnd(q, r, n1, n0, d) \ + __asm__ ("divl %4" \ + : "=a" ((USItype)(q)), \ + "=d" ((USItype)(r)) \ + : "0" ((USItype)(n0)), \ + "1" ((USItype)(n1)), \ + "rm" ((USItype)(d))) +#define count_leading_zeros(count, x) \ + do { \ + USItype __cbtmp; \ + __asm__ ("bsrl %1,%0" \ + : "=r" (__cbtmp) : "rm" ((USItype)(x))); \ + (count) = __cbtmp ^ 31; \ + } while (0) +#define UMUL_TIME 40 +#define UDIV_TIME 40 +#endif /* 80x86 */ + +#if defined (__i860__) +#if 0 +/* Make sure these patterns really improve the code before + switching them on. */ +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + do { \ + union \ + { \ + DItype __ll; \ + struct {USItype __l, __h;} __i; \ + } __a, __b, __s; \ + __a.__i.__l = (al); \ + __a.__i.__h = (ah); \ + __b.__i.__l = (bl); \ + __b.__i.__h = (bh); \ + __asm__ ("fiadd.dd %1,%2,%0" \ + : "=f" (__s.__ll) \ + : "%f" (__a.__ll), "f" (__b.__ll)); \ + (sh) = __s.__i.__h; \ + (sl) = __s.__i.__l; \ + } while (0) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + do { \ + union \ + { \ + DItype __ll; \ + struct {USItype __l, __h;} __i; \ + } __a, __b, __s; \ + __a.__i.__l = (al); \ + __a.__i.__h = (ah); \ + __b.__i.__l = (bl); \ + __b.__i.__h = (bh); \ + __asm__ ("fisub.dd %1,%2,%0" \ + : "=f" (__s.__ll) \ + : "%f" (__a.__ll), "f" (__b.__ll)); \ + (sh) = __s.__i.__h; \ + (sl) = __s.__i.__l; \ + } while (0) +#endif +#endif /* __i860__ */ + +#if defined (___IBMR2__) /* IBM RS6000 */ +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("a%I5 %1,%4,%5 + ae %0,%2,%3" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "%r" ((USItype)(ah)), \ + "r" ((USItype)(bh)), \ + "%r" ((USItype)(al)), \ + "rI" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("sf%I4 %1,%5,%4 + sfe %0,%3,%2" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "r" ((USItype)(ah)), \ + "r" ((USItype)(bh)), \ + "rI" ((USItype)(al)), \ + "r" ((USItype)(bl))) +#define umul_ppmm(xh, xl, m0, m1) \ + do { \ + USItype __m0 = (m0), __m1 = (m1); \ + __asm__ ("mul %0,%2,%3" \ + : "=r" ((USItype)(xh)), \ + "=q" ((USItype)(xl)) \ + : "r" (__m0), \ + "r" (__m1)); \ + (xh) += ((((SItype) __m0 >> 31) & __m1) \ + + (((SItype) __m1 >> 31) & __m0)); \ + } while (0) +#define smul_ppmm(xh, xl, m0, m1) \ + __asm__ ("mul %0,%2,%3" \ + : "=r" ((USItype)(xh)), \ + "=q" ((USItype)(xl)) \ + : "r" ((USItype)(m0)), \ + "r" ((USItype)(m1))) +#define UMUL_TIME 8 +#define sdiv_qrnnd(q, r, nh, nl, d) \ + __asm__ ("div %0,%2,%4" \ + : "=r" ((USItype)(q)), "=q" ((USItype)(r)) \ + : "r" ((USItype)(nh)), "1" ((USItype)(nl)), "r" ((USItype)(d))) +#define UDIV_TIME 40 +#define UDIV_NEEDS_NORMALIZATION 1 +#define count_leading_zeros(count, x) \ + __asm__ ("cntlz %0,%1" \ + : "=r" ((USItype)(count)) \ + : "r" ((USItype)(x))) +#endif /* ___IBMR2__ */ + +#if defined (__mc68000__) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("add%.l %5,%1 + addx%.l %3,%0" \ + : "=d" ((USItype)(sh)), \ + "=&d" ((USItype)(sl)) \ + : "%0" ((USItype)(ah)), \ + "d" ((USItype)(bh)), \ + "%1" ((USItype)(al)), \ + "g" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("sub%.l %5,%1 + subx%.l %3,%0" \ + : "=d" ((USItype)(sh)), \ + "=&d" ((USItype)(sl)) \ + : "0" ((USItype)(ah)), \ + "d" ((USItype)(bh)), \ + "1" ((USItype)(al)), \ + "g" ((USItype)(bl))) +#if defined (__mc68020__) || defined (__NeXT__) || defined(mc68020) +#define umul_ppmm(w1, w0, u, v) \ + __asm__ ("mulu%.l %3,%1:%0" \ + : "=d" ((USItype)(w0)), \ + "=d" ((USItype)(w1)) \ + : "%0" ((USItype)(u)), \ + "dmi" ((USItype)(v))) +#define UMUL_TIME 45 +#define udiv_qrnnd(q, r, n1, n0, d) \ + __asm__ ("divu%.l %4,%1:%0" \ + : "=d" ((USItype)(q)), \ + "=d" ((USItype)(r)) \ + : "0" ((USItype)(n0)), \ + "1" ((USItype)(n1)), \ + "dmi" ((USItype)(d))) +#define UDIV_TIME 90 +#define sdiv_qrnnd(q, r, n1, n0, d) \ + __asm__ ("divs%.l %4,%1:%0" \ + : "=d" ((USItype)(q)), \ + "=d" ((USItype)(r)) \ + : "0" ((USItype)(n0)), \ + "1" ((USItype)(n1)), \ + "dmi" ((USItype)(d))) +#define count_leading_zeros(count, x) \ + __asm__ ("bfffo %1{%b2:%b2},%0" \ + : "=d" ((USItype)(count)) \ + : "od" ((USItype)(x)), "n" (0)) +#else /* not mc68020 */ +/* %/ inserts REGISTER_PREFIX. */ +#define umul_ppmm(xh, xl, a, b) \ + __asm__ ("| Inlined umul_ppmm + movel %2,%/d0 + movel %3,%/d1 + movel %/d0,%/d2 + swap %/d0 + movel %/d1,%/d3 + swap %/d1 + movew %/d2,%/d4 + mulu %/d3,%/d4 + mulu %/d1,%/d2 + mulu %/d0,%/d3 + mulu %/d0,%/d1 + movel %/d4,%/d0 + eorw %/d0,%/d0 + swap %/d0 + addl %/d0,%/d2 + addl %/d3,%/d2 + jcc 1f + addl #65536,%/d1 +1: swap %/d2 + moveq #0,%/d0 + movew %/d2,%/d0 + movew %/d4,%/d2 + movel %/d2,%1 + addl %/d1,%/d0 + movel %/d0,%0" \ + : "=g" ((USItype)(xh)), \ + "=g" ((USItype)(xl)) \ + : "g" ((USItype)(a)), \ + "g" ((USItype)(b)) \ + : "d0", "d1", "d2", "d3", "d4") +#define UMUL_TIME 100 +#define UDIV_TIME 400 +#endif /* not mc68020 */ +#endif /* mc68000 */ + +#if defined (__m88000__) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("addu.co %1,%r4,%r5 + addu.ci %0,%r2,%r3" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "%rJ" ((USItype)(ah)), \ + "rJ" ((USItype)(bh)), \ + "%rJ" ((USItype)(al)), \ + "rJ" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("subu.co %1,%r4,%r5 + subu.ci %0,%r2,%r3" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "rJ" ((USItype)(ah)), \ + "rJ" ((USItype)(bh)), \ + "rJ" ((USItype)(al)), \ + "rJ" ((USItype)(bl))) +#define UMUL_TIME 17 +#define UDIV_TIME 150 +#define count_leading_zeros(count, x) \ + do { \ + USItype __cbtmp; \ + __asm__ ("ff1 %0,%1" \ + : "=r" (__cbtmp) \ + : "r" ((USItype)(x))); \ + (count) = __cbtmp ^ 31; \ + } while (0) +#if defined (__mc88110__) +#define umul_ppmm(w1, w0, u, v) \ + __asm__ ("mulu.d r10,%2,%3 + or %0,r10,0 + or %1,r11,0" \ + : "=r" (w1), \ + "=r" (w0) \ + : "r" ((USItype)(u)), \ + "r" ((USItype)(v)) \ + : "r10", "r11") +#define udiv_qrnnd(q, r, n1, n0, d) \ + __asm__ ("or r10,%2,0 + or r11,%3,0 + divu.d r10,r10,%4 + mulu %1,%4,r11 + subu %1,%3,%1 + or %0,r11,0" \ + : "=r" (q), \ + "=&r" (r) \ + : "r" ((USItype)(n1)), \ + "r" ((USItype)(n0)), \ + "r" ((USItype)(d)) \ + : "r10", "r11") +#endif +#endif /* __m88000__ */ + +#if defined (__mips__) +#define umul_ppmm(w1, w0, u, v) \ + __asm__ ("multu %2,%3 + mflo %0 + mfhi %1" \ + : "=d" ((USItype)(w0)), \ + "=d" ((USItype)(w1)) \ + : "d" ((USItype)(u)), \ + "d" ((USItype)(v))) +#define UMUL_TIME 5 +#define UDIV_TIME 100 +#endif /* __mips__ */ + +#if defined (__ns32000__) +#define __umulsidi3(u, v) \ + ({UDItype __w; \ + __asm__ ("meid %2,%0" \ + : "=g" (__w) \ + : "%0" ((USItype)(u)), \ + "g" ((USItype)(v))); \ + __w; }) +#define div_qrnnd(q, r, n1, n0, d) \ + __asm__ ("movd %2,r0 + movd %3,r1 + deid %4,r0 + movd r1,%0 + movd r0,%1" \ + : "=g" ((USItype)(q)), \ + "=g" ((USItype)(r)) \ + : "g" ((USItype)(n0)), \ + "g" ((USItype)(n1)), \ + "g" ((USItype)(d)) \ + : "r0", "r1") +#endif /* __ns32000__ */ + +#if defined (__pyr__) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("addw %5,%1 + addwc %3,%0" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "%0" ((USItype)(ah)), \ + "g" ((USItype)(bh)), \ + "%1" ((USItype)(al)), \ + "g" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("subw %5,%1 + subwb %3,%0" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "0" ((USItype)(ah)), \ + "g" ((USItype)(bh)), \ + "1" ((USItype)(al)), \ + "g" ((USItype)(bl))) +/* This insn doesn't work on ancient pyramids. */ +#define umul_ppmm(w1, w0, u, v) \ + ({union { \ + UDItype __ll; \ + struct {USItype __h, __l;} __i; \ + } __xx; \ + __xx.__i.__l = u; \ + __asm__ ("uemul %3,%0" \ + : "=r" (__xx.__i.__h), \ + "=r" (__xx.__i.__l) \ + : "1" (__xx.__i.__l), \ + "g" ((UDItype)(v))); \ + (w1) = __xx.__i.__h; \ + (w0) = __xx.__i.__l;}) +#endif /* __pyr__ */ + +#if defined (__ibm032__) /* RT/ROMP */ +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("a %1,%5 + ae %0,%3" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "%0" ((USItype)(ah)), \ + "r" ((USItype)(bh)), \ + "%1" ((USItype)(al)), \ + "r" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("s %1,%5 + se %0,%3" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "0" ((USItype)(ah)), \ + "r" ((USItype)(bh)), \ + "1" ((USItype)(al)), \ + "r" ((USItype)(bl))) +#define umul_ppmm(ph, pl, m0, m1) \ + do { \ + USItype __m0 = (m0), __m1 = (m1); \ + __asm__ ( \ + "s r2,r2 + mts r10,%2 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + m r2,%3 + cas %0,r2,r0 + mfs r10,%1" \ + : "=r" ((USItype)(ph)), \ + "=r" ((USItype)(pl)) \ + : "%r" (__m0), \ + "r" (__m1) \ + : "r2"); \ + (ph) += ((((SItype) __m0 >> 31) & __m1) \ + + (((SItype) __m1 >> 31) & __m0)); \ + } while (0) +#define UMUL_TIME 20 +#define UDIV_TIME 200 +#define count_leading_zeros(count, x) \ + do { \ + if ((x) >= 0x10000) \ + __asm__ ("clz %0,%1" \ + : "=r" ((USItype)(count)) \ + : "r" ((USItype)(x) >> 16)); \ + else \ + { \ + __asm__ ("clz %0,%1" \ + : "=r" ((USItype)(count)) \ + : "r" ((USItype)(x))); \ + (count) += 16; \ + } \ + } while (0) +#endif + +#if defined (__sparc__) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("addcc %4,%5,%1 + addx %2,%3,%0" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "%r" ((USItype)(ah)), \ + "rI" ((USItype)(bh)), \ + "%r" ((USItype)(al)), \ + "rI" ((USItype)(bl)) \ + __CLOBBER_CC) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("subcc %4,%5,%1 + subx %2,%3,%0" \ + : "=r" ((USItype)(sh)), \ + "=&r" ((USItype)(sl)) \ + : "r" ((USItype)(ah)), \ + "rI" ((USItype)(bh)), \ + "r" ((USItype)(al)), \ + "rI" ((USItype)(bl)) \ + __CLOBBER_CC) +#if defined (__sparc_v8__) +#define umul_ppmm(w1, w0, u, v) \ + __asm__ ("umul %2,%3,%1;rd %%y,%0" \ + : "=r" ((USItype)(w1)), \ + "=r" ((USItype)(w0)) \ + : "r" ((USItype)(u)), \ + "r" ((USItype)(v))) +#define udiv_qrnnd(q, r, n1, n0, d) \ + __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\ + : "=&r" ((USItype)(q)), \ + "=&r" ((USItype)(r)) \ + : "r" ((USItype)(n1)), \ + "r" ((USItype)(n0)), \ + "r" ((USItype)(d))) +#else +#if defined (__sparclite__) +/* This has hardware multiply but not divide. It also has two additional + instructions scan (ffs from high bit) and divscc. */ +#define umul_ppmm(w1, w0, u, v) \ + __asm__ ("umul %2,%3,%1;rd %%y,%0" \ + : "=r" ((USItype)(w1)), \ + "=r" ((USItype)(w0)) \ + : "r" ((USItype)(u)), \ + "r" ((USItype)(v))) +#define udiv_qrnnd(q, r, n1, n0, d) \ + __asm__ ("! Inlined udiv_qrnnd + wr %%g0,%2,%%y ! Not a delayed write for sparclite + tst %%g0 + divscc %3,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%%g1 + divscc %%g1,%4,%0 + rd %%y,%1 + bl,a 1f + add %1,%4,%1 +1: ! End of inline udiv_qrnnd" \ + : "=r" ((USItype)(q)), \ + "=r" ((USItype)(r)) \ + : "r" ((USItype)(n1)), \ + "r" ((USItype)(n0)), \ + "rI" ((USItype)(d)) \ + : "%g1" __AND_CLOBBER_CC) +#define UDIV_TIME 37 +#define count_leading_zeros(count, x) \ + __asm__ ("scan %1,0,%0" \ + : "=r" ((USItype)(x)) \ + : "r" ((USItype)(count))) +#else +/* SPARC without integer multiplication and divide instructions. + (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */ +#define umul_ppmm(w1, w0, u, v) \ + __asm__ ("! Inlined umul_ppmm + wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr + sra %3,31,%%g2 ! Don't move this insn + and %2,%%g2,%%g2 ! Don't move this insn + andcc %%g0,0,%%g1 ! Don't move this insn + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,%3,%%g1 + mulscc %%g1,0,%%g1 + add %%g1,%%g2,%0 + rd %%y,%1" \ + : "=r" ((USItype)(w1)), \ + "=r" ((USItype)(w0)) \ + : "%rI" ((USItype)(u)), \ + "r" ((USItype)(v)) \ + : "%g1", "%g2" __AND_CLOBBER_CC) +#define UMUL_TIME 39 /* 39 instructions */ +/* It's quite necessary to add this much assembler for the sparc. + The default udiv_qrnnd (in C) is more than 10 times slower! */ +#define udiv_qrnnd(q, r, n1, n0, d) \ + __asm__ ("! Inlined udiv_qrnnd + mov 32,%%g1 + subcc %1,%2,%%g0 +1: bcs 5f + addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb + sub %1,%2,%1 ! this kills msb of n + addx %1,%1,%1 ! so this can't give carry + subcc %%g1,1,%%g1 +2: bne 1b + subcc %1,%2,%%g0 + bcs 3f + addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb + b 3f + sub %1,%2,%1 ! this kills msb of n +4: sub %1,%2,%1 +5: addxcc %1,%1,%1 + bcc 2b + subcc %%g1,1,%%g1 +! Got carry from n. Subtract next step to cancel this carry. + bne 4b + addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb + sub %1,%2,%1 +3: xnor %0,0,%0 + ! End of inline udiv_qrnnd" \ + : "=&r" ((USItype)(q)), \ + "=&r" ((USItype)(r)) \ + : "r" ((USItype)(d)), \ + "1" ((USItype)(n1)), \ + "0" ((USItype)(n0)) : "%g1" __AND_CLOBBER_CC) +#define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */ +#endif /* __sparclite__ */ +#endif /* __sparc_v8__ */ +#endif /* __sparc__ */ + +#if defined (__vax__) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("addl2 %5,%1 + adwc %3,%0" \ + : "=g" ((USItype)(sh)), \ + "=&g" ((USItype)(sl)) \ + : "%0" ((USItype)(ah)), \ + "g" ((USItype)(bh)), \ + "%1" ((USItype)(al)), \ + "g" ((USItype)(bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("subl2 %5,%1 + sbwc %3,%0" \ + : "=g" ((USItype)(sh)), \ + "=&g" ((USItype)(sl)) \ + : "0" ((USItype)(ah)), \ + "g" ((USItype)(bh)), \ + "1" ((USItype)(al)), \ + "g" ((USItype)(bl))) +#define umul_ppmm(xh, xl, m0, m1) \ + do { \ + union { \ + UDItype __ll; \ + struct {USItype __l, __h;} __i; \ + } __xx; \ + USItype __m0 = (m0), __m1 = (m1); \ + __asm__ ("emul %1,%2,$0,%0" \ + : "=r" (__xx.__ll) \ + : "g" (__m0), \ + "g" (__m1)); \ + (xh) = __xx.__i.__h; \ + (xl) = __xx.__i.__l; \ + (xh) += ((((SItype) __m0 >> 31) & __m1) \ + + (((SItype) __m1 >> 31) & __m0)); \ + } while (0) +#endif /* __vax__ */ + +#endif /* __GNUC__ */ + +/* If this machine has no inline assembler, use C macros. */ + +#if !defined (add_ssaaaa) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + do { \ + USItype __x; \ + __x = (al) + (bl); \ + (sh) = (ah) + (bh) + (__x < (al)); \ + (sl) = __x; \ + } while (0) +#endif + +#if !defined (sub_ddmmss) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + do { \ + USItype __x; \ + __x = (al) - (bl); \ + (sh) = (ah) - (bh) - (__x > (al)); \ + (sl) = __x; \ + } while (0) +#endif + +#if !defined (umul_ppmm) +#define umul_ppmm(w1, w0, u, v) \ + do { \ + USItype __x0, __x1, __x2, __x3; \ + USItype __ul, __vl, __uh, __vh; \ + \ + __ul = __ll_lowpart (u); \ + __uh = __ll_highpart (u); \ + __vl = __ll_lowpart (v); \ + __vh = __ll_highpart (v); \ + \ + __x0 = (USItype) __ul * __vl; \ + __x1 = (USItype) __ul * __vh; \ + __x2 = (USItype) __uh * __vl; \ + __x3 = (USItype) __uh * __vh; \ + \ + __x1 += __ll_highpart (__x0);/* this can't give carry */ \ + __x1 += __x2; /* but this indeed can */ \ + if (__x1 < __x2) /* did we get it? */ \ + __x3 += __ll_B; /* yes, add it in the proper pos. */ \ + \ + (w1) = __x3 + __ll_highpart (__x1); \ + (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \ + } while (0) +#endif + +#if !defined (__umulsidi3) +#define __umulsidi3(u, v) \ + ({DIunion __w; \ + umul_ppmm (__w.s.high, __w.s.low, u, v); \ + __w.ll; }) +#endif + +/* Define this unconditionally, so it can be used for debugging. */ +#define __udiv_qrnnd_c(q, r, n1, n0, d) \ + do { \ + USItype __d1, __d0, __q1, __q0; \ + USItype __r1, __r0, __m; \ + __d1 = __ll_highpart (d); \ + __d0 = __ll_lowpart (d); \ + \ + __r1 = (n1) % __d1; \ + __q1 = (n1) / __d1; \ + __m = (USItype) __q1 * __d0; \ + __r1 = __r1 * __ll_B | __ll_highpart (n0); \ + if (__r1 < __m) \ + { \ + __q1--, __r1 += (d); \ + if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\ + if (__r1 < __m) \ + __q1--, __r1 += (d); \ + } \ + __r1 -= __m; \ + \ + __r0 = __r1 % __d1; \ + __q0 = __r1 / __d1; \ + __m = (USItype) __q0 * __d0; \ + __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ + if (__r0 < __m) \ + { \ + __q0--, __r0 += (d); \ + if (__r0 >= (d)) \ + if (__r0 < __m) \ + __q0--, __r0 += (d); \ + } \ + __r0 -= __m; \ + \ + (q) = (USItype) __q1 * __ll_B | __q0; \ + (r) = __r0; \ + } while (0) + +/* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through + __udiv_w_sdiv (defined in libgcc or elsewhere). */ +#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd) +#define udiv_qrnnd(q, r, nh, nl, d) \ + do { \ + USItype __r; \ + (q) = __udiv_w_sdiv (&__r, nh, nl, d); \ + (r) = __r; \ + } while (0) +#endif + +/* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */ +#if !defined (udiv_qrnnd) +#define UDIV_NEEDS_NORMALIZATION 1 +#define udiv_qrnnd __udiv_qrnnd_c +#endif + +#if !defined (count_leading_zeros) +extern const UQItype __clz_tab[]; +#define count_leading_zeros(count, x) \ + do { \ + USItype __xr = (x); \ + USItype __a; \ + \ + if (SI_TYPE_SIZE <= 32) \ + { \ + __a = __xr < (1<<2*__BITS4) \ + ? (__xr < (1<<__BITS4) ? 0 : __BITS4) \ + : (__xr < (1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \ + } \ + else \ + { \ + for (__a = SI_TYPE_SIZE - 8; __a > 0; __a -= 8) \ + if (((__xr >> __a) & 0xff) != 0) \ + break; \ + } \ + \ + (count) = SI_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \ + } while (0) +#endif + +#ifndef UDIV_NEEDS_NORMALIZATION +#define UDIV_NEEDS_NORMALIZATION 0 +#endif diff --git a/gnu/usr.bin/cc/lib/loop.c b/gnu/usr.bin/cc/lib/loop.c new file mode 100644 index 000000000000..ad82384c148f --- /dev/null +++ b/gnu/usr.bin/cc/lib/loop.c @@ -0,0 +1,6508 @@ +/* Move constant computations out of loops. + Copyright (C) 1987, 1988, 1989, 1991, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This is the loop optimization pass of the compiler. + It finds invariant computations within loops and moves them + to the beginning of the loop. Then it identifies basic and + general induction variables. Strength reduction is applied to the general + induction variables, and induction variable elimination is applied to + the basic induction variables. + + It also finds cases where + a register is set within the loop by zero-extending a narrower value + and changes these to zero the entire register once before the loop + and merely copy the low part within the loop. + + Most of the complexity is in heuristics to decide when it is worth + while to do these things. */ + +#include +#include "config.h" +#include "rtl.h" +#include "obstack.h" +#include "expr.h" +#include "insn-config.h" +#include "insn-flags.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "recog.h" +#include "flags.h" +#include "real.h" +#include "loop.h" + +/* Vector mapping INSN_UIDs to luids. + The luids are like uids but increase monotonically always. + We use them to see whether a jump comes from outside a given loop. */ + +int *uid_luid; + +/* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop + number the insn is contained in. */ + +int *uid_loop_num; + +/* 1 + largest uid of any insn. */ + +int max_uid_for_loop; + +/* 1 + luid of last insn. */ + +static int max_luid; + +/* Number of loops detected in current function. Used as index to the + next few tables. */ + +static int max_loop_num; + +/* Indexed by loop number, contains the first and last insn of each loop. */ + +static rtx *loop_number_loop_starts, *loop_number_loop_ends; + +/* For each loop, gives the containing loop number, -1 if none. */ + +int *loop_outer_loop; + +/* Indexed by loop number, contains a nonzero value if the "loop" isn't + really a loop (an insn outside the loop branches into it). */ + +static char *loop_invalid; + +/* Indexed by loop number, links together all LABEL_REFs which refer to + code labels outside the loop. Used by routines that need to know all + loop exits, such as final_biv_value and final_giv_value. + + This does not include loop exits due to return instructions. This is + because all bivs and givs are pseudos, and hence must be dead after a + return, so the presense of a return does not affect any of the + optimizations that use this info. It is simpler to just not include return + instructions on this list. */ + +rtx *loop_number_exit_labels; + +/* Holds the number of loop iterations. It is zero if the number could not be + calculated. Must be unsigned since the number of iterations can + be as high as 2^wordsize-1. For loops with a wider iterator, this number + will will be zero if the number of loop iterations is too large for an + unsigned integer to hold. */ + +unsigned HOST_WIDE_INT loop_n_iterations; + +/* Nonzero if there is a subroutine call in the current loop. + (unknown_address_altered is also nonzero in this case.) */ + +static int loop_has_call; + +/* Nonzero if there is a volatile memory reference in the current + loop. */ + +static int loop_has_volatile; + +/* Added loop_continue which is the NOTE_INSN_LOOP_CONT of the + current loop. A continue statement will generate a branch to + NEXT_INSN (loop_continue). */ + +static rtx loop_continue; + +/* Indexed by register number, contains the number of times the reg + is set during the loop being scanned. + During code motion, a negative value indicates a reg that has been + made a candidate; in particular -2 means that it is an candidate that + we know is equal to a constant and -1 means that it is an candidate + not known equal to a constant. + After code motion, regs moved have 0 (which is accurate now) + while the failed candidates have the original number of times set. + + Therefore, at all times, == 0 indicates an invariant register; + < 0 a conditionally invariant one. */ + +static short *n_times_set; + +/* Original value of n_times_set; same except that this value + is not set negative for a reg whose sets have been made candidates + and not set to 0 for a reg that is moved. */ + +static short *n_times_used; + +/* Index by register number, 1 indicates that the register + cannot be moved or strength reduced. */ + +static char *may_not_optimize; + +/* Nonzero means reg N has already been moved out of one loop. + This reduces the desire to move it out of another. */ + +static char *moved_once; + +/* Array of MEMs that are stored in this loop. If there are too many to fit + here, we just turn on unknown_address_altered. */ + +#define NUM_STORES 20 +static rtx loop_store_mems[NUM_STORES]; + +/* Index of first available slot in above array. */ +static int loop_store_mems_idx; + +/* Nonzero if we don't know what MEMs were changed in the current loop. + This happens if the loop contains a call (in which case `loop_has_call' + will also be set) or if we store into more than NUM_STORES MEMs. */ + +static int unknown_address_altered; + +/* Count of movable (i.e. invariant) instructions discovered in the loop. */ +static int num_movables; + +/* Count of memory write instructions discovered in the loop. */ +static int num_mem_sets; + +/* Number of loops contained within the current one, including itself. */ +static int loops_enclosed; + +/* Bound on pseudo register number before loop optimization. + A pseudo has valid regscan info if its number is < max_reg_before_loop. */ +int max_reg_before_loop; + +/* This obstack is used in product_cheap_p to allocate its rtl. It + may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx. + If we used the same obstack that it did, we would be deallocating + that array. */ + +static struct obstack temp_obstack; + +/* This is where the pointer to the obstack being used for RTL is stored. */ + +extern struct obstack *rtl_obstack; + +#define obstack_chunk_alloc xmalloc +#define obstack_chunk_free free + +extern char *oballoc (); + +/* During the analysis of a loop, a chain of `struct movable's + is made to record all the movable insns found. + Then the entire chain can be scanned to decide which to move. */ + +struct movable +{ + rtx insn; /* A movable insn */ + rtx set_src; /* The expression this reg is set from. */ + rtx set_dest; /* The destination of this SET. */ + rtx dependencies; /* When INSN is libcall, this is an EXPR_LIST + of any registers used within the LIBCALL. */ + int consec; /* Number of consecutive following insns + that must be moved with this one. */ + int regno; /* The register it sets */ + short lifetime; /* lifetime of that register; + may be adjusted when matching movables + that load the same value are found. */ + short savings; /* Number of insns we can move for this reg, + including other movables that force this + or match this one. */ + unsigned int cond : 1; /* 1 if only conditionally movable */ + unsigned int force : 1; /* 1 means MUST move this insn */ + unsigned int global : 1; /* 1 means reg is live outside this loop */ + /* If PARTIAL is 1, GLOBAL means something different: + that the reg is live outside the range from where it is set + to the following label. */ + unsigned int done : 1; /* 1 inhibits further processing of this */ + + unsigned int partial : 1; /* 1 means this reg is used for zero-extending. + In particular, moving it does not make it + invariant. */ + unsigned int move_insn : 1; /* 1 means that we call emit_move_insn to + load SRC, rather than copying INSN. */ + unsigned int is_equiv : 1; /* 1 means a REG_EQUIV is present on INSN. */ + enum machine_mode savemode; /* Nonzero means it is a mode for a low part + that we should avoid changing when clearing + the rest of the reg. */ + struct movable *match; /* First entry for same value */ + struct movable *forces; /* An insn that must be moved if this is */ + struct movable *next; +}; + +FILE *loop_dump_stream; + +/* Forward declarations. */ + +static void find_and_verify_loops (); +static void mark_loop_jump (); +static void prescan_loop (); +static int reg_in_basic_block_p (); +static int consec_sets_invariant_p (); +static rtx libcall_other_reg (); +static int labels_in_range_p (); +static void count_loop_regs_set (); +static void note_addr_stored (); +static int loop_reg_used_before_p (); +static void scan_loop (); +static void replace_call_address (); +static rtx skip_consec_insns (); +static int libcall_benefit (); +static void ignore_some_movables (); +static void force_movables (); +static void combine_movables (); +static int rtx_equal_for_loop_p (); +static void move_movables (); +static void strength_reduce (); +static int valid_initial_value_p (); +static void find_mem_givs (); +static void record_biv (); +static void check_final_value (); +static void record_giv (); +static void update_giv_derive (); +static int basic_induction_var (); +static rtx simplify_giv_expr (); +static int general_induction_var (); +static int consec_sets_giv (); +static int check_dbra_loop (); +static rtx express_from (); +static int combine_givs_p (); +static void combine_givs (); +static int product_cheap_p (); +static int maybe_eliminate_biv (); +static int maybe_eliminate_biv_1 (); +static int last_use_this_basic_block (); +static void record_initial (); +static void update_reg_last_use (); + +/* Relative gain of eliminating various kinds of operations. */ +int add_cost; +#if 0 +int shift_cost; +int mult_cost; +#endif + +/* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to + copy the value of the strength reduced giv to its original register. */ +int copy_cost; + +void +init_loop () +{ + char *free_point = (char *) oballoc (1); + rtx reg = gen_rtx (REG, word_mode, 0); + rtx pow2 = GEN_INT (32); + rtx lea; + int i; + + add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET); + + /* We multiply by 2 to reconcile the difference in scale between + these two ways of computing costs. Otherwise the cost of a copy + will be far less than the cost of an add. */ + + copy_cost = 2 * 2; + + /* Free the objects we just allocated. */ + obfree (free_point); + + /* Initialize the obstack used for rtl in product_cheap_p. */ + gcc_obstack_init (&temp_obstack); +} + +/* Entry point of this file. Perform loop optimization + on the current function. F is the first insn of the function + and DUMPFILE is a stream for output of a trace of actions taken + (or 0 if none should be output). */ + +void +loop_optimize (f, dumpfile) + /* f is the first instruction of a chain of insns for one function */ + rtx f; + FILE *dumpfile; +{ + register rtx insn; + register int i; + rtx end; + rtx last_insn; + + loop_dump_stream = dumpfile; + + init_recog_no_volatile (); + init_alias_analysis (); + + max_reg_before_loop = max_reg_num (); + + moved_once = (char *) alloca (max_reg_before_loop); + bzero (moved_once, max_reg_before_loop); + + regs_may_share = 0; + + /* Count the number of loops. */ + + max_loop_num = 0; + for (insn = f; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) + max_loop_num++; + } + + /* Don't waste time if no loops. */ + if (max_loop_num == 0) + return; + + /* Get size to use for tables indexed by uids. + Leave some space for labels allocated by find_and_verify_loops. */ + max_uid_for_loop = get_max_uid () + 1 + max_loop_num * 32; + + uid_luid = (int *) alloca (max_uid_for_loop * sizeof (int)); + uid_loop_num = (int *) alloca (max_uid_for_loop * sizeof (int)); + + bzero (uid_luid, max_uid_for_loop * sizeof (int)); + bzero (uid_loop_num, max_uid_for_loop * sizeof (int)); + + /* Allocate tables for recording each loop. We set each entry, so they need + not be zeroed. */ + loop_number_loop_starts = (rtx *) alloca (max_loop_num * sizeof (rtx)); + loop_number_loop_ends = (rtx *) alloca (max_loop_num * sizeof (rtx)); + loop_outer_loop = (int *) alloca (max_loop_num * sizeof (int)); + loop_invalid = (char *) alloca (max_loop_num * sizeof (char)); + loop_number_exit_labels = (rtx *) alloca (max_loop_num * sizeof (rtx)); + + /* Find and process each loop. + First, find them, and record them in order of their beginnings. */ + find_and_verify_loops (f); + + /* Now find all register lifetimes. This must be done after + find_and_verify_loops, because it might reorder the insns in the + function. */ + reg_scan (f, max_reg_num (), 1); + + /* See if we went too far. */ + if (get_max_uid () > max_uid_for_loop) + abort (); + + /* Compute the mapping from uids to luids. + LUIDs are numbers assigned to insns, like uids, + except that luids increase monotonically through the code. + Don't assign luids to line-number NOTEs, so that the distance in luids + between two insns is not affected by -g. */ + + for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) + { + last_insn = insn; + if (GET_CODE (insn) != NOTE + || NOTE_LINE_NUMBER (insn) <= 0) + uid_luid[INSN_UID (insn)] = ++i; + else + /* Give a line number note the same luid as preceding insn. */ + uid_luid[INSN_UID (insn)] = i; + } + + max_luid = i + 1; + + /* Don't leave gaps in uid_luid for insns that have been + deleted. It is possible that the first or last insn + using some register has been deleted by cross-jumping. + Make sure that uid_luid for that former insn's uid + points to the general area where that insn used to be. */ + for (i = 0; i < max_uid_for_loop; i++) + { + uid_luid[0] = uid_luid[i]; + if (uid_luid[0] != 0) + break; + } + for (i = 0; i < max_uid_for_loop; i++) + if (uid_luid[i] == 0) + uid_luid[i] = uid_luid[i - 1]; + + /* Create a mapping from loops to BLOCK tree nodes. */ + if (flag_unroll_loops && write_symbols != NO_DEBUG) + find_loop_tree_blocks (); + + /* Now scan the loops, last ones first, since this means inner ones are done + before outer ones. */ + for (i = max_loop_num-1; i >= 0; i--) + if (! loop_invalid[i] && loop_number_loop_ends[i]) + scan_loop (loop_number_loop_starts[i], loop_number_loop_ends[i], + max_reg_num ()); + + /* If debugging and unrolling loops, we must replicate the tree nodes + corresponding to the blocks inside the loop, so that the original one + to one mapping will remain. */ + if (flag_unroll_loops && write_symbols != NO_DEBUG) + unroll_block_trees (); +} + +/* Optimize one loop whose start is LOOP_START and end is END. + LOOP_START is the NOTE_INSN_LOOP_BEG and END is the matching + NOTE_INSN_LOOP_END. */ + +/* ??? Could also move memory writes out of loops if the destination address + is invariant, the source is invariant, the memory write is not volatile, + and if we can prove that no read inside the loop can read this address + before the write occurs. If there is a read of this address after the + write, then we can also mark the memory read as invariant. */ + +static void +scan_loop (loop_start, end, nregs) + rtx loop_start, end; + int nregs; +{ + register int i; + register rtx p; + /* 1 if we are scanning insns that could be executed zero times. */ + int maybe_never = 0; + /* 1 if we are scanning insns that might never be executed + due to a subroutine call which might exit before they are reached. */ + int call_passed = 0; + /* For a rotated loop that is entered near the bottom, + this is the label at the top. Otherwise it is zero. */ + rtx loop_top = 0; + /* Jump insn that enters the loop, or 0 if control drops in. */ + rtx loop_entry_jump = 0; + /* Place in the loop where control enters. */ + rtx scan_start; + /* Number of insns in the loop. */ + int insn_count; + int in_libcall = 0; + int tem; + rtx temp; + /* The SET from an insn, if it is the only SET in the insn. */ + rtx set, set1; + /* Chain describing insns movable in current loop. */ + struct movable *movables = 0; + /* Last element in `movables' -- so we can add elements at the end. */ + struct movable *last_movable = 0; + /* Ratio of extra register life span we can justify + for saving an instruction. More if loop doesn't call subroutines + since in that case saving an insn makes more difference + and more registers are available. */ + int threshold; + /* If we have calls, contains the insn in which a register was used + if it was used exactly once; contains const0_rtx if it was used more + than once. */ + rtx *reg_single_usage = 0; + + n_times_set = (short *) alloca (nregs * sizeof (short)); + n_times_used = (short *) alloca (nregs * sizeof (short)); + may_not_optimize = (char *) alloca (nregs); + + /* Determine whether this loop starts with a jump down to a test at + the end. This will occur for a small number of loops with a test + that is too complex to duplicate in front of the loop. + + We search for the first insn or label in the loop, skipping NOTEs. + However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG + (because we might have a loop executed only once that contains a + loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END + (in case we have a degenerate loop). + + Note that if we mistakenly think that a loop is entered at the top + when, in fact, it is entered at the exit test, the only effect will be + slightly poorer optimization. Making the opposite error can generate + incorrect code. Since very few loops now start with a jump to the + exit test, the code here to detect that case is very conservative. */ + + for (p = NEXT_INSN (loop_start); + p != end + && GET_CODE (p) != CODE_LABEL && GET_RTX_CLASS (GET_CODE (p)) != 'i' + && (GET_CODE (p) != NOTE + || (NOTE_LINE_NUMBER (p) != NOTE_INSN_LOOP_BEG + && NOTE_LINE_NUMBER (p) != NOTE_INSN_LOOP_END)); + p = NEXT_INSN (p)) + ; + + scan_start = p; + + /* Set up variables describing this loop. */ + prescan_loop (loop_start, end); + threshold = (loop_has_call ? 1 : 2) * (1 + n_non_fixed_regs); + + /* If loop has a jump before the first label, + the true entry is the target of that jump. + Start scan from there. + But record in LOOP_TOP the place where the end-test jumps + back to so we can scan that after the end of the loop. */ + if (GET_CODE (p) == JUMP_INSN) + { + loop_entry_jump = p; + + /* Loop entry must be unconditional jump (and not a RETURN) */ + if (simplejump_p (p) + && JUMP_LABEL (p) != 0 + /* Check to see whether the jump actually + jumps out of the loop (meaning it's no loop). + This case can happen for things like + do {..} while (0). If this label was generated previously + by loop, we can't tell anything about it and have to reject + the loop. */ + && INSN_UID (JUMP_LABEL (p)) < max_uid_for_loop + && INSN_LUID (JUMP_LABEL (p)) >= INSN_LUID (loop_start) + && INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (end)) + { + loop_top = next_label (scan_start); + scan_start = JUMP_LABEL (p); + } + } + + /* If SCAN_START was an insn created by loop, we don't know its luid + as required by loop_reg_used_before_p. So skip such loops. (This + test may never be true, but it's best to play it safe.) + + Also, skip loops where we do not start scanning at a label. This + test also rejects loops starting with a JUMP_INSN that failed the + test above. */ + + if (INSN_UID (scan_start) >= max_uid_for_loop + || GET_CODE (scan_start) != CODE_LABEL) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, "\nLoop from %d to %d is phony.\n\n", + INSN_UID (loop_start), INSN_UID (end)); + return; + } + + /* Count number of times each reg is set during this loop. + Set may_not_optimize[I] if it is not safe to move out + the setting of register I. If this loop has calls, set + reg_single_usage[I]. */ + + bzero (n_times_set, nregs * sizeof (short)); + bzero (may_not_optimize, nregs); + + if (loop_has_call) + { + reg_single_usage = (rtx *) alloca (nregs * sizeof (rtx)); + bzero (reg_single_usage, nregs * sizeof (rtx)); + } + + count_loop_regs_set (loop_top ? loop_top : loop_start, end, + may_not_optimize, reg_single_usage, &insn_count, nregs); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + may_not_optimize[i] = 1, n_times_set[i] = 1; + bcopy (n_times_set, n_times_used, nregs * sizeof (short)); + + if (loop_dump_stream) + { + fprintf (loop_dump_stream, "\nLoop from %d to %d: %d real insns.\n", + INSN_UID (loop_start), INSN_UID (end), insn_count); + if (loop_continue) + fprintf (loop_dump_stream, "Continue at insn %d.\n", + INSN_UID (loop_continue)); + } + + /* Scan through the loop finding insns that are safe to move. + Set n_times_set negative for the reg being set, so that + this reg will be considered invariant for subsequent insns. + We consider whether subsequent insns use the reg + in deciding whether it is worth actually moving. + + MAYBE_NEVER is nonzero if we have passed a conditional jump insn + and therefore it is possible that the insns we are scanning + would never be executed. At such times, we must make sure + that it is safe to execute the insn once instead of zero times. + When MAYBE_NEVER is 0, all insns will be executed at least once + so that is not a problem. */ + + p = scan_start; + while (1) + { + p = NEXT_INSN (p); + /* At end of a straight-in loop, we are done. + At end of a loop entered at the bottom, scan the top. */ + if (p == scan_start) + break; + if (p == end) + { + if (loop_top != 0) + p = NEXT_INSN (loop_top); + else + break; + if (p == scan_start) + break; + } + + if (GET_RTX_CLASS (GET_CODE (p)) == 'i' + && find_reg_note (p, REG_LIBCALL, NULL_RTX)) + in_libcall = 1; + else if (GET_RTX_CLASS (GET_CODE (p)) == 'i' + && find_reg_note (p, REG_RETVAL, NULL_RTX)) + in_libcall = 0; + + if (GET_CODE (p) == INSN + && (set = single_set (p)) + && GET_CODE (SET_DEST (set)) == REG + && ! may_not_optimize[REGNO (SET_DEST (set))]) + { + int tem1 = 0; + int tem2 = 0; + int move_insn = 0; + rtx src = SET_SRC (set); + rtx dependencies = 0; + + /* Figure out what to use as a source of this insn. If a REG_EQUIV + note is given or if a REG_EQUAL note with a constant operand is + specified, use it as the source and mark that we should move + this insn by calling emit_move_insn rather that duplicating the + insn. + + Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note + is present. */ + temp = find_reg_note (p, REG_EQUIV, NULL_RTX); + if (temp) + src = XEXP (temp, 0), move_insn = 1; + else + { + temp = find_reg_note (p, REG_EQUAL, NULL_RTX); + if (temp && CONSTANT_P (XEXP (temp, 0))) + src = XEXP (temp, 0), move_insn = 1; + if (temp && find_reg_note (p, REG_RETVAL, NULL_RTX)) + { + src = XEXP (temp, 0); + /* A libcall block can use regs that don't appear in + the equivalent expression. To move the libcall, + we must move those regs too. */ + dependencies = libcall_other_reg (p, src); + } + } + + /* Don't try to optimize a register that was made + by loop-optimization for an inner loop. + We don't know its life-span, so we can't compute the benefit. */ + if (REGNO (SET_DEST (set)) >= max_reg_before_loop) + ; + /* In order to move a register, we need to have one of three cases: + (1) it is used only in the same basic block as the set + (2) it is not a user variable and it is not used in the + exit test (this can cause the variable to be used + before it is set just like a user-variable). + (3) the set is guaranteed to be executed once the loop starts, + and the reg is not used until after that. */ + else if (! ((! maybe_never + && ! loop_reg_used_before_p (set, p, loop_start, + scan_start, end)) + || (! REG_USERVAR_P (SET_DEST (PATTERN (p))) + && ! REG_LOOP_TEST_P (SET_DEST (PATTERN (p)))) + || reg_in_basic_block_p (p, SET_DEST (PATTERN (p))))) + ; + else if ((tem = invariant_p (src)) + && (dependencies == 0 + || (tem2 = invariant_p (dependencies)) != 0) + && (n_times_set[REGNO (SET_DEST (set))] == 1 + || (tem1 + = consec_sets_invariant_p (SET_DEST (set), + n_times_set[REGNO (SET_DEST (set))], + p))) + /* If the insn can cause a trap (such as divide by zero), + can't move it unless it's guaranteed to be executed + once loop is entered. Even a function call might + prevent the trap insn from being reached + (since it might exit!) */ + && ! ((maybe_never || call_passed) + && may_trap_p (src))) + { + register struct movable *m; + register int regno = REGNO (SET_DEST (set)); + + /* A potential lossage is where we have a case where two insns + can be combined as long as they are both in the loop, but + we move one of them outside the loop. For large loops, + this can lose. The most common case of this is the address + of a function being called. + + Therefore, if this register is marked as being used exactly + once if we are in a loop with calls (a "large loop"), see if + we can replace the usage of this register with the source + of this SET. If we can, delete this insn. + + Don't do this if P has a REG_RETVAL note or if we have + SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */ + + if (reg_single_usage && reg_single_usage[regno] != 0 + && reg_single_usage[regno] != const0_rtx + && regno_first_uid[regno] == INSN_UID (p) + && (regno_last_uid[regno] + == INSN_UID (reg_single_usage[regno])) + && n_times_set[REGNO (SET_DEST (set))] == 1 + && ! side_effects_p (SET_SRC (set)) + && ! find_reg_note (p, REG_RETVAL, NULL_RTX) +#ifdef SMALL_REGISTER_CLASSES + && ! (GET_CODE (SET_SRC (set)) == REG + && REGNO (SET_SRC (set)) < FIRST_PSEUDO_REGISTER) +#endif + /* This test is not redundant; SET_SRC (set) might be + a call-clobbered register and the life of REGNO + might span a call. */ + && ! modified_between_p (SET_SRC (set), p, + reg_single_usage[regno]) + && validate_replace_rtx (SET_DEST (set), SET_SRC (set), + reg_single_usage[regno])) + { + /* Replace any usage in a REG_EQUAL note. */ + REG_NOTES (reg_single_usage[regno]) + = replace_rtx (REG_NOTES (reg_single_usage[regno]), + SET_DEST (set), SET_SRC (set)); + + PUT_CODE (p, NOTE); + NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (p) = 0; + n_times_set[regno] = 0; + continue; + } + + m = (struct movable *) alloca (sizeof (struct movable)); + m->next = 0; + m->insn = p; + m->set_src = src; + m->dependencies = dependencies; + m->set_dest = SET_DEST (set); + m->force = 0; + m->consec = n_times_set[REGNO (SET_DEST (set))] - 1; + m->done = 0; + m->forces = 0; + m->partial = 0; + m->move_insn = move_insn; + m->is_equiv = (find_reg_note (p, REG_EQUIV, NULL_RTX) != 0); + m->savemode = VOIDmode; + m->regno = regno; + /* Set M->cond if either invariant_p or consec_sets_invariant_p + returned 2 (only conditionally invariant). */ + m->cond = ((tem | tem1 | tem2) > 1); + m->global = (uid_luid[regno_last_uid[regno]] > INSN_LUID (end) + || uid_luid[regno_first_uid[regno]] < INSN_LUID (loop_start)); + m->match = 0; + m->lifetime = (uid_luid[regno_last_uid[regno]] + - uid_luid[regno_first_uid[regno]]); + m->savings = n_times_used[regno]; + if (find_reg_note (p, REG_RETVAL, NULL_RTX)) + m->savings += libcall_benefit (p); + n_times_set[regno] = move_insn ? -2 : -1; + /* Add M to the end of the chain MOVABLES. */ + if (movables == 0) + movables = m; + else + last_movable->next = m; + last_movable = m; + + if (m->consec > 0) + { + /* Skip this insn, not checking REG_LIBCALL notes. */ + p = NEXT_INSN (p); + /* Skip the consecutive insns, if there are any. */ + p = skip_consec_insns (p, m->consec); + /* Back up to the last insn of the consecutive group. */ + p = prev_nonnote_insn (p); + + /* We must now reset m->move_insn, m->is_equiv, and possibly + m->set_src to correspond to the effects of all the + insns. */ + temp = find_reg_note (p, REG_EQUIV, NULL_RTX); + if (temp) + m->set_src = XEXP (temp, 0), m->move_insn = 1; + else + { + temp = find_reg_note (p, REG_EQUAL, NULL_RTX); + if (temp && CONSTANT_P (XEXP (temp, 0))) + m->set_src = XEXP (temp, 0), m->move_insn = 1; + else + m->move_insn = 0; + + } + m->is_equiv = (find_reg_note (p, REG_EQUIV, NULL_RTX) != 0); + } + } + /* If this register is always set within a STRICT_LOW_PART + or set to zero, then its high bytes are constant. + So clear them outside the loop and within the loop + just load the low bytes. + We must check that the machine has an instruction to do so. + Also, if the value loaded into the register + depends on the same register, this cannot be done. */ + else if (SET_SRC (set) == const0_rtx + && GET_CODE (NEXT_INSN (p)) == INSN + && (set1 = single_set (NEXT_INSN (p))) + && GET_CODE (set1) == SET + && (GET_CODE (SET_DEST (set1)) == STRICT_LOW_PART) + && (GET_CODE (XEXP (SET_DEST (set1), 0)) == SUBREG) + && (SUBREG_REG (XEXP (SET_DEST (set1), 0)) + == SET_DEST (set)) + && !reg_mentioned_p (SET_DEST (set), SET_SRC (set1))) + { + register int regno = REGNO (SET_DEST (set)); + if (n_times_set[regno] == 2) + { + register struct movable *m; + m = (struct movable *) alloca (sizeof (struct movable)); + m->next = 0; + m->insn = p; + m->set_dest = SET_DEST (set); + m->dependencies = 0; + m->force = 0; + m->consec = 0; + m->done = 0; + m->forces = 0; + m->move_insn = 0; + m->partial = 1; + /* If the insn may not be executed on some cycles, + we can't clear the whole reg; clear just high part. + Not even if the reg is used only within this loop. + Consider this: + while (1) + while (s != t) { + if (foo ()) x = *s; + use (x); + } + Clearing x before the inner loop could clobber a value + being saved from the last time around the outer loop. + However, if the reg is not used outside this loop + and all uses of the register are in the same + basic block as the store, there is no problem. + + If this insn was made by loop, we don't know its + INSN_LUID and hence must make a conservative + assumption. */ + m->global = (INSN_UID (p) >= max_uid_for_loop + || (uid_luid[regno_last_uid[regno]] + > INSN_LUID (end)) + || (uid_luid[regno_first_uid[regno]] + < INSN_LUID (p)) + || (labels_in_range_p + (p, uid_luid[regno_first_uid[regno]]))); + if (maybe_never && m->global) + m->savemode = GET_MODE (SET_SRC (set1)); + else + m->savemode = VOIDmode; + m->regno = regno; + m->cond = 0; + m->match = 0; + m->lifetime = (uid_luid[regno_last_uid[regno]] + - uid_luid[regno_first_uid[regno]]); + m->savings = 1; + n_times_set[regno] = -1; + /* Add M to the end of the chain MOVABLES. */ + if (movables == 0) + movables = m; + else + last_movable->next = m; + last_movable = m; + } + } + } + /* Past a call insn, we get to insns which might not be executed + because the call might exit. This matters for insns that trap. + Call insns inside a REG_LIBCALL/REG_RETVAL block always return, + so they don't count. */ + else if (GET_CODE (p) == CALL_INSN && ! in_libcall) + call_passed = 1; + /* Past a label or a jump, we get to insns for which we + can't count on whether or how many times they will be + executed during each iteration. Therefore, we can + only move out sets of trivial variables + (those not used after the loop). */ + /* This code appears in three places, once in scan_loop, and twice + in strength_reduce. */ + else if ((GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN) + /* If we enter the loop in the middle, and scan around to the + beginning, don't set maybe_never for that. This must be an + unconditional jump, otherwise the code at the top of the + loop might never be executed. Unconditional jumps are + followed a by barrier then loop end. */ + && ! (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) == loop_top + && NEXT_INSN (NEXT_INSN (p)) == end + && simplejump_p (p))) + maybe_never = 1; + /* At the virtual top of a converted loop, insns are again known to + be executed: logically, the loop begins here even though the exit + code has been duplicated. */ + else if (GET_CODE (p) == NOTE + && NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP) + maybe_never = call_passed = 0; + } + + /* If one movable subsumes another, ignore that other. */ + + ignore_some_movables (movables); + + /* For each movable insn, see if the reg that it loads + leads when it dies right into another conditionally movable insn. + If so, record that the second insn "forces" the first one, + since the second can be moved only if the first is. */ + + force_movables (movables); + + /* See if there are multiple movable insns that load the same value. + If there are, make all but the first point at the first one + through the `match' field, and add the priorities of them + all together as the priority of the first. */ + + combine_movables (movables, nregs); + + /* Now consider each movable insn to decide whether it is worth moving. + Store 0 in n_times_set for each reg that is moved. */ + + move_movables (movables, threshold, + insn_count, loop_start, end, nregs); + + /* Now candidates that still are negative are those not moved. + Change n_times_set to indicate that those are not actually invariant. */ + for (i = 0; i < nregs; i++) + if (n_times_set[i] < 0) + n_times_set[i] = n_times_used[i]; + + if (flag_strength_reduce) + strength_reduce (scan_start, end, loop_top, + insn_count, loop_start, end); +} + +/* Add elements to *OUTPUT to record all the pseudo-regs + mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */ + +void +record_excess_regs (in_this, not_in_this, output) + rtx in_this, not_in_this; + rtx *output; +{ + enum rtx_code code; + char *fmt; + int i; + + code = GET_CODE (in_this); + + switch (code) + { + case PC: + case CC0: + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + return; + + case REG: + if (REGNO (in_this) >= FIRST_PSEUDO_REGISTER + && ! reg_mentioned_p (in_this, not_in_this)) + *output = gen_rtx (EXPR_LIST, VOIDmode, in_this, *output); + return; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + int j; + + switch (fmt[i]) + { + case 'E': + for (j = 0; j < XVECLEN (in_this, i); j++) + record_excess_regs (XVECEXP (in_this, i, j), not_in_this, output); + break; + + case 'e': + record_excess_regs (XEXP (in_this, i), not_in_this, output); + break; + } + } +} + +/* Check what regs are referred to in the libcall block ending with INSN, + aside from those mentioned in the equivalent value. + If there are none, return 0. + If there are one or more, return an EXPR_LIST containing all of them. */ + +static rtx +libcall_other_reg (insn, equiv) + rtx insn, equiv; +{ + rtx note = find_reg_note (insn, REG_RETVAL, NULL_RTX); + rtx p = XEXP (note, 0); + rtx output = 0; + + /* First, find all the regs used in the libcall block + that are not mentioned as inputs to the result. */ + + while (p != insn) + { + if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN + || GET_CODE (p) == CALL_INSN) + record_excess_regs (PATTERN (p), equiv, &output); + p = NEXT_INSN (p); + } + + return output; +} + +/* Return 1 if all uses of REG + are between INSN and the end of the basic block. */ + +static int +reg_in_basic_block_p (insn, reg) + rtx insn, reg; +{ + int regno = REGNO (reg); + rtx p; + + if (regno_first_uid[regno] != INSN_UID (insn)) + return 0; + + /* Search this basic block for the already recorded last use of the reg. */ + for (p = insn; p; p = NEXT_INSN (p)) + { + switch (GET_CODE (p)) + { + case NOTE: + break; + + case INSN: + case CALL_INSN: + /* Ordinary insn: if this is the last use, we win. */ + if (regno_last_uid[regno] == INSN_UID (p)) + return 1; + break; + + case JUMP_INSN: + /* Jump insn: if this is the last use, we win. */ + if (regno_last_uid[regno] == INSN_UID (p)) + return 1; + /* Otherwise, it's the end of the basic block, so we lose. */ + return 0; + + case CODE_LABEL: + case BARRIER: + /* It's the end of the basic block, so we lose. */ + return 0; + } + } + + /* The "last use" doesn't follow the "first use"?? */ + abort (); +} + +/* Compute the benefit of eliminating the insns in the block whose + last insn is LAST. This may be a group of insns used to compute a + value directly or can contain a library call. */ + +static int +libcall_benefit (last) + rtx last; +{ + rtx insn; + int benefit = 0; + + for (insn = XEXP (find_reg_note (last, REG_RETVAL, NULL_RTX), 0); + insn != last; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == CALL_INSN) + benefit += 10; /* Assume at least this many insns in a library + routine. */ + else if (GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) != USE + && GET_CODE (PATTERN (insn)) != CLOBBER) + benefit++; + } + + return benefit; +} + +/* Skip COUNT insns from INSN, counting library calls as 1 insn. */ + +static rtx +skip_consec_insns (insn, count) + rtx insn; + int count; +{ + for (; count > 0; count--) + { + rtx temp; + + /* If first insn of libcall sequence, skip to end. */ + /* Do this at start of loop, since INSN is guaranteed to + be an insn here. */ + if (GET_CODE (insn) != NOTE + && (temp = find_reg_note (insn, REG_LIBCALL, NULL_RTX))) + insn = XEXP (temp, 0); + + do insn = NEXT_INSN (insn); + while (GET_CODE (insn) == NOTE); + } + + return insn; +} + +/* Ignore any movable whose insn falls within a libcall + which is part of another movable. + We make use of the fact that the movable for the libcall value + was made later and so appears later on the chain. */ + +static void +ignore_some_movables (movables) + struct movable *movables; +{ + register struct movable *m, *m1; + + for (m = movables; m; m = m->next) + { + /* Is this a movable for the value of a libcall? */ + rtx note = find_reg_note (m->insn, REG_RETVAL, NULL_RTX); + if (note) + { + rtx insn; + /* Check for earlier movables inside that range, + and mark them invalid. We cannot use LUIDs here because + insns created by loop.c for prior loops don't have LUIDs. + Rather than reject all such insns from movables, we just + explicitly check each insn in the libcall (since invariant + libcalls aren't that common). */ + for (insn = XEXP (note, 0); insn != m->insn; insn = NEXT_INSN (insn)) + for (m1 = movables; m1 != m; m1 = m1->next) + if (m1->insn == insn) + m1->done = 1; + } + } +} + +/* For each movable insn, see if the reg that it loads + leads when it dies right into another conditionally movable insn. + If so, record that the second insn "forces" the first one, + since the second can be moved only if the first is. */ + +static void +force_movables (movables) + struct movable *movables; +{ + register struct movable *m, *m1; + for (m1 = movables; m1; m1 = m1->next) + /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */ + if (!m1->partial && !m1->done) + { + int regno = m1->regno; + for (m = m1->next; m; m = m->next) + /* ??? Could this be a bug? What if CSE caused the + register of M1 to be used after this insn? + Since CSE does not update regno_last_uid, + this insn M->insn might not be where it dies. + But very likely this doesn't matter; what matters is + that M's reg is computed from M1's reg. */ + if (INSN_UID (m->insn) == regno_last_uid[regno] + && !m->done) + break; + if (m != 0 && m->set_src == m1->set_dest + /* If m->consec, m->set_src isn't valid. */ + && m->consec == 0) + m = 0; + + /* Increase the priority of the moving the first insn + since it permits the second to be moved as well. */ + if (m != 0) + { + m->forces = m1; + m1->lifetime += m->lifetime; + m1->savings += m1->savings; + } + } +} + +/* Find invariant expressions that are equal and can be combined into + one register. */ + +static void +combine_movables (movables, nregs) + struct movable *movables; + int nregs; +{ + register struct movable *m; + char *matched_regs = (char *) alloca (nregs); + enum machine_mode mode; + + /* Regs that are set more than once are not allowed to match + or be matched. I'm no longer sure why not. */ + /* Perhaps testing m->consec_sets would be more appropriate here? */ + + for (m = movables; m; m = m->next) + if (m->match == 0 && n_times_used[m->regno] == 1 && !m->partial) + { + register struct movable *m1; + int regno = m->regno; + rtx reg_note, reg_note1; + + bzero (matched_regs, nregs); + matched_regs[regno] = 1; + + for (m1 = movables; m1; m1 = m1->next) + if (m != m1 && m1->match == 0 && n_times_used[m1->regno] == 1 + /* A reg used outside the loop mustn't be eliminated. */ + && !m1->global + /* A reg used for zero-extending mustn't be eliminated. */ + && !m1->partial + && (matched_regs[m1->regno] + || + ( + /* Can combine regs with different modes loaded from the + same constant only if the modes are the same or + if both are integer modes with M wider or the same + width as M1. The check for integer is redundant, but + safe, since the only case of differing destination + modes with equal sources is when both sources are + VOIDmode, i.e., CONST_INT. */ + (GET_MODE (m->set_dest) == GET_MODE (m1->set_dest) + || (GET_MODE_CLASS (GET_MODE (m->set_dest)) == MODE_INT + && GET_MODE_CLASS (GET_MODE (m1->set_dest)) == MODE_INT + && (GET_MODE_BITSIZE (GET_MODE (m->set_dest)) + >= GET_MODE_BITSIZE (GET_MODE (m1->set_dest))))) + /* See if the source of M1 says it matches M. */ + && ((GET_CODE (m1->set_src) == REG + && matched_regs[REGNO (m1->set_src)]) + || rtx_equal_for_loop_p (m->set_src, m1->set_src, + movables)))) + && ((m->dependencies == m1->dependencies) + || rtx_equal_p (m->dependencies, m1->dependencies))) + { + m->lifetime += m1->lifetime; + m->savings += m1->savings; + m1->done = 1; + m1->match = m; + matched_regs[m1->regno] = 1; + } + } + + /* Now combine the regs used for zero-extension. + This can be done for those not marked `global' + provided their lives don't overlap. */ + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + { + register struct movable *m0 = 0; + + /* Combine all the registers for extension from mode MODE. + Don't combine any that are used outside this loop. */ + for (m = movables; m; m = m->next) + if (m->partial && ! m->global + && mode == GET_MODE (SET_SRC (PATTERN (NEXT_INSN (m->insn))))) + { + register struct movable *m1; + int first = uid_luid[regno_first_uid[m->regno]]; + int last = uid_luid[regno_last_uid[m->regno]]; + + if (m0 == 0) + { + /* First one: don't check for overlap, just record it. */ + m0 = m; + continue; + } + + /* Make sure they extend to the same mode. + (Almost always true.) */ + if (GET_MODE (m->set_dest) != GET_MODE (m0->set_dest)) + continue; + + /* We already have one: check for overlap with those + already combined together. */ + for (m1 = movables; m1 != m; m1 = m1->next) + if (m1 == m0 || (m1->partial && m1->match == m0)) + if (! (uid_luid[regno_first_uid[m1->regno]] > last + || uid_luid[regno_last_uid[m1->regno]] < first)) + goto overlap; + + /* No overlap: we can combine this with the others. */ + m0->lifetime += m->lifetime; + m0->savings += m->savings; + m->done = 1; + m->match = m0; + + overlap: ; + } + } +} + +/* Return 1 if regs X and Y will become the same if moved. */ + +static int +regs_match_p (x, y, movables) + rtx x, y; + struct movable *movables; +{ + int xn = REGNO (x); + int yn = REGNO (y); + struct movable *mx, *my; + + for (mx = movables; mx; mx = mx->next) + if (mx->regno == xn) + break; + + for (my = movables; my; my = my->next) + if (my->regno == yn) + break; + + return (mx && my + && ((mx->match == my->match && mx->match != 0) + || mx->match == my + || mx == my->match)); +} + +/* Return 1 if X and Y are identical-looking rtx's. + This is the Lisp function EQUAL for rtx arguments. + + If two registers are matching movables or a movable register and an + equivalent constant, consider them equal. */ + +static int +rtx_equal_for_loop_p (x, y, movables) + rtx x, y; + struct movable *movables; +{ + register int i; + register int j; + register struct movable *m; + register enum rtx_code code; + register char *fmt; + + if (x == y) + return 1; + if (x == 0 || y == 0) + return 0; + + code = GET_CODE (x); + + /* If we have a register and a constant, they may sometimes be + equal. */ + if (GET_CODE (x) == REG && n_times_set[REGNO (x)] == -2 + && CONSTANT_P (y)) + for (m = movables; m; m = m->next) + if (m->move_insn && m->regno == REGNO (x) + && rtx_equal_p (m->set_src, y)) + return 1; + + else if (GET_CODE (y) == REG && n_times_set[REGNO (y)] == -2 + && CONSTANT_P (x)) + for (m = movables; m; m = m->next) + if (m->move_insn && m->regno == REGNO (y) + && rtx_equal_p (m->set_src, x)) + return 1; + + /* Otherwise, rtx's of different codes cannot be equal. */ + if (code != GET_CODE (y)) + return 0; + + /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. + (REG:SI x) and (REG:HI x) are NOT equivalent. */ + + if (GET_MODE (x) != GET_MODE (y)) + return 0; + + /* These three types of rtx's can be compared nonrecursively. */ + if (code == REG) + return (REGNO (x) == REGNO (y) || regs_match_p (x, y, movables)); + + if (code == LABEL_REF) + return XEXP (x, 0) == XEXP (y, 0); + if (code == SYMBOL_REF) + return XSTR (x, 0) == XSTR (y, 0); + + /* Compare the elements. If any pair of corresponding elements + fail to match, return 0 for the whole things. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + switch (fmt[i]) + { + case 'w': + if (XWINT (x, i) != XWINT (y, i)) + return 0; + break; + + case 'i': + if (XINT (x, i) != XINT (y, i)) + return 0; + break; + + case 'E': + /* Two vectors must have the same length. */ + if (XVECLEN (x, i) != XVECLEN (y, i)) + return 0; + + /* And the corresponding elements must match. */ + for (j = 0; j < XVECLEN (x, i); j++) + if (rtx_equal_for_loop_p (XVECEXP (x, i, j), XVECEXP (y, i, j), movables) == 0) + return 0; + break; + + case 'e': + if (rtx_equal_for_loop_p (XEXP (x, i), XEXP (y, i), movables) == 0) + return 0; + break; + + case 's': + if (strcmp (XSTR (x, i), XSTR (y, i))) + return 0; + break; + + case 'u': + /* These are just backpointers, so they don't matter. */ + break; + + case '0': + break; + + /* It is believed that rtx's at this level will never + contain anything but integers and other rtx's, + except for within LABEL_REFs and SYMBOL_REFs. */ + default: + abort (); + } + } + return 1; +} + +/* If X contains any LABEL_REF's, add REG_LABEL notes for them to all + insns in INSNS which use thet reference. */ + +static void +add_label_notes (x, insns) + rtx x; + rtx insns; +{ + enum rtx_code code = GET_CODE (x); + int i, j; + char *fmt; + rtx insn; + + if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x)) + { + rtx next = next_real_insn (XEXP (x, 0)); + + /* Don't record labels that refer to dispatch tables. + This is not necessary, since the tablejump references the same label. + And if we did record them, flow.c would make worse code. */ + if (next == 0 + || ! (GET_CODE (next) == JUMP_INSN + && (GET_CODE (PATTERN (next)) == ADDR_VEC + || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC))) + { + for (insn = insns; insn; insn = NEXT_INSN (insn)) + if (reg_mentioned_p (XEXP (x, 0), insn)) + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL, XEXP (x, 0), + REG_NOTES (insn)); + } + return; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + add_label_notes (XEXP (x, i), insns); + else if (fmt[i] == 'E') + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + add_label_notes (XVECEXP (x, i, j), insns); + } +} + +/* Scan MOVABLES, and move the insns that deserve to be moved. + If two matching movables are combined, replace one reg with the + other throughout. */ + +static void +move_movables (movables, threshold, insn_count, loop_start, end, nregs) + struct movable *movables; + int threshold; + int insn_count; + rtx loop_start; + rtx end; + int nregs; +{ + rtx new_start = 0; + register struct movable *m; + register rtx p; + /* Map of pseudo-register replacements to handle combining + when we move several insns that load the same value + into different pseudo-registers. */ + rtx *reg_map = (rtx *) alloca (nregs * sizeof (rtx)); + char *already_moved = (char *) alloca (nregs); + + bzero (already_moved, nregs); + bzero (reg_map, nregs * sizeof (rtx)); + + num_movables = 0; + + for (m = movables; m; m = m->next) + { + /* Describe this movable insn. */ + + if (loop_dump_stream) + { + fprintf (loop_dump_stream, "Insn %d: regno %d (life %d), ", + INSN_UID (m->insn), m->regno, m->lifetime); + if (m->consec > 0) + fprintf (loop_dump_stream, "consec %d, ", m->consec); + if (m->cond) + fprintf (loop_dump_stream, "cond "); + if (m->force) + fprintf (loop_dump_stream, "force "); + if (m->global) + fprintf (loop_dump_stream, "global "); + if (m->done) + fprintf (loop_dump_stream, "done "); + if (m->move_insn) + fprintf (loop_dump_stream, "move-insn "); + if (m->match) + fprintf (loop_dump_stream, "matches %d ", + INSN_UID (m->match->insn)); + if (m->forces) + fprintf (loop_dump_stream, "forces %d ", + INSN_UID (m->forces->insn)); + } + + /* Count movables. Value used in heuristics in strength_reduce. */ + num_movables++; + + /* Ignore the insn if it's already done (it matched something else). + Otherwise, see if it is now safe to move. */ + + if (!m->done + && (! m->cond + || (1 == invariant_p (m->set_src) + && (m->dependencies == 0 + || 1 == invariant_p (m->dependencies)) + && (m->consec == 0 + || 1 == consec_sets_invariant_p (m->set_dest, + m->consec + 1, + m->insn)))) + && (! m->forces || m->forces->done)) + { + register int regno; + register rtx p; + int savings = m->savings; + + /* We have an insn that is safe to move. + Compute its desirability. */ + + p = m->insn; + regno = m->regno; + + if (loop_dump_stream) + fprintf (loop_dump_stream, "savings %d ", savings); + + if (moved_once[regno]) + { + insn_count *= 2; + + if (loop_dump_stream) + fprintf (loop_dump_stream, "halved since already moved "); + } + + /* An insn MUST be moved if we already moved something else + which is safe only if this one is moved too: that is, + if already_moved[REGNO] is nonzero. */ + + /* An insn is desirable to move if the new lifetime of the + register is no more than THRESHOLD times the old lifetime. + If it's not desirable, it means the loop is so big + that moving won't speed things up much, + and it is liable to make register usage worse. */ + + /* It is also desirable to move if it can be moved at no + extra cost because something else was already moved. */ + + if (already_moved[regno] + || (threshold * savings * m->lifetime) >= insn_count + || (m->forces && m->forces->done + && n_times_used[m->forces->regno] == 1)) + { + int count; + register struct movable *m1; + rtx first; + + /* Now move the insns that set the reg. */ + + if (m->partial && m->match) + { + rtx newpat, i1; + rtx r1, r2; + /* Find the end of this chain of matching regs. + Thus, we load each reg in the chain from that one reg. + And that reg is loaded with 0 directly, + since it has ->match == 0. */ + for (m1 = m; m1->match; m1 = m1->match); + newpat = gen_move_insn (SET_DEST (PATTERN (m->insn)), + SET_DEST (PATTERN (m1->insn))); + i1 = emit_insn_before (newpat, loop_start); + + /* Mark the moved, invariant reg as being allowed to + share a hard reg with the other matching invariant. */ + REG_NOTES (i1) = REG_NOTES (m->insn); + r1 = SET_DEST (PATTERN (m->insn)); + r2 = SET_DEST (PATTERN (m1->insn)); + regs_may_share = gen_rtx (EXPR_LIST, VOIDmode, r1, + gen_rtx (EXPR_LIST, VOIDmode, r2, + regs_may_share)); + delete_insn (m->insn); + + if (new_start == 0) + new_start = i1; + + if (loop_dump_stream) + fprintf (loop_dump_stream, " moved to %d", INSN_UID (i1)); + } + /* If we are to re-generate the item being moved with a + new move insn, first delete what we have and then emit + the move insn before the loop. */ + else if (m->move_insn) + { + rtx i1, temp; + + for (count = m->consec; count >= 0; count--) + { + /* If this is the first insn of a library call sequence, + skip to the end. */ + if (GET_CODE (p) != NOTE + && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) + p = XEXP (temp, 0); + + /* If this is the last insn of a libcall sequence, then + delete every insn in the sequence except the last. + The last insn is handled in the normal manner. */ + if (GET_CODE (p) != NOTE + && (temp = find_reg_note (p, REG_RETVAL, NULL_RTX))) + { + temp = XEXP (temp, 0); + while (temp != p) + temp = delete_insn (temp); + } + + p = delete_insn (p); + } + + start_sequence (); + emit_move_insn (m->set_dest, m->set_src); + temp = get_insns (); + end_sequence (); + + add_label_notes (m->set_src, temp); + + i1 = emit_insns_before (temp, loop_start); + if (! find_reg_note (i1, REG_EQUAL, NULL_RTX)) + REG_NOTES (i1) + = gen_rtx (EXPR_LIST, + m->is_equiv ? REG_EQUIV : REG_EQUAL, + m->set_src, REG_NOTES (i1)); + + if (loop_dump_stream) + fprintf (loop_dump_stream, " moved to %d", INSN_UID (i1)); + + /* The more regs we move, the less we like moving them. */ + threshold -= 3; + } + else + { + for (count = m->consec; count >= 0; count--) + { + rtx i1, temp; + + /* If first insn of libcall sequence, skip to end. */ + /* Do this at start of loop, since p is guaranteed to + be an insn here. */ + if (GET_CODE (p) != NOTE + && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) + p = XEXP (temp, 0); + + /* If last insn of libcall sequence, move all + insns except the last before the loop. The last + insn is handled in the normal manner. */ + if (GET_CODE (p) != NOTE + && (temp = find_reg_note (p, REG_RETVAL, NULL_RTX))) + { + rtx fn_address = 0; + rtx fn_reg = 0; + rtx fn_address_insn = 0; + + first = 0; + for (temp = XEXP (temp, 0); temp != p; + temp = NEXT_INSN (temp)) + { + rtx body; + rtx n; + rtx next; + + if (GET_CODE (temp) == NOTE) + continue; + + body = PATTERN (temp); + + /* Find the next insn after TEMP, + not counting USE or NOTE insns. */ + for (next = NEXT_INSN (temp); next != p; + next = NEXT_INSN (next)) + if (! (GET_CODE (next) == INSN + && GET_CODE (PATTERN (next)) == USE) + && GET_CODE (next) != NOTE) + break; + + /* If that is the call, this may be the insn + that loads the function address. + + Extract the function address from the insn + that loads it into a register. + If this insn was cse'd, we get incorrect code. + + So emit a new move insn that copies the + function address into the register that the + call insn will use. flow.c will delete any + redundant stores that we have created. */ + if (GET_CODE (next) == CALL_INSN + && GET_CODE (body) == SET + && GET_CODE (SET_DEST (body)) == REG + && (n = find_reg_note (temp, REG_EQUAL, + NULL_RTX))) + { + fn_reg = SET_SRC (body); + if (GET_CODE (fn_reg) != REG) + fn_reg = SET_DEST (body); + fn_address = XEXP (n, 0); + fn_address_insn = temp; + } + /* We have the call insn. + If it uses the register we suspect it might, + load it with the correct address directly. */ + if (GET_CODE (temp) == CALL_INSN + && fn_address != 0 + && reg_referenced_p (fn_reg, body)) + emit_insn_after (gen_move_insn (fn_reg, + fn_address), + fn_address_insn); + + if (GET_CODE (temp) == CALL_INSN) + i1 = emit_call_insn_before (body, loop_start); + else + i1 = emit_insn_before (body, loop_start); + if (first == 0) + first = i1; + if (temp == fn_address_insn) + fn_address_insn = i1; + REG_NOTES (i1) = REG_NOTES (temp); + delete_insn (temp); + } + } + if (m->savemode != VOIDmode) + { + /* P sets REG to zero; but we should clear only + the bits that are not covered by the mode + m->savemode. */ + rtx reg = m->set_dest; + rtx sequence; + rtx tem; + + start_sequence (); + tem = expand_binop + (GET_MODE (reg), and_optab, reg, + GEN_INT ((((HOST_WIDE_INT) 1 + << GET_MODE_BITSIZE (m->savemode))) + - 1), + reg, 1, OPTAB_LIB_WIDEN); + if (tem == 0) + abort (); + if (tem != reg) + emit_move_insn (reg, tem); + sequence = gen_sequence (); + end_sequence (); + i1 = emit_insn_before (sequence, loop_start); + } + else if (GET_CODE (p) == CALL_INSN) + i1 = emit_call_insn_before (PATTERN (p), loop_start); + else + i1 = emit_insn_before (PATTERN (p), loop_start); + + REG_NOTES (i1) = REG_NOTES (p); + + /* If there is a REG_EQUAL note present whose value is + not loop invariant, then delete it, since it may + cause problems with later optimization passes. + It is possible for cse to create such notes + like this as a result of record_jump_cond. */ + + if ((temp = find_reg_note (i1, REG_EQUAL, NULL_RTX)) + && ! invariant_p (XEXP (temp, 0))) + remove_note (i1, temp); + + if (new_start == 0) + new_start = i1; + + if (loop_dump_stream) + fprintf (loop_dump_stream, " moved to %d", + INSN_UID (i1)); + +#if 0 + /* This isn't needed because REG_NOTES is copied + below and is wrong since P might be a PARALLEL. */ + if (REG_NOTES (i1) == 0 + && ! m->partial /* But not if it's a zero-extend clr. */ + && ! m->global /* and not if used outside the loop + (since it might get set outside). */ + && CONSTANT_P (SET_SRC (PATTERN (p)))) + REG_NOTES (i1) + = gen_rtx (EXPR_LIST, REG_EQUAL, + SET_SRC (PATTERN (p)), REG_NOTES (i1)); +#endif + + /* If library call, now fix the REG_NOTES that contain + insn pointers, namely REG_LIBCALL on FIRST + and REG_RETVAL on I1. */ + if (temp = find_reg_note (i1, REG_RETVAL, NULL_RTX)) + { + XEXP (temp, 0) = first; + temp = find_reg_note (first, REG_LIBCALL, NULL_RTX); + XEXP (temp, 0) = i1; + } + + delete_insn (p); + do p = NEXT_INSN (p); + while (p && GET_CODE (p) == NOTE); + } + + /* The more regs we move, the less we like moving them. */ + threshold -= 3; + } + + /* Any other movable that loads the same register + MUST be moved. */ + already_moved[regno] = 1; + + /* This reg has been moved out of one loop. */ + moved_once[regno] = 1; + + /* The reg set here is now invariant. */ + if (! m->partial) + n_times_set[regno] = 0; + + m->done = 1; + + /* Change the length-of-life info for the register + to say it lives at least the full length of this loop. + This will help guide optimizations in outer loops. */ + + if (uid_luid[regno_first_uid[regno]] > INSN_LUID (loop_start)) + /* This is the old insn before all the moved insns. + We can't use the moved insn because it is out of range + in uid_luid. Only the old insns have luids. */ + regno_first_uid[regno] = INSN_UID (loop_start); + if (uid_luid[regno_last_uid[regno]] < INSN_LUID (end)) + regno_last_uid[regno] = INSN_UID (end); + + /* Combine with this moved insn any other matching movables. */ + + if (! m->partial) + for (m1 = movables; m1; m1 = m1->next) + if (m1->match == m) + { + rtx temp; + + /* Schedule the reg loaded by M1 + for replacement so that shares the reg of M. + If the modes differ (only possible in restricted + circumstances, make a SUBREG. */ + if (GET_MODE (m->set_dest) == GET_MODE (m1->set_dest)) + reg_map[m1->regno] = m->set_dest; + else + reg_map[m1->regno] + = gen_lowpart_common (GET_MODE (m1->set_dest), + m->set_dest); + + /* Get rid of the matching insn + and prevent further processing of it. */ + m1->done = 1; + + /* if library call, delete all insn except last, which + is deleted below */ + if (temp = find_reg_note (m1->insn, REG_RETVAL, + NULL_RTX)) + { + for (temp = XEXP (temp, 0); temp != m1->insn; + temp = NEXT_INSN (temp)) + delete_insn (temp); + } + delete_insn (m1->insn); + + /* Any other movable that loads the same register + MUST be moved. */ + already_moved[m1->regno] = 1; + + /* The reg merged here is now invariant, + if the reg it matches is invariant. */ + if (! m->partial) + n_times_set[m1->regno] = 0; + } + } + else if (loop_dump_stream) + fprintf (loop_dump_stream, "not desirable"); + } + else if (loop_dump_stream && !m->match) + fprintf (loop_dump_stream, "not safe"); + + if (loop_dump_stream) + fprintf (loop_dump_stream, "\n"); + } + + if (new_start == 0) + new_start = loop_start; + + /* Go through all the instructions in the loop, making + all the register substitutions scheduled in REG_MAP. */ + for (p = new_start; p != end; p = NEXT_INSN (p)) + if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN + || GET_CODE (p) == CALL_INSN) + { + replace_regs (PATTERN (p), reg_map, nregs, 0); + replace_regs (REG_NOTES (p), reg_map, nregs, 0); + INSN_CODE (p) = -1; + } +} + +#if 0 +/* Scan X and replace the address of any MEM in it with ADDR. + REG is the address that MEM should have before the replacement. */ + +static void +replace_call_address (x, reg, addr) + rtx x, reg, addr; +{ + register enum rtx_code code; + register int i; + register char *fmt; + + if (x == 0) + return; + code = GET_CODE (x); + switch (code) + { + case PC: + case CC0: + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + case REG: + return; + + case SET: + /* Short cut for very common case. */ + replace_call_address (XEXP (x, 1), reg, addr); + return; + + case CALL: + /* Short cut for very common case. */ + replace_call_address (XEXP (x, 0), reg, addr); + return; + + case MEM: + /* If this MEM uses a reg other than the one we expected, + something is wrong. */ + if (XEXP (x, 0) != reg) + abort (); + XEXP (x, 0) = addr; + return; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + replace_call_address (XEXP (x, i), reg, addr); + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + replace_call_address (XVECEXP (x, i, j), reg, addr); + } + } +} +#endif + +/* Return the number of memory refs to addresses that vary + in the rtx X. */ + +static int +count_nonfixed_reads (x) + rtx x; +{ + register enum rtx_code code; + register int i; + register char *fmt; + int value; + + if (x == 0) + return 0; + + code = GET_CODE (x); + switch (code) + { + case PC: + case CC0: + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + case REG: + return 0; + + case MEM: + return ((invariant_p (XEXP (x, 0)) != 1) + + count_nonfixed_reads (XEXP (x, 0))); + } + + value = 0; + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + value += count_nonfixed_reads (XEXP (x, i)); + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + value += count_nonfixed_reads (XVECEXP (x, i, j)); + } + } + return value; +} + + +#if 0 +/* P is an instruction that sets a register to the result of a ZERO_EXTEND. + Replace it with an instruction to load just the low bytes + if the machine supports such an instruction, + and insert above LOOP_START an instruction to clear the register. */ + +static void +constant_high_bytes (p, loop_start) + rtx p, loop_start; +{ + register rtx new; + register int insn_code_number; + + /* Try to change (SET (REG ...) (ZERO_EXTEND (..:B ...))) + to (SET (STRICT_LOW_PART (SUBREG:B (REG...))) ...). */ + + new = gen_rtx (SET, VOIDmode, + gen_rtx (STRICT_LOW_PART, VOIDmode, + gen_rtx (SUBREG, GET_MODE (XEXP (SET_SRC (PATTERN (p)), 0)), + SET_DEST (PATTERN (p)), + 0)), + XEXP (SET_SRC (PATTERN (p)), 0)); + insn_code_number = recog (new, p); + + if (insn_code_number) + { + register int i; + + /* Clear destination register before the loop. */ + emit_insn_before (gen_rtx (SET, VOIDmode, + SET_DEST (PATTERN (p)), + const0_rtx), + loop_start); + + /* Inside the loop, just load the low part. */ + PATTERN (p) = new; + } +} +#endif + +/* Scan a loop setting the variables `unknown_address_altered', + `num_mem_sets', `loop_continue', loops_enclosed', `loop_has_call', + and `loop_has_volatile'. + Also, fill in the array `loop_store_mems'. */ + +static void +prescan_loop (start, end) + rtx start, end; +{ + register int level = 1; + register rtx insn; + + unknown_address_altered = 0; + loop_has_call = 0; + loop_has_volatile = 0; + loop_store_mems_idx = 0; + + num_mem_sets = 0; + loops_enclosed = 1; + loop_continue = 0; + + for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); + insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == NOTE) + { + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) + { + ++level; + /* Count number of loops contained in this one. */ + loops_enclosed++; + } + else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) + { + --level; + if (level == 0) + { + end = insn; + break; + } + } + else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_CONT) + { + if (level == 1) + loop_continue = insn; + } + } + else if (GET_CODE (insn) == CALL_INSN) + { + unknown_address_altered = 1; + loop_has_call = 1; + } + else + { + if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) + { + if (volatile_refs_p (PATTERN (insn))) + loop_has_volatile = 1; + + note_stores (PATTERN (insn), note_addr_stored); + } + } + } +} + +/* Scan the function looking for loops. Record the start and end of each loop. + Also mark as invalid loops any loops that contain a setjmp or are branched + to from outside the loop. */ + +static void +find_and_verify_loops (f) + rtx f; +{ + rtx insn, label; + int current_loop = -1; + int next_loop = -1; + int loop; + + /* If there are jumps to undefined labels, + treat them as jumps out of any/all loops. + This also avoids writing past end of tables when there are no loops. */ + uid_loop_num[0] = -1; + + /* Find boundaries of loops, mark which loops are contained within + loops, and invalidate loops that have setjmp. */ + + for (insn = f; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == NOTE) + switch (NOTE_LINE_NUMBER (insn)) + { + case NOTE_INSN_LOOP_BEG: + loop_number_loop_starts[++next_loop] = insn; + loop_number_loop_ends[next_loop] = 0; + loop_outer_loop[next_loop] = current_loop; + loop_invalid[next_loop] = 0; + loop_number_exit_labels[next_loop] = 0; + current_loop = next_loop; + break; + + case NOTE_INSN_SETJMP: + /* In this case, we must invalidate our current loop and any + enclosing loop. */ + for (loop = current_loop; loop != -1; loop = loop_outer_loop[loop]) + { + loop_invalid[loop] = 1; + if (loop_dump_stream) + fprintf (loop_dump_stream, + "\nLoop at %d ignored due to setjmp.\n", + INSN_UID (loop_number_loop_starts[loop])); + } + break; + + case NOTE_INSN_LOOP_END: + if (current_loop == -1) + abort (); + + loop_number_loop_ends[current_loop] = insn; + current_loop = loop_outer_loop[current_loop]; + break; + + } + + /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the + enclosing loop, but this doesn't matter. */ + uid_loop_num[INSN_UID (insn)] = current_loop; + } + + /* Any loop containing a label used in an initializer must be invalidated, + because it can be jumped into from anywhere. */ + + for (label = forced_labels; label; label = XEXP (label, 1)) + { + int loop_num; + + for (loop_num = uid_loop_num[INSN_UID (XEXP (label, 0))]; + loop_num != -1; + loop_num = loop_outer_loop[loop_num]) + loop_invalid[loop_num] = 1; + } + + /* Now scan all insn's in the function. If any JUMP_INSN branches into a + loop that it is not contained within, that loop is marked invalid. + If any INSN or CALL_INSN uses a label's address, then the loop containing + that label is marked invalid, because it could be jumped into from + anywhere. + + Also look for blocks of code ending in an unconditional branch that + exits the loop. If such a block is surrounded by a conditional + branch around the block, move the block elsewhere (see below) and + invert the jump to point to the code block. This may eliminate a + label in our loop and will simplify processing by both us and a + possible second cse pass. */ + + for (insn = f; insn; insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + int this_loop_num = uid_loop_num[INSN_UID (insn)]; + + if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) + { + rtx note = find_reg_note (insn, REG_LABEL, NULL_RTX); + if (note) + { + int loop_num; + + for (loop_num = uid_loop_num[INSN_UID (XEXP (note, 0))]; + loop_num != -1; + loop_num = loop_outer_loop[loop_num]) + loop_invalid[loop_num] = 1; + } + } + + if (GET_CODE (insn) != JUMP_INSN) + continue; + + mark_loop_jump (PATTERN (insn), this_loop_num); + + /* See if this is an unconditional branch outside the loop. */ + if (this_loop_num != -1 + && (GET_CODE (PATTERN (insn)) == RETURN + || (simplejump_p (insn) + && (uid_loop_num[INSN_UID (JUMP_LABEL (insn))] + != this_loop_num))) + && get_max_uid () < max_uid_for_loop) + { + rtx p; + rtx our_next = next_real_insn (insn); + + /* Go backwards until we reach the start of the loop, a label, + or a JUMP_INSN. */ + for (p = PREV_INSN (insn); + GET_CODE (p) != CODE_LABEL + && ! (GET_CODE (p) == NOTE + && NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG) + && GET_CODE (p) != JUMP_INSN; + p = PREV_INSN (p)) + ; + + /* If we stopped on a JUMP_INSN to the next insn after INSN, + we have a block of code to try to move. + + We look backward and then forward from the target of INSN + to find a BARRIER at the same loop depth as the target. + If we find such a BARRIER, we make a new label for the start + of the block, invert the jump in P and point it to that label, + and move the block of code to the spot we found. */ + + if (GET_CODE (p) == JUMP_INSN + && JUMP_LABEL (p) != 0 + /* Just ignore jumps to labels that were never emitted. + These always indicate compilation errors. */ + && INSN_UID (JUMP_LABEL (p)) != 0 + && condjump_p (p) + && ! simplejump_p (p) + && next_real_insn (JUMP_LABEL (p)) == our_next) + { + rtx target + = JUMP_LABEL (insn) ? JUMP_LABEL (insn) : get_last_insn (); + int target_loop_num = uid_loop_num[INSN_UID (target)]; + rtx loc; + + for (loc = target; loc; loc = PREV_INSN (loc)) + if (GET_CODE (loc) == BARRIER + && uid_loop_num[INSN_UID (loc)] == target_loop_num) + break; + + if (loc == 0) + for (loc = target; loc; loc = NEXT_INSN (loc)) + if (GET_CODE (loc) == BARRIER + && uid_loop_num[INSN_UID (loc)] == target_loop_num) + break; + + if (loc) + { + rtx cond_label = JUMP_LABEL (p); + rtx new_label = get_label_after (p); + + /* Ensure our label doesn't go away. */ + LABEL_NUSES (cond_label)++; + + /* Verify that uid_loop_num is large enough and that + we can invert P. */ + if (invert_jump (p, new_label)) + { + rtx q, r; + + /* Include the BARRIER after INSN and copy the + block after LOC. */ + new_label = squeeze_notes (new_label, NEXT_INSN (insn)); + reorder_insns (new_label, NEXT_INSN (insn), loc); + + /* All those insns are now in TARGET_LOOP_NUM. */ + for (q = new_label; q != NEXT_INSN (NEXT_INSN (insn)); + q = NEXT_INSN (q)) + uid_loop_num[INSN_UID (q)] = target_loop_num; + + /* The label jumped to by INSN is no longer a loop exit. + Unless INSN does not have a label (e.g., it is a + RETURN insn), search loop_number_exit_labels to find + its label_ref, and remove it. Also turn off + LABEL_OUTSIDE_LOOP_P bit. */ + if (JUMP_LABEL (insn)) + { + for (q = 0, + r = loop_number_exit_labels[this_loop_num]; + r; q = r, r = LABEL_NEXTREF (r)) + if (XEXP (r, 0) == JUMP_LABEL (insn)) + { + LABEL_OUTSIDE_LOOP_P (r) = 0; + if (q) + LABEL_NEXTREF (q) = LABEL_NEXTREF (r); + else + loop_number_exit_labels[this_loop_num] + = LABEL_NEXTREF (r); + break; + } + + /* If we didn't find it, then something is wrong. */ + if (! r) + abort (); + } + + /* P is now a jump outside the loop, so it must be put + in loop_number_exit_labels, and marked as such. + The easiest way to do this is to just call + mark_loop_jump again for P. */ + mark_loop_jump (PATTERN (p), this_loop_num); + + /* If INSN now jumps to the insn after it, + delete INSN. */ + if (JUMP_LABEL (insn) != 0 + && (next_real_insn (JUMP_LABEL (insn)) + == next_real_insn (insn))) + delete_insn (insn); + } + + /* Continue the loop after where the conditional + branch used to jump, since the only branch insn + in the block (if it still remains) is an inter-loop + branch and hence needs no processing. */ + insn = NEXT_INSN (cond_label); + + if (--LABEL_NUSES (cond_label) == 0) + delete_insn (cond_label); + } + } + } + } +} + +/* If any label in X jumps to a loop different from LOOP_NUM and any of the + loops it is contained in, mark the target loop invalid. + + For speed, we assume that X is part of a pattern of a JUMP_INSN. */ + +static void +mark_loop_jump (x, loop_num) + rtx x; + int loop_num; +{ + int dest_loop; + int outer_loop; + int i; + + switch (GET_CODE (x)) + { + case PC: + case USE: + case CLOBBER: + case REG: + case MEM: + case CONST_INT: + case CONST_DOUBLE: + case RETURN: + return; + + case CONST: + /* There could be a label reference in here. */ + mark_loop_jump (XEXP (x, 0), loop_num); + return; + + case PLUS: + case MINUS: + case MULT: + case LSHIFT: + mark_loop_jump (XEXP (x, 0), loop_num); + mark_loop_jump (XEXP (x, 1), loop_num); + return; + + case SIGN_EXTEND: + case ZERO_EXTEND: + mark_loop_jump (XEXP (x, 0), loop_num); + return; + + case LABEL_REF: + dest_loop = uid_loop_num[INSN_UID (XEXP (x, 0))]; + + /* Link together all labels that branch outside the loop. This + is used by final_[bg]iv_value and the loop unrolling code. Also + mark this LABEL_REF so we know that this branch should predict + false. */ + + if (dest_loop != loop_num && loop_num != -1) + { + LABEL_OUTSIDE_LOOP_P (x) = 1; + LABEL_NEXTREF (x) = loop_number_exit_labels[loop_num]; + loop_number_exit_labels[loop_num] = x; + } + + /* If this is inside a loop, but not in the current loop or one enclosed + by it, it invalidates at least one loop. */ + + if (dest_loop == -1) + return; + + /* We must invalidate every nested loop containing the target of this + label, except those that also contain the jump insn. */ + + for (; dest_loop != -1; dest_loop = loop_outer_loop[dest_loop]) + { + /* Stop when we reach a loop that also contains the jump insn. */ + for (outer_loop = loop_num; outer_loop != -1; + outer_loop = loop_outer_loop[outer_loop]) + if (dest_loop == outer_loop) + return; + + /* If we get here, we know we need to invalidate a loop. */ + if (loop_dump_stream && ! loop_invalid[dest_loop]) + fprintf (loop_dump_stream, + "\nLoop at %d ignored due to multiple entry points.\n", + INSN_UID (loop_number_loop_starts[dest_loop])); + + loop_invalid[dest_loop] = 1; + } + return; + + case SET: + /* If this is not setting pc, ignore. */ + if (SET_DEST (x) == pc_rtx) + mark_loop_jump (SET_SRC (x), loop_num); + return; + + case IF_THEN_ELSE: + mark_loop_jump (XEXP (x, 1), loop_num); + mark_loop_jump (XEXP (x, 2), loop_num); + return; + + case PARALLEL: + case ADDR_VEC: + for (i = 0; i < XVECLEN (x, 0); i++) + mark_loop_jump (XVECEXP (x, 0, i), loop_num); + return; + + case ADDR_DIFF_VEC: + for (i = 0; i < XVECLEN (x, 1); i++) + mark_loop_jump (XVECEXP (x, 1, i), loop_num); + return; + + default: + /* Nothing else should occur in a JUMP_INSN. */ + abort (); + } +} + +/* Return nonzero if there is a label in the range from + insn INSN to and including the insn whose luid is END + INSN must have an assigned luid (i.e., it must not have + been previously created by loop.c). */ + +static int +labels_in_range_p (insn, end) + rtx insn; + int end; +{ + while (insn && INSN_LUID (insn) <= end) + { + if (GET_CODE (insn) == CODE_LABEL) + return 1; + insn = NEXT_INSN (insn); + } + + return 0; +} + +/* Record that a memory reference X is being set. */ + +static void +note_addr_stored (x) + rtx x; +{ + register int i; + + if (x == 0 || GET_CODE (x) != MEM) + return; + + /* Count number of memory writes. + This affects heuristics in strength_reduce. */ + num_mem_sets++; + + if (unknown_address_altered) + return; + + for (i = 0; i < loop_store_mems_idx; i++) + if (rtx_equal_p (XEXP (loop_store_mems[i], 0), XEXP (x, 0)) + && MEM_IN_STRUCT_P (x) == MEM_IN_STRUCT_P (loop_store_mems[i])) + { + /* We are storing at the same address as previously noted. Save the + wider reference, treating BLKmode as wider. */ + if (GET_MODE (x) == BLKmode + || (GET_MODE_SIZE (GET_MODE (x)) + > GET_MODE_SIZE (GET_MODE (loop_store_mems[i])))) + loop_store_mems[i] = x; + break; + } + + if (i == NUM_STORES) + unknown_address_altered = 1; + + else if (i == loop_store_mems_idx) + loop_store_mems[loop_store_mems_idx++] = x; +} + +/* Return nonzero if the rtx X is invariant over the current loop. + + The value is 2 if we refer to something only conditionally invariant. + + If `unknown_address_altered' is nonzero, no memory ref is invariant. + Otherwise, a memory ref is invariant if it does not conflict with + anything stored in `loop_store_mems'. */ + +int +invariant_p (x) + register rtx x; +{ + register int i; + register enum rtx_code code; + register char *fmt; + int conditional = 0; + + if (x == 0) + return 1; + code = GET_CODE (x); + switch (code) + { + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CONST: + return 1; + + case LABEL_REF: + /* A LABEL_REF is normally invariant, however, if we are unrolling + loops, and this label is inside the loop, then it isn't invariant. + This is because each unrolled copy of the loop body will have + a copy of this label. If this was invariant, then an insn loading + the address of this label into a register might get moved outside + the loop, and then each loop body would end up using the same label. + + We don't know the loop bounds here though, so just fail for all + labels. */ + if (flag_unroll_loops) + return 0; + else + return 1; + + case PC: + case CC0: + case UNSPEC_VOLATILE: + return 0; + + case REG: + /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid + since the reg might be set by initialization within the loop. */ + if (x == frame_pointer_rtx || x == arg_pointer_rtx) + return 1; + if (loop_has_call + && REGNO (x) < FIRST_PSEUDO_REGISTER && call_used_regs[REGNO (x)]) + return 0; + if (n_times_set[REGNO (x)] < 0) + return 2; + return n_times_set[REGNO (x)] == 0; + + case MEM: + /* Read-only items (such as constants in a constant pool) are + invariant if their address is. */ + if (RTX_UNCHANGING_P (x)) + break; + + /* If we filled the table (or had a subroutine call), any location + in memory could have been clobbered. */ + if (unknown_address_altered + /* Don't mess with volatile memory references. */ + || MEM_VOLATILE_P (x)) + return 0; + + /* See if there is any dependence between a store and this load. */ + for (i = loop_store_mems_idx - 1; i >= 0; i--) + if (true_dependence (loop_store_mems[i], x)) + return 0; + + /* It's not invalidated by a store in memory + but we must still verify the address is invariant. */ + break; + + case ASM_OPERANDS: + /* Don't mess with insns declared volatile. */ + if (MEM_VOLATILE_P (x)) + return 0; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + { + int tem = invariant_p (XEXP (x, i)); + if (tem == 0) + return 0; + if (tem == 2) + conditional = 1; + } + else if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + { + int tem = invariant_p (XVECEXP (x, i, j)); + if (tem == 0) + return 0; + if (tem == 2) + conditional = 1; + } + + } + } + + return 1 + conditional; +} + + +/* Return nonzero if all the insns in the loop that set REG + are INSN and the immediately following insns, + and if each of those insns sets REG in an invariant way + (not counting uses of REG in them). + + The value is 2 if some of these insns are only conditionally invariant. + + We assume that INSN itself is the first set of REG + and that its source is invariant. */ + +static int +consec_sets_invariant_p (reg, n_sets, insn) + int n_sets; + rtx reg, insn; +{ + register rtx p = insn; + register int regno = REGNO (reg); + rtx temp; + /* Number of sets we have to insist on finding after INSN. */ + int count = n_sets - 1; + int old = n_times_set[regno]; + int value = 0; + int this; + + /* If N_SETS hit the limit, we can't rely on its value. */ + if (n_sets == 127) + return 0; + + n_times_set[regno] = 0; + + while (count > 0) + { + register enum rtx_code code; + rtx set; + + p = NEXT_INSN (p); + code = GET_CODE (p); + + /* If library call, skip to end of of it. */ + if (code == INSN && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) + p = XEXP (temp, 0); + + this = 0; + if (code == INSN + && (set = single_set (p)) + && GET_CODE (SET_DEST (set)) == REG + && REGNO (SET_DEST (set)) == regno) + { + this = invariant_p (SET_SRC (set)); + if (this != 0) + value |= this; + else if (temp = find_reg_note (p, REG_EQUAL, NULL_RTX)) + { + /* If this is a libcall, then any invariant REG_EQUAL note is OK. + If this is an ordinary insn, then only CONSTANT_P REG_EQUAL + notes are OK. */ + this = (CONSTANT_P (XEXP (temp, 0)) + || (find_reg_note (p, REG_RETVAL, NULL_RTX) + && invariant_p (XEXP (temp, 0)))); + if (this != 0) + value |= this; + } + } + if (this != 0) + count--; + else if (code != NOTE) + { + n_times_set[regno] = old; + return 0; + } + } + + n_times_set[regno] = old; + /* If invariant_p ever returned 2, we return 2. */ + return 1 + (value & 2); +} + +#if 0 +/* I don't think this condition is sufficient to allow INSN + to be moved, so we no longer test it. */ + +/* Return 1 if all insns in the basic block of INSN and following INSN + that set REG are invariant according to TABLE. */ + +static int +all_sets_invariant_p (reg, insn, table) + rtx reg, insn; + short *table; +{ + register rtx p = insn; + register int regno = REGNO (reg); + + while (1) + { + register enum rtx_code code; + p = NEXT_INSN (p); + code = GET_CODE (p); + if (code == CODE_LABEL || code == JUMP_INSN) + return 1; + if (code == INSN && GET_CODE (PATTERN (p)) == SET + && GET_CODE (SET_DEST (PATTERN (p))) == REG + && REGNO (SET_DEST (PATTERN (p))) == regno) + { + if (!invariant_p (SET_SRC (PATTERN (p)), table)) + return 0; + } + } +} +#endif /* 0 */ + +/* Look at all uses (not sets) of registers in X. For each, if it is + the single use, set USAGE[REGNO] to INSN; if there was a previous use in + a different insn, set USAGE[REGNO] to const0_rtx. */ + +static void +find_single_use_in_loop (insn, x, usage) + rtx insn; + rtx x; + rtx *usage; +{ + enum rtx_code code = GET_CODE (x); + char *fmt = GET_RTX_FORMAT (code); + int i, j; + + if (code == REG) + usage[REGNO (x)] + = (usage[REGNO (x)] != 0 && usage[REGNO (x)] != insn) + ? const0_rtx : insn; + + else if (code == SET) + { + /* Don't count SET_DEST if it is a REG; otherwise count things + in SET_DEST because if a register is partially modified, it won't + show up as a potential movable so we don't care how USAGE is set + for it. */ + if (GET_CODE (SET_DEST (x)) != REG) + find_single_use_in_loop (insn, SET_DEST (x), usage); + find_single_use_in_loop (insn, SET_SRC (x), usage); + } + else + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e' && XEXP (x, i) != 0) + find_single_use_in_loop (insn, XEXP (x, i), usage); + else if (fmt[i] == 'E') + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + find_single_use_in_loop (insn, XVECEXP (x, i, j), usage); + } +} + +/* Increment N_TIMES_SET at the index of each register + that is modified by an insn between FROM and TO. + If the value of an element of N_TIMES_SET becomes 127 or more, + stop incrementing it, to avoid overflow. + + Store in SINGLE_USAGE[I] the single insn in which register I is + used, if it is only used once. Otherwise, it is set to 0 (for no + uses) or const0_rtx for more than one use. This parameter may be zero, + in which case this processing is not done. + + Store in *COUNT_PTR the number of actual instruction + in the loop. We use this to decide what is worth moving out. */ + +/* last_set[n] is nonzero iff reg n has been set in the current basic block. + In that case, it is the insn that last set reg n. */ + +static void +count_loop_regs_set (from, to, may_not_move, single_usage, count_ptr, nregs) + register rtx from, to; + char *may_not_move; + rtx *single_usage; + int *count_ptr; + int nregs; +{ + register rtx *last_set = (rtx *) alloca (nregs * sizeof (rtx)); + register rtx insn; + register int count = 0; + register rtx dest; + + bzero (last_set, nregs * sizeof (rtx)); + for (insn = from; insn != to; insn = NEXT_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + ++count; + + /* If requested, record registers that have exactly one use. */ + if (single_usage) + { + find_single_use_in_loop (insn, PATTERN (insn), single_usage); + + /* Include uses in REG_EQUAL notes. */ + if (REG_NOTES (insn)) + find_single_use_in_loop (insn, REG_NOTES (insn), single_usage); + } + + if (GET_CODE (PATTERN (insn)) == CLOBBER + && GET_CODE (XEXP (PATTERN (insn), 0)) == REG) + /* Don't move a reg that has an explicit clobber. + We might do so sometimes, but it's not worth the pain. */ + may_not_move[REGNO (XEXP (PATTERN (insn), 0))] = 1; + + if (GET_CODE (PATTERN (insn)) == SET + || GET_CODE (PATTERN (insn)) == CLOBBER) + { + dest = SET_DEST (PATTERN (insn)); + while (GET_CODE (dest) == SUBREG + || GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == SIGN_EXTRACT + || GET_CODE (dest) == STRICT_LOW_PART) + dest = XEXP (dest, 0); + if (GET_CODE (dest) == REG) + { + register int regno = REGNO (dest); + /* If this is the first setting of this reg + in current basic block, and it was set before, + it must be set in two basic blocks, so it cannot + be moved out of the loop. */ + if (n_times_set[regno] > 0 && last_set[regno] == 0) + may_not_move[regno] = 1; + /* If this is not first setting in current basic block, + see if reg was used in between previous one and this. + If so, neither one can be moved. */ + if (last_set[regno] != 0 + && reg_used_between_p (dest, last_set[regno], insn)) + may_not_move[regno] = 1; + if (n_times_set[regno] < 127) + ++n_times_set[regno]; + last_set[regno] = insn; + } + } + else if (GET_CODE (PATTERN (insn)) == PARALLEL) + { + register int i; + for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) + { + register rtx x = XVECEXP (PATTERN (insn), 0, i); + if (GET_CODE (x) == CLOBBER && GET_CODE (XEXP (x, 0)) == REG) + /* Don't move a reg that has an explicit clobber. + It's not worth the pain to try to do it correctly. */ + may_not_move[REGNO (XEXP (x, 0))] = 1; + + if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) + { + dest = SET_DEST (x); + while (GET_CODE (dest) == SUBREG + || GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == SIGN_EXTRACT + || GET_CODE (dest) == STRICT_LOW_PART) + dest = XEXP (dest, 0); + if (GET_CODE (dest) == REG) + { + register int regno = REGNO (dest); + if (n_times_set[regno] > 0 && last_set[regno] == 0) + may_not_move[regno] = 1; + if (last_set[regno] != 0 + && reg_used_between_p (dest, last_set[regno], insn)) + may_not_move[regno] = 1; + if (n_times_set[regno] < 127) + ++n_times_set[regno]; + last_set[regno] = insn; + } + } + } + } + } + if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN) + bzero (last_set, nregs * sizeof (rtx)); + } + *count_ptr = count; +} + +/* Given a loop that is bounded by LOOP_START and LOOP_END + and that is entered at SCAN_START, + return 1 if the register set in SET contained in insn INSN is used by + any insn that precedes INSN in cyclic order starting + from the loop entry point. + + We don't want to use INSN_LUID here because if we restrict INSN to those + that have a valid INSN_LUID, it means we cannot move an invariant out + from an inner loop past two loops. */ + +static int +loop_reg_used_before_p (set, insn, loop_start, scan_start, loop_end) + rtx set, insn, loop_start, scan_start, loop_end; +{ + rtx reg = SET_DEST (set); + rtx p; + + /* Scan forward checking for register usage. If we hit INSN, we + are done. Otherwise, if we hit LOOP_END, wrap around to LOOP_START. */ + for (p = scan_start; p != insn; p = NEXT_INSN (p)) + { + if (GET_RTX_CLASS (GET_CODE (p)) == 'i' + && reg_overlap_mentioned_p (reg, PATTERN (p))) + return 1; + + if (p == loop_end) + p = loop_start; + } + + return 0; +} + +/* A "basic induction variable" or biv is a pseudo reg that is set + (within this loop) only by incrementing or decrementing it. */ +/* A "general induction variable" or giv is a pseudo reg whose + value is a linear function of a biv. */ + +/* Bivs are recognized by `basic_induction_var'; + Givs by `general_induct_var'. */ + +/* Indexed by register number, indicates whether or not register is an + induction variable, and if so what type. */ + +enum iv_mode *reg_iv_type; + +/* Indexed by register number, contains pointer to `struct induction' + if register is an induction variable. This holds general info for + all induction variables. */ + +struct induction **reg_iv_info; + +/* Indexed by register number, contains pointer to `struct iv_class' + if register is a basic induction variable. This holds info describing + the class (a related group) of induction variables that the biv belongs + to. */ + +struct iv_class **reg_biv_class; + +/* The head of a list which links together (via the next field) + every iv class for the current loop. */ + +struct iv_class *loop_iv_list; + +/* Communication with routines called via `note_stores'. */ + +static rtx note_insn; + +/* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */ + +static rtx addr_placeholder; + +/* ??? Unfinished optimizations, and possible future optimizations, + for the strength reduction code. */ + +/* ??? There is one more optimization you might be interested in doing: to + allocate pseudo registers for frequently-accessed memory locations. + If the same memory location is referenced each time around, it might + be possible to copy it into a register before and out after. + This is especially useful when the memory location is a variable which + is in a stack slot because somewhere its address is taken. If the + loop doesn't contain a function call and the variable isn't volatile, + it is safe to keep the value in a register for the duration of the + loop. One tricky thing is that the copying of the value back from the + register has to be done on all exits from the loop. You need to check that + all the exits from the loop go to the same place. */ + +/* ??? The interaction of biv elimination, and recognition of 'constant' + bivs, may cause problems. */ + +/* ??? Add heuristics so that DEST_ADDR strength reduction does not cause + performance problems. + + Perhaps don't eliminate things that can be combined with an addressing + mode. Find all givs that have the same biv, mult_val, and add_val; + then for each giv, check to see if its only use dies in a following + memory address. If so, generate a new memory address and check to see + if it is valid. If it is valid, then store the modified memory address, + otherwise, mark the giv as not done so that it will get its own iv. */ + +/* ??? Could try to optimize branches when it is known that a biv is always + positive. */ + +/* ??? When replace a biv in a compare insn, we should replace with closest + giv so that an optimized branch can still be recognized by the combiner, + e.g. the VAX acb insn. */ + +/* ??? Many of the checks involving uid_luid could be simplified if regscan + was rerun in loop_optimize whenever a register was added or moved. + Also, some of the optimizations could be a little less conservative. */ + +/* Perform strength reduction and induction variable elimination. */ + +/* Pseudo registers created during this function will be beyond the last + valid index in several tables including n_times_set and regno_last_uid. + This does not cause a problem here, because the added registers cannot be + givs outside of their loop, and hence will never be reconsidered. + But scan_loop must check regnos to make sure they are in bounds. */ + +static void +strength_reduce (scan_start, end, loop_top, insn_count, + loop_start, loop_end) + rtx scan_start; + rtx end; + rtx loop_top; + int insn_count; + rtx loop_start; + rtx loop_end; +{ + rtx p; + rtx set; + rtx inc_val; + rtx mult_val; + rtx dest_reg; + /* This is 1 if current insn is not executed at least once for every loop + iteration. */ + int not_every_iteration = 0; + /* This is 1 if current insn may be executed more than once for every + loop iteration. */ + int maybe_multiple = 0; + /* Temporary list pointers for traversing loop_iv_list. */ + struct iv_class *bl, **backbl; + /* Ratio of extra register life span we can justify + for saving an instruction. More if loop doesn't call subroutines + since in that case saving an insn makes more difference + and more registers are available. */ + /* ??? could set this to last value of threshold in move_movables */ + int threshold = (loop_has_call ? 1 : 2) * (3 + n_non_fixed_regs); + /* Map of pseudo-register replacements. */ + rtx *reg_map; + int call_seen; + rtx test; + rtx end_insert_before; + + reg_iv_type = (enum iv_mode *) alloca (max_reg_before_loop + * sizeof (enum iv_mode *)); + bzero ((char *) reg_iv_type, max_reg_before_loop * sizeof (enum iv_mode *)); + reg_iv_info = (struct induction **) + alloca (max_reg_before_loop * sizeof (struct induction *)); + bzero ((char *) reg_iv_info, (max_reg_before_loop + * sizeof (struct induction *))); + reg_biv_class = (struct iv_class **) + alloca (max_reg_before_loop * sizeof (struct iv_class *)); + bzero ((char *) reg_biv_class, (max_reg_before_loop + * sizeof (struct iv_class *))); + + loop_iv_list = 0; + addr_placeholder = gen_reg_rtx (Pmode); + + /* Save insn immediately after the loop_end. Insns inserted after loop_end + must be put before this insn, so that they will appear in the right + order (i.e. loop order). + + If loop_end is the end of the current function, then emit a + NOTE_INSN_DELETED after loop_end and set end_insert_before to the + dummy note insn. */ + if (NEXT_INSN (loop_end) != 0) + end_insert_before = NEXT_INSN (loop_end); + else + end_insert_before = emit_note_after (NOTE_INSN_DELETED, loop_end); + + /* Scan through loop to find all possible bivs. */ + + p = scan_start; + while (1) + { + p = NEXT_INSN (p); + /* At end of a straight-in loop, we are done. + At end of a loop entered at the bottom, scan the top. */ + if (p == scan_start) + break; + if (p == end) + { + if (loop_top != 0) + p = NEXT_INSN (loop_top); + else + break; + if (p == scan_start) + break; + } + + if (GET_CODE (p) == INSN + && (set = single_set (p)) + && GET_CODE (SET_DEST (set)) == REG) + { + dest_reg = SET_DEST (set); + if (REGNO (dest_reg) < max_reg_before_loop + && REGNO (dest_reg) >= FIRST_PSEUDO_REGISTER + && reg_iv_type[REGNO (dest_reg)] != NOT_BASIC_INDUCT) + { + if (basic_induction_var (SET_SRC (set), dest_reg, p, + &inc_val, &mult_val)) + { + /* It is a possible basic induction variable. + Create and initialize an induction structure for it. */ + + struct induction *v + = (struct induction *) alloca (sizeof (struct induction)); + + record_biv (v, p, dest_reg, inc_val, mult_val, + not_every_iteration, maybe_multiple); + reg_iv_type[REGNO (dest_reg)] = BASIC_INDUCT; + } + else if (REGNO (dest_reg) < max_reg_before_loop) + reg_iv_type[REGNO (dest_reg)] = NOT_BASIC_INDUCT; + } + } + + /* Past CODE_LABEL, we get to insns that may be executed multiple + times. The only way we can be sure that they can't is if every + every jump insn between here and the end of the loop either + returns, exits the loop, or is a forward jump. */ + + if (GET_CODE (p) == CODE_LABEL) + { + rtx insn = p; + + maybe_multiple = 0; + + while (1) + { + insn = NEXT_INSN (insn); + if (insn == scan_start) + break; + if (insn == end) + { + if (loop_top != 0) + insn = NEXT_INSN (loop_top); + else + break; + if (insn == scan_start) + break; + } + + if (GET_CODE (insn) == JUMP_INSN + && GET_CODE (PATTERN (insn)) != RETURN + && (! condjump_p (insn) + || (JUMP_LABEL (insn) != 0 + && (INSN_UID (JUMP_LABEL (insn)) >= max_uid_for_loop + || INSN_UID (insn) >= max_uid_for_loop + || (INSN_LUID (JUMP_LABEL (insn)) + < INSN_LUID (insn)))))) + { + maybe_multiple = 1; + break; + } + } + } + + /* Past a label or a jump, we get to insns for which we can't count + on whether or how many times they will be executed during each + iteration. */ + /* This code appears in three places, once in scan_loop, and twice + in strength_reduce. */ + if ((GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN) + /* If we enter the loop in the middle, and scan around to the + beginning, don't set not_every_iteration for that. + This can be any kind of jump, since we want to know if insns + will be executed if the loop is executed. */ + && ! (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) == loop_top + && ((NEXT_INSN (NEXT_INSN (p)) == loop_end && simplejump_p (p)) + || (NEXT_INSN (p) == loop_end && condjump_p (p))))) + not_every_iteration = 1; + + /* At the virtual top of a converted loop, insns are again known to + be executed each iteration: logically, the loop begins here + even though the exit code has been duplicated. */ + + else if (GET_CODE (p) == NOTE + && NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP) + not_every_iteration = 0; + + /* Unlike in the code motion pass where MAYBE_NEVER indicates that + an insn may never be executed, NOT_EVERY_ITERATION indicates whether + or not an insn is known to be executed each iteration of the + loop, whether or not any iterations are known to occur. + + Therefore, if we have just passed a label and have no more labels + between here and the test insn of the loop, we know these insns + will be executed each iteration. This can also happen if we + have just passed a jump, for example, when there are nested loops. */ + + if (not_every_iteration && GET_CODE (p) == CODE_LABEL + && no_labels_between_p (p, loop_end)) + not_every_iteration = 0; + } + + /* Scan loop_iv_list to remove all regs that proved not to be bivs. + Make a sanity check against n_times_set. */ + for (backbl = &loop_iv_list, bl = *backbl; bl; bl = bl->next) + { + if (reg_iv_type[bl->regno] != BASIC_INDUCT + /* Above happens if register modified by subreg, etc. */ + /* Make sure it is not recognized as a basic induction var: */ + || n_times_set[bl->regno] != bl->biv_count + /* If never incremented, it is invariant that we decided not to + move. So leave it alone. */ + || ! bl->incremented) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, "Reg %d: biv discarded, %s\n", + bl->regno, + (reg_iv_type[bl->regno] != BASIC_INDUCT + ? "not induction variable" + : (! bl->incremented ? "never incremented" + : "count error"))); + + reg_iv_type[bl->regno] = NOT_BASIC_INDUCT; + *backbl = bl->next; + } + else + { + backbl = &bl->next; + + if (loop_dump_stream) + fprintf (loop_dump_stream, "Reg %d: biv verified\n", bl->regno); + } + } + + /* Exit if there are no bivs. */ + if (! loop_iv_list) + { + /* Can still unroll the loop anyways, but indicate that there is no + strength reduction info available. */ + if (flag_unroll_loops) + unroll_loop (loop_end, insn_count, loop_start, end_insert_before, 0); + + return; + } + + /* Find initial value for each biv by searching backwards from loop_start, + halting at first label. Also record any test condition. */ + + call_seen = 0; + for (p = loop_start; p && GET_CODE (p) != CODE_LABEL; p = PREV_INSN (p)) + { + note_insn = p; + + if (GET_CODE (p) == CALL_INSN) + call_seen = 1; + + if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN + || GET_CODE (p) == CALL_INSN) + note_stores (PATTERN (p), record_initial); + + /* Record any test of a biv that branches around the loop if no store + between it and the start of loop. We only care about tests with + constants and registers and only certain of those. */ + if (GET_CODE (p) == JUMP_INSN + && JUMP_LABEL (p) != 0 + && next_real_insn (JUMP_LABEL (p)) == next_real_insn (loop_end) + && (test = get_condition_for_loop (p)) != 0 + && GET_CODE (XEXP (test, 0)) == REG + && REGNO (XEXP (test, 0)) < max_reg_before_loop + && (bl = reg_biv_class[REGNO (XEXP (test, 0))]) != 0 + && valid_initial_value_p (XEXP (test, 1), p, call_seen, loop_start) + && bl->init_insn == 0) + { + /* If an NE test, we have an initial value! */ + if (GET_CODE (test) == NE) + { + bl->init_insn = p; + bl->init_set = gen_rtx (SET, VOIDmode, + XEXP (test, 0), XEXP (test, 1)); + } + else + bl->initial_test = test; + } + } + + /* Look at the each biv and see if we can say anything better about its + initial value from any initializing insns set up above. (This is done + in two passes to avoid missing SETs in a PARALLEL.) */ + for (bl = loop_iv_list; bl; bl = bl->next) + { + rtx src; + + if (! bl->init_insn) + continue; + + src = SET_SRC (bl->init_set); + + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Biv %d initialized at insn %d: initial value ", + bl->regno, INSN_UID (bl->init_insn)); + + if (valid_initial_value_p (src, bl->init_insn, call_seen, loop_start)) + { + bl->initial_value = src; + + if (loop_dump_stream) + { + if (GET_CODE (src) == CONST_INT) + fprintf (loop_dump_stream, "%d\n", INTVAL (src)); + else + { + print_rtl (loop_dump_stream, src); + fprintf (loop_dump_stream, "\n"); + } + } + } + else + { + /* Biv initial value is not simple move, + so let it keep initial value of "itself". */ + + if (loop_dump_stream) + fprintf (loop_dump_stream, "is complex\n"); + } + } + + /* Search the loop for general induction variables. */ + + /* A register is a giv if: it is only set once, it is a function of a + biv and a constant (or invariant), and it is not a biv. */ + + not_every_iteration = 0; + p = scan_start; + while (1) + { + p = NEXT_INSN (p); + /* At end of a straight-in loop, we are done. + At end of a loop entered at the bottom, scan the top. */ + if (p == scan_start) + break; + if (p == end) + { + if (loop_top != 0) + p = NEXT_INSN (loop_top); + else + break; + if (p == scan_start) + break; + } + + /* Look for a general induction variable in a register. */ + if (GET_CODE (p) == INSN + && (set = single_set (p)) + && GET_CODE (SET_DEST (set)) == REG + && ! may_not_optimize[REGNO (SET_DEST (set))]) + { + rtx src_reg; + rtx add_val; + rtx mult_val; + int benefit; + rtx regnote = 0; + + dest_reg = SET_DEST (set); + if (REGNO (dest_reg) < FIRST_PSEUDO_REGISTER) + continue; + + if (/* SET_SRC is a giv. */ + ((benefit = general_induction_var (SET_SRC (set), + &src_reg, &add_val, + &mult_val)) + /* Equivalent expression is a giv. */ + || ((regnote = find_reg_note (p, REG_EQUAL, NULL_RTX)) + && (benefit = general_induction_var (XEXP (regnote, 0), + &src_reg, + &add_val, &mult_val)))) + /* Don't try to handle any regs made by loop optimization. + We have nothing on them in regno_first_uid, etc. */ + && REGNO (dest_reg) < max_reg_before_loop + /* Don't recognize a BASIC_INDUCT_VAR here. */ + && dest_reg != src_reg + /* This must be the only place where the register is set. */ + && (n_times_set[REGNO (dest_reg)] == 1 + /* or all sets must be consecutive and make a giv. */ + || (benefit = consec_sets_giv (benefit, p, + src_reg, dest_reg, + &add_val, &mult_val)))) + { + int count; + struct induction *v + = (struct induction *) alloca (sizeof (struct induction)); + rtx temp; + + /* If this is a library call, increase benefit. */ + if (find_reg_note (p, REG_RETVAL, NULL_RTX)) + benefit += libcall_benefit (p); + + /* Skip the consecutive insns, if there are any. */ + for (count = n_times_set[REGNO (dest_reg)] - 1; + count > 0; count--) + { + /* If first insn of libcall sequence, skip to end. + Do this at start of loop, since INSN is guaranteed to + be an insn here. */ + if (GET_CODE (p) != NOTE + && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) + p = XEXP (temp, 0); + + do p = NEXT_INSN (p); + while (GET_CODE (p) == NOTE); + } + + record_giv (v, p, src_reg, dest_reg, mult_val, add_val, benefit, + DEST_REG, not_every_iteration, NULL_PTR, loop_start, + loop_end); + + } + } + +#ifndef DONT_REDUCE_ADDR + /* Look for givs which are memory addresses. */ + /* This resulted in worse code on a VAX 8600. I wonder if it + still does. */ + if (GET_CODE (p) == INSN) + find_mem_givs (PATTERN (p), p, not_every_iteration, loop_start, + loop_end); +#endif + + /* Update the status of whether giv can derive other givs. This can + change when we pass a label or an insn that updates a biv. */ + if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN + || GET_CODE (p) == CODE_LABEL) + update_giv_derive (p); + + /* Past a label or a jump, we get to insns for which we can't count + on whether or how many times they will be executed during each + iteration. */ + /* This code appears in three places, once in scan_loop, and twice + in strength_reduce. */ + if ((GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN) + /* If we enter the loop in the middle, and scan around + to the beginning, don't set not_every_iteration for that. + This can be any kind of jump, since we want to know if insns + will be executed if the loop is executed. */ + && ! (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) == loop_top + && ((NEXT_INSN (NEXT_INSN (p)) == loop_end && simplejump_p (p)) + || (NEXT_INSN (p) == loop_end && condjump_p (p))))) + not_every_iteration = 1; + + /* At the virtual top of a converted loop, insns are again known to + be executed each iteration: logically, the loop begins here + even though the exit code has been duplicated. */ + + else if (GET_CODE (p) == NOTE + && NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP) + not_every_iteration = 0; + + /* Unlike in the code motion pass where MAYBE_NEVER indicates that + an insn may never be executed, NOT_EVERY_ITERATION indicates whether + or not an insn is known to be executed each iteration of the + loop, whether or not any iterations are known to occur. + + Therefore, if we have just passed a label and have no more labels + between here and the test insn of the loop, we know these insns + will be executed each iteration. */ + + if (not_every_iteration && GET_CODE (p) == CODE_LABEL + && no_labels_between_p (p, loop_end)) + not_every_iteration = 0; + } + + /* Try to calculate and save the number of loop iterations. This is + set to zero if the actual number can not be calculated. This must + be called after all giv's have been identified, since otherwise it may + fail if the iteration variable is a giv. */ + + loop_n_iterations = loop_iterations (loop_start, loop_end); + + /* Now for each giv for which we still don't know whether or not it is + replaceable, check to see if it is replaceable because its final value + can be calculated. This must be done after loop_iterations is called, + so that final_giv_value will work correctly. */ + + for (bl = loop_iv_list; bl; bl = bl->next) + { + struct induction *v; + + for (v = bl->giv; v; v = v->next_iv) + if (! v->replaceable && ! v->not_replaceable) + check_final_value (v, loop_start, loop_end); + } + + /* Try to prove that the loop counter variable (if any) is always + nonnegative; if so, record that fact with a REG_NONNEG note + so that "decrement and branch until zero" insn can be used. */ + check_dbra_loop (loop_end, insn_count, loop_start); + + /* Create reg_map to hold substitutions for replaceable giv regs. */ + reg_map = (rtx *) alloca (max_reg_before_loop * sizeof (rtx)); + bzero ((char *) reg_map, max_reg_before_loop * sizeof (rtx)); + + /* Examine each iv class for feasibility of strength reduction/induction + variable elimination. */ + + for (bl = loop_iv_list; bl; bl = bl->next) + { + struct induction *v; + int benefit; + int all_reduced; + rtx final_value = 0; + + /* Test whether it will be possible to eliminate this biv + provided all givs are reduced. This is possible if either + the reg is not used outside the loop, or we can compute + what its final value will be. + + For architectures with a decrement_and_branch_until_zero insn, + don't do this if we put a REG_NONNEG note on the endtest for + this biv. */ + + /* Compare against bl->init_insn rather than loop_start. + We aren't concerned with any uses of the biv between + init_insn and loop_start since these won't be affected + by the value of the biv elsewhere in the function, so + long as init_insn doesn't use the biv itself. + March 14, 1989 -- self@bayes.arc.nasa.gov */ + + if ((uid_luid[regno_last_uid[bl->regno]] < INSN_LUID (loop_end) + && bl->init_insn + && INSN_UID (bl->init_insn) < max_uid_for_loop + && uid_luid[regno_first_uid[bl->regno]] >= INSN_LUID (bl->init_insn) +#ifdef HAVE_decrement_and_branch_until_zero + && ! bl->nonneg +#endif + && ! reg_mentioned_p (bl->biv->dest_reg, SET_SRC (bl->init_set))) + || ((final_value = final_biv_value (bl, loop_start, loop_end)) +#ifdef HAVE_decrement_and_branch_until_zero + && ! bl->nonneg +#endif + )) + bl->eliminable = maybe_eliminate_biv (bl, loop_start, end, 0, + threshold, insn_count); + else + { + if (loop_dump_stream) + { + fprintf (loop_dump_stream, + "Cannot eliminate biv %d.\n", + bl->regno); + fprintf (loop_dump_stream, + "First use: insn %d, last use: insn %d.\n", + regno_first_uid[bl->regno], + regno_last_uid[bl->regno]); + } + } + + /* Combine all giv's for this iv_class. */ + combine_givs (bl); + + /* This will be true at the end, if all givs which depend on this + biv have been strength reduced. + We can't (currently) eliminate the biv unless this is so. */ + all_reduced = 1; + + /* Check each giv in this class to see if we will benefit by reducing + it. Skip giv's combined with others. */ + for (v = bl->giv; v; v = v->next_iv) + { + struct induction *tv; + + if (v->ignore || v->same) + continue; + + benefit = v->benefit; + + /* Reduce benefit if not replaceable, since we will insert + a move-insn to replace the insn that calculates this giv. + Don't do this unless the giv is a user variable, since it + will often be marked non-replaceable because of the duplication + of the exit code outside the loop. In such a case, the copies + we insert are dead and will be deleted. So they don't have + a cost. Similar situations exist. */ + /* ??? The new final_[bg]iv_value code does a much better job + of finding replaceable giv's, and hence this code may no longer + be necessary. */ + if (! v->replaceable && ! bl->eliminable + && REG_USERVAR_P (v->dest_reg)) + benefit -= copy_cost; + + /* Decrease the benefit to count the add-insns that we will + insert to increment the reduced reg for the giv. */ + benefit -= add_cost * bl->biv_count; + + /* Decide whether to strength-reduce this giv or to leave the code + unchanged (recompute it from the biv each time it is used). + This decision can be made independently for each giv. */ + + /* ??? Perhaps attempt to guess whether autoincrement will handle + some of the new add insns; if so, can increase BENEFIT + (undo the subtraction of add_cost that was done above). */ + + /* If an insn is not to be strength reduced, then set its ignore + flag, and clear all_reduced. */ + + if (v->lifetime * threshold * benefit < insn_count) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "giv of insn %d not worth while, %d vs %d.\n", + INSN_UID (v->insn), + v->lifetime * threshold * benefit, insn_count); + v->ignore = 1; + all_reduced = 0; + } + else + { + /* Check that we can increment the reduced giv without a + multiply insn. If not, reject it. */ + + for (tv = bl->biv; tv; tv = tv->next_iv) + if (tv->mult_val == const1_rtx + && ! product_cheap_p (tv->add_val, v->mult_val)) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "giv of insn %d: would need a multiply.\n", + INSN_UID (v->insn)); + v->ignore = 1; + all_reduced = 0; + break; + } + } + } + + /* Reduce each giv that we decided to reduce. */ + + for (v = bl->giv; v; v = v->next_iv) + { + struct induction *tv; + if (! v->ignore && v->same == 0) + { + v->new_reg = gen_reg_rtx (v->mode); + + /* For each place where the biv is incremented, + add an insn to increment the new, reduced reg for the giv. */ + for (tv = bl->biv; tv; tv = tv->next_iv) + { + if (tv->mult_val == const1_rtx) + emit_iv_add_mult (tv->add_val, v->mult_val, + v->new_reg, v->new_reg, tv->insn); + else /* tv->mult_val == const0_rtx */ + /* A multiply is acceptable here + since this is presumed to be seldom executed. */ + emit_iv_add_mult (tv->add_val, v->mult_val, + v->add_val, v->new_reg, tv->insn); + } + + /* Add code at loop start to initialize giv's reduced reg. */ + + emit_iv_add_mult (bl->initial_value, v->mult_val, + v->add_val, v->new_reg, loop_start); + } + } + + /* Rescan all givs. If a giv is the same as a giv not reduced, mark it + as not reduced. + + For each giv register that can be reduced now: if replaceable, + substitute reduced reg wherever the old giv occurs; + else add new move insn "giv_reg = reduced_reg". + + Also check for givs whose first use is their definition and whose + last use is the definition of another giv. If so, it is likely + dead and should not be used to eliminate a biv. */ + for (v = bl->giv; v; v = v->next_iv) + { + if (v->same && v->same->ignore) + v->ignore = 1; + + if (v->ignore) + continue; + + if (v->giv_type == DEST_REG + && regno_first_uid[REGNO (v->dest_reg)] == INSN_UID (v->insn)) + { + struct induction *v1; + + for (v1 = bl->giv; v1; v1 = v1->next_iv) + if (regno_last_uid[REGNO (v->dest_reg)] == INSN_UID (v1->insn)) + v->maybe_dead = 1; + } + + /* Update expression if this was combined, in case other giv was + replaced. */ + if (v->same) + v->new_reg = replace_rtx (v->new_reg, + v->same->dest_reg, v->same->new_reg); + + if (v->giv_type == DEST_ADDR) + /* Store reduced reg as the address in the memref where we found + this giv. */ + *v->location = v->new_reg; + else if (v->replaceable) + { + reg_map[REGNO (v->dest_reg)] = v->new_reg; + +#if 0 + /* I can no longer duplicate the original problem. Perhaps + this is unnecessary now? */ + + /* Replaceable; it isn't strictly necessary to delete the old + insn and emit a new one, because v->dest_reg is now dead. + + However, especially when unrolling loops, the special + handling for (set REG0 REG1) in the second cse pass may + make v->dest_reg live again. To avoid this problem, emit + an insn to set the original giv reg from the reduced giv. + We can not delete the original insn, since it may be part + of a LIBCALL, and the code in flow that eliminates dead + libcalls will fail if it is deleted. */ + emit_insn_after (gen_move_insn (v->dest_reg, v->new_reg), + v->insn); +#endif + } + else + { + /* Not replaceable; emit an insn to set the original giv reg from + the reduced giv, same as above. */ + emit_insn_after (gen_move_insn (v->dest_reg, v->new_reg), + v->insn); + } + + /* When a loop is reversed, givs which depend on the reversed + biv, and which are live outside the loop, must be set to their + correct final value. This insn is only needed if the giv is + not replaceable. The correct final value is the same as the + value that the giv starts the reversed loop with. */ + if (bl->reversed && ! v->replaceable) + emit_iv_add_mult (bl->initial_value, v->mult_val, + v->add_val, v->dest_reg, end_insert_before); + else if (v->final_value) + { + rtx insert_before; + + /* If the loop has multiple exits, emit the insn before the + loop to ensure that it will always be executed no matter + how the loop exits. Otherwise, emit the insn after the loop, + since this is slightly more efficient. */ + if (loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]]) + insert_before = loop_start; + else + insert_before = end_insert_before; + emit_insn_before (gen_move_insn (v->dest_reg, v->final_value), + insert_before); + +#if 0 + /* If the insn to set the final value of the giv was emitted + before the loop, then we must delete the insn inside the loop + that sets it. If this is a LIBCALL, then we must delete + every insn in the libcall. Note, however, that + final_giv_value will only succeed when there are multiple + exits if the giv is dead at each exit, hence it does not + matter that the original insn remains because it is dead + anyways. */ + /* Delete the insn inside the loop that sets the giv since + the giv is now set before (or after) the loop. */ + delete_insn (v->insn); +#endif + } + + if (loop_dump_stream) + { + fprintf (loop_dump_stream, "giv at %d reduced to ", + INSN_UID (v->insn)); + print_rtl (loop_dump_stream, v->new_reg); + fprintf (loop_dump_stream, "\n"); + } + } + + /* All the givs based on the biv bl have been reduced if they + merit it. */ + + /* For each giv not marked as maybe dead that has been combined with a + second giv, clear any "maybe dead" mark on that second giv. + v->new_reg will either be or refer to the register of the giv it + combined with. + + Doing this clearing avoids problems in biv elimination where a + giv's new_reg is a complex value that can't be put in the insn but + the giv combined with (with a reg as new_reg) is marked maybe_dead. + Since the register will be used in either case, we'd prefer it be + used from the simpler giv. */ + + for (v = bl->giv; v; v = v->next_iv) + if (! v->maybe_dead && v->same) + v->same->maybe_dead = 0; + + /* Try to eliminate the biv, if it is a candidate. + This won't work if ! all_reduced, + since the givs we planned to use might not have been reduced. + + We have to be careful that we didn't initially think we could eliminate + this biv because of a giv that we now think may be dead and shouldn't + be used as a biv replacement. + + Also, there is the possibility that we may have a giv that looks + like it can be used to eliminate a biv, but the resulting insn + isn't valid. This can happen, for example, on the 88k, where a + JUMP_INSN can compare a register only with zero. Attempts to + replace it with a compare with a constant will fail. + + Note that in cases where this call fails, we may have replaced some + of the occurrences of the biv with a giv, but no harm was done in + doing so in the rare cases where it can occur. */ + + if (all_reduced == 1 && bl->eliminable + && maybe_eliminate_biv (bl, loop_start, end, 1, + threshold, insn_count)) + + { + /* ?? If we created a new test to bypass the loop entirely, + or otherwise drop straight in, based on this test, then + we might want to rewrite it also. This way some later + pass has more hope of removing the initialization of this + biv entirely. */ + + /* If final_value != 0, then the biv may be used after loop end + and we must emit an insn to set it just in case. + + Reversed bivs already have an insn after the loop setting their + value, so we don't need another one. We can't calculate the + proper final value for such a biv here anyways. */ + if (final_value != 0 && ! bl->reversed) + { + rtx insert_before; + + /* If the loop has multiple exits, emit the insn before the + loop to ensure that it will always be executed no matter + how the loop exits. Otherwise, emit the insn after the + loop, since this is slightly more efficient. */ + if (loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]]) + insert_before = loop_start; + else + insert_before = end_insert_before; + + emit_insn_before (gen_move_insn (bl->biv->dest_reg, final_value), + end_insert_before); + } + +#if 0 + /* Delete all of the instructions inside the loop which set + the biv, as they are all dead. If is safe to delete them, + because an insn setting a biv will never be part of a libcall. */ + /* However, deleting them will invalidate the regno_last_uid info, + so keeping them around is more convenient. Final_biv_value + will only succeed when there are multiple exits if the biv + is dead at each exit, hence it does not matter that the original + insn remains, because it is dead anyways. */ + for (v = bl->biv; v; v = v->next_iv) + delete_insn (v->insn); +#endif + + if (loop_dump_stream) + fprintf (loop_dump_stream, "Reg %d: biv eliminated\n", + bl->regno); + } + } + + /* Go through all the instructions in the loop, making all the + register substitutions scheduled in REG_MAP. */ + + for (p = loop_start; p != end; p = NEXT_INSN (p)) + if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN + || GET_CODE (p) == CALL_INSN) + { + replace_regs (PATTERN (p), reg_map, max_reg_before_loop, 0); + replace_regs (REG_NOTES (p), reg_map, max_reg_before_loop, 0); + INSN_CODE (p) = -1; + } + + /* Unroll loops from within strength reduction so that we can use the + induction variable information that strength_reduce has already + collected. */ + + if (flag_unroll_loops) + unroll_loop (loop_end, insn_count, loop_start, end_insert_before, 1); + + if (loop_dump_stream) + fprintf (loop_dump_stream, "\n"); +} + +/* Return 1 if X is a valid source for an initial value (or as value being + compared against in an initial test). + + X must be either a register or constant and must not be clobbered between + the current insn and the start of the loop. + + INSN is the insn containing X. */ + +static int +valid_initial_value_p (x, insn, call_seen, loop_start) + rtx x; + rtx insn; + int call_seen; + rtx loop_start; +{ + if (CONSTANT_P (x)) + return 1; + + /* Only consider pseudos we know about initialized in insns whose luids + we know. */ + if (GET_CODE (x) != REG + || REGNO (x) >= max_reg_before_loop) + return 0; + + /* Don't use call-clobbered registers across a call which clobbers it. On + some machines, don't use any hard registers at all. */ + if (REGNO (x) < FIRST_PSEUDO_REGISTER +#ifndef SMALL_REGISTER_CLASSES + && call_used_regs[REGNO (x)] && call_seen +#endif + ) + return 0; + + /* Don't use registers that have been clobbered before the start of the + loop. */ + if (reg_set_between_p (x, insn, loop_start)) + return 0; + + return 1; +} + +/* Scan X for memory refs and check each memory address + as a possible giv. INSN is the insn whose pattern X comes from. + NOT_EVERY_ITERATION is 1 if the insn might not be executed during + every loop iteration. */ + +static void +find_mem_givs (x, insn, not_every_iteration, loop_start, loop_end) + rtx x; + rtx insn; + int not_every_iteration; + rtx loop_start, loop_end; +{ + register int i, j; + register enum rtx_code code; + register char *fmt; + + if (x == 0) + return; + + code = GET_CODE (x); + switch (code) + { + case REG: + case CONST_INT: + case CONST: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case PC: + case CC0: + case ADDR_VEC: + case ADDR_DIFF_VEC: + case USE: + case CLOBBER: + return; + + case MEM: + { + rtx src_reg; + rtx add_val; + rtx mult_val; + int benefit; + + benefit = general_induction_var (XEXP (x, 0), + &src_reg, &add_val, &mult_val); + + /* Don't make a DEST_ADDR giv with mult_val == 1 && add_val == 0. + Such a giv isn't useful. */ + if (benefit > 0 && (mult_val != const1_rtx || add_val != const0_rtx)) + { + /* Found one; record it. */ + struct induction *v + = (struct induction *) oballoc (sizeof (struct induction)); + + record_giv (v, insn, src_reg, addr_placeholder, mult_val, + add_val, benefit, DEST_ADDR, not_every_iteration, + &XEXP (x, 0), loop_start, loop_end); + + v->mem_mode = GET_MODE (x); + } + return; + } + } + + /* Recursively scan the subexpressions for other mem refs. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + find_mem_givs (XEXP (x, i), insn, not_every_iteration, loop_start, + loop_end); + else if (fmt[i] == 'E') + for (j = 0; j < XVECLEN (x, i); j++) + find_mem_givs (XVECEXP (x, i, j), insn, not_every_iteration, + loop_start, loop_end); +} + +/* Fill in the data about one biv update. + V is the `struct induction' in which we record the biv. (It is + allocated by the caller, with alloca.) + INSN is the insn that sets it. + DEST_REG is the biv's reg. + + MULT_VAL is const1_rtx if the biv is being incremented here, in which case + INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is + being set to INC_VAL. + + NOT_EVERY_ITERATION is nonzero if this biv update is not know to be + executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update + can be executed more than once per iteration. If MAYBE_MULTIPLE + and NOT_EVERY_ITERATION are both zero, we know that the biv update is + executed exactly once per iteration. */ + +static void +record_biv (v, insn, dest_reg, inc_val, mult_val, + not_every_iteration, maybe_multiple) + struct induction *v; + rtx insn; + rtx dest_reg; + rtx inc_val; + rtx mult_val; + int not_every_iteration; + int maybe_multiple; +{ + struct iv_class *bl; + + v->insn = insn; + v->src_reg = dest_reg; + v->dest_reg = dest_reg; + v->mult_val = mult_val; + v->add_val = inc_val; + v->mode = GET_MODE (dest_reg); + v->always_computable = ! not_every_iteration; + v->maybe_multiple = maybe_multiple; + + /* Add this to the reg's iv_class, creating a class + if this is the first incrementation of the reg. */ + + bl = reg_biv_class[REGNO (dest_reg)]; + if (bl == 0) + { + /* Create and initialize new iv_class. */ + + bl = (struct iv_class *) oballoc (sizeof (struct iv_class)); + + bl->regno = REGNO (dest_reg); + bl->biv = 0; + bl->giv = 0; + bl->biv_count = 0; + bl->giv_count = 0; + + /* Set initial value to the reg itself. */ + bl->initial_value = dest_reg; + /* We haven't seen the initializing insn yet */ + bl->init_insn = 0; + bl->init_set = 0; + bl->initial_test = 0; + bl->incremented = 0; + bl->eliminable = 0; + bl->nonneg = 0; + bl->reversed = 0; + bl->total_benefit = 0; + + /* Add this class to loop_iv_list. */ + bl->next = loop_iv_list; + loop_iv_list = bl; + + /* Put it in the array of biv register classes. */ + reg_biv_class[REGNO (dest_reg)] = bl; + } + + /* Update IV_CLASS entry for this biv. */ + v->next_iv = bl->biv; + bl->biv = v; + bl->biv_count++; + if (mult_val == const1_rtx) + bl->incremented = 1; + + if (loop_dump_stream) + { + fprintf (loop_dump_stream, + "Insn %d: possible biv, reg %d,", + INSN_UID (insn), REGNO (dest_reg)); + if (GET_CODE (inc_val) == CONST_INT) + fprintf (loop_dump_stream, " const = %d\n", + INTVAL (inc_val)); + else + { + fprintf (loop_dump_stream, " const = "); + print_rtl (loop_dump_stream, inc_val); + fprintf (loop_dump_stream, "\n"); + } + } +} + +/* Fill in the data about one giv. + V is the `struct induction' in which we record the giv. (It is + allocated by the caller, with alloca.) + INSN is the insn that sets it. + BENEFIT estimates the savings from deleting this insn. + TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed + into a register or is used as a memory address. + + SRC_REG is the biv reg which the giv is computed from. + DEST_REG is the giv's reg (if the giv is stored in a reg). + MULT_VAL and ADD_VAL are the coefficients used to compute the giv. + LOCATION points to the place where this giv's value appears in INSN. */ + +static void +record_giv (v, insn, src_reg, dest_reg, mult_val, add_val, benefit, + type, not_every_iteration, location, loop_start, loop_end) + struct induction *v; + rtx insn; + rtx src_reg; + rtx dest_reg; + rtx mult_val, add_val; + int benefit; + enum g_types type; + int not_every_iteration; + rtx *location; + rtx loop_start, loop_end; +{ + struct induction *b; + struct iv_class *bl; + rtx set = single_set (insn); + rtx p; + + v->insn = insn; + v->src_reg = src_reg; + v->giv_type = type; + v->dest_reg = dest_reg; + v->mult_val = mult_val; + v->add_val = add_val; + v->benefit = benefit; + v->location = location; + v->cant_derive = 0; + v->combined_with = 0; + v->maybe_multiple = 0; + v->maybe_dead = 0; + v->derive_adjustment = 0; + v->same = 0; + v->ignore = 0; + v->new_reg = 0; + v->final_value = 0; + + /* The v->always_computable field is used in update_giv_derive, to + determine whether a giv can be used to derive another giv. For a + DEST_REG giv, INSN computes a new value for the giv, so its value + isn't computable if INSN insn't executed every iteration. + However, for a DEST_ADDR giv, INSN merely uses the value of the giv; + it does not compute a new value. Hence the value is always computable + regardless of whether INSN is executed each iteration. */ + + if (type == DEST_ADDR) + v->always_computable = 1; + else + v->always_computable = ! not_every_iteration; + + if (type == DEST_ADDR) + { + v->mode = GET_MODE (*location); + v->lifetime = 1; + v->times_used = 1; + } + else /* type == DEST_REG */ + { + v->mode = GET_MODE (SET_DEST (set)); + + v->lifetime = (uid_luid[regno_last_uid[REGNO (dest_reg)]] + - uid_luid[regno_first_uid[REGNO (dest_reg)]]); + + v->times_used = n_times_used[REGNO (dest_reg)]; + + /* If the lifetime is zero, it means that this register is + really a dead store. So mark this as a giv that can be + ignored. This will not prevent the biv from being eliminated. */ + if (v->lifetime == 0) + v->ignore = 1; + + reg_iv_type[REGNO (dest_reg)] = GENERAL_INDUCT; + reg_iv_info[REGNO (dest_reg)] = v; + } + + /* Add the giv to the class of givs computed from one biv. */ + + bl = reg_biv_class[REGNO (src_reg)]; + if (bl) + { + v->next_iv = bl->giv; + bl->giv = v; + /* Don't count DEST_ADDR. This is supposed to count the number of + insns that calculate givs. */ + if (type == DEST_REG) + bl->giv_count++; + bl->total_benefit += benefit; + } + else + /* Fatal error, biv missing for this giv? */ + abort (); + + if (type == DEST_ADDR) + v->replaceable = 1; + else + { + /* The giv can be replaced outright by the reduced register only if all + of the following conditions are true: + - the insn that sets the giv is always executed on any iteration + on which the giv is used at all + (there are two ways to deduce this: + either the insn is executed on every iteration, + or all uses follow that insn in the same basic block), + - the giv is not used outside the loop + - no assignments to the biv occur during the giv's lifetime. */ + + if (regno_first_uid[REGNO (dest_reg)] == INSN_UID (insn) + /* Previous line always fails if INSN was moved by loop opt. */ + && uid_luid[regno_last_uid[REGNO (dest_reg)]] < INSN_LUID (loop_end) + && (! not_every_iteration + || last_use_this_basic_block (dest_reg, insn))) + { + /* Now check that there are no assignments to the biv within the + giv's lifetime. This requires two separate checks. */ + + /* Check each biv update, and fail if any are between the first + and last use of the giv. + + If this loop contains an inner loop that was unrolled, then + the insn modifying the biv may have been emitted by the loop + unrolling code, and hence does not have a valid luid. Just + mark the biv as not replaceable in this case. It is not very + useful as a biv, because it is used in two different loops. + It is very unlikely that we would be able to optimize the giv + using this biv anyways. */ + + v->replaceable = 1; + for (b = bl->biv; b; b = b->next_iv) + { + if (INSN_UID (b->insn) >= max_uid_for_loop + || ((uid_luid[INSN_UID (b->insn)] + >= uid_luid[regno_first_uid[REGNO (dest_reg)]]) + && (uid_luid[INSN_UID (b->insn)] + <= uid_luid[regno_last_uid[REGNO (dest_reg)]]))) + { + v->replaceable = 0; + v->not_replaceable = 1; + break; + } + } + + /* Check each insn between the first and last use of the giv, + and fail if any of them are branches that jump to a named label + outside this range, but still inside the loop. This catches + cases of spaghetti code where the execution order of insns + is not linear, and hence the above test fails. For example, + in the following code, j is not replaceable: + for (i = 0; i < 100; ) { + L0: j = 4*i; goto L1; + L2: k = j; goto L3; + L1: i++; goto L2; + L3: ; } + printf ("k = %d\n", k); } + This test is conservative, but this test succeeds rarely enough + that it isn't a problem. See also check_final_value below. */ + + if (v->replaceable) + for (p = insn; + INSN_UID (p) >= max_uid_for_loop + || INSN_LUID (p) < uid_luid[regno_last_uid[REGNO (dest_reg)]]; + p = NEXT_INSN (p)) + { + if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) + && LABEL_NAME (JUMP_LABEL (p)) + && ((INSN_LUID (JUMP_LABEL (p)) > INSN_LUID (loop_start) + && (INSN_LUID (JUMP_LABEL (p)) + < uid_luid[regno_first_uid[REGNO (dest_reg)]])) + || (INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (loop_end) + && (INSN_LUID (JUMP_LABEL (p)) + > uid_luid[regno_last_uid[REGNO (dest_reg)]])))) + { + v->replaceable = 0; + v->not_replaceable = 1; + + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Found branch outside giv lifetime.\n"); + + break; + } + } + } + else + { + /* May still be replaceable, we don't have enough info here to + decide. */ + v->replaceable = 0; + v->not_replaceable = 0; + } + } + + if (loop_dump_stream) + { + if (type == DEST_REG) + fprintf (loop_dump_stream, "Insn %d: giv reg %d", + INSN_UID (insn), REGNO (dest_reg)); + else + fprintf (loop_dump_stream, "Insn %d: dest address", + INSN_UID (insn)); + + fprintf (loop_dump_stream, " src reg %d benefit %d", + REGNO (src_reg), v->benefit); + fprintf (loop_dump_stream, " used %d lifetime %d", + v->times_used, v->lifetime); + + if (v->replaceable) + fprintf (loop_dump_stream, " replaceable"); + + if (GET_CODE (mult_val) == CONST_INT) + fprintf (loop_dump_stream, " mult %d", + INTVAL (mult_val)); + else + { + fprintf (loop_dump_stream, " mult "); + print_rtl (loop_dump_stream, mult_val); + } + + if (GET_CODE (add_val) == CONST_INT) + fprintf (loop_dump_stream, " add %d", + INTVAL (add_val)); + else + { + fprintf (loop_dump_stream, " add "); + print_rtl (loop_dump_stream, add_val); + } + } + + if (loop_dump_stream) + fprintf (loop_dump_stream, "\n"); + +} + + +/* All this does is determine whether a giv can be made replaceable because + its final value can be calculated. This code can not be part of record_giv + above, because final_giv_value requires that the number of loop iterations + be known, and that can not be accurately calculated until after all givs + have been identified. */ + +static void +check_final_value (v, loop_start, loop_end) + struct induction *v; + rtx loop_start, loop_end; +{ + struct iv_class *bl; + rtx final_value = 0; + rtx tem; + + bl = reg_biv_class[REGNO (v->src_reg)]; + + /* DEST_ADDR givs will never reach here, because they are always marked + replaceable above in record_giv. */ + + /* The giv can be replaced outright by the reduced register only if all + of the following conditions are true: + - the insn that sets the giv is always executed on any iteration + on which the giv is used at all + (there are two ways to deduce this: + either the insn is executed on every iteration, + or all uses follow that insn in the same basic block), + - its final value can be calculated (this condition is different + than the one above in record_giv) + - no assignments to the biv occur during the giv's lifetime. */ + +#if 0 + /* This is only called now when replaceable is known to be false. */ + /* Clear replaceable, so that it won't confuse final_giv_value. */ + v->replaceable = 0; +#endif + + if ((final_value = final_giv_value (v, loop_start, loop_end)) + && (v->always_computable || last_use_this_basic_block (v->dest_reg, v->insn))) + { + int biv_increment_seen = 0; + rtx p = v->insn; + rtx last_giv_use; + + v->replaceable = 1; + + /* When trying to determine whether or not a biv increment occurs + during the lifetime of the giv, we can ignore uses of the variable + outside the loop because final_value is true. Hence we can not + use regno_last_uid and regno_first_uid as above in record_giv. */ + + /* Search the loop to determine whether any assignments to the + biv occur during the giv's lifetime. Start with the insn + that sets the giv, and search around the loop until we come + back to that insn again. + + Also fail if there is a jump within the giv's lifetime that jumps + to somewhere outside the lifetime but still within the loop. This + catches spaghetti code where the execution order is not linear, and + hence the above test fails. Here we assume that the giv lifetime + does not extend from one iteration of the loop to the next, so as + to make the test easier. Since the lifetime isn't known yet, + this requires two loops. See also record_giv above. */ + + last_giv_use = v->insn; + + while (1) + { + p = NEXT_INSN (p); + if (p == loop_end) + p = NEXT_INSN (loop_start); + if (p == v->insn) + break; + + if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN + || GET_CODE (p) == CALL_INSN) + { + if (biv_increment_seen) + { + if (reg_mentioned_p (v->dest_reg, PATTERN (p))) + { + v->replaceable = 0; + v->not_replaceable = 1; + break; + } + } + else if (GET_CODE (PATTERN (p)) == SET + && SET_DEST (PATTERN (p)) == v->src_reg) + biv_increment_seen = 1; + else if (reg_mentioned_p (v->dest_reg, PATTERN (p))) + last_giv_use = p; + } + } + + /* Now that the lifetime of the giv is known, check for branches + from within the lifetime to outside the lifetime if it is still + replaceable. */ + + if (v->replaceable) + { + p = v->insn; + while (1) + { + p = NEXT_INSN (p); + if (p == loop_end) + p = NEXT_INSN (loop_start); + if (p == last_giv_use) + break; + + if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) + && LABEL_NAME (JUMP_LABEL (p)) + && ((INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (v->insn) + && INSN_LUID (JUMP_LABEL (p)) > INSN_LUID (loop_start)) + || (INSN_LUID (JUMP_LABEL (p)) > INSN_LUID (last_giv_use) + && INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (loop_end)))) + { + v->replaceable = 0; + v->not_replaceable = 1; + + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Found branch outside giv lifetime.\n"); + + break; + } + } + } + + /* If it is replaceable, then save the final value. */ + if (v->replaceable) + v->final_value = final_value; + } + + if (loop_dump_stream && v->replaceable) + fprintf (loop_dump_stream, "Insn %d: giv reg %d final_value replaceable\n", + INSN_UID (v->insn), REGNO (v->dest_reg)); +} + +/* Update the status of whether a giv can derive other givs. + + We need to do something special if there is or may be an update to the biv + between the time the giv is defined and the time it is used to derive + another giv. + + In addition, a giv that is only conditionally set is not allowed to + derive another giv once a label has been passed. + + The cases we look at are when a label or an update to a biv is passed. */ + +static void +update_giv_derive (p) + rtx p; +{ + struct iv_class *bl; + struct induction *biv, *giv; + rtx tem; + int dummy; + + /* Search all IV classes, then all bivs, and finally all givs. + + There are three cases we are concerned with. First we have the situation + of a giv that is only updated conditionally. In that case, it may not + derive any givs after a label is passed. + + The second case is when a biv update occurs, or may occur, after the + definition of a giv. For certain biv updates (see below) that are + known to occur between the giv definition and use, we can adjust the + giv definition. For others, or when the biv update is conditional, + we must prevent the giv from deriving any other givs. There are two + sub-cases within this case. + + If this is a label, we are concerned with any biv update that is done + conditionally, since it may be done after the giv is defined followed by + a branch here (actually, we need to pass both a jump and a label, but + this extra tracking doesn't seem worth it). + + If this is a jump, we are concerned about any biv update that may be + executed multiple times. We are actually only concerned about + backward jumps, but it is probably not worth performing the test + on the jump again here. + + If this is a biv update, we must adjust the giv status to show that a + subsequent biv update was performed. If this adjustment cannot be done, + the giv cannot derive further givs. */ + + for (bl = loop_iv_list; bl; bl = bl->next) + for (biv = bl->biv; biv; biv = biv->next_iv) + if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN + || biv->insn == p) + { + for (giv = bl->giv; giv; giv = giv->next_iv) + { + /* If cant_derive is already true, there is no point in + checking all of these conditions again. */ + if (giv->cant_derive) + continue; + + /* If this giv is conditionally set and we have passed a label, + it cannot derive anything. */ + if (GET_CODE (p) == CODE_LABEL && ! giv->always_computable) + giv->cant_derive = 1; + + /* Skip givs that have mult_val == 0, since + they are really invariants. Also skip those that are + replaceable, since we know their lifetime doesn't contain + any biv update. */ + else if (giv->mult_val == const0_rtx || giv->replaceable) + continue; + + /* The only way we can allow this giv to derive another + is if this is a biv increment and we can form the product + of biv->add_val and giv->mult_val. In this case, we will + be able to compute a compensation. */ + else if (biv->insn == p) + { + tem = 0; + + if (biv->mult_val == const1_rtx) + tem = simplify_giv_expr (gen_rtx (MULT, giv->mode, + biv->add_val, + giv->mult_val), + &dummy); + + if (tem && giv->derive_adjustment) + tem = simplify_giv_expr (gen_rtx (PLUS, giv->mode, tem, + giv->derive_adjustment), + &dummy); + if (tem) + giv->derive_adjustment = tem; + else + giv->cant_derive = 1; + } + else if ((GET_CODE (p) == CODE_LABEL && ! biv->always_computable) + || (GET_CODE (p) == JUMP_INSN && biv->maybe_multiple)) + giv->cant_derive = 1; + } + } +} + +/* Check whether an insn is an increment legitimate for a basic induction var. + X is the source of insn P. + DEST_REG is the putative biv, also the destination of the insn. + We accept patterns of these forms: + REG = REG + INVARIANT (includes REG = REG - CONSTANT) + REG = INVARIANT + REG + + If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX, + and store the additive term into *INC_VAL. + + If X is an assignment of an invariant into DEST_REG, we set + *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL. + + We also want to detect a BIV when it corresponds to a variable + whose mode was promoted via PROMOTED_MODE. In that case, an increment + of the variable may be a PLUS that adds a SUBREG of that variable to + an invariant and then sign- or zero-extends the result of the PLUS + into the variable. + + Most GIVs in such cases will be in the promoted mode, since that is the + probably the natural computation mode (and almost certainly the mode + used for addresses) on the machine. So we view the pseudo-reg containing + the variable as the BIV, as if it were simply incremented. + + Note that treating the entire pseudo as a BIV will result in making + simple increments to any GIVs based on it. However, if the variable + overflows in its declared mode but not its promoted mode, the result will + be incorrect. This is acceptable if the variable is signed, since + overflows in such cases are undefined, but not if it is unsigned, since + those overflows are defined. So we only check for SIGN_EXTEND and + not ZERO_EXTEND. + + If we cannot find a biv, we return 0. */ + +static int +basic_induction_var (x, dest_reg, p, inc_val, mult_val) + register rtx x; + rtx p; + rtx dest_reg; + rtx *inc_val; + rtx *mult_val; +{ + register enum rtx_code code; + rtx arg; + rtx insn, set = 0; + + code = GET_CODE (x); + switch (code) + { + case PLUS: + if (XEXP (x, 0) == dest_reg + || (GET_CODE (XEXP (x, 0)) == SUBREG + && SUBREG_PROMOTED_VAR_P (XEXP (x, 0)) + && SUBREG_REG (XEXP (x, 0)) == dest_reg)) + arg = XEXP (x, 1); + else if (XEXP (x, 1) == dest_reg + || (GET_CODE (XEXP (x, 1)) == SUBREG + && SUBREG_PROMOTED_VAR_P (XEXP (x, 1)) + && SUBREG_REG (XEXP (x, 1)) == dest_reg)) + arg = XEXP (x, 0); + else + return 0; + + if (invariant_p (arg) != 1) + return 0; + + *inc_val = convert_to_mode (GET_MODE (dest_reg), arg, 0);; + *mult_val = const1_rtx; + return 1; + + case SUBREG: + /* If this is a SUBREG for a promoted variable, check the inner + value. */ + if (SUBREG_PROMOTED_VAR_P (x)) + return basic_induction_var (SUBREG_REG (x), dest_reg, p, + inc_val, mult_val); + + case REG: + /* If this register is assigned in the previous insn, look at its + source, but don't go outside the loop or past a label. */ + + for (insn = PREV_INSN (p); + (insn && GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG); + insn = PREV_INSN (insn)) + ; + + if (insn) + set = single_set (insn); + + if (set != 0 && SET_DEST (set) == x) + return basic_induction_var (SET_SRC (set), dest_reg, insn, + inc_val, mult_val); + /* ... fall through ... */ + + /* Can accept constant setting of biv only when inside inner most loop. + Otherwise, a biv of an inner loop may be incorrectly recognized + as a biv of the outer loop, + causing code to be moved INTO the inner loop. */ + case MEM: + if (invariant_p (x) != 1) + return 0; + case CONST_INT: + case SYMBOL_REF: + case CONST: + if (loops_enclosed == 1) + { + *inc_val = convert_to_mode (GET_MODE (dest_reg), x, 0);; + *mult_val = const0_rtx; + return 1; + } + else + return 0; + + case SIGN_EXTEND: + return basic_induction_var (XEXP (x, 0), dest_reg, p, + inc_val, mult_val); + case ASHIFTRT: + /* Similar, since this can be a sign extension. */ + for (insn = PREV_INSN (p); + (insn && GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG); + insn = PREV_INSN (insn)) + ; + + if (insn) + set = single_set (insn); + + if (set && SET_DEST (set) == XEXP (x, 0) + && GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) >= 0 + && GET_CODE (SET_SRC (set)) == ASHIFT + && XEXP (x, 1) == XEXP (SET_SRC (set), 1)) + return basic_induction_var (XEXP (SET_SRC (set), 0), dest_reg, insn, + inc_val, mult_val); + return 0; + + default: + return 0; + } +} + +/* A general induction variable (giv) is any quantity that is a linear + function of a basic induction variable, + i.e. giv = biv * mult_val + add_val. + The coefficients can be any loop invariant quantity. + A giv need not be computed directly from the biv; + it can be computed by way of other givs. */ + +/* Determine whether X computes a giv. + If it does, return a nonzero value + which is the benefit from eliminating the computation of X; + set *SRC_REG to the register of the biv that it is computed from; + set *ADD_VAL and *MULT_VAL to the coefficients, + such that the value of X is biv * mult + add; */ + +static int +general_induction_var (x, src_reg, add_val, mult_val) + rtx x; + rtx *src_reg; + rtx *add_val; + rtx *mult_val; +{ + rtx orig_x = x; + int benefit = 0; + char *storage; + + /* If this is an invariant, forget it, it isn't a giv. */ + if (invariant_p (x) == 1) + return 0; + + /* See if the expression could be a giv and get its form. + Mark our place on the obstack in case we don't find a giv. */ + storage = (char *) oballoc (0); + x = simplify_giv_expr (x, &benefit); + if (x == 0) + { + obfree (storage); + return 0; + } + + switch (GET_CODE (x)) + { + case USE: + case CONST_INT: + /* Since this is now an invariant and wasn't before, it must be a giv + with MULT_VAL == 0. It doesn't matter which BIV we associate this + with. */ + *src_reg = loop_iv_list->biv->dest_reg; + *mult_val = const0_rtx; + *add_val = x; + break; + + case REG: + /* This is equivalent to a BIV. */ + *src_reg = x; + *mult_val = const1_rtx; + *add_val = const0_rtx; + break; + + case PLUS: + /* Either (plus (biv) (invar)) or + (plus (mult (biv) (invar_1)) (invar_2)). */ + if (GET_CODE (XEXP (x, 0)) == MULT) + { + *src_reg = XEXP (XEXP (x, 0), 0); + *mult_val = XEXP (XEXP (x, 0), 1); + } + else + { + *src_reg = XEXP (x, 0); + *mult_val = const1_rtx; + } + *add_val = XEXP (x, 1); + break; + + case MULT: + /* ADD_VAL is zero. */ + *src_reg = XEXP (x, 0); + *mult_val = XEXP (x, 1); + *add_val = const0_rtx; + break; + + default: + abort (); + } + + /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be + unless they are CONST_INT). */ + if (GET_CODE (*add_val) == USE) + *add_val = XEXP (*add_val, 0); + if (GET_CODE (*mult_val) == USE) + *mult_val = XEXP (*mult_val, 0); + + benefit += rtx_cost (orig_x, SET); + + /* Always return some benefit if this is a giv so it will be detected + as such. This allows elimination of bivs that might otherwise + not be eliminated. */ + return benefit == 0 ? 1 : benefit; +} + +/* Given an expression, X, try to form it as a linear function of a biv. + We will canonicalize it to be of the form + (plus (mult (BIV) (invar_1)) + (invar_2)) + with possible degeneracies. + + The invariant expressions must each be of a form that can be used as a + machine operand. We surround then with a USE rtx (a hack, but localized + and certainly unambiguous!) if not a CONST_INT for simplicity in this + routine; it is the caller's responsibility to strip them. + + If no such canonicalization is possible (i.e., two biv's are used or an + expression that is neither invariant nor a biv or giv), this routine + returns 0. + + For a non-zero return, the result will have a code of CONST_INT, USE, + REG (for a BIV), PLUS, or MULT. No other codes will occur. + + *BENEFIT will be incremented by the benefit of any sub-giv encountered. */ + +static rtx +simplify_giv_expr (x, benefit) + rtx x; + int *benefit; +{ + enum machine_mode mode = GET_MODE (x); + rtx arg0, arg1; + rtx tem; + + /* If this is not an integer mode, or if we cannot do arithmetic in this + mode, this can't be a giv. */ + if (mode != VOIDmode + && (GET_MODE_CLASS (mode) != MODE_INT + || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)) + return 0; + + switch (GET_CODE (x)) + { + case PLUS: + arg0 = simplify_giv_expr (XEXP (x, 0), benefit); + arg1 = simplify_giv_expr (XEXP (x, 1), benefit); + if (arg0 == 0 || arg1 == 0) + return 0; + + /* Put constant last, CONST_INT last if both constant. */ + if ((GET_CODE (arg0) == USE + || GET_CODE (arg0) == CONST_INT) + && GET_CODE (arg1) != CONST_INT) + tem = arg0, arg0 = arg1, arg1 = tem; + + /* Handle addition of zero, then addition of an invariant. */ + if (arg1 == const0_rtx) + return arg0; + else if (GET_CODE (arg1) == CONST_INT || GET_CODE (arg1) == USE) + switch (GET_CODE (arg0)) + { + case CONST_INT: + case USE: + /* Both invariant. Only valid if sum is machine operand. + First strip off possible USE on first operand. */ + if (GET_CODE (arg0) == USE) + arg0 = XEXP (arg0, 0); + + tem = 0; + if (CONSTANT_P (arg0) && GET_CODE (arg1) == CONST_INT) + { + tem = plus_constant (arg0, INTVAL (arg1)); + if (GET_CODE (tem) != CONST_INT) + tem = gen_rtx (USE, mode, tem); + } + + return tem; + + case REG: + case MULT: + /* biv + invar or mult + invar. Return sum. */ + return gen_rtx (PLUS, mode, arg0, arg1); + + case PLUS: + /* (a + invar_1) + invar_2. Associate. */ + return simplify_giv_expr (gen_rtx (PLUS, mode, + XEXP (arg0, 0), + gen_rtx (PLUS, mode, + XEXP (arg0, 1), arg1)), + benefit); + + default: + abort (); + } + + /* Each argument must be either REG, PLUS, or MULT. Convert REG to + MULT to reduce cases. */ + if (GET_CODE (arg0) == REG) + arg0 = gen_rtx (MULT, mode, arg0, const1_rtx); + if (GET_CODE (arg1) == REG) + arg1 = gen_rtx (MULT, mode, arg1, const1_rtx); + + /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT. + Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT. + Recurse to associate the second PLUS. */ + if (GET_CODE (arg1) == MULT) + tem = arg0, arg0 = arg1, arg1 = tem; + + if (GET_CODE (arg1) == PLUS) + return simplify_giv_expr (gen_rtx (PLUS, mode, + gen_rtx (PLUS, mode, + arg0, XEXP (arg1, 0)), + XEXP (arg1, 1)), + benefit); + + /* Now must have MULT + MULT. Distribute if same biv, else not giv. */ + if (GET_CODE (arg0) != MULT || GET_CODE (arg1) != MULT) + abort (); + + if (XEXP (arg0, 0) != XEXP (arg1, 0)) + return 0; + + return simplify_giv_expr (gen_rtx (MULT, mode, + XEXP (arg0, 0), + gen_rtx (PLUS, mode, + XEXP (arg0, 1), + XEXP (arg1, 1))), + benefit); + + case MINUS: + /* Handle "a - b" as "a + b * (-1)". */ + return simplify_giv_expr (gen_rtx (PLUS, mode, + XEXP (x, 0), + gen_rtx (MULT, mode, + XEXP (x, 1), constm1_rtx)), + benefit); + + case MULT: + arg0 = simplify_giv_expr (XEXP (x, 0), benefit); + arg1 = simplify_giv_expr (XEXP (x, 1), benefit); + if (arg0 == 0 || arg1 == 0) + return 0; + + /* Put constant last, CONST_INT last if both constant. */ + if ((GET_CODE (arg0) == USE || GET_CODE (arg0) == CONST_INT) + && GET_CODE (arg1) != CONST_INT) + tem = arg0, arg0 = arg1, arg1 = tem; + + /* If second argument is not now constant, not giv. */ + if (GET_CODE (arg1) != USE && GET_CODE (arg1) != CONST_INT) + return 0; + + /* Handle multiply by 0 or 1. */ + if (arg1 == const0_rtx) + return const0_rtx; + + else if (arg1 == const1_rtx) + return arg0; + + switch (GET_CODE (arg0)) + { + case REG: + /* biv * invar. Done. */ + return gen_rtx (MULT, mode, arg0, arg1); + + case CONST_INT: + /* Product of two constants. */ + return GEN_INT (INTVAL (arg0) * INTVAL (arg1)); + + case USE: + /* invar * invar. Not giv. */ + return 0; + + case MULT: + /* (a * invar_1) * invar_2. Associate. */ + return simplify_giv_expr (gen_rtx (MULT, mode, + XEXP (arg0, 0), + gen_rtx (MULT, mode, + XEXP (arg0, 1), arg1)), + benefit); + + case PLUS: + /* (a + invar_1) * invar_2. Distribute. */ + return simplify_giv_expr (gen_rtx (PLUS, mode, + gen_rtx (MULT, mode, + XEXP (arg0, 0), arg1), + gen_rtx (MULT, mode, + XEXP (arg0, 1), arg1)), + benefit); + + default: + abort (); + } + + case ASHIFT: + case LSHIFT: + /* Shift by constant is multiply by power of two. */ + if (GET_CODE (XEXP (x, 1)) != CONST_INT) + return 0; + + return simplify_giv_expr (gen_rtx (MULT, mode, + XEXP (x, 0), + GEN_INT ((HOST_WIDE_INT) 1 + << INTVAL (XEXP (x, 1)))), + benefit); + + case NEG: + /* "-a" is "a * (-1)" */ + return simplify_giv_expr (gen_rtx (MULT, mode, XEXP (x, 0), constm1_rtx), + benefit); + + case NOT: + /* "~a" is "-a - 1". Silly, but easy. */ + return simplify_giv_expr (gen_rtx (MINUS, mode, + gen_rtx (NEG, mode, XEXP (x, 0)), + const1_rtx), + benefit); + + case USE: + /* Already in proper form for invariant. */ + return x; + + case REG: + /* If this is a new register, we can't deal with it. */ + if (REGNO (x) >= max_reg_before_loop) + return 0; + + /* Check for biv or giv. */ + switch (reg_iv_type[REGNO (x)]) + { + case BASIC_INDUCT: + return x; + case GENERAL_INDUCT: + { + struct induction *v = reg_iv_info[REGNO (x)]; + + /* Form expression from giv and add benefit. Ensure this giv + can derive another and subtract any needed adjustment if so. */ + *benefit += v->benefit; + if (v->cant_derive) + return 0; + + tem = gen_rtx (PLUS, mode, gen_rtx (MULT, mode, + v->src_reg, v->mult_val), + v->add_val); + if (v->derive_adjustment) + tem = gen_rtx (MINUS, mode, tem, v->derive_adjustment); + return simplify_giv_expr (tem, benefit); + } + } + + /* Fall through to general case. */ + default: + /* If invariant, return as USE (unless CONST_INT). + Otherwise, not giv. */ + if (GET_CODE (x) == USE) + x = XEXP (x, 0); + + if (invariant_p (x) == 1) + { + if (GET_CODE (x) == CONST_INT) + return x; + else + return gen_rtx (USE, mode, x); + } + else + return 0; + } +} + +/* Help detect a giv that is calculated by several consecutive insns; + for example, + giv = biv * M + giv = giv + A + The caller has already identified the first insn P as having a giv as dest; + we check that all other insns that set the same register follow + immediately after P, that they alter nothing else, + and that the result of the last is still a giv. + + The value is 0 if the reg set in P is not really a giv. + Otherwise, the value is the amount gained by eliminating + all the consecutive insns that compute the value. + + FIRST_BENEFIT is the amount gained by eliminating the first insn, P. + SRC_REG is the reg of the biv; DEST_REG is the reg of the giv. + + The coefficients of the ultimate giv value are stored in + *MULT_VAL and *ADD_VAL. */ + +static int +consec_sets_giv (first_benefit, p, src_reg, dest_reg, + add_val, mult_val) + int first_benefit; + rtx p; + rtx src_reg; + rtx dest_reg; + rtx *add_val; + rtx *mult_val; +{ + int count; + enum rtx_code code; + int benefit; + rtx temp; + rtx set; + + /* Indicate that this is a giv so that we can update the value produced in + each insn of the multi-insn sequence. + + This induction structure will be used only by the call to + general_induction_var below, so we can allocate it on our stack. + If this is a giv, our caller will replace the induct var entry with + a new induction structure. */ + struct induction *v + = (struct induction *) alloca (sizeof (struct induction)); + v->src_reg = src_reg; + v->mult_val = *mult_val; + v->add_val = *add_val; + v->benefit = first_benefit; + v->cant_derive = 0; + v->derive_adjustment = 0; + + reg_iv_type[REGNO (dest_reg)] = GENERAL_INDUCT; + reg_iv_info[REGNO (dest_reg)] = v; + + count = n_times_set[REGNO (dest_reg)] - 1; + + while (count > 0) + { + p = NEXT_INSN (p); + code = GET_CODE (p); + + /* If libcall, skip to end of call sequence. */ + if (code == INSN && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) + p = XEXP (temp, 0); + + if (code == INSN + && (set = single_set (p)) + && GET_CODE (SET_DEST (set)) == REG + && SET_DEST (set) == dest_reg + && ((benefit = general_induction_var (SET_SRC (set), &src_reg, + add_val, mult_val)) + /* Giv created by equivalent expression. */ + || ((temp = find_reg_note (p, REG_EQUAL, NULL_RTX)) + && (benefit = general_induction_var (XEXP (temp, 0), &src_reg, + add_val, mult_val)))) + && src_reg == v->src_reg) + { + if (find_reg_note (p, REG_RETVAL, NULL_RTX)) + benefit += libcall_benefit (p); + + count--; + v->mult_val = *mult_val; + v->add_val = *add_val; + v->benefit = benefit; + } + else if (code != NOTE) + { + /* Allow insns that set something other than this giv to a + constant. Such insns are needed on machines which cannot + include long constants and should not disqualify a giv. */ + if (code == INSN + && (set = single_set (p)) + && SET_DEST (set) != dest_reg + && CONSTANT_P (SET_SRC (set))) + continue; + + reg_iv_type[REGNO (dest_reg)] = UNKNOWN_INDUCT; + return 0; + } + } + + return v->benefit; +} + +/* Return an rtx, if any, that expresses giv G2 as a function of the register + represented by G1. If no such expression can be found, or it is clear that + it cannot possibly be a valid address, 0 is returned. + + To perform the computation, we note that + G1 = a * v + b and + G2 = c * v + d + where `v' is the biv. + + So G2 = (c/a) * G1 + (d - b*c/a) */ + +#ifdef ADDRESS_COST +static rtx +express_from (g1, g2) + struct induction *g1, *g2; +{ + rtx mult, add; + + /* The value that G1 will be multiplied by must be a constant integer. Also, + the only chance we have of getting a valid address is if b*c/a (see above + for notation) is also an integer. */ + if (GET_CODE (g1->mult_val) != CONST_INT + || GET_CODE (g2->mult_val) != CONST_INT + || GET_CODE (g1->add_val) != CONST_INT + || g1->mult_val == const0_rtx + || INTVAL (g2->mult_val) % INTVAL (g1->mult_val) != 0) + return 0; + + mult = GEN_INT (INTVAL (g2->mult_val) / INTVAL (g1->mult_val)); + add = plus_constant (g2->add_val, - INTVAL (g1->add_val) * INTVAL (mult)); + + /* Form simplified final result. */ + if (mult == const0_rtx) + return add; + else if (mult == const1_rtx) + mult = g1->dest_reg; + else + mult = gen_rtx (MULT, g2->mode, g1->dest_reg, mult); + + if (add == const0_rtx) + return mult; + else + return gen_rtx (PLUS, g2->mode, mult, add); +} +#endif + +/* Return 1 if giv G2 can be combined with G1. This means that G2 can use + (either directly or via an address expression) a register used to represent + G1. Set g2->new_reg to a represtation of G1 (normally just + g1->dest_reg). */ + +static int +combine_givs_p (g1, g2) + struct induction *g1, *g2; +{ + rtx tem; + + /* If these givs are identical, they can be combined. */ + if (rtx_equal_p (g1->mult_val, g2->mult_val) + && rtx_equal_p (g1->add_val, g2->add_val)) + { + g2->new_reg = g1->dest_reg; + return 1; + } + +#ifdef ADDRESS_COST + /* If G2 can be expressed as a function of G1 and that function is valid + as an address and no more expensive than using a register for G2, + the expression of G2 in terms of G1 can be used. */ + if (g2->giv_type == DEST_ADDR + && (tem = express_from (g1, g2)) != 0 + && memory_address_p (g2->mem_mode, tem) + && ADDRESS_COST (tem) <= ADDRESS_COST (*g2->location)) + { + g2->new_reg = tem; + return 1; + } +#endif + + return 0; +} + +/* Check all pairs of givs for iv_class BL and see if any can be combined with + any other. If so, point SAME to the giv combined with and set NEW_REG to + be an expression (in terms of the other giv's DEST_REG) equivalent to the + giv. Also, update BENEFIT and related fields for cost/benefit analysis. */ + +static void +combine_givs (bl) + struct iv_class *bl; +{ + struct induction *g1, *g2; + int pass; + + for (g1 = bl->giv; g1; g1 = g1->next_iv) + for (pass = 0; pass <= 1; pass++) + for (g2 = bl->giv; g2; g2 = g2->next_iv) + if (g1 != g2 + /* First try to combine with replaceable givs, then all givs. */ + && (g1->replaceable || pass == 1) + /* If either has already been combined or is to be ignored, can't + combine. */ + && ! g1->ignore && ! g2->ignore && ! g1->same && ! g2->same + /* If something has been based on G2, G2 cannot itself be based + on something else. */ + && ! g2->combined_with + && combine_givs_p (g1, g2)) + { + /* g2->new_reg set by `combine_givs_p' */ + g2->same = g1; + g1->combined_with = 1; + g1->benefit += g2->benefit; + /* ??? The new final_[bg]iv_value code does a much better job + of finding replaceable giv's, and hence this code may no + longer be necessary. */ + if (! g2->replaceable && REG_USERVAR_P (g2->dest_reg)) + g1->benefit -= copy_cost; + g1->lifetime += g2->lifetime; + g1->times_used += g2->times_used; + + if (loop_dump_stream) + fprintf (loop_dump_stream, "giv at %d combined with giv at %d\n", + INSN_UID (g2->insn), INSN_UID (g1->insn)); + } +} + +/* EMIT code before INSERT_BEFORE to set REG = B * M + A. */ + +void +emit_iv_add_mult (b, m, a, reg, insert_before) + rtx b; /* initial value of basic induction variable */ + rtx m; /* multiplicative constant */ + rtx a; /* additive constant */ + rtx reg; /* destination register */ + rtx insert_before; +{ + rtx seq; + rtx result; + + /* Prevent unexpected sharing of these rtx. */ + a = copy_rtx (a); + b = copy_rtx (b); + + /* Increase the lifetime of any invariants moved further in code. */ + update_reg_last_use (a, insert_before); + update_reg_last_use (b, insert_before); + update_reg_last_use (m, insert_before); + + start_sequence (); + result = expand_mult_add (b, reg, m, a, GET_MODE (reg), 0); + if (reg != result) + emit_move_insn (reg, result); + seq = gen_sequence (); + end_sequence (); + + emit_insn_before (seq, insert_before); +} + +/* Test whether A * B can be computed without + an actual multiply insn. Value is 1 if so. */ + +static int +product_cheap_p (a, b) + rtx a; + rtx b; +{ + int i; + rtx tmp; + struct obstack *old_rtl_obstack = rtl_obstack; + char *storage = (char *) obstack_alloc (&temp_obstack, 0); + int win = 1; + + /* If only one is constant, make it B. */ + if (GET_CODE (a) == CONST_INT) + tmp = a, a = b, b = tmp; + + /* If first constant, both constant, so don't need multiply. */ + if (GET_CODE (a) == CONST_INT) + return 1; + + /* If second not constant, neither is constant, so would need multiply. */ + if (GET_CODE (b) != CONST_INT) + return 0; + + /* One operand is constant, so might not need multiply insn. Generate the + code for the multiply and see if a call or multiply, or long sequence + of insns is generated. */ + + rtl_obstack = &temp_obstack; + start_sequence (); + expand_mult (GET_MODE (a), a, b, NULL_RTX, 0); + tmp = gen_sequence (); + end_sequence (); + + if (GET_CODE (tmp) == SEQUENCE) + { + if (XVEC (tmp, 0) == 0) + win = 1; + else if (XVECLEN (tmp, 0) > 3) + win = 0; + else + for (i = 0; i < XVECLEN (tmp, 0); i++) + { + rtx insn = XVECEXP (tmp, 0, i); + + if (GET_CODE (insn) != INSN + || (GET_CODE (PATTERN (insn)) == SET + && GET_CODE (SET_SRC (PATTERN (insn))) == MULT) + || (GET_CODE (PATTERN (insn)) == PARALLEL + && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (PATTERN (insn), 0, 0))) == MULT)) + { + win = 0; + break; + } + } + } + else if (GET_CODE (tmp) == SET + && GET_CODE (SET_SRC (tmp)) == MULT) + win = 0; + else if (GET_CODE (tmp) == PARALLEL + && GET_CODE (XVECEXP (tmp, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (tmp, 0, 0))) == MULT) + win = 0; + + /* Free any storage we obtained in generating this multiply and restore rtl + allocation to its normal obstack. */ + obstack_free (&temp_obstack, storage); + rtl_obstack = old_rtl_obstack; + + return win; +} + +/* Check to see if loop can be terminated by a "decrement and branch until + zero" instruction. If so, add a REG_NONNEG note to the branch insn if so. + Also try reversing an increment loop to a decrement loop + to see if the optimization can be performed. + Value is nonzero if optimization was performed. */ + +/* This is useful even if the architecture doesn't have such an insn, + because it might change a loops which increments from 0 to n to a loop + which decrements from n to 0. A loop that decrements to zero is usually + faster than one that increments from zero. */ + +/* ??? This could be rewritten to use some of the loop unrolling procedures, + such as approx_final_value, biv_total_increment, loop_iterations, and + final_[bg]iv_value. */ + +static int +check_dbra_loop (loop_end, insn_count, loop_start) + rtx loop_end; + int insn_count; + rtx loop_start; +{ + struct iv_class *bl; + rtx reg; + rtx jump_label; + rtx final_value; + rtx start_value; + enum rtx_code branch_code; + rtx new_add_val; + rtx comparison; + rtx before_comparison; + rtx p; + + /* If last insn is a conditional branch, and the insn before tests a + register value, try to optimize it. Otherwise, we can't do anything. */ + + comparison = get_condition_for_loop (PREV_INSN (loop_end)); + if (comparison == 0) + return 0; + + /* Check all of the bivs to see if the compare uses one of them. + Skip biv's set more than once because we can't guarantee that + it will be zero on the last iteration. Also skip if the biv is + used between its update and the test insn. */ + + for (bl = loop_iv_list; bl; bl = bl->next) + { + if (bl->biv_count == 1 + && bl->biv->dest_reg == XEXP (comparison, 0) + && ! reg_used_between_p (regno_reg_rtx[bl->regno], bl->biv->insn, + PREV_INSN (PREV_INSN (loop_end)))) + break; + } + + if (! bl) + return 0; + + /* Look for the case where the basic induction variable is always + nonnegative, and equals zero on the last iteration. + In this case, add a reg_note REG_NONNEG, which allows the + m68k DBRA instruction to be used. */ + + if (((GET_CODE (comparison) == GT + && GET_CODE (XEXP (comparison, 1)) == CONST_INT + && INTVAL (XEXP (comparison, 1)) == -1) + || (GET_CODE (comparison) == NE && XEXP (comparison, 1) == const0_rtx)) + && GET_CODE (bl->biv->add_val) == CONST_INT + && INTVAL (bl->biv->add_val) < 0) + { + /* Initial value must be greater than 0, + init_val % -dec_value == 0 to ensure that it equals zero on + the last iteration */ + + if (GET_CODE (bl->initial_value) == CONST_INT + && INTVAL (bl->initial_value) > 0 + && (INTVAL (bl->initial_value) % + (-INTVAL (bl->biv->add_val))) == 0) + { + /* register always nonnegative, add REG_NOTE to branch */ + REG_NOTES (PREV_INSN (loop_end)) + = gen_rtx (EXPR_LIST, REG_NONNEG, NULL_RTX, + REG_NOTES (PREV_INSN (loop_end))); + bl->nonneg = 1; + + return 1; + } + + /* If the decrement is 1 and the value was tested as >= 0 before + the loop, then we can safely optimize. */ + for (p = loop_start; p; p = PREV_INSN (p)) + { + if (GET_CODE (p) == CODE_LABEL) + break; + if (GET_CODE (p) != JUMP_INSN) + continue; + + before_comparison = get_condition_for_loop (p); + if (before_comparison + && XEXP (before_comparison, 0) == bl->biv->dest_reg + && GET_CODE (before_comparison) == LT + && XEXP (before_comparison, 1) == const0_rtx + && ! reg_set_between_p (bl->biv->dest_reg, p, loop_start) + && INTVAL (bl->biv->add_val) == -1) + { + REG_NOTES (PREV_INSN (loop_end)) + = gen_rtx (EXPR_LIST, REG_NONNEG, NULL_RTX, + REG_NOTES (PREV_INSN (loop_end))); + bl->nonneg = 1; + + return 1; + } + } + } + else if (num_mem_sets <= 1) + { + /* Try to change inc to dec, so can apply above optimization. */ + /* Can do this if: + all registers modified are induction variables or invariant, + all memory references have non-overlapping addresses + (obviously true if only one write) + allow 2 insns for the compare/jump at the end of the loop. */ + int num_nonfixed_reads = 0; + /* 1 if the iteration var is used only to count iterations. */ + int no_use_except_counting = 0; + + for (p = loop_start; p != loop_end; p = NEXT_INSN (p)) + if (GET_RTX_CLASS (GET_CODE (p)) == 'i') + num_nonfixed_reads += count_nonfixed_reads (PATTERN (p)); + + if (bl->giv_count == 0 + && ! loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]]) + { + rtx bivreg = regno_reg_rtx[bl->regno]; + + /* If there are no givs for this biv, and the only exit is the + fall through at the end of the the loop, then + see if perhaps there are no uses except to count. */ + no_use_except_counting = 1; + for (p = loop_start; p != loop_end; p = NEXT_INSN (p)) + if (GET_RTX_CLASS (GET_CODE (p)) == 'i') + { + rtx set = single_set (p); + + if (set && GET_CODE (SET_DEST (set)) == REG + && REGNO (SET_DEST (set)) == bl->regno) + /* An insn that sets the biv is okay. */ + ; + else if (p == prev_nonnote_insn (prev_nonnote_insn (loop_end)) + || p == prev_nonnote_insn (loop_end)) + /* Don't bother about the end test. */ + ; + else if (reg_mentioned_p (bivreg, PATTERN (p))) + /* Any other use of the biv is no good. */ + { + no_use_except_counting = 0; + break; + } + } + } + + /* This code only acts for innermost loops. Also it simplifies + the memory address check by only reversing loops with + zero or one memory access. + Two memory accesses could involve parts of the same array, + and that can't be reversed. */ + + if (num_nonfixed_reads <= 1 + && !loop_has_call + && !loop_has_volatile + && (no_use_except_counting + || (bl->giv_count + bl->biv_count + num_mem_sets + + num_movables + 2 == insn_count))) + { + rtx condition = get_condition_for_loop (PREV_INSN (loop_end)); + int win; + rtx tem; + + /* Loop can be reversed. */ + if (loop_dump_stream) + fprintf (loop_dump_stream, "Can reverse loop\n"); + + /* Now check other conditions: + initial_value must be zero, + final_value % add_val == 0, so that when reversed, the + biv will be zero on the last iteration. + + This test can probably be improved since +/- 1 in the constant + can be obtained by changing LT to LE and vice versa; this is + confusing. */ + + if (comparison && bl->initial_value == const0_rtx + && GET_CODE (XEXP (comparison, 1)) == CONST_INT + /* LE gets turned into LT */ + && GET_CODE (comparison) == LT + && (INTVAL (XEXP (comparison, 1)) + % INTVAL (bl->biv->add_val)) == 0) + { + /* Register will always be nonnegative, with value + 0 on last iteration if loop reversed */ + + /* Save some info needed to produce the new insns. */ + reg = bl->biv->dest_reg; + jump_label = XEXP (SET_SRC (PATTERN (PREV_INSN (loop_end))), 1); + new_add_val = GEN_INT (- INTVAL (bl->biv->add_val)); + + final_value = XEXP (comparison, 1); + start_value = GEN_INT (INTVAL (XEXP (comparison, 1)) + - INTVAL (bl->biv->add_val)); + + /* Initialize biv to start_value before loop start. + The old initializing insn will be deleted as a + dead store by flow.c. */ + emit_insn_before (gen_move_insn (reg, start_value), loop_start); + + /* Add insn to decrement register, and delete insn + that incremented the register. */ + p = emit_insn_before (gen_add2_insn (reg, new_add_val), + bl->biv->insn); + delete_insn (bl->biv->insn); + + /* Update biv info to reflect its new status. */ + bl->biv->insn = p; + bl->initial_value = start_value; + bl->biv->add_val = new_add_val; + + /* Inc LABEL_NUSES so that delete_insn will + not delete the label. */ + LABEL_NUSES (XEXP (jump_label, 0)) ++; + + /* Emit an insn after the end of the loop to set the biv's + proper exit value if it is used anywhere outside the loop. */ + if ((regno_last_uid[bl->regno] + != INSN_UID (PREV_INSN (PREV_INSN (loop_end)))) + || ! bl->init_insn + || regno_first_uid[bl->regno] != INSN_UID (bl->init_insn)) + emit_insn_after (gen_move_insn (reg, final_value), + loop_end); + + /* Delete compare/branch at end of loop. */ + delete_insn (PREV_INSN (loop_end)); + delete_insn (PREV_INSN (loop_end)); + + /* Add new compare/branch insn at end of loop. */ + start_sequence (); + emit_cmp_insn (reg, const0_rtx, GE, NULL_RTX, + GET_MODE (reg), 0, 0); + emit_jump_insn (gen_bge (XEXP (jump_label, 0))); + tem = gen_sequence (); + end_sequence (); + emit_jump_insn_before (tem, loop_end); + + for (tem = PREV_INSN (loop_end); + tem && GET_CODE (tem) != JUMP_INSN; tem = PREV_INSN (tem)) + ; + if (tem) + { + JUMP_LABEL (tem) = XEXP (jump_label, 0); + + /* Increment of LABEL_NUSES done above. */ + /* Register is now always nonnegative, + so add REG_NONNEG note to the branch. */ + REG_NOTES (tem) = gen_rtx (EXPR_LIST, REG_NONNEG, NULL_RTX, + REG_NOTES (tem)); + } + + bl->nonneg = 1; + + /* Mark that this biv has been reversed. Each giv which depends + on this biv, and which is also live past the end of the loop + will have to be fixed up. */ + + bl->reversed = 1; + + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Reversed loop and added reg_nonneg\n"); + + return 1; + } + } + } + + return 0; +} + +/* Verify whether the biv BL appears to be eliminable, + based on the insns in the loop that refer to it. + LOOP_START is the first insn of the loop, and END is the end insn. + + If ELIMINATE_P is non-zero, actually do the elimination. + + THRESHOLD and INSN_COUNT are from loop_optimize and are used to + determine whether invariant insns should be placed inside or at the + start of the loop. */ + +static int +maybe_eliminate_biv (bl, loop_start, end, eliminate_p, threshold, insn_count) + struct iv_class *bl; + rtx loop_start; + rtx end; + int eliminate_p; + int threshold, insn_count; +{ + rtx reg = bl->biv->dest_reg; + rtx p, set; + struct induction *v; + + /* Scan all insns in the loop, stopping if we find one that uses the + biv in a way that we cannot eliminate. */ + + for (p = loop_start; p != end; p = NEXT_INSN (p)) + { + enum rtx_code code = GET_CODE (p); + rtx where = threshold >= insn_count ? loop_start : p; + + if ((code == INSN || code == JUMP_INSN || code == CALL_INSN) + && reg_mentioned_p (reg, PATTERN (p)) + && ! maybe_eliminate_biv_1 (PATTERN (p), p, bl, eliminate_p, where)) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Cannot eliminate biv %d: biv used in insn %d.\n", + bl->regno, INSN_UID (p)); + break; + } + } + + if (p == end) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, "biv %d %s eliminated.\n", + bl->regno, eliminate_p ? "was" : "can be"); + return 1; + } + + return 0; +} + +/* If BL appears in X (part of the pattern of INSN), see if we can + eliminate its use. If so, return 1. If not, return 0. + + If BIV does not appear in X, return 1. + + If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates + where extra insns should be added. Depending on how many items have been + moved out of the loop, it will either be before INSN or at the start of + the loop. */ + +static int +maybe_eliminate_biv_1 (x, insn, bl, eliminate_p, where) + rtx x, insn; + struct iv_class *bl; + int eliminate_p; + rtx where; +{ + enum rtx_code code = GET_CODE (x); + rtx reg = bl->biv->dest_reg; + enum machine_mode mode = GET_MODE (reg); + struct induction *v; + rtx arg, new, tem; + int arg_operand; + char *fmt; + int i, j; + + switch (code) + { + case REG: + /* If we haven't already been able to do something with this BIV, + we can't eliminate it. */ + if (x == reg) + return 0; + return 1; + + case SET: + /* If this sets the BIV, it is not a problem. */ + if (SET_DEST (x) == reg) + return 1; + + /* If this is an insn that defines a giv, it is also ok because + it will go away when the giv is reduced. */ + for (v = bl->giv; v; v = v->next_iv) + if (v->giv_type == DEST_REG && SET_DEST (x) == v->dest_reg) + return 1; + +#ifdef HAVE_cc0 + if (SET_DEST (x) == cc0_rtx && SET_SRC (x) == reg) + { + /* Can replace with any giv that was reduced and + that has (MULT_VAL != 0) and (ADD_VAL == 0). + Require a constant for MULT_VAL, so we know it's nonzero. */ + + for (v = bl->giv; v; v = v->next_iv) + if (CONSTANT_P (v->mult_val) && v->mult_val != const0_rtx + && v->add_val == const0_rtx + && ! v->ignore && ! v->maybe_dead + && v->mode == mode) + { + if (! eliminate_p) + return 1; + + /* If the giv has the opposite direction of change, + then reverse the comparison. */ + if (INTVAL (v->mult_val) < 0) + new = gen_rtx (COMPARE, GET_MODE (v->new_reg), + const0_rtx, v->new_reg); + else + new = v->new_reg; + + /* We can probably test that giv's reduced reg. */ + if (validate_change (insn, &SET_SRC (x), new, 0)) + return 1; + } + + /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0); + replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL). + Require a constant for MULT_VAL, so we know it's nonzero. */ + + for (v = bl->giv; v; v = v->next_iv) + if (CONSTANT_P (v->mult_val) && v->mult_val != const0_rtx + && ! v->ignore && ! v->maybe_dead + && v->mode == mode) + { + if (! eliminate_p) + return 1; + + /* If the giv has the opposite direction of change, + then reverse the comparison. */ + if (INTVAL (v->mult_val) < 0) + new = gen_rtx (COMPARE, VOIDmode, copy_rtx (v->add_val), + v->new_reg); + else + new = gen_rtx (COMPARE, VOIDmode, v->new_reg, + copy_rtx (v->add_val)); + + /* Replace biv with the giv's reduced register. */ + update_reg_last_use (v->add_val, insn); + if (validate_change (insn, &SET_SRC (PATTERN (insn)), new, 0)) + return 1; + + /* Insn doesn't support that constant or invariant. Copy it + into a register (it will be a loop invariant.) */ + tem = gen_reg_rtx (GET_MODE (v->new_reg)); + + emit_insn_before (gen_move_insn (tem, copy_rtx (v->add_val)), + where); + + if (validate_change (insn, &SET_SRC (PATTERN (insn)), + gen_rtx (COMPARE, VOIDmode, + v->new_reg, tem), 0)) + return 1; + } + } +#endif + break; + + case COMPARE: + case EQ: case NE: + case GT: case GE: case GTU: case GEU: + case LT: case LE: case LTU: case LEU: + /* See if either argument is the biv. */ + if (XEXP (x, 0) == reg) + arg = XEXP (x, 1), arg_operand = 1; + else if (XEXP (x, 1) == reg) + arg = XEXP (x, 0), arg_operand = 0; + else + break; + + if (CONSTANT_P (arg)) + { + /* First try to replace with any giv that has constant positive + mult_val and constant add_val. We might be able to support + negative mult_val, but it seems complex to do it in general. */ + + for (v = bl->giv; v; v = v->next_iv) + if (CONSTANT_P (v->mult_val) && INTVAL (v->mult_val) > 0 + && CONSTANT_P (v->add_val) + && ! v->ignore && ! v->maybe_dead + && v->mode == mode) + { + if (! eliminate_p) + return 1; + + /* Replace biv with the giv's reduced reg. */ + XEXP (x, 1-arg_operand) = v->new_reg; + + /* If all constants are actually constant integers and + the derived constant can be directly placed in the COMPARE, + do so. */ + if (GET_CODE (arg) == CONST_INT + && GET_CODE (v->mult_val) == CONST_INT + && GET_CODE (v->add_val) == CONST_INT + && validate_change (insn, &XEXP (x, arg_operand), + GEN_INT (INTVAL (arg) + * INTVAL (v->mult_val) + + INTVAL (v->add_val)), 0)) + return 1; + + /* Otherwise, load it into a register. */ + tem = gen_reg_rtx (mode); + emit_iv_add_mult (arg, v->mult_val, v->add_val, tem, where); + if (validate_change (insn, &XEXP (x, arg_operand), tem, 0)) + return 1; + + /* If that failed, put back the change we made above. */ + XEXP (x, 1-arg_operand) = reg; + } + + /* Look for giv with positive constant mult_val and nonconst add_val. + Insert insns to calculate new compare value. */ + + for (v = bl->giv; v; v = v->next_iv) + if (CONSTANT_P (v->mult_val) && INTVAL (v->mult_val) > 0 + && ! v->ignore && ! v->maybe_dead + && v->mode == mode) + { + rtx tem; + + if (! eliminate_p) + return 1; + + tem = gen_reg_rtx (mode); + + /* Replace biv with giv's reduced register. */ + validate_change (insn, &XEXP (x, 1 - arg_operand), + v->new_reg, 1); + + /* Compute value to compare against. */ + emit_iv_add_mult (arg, v->mult_val, v->add_val, tem, where); + /* Use it in this insn. */ + validate_change (insn, &XEXP (x, arg_operand), tem, 1); + if (apply_change_group ()) + return 1; + } + } + else if (GET_CODE (arg) == REG || GET_CODE (arg) == MEM) + { + if (invariant_p (arg) == 1) + { + /* Look for giv with constant positive mult_val and nonconst + add_val. Insert insns to compute new compare value. */ + + for (v = bl->giv; v; v = v->next_iv) + if (CONSTANT_P (v->mult_val) && INTVAL (v->mult_val) > 0 + && ! v->ignore && ! v->maybe_dead + && v->mode == mode) + { + rtx tem; + + if (! eliminate_p) + return 1; + + tem = gen_reg_rtx (mode); + + /* Replace biv with giv's reduced register. */ + validate_change (insn, &XEXP (x, 1 - arg_operand), + v->new_reg, 1); + + /* Compute value to compare against. */ + emit_iv_add_mult (arg, v->mult_val, v->add_val, + tem, where); + validate_change (insn, &XEXP (x, arg_operand), tem, 1); + if (apply_change_group ()) + return 1; + } + } + + /* This code has problems. Basically, you can't know when + seeing if we will eliminate BL, whether a particular giv + of ARG will be reduced. If it isn't going to be reduced, + we can't eliminate BL. We can try forcing it to be reduced, + but that can generate poor code. + + The problem is that the benefit of reducing TV, below should + be increased if BL can actually be eliminated, but this means + we might have to do a topological sort of the order in which + we try to process biv. It doesn't seem worthwhile to do + this sort of thing now. */ + +#if 0 + /* Otherwise the reg compared with had better be a biv. */ + if (GET_CODE (arg) != REG + || reg_iv_type[REGNO (arg)] != BASIC_INDUCT) + return 0; + + /* Look for a pair of givs, one for each biv, + with identical coefficients. */ + for (v = bl->giv; v; v = v->next_iv) + { + struct induction *tv; + + if (v->ignore || v->maybe_dead || v->mode != mode) + continue; + + for (tv = reg_biv_class[REGNO (arg)]->giv; tv; tv = tv->next_iv) + if (! tv->ignore && ! tv->maybe_dead + && rtx_equal_p (tv->mult_val, v->mult_val) + && rtx_equal_p (tv->add_val, v->add_val) + && tv->mode == mode) + { + if (! eliminate_p) + return 1; + + /* Replace biv with its giv's reduced reg. */ + XEXP (x, 1-arg_operand) = v->new_reg; + /* Replace other operand with the other giv's + reduced reg. */ + XEXP (x, arg_operand) = tv->new_reg; + return 1; + } + } +#endif + } + + /* If we get here, the biv can't be eliminated. */ + return 0; + + case MEM: + /* If this address is a DEST_ADDR giv, it doesn't matter if the + biv is used in it, since it will be replaced. */ + for (v = bl->giv; v; v = v->next_iv) + if (v->giv_type == DEST_ADDR && v->location == &XEXP (x, 0)) + return 1; + break; + } + + /* See if any subexpression fails elimination. */ + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + switch (fmt[i]) + { + case 'e': + if (! maybe_eliminate_biv_1 (XEXP (x, i), insn, bl, + eliminate_p, where)) + return 0; + break; + + case 'E': + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + if (! maybe_eliminate_biv_1 (XVECEXP (x, i, j), insn, bl, + eliminate_p, where)) + return 0; + break; + } + } + + return 1; +} + +/* Return nonzero if the last use of REG + is in an insn following INSN in the same basic block. */ + +static int +last_use_this_basic_block (reg, insn) + rtx reg; + rtx insn; +{ + rtx n; + for (n = insn; + n && GET_CODE (n) != CODE_LABEL && GET_CODE (n) != JUMP_INSN; + n = NEXT_INSN (n)) + { + if (regno_last_uid[REGNO (reg)] == INSN_UID (n)) + return 1; + } + return 0; +} + +/* Called via `note_stores' to record the initial value of a biv. Here we + just record the location of the set and process it later. */ + +static void +record_initial (dest, set) + rtx dest; + rtx set; +{ + struct iv_class *bl; + + if (GET_CODE (dest) != REG + || REGNO (dest) >= max_reg_before_loop + || reg_iv_type[REGNO (dest)] != BASIC_INDUCT + /* Reject this insn if the source isn't valid for the mode of DEST. */ + || GET_MODE (dest) != GET_MODE (SET_DEST (set))) + return; + + bl = reg_biv_class[REGNO (dest)]; + + /* If this is the first set found, record it. */ + if (bl->init_insn == 0) + { + bl->init_insn = note_insn; + bl->init_set = set; + } +} + +/* If any of the registers in X are "old" and currently have a last use earlier + than INSN, update them to have a last use of INSN. Their actual last use + will be the previous insn but it will not have a valid uid_luid so we can't + use it. */ + +static void +update_reg_last_use (x, insn) + rtx x; + rtx insn; +{ + /* Check for the case where INSN does not have a valid luid. In this case, + there is no need to modify the regno_last_uid, as this can only happen + when code is inserted after the loop_end to set a pseudo's final value, + and hence this insn will never be the last use of x. */ + if (GET_CODE (x) == REG && REGNO (x) < max_reg_before_loop + && INSN_UID (insn) < max_uid_for_loop + && uid_luid[regno_last_uid[REGNO (x)]] < uid_luid[INSN_UID (insn)]) + regno_last_uid[REGNO (x)] = INSN_UID (insn); + else + { + register int i, j; + register char *fmt = GET_RTX_FORMAT (GET_CODE (x)); + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + update_reg_last_use (XEXP (x, i), insn); + else if (fmt[i] == 'E') + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + update_reg_last_use (XVECEXP (x, i, j), insn); + } + } +} + +/* Given a jump insn JUMP, return the condition that will cause it to branch + to its JUMP_LABEL. If the condition cannot be understood, or is an + inequality floating-point comparison which needs to be reversed, 0 will + be returned. + + If EARLIEST is non-zero, it is a pointer to a place where the earliest + insn used in locating the condition was found. If a replacement test + of the condition is desired, it should be placed in front of that + insn and we will be sure that the inputs are still valid. + + The condition will be returned in a canonical form to simplify testing by + callers. Specifically: + + (1) The code will always be a comparison operation (EQ, NE, GT, etc.). + (2) Both operands will be machine operands; (cc0) will have been replaced. + (3) If an operand is a constant, it will be the second operand. + (4) (LE x const) will be replaced with (LT x ) and similarly + for GE, GEU, and LEU. */ + +rtx +get_condition (jump, earliest) + rtx jump; + rtx *earliest; +{ + enum rtx_code code; + rtx prev = jump; + rtx set; + rtx tem; + rtx op0, op1; + int reverse_code = 0; + int did_reverse_condition = 0; + + /* If this is not a standard conditional jump, we can't parse it. */ + if (GET_CODE (jump) != JUMP_INSN + || ! condjump_p (jump) || simplejump_p (jump)) + return 0; + + code = GET_CODE (XEXP (SET_SRC (PATTERN (jump)), 0)); + op0 = XEXP (XEXP (SET_SRC (PATTERN (jump)), 0), 0); + op1 = XEXP (XEXP (SET_SRC (PATTERN (jump)), 0), 1); + + if (earliest) + *earliest = jump; + + /* If this branches to JUMP_LABEL when the condition is false, reverse + the condition. */ + if (GET_CODE (XEXP (SET_SRC (PATTERN (jump)), 2)) == LABEL_REF + && XEXP (XEXP (SET_SRC (PATTERN (jump)), 2), 0) == JUMP_LABEL (jump)) + code = reverse_condition (code), did_reverse_condition ^= 1; + + /* If we are comparing a register with zero, see if the register is set + in the previous insn to a COMPARE or a comparison operation. Perform + the same tests as a function of STORE_FLAG_VALUE as find_comparison_args + in cse.c */ + + while (GET_RTX_CLASS (code) == '<' && op1 == const0_rtx) + { + /* Set non-zero when we find something of interest. */ + rtx x = 0; + +#ifdef HAVE_cc0 + /* If comparison with cc0, import actual comparison from compare + insn. */ + if (op0 == cc0_rtx) + { + if ((prev = prev_nonnote_insn (prev)) == 0 + || GET_CODE (prev) != INSN + || (set = single_set (prev)) == 0 + || SET_DEST (set) != cc0_rtx) + return 0; + + op0 = SET_SRC (set); + op1 = CONST0_RTX (GET_MODE (op0)); + if (earliest) + *earliest = prev; + } +#endif + + /* If this is a COMPARE, pick up the two things being compared. */ + if (GET_CODE (op0) == COMPARE) + { + op1 = XEXP (op0, 1); + op0 = XEXP (op0, 0); + continue; + } + else if (GET_CODE (op0) != REG) + break; + + /* Go back to the previous insn. Stop if it is not an INSN. We also + stop if it isn't a single set or if it has a REG_INC note because + we don't want to bother dealing with it. */ + + if ((prev = prev_nonnote_insn (prev)) == 0 + || GET_CODE (prev) != INSN + || FIND_REG_INC_NOTE (prev, 0) + || (set = single_set (prev)) == 0) + break; + + /* If this is setting OP0, get what it sets it to if it looks + relevant. */ + if (SET_DEST (set) == op0) + { + enum machine_mode inner_mode = GET_MODE (SET_SRC (set)); + + if ((GET_CODE (SET_SRC (set)) == COMPARE + || (((code == NE + || (code == LT + && GET_MODE_CLASS (inner_mode) == MODE_INT + && (GET_MODE_BITSIZE (inner_mode) + <= HOST_BITS_PER_WIDE_INT) + && (STORE_FLAG_VALUE + & ((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (inner_mode) - 1)))) +#ifdef FLOAT_STORE_FLAG_VALUE + || (code == LT + && GET_MODE_CLASS (inner_mode) == MODE_FLOAT + && FLOAT_STORE_FLAG_VALUE < 0) +#endif + )) + && GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == '<'))) + x = SET_SRC (set); + else if (((code == EQ + || (code == GE + && (GET_MODE_BITSIZE (inner_mode) + <= HOST_BITS_PER_WIDE_INT) + && GET_MODE_CLASS (inner_mode) == MODE_INT + && (STORE_FLAG_VALUE + & ((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (inner_mode) - 1)))) +#ifdef FLOAT_STORE_FLAG_VALUE + || (code == GE + && GET_MODE_CLASS (inner_mode) == MODE_FLOAT + && FLOAT_STORE_FLAG_VALUE < 0) +#endif + )) + && GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == '<') + { + /* We might have reversed a LT to get a GE here. But this wasn't + actually the comparison of data, so we don't flag that we + have had to reverse the condition. */ + did_reverse_condition ^= 1; + reverse_code = 1; + x = SET_SRC (set); + } + } + + else if (reg_set_p (op0, prev)) + /* If this sets OP0, but not directly, we have to give up. */ + break; + + if (x) + { + if (GET_RTX_CLASS (GET_CODE (x)) == '<') + code = GET_CODE (x); + if (reverse_code) + { + code = reverse_condition (code); + did_reverse_condition ^= 1; + reverse_code = 0; + } + + op0 = XEXP (x, 0), op1 = XEXP (x, 1); + if (earliest) + *earliest = prev; + } + } + + /* If constant is first, put it last. */ + if (CONSTANT_P (op0)) + code = swap_condition (code), tem = op0, op0 = op1, op1 = tem; + + /* If OP0 is the result of a comparison, we weren't able to find what + was really being compared, so fail. */ + if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) + return 0; + + /* Canonicalize any ordered comparison with integers involving equality + if we can do computations in the relevant mode and we do not + overflow. */ + + if (GET_CODE (op1) == CONST_INT + && GET_MODE (op0) != VOIDmode + && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT) + { + HOST_WIDE_INT const_val = INTVAL (op1); + unsigned HOST_WIDE_INT uconst_val = const_val; + unsigned HOST_WIDE_INT max_val + = (unsigned HOST_WIDE_INT) GET_MODE_MASK (GET_MODE (op0)); + + switch (code) + { + case LE: + if (const_val != max_val >> 1) + code = LT, op1 = GEN_INT (const_val + 1); + break; + + case GE: + if (const_val + != (((HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) + code = GT, op1 = GEN_INT (const_val - 1); + break; + + case LEU: + if (uconst_val != max_val) + code = LTU, op1 = GEN_INT (uconst_val + 1); + break; + + case GEU: + if (uconst_val != 0) + code = GTU, op1 = GEN_INT (uconst_val - 1); + break; + } + } + + /* If this was floating-point and we reversed anything other than an + EQ or NE, return zero. */ + if (TARGET_FLOAT_FORMAT == IEEE_FLOAT_FORMAT + && did_reverse_condition && code != NE && code != EQ + && GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT) + return 0; + +#ifdef HAVE_cc0 + /* Never return CC0; return zero instead. */ + if (op0 == cc0_rtx) + return 0; +#endif + + return gen_rtx (code, VOIDmode, op0, op1); +} + +/* Similar to above routine, except that we also put an invariant last + unless both operands are invariants. */ + +rtx +get_condition_for_loop (x) + rtx x; +{ + rtx comparison = get_condition (x, NULL_PTR); + + if (comparison == 0 + || ! invariant_p (XEXP (comparison, 0)) + || invariant_p (XEXP (comparison, 1))) + return comparison; + + return gen_rtx (swap_condition (GET_CODE (comparison)), VOIDmode, + XEXP (comparison, 1), XEXP (comparison, 0)); +} diff --git a/gnu/usr.bin/cc/lib/loop.h b/gnu/usr.bin/cc/lib/loop.h new file mode 100644 index 000000000000..bb219c32d210 --- /dev/null +++ b/gnu/usr.bin/cc/lib/loop.h @@ -0,0 +1,169 @@ +/* Loop optimization definitions for GNU C-Compiler + Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Get the luid of an insn. Catch the error of trying to reference the LUID + of an insn added during loop, since these don't have LUIDs. */ + +#define INSN_LUID(INSN) \ + (INSN_UID (INSN) < max_uid_for_loop ? uid_luid[INSN_UID (INSN)] \ + : (abort (), -1)) + +/* A "basic induction variable" or biv is a pseudo reg that is set + (within this loop) only by incrementing or decrementing it. */ +/* A "general induction variable" or giv is a pseudo reg whose + value is a linear function of a biv. */ + +/* Bivs are recognized by `basic_induction_var'; + Givs by `general_induct_var'. */ + +/* An enum for the two different types of givs, those that are used + as memory addresses and those that are calculated into registers. */ +enum g_types { DEST_ADDR, DEST_REG }; + +/* A `struct induction' is created for every instruction that sets + an induction variable (either a biv or a giv). */ + +struct induction +{ + rtx insn; /* The insn that sets a biv or giv */ + rtx new_reg; /* New register, containing strength reduced + version of this giv. */ + rtx src_reg; /* Biv from which this giv is computed. + (If this is a biv, then this is the biv.) */ + enum g_types giv_type; /* Indicate whether DEST_ADDR or DEST_REG */ + rtx dest_reg; /* Destination register for insn: this is the + register which was the biv or giv. + For a biv, this equals src_reg. + For a DEST_ADDR type giv, this is 0. */ + rtx *location; /* Place in the insn where this giv occurs. + If GIV_TYPE is DEST_REG, this is 0. */ + enum machine_mode mode; /* The mode of this biv or giv */ + enum machine_mode mem_mode; /* For DEST_ADDR, mode of the memory object. */ + rtx mult_val; /* Multiplicative factor for src_reg. */ + rtx add_val; /* Additive constant for that product. */ + int benefit; /* Gain from eliminating this insn. */ + rtx final_value; /* If the giv is used outside the loop, and its + final value could be calculated, it is put + here, and the giv is made replaceable. Set + the giv to this value before the loop. */ + unsigned replaceable : 1; /* 1 if we can substitute the strength-reduced + variable for the original variable. + 0 means they must be kept separate and the + new one must be copied into the old pseudo + reg each time the old one is set. */ + unsigned not_replaceable : 1; /* Used to prevent duplicating work. This is + 1 if we know that the giv definitely can + not be made replaceable, in which case we + don't bother checking the variable again + even if further info is available. + Both this and the above can be zero. */ + unsigned ignore : 1; /* 1 prohibits further processing of giv */ + unsigned always_computable : 1;/* 1 if this set occurs each iteration */ + unsigned maybe_multiple : 1; /* Only used for a biv and 1 if this biv + update may be done multiple times per + iteration. */ + unsigned cant_derive : 1; /* For giv's, 1 if this giv cannot derive + another giv. This occurs in many cases + where a giv's lifetime spans an update to + a biv. */ + unsigned combined_with : 1; /* 1 if this giv has been combined with. It + then cannot combine with any other giv. */ + unsigned maybe_dead : 1; /* 1 if this giv might be dead. In that case, + we won't use it to eliminate a biv, it + would probably lose. */ + int lifetime; /* Length of life of this giv */ + int times_used; /* # times this giv is used. */ + rtx derive_adjustment; /* If nonzero, is an adjustment to be + subtracted from add_val when this giv + derives another. This occurs when the + giv spans a biv update by incrementation. */ + struct induction *next_iv; /* For givs, links together all givs that are + based on the same biv. For bivs, links + together all biv entries that refer to the + same biv register. */ + struct induction *same; /* If this giv has been combined with another + giv, this points to the base giv. The base + giv will have COMBINED_WITH non-zero. */ + HOST_WIDE_INT const_adjust; /* Used by loop unrolling, when an address giv + is split, and a constant is eliminated from + the address, the -constant is stored here + for later use. */ +}; + +/* A `struct iv_class' is created for each biv. */ + +struct iv_class { + int regno; /* Pseudo reg which is the biv. */ + int biv_count; /* Number of insns setting this reg. */ + struct induction *biv; /* List of all insns that set this reg. */ + int giv_count; /* Number of DEST_REG givs computed from this + biv. The resulting count is only used in + check_dbra_loop. */ + struct induction *giv; /* List of all insns that compute a giv + from this reg. */ + int total_benefit; /* Sum of BENEFITs of all those givs */ + rtx initial_value; /* Value of reg at loop start */ + rtx initial_test; /* Test performed on BIV before loop */ + struct iv_class *next; /* Links all class structures together */ + rtx init_insn; /* insn which initializes biv, 0 if none. */ + rtx init_set; /* SET of INIT_INSN, if any. */ + unsigned incremented : 1; /* 1 if somewhere incremented/decremented */ + unsigned eliminable : 1; /* 1 if plausible candidate for elimination. */ + unsigned nonneg : 1; /* 1 if we added a REG_NONNEG note for this. */ + unsigned reversed : 1; /* 1 if we reversed the loop that this + biv controls. */ +}; + +/* Definitions used by the basic induction variable discovery code. */ +enum iv_mode { UNKNOWN_INDUCT, BASIC_INDUCT, NOT_BASIC_INDUCT, + GENERAL_INDUCT }; + +/* Variables declared in loop.c, but also needed in unroll.c. */ + +extern int *uid_luid; +extern int max_uid_for_loop; +extern int *uid_loop_num; +extern int *loop_outer_loop; +extern rtx *loop_number_exit_labels; +extern unsigned HOST_WIDE_INT loop_n_iterations; +extern int max_reg_before_loop; + +extern FILE *loop_dump_stream; + +extern enum iv_mode *reg_iv_type; +extern struct induction **reg_iv_info; +extern struct iv_class **reg_biv_class; +extern struct iv_class *loop_iv_list; + +/* Forward declarations for non-static functions declared in loop.c and + unroll.c. */ +int invariant_p PROTO((rtx)); +rtx get_condition_for_loop PROTO((rtx)); +void emit_iv_add_mult PROTO((rtx, rtx, rtx, rtx, rtx)); + +/* Forward declarations for non-static functions declared in stmt.c. */ +void find_loop_tree_blocks PROTO((void)); +void unroll_block_trees PROTO((void)); + +void unroll_loop PROTO((rtx, int, rtx, rtx, int)); +rtx biv_total_increment PROTO((struct iv_class *, rtx, rtx)); +unsigned HOST_WIDE_INT loop_iterations PROTO((rtx, rtx)); +rtx final_biv_value PROTO((struct iv_class *, rtx, rtx)); +rtx final_giv_value PROTO((struct induction *, rtx, rtx)); +void emit_unrolled_add PROTO((rtx, rtx, rtx)); diff --git a/gnu/usr.bin/cc/lib/machmode.def b/gnu/usr.bin/cc/lib/machmode.def new file mode 100644 index 000000000000..0cbe9f8163a1 --- /dev/null +++ b/gnu/usr.bin/cc/lib/machmode.def @@ -0,0 +1,117 @@ +/* This file contains the definitions and documentation for the + machine modes used in the the GNU compiler. + Copyright (C) 1987-1990 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This file defines all the MACHINE MODES used by GNU CC. + + A machine mode specifies a size and format of data + at the machine level. + + Each RTL expression has a machine mode. + + At the syntax tree level, each ..._TYPE and each ..._DECL node + has a machine mode which describes data of that type or the + data of the variable declared. */ + +/* The first argument is the internal name of the machine mode + used in the C source. + By convention these are in UPPER_CASE, except for the word "mode". + + The second argument is the name of the machine mode in the + external ASCII format used for reading and printing RTL and trees. + By convention these names in UPPER_CASE. + + Third argument states the kind of representation: + MODE_INT - integer + MODE_FLOAT - floating + MODE_PARTIAL_INT - PSImode and PDImode + MODE_CC - modes used for representing the condition code in a register + MODE_COMPLEX_INT, MODE_COMPLEX_FLOAT - complex number + MODE_RANDOM - anything else + + Fourth argument is the relative size of the object, in bytes. + It is zero when the size is meaningless or not determined. + A byte's size is determined by BITS_PER_UNIT in tm.h. + + + Fifth arg is the relative size of subunits of the object. + It is same as the fourth argument except for complexes, + since they are really made of two equal size subunits. + + Sixth arg is next wider natural mode of the same class. + 0 if there is none. */ + +/* VOIDmode is used when no mode needs to be specified, + as for example on CONST_INT RTL expressions. */ +DEF_MACHMODE (VOIDmode, "VOID", MODE_RANDOM, 0, 0, VOIDmode) + +DEF_MACHMODE (QImode, "QI", MODE_INT, 1, 1, HImode) /* int types */ +DEF_MACHMODE (HImode, "HI", MODE_INT, 2, 2, SImode) +/* Pointers on some machines use this type to distinguish them from ints. + Useful if a pointer is 4 bytes but has some bits that are not significant, + so it is really not quite as wide as an integer. */ +DEF_MACHMODE (PSImode, "PSI", MODE_PARTIAL_INT, 4, 4, VOIDmode) +DEF_MACHMODE (SImode, "SI", MODE_INT, 4, 4, DImode) +DEF_MACHMODE (PDImode, "PDI", MODE_PARTIAL_INT, 8, 8, VOIDmode) +DEF_MACHMODE (DImode, "DI", MODE_INT, 8, 8, TImode) +DEF_MACHMODE (TImode, "TI", MODE_INT, 16, 16, OImode) +DEF_MACHMODE (OImode, "OI", MODE_INT, 32, 32, VOIDmode) + +DEF_MACHMODE (QFmode, "QF", MODE_FLOAT, 1, 1, HFmode) +DEF_MACHMODE (HFmode, "HF", MODE_FLOAT, 2, 2, SFmode) +DEF_MACHMODE (SFmode, "SF", MODE_FLOAT, 4, 4, DFmode) +DEF_MACHMODE (DFmode, "DF", MODE_FLOAT, 8, 8, XFmode) +DEF_MACHMODE (XFmode, "XF", MODE_FLOAT, 12, 12, TFmode) /* IEEE extended */ +DEF_MACHMODE (TFmode, "TF", MODE_FLOAT, 16, 16, VOIDmode) + +/* Complex modes. */ +DEF_MACHMODE (SCmode, "SC", MODE_COMPLEX_FLOAT, 8, 4, DCmode) +DEF_MACHMODE (DCmode, "DC", MODE_COMPLEX_FLOAT, 16, 8, XCmode) +DEF_MACHMODE (XCmode, "XC", MODE_COMPLEX_FLOAT, 24, 12, TCmode) +DEF_MACHMODE (TCmode, "TC", MODE_COMPLEX_FLOAT, 32, 16, VOIDmode) + +DEF_MACHMODE (CQImode, "CQI", MODE_COMPLEX_INT, 2, 1, CHImode) +DEF_MACHMODE (CHImode, "CHI", MODE_COMPLEX_INT, 4, 2, CSImode) +DEF_MACHMODE (CSImode, "CSI", MODE_COMPLEX_INT, 8, 4, CDImode) +DEF_MACHMODE (CDImode, "CDI", MODE_COMPLEX_INT, 16, 8, CTImode) +DEF_MACHMODE (CTImode, "CTI", MODE_COMPLEX_INT, 32, 16, COImode) +DEF_MACHMODE (COImode, "COI", MODE_COMPLEX_INT, 64, 32, VOIDmode) + +/* BLKmode is used for structures, arrays, etc. + that fit no more specific mode. */ +DEF_MACHMODE (BLKmode, "BLK", MODE_RANDOM, 0, 0, VOIDmode) + +/* The modes for representing the condition codes come last. CCmode is + always defined. Additional modes for the condition code can be specified + in the EXTRA_CC_MODES macro. Everything but the names of the modes + are copied from CCmode. For these modes, GET_MODE_WIDER_MODE points + to the next defined CC mode, if any. */ + +DEF_MACHMODE (CCmode, "CC", MODE_CC, 4, 4, VOIDmode) + +/* The symbol Pmode stands for one of the above machine modes (usually SImode). + The tm file specifies which one. It is not a distinct mode. */ + +/* +Local variables: +mode:c +version-control: t +End: +*/ diff --git a/gnu/usr.bin/cc/lib/machmode.h b/gnu/usr.bin/cc/lib/machmode.h new file mode 100644 index 000000000000..240bd5725f30 --- /dev/null +++ b/gnu/usr.bin/cc/lib/machmode.h @@ -0,0 +1,166 @@ +/* Machine mode definitions for GNU C-Compiler; included by rtl.h and tree.h. + Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* Add prototype support. */ +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif + +#ifndef HAVE_MACHINE_MODES + +/* Strictly speaking, this isn't the proper place to include these definitions, + but this file is included by every GCC file. + + Some systems define these in, e.g., param.h. We undefine these names + here to avoid the warnings. We prefer to use our definitions since we + know they are correct. */ + +#undef MIN +#undef MAX + +#define MIN(X,Y) ((X) < (Y) ? (X) : (Y)) +#define MAX(X,Y) ((X) > (Y) ? (X) : (Y)) + +/* Find the largest host integer type and set its size and type. */ + +#ifndef HOST_BITS_PER_WIDE_INT + +#if HOST_BITS_PER_LONG > HOST_BITS_PER_INT +#define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONG +#define HOST_WIDE_INT long +#else +#define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_INT +#define HOST_WIDE_INT int +#endif + +#endif + +/* Define the number of entries in an 8-bit `shorts' array needed to represent + the largest supported constant, which is twice the width of the largest + host integer type. */ + +#ifndef MAX_SHORTS +#define MAX_SHORTS (HOST_BITS_PER_WIDE_INT * 2 / 8) +#endif + +/* Provide a default way to print an address in hex via printf. */ + +#ifndef HOST_PTR_PRINTF +#define HOST_PTR_PRINTF sizeof (int) == sizeof (char *) ? "%x" : "%lx" +#endif + +/* Make an enum class that gives all the machine modes. */ + +#define DEF_MACHMODE(SYM, NAME, TYPE, SIZE, UNIT, WIDER) SYM, + +enum machine_mode { +#include "machmode.def" + +#ifdef EXTRA_CC_MODES + EXTRA_CC_MODES, +#endif +MAX_MACHINE_MODE }; + +#undef DEF_MACHMODE + +#define HAVE_MACHINE_MODES + +#ifndef NUM_MACHINE_MODES +#define NUM_MACHINE_MODES (int) MAX_MACHINE_MODE +#endif + +/* Get the name of mode MODE as a string. */ + +extern char *mode_name[]; +#define GET_MODE_NAME(MODE) (mode_name[(int)(MODE)]) + +enum mode_class { MODE_RANDOM, MODE_INT, MODE_FLOAT, MODE_PARTIAL_INT, MODE_CC, + MODE_COMPLEX_INT, MODE_COMPLEX_FLOAT, MAX_MODE_CLASS}; + +/* Get the general kind of object that mode MODE represents + (integer, floating, complex, etc.) */ + +extern enum mode_class mode_class[]; +#define GET_MODE_CLASS(MODE) (mode_class[(int)(MODE)]) + +/* Get the size in bytes of an object of mode MODE. */ + +extern int mode_size[]; +#define GET_MODE_SIZE(MODE) (mode_size[(int)(MODE)]) + +/* Get the size in bytes of the basic parts of an object of mode MODE. */ + +extern int mode_unit_size[]; +#define GET_MODE_UNIT_SIZE(MODE) (mode_unit_size[(int)(MODE)]) + +/* Get the number of units in the object. */ + +#define GET_MODE_NUNITS(MODE) \ + ((GET_MODE_UNIT_SIZE ((MODE)) == 0) ? 0 \ + : (GET_MODE_SIZE ((MODE)) / GET_MODE_UNIT_SIZE ((MODE)))) + +/* Get the size in bits of an object of mode MODE. */ + +#define GET_MODE_BITSIZE(MODE) (BITS_PER_UNIT * mode_size[(int)(MODE)]) + +/* Get a bitmask containing 1 for all bits in a word + that fit within mode MODE. */ + +#define GET_MODE_MASK(MODE) \ + ((GET_MODE_BITSIZE (MODE) >= HOST_BITS_PER_WIDE_INT) \ + ?(HOST_WIDE_INT) ~0 : (((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (MODE)) - 1)) + +/* Get the next wider natural mode (eg, QI -> HI -> SI -> DI -> TI). */ + +extern enum machine_mode mode_wider_mode[]; +#define GET_MODE_WIDER_MODE(MODE) (mode_wider_mode[(int)(MODE)]) + +/* Return the mode for data of a given size SIZE and mode class CLASS. + If LIMIT is nonzero, then don't use modes bigger than MAX_FIXED_MODE_SIZE. + The value is BLKmode if no other mode is found. */ + +extern enum machine_mode mode_for_size PROTO((unsigned int, enum mode_class, int)); + +/* Find the best mode to use to access a bit field. */ + +extern enum machine_mode get_best_mode PROTO((int, int, int, enum machine_mode, int)); + +/* Determine alignment, 1<=result<=BIGGEST_ALIGNMENT. */ + +#define GET_MODE_ALIGNMENT(MODE) \ + MIN (BIGGEST_ALIGNMENT, \ + MAX (1, (GET_MODE_UNIT_SIZE (MODE) * BITS_PER_UNIT))) + +/* For each class, get the narrowest mode in that class. */ + +extern enum machine_mode class_narrowest_mode[]; +#define GET_CLASS_NARROWEST_MODE(CLASS) class_narrowest_mode[(int)(CLASS)] + +/* Define the integer modes whose sizes are BITS_PER_UNIT + and BITS_PER_WORD. */ + +extern enum machine_mode byte_mode; +extern enum machine_mode word_mode; + +#endif /* not HAVE_MACHINE_MODES */ diff --git a/gnu/usr.bin/cc/lib/obstack.c b/gnu/usr.bin/cc/lib/obstack.c new file mode 100644 index 000000000000..7b9d3b9046d4 --- /dev/null +++ b/gnu/usr.bin/cc/lib/obstack.c @@ -0,0 +1,454 @@ +/* obstack.c - subroutines used implicitly by object stack macros + Copyright (C) 1988, 1993 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include "obstack.h" + +/* This is just to get __GNU_LIBRARY__ defined. */ +#include + +/* Comment out all this code if we are using the GNU C Library, and are not + actually compiling the library itself. This code is part of the GNU C + Library, but also included in many other GNU distributions. Compiling + and linking in this code is a waste when using the GNU C library + (especially if it is a shared library). Rather than having every GNU + program understand `configure --with-gnu-libc' and omit the object files, + it is simpler to just do this in the source for each such file. */ + +#if defined (_LIBC) || !defined (__GNU_LIBRARY__) + + +#ifdef __STDC__ +#define POINTER void * +#else +#define POINTER char * +#endif + +/* Determine default alignment. */ +struct fooalign {char x; double d;}; +#define DEFAULT_ALIGNMENT \ + ((PTR_INT_TYPE) ((char *)&((struct fooalign *) 0)->d - (char *)0)) +/* If malloc were really smart, it would round addresses to DEFAULT_ALIGNMENT. + But in fact it might be less smart and round addresses to as much as + DEFAULT_ROUNDING. So we prepare for it to do that. */ +union fooround {long x; double d;}; +#define DEFAULT_ROUNDING (sizeof (union fooround)) + +/* When we copy a long block of data, this is the unit to do it with. + On some machines, copying successive ints does not work; + in such a case, redefine COPYING_UNIT to `long' (if that works) + or `char' as a last resort. */ +#ifndef COPYING_UNIT +#define COPYING_UNIT int +#endif + +/* The non-GNU-C macros copy the obstack into this global variable + to avoid multiple evaluation. */ + +struct obstack *_obstack; + +/* Define a macro that either calls functions with the traditional malloc/free + calling interface, or calls functions with the mmalloc/mfree interface + (that adds an extra first argument), based on the state of use_extra_arg. + For free, do not use ?:, since some compilers, like the MIPS compilers, + do not allow (expr) ? void : void. */ + +#define CALL_CHUNKFUN(h, size) \ + (((h) -> use_extra_arg) \ + ? (*(h)->chunkfun) ((h)->extra_arg, (size)) \ + : (*(h)->chunkfun) ((size))) + +#define CALL_FREEFUN(h, old_chunk) \ + do { \ + if ((h) -> use_extra_arg) \ + (*(h)->freefun) ((h)->extra_arg, (old_chunk)); \ + else \ + (*(h)->freefun) ((old_chunk)); \ + } while (0) + + +/* Initialize an obstack H for use. Specify chunk size SIZE (0 means default). + Objects start on multiples of ALIGNMENT (0 means use default). + CHUNKFUN is the function to use to allocate chunks, + and FREEFUN the function to free them. */ + +void +_obstack_begin (h, size, alignment, chunkfun, freefun) + struct obstack *h; + int size; + int alignment; + POINTER (*chunkfun) (); + void (*freefun) (); +{ + register struct _obstack_chunk* chunk; /* points to new chunk */ + + if (alignment == 0) + alignment = DEFAULT_ALIGNMENT; + if (size == 0) + /* Default size is what GNU malloc can fit in a 4096-byte block. */ + { + /* 12 is sizeof (mhead) and 4 is EXTRA from GNU malloc. + Use the values for range checking, because if range checking is off, + the extra bytes won't be missed terribly, but if range checking is on + and we used a larger request, a whole extra 4096 bytes would be + allocated. + + These number are irrelevant to the new GNU malloc. I suspect it is + less sensitive to the size of the request. */ + int extra = ((((12 + DEFAULT_ROUNDING - 1) & ~(DEFAULT_ROUNDING - 1)) + + 4 + DEFAULT_ROUNDING - 1) + & ~(DEFAULT_ROUNDING - 1)); + size = 4096 - extra; + } + + h->chunkfun = (struct _obstack_chunk * (*)()) chunkfun; + h->freefun = freefun; + h->chunk_size = size; + h->alignment_mask = alignment - 1; + h->use_extra_arg = 0; + + chunk = h->chunk = CALL_CHUNKFUN (h, h -> chunk_size); + h->next_free = h->object_base = chunk->contents; + h->chunk_limit = chunk->limit + = (char *) chunk + h->chunk_size; + chunk->prev = 0; + /* The initial chunk now contains no empty object. */ + h->maybe_empty_object = 0; +} + +void +_obstack_begin_1 (h, size, alignment, chunkfun, freefun, arg) + struct obstack *h; + int size; + int alignment; + POINTER (*chunkfun) (); + void (*freefun) (); + POINTER arg; +{ + register struct _obstack_chunk* chunk; /* points to new chunk */ + + if (alignment == 0) + alignment = DEFAULT_ALIGNMENT; + if (size == 0) + /* Default size is what GNU malloc can fit in a 4096-byte block. */ + { + /* 12 is sizeof (mhead) and 4 is EXTRA from GNU malloc. + Use the values for range checking, because if range checking is off, + the extra bytes won't be missed terribly, but if range checking is on + and we used a larger request, a whole extra 4096 bytes would be + allocated. + + These number are irrelevant to the new GNU malloc. I suspect it is + less sensitive to the size of the request. */ + int extra = ((((12 + DEFAULT_ROUNDING - 1) & ~(DEFAULT_ROUNDING - 1)) + + 4 + DEFAULT_ROUNDING - 1) + & ~(DEFAULT_ROUNDING - 1)); + size = 4096 - extra; + } + + h->chunkfun = (struct _obstack_chunk * (*)()) chunkfun; + h->freefun = freefun; + h->chunk_size = size; + h->alignment_mask = alignment - 1; + h->extra_arg = arg; + h->use_extra_arg = 1; + + chunk = h->chunk = CALL_CHUNKFUN (h, h -> chunk_size); + h->next_free = h->object_base = chunk->contents; + h->chunk_limit = chunk->limit + = (char *) chunk + h->chunk_size; + chunk->prev = 0; + /* The initial chunk now contains no empty object. */ + h->maybe_empty_object = 0; +} + +/* Allocate a new current chunk for the obstack *H + on the assumption that LENGTH bytes need to be added + to the current object, or a new object of length LENGTH allocated. + Copies any partial object from the end of the old chunk + to the beginning of the new one. */ + +void +_obstack_newchunk (h, length) + struct obstack *h; + int length; +{ + register struct _obstack_chunk* old_chunk = h->chunk; + register struct _obstack_chunk* new_chunk; + register long new_size; + register int obj_size = h->next_free - h->object_base; + register int i; + int already; + + /* Compute size for new chunk. */ + new_size = (obj_size + length) + (obj_size >> 3) + 100; + if (new_size < h->chunk_size) + new_size = h->chunk_size; + + /* Allocate and initialize the new chunk. */ + new_chunk = h->chunk = CALL_CHUNKFUN (h, new_size); + new_chunk->prev = old_chunk; + new_chunk->limit = h->chunk_limit = (char *) new_chunk + new_size; + + /* Move the existing object to the new chunk. + Word at a time is fast and is safe if the object + is sufficiently aligned. */ + if (h->alignment_mask + 1 >= DEFAULT_ALIGNMENT) + { + for (i = obj_size / sizeof (COPYING_UNIT) - 1; + i >= 0; i--) + ((COPYING_UNIT *)new_chunk->contents)[i] + = ((COPYING_UNIT *)h->object_base)[i]; + /* We used to copy the odd few remaining bytes as one extra COPYING_UNIT, + but that can cross a page boundary on a machine + which does not do strict alignment for COPYING_UNITS. */ + already = obj_size / sizeof (COPYING_UNIT) * sizeof (COPYING_UNIT); + } + else + already = 0; + /* Copy remaining bytes one by one. */ + for (i = already; i < obj_size; i++) + new_chunk->contents[i] = h->object_base[i]; + + /* If the object just copied was the only data in OLD_CHUNK, + free that chunk and remove it from the chain. + But not if that chunk might contain an empty object. */ + if (h->object_base == old_chunk->contents && ! h->maybe_empty_object) + { + new_chunk->prev = old_chunk->prev; + CALL_FREEFUN (h, old_chunk); + } + + h->object_base = new_chunk->contents; + h->next_free = h->object_base + obj_size; + /* The new chunk certainly contains no empty object yet. */ + h->maybe_empty_object = 0; +} + +/* Return nonzero if object OBJ has been allocated from obstack H. + This is here for debugging. + If you use it in a program, you are probably losing. */ + +int +_obstack_allocated_p (h, obj) + struct obstack *h; + POINTER obj; +{ + register struct _obstack_chunk* lp; /* below addr of any objects in this chunk */ + register struct _obstack_chunk* plp; /* point to previous chunk if any */ + + lp = (h)->chunk; + /* We use >= rather than > since the object cannot be exactly at + the beginning of the chunk but might be an empty object exactly + at the end of an adjacent chunk. */ + while (lp != 0 && ((POINTER)lp >= obj || (POINTER)(lp)->limit < obj)) + { + plp = lp->prev; + lp = plp; + } + return lp != 0; +} + +/* Free objects in obstack H, including OBJ and everything allocate + more recently than OBJ. If OBJ is zero, free everything in H. */ + +#undef obstack_free + +/* This function has two names with identical definitions. + This is the first one, called from non-ANSI code. */ + +void +_obstack_free (h, obj) + struct obstack *h; + POINTER obj; +{ + register struct _obstack_chunk* lp; /* below addr of any objects in this chunk */ + register struct _obstack_chunk* plp; /* point to previous chunk if any */ + + lp = h->chunk; + /* We use >= because there cannot be an object at the beginning of a chunk. + But there can be an empty object at that address + at the end of another chunk. */ + while (lp != 0 && ((POINTER)lp >= obj || (POINTER)(lp)->limit < obj)) + { + plp = lp->prev; + CALL_FREEFUN (h, lp); + lp = plp; + /* If we switch chunks, we can't tell whether the new current + chunk contains an empty object, so assume that it may. */ + h->maybe_empty_object = 1; + } + if (lp) + { + h->object_base = h->next_free = (char *)(obj); + h->chunk_limit = lp->limit; + h->chunk = lp; + } + else if (obj != 0) + /* obj is not in any of the chunks! */ + abort (); +} + +/* This function is used from ANSI code. */ + +void +obstack_free (h, obj) + struct obstack *h; + POINTER obj; +{ + register struct _obstack_chunk* lp; /* below addr of any objects in this chunk */ + register struct _obstack_chunk* plp; /* point to previous chunk if any */ + + lp = h->chunk; + /* We use >= because there cannot be an object at the beginning of a chunk. + But there can be an empty object at that address + at the end of another chunk. */ + while (lp != 0 && ((POINTER)lp >= obj || (POINTER)(lp)->limit < obj)) + { + plp = lp->prev; + CALL_FREEFUN (h, lp); + lp = plp; + /* If we switch chunks, we can't tell whether the new current + chunk contains an empty object, so assume that it may. */ + h->maybe_empty_object = 1; + } + if (lp) + { + h->object_base = h->next_free = (char *)(obj); + h->chunk_limit = lp->limit; + h->chunk = lp; + } + else if (obj != 0) + /* obj is not in any of the chunks! */ + abort (); +} + +#if 0 +/* These are now turned off because the applications do not use it + and it uses bcopy via obstack_grow, which causes trouble on sysV. */ + +/* Now define the functional versions of the obstack macros. + Define them to simply use the corresponding macros to do the job. */ + +#ifdef __STDC__ +/* These function definitions do not work with non-ANSI preprocessors; + they won't pass through the macro names in parentheses. */ + +/* The function names appear in parentheses in order to prevent + the macro-definitions of the names from being expanded there. */ + +POINTER (obstack_base) (obstack) + struct obstack *obstack; +{ + return obstack_base (obstack); +} + +POINTER (obstack_next_free) (obstack) + struct obstack *obstack; +{ + return obstack_next_free (obstack); +} + +int (obstack_object_size) (obstack) + struct obstack *obstack; +{ + return obstack_object_size (obstack); +} + +int (obstack_room) (obstack) + struct obstack *obstack; +{ + return obstack_room (obstack); +} + +void (obstack_grow) (obstack, pointer, length) + struct obstack *obstack; + POINTER pointer; + int length; +{ + obstack_grow (obstack, pointer, length); +} + +void (obstack_grow0) (obstack, pointer, length) + struct obstack *obstack; + POINTER pointer; + int length; +{ + obstack_grow0 (obstack, pointer, length); +} + +void (obstack_1grow) (obstack, character) + struct obstack *obstack; + int character; +{ + obstack_1grow (obstack, character); +} + +void (obstack_blank) (obstack, length) + struct obstack *obstack; + int length; +{ + obstack_blank (obstack, length); +} + +void (obstack_1grow_fast) (obstack, character) + struct obstack *obstack; + int character; +{ + obstack_1grow_fast (obstack, character); +} + +void (obstack_blank_fast) (obstack, length) + struct obstack *obstack; + int length; +{ + obstack_blank_fast (obstack, length); +} + +POINTER (obstack_finish) (obstack) + struct obstack *obstack; +{ + return obstack_finish (obstack); +} + +POINTER (obstack_alloc) (obstack, length) + struct obstack *obstack; + int length; +{ + return obstack_alloc (obstack, length); +} + +POINTER (obstack_copy) (obstack, pointer, length) + struct obstack *obstack; + POINTER pointer; + int length; +{ + return obstack_copy (obstack, pointer, length); +} + +POINTER (obstack_copy0) (obstack, pointer, length) + struct obstack *obstack; + POINTER pointer; + int length; +{ + return obstack_copy0 (obstack, pointer, length); +} + +#endif /* __STDC__ */ + +#endif /* 0 */ + +#endif /* _LIBC or not __GNU_LIBRARY__. */ diff --git a/gnu/usr.bin/cc/lib/obstack.h b/gnu/usr.bin/cc/lib/obstack.h new file mode 100644 index 000000000000..d4335cf46ac0 --- /dev/null +++ b/gnu/usr.bin/cc/lib/obstack.h @@ -0,0 +1,484 @@ +/* obstack.h - object stack macros + Copyright (C) 1988, 1992 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Summary: + +All the apparent functions defined here are macros. The idea +is that you would use these pre-tested macros to solve a +very specific set of problems, and they would run fast. +Caution: no side-effects in arguments please!! They may be +evaluated MANY times!! + +These macros operate a stack of objects. Each object starts life +small, and may grow to maturity. (Consider building a word syllable +by syllable.) An object can move while it is growing. Once it has +been "finished" it never changes address again. So the "top of the +stack" is typically an immature growing object, while the rest of the +stack is of mature, fixed size and fixed address objects. + +These routines grab large chunks of memory, using a function you +supply, called `obstack_chunk_alloc'. On occasion, they free chunks, +by calling `obstack_chunk_free'. You must define them and declare +them before using any obstack macros. + +Each independent stack is represented by a `struct obstack'. +Each of the obstack macros expects a pointer to such a structure +as the first argument. + +One motivation for this package is the problem of growing char strings +in symbol tables. Unless you are "fascist pig with a read-only mind" +--Gosper's immortal quote from HAKMEM item 154, out of context--you +would not like to put any arbitrary upper limit on the length of your +symbols. + +In practice this often means you will build many short symbols and a +few long symbols. At the time you are reading a symbol you don't know +how long it is. One traditional method is to read a symbol into a +buffer, realloc()ating the buffer every time you try to read a symbol +that is longer than the buffer. This is beaut, but you still will +want to copy the symbol from the buffer to a more permanent +symbol-table entry say about half the time. + +With obstacks, you can work differently. Use one obstack for all symbol +names. As you read a symbol, grow the name in the obstack gradually. +When the name is complete, finalize it. Then, if the symbol exists already, +free the newly read name. + +The way we do this is to take a large chunk, allocating memory from +low addresses. When you want to build a symbol in the chunk you just +add chars above the current "high water mark" in the chunk. When you +have finished adding chars, because you got to the end of the symbol, +you know how long the chars are, and you can create a new object. +Mostly the chars will not burst over the highest address of the chunk, +because you would typically expect a chunk to be (say) 100 times as +long as an average object. + +In case that isn't clear, when we have enough chars to make up +the object, THEY ARE ALREADY CONTIGUOUS IN THE CHUNK (guaranteed) +so we just point to it where it lies. No moving of chars is +needed and this is the second win: potentially long strings need +never be explicitly shuffled. Once an object is formed, it does not +change its address during its lifetime. + +When the chars burst over a chunk boundary, we allocate a larger +chunk, and then copy the partly formed object from the end of the old +chunk to the beginning of the new larger chunk. We then carry on +accreting characters to the end of the object as we normally would. + +A special macro is provided to add a single char at a time to a +growing object. This allows the use of register variables, which +break the ordinary 'growth' macro. + +Summary: + We allocate large chunks. + We carve out one object at a time from the current chunk. + Once carved, an object never moves. + We are free to append data of any size to the currently + growing object. + Exactly one object is growing in an obstack at any one time. + You can run one obstack per control block. + You may have as many control blocks as you dare. + Because of the way we do it, you can `unwind' an obstack + back to a previous state. (You may remove objects much + as you would with a stack.) +*/ + + +/* Don't do the contents of this file more than once. */ + +#ifndef __OBSTACKS__ +#define __OBSTACKS__ + +/* We use subtraction of (char *)0 instead of casting to int + because on word-addressable machines a simple cast to int + may ignore the byte-within-word field of the pointer. */ + +#ifndef __PTR_TO_INT +#define __PTR_TO_INT(P) ((P) - (char *)0) +#endif + +#ifndef __INT_TO_PTR +#define __INT_TO_PTR(P) ((P) + (char *)0) +#endif + +/* We need the type of the resulting object. In ANSI C it is ptrdiff_t + but in traditional C it is usually long. If we are in ANSI C and + don't already have ptrdiff_t get it. */ + +#if defined (__STDC__) && ! defined (offsetof) +#if defined (__GNUC__) && defined (IN_GCC) +/* On Next machine, the system's stddef.h screws up if included + after we have defined just ptrdiff_t, so include all of gstddef.h. + Otherwise, define just ptrdiff_t, which is all we need. */ +#ifndef __NeXT__ +#define __need_ptrdiff_t +#endif + +/* While building GCC, the stddef.h that goes with GCC has this name. */ +#include "gstddef.h" +#else +#include +#endif +#endif + +#ifdef __STDC__ +#define PTR_INT_TYPE ptrdiff_t +#else +#define PTR_INT_TYPE long +#endif + +struct _obstack_chunk /* Lives at front of each chunk. */ +{ + char *limit; /* 1 past end of this chunk */ + struct _obstack_chunk *prev; /* address of prior chunk or NULL */ + char contents[4]; /* objects begin here */ +}; + +struct obstack /* control current object in current chunk */ +{ + long chunk_size; /* preferred size to allocate chunks in */ + struct _obstack_chunk* chunk; /* address of current struct obstack_chunk */ + char *object_base; /* address of object we are building */ + char *next_free; /* where to add next char to current object */ + char *chunk_limit; /* address of char after current chunk */ + PTR_INT_TYPE temp; /* Temporary for some macros. */ + int alignment_mask; /* Mask of alignment for each object. */ + struct _obstack_chunk *(*chunkfun) (); /* User's fcn to allocate a chunk. */ + void (*freefun) (); /* User's function to free a chunk. */ + char *extra_arg; /* first arg for chunk alloc/dealloc funcs */ + unsigned use_extra_arg:1; /* chunk alloc/dealloc funcs take extra arg */ + unsigned maybe_empty_object:1;/* There is a possibility that the current + chunk contains a zero-length object. This + prevents freeing the chunk if we allocate + a bigger chunk to replace it. */ +}; + +/* Declare the external functions we use; they are in obstack.c. */ + +#ifdef __STDC__ +extern void _obstack_newchunk (struct obstack *, int); +extern void _obstack_free (struct obstack *, void *); +extern void _obstack_begin (struct obstack *, int, int, + void *(*) (), void (*) ()); +extern void _obstack_begin_1 (struct obstack *, int, int, + void *(*) (), void (*) (), void *); +#else +extern void _obstack_newchunk (); +extern void _obstack_free (); +extern void _obstack_begin (); +extern void _obstack_begin_1 (); +#endif + +#ifdef __STDC__ + +/* Do the function-declarations after the structs + but before defining the macros. */ + +void obstack_init (struct obstack *obstack); + +void * obstack_alloc (struct obstack *obstack, int size); + +void * obstack_copy (struct obstack *obstack, void *address, int size); +void * obstack_copy0 (struct obstack *obstack, void *address, int size); + +void obstack_free (struct obstack *obstack, void *block); + +void obstack_blank (struct obstack *obstack, int size); + +void obstack_grow (struct obstack *obstack, void *data, int size); +void obstack_grow0 (struct obstack *obstack, void *data, int size); + +void obstack_1grow (struct obstack *obstack, int data_char); +void obstack_ptr_grow (struct obstack *obstack, void *data); +void obstack_int_grow (struct obstack *obstack, int data); + +void * obstack_finish (struct obstack *obstack); + +int obstack_object_size (struct obstack *obstack); + +int obstack_room (struct obstack *obstack); +void obstack_1grow_fast (struct obstack *obstack, int data_char); +void obstack_ptr_grow_fast (struct obstack *obstack, void *data); +void obstack_int_grow_fast (struct obstack *obstack, int data); +void obstack_blank_fast (struct obstack *obstack, int size); + +void * obstack_base (struct obstack *obstack); +void * obstack_next_free (struct obstack *obstack); +int obstack_alignment_mask (struct obstack *obstack); +int obstack_chunk_size (struct obstack *obstack); + +#endif /* __STDC__ */ + +/* Non-ANSI C cannot really support alternative functions for these macros, + so we do not declare them. */ + +/* Pointer to beginning of object being allocated or to be allocated next. + Note that this might not be the final address of the object + because a new chunk might be needed to hold the final size. */ + +#define obstack_base(h) ((h)->object_base) + +/* Size for allocating ordinary chunks. */ + +#define obstack_chunk_size(h) ((h)->chunk_size) + +/* Pointer to next byte not yet allocated in current chunk. */ + +#define obstack_next_free(h) ((h)->next_free) + +/* Mask specifying low bits that should be clear in address of an object. */ + +#define obstack_alignment_mask(h) ((h)->alignment_mask) + +#define obstack_init(h) \ + _obstack_begin ((h), 0, 0, \ + (void *(*) ()) obstack_chunk_alloc, (void (*) ()) obstack_chunk_free) + +#define obstack_begin(h, size) \ + _obstack_begin ((h), (size), 0, \ + (void *(*) ()) obstack_chunk_alloc, (void (*) ()) obstack_chunk_free) + +#define obstack_specify_allocation(h, size, alignment, chunkfun, freefun) \ + _obstack_begin ((h), (size), (alignment), \ + (void *(*) ()) (chunkfun), (void (*) ()) (freefun)) + +#define obstack_specify_allocation_with_arg(h, size, alignment, chunkfun, freefun, arg) \ + _obstack_begin_1 ((h), (size), (alignment), \ + (void *(*) ()) (chunkfun), (void (*) ()) (freefun), (arg)) + +#define obstack_1grow_fast(h,achar) (*((h)->next_free)++ = achar) + +#define obstack_blank_fast(h,n) ((h)->next_free += (n)) + +#if defined (__GNUC__) && defined (__STDC__) +#if __GNUC__ < 2 +#define __extension__ +#endif + +/* For GNU C, if not -traditional, + we can define these macros to compute all args only once + without using a global variable. + Also, we can avoid using the `temp' slot, to make faster code. */ + +#define obstack_object_size(OBSTACK) \ + __extension__ \ + ({ struct obstack *__o = (OBSTACK); \ + (unsigned) (__o->next_free - __o->object_base); }) + +#define obstack_room(OBSTACK) \ + __extension__ \ + ({ struct obstack *__o = (OBSTACK); \ + (unsigned) (__o->chunk_limit - __o->next_free); }) + +/* Note that the call to _obstack_newchunk is enclosed in (..., 0) + so that we can avoid having void expressions + in the arms of the conditional expression. + Casting the third operand to void was tried before, + but some compilers won't accept it. */ +#define obstack_grow(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + ((__o->next_free + __len > __o->chunk_limit) \ + ? (_obstack_newchunk (__o, __len), 0) : 0); \ + bcopy (where, __o->next_free, __len); \ + __o->next_free += __len; \ + (void) 0; }) + +#define obstack_grow0(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + ((__o->next_free + __len + 1 > __o->chunk_limit) \ + ? (_obstack_newchunk (__o, __len + 1), 0) : 0), \ + bcopy (where, __o->next_free, __len), \ + __o->next_free += __len, \ + *(__o->next_free)++ = 0; \ + (void) 0; }) + +#define obstack_1grow(OBSTACK,datum) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + ((__o->next_free + 1 > __o->chunk_limit) \ + ? (_obstack_newchunk (__o, 1), 0) : 0), \ + *(__o->next_free)++ = (datum); \ + (void) 0; }) + +/* These assume that the obstack alignment is good enough for pointers or ints, + and that the data added so far to the current object + shares that much alignment. */ + +#define obstack_ptr_grow(OBSTACK,datum) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + ((__o->next_free + sizeof (void *) > __o->chunk_limit) \ + ? (_obstack_newchunk (__o, sizeof (void *)), 0) : 0), \ + *((void **)__o->next_free)++ = ((void *)datum); \ + (void) 0; }) + +#define obstack_int_grow(OBSTACK,datum) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + ((__o->next_free + sizeof (int) > __o->chunk_limit) \ + ? (_obstack_newchunk (__o, sizeof (int)), 0) : 0), \ + *((int *)__o->next_free)++ = ((int)datum); \ + (void) 0; }) + +#define obstack_ptr_grow_fast(h,aptr) (*((void **)(h)->next_free)++ = (void *)aptr) +#define obstack_int_grow_fast(h,aint) (*((int *)(h)->next_free)++ = (int)aint) + +#define obstack_blank(OBSTACK,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + ((__o->chunk_limit - __o->next_free < __len) \ + ? (_obstack_newchunk (__o, __len), 0) : 0); \ + __o->next_free += __len; \ + (void) 0; }) + +#define obstack_alloc(OBSTACK,length) \ +__extension__ \ +({ struct obstack *__h = (OBSTACK); \ + obstack_blank (__h, (length)); \ + obstack_finish (__h); }) + +#define obstack_copy(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__h = (OBSTACK); \ + obstack_grow (__h, (where), (length)); \ + obstack_finish (__h); }) + +#define obstack_copy0(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__h = (OBSTACK); \ + obstack_grow0 (__h, (where), (length)); \ + obstack_finish (__h); }) + +/* The local variable is named __o1 to avoid a name conflict + when obstack_blank is called. */ +#define obstack_finish(OBSTACK) \ +__extension__ \ +({ struct obstack *__o1 = (OBSTACK); \ + void *value = (void *) __o1->object_base; \ + if (__o1->next_free == value) \ + __o1->maybe_empty_object = 1; \ + __o1->next_free \ + = __INT_TO_PTR ((__PTR_TO_INT (__o1->next_free)+__o1->alignment_mask)\ + & ~ (__o1->alignment_mask)); \ + ((__o1->next_free - (char *)__o1->chunk \ + > __o1->chunk_limit - (char *)__o1->chunk) \ + ? (__o1->next_free = __o1->chunk_limit) : 0); \ + __o1->object_base = __o1->next_free; \ + value; }) + +#define obstack_free(OBSTACK, OBJ) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + void *__obj = (OBJ); \ + if (__obj > (void *)__o->chunk && __obj < (void *)__o->chunk_limit) \ + __o->next_free = __o->object_base = __obj; \ + else (obstack_free) (__o, __obj); }) + +#else /* not __GNUC__ or not __STDC__ */ + +#define obstack_object_size(h) \ + (unsigned) ((h)->next_free - (h)->object_base) + +#define obstack_room(h) \ + (unsigned) ((h)->chunk_limit - (h)->next_free) + +#define obstack_grow(h,where,length) \ +( (h)->temp = (length), \ + (((h)->next_free + (h)->temp > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), (h)->temp), 0) : 0), \ + bcopy (where, (h)->next_free, (h)->temp), \ + (h)->next_free += (h)->temp) + +#define obstack_grow0(h,where,length) \ +( (h)->temp = (length), \ + (((h)->next_free + (h)->temp + 1 > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), (h)->temp + 1), 0) : 0), \ + bcopy (where, (h)->next_free, (h)->temp), \ + (h)->next_free += (h)->temp, \ + *((h)->next_free)++ = 0) + +#define obstack_1grow(h,datum) \ +( (((h)->next_free + 1 > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), 1), 0) : 0), \ + *((h)->next_free)++ = (datum)) + +#define obstack_ptr_grow(h,datum) \ +( (((h)->next_free + sizeof (char *) > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), sizeof (char *)), 0) : 0), \ + *((char **)(((h)->next_free+=sizeof(char *))-sizeof(char *))) = ((char *)datum)) + +#define obstack_int_grow(h,datum) \ +( (((h)->next_free + sizeof (int) > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), sizeof (int)), 0) : 0), \ + *((int *)(((h)->next_free+=sizeof(int))-sizeof(int))) = ((int)datum)) + +#define obstack_ptr_grow_fast(h,aptr) (*((char **)(h)->next_free)++ = (char *)aptr) +#define obstack_int_grow_fast(h,aint) (*((int *)(h)->next_free)++ = (int)aint) + +#define obstack_blank(h,length) \ +( (h)->temp = (length), \ + (((h)->chunk_limit - (h)->next_free < (h)->temp) \ + ? (_obstack_newchunk ((h), (h)->temp), 0) : 0), \ + (h)->next_free += (h)->temp) + +#define obstack_alloc(h,length) \ + (obstack_blank ((h), (length)), obstack_finish ((h))) + +#define obstack_copy(h,where,length) \ + (obstack_grow ((h), (where), (length)), obstack_finish ((h))) + +#define obstack_copy0(h,where,length) \ + (obstack_grow0 ((h), (where), (length)), obstack_finish ((h))) + +#define obstack_finish(h) \ +( ((h)->next_free == (h)->object_base \ + ? (((h)->maybe_empty_object = 1), 0) \ + : 0), \ + (h)->temp = __PTR_TO_INT ((h)->object_base), \ + (h)->next_free \ + = __INT_TO_PTR ((__PTR_TO_INT ((h)->next_free)+(h)->alignment_mask) \ + & ~ ((h)->alignment_mask)), \ + (((h)->next_free - (char *)(h)->chunk \ + > (h)->chunk_limit - (char *)(h)->chunk) \ + ? ((h)->next_free = (h)->chunk_limit) : 0), \ + (h)->object_base = (h)->next_free, \ + __INT_TO_PTR ((h)->temp)) + +#ifdef __STDC__ +#define obstack_free(h,obj) \ +( (h)->temp = (char *)(obj) - (char *) (h)->chunk, \ + (((h)->temp > 0 && (h)->temp < (h)->chunk_limit - (char *) (h)->chunk)\ + ? (int) ((h)->next_free = (h)->object_base \ + = (h)->temp + (char *) (h)->chunk) \ + : (((obstack_free) ((h), (h)->temp + (char *) (h)->chunk), 0), 0))) +#else +#define obstack_free(h,obj) \ +( (h)->temp = (char *)(obj) - (char *) (h)->chunk, \ + (((h)->temp > 0 && (h)->temp < (h)->chunk_limit - (char *) (h)->chunk)\ + ? (int) ((h)->next_free = (h)->object_base \ + = (h)->temp + (char *) (h)->chunk) \ + : (_obstack_free ((h), (h)->temp + (char *) (h)->chunk), 0))) +#endif + +#endif /* not __GNUC__ or not __STDC__ */ + +#endif /* not __OBSTACKS__ */ diff --git a/gnu/usr.bin/cc/lib/optabs.c b/gnu/usr.bin/cc/lib/optabs.c new file mode 100644 index 000000000000..9f37c5233a4a --- /dev/null +++ b/gnu/usr.bin/cc/lib/optabs.c @@ -0,0 +1,3614 @@ +/* Expand the basic unary and binary arithmetic operations, for GNU compiler. + Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include "rtl.h" +#include "tree.h" +#include "flags.h" +#include "insn-flags.h" +#include "insn-codes.h" +#include "expr.h" +#include "insn-config.h" +#include "recog.h" +#include "reload.h" +#include + +/* Each optab contains info on how this target machine + can perform a particular operation + for all sizes and kinds of operands. + + The operation to be performed is often specified + by passing one of these optabs as an argument. + + See expr.h for documentation of these optabs. */ + +optab add_optab; +optab sub_optab; +optab smul_optab; +optab smul_widen_optab; +optab umul_widen_optab; +optab sdiv_optab; +optab sdivmod_optab; +optab udiv_optab; +optab udivmod_optab; +optab smod_optab; +optab umod_optab; +optab flodiv_optab; +optab ftrunc_optab; +optab and_optab; +optab ior_optab; +optab xor_optab; +optab ashl_optab; +optab lshr_optab; +optab lshl_optab; +optab ashr_optab; +optab rotl_optab; +optab rotr_optab; +optab smin_optab; +optab smax_optab; +optab umin_optab; +optab umax_optab; + +optab mov_optab; +optab movstrict_optab; + +optab neg_optab; +optab abs_optab; +optab one_cmpl_optab; +optab ffs_optab; +optab sqrt_optab; +optab sin_optab; +optab cos_optab; + +optab cmp_optab; +optab ucmp_optab; /* Used only for libcalls for unsigned comparisons. */ +optab tst_optab; + +optab strlen_optab; + +/* Tables of patterns for extending one integer mode to another. */ +enum insn_code extendtab[MAX_MACHINE_MODE][MAX_MACHINE_MODE][2]; + +/* Tables of patterns for converting between fixed and floating point. */ +enum insn_code fixtab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2]; +enum insn_code fixtrunctab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2]; +enum insn_code floattab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2]; + +/* SYMBOL_REF rtx's for the library functions that are called + implicitly and not via optabs. */ + +rtx extendsfdf2_libfunc; +rtx extendsfxf2_libfunc; +rtx extendsftf2_libfunc; +rtx extenddfxf2_libfunc; +rtx extenddftf2_libfunc; + +rtx truncdfsf2_libfunc; +rtx truncxfsf2_libfunc; +rtx trunctfsf2_libfunc; +rtx truncxfdf2_libfunc; +rtx trunctfdf2_libfunc; + +rtx memcpy_libfunc; +rtx bcopy_libfunc; +rtx memcmp_libfunc; +rtx bcmp_libfunc; +rtx memset_libfunc; +rtx bzero_libfunc; + +rtx eqsf2_libfunc; +rtx nesf2_libfunc; +rtx gtsf2_libfunc; +rtx gesf2_libfunc; +rtx ltsf2_libfunc; +rtx lesf2_libfunc; + +rtx eqdf2_libfunc; +rtx nedf2_libfunc; +rtx gtdf2_libfunc; +rtx gedf2_libfunc; +rtx ltdf2_libfunc; +rtx ledf2_libfunc; + +rtx eqxf2_libfunc; +rtx nexf2_libfunc; +rtx gtxf2_libfunc; +rtx gexf2_libfunc; +rtx ltxf2_libfunc; +rtx lexf2_libfunc; + +rtx eqtf2_libfunc; +rtx netf2_libfunc; +rtx gttf2_libfunc; +rtx getf2_libfunc; +rtx lttf2_libfunc; +rtx letf2_libfunc; + +rtx floatsisf_libfunc; +rtx floatdisf_libfunc; +rtx floattisf_libfunc; + +rtx floatsidf_libfunc; +rtx floatdidf_libfunc; +rtx floattidf_libfunc; + +rtx floatsixf_libfunc; +rtx floatdixf_libfunc; +rtx floattixf_libfunc; + +rtx floatsitf_libfunc; +rtx floatditf_libfunc; +rtx floattitf_libfunc; + +rtx fixsfsi_libfunc; +rtx fixsfdi_libfunc; +rtx fixsfti_libfunc; + +rtx fixdfsi_libfunc; +rtx fixdfdi_libfunc; +rtx fixdfti_libfunc; + +rtx fixxfsi_libfunc; +rtx fixxfdi_libfunc; +rtx fixxfti_libfunc; + +rtx fixtfsi_libfunc; +rtx fixtfdi_libfunc; +rtx fixtfti_libfunc; + +rtx fixunssfsi_libfunc; +rtx fixunssfdi_libfunc; +rtx fixunssfti_libfunc; + +rtx fixunsdfsi_libfunc; +rtx fixunsdfdi_libfunc; +rtx fixunsdfti_libfunc; + +rtx fixunsxfsi_libfunc; +rtx fixunsxfdi_libfunc; +rtx fixunsxfti_libfunc; + +rtx fixunstfsi_libfunc; +rtx fixunstfdi_libfunc; +rtx fixunstfti_libfunc; + +/* from emit-rtl.c */ +extern rtx gen_highpart (); + +/* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) + gives the gen_function to make a branch to test that condition. */ + +rtxfun bcc_gen_fctn[NUM_RTX_CODE]; + +/* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) + gives the insn code to make a store-condition insn + to test that condition. */ + +enum insn_code setcc_gen_code[NUM_RTX_CODE]; + +static int add_equal_note PROTO((rtx, rtx, enum rtx_code, rtx, rtx)); +static void emit_float_lib_cmp PROTO((rtx, rtx, enum rtx_code)); +static enum insn_code can_fix_p PROTO((enum machine_mode, enum machine_mode, + int, int *)); +static enum insn_code can_float_p PROTO((enum machine_mode, enum machine_mode, + int)); +static rtx ftruncify PROTO((rtx)); +static optab init_optab PROTO((enum rtx_code)); +static void init_libfuncs PROTO((optab, int, int, char *, int)); +static void init_integral_libfuncs PROTO((optab, char *, int)); +static void init_floating_libfuncs PROTO((optab, char *, int)); +static void init_complex_libfuncs PROTO((optab, char *, int)); + +/* Add a REG_EQUAL note to the last insn in SEQ. TARGET is being set to + the result of operation CODE applied to OP0 (and OP1 if it is a binary + operation). + + If the last insn does not set TARGET, don't do anything, but return 1. + + If a previous insn sets TARGET and TARGET is one of OP0 or OP1, + don't add the REG_EQUAL note but return 0. Our caller can then try + again, ensuring that TARGET is not one of the operands. */ + +static int +add_equal_note (seq, target, code, op0, op1) + rtx seq; + rtx target; + enum rtx_code code; + rtx op0, op1; +{ + rtx set; + int i; + rtx note; + + if ((GET_RTX_CLASS (code) != '1' && GET_RTX_CLASS (code) != '2' + && GET_RTX_CLASS (code) != 'c' && GET_RTX_CLASS (code) != '<') + || GET_CODE (seq) != SEQUENCE + || (set = single_set (XVECEXP (seq, 0, XVECLEN (seq, 0) - 1))) == 0 + || GET_CODE (target) == ZERO_EXTRACT + || (! rtx_equal_p (SET_DEST (set), target) + /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside the + SUBREG. */ + && (GET_CODE (SET_DEST (set)) != STRICT_LOW_PART + || ! rtx_equal_p (SUBREG_REG (XEXP (SET_DEST (set), 0)), + target)))) + return 1; + + /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET + besides the last insn. */ + if (reg_overlap_mentioned_p (target, op0) + || (op1 && reg_overlap_mentioned_p (target, op1))) + for (i = XVECLEN (seq, 0) - 2; i >= 0; i--) + if (reg_set_p (target, XVECEXP (seq, 0, i))) + return 0; + + if (GET_RTX_CLASS (code) == '1') + note = gen_rtx (code, GET_MODE (target), copy_rtx (op0)); + else + note = gen_rtx (code, GET_MODE (target), copy_rtx (op0), copy_rtx (op1)); + + REG_NOTES (XVECEXP (seq, 0, XVECLEN (seq, 0) - 1)) + = gen_rtx (EXPR_LIST, REG_EQUAL, note, + REG_NOTES (XVECEXP (seq, 0, XVECLEN (seq, 0) - 1))); + + return 1; +} + +/* Generate code to perform an operation specified by BINOPTAB + on operands OP0 and OP1, with result having machine-mode MODE. + + UNSIGNEDP is for the case where we have to widen the operands + to perform the operation. It says to use zero-extension. + + If TARGET is nonzero, the value + is generated there, if it is convenient to do so. + In all cases an rtx is returned for the locus of the value; + this may or may not be TARGET. */ + +rtx +expand_binop (mode, binoptab, op0, op1, target, unsignedp, methods) + enum machine_mode mode; + optab binoptab; + rtx op0, op1; + rtx target; + int unsignedp; + enum optab_methods methods; +{ + enum mode_class class; + enum machine_mode wider_mode; + register rtx temp; + int commutative_op = 0; + int shift_op = (binoptab->code == ASHIFT + || binoptab->code == ASHIFTRT + || binoptab->code == LSHIFT + || binoptab->code == LSHIFTRT + || binoptab->code == ROTATE + || binoptab->code == ROTATERT); + rtx entry_last = get_last_insn (); + rtx last; + + class = GET_MODE_CLASS (mode); + + op0 = protect_from_queue (op0, 0); + op1 = protect_from_queue (op1, 0); + if (target) + target = protect_from_queue (target, 1); + + if (flag_force_mem) + { + op0 = force_not_mem (op0); + op1 = force_not_mem (op1); + } + + /* If subtracting an integer constant, convert this into an addition of + the negated constant. */ + + if (binoptab == sub_optab && GET_CODE (op1) == CONST_INT) + { + op1 = negate_rtx (mode, op1); + binoptab = add_optab; + } + + /* If we are inside an appropriately-short loop and one operand is an + expensive constant, force it into a register. */ + if (CONSTANT_P (op0) && preserve_subexpressions_p () + && rtx_cost (op0, binoptab->code) > 2) + op0 = force_reg (mode, op0); + + if (CONSTANT_P (op1) && preserve_subexpressions_p () + && rtx_cost (op1, binoptab->code) > 2) + op1 = force_reg (shift_op ? word_mode : mode, op1); + + /* Record where to delete back to if we backtrack. */ + last = get_last_insn (); + + /* If operation is commutative, + try to make the first operand a register. + Even better, try to make it the same as the target. + Also try to make the last operand a constant. */ + if (GET_RTX_CLASS (binoptab->code) == 'c' + || binoptab == smul_widen_optab + || binoptab == umul_widen_optab) + { + commutative_op = 1; + + if (((target == 0 || GET_CODE (target) == REG) + ? ((GET_CODE (op1) == REG + && GET_CODE (op0) != REG) + || target == op1) + : rtx_equal_p (op1, target)) + || GET_CODE (op0) == CONST_INT) + { + temp = op1; + op1 = op0; + op0 = temp; + } + } + + /* If we can do it with a three-operand insn, do so. */ + + if (methods != OPTAB_MUST_WIDEN + && binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + { + int icode = (int) binoptab->handlers[(int) mode].insn_code; + enum machine_mode mode0 = insn_operand_mode[icode][1]; + enum machine_mode mode1 = insn_operand_mode[icode][2]; + rtx pat; + rtx xop0 = op0, xop1 = op1; + + if (target) + temp = target; + else + temp = gen_reg_rtx (mode); + + /* If it is a commutative operator and the modes would match + if we would swap the operands, we can save the conversions. */ + if (commutative_op) + { + if (GET_MODE (op0) != mode0 && GET_MODE (op1) != mode1 + && GET_MODE (op0) == mode1 && GET_MODE (op1) == mode0) + { + register rtx tmp; + + tmp = op0; op0 = op1; op1 = tmp; + tmp = xop0; xop0 = xop1; xop1 = tmp; + } + } + + /* In case the insn wants input operands in modes different from + the result, convert the operands. */ + + if (GET_MODE (op0) != VOIDmode + && GET_MODE (op0) != mode0) + xop0 = convert_to_mode (mode0, xop0, unsignedp); + + if (GET_MODE (xop1) != VOIDmode + && GET_MODE (xop1) != mode1) + xop1 = convert_to_mode (mode1, xop1, unsignedp); + + /* Now, if insn's predicates don't allow our operands, put them into + pseudo regs. */ + + if (! (*insn_operand_predicate[icode][1]) (xop0, mode0)) + xop0 = copy_to_mode_reg (mode0, xop0); + + if (! (*insn_operand_predicate[icode][2]) (xop1, mode1)) + xop1 = copy_to_mode_reg (mode1, xop1); + + if (! (*insn_operand_predicate[icode][0]) (temp, mode)) + temp = gen_reg_rtx (mode); + + pat = GEN_FCN (icode) (temp, xop0, xop1); + if (pat) + { + /* If PAT is a multi-insn sequence, try to add an appropriate + REG_EQUAL note to it. If we can't because TEMP conflicts with an + operand, call ourselves again, this time without a target. */ + if (GET_CODE (pat) == SEQUENCE + && ! add_equal_note (pat, temp, binoptab->code, xop0, xop1)) + { + delete_insns_since (last); + return expand_binop (mode, binoptab, op0, op1, NULL_RTX, + unsignedp, methods); + } + + emit_insn (pat); + return temp; + } + else + delete_insns_since (last); + } + + /* If this is a multiply, see if we can do a widening operation that + takes operands of this mode and makes a wider mode. */ + + if (binoptab == smul_optab && GET_MODE_WIDER_MODE (mode) != VOIDmode + && (((unsignedp ? umul_widen_optab : smul_widen_optab) + ->handlers[(int) GET_MODE_WIDER_MODE (mode)].insn_code) + != CODE_FOR_nothing)) + { + temp = expand_binop (GET_MODE_WIDER_MODE (mode), + unsignedp ? umul_widen_optab : smul_widen_optab, + op0, op1, 0, unsignedp, OPTAB_DIRECT); + + if (GET_MODE_CLASS (mode) == MODE_INT) + return gen_lowpart (mode, temp); + else + return convert_to_mode (mode, temp, unsignedp); + } + + /* Look for a wider mode of the same class for which we think we + can open-code the operation. Check for a widening multiply at the + wider mode as well. */ + + if ((class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) + && methods != OPTAB_DIRECT && methods != OPTAB_LIB) + for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + { + if (binoptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing + || (binoptab == smul_optab + && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode + && (((unsignedp ? umul_widen_optab : smul_widen_optab) + ->handlers[(int) GET_MODE_WIDER_MODE (wider_mode)].insn_code) + != CODE_FOR_nothing))) + { + rtx xop0 = op0, xop1 = op1; + int no_extend = 0; + + /* For certain integer operations, we need not actually extend + the narrow operands, as long as we will truncate + the results to the same narrowness. Don't do this when + WIDER_MODE is wider than a word since a paradoxical SUBREG + isn't valid for such modes. */ + + if ((binoptab == ior_optab || binoptab == and_optab + || binoptab == xor_optab + || binoptab == add_optab || binoptab == sub_optab + || binoptab == smul_optab + || binoptab == ashl_optab || binoptab == lshl_optab) + && class == MODE_INT + && GET_MODE_SIZE (wider_mode) <= UNITS_PER_WORD) + no_extend = 1; + + /* If an operand is a constant integer, we might as well + convert it since that is more efficient than using a SUBREG, + unlike the case for other operands. Similarly for + SUBREGs that were made due to promoted objects. */ + + if (no_extend && GET_MODE (xop0) != VOIDmode + && ! (GET_CODE (xop0) == SUBREG + && SUBREG_PROMOTED_VAR_P (xop0))) + xop0 = gen_rtx (SUBREG, wider_mode, + force_reg (GET_MODE (xop0), xop0), 0); + else + xop0 = convert_to_mode (wider_mode, xop0, unsignedp); + + if (no_extend && GET_MODE (xop1) != VOIDmode + && ! (GET_CODE (xop1) == SUBREG + && SUBREG_PROMOTED_VAR_P (xop1))) + xop1 = gen_rtx (SUBREG, wider_mode, + force_reg (GET_MODE (xop1), xop1), 0); + else + xop1 = convert_to_mode (wider_mode, xop1, unsignedp); + + temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, + unsignedp, OPTAB_DIRECT); + if (temp) + { + if (class != MODE_INT) + { + if (target == 0) + target = gen_reg_rtx (mode); + convert_move (target, temp, 0); + return target; + } + else + return gen_lowpart (mode, temp); + } + else + delete_insns_since (last); + } + } + + /* These can be done a word at a time. */ + if ((binoptab == and_optab || binoptab == ior_optab || binoptab == xor_optab) + && class == MODE_INT + && GET_MODE_SIZE (mode) > UNITS_PER_WORD + && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) + { + int i; + rtx insns; + rtx equiv_value; + + /* If TARGET is the same as one of the operands, the REG_EQUAL note + won't be accurate, so use a new target. */ + if (target == 0 || target == op0 || target == op1) + target = gen_reg_rtx (mode); + + start_sequence (); + + /* Do the actual arithmetic. */ + for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) + { + rtx target_piece = operand_subword (target, i, 1, mode); + rtx x = expand_binop (word_mode, binoptab, + operand_subword_force (op0, i, mode), + operand_subword_force (op1, i, mode), + target_piece, unsignedp, methods); + if (target_piece != x) + emit_move_insn (target_piece, x); + } + + insns = get_insns (); + end_sequence (); + + if (binoptab->code != UNKNOWN) + equiv_value + = gen_rtx (binoptab->code, mode, copy_rtx (op0), copy_rtx (op1)); + else + equiv_value = 0; + + emit_no_conflict_block (insns, target, op0, op1, equiv_value); + return target; + } + + /* These can be done a word at a time by propagating carries. */ + if ((binoptab == add_optab || binoptab == sub_optab) + && class == MODE_INT + && GET_MODE_SIZE (mode) >= 2 * UNITS_PER_WORD + && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) + { + int i; + rtx carry_tmp = gen_reg_rtx (word_mode); + optab otheroptab = binoptab == add_optab ? sub_optab : add_optab; + int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; + rtx carry_in, carry_out; + rtx xop0, xop1; + + /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG + value is one of those, use it. Otherwise, use 1 since it is the + one easiest to get. */ +#if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 + int normalizep = STORE_FLAG_VALUE; +#else + int normalizep = 1; +#endif + + /* Prepare the operands. */ + xop0 = force_reg (mode, op0); + xop1 = force_reg (mode, op1); + + if (target == 0 || GET_CODE (target) != REG + || target == xop0 || target == xop1) + target = gen_reg_rtx (mode); + + /* Indicate for flow that the entire target reg is being set. */ + if (GET_CODE (target) == REG) + emit_insn (gen_rtx (CLOBBER, VOIDmode, target)); + + /* Do the actual arithmetic. */ + for (i = 0; i < nwords; i++) + { + int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); + rtx target_piece = operand_subword (target, index, 1, mode); + rtx op0_piece = operand_subword_force (xop0, index, mode); + rtx op1_piece = operand_subword_force (xop1, index, mode); + rtx x; + + /* Main add/subtract of the input operands. */ + x = expand_binop (word_mode, binoptab, + op0_piece, op1_piece, + target_piece, unsignedp, methods); + if (x == 0) + break; + + if (i + 1 < nwords) + { + /* Store carry from main add/subtract. */ + carry_out = gen_reg_rtx (word_mode); + carry_out = emit_store_flag (carry_out, + binoptab == add_optab ? LTU : GTU, + x, op0_piece, + word_mode, 1, normalizep); + if (!carry_out) + break; + } + + if (i > 0) + { + /* Add/subtract previous carry to main result. */ + x = expand_binop (word_mode, + normalizep == 1 ? binoptab : otheroptab, + x, carry_in, + target_piece, 1, methods); + if (target_piece != x) + emit_move_insn (target_piece, x); + + if (i + 1 < nwords) + { + /* THIS CODE HAS NOT BEEN TESTED. */ + /* Get out carry from adding/subtracting carry in. */ + carry_tmp = emit_store_flag (carry_tmp, + binoptab == add_optab + ? LTU : GTU, + x, carry_in, + word_mode, 1, normalizep); + /* Logical-ior the two poss. carry together. */ + carry_out = expand_binop (word_mode, ior_optab, + carry_out, carry_tmp, + carry_out, 0, methods); + if (!carry_out) + break; + } + } + + carry_in = carry_out; + } + + if (i == GET_MODE_BITSIZE (mode) / BITS_PER_WORD) + { + rtx temp; + + temp = emit_move_insn (target, target); + REG_NOTES (temp) = gen_rtx (EXPR_LIST, REG_EQUAL, + gen_rtx (binoptab->code, mode, + copy_rtx (xop0), + copy_rtx (xop1)), + REG_NOTES (temp)); + return target; + } + else + delete_insns_since (last); + } + + /* If we want to multiply two two-word values and have normal and widening + multiplies of single-word values, we can do this with three smaller + multiplications. Note that we do not make a REG_NO_CONFLICT block here + because we are not operating on one word at a time. + + The multiplication proceeds as follows: + _______________________ + [__op0_high_|__op0_low__] + _______________________ + * [__op1_high_|__op1_low__] + _______________________________________________ + _______________________ + (1) [__op0_low__*__op1_low__] + _______________________ + (2a) [__op0_low__*__op1_high_] + _______________________ + (2b) [__op0_high_*__op1_low__] + _______________________ + (3) [__op0_high_*__op1_high_] + + + This gives a 4-word result. Since we are only interested in the + lower 2 words, partial result (3) and the upper words of (2a) and + (2b) don't need to be calculated. Hence (2a) and (2b) can be + calculated using non-widening multiplication. + + (1), however, needs to be calculated with an unsigned widening + multiplication. If this operation is not directly supported we + try using a signed widening multiplication and adjust the result. + This adjustment works as follows: + + If both operands are positive then no adjustment is needed. + + If the operands have different signs, for example op0_low < 0 and + op1_low >= 0, the instruction treats the most significant bit of + op0_low as a sign bit instead of a bit with significance + 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low + with 2**BITS_PER_WORD - op0_low, and two's complements the + result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to + the result. + + Similarly, if both operands are negative, we need to add + (op0_low + op1_low) * 2**BITS_PER_WORD. + + We use a trick to adjust quickly. We logically shift op0_low right + (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to + op0_high (op1_high) before it is used to calculate 2b (2a). If no + logical shift exists, we do an arithmetic right shift and subtract + the 0 or -1. */ + + if (binoptab == smul_optab + && class == MODE_INT + && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD + && smul_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing + && add_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing + && ((umul_widen_optab->handlers[(int) mode].insn_code + != CODE_FOR_nothing) + || (smul_widen_optab->handlers[(int) mode].insn_code + != CODE_FOR_nothing))) + { + int low = (WORDS_BIG_ENDIAN ? 1 : 0); + int high = (WORDS_BIG_ENDIAN ? 0 : 1); + rtx op0_high = operand_subword_force (op0, high, mode); + rtx op0_low = operand_subword_force (op0, low, mode); + rtx op1_high = operand_subword_force (op1, high, mode); + rtx op1_low = operand_subword_force (op1, low, mode); + rtx product = 0; + rtx op0_xhigh; + rtx op1_xhigh; + + /* If the target is the same as one of the inputs, don't use it. This + prevents problems with the REG_EQUAL note. */ + if (target == op0 || target == op1) + target = 0; + + /* Multiply the two lower words to get a double-word product. + If unsigned widening multiplication is available, use that; + otherwise use the signed form and compensate. */ + + if (umul_widen_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + { + product = expand_binop (mode, umul_widen_optab, op0_low, op1_low, + target, 1, OPTAB_DIRECT); + + /* If we didn't succeed, delete everything we did so far. */ + if (product == 0) + delete_insns_since (last); + else + op0_xhigh = op0_high, op1_xhigh = op1_high; + } + + if (product == 0 + && smul_widen_optab->handlers[(int) mode].insn_code + != CODE_FOR_nothing) + { + rtx wordm1 = GEN_INT (BITS_PER_WORD - 1); + product = expand_binop (mode, smul_widen_optab, op0_low, op1_low, + target, 1, OPTAB_DIRECT); + op0_xhigh = expand_binop (word_mode, lshr_optab, op0_low, wordm1, + NULL_RTX, 1, OPTAB_DIRECT); + if (op0_xhigh) + op0_xhigh = expand_binop (word_mode, add_optab, op0_high, + op0_xhigh, op0_xhigh, 0, OPTAB_DIRECT); + else + { + op0_xhigh = expand_binop (word_mode, ashr_optab, op0_low, wordm1, + NULL_RTX, 0, OPTAB_DIRECT); + if (op0_xhigh) + op0_xhigh = expand_binop (word_mode, sub_optab, op0_high, + op0_xhigh, op0_xhigh, 0, + OPTAB_DIRECT); + } + + op1_xhigh = expand_binop (word_mode, lshr_optab, op1_low, wordm1, + NULL_RTX, 1, OPTAB_DIRECT); + if (op1_xhigh) + op1_xhigh = expand_binop (word_mode, add_optab, op1_high, + op1_xhigh, op1_xhigh, 0, OPTAB_DIRECT); + else + { + op1_xhigh = expand_binop (word_mode, ashr_optab, op1_low, wordm1, + NULL_RTX, 0, OPTAB_DIRECT); + if (op1_xhigh) + op1_xhigh = expand_binop (word_mode, sub_optab, op1_high, + op1_xhigh, op1_xhigh, 0, + OPTAB_DIRECT); + } + } + + /* If we have been able to directly compute the product of the + low-order words of the operands and perform any required adjustments + of the operands, we proceed by trying two more multiplications + and then computing the appropriate sum. + + We have checked above that the required addition is provided. + Full-word addition will normally always succeed, especially if + it is provided at all, so we don't worry about its failure. The + multiplication may well fail, however, so we do handle that. */ + + if (product && op0_xhigh && op1_xhigh) + { + rtx product_piece; + rtx product_high = operand_subword (product, high, 1, mode); + rtx temp = expand_binop (word_mode, binoptab, op0_low, op1_xhigh, + NULL_RTX, 0, OPTAB_DIRECT); + + if (temp) + { + product_piece = expand_binop (word_mode, add_optab, temp, + product_high, product_high, + 0, OPTAB_LIB_WIDEN); + if (product_piece != product_high) + emit_move_insn (product_high, product_piece); + + temp = expand_binop (word_mode, binoptab, op1_low, op0_xhigh, + NULL_RTX, 0, OPTAB_DIRECT); + + product_piece = expand_binop (word_mode, add_optab, temp, + product_high, product_high, + 0, OPTAB_LIB_WIDEN); + if (product_piece != product_high) + emit_move_insn (product_high, product_piece); + + temp = emit_move_insn (product, product); + REG_NOTES (temp) = gen_rtx (EXPR_LIST, REG_EQUAL, + gen_rtx (MULT, mode, copy_rtx (op0), + copy_rtx (op1)), + REG_NOTES (temp)); + + return product; + } + } + + /* If we get here, we couldn't do it for some reason even though we + originally thought we could. Delete anything we've emitted in + trying to do it. */ + + delete_insns_since (last); + } + + /* We need to open-code the complex type operations: '+, -, * and /' */ + + /* At this point we allow operations between two similar complex + numbers, and also if one of the operands is not a complex number + but rather of MODE_FLOAT or MODE_INT. However, the caller + must make sure that the MODE of the non-complex operand matches + the SUBMODE of the complex operand. */ + + if (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT) + { + rtx real0 = (rtx) 0; + rtx imag0 = (rtx) 0; + rtx real1 = (rtx) 0; + rtx imag1 = (rtx) 0; + rtx realr; + rtx imagr; + rtx res; + rtx seq; + rtx equiv_value; + + /* Find the correct mode for the real and imaginary parts */ + enum machine_mode submode + = mode_for_size (GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT, + class == MODE_COMPLEX_INT ? MODE_INT : MODE_FLOAT, + 0); + + if (submode == BLKmode) + abort (); + + if (! target) + target = gen_reg_rtx (mode); + + start_sequence (); + + realr = gen_realpart (submode, target); + imagr = gen_imagpart (submode, target); + + if (GET_MODE (op0) == mode) + { + real0 = gen_realpart (submode, op0); + imag0 = gen_imagpart (submode, op0); + } + else + real0 = op0; + + if (GET_MODE (op1) == mode) + { + real1 = gen_realpart (submode, op1); + imag1 = gen_imagpart (submode, op1); + } + else + real1 = op1; + + if (! real0 || ! real1 || ! (imag0 || imag1)) + abort (); + + switch (binoptab->code) + { + case PLUS: + /* (a+ib) + (c+id) = (a+c) + i(b+d) */ + case MINUS: + /* (a+ib) - (c+id) = (a-c) + i(b-d) */ + res = expand_binop (submode, binoptab, real0, real1, + realr, unsignedp, methods); + if (res != realr) + emit_move_insn (realr, res); + + if (imag0 && imag1) + res = expand_binop (submode, binoptab, imag0, imag1, + imagr, unsignedp, methods); + else if (imag0) + res = imag0; + else if (binoptab->code == MINUS) + res = expand_unop (submode, neg_optab, imag1, imagr, unsignedp); + else + res = imag1; + + if (res != imagr) + emit_move_insn (imagr, res); + break; + + case MULT: + /* (a+ib) * (c+id) = (ac-bd) + i(ad+cb) */ + + if (imag0 && imag1) + { + /* Don't fetch these from memory more than once. */ + real0 = force_reg (submode, real0); + real1 = force_reg (submode, real1); + imag0 = force_reg (submode, imag0); + imag1 = force_reg (submode, imag1); + + res = expand_binop (submode, sub_optab, + expand_binop (submode, binoptab, real0, + real1, 0, unsignedp, methods), + expand_binop (submode, binoptab, imag0, + imag1, 0, unsignedp, methods), + realr, unsignedp, methods); + + if (res != realr) + emit_move_insn (realr, res); + + res = expand_binop (submode, add_optab, + expand_binop (submode, binoptab, + real0, imag1, + 0, unsignedp, methods), + expand_binop (submode, binoptab, + real1, imag0, + 0, unsignedp, methods), + imagr, unsignedp, methods); + if (res != imagr) + emit_move_insn (imagr, res); + } + else + { + /* Don't fetch these from memory more than once. */ + real0 = force_reg (submode, real0); + real1 = force_reg (submode, real1); + + res = expand_binop (submode, binoptab, real0, real1, + realr, unsignedp, methods); + if (res != realr) + emit_move_insn (realr, res); + + if (imag0) + res = expand_binop (submode, binoptab, + real1, imag0, imagr, unsignedp, methods); + else + res = expand_binop (submode, binoptab, + real0, imag1, imagr, unsignedp, methods); + if (res != imagr) + emit_move_insn (imagr, res); + } + break; + + case DIV: + /* (a+ib) / (c+id) = ((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd)) */ + + if (! imag1) + { /* (a+ib) / (c+i0) = (a/c) + i(b/c) */ + + /* Don't fetch these from memory more than once. */ + real1 = force_reg (submode, real1); + + /* Simply divide the real and imaginary parts by `c' */ + res = expand_binop (submode, binoptab, real0, real1, + realr, unsignedp, methods); + if (res != realr) + emit_move_insn (realr, res); + + res = expand_binop (submode, binoptab, imag0, real1, + imagr, unsignedp, methods); + if (res != imagr) + emit_move_insn (imagr, res); + } + else /* Divisor is of complex type */ + { /* X/(a+ib) */ + + rtx divisor; + rtx real_t; + rtx imag_t; + + optab mulopt = unsignedp ? umul_widen_optab : smul_optab; + + /* Don't fetch these from memory more than once. */ + real0 = force_reg (submode, real0); + real1 = force_reg (submode, real1); + if (imag0) + imag0 = force_reg (submode, imag0); + imag1 = force_reg (submode, imag1); + + /* Divisor: c*c + d*d */ + divisor = expand_binop (submode, add_optab, + expand_binop (submode, mulopt, + real1, real1, + 0, unsignedp, methods), + expand_binop (submode, mulopt, + imag1, imag1, + 0, unsignedp, methods), + 0, unsignedp, methods); + + if (! imag0) /* ((a)(c-id))/divisor */ + { /* (a+i0) / (c+id) = (ac/(cc+dd)) + i(-ad/(cc+dd)) */ + /* Calculate the dividend */ + real_t = expand_binop (submode, mulopt, real0, real1, + 0, unsignedp, methods); + + imag_t + = expand_unop (submode, neg_optab, + expand_binop (submode, mulopt, real0, imag1, + 0, unsignedp, methods), + 0, unsignedp); + } + else /* ((a+ib)(c-id))/divider */ + { + /* Calculate the dividend */ + real_t = expand_binop (submode, add_optab, + expand_binop (submode, mulopt, + real0, real1, + 0, unsignedp, methods), + expand_binop (submode, mulopt, + imag0, imag1, + 0, unsignedp, methods), + 0, unsignedp, methods); + + imag_t = expand_binop (submode, sub_optab, + expand_binop (submode, mulopt, + imag0, real1, + 0, unsignedp, methods), + expand_binop (submode, mulopt, + real0, imag1, + 0, unsignedp, methods), + 0, unsignedp, methods); + + } + + res = expand_binop (submode, binoptab, real_t, divisor, + realr, unsignedp, methods); + if (res != realr) + emit_move_insn (realr, res); + + res = expand_binop (submode, binoptab, imag_t, divisor, + imagr, unsignedp, methods); + if (res != imagr) + emit_move_insn (imagr, res); + } + break; + + default: + abort (); + } + + seq = get_insns (); + end_sequence (); + + if (binoptab->code != UNKNOWN) + equiv_value + = gen_rtx (binoptab->code, mode, copy_rtx (op0), copy_rtx (op1)); + else + equiv_value = 0; + + emit_no_conflict_block (seq, target, op0, op1, equiv_value); + + return target; + } + + /* It can't be open-coded in this mode. + Use a library call if one is available and caller says that's ok. */ + + if (binoptab->handlers[(int) mode].libfunc + && (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN)) + { + rtx insns; + rtx funexp = binoptab->handlers[(int) mode].libfunc; + rtx op1x = op1; + enum machine_mode op1_mode = mode; + + start_sequence (); + + if (shift_op) + { + op1_mode = word_mode; + /* Specify unsigned here, + since negative shift counts are meaningless. */ + op1x = convert_to_mode (word_mode, op1, 1); + } + + /* Pass 1 for NO_QUEUE so we don't lose any increments + if the libcall is cse'd or moved. */ + emit_library_call (binoptab->handlers[(int) mode].libfunc, + 1, mode, 2, op0, mode, op1x, op1_mode); + + insns = get_insns (); + end_sequence (); + + target = gen_reg_rtx (mode); + emit_libcall_block (insns, target, hard_libcall_value (mode), + gen_rtx (binoptab->code, mode, op0, op1)); + + return target; + } + + delete_insns_since (last); + + /* It can't be done in this mode. Can we do it in a wider mode? */ + + if (! (methods == OPTAB_WIDEN || methods == OPTAB_LIB_WIDEN + || methods == OPTAB_MUST_WIDEN)) + { + /* Caller says, don't even try. */ + delete_insns_since (entry_last); + return 0; + } + + /* Compute the value of METHODS to pass to recursive calls. + Don't allow widening to be tried recursively. */ + + methods = (methods == OPTAB_LIB_WIDEN ? OPTAB_LIB : OPTAB_DIRECT); + + /* Look for a wider mode of the same class for which it appears we can do + the operation. */ + + if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) + { + for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + { + if ((binoptab->handlers[(int) wider_mode].insn_code + != CODE_FOR_nothing) + || (methods == OPTAB_LIB + && binoptab->handlers[(int) wider_mode].libfunc)) + { + rtx xop0 = op0, xop1 = op1; + int no_extend = 0; + + /* For certain integer operations, we need not actually extend + the narrow operands, as long as we will truncate + the results to the same narrowness. Don't do this when + WIDER_MODE is wider than a word since a paradoxical SUBREG + isn't valid for such modes. */ + + if ((binoptab == ior_optab || binoptab == and_optab + || binoptab == xor_optab + || binoptab == add_optab || binoptab == sub_optab + || binoptab == smul_optab + || binoptab == ashl_optab || binoptab == lshl_optab) + && class == MODE_INT + && GET_MODE_SIZE (wider_mode) <= UNITS_PER_WORD) + no_extend = 1; + + /* If an operand is a constant integer, we might as well + convert it since that is more efficient than using a SUBREG, + unlike the case for other operands. Similarly for + SUBREGs that were made due to promoted objects.*/ + + if (no_extend && GET_MODE (xop0) != VOIDmode + && ! (GET_CODE (xop0) == SUBREG + && SUBREG_PROMOTED_VAR_P (xop0))) + xop0 = gen_rtx (SUBREG, wider_mode, + force_reg (GET_MODE (xop0), xop0), 0); + else + xop0 = convert_to_mode (wider_mode, xop0, unsignedp); + + if (no_extend && GET_MODE (xop1) != VOIDmode + && ! (GET_CODE (xop1) == SUBREG + && SUBREG_PROMOTED_VAR_P (xop1))) + xop1 = gen_rtx (SUBREG, wider_mode, + force_reg (GET_MODE (xop1), xop1), 0); + else + xop1 = convert_to_mode (wider_mode, xop1, unsignedp); + + temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, + unsignedp, methods); + if (temp) + { + if (class != MODE_INT) + { + if (target == 0) + target = gen_reg_rtx (mode); + convert_move (target, temp, 0); + return target; + } + else + return gen_lowpart (mode, temp); + } + else + delete_insns_since (last); + } + } + } + + delete_insns_since (entry_last); + return 0; +} + +/* Expand a binary operator which has both signed and unsigned forms. + UOPTAB is the optab for unsigned operations, and SOPTAB is for + signed operations. + + If we widen unsigned operands, we may use a signed wider operation instead + of an unsigned wider operation, since the result would be the same. */ + +rtx +sign_expand_binop (mode, uoptab, soptab, op0, op1, target, unsignedp, methods) + enum machine_mode mode; + optab uoptab, soptab; + rtx op0, op1, target; + int unsignedp; + enum optab_methods methods; +{ + register rtx temp; + optab direct_optab = unsignedp ? uoptab : soptab; + struct optab wide_soptab; + + /* Do it without widening, if possible. */ + temp = expand_binop (mode, direct_optab, op0, op1, target, + unsignedp, OPTAB_DIRECT); + if (temp || methods == OPTAB_DIRECT) + return temp; + + /* Try widening to a signed int. Make a fake signed optab that + hides any signed insn for direct use. */ + wide_soptab = *soptab; + wide_soptab.handlers[(int) mode].insn_code = CODE_FOR_nothing; + wide_soptab.handlers[(int) mode].libfunc = 0; + + temp = expand_binop (mode, &wide_soptab, op0, op1, target, + unsignedp, OPTAB_WIDEN); + + /* For unsigned operands, try widening to an unsigned int. */ + if (temp == 0 && unsignedp) + temp = expand_binop (mode, uoptab, op0, op1, target, + unsignedp, OPTAB_WIDEN); + if (temp || methods == OPTAB_WIDEN) + return temp; + + /* Use the right width lib call if that exists. */ + temp = expand_binop (mode, direct_optab, op0, op1, target, unsignedp, OPTAB_LIB); + if (temp || methods == OPTAB_LIB) + return temp; + + /* Must widen and use a lib call, use either signed or unsigned. */ + temp = expand_binop (mode, &wide_soptab, op0, op1, target, + unsignedp, methods); + if (temp != 0) + return temp; + if (unsignedp) + return expand_binop (mode, uoptab, op0, op1, target, + unsignedp, methods); + return 0; +} + +/* Generate code to perform an operation specified by BINOPTAB + on operands OP0 and OP1, with two results to TARG1 and TARG2. + We assume that the order of the operands for the instruction + is TARG0, OP0, OP1, TARG1, which would fit a pattern like + [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))]. + + Either TARG0 or TARG1 may be zero, but what that means is that + that result is not actually wanted. We will generate it into + a dummy pseudo-reg and discard it. They may not both be zero. + + Returns 1 if this operation can be performed; 0 if not. */ + +int +expand_twoval_binop (binoptab, op0, op1, targ0, targ1, unsignedp) + optab binoptab; + rtx op0, op1; + rtx targ0, targ1; + int unsignedp; +{ + enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); + enum mode_class class; + enum machine_mode wider_mode; + rtx entry_last = get_last_insn (); + rtx last; + + class = GET_MODE_CLASS (mode); + + op0 = protect_from_queue (op0, 0); + op1 = protect_from_queue (op1, 0); + + if (flag_force_mem) + { + op0 = force_not_mem (op0); + op1 = force_not_mem (op1); + } + + /* If we are inside an appropriately-short loop and one operand is an + expensive constant, force it into a register. */ + if (CONSTANT_P (op0) && preserve_subexpressions_p () + && rtx_cost (op0, binoptab->code) > 2) + op0 = force_reg (mode, op0); + + if (CONSTANT_P (op1) && preserve_subexpressions_p () + && rtx_cost (op1, binoptab->code) > 2) + op1 = force_reg (mode, op1); + + if (targ0) + targ0 = protect_from_queue (targ0, 1); + else + targ0 = gen_reg_rtx (mode); + if (targ1) + targ1 = protect_from_queue (targ1, 1); + else + targ1 = gen_reg_rtx (mode); + + /* Record where to go back to if we fail. */ + last = get_last_insn (); + + if (binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + { + int icode = (int) binoptab->handlers[(int) mode].insn_code; + enum machine_mode mode0 = insn_operand_mode[icode][1]; + enum machine_mode mode1 = insn_operand_mode[icode][2]; + rtx pat; + rtx xop0 = op0, xop1 = op1; + + /* In case this insn wants input operands in modes different from the + result, convert the operands. */ + if (GET_MODE (op0) != VOIDmode && GET_MODE (op0) != mode0) + xop0 = convert_to_mode (mode0, xop0, unsignedp); + + if (GET_MODE (op1) != VOIDmode && GET_MODE (op1) != mode1) + xop1 = convert_to_mode (mode1, xop1, unsignedp); + + /* Now, if insn doesn't accept these operands, put them into pseudos. */ + if (! (*insn_operand_predicate[icode][1]) (xop0, mode0)) + xop0 = copy_to_mode_reg (mode0, xop0); + + if (! (*insn_operand_predicate[icode][2]) (xop1, mode1)) + xop1 = copy_to_mode_reg (mode1, xop1); + + /* We could handle this, but we should always be called with a pseudo + for our targets and all insns should take them as outputs. */ + if (! (*insn_operand_predicate[icode][0]) (targ0, mode) + || ! (*insn_operand_predicate[icode][3]) (targ1, mode)) + abort (); + + pat = GEN_FCN (icode) (targ0, xop0, xop1, targ1); + if (pat) + { + emit_insn (pat); + return 1; + } + else + delete_insns_since (last); + } + + /* It can't be done in this mode. Can we do it in a wider mode? */ + + if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) + { + for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + { + if (binoptab->handlers[(int) wider_mode].insn_code + != CODE_FOR_nothing) + { + register rtx t0 = gen_reg_rtx (wider_mode); + register rtx t1 = gen_reg_rtx (wider_mode); + + if (expand_twoval_binop (binoptab, + convert_to_mode (wider_mode, op0, + unsignedp), + convert_to_mode (wider_mode, op1, + unsignedp), + t0, t1, unsignedp)) + { + convert_move (targ0, t0, unsignedp); + convert_move (targ1, t1, unsignedp); + return 1; + } + else + delete_insns_since (last); + } + } + } + + delete_insns_since (entry_last); + return 0; +} + +/* Generate code to perform an operation specified by UNOPTAB + on operand OP0, with result having machine-mode MODE. + + UNSIGNEDP is for the case where we have to widen the operands + to perform the operation. It says to use zero-extension. + + If TARGET is nonzero, the value + is generated there, if it is convenient to do so. + In all cases an rtx is returned for the locus of the value; + this may or may not be TARGET. */ + +rtx +expand_unop (mode, unoptab, op0, target, unsignedp) + enum machine_mode mode; + optab unoptab; + rtx op0; + rtx target; + int unsignedp; +{ + enum mode_class class; + enum machine_mode wider_mode; + register rtx temp; + rtx last = get_last_insn (); + rtx pat; + + class = GET_MODE_CLASS (mode); + + op0 = protect_from_queue (op0, 0); + + if (flag_force_mem) + { + op0 = force_not_mem (op0); + } + + if (target) + target = protect_from_queue (target, 1); + + if (unoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + { + int icode = (int) unoptab->handlers[(int) mode].insn_code; + enum machine_mode mode0 = insn_operand_mode[icode][1]; + rtx xop0 = op0; + + if (target) + temp = target; + else + temp = gen_reg_rtx (mode); + + if (GET_MODE (xop0) != VOIDmode + && GET_MODE (xop0) != mode0) + xop0 = convert_to_mode (mode0, xop0, unsignedp); + + /* Now, if insn doesn't accept our operand, put it into a pseudo. */ + + if (! (*insn_operand_predicate[icode][1]) (xop0, mode0)) + xop0 = copy_to_mode_reg (mode0, xop0); + + if (! (*insn_operand_predicate[icode][0]) (temp, mode)) + temp = gen_reg_rtx (mode); + + pat = GEN_FCN (icode) (temp, xop0); + if (pat) + { + if (GET_CODE (pat) == SEQUENCE + && ! add_equal_note (pat, temp, unoptab->code, xop0, NULL_RTX)) + { + delete_insns_since (last); + return expand_unop (mode, unoptab, op0, NULL_RTX, unsignedp); + } + + emit_insn (pat); + + return temp; + } + else + delete_insns_since (last); + } + + /* It can't be done in this mode. Can we open-code it in a wider mode? */ + + if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) + for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + { + if (unoptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing) + { + rtx xop0 = op0; + + /* For certain operations, we need not actually extend + the narrow operand, as long as we will truncate the + results to the same narrowness. But it is faster to + convert a SUBREG due to mode promotion. */ + + if ((unoptab == neg_optab || unoptab == one_cmpl_optab) + && GET_MODE_SIZE (wider_mode) <= UNITS_PER_WORD + && class == MODE_INT + && ! (GET_CODE (xop0) == SUBREG + && SUBREG_PROMOTED_VAR_P (xop0))) + xop0 = gen_rtx (SUBREG, wider_mode, force_reg (mode, xop0), 0); + else + xop0 = convert_to_mode (wider_mode, xop0, unsignedp); + + temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, + unsignedp); + + if (temp) + { + if (class != MODE_INT) + { + if (target == 0) + target = gen_reg_rtx (mode); + convert_move (target, temp, 0); + return target; + } + else + return gen_lowpart (mode, temp); + } + else + delete_insns_since (last); + } + } + + /* These can be done a word at a time. */ + if (unoptab == one_cmpl_optab + && class == MODE_INT + && GET_MODE_SIZE (mode) > UNITS_PER_WORD + && unoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) + { + int i; + rtx insns; + + if (target == 0 || target == op0) + target = gen_reg_rtx (mode); + + start_sequence (); + + /* Do the actual arithmetic. */ + for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) + { + rtx target_piece = operand_subword (target, i, 1, mode); + rtx x = expand_unop (word_mode, unoptab, + operand_subword_force (op0, i, mode), + target_piece, unsignedp); + if (target_piece != x) + emit_move_insn (target_piece, x); + } + + insns = get_insns (); + end_sequence (); + + emit_no_conflict_block (insns, target, op0, NULL_RTX, + gen_rtx (unoptab->code, mode, copy_rtx (op0))); + return target; + } + + /* Open-code the complex negation operation. */ + else if (unoptab == neg_optab + && (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT)) + { + rtx target_piece; + rtx x; + rtx seq; + + /* Find the correct mode for the real and imaginary parts */ + enum machine_mode submode + = mode_for_size (GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT, + class == MODE_COMPLEX_INT ? MODE_INT : MODE_FLOAT, + 0); + + if (submode == BLKmode) + abort (); + + if (target == 0) + target = gen_reg_rtx (mode); + + start_sequence (); + + target_piece = gen_imagpart (submode, target); + x = expand_unop (submode, unoptab, + gen_imagpart (submode, op0), + target_piece, unsignedp); + if (target_piece != x) + emit_move_insn (target_piece, x); + + target_piece = gen_realpart (submode, target); + x = expand_unop (submode, unoptab, + gen_realpart (submode, op0), + target_piece, unsignedp); + if (target_piece != x) + emit_move_insn (target_piece, x); + + seq = get_insns (); + end_sequence (); + + emit_no_conflict_block (seq, target, op0, 0, + gen_rtx (unoptab->code, mode, copy_rtx (op0))); + return target; + } + + /* Now try a library call in this mode. */ + if (unoptab->handlers[(int) mode].libfunc) + { + rtx insns; + rtx funexp = unoptab->handlers[(int) mode].libfunc; + + start_sequence (); + + /* Pass 1 for NO_QUEUE so we don't lose any increments + if the libcall is cse'd or moved. */ + emit_library_call (unoptab->handlers[(int) mode].libfunc, + 1, mode, 1, op0, mode); + insns = get_insns (); + end_sequence (); + + target = gen_reg_rtx (mode); + emit_libcall_block (insns, target, hard_libcall_value (mode), + gen_rtx (unoptab->code, mode, op0)); + + return target; + } + + /* It can't be done in this mode. Can we do it in a wider mode? */ + + if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) + { + for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + { + if ((unoptab->handlers[(int) wider_mode].insn_code + != CODE_FOR_nothing) + || unoptab->handlers[(int) wider_mode].libfunc) + { + rtx xop0 = op0; + + /* For certain operations, we need not actually extend + the narrow operand, as long as we will truncate the + results to the same narrowness. */ + + if ((unoptab == neg_optab || unoptab == one_cmpl_optab) + && GET_MODE_SIZE (wider_mode) <= UNITS_PER_WORD + && class == MODE_INT + && ! (GET_CODE (xop0) == SUBREG + && SUBREG_PROMOTED_VAR_P (xop0))) + xop0 = gen_rtx (SUBREG, wider_mode, force_reg (mode, xop0), 0); + else + xop0 = convert_to_mode (wider_mode, xop0, unsignedp); + + temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, + unsignedp); + + if (temp) + { + if (class != MODE_INT) + { + if (target == 0) + target = gen_reg_rtx (mode); + convert_move (target, temp, 0); + return target; + } + else + return gen_lowpart (mode, temp); + } + else + delete_insns_since (last); + } + } + } + + return 0; +} + +/* Emit code to compute the absolute value of OP0, with result to + TARGET if convenient. (TARGET may be 0.) The return value says + where the result actually is to be found. + + MODE is the mode of the operand; the mode of the result is + different but can be deduced from MODE. + + UNSIGNEDP is relevant for complex integer modes. */ + +rtx +expand_complex_abs (mode, op0, target, unsignedp) + enum machine_mode mode; + rtx op0; + rtx target; + int unsignedp; +{ + enum mode_class class = GET_MODE_CLASS (mode); + enum machine_mode wider_mode; + register rtx temp; + rtx entry_last = get_last_insn (); + rtx last; + rtx pat; + + /* Find the correct mode for the real and imaginary parts. */ + enum machine_mode submode + = mode_for_size (GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT, + class == MODE_COMPLEX_INT ? MODE_INT : MODE_FLOAT, + 0); + + if (submode == BLKmode) + abort (); + + op0 = protect_from_queue (op0, 0); + + if (flag_force_mem) + { + op0 = force_not_mem (op0); + } + + last = get_last_insn (); + + if (target) + target = protect_from_queue (target, 1); + + if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + { + int icode = (int) abs_optab->handlers[(int) mode].insn_code; + enum machine_mode mode0 = insn_operand_mode[icode][1]; + rtx xop0 = op0; + + if (target) + temp = target; + else + temp = gen_reg_rtx (submode); + + if (GET_MODE (xop0) != VOIDmode + && GET_MODE (xop0) != mode0) + xop0 = convert_to_mode (mode0, xop0, unsignedp); + + /* Now, if insn doesn't accept our operand, put it into a pseudo. */ + + if (! (*insn_operand_predicate[icode][1]) (xop0, mode0)) + xop0 = copy_to_mode_reg (mode0, xop0); + + if (! (*insn_operand_predicate[icode][0]) (temp, submode)) + temp = gen_reg_rtx (submode); + + pat = GEN_FCN (icode) (temp, xop0); + if (pat) + { + if (GET_CODE (pat) == SEQUENCE + && ! add_equal_note (pat, temp, abs_optab->code, xop0, NULL_RTX)) + { + delete_insns_since (last); + return expand_unop (mode, abs_optab, op0, NULL_RTX, unsignedp); + } + + emit_insn (pat); + + return temp; + } + else + delete_insns_since (last); + } + + /* It can't be done in this mode. Can we open-code it in a wider mode? */ + + for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + { + if (abs_optab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing) + { + rtx xop0 = op0; + + xop0 = convert_to_mode (wider_mode, xop0, unsignedp); + temp = expand_complex_abs (wider_mode, xop0, NULL_RTX, unsignedp); + + if (temp) + { + if (class != MODE_COMPLEX_INT) + { + if (target == 0) + target = gen_reg_rtx (submode); + convert_move (target, temp, 0); + return target; + } + else + return gen_lowpart (submode, temp); + } + else + delete_insns_since (last); + } + } + + /* Open-code the complex absolute-value operation + if we can open-code sqrt. Otherwise it's not worth while. */ + if (sqrt_optab->handlers[(int) submode].insn_code != CODE_FOR_nothing) + { + rtx real, imag, total; + + real = gen_realpart (submode, op0); + imag = gen_imagpart (submode, op0); + /* Square both parts. */ + real = expand_mult (mode, real, real, NULL_RTX, 0); + imag = expand_mult (mode, imag, imag, NULL_RTX, 0); + /* Sum the parts. */ + total = expand_binop (submode, add_optab, real, imag, 0, + 0, OPTAB_LIB_WIDEN); + /* Get sqrt in TARGET. Set TARGET to where the result is. */ + target = expand_unop (submode, sqrt_optab, total, target, 0); + if (target == 0) + delete_insns_since (last); + else + return target; + } + + /* Now try a library call in this mode. */ + if (abs_optab->handlers[(int) mode].libfunc) + { + rtx insns; + rtx funexp = abs_optab->handlers[(int) mode].libfunc; + + start_sequence (); + + /* Pass 1 for NO_QUEUE so we don't lose any increments + if the libcall is cse'd or moved. */ + emit_library_call (abs_optab->handlers[(int) mode].libfunc, + 1, mode, 1, op0, mode); + insns = get_insns (); + end_sequence (); + + target = gen_reg_rtx (submode); + emit_libcall_block (insns, target, hard_libcall_value (submode), + gen_rtx (abs_optab->code, mode, op0)); + + return target; + } + + /* It can't be done in this mode. Can we do it in a wider mode? */ + + for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + { + if ((abs_optab->handlers[(int) wider_mode].insn_code + != CODE_FOR_nothing) + || abs_optab->handlers[(int) wider_mode].libfunc) + { + rtx xop0 = op0; + + xop0 = convert_to_mode (wider_mode, xop0, unsignedp); + + temp = expand_complex_abs (wider_mode, xop0, NULL_RTX, unsignedp); + + if (temp) + { + if (class != MODE_COMPLEX_INT) + { + if (target == 0) + target = gen_reg_rtx (submode); + convert_move (target, temp, 0); + return target; + } + else + return gen_lowpart (submode, temp); + } + else + delete_insns_since (last); + } + } + + delete_insns_since (entry_last); + return 0; +} + +/* Generate an instruction whose insn-code is INSN_CODE, + with two operands: an output TARGET and an input OP0. + TARGET *must* be nonzero, and the output is always stored there. + CODE is an rtx code such that (CODE OP0) is an rtx that describes + the value that is stored into TARGET. */ + +void +emit_unop_insn (icode, target, op0, code) + int icode; + rtx target; + rtx op0; + enum rtx_code code; +{ + register rtx temp; + enum machine_mode mode0 = insn_operand_mode[icode][1]; + rtx pat; + + temp = target = protect_from_queue (target, 1); + + op0 = protect_from_queue (op0, 0); + + if (flag_force_mem) + op0 = force_not_mem (op0); + + /* Now, if insn does not accept our operands, put them into pseudos. */ + + if (! (*insn_operand_predicate[icode][1]) (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + + if (! (*insn_operand_predicate[icode][0]) (temp, GET_MODE (temp)) + || (flag_force_mem && GET_CODE (temp) == MEM)) + temp = gen_reg_rtx (GET_MODE (temp)); + + pat = GEN_FCN (icode) (temp, op0); + + if (GET_CODE (pat) == SEQUENCE && code != UNKNOWN) + add_equal_note (pat, temp, code, op0, NULL_RTX); + + emit_insn (pat); + + if (temp != target) + emit_move_insn (target, temp); +} + +/* Emit code to perform a series of operations on a multi-word quantity, one + word at a time. + + Such a block is preceded by a CLOBBER of the output, consists of multiple + insns, each setting one word of the output, and followed by a SET copying + the output to itself. + + Each of the insns setting words of the output receives a REG_NO_CONFLICT + note indicating that it doesn't conflict with the (also multi-word) + inputs. The entire block is surrounded by REG_LIBCALL and REG_RETVAL + notes. + + INSNS is a block of code generated to perform the operation, not including + the CLOBBER and final copy. All insns that compute intermediate values + are first emitted, followed by the block as described above. Only + INSNs are allowed in the block; no library calls or jumps may be + present. + + TARGET, OP0, and OP1 are the output and inputs of the operations, + respectively. OP1 may be zero for a unary operation. + + EQUIV, if non-zero, is an expression to be placed into a REG_EQUAL note + on the last insn. + + If TARGET is not a register, INSNS is simply emitted with no special + processing. + + The final insn emitted is returned. */ + +rtx +emit_no_conflict_block (insns, target, op0, op1, equiv) + rtx insns; + rtx target; + rtx op0, op1; + rtx equiv; +{ + rtx prev, next, first, last, insn; + + if (GET_CODE (target) != REG || reload_in_progress) + return emit_insns (insns); + + /* First emit all insns that do not store into words of the output and remove + these from the list. */ + for (insn = insns; insn; insn = next) + { + rtx set = 0; + int i; + + next = NEXT_INSN (insn); + + if (GET_CODE (insn) != INSN) + abort (); + + if (GET_CODE (PATTERN (insn)) == SET) + set = PATTERN (insn); + else if (GET_CODE (PATTERN (insn)) == PARALLEL) + { + for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) + if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET) + { + set = XVECEXP (PATTERN (insn), 0, i); + break; + } + } + + if (set == 0) + abort (); + + if (! reg_overlap_mentioned_p (target, SET_DEST (set))) + { + if (PREV_INSN (insn)) + NEXT_INSN (PREV_INSN (insn)) = next; + else + insns = next; + + if (next) + PREV_INSN (next) = PREV_INSN (insn); + + add_insn (insn); + } + } + + prev = get_last_insn (); + + /* Now write the CLOBBER of the output, followed by the setting of each + of the words, followed by the final copy. */ + if (target != op0 && target != op1) + emit_insn (gen_rtx (CLOBBER, VOIDmode, target)); + + for (insn = insns; insn; insn = next) + { + next = NEXT_INSN (insn); + add_insn (insn); + + if (op1 && GET_CODE (op1) == REG) + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_NO_CONFLICT, op1, + REG_NOTES (insn)); + + if (op0 && GET_CODE (op0) == REG) + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_NO_CONFLICT, op0, + REG_NOTES (insn)); + } + + if (mov_optab->handlers[(int) GET_MODE (target)].insn_code + != CODE_FOR_nothing) + { + last = emit_move_insn (target, target); + if (equiv) + REG_NOTES (last) + = gen_rtx (EXPR_LIST, REG_EQUAL, equiv, REG_NOTES (last)); + } + else + last = get_last_insn (); + + if (prev == 0) + first = get_insns (); + else + first = NEXT_INSN (prev); + + /* Encapsulate the block so it gets manipulated as a unit. */ + REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last, + REG_NOTES (first)); + REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last)); + + return last; +} + +/* Emit code to make a call to a constant function or a library call. + + INSNS is a list containing all insns emitted in the call. + These insns leave the result in RESULT. Our block is to copy RESULT + to TARGET, which is logically equivalent to EQUIV. + + We first emit any insns that set a pseudo on the assumption that these are + loading constants into registers; doing so allows them to be safely cse'ed + between blocks. Then we emit all the other insns in the block, followed by + an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL + note with an operand of EQUIV. + + Moving assignments to pseudos outside of the block is done to improve + the generated code, but is not required to generate correct code, + hence being unable to move an assignment is not grounds for not making + a libcall block. There are two reasons why it is safe to leave these + insns inside the block: First, we know that these pseudos cannot be + used in generated RTL outside the block since they are created for + temporary purposes within the block. Second, CSE will not record the + values of anything set inside a libcall block, so we know they must + be dead at the end of the block. + + Except for the first group of insns (the ones setting pseudos), the + block is delimited by REG_RETVAL and REG_LIBCALL notes. */ + +void +emit_libcall_block (insns, target, result, equiv) + rtx insns; + rtx target; + rtx result; + rtx equiv; +{ + rtx prev, next, first, last, insn; + + /* First emit all insns that set pseudos. Remove them from the list as + we go. Avoid insns that set pseudo which were referenced in previous + insns. These can be generated by move_by_pieces, for example, + to update an address. */ + + for (insn = insns; insn; insn = next) + { + rtx set = single_set (insn); + + next = NEXT_INSN (insn); + + if (set != 0 && GET_CODE (SET_DEST (set)) == REG + && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER + && (insn == insns + || (! reg_mentioned_p (SET_DEST (set), PATTERN (insns)) + && ! reg_used_between_p (SET_DEST (set), insns, insn)))) + { + if (PREV_INSN (insn)) + NEXT_INSN (PREV_INSN (insn)) = next; + else + insns = next; + + if (next) + PREV_INSN (next) = PREV_INSN (insn); + + add_insn (insn); + } + } + + prev = get_last_insn (); + + /* Write the remaining insns followed by the final copy. */ + + for (insn = insns; insn; insn = next) + { + next = NEXT_INSN (insn); + + add_insn (insn); + } + + last = emit_move_insn (target, result); + REG_NOTES (last) = gen_rtx (EXPR_LIST, + REG_EQUAL, copy_rtx (equiv), REG_NOTES (last)); + + if (prev == 0) + first = get_insns (); + else + first = NEXT_INSN (prev); + + /* Encapsulate the block so it gets manipulated as a unit. */ + REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last, + REG_NOTES (first)); + REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last)); +} + +/* Generate code to store zero in X. */ + +void +emit_clr_insn (x) + rtx x; +{ + emit_move_insn (x, const0_rtx); +} + +/* Generate code to store 1 in X + assuming it contains zero beforehand. */ + +void +emit_0_to_1_insn (x) + rtx x; +{ + emit_move_insn (x, const1_rtx); +} + +/* Generate code to compare X with Y + so that the condition codes are set. + + MODE is the mode of the inputs (in case they are const_int). + UNSIGNEDP nonzero says that X and Y are unsigned; + this matters if they need to be widened. + + If they have mode BLKmode, then SIZE specifies the size of both X and Y, + and ALIGN specifies the known shared alignment of X and Y. + + COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). + It is ignored for fixed-point and block comparisons; + it is used only for floating-point comparisons. */ + +void +emit_cmp_insn (x, y, comparison, size, mode, unsignedp, align) + rtx x, y; + enum rtx_code comparison; + rtx size; + enum machine_mode mode; + int unsignedp; + int align; +{ + enum mode_class class; + enum machine_mode wider_mode; + + class = GET_MODE_CLASS (mode); + + /* They could both be VOIDmode if both args are immediate constants, + but we should fold that at an earlier stage. + With no special code here, this will call abort, + reminding the programmer to implement such folding. */ + + if (mode != BLKmode && flag_force_mem) + { + x = force_not_mem (x); + y = force_not_mem (y); + } + + /* If we are inside an appropriately-short loop and one operand is an + expensive constant, force it into a register. */ + if (CONSTANT_P (x) && preserve_subexpressions_p () && rtx_cost (x, COMPARE) > 2) + x = force_reg (mode, x); + + if (CONSTANT_P (y) && preserve_subexpressions_p () && rtx_cost (y, COMPARE) > 2) + y = force_reg (mode, y); + + /* Don't let both operands fail to indicate the mode. */ + if (GET_MODE (x) == VOIDmode && GET_MODE (y) == VOIDmode) + x = force_reg (mode, x); + + /* Handle all BLKmode compares. */ + + if (mode == BLKmode) + { + emit_queue (); + x = protect_from_queue (x, 0); + y = protect_from_queue (y, 0); + + if (size == 0) + abort (); +#ifdef HAVE_cmpstrqi + if (HAVE_cmpstrqi + && GET_CODE (size) == CONST_INT + && INTVAL (size) < (1 << GET_MODE_BITSIZE (QImode))) + { + enum machine_mode result_mode + = insn_operand_mode[(int) CODE_FOR_cmpstrqi][0]; + rtx result = gen_reg_rtx (result_mode); + emit_insn (gen_cmpstrqi (result, x, y, size, GEN_INT (align))); + emit_cmp_insn (result, const0_rtx, comparison, NULL_RTX, + result_mode, 0, 0); + } + else +#endif +#ifdef HAVE_cmpstrhi + if (HAVE_cmpstrhi + && GET_CODE (size) == CONST_INT + && INTVAL (size) < (1 << GET_MODE_BITSIZE (HImode))) + { + enum machine_mode result_mode + = insn_operand_mode[(int) CODE_FOR_cmpstrhi][0]; + rtx result = gen_reg_rtx (result_mode); + emit_insn (gen_cmpstrhi (result, x, y, size, GEN_INT (align))); + emit_cmp_insn (result, const0_rtx, comparison, NULL_RTX, + result_mode, 0, 0); + } + else +#endif +#ifdef HAVE_cmpstrsi + if (HAVE_cmpstrsi) + { + enum machine_mode result_mode + = insn_operand_mode[(int) CODE_FOR_cmpstrsi][0]; + rtx result = gen_reg_rtx (result_mode); + size = protect_from_queue (size, 0); + emit_insn (gen_cmpstrsi (result, x, y, + convert_to_mode (SImode, size, 1), + GEN_INT (align))); + emit_cmp_insn (result, const0_rtx, comparison, NULL_RTX, + result_mode, 0, 0); + } + else +#endif + { +#ifdef TARGET_MEM_FUNCTIONS + emit_library_call (memcmp_libfunc, 0, + TYPE_MODE (integer_type_node), 3, + XEXP (x, 0), Pmode, XEXP (y, 0), Pmode, + size, Pmode); +#else + emit_library_call (bcmp_libfunc, 0, + TYPE_MODE (integer_type_node), 3, + XEXP (x, 0), Pmode, XEXP (y, 0), Pmode, + size, Pmode); +#endif + emit_cmp_insn (hard_libcall_value (TYPE_MODE (integer_type_node)), + const0_rtx, comparison, NULL_RTX, + TYPE_MODE (integer_type_node), 0, 0); + } + return; + } + + /* Handle some compares against zero. */ + + if (y == CONST0_RTX (mode) + && tst_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + { + int icode = (int) tst_optab->handlers[(int) mode].insn_code; + + emit_queue (); + x = protect_from_queue (x, 0); + y = protect_from_queue (y, 0); + + /* Now, if insn does accept these operands, put them into pseudos. */ + if (! (*insn_operand_predicate[icode][0]) + (x, insn_operand_mode[icode][0])) + x = copy_to_mode_reg (insn_operand_mode[icode][0], x); + + emit_insn (GEN_FCN (icode) (x)); + return; + } + + /* Handle compares for which there is a directly suitable insn. */ + + if (cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) + { + int icode = (int) cmp_optab->handlers[(int) mode].insn_code; + + emit_queue (); + x = protect_from_queue (x, 0); + y = protect_from_queue (y, 0); + + /* Now, if insn doesn't accept these operands, put them into pseudos. */ + if (! (*insn_operand_predicate[icode][0]) + (x, insn_operand_mode[icode][0])) + x = copy_to_mode_reg (insn_operand_mode[icode][0], x); + + if (! (*insn_operand_predicate[icode][1]) + (y, insn_operand_mode[icode][1])) + y = copy_to_mode_reg (insn_operand_mode[icode][1], y); + + emit_insn (GEN_FCN (icode) (x, y)); + return; + } + + /* Try widening if we can find a direct insn that way. */ + + if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) + { + for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + { + if (cmp_optab->handlers[(int) wider_mode].insn_code + != CODE_FOR_nothing) + { + x = protect_from_queue (x, 0); + y = protect_from_queue (y, 0); + x = convert_to_mode (wider_mode, x, unsignedp); + y = convert_to_mode (wider_mode, y, unsignedp); + emit_cmp_insn (x, y, comparison, NULL_RTX, + wider_mode, unsignedp, align); + return; + } + } + } + + /* Handle a lib call just for the mode we are using. */ + + if (cmp_optab->handlers[(int) mode].libfunc + && class != MODE_FLOAT) + { + rtx libfunc = cmp_optab->handlers[(int) mode].libfunc; + /* If we want unsigned, and this mode has a distinct unsigned + comparison routine, use that. */ + if (unsignedp && ucmp_optab->handlers[(int) mode].libfunc) + libfunc = ucmp_optab->handlers[(int) mode].libfunc; + + emit_library_call (libfunc, 1, + word_mode, 2, x, mode, y, mode); + + /* Integer comparison returns a result that must be compared against 1, + so that even if we do an unsigned compare afterward, + there is still a value that can represent the result "less than". */ + + emit_cmp_insn (hard_libcall_value (word_mode), const1_rtx, + comparison, NULL_RTX, word_mode, unsignedp, 0); + return; + } + + if (class == MODE_FLOAT) + emit_float_lib_cmp (x, y, comparison); + + else + abort (); +} + +/* Nonzero if a compare of mode MODE can be done straightforwardly + (without splitting it into pieces). */ + +int +can_compare_p (mode) + enum machine_mode mode; +{ + do + { + if (cmp_optab->handlers[(int)mode].insn_code != CODE_FOR_nothing) + return 1; + mode = GET_MODE_WIDER_MODE (mode); + } while (mode != VOIDmode); + + return 0; +} + +/* Emit a library call comparison between floating point X and Y. + COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */ + +static void +emit_float_lib_cmp (x, y, comparison) + rtx x, y; + enum rtx_code comparison; +{ + enum machine_mode mode = GET_MODE (x); + rtx libfunc; + + if (mode == SFmode) + switch (comparison) + { + case EQ: + libfunc = eqsf2_libfunc; + break; + + case NE: + libfunc = nesf2_libfunc; + break; + + case GT: + libfunc = gtsf2_libfunc; + break; + + case GE: + libfunc = gesf2_libfunc; + break; + + case LT: + libfunc = ltsf2_libfunc; + break; + + case LE: + libfunc = lesf2_libfunc; + break; + } + else if (mode == DFmode) + switch (comparison) + { + case EQ: + libfunc = eqdf2_libfunc; + break; + + case NE: + libfunc = nedf2_libfunc; + break; + + case GT: + libfunc = gtdf2_libfunc; + break; + + case GE: + libfunc = gedf2_libfunc; + break; + + case LT: + libfunc = ltdf2_libfunc; + break; + + case LE: + libfunc = ledf2_libfunc; + break; + } + else if (mode == XFmode) + switch (comparison) + { + case EQ: + libfunc = eqxf2_libfunc; + break; + + case NE: + libfunc = nexf2_libfunc; + break; + + case GT: + libfunc = gtxf2_libfunc; + break; + + case GE: + libfunc = gexf2_libfunc; + break; + + case LT: + libfunc = ltxf2_libfunc; + break; + + case LE: + libfunc = lexf2_libfunc; + break; + } + else if (mode == TFmode) + switch (comparison) + { + case EQ: + libfunc = eqtf2_libfunc; + break; + + case NE: + libfunc = netf2_libfunc; + break; + + case GT: + libfunc = gttf2_libfunc; + break; + + case GE: + libfunc = getf2_libfunc; + break; + + case LT: + libfunc = lttf2_libfunc; + break; + + case LE: + libfunc = letf2_libfunc; + break; + } + else + { + enum machine_mode wider_mode; + + for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + { + if ((cmp_optab->handlers[(int) wider_mode].insn_code + != CODE_FOR_nothing) + || (cmp_optab->handlers[(int) wider_mode].libfunc != 0)) + { + x = protect_from_queue (x, 0); + y = protect_from_queue (y, 0); + x = convert_to_mode (wider_mode, x, 0); + y = convert_to_mode (wider_mode, y, 0); + emit_float_lib_cmp (x, y, comparison); + return; + } + } + abort (); + } + + emit_library_call (libfunc, 1, + word_mode, 2, x, mode, y, mode); + + emit_cmp_insn (hard_libcall_value (word_mode), const0_rtx, comparison, + NULL_RTX, word_mode, 0, 0); +} + +/* Generate code to indirectly jump to a location given in the rtx LOC. */ + +void +emit_indirect_jump (loc) + rtx loc; +{ + if (! ((*insn_operand_predicate[(int)CODE_FOR_indirect_jump][0]) + (loc, Pmode))) + loc = copy_to_mode_reg (Pmode, loc); + + emit_jump_insn (gen_indirect_jump (loc)); + emit_barrier (); +} + +/* These three functions generate an insn body and return it + rather than emitting the insn. + + They do not protect from queued increments, + because they may be used 1) in protect_from_queue itself + and 2) in other passes where there is no queue. */ + +/* Generate and return an insn body to add Y to X. */ + +rtx +gen_add2_insn (x, y) + rtx x, y; +{ + int icode = (int) add_optab->handlers[(int) GET_MODE (x)].insn_code; + + if (! (*insn_operand_predicate[icode][0]) (x, insn_operand_mode[icode][0]) + || ! (*insn_operand_predicate[icode][1]) (x, insn_operand_mode[icode][1]) + || ! (*insn_operand_predicate[icode][2]) (y, insn_operand_mode[icode][2])) + abort (); + + return (GEN_FCN (icode) (x, x, y)); +} + +int +have_add2_insn (mode) + enum machine_mode mode; +{ + return add_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing; +} + +/* Generate and return an insn body to subtract Y from X. */ + +rtx +gen_sub2_insn (x, y) + rtx x, y; +{ + int icode = (int) sub_optab->handlers[(int) GET_MODE (x)].insn_code; + + if (! (*insn_operand_predicate[icode][0]) (x, insn_operand_mode[icode][0]) + || ! (*insn_operand_predicate[icode][1]) (x, insn_operand_mode[icode][1]) + || ! (*insn_operand_predicate[icode][2]) (y, insn_operand_mode[icode][2])) + abort (); + + return (GEN_FCN (icode) (x, x, y)); +} + +int +have_sub2_insn (mode) + enum machine_mode mode; +{ + return sub_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing; +} + +/* Generate the body of an instruction to copy Y into X. + It may be a SEQUENCE, if one insn isn't enough. */ + +rtx +gen_move_insn (x, y) + rtx x, y; +{ + register enum machine_mode mode = GET_MODE (x); + enum insn_code insn_code; + rtx seq; + + if (mode == VOIDmode) + mode = GET_MODE (y); + + insn_code = mov_optab->handlers[(int) mode].insn_code; + + /* Handle MODE_CC modes: If we don't have a special move insn for this mode, + find a mode to do it in. If we have a movcc, use it. Otherwise, + find the MODE_INT mode of the same width. */ + + if (GET_MODE_CLASS (mode) == MODE_CC && insn_code == CODE_FOR_nothing) + { + enum machine_mode tmode = VOIDmode; + rtx x1 = x, y1 = y; + + if (mode != CCmode + && mov_optab->handlers[(int) CCmode].insn_code != CODE_FOR_nothing) + tmode = CCmode; + else + for (tmode = QImode; tmode != VOIDmode; + tmode = GET_MODE_WIDER_MODE (tmode)) + if (GET_MODE_SIZE (tmode) == GET_MODE_SIZE (mode)) + break; + + if (tmode == VOIDmode) + abort (); + + /* Get X and Y in TMODE. We can't use gen_lowpart here because it + may call change_address which is not appropriate if we were + called when a reload was in progress. We don't have to worry + about changing the address since the size in bytes is supposed to + be the same. Copy the MEM to change the mode and move any + substitutions from the old MEM to the new one. */ + + if (reload_in_progress) + { + x = gen_lowpart_common (tmode, x1); + if (x == 0 && GET_CODE (x1) == MEM) + { + x = gen_rtx (MEM, tmode, XEXP (x1, 0)); + RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (x1); + MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (x1); + MEM_VOLATILE_P (x) = MEM_VOLATILE_P (x1); + copy_replacements (x1, x); + } + + y = gen_lowpart_common (tmode, y1); + if (y == 0 && GET_CODE (y1) == MEM) + { + y = gen_rtx (MEM, tmode, XEXP (y1, 0)); + RTX_UNCHANGING_P (y) = RTX_UNCHANGING_P (y1); + MEM_IN_STRUCT_P (y) = MEM_IN_STRUCT_P (y1); + MEM_VOLATILE_P (y) = MEM_VOLATILE_P (y1); + copy_replacements (y1, y); + } + } + else + { + x = gen_lowpart (tmode, x); + y = gen_lowpart (tmode, y); + } + + insn_code = mov_optab->handlers[(int) tmode].insn_code; + return (GEN_FCN (insn_code) (x, y)); + } + + start_sequence (); + emit_move_insn_1 (x, y); + seq = gen_sequence (); + end_sequence (); + return seq; +} + +/* Return the insn code used to extend FROM_MODE to TO_MODE. + UNSIGNEDP specifies zero-extension instead of sign-extension. If + no such operation exists, CODE_FOR_nothing will be returned. */ + +enum insn_code +can_extend_p (to_mode, from_mode, unsignedp) + enum machine_mode to_mode, from_mode; + int unsignedp; +{ + return extendtab[(int) to_mode][(int) from_mode][unsignedp]; +} + +/* Generate the body of an insn to extend Y (with mode MFROM) + into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ + +rtx +gen_extend_insn (x, y, mto, mfrom, unsignedp) + rtx x, y; + enum machine_mode mto, mfrom; + int unsignedp; +{ + return (GEN_FCN (extendtab[(int) mto][(int) mfrom][unsignedp]) (x, y)); +} + +/* can_fix_p and can_float_p say whether the target machine + can directly convert a given fixed point type to + a given floating point type, or vice versa. + The returned value is the CODE_FOR_... value to use, + or CODE_FOR_nothing if these modes cannot be directly converted. + + *TRUNCP_PTR is set to 1 if it is necessary to output + an explicit FTRUNC insn before the fix insn; otherwise 0. */ + +static enum insn_code +can_fix_p (fixmode, fltmode, unsignedp, truncp_ptr) + enum machine_mode fltmode, fixmode; + int unsignedp; + int *truncp_ptr; +{ + *truncp_ptr = 0; + if (fixtrunctab[(int) fltmode][(int) fixmode][unsignedp] != CODE_FOR_nothing) + return fixtrunctab[(int) fltmode][(int) fixmode][unsignedp]; + + if (ftrunc_optab->handlers[(int) fltmode].insn_code != CODE_FOR_nothing) + { + *truncp_ptr = 1; + return fixtab[(int) fltmode][(int) fixmode][unsignedp]; + } + return CODE_FOR_nothing; +} + +static enum insn_code +can_float_p (fltmode, fixmode, unsignedp) + enum machine_mode fixmode, fltmode; + int unsignedp; +{ + return floattab[(int) fltmode][(int) fixmode][unsignedp]; +} + +/* Generate code to convert FROM to floating point + and store in TO. FROM must be fixed point and not VOIDmode. + UNSIGNEDP nonzero means regard FROM as unsigned. + Normally this is done by correcting the final value + if it is negative. */ + +void +expand_float (to, from, unsignedp) + rtx to, from; + int unsignedp; +{ + enum insn_code icode; + register rtx target = to; + enum machine_mode fmode, imode; + + /* Crash now, because we won't be able to decide which mode to use. */ + if (GET_MODE (from) == VOIDmode) + abort (); + + /* Look for an insn to do the conversion. Do it in the specified + modes if possible; otherwise convert either input, output or both to + wider mode. If the integer mode is wider than the mode of FROM, + we can do the conversion signed even if the input is unsigned. */ + + for (imode = GET_MODE (from); imode != VOIDmode; + imode = GET_MODE_WIDER_MODE (imode)) + for (fmode = GET_MODE (to); fmode != VOIDmode; + fmode = GET_MODE_WIDER_MODE (fmode)) + { + int doing_unsigned = unsignedp; + + icode = can_float_p (fmode, imode, unsignedp); + if (icode == CODE_FOR_nothing && imode != GET_MODE (from) && unsignedp) + icode = can_float_p (fmode, imode, 0), doing_unsigned = 0; + + if (icode != CODE_FOR_nothing) + { + to = protect_from_queue (to, 1); + from = protect_from_queue (from, 0); + + if (imode != GET_MODE (from)) + from = convert_to_mode (imode, from, unsignedp); + + if (fmode != GET_MODE (to)) + target = gen_reg_rtx (fmode); + + emit_unop_insn (icode, target, from, + doing_unsigned ? UNSIGNED_FLOAT : FLOAT); + + if (target != to) + convert_move (to, target, 0); + return; + } + } + +#if !defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + + /* Unsigned integer, and no way to convert directly. + Convert as signed, then conditionally adjust the result. */ + if (unsignedp) + { + rtx label = gen_label_rtx (); + rtx temp; + REAL_VALUE_TYPE offset; + + emit_queue (); + + to = protect_from_queue (to, 1); + from = protect_from_queue (from, 0); + + if (flag_force_mem) + from = force_not_mem (from); + + /* Look for a usable floating mode FMODE wider than the source and at + least as wide as the target. Using FMODE will avoid rounding woes + with unsigned values greater than the signed maximum value. */ + for (fmode = GET_MODE (to); fmode != VOIDmode; + fmode = GET_MODE_WIDER_MODE (fmode)) + if (GET_MODE_BITSIZE (GET_MODE (from)) < GET_MODE_BITSIZE (fmode) + && can_float_p (fmode, GET_MODE (from), 0) != CODE_FOR_nothing) + break; + if (fmode == VOIDmode) + { + /* There is no such mode. Pretend the target is wide enough. + This may cause rounding problems, unfortunately. */ + fmode = GET_MODE (to); + } + + /* If we are about to do some arithmetic to correct for an + unsigned operand, do it in a pseudo-register. */ + + if (GET_MODE (to) != fmode + || GET_CODE (to) != REG || REGNO (to) <= LAST_VIRTUAL_REGISTER) + target = gen_reg_rtx (fmode); + + /* Convert as signed integer to floating. */ + expand_float (target, from, 0); + + /* If FROM is negative (and therefore TO is negative), + correct its value by 2**bitwidth. */ + + do_pending_stack_adjust (); + emit_cmp_insn (from, const0_rtx, GE, NULL_RTX, GET_MODE (from), 0, 0); + emit_jump_insn (gen_bge (label)); + /* On SCO 3.2.1, ldexp rejects values outside [0.5, 1). + Rather than setting up a dconst_dot_5, let's hope SCO + fixes the bug. */ + offset = REAL_VALUE_LDEXP (dconst1, GET_MODE_BITSIZE (GET_MODE (from))); + temp = expand_binop (fmode, add_optab, target, + immed_real_const_1 (offset, fmode), + target, 0, OPTAB_LIB_WIDEN); + if (temp != target) + emit_move_insn (target, temp); + do_pending_stack_adjust (); + emit_label (label); + } + else +#endif + + /* No hardware instruction available; call a library rotine to convert from + SImode, DImode, or TImode into SFmode, DFmode, XFmode, or TFmode. */ + { + rtx libfcn; + rtx insns; + + to = protect_from_queue (to, 1); + from = protect_from_queue (from, 0); + + if (GET_MODE_SIZE (GET_MODE (from)) < GET_MODE_SIZE (SImode)) + from = convert_to_mode (SImode, from, unsignedp); + + if (flag_force_mem) + from = force_not_mem (from); + + if (GET_MODE (to) == SFmode) + { + if (GET_MODE (from) == SImode) + libfcn = floatsisf_libfunc; + else if (GET_MODE (from) == DImode) + libfcn = floatdisf_libfunc; + else if (GET_MODE (from) == TImode) + libfcn = floattisf_libfunc; + else + abort (); + } + else if (GET_MODE (to) == DFmode) + { + if (GET_MODE (from) == SImode) + libfcn = floatsidf_libfunc; + else if (GET_MODE (from) == DImode) + libfcn = floatdidf_libfunc; + else if (GET_MODE (from) == TImode) + libfcn = floattidf_libfunc; + else + abort (); + } + else if (GET_MODE (to) == XFmode) + { + if (GET_MODE (from) == SImode) + libfcn = floatsixf_libfunc; + else if (GET_MODE (from) == DImode) + libfcn = floatdixf_libfunc; + else if (GET_MODE (from) == TImode) + libfcn = floattixf_libfunc; + else + abort (); + } + else if (GET_MODE (to) == TFmode) + { + if (GET_MODE (from) == SImode) + libfcn = floatsitf_libfunc; + else if (GET_MODE (from) == DImode) + libfcn = floatditf_libfunc; + else if (GET_MODE (from) == TImode) + libfcn = floattitf_libfunc; + else + abort (); + } + else + abort (); + + start_sequence (); + + emit_library_call (libfcn, 1, GET_MODE (to), 1, from, GET_MODE (from)); + insns = get_insns (); + end_sequence (); + + emit_libcall_block (insns, target, hard_libcall_value (GET_MODE (to)), + gen_rtx (FLOAT, GET_MODE (to), from)); + } + + /* Copy result to requested destination + if we have been computing in a temp location. */ + + if (target != to) + { + if (GET_MODE (target) == GET_MODE (to)) + emit_move_insn (to, target); + else + convert_move (to, target, 0); + } +} + +/* expand_fix: generate code to convert FROM to fixed point + and store in TO. FROM must be floating point. */ + +static rtx +ftruncify (x) + rtx x; +{ + rtx temp = gen_reg_rtx (GET_MODE (x)); + return expand_unop (GET_MODE (x), ftrunc_optab, x, temp, 0); +} + +void +expand_fix (to, from, unsignedp) + register rtx to, from; + int unsignedp; +{ + enum insn_code icode; + register rtx target = to; + enum machine_mode fmode, imode; + int must_trunc = 0; + rtx libfcn = 0; + + /* We first try to find a pair of modes, one real and one integer, at + least as wide as FROM and TO, respectively, in which we can open-code + this conversion. If the integer mode is wider than the mode of TO, + we can do the conversion either signed or unsigned. */ + + for (imode = GET_MODE (to); imode != VOIDmode; + imode = GET_MODE_WIDER_MODE (imode)) + for (fmode = GET_MODE (from); fmode != VOIDmode; + fmode = GET_MODE_WIDER_MODE (fmode)) + { + int doing_unsigned = unsignedp; + + icode = can_fix_p (imode, fmode, unsignedp, &must_trunc); + if (icode == CODE_FOR_nothing && imode != GET_MODE (to) && unsignedp) + icode = can_fix_p (imode, fmode, 0, &must_trunc), doing_unsigned = 0; + + if (icode != CODE_FOR_nothing) + { + to = protect_from_queue (to, 1); + from = protect_from_queue (from, 0); + + if (fmode != GET_MODE (from)) + from = convert_to_mode (fmode, from, 0); + + if (must_trunc) + from = ftruncify (from); + + if (imode != GET_MODE (to)) + target = gen_reg_rtx (imode); + + emit_unop_insn (icode, target, from, + doing_unsigned ? UNSIGNED_FIX : FIX); + if (target != to) + convert_move (to, target, unsignedp); + return; + } + } + +#if !defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + /* For an unsigned conversion, there is one more way to do it. + If we have a signed conversion, we generate code that compares + the real value to the largest representable positive number. If if + is smaller, the conversion is done normally. Otherwise, subtract + one plus the highest signed number, convert, and add it back. + + We only need to check all real modes, since we know we didn't find + anything with a wider integer mode. */ + + if (unsignedp && GET_MODE_BITSIZE (GET_MODE (to)) <= HOST_BITS_PER_WIDE_INT) + for (fmode = GET_MODE (from); fmode != VOIDmode; + fmode = GET_MODE_WIDER_MODE (fmode)) + /* Make sure we won't lose significant bits doing this. */ + if (GET_MODE_BITSIZE (fmode) > GET_MODE_BITSIZE (GET_MODE (to)) + && CODE_FOR_nothing != can_fix_p (GET_MODE (to), fmode, 0, + &must_trunc)) + { + int bitsize; + REAL_VALUE_TYPE offset; + rtx limit, lab1, lab2, insn; + + bitsize = GET_MODE_BITSIZE (GET_MODE (to)); + offset = REAL_VALUE_LDEXP (dconst1, bitsize - 1); + limit = immed_real_const_1 (offset, fmode); + lab1 = gen_label_rtx (); + lab2 = gen_label_rtx (); + + emit_queue (); + to = protect_from_queue (to, 1); + from = protect_from_queue (from, 0); + + if (flag_force_mem) + from = force_not_mem (from); + + if (fmode != GET_MODE (from)) + from = convert_to_mode (fmode, from, 0); + + /* See if we need to do the subtraction. */ + do_pending_stack_adjust (); + emit_cmp_insn (from, limit, GE, NULL_RTX, GET_MODE (from), 0, 0); + emit_jump_insn (gen_bge (lab1)); + + /* If not, do the signed "fix" and branch around fixup code. */ + expand_fix (to, from, 0); + emit_jump_insn (gen_jump (lab2)); + emit_barrier (); + + /* Otherwise, subtract 2**(N-1), convert to signed number, + then add 2**(N-1). Do the addition using XOR since this + will often generate better code. */ + emit_label (lab1); + target = expand_binop (GET_MODE (from), sub_optab, from, limit, + NULL_RTX, 0, OPTAB_LIB_WIDEN); + expand_fix (to, target, 0); + target = expand_binop (GET_MODE (to), xor_optab, to, + GEN_INT ((HOST_WIDE_INT) 1 << (bitsize - 1)), + to, 1, OPTAB_LIB_WIDEN); + + if (target != to) + emit_move_insn (to, target); + + emit_label (lab2); + + /* Make a place for a REG_NOTE and add it. */ + insn = emit_move_insn (to, to); + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, + gen_rtx (UNSIGNED_FIX, GET_MODE (to), + copy_rtx (from)), + REG_NOTES (insn)); + + return; + } +#endif + + /* We can't do it with an insn, so use a library call. But first ensure + that the mode of TO is at least as wide as SImode, since those are the + only library calls we know about. */ + + if (GET_MODE_SIZE (GET_MODE (to)) < GET_MODE_SIZE (SImode)) + { + target = gen_reg_rtx (SImode); + + expand_fix (target, from, unsignedp); + } + else if (GET_MODE (from) == SFmode) + { + if (GET_MODE (to) == SImode) + libfcn = unsignedp ? fixunssfsi_libfunc : fixsfsi_libfunc; + else if (GET_MODE (to) == DImode) + libfcn = unsignedp ? fixunssfdi_libfunc : fixsfdi_libfunc; + else if (GET_MODE (to) == TImode) + libfcn = unsignedp ? fixunssfti_libfunc : fixsfti_libfunc; + else + abort (); + } + else if (GET_MODE (from) == DFmode) + { + if (GET_MODE (to) == SImode) + libfcn = unsignedp ? fixunsdfsi_libfunc : fixdfsi_libfunc; + else if (GET_MODE (to) == DImode) + libfcn = unsignedp ? fixunsdfdi_libfunc : fixdfdi_libfunc; + else if (GET_MODE (to) == TImode) + libfcn = unsignedp ? fixunsdfti_libfunc : fixdfti_libfunc; + else + abort (); + } + else if (GET_MODE (from) == XFmode) + { + if (GET_MODE (to) == SImode) + libfcn = unsignedp ? fixunsxfsi_libfunc : fixxfsi_libfunc; + else if (GET_MODE (to) == DImode) + libfcn = unsignedp ? fixunsxfdi_libfunc : fixxfdi_libfunc; + else if (GET_MODE (to) == TImode) + libfcn = unsignedp ? fixunsxfti_libfunc : fixxfti_libfunc; + else + abort (); + } + else if (GET_MODE (from) == TFmode) + { + if (GET_MODE (to) == SImode) + libfcn = unsignedp ? fixunstfsi_libfunc : fixtfsi_libfunc; + else if (GET_MODE (to) == DImode) + libfcn = unsignedp ? fixunstfdi_libfunc : fixtfdi_libfunc; + else if (GET_MODE (to) == TImode) + libfcn = unsignedp ? fixunstfti_libfunc : fixtfti_libfunc; + else + abort (); + } + else + abort (); + + if (libfcn) + { + rtx insns; + + to = protect_from_queue (to, 1); + from = protect_from_queue (from, 0); + + if (flag_force_mem) + from = force_not_mem (from); + + start_sequence (); + + emit_library_call (libfcn, 1, GET_MODE (to), 1, from, GET_MODE (from)); + insns = get_insns (); + end_sequence (); + + emit_libcall_block (insns, target, hard_libcall_value (GET_MODE (to)), + gen_rtx (unsignedp ? FIX : UNSIGNED_FIX, + GET_MODE (to), from)); + } + + if (GET_MODE (to) == GET_MODE (target)) + emit_move_insn (to, target); + else + convert_move (to, target, 0); +} + +static optab +init_optab (code) + enum rtx_code code; +{ + int i; + optab op = (optab) xmalloc (sizeof (struct optab)); + op->code = code; + for (i = 0; i < NUM_MACHINE_MODES; i++) + { + op->handlers[i].insn_code = CODE_FOR_nothing; + op->handlers[i].libfunc = 0; + } + return op; +} + +/* Initialize the libfunc fields of an entire group of entries in some + optab. Each entry is set equal to a string consisting of a leading + pair of underscores followed by a generic operation name followed by + a mode name (downshifted to lower case) followed by a single character + representing the number of operands for the given operation (which is + usually one of the characters '2', '3', or '4'). + + OPTABLE is the table in which libfunc fields are to be initialized. + FIRST_MODE is the first machine mode index in the given optab to + initialize. + LAST_MODE is the last machine mode index in the given optab to + initialize. + OPNAME is the generic (string) name of the operation. + SUFFIX is the character which specifies the number of operands for + the given generic operation. +*/ + +static void +init_libfuncs (optable, first_mode, last_mode, opname, suffix) + register optab optable; + register int first_mode; + register int last_mode; + register char *opname; + register char suffix; +{ + register int mode; + register unsigned opname_len = strlen (opname); + + for (mode = first_mode; (int) mode <= (int) last_mode; + mode = (enum machine_mode) ((int) mode + 1)) + { + register char *mname = mode_name[(int) mode]; + register unsigned mname_len = strlen (mname); + register char *libfunc_name + = (char *) xmalloc (2 + opname_len + mname_len + 1 + 1); + register char *p; + register char *q; + + p = libfunc_name; + *p++ = '_'; + *p++ = '_'; + for (q = opname; *q; ) + *p++ = *q++; + for (q = mname; *q; q++) + *p++ = tolower (*q); + *p++ = suffix; + *p++ = '\0'; + optable->handlers[(int) mode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, libfunc_name); + } +} + +/* Initialize the libfunc fields of an entire group of entries in some + optab which correspond to all integer mode operations. The parameters + have the same meaning as similarly named ones for the `init_libfuncs' + routine. (See above). */ + +static void +init_integral_libfuncs (optable, opname, suffix) + register optab optable; + register char *opname; + register char suffix; +{ + init_libfuncs (optable, SImode, TImode, opname, suffix); +} + +/* Initialize the libfunc fields of an entire group of entries in some + optab which correspond to all real mode operations. The parameters + have the same meaning as similarly named ones for the `init_libfuncs' + routine. (See above). */ + +static void +init_floating_libfuncs (optable, opname, suffix) + register optab optable; + register char *opname; + register char suffix; +{ + init_libfuncs (optable, SFmode, TFmode, opname, suffix); +} + +/* Initialize the libfunc fields of an entire group of entries in some + optab which correspond to all complex floating modes. The parameters + have the same meaning as similarly named ones for the `init_libfuncs' + routine. (See above). */ + +static void +init_complex_libfuncs (optable, opname, suffix) + register optab optable; + register char *opname; + register char suffix; +{ + init_libfuncs (optable, SCmode, TCmode, opname, suffix); +} + +/* Call this once to initialize the contents of the optabs + appropriately for the current target machine. */ + +void +init_optabs () +{ + int i, j; + enum insn_code *p; + + /* Start by initializing all tables to contain CODE_FOR_nothing. */ + + for (p = fixtab[0][0]; + p < fixtab[0][0] + sizeof fixtab / sizeof (fixtab[0][0][0]); + p++) + *p = CODE_FOR_nothing; + + for (p = fixtrunctab[0][0]; + p < fixtrunctab[0][0] + sizeof fixtrunctab / sizeof (fixtrunctab[0][0][0]); + p++) + *p = CODE_FOR_nothing; + + for (p = floattab[0][0]; + p < floattab[0][0] + sizeof floattab / sizeof (floattab[0][0][0]); + p++) + *p = CODE_FOR_nothing; + + for (p = extendtab[0][0]; + p < extendtab[0][0] + sizeof extendtab / sizeof extendtab[0][0][0]; + p++) + *p = CODE_FOR_nothing; + + for (i = 0; i < NUM_RTX_CODE; i++) + setcc_gen_code[i] = CODE_FOR_nothing; + + add_optab = init_optab (PLUS); + sub_optab = init_optab (MINUS); + smul_optab = init_optab (MULT); + smul_widen_optab = init_optab (UNKNOWN); + umul_widen_optab = init_optab (UNKNOWN); + sdiv_optab = init_optab (DIV); + sdivmod_optab = init_optab (UNKNOWN); + udiv_optab = init_optab (UDIV); + udivmod_optab = init_optab (UNKNOWN); + smod_optab = init_optab (MOD); + umod_optab = init_optab (UMOD); + flodiv_optab = init_optab (DIV); + ftrunc_optab = init_optab (UNKNOWN); + and_optab = init_optab (AND); + ior_optab = init_optab (IOR); + xor_optab = init_optab (XOR); + ashl_optab = init_optab (ASHIFT); + ashr_optab = init_optab (ASHIFTRT); + lshl_optab = init_optab (LSHIFT); + lshr_optab = init_optab (LSHIFTRT); + rotl_optab = init_optab (ROTATE); + rotr_optab = init_optab (ROTATERT); + smin_optab = init_optab (SMIN); + smax_optab = init_optab (SMAX); + umin_optab = init_optab (UMIN); + umax_optab = init_optab (UMAX); + mov_optab = init_optab (UNKNOWN); + movstrict_optab = init_optab (UNKNOWN); + cmp_optab = init_optab (UNKNOWN); + ucmp_optab = init_optab (UNKNOWN); + tst_optab = init_optab (UNKNOWN); + neg_optab = init_optab (NEG); + abs_optab = init_optab (ABS); + one_cmpl_optab = init_optab (NOT); + ffs_optab = init_optab (FFS); + sqrt_optab = init_optab (SQRT); + sin_optab = init_optab (UNKNOWN); + cos_optab = init_optab (UNKNOWN); + strlen_optab = init_optab (UNKNOWN); + + for (i = 0; i < NUM_MACHINE_MODES; i++) + { + movstr_optab[i] = CODE_FOR_nothing; + +#ifdef HAVE_SECONDARY_RELOADS + reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing; +#endif + } + + /* Fill in the optabs with the insns we support. */ + init_all_optabs (); + +#ifdef FIXUNS_TRUNC_LIKE_FIX_TRUNC + /* This flag says the same insns that convert to a signed fixnum + also convert validly to an unsigned one. */ + for (i = 0; i < NUM_MACHINE_MODES; i++) + for (j = 0; j < NUM_MACHINE_MODES; j++) + fixtrunctab[i][j][1] = fixtrunctab[i][j][0]; +#endif + +#ifdef EXTRA_CC_MODES + init_mov_optab (); +#endif + + /* Initialize the optabs with the names of the library functions. */ + init_integral_libfuncs (add_optab, "add", '3'); + init_floating_libfuncs (add_optab, "add", '3'); + init_integral_libfuncs (sub_optab, "sub", '3'); + init_floating_libfuncs (sub_optab, "sub", '3'); + init_integral_libfuncs (smul_optab, "mul", '3'); + init_floating_libfuncs (smul_optab, "mul", '3'); + init_integral_libfuncs (sdiv_optab, "div", '3'); + init_integral_libfuncs (udiv_optab, "udiv", '3'); + init_integral_libfuncs (sdivmod_optab, "divmod", '4'); + init_integral_libfuncs (udivmod_optab, "udivmod", '4'); + init_integral_libfuncs (smod_optab, "mod", '3'); + init_integral_libfuncs (umod_optab, "umod", '3'); + init_floating_libfuncs (flodiv_optab, "div", '3'); + init_floating_libfuncs (ftrunc_optab, "ftrunc", '2'); + init_integral_libfuncs (and_optab, "and", '3'); + init_integral_libfuncs (ior_optab, "ior", '3'); + init_integral_libfuncs (xor_optab, "xor", '3'); + init_integral_libfuncs (ashl_optab, "ashl", '3'); + init_integral_libfuncs (ashr_optab, "ashr", '3'); + init_integral_libfuncs (lshl_optab, "lshl", '3'); + init_integral_libfuncs (lshr_optab, "lshr", '3'); + init_integral_libfuncs (rotl_optab, "rotl", '3'); + init_integral_libfuncs (rotr_optab, "rotr", '3'); + init_integral_libfuncs (smin_optab, "min", '3'); + init_floating_libfuncs (smin_optab, "min", '3'); + init_integral_libfuncs (smax_optab, "max", '3'); + init_floating_libfuncs (smax_optab, "max", '3'); + init_integral_libfuncs (umin_optab, "umin", '3'); + init_integral_libfuncs (umax_optab, "umax", '3'); + init_integral_libfuncs (neg_optab, "neg", '2'); + init_floating_libfuncs (neg_optab, "neg", '2'); + init_integral_libfuncs (one_cmpl_optab, "one_cmpl", '2'); + init_integral_libfuncs (ffs_optab, "ffs", '2'); + + /* Comparison libcalls for integers MUST come in pairs, signed/unsigned. */ + init_integral_libfuncs (cmp_optab, "cmp", '2'); + init_integral_libfuncs (ucmp_optab, "ucmp", '2'); + init_floating_libfuncs (cmp_optab, "cmp", '2'); + +#ifdef MULSI3_LIBCALL + smul_optab->handlers[(int) SImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, MULSI3_LIBCALL); +#endif +#ifdef MULDI3_LIBCALL + smul_optab->handlers[(int) DImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, MULDI3_LIBCALL); +#endif +#ifdef MULTI3_LIBCALL + smul_optab->handlers[(int) TImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, MULTI3_LIBCALL); +#endif + +#ifdef DIVSI3_LIBCALL + sdiv_optab->handlers[(int) SImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, DIVSI3_LIBCALL); +#endif +#ifdef DIVDI3_LIBCALL + sdiv_optab->handlers[(int) DImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, DIVDI3_LIBCALL); +#endif +#ifdef DIVTI3_LIBCALL + sdiv_optab->handlers[(int) TImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, DIVTI3_LIBCALL); +#endif + +#ifdef UDIVSI3_LIBCALL + udiv_optab->handlers[(int) SImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, UDIVSI3_LIBCALL); +#endif +#ifdef UDIVDI3_LIBCALL + udiv_optab->handlers[(int) DImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, UDIVDI3_LIBCALL); +#endif +#ifdef UDIVTI3_LIBCALL + udiv_optab->handlers[(int) TImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, UDIVTI3_LIBCALL); +#endif + + +#ifdef MODSI3_LIBCALL + smod_optab->handlers[(int) SImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, MODSI3_LIBCALL); +#endif +#ifdef MODDI3_LIBCALL + smod_optab->handlers[(int) DImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, MODDI3_LIBCALL); +#endif +#ifdef MODTI3_LIBCALL + smod_optab->handlers[(int) TImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, MODTI3_LIBCALL); +#endif + + +#ifdef UMODSI3_LIBCALL + umod_optab->handlers[(int) SImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, UMODSI3_LIBCALL); +#endif +#ifdef UMODDI3_LIBCALL + umod_optab->handlers[(int) DImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, UMODDI3_LIBCALL); +#endif +#ifdef UMODTI3_LIBCALL + umod_optab->handlers[(int) TImode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, UMODTI3_LIBCALL); +#endif + + /* Use cabs for DC complex abs, since systems generally have cabs. + Don't define any libcall for SCmode, so that cabs will be used. */ + abs_optab->handlers[(int) DCmode].libfunc + = gen_rtx (SYMBOL_REF, Pmode, "cabs"); + + ffs_optab->handlers[(int) mode_for_size (BITS_PER_WORD, MODE_INT, 0)] .libfunc + = gen_rtx (SYMBOL_REF, Pmode, "ffs"); + + extendsfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__extendsfdf2"); + extendsfxf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__extendsfxf2"); + extendsftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__extendsftf2"); + extenddfxf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__extenddfxf2"); + extenddftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__extenddftf2"); + + truncdfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__truncdfsf2"); + truncxfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__truncxfsf2"); + trunctfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__trunctfsf2"); + truncxfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__truncxfdf2"); + trunctfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__trunctfdf2"); + + memcpy_libfunc = gen_rtx (SYMBOL_REF, Pmode, "memcpy"); + bcopy_libfunc = gen_rtx (SYMBOL_REF, Pmode, "bcopy"); + memcmp_libfunc = gen_rtx (SYMBOL_REF, Pmode, "memcmp"); + bcmp_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__gcc_bcmp"); + memset_libfunc = gen_rtx (SYMBOL_REF, Pmode, "memset"); + bzero_libfunc = gen_rtx (SYMBOL_REF, Pmode, "bzero"); + + eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__eqsf2"); + nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__nesf2"); + gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__gtsf2"); + gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__gesf2"); + ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__ltsf2"); + lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__lesf2"); + + eqdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__eqdf2"); + nedf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__nedf2"); + gtdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__gtdf2"); + gedf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__gedf2"); + ltdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__ltdf2"); + ledf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__ledf2"); + + eqxf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__eqxf2"); + nexf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__nexf2"); + gtxf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__gtxf2"); + gexf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__gexf2"); + ltxf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__ltxf2"); + lexf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__lexf2"); + + eqtf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__eqtf2"); + netf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__netf2"); + gttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__gttf2"); + getf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__getf2"); + lttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__lttf2"); + letf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__letf2"); + + floatsisf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floatsisf"); + floatdisf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floatdisf"); + floattisf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floattisf"); + + floatsidf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floatsidf"); + floatdidf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floatdidf"); + floattidf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floattidf"); + + floatsixf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floatsixf"); + floatdixf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floatdixf"); + floattixf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floattixf"); + + floatsitf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floatsitf"); + floatditf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floatditf"); + floattitf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__floattitf"); + + fixsfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixsfsi"); + fixsfdi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixsfdi"); + fixsfti_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixsfti"); + + fixdfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixdfsi"); + fixdfdi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixdfdi"); + fixdfti_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixdfti"); + + fixxfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixxfsi"); + fixxfdi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixxfdi"); + fixxfti_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixxfti"); + + fixtfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixtfsi"); + fixtfdi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixtfdi"); + fixtfti_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixtfti"); + + fixunssfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunssfsi"); + fixunssfdi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunssfdi"); + fixunssfti_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunssfti"); + + fixunsdfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunsdfsi"); + fixunsdfdi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunsdfdi"); + fixunsdfti_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunsdfti"); + + fixunsxfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunsxfsi"); + fixunsxfdi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunsxfdi"); + fixunsxfti_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunsxfti"); + + fixunstfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunstfsi"); + fixunstfdi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunstfdi"); + fixunstfti_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__fixunstfti"); +} + +#ifdef BROKEN_LDEXP + +/* SCO 3.2 apparently has a broken ldexp. */ + +double +ldexp(x,n) + double x; + int n; +{ + if (n > 0) + while (n--) + x *= 2; + + return x; +} +#endif /* BROKEN_LDEXP */ diff --git a/gnu/usr.bin/cc/lib/output.h b/gnu/usr.bin/cc/lib/output.h new file mode 100644 index 000000000000..7e5d03e74b0a --- /dev/null +++ b/gnu/usr.bin/cc/lib/output.h @@ -0,0 +1,171 @@ +/* Declarations for insn-output.c. These functions are defined in recog.c, + final.c, and varasm.c. + Copyright (C) 1987, 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef STDIO_PROTO +#ifdef BUFSIZ +#define STDIO_PROTO(ARGS) PROTO(ARGS) +#else +#define STDIO_PROTO(ARGS) () +#endif +#endif + +/* Output a string of assembler code, substituting insn operands. + Defined in final.c. */ +extern void output_asm_insn PROTO((char *, rtx *)); + +/* Output a string of assembler code, substituting numbers, strings + and fixed syntactic prefixes. */ +extern void asm_fprintf (); + +/* Print an integer constant expression in assembler syntax. + Addition and subtraction are the only arithmetic + that may appear in these expressions. */ +extern void output_addr_const STDIO_PROTO((FILE *, rtx)); + +/* Output a name (as found inside a symbol_ref) in assembler syntax. */ +extern void assemble_name STDIO_PROTO((FILE *, char *)); + +/* Replace a SUBREG with a REG or a MEM, based on the thing it is a + subreg of. */ +extern rtx alter_subreg PROTO((rtx)); + +/* When outputting assembler code, indicates which alternative + of the constraints was actually satisfied. */ +extern int which_alternative; + +/* When outputting delayed branch sequences, this rtx holds the + sequence being output. It is null when no delayed branch + sequence is being output, so it can be used as a test in the + insn output code. + + This variable is defined in final.c. */ +extern rtx final_sequence; + +/* Number of bytes of args popped by function being compiled on its return. + Zero if no bytes are to be popped. + May affect compilation of return insn or of function epilogue. */ + +extern int current_function_pops_args; + +/* Nonzero if function being compiled needs to be given an address + where the value should be stored. */ + +extern int current_function_returns_struct; + +/* Nonzero if function being compiled needs to + return the address of where it has put a structure value. */ + +extern int current_function_returns_pcc_struct; + +/* Nonzero if function being compiled needs to be passed a static chain. */ + +extern int current_function_needs_context; + +/* Nonzero if function being compiled can call setjmp. */ + +extern int current_function_calls_setjmp; + +/* Nonzero if function being compiled can call longjmp. */ + +extern int current_function_calls_longjmp; + +/* Nonzero if function being compiled can call alloca, + either as a subroutine or builtin. */ + +extern int current_function_calls_alloca; + +/* Nonzero if function being compiled receives nonlocal gotos + from nested functions. */ + +extern int current_function_has_nonlocal_label; + +/* Nonzero if function being compiled contains nested functions. */ + +extern int current_function_contains_functions; + +/* Nonzero if the current function returns a pointer type */ + +extern int current_function_returns_pointer; + +/* If function's args have a fixed size, this is that size, in bytes. + Otherwise, it is -1. + May affect compilation of return insn or of function epilogue. */ + +extern int current_function_args_size; + +/* # bytes the prologue should push and pretend that the caller pushed them. + The prologue must do this, but only if parms can be passed in registers. */ + +extern int current_function_pretend_args_size; + +/* # of bytes of outgoing arguments required to be pushed by the prologue. + If this is non-zero, it means that ACCUMULATE_OUTGOING_ARGS was defined + and no stack adjusts will be done on function calls. */ + +extern int current_function_outgoing_args_size; + +/* Nonzero if current function uses varargs.h or equivalent. + Zero for functions that use stdarg.h. */ + +extern int current_function_varargs; + +/* Quantities of various kinds of registers + used for the current function's args. */ + +extern CUMULATIVE_ARGS current_function_args_info; + +/* Name of function now being compiled. */ + +extern char *current_function_name; + +/* If non-zero, an RTL expression for that location at which the current + function returns its result. Usually equal to + DECL_RTL (DECL_RESULT (current_function_decl)). */ + +extern rtx current_function_return_rtx; + +/* If some insns can be deferred to the delay slots of the epilogue, the + delay list for them is recorded here. */ + +extern rtx current_function_epilogue_delay_list; + +/* Nonzero means generate position-independent code. + This is not fully implemented yet. */ + +extern int flag_pic; + +/* This is nonzero if the current function uses pic_offset_table_rtx. */ +extern int current_function_uses_pic_offset_table; + +/* This is nonzero if the current function uses the constant pool. */ +extern int current_function_uses_const_pool; + +/* The line number of the beginning of the current function. + sdbout.c needs this so that it can output relative linenumbers. */ + +#ifdef SDB_DEBUGGING_INFO /* Avoid undef sym in certain broken linkers. */ +extern int sdb_begin_function_line; +#endif + +/* File in which assembler code is being written. */ + +#ifdef BUFSIZ +extern FILE *asm_out_file; +#endif diff --git a/gnu/usr.bin/cc/lib/print-rtl.c b/gnu/usr.bin/cc/lib/print-rtl.c new file mode 100644 index 000000000000..651659eb9249 --- /dev/null +++ b/gnu/usr.bin/cc/lib/print-rtl.c @@ -0,0 +1,328 @@ +/* Print RTL for GNU C Compiler. + Copyright (C) 1987-1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include +#include +#include "rtl.h" + + +/* How to print out a register name. + We don't use PRINT_REG because some definitions of PRINT_REG + don't work here. */ +#ifndef DEBUG_PRINT_REG +#define DEBUG_PRINT_REG(RTX, CODE, FILE) \ + fprintf ((FILE), "%d %s", REGNO (RTX), reg_names[REGNO (RTX)]) +#endif + +/* Array containing all of the register names */ + +#ifdef DEBUG_REGISTER_NAMES +static char *reg_names[] = DEBUG_REGISTER_NAMES; +#else +static char *reg_names[] = REGISTER_NAMES; +#endif + +static FILE *outfile; + +char spaces[] = " "; + +static int sawclose = 0; + +/* Names for patterns. Non-zero only when linked with insn-output.c. */ + +extern char **insn_name_ptr; + +/* Print IN_RTX onto OUTFILE. This is the recursive part of printing. */ + +static void +print_rtx (in_rtx) + register rtx in_rtx; +{ + static int indent; + register int i, j; + register char *format_ptr; + register int is_insn; + + if (sawclose) + { + fprintf (outfile, "\n%s", + (spaces + (sizeof spaces - 1 - indent * 2))); + sawclose = 0; + } + + if (in_rtx == 0) + { + fprintf (outfile, "(nil)"); + sawclose = 1; + return; + } + + /* print name of expression code */ + fprintf (outfile, "(%s", GET_RTX_NAME (GET_CODE (in_rtx))); + + if (in_rtx->in_struct) + fprintf (outfile, "/s"); + + if (in_rtx->volatil) + fprintf (outfile, "/v"); + + if (in_rtx->unchanging) + fprintf (outfile, "/u"); + + if (in_rtx->integrated) + fprintf (outfile, "/i"); + + if (GET_MODE (in_rtx) != VOIDmode) + { + /* Print REG_NOTE names for EXPR_LIST and INSN_LIST. */ + if (GET_CODE (in_rtx) == EXPR_LIST || GET_CODE (in_rtx) == INSN_LIST) + fprintf (outfile, ":%s", GET_REG_NOTE_NAME (GET_MODE (in_rtx))); + else + fprintf (outfile, ":%s", GET_MODE_NAME (GET_MODE (in_rtx))); + } + + is_insn = (GET_RTX_CLASS (GET_CODE (in_rtx)) == 'i'); + format_ptr = GET_RTX_FORMAT (GET_CODE (in_rtx)); + + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (in_rtx)); i++) + switch (*format_ptr++) + { + case 'S': + case 's': + if (XSTR (in_rtx, i) == 0) + fprintf (outfile, " \"\""); + else + fprintf (outfile, " (\"%s\")", XSTR (in_rtx, i)); + sawclose = 1; + break; + + /* 0 indicates a field for internal use that should not be printed. */ + case '0': + break; + + case 'e': + indent += 2; + if (!sawclose) + fprintf (outfile, " "); + print_rtx (XEXP (in_rtx, i)); + indent -= 2; + break; + + case 'E': + case 'V': + indent += 2; + if (sawclose) + { + fprintf (outfile, "\n%s", + (spaces + (sizeof spaces - 1 - indent * 2))); + sawclose = 0; + } + fprintf (outfile, "[ "); + if (NULL != XVEC (in_rtx, i)) + { + indent += 2; + if (XVECLEN (in_rtx, i)) + sawclose = 1; + + for (j = 0; j < XVECLEN (in_rtx, i); j++) + print_rtx (XVECEXP (in_rtx, i, j)); + + indent -= 2; + } + if (sawclose) + fprintf (outfile, "\n%s", + (spaces + (sizeof spaces - 1 - indent * 2))); + + fprintf (outfile, "] "); + sawclose = 1; + indent -= 2; + break; + + case 'w': + fprintf (outfile, +#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT + " %d", +#else + " %ld", +#endif + XWINT (in_rtx, i)); + break; + + case 'i': + { + register int value = XINT (in_rtx, i); + + if (GET_CODE (in_rtx) == REG && value < FIRST_PSEUDO_REGISTER) + { + fputc (' ', outfile); + DEBUG_PRINT_REG (in_rtx, 0, outfile); + } + else + fprintf (outfile, " %d", value); + } + if (is_insn && &INSN_CODE (in_rtx) == &XINT (in_rtx, i) + && insn_name_ptr + && XINT (in_rtx, i) >= 0) + fprintf (outfile, " {%s}", insn_name_ptr[XINT (in_rtx, i)]); + sawclose = 0; + break; + + /* Print NOTE_INSN names rather than integer codes. */ + + case 'n': + if (XINT (in_rtx, i) <= 0) + fprintf (outfile, " %s", GET_NOTE_INSN_NAME (XINT (in_rtx, i))); + else + fprintf (outfile, " %d", XINT (in_rtx, i)); + sawclose = 0; + break; + + case 'u': + if (XEXP (in_rtx, i) != NULL) + fprintf (outfile, " %d", INSN_UID (XEXP (in_rtx, i))); + else + fprintf (outfile, " 0"); + sawclose = 0; + break; + + case '*': + fprintf (outfile, " Unknown"); + sawclose = 0; + break; + + default: + fprintf (stderr, + "switch format wrong in rtl.print_rtx(). format was: %c.\n", + format_ptr[-1]); + abort (); + } + + fprintf (outfile, ")"); + sawclose = 1; +} + +/* Call this function from the debugger to see what X looks like. */ + +void +debug_rtx (x) + rtx x; +{ + outfile = stderr; + print_rtx (x); + fprintf (stderr, "\n"); +} + +/* Count of rtx's to print with debug_rtx_list. + This global exists because gdb user defined commands have no arguments. */ + +int debug_rtx_count = 0; /* 0 is treated as equivalent to 1 */ + +/* Call this function to print list from X on. + + N is a count of the rtx's to print. Positive values print from the specified + rtx on. Negative values print a window around the rtx. + EG: -5 prints 2 rtx's on either side (in addition to the specified rtx). */ + +void +debug_rtx_list (x, n) + rtx x; + int n; +{ + int i,count; + rtx insn; + + count = n == 0 ? 1 : n < 0 ? -n : n; + + /* If we are printing a window, back up to the start. */ + + if (n < 0) + for (i = count / 2; i > 0; i--) + { + if (PREV_INSN (x) == 0) + break; + x = PREV_INSN (x); + } + + for (i = count, insn = x; i > 0 && insn != 0; i--, insn = NEXT_INSN (insn)) + debug_rtx (insn); +} + +/* Call this function to search an rtx list to find one with insn uid UID, + and then call debug_rtx_list to print it, using DEBUG_RTX_COUNT. + The found insn is returned to enable further debugging analysis. */ + +rtx +debug_rtx_find(x, uid) + rtx x; + int uid; +{ + while (x != 0 && INSN_UID (x) != uid) + x = NEXT_INSN (x); + if (x != 0) + { + debug_rtx_list (x, debug_rtx_count); + return x; + } + else + { + fprintf (stderr, "insn uid %d not found\n", uid); + return 0; + } +} + +/* External entry point for printing a chain of insns + starting with RTX_FIRST onto file OUTF. + A blank line separates insns. + + If RTX_FIRST is not an insn, then it alone is printed, with no newline. */ + +void +print_rtl (outf, rtx_first) + FILE *outf; + rtx rtx_first; +{ + register rtx tmp_rtx; + + outfile = outf; + sawclose = 0; + + if (rtx_first == 0) + fprintf (outf, "(nil)\n"); + else + switch (GET_CODE (rtx_first)) + { + case INSN: + case JUMP_INSN: + case CALL_INSN: + case NOTE: + case CODE_LABEL: + case BARRIER: + for (tmp_rtx = rtx_first; NULL != tmp_rtx; tmp_rtx = NEXT_INSN (tmp_rtx)) + { + print_rtx (tmp_rtx); + fprintf (outfile, "\n"); + } + break; + + default: + print_rtx (rtx_first); + } +} diff --git a/gnu/usr.bin/cc/lib/print-tree.c b/gnu/usr.bin/cc/lib/print-tree.c new file mode 100644 index 000000000000..f1c5b2100a95 --- /dev/null +++ b/gnu/usr.bin/cc/lib/print-tree.c @@ -0,0 +1,630 @@ +/* Prints out tree in human readable form - GNU C-compiler + Copyright (C) 1990, 1991, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include "tree.h" +#include + +extern char **tree_code_name; + +extern char *mode_name[]; + +void print_node (); +void indent_to (); + +/* Define the hash table of nodes already seen. + Such nodes are not repeated; brief cross-references are used. */ + +#define HASH_SIZE 37 + +struct bucket +{ + tree node; + struct bucket *next; +}; + +static struct bucket **table; + +/* Print the node NODE on standard error, for debugging. + Most nodes referred to by this one are printed recursively + down to a depth of six. */ + +void +debug_tree (node) + tree node; +{ + char *object = (char *) oballoc (0); + table = (struct bucket **) oballoc (HASH_SIZE * sizeof (struct bucket *)); + bzero (table, HASH_SIZE * sizeof (struct bucket *)); + print_node (stderr, "", node, 0); + table = 0; + obfree (object); + fprintf (stderr, "\n"); +} + +/* Print a node in brief fashion, with just the code, address and name. */ + +void +print_node_brief (file, prefix, node, indent) + FILE *file; + char *prefix; + tree node; + int indent; +{ + char class; + + if (node == 0) + return; + + class = TREE_CODE_CLASS (TREE_CODE (node)); + + /* Always print the slot this node is in, and its code, address and + name if any. */ + if (indent > 0) + fprintf (file, " "); + fprintf (file, "%s <%s ", prefix, tree_code_name[(int) TREE_CODE (node)]); + fprintf (file, HOST_PTR_PRINTF, (HOST_WIDE_INT) node); + + if (class == 'd') + { + if (DECL_NAME (node)) + fprintf (file, " %s", IDENTIFIER_POINTER (DECL_NAME (node))); + } + else if (class == 't') + { + if (TYPE_NAME (node)) + { + if (TREE_CODE (TYPE_NAME (node)) == IDENTIFIER_NODE) + fprintf (file, " %s", IDENTIFIER_POINTER (TYPE_NAME (node))); + else if (TREE_CODE (TYPE_NAME (node)) == TYPE_DECL + && DECL_NAME (TYPE_NAME (node))) + fprintf (file, " %s", + IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (node)))); + } + } + if (TREE_CODE (node) == IDENTIFIER_NODE) + fprintf (file, " %s", IDENTIFIER_POINTER (node)); + /* We might as well always print the value of an integer. */ + if (TREE_CODE (node) == INTEGER_CST) + { + if (TREE_INT_CST_HIGH (node) == 0) + fprintf (file, " %1u", TREE_INT_CST_LOW (node)); + else if (TREE_INT_CST_HIGH (node) == -1 + && TREE_INT_CST_LOW (node) != 0) + fprintf (file, " -%1u", -TREE_INT_CST_LOW (node)); + else + fprintf (file, +#if HOST_BITS_PER_WIDE_INT == 64 +#if HOST_BITS_PER_WIDE_INT != HOST_BITS_PER_INT + " 0x%lx%016lx", +#else + " 0x%x%016x", +#endif +#else +#if HOST_BITS_PER_WIDE_INT != HOST_BITS_PER_INT + " 0x%lx%08lx", +#else + " 0x%x%08x", +#endif +#endif + TREE_INT_CST_HIGH (node), TREE_INT_CST_LOW (node)); + } + if (TREE_CODE (node) == REAL_CST) + { +#ifndef REAL_IS_NOT_DOUBLE + fprintf (file, " %e", TREE_REAL_CST (node)); +#else + { + int i; + char *p = (char *) &TREE_REAL_CST (node); + fprintf (file, " 0x"); + for (i = 0; i < sizeof TREE_REAL_CST (node); i++) + fprintf (file, "%02x", *p++); + fprintf (file, ""); + } +#endif /* REAL_IS_NOT_DOUBLE */ + } + + fprintf (file, ">"); +} + +void +indent_to (file, column) + FILE *file; + int column; +{ + int i; + + /* Since this is the long way, indent to desired column. */ + if (column > 0) + fprintf (file, "\n"); + for (i = 0; i < column; i++) + fprintf (file, " "); +} + +/* Print the node NODE in full on file FILE, preceded by PREFIX, + starting in column INDENT. */ + +void +print_node (file, prefix, node, indent) + FILE *file; + char *prefix; + tree node; + int indent; +{ + int hash; + struct bucket *b; + enum machine_mode mode; + char class; + int len; + int first_rtl; + int i; + + if (node == 0) + return; + + class = TREE_CODE_CLASS (TREE_CODE (node)); + + /* Don't get too deep in nesting. If the user wants to see deeper, + it is easy to use the address of a lowest-level node + as an argument in another call to debug_tree. */ + + if (indent > 24) + { + print_node_brief (file, prefix, node, indent); + return; + } + + if (indent > 8 && (class == 't' || class == 'd')) + { + print_node_brief (file, prefix, node, indent); + return; + } + + /* It is unsafe to look at any other filds of an ERROR_MARK node. */ + if (TREE_CODE (node) == ERROR_MARK) + { + print_node_brief (file, prefix, node, indent); + return; + } + + hash = ((unsigned HOST_WIDE_INT) node) % HASH_SIZE; + + /* If node is in the table, just mention its address. */ + for (b = table[hash]; b; b = b->next) + if (b->node == node) + { + print_node_brief (file, prefix, node, indent); + return; + } + + /* Add this node to the table. */ + b = (struct bucket *) oballoc (sizeof (struct bucket)); + b->node = node; + b->next = table[hash]; + table[hash] = b; + + /* Indent to the specified column, since this is the long form. */ + indent_to (file, indent); + + /* Print the slot this node is in, and its code, and address. */ + fprintf (file, "%s <%s ", prefix, tree_code_name[(int) TREE_CODE (node)]); + fprintf (file, HOST_PTR_PRINTF, (HOST_WIDE_INT) node); + + /* Print the name, if any. */ + if (class == 'd') + { + if (DECL_NAME (node)) + fprintf (file, " %s", IDENTIFIER_POINTER (DECL_NAME (node))); + } + else if (class == 't') + { + if (TYPE_NAME (node)) + { + if (TREE_CODE (TYPE_NAME (node)) == IDENTIFIER_NODE) + fprintf (file, " %s", IDENTIFIER_POINTER (TYPE_NAME (node))); + else if (TREE_CODE (TYPE_NAME (node)) == TYPE_DECL + && DECL_NAME (TYPE_NAME (node))) + fprintf (file, " %s", + IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (node)))); + } + } + if (TREE_CODE (node) == IDENTIFIER_NODE) + fprintf (file, " %s", IDENTIFIER_POINTER (node)); + + if (TREE_CODE (node) == INTEGER_CST) + { + if (indent <= 4) + print_node_brief (file, "type", TREE_TYPE (node), indent + 4); + } + else + { + print_node (file, "type", TREE_TYPE (node), indent + 4); + if (TREE_TYPE (node)) + indent_to (file, indent + 3); + } + + /* If a permanent object is in the wrong obstack, or the reverse, warn. */ + if (object_permanent_p (node) != TREE_PERMANENT (node)) + { + if (TREE_PERMANENT (node)) + fputs (" !!permanent object in non-permanent obstack!!", file); + else + fputs (" !!non-permanent object in permanent obstack!!", file); + indent_to (file, indent + 3); + } + + if (TREE_SIDE_EFFECTS (node)) + fputs (" side-effects", file); + if (TREE_READONLY (node)) + fputs (" readonly", file); + if (TREE_CONSTANT (node)) + fputs (" constant", file); + if (TREE_ADDRESSABLE (node)) + fputs (" addressable", file); + if (TREE_THIS_VOLATILE (node)) + fputs (" volatile", file); + if (TREE_UNSIGNED (node)) + fputs (" unsigned", file); + if (TREE_ASM_WRITTEN (node)) + fputs (" asm_written", file); + if (TREE_USED (node)) + fputs (" used", file); + if (TREE_RAISES (node)) + fputs (" raises", file); + if (TREE_PERMANENT (node)) + fputs (" permanent", file); + if (TREE_PUBLIC (node)) + fputs (" public", file); + if (TREE_STATIC (node)) + fputs (" static", file); + if (TREE_LANG_FLAG_0 (node)) + fputs (" tree_0", file); + if (TREE_LANG_FLAG_1 (node)) + fputs (" tree_1", file); + if (TREE_LANG_FLAG_2 (node)) + fputs (" tree_2", file); + if (TREE_LANG_FLAG_3 (node)) + fputs (" tree_3", file); + if (TREE_LANG_FLAG_4 (node)) + fputs (" tree_4", file); + if (TREE_LANG_FLAG_5 (node)) + fputs (" tree_5", file); + if (TREE_LANG_FLAG_6 (node)) + fputs (" tree_6", file); + + /* DECL_ nodes have additional attributes. */ + + switch (TREE_CODE_CLASS (TREE_CODE (node))) + { + case 'd': + mode = DECL_MODE (node); + + if (DECL_EXTERNAL (node)) + fputs (" external", file); + if (DECL_NONLOCAL (node)) + fputs (" nonlocal", file); + if (DECL_REGISTER (node)) + fputs (" regdecl", file); + if (DECL_INLINE (node)) + fputs (" inline", file); + if (DECL_BIT_FIELD (node)) + fputs (" bit-field", file); + if (DECL_VIRTUAL_P (node)) + fputs (" virtual", file); + if (DECL_IGNORED_P (node)) + fputs (" ignored", file); + if (DECL_IN_SYSTEM_HEADER (node)) + fputs (" in_system_header", file); + if (DECL_LANG_FLAG_0 (node)) + fputs (" decl_0", file); + if (DECL_LANG_FLAG_1 (node)) + fputs (" decl_1", file); + if (DECL_LANG_FLAG_2 (node)) + fputs (" decl_2", file); + if (DECL_LANG_FLAG_3 (node)) + fputs (" decl_3", file); + if (DECL_LANG_FLAG_4 (node)) + fputs (" decl_4", file); + if (DECL_LANG_FLAG_5 (node)) + fputs (" decl_5", file); + if (DECL_LANG_FLAG_6 (node)) + fputs (" decl_6", file); + if (DECL_LANG_FLAG_7 (node)) + fputs (" decl_7", file); + + fprintf (file, " %s", mode_name[(int) mode]); + + fprintf (file, " file %s line %d", + DECL_SOURCE_FILE (node), DECL_SOURCE_LINE (node)); + + print_node (file, "size", DECL_SIZE (node), indent + 4); + indent_to (file, indent + 3); + if (TREE_CODE (node) != FUNCTION_DECL) + fprintf (file, " align %d", DECL_ALIGN (node)); + else if (DECL_INLINE (node)) + fprintf (file, " frame_size %d", DECL_FRAME_SIZE (node)); + else if (DECL_BUILT_IN (node)) + fprintf (file, " built-in code %d", DECL_FUNCTION_CODE (node)); + if (TREE_CODE (node) == FIELD_DECL) + print_node (file, "bitpos", DECL_FIELD_BITPOS (node), indent + 4); + print_node_brief (file, "context", DECL_CONTEXT (node), indent + 4); + print_node_brief (file, "abstract_origin", + DECL_ABSTRACT_ORIGIN (node), indent + 4); + + print_node (file, "arguments", DECL_ARGUMENTS (node), indent + 4); + print_node (file, "result", DECL_RESULT (node), indent + 4); + print_node_brief (file, "initial", DECL_INITIAL (node), indent + 4); + + print_lang_decl (file, node, indent); + + if (DECL_RTL (node) != 0) + { + indent_to (file, indent + 4); + print_rtl (file, DECL_RTL (node)); + } + + if (DECL_SAVED_INSNS (node) != 0) + { + indent_to (file, indent + 4); + if (TREE_CODE (node) == PARM_DECL) + { + fprintf (file, "incoming-rtl "); + print_rtl (file, DECL_INCOMING_RTL (node)); + } + else if (TREE_CODE (node) == FUNCTION_DECL) + { + fprintf (file, "saved-insns "); + fprintf (file, HOST_PTR_PRINTF, + (HOST_WIDE_INT) DECL_SAVED_INSNS (node)); + } + } + + /* Print the decl chain only if decl is at second level. */ + if (indent == 4) + print_node (file, "chain", TREE_CHAIN (node), indent + 4); + else + print_node_brief (file, "chain", TREE_CHAIN (node), indent + 4); + break; + + case 't': + if (TYPE_NO_FORCE_BLK (node)) + fputs (" no_force_blk", file); + if (TYPE_LANG_FLAG_0 (node)) + fputs (" type_0", file); + if (TYPE_LANG_FLAG_1 (node)) + fputs (" type_1", file); + if (TYPE_LANG_FLAG_2 (node)) + fputs (" type_2", file); + if (TYPE_LANG_FLAG_3 (node)) + fputs (" type_3", file); + if (TYPE_LANG_FLAG_4 (node)) + fputs (" type_4", file); + if (TYPE_LANG_FLAG_5 (node)) + fputs (" type_5", file); + if (TYPE_LANG_FLAG_6 (node)) + fputs (" type_6", file); + + mode = TYPE_MODE (node); + fprintf (file, " %s", mode_name[(int) mode]); + + print_node (file, "size", TYPE_SIZE (node), indent + 4); + indent_to (file, indent + 3); + + fprintf (file, " align %d", TYPE_ALIGN (node)); + fprintf (file, " symtab %d", TYPE_SYMTAB_ADDRESS (node)); + + if (TREE_CODE (node) == ARRAY_TYPE || TREE_CODE (node) == SET_TYPE) + print_node (file, "domain", TYPE_DOMAIN (node), indent + 4); + else if (TREE_CODE (node) == INTEGER_TYPE + || TREE_CODE (node) == BOOLEAN_TYPE + || TREE_CODE (node) == CHAR_TYPE) + { + fprintf (file, " precision %d", TYPE_PRECISION (node)); + print_node (file, "min", TYPE_MIN_VALUE (node), indent + 4); + print_node (file, "max", TYPE_MAX_VALUE (node), indent + 4); + } + else if (TREE_CODE (node) == ENUMERAL_TYPE) + { + fprintf (file, " precision %d", TYPE_PRECISION (node)); + print_node (file, "min", TYPE_MIN_VALUE (node), indent + 4); + print_node (file, "max", TYPE_MAX_VALUE (node), indent + 4); + print_node (file, "values", TYPE_VALUES (node), indent + 4); + } + else if (TREE_CODE (node) == REAL_TYPE) + fprintf (file, " precision %d", TYPE_PRECISION (node)); + else if (TREE_CODE (node) == RECORD_TYPE + || TREE_CODE (node) == UNION_TYPE + || TREE_CODE (node) == QUAL_UNION_TYPE) + print_node (file, "fields", TYPE_FIELDS (node), indent + 4); + else if (TREE_CODE (node) == FUNCTION_TYPE || TREE_CODE (node) == METHOD_TYPE) + { + if (TYPE_METHOD_BASETYPE (node)) + print_node_brief (file, "method basetype", TYPE_METHOD_BASETYPE (node), indent + 4); + print_node (file, "arg-types", TYPE_ARG_TYPES (node), indent + 4); + } + if (TYPE_CONTEXT (node)) + print_node_brief (file, "context", TYPE_CONTEXT (node), indent + 4); + + print_lang_type (file, node, indent); + + if (TYPE_POINTER_TO (node) || TREE_CHAIN (node)) + indent_to (file, indent + 3); + print_node_brief (file, "pointer_to_this", TYPE_POINTER_TO (node), indent + 4); + print_node_brief (file, "reference_to_this", TYPE_REFERENCE_TO (node), indent + 4); + print_node_brief (file, "chain", TREE_CHAIN (node), indent + 4); + break; + + case 'b': + print_node (file, "vars", BLOCK_VARS (node), indent + 4); + print_node (file, "tags", BLOCK_TYPE_TAGS (node), indent + 4); + print_node (file, "supercontext", BLOCK_SUPERCONTEXT (node), indent + 4); + print_node (file, "subblocks", BLOCK_SUBBLOCKS (node), indent + 4); + print_node (file, "chain", BLOCK_CHAIN (node), indent + 4); + print_node (file, "abstract_origin", + BLOCK_ABSTRACT_ORIGIN (node), indent + 4); + return; + + case 'e': + case '<': + case '1': + case '2': + case 'r': + case 's': + switch (TREE_CODE (node)) + { + case BIND_EXPR: + print_node (file, "vars", TREE_OPERAND (node, 0), indent + 4); + print_node (file, "body", TREE_OPERAND (node, 1), indent + 4); + print_node (file, "block", TREE_OPERAND (node, 2), indent + 4); + return; + } + + first_rtl = len = tree_code_length[(int) TREE_CODE (node)]; + /* These kinds of nodes contain rtx's, not trees, + after a certain point. Print the rtx's as rtx's. */ + switch (TREE_CODE (node)) + { + case SAVE_EXPR: + first_rtl = 2; + break; + case CALL_EXPR: + first_rtl = 2; + break; + case METHOD_CALL_EXPR: + first_rtl = 3; + break; + case WITH_CLEANUP_EXPR: + /* Should be defined to be 2. */ + first_rtl = 1; + break; + case RTL_EXPR: + first_rtl = 0; + } + for (i = 0; i < len; i++) + { + if (i >= first_rtl) + { + indent_to (file, indent + 4); + fprintf (file, "rtl %d ", i); + if (TREE_OPERAND (node, i)) + print_rtl (file, (struct rtx_def *) TREE_OPERAND (node, i)); + else + fprintf (file, "(nil)"); + fprintf (file, "\n"); + } + else + { + char temp[10]; + + sprintf (temp, "arg %d", i); + print_node (file, temp, TREE_OPERAND (node, i), indent + 4); + } + } + break; + + case 'c': + case 'x': + switch (TREE_CODE (node)) + { + case INTEGER_CST: + if (TREE_INT_CST_HIGH (node) == 0) + fprintf (file, " %1u", TREE_INT_CST_LOW (node)); + else if (TREE_INT_CST_HIGH (node) == -1 + && TREE_INT_CST_LOW (node) != 0) + fprintf (file, " -%1u", -TREE_INT_CST_LOW (node)); + else + fprintf (file, +#if HOST_BITS_PER_WIDE_INT == 64 +#if HOST_BITS_PER_WIDE_INT != HOST_BITS_PER_INT + " 0x%lx%016lx", +#else + " 0x%x%016x", +#endif +#else +#if HOST_BITS_PER_WIDE_INT != HOST_BITS_PER_INT + " 0x%lx%08lx", +#else + " 0x%x%08x", +#endif +#endif + TREE_INT_CST_HIGH (node), TREE_INT_CST_LOW (node)); + break; + + case REAL_CST: +#ifndef REAL_IS_NOT_DOUBLE + fprintf (file, " %e", TREE_REAL_CST (node)); +#else + { + char *p = (char *) &TREE_REAL_CST (node); + fprintf (file, " 0x"); + for (i = 0; i < sizeof TREE_REAL_CST (node); i++) + fprintf (file, "%02x", *p++); + fprintf (file, ""); + } +#endif /* REAL_IS_NOT_DOUBLE */ + break; + + case COMPLEX_CST: + print_node (file, "real", TREE_REALPART (node), indent + 4); + print_node (file, "imag", TREE_IMAGPART (node), indent + 4); + break; + + case STRING_CST: + fprintf (file, " \"%s\"", TREE_STRING_POINTER (node)); + /* Print the chain at second level. */ + if (indent == 4) + print_node (file, "chain", TREE_CHAIN (node), indent + 4); + else + print_node_brief (file, "chain", TREE_CHAIN (node), indent + 4); + break; + + case IDENTIFIER_NODE: + print_lang_identifier (file, node, indent); + break; + + case TREE_LIST: + print_node (file, "purpose", TREE_PURPOSE (node), indent + 4); + print_node (file, "value", TREE_VALUE (node), indent + 4); + print_node (file, "chain", TREE_CHAIN (node), indent + 4); + break; + + case TREE_VEC: + len = TREE_VEC_LENGTH (node); + for (i = 0; i < len; i++) + if (TREE_VEC_ELT (node, i)) + { + char temp[10]; + sprintf (temp, "elt %d", i); + indent_to (file, indent + 4); + print_node_brief (file, temp, TREE_VEC_ELT (node, i), 0); + } + break; + + case OP_IDENTIFIER: + print_node (file, "op1", TREE_PURPOSE (node), indent + 4); + print_node (file, "op2", TREE_VALUE (node), indent + 4); + } + + break; + } + + fprintf (file, ">"); +} diff --git a/gnu/usr.bin/cc/lib/real.c b/gnu/usr.bin/cc/lib/real.c new file mode 100644 index 000000000000..1e4a4fae5c8b --- /dev/null +++ b/gnu/usr.bin/cc/lib/real.c @@ -0,0 +1,5060 @@ +/* real.c - implementation of REAL_ARITHMETIC, REAL_VALUE_ATOF, +and support for XFmode IEEE extended real floating point arithmetic. +Contributed by Stephen L. Moshier (moshier@world.std.com). + + Copyright (C) 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include +#include +#include "config.h" +#include "tree.h" + +#ifndef errno +extern int errno; +#endif + +/* To enable support of XFmode extended real floating point, define +LONG_DOUBLE_TYPE_SIZE 96 in the tm.h file (m68k.h or i386.h). + +To support cross compilation between IEEE and VAX floating +point formats, define REAL_ARITHMETIC in the tm.h file. + +In either case the machine files (tm.h) must not contain any code +that tries to use host floating point arithmetic to convert +REAL_VALUE_TYPEs from `double' to `float', pass them to fprintf, +etc. In cross-compile situations a REAL_VALUE_TYPE may not +be intelligible to the host computer's native arithmetic. + +The emulator defaults to the host's floating point format so that +its decimal conversion functions can be used if desired (see +real.h). + +The first part of this file interfaces gcc to ieee.c, which is a +floating point arithmetic suite that was not written with gcc in +mind. The interface is followed by ieee.c itself and related +items. Avoid changing ieee.c unless you have suitable test +programs available. A special version of the PARANOIA floating +point arithmetic tester, modified for this purpose, can be found +on usc.edu : /pub/C-numanal/ieeetest.zoo. Some tutorial +information on ieee.c is given in my book: S. L. Moshier, +_Methods and Programs for Mathematical Functions_, Prentice-Hall +or Simon & Schuster Int'l, 1989. A library of XFmode elementary +transcendental functions can be obtained by ftp from +research.att.com: netlib/cephes/ldouble.shar.Z */ + +/* Type of computer arithmetic. + * Only one of DEC, MIEEE, IBMPC, or UNK should get defined. + */ + +/* `MIEEE' refers generically to big-endian IEEE floating-point data + structure. This definition should work in SFmode `float' type and + DFmode `double' type on virtually all big-endian IEEE machines. + If LONG_DOUBLE_TYPE_SIZE has been defined to be 96, then MIEEE + also invokes the particular XFmode (`long double' type) data + structure used by the Motorola 680x0 series processors. + + `IBMPC' refers generally to little-endian IEEE machines. In this + case, if LONG_DOUBLE_TYPE_SIZE has been defined to be 96, then + IBMPC also invokes the particular XFmode `long double' data + structure used by the Intel 80x86 series processors. + + `DEC' refers specifically to the Digital Equipment Corp PDP-11 + and VAX floating point data structure. This model currently + supports no type wider than DFmode. + + If LONG_DOUBLE_TYPE_SIZE = 64 (the default, unless tm.h defines it) + then `long double' and `double' are both implemented, but they + both mean DFmode. In this case, the software floating-point + support available here is activated by writing + #define REAL_ARITHMETIC + in tm.h. + + The case LONG_DOUBLE_TYPE_SIZE = 128 activates TFmode support + (Not Yet Implemented) and may deactivate XFmode since + `long double' is used to refer to both modes. */ + +/* The following converts gcc macros into the ones used by this file. */ + +/* REAL_ARITHMETIC defined means that macros in real.h are + defined to call emulator functions. */ +#ifdef REAL_ARITHMETIC + +#if TARGET_FLOAT_FORMAT == VAX_FLOAT_FORMAT +/* PDP-11, Pro350, VAX: */ +#define DEC 1 +#else /* it's not VAX */ +#if TARGET_FLOAT_FORMAT == IEEE_FLOAT_FORMAT +#if WORDS_BIG_ENDIAN +/* Motorola IEEE, high order words come first (Sun workstation): */ +#define MIEEE 1 +#else /* not big-endian */ +/* Intel IEEE, low order words come first: + */ +#define IBMPC 1 +#endif /* big-endian */ +#else /* it's not IEEE either */ +/* UNKnown arithmetic. We don't support this and can't go on. */ +unknown arithmetic type +#define UNK 1 +#endif /* not IEEE */ +#endif /* not VAX */ + +#else +/* REAL_ARITHMETIC not defined means that the *host's* data + structure will be used. It may differ by endian-ness from the + target machine's structure and will get its ends swapped + accordingly (but not here). Probably only the decimal <-> binary + functions in this file will actually be used in this case. */ +#if HOST_FLOAT_FORMAT == VAX_FLOAT_FORMAT +#define DEC 1 +#else /* it's not VAX */ +#if HOST_FLOAT_FORMAT == IEEE_FLOAT_FORMAT +#ifdef HOST_WORDS_BIG_ENDIAN +#define MIEEE 1 +#else /* not big-endian */ +#define IBMPC 1 +#endif /* big-endian */ +#else /* it's not IEEE either */ +unknown arithmetic type +#define UNK 1 +#endif /* not IEEE */ +#endif /* not VAX */ + +#endif /* REAL_ARITHMETIC not defined */ + +/* Define INFINITY for support of infinity. + Define NANS for support of Not-a-Number's (NaN's). */ +#ifndef DEC +#define INFINITY +#define NANS +#endif + +/* Support of NaNs requires support of infinity. */ +#ifdef NANS +#ifndef INFINITY +#define INFINITY +#endif +#endif + +/* ehead.h + * + * Include file for extended precision arithmetic programs. + */ + +/* Number of 16 bit words in external e type format */ +#define NE 6 + +/* Number of 16 bit words in internal format */ +#define NI (NE+3) + +/* Array offset to exponent */ +#define E 1 + +/* Array offset to high guard word */ +#define M 2 + +/* Number of bits of precision */ +#define NBITS ((NI-4)*16) + +/* Maximum number of decimal digits in ASCII conversion + * = NBITS*log10(2) + */ +#define NDEC (NBITS*8/27) + +/* The exponent of 1.0 */ +#define EXONE (0x3fff) + +/* Find a host integer type that is at least 16 bits wide, + and another type at least twice whatever that size is. */ + +#if HOST_BITS_PER_CHAR >= 16 +#define EMUSHORT char +#define EMUSHORT_SIZE HOST_BITS_PER_CHAR +#define EMULONG_SIZE (2 * HOST_BITS_PER_CHAR) +#else +#if HOST_BITS_PER_SHORT >= 16 +#define EMUSHORT short +#define EMUSHORT_SIZE HOST_BITS_PER_SHORT +#define EMULONG_SIZE (2 * HOST_BITS_PER_SHORT) +#else +#if HOST_BITS_PER_INT >= 16 +#define EMUSHORT int +#define EMUSHORT_SIZE HOST_BITS_PER_INT +#define EMULONG_SIZE (2 * HOST_BITS_PER_INT) +#else +#if HOST_BITS_PER_LONG >= 16 +#define EMUSHORT long +#define EMUSHORT_SIZE HOST_BITS_PER_LONG +#define EMULONG_SIZE (2 * HOST_BITS_PER_LONG) +#else +/* You will have to modify this program to have a smaller unit size. */ +#define EMU_NON_COMPILE +#endif +#endif +#endif +#endif + +#if HOST_BITS_PER_SHORT >= EMULONG_SIZE +#define EMULONG short +#else +#if HOST_BITS_PER_INT >= EMULONG_SIZE +#define EMULONG int +#else +#if HOST_BITS_PER_LONG >= EMULONG_SIZE +#define EMULONG long +#else +#if HOST_BITS_PER_LONG_LONG >= EMULONG_SIZE +#define EMULONG long long int +#else +/* You will have to modify this program to have a smaller unit size. */ +#define EMU_NON_COMPILE +#endif +#endif +#endif +#endif + + +/* The host interface doesn't work if no 16-bit size exists. */ +#if EMUSHORT_SIZE != 16 +#define EMU_NON_COMPILE +#endif + +/* OK to continue compilation. */ +#ifndef EMU_NON_COMPILE + +/* Construct macros to translate between REAL_VALUE_TYPE and e type. + In GET_REAL and PUT_REAL, r and e are pointers. + A REAL_VALUE_TYPE is guaranteed to occupy contiguous locations + in memory, with no holes. */ + +#if LONG_DOUBLE_TYPE_SIZE == 96 +#define GET_REAL(r,e) bcopy (r, e, 2*NE) +#define PUT_REAL(e,r) bcopy (e, r, 2*NE) +#else /* no XFmode */ + +#ifdef REAL_ARITHMETIC +/* Emulator uses target format internally + but host stores it in host endian-ness. */ + +#if defined (HOST_WORDS_BIG_ENDIAN) == WORDS_BIG_ENDIAN +#define GET_REAL(r,e) e53toe ((r), (e)) +#define PUT_REAL(e,r) etoe53 ((e), (r)) + +#else /* endian-ness differs */ +/* emulator uses target endian-ness internally */ +#define GET_REAL(r,e) \ +do { EMUSHORT w[4]; \ + w[3] = ((EMUSHORT *) r)[0]; \ + w[2] = ((EMUSHORT *) r)[1]; \ + w[1] = ((EMUSHORT *) r)[2]; \ + w[0] = ((EMUSHORT *) r)[3]; \ + e53toe (w, (e)); } while (0) + +#define PUT_REAL(e,r) \ +do { EMUSHORT w[4]; \ + etoe53 ((e), w); \ + *((EMUSHORT *) r) = w[3]; \ + *((EMUSHORT *) r + 1) = w[2]; \ + *((EMUSHORT *) r + 2) = w[1]; \ + *((EMUSHORT *) r + 3) = w[0]; } while (0) + +#endif /* endian-ness differs */ + +#else /* not REAL_ARITHMETIC */ + +/* emulator uses host format */ +#define GET_REAL(r,e) e53toe ((r), (e)) +#define PUT_REAL(e,r) etoe53 ((e), (r)) + +#endif /* not REAL_ARITHMETIC */ +#endif /* no XFmode */ + +void warning (); +extern int extra_warnings; +int ecmp (), enormlz (), eshift (); +int eisneg (), eisinf (), eisnan (), eiisinf (), eiisnan (); +void eadd (), esub (), emul (), ediv (); +void eshup1 (), eshup8 (), eshup6 (), eshdn1 (), eshdn8 (), eshdn6 (); +void eabs (), eneg (), emov (), eclear (), einfin (), efloor (); +void eldexp (), efrexp (), eifrac (), euifrac (), ltoe (), ultoe (); +void eround (), ereal_to_decimal (), eiinfin (), einan (); +void esqrt (), elog (), eexp (), etanh (), epow (); +void asctoe (), asctoe24 (), asctoe53 (), asctoe64 (); +void etoasc (), e24toasc (), e53toasc (), e64toasc (); +void etoe64 (), etoe53 (), etoe24 (), e64toe (), e53toe (), e24toe (); +void mtherr (), make_nan (); +void enan (); +extern unsigned EMUSHORT ezero[], ehalf[], eone[], etwo[]; +extern unsigned EMUSHORT elog2[], esqrt2[]; + +/* Pack output array with 32-bit numbers obtained from + array containing 16-bit numbers, swapping ends if required. */ +void +endian (e, x, mode) + unsigned EMUSHORT e[]; + long x[]; + enum machine_mode mode; +{ + unsigned long th, t; + +#if WORDS_BIG_ENDIAN + switch (mode) + { + + case XFmode: + + /* Swap halfwords in the third long. */ + th = (unsigned long) e[4] & 0xffff; + t = (unsigned long) e[5] & 0xffff; + t |= th << 16; + x[2] = (long) t; + /* fall into the double case */ + + case DFmode: + + /* swap halfwords in the second word */ + th = (unsigned long) e[2] & 0xffff; + t = (unsigned long) e[3] & 0xffff; + t |= th << 16; + x[1] = (long) t; + /* fall into the float case */ + + case SFmode: + + /* swap halfwords in the first word */ + th = (unsigned long) e[0] & 0xffff; + t = (unsigned long) e[1] & 0xffff; + t |= th << 16; + x[0] = t; + break; + + default: + abort (); + } + +#else + + /* Pack the output array without swapping. */ + + switch (mode) + { + + case XFmode: + + /* Pack the third long. + Each element of the input REAL_VALUE_TYPE array has 16 bit useful bits + in it. */ + th = (unsigned long) e[5] & 0xffff; + t = (unsigned long) e[4] & 0xffff; + t |= th << 16; + x[2] = (long) t; + /* fall into the double case */ + + case DFmode: + + /* pack the second long */ + th = (unsigned long) e[3] & 0xffff; + t = (unsigned long) e[2] & 0xffff; + t |= th << 16; + x[1] = (long) t; + /* fall into the float case */ + + case SFmode: + + /* pack the first long */ + th = (unsigned long) e[1] & 0xffff; + t = (unsigned long) e[0] & 0xffff; + t |= th << 16; + x[0] = t; + break; + + default: + abort (); + } + +#endif +} + + +/* This is the implementation of the REAL_ARITHMETIC macro. + */ +void +earith (value, icode, r1, r2) + REAL_VALUE_TYPE *value; + int icode; + REAL_VALUE_TYPE *r1; + REAL_VALUE_TYPE *r2; +{ + unsigned EMUSHORT d1[NE], d2[NE], v[NE]; + enum tree_code code; + + GET_REAL (r1, d1); + GET_REAL (r2, d2); +#ifdef NANS +/* Return NaN input back to the caller. */ + if (eisnan (d1)) + { + PUT_REAL (d1, value); + return; + } + if (eisnan (d2)) + { + PUT_REAL (d2, value); + return; + } +#endif + code = (enum tree_code) icode; + switch (code) + { + case PLUS_EXPR: + eadd (d2, d1, v); + break; + + case MINUS_EXPR: + esub (d2, d1, v); /* d1 - d2 */ + break; + + case MULT_EXPR: + emul (d2, d1, v); + break; + + case RDIV_EXPR: +#ifndef REAL_INFINITY + if (ecmp (d2, ezero) == 0) + { +#ifdef NANS + enan (v); + break; +#else + abort (); +#endif + } +#endif + ediv (d2, d1, v); /* d1/d2 */ + break; + + case MIN_EXPR: /* min (d1,d2) */ + if (ecmp (d1, d2) < 0) + emov (d1, v); + else + emov (d2, v); + break; + + case MAX_EXPR: /* max (d1,d2) */ + if (ecmp (d1, d2) > 0) + emov (d1, v); + else + emov (d2, v); + break; + default: + emov (ezero, v); + break; + } +PUT_REAL (v, value); +} + + +/* Truncate REAL_VALUE_TYPE toward zero to signed HOST_WIDE_INT + * implements REAL_VALUE_RNDZINT (x) (etrunci (x)) + */ +REAL_VALUE_TYPE +etrunci (x) + REAL_VALUE_TYPE x; +{ + unsigned EMUSHORT f[NE], g[NE]; + REAL_VALUE_TYPE r; + long l; + + GET_REAL (&x, g); +#ifdef NANS + if (eisnan (g)) + return (x); +#endif + eifrac (g, &l, f); + ltoe (&l, g); + PUT_REAL (g, &r); + return (r); +} + + +/* Truncate REAL_VALUE_TYPE toward zero to unsigned HOST_WIDE_INT + * implements REAL_VALUE_UNSIGNED_RNDZINT (x) (etruncui (x)) + */ +REAL_VALUE_TYPE +etruncui (x) + REAL_VALUE_TYPE x; +{ + unsigned EMUSHORT f[NE], g[NE]; + REAL_VALUE_TYPE r; + unsigned long l; + + GET_REAL (&x, g); +#ifdef NANS + if (eisnan (g)) + return (x); +#endif + euifrac (g, &l, f); + ultoe (&l, g); + PUT_REAL (g, &r); + return (r); +} + + +/* This is the REAL_VALUE_ATOF function. + * It converts a decimal string to binary, rounding off + * as indicated by the machine_mode argument. Then it + * promotes the rounded value to REAL_VALUE_TYPE. + */ +REAL_VALUE_TYPE +ereal_atof (s, t) + char *s; + enum machine_mode t; +{ + unsigned EMUSHORT tem[NE], e[NE]; + REAL_VALUE_TYPE r; + + switch (t) + { + case SFmode: + asctoe24 (s, tem); + e24toe (tem, e); + break; + case DFmode: + asctoe53 (s, tem); + e53toe (tem, e); + break; + case XFmode: + asctoe64 (s, tem); + e64toe (tem, e); + break; + default: + asctoe (s, e); + } + PUT_REAL (e, &r); + return (r); +} + + +/* Expansion of REAL_NEGATE. + */ +REAL_VALUE_TYPE +ereal_negate (x) + REAL_VALUE_TYPE x; +{ + unsigned EMUSHORT e[NE]; + REAL_VALUE_TYPE r; + + GET_REAL (&x, e); +#ifdef NANS + if (eisnan (e)) + return (x); +#endif + eneg (e); + PUT_REAL (e, &r); + return (r); +} + + +/* Round real to int + * implements REAL_VALUE_FIX (x) (eroundi (x)) + * The type of rounding is left unspecified by real.h. + * It is implemented here as round to nearest (add .5 and chop). + */ +int +eroundi (x) + REAL_VALUE_TYPE x; +{ + unsigned EMUSHORT f[NE], g[NE]; + EMULONG l; + + GET_REAL (&x, f); +#ifdef NANS + if (eisnan (f)) + { + warning ("conversion from NaN to int"); + return (-1); + } +#endif + eround (f, g); + eifrac (g, &l, f); + return ((int) l); +} + +/* Round real to nearest unsigned int + * implements REAL_VALUE_UNSIGNED_FIX (x) ((unsigned int) eroundi (x)) + * Negative input returns zero. + * The type of rounding is left unspecified by real.h. + * It is implemented here as round to nearest (add .5 and chop). + */ +unsigned int +eroundui (x) + REAL_VALUE_TYPE x; +{ + unsigned EMUSHORT f[NE], g[NE]; + unsigned EMULONG l; + + GET_REAL (&x, f); +#ifdef NANS + if (eisnan (f)) + { + warning ("conversion from NaN to unsigned int"); + return (-1); + } +#endif + eround (f, g); + euifrac (g, &l, f); + return ((unsigned int)l); +} + + +/* REAL_VALUE_FROM_INT macro. + */ +void +ereal_from_int (d, i, j) + REAL_VALUE_TYPE *d; + long i, j; +{ + unsigned EMUSHORT df[NE], dg[NE]; + long low, high; + int sign; + + sign = 0; + low = i; + if ((high = j) < 0) + { + sign = 1; + /* complement and add 1 */ + high = ~high; + if (low) + low = -low; + else + high += 1; + } + eldexp (eone, HOST_BITS_PER_LONG, df); + ultoe (&high, dg); + emul (dg, df, dg); + ultoe (&low, df); + eadd (df, dg, dg); + if (sign) + eneg (dg); + PUT_REAL (dg, d); +} + + +/* REAL_VALUE_FROM_UNSIGNED_INT macro. + */ +void +ereal_from_uint (d, i, j) + REAL_VALUE_TYPE *d; + unsigned long i, j; +{ + unsigned EMUSHORT df[NE], dg[NE]; + unsigned long low, high; + + low = i; + high = j; + eldexp (eone, HOST_BITS_PER_LONG, df); + ultoe (&high, dg); + emul (dg, df, dg); + ultoe (&low, df); + eadd (df, dg, dg); + PUT_REAL (dg, d); +} + + +/* REAL_VALUE_TO_INT macro + */ +void +ereal_to_int (low, high, rr) + long *low, *high; + REAL_VALUE_TYPE rr; +{ + unsigned EMUSHORT d[NE], df[NE], dg[NE], dh[NE]; + int s; + + GET_REAL (&rr, d); +#ifdef NANS + if (eisnan (d)) + { + warning ("conversion from NaN to int"); + *low = -1; + *high = -1; + return; + } +#endif + /* convert positive value */ + s = 0; + if (eisneg (d)) + { + eneg (d); + s = 1; + } + eldexp (eone, HOST_BITS_PER_LONG, df); + ediv (df, d, dg); /* dg = d / 2^32 is the high word */ + euifrac (dg, high, dh); + emul (df, dh, dg); /* fractional part is the low word */ + euifrac (dg, low, dh); + if (s) + { + /* complement and add 1 */ + *high = ~(*high); + if (*low) + *low = -(*low); + else + *high += 1; + } +} + + +/* REAL_VALUE_LDEXP macro. + */ +REAL_VALUE_TYPE +ereal_ldexp (x, n) + REAL_VALUE_TYPE x; + int n; +{ + unsigned EMUSHORT e[NE], y[NE]; + REAL_VALUE_TYPE r; + + GET_REAL (&x, e); +#ifdef NANS + if (eisnan (e)) + return (x); +#endif + eldexp (e, n, y); + PUT_REAL (y, &r); + return (r); +} + +/* These routines are conditionally compiled because functions + * of the same names may be defined in fold-const.c. */ +#ifdef REAL_ARITHMETIC + +/* Check for infinity in a REAL_VALUE_TYPE. */ +int +target_isinf (x) + REAL_VALUE_TYPE x; +{ + unsigned EMUSHORT e[NE]; + +#ifdef INFINITY + GET_REAL (&x, e); + return (eisinf (e)); +#else + return 0; +#endif +} + + +/* Check whether a REAL_VALUE_TYPE item is a NaN. */ + +int +target_isnan (x) + REAL_VALUE_TYPE x; +{ + unsigned EMUSHORT e[NE]; + +#ifdef NANS + GET_REAL (&x, e); + return (eisnan (e)); +#else + return (0); +#endif +} + + +/* Check for a negative REAL_VALUE_TYPE number. + * this means strictly less than zero, not -0. + */ + +int +target_negative (x) + REAL_VALUE_TYPE x; +{ + unsigned EMUSHORT e[NE]; + + GET_REAL (&x, e); + if (ecmp (e, ezero) == -1) + return (1); + return (0); +} + +/* Expansion of REAL_VALUE_TRUNCATE. + * The result is in floating point, rounded to nearest or even. + */ +REAL_VALUE_TYPE +real_value_truncate (mode, arg) + enum machine_mode mode; + REAL_VALUE_TYPE arg; +{ + unsigned EMUSHORT e[NE], t[NE]; + REAL_VALUE_TYPE r; + + GET_REAL (&arg, e); +#ifdef NANS + if (eisnan (e)) + return (arg); +#endif + eclear (t); + switch (mode) + { + case XFmode: + etoe64 (e, t); + e64toe (t, t); + break; + + case DFmode: + etoe53 (e, t); + e53toe (t, t); + break; + + case SFmode: + etoe24 (e, t); + e24toe (t, t); + break; + + case SImode: + r = etrunci (e); + return (r); + + default: + abort (); + } + PUT_REAL (t, &r); + return (r); +} + +#endif /* REAL_ARITHMETIC defined */ + +/* Target values are arrays of host longs. A long is guaranteed + to be at least 32 bits wide. */ +void +etarldouble (r, l) + REAL_VALUE_TYPE r; + long l[]; +{ + unsigned EMUSHORT e[NE]; + + GET_REAL (&r, e); + etoe64 (e, e); + endian (e, l, XFmode); +} + +void +etardouble (r, l) + REAL_VALUE_TYPE r; + long l[]; +{ + unsigned EMUSHORT e[NE]; + + GET_REAL (&r, e); + etoe53 (e, e); + endian (e, l, DFmode); +} + +long +etarsingle (r) + REAL_VALUE_TYPE r; +{ + unsigned EMUSHORT e[NE]; + unsigned long l; + + GET_REAL (&r, e); + etoe24 (e, e); + endian (e, &l, SFmode); + return ((long) l); +} + +void +ereal_to_decimal (x, s) + REAL_VALUE_TYPE x; + char *s; +{ + unsigned EMUSHORT e[NE]; + + GET_REAL (&x, e); + etoasc (e, s, 20); +} + +int +ereal_cmp (x, y) + REAL_VALUE_TYPE x, y; +{ + unsigned EMUSHORT ex[NE], ey[NE]; + + GET_REAL (&x, ex); + GET_REAL (&y, ey); + return (ecmp (ex, ey)); +} + +int +ereal_isneg (x) + REAL_VALUE_TYPE x; +{ + unsigned EMUSHORT ex[NE]; + + GET_REAL (&x, ex); + return (eisneg (ex)); +} + +/* End of REAL_ARITHMETIC interface */ + +/* ieee.c + * + * Extended precision IEEE binary floating point arithmetic routines + * + * Numbers are stored in C language as arrays of 16-bit unsigned + * short integers. The arguments of the routines are pointers to + * the arrays. + * + * + * External e type data structure, simulates Intel 8087 chip + * temporary real format but possibly with a larger significand: + * + * NE-1 significand words (least significant word first, + * most significant bit is normally set) + * exponent (value = EXONE for 1.0, + * top bit is the sign) + * + * + * Internal data structure of a number (a "word" is 16 bits): + * + * ei[0] sign word (0 for positive, 0xffff for negative) + * ei[1] biased exponent (value = EXONE for the number 1.0) + * ei[2] high guard word (always zero after normalization) + * ei[3] + * to ei[NI-2] significand (NI-4 significand words, + * most significant word first, + * most significant bit is set) + * ei[NI-1] low guard word (0x8000 bit is rounding place) + * + * + * + * Routines for external format numbers + * + * asctoe (string, e) ASCII string to extended double e type + * asctoe64 (string, &d) ASCII string to long double + * asctoe53 (string, &d) ASCII string to double + * asctoe24 (string, &f) ASCII string to single + * asctoeg (string, e, prec) ASCII string to specified precision + * e24toe (&f, e) IEEE single precision to e type + * e53toe (&d, e) IEEE double precision to e type + * e64toe (&d, e) IEEE long double precision to e type + * eabs (e) absolute value + * eadd (a, b, c) c = b + a + * eclear (e) e = 0 + * ecmp (a, b) Returns 1 if a > b, 0 if a == b, + * -1 if a < b, -2 if either a or b is a NaN. + * ediv (a, b, c) c = b / a + * efloor (a, b) truncate to integer, toward -infinity + * efrexp (a, exp, s) extract exponent and significand + * eifrac (e, &l, frac) e to long integer and e type fraction + * euifrac (e, &l, frac) e to unsigned long integer and e type fraction + * einfin (e) set e to infinity, leaving its sign alone + * eldexp (a, n, b) multiply by 2**n + * emov (a, b) b = a + * emul (a, b, c) c = b * a + * eneg (e) e = -e + * eround (a, b) b = nearest integer value to a + * esub (a, b, c) c = b - a + * e24toasc (&f, str, n) single to ASCII string, n digits after decimal + * e53toasc (&d, str, n) double to ASCII string, n digits after decimal + * e64toasc (&d, str, n) long double to ASCII string + * etoasc (e, str, n) e to ASCII string, n digits after decimal + * etoe24 (e, &f) convert e type to IEEE single precision + * etoe53 (e, &d) convert e type to IEEE double precision + * etoe64 (e, &d) convert e type to IEEE long double precision + * ltoe (&l, e) long (32 bit) integer to e type + * ultoe (&l, e) unsigned long (32 bit) integer to e type + * eisneg (e) 1 if sign bit of e != 0, else 0 + * eisinf (e) 1 if e has maximum exponent (non-IEEE) + * or is infinite (IEEE) + * eisnan (e) 1 if e is a NaN + * + * + * Routines for internal format numbers + * + * eaddm (ai, bi) add significands, bi = bi + ai + * ecleaz (ei) ei = 0 + * ecleazs (ei) set ei = 0 but leave its sign alone + * ecmpm (ai, bi) compare significands, return 1, 0, or -1 + * edivm (ai, bi) divide significands, bi = bi / ai + * emdnorm (ai,l,s,exp) normalize and round off + * emovi (a, ai) convert external a to internal ai + * emovo (ai, a) convert internal ai to external a + * emovz (ai, bi) bi = ai, low guard word of bi = 0 + * emulm (ai, bi) multiply significands, bi = bi * ai + * enormlz (ei) left-justify the significand + * eshdn1 (ai) shift significand and guards down 1 bit + * eshdn8 (ai) shift down 8 bits + * eshdn6 (ai) shift down 16 bits + * eshift (ai, n) shift ai n bits up (or down if n < 0) + * eshup1 (ai) shift significand and guards up 1 bit + * eshup8 (ai) shift up 8 bits + * eshup6 (ai) shift up 16 bits + * esubm (ai, bi) subtract significands, bi = bi - ai + * eiisinf (ai) 1 if infinite + * eiisnan (ai) 1 if a NaN + * einan (ai) set ai = NaN + * eiinfin (ai) set ai = infinity + * + * + * The result is always normalized and rounded to NI-4 word precision + * after each arithmetic operation. + * + * Exception flags are NOT fully supported. + * + * Signaling NaN's are NOT supported; they are treated the same + * as quiet NaN's. + * + * Define INFINITY for support of infinity; otherwise a + * saturation arithmetic is implemented. + * + * Define NANS for support of Not-a-Number items; otherwise the + * arithmetic will never produce a NaN output, and might be confused + * by a NaN input. + * If NaN's are supported, the output of `ecmp (a,b)' is -2 if + * either a or b is a NaN. This means asking `if (ecmp (a,b) < 0)' + * may not be legitimate. Use `if (ecmp (a,b) == -1)' for `less than' + * if in doubt. + * + * Denormals are always supported here where appropriate (e.g., not + * for conversion to DEC numbers). + * + */ + + +/* mconf.h + * + * Common include file for math routines + * + * + * + * SYNOPSIS: + * + * #include "mconf.h" + * + * + * + * DESCRIPTION: + * + * This file contains definitions for error codes that are + * passed to the common error handling routine mtherr + * (which see). + * + * The file also includes a conditional assembly definition + * for the type of computer arithmetic (Intel IEEE, DEC, Motorola + * IEEE, or UNKnown). + * + * For Digital Equipment PDP-11 and VAX computers, certain + * IBM systems, and others that use numbers with a 56-bit + * significand, the symbol DEC should be defined. In this + * mode, most floating point constants are given as arrays + * of octal integers to eliminate decimal to binary conversion + * errors that might be introduced by the compiler. + * + * For computers, such as IBM PC, that follow the IEEE + * Standard for Binary Floating Point Arithmetic (ANSI/IEEE + * Std 754-1985), the symbol IBMPC or MIEEE should be defined. + * These numbers have 53-bit significands. In this mode, constants + * are provided as arrays of hexadecimal 16 bit integers. + * + * To accommodate other types of computer arithmetic, all + * constants are also provided in a normal decimal radix + * which one can hope are correctly converted to a suitable + * format by the available C language compiler. To invoke + * this mode, the symbol UNK is defined. + * + * An important difference among these modes is a predefined + * set of machine arithmetic constants for each. The numbers + * MACHEP (the machine roundoff error), MAXNUM (largest number + * represented), and several other parameters are preset by + * the configuration symbol. Check the file const.c to + * ensure that these values are correct for your computer. + * + * For ANSI C compatibility, define ANSIC equal to 1. Currently + * this affects only the atan2 function and others that use it. + */ + +/* Constant definitions for math error conditions. */ + +#define DOMAIN 1 /* argument domain error */ +#define SING 2 /* argument singularity */ +#define OVERFLOW 3 /* overflow range error */ +#define UNDERFLOW 4 /* underflow range error */ +#define TLOSS 5 /* total loss of precision */ +#define PLOSS 6 /* partial loss of precision */ +#define INVALID 7 /* NaN-producing operation */ + +/* e type constants used by high precision check routines */ + +/*include "ehead.h"*/ +/* 0.0 */ +unsigned EMUSHORT ezero[NE] = +{ + 0, 0000000, 0000000, 0000000, 0000000, 0000000,}; +extern unsigned EMUSHORT ezero[]; + +/* 5.0E-1 */ +unsigned EMUSHORT ehalf[NE] = +{ + 0, 0000000, 0000000, 0000000, 0100000, 0x3ffe,}; +extern unsigned EMUSHORT ehalf[]; + +/* 1.0E0 */ +unsigned EMUSHORT eone[NE] = +{ + 0, 0000000, 0000000, 0000000, 0100000, 0x3fff,}; +extern unsigned EMUSHORT eone[]; + +/* 2.0E0 */ +unsigned EMUSHORT etwo[NE] = +{ + 0, 0000000, 0000000, 0000000, 0100000, 0040000,}; +extern unsigned EMUSHORT etwo[]; + +/* 3.2E1 */ +unsigned EMUSHORT e32[NE] = +{ + 0, 0000000, 0000000, 0000000, 0100000, 0040004,}; +extern unsigned EMUSHORT e32[]; + +/* 6.93147180559945309417232121458176568075500134360255E-1 */ +unsigned EMUSHORT elog2[NE] = +{ + 0xc9e4, 0x79ab, 0150717, 0013767, 0130562, 0x3ffe,}; +extern unsigned EMUSHORT elog2[]; + +/* 1.41421356237309504880168872420969807856967187537695E0 */ +unsigned EMUSHORT esqrt2[NE] = +{ + 0x597e, 0x6484, 0174736, 0171463, 0132404, 0x3fff,}; +extern unsigned EMUSHORT esqrt2[]; + +/* 2/sqrt (PI) = + * 1.12837916709551257389615890312154517168810125865800E0 */ +unsigned EMUSHORT eoneopi[NE] = +{ + 0x71d5, 0x688d, 0012333, 0135202, 0110156, 0x3fff,}; +extern unsigned EMUSHORT eoneopi[]; + +/* 3.14159265358979323846264338327950288419716939937511E0 */ +unsigned EMUSHORT epi[NE] = +{ + 0xc4c6, 0xc234, 0020550, 0155242, 0144417, 0040000,}; +extern unsigned EMUSHORT epi[]; + +/* 5.7721566490153286060651209008240243104215933593992E-1 */ +unsigned EMUSHORT eeul[NE] = +{ + 0xd1be, 0xc7a4, 0076660, 0063743, 0111704, 0x3ffe,}; +extern unsigned EMUSHORT eeul[]; + +/* +include "ehead.h" +include "mconf.h" +*/ + + + +/* Control register for rounding precision. + * This can be set to 80 (if NE=6), 64, 56, 53, or 24 bits. + */ +int rndprc = NBITS; +extern int rndprc; + +void eaddm (), esubm (), emdnorm (), asctoeg (); +static void toe24 (), toe53 (), toe64 (); +void eremain (), einit (), eiremain (); +int ecmpm (), edivm (), emulm (); +void emovi (), emovo (), emovz (), ecleaz (), ecleazs (), eadd1 (); +void etodec (), todec (), dectoe (); + + + + +void +einit () +{ +} + +/* +; Clear out entire external format number. +; +; unsigned EMUSHORT x[]; +; eclear (x); +*/ + +void +eclear (x) + register unsigned EMUSHORT *x; +{ + register int i; + + for (i = 0; i < NE; i++) + *x++ = 0; +} + + + +/* Move external format number from a to b. + * + * emov (a, b); + */ + +void +emov (a, b) + register unsigned EMUSHORT *a, *b; +{ + register int i; + + for (i = 0; i < NE; i++) + *b++ = *a++; +} + + +/* +; Absolute value of external format number +; +; EMUSHORT x[NE]; +; eabs (x); +*/ + +void +eabs (x) + unsigned EMUSHORT x[]; /* x is the memory address of a short */ +{ + + x[NE - 1] &= 0x7fff; /* sign is top bit of last word of external format */ +} + + + + +/* +; Negate external format number +; +; unsigned EMUSHORT x[NE]; +; eneg (x); +*/ + +void +eneg (x) + unsigned EMUSHORT x[]; +{ + +#ifdef NANS + if (eisnan (x)) + return; +#endif + x[NE - 1] ^= 0x8000; /* Toggle the sign bit */ +} + + + +/* Return 1 if external format number is negative, + * else return zero, including when it is a NaN. + */ +int +eisneg (x) + unsigned EMUSHORT x[]; +{ + +#ifdef NANS + if (eisnan (x)) + return (0); +#endif + if (x[NE - 1] & 0x8000) + return (1); + else + return (0); +} + + +/* Return 1 if external format number is infinity. + * else return zero. + */ +int +eisinf (x) + unsigned EMUSHORT x[]; +{ + +#ifdef NANS + if (eisnan (x)) + return (0); +#endif + if ((x[NE - 1] & 0x7fff) == 0x7fff) + return (1); + else + return (0); +} + + +/* Check if e-type number is not a number. + The bit pattern is one that we defined, so we know for sure how to + detect it. */ + +int +eisnan (x) + unsigned EMUSHORT x[]; +{ + +#ifdef NANS + int i; +/* NaN has maximum exponent */ + if ((x[NE - 1] & 0x7fff) != 0x7fff) + return (0); +/* ... and non-zero significand field. */ + for (i = 0; i < NE - 1; i++) + { + if (*x++ != 0) + return (1); + } +#endif + return (0); +} + +/* Fill external format number with infinity pattern (IEEE) + or largest possible number (non-IEEE). + Before calling einfin, you should either call eclear + or set up the sign bit by hand. */ + +void +einfin (x) + register unsigned EMUSHORT *x; +{ + register int i; + +#ifdef INFINITY + for (i = 0; i < NE - 1; i++) + *x++ = 0; + *x |= 32767; +#else + for (i = 0; i < NE - 1; i++) + *x++ = 0xffff; + *x |= 32766; + if (rndprc < NBITS) + { + if (rndprc == 64) + { + *(x - 5) = 0; + } + if (rndprc == 53) + { + *(x - 4) = 0xf800; + } + else + { + *(x - 4) = 0; + *(x - 3) = 0; + *(x - 2) = 0xff00; + } + } +#endif +} + + +/* Output an e-type NaN. + This generates Intel's quiet NaN pattern for extended real. + The exponent is 7fff, the leading mantissa word is c000. */ + +void +enan (x) + register unsigned EMUSHORT *x; +{ + register int i; + + for (i = 0; i < NE - 2; i++) + *x++ = 0; + *x++ = 0xc000; + *x = 0x7fff; +} + + +/* Move in external format number, + * converting it to internal format. + */ +void +emovi (a, b) + unsigned EMUSHORT *a, *b; +{ + register unsigned EMUSHORT *p, *q; + int i; + + q = b; + p = a + (NE - 1); /* point to last word of external number */ + /* get the sign bit */ + if (*p & 0x8000) + *q++ = 0xffff; + else + *q++ = 0; + /* get the exponent */ + *q = *p--; + *q++ &= 0x7fff; /* delete the sign bit */ +#ifdef INFINITY + if ((*(q - 1) & 0x7fff) == 0x7fff) + { +#ifdef NANS + if (eisnan (a)) + { + *q++ = 0; + for (i = 3; i < NI; i++) + *q++ = *p--; + return; + } +#endif + for (i = 2; i < NI; i++) + *q++ = 0; + return; + } +#endif + /* clear high guard word */ + *q++ = 0; + /* move in the significand */ + for (i = 0; i < NE - 1; i++) + *q++ = *p--; + /* clear low guard word */ + *q = 0; +} + + +/* Move internal format number out, + * converting it to external format. + */ +void +emovo (a, b) + unsigned EMUSHORT *a, *b; +{ + register unsigned EMUSHORT *p, *q; + unsigned EMUSHORT i; + + p = a; + q = b + (NE - 1); /* point to output exponent */ + /* combine sign and exponent */ + i = *p++; + if (i) + *q-- = *p++ | 0x8000; + else + *q-- = *p++; +#ifdef INFINITY + if (*(p - 1) == 0x7fff) + { +#ifdef NANS + if (eiisnan (a)) + { + enan (b); + return; + } +#endif + einfin (b); + return; + } +#endif + /* skip over guard word */ + ++p; + /* move the significand */ + for (i = 0; i < NE - 1; i++) + *q-- = *p++; +} + + + + +/* Clear out internal format number. + */ + +void +ecleaz (xi) + register unsigned EMUSHORT *xi; +{ + register int i; + + for (i = 0; i < NI; i++) + *xi++ = 0; +} + + +/* same, but don't touch the sign. */ + +void +ecleazs (xi) + register unsigned EMUSHORT *xi; +{ + register int i; + + ++xi; + for (i = 0; i < NI - 1; i++) + *xi++ = 0; +} + + + +/* Move internal format number from a to b. + */ +void +emovz (a, b) + register unsigned EMUSHORT *a, *b; +{ + register int i; + + for (i = 0; i < NI - 1; i++) + *b++ = *a++; + /* clear low guard word */ + *b = 0; +} + +/* Generate internal format NaN. + The explicit pattern for this is maximum exponent and + top two significand bits set. */ + +void +einan (x) + unsigned EMUSHORT x[]; +{ + + ecleaz (x); + x[E] = 0x7fff; + x[M + 1] = 0xc000; +} + +/* Return nonzero if internal format number is a NaN. */ + +int +eiisnan (x) + unsigned EMUSHORT x[]; +{ + int i; + + if ((x[E] & 0x7fff) == 0x7fff) + { + for (i = M + 1; i < NI; i++) + { + if (x[i] != 0) + return (1); + } + } + return (0); +} + +/* Fill internal format number with infinity pattern. + This has maximum exponent and significand all zeros. */ + +void +eiinfin (x) + unsigned EMUSHORT x[]; +{ + + ecleaz (x); + x[E] = 0x7fff; +} + +/* Return nonzero if internal format number is infinite. */ + +int +eiisinf (x) + unsigned EMUSHORT x[]; +{ + +#ifdef NANS + if (eiisnan (x)) + return (0); +#endif + if ((x[E] & 0x7fff) == 0x7fff) + return (1); + return (0); +} + + +/* +; Compare significands of numbers in internal format. +; Guard words are included in the comparison. +; +; unsigned EMUSHORT a[NI], b[NI]; +; cmpm (a, b); +; +; for the significands: +; returns +1 if a > b +; 0 if a == b +; -1 if a < b +*/ +int +ecmpm (a, b) + register unsigned EMUSHORT *a, *b; +{ + int i; + + a += M; /* skip up to significand area */ + b += M; + for (i = M; i < NI; i++) + { + if (*a++ != *b++) + goto difrnt; + } + return (0); + + difrnt: + if (*(--a) > *(--b)) + return (1); + else + return (-1); +} + + +/* +; Shift significand down by 1 bit +*/ + +void +eshdn1 (x) + register unsigned EMUSHORT *x; +{ + register unsigned EMUSHORT bits; + int i; + + x += M; /* point to significand area */ + + bits = 0; + for (i = M; i < NI; i++) + { + if (*x & 1) + bits |= 1; + *x >>= 1; + if (bits & 2) + *x |= 0x8000; + bits <<= 1; + ++x; + } +} + + + +/* +; Shift significand up by 1 bit +*/ + +void +eshup1 (x) + register unsigned EMUSHORT *x; +{ + register unsigned EMUSHORT bits; + int i; + + x += NI - 1; + bits = 0; + + for (i = M; i < NI; i++) + { + if (*x & 0x8000) + bits |= 1; + *x <<= 1; + if (bits & 2) + *x |= 1; + bits <<= 1; + --x; + } +} + + + +/* +; Shift significand down by 8 bits +*/ + +void +eshdn8 (x) + register unsigned EMUSHORT *x; +{ + register unsigned EMUSHORT newbyt, oldbyt; + int i; + + x += M; + oldbyt = 0; + for (i = M; i < NI; i++) + { + newbyt = *x << 8; + *x >>= 8; + *x |= oldbyt; + oldbyt = newbyt; + ++x; + } +} + +/* +; Shift significand up by 8 bits +*/ + +void +eshup8 (x) + register unsigned EMUSHORT *x; +{ + int i; + register unsigned EMUSHORT newbyt, oldbyt; + + x += NI - 1; + oldbyt = 0; + + for (i = M; i < NI; i++) + { + newbyt = *x >> 8; + *x <<= 8; + *x |= oldbyt; + oldbyt = newbyt; + --x; + } +} + +/* +; Shift significand up by 16 bits +*/ + +void +eshup6 (x) + register unsigned EMUSHORT *x; +{ + int i; + register unsigned EMUSHORT *p; + + p = x + M; + x += M + 1; + + for (i = M; i < NI - 1; i++) + *p++ = *x++; + + *p = 0; +} + +/* +; Shift significand down by 16 bits +*/ + +void +eshdn6 (x) + register unsigned EMUSHORT *x; +{ + int i; + register unsigned EMUSHORT *p; + + x += NI - 1; + p = x + 1; + + for (i = M; i < NI - 1; i++) + *(--p) = *(--x); + + *(--p) = 0; +} + +/* +; Add significands +; x + y replaces y +*/ + +void +eaddm (x, y) + unsigned EMUSHORT *x, *y; +{ + register unsigned EMULONG a; + int i; + unsigned int carry; + + x += NI - 1; + y += NI - 1; + carry = 0; + for (i = M; i < NI; i++) + { + a = (unsigned EMULONG) (*x) + (unsigned EMULONG) (*y) + carry; + if (a & 0x10000) + carry = 1; + else + carry = 0; + *y = (unsigned EMUSHORT) a; + --x; + --y; + } +} + +/* +; Subtract significands +; y - x replaces y +*/ + +void +esubm (x, y) + unsigned EMUSHORT *x, *y; +{ + unsigned EMULONG a; + int i; + unsigned int carry; + + x += NI - 1; + y += NI - 1; + carry = 0; + for (i = M; i < NI; i++) + { + a = (unsigned EMULONG) (*y) - (unsigned EMULONG) (*x) - carry; + if (a & 0x10000) + carry = 1; + else + carry = 0; + *y = (unsigned EMUSHORT) a; + --x; + --y; + } +} + + +/* Divide significands */ + +static unsigned EMUSHORT equot[NI]; + +int +edivm (den, num) + unsigned EMUSHORT den[], num[]; +{ + int i; + register unsigned EMUSHORT *p, *q; + unsigned EMUSHORT j; + + p = &equot[0]; + *p++ = num[0]; + *p++ = num[1]; + + for (i = M; i < NI; i++) + { + *p++ = 0; + } + + /* Use faster compare and subtraction if denominator + * has only 15 bits of significance. + */ + p = &den[M + 2]; + if (*p++ == 0) + { + for (i = M + 3; i < NI; i++) + { + if (*p++ != 0) + goto fulldiv; + } + if ((den[M + 1] & 1) != 0) + goto fulldiv; + eshdn1 (num); + eshdn1 (den); + + p = &den[M + 1]; + q = &num[M + 1]; + + for (i = 0; i < NBITS + 2; i++) + { + if (*p <= *q) + { + *q -= *p; + j = 1; + } + else + { + j = 0; + } + eshup1 (equot); + equot[NI - 2] |= j; + eshup1 (num); + } + goto divdon; + } + + /* The number of quotient bits to calculate is + * NBITS + 1 scaling guard bit + 1 roundoff bit. + */ + fulldiv: + + p = &equot[NI - 2]; + for (i = 0; i < NBITS + 2; i++) + { + if (ecmpm (den, num) <= 0) + { + esubm (den, num); + j = 1; /* quotient bit = 1 */ + } + else + j = 0; + eshup1 (equot); + *p |= j; + eshup1 (num); + } + + divdon: + + eshdn1 (equot); + eshdn1 (equot); + + /* test for nonzero remainder after roundoff bit */ + p = &num[M]; + j = 0; + for (i = M; i < NI; i++) + { + j |= *p++; + } + if (j) + j = 1; + + + for (i = 0; i < NI; i++) + num[i] = equot[i]; + return ((int) j); +} + + +/* Multiply significands */ +int +emulm (a, b) + unsigned EMUSHORT a[], b[]; +{ + unsigned EMUSHORT *p, *q; + int i, j, k; + + equot[0] = b[0]; + equot[1] = b[1]; + for (i = M; i < NI; i++) + equot[i] = 0; + + p = &a[NI - 2]; + k = NBITS; + while (*p == 0) /* significand is not supposed to be all zero */ + { + eshdn6 (a); + k -= 16; + } + if ((*p & 0xff) == 0) + { + eshdn8 (a); + k -= 8; + } + + q = &equot[NI - 1]; + j = 0; + for (i = 0; i < k; i++) + { + if (*p & 1) + eaddm (b, equot); + /* remember if there were any nonzero bits shifted out */ + if (*q & 1) + j |= 1; + eshdn1 (a); + eshdn1 (equot); + } + + for (i = 0; i < NI; i++) + b[i] = equot[i]; + + /* return flag for lost nonzero bits */ + return (j); +} + + + +/* + * Normalize and round off. + * + * The internal format number to be rounded is "s". + * Input "lost" indicates whether or not the number is exact. + * This is the so-called sticky bit. + * + * Input "subflg" indicates whether the number was obtained + * by a subtraction operation. In that case if lost is nonzero + * then the number is slightly smaller than indicated. + * + * Input "exp" is the biased exponent, which may be negative. + * the exponent field of "s" is ignored but is replaced by + * "exp" as adjusted by normalization and rounding. + * + * Input "rcntrl" is the rounding control. + */ + +static int rlast = -1; +static int rw = 0; +static unsigned EMUSHORT rmsk = 0; +static unsigned EMUSHORT rmbit = 0; +static unsigned EMUSHORT rebit = 0; +static int re = 0; +static unsigned EMUSHORT rbit[NI]; + +void +emdnorm (s, lost, subflg, exp, rcntrl) + unsigned EMUSHORT s[]; + int lost; + int subflg; + EMULONG exp; + int rcntrl; +{ + int i, j; + unsigned EMUSHORT r; + + /* Normalize */ + j = enormlz (s); + + /* a blank significand could mean either zero or infinity. */ +#ifndef INFINITY + if (j > NBITS) + { + ecleazs (s); + return; + } +#endif + exp -= j; +#ifndef INFINITY + if (exp >= 32767L) + goto overf; +#else + if ((j > NBITS) && (exp < 32767)) + { + ecleazs (s); + return; + } +#endif + if (exp < 0L) + { + if (exp > (EMULONG) (-NBITS - 1)) + { + j = (int) exp; + i = eshift (s, j); + if (i) + lost = 1; + } + else + { + ecleazs (s); + return; + } + } + /* Round off, unless told not to by rcntrl. */ + if (rcntrl == 0) + goto mdfin; + /* Set up rounding parameters if the control register changed. */ + if (rndprc != rlast) + { + ecleaz (rbit); + switch (rndprc) + { + default: + case NBITS: + rw = NI - 1; /* low guard word */ + rmsk = 0xffff; + rmbit = 0x8000; + rbit[rw - 1] = 1; + re = NI - 2; + rebit = 1; + break; + case 64: + rw = 7; + rmsk = 0xffff; + rmbit = 0x8000; + rbit[rw - 1] = 1; + re = rw - 1; + rebit = 1; + break; + /* For DEC arithmetic */ + case 56: + rw = 6; + rmsk = 0xff; + rmbit = 0x80; + rbit[rw] = 0x100; + re = rw; + rebit = 0x100; + break; + case 53: + rw = 6; + rmsk = 0x7ff; + rmbit = 0x0400; + rbit[rw] = 0x800; + re = rw; + rebit = 0x800; + break; + case 24: + rw = 4; + rmsk = 0xff; + rmbit = 0x80; + rbit[rw] = 0x100; + re = rw; + rebit = 0x100; + break; + } + rlast = rndprc; + } + + if (rndprc >= 64) + { + r = s[rw] & rmsk; + if (rndprc == 64) + { + i = rw + 1; + while (i < NI) + { + if (s[i]) + r |= 1; + s[i] = 0; + ++i; + } + } + } + else + { + if (exp <= 0) + eshdn1 (s); + r = s[rw] & rmsk; + /* These tests assume NI = 8 */ + i = rw + 1; + while (i < NI) + { + if (s[i]) + r |= 1; + s[i] = 0; + ++i; + } + /* + if (rndprc == 24) + { + if (s[5] || s[6]) + r |= 1; + s[5] = 0; + s[6] = 0; + } + */ + } + s[rw] &= ~rmsk; + if ((r & rmbit) != 0) + { + if (r == rmbit) + { + if (lost == 0) + { /* round to even */ + if ((s[re] & rebit) == 0) + goto mddone; + } + else + { + if (subflg != 0) + goto mddone; + } + } + eaddm (rbit, s); + } + mddone: + if ((rndprc < 64) && (exp <= 0)) + { + eshup1 (s); + } + if (s[2] != 0) + { /* overflow on roundoff */ + eshdn1 (s); + exp += 1; + } + mdfin: + s[NI - 1] = 0; + if (exp >= 32767L) + { +#ifndef INFINITY + overf: +#endif +#ifdef INFINITY + s[1] = 32767; + for (i = 2; i < NI - 1; i++) + s[i] = 0; + if (extra_warnings) + warning ("floating point overflow"); +#else + s[1] = 32766; + s[2] = 0; + for (i = M + 1; i < NI - 1; i++) + s[i] = 0xffff; + s[NI - 1] = 0; + if (rndprc < 64) + { + s[rw] &= ~rmsk; + if (rndprc == 24) + { + s[5] = 0; + s[6] = 0; + } + } +#endif + return; + } + if (exp < 0) + s[1] = 0; + else + s[1] = (unsigned EMUSHORT) exp; +} + + + +/* +; Subtract external format numbers. +; +; unsigned EMUSHORT a[NE], b[NE], c[NE]; +; esub (a, b, c); c = b - a +*/ + +static int subflg = 0; + +void +esub (a, b, c) + unsigned EMUSHORT *a, *b, *c; +{ + +#ifdef NANS + if (eisnan (a)) + { + emov (a, c); + return; + } + if (eisnan (b)) + { + emov (b, c); + return; + } +/* Infinity minus infinity is a NaN. + Test for subtracting infinities of the same sign. */ + if (eisinf (a) && eisinf (b) + && ((eisneg (a) ^ eisneg (b)) == 0)) + { + mtherr ("esub", INVALID); + enan (c); + return; + } +#endif + subflg = 1; + eadd1 (a, b, c); +} + + +/* +; Add. +; +; unsigned EMUSHORT a[NE], b[NE], c[NE]; +; eadd (a, b, c); c = b + a +*/ +void +eadd (a, b, c) + unsigned EMUSHORT *a, *b, *c; +{ + +#ifdef NANS +/* NaN plus anything is a NaN. */ + if (eisnan (a)) + { + emov (a, c); + return; + } + if (eisnan (b)) + { + emov (b, c); + return; + } +/* Infinity minus infinity is a NaN. + Test for adding infinities of opposite signs. */ + if (eisinf (a) && eisinf (b) + && ((eisneg (a) ^ eisneg (b)) != 0)) + { + mtherr ("esub", INVALID); + enan (c); + return; + } +#endif + subflg = 0; + eadd1 (a, b, c); +} + +void +eadd1 (a, b, c) + unsigned EMUSHORT *a, *b, *c; +{ + unsigned EMUSHORT ai[NI], bi[NI], ci[NI]; + int i, lost, j, k; + EMULONG lt, lta, ltb; + +#ifdef INFINITY + if (eisinf (a)) + { + emov (a, c); + if (subflg) + eneg (c); + return; + } + if (eisinf (b)) + { + emov (b, c); + return; + } +#endif + emovi (a, ai); + emovi (b, bi); + if (subflg) + ai[0] = ~ai[0]; + + /* compare exponents */ + lta = ai[E]; + ltb = bi[E]; + lt = lta - ltb; + if (lt > 0L) + { /* put the larger number in bi */ + emovz (bi, ci); + emovz (ai, bi); + emovz (ci, ai); + ltb = bi[E]; + lt = -lt; + } + lost = 0; + if (lt != 0L) + { + if (lt < (EMULONG) (-NBITS - 1)) + goto done; /* answer same as larger addend */ + k = (int) lt; + lost = eshift (ai, k); /* shift the smaller number down */ + } + else + { + /* exponents were the same, so must compare significands */ + i = ecmpm (ai, bi); + if (i == 0) + { /* the numbers are identical in magnitude */ + /* if different signs, result is zero */ + if (ai[0] != bi[0]) + { + eclear (c); + return; + } + /* if same sign, result is double */ + /* double denomalized tiny number */ + if ((bi[E] == 0) && ((bi[3] & 0x8000) == 0)) + { + eshup1 (bi); + goto done; + } + /* add 1 to exponent unless both are zero! */ + for (j = 1; j < NI - 1; j++) + { + if (bi[j] != 0) + { + /* This could overflow, but let emovo take care of that. */ + ltb += 1; + break; + } + } + bi[E] = (unsigned EMUSHORT) ltb; + goto done; + } + if (i > 0) + { /* put the larger number in bi */ + emovz (bi, ci); + emovz (ai, bi); + emovz (ci, ai); + } + } + if (ai[0] == bi[0]) + { + eaddm (ai, bi); + subflg = 0; + } + else + { + esubm (ai, bi); + subflg = 1; + } + emdnorm (bi, lost, subflg, ltb, 64); + + done: + emovo (bi, c); +} + + + +/* +; Divide. +; +; unsigned EMUSHORT a[NE], b[NE], c[NE]; +; ediv (a, b, c); c = b / a +*/ +void +ediv (a, b, c) + unsigned EMUSHORT *a, *b, *c; +{ + unsigned EMUSHORT ai[NI], bi[NI]; + int i; + EMULONG lt, lta, ltb; + +#ifdef NANS +/* Return any NaN input. */ + if (eisnan (a)) + { + emov (a, c); + return; + } + if (eisnan (b)) + { + emov (b, c); + return; + } +/* Zero over zero, or infinity over infinity, is a NaN. */ + if (((ecmp (a, ezero) == 0) && (ecmp (b, ezero) == 0)) + || (eisinf (a) && eisinf (b))) + { + mtherr ("ediv", INVALID); + enan (c); + return; + } +#endif +/* Infinity over anything else is infinity. */ +#ifdef INFINITY + if (eisinf (b)) + { + if (eisneg (a) ^ eisneg (b)) + *(c + (NE - 1)) = 0x8000; + else + *(c + (NE - 1)) = 0; + einfin (c); + return; + } +/* Anything else over infinity is zero. */ + if (eisinf (a)) + { + eclear (c); + return; + } +#endif + emovi (a, ai); + emovi (b, bi); + lta = ai[E]; + ltb = bi[E]; + if (bi[E] == 0) + { /* See if numerator is zero. */ + for (i = 1; i < NI - 1; i++) + { + if (bi[i] != 0) + { + ltb -= enormlz (bi); + goto dnzro1; + } + } + eclear (c); + return; + } + dnzro1: + + if (ai[E] == 0) + { /* possible divide by zero */ + for (i = 1; i < NI - 1; i++) + { + if (ai[i] != 0) + { + lta -= enormlz (ai); + goto dnzro2; + } + } + if (ai[0] == bi[0]) + *(c + (NE - 1)) = 0; + else + *(c + (NE - 1)) = 0x8000; +/* Divide by zero is not an invalid operation. + It is a divide-by-zero operation! */ + einfin (c); + mtherr ("ediv", SING); + return; + } + dnzro2: + + i = edivm (ai, bi); + /* calculate exponent */ + lt = ltb - lta + EXONE; + emdnorm (bi, i, 0, lt, 64); + /* set the sign */ + if (ai[0] == bi[0]) + bi[0] = 0; + else + bi[0] = 0Xffff; + emovo (bi, c); +} + + + +/* +; Multiply. +; +; unsigned EMUSHORT a[NE], b[NE], c[NE]; +; emul (a, b, c); c = b * a +*/ +void +emul (a, b, c) + unsigned EMUSHORT *a, *b, *c; +{ + unsigned EMUSHORT ai[NI], bi[NI]; + int i, j; + EMULONG lt, lta, ltb; + +#ifdef NANS +/* NaN times anything is the same NaN. */ + if (eisnan (a)) + { + emov (a, c); + return; + } + if (eisnan (b)) + { + emov (b, c); + return; + } +/* Zero times infinity is a NaN. */ + if ((eisinf (a) && (ecmp (b, ezero) == 0)) + || (eisinf (b) && (ecmp (a, ezero) == 0))) + { + mtherr ("emul", INVALID); + enan (c); + return; + } +#endif +/* Infinity times anything else is infinity. */ +#ifdef INFINITY + if (eisinf (a) || eisinf (b)) + { + if (eisneg (a) ^ eisneg (b)) + *(c + (NE - 1)) = 0x8000; + else + *(c + (NE - 1)) = 0; + einfin (c); + return; + } +#endif + emovi (a, ai); + emovi (b, bi); + lta = ai[E]; + ltb = bi[E]; + if (ai[E] == 0) + { + for (i = 1; i < NI - 1; i++) + { + if (ai[i] != 0) + { + lta -= enormlz (ai); + goto mnzer1; + } + } + eclear (c); + return; + } + mnzer1: + + if (bi[E] == 0) + { + for (i = 1; i < NI - 1; i++) + { + if (bi[i] != 0) + { + ltb -= enormlz (bi); + goto mnzer2; + } + } + eclear (c); + return; + } + mnzer2: + + /* Multiply significands */ + j = emulm (ai, bi); + /* calculate exponent */ + lt = lta + ltb - (EXONE - 1); + emdnorm (bi, j, 0, lt, 64); + /* calculate sign of product */ + if (ai[0] == bi[0]) + bi[0] = 0; + else + bi[0] = 0xffff; + emovo (bi, c); +} + + + + +/* +; Convert IEEE double precision to e type +; double d; +; unsigned EMUSHORT x[N+2]; +; e53toe (&d, x); +*/ +void +e53toe (pe, y) + unsigned EMUSHORT *pe, *y; +{ +#ifdef DEC + + dectoe (pe, y); /* see etodec.c */ + +#else + + register unsigned EMUSHORT r; + register unsigned EMUSHORT *e, *p; + unsigned EMUSHORT yy[NI]; + int denorm, k; + + e = pe; + denorm = 0; /* flag if denormalized number */ + ecleaz (yy); +#ifdef IBMPC + e += 3; +#endif + r = *e; + yy[0] = 0; + if (r & 0x8000) + yy[0] = 0xffff; + yy[M] = (r & 0x0f) | 0x10; + r &= ~0x800f; /* strip sign and 4 significand bits */ +#ifdef INFINITY + if (r == 0x7ff0) + { +#ifdef NANS +#ifdef IBMPC + if (((pe[3] & 0xf) != 0) || (pe[2] != 0) + || (pe[1] != 0) || (pe[0] != 0)) + { + enan (y); + return; + } +#else + if (((pe[0] & 0xf) != 0) || (pe[1] != 0) + || (pe[2] != 0) || (pe[3] != 0)) + { + enan (y); + return; + } +#endif +#endif /* NANS */ + eclear (y); + einfin (y); + if (yy[0]) + eneg (y); + return; + } +#endif /* INFINITY */ + r >>= 4; + /* If zero exponent, then the significand is denormalized. + * So, take back the understood high significand bit. */ + if (r == 0) + { + denorm = 1; + yy[M] &= ~0x10; + } + r += EXONE - 01777; + yy[E] = r; + p = &yy[M + 1]; +#ifdef IBMPC + *p++ = *(--e); + *p++ = *(--e); + *p++ = *(--e); +#endif +#ifdef MIEEE + ++e; + *p++ = *e++; + *p++ = *e++; + *p++ = *e++; +#endif + eshift (yy, -5); + if (denorm) + { /* if zero exponent, then normalize the significand */ + if ((k = enormlz (yy)) > NBITS) + ecleazs (yy); + else + yy[E] -= (unsigned EMUSHORT) (k - 1); + } + emovo (yy, y); +#endif /* not DEC */ +} + +void +e64toe (pe, y) + unsigned EMUSHORT *pe, *y; +{ + unsigned EMUSHORT yy[NI]; + unsigned EMUSHORT *e, *p, *q; + int i; + + e = pe; + p = yy; + for (i = 0; i < NE - 5; i++) + *p++ = 0; +#ifdef IBMPC + for (i = 0; i < 5; i++) + *p++ = *e++; +#endif +#ifdef DEC + for (i = 0; i < 5; i++) + *p++ = *e++; +#endif +#ifdef MIEEE + p = &yy[0] + (NE - 1); + *p-- = *e++; + ++e; + for (i = 0; i < 4; i++) + *p-- = *e++; +#endif + p = yy; + q = y; +#ifdef INFINITY + if (*p == 0x7fff) + { +#ifdef NANS +#ifdef IBMPC + for (i = 0; i < 4; i++) + { + if (pe[i] != 0) + { + enan (y); + return; + } + } +#else + for (i = 1; i <= 4; i++) + { + if (pe[i] != 0) + { + enan (y); + return; + } + } +#endif +#endif /* NANS */ + eclear (y); + einfin (y); + if (*p & 0x8000) + eneg (y); + return; + } +#endif /* INFINITY */ + for (i = 0; i < NE; i++) + *q++ = *p++; +} + + +/* +; Convert IEEE single precision to e type +; float d; +; unsigned EMUSHORT x[N+2]; +; dtox (&d, x); +*/ +void +e24toe (pe, y) + unsigned EMUSHORT *pe, *y; +{ + register unsigned EMUSHORT r; + register unsigned EMUSHORT *e, *p; + unsigned EMUSHORT yy[NI]; + int denorm, k; + + e = pe; + denorm = 0; /* flag if denormalized number */ + ecleaz (yy); +#ifdef IBMPC + e += 1; +#endif +#ifdef DEC + e += 1; +#endif + r = *e; + yy[0] = 0; + if (r & 0x8000) + yy[0] = 0xffff; + yy[M] = (r & 0x7f) | 0200; + r &= ~0x807f; /* strip sign and 7 significand bits */ +#ifdef INFINITY + if (r == 0x7f80) + { +#ifdef NANS +#ifdef MIEEE + if (((pe[0] & 0x7f) != 0) || (pe[1] != 0)) + { + enan (y); + return; + } +#else + if (((pe[1] & 0x7f) != 0) || (pe[0] != 0)) + { + enan (y); + return; + } +#endif +#endif /* NANS */ + eclear (y); + einfin (y); + if (yy[0]) + eneg (y); + return; + } +#endif /* INFINITY */ + r >>= 7; + /* If zero exponent, then the significand is denormalized. + * So, take back the understood high significand bit. */ + if (r == 0) + { + denorm = 1; + yy[M] &= ~0200; + } + r += EXONE - 0177; + yy[E] = r; + p = &yy[M + 1]; +#ifdef IBMPC + *p++ = *(--e); +#endif +#ifdef DEC + *p++ = *(--e); +#endif +#ifdef MIEEE + ++e; + *p++ = *e++; +#endif + eshift (yy, -8); + if (denorm) + { /* if zero exponent, then normalize the significand */ + if ((k = enormlz (yy)) > NBITS) + ecleazs (yy); + else + yy[E] -= (unsigned EMUSHORT) (k - 1); + } + emovo (yy, y); +} + + +void +etoe64 (x, e) + unsigned EMUSHORT *x, *e; +{ + unsigned EMUSHORT xi[NI]; + EMULONG exp; + int rndsav; + +#ifdef NANS + if (eisnan (x)) + { + make_nan (e, XFmode); + return; + } +#endif + emovi (x, xi); + /* adjust exponent for offset */ + exp = (EMULONG) xi[E]; +#ifdef INFINITY + if (eisinf (x)) + goto nonorm; +#endif + /* round off to nearest or even */ + rndsav = rndprc; + rndprc = 64; + emdnorm (xi, 0, 0, exp, 64); + rndprc = rndsav; + nonorm: + toe64 (xi, e); +} + +/* move out internal format to ieee long double */ +static void +toe64 (a, b) + unsigned EMUSHORT *a, *b; +{ + register unsigned EMUSHORT *p, *q; + unsigned EMUSHORT i; + +#ifdef NANS + if (eiisnan (a)) + { + make_nan (b, XFmode); + return; + } +#endif + p = a; +#ifdef MIEEE + q = b; +#else + q = b + 4; /* point to output exponent */ +#if LONG_DOUBLE_TYPE_SIZE == 96 + /* Clear the last two bytes of 12-byte Intel format */ + *(q+1) = 0; +#endif +#endif + + /* combine sign and exponent */ + i = *p++; +#ifdef MIEEE + if (i) + *q++ = *p++ | 0x8000; + else + *q++ = *p++; + *q++ = 0; +#else + if (i) + *q-- = *p++ | 0x8000; + else + *q-- = *p++; +#endif + /* skip over guard word */ + ++p; + /* move the significand */ +#ifdef MIEEE + for (i = 0; i < 4; i++) + *q++ = *p++; +#else + for (i = 0; i < 4; i++) + *q-- = *p++; +#endif +} + + +/* +; e type to IEEE double precision +; double d; +; unsigned EMUSHORT x[NE]; +; etoe53 (x, &d); +*/ + +#ifdef DEC + +void +etoe53 (x, e) + unsigned EMUSHORT *x, *e; +{ + etodec (x, e); /* see etodec.c */ +} + +static void +toe53 (x, y) + unsigned EMUSHORT *x, *y; +{ + todec (x, y); +} + +#else + +void +etoe53 (x, e) + unsigned EMUSHORT *x, *e; +{ + unsigned EMUSHORT xi[NI]; + EMULONG exp; + int rndsav; + +#ifdef NANS + if (eisnan (x)) + { + make_nan (e, DFmode); + return; + } +#endif + emovi (x, xi); + /* adjust exponent for offsets */ + exp = (EMULONG) xi[E] - (EXONE - 0x3ff); +#ifdef INFINITY + if (eisinf (x)) + goto nonorm; +#endif + /* round off to nearest or even */ + rndsav = rndprc; + rndprc = 53; + emdnorm (xi, 0, 0, exp, 64); + rndprc = rndsav; + nonorm: + toe53 (xi, e); +} + + +static void +toe53 (x, y) + unsigned EMUSHORT *x, *y; +{ + unsigned EMUSHORT i; + unsigned EMUSHORT *p; + +#ifdef NANS + if (eiisnan (x)) + { + make_nan (y, DFmode); + return; + } +#endif + p = &x[0]; +#ifdef IBMPC + y += 3; +#endif + *y = 0; /* output high order */ + if (*p++) + *y = 0x8000; /* output sign bit */ + + i = *p++; + if (i >= (unsigned int) 2047) + { /* Saturate at largest number less than infinity. */ +#ifdef INFINITY + *y |= 0x7ff0; +#ifdef IBMPC + *(--y) = 0; + *(--y) = 0; + *(--y) = 0; +#endif +#ifdef MIEEE + ++y; + *y++ = 0; + *y++ = 0; + *y++ = 0; +#endif +#else + *y |= (unsigned EMUSHORT) 0x7fef; +#ifdef IBMPC + *(--y) = 0xffff; + *(--y) = 0xffff; + *(--y) = 0xffff; +#endif +#ifdef MIEEE + ++y; + *y++ = 0xffff; + *y++ = 0xffff; + *y++ = 0xffff; +#endif +#endif + return; + } + if (i == 0) + { + eshift (x, 4); + } + else + { + i <<= 4; + eshift (x, 5); + } + i |= *p++ & (unsigned EMUSHORT) 0x0f; /* *p = xi[M] */ + *y |= (unsigned EMUSHORT) i; /* high order output already has sign bit set */ +#ifdef IBMPC + *(--y) = *p++; + *(--y) = *p++; + *(--y) = *p; +#endif +#ifdef MIEEE + ++y; + *y++ = *p++; + *y++ = *p++; + *y++ = *p++; +#endif +} + +#endif /* not DEC */ + + + +/* +; e type to IEEE single precision +; float d; +; unsigned EMUSHORT x[N+2]; +; xtod (x, &d); +*/ +void +etoe24 (x, e) + unsigned EMUSHORT *x, *e; +{ + EMULONG exp; + unsigned EMUSHORT xi[NI]; + int rndsav; + +#ifdef NANS + if (eisnan (x)) + { + make_nan (e, SFmode); + return; + } +#endif + emovi (x, xi); + /* adjust exponent for offsets */ + exp = (EMULONG) xi[E] - (EXONE - 0177); +#ifdef INFINITY + if (eisinf (x)) + goto nonorm; +#endif + /* round off to nearest or even */ + rndsav = rndprc; + rndprc = 24; + emdnorm (xi, 0, 0, exp, 64); + rndprc = rndsav; + nonorm: + toe24 (xi, e); +} + +static void +toe24 (x, y) + unsigned EMUSHORT *x, *y; +{ + unsigned EMUSHORT i; + unsigned EMUSHORT *p; + +#ifdef NANS + if (eiisnan (x)) + { + make_nan (y, SFmode); + return; + } +#endif + p = &x[0]; +#ifdef IBMPC + y += 1; +#endif +#ifdef DEC + y += 1; +#endif + *y = 0; /* output high order */ + if (*p++) + *y = 0x8000; /* output sign bit */ + + i = *p++; +/* Handle overflow cases. */ + if (i >= 255) + { +#ifdef INFINITY + *y |= (unsigned EMUSHORT) 0x7f80; +#ifdef IBMPC + *(--y) = 0; +#endif +#ifdef DEC + *(--y) = 0; +#endif +#ifdef MIEEE + ++y; + *y = 0; +#endif +#else /* no INFINITY */ + *y |= (unsigned EMUSHORT) 0x7f7f; +#ifdef IBMPC + *(--y) = 0xffff; +#endif +#ifdef DEC + *(--y) = 0xffff; +#endif +#ifdef MIEEE + ++y; + *y = 0xffff; +#endif +#ifdef ERANGE + errno = ERANGE; +#endif +#endif /* no INFINITY */ + return; + } + if (i == 0) + { + eshift (x, 7); + } + else + { + i <<= 7; + eshift (x, 8); + } + i |= *p++ & (unsigned EMUSHORT) 0x7f; /* *p = xi[M] */ + *y |= i; /* high order output already has sign bit set */ +#ifdef IBMPC + *(--y) = *p; +#endif +#ifdef DEC + *(--y) = *p; +#endif +#ifdef MIEEE + ++y; + *y = *p; +#endif +} + + +/* Compare two e type numbers. + * + * unsigned EMUSHORT a[NE], b[NE]; + * ecmp (a, b); + * + * returns +1 if a > b + * 0 if a == b + * -1 if a < b + * -2 if either a or b is a NaN. + */ +int +ecmp (a, b) + unsigned EMUSHORT *a, *b; +{ + unsigned EMUSHORT ai[NI], bi[NI]; + register unsigned EMUSHORT *p, *q; + register int i; + int msign; + +#ifdef NANS + if (eisnan (a) || eisnan (b)) + return (-2); +#endif + emovi (a, ai); + p = ai; + emovi (b, bi); + q = bi; + + if (*p != *q) + { /* the signs are different */ + /* -0 equals + 0 */ + for (i = 1; i < NI - 1; i++) + { + if (ai[i] != 0) + goto nzro; + if (bi[i] != 0) + goto nzro; + } + return (0); + nzro: + if (*p == 0) + return (1); + else + return (-1); + } + /* both are the same sign */ + if (*p == 0) + msign = 1; + else + msign = -1; + i = NI - 1; + do + { + if (*p++ != *q++) + { + goto diff; + } + } + while (--i > 0); + + return (0); /* equality */ + + + + diff: + + if (*(--p) > *(--q)) + return (msign); /* p is bigger */ + else + return (-msign); /* p is littler */ +} + + + + +/* Find nearest integer to x = floor (x + 0.5) + * + * unsigned EMUSHORT x[NE], y[NE] + * eround (x, y); + */ +void +eround (x, y) + unsigned EMUSHORT *x, *y; +{ + eadd (ehalf, x, y); + efloor (y, y); +} + + + + +/* +; convert long integer to e type +; +; long l; +; unsigned EMUSHORT x[NE]; +; ltoe (&l, x); +; note &l is the memory address of l +*/ +void +ltoe (lp, y) + long *lp; /* lp is the memory address of a long integer */ + unsigned EMUSHORT *y; /* y is the address of a short */ +{ + unsigned EMUSHORT yi[NI]; + unsigned long ll; + int k; + + ecleaz (yi); + if (*lp < 0) + { + /* make it positive */ + ll = (unsigned long) (-(*lp)); + yi[0] = 0xffff; /* put correct sign in the e type number */ + } + else + { + ll = (unsigned long) (*lp); + } + /* move the long integer to yi significand area */ +#if HOST_BITS_PER_LONG == 64 + yi[M] = (unsigned EMUSHORT) (ll >> 48); + yi[M + 1] = (unsigned EMUSHORT) (ll >> 32); + yi[M + 2] = (unsigned EMUSHORT) (ll >> 16); + yi[M + 3] = (unsigned EMUSHORT) ll; + yi[E] = EXONE + 47; /* exponent if normalize shift count were 0 */ +#else + yi[M] = (unsigned EMUSHORT) (ll >> 16); + yi[M + 1] = (unsigned EMUSHORT) ll; + yi[E] = EXONE + 15; /* exponent if normalize shift count were 0 */ +#endif + + if ((k = enormlz (yi)) > NBITS)/* normalize the significand */ + ecleaz (yi); /* it was zero */ + else + yi[E] -= (unsigned EMUSHORT) k;/* subtract shift count from exponent */ + emovo (yi, y); /* output the answer */ +} + +/* +; convert unsigned long integer to e type +; +; unsigned long l; +; unsigned EMUSHORT x[NE]; +; ltox (&l, x); +; note &l is the memory address of l +*/ +void +ultoe (lp, y) + unsigned long *lp; /* lp is the memory address of a long integer */ + unsigned EMUSHORT *y; /* y is the address of a short */ +{ + unsigned EMUSHORT yi[NI]; + unsigned long ll; + int k; + + ecleaz (yi); + ll = *lp; + + /* move the long integer to ayi significand area */ +#if HOST_BITS_PER_LONG == 64 + yi[M] = (unsigned EMUSHORT) (ll >> 48); + yi[M + 1] = (unsigned EMUSHORT) (ll >> 32); + yi[M + 2] = (unsigned EMUSHORT) (ll >> 16); + yi[M + 3] = (unsigned EMUSHORT) ll; + yi[E] = EXONE + 47; /* exponent if normalize shift count were 0 */ +#else + yi[M] = (unsigned EMUSHORT) (ll >> 16); + yi[M + 1] = (unsigned EMUSHORT) ll; + yi[E] = EXONE + 15; /* exponent if normalize shift count were 0 */ +#endif + + if ((k = enormlz (yi)) > NBITS)/* normalize the significand */ + ecleaz (yi); /* it was zero */ + else + yi[E] -= (unsigned EMUSHORT) k; /* subtract shift count from exponent */ + emovo (yi, y); /* output the answer */ +} + + +/* +; Find long integer and fractional parts + +; long i; +; unsigned EMUSHORT x[NE], frac[NE]; +; xifrac (x, &i, frac); + + The integer output has the sign of the input. The fraction is +the positive fractional part of abs (x). +*/ +void +eifrac (x, i, frac) + unsigned EMUSHORT *x; + long *i; + unsigned EMUSHORT *frac; +{ + unsigned EMUSHORT xi[NI]; + int j, k; + unsigned long ll; + + emovi (x, xi); + k = (int) xi[E] - (EXONE - 1); + if (k <= 0) + { + /* if exponent <= 0, integer = 0 and real output is fraction */ + *i = 0L; + emovo (xi, frac); + return; + } + if (k > (HOST_BITS_PER_LONG - 1)) + { + /* long integer overflow: output large integer + and correct fraction */ + if (xi[0]) + *i = ((unsigned long) 1) << (HOST_BITS_PER_LONG - 1); + else + *i = (((unsigned long) 1) << (HOST_BITS_PER_LONG - 1)) - 1; + eshift (xi, k); + if (extra_warnings) + warning ("overflow on truncation to integer"); + } + else if (k > 16) + { + /* Shift more than 16 bits: first shift up k-16 mod 16, + then shift up by 16's. */ + j = k - ((k >> 4) << 4); + eshift (xi, j); + ll = xi[M]; + k -= j; + do + { + eshup6 (xi); + ll = (ll << 16) | xi[M]; + } + while ((k -= 16) > 0); + *i = ll; + if (xi[0]) + *i = -(*i); + } + else + { + /* shift not more than 16 bits */ + eshift (xi, k); + *i = (long) xi[M] & 0xffff; + if (xi[0]) + *i = -(*i); + } + xi[0] = 0; + xi[E] = EXONE - 1; + xi[M] = 0; + if ((k = enormlz (xi)) > NBITS) + ecleaz (xi); + else + xi[E] -= (unsigned EMUSHORT) k; + + emovo (xi, frac); +} + + +/* Find unsigned long integer and fractional parts. + A negative e type input yields integer output = 0 + but correct fraction. */ + +void +euifrac (x, i, frac) + unsigned EMUSHORT *x; + unsigned long *i; + unsigned EMUSHORT *frac; +{ + unsigned long ll; + unsigned EMUSHORT xi[NI]; + int j, k; + + emovi (x, xi); + k = (int) xi[E] - (EXONE - 1); + if (k <= 0) + { + /* if exponent <= 0, integer = 0 and argument is fraction */ + *i = 0L; + emovo (xi, frac); + return; + } + if (k > HOST_BITS_PER_LONG) + { + /* Long integer overflow: output large integer + and correct fraction. + Note, the BSD microvax compiler says that ~(0UL) + is a syntax error. */ + *i = ~(0L); + eshift (xi, k); + if (extra_warnings) + warning ("overflow on truncation to unsigned integer"); + } + else if (k > 16) + { + /* Shift more than 16 bits: first shift up k-16 mod 16, + then shift up by 16's. */ + j = k - ((k >> 4) << 4); + eshift (xi, j); + ll = xi[M]; + k -= j; + do + { + eshup6 (xi); + ll = (ll << 16) | xi[M]; + } + while ((k -= 16) > 0); + *i = ll; + } + else + { + /* shift not more than 16 bits */ + eshift (xi, k); + *i = (long) xi[M] & 0xffff; + } + + if (xi[0]) /* A negative value yields unsigned integer 0. */ + *i = 0L; + xi[0] = 0; + xi[E] = EXONE - 1; + xi[M] = 0; + if ((k = enormlz (xi)) > NBITS) + ecleaz (xi); + else + xi[E] -= (unsigned EMUSHORT) k; + + emovo (xi, frac); +} + + + +/* +; Shift significand +; +; Shifts significand area up or down by the number of bits +; given by the variable sc. +*/ +int +eshift (x, sc) + unsigned EMUSHORT *x; + int sc; +{ + unsigned EMUSHORT lost; + unsigned EMUSHORT *p; + + if (sc == 0) + return (0); + + lost = 0; + p = x + NI - 1; + + if (sc < 0) + { + sc = -sc; + while (sc >= 16) + { + lost |= *p; /* remember lost bits */ + eshdn6 (x); + sc -= 16; + } + + while (sc >= 8) + { + lost |= *p & 0xff; + eshdn8 (x); + sc -= 8; + } + + while (sc > 0) + { + lost |= *p & 1; + eshdn1 (x); + sc -= 1; + } + } + else + { + while (sc >= 16) + { + eshup6 (x); + sc -= 16; + } + + while (sc >= 8) + { + eshup8 (x); + sc -= 8; + } + + while (sc > 0) + { + eshup1 (x); + sc -= 1; + } + } + if (lost) + lost = 1; + return ((int) lost); +} + + + +/* +; normalize +; +; Shift normalizes the significand area pointed to by argument +; shift count (up = positive) is returned. +*/ +int +enormlz (x) + unsigned EMUSHORT x[]; +{ + register unsigned EMUSHORT *p; + int sc; + + sc = 0; + p = &x[M]; + if (*p != 0) + goto normdn; + ++p; + if (*p & 0x8000) + return (0); /* already normalized */ + while (*p == 0) + { + eshup6 (x); + sc += 16; + /* With guard word, there are NBITS+16 bits available. + * return true if all are zero. + */ + if (sc > NBITS) + return (sc); + } + /* see if high byte is zero */ + while ((*p & 0xff00) == 0) + { + eshup8 (x); + sc += 8; + } + /* now shift 1 bit at a time */ + while ((*p & 0x8000) == 0) + { + eshup1 (x); + sc += 1; + if (sc > NBITS) + { + mtherr ("enormlz", UNDERFLOW); + return (sc); + } + } + return (sc); + + /* Normalize by shifting down out of the high guard word + of the significand */ + normdn: + + if (*p & 0xff00) + { + eshdn8 (x); + sc -= 8; + } + while (*p != 0) + { + eshdn1 (x); + sc -= 1; + + if (sc < -NBITS) + { + mtherr ("enormlz", OVERFLOW); + return (sc); + } + } + return (sc); +} + + + + +/* Convert e type number to decimal format ASCII string. + * The constants are for 64 bit precision. + */ + +#define NTEN 12 +#define MAXP 4096 + +static unsigned EMUSHORT etens[NTEN + 1][NE] = +{ + {0xc94c, 0x979a, 0x8a20, 0x5202, 0xc460, 0x7525,}, /* 10**4096 */ + {0xa74d, 0x5de4, 0xc53d, 0x3b5d, 0x9e8b, 0x5a92,}, /* 10**2048 */ + {0x650d, 0x0c17, 0x8175, 0x7586, 0xc976, 0x4d48,}, + {0xcc65, 0x91c6, 0xa60e, 0xa0ae, 0xe319, 0x46a3,}, + {0xddbc, 0xde8d, 0x9df9, 0xebfb, 0xaa7e, 0x4351,}, + {0xc66f, 0x8cdf, 0x80e9, 0x47c9, 0x93ba, 0x41a8,}, + {0x3cbf, 0xa6d5, 0xffcf, 0x1f49, 0xc278, 0x40d3,}, + {0xf020, 0xb59d, 0x2b70, 0xada8, 0x9dc5, 0x4069,}, + {0x0000, 0x0000, 0x0400, 0xc9bf, 0x8e1b, 0x4034,}, + {0x0000, 0x0000, 0x0000, 0x2000, 0xbebc, 0x4019,}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x9c40, 0x400c,}, + {0x0000, 0x0000, 0x0000, 0x0000, 0xc800, 0x4005,}, + {0x0000, 0x0000, 0x0000, 0x0000, 0xa000, 0x4002,}, /* 10**1 */ +}; + +static unsigned EMUSHORT emtens[NTEN + 1][NE] = +{ + {0x2de4, 0x9fde, 0xd2ce, 0x04c8, 0xa6dd, 0x0ad8,}, /* 10**-4096 */ + {0x4925, 0x2de4, 0x3436, 0x534f, 0xceae, 0x256b,}, /* 10**-2048 */ + {0x87a6, 0xc0bd, 0xda57, 0x82a5, 0xa2a6, 0x32b5,}, + {0x7133, 0xd21c, 0xdb23, 0xee32, 0x9049, 0x395a,}, + {0xfa91, 0x1939, 0x637a, 0x4325, 0xc031, 0x3cac,}, + {0xac7d, 0xe4a0, 0x64bc, 0x467c, 0xddd0, 0x3e55,}, + {0x3f24, 0xe9a5, 0xa539, 0xea27, 0xa87f, 0x3f2a,}, + {0x67de, 0x94ba, 0x4539, 0x1ead, 0xcfb1, 0x3f94,}, + {0x4c2f, 0xe15b, 0xc44d, 0x94be, 0xe695, 0x3fc9,}, + {0xfdc2, 0xcefc, 0x8461, 0x7711, 0xabcc, 0x3fe4,}, + {0xd3c3, 0x652b, 0xe219, 0x1758, 0xd1b7, 0x3ff1,}, + {0x3d71, 0xd70a, 0x70a3, 0x0a3d, 0xa3d7, 0x3ff8,}, + {0xcccd, 0xcccc, 0xcccc, 0xcccc, 0xcccc, 0x3ffb,}, /* 10**-1 */ +}; + +void +e24toasc (x, string, ndigs) + unsigned EMUSHORT x[]; + char *string; + int ndigs; +{ + unsigned EMUSHORT w[NI]; + + e24toe (x, w); + etoasc (w, string, ndigs); +} + + +void +e53toasc (x, string, ndigs) + unsigned EMUSHORT x[]; + char *string; + int ndigs; +{ + unsigned EMUSHORT w[NI]; + + e53toe (x, w); + etoasc (w, string, ndigs); +} + + +void +e64toasc (x, string, ndigs) + unsigned EMUSHORT x[]; + char *string; + int ndigs; +{ + unsigned EMUSHORT w[NI]; + + e64toe (x, w); + etoasc (w, string, ndigs); +} + + +static char wstring[80]; /* working storage for ASCII output */ + +void +etoasc (x, string, ndigs) + unsigned EMUSHORT x[]; + char *string; + int ndigs; +{ + EMUSHORT digit; + unsigned EMUSHORT y[NI], t[NI], u[NI], w[NI]; + unsigned EMUSHORT *p, *r, *ten; + unsigned EMUSHORT sign; + int i, j, k, expon, rndsav; + char *s, *ss; + unsigned EMUSHORT m; + + + rndsav = rndprc; + ss = string; + s = wstring; + *ss = '\0'; + *s = '\0'; +#ifdef NANS + if (eisnan (x)) + { + sprintf (wstring, " NaN "); + goto bxit; + } +#endif + rndprc = NBITS; /* set to full precision */ + emov (x, y); /* retain external format */ + if (y[NE - 1] & 0x8000) + { + sign = 0xffff; + y[NE - 1] &= 0x7fff; + } + else + { + sign = 0; + } + expon = 0; + ten = &etens[NTEN][0]; + emov (eone, t); + /* Test for zero exponent */ + if (y[NE - 1] == 0) + { + for (k = 0; k < NE - 1; k++) + { + if (y[k] != 0) + goto tnzro; /* denormalized number */ + } + goto isone; /* legal all zeros */ + } + tnzro: + + /* Test for infinity. */ + if (y[NE - 1] == 0x7fff) + { + if (sign) + sprintf (wstring, " -Infinity "); + else + sprintf (wstring, " Infinity "); + goto bxit; + } + + /* Test for exponent nonzero but significand denormalized. + * This is an error condition. + */ + if ((y[NE - 1] != 0) && ((y[NE - 2] & 0x8000) == 0)) + { + mtherr ("etoasc", DOMAIN); + sprintf (wstring, "NaN"); + goto bxit; + } + + /* Compare to 1.0 */ + i = ecmp (eone, y); + if (i == 0) + goto isone; + + if (i == -2) + abort (); + + if (i < 0) + { /* Number is greater than 1 */ + /* Convert significand to an integer and strip trailing decimal zeros. */ + emov (y, u); + u[NE - 1] = EXONE + NBITS - 1; + + p = &etens[NTEN - 4][0]; + m = 16; + do + { + ediv (p, u, t); + efloor (t, w); + for (j = 0; j < NE - 1; j++) + { + if (t[j] != w[j]) + goto noint; + } + emov (t, u); + expon += (int) m; + noint: + p += NE; + m >>= 1; + } + while (m != 0); + + /* Rescale from integer significand */ + u[NE - 1] += y[NE - 1] - (unsigned int) (EXONE + NBITS - 1); + emov (u, y); + /* Find power of 10 */ + emov (eone, t); + m = MAXP; + p = &etens[0][0]; + /* An unordered compare result shouldn't happen here. */ + while (ecmp (ten, u) <= 0) + { + if (ecmp (p, u) <= 0) + { + ediv (p, u, u); + emul (p, t, t); + expon += (int) m; + } + m >>= 1; + if (m == 0) + break; + p += NE; + } + } + else + { /* Number is less than 1.0 */ + /* Pad significand with trailing decimal zeros. */ + if (y[NE - 1] == 0) + { + while ((y[NE - 2] & 0x8000) == 0) + { + emul (ten, y, y); + expon -= 1; + } + } + else + { + emovi (y, w); + for (i = 0; i < NDEC + 1; i++) + { + if ((w[NI - 1] & 0x7) != 0) + break; + /* multiply by 10 */ + emovz (w, u); + eshdn1 (u); + eshdn1 (u); + eaddm (w, u); + u[1] += 3; + while (u[2] != 0) + { + eshdn1 (u); + u[1] += 1; + } + if (u[NI - 1] != 0) + break; + if (eone[NE - 1] <= u[1]) + break; + emovz (u, w); + expon -= 1; + } + emovo (w, y); + } + k = -MAXP; + p = &emtens[0][0]; + r = &etens[0][0]; + emov (y, w); + emov (eone, t); + while (ecmp (eone, w) > 0) + { + if (ecmp (p, w) >= 0) + { + emul (r, w, w); + emul (r, t, t); + expon += k; + } + k /= 2; + if (k == 0) + break; + p += NE; + r += NE; + } + ediv (t, eone, t); + } + isone: + /* Find the first (leading) digit. */ + emovi (t, w); + emovz (w, t); + emovi (y, w); + emovz (w, y); + eiremain (t, y); + digit = equot[NI - 1]; + while ((digit == 0) && (ecmp (y, ezero) != 0)) + { + eshup1 (y); + emovz (y, u); + eshup1 (u); + eshup1 (u); + eaddm (u, y); + eiremain (t, y); + digit = equot[NI - 1]; + expon -= 1; + } + s = wstring; + if (sign) + *s++ = '-'; + else + *s++ = ' '; + /* Examine number of digits requested by caller. */ + if (ndigs < 0) + ndigs = 0; + if (ndigs > NDEC) + ndigs = NDEC; + if (digit == 10) + { + *s++ = '1'; + *s++ = '.'; + if (ndigs > 0) + { + *s++ = '0'; + ndigs -= 1; + } + expon += 1; + } + else + { + *s++ = (char )digit + '0'; + *s++ = '.'; + } + /* Generate digits after the decimal point. */ + for (k = 0; k <= ndigs; k++) + { + /* multiply current number by 10, without normalizing */ + eshup1 (y); + emovz (y, u); + eshup1 (u); + eshup1 (u); + eaddm (u, y); + eiremain (t, y); + *s++ = (char) equot[NI - 1] + '0'; + } + digit = equot[NI - 1]; + --s; + ss = s; + /* round off the ASCII string */ + if (digit > 4) + { + /* Test for critical rounding case in ASCII output. */ + if (digit == 5) + { + emovo (y, t); + if (ecmp (t, ezero) != 0) + goto roun; /* round to nearest */ + if ((*(s - 1) & 1) == 0) + goto doexp; /* round to even */ + } + /* Round up and propagate carry-outs */ + roun: + --s; + k = *s & 0x7f; + /* Carry out to most significant digit? */ + if (k == '.') + { + --s; + k = *s; + k += 1; + *s = (char) k; + /* Most significant digit carries to 10? */ + if (k > '9') + { + expon += 1; + *s = '1'; + } + goto doexp; + } + /* Round up and carry out from less significant digits */ + k += 1; + *s = (char) k; + if (k > '9') + { + *s = '0'; + goto roun; + } + } + doexp: + /* + if (expon >= 0) + sprintf (ss, "e+%d", expon); + else + sprintf (ss, "e%d", expon); + */ + sprintf (ss, "e%d", expon); + bxit: + rndprc = rndsav; + /* copy out the working string */ + s = string; + ss = wstring; + while (*ss == ' ') /* strip possible leading space */ + ++ss; + while ((*s++ = *ss++) != '\0') + ; +} + + + + +/* +; ASCTOQ +; ASCTOQ.MAC LATEST REV: 11 JAN 84 +; SLM, 3 JAN 78 +; +; Convert ASCII string to quadruple precision floating point +; +; Numeric input is free field decimal number +; with max of 15 digits with or without +; decimal point entered as ASCII from teletype. +; Entering E after the number followed by a second +; number causes the second number to be interpreted +; as a power of 10 to be multiplied by the first number +; (i.e., "scientific" notation). +; +; Usage: +; asctoq (string, q); +*/ + +/* ASCII to single */ +void +asctoe24 (s, y) + char *s; + unsigned EMUSHORT *y; +{ + asctoeg (s, y, 24); +} + + +/* ASCII to double */ +void +asctoe53 (s, y) + char *s; + unsigned EMUSHORT *y; +{ +#ifdef DEC + asctoeg (s, y, 56); +#else + asctoeg (s, y, 53); +#endif +} + + +/* ASCII to long double */ +void +asctoe64 (s, y) + char *s; + unsigned EMUSHORT *y; +{ + asctoeg (s, y, 64); +} + +/* ASCII to super double */ +void +asctoe (s, y) + char *s; + unsigned EMUSHORT *y; +{ + asctoeg (s, y, NBITS); +} + +/* Space to make a copy of the input string: */ +static char lstr[82]; + +void +asctoeg (ss, y, oprec) + char *ss; + unsigned EMUSHORT *y; + int oprec; +{ + unsigned EMUSHORT yy[NI], xt[NI], tt[NI]; + int esign, decflg, sgnflg, nexp, exp, prec, lost; + int k, trail, c, rndsav; + EMULONG lexp; + unsigned EMUSHORT nsign, *p; + char *sp, *s; + + /* Copy the input string. */ + s = ss; + while (*s == ' ') /* skip leading spaces */ + ++s; + sp = lstr; + for (k = 0; k < 79; k++) + { + if ((*sp++ = *s++) == '\0') + break; + } + *sp = '\0'; + s = lstr; + + rndsav = rndprc; + rndprc = NBITS; /* Set to full precision */ + lost = 0; + nsign = 0; + decflg = 0; + sgnflg = 0; + nexp = 0; + exp = 0; + prec = 0; + ecleaz (yy); + trail = 0; + + nxtcom: + k = *s - '0'; + if ((k >= 0) && (k <= 9)) + { + /* Ignore leading zeros */ + if ((prec == 0) && (decflg == 0) && (k == 0)) + goto donchr; + /* Identify and strip trailing zeros after the decimal point. */ + if ((trail == 0) && (decflg != 0)) + { + sp = s; + while ((*sp >= '0') && (*sp <= '9')) + ++sp; + /* Check for syntax error */ + c = *sp & 0x7f; + if ((c != 'e') && (c != 'E') && (c != '\0') + && (c != '\n') && (c != '\r') && (c != ' ') + && (c != ',')) + goto error; + --sp; + while (*sp == '0') + *sp-- = 'z'; + trail = 1; + if (*s == 'z') + goto donchr; + } + /* If enough digits were given to more than fill up the yy register, + * continuing until overflow into the high guard word yy[2] + * guarantees that there will be a roundoff bit at the top + * of the low guard word after normalization. + */ + if (yy[2] == 0) + { + if (decflg) + nexp += 1; /* count digits after decimal point */ + eshup1 (yy); /* multiply current number by 10 */ + emovz (yy, xt); + eshup1 (xt); + eshup1 (xt); + eaddm (xt, yy); + ecleaz (xt); + xt[NI - 2] = (unsigned EMUSHORT) k; + eaddm (xt, yy); + } + else + { + lost |= k; + } + prec += 1; + goto donchr; + } + + switch (*s) + { + case 'z': + break; + case 'E': + case 'e': + goto expnt; + case '.': /* decimal point */ + if (decflg) + goto error; + ++decflg; + break; + case '-': + nsign = 0xffff; + if (sgnflg) + goto error; + ++sgnflg; + break; + case '+': + if (sgnflg) + goto error; + ++sgnflg; + break; + case ',': + case ' ': + case '\0': + case '\n': + case '\r': + goto daldone; + case 'i': + case 'I': + goto infinite; + default: + error: +#ifdef NANS + einan (yy); +#else + mtherr ("asctoe", DOMAIN); + eclear (yy); +#endif + goto aexit; + } + donchr: + ++s; + goto nxtcom; + + /* Exponent interpretation */ + expnt: + + esign = 1; + exp = 0; + ++s; + /* check for + or - */ + if (*s == '-') + { + esign = -1; + ++s; + } + if (*s == '+') + ++s; + while ((*s >= '0') && (*s <= '9')) + { + exp *= 10; + exp += *s++ - '0'; + if (exp > 4956) + { + if (esign < 0) + goto zero; + else + goto infinite; + } + } + if (esign < 0) + exp = -exp; + if (exp > 4932) + { + infinite: + ecleaz (yy); + yy[E] = 0x7fff; /* infinity */ + goto aexit; + } + if (exp < -4956) + { + zero: + ecleaz (yy); + goto aexit; + } + + daldone: + nexp = exp - nexp; + /* Pad trailing zeros to minimize power of 10, per IEEE spec. */ + while ((nexp > 0) && (yy[2] == 0)) + { + emovz (yy, xt); + eshup1 (xt); + eshup1 (xt); + eaddm (yy, xt); + eshup1 (xt); + if (xt[2] != 0) + break; + nexp -= 1; + emovz (xt, yy); + } + if ((k = enormlz (yy)) > NBITS) + { + ecleaz (yy); + goto aexit; + } + lexp = (EXONE - 1 + NBITS) - k; + emdnorm (yy, lost, 0, lexp, 64); + /* convert to external format */ + + + /* Multiply by 10**nexp. If precision is 64 bits, + * the maximum relative error incurred in forming 10**n + * for 0 <= n <= 324 is 8.2e-20, at 10**180. + * For 0 <= n <= 999, the peak relative error is 1.4e-19 at 10**947. + * For 0 >= n >= -999, it is -1.55e-19 at 10**-435. + */ + lexp = yy[E]; + if (nexp == 0) + { + k = 0; + goto expdon; + } + esign = 1; + if (nexp < 0) + { + nexp = -nexp; + esign = -1; + if (nexp > 4096) + { /* Punt. Can't handle this without 2 divides. */ + emovi (etens[0], tt); + lexp -= tt[E]; + k = edivm (tt, yy); + lexp += EXONE; + nexp -= 4096; + } + } + p = &etens[NTEN][0]; + emov (eone, xt); + exp = 1; + do + { + if (exp & nexp) + emul (p, xt, xt); + p -= NE; + exp = exp + exp; + } + while (exp <= MAXP); + + emovi (xt, tt); + if (esign < 0) + { + lexp -= tt[E]; + k = edivm (tt, yy); + lexp += EXONE; + } + else + { + lexp += tt[E]; + k = emulm (tt, yy); + lexp -= EXONE - 1; + } + + expdon: + + /* Round and convert directly to the destination type */ + if (oprec == 53) + lexp -= EXONE - 0x3ff; + else if (oprec == 24) + lexp -= EXONE - 0177; +#ifdef DEC + else if (oprec == 56) + lexp -= EXONE - 0201; +#endif + rndprc = oprec; + emdnorm (yy, k, 0, lexp, 64); + + aexit: + + rndprc = rndsav; + yy[0] = nsign; + switch (oprec) + { +#ifdef DEC + case 56: + todec (yy, y); /* see etodec.c */ + break; +#endif + case 53: + toe53 (yy, y); + break; + case 24: + toe24 (yy, y); + break; + case 64: + toe64 (yy, y); + break; + case NBITS: + emovo (yy, y); + break; + } +} + + + +/* y = largest integer not greater than x + * (truncated toward minus infinity) + * + * unsigned EMUSHORT x[NE], y[NE] + * + * efloor (x, y); + */ +static unsigned EMUSHORT bmask[] = +{ + 0xffff, + 0xfffe, + 0xfffc, + 0xfff8, + 0xfff0, + 0xffe0, + 0xffc0, + 0xff80, + 0xff00, + 0xfe00, + 0xfc00, + 0xf800, + 0xf000, + 0xe000, + 0xc000, + 0x8000, + 0x0000, +}; + +void +efloor (x, y) + unsigned EMUSHORT x[], y[]; +{ + register unsigned EMUSHORT *p; + int e, expon, i; + unsigned EMUSHORT f[NE]; + + emov (x, f); /* leave in external format */ + expon = (int) f[NE - 1]; + e = (expon & 0x7fff) - (EXONE - 1); + if (e <= 0) + { + eclear (y); + goto isitneg; + } + /* number of bits to clear out */ + e = NBITS - e; + emov (f, y); + if (e <= 0) + return; + + p = &y[0]; + while (e >= 16) + { + *p++ = 0; + e -= 16; + } + /* clear the remaining bits */ + *p &= bmask[e]; + /* truncate negatives toward minus infinity */ + isitneg: + + if ((unsigned EMUSHORT) expon & (unsigned EMUSHORT) 0x8000) + { + for (i = 0; i < NE - 1; i++) + { + if (f[i] != y[i]) + { + esub (eone, y, y); + break; + } + } + } +} + + +/* unsigned EMUSHORT x[], s[]; + * int *exp; + * + * efrexp (x, exp, s); + * + * Returns s and exp such that s * 2**exp = x and .5 <= s < 1. + * For example, 1.1 = 0.55 * 2**1 + * Handles denormalized numbers properly using long integer exp. + */ +void +efrexp (x, exp, s) + unsigned EMUSHORT x[]; + int *exp; + unsigned EMUSHORT s[]; +{ + unsigned EMUSHORT xi[NI]; + EMULONG li; + + emovi (x, xi); + li = (EMULONG) ((EMUSHORT) xi[1]); + + if (li == 0) + { + li -= enormlz (xi); + } + xi[1] = 0x3ffe; + emovo (xi, s); + *exp = (int) (li - 0x3ffe); +} + + + +/* unsigned EMUSHORT x[], y[]; + * long pwr2; + * + * eldexp (x, pwr2, y); + * + * Returns y = x * 2**pwr2. + */ +void +eldexp (x, pwr2, y) + unsigned EMUSHORT x[]; + int pwr2; + unsigned EMUSHORT y[]; +{ + unsigned EMUSHORT xi[NI]; + EMULONG li; + int i; + + emovi (x, xi); + li = xi[1]; + li += pwr2; + i = 0; + emdnorm (xi, i, i, li, 64); + emovo (xi, y); +} + + +/* c = remainder after dividing b by a + * Least significant integer quotient bits left in equot[]. + */ +void +eremain (a, b, c) + unsigned EMUSHORT a[], b[], c[]; +{ + unsigned EMUSHORT den[NI], num[NI]; + +#ifdef NANS + if ( eisinf (b) + || (ecmp (a, ezero) == 0) + || eisnan (a) + || eisnan (b)) + { + enan (c); + return; + } +#endif + if (ecmp (a, ezero) == 0) + { + mtherr ("eremain", SING); + eclear (c); + return; + } + emovi (a, den); + emovi (b, num); + eiremain (den, num); + /* Sign of remainder = sign of quotient */ + if (a[0] == b[0]) + num[0] = 0; + else + num[0] = 0xffff; + emovo (num, c); +} + +void +eiremain (den, num) + unsigned EMUSHORT den[], num[]; +{ + EMULONG ld, ln; + unsigned EMUSHORT j; + + ld = den[E]; + ld -= enormlz (den); + ln = num[E]; + ln -= enormlz (num); + ecleaz (equot); + while (ln >= ld) + { + if (ecmpm (den, num) <= 0) + { + esubm (den, num); + j = 1; + } + else + { + j = 0; + } + eshup1 (equot); + equot[NI - 1] |= j; + eshup1 (num); + ln -= 1; + } + emdnorm (num, 0, 0, ln, 0); +} + +/* mtherr.c + * + * Library common error handling routine + * + * + * + * SYNOPSIS: + * + * char *fctnam; + * int code; + * void mtherr (); + * + * mtherr (fctnam, code); + * + * + * + * DESCRIPTION: + * + * This routine may be called to report one of the following + * error conditions (in the include file mconf.h). + * + * Mnemonic Value Significance + * + * DOMAIN 1 argument domain error + * SING 2 function singularity + * OVERFLOW 3 overflow range error + * UNDERFLOW 4 underflow range error + * TLOSS 5 total loss of precision + * PLOSS 6 partial loss of precision + * INVALID 7 NaN - producing operation + * EDOM 33 Unix domain error code + * ERANGE 34 Unix range error code + * + * The default version of the file prints the function name, + * passed to it by the pointer fctnam, followed by the + * error condition. The display is directed to the standard + * output device. The routine then returns to the calling + * program. Users may wish to modify the program to abort by + * calling exit under severe error conditions such as domain + * errors. + * + * Since all error conditions pass control to this function, + * the display may be easily changed, eliminated, or directed + * to an error logging device. + * + * SEE ALSO: + * + * mconf.h + * + */ + +/* +Cephes Math Library Release 2.0: April, 1987 +Copyright 1984, 1987 by Stephen L. Moshier +Direct inquiries to 30 Frost Street, Cambridge, MA 02140 +*/ + +/* include "mconf.h" */ + +/* Notice: the order of appearance of the following + * messages is bound to the error codes defined + * in mconf.h. + */ +#define NMSGS 8 +static char *ermsg[NMSGS] = +{ + "unknown", /* error code 0 */ + "domain", /* error code 1 */ + "singularity", /* et seq. */ + "overflow", + "underflow", + "total loss of precision", + "partial loss of precision", + "invalid operation" +}; + +int merror = 0; +extern int merror; + +void +mtherr (name, code) + char *name; + int code; +{ + char errstr[80]; + + /* Display string passed by calling program, + * which is supposed to be the name of the + * function in which the error occurred. + */ + + /* Display error message defined + * by the code argument. + */ + if ((code <= 0) || (code >= NMSGS)) + code = 0; + sprintf (errstr, " %s %s error", name, ermsg[code]); + if (extra_warnings) + warning (errstr); + /* Set global error message word */ + merror = code + 1; + + /* Return to calling + * program + */ +} + +/* Here is etodec.c . + * + */ + +/* +; convert DEC double precision to e type +; double d; +; EMUSHORT e[NE]; +; dectoe (&d, e); +*/ +void +dectoe (d, e) + unsigned EMUSHORT *d; + unsigned EMUSHORT *e; +{ + unsigned EMUSHORT y[NI]; + register unsigned EMUSHORT r, *p; + + ecleaz (y); /* start with a zero */ + p = y; /* point to our number */ + r = *d; /* get DEC exponent word */ + if (*d & (unsigned int) 0x8000) + *p = 0xffff; /* fill in our sign */ + ++p; /* bump pointer to our exponent word */ + r &= 0x7fff; /* strip the sign bit */ + if (r == 0) /* answer = 0 if high order DEC word = 0 */ + goto done; + + + r >>= 7; /* shift exponent word down 7 bits */ + r += EXONE - 0201; /* subtract DEC exponent offset */ + /* add our e type exponent offset */ + *p++ = r; /* to form our exponent */ + + r = *d++; /* now do the high order mantissa */ + r &= 0177; /* strip off the DEC exponent and sign bits */ + r |= 0200; /* the DEC understood high order mantissa bit */ + *p++ = r; /* put result in our high guard word */ + + *p++ = *d++; /* fill in the rest of our mantissa */ + *p++ = *d++; + *p = *d; + + eshdn8 (y); /* shift our mantissa down 8 bits */ + done: + emovo (y, e); +} + + + +/* +; convert e type to DEC double precision +; double d; +; EMUSHORT e[NE]; +; etodec (e, &d); +*/ +#if 0 +static unsigned EMUSHORT decbit[NI] = {0, 0, 0, 0, 0, 0, 0200, 0}; + +void +etodec (x, d) + unsigned EMUSHORT *x, *d; +{ + unsigned EMUSHORT xi[NI]; + register unsigned EMUSHORT r; + int i, j; + + emovi (x, xi); + *d = 0; + if (xi[0] != 0) + *d = 0100000; + r = xi[E]; + if (r < (EXONE - 128)) + goto zout; + i = xi[M + 4]; + if ((i & 0200) != 0) + { + if ((i & 0377) == 0200) + { + if ((i & 0400) != 0) + { + /* check all less significant bits */ + for (j = M + 5; j < NI; j++) + { + if (xi[j] != 0) + goto yesrnd; + } + } + goto nornd; + } + yesrnd: + eaddm (decbit, xi); + r -= enormlz (xi); + } + + nornd: + + r -= EXONE; + r += 0201; + if (r < 0) + { + zout: + *d++ = 0; + *d++ = 0; + *d++ = 0; + *d++ = 0; + return; + } + if (r >= 0377) + { + *d++ = 077777; + *d++ = -1; + *d++ = -1; + *d++ = -1; + return; + } + r &= 0377; + r <<= 7; + eshup8 (xi); + xi[M] &= 0177; + r |= xi[M]; + *d++ |= r; + *d++ = xi[M + 1]; + *d++ = xi[M + 2]; + *d++ = xi[M + 3]; +} + +#else + +void +etodec (x, d) + unsigned EMUSHORT *x, *d; +{ + unsigned EMUSHORT xi[NI]; + EMULONG exp; + int rndsav; + + emovi (x, xi); + exp = (EMULONG) xi[E] - (EXONE - 0201); /* adjust exponent for offsets */ +/* round off to nearest or even */ + rndsav = rndprc; + rndprc = 56; + emdnorm (xi, 0, 0, exp, 64); + rndprc = rndsav; + todec (xi, d); +} + +void +todec (x, y) + unsigned EMUSHORT *x, *y; +{ + unsigned EMUSHORT i; + unsigned EMUSHORT *p; + + p = x; + *y = 0; + if (*p++) + *y = 0100000; + i = *p++; + if (i == 0) + { + *y++ = 0; + *y++ = 0; + *y++ = 0; + *y++ = 0; + return; + } + if (i > 0377) + { + *y++ |= 077777; + *y++ = 0xffff; + *y++ = 0xffff; + *y++ = 0xffff; +#ifdef ERANGE + errno = ERANGE; +#endif + return; + } + i &= 0377; + i <<= 7; + eshup8 (x); + x[M] &= 0177; + i |= x[M]; + *y++ |= i; + *y++ = x[M + 1]; + *y++ = x[M + 2]; + *y++ = x[M + 3]; +} + +#endif /* not 0 */ + + +/* Output a binary NaN bit pattern in the target machine's format. */ + +/* If special NaN bit patterns are required, define them in tm.h + as arrays of unsigned 16-bit shorts. Otherwise, use the default + patterns here. */ +#ifdef TFMODE_NAN +TFMODE_NAN; +#else +#ifdef MIEEE +unsigned EMUSHORT TFnan[8] = + {0x7fff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff}; +#endif +#ifdef IBMPC +unsigned EMUSHORT TFnan[8] = {0, 0, 0, 0, 0, 0, 0x8000, 0xffff}; +#endif +#endif + +#ifdef XFMODE_NAN +XFMODE_NAN; +#else +#ifdef MIEEE +unsigned EMUSHORT XFnan[6] = {0x7fff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff}; +#endif +#ifdef IBMPC +unsigned EMUSHORT XFnan[6] = {0, 0, 0, 0xc000, 0xffff, 0}; +#endif +#endif + +#ifdef DFMODE_NAN +DFMODE_NAN; +#else +#ifdef MIEEE +unsigned EMUSHORT DFnan[4] = {0x7fff, 0xffff, 0xffff, 0xffff}; +#endif +#ifdef IBMPC +unsigned EMUSHORT DFnan[4] = {0, 0, 0, 0xfff8}; +#endif +#endif + +#ifdef SFMODE_NAN +SFMODE_NAN; +#else +#ifdef MIEEE +unsigned EMUSHORT SFnan[2] = {0x7fff, 0xffff}; +#endif +#ifdef IBMPC +unsigned EMUSHORT SFnan[2] = {0, 0xffc0}; +#endif +#endif + + +void +make_nan (nan, mode) +unsigned EMUSHORT *nan; +enum machine_mode mode; +{ + int i, n; + unsigned EMUSHORT *p; + + switch (mode) + { +/* Possibly the `reserved operand' patterns on a VAX can be + used like NaN's, but probably not in the same way as IEEE. */ +#ifndef DEC + case TFmode: + n = 8; + p = TFnan; + break; + case XFmode: + n = 6; + p = XFnan; + break; + case DFmode: + n = 4; + p = DFnan; + break; + case SFmode: + n = 2; + p = SFnan; + break; +#endif + default: + abort (); + } + for (i=0; i < n; i++) + *nan++ = *p++; +} + +/* Convert an SFmode target `float' value to a REAL_VALUE_TYPE. + This is the inverse of the function `etarsingle' invoked by + REAL_VALUE_TO_TARGET_SINGLE. */ + +REAL_VALUE_TYPE +ereal_from_float (f) + unsigned long f; +{ + REAL_VALUE_TYPE r; + unsigned EMUSHORT s[2]; + unsigned EMUSHORT e[NE]; + + /* Convert 32 bit integer to array of 16 bit pieces in target machine order. + This is the inverse operation to what the function `endian' does. */ +#if WORDS_BIG_ENDIAN + s[0] = (unsigned EMUSHORT) (f >> 16); + s[1] = (unsigned EMUSHORT) f; +#else + s[0] = (unsigned EMUSHORT) f; + s[1] = (unsigned EMUSHORT) (f >> 16); +#endif + /* Convert and promote the target float to E-type. */ + e24toe (s, e); + /* Output E-type to REAL_VALUE_TYPE. */ + PUT_REAL (e, &r); + return r; +} + +/* Convert a DFmode target `double' value to a REAL_VALUE_TYPE. + This is the inverse of the function `etardouble' invoked by + REAL_VALUE_TO_TARGET_DOUBLE. + + The DFmode is stored as an array of longs (i.e., HOST_WIDE_INTs) + with 32 bits of the value per each long. The first element + of the input array holds the bits that would come first in the + target computer's memory. */ + +REAL_VALUE_TYPE +ereal_from_double (d) + unsigned long d[]; +{ + REAL_VALUE_TYPE r; + unsigned EMUSHORT s[4]; + unsigned EMUSHORT e[NE]; + + /* Convert array of 32 bit pieces to equivalent array of 16 bit pieces. + This is the inverse of `endian'. */ +#if WORDS_BIG_ENDIAN + s[0] = (unsigned EMUSHORT) (d[0] >> 16); + s[1] = (unsigned EMUSHORT) d[0]; + s[2] = (unsigned EMUSHORT) (d[1] >> 16); + s[3] = (unsigned EMUSHORT) d[1]; +#else + s[0] = (unsigned EMUSHORT) d[0]; + s[1] = (unsigned EMUSHORT) (d[0] >> 16); + s[2] = (unsigned EMUSHORT) d[1]; + s[3] = (unsigned EMUSHORT) (d[1] >> 16); +#endif + /* Convert target double to E-type. */ + e53toe (s, e); + /* Output E-type to REAL_VALUE_TYPE. */ + PUT_REAL (e, &r); + return r; +} +#endif /* EMU_NON_COMPILE not defined */ diff --git a/gnu/usr.bin/cc/lib/real.h b/gnu/usr.bin/cc/lib/real.h new file mode 100644 index 000000000000..4ac1822899e8 --- /dev/null +++ b/gnu/usr.bin/cc/lib/real.h @@ -0,0 +1,363 @@ +/* Front-end tree definitions for GNU compiler. + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef REAL_H_INCLUDED +#define REAL_H_INCLUDED + +/* Define codes for all the float formats that we know of. */ +#define UNKNOWN_FLOAT_FORMAT 0 +#define IEEE_FLOAT_FORMAT 1 +#define VAX_FLOAT_FORMAT 2 +#define IBM_FLOAT_FORMAT 3 + +/* Default to IEEE float if not specified. Nearly all machines use it. */ + +#ifndef TARGET_FLOAT_FORMAT +#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT +#endif + +#ifndef HOST_FLOAT_FORMAT +#define HOST_FLOAT_FORMAT IEEE_FLOAT_FORMAT +#endif + +#if TARGET_FLOAT_FORMAT == IEEE_FLOAT_FORMAT +#define REAL_INFINITY +#endif + +/* Defining REAL_ARITHMETIC invokes a floating point emulator + that can produce a target machine format differing by more + than just endian-ness from the host's format. The emulator + is also used to support extended real XFmode. */ +#ifndef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 64 +#endif +#if (LONG_DOUBLE_TYPE_SIZE == 96) || defined (REAL_ARITHMETIC) +/* **** Start of software floating point emulator interface macros **** */ + +/* Support 80-bit extended real XFmode if LONG_DOUBLE_TYPE_SIZE + has been defined to be 96 in the tm.h machine file. */ +#if (LONG_DOUBLE_TYPE_SIZE == 96) +#define REAL_IS_NOT_DOUBLE +#define REAL_ARITHMETIC +typedef struct { + HOST_WIDE_INT r[(11 + sizeof (HOST_WIDE_INT))/(sizeof (HOST_WIDE_INT))]; +} realvaluetype; +#define REAL_VALUE_TYPE realvaluetype + +#else /* no XFmode support */ + +#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT +/* If no XFmode support, then a REAL_VALUE_TYPE is 64 bits wide + but it is not necessarily a host machine double. */ +#define REAL_IS_NOT_DOUBLE +typedef struct { + HOST_WIDE_INT r[(7 + sizeof (HOST_WIDE_INT))/(sizeof (HOST_WIDE_INT))]; +} realvaluetype; +#define REAL_VALUE_TYPE realvaluetype +#else +/* If host and target formats are compatible, then a REAL_VALUE_TYPE + is actually a host machine double. */ +#define REAL_VALUE_TYPE double +#endif +#endif /* no XFmode support */ + +/* If emulation has been enabled by defining REAL_ARITHMETIC or by + setting LONG_DOUBLE_TYPE_SIZE to 96, then define macros so that + they invoke emulator functions. This will succeed only if the machine + files have been updated to use these macros in place of any + references to host machine `double' or `float' types. */ +#ifdef REAL_ARITHMETIC +#undef REAL_ARITHMETIC +#define REAL_ARITHMETIC(value, code, d1, d2) \ + earith (&(value), (code), &(d1), &(d2)) + +/* Declare functions in real.c that are referenced here. */ +void earith (), ereal_from_uint (), ereal_from_int (), ereal_to_int (); +void etarldouble (), etardouble (); +long etarsingle (); +int ereal_cmp (), eroundi (), ereal_isneg (); +unsigned int eroundui (); +REAL_VALUE_TYPE etrunci (), etruncui (), ereal_ldexp (), ereal_atof (); +REAL_VALUE_TYPE ereal_negate (), ereal_truncate (); +REAL_VALUE_TYPE ereal_from_float (), ereal_from_double (); + +#define REAL_VALUES_EQUAL(x, y) (ereal_cmp ((x), (y)) == 0) +/* true if x < y : */ +#define REAL_VALUES_LESS(x, y) (ereal_cmp ((x), (y)) == -1) +#define REAL_VALUE_LDEXP(x, n) ereal_ldexp (x, n) + +/* These return REAL_VALUE_TYPE: */ +#define REAL_VALUE_RNDZINT(x) (etrunci (x)) +#define REAL_VALUE_UNSIGNED_RNDZINT(x) (etruncui (x)) +extern REAL_VALUE_TYPE real_value_truncate (); +#define REAL_VALUE_TRUNCATE(mode, x) real_value_truncate (mode, x) + +/* These return int: */ +#define REAL_VALUE_FIX(x) (eroundi (x)) +#define REAL_VALUE_UNSIGNED_FIX(x) ((unsigned int) eroundui (x)) + +#define REAL_VALUE_ATOF ereal_atof +#define REAL_VALUE_NEGATE ereal_negate + +#define REAL_VALUE_MINUS_ZERO(x) \ + ((ereal_cmp (x, dconst0) == 0) && (ereal_isneg (x) != 0 )) + +#define REAL_VALUE_TO_INT ereal_to_int +#define REAL_VALUE_FROM_INT(d, i, j) (ereal_from_int (&d, i, j)) +#define REAL_VALUE_FROM_UNSIGNED_INT(d, i, j) (ereal_from_uint (&d, i, j)) + +/* IN is a REAL_VALUE_TYPE. OUT is an array of longs. */ +#define REAL_VALUE_TO_TARGET_LONG_DOUBLE(IN, OUT) (etarldouble ((IN), (OUT))) +#define REAL_VALUE_TO_TARGET_DOUBLE(IN, OUT) (etardouble ((IN), (OUT))) +/* d is an array of longs. */ +#define REAL_VALUE_FROM_TARGET_DOUBLE(d) (ereal_from_double (d)) +/* IN is a REAL_VALUE_TYPE. OUT is a long. */ +#define REAL_VALUE_TO_TARGET_SINGLE(IN, OUT) ((OUT) = etarsingle ((IN))) +/* f is a long. */ +#define REAL_VALUE_FROM_TARGET_SINGLE(f) (ereal_from_float (f)) + +/* Conversions to decimal ASCII string. */ +#define REAL_VALUE_TO_DECIMAL(r, fmt, s) (ereal_to_decimal (r, s)) + +#endif /* REAL_ARITHMETIC defined */ + +/* **** End of software floating point emulator interface macros **** */ +#else /* LONG_DOUBLE_TYPE_SIZE != 96 and REAL_ARITHMETIC not defined */ + +/* old interface */ +#ifdef REAL_ARITHMETIC +/* Defining REAL_IS_NOT_DOUBLE breaks certain initializations + when REAL_ARITHMETIC etc. are not defined. */ + +/* Now see if the host and target machines use the same format. + If not, define REAL_IS_NOT_DOUBLE (even if we end up representing + reals as doubles because we have no better way in this cross compiler.) + This turns off various optimizations that can happen when we know the + compiler's float format matches the target's float format. + */ +#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT +#define REAL_IS_NOT_DOUBLE +#ifndef REAL_VALUE_TYPE +typedef struct { + HOST_WIDE_INT r[sizeof (double)/sizeof (HOST_WIDE_INT)]; + } realvaluetype; +#define REAL_VALUE_TYPE realvaluetype +#endif /* no REAL_VALUE_TYPE */ +#endif /* formats differ */ +#endif /* 0 */ + +#endif /* emulator not used */ + +/* If we are not cross-compiling, use a `double' to represent the + floating-point value. Otherwise, use some other type + (probably a struct containing an array of longs). */ +#ifndef REAL_VALUE_TYPE +#define REAL_VALUE_TYPE double +#else +#define REAL_IS_NOT_DOUBLE +#endif + +#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + +/* Convert a type `double' value in host format first to a type `float' + value in host format and then to a single type `long' value which + is the bitwise equivalent of the `float' value. */ +#ifndef REAL_VALUE_TO_TARGET_SINGLE +#define REAL_VALUE_TO_TARGET_SINGLE(IN, OUT) \ +do { float f = (float) (IN); \ + (OUT) = *(long *) &f; \ + } while (0) +#endif + +/* Convert a type `double' value in host format to a pair of type `long' + values which is its bitwise equivalent, but put the two words into + proper word order for the target. */ +#ifndef REAL_VALUE_TO_TARGET_DOUBLE +#if defined (HOST_WORDS_BIG_ENDIAN) == WORDS_BIG_ENDIAN +#define REAL_VALUE_TO_TARGET_DOUBLE(IN, OUT) \ +do { REAL_VALUE_TYPE in = (IN); /* Make sure it's not in a register. */\ + (OUT)[0] = ((long *) &in)[0]; \ + (OUT)[1] = ((long *) &in)[1]; \ + } while (0) +#else +#define REAL_VALUE_TO_TARGET_DOUBLE(IN, OUT) \ +do { REAL_VALUE_TYPE in = (IN); /* Make sure it's not in a register. */\ + (OUT)[1] = ((long *) &in)[0]; \ + (OUT)[0] = ((long *) &in)[1]; \ + } while (0) +#endif +#endif +#endif /* HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT */ + +/* In this configuration, double and long double are the same. */ +#ifndef REAL_VALUE_TO_TARGET_LONG_DOUBLE +#define REAL_VALUE_TO_TARGET_LONG_DOUBLE(a, b) REAL_VALUE_TO_TARGET_DOUBLE (a, b) +#endif + +/* Compare two floating-point values for equality. */ +#ifndef REAL_VALUES_EQUAL +#define REAL_VALUES_EQUAL(x, y) ((x) == (y)) +#endif + +/* Compare two floating-point values for less than. */ +#ifndef REAL_VALUES_LESS +#define REAL_VALUES_LESS(x, y) ((x) < (y)) +#endif + +/* Truncate toward zero to an integer floating-point value. */ +#ifndef REAL_VALUE_RNDZINT +#define REAL_VALUE_RNDZINT(x) ((double) ((int) (x))) +#endif + +/* Truncate toward zero to an unsigned integer floating-point value. */ +#ifndef REAL_VALUE_UNSIGNED_RNDZINT +#define REAL_VALUE_UNSIGNED_RNDZINT(x) ((double) ((unsigned int) (x))) +#endif + +/* Convert a floating-point value to integer, using any rounding mode. */ +#ifndef REAL_VALUE_FIX +#define REAL_VALUE_FIX(x) ((int) (x)) +#endif + +/* Convert a floating-point value to unsigned integer, using any rounding + mode. */ +#ifndef REAL_VALUE_UNSIGNED_FIX +#define REAL_VALUE_UNSIGNED_FIX(x) ((unsigned int) (x)) +#endif + +/* Scale X by Y powers of 2. */ +#ifndef REAL_VALUE_LDEXP +#define REAL_VALUE_LDEXP(x, y) ldexp (x, y) +extern double ldexp (); +#endif + +/* Convert the string X to a floating-point value. */ +#ifndef REAL_VALUE_ATOF +#if 1 +/* Use real.c to convert decimal numbers to binary, ... */ +REAL_VALUE_TYPE ereal_atof (); +#define REAL_VALUE_ATOF(x, s) ereal_atof (x, s) +#else +/* ... or, if you like the host computer's atof, go ahead and use it: */ +#define REAL_VALUE_ATOF(x, s) atof (x) +#if defined (MIPSEL) || defined (MIPSEB) +/* MIPS compiler can't handle parens around the function name. + This problem *does not* appear to be connected with any + macro definition for atof. It does not seem there is one. */ +extern double atof (); +#else +extern double (atof) (); +#endif +#endif +#endif + +/* Negate the floating-point value X. */ +#ifndef REAL_VALUE_NEGATE +#define REAL_VALUE_NEGATE(x) (- (x)) +#endif + +/* Truncate the floating-point value X to mode MODE. This is correct only + for the most common case where the host and target have objects of the same + size and where `float' is SFmode. */ + +/* Don't use REAL_VALUE_TRUNCATE directly--always call real_value_truncate. */ +extern REAL_VALUE_TYPE real_value_truncate (); + +#ifndef REAL_VALUE_TRUNCATE +#define REAL_VALUE_TRUNCATE(mode, x) \ + (GET_MODE_BITSIZE (mode) == sizeof (float) * HOST_BITS_PER_CHAR \ + ? (float) (x) : (x)) +#endif + +/* Determine whether a floating-point value X is infinite. */ +#ifndef REAL_VALUE_ISINF +#define REAL_VALUE_ISINF(x) (target_isinf (x)) +#endif + +/* Determine whether a floating-point value X is a NaN. */ +#ifndef REAL_VALUE_ISNAN +#define REAL_VALUE_ISNAN(x) (target_isnan (x)) +#endif + +/* Determine whether a floating-point value X is negative. */ +#ifndef REAL_VALUE_NEGATIVE +#define REAL_VALUE_NEGATIVE(x) (target_negative (x)) +#endif + +/* Determine whether a floating-point value X is minus 0. */ +#ifndef REAL_VALUE_MINUS_ZERO +#define REAL_VALUE_MINUS_ZERO(x) ((x) == 0 && REAL_VALUE_NEGATIVE (x)) +#endif + +/* Constant real values 0, 1, 2, and -1. */ + +extern REAL_VALUE_TYPE dconst0; +extern REAL_VALUE_TYPE dconst1; +extern REAL_VALUE_TYPE dconst2; +extern REAL_VALUE_TYPE dconstm1; + +/* Union type used for extracting real values from CONST_DOUBLEs + or putting them in. */ + +union real_extract +{ + REAL_VALUE_TYPE d; + HOST_WIDE_INT i[sizeof (REAL_VALUE_TYPE) / sizeof (HOST_WIDE_INT)]; +}; + +/* For a CONST_DOUBLE: + The usual two ints that hold the value. + For a DImode, that is all there are; + and CONST_DOUBLE_LOW is the low-order word and ..._HIGH the high-order. + For a float, the number of ints varies, + and CONST_DOUBLE_LOW is the one that should come first *in memory*. + So use &CONST_DOUBLE_LOW(r) as the address of an array of ints. */ +#define CONST_DOUBLE_LOW(r) XWINT (r, 2) +#define CONST_DOUBLE_HIGH(r) XWINT (r, 3) + +/* Link for chain of all CONST_DOUBLEs in use in current function. */ +#define CONST_DOUBLE_CHAIN(r) XEXP (r, 1) +/* The MEM which represents this CONST_DOUBLE's value in memory, + or const0_rtx if no MEM has been made for it yet, + or cc0_rtx if it is not on the chain. */ +#define CONST_DOUBLE_MEM(r) XEXP (r, 0) + +/* Function to return a real value (not a tree node) + from a given integer constant. */ +REAL_VALUE_TYPE real_value_from_int_cst (); + +/* Given a CONST_DOUBLE in FROM, store into TO the value it represents. */ + +#define REAL_VALUE_FROM_CONST_DOUBLE(to, from) \ +do { union real_extract u; \ + bcopy (&CONST_DOUBLE_LOW ((from)), &u, sizeof u); \ + to = u.d; } while (0) + +/* Return a CONST_DOUBLE with value R and mode M. */ + +#define CONST_DOUBLE_FROM_REAL_VALUE(r, m) immed_real_const_1 (r, m) + +/* Convert a floating point value `r', that can be interpreted + as a host machine float or double, to a decimal ASCII string `s' + using printf format string `fmt'. */ +#ifndef REAL_VALUE_TO_DECIMAL +#define REAL_VALUE_TO_DECIMAL(r, fmt, s) (sprintf (s, fmt, r)) +#endif + +#endif /* Not REAL_H_INCLUDED */ diff --git a/gnu/usr.bin/cc/lib/recog.c b/gnu/usr.bin/cc/lib/recog.c new file mode 100644 index 000000000000..2232db29a1eb --- /dev/null +++ b/gnu/usr.bin/cc/lib/recog.c @@ -0,0 +1,1961 @@ +/* Subroutines used by or related to instruction recognition. + Copyright (C) 1987, 1988, 1991, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include "rtl.h" +#include +#include "insn-config.h" +#include "insn-attr.h" +#include "insn-flags.h" +#include "insn-codes.h" +#include "recog.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "flags.h" +#include "real.h" + +#ifndef STACK_PUSH_CODE +#ifdef STACK_GROWS_DOWNWARD +#define STACK_PUSH_CODE PRE_DEC +#else +#define STACK_PUSH_CODE PRE_INC +#endif +#endif + +/* Import from final.c: */ +extern rtx alter_subreg (); + +int strict_memory_address_p (); +int memory_address_p (); + +/* Nonzero means allow operands to be volatile. + This should be 0 if you are generating rtl, such as if you are calling + the functions in optabs.c and expmed.c (most of the time). + This should be 1 if all valid insns need to be recognized, + such as in regclass.c and final.c and reload.c. + + init_recog and init_recog_no_volatile are responsible for setting this. */ + +int volatile_ok; + +/* On return from `constrain_operands', indicate which alternative + was satisfied. */ + +int which_alternative; + +/* Nonzero after end of reload pass. + Set to 1 or 0 by toplev.c. + Controls the significance of (SUBREG (MEM)). */ + +int reload_completed; + +/* Initialize data used by the function `recog'. + This must be called once in the compilation of a function + before any insn recognition may be done in the function. */ + +void +init_recog_no_volatile () +{ + volatile_ok = 0; +} + +void +init_recog () +{ + volatile_ok = 1; +} + +/* Try recognizing the instruction INSN, + and return the code number that results. + Remeber the code so that repeated calls do not + need to spend the time for actual rerecognition. + + This function is the normal interface to instruction recognition. + The automatically-generated function `recog' is normally called + through this one. (The only exception is in combine.c.) */ + +int +recog_memoized (insn) + rtx insn; +{ + if (INSN_CODE (insn) < 0) + INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR); + return INSN_CODE (insn); +} + +/* Check that X is an insn-body for an `asm' with operands + and that the operands mentioned in it are legitimate. */ + +int +check_asm_operands (x) + rtx x; +{ + int noperands = asm_noperands (x); + rtx *operands; + int i; + + if (noperands < 0) + return 0; + if (noperands == 0) + return 1; + + operands = (rtx *) alloca (noperands * sizeof (rtx)); + decode_asm_operands (x, operands, NULL_PTR, NULL_PTR, NULL_PTR); + + for (i = 0; i < noperands; i++) + if (!general_operand (operands[i], VOIDmode)) + return 0; + + return 1; +} + +/* Static data for the next two routines. + + The maximum number of changes supported is defined as the maximum + number of operands times 5. This allows for repeated substitutions + inside complex indexed address, or, alternatively, changes in up + to 5 insns. */ + +#define MAX_CHANGE_LOCS (MAX_RECOG_OPERANDS * 5) + +static rtx change_objects[MAX_CHANGE_LOCS]; +static int change_old_codes[MAX_CHANGE_LOCS]; +static rtx *change_locs[MAX_CHANGE_LOCS]; +static rtx change_olds[MAX_CHANGE_LOCS]; + +static int num_changes = 0; + +/* Validate a proposed change to OBJECT. LOC is the location in the rtl for + at which NEW will be placed. If OBJECT is zero, no validation is done, + the change is simply made. + + Two types of objects are supported: If OBJECT is a MEM, memory_address_p + will be called with the address and mode as parameters. If OBJECT is + an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with + the change in place. + + IN_GROUP is non-zero if this is part of a group of changes that must be + performed as a group. In that case, the changes will be stored. The + function `apply_change_group' will validate and apply the changes. + + If IN_GROUP is zero, this is a single change. Try to recognize the insn + or validate the memory reference with the change applied. If the result + is not valid for the machine, suppress the change and return zero. + Otherwise, perform the change and return 1. */ + +int +validate_change (object, loc, new, in_group) + rtx object; + rtx *loc; + rtx new; + int in_group; +{ + rtx old = *loc; + + if (old == new || rtx_equal_p (old, new)) + return 1; + + if (num_changes >= MAX_CHANGE_LOCS + || (in_group == 0 && num_changes != 0)) + abort (); + + *loc = new; + + /* Save the information describing this change. */ + change_objects[num_changes] = object; + change_locs[num_changes] = loc; + change_olds[num_changes] = old; + + if (object && GET_CODE (object) != MEM) + { + /* Set INSN_CODE to force rerecognition of insn. Save old code in + case invalid. */ + change_old_codes[num_changes] = INSN_CODE (object); + INSN_CODE (object) = -1; + } + + num_changes++; + + /* If we are making a group of changes, return 1. Otherwise, validate the + change group we made. */ + + if (in_group) + return 1; + else + return apply_change_group (); +} + +/* Apply a group of changes previously issued with `validate_change'. + Return 1 if all changes are valid, zero otherwise. */ + +int +apply_change_group () +{ + int i; + + /* The changes have been applied and all INSN_CODEs have been reset to force + rerecognition. + + The changes are valid if we aren't given an object, or if we are + given a MEM and it still is a valid address, or if this is in insn + and it is recognized. In the latter case, if reload has completed, + we also require that the operands meet the constraints for + the insn. We do not allow modifying an ASM_OPERANDS after reload + has completed because verifying the constraints is too difficult. */ + + for (i = 0; i < num_changes; i++) + { + rtx object = change_objects[i]; + + if (object == 0) + continue; + + if (GET_CODE (object) == MEM) + { + if (! memory_address_p (GET_MODE (object), XEXP (object, 0))) + break; + } + else if ((recog_memoized (object) < 0 + && (asm_noperands (PATTERN (object)) < 0 + || ! check_asm_operands (PATTERN (object)) + || reload_completed)) + || (reload_completed + && (insn_extract (object), + ! constrain_operands (INSN_CODE (object), 1)))) + { + rtx pat = PATTERN (object); + + /* Perhaps we couldn't recognize the insn because there were + extra CLOBBERs at the end. If so, try to re-recognize + without the last CLOBBER (later iterations will cause each of + them to be eliminated, in turn). But don't do this if we + have an ASM_OPERAND. */ + if (GET_CODE (pat) == PARALLEL + && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER + && asm_noperands (PATTERN (object)) < 0) + { + rtx newpat; + + if (XVECLEN (pat, 0) == 2) + newpat = XVECEXP (pat, 0, 0); + else + { + int j; + + newpat = gen_rtx (PARALLEL, VOIDmode, + gen_rtvec (XVECLEN (pat, 0) - 1)); + for (j = 0; j < XVECLEN (newpat, 0); j++) + XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j); + } + + /* Add a new change to this group to replace the pattern + with this new pattern. Then consider this change + as having succeeded. The change we added will + cause the entire call to fail if things remain invalid. + + Note that this can lose if a later change than the one + we are processing specified &XVECEXP (PATTERN (object), 0, X) + but this shouldn't occur. */ + + validate_change (object, &PATTERN (object), newpat, 1); + } + else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + /* If this insn is a CLOBBER or USE, it is always valid, but is + never recognized. */ + continue; + else + break; + } + } + + if (i == num_changes) + { + num_changes = 0; + return 1; + } + else + { + cancel_changes (0); + return 0; + } +} + +/* Return the number of changes so far in the current group. */ + +int +num_validated_changes () +{ + return num_changes; +} + +/* Retract the changes numbered NUM and up. */ + +void +cancel_changes (num) + int num; +{ + int i; + + /* Back out all the changes. Do this in the opposite order in which + they were made. */ + for (i = num_changes - 1; i >= num; i--) + { + *change_locs[i] = change_olds[i]; + if (change_objects[i] && GET_CODE (change_objects[i]) != MEM) + INSN_CODE (change_objects[i]) = change_old_codes[i]; + } + num_changes = num; +} + +/* Replace every occurrence of FROM in X with TO. Mark each change with + validate_change passing OBJECT. */ + +static void +validate_replace_rtx_1 (loc, from, to, object) + rtx *loc; + rtx from, to, object; +{ + register int i, j; + register char *fmt; + register rtx x = *loc; + enum rtx_code code = GET_CODE (x); + + /* X matches FROM if it is the same rtx or they are both referring to the + same register in the same mode. Avoid calling rtx_equal_p unless the + operands look similar. */ + + if (x == from + || (GET_CODE (x) == REG && GET_CODE (from) == REG + && GET_MODE (x) == GET_MODE (from) + && REGNO (x) == REGNO (from)) + || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from) + && rtx_equal_p (x, from))) + { + validate_change (object, loc, to, 1); + return; + } + + /* For commutative or comparison operations, try replacing each argument + separately and seeing if we made any changes. If so, put a constant + argument last.*/ + if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') + { + int prev_changes = num_changes; + + validate_replace_rtx_1 (&XEXP (x, 0), from, to, object); + validate_replace_rtx_1 (&XEXP (x, 1), from, to, object); + if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0))) + { + validate_change (object, loc, + gen_rtx (GET_RTX_CLASS (code) == 'c' ? code + : swap_condition (code), + GET_MODE (x), XEXP (x, 1), XEXP (x, 0)), + 1); + x = *loc; + code = GET_CODE (x); + } + } + + switch (code) + { + case PLUS: + /* If we have have a PLUS whose second operand is now a CONST_INT, use + plus_constant to try to simplify it. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to) + validate_change (object, loc, + plus_constant (XEXP (x, 0), INTVAL (XEXP (x, 1))), 1); + return; + + case ZERO_EXTEND: + case SIGN_EXTEND: + /* In these cases, the operation to be performed depends on the mode + of the operand. If we are replacing the operand with a VOIDmode + constant, we lose the information. So try to simplify the operation + in that case. If it fails, substitute in something that we know + won't be recognized. */ + if (GET_MODE (to) == VOIDmode + && (XEXP (x, 0) == from + || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG + && GET_MODE (XEXP (x, 0)) == GET_MODE (from) + && REGNO (XEXP (x, 0)) == REGNO (from)))) + { + rtx new = simplify_unary_operation (code, GET_MODE (x), to, + GET_MODE (from)); + if (new == 0) + new = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); + + validate_change (object, loc, new, 1); + return; + } + break; + + case SUBREG: + /* If we have a SUBREG of a register that we are replacing and we are + replacing it with a MEM, make a new MEM and try replacing the + SUBREG with it. Don't do this if the MEM has a mode-dependent address + or if we would be widening it. */ + + if (SUBREG_REG (x) == from + && GET_CODE (from) == REG + && GET_CODE (to) == MEM + && ! mode_dependent_address_p (XEXP (to, 0)) + && ! MEM_VOLATILE_P (to) + && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to))) + { + int offset = SUBREG_WORD (x) * UNITS_PER_WORD; + enum machine_mode mode = GET_MODE (x); + rtx new; + +#if BYTES_BIG_ENDIAN + offset += (MIN (UNITS_PER_WORD, + GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) + - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); +#endif + + new = gen_rtx (MEM, mode, plus_constant (XEXP (to, 0), offset)); + MEM_VOLATILE_P (new) = MEM_VOLATILE_P (to); + RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to); + MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (to); + validate_change (object, loc, new, 1); + return; + } + break; + + case ZERO_EXTRACT: + case SIGN_EXTRACT: + /* If we are replacing a register with memory, try to change the memory + to be the mode required for memory in extract operations (this isn't + likely to be an insertion operation; if it was, nothing bad will + happen, we might just fail in some cases). */ + + if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM + && GET_CODE (XEXP (x, 1)) == CONST_INT + && GET_CODE (XEXP (x, 2)) == CONST_INT + && ! mode_dependent_address_p (XEXP (to, 0)) + && ! MEM_VOLATILE_P (to)) + { + enum machine_mode wanted_mode = VOIDmode; + enum machine_mode is_mode = GET_MODE (to); + int width = INTVAL (XEXP (x, 1)); + int pos = INTVAL (XEXP (x, 2)); + +#ifdef HAVE_extzv + if (code == ZERO_EXTRACT) + wanted_mode = insn_operand_mode[(int) CODE_FOR_extzv][1]; +#endif +#ifdef HAVE_extv + if (code == SIGN_EXTRACT) + wanted_mode = insn_operand_mode[(int) CODE_FOR_extv][1]; +#endif + + /* If we have a narrower mode, we can do something. */ + if (wanted_mode != VOIDmode + && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode)) + { + int offset = pos / BITS_PER_UNIT; + rtx newmem; + + /* If the bytes and bits are counted differently, we + must adjust the offset. */ +#if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN + offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) + - offset); +#endif + + pos %= GET_MODE_BITSIZE (wanted_mode); + + newmem = gen_rtx (MEM, wanted_mode, + plus_constant (XEXP (to, 0), offset)); + RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (to); + MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (to); + MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (to); + + validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1); + validate_change (object, &XEXP (x, 0), newmem, 1); + } + } + + break; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + validate_replace_rtx_1 (&XEXP (x, i), from, to, object); + else if (fmt[i] == 'E') + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object); + } +} + +/* Try replacing every occurrence of FROM in INSN with TO. After all + changes have been made, validate by seeing if INSN is still valid. */ + +int +validate_replace_rtx (from, to, insn) + rtx from, to, insn; +{ + validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); + return apply_change_group (); +} + +#ifdef HAVE_cc0 +/* Return 1 if the insn using CC0 set by INSN does not contain + any ordered tests applied to the condition codes. + EQ and NE tests do not count. */ + +int +next_insn_tests_no_inequality (insn) + rtx insn; +{ + register rtx next = next_cc0_user (insn); + + /* If there is no next insn, we have to take the conservative choice. */ + if (next == 0) + return 0; + + return ((GET_CODE (next) == JUMP_INSN + || GET_CODE (next) == INSN + || GET_CODE (next) == CALL_INSN) + && ! inequality_comparisons_p (PATTERN (next))); +} + +#if 0 /* This is useless since the insn that sets the cc's + must be followed immediately by the use of them. */ +/* Return 1 if the CC value set up by INSN is not used. */ + +int +next_insns_test_no_inequality (insn) + rtx insn; +{ + register rtx next = NEXT_INSN (insn); + + for (; next != 0; next = NEXT_INSN (next)) + { + if (GET_CODE (next) == CODE_LABEL + || GET_CODE (next) == BARRIER) + return 1; + if (GET_CODE (next) == NOTE) + continue; + if (inequality_comparisons_p (PATTERN (next))) + return 0; + if (sets_cc0_p (PATTERN (next)) == 1) + return 1; + if (! reg_mentioned_p (cc0_rtx, PATTERN (next))) + return 1; + } + return 1; +} +#endif +#endif + +/* This is used by find_single_use to locate an rtx that contains exactly one + use of DEST, which is typically either a REG or CC0. It returns a + pointer to the innermost rtx expression containing DEST. Appearances of + DEST that are being used to totally replace it are not counted. */ + +static rtx * +find_single_use_1 (dest, loc) + rtx dest; + rtx *loc; +{ + rtx x = *loc; + enum rtx_code code = GET_CODE (x); + rtx *result = 0; + rtx *this_result; + int i; + char *fmt; + + switch (code) + { + case CONST_INT: + case CONST: + case LABEL_REF: + case SYMBOL_REF: + case CONST_DOUBLE: + case CLOBBER: + return 0; + + case SET: + /* If the destination is anything other than CC0, PC, a REG or a SUBREG + of a REG that occupies all of the REG, the insn uses DEST if + it is mentioned in the destination or the source. Otherwise, we + need just check the source. */ + if (GET_CODE (SET_DEST (x)) != CC0 + && GET_CODE (SET_DEST (x)) != PC + && GET_CODE (SET_DEST (x)) != REG + && ! (GET_CODE (SET_DEST (x)) == SUBREG + && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG + && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) + + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) + == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) + + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) + break; + + return find_single_use_1 (dest, &SET_SRC (x)); + + case MEM: + case SUBREG: + return find_single_use_1 (dest, &XEXP (x, 0)); + } + + /* If it wasn't one of the common cases above, check each expression and + vector of this code. Look for a unique usage of DEST. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + { + if (dest == XEXP (x, i) + || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG + && REGNO (dest) == REGNO (XEXP (x, i)))) + this_result = loc; + else + this_result = find_single_use_1 (dest, &XEXP (x, i)); + + if (result == 0) + result = this_result; + else if (this_result) + /* Duplicate usage. */ + return 0; + } + else if (fmt[i] == 'E') + { + int j; + + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + { + if (XVECEXP (x, i, j) == dest + || (GET_CODE (dest) == REG + && GET_CODE (XVECEXP (x, i, j)) == REG + && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) + this_result = loc; + else + this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); + + if (result == 0) + result = this_result; + else if (this_result) + return 0; + } + } + } + + return result; +} + +/* See if DEST, produced in INSN, is used only a single time in the + sequel. If so, return a pointer to the innermost rtx expression in which + it is used. + + If PLOC is non-zero, *PLOC is set to the insn containing the single use. + + This routine will return usually zero either before flow is called (because + there will be no LOG_LINKS notes) or after reload (because the REG_DEAD + note can't be trusted). + + If DEST is cc0_rtx, we look only at the next insn. In that case, we don't + care about REG_DEAD notes or LOG_LINKS. + + Otherwise, we find the single use by finding an insn that has a + LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is + only referenced once in that insn, we know that it must be the first + and last insn referencing DEST. */ + +rtx * +find_single_use (dest, insn, ploc) + rtx dest; + rtx insn; + rtx *ploc; +{ + rtx next; + rtx *result; + rtx link; + +#ifdef HAVE_cc0 + if (dest == cc0_rtx) + { + next = NEXT_INSN (insn); + if (next == 0 + || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN)) + return 0; + + result = find_single_use_1 (dest, &PATTERN (next)); + if (result && ploc) + *ploc = next; + return result; + } +#endif + + if (reload_completed || reload_in_progress || GET_CODE (dest) != REG) + return 0; + + for (next = next_nonnote_insn (insn); + next != 0 && GET_CODE (next) != CODE_LABEL; + next = next_nonnote_insn (next)) + if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest)) + { + for (link = LOG_LINKS (next); link; link = XEXP (link, 1)) + if (XEXP (link, 0) == insn) + break; + + if (link) + { + result = find_single_use_1 (dest, &PATTERN (next)); + if (ploc) + *ploc = next; + return result; + } + } + + return 0; +} + +/* Return 1 if OP is a valid general operand for machine mode MODE. + This is either a register reference, a memory reference, + or a constant. In the case of a memory reference, the address + is checked for general validity for the target machine. + + Register and memory references must have mode MODE in order to be valid, + but some constants have no machine mode and are valid for any mode. + + If MODE is VOIDmode, OP is checked for validity for whatever mode + it has. + + The main use of this function is as a predicate in match_operand + expressions in the machine description. + + For an explanation of this function's behavior for registers of + class NO_REGS, see the comment for `register_operand'. */ + +int +general_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + register enum rtx_code code = GET_CODE (op); + int mode_altering_drug = 0; + + if (mode == VOIDmode) + mode = GET_MODE (op); + + /* Don't accept CONST_INT or anything similar + if the caller wants something floating. */ + if (GET_MODE (op) == VOIDmode && mode != VOIDmode + && GET_MODE_CLASS (mode) != MODE_INT + && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) + return 0; + + if (CONSTANT_P (op)) + return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) +#ifdef LEGITIMATE_PIC_OPERAND_P + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) +#endif + && LEGITIMATE_CONSTANT_P (op)); + + /* Except for certain constants with VOIDmode, already checked for, + OP's mode must match MODE if MODE specifies a mode. */ + + if (GET_MODE (op) != mode) + return 0; + + if (code == SUBREG) + { +#ifdef INSN_SCHEDULING + /* On machines that have insn scheduling, we want all memory + reference to be explicit, so outlaw paradoxical SUBREGs. */ + if (GET_CODE (SUBREG_REG (op)) == MEM + && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) + return 0; +#endif + + op = SUBREG_REG (op); + code = GET_CODE (op); +#if 0 + /* No longer needed, since (SUBREG (MEM...)) + will load the MEM into a reload reg in the MEM's own mode. */ + mode_altering_drug = 1; +#endif + } + + if (code == REG) + /* A register whose class is NO_REGS is not a general operand. */ + return (REGNO (op) >= FIRST_PSEUDO_REGISTER + || REGNO_REG_CLASS (REGNO (op)) != NO_REGS); + + if (code == MEM) + { + register rtx y = XEXP (op, 0); + if (! volatile_ok && MEM_VOLATILE_P (op)) + return 0; + /* Use the mem's mode, since it will be reloaded thus. */ + mode = GET_MODE (op); + GO_IF_LEGITIMATE_ADDRESS (mode, y, win); + } + return 0; + + win: + if (mode_altering_drug) + return ! mode_dependent_address_p (XEXP (op, 0)); + return 1; +} + +/* Return 1 if OP is a valid memory address for a memory reference + of mode MODE. + + The main use of this function is as a predicate in match_operand + expressions in the machine description. */ + +int +address_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + return memory_address_p (mode, op); +} + +/* Return 1 if OP is a register reference of mode MODE. + If MODE is VOIDmode, accept a register in any mode. + + The main use of this function is as a predicate in match_operand + expressions in the machine description. + + As a special exception, registers whose class is NO_REGS are + not accepted by `register_operand'. The reason for this change + is to allow the representation of special architecture artifacts + (such as a condition code register) without extending the rtl + definitions. Since registers of class NO_REGS cannot be used + as registers in any case where register classes are examined, + it is most consistent to keep this function from accepting them. */ + +int +register_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (GET_MODE (op) != mode && mode != VOIDmode) + return 0; + + if (GET_CODE (op) == SUBREG) + { + /* Before reload, we can allow (SUBREG (MEM...)) as a register operand + because it is guaranteed to be reloaded into one. + Just make sure the MEM is valid in itself. + (Ideally, (SUBREG (MEM)...) should not exist after reload, + but currently it does result from (SUBREG (REG)...) where the + reg went on the stack.) */ + if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) + return general_operand (op, mode); + op = SUBREG_REG (op); + } + + /* We don't consider registers whose class is NO_REGS + to be a register operand. */ + return (GET_CODE (op) == REG + && (REGNO (op) >= FIRST_PSEUDO_REGISTER + || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); +} + +/* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH + or a hard register. */ + +int +scratch_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + return (GET_MODE (op) == mode + && (GET_CODE (op) == SCRATCH + || (GET_CODE (op) == REG + && REGNO (op) < FIRST_PSEUDO_REGISTER))); +} + +/* Return 1 if OP is a valid immediate operand for mode MODE. + + The main use of this function is as a predicate in match_operand + expressions in the machine description. */ + +int +immediate_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + /* Don't accept CONST_INT or anything similar + if the caller wants something floating. */ + if (GET_MODE (op) == VOIDmode && mode != VOIDmode + && GET_MODE_CLASS (mode) != MODE_INT + && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) + return 0; + + return (CONSTANT_P (op) + && (GET_MODE (op) == mode || mode == VOIDmode + || GET_MODE (op) == VOIDmode) +#ifdef LEGITIMATE_PIC_OPERAND_P + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) +#endif + && LEGITIMATE_CONSTANT_P (op)); +} + +/* Returns 1 if OP is an operand that is a CONST_INT. */ + +int +const_int_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + return GET_CODE (op) == CONST_INT; +} + +/* Returns 1 if OP is an operand that is a constant integer or constant + floating-point number. */ + +int +const_double_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + /* Don't accept CONST_INT or anything similar + if the caller wants something floating. */ + if (GET_MODE (op) == VOIDmode && mode != VOIDmode + && GET_MODE_CLASS (mode) != MODE_INT + && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) + return 0; + + return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT) + && (mode == VOIDmode || GET_MODE (op) == mode + || GET_MODE (op) == VOIDmode)); +} + +/* Return 1 if OP is a general operand that is not an immediate operand. */ + +int +nonimmediate_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + return (general_operand (op, mode) && ! CONSTANT_P (op)); +} + +/* Return 1 if OP is a register reference or immediate value of mode MODE. */ + +int +nonmemory_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (CONSTANT_P (op)) + { + /* Don't accept CONST_INT or anything similar + if the caller wants something floating. */ + if (GET_MODE (op) == VOIDmode && mode != VOIDmode + && GET_MODE_CLASS (mode) != MODE_INT + && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) + return 0; + + return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) +#ifdef LEGITIMATE_PIC_OPERAND_P + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) +#endif + && LEGITIMATE_CONSTANT_P (op)); + } + + if (GET_MODE (op) != mode && mode != VOIDmode) + return 0; + + if (GET_CODE (op) == SUBREG) + { + /* Before reload, we can allow (SUBREG (MEM...)) as a register operand + because it is guaranteed to be reloaded into one. + Just make sure the MEM is valid in itself. + (Ideally, (SUBREG (MEM)...) should not exist after reload, + but currently it does result from (SUBREG (REG)...) where the + reg went on the stack.) */ + if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) + return general_operand (op, mode); + op = SUBREG_REG (op); + } + + /* We don't consider registers whose class is NO_REGS + to be a register operand. */ + return (GET_CODE (op) == REG + && (REGNO (op) >= FIRST_PSEUDO_REGISTER + || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); +} + +/* Return 1 if OP is a valid operand that stands for pushing a + value of mode MODE onto the stack. + + The main use of this function is as a predicate in match_operand + expressions in the machine description. */ + +int +push_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) != MEM) + return 0; + + if (GET_MODE (op) != mode) + return 0; + + op = XEXP (op, 0); + + if (GET_CODE (op) != STACK_PUSH_CODE) + return 0; + + return XEXP (op, 0) == stack_pointer_rtx; +} + +/* Return 1 if ADDR is a valid memory address for mode MODE. */ + +int +memory_address_p (mode, addr) + enum machine_mode mode; + register rtx addr; +{ + GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); + return 0; + + win: + return 1; +} + +/* Return 1 if OP is a valid memory reference with mode MODE, + including a valid address. + + The main use of this function is as a predicate in match_operand + expressions in the machine description. */ + +int +memory_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + rtx inner; + + if (! reload_completed) + /* Note that no SUBREG is a memory operand before end of reload pass, + because (SUBREG (MEM...)) forces reloading into a register. */ + return GET_CODE (op) == MEM && general_operand (op, mode); + + if (mode != VOIDmode && GET_MODE (op) != mode) + return 0; + + inner = op; + if (GET_CODE (inner) == SUBREG) + inner = SUBREG_REG (inner); + + return (GET_CODE (inner) == MEM && general_operand (op, mode)); +} + +/* Return 1 if OP is a valid indirect memory reference with mode MODE; + that is, a memory reference whose address is a general_operand. */ + +int +indirect_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */ + if (! reload_completed + && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM) + { + register int offset = SUBREG_WORD (op) * UNITS_PER_WORD; + rtx inner = SUBREG_REG (op); + +#if BYTES_BIG_ENDIAN + offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op))) + - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner)))); +#endif + + /* The only way that we can have a general_operand as the resulting + address is if OFFSET is zero and the address already is an operand + or if the address is (plus Y (const_int -OFFSET)) and Y is an + operand. */ + + return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode)) + || (GET_CODE (XEXP (inner, 0)) == PLUS + && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT + && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset + && general_operand (XEXP (XEXP (inner, 0), 0), Pmode))); + } + + return (GET_CODE (op) == MEM + && memory_operand (op, mode) + && general_operand (XEXP (op, 0), Pmode)); +} + +/* Return 1 if this is a comparison operator. This allows the use of + MATCH_OPERATOR to recognize all the branch insns. */ + +int +comparison_operator (op, mode) + register rtx op; + enum machine_mode mode; +{ + return ((mode == VOIDmode || GET_MODE (op) == mode) + && GET_RTX_CLASS (GET_CODE (op)) == '<'); +} + +/* If BODY is an insn body that uses ASM_OPERANDS, + return the number of operands (both input and output) in the insn. + Otherwise return -1. */ + +int +asm_noperands (body) + rtx body; +{ + if (GET_CODE (body) == ASM_OPERANDS) + /* No output operands: return number of input operands. */ + return ASM_OPERANDS_INPUT_LENGTH (body); + if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) + /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ + return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; + else if (GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) + { + /* Multiple output operands, or 1 output plus some clobbers: + body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ + int i; + int n_sets; + + /* Count backwards through CLOBBERs to determine number of SETs. */ + for (i = XVECLEN (body, 0); i > 0; i--) + { + if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) + break; + if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) + return -1; + } + + /* N_SETS is now number of output operands. */ + n_sets = i; + + /* Verify that all the SETs we have + came from a single original asm_operands insn + (so that invalid combinations are blocked). */ + for (i = 0; i < n_sets; i++) + { + rtx elt = XVECEXP (body, 0, i); + if (GET_CODE (elt) != SET) + return -1; + if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) + return -1; + /* If these ASM_OPERANDS rtx's came from different original insns + then they aren't allowed together. */ + if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) + != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) + return -1; + } + return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) + + n_sets); + } + else if (GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) + { + /* 0 outputs, but some clobbers: + body is [(asm_operands ...) (clobber (reg ...))...]. */ + int i; + + /* Make sure all the other parallel things really are clobbers. */ + for (i = XVECLEN (body, 0) - 1; i > 0; i--) + if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) + return -1; + + return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); + } + else + return -1; +} + +/* Assuming BODY is an insn body that uses ASM_OPERANDS, + copy its operands (both input and output) into the vector OPERANDS, + the locations of the operands within the insn into the vector OPERAND_LOCS, + and the constraints for the operands into CONSTRAINTS. + Write the modes of the operands into MODES. + Return the assembler-template. + + If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, + we don't store that info. */ + +char * +decode_asm_operands (body, operands, operand_locs, constraints, modes) + rtx body; + rtx *operands; + rtx **operand_locs; + char **constraints; + enum machine_mode *modes; +{ + register int i; + int noperands; + char *template = 0; + + if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) + { + rtx asmop = SET_SRC (body); + /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */ + + noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1; + + for (i = 1; i < noperands; i++) + { + if (operand_locs) + operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1); + if (operands) + operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1); + if (constraints) + constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1); + if (modes) + modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1); + } + + /* The output is in the SET. + Its constraint is in the ASM_OPERANDS itself. */ + if (operands) + operands[0] = SET_DEST (body); + if (operand_locs) + operand_locs[0] = &SET_DEST (body); + if (constraints) + constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop); + if (modes) + modes[0] = GET_MODE (SET_DEST (body)); + template = ASM_OPERANDS_TEMPLATE (asmop); + } + else if (GET_CODE (body) == ASM_OPERANDS) + { + rtx asmop = body; + /* No output operands: BODY is (asm_operands ....). */ + + noperands = ASM_OPERANDS_INPUT_LENGTH (asmop); + + /* The input operands are found in the 1st element vector. */ + /* Constraints for inputs are in the 2nd element vector. */ + for (i = 0; i < noperands; i++) + { + if (operand_locs) + operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); + if (operands) + operands[i] = ASM_OPERANDS_INPUT (asmop, i); + if (constraints) + constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); + if (modes) + modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); + } + template = ASM_OPERANDS_TEMPLATE (asmop); + } + else if (GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == SET) + { + rtx asmop = SET_SRC (XVECEXP (body, 0, 0)); + int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */ + int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); + int nout = 0; /* Does not include CLOBBERs. */ + + /* At least one output, plus some CLOBBERs. */ + + /* The outputs are in the SETs. + Their constraints are in the ASM_OPERANDS itself. */ + for (i = 0; i < nparallel; i++) + { + if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) + break; /* Past last SET */ + + if (operands) + operands[i] = SET_DEST (XVECEXP (body, 0, i)); + if (operand_locs) + operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i)); + if (constraints) + constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1); + if (modes) + modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i))); + nout++; + } + + for (i = 0; i < nin; i++) + { + if (operand_locs) + operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i); + if (operands) + operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i); + if (constraints) + constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); + if (modes) + modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i); + } + + template = ASM_OPERANDS_TEMPLATE (asmop); + } + else if (GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) + { + /* No outputs, but some CLOBBERs. */ + + rtx asmop = XVECEXP (body, 0, 0); + int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); + + for (i = 0; i < nin; i++) + { + if (operand_locs) + operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); + if (operands) + operands[i] = ASM_OPERANDS_INPUT (asmop, i); + if (constraints) + constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); + if (modes) + modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); + } + + template = ASM_OPERANDS_TEMPLATE (asmop); + } + + return template; +} + +/* Given an rtx *P, if it is a sum containing an integer constant term, + return the location (type rtx *) of the pointer to that constant term. + Otherwise, return a null pointer. */ + +static rtx * +find_constant_term_loc (p) + rtx *p; +{ + register rtx *tem; + register enum rtx_code code = GET_CODE (*p); + + /* If *P IS such a constant term, P is its location. */ + + if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF + || code == CONST) + return p; + + /* Otherwise, if not a sum, it has no constant term. */ + + if (GET_CODE (*p) != PLUS) + return 0; + + /* If one of the summands is constant, return its location. */ + + if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0)) + && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1))) + return p; + + /* Otherwise, check each summand for containing a constant term. */ + + if (XEXP (*p, 0) != 0) + { + tem = find_constant_term_loc (&XEXP (*p, 0)); + if (tem != 0) + return tem; + } + + if (XEXP (*p, 1) != 0) + { + tem = find_constant_term_loc (&XEXP (*p, 1)); + if (tem != 0) + return tem; + } + + return 0; +} + +/* Return 1 if OP is a memory reference + whose address contains no side effects + and remains valid after the addition + of a positive integer less than the + size of the object being referenced. + + We assume that the original address is valid and do not check it. + + This uses strict_memory_address_p as a subroutine, so + don't use it before reload. */ + +int +offsettable_memref_p (op) + rtx op; +{ + return ((GET_CODE (op) == MEM) + && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0))); +} + +/* Similar, but don't require a strictly valid mem ref: + consider pseudo-regs valid as index or base regs. */ + +int +offsettable_nonstrict_memref_p (op) + rtx op; +{ + return ((GET_CODE (op) == MEM) + && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0))); +} + +/* Return 1 if Y is a memory address which contains no side effects + and would remain valid after the addition of a positive integer + less than the size of that mode. + + We assume that the original address is valid and do not check it. + We do check that it is valid for narrower modes. + + If STRICTP is nonzero, we require a strictly valid address, + for the sake of use in reload.c. */ + +int +offsettable_address_p (strictp, mode, y) + int strictp; + enum machine_mode mode; + register rtx y; +{ + register enum rtx_code ycode = GET_CODE (y); + register rtx z; + rtx y1 = y; + rtx *y2; + int (*addressp) () = (strictp ? strict_memory_address_p : memory_address_p); + + if (CONSTANT_ADDRESS_P (y)) + return 1; + + /* Adjusting an offsettable address involves changing to a narrower mode. + Make sure that's OK. */ + + if (mode_dependent_address_p (y)) + return 0; + + /* If the expression contains a constant term, + see if it remains valid when max possible offset is added. */ + + if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1))) + { + int good; + + y1 = *y2; + *y2 = plus_constant (*y2, GET_MODE_SIZE (mode) - 1); + /* Use QImode because an odd displacement may be automatically invalid + for any wider mode. But it should be valid for a single byte. */ + good = (*addressp) (QImode, y); + + /* In any case, restore old contents of memory. */ + *y2 = y1; + return good; + } + + if (ycode == PRE_DEC || ycode == PRE_INC + || ycode == POST_DEC || ycode == POST_INC) + return 0; + + /* The offset added here is chosen as the maximum offset that + any instruction could need to add when operating on something + of the specified mode. We assume that if Y and Y+c are + valid addresses then so is Y+d for all 0 0) + { + funny_match[funny_match_index].this = opno; + funny_match[funny_match_index++].other = c - '0'; + } + break; + + case 'p': + /* p is used for address_operands. When we are called by + gen_input_reload, no one will have checked that the + address is strictly valid, i.e., that all pseudos + requiring hard regs have gotten them. */ + if (strict <= 0 + || (strict_memory_address_p + (insn_operand_mode[insn_code_num][opno], op))) + win = 1; + break; + + /* No need to check general_operand again; + it was done in insn-recog.c. */ + case 'g': + /* Anything goes unless it is a REG and really has a hard reg + but the hard reg is not in the class GENERAL_REGS. */ + if (strict < 0 + || GENERAL_REGS == ALL_REGS + || GET_CODE (op) != REG + || (reload_in_progress + && REGNO (op) >= FIRST_PSEUDO_REGISTER) + || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) + win = 1; + break; + + case 'r': + if (strict < 0 + || (strict == 0 + && GET_CODE (op) == REG + && REGNO (op) >= FIRST_PSEUDO_REGISTER) + || (strict == 0 && GET_CODE (op) == SCRATCH) + || (GET_CODE (op) == REG + && ((GENERAL_REGS == ALL_REGS + && REGNO (op) < FIRST_PSEUDO_REGISTER) + || reg_fits_class_p (op, GENERAL_REGS, + offset, mode)))) + win = 1; + break; + + case 'X': + /* This is used for a MATCH_SCRATCH in the cases when we + don't actually need anything. So anything goes any time. */ + win = 1; + break; + + case 'm': + if (GET_CODE (op) == MEM + /* Before reload, accept what reload can turn into mem. */ + || (strict < 0 && CONSTANT_P (op)) + /* During reload, accept a pseudo */ + || (reload_in_progress && GET_CODE (op) == REG + && REGNO (op) >= FIRST_PSEUDO_REGISTER)) + win = 1; + break; + + case '<': + if (GET_CODE (op) == MEM + && (GET_CODE (XEXP (op, 0)) == PRE_DEC + || GET_CODE (XEXP (op, 0)) == POST_DEC)) + win = 1; + break; + + case '>': + if (GET_CODE (op) == MEM + && (GET_CODE (XEXP (op, 0)) == PRE_INC + || GET_CODE (XEXP (op, 0)) == POST_INC)) + win = 1; + break; + + case 'E': + /* Match any CONST_DOUBLE, but only if + we can examine the bits of it reliably. */ + if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT + || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) + && GET_MODE (op) != VOIDmode && ! flag_pretend_float) + break; + if (GET_CODE (op) == CONST_DOUBLE) + win = 1; + break; + + case 'F': + if (GET_CODE (op) == CONST_DOUBLE) + win = 1; + break; + + case 'G': + case 'H': + if (GET_CODE (op) == CONST_DOUBLE + && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) + win = 1; + break; + + case 's': + if (GET_CODE (op) == CONST_INT + || (GET_CODE (op) == CONST_DOUBLE + && GET_MODE (op) == VOIDmode)) + break; + case 'i': + if (CONSTANT_P (op)) + win = 1; + break; + + case 'n': + if (GET_CODE (op) == CONST_INT + || (GET_CODE (op) == CONST_DOUBLE + && GET_MODE (op) == VOIDmode)) + win = 1; + break; + + case 'I': + case 'J': + case 'K': + case 'L': + case 'M': + case 'N': + case 'O': + case 'P': + if (GET_CODE (op) == CONST_INT + && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) + win = 1; + break; + +#ifdef EXTRA_CONSTRAINT + case 'Q': + case 'R': + case 'S': + case 'T': + case 'U': + if (EXTRA_CONSTRAINT (op, c)) + win = 1; + break; +#endif + + case 'V': + if (GET_CODE (op) == MEM + && ! offsettable_memref_p (op)) + win = 1; + break; + + case 'o': + if ((strict > 0 && offsettable_memref_p (op)) + || (strict == 0 && offsettable_nonstrict_memref_p (op)) + /* Before reload, accept what reload can handle. */ + || (strict < 0 + && (CONSTANT_P (op) || GET_CODE (op) == MEM)) + /* During reload, accept a pseudo */ + || (reload_in_progress && GET_CODE (op) == REG + && REGNO (op) >= FIRST_PSEUDO_REGISTER)) + win = 1; + break; + + default: + if (strict < 0 + || (strict == 0 + && GET_CODE (op) == REG + && REGNO (op) >= FIRST_PSEUDO_REGISTER) + || (strict == 0 && GET_CODE (op) == SCRATCH) + || (GET_CODE (op) == REG + && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c), + offset, mode))) + win = 1; + } + + constraints[opno] = p; + /* If this operand did not win somehow, + this alternative loses. */ + if (! win) + lose = 1; + } + /* This alternative won; the operands are ok. + Change whichever operands this alternative says to change. */ + if (! lose) + { + int opno, eopno; + + /* See if any earlyclobber operand conflicts with some other + operand. */ + + if (strict > 0) + for (eopno = 0; eopno < noperands; eopno++) + /* Ignore earlyclobber operands now in memory, + because we would often report failure when we have + two memory operands, one of which was formerly a REG. */ + if (earlyclobber[eopno] + && GET_CODE (recog_operand[eopno]) == REG) + for (opno = 0; opno < noperands; opno++) + if ((GET_CODE (recog_operand[opno]) == MEM + || op_types[opno] != OP_OUT) + && opno != eopno + /* Ignore things like match_operator operands. */ + && *constraints[opno] != 0 + && ! (matching_operands[opno] == eopno + && rtx_equal_p (recog_operand[opno], + recog_operand[eopno])) + && ! safe_from_earlyclobber (recog_operand[opno], + recog_operand[eopno])) + lose = 1; + + if (! lose) + { + while (--funny_match_index >= 0) + { + recog_operand[funny_match[funny_match_index].other] + = recog_operand[funny_match[funny_match_index].this]; + } + + return 1; + } + } + + which_alternative++; + } + + /* If we are about to reject this, but we are not to test strictly, + try a very loose test. Only return failure if it fails also. */ + if (strict == 0) + return constrain_operands (insn_code_num, -1); + else + return 0; +} + +/* Return 1 iff OPERAND (assumed to be a REG rtx) + is a hard reg in class CLASS when its regno is offsetted by OFFSET + and changed to mode MODE. + If REG occupies multiple hard regs, all of them must be in CLASS. */ + +int +reg_fits_class_p (operand, class, offset, mode) + rtx operand; + register enum reg_class class; + int offset; + enum machine_mode mode; +{ + register int regno = REGNO (operand); + if (regno < FIRST_PSEUDO_REGISTER + && TEST_HARD_REG_BIT (reg_class_contents[(int) class], + regno + offset)) + { + register int sr; + regno += offset; + for (sr = HARD_REGNO_NREGS (regno, mode) - 1; + sr > 0; sr--) + if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], + regno + sr)) + break; + return sr == 0; + } + + return 0; +} + +#endif /* REGISTER_CONSTRAINTS */ diff --git a/gnu/usr.bin/cc/lib/recog.h b/gnu/usr.bin/cc/lib/recog.h new file mode 100644 index 000000000000..8fc2efb47727 --- /dev/null +++ b/gnu/usr.bin/cc/lib/recog.h @@ -0,0 +1,120 @@ +/* Declarations for interface to insn recognizer and insn-output.c. + Copyright (C) 1987 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Add prototype support. */ +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif + +/* Recognize an insn and return its insn-code, + which is the sequence number of the DEFINE_INSN that it matches. + If the insn does not match, return -1. */ + +extern int recog_memoized PROTO((rtx)); + +/* Determine whether a proposed change to an insn or MEM will make it + invalid. Make the change if not. */ + +extern int validate_change PROTO((rtx, rtx *, rtx, int)); + +/* Apply a group of changes if valid. */ + +extern int apply_change_group PROTO((void)); + +/* Return the number of changes so far in the current group. */ + +extern int num_validated_changes PROTO((void)); + +/* Retract some changes. */ + +extern void cancel_changes PROTO((int)); + +/* Nonzero means volatile operands are recognized. */ + +extern int volatile_ok; + +/* Extract the operands from an insn that has been recognized. */ + +extern void insn_extract PROTO((rtx)); + +/* The following vectors hold the results from insn_extract. */ + +/* Indexed by N, gives value of operand N. */ +extern rtx recog_operand[]; + +/* Indexed by N, gives location where operand N was found. */ +extern rtx *recog_operand_loc[]; + +/* Indexed by N, gives location where the Nth duplicate-appearance of + an operand was found. This is something that matched MATCH_DUP. */ +extern rtx *recog_dup_loc[]; + +/* Indexed by N, gives the operand number that was duplicated in the + Nth duplicate-appearance of an operand. */ +extern char recog_dup_num[]; + +#ifndef __STDC__ +#ifndef const +#define const +#endif +#endif + +/* Access the output function for CODE. */ + +#define OUT_FCN(CODE) (*insn_outfun[(int) (CODE)]) + +/* Tables defined in insn-output.c that give information about + each insn-code value. */ + +/* These are vectors indexed by insn-code. Details in genoutput.c. */ + +extern char *const insn_template[]; + +extern char *(*const insn_outfun[]) (); + +extern const int insn_n_operands[]; + +extern const int insn_n_dups[]; + +/* Indexed by insn code number, gives # of constraint alternatives. */ + +extern const int insn_n_alternatives[]; + +/* These are two-dimensional arrays indexed first by the insn-code + and second by the operand number. Details in genoutput.c. */ + +#ifdef REGISTER_CONSTRAINTS /* Avoid undef sym in certain broken linkers. */ +extern char *const insn_operand_constraint[][MAX_RECOG_OPERANDS]; +#endif + +#ifndef REGISTER_CONSTRAINTS /* Avoid undef sym in certain broken linkers. */ +extern const char insn_operand_address_p[][MAX_RECOG_OPERANDS]; +#endif + +extern const enum machine_mode insn_operand_mode[][MAX_RECOG_OPERANDS]; + +extern const char insn_operand_strict_low[][MAX_RECOG_OPERANDS]; + +extern int (*const insn_operand_predicate[][MAX_RECOG_OPERANDS]) (); + +extern char * insn_name[]; diff --git a/gnu/usr.bin/cc/lib/reg-stack.c b/gnu/usr.bin/cc/lib/reg-stack.c new file mode 100644 index 000000000000..33bd2689d762 --- /dev/null +++ b/gnu/usr.bin/cc/lib/reg-stack.c @@ -0,0 +1,2897 @@ +/* Register to Stack convert for GNU compiler. + Copyright (C) 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* This pass converts stack-like registers from the "flat register + file" model that gcc uses, to a stack convention that the 387 uses. + + * The form of the input: + + On input, the function consists of insn that have had their + registers fully allocated to a set of "virtual" registers. Note that + the word "virtual" is used differently here than elsewhere in gcc: for + each virtual stack reg, there is a hard reg, but the mapping between + them is not known until this pass is run. On output, hard register + numbers have been substituted, and various pop and exchange insns have + been emitted. The hard register numbers and the virtual register + numbers completely overlap - before this pass, all stack register + numbers are virtual, and afterward they are all hard. + + The virtual registers can be manipulated normally by gcc, and their + semantics are the same as for normal registers. After the hard + register numbers are substituted, the semantics of an insn containing + stack-like regs are not the same as for an insn with normal regs: for + instance, it is not safe to delete an insn that appears to be a no-op + move. In general, no insn containing hard regs should be changed + after this pass is done. + + * The form of the output: + + After this pass, hard register numbers represent the distance from + the current top of stack to the desired register. A reference to + FIRST_STACK_REG references the top of stack, FIRST_STACK_REG + 1, + represents the register just below that, and so forth. Also, REG_DEAD + notes indicate whether or not a stack register should be popped. + + A "swap" insn looks like a parallel of two patterns, where each + pattern is a SET: one sets A to B, the other B to A. + + A "push" or "load" insn is a SET whose SET_DEST is FIRST_STACK_REG + and whose SET_DEST is REG or MEM. Any other SET_DEST, such as PLUS, + will replace the existing stack top, not push a new value. + + A store insn is a SET whose SET_DEST is FIRST_STACK_REG, and whose + SET_SRC is REG or MEM. + + The case where the SET_SRC and SET_DEST are both FIRST_STACK_REG + appears ambiguous. As a special case, the presence of a REG_DEAD note + for FIRST_STACK_REG differentiates between a load insn and a pop. + + If a REG_DEAD is present, the insn represents a "pop" that discards + the top of the register stack. If there is no REG_DEAD note, then the + insn represents a "dup" or a push of the current top of stack onto the + stack. + + * Methodology: + + Existing REG_DEAD and REG_UNUSED notes for stack registers are + deleted and recreated from scratch. REG_DEAD is never created for a + SET_DEST, only REG_UNUSED. + + Before life analysis, the mode of each insn is set based on whether + or not any stack registers are mentioned within that insn. VOIDmode + means that no regs are mentioned anyway, and QImode means that at + least one pattern within the insn mentions stack registers. This + information is valid until after reg_to_stack returns, and is used + from jump_optimize. + + * asm_operands: + + There are several rules on the usage of stack-like regs in + asm_operands insns. These rules apply only to the operands that are + stack-like regs: + + 1. Given a set of input regs that die in an asm_operands, it is + necessary to know which are implicitly popped by the asm, and + which must be explicitly popped by gcc. + + An input reg that is implicitly popped by the asm must be + explicitly clobbered, unless it is constrained to match an + output operand. + + 2. For any input reg that is implicitly popped by an asm, it is + necessary to know how to adjust the stack to compensate for the pop. + If any non-popped input is closer to the top of the reg-stack than + the implicitly popped reg, it would not be possible to know what the + stack looked like - it's not clear how the rest of the stack "slides + up". + + All implicitly popped input regs must be closer to the top of + the reg-stack than any input that is not implicitly popped. + + 3. It is possible that if an input dies in an insn, reload might + use the input reg for an output reload. Consider this example: + + asm ("foo" : "=t" (a) : "f" (b)); + + This asm says that input B is not popped by the asm, and that + the asm pushes a result onto the reg-stack, ie, the stack is one + deeper after the asm than it was before. But, it is possible that + reload will think that it can use the same reg for both the input and + the output, if input B dies in this insn. + + If any input operand uses the "f" constraint, all output reg + constraints must use the "&" earlyclobber. + + The asm above would be written as + + asm ("foo" : "=&t" (a) : "f" (b)); + + 4. Some operands need to be in particular places on the stack. All + output operands fall in this category - there is no other way to + know which regs the outputs appear in unless the user indicates + this in the constraints. + + Output operands must specifically indicate which reg an output + appears in after an asm. "=f" is not allowed: the operand + constraints must select a class with a single reg. + + 5. Output operands may not be "inserted" between existing stack regs. + Since no 387 opcode uses a read/write operand, all output operands + are dead before the asm_operands, and are pushed by the asm_operands. + It makes no sense to push anywhere but the top of the reg-stack. + + Output operands must start at the top of the reg-stack: output + operands may not "skip" a reg. + + 6. Some asm statements may need extra stack space for internal + calculations. This can be guaranteed by clobbering stack registers + unrelated to the inputs and outputs. + + Here are a couple of reasonable asms to want to write. This asm + takes one input, which is internally popped, and produces two outputs. + + asm ("fsincos" : "=t" (cos), "=u" (sin) : "0" (inp)); + + This asm takes two inputs, which are popped by the fyl2xp1 opcode, + and replaces them with one output. The user must code the "st(1)" + clobber for reg-stack.c to know that fyl2xp1 pops both inputs. + + asm ("fyl2xp1" : "=t" (result) : "0" (x), "u" (y) : "st(1)"); + + */ + +#include +#include "config.h" +#include "tree.h" +#include "rtl.h" +#include "insn-config.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "flags.h" + +#ifdef STACK_REGS + +#define REG_STACK_SIZE (LAST_STACK_REG - FIRST_STACK_REG + 1) + +/* True if the current function returns a real value. */ +static int current_function_returns_real; + +/* This is the basic stack record. TOP is an index into REG[] such + that REG[TOP] is the top of stack. If TOP is -1 the stack is empty. + + If TOP is -2, REG[] is not yet initialized. Stack initialization + consists of placing each live reg in array `reg' and setting `top' + appropriately. + + REG_SET indicates which registers are live. */ + +typedef struct stack_def +{ + int top; /* index to top stack element */ + HARD_REG_SET reg_set; /* set of live registers */ + char reg[REG_STACK_SIZE]; /* register - stack mapping */ +} *stack; + +/* highest instruction uid */ +static int max_uid = 0; + +/* Number of basic blocks in the current function. */ +static int blocks; + +/* Element N is first insn in basic block N. + This info lasts until we finish compiling the function. */ +static rtx *block_begin; + +/* Element N is last insn in basic block N. + This info lasts until we finish compiling the function. */ +static rtx *block_end; + +/* Element N is nonzero if control can drop into basic block N */ +static char *block_drops_in; + +/* Element N says all about the stack at entry block N */ +static stack block_stack_in; + +/* Element N says all about the stack life at the end of block N */ +static HARD_REG_SET *block_out_reg_set; + +/* This is where the BLOCK_NUM values are really stored. This is set + up by find_blocks and used there and in life_analysis. It can be used + later, but only to look up an insn that is the head or tail of some + block. life_analysis and the stack register conversion process can + add insns within a block. */ +static int *block_number; + +/* This is the register file for all register after conversion */ +static rtx FP_mode_reg[FIRST_PSEUDO_REGISTER][(int) MAX_MACHINE_MODE]; + +/* Get the basic block number of an insn. See note at block_number + definition are validity of this information. */ + +#define BLOCK_NUM(INSN) \ + (((INSN_UID (INSN) > max_uid) \ + ? (int *)(abort() , 0) \ + : block_number)[INSN_UID (INSN)]) + +extern rtx gen_jump (); +extern rtx gen_movdf (); +extern rtx find_regno_note (); +extern rtx emit_jump_insn_before (); +extern rtx emit_label_after (); + +/* Forward declarations */ + +static void find_blocks (); +static void stack_reg_life_analysis (); +static void change_stack (); +static void convert_regs (); +static void dump_stack_info (); + +/* Return non-zero if any stack register is mentioned somewhere within PAT. */ + +int +stack_regs_mentioned_p (pat) + rtx pat; +{ + register char *fmt; + register int i; + + if (STACK_REG_P (pat)) + return 1; + + fmt = GET_RTX_FORMAT (GET_CODE (pat)); + for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + + for (j = XVECLEN (pat, i) - 1; j >= 0; j--) + if (stack_regs_mentioned_p (XVECEXP (pat, i, j))) + return 1; + } + else if (fmt[i] == 'e' && stack_regs_mentioned_p (XEXP (pat, i))) + return 1; + } + + return 0; +} + +/* Convert register usage from "flat" register file usage to a "stack + register file. FIRST is the first insn in the function, FILE is the + dump file, if used. + + First compute the beginning and end of each basic block. Do a + register life analysis on the stack registers, recording the result + for the head and tail of each basic block. The convert each insn one + by one. Run a last jump_optimize() pass, if optimizing, to eliminate + any cross-jumping created when the converter inserts pop insns.*/ + +void +reg_to_stack (first, file) + rtx first; + FILE *file; +{ + register rtx insn; + register int i; + int stack_reg_seen = 0; + enum machine_mode mode; + + current_function_returns_real + = TREE_CODE (TREE_TYPE (DECL_RESULT (current_function_decl))) == REAL_TYPE; + + for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + FP_mode_reg[i][(int) mode] = gen_rtx (REG, mode, i); + + /* Count the basic blocks. Also find maximum insn uid. */ + { + register RTX_CODE prev_code = JUMP_INSN; + register RTX_CODE code; + + max_uid = 0; + blocks = 0; + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + /* Note that this loop must select the same block boundaries + as code in find_blocks. */ + + if (INSN_UID (insn) > max_uid) + max_uid = INSN_UID (insn); + + code = GET_CODE (insn); + + if (code == CODE_LABEL + || (prev_code != INSN + && prev_code != CALL_INSN + && prev_code != CODE_LABEL + && (code == INSN || code == CALL_INSN || code == JUMP_INSN))) + blocks++; + + /* Remember whether or not this insn mentions an FP regs. + Check JUMP_INSNs too, in case someone creates a funny PARALLEL. */ + + if ((GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN + || GET_CODE (insn) == JUMP_INSN) + && stack_regs_mentioned_p (PATTERN (insn))) + { + stack_reg_seen = 1; + PUT_MODE (insn, QImode); + } + else + PUT_MODE (insn, VOIDmode); + + if (code != NOTE) + prev_code = code; + } + } + + /* If no stack register reference exists in this insn, there isn't + anything to convert. */ + + if (! stack_reg_seen) + return; + + /* If there are stack registers, there must be at least one block. */ + + if (! blocks) + abort (); + + /* Allocate some tables that last till end of compiling this function + and some needed only in find_blocks and life_analysis. */ + + block_begin = (rtx *) alloca (blocks * sizeof (rtx)); + block_end = (rtx *) alloca (blocks * sizeof (rtx)); + block_drops_in = (char *) alloca (blocks); + + block_stack_in = (stack) alloca (blocks * sizeof (struct stack_def)); + block_out_reg_set = (HARD_REG_SET *) alloca (blocks * sizeof (HARD_REG_SET)); + bzero (block_stack_in, blocks * sizeof (struct stack_def)); + bzero (block_out_reg_set, blocks * sizeof (HARD_REG_SET)); + + block_number = (int *) alloca ((max_uid + 1) * sizeof (int)); + + find_blocks (first); + stack_reg_life_analysis (first); + + /* Dump the life analysis debug information before jump + optimization, as that will destroy the LABEL_REFS we keep the + information in. */ + + if (file) + dump_stack_info (file); + + convert_regs (); + + if (optimize) + jump_optimize (first, 2, 0, 0); +} + +/* Check PAT, which is in INSN, for LABEL_REFs. Add INSN to the + label's chain of references, and note which insn contains each + reference. */ + +static void +record_label_references (insn, pat) + rtx insn, pat; +{ + register enum rtx_code code = GET_CODE (pat); + register int i; + register char *fmt; + + if (code == LABEL_REF) + { + register rtx label = XEXP (pat, 0); + register rtx ref; + + if (GET_CODE (label) != CODE_LABEL) + abort (); + + /* Don't make a duplicate in the code_label's chain. */ + + for (ref = LABEL_REFS (label); ref != label; ref = LABEL_NEXTREF (ref)) + if (CONTAINING_INSN (ref) == insn) + return; + + CONTAINING_INSN (pat) = insn; + LABEL_NEXTREF (pat) = LABEL_REFS (label); + LABEL_REFS (label) = pat; + + return; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + record_label_references (insn, XEXP (pat, i)); + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (pat, i); j++) + record_label_references (insn, XVECEXP (pat, i, j)); + } + } +} + +/* Return a pointer to the REG expression within PAT. If PAT is not a + REG, possible enclosed by a conversion rtx, return the inner part of + PAT that stopped the search. */ + +static rtx * +get_true_reg (pat) + rtx *pat; +{ + while (GET_CODE (*pat) == SUBREG + || GET_CODE (*pat) == FLOAT + || GET_CODE (*pat) == FIX + || GET_CODE (*pat) == FLOAT_EXTEND) + pat = & XEXP (*pat, 0); + + return pat; +} + +/* Scan the OPERANDS and OPERAND_CONSTRAINTS of an asm_operands. + N_OPERANDS is the total number of operands. Return which alternative + matched, or -1 is no alternative matches. + + OPERAND_MATCHES is an array which indicates which operand this + operand matches due to the constraints, or -1 if no match is required. + If two operands match by coincidence, but are not required to match by + the constraints, -1 is returned. + + OPERAND_CLASS is an array which indicates the smallest class + required by the constraints. If the alternative that matches calls + for some class `class', and the operand matches a subclass of `class', + OPERAND_CLASS is set to `class' as required by the constraints, not to + the subclass. If an alternative allows more than one class, + OPERAND_CLASS is set to the smallest class that is a union of the + allowed classes. */ + +static int +constrain_asm_operands (n_operands, operands, operand_constraints, + operand_matches, operand_class) + int n_operands; + rtx *operands; + char **operand_constraints; + int *operand_matches; + enum reg_class *operand_class; +{ + char **constraints = (char **) alloca (n_operands * sizeof (char *)); + char *q; + int this_alternative, this_operand; + int n_alternatives; + int j; + + for (j = 0; j < n_operands; j++) + constraints[j] = operand_constraints[j]; + + /* Compute the number of alternatives in the operands. reload has + already guaranteed that all operands have the same number of + alternatives. */ + + n_alternatives = 1; + for (q = constraints[0]; *q; q++) + n_alternatives += (*q == ','); + + this_alternative = 0; + while (this_alternative < n_alternatives) + { + int lose = 0; + int i; + + /* No operands match, no narrow class requirements yet. */ + for (i = 0; i < n_operands; i++) + { + operand_matches[i] = -1; + operand_class[i] = NO_REGS; + } + + for (this_operand = 0; this_operand < n_operands; this_operand++) + { + rtx op = operands[this_operand]; + enum machine_mode mode = GET_MODE (op); + char *p = constraints[this_operand]; + int offset = 0; + int win = 0; + int c; + + if (GET_CODE (op) == SUBREG) + { + if (GET_CODE (SUBREG_REG (op)) == REG + && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) + offset = SUBREG_WORD (op); + op = SUBREG_REG (op); + } + + /* An empty constraint or empty alternative + allows anything which matched the pattern. */ + if (*p == 0 || *p == ',') + win = 1; + + while (*p && (c = *p++) != ',') + switch (c) + { + case '=': + case '+': + case '?': + case '&': + case '!': + case '*': + case '%': + /* Ignore these. */ + break; + + case '#': + /* Ignore rest of this alternative. */ + while (*p && *p != ',') p++; + break; + + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + /* This operand must be the same as a previous one. + This kind of constraint is used for instructions such + as add when they take only two operands. + + Note that the lower-numbered operand is passed first. */ + + if (operands_match_p (operands[c - '0'], + operands[this_operand])) + { + operand_matches[this_operand] = c - '0'; + win = 1; + } + break; + + case 'p': + /* p is used for address_operands. Since this is an asm, + just to make sure that the operand is valid for Pmode. */ + + if (strict_memory_address_p (Pmode, op)) + win = 1; + break; + + case 'g': + /* Anything goes unless it is a REG and really has a hard reg + but the hard reg is not in the class GENERAL_REGS. */ + if (GENERAL_REGS == ALL_REGS + || GET_CODE (op) != REG + || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) + { + if (GET_CODE (op) == REG) + operand_class[this_operand] + = reg_class_subunion[(int) operand_class[this_operand]][(int) GENERAL_REGS]; + win = 1; + } + break; + + case 'r': + if (GET_CODE (op) == REG + && (GENERAL_REGS == ALL_REGS + || reg_fits_class_p (op, GENERAL_REGS, offset, mode))) + { + operand_class[this_operand] + = reg_class_subunion[(int) operand_class[this_operand]][(int) GENERAL_REGS]; + win = 1; + } + break; + + case 'X': + /* This is used for a MATCH_SCRATCH in the cases when we + don't actually need anything. So anything goes any time. */ + win = 1; + break; + + case 'm': + if (GET_CODE (op) == MEM) + win = 1; + break; + + case '<': + if (GET_CODE (op) == MEM + && (GET_CODE (XEXP (op, 0)) == PRE_DEC + || GET_CODE (XEXP (op, 0)) == POST_DEC)) + win = 1; + break; + + case '>': + if (GET_CODE (op) == MEM + && (GET_CODE (XEXP (op, 0)) == PRE_INC + || GET_CODE (XEXP (op, 0)) == POST_INC)) + win = 1; + break; + + case 'E': + /* Match any CONST_DOUBLE, but only if + we can examine the bits of it reliably. */ + if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT + || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) + && GET_CODE (op) != VOIDmode && ! flag_pretend_float) + break; + if (GET_CODE (op) == CONST_DOUBLE) + win = 1; + break; + + case 'F': + if (GET_CODE (op) == CONST_DOUBLE) + win = 1; + break; + + case 'G': + case 'H': + if (GET_CODE (op) == CONST_DOUBLE + && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) + win = 1; + break; + + case 's': + if (GET_CODE (op) == CONST_INT + || (GET_CODE (op) == CONST_DOUBLE + && GET_MODE (op) == VOIDmode)) + break; + /* Fall through */ + case 'i': + if (CONSTANT_P (op)) + win = 1; + break; + + case 'n': + if (GET_CODE (op) == CONST_INT + || (GET_CODE (op) == CONST_DOUBLE + && GET_MODE (op) == VOIDmode)) + win = 1; + break; + + case 'I': + case 'J': + case 'K': + case 'L': + case 'M': + case 'N': + case 'O': + case 'P': + if (GET_CODE (op) == CONST_INT + && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) + win = 1; + break; + +#ifdef EXTRA_CONSTRAINT + case 'Q': + case 'R': + case 'S': + case 'T': + case 'U': + if (EXTRA_CONSTRAINT (op, c)) + win = 1; + break; +#endif + + case 'V': + if (GET_CODE (op) == MEM && ! offsettable_memref_p (op)) + win = 1; + break; + + case 'o': + if (offsettable_memref_p (op)) + win = 1; + break; + + default: + if (GET_CODE (op) == REG + && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c), + offset, mode)) + { + operand_class[this_operand] + = reg_class_subunion[(int)operand_class[this_operand]][(int) REG_CLASS_FROM_LETTER (c)]; + win = 1; + } + } + + constraints[this_operand] = p; + /* If this operand did not win somehow, + this alternative loses. */ + if (! win) + lose = 1; + } + /* This alternative won; the operands are ok. + Change whichever operands this alternative says to change. */ + if (! lose) + break; + + this_alternative++; + } + + /* For operands constrained to match another operand, copy the other + operand's class to this operand's class. */ + for (j = 0; j < n_operands; j++) + if (operand_matches[j] >= 0) + operand_class[j] = operand_class[operand_matches[j]]; + + return this_alternative == n_alternatives ? -1 : this_alternative; +} + +/* Record the life info of each stack reg in INSN, updating REGSTACK. + N_INPUTS is the number of inputs; N_OUTPUTS the outputs. CONSTRAINTS + is an array of the constraint strings used in the asm statement. + OPERANDS is an array of all operands for the insn, and is assumed to + contain all output operands, then all inputs operands. + + There are many rules that an asm statement for stack-like regs must + follow. Those rules are explained at the top of this file: the rule + numbers below refer to that explanation. */ + +static void +record_asm_reg_life (insn, regstack, operands, constraints, + n_inputs, n_outputs) + rtx insn; + stack regstack; + rtx *operands; + char **constraints; + int n_inputs, n_outputs; +{ + int i; + int n_operands = n_inputs + n_outputs; + int first_input = n_outputs; + int n_clobbers; + int malformed_asm = 0; + rtx body = PATTERN (insn); + + int *operand_matches = (int *) alloca (n_operands * sizeof (int *)); + + enum reg_class *operand_class + = (enum reg_class *) alloca (n_operands * sizeof (enum reg_class *)); + + int reg_used_as_output[FIRST_PSEUDO_REGISTER]; + int implicitly_dies[FIRST_PSEUDO_REGISTER]; + + rtx *clobber_reg; + + /* Find out what the constraints require. If no constraint + alternative matches, this asm is malformed. */ + i = constrain_asm_operands (n_operands, operands, constraints, + operand_matches, operand_class); + if (i < 0) + malformed_asm = 1; + + /* Strip SUBREGs here to make the following code simpler. */ + for (i = 0; i < n_operands; i++) + if (GET_CODE (operands[i]) == SUBREG + && GET_CODE (SUBREG_REG (operands[i])) == REG) + operands[i] = SUBREG_REG (operands[i]); + + /* Set up CLOBBER_REG. */ + + n_clobbers = 0; + + if (GET_CODE (body) == PARALLEL) + { + clobber_reg = (rtx *) alloca (XVECLEN (body, 0) * sizeof (rtx *)); + + for (i = 0; i < XVECLEN (body, 0); i++) + if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) + { + rtx clobber = XVECEXP (body, 0, i); + rtx reg = XEXP (clobber, 0); + + if (GET_CODE (reg) == SUBREG && GET_CODE (SUBREG_REG (reg)) == REG) + reg = SUBREG_REG (reg); + + if (STACK_REG_P (reg)) + { + clobber_reg[n_clobbers] = reg; + n_clobbers++; + } + } + } + + /* Enforce rule #4: Output operands must specifically indicate which + reg an output appears in after an asm. "=f" is not allowed: the + operand constraints must select a class with a single reg. + + Also enforce rule #5: Output operands must start at the top of + the reg-stack: output operands may not "skip" a reg. */ + + bzero (reg_used_as_output, sizeof (reg_used_as_output)); + for (i = 0; i < n_outputs; i++) + if (STACK_REG_P (operands[i])) + if (reg_class_size[(int) operand_class[i]] != 1) + { + error_for_asm + (insn, "Output constraint %d must specify a single register", i); + malformed_asm = 1; + } + else + reg_used_as_output[REGNO (operands[i])] = 1; + + + /* Search for first non-popped reg. */ + for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++) + if (! reg_used_as_output[i]) + break; + + /* If there are any other popped regs, that's an error. */ + for (; i < LAST_STACK_REG + 1; i++) + if (reg_used_as_output[i]) + break; + + if (i != LAST_STACK_REG + 1) + { + error_for_asm (insn, "Output regs must be grouped at top of stack"); + malformed_asm = 1; + } + + /* Enforce rule #2: All implicitly popped input regs must be closer + to the top of the reg-stack than any input that is not implicitly + popped. */ + + bzero (implicitly_dies, sizeof (implicitly_dies)); + for (i = first_input; i < first_input + n_inputs; i++) + if (STACK_REG_P (operands[i])) + { + /* An input reg is implicitly popped if it is tied to an + output, or if there is a CLOBBER for it. */ + int j; + + for (j = 0; j < n_clobbers; j++) + if (operands_match_p (clobber_reg[j], operands[i])) + break; + + if (j < n_clobbers || operand_matches[i] >= 0) + implicitly_dies[REGNO (operands[i])] = 1; + } + + /* Search for first non-popped reg. */ + for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++) + if (! implicitly_dies[i]) + break; + + /* If there are any other popped regs, that's an error. */ + for (; i < LAST_STACK_REG + 1; i++) + if (implicitly_dies[i]) + break; + + if (i != LAST_STACK_REG + 1) + { + error_for_asm (insn, + "Implicitly popped regs must be grouped at top of stack"); + malformed_asm = 1; + } + + /* Enfore rule #3: If any input operand uses the "f" constraint, all + output constraints must use the "&" earlyclobber. + + ??? Detect this more deterministically by having constraint_asm_operands + record any earlyclobber. */ + + for (i = first_input; i < first_input + n_inputs; i++) + if (operand_matches[i] == -1) + { + int j; + + for (j = 0; j < n_outputs; j++) + if (operands_match_p (operands[j], operands[i])) + { + error_for_asm (insn, + "Output operand %d must use `&' constraint", j); + malformed_asm = 1; + } + } + + if (malformed_asm) + { + /* Avoid further trouble with this insn. */ + PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); + PUT_MODE (insn, VOIDmode); + return; + } + + /* Process all outputs */ + for (i = 0; i < n_outputs; i++) + { + rtx op = operands[i]; + + if (! STACK_REG_P (op)) + if (stack_regs_mentioned_p (op)) + abort (); + else + continue; + + /* Each destination is dead before this insn. If the + destination is not used after this insn, record this with + REG_UNUSED. */ + + if (! TEST_HARD_REG_BIT (regstack->reg_set, REGNO (op))) + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_UNUSED, op, + REG_NOTES (insn)); + + CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (op)); + } + + /* Process all inputs */ + for (i = first_input; i < first_input + n_inputs; i++) + { + if (! STACK_REG_P (operands[i])) + if (stack_regs_mentioned_p (operands[i])) + abort (); + else + continue; + + /* If an input is dead after the insn, record a death note. + But don't record a death note if there is already a death note, + or if the input is also an output. */ + + if (! TEST_HARD_REG_BIT (regstack->reg_set, REGNO (operands[i])) + && operand_matches[i] == -1 + && find_regno_note (insn, REG_DEAD, REGNO (operands[i])) == NULL_RTX) + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_DEAD, operands[i], + REG_NOTES (insn)); + + SET_HARD_REG_BIT (regstack->reg_set, REGNO (operands[i])); + } +} + +/* Scan PAT, which is part of INSN, and record registers appearing in + a SET_DEST in DEST, and other registers in SRC. + + This function does not know about SET_DESTs that are both input and + output (such as ZERO_EXTRACT) - this cannot happen on a 387. */ + +void +record_reg_life_pat (pat, src, dest) + rtx pat; + HARD_REG_SET *src, *dest; +{ + register char *fmt; + register int i; + + if (STACK_REG_P (pat)) + { + if (src) + SET_HARD_REG_BIT (*src, REGNO (pat)); + + if (dest) + SET_HARD_REG_BIT (*dest, REGNO (pat)); + + return; + } + + if (GET_CODE (pat) == SET) + { + record_reg_life_pat (XEXP (pat, 0), NULL_PTR, dest); + record_reg_life_pat (XEXP (pat, 1), src, NULL_PTR); + return; + } + + /* We don't need to consider either of these cases. */ + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + return; + + fmt = GET_RTX_FORMAT (GET_CODE (pat)); + for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + + for (j = XVECLEN (pat, i) - 1; j >= 0; j--) + record_reg_life_pat (XVECEXP (pat, i, j), src, dest); + } + else if (fmt[i] == 'e') + record_reg_life_pat (XEXP (pat, i), src, dest); + } +} + +/* Calculate the number of inputs and outputs in BODY, an + asm_operands. N_OPERANDS is the total number of operands, and + N_INPUTS and N_OUTPUTS are pointers to ints into which the results are + placed. */ + +static void +get_asm_operand_lengths (body, n_operands, n_inputs, n_outputs) + rtx body; + int n_operands; + int *n_inputs, *n_outputs; +{ + if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) + *n_inputs = ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)); + + else if (GET_CODE (body) == ASM_OPERANDS) + *n_inputs = ASM_OPERANDS_INPUT_LENGTH (body); + + else if (GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == SET) + *n_inputs = ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))); + + else if (GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) + *n_inputs = ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); + else + abort (); + + *n_outputs = n_operands - *n_inputs; +} + +/* Scan INSN, which is in BLOCK, and record the life & death of stack + registers in REGSTACK. This function is called to process insns from + the last insn in a block to the first. The actual scanning is done in + record_reg_life_pat. + + If a register is live after a CALL_INSN, but is not a value return + register for that CALL_INSN, then code is emitted to initialize that + register. The block_end[] data is kept accurate. + + Existing death and unset notes for stack registers are deleted + before processing the insn. */ + +static void +record_reg_life (insn, block, regstack) + rtx insn; + int block; + stack regstack; +{ + rtx note, *note_link; + int n_operands; + + if ((GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN) + || INSN_DELETED_P (insn)) + return; + + /* Strip death notes for stack regs from this insn */ + + note_link = ®_NOTES(insn); + for (note = *note_link; note; note = XEXP (note, 1)) + if (STACK_REG_P (XEXP (note, 0)) + && (REG_NOTE_KIND (note) == REG_DEAD + || REG_NOTE_KIND (note) == REG_UNUSED)) + *note_link = XEXP (note, 1); + else + note_link = &XEXP (note, 1); + + /* Process all patterns in the insn. */ + + n_operands = asm_noperands (PATTERN (insn)); + if (n_operands >= 0) + { + /* This insn is an `asm' with operands. Decode the operands, + decide how many are inputs, and record the life information. */ + + rtx operands[MAX_RECOG_OPERANDS]; + rtx body = PATTERN (insn); + int n_inputs, n_outputs; + char **constraints = (char **) alloca (n_operands * sizeof (char *)); + + decode_asm_operands (body, operands, NULL_PTR, constraints, NULL_PTR); + get_asm_operand_lengths (body, n_operands, &n_inputs, &n_outputs); + record_asm_reg_life (insn, regstack, operands, constraints, + n_inputs, n_outputs); + return; + } + + /* An insn referencing a stack reg has a mode of QImode. */ + if (GET_MODE (insn) == QImode) + { + HARD_REG_SET src, dest; + int regno; + + CLEAR_HARD_REG_SET (src); + CLEAR_HARD_REG_SET (dest); + record_reg_life_pat (PATTERN (insn), &src, &dest); + + for (regno = FIRST_STACK_REG; regno <= LAST_STACK_REG; regno++) + if (! TEST_HARD_REG_BIT (regstack->reg_set, regno)) + { + if (TEST_HARD_REG_BIT (src, regno) + && ! TEST_HARD_REG_BIT (dest, regno)) + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_DEAD, + FP_mode_reg[regno][(int) DFmode], + REG_NOTES (insn)); + else if (TEST_HARD_REG_BIT (dest, regno)) + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_UNUSED, + FP_mode_reg[regno][(int) DFmode], + REG_NOTES (insn)); + } + + AND_COMPL_HARD_REG_SET (regstack->reg_set, dest); + IOR_HARD_REG_SET (regstack->reg_set, src); + } + + /* There might be a reg that is live after a function call. + Initialize it to zero so that the program does not crash. See comment + towards the end of stack_reg_life_analysis(). */ + + if (GET_CODE (insn) == CALL_INSN) + { + int reg = FIRST_FLOAT_REG; + + /* If a stack reg is mentioned in a CALL_INSN, it must be as the + return value. */ + + if (stack_regs_mentioned_p (PATTERN (insn))) + reg++; + + for (; reg <= LAST_STACK_REG; reg++) + if (TEST_HARD_REG_BIT (regstack->reg_set, reg)) + { + rtx init, pat; + + /* The insn will use virtual register numbers, and so + convert_regs is expected to process these. But BLOCK_NUM + cannot be used on these insns, because they do not appear in + block_number[]. */ + + pat = gen_rtx (SET, VOIDmode, FP_mode_reg[reg][(int) DFmode], + CONST0_RTX (DFmode)); + init = emit_insn_after (pat, insn); + PUT_MODE (init, QImode); + + CLEAR_HARD_REG_BIT (regstack->reg_set, reg); + + /* If the CALL_INSN was the end of a block, move the + block_end to point to the new insn. */ + + if (block_end[block] == insn) + block_end[block] = init; + } + + /* Some regs do not survive a CALL */ + + AND_COMPL_HARD_REG_SET (regstack->reg_set, call_used_reg_set); + } +} + +/* Find all basic blocks of the function, which starts with FIRST. + For each JUMP_INSN, build the chain of LABEL_REFS on each CODE_LABEL. */ + +static void +find_blocks (first) + rtx first; +{ + register rtx insn; + register int block; + register RTX_CODE prev_code = BARRIER; + register RTX_CODE code; + + /* Record where all the blocks start and end. + Record which basic blocks control can drop in to. */ + + block = -1; + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + /* Note that this loop must select the same block boundaries + as code in reg_to_stack. */ + + code = GET_CODE (insn); + + if (code == CODE_LABEL + || (prev_code != INSN + && prev_code != CALL_INSN + && prev_code != CODE_LABEL + && (code == INSN || code == CALL_INSN || code == JUMP_INSN))) + { + block_begin[++block] = insn; + block_end[block] = insn; + block_drops_in[block] = prev_code != BARRIER; + } + else if (code == INSN || code == CALL_INSN || code == JUMP_INSN) + block_end[block] = insn; + + BLOCK_NUM (insn) = block; + + if (code == CODE_LABEL) + LABEL_REFS (insn) = insn; /* delete old chain */ + + if (code != NOTE) + prev_code = code; + } + + if (block + 1 != blocks) + abort (); + + /* generate all label references to the corresponding jump insn */ + for (block = 0; block < blocks; block++) + { + insn = block_end[block]; + + if (GET_CODE (insn) == JUMP_INSN) + record_label_references (insn, PATTERN (insn)); + } +} + +/* If current function returns its result in an fp stack register, + return the register number. Otherwise return -1. */ + +static int +stack_result_p (decl) + tree decl; +{ + rtx result = DECL_RTL (DECL_RESULT (decl)); + + if (result != 0 + && !(GET_CODE (result) == REG + && REGNO (result) < FIRST_PSEUDO_REGISTER)) + { +#ifdef FUNCTION_OUTGOING_VALUE + result + = FUNCTION_OUTGOING_VALUE (TREE_TYPE (DECL_RESULT (decl)), decl); +#else + result = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (decl)), decl); +#endif + } + + return STACK_REG_P (result) ? REGNO (result) : -1; +} + +/* Determine the which registers are live at the start of each basic + block of the function whose first insn is FIRST. + + First, if the function returns a real_type, mark the function + return type as live at each return point, as the RTL may not give any + hint that the register is live. + + Then, start with the last block and work back to the first block. + Similarly, work backwards within each block, insn by insn, recording + which regs are die and which are used (and therefore live) in the + hard reg set of block_stack_in[]. + + After processing each basic block, if there is a label at the start + of the block, propagate the live registers to all jumps to this block. + + As a special case, if there are regs live in this block, that are + not live in a block containing a jump to this label, and the block + containing the jump has already been processed, we must propagate this + block's entry register life back to the block containing the jump, and + restart life analysis from there. + + In the worst case, this function may traverse the insns + REG_STACK_SIZE times. This is necessary, since a jump towards the end + of the insns may not know that a reg is live at a target that is early + in the insns. So we back up and start over with the new reg live. + + If there are registers that are live at the start of the function, + insns are emitted to initialize these registers. Something similar is + done after CALL_INSNs in record_reg_life. */ + +static void +stack_reg_life_analysis (first) + rtx first; +{ + int reg, block; + struct stack_def regstack; + + if (current_function_returns_real + && stack_result_p (current_function_decl) >= 0) + { + /* Find all RETURN insns and mark them. */ + + int value_regno = stack_result_p (current_function_decl); + + for (block = blocks - 1; block >= 0; block--) + if (GET_CODE (block_end[block]) == JUMP_INSN + && GET_CODE (PATTERN (block_end[block])) == RETURN) + SET_HARD_REG_BIT (block_out_reg_set[block], value_regno); + + /* Mark of the end of last block if we "fall off" the end of the + function into the epilogue. */ + + if (GET_CODE (block_end[blocks-1]) != JUMP_INSN + || GET_CODE (PATTERN (block_end[blocks-1])) == RETURN) + SET_HARD_REG_BIT (block_out_reg_set[blocks-1], value_regno); + } + + /* now scan all blocks backward for stack register use */ + + block = blocks - 1; + while (block >= 0) + { + register rtx insn, prev; + + /* current register status at last instruction */ + + COPY_HARD_REG_SET (regstack.reg_set, block_out_reg_set[block]); + + prev = block_end[block]; + do + { + insn = prev; + prev = PREV_INSN (insn); + + /* If the insn is a CALL_INSN, we need to ensure that + everything dies. But otherwise don't process unless there + are some stack regs present. */ + + if (GET_MODE (insn) == QImode || GET_CODE (insn) == CALL_INSN) + record_reg_life (insn, block, ®stack); + + } while (insn != block_begin[block]); + + /* Set the state at the start of the block. Mark that no + register mapping information known yet. */ + + COPY_HARD_REG_SET (block_stack_in[block].reg_set, regstack.reg_set); + block_stack_in[block].top = -2; + + /* If there is a label, propagate our register life to all jumps + to this label. */ + + if (GET_CODE (insn) == CODE_LABEL) + { + register rtx label; + int must_restart = 0; + + for (label = LABEL_REFS (insn); label != insn; + label = LABEL_NEXTREF (label)) + { + int jump_block = BLOCK_NUM (CONTAINING_INSN (label)); + + if (jump_block < block) + IOR_HARD_REG_SET (block_out_reg_set[jump_block], + block_stack_in[block].reg_set); + else + { + /* The block containing the jump has already been + processed. If there are registers that were not known + to be live then, but are live now, we must back up + and restart life analysis from that point with the new + life information. */ + + GO_IF_HARD_REG_SUBSET (block_stack_in[block].reg_set, + block_out_reg_set[jump_block], + win); + + IOR_HARD_REG_SET (block_out_reg_set[jump_block], + block_stack_in[block].reg_set); + + block = jump_block; + must_restart = 1; + + win: + ; + } + } + if (must_restart) + continue; + } + + if (block_drops_in[block]) + IOR_HARD_REG_SET (block_out_reg_set[block-1], + block_stack_in[block].reg_set); + + block -= 1; + } + + { + /* If any reg is live at the start of the first block of a + function, then we must guarantee that the reg holds some value by + generating our own "load" of that register. Otherwise a 387 would + fault trying to access an empty register. */ + + HARD_REG_SET empty_regs; + CLEAR_HARD_REG_SET (empty_regs); + GO_IF_HARD_REG_SUBSET (block_stack_in[0].reg_set, empty_regs, + no_live_regs); + } + + /* Load zero into each live register. The fact that a register + appears live at the function start does not necessarily imply an error + in the user program: it merely means that we could not determine that + there wasn't such an error, just as -Wunused sometimes gives + "incorrect" warnings. In those cases, these initializations will do + no harm. + + Note that we are inserting virtual register references here: + these insns must be processed by convert_regs later. Also, these + insns will not be in block_number, so BLOCK_NUM() will fail for them. */ + + for (reg = LAST_STACK_REG; reg >= FIRST_STACK_REG; reg--) + if (TEST_HARD_REG_BIT (block_stack_in[0].reg_set, reg)) + { + rtx init_rtx; + + init_rtx = gen_rtx (SET, VOIDmode, FP_mode_reg[reg][(int) DFmode], + CONST0_RTX (DFmode)); + block_begin[0] = emit_insn_after (init_rtx, first); + PUT_MODE (block_begin[0], QImode); + + CLEAR_HARD_REG_BIT (block_stack_in[0].reg_set, reg); + } + + no_live_regs: + ; +} + +/***************************************************************************** + This section deals with stack register substitution, and forms the second + pass over the RTL. + *****************************************************************************/ + +/* Replace REG, which is a pointer to a stack reg RTX, with an RTX for + the desired hard REGNO. */ + +static void +replace_reg (reg, regno) + rtx *reg; + int regno; +{ + if (regno < FIRST_STACK_REG || regno > LAST_STACK_REG + || ! STACK_REG_P (*reg)) + abort (); + + if (GET_MODE_CLASS (GET_MODE (*reg)) != MODE_FLOAT) + abort (); + + *reg = FP_mode_reg[regno][(int) GET_MODE (*reg)]; +} + +/* Remove a note of type NOTE, which must be found, for register + number REGNO from INSN. Remove only one such note. */ + +static void +remove_regno_note (insn, note, regno) + rtx insn; + enum reg_note note; + int regno; +{ + register rtx *note_link, this; + + note_link = ®_NOTES(insn); + for (this = *note_link; this; this = XEXP (this, 1)) + if (REG_NOTE_KIND (this) == note + && REG_P (XEXP (this, 0)) && REGNO (XEXP (this, 0)) == regno) + { + *note_link = XEXP (this, 1); + return; + } + else + note_link = &XEXP (this, 1); + + abort (); +} + +/* Find the hard register number of virtual register REG in REGSTACK. + The hard register number is relative to the top of the stack. -1 is + returned if the register is not found. */ + +static int +get_hard_regnum (regstack, reg) + stack regstack; + rtx reg; +{ + int i; + + if (! STACK_REG_P (reg)) + abort (); + + for (i = regstack->top; i >= 0; i--) + if (regstack->reg[i] == REGNO (reg)) + break; + + return i >= 0 ? (FIRST_STACK_REG + regstack->top - i) : -1; +} + +/* Delete INSN from the RTL. Mark the insn, but don't remove it from + the chain of insns. Doing so could confuse block_begin and block_end + if this were the only insn in the block. */ + +static void +delete_insn_for_stacker (insn) + rtx insn; +{ + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + INSN_DELETED_P (insn) = 1; +} + +/* Emit an insn to pop virtual register REG before or after INSN. + REGSTACK is the stack state after INSN and is updated to reflect this + pop. WHEN is either emit_insn_before or emit_insn_after. A pop insn + is represented as a SET whose destination is the register to be popped + and source is the top of stack. A death note for the top of stack + cases the movdf pattern to pop. */ + +static rtx +emit_pop_insn (insn, regstack, reg, when) + rtx insn; + stack regstack; + rtx reg; + rtx (*when)(); +{ + rtx pop_insn, pop_rtx; + int hard_regno; + + hard_regno = get_hard_regnum (regstack, reg); + + if (hard_regno < FIRST_STACK_REG) + abort (); + + pop_rtx = gen_rtx (SET, VOIDmode, FP_mode_reg[hard_regno][(int) DFmode], + FP_mode_reg[FIRST_STACK_REG][(int) DFmode]); + + pop_insn = (*when) (pop_rtx, insn); + /* ??? This used to be VOIDmode, but that seems wrong. */ + PUT_MODE (pop_insn, QImode); + + REG_NOTES (pop_insn) = gen_rtx (EXPR_LIST, REG_DEAD, + FP_mode_reg[FIRST_STACK_REG][(int) DFmode], + REG_NOTES (pop_insn)); + + regstack->reg[regstack->top - (hard_regno - FIRST_STACK_REG)] + = regstack->reg[regstack->top]; + regstack->top -= 1; + CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (reg)); + + return pop_insn; +} + +/* Emit an insn before or after INSN to swap virtual register REG with the + top of stack. WHEN should be `emit_insn_before' or `emit_insn_before' + REGSTACK is the stack state before the swap, and is updated to reflect + the swap. A swap insn is represented as a PARALLEL of two patterns: + each pattern moves one reg to the other. + + If REG is already at the top of the stack, no insn is emitted. */ + +static void +emit_swap_insn (insn, regstack, reg) + rtx insn; + stack regstack; + rtx reg; +{ + int hard_regno; + rtx gen_swapdf(); + rtx swap_rtx, swap_insn; + int tmp, other_reg; /* swap regno temps */ + rtx i1; /* the stack-reg insn prior to INSN */ + rtx i1set = NULL_RTX; /* the SET rtx within I1 */ + + hard_regno = get_hard_regnum (regstack, reg); + + if (hard_regno < FIRST_STACK_REG) + abort (); + if (hard_regno == FIRST_STACK_REG) + return; + + other_reg = regstack->top - (hard_regno - FIRST_STACK_REG); + + tmp = regstack->reg[other_reg]; + regstack->reg[other_reg] = regstack->reg[regstack->top]; + regstack->reg[regstack->top] = tmp; + + /* Find the previous insn involving stack regs, but don't go past + any labels, calls or jumps. */ + i1 = prev_nonnote_insn (insn); + while (i1 && GET_CODE (i1) == INSN && GET_MODE (i1) != QImode) + i1 = prev_nonnote_insn (i1); + + if (i1) + i1set = single_set (i1); + + if (i1set) + { + rtx i2; /* the stack-reg insn prior to I1 */ + rtx i1src = *get_true_reg (&SET_SRC (i1set)); + rtx i1dest = *get_true_reg (&SET_DEST (i1set)); + + /* If the previous register stack push was from the reg we are to + swap with, omit the swap. */ + + if (GET_CODE (i1dest) == REG && REGNO (i1dest) == FIRST_STACK_REG + && GET_CODE (i1src) == REG && REGNO (i1src) == hard_regno - 1 + && find_regno_note (i1, REG_DEAD, FIRST_STACK_REG) == NULL_RTX) + return; + + /* If the previous insn wrote to the reg we are to swap with, + omit the swap. */ + + if (GET_CODE (i1dest) == REG && REGNO (i1dest) == hard_regno + && GET_CODE (i1src) == REG && REGNO (i1src) == FIRST_STACK_REG + && find_regno_note (i1, REG_DEAD, FIRST_STACK_REG) == NULL_RTX) + return; + } + + if (GET_RTX_CLASS (GET_CODE (i1)) == 'i' && sets_cc0_p (PATTERN (i1))) + { + i1 = next_nonnote_insn (i1); + if (i1 == insn) + abort (); + } + + swap_rtx = gen_swapdf (FP_mode_reg[hard_regno][(int) DFmode], + FP_mode_reg[FIRST_STACK_REG][(int) DFmode]); + swap_insn = emit_insn_after (swap_rtx, i1); + /* ??? This used to be VOIDmode, but that seems wrong. */ + PUT_MODE (swap_insn, QImode); +} + +/* Handle a move to or from a stack register in PAT, which is in INSN. + REGSTACK is the current stack. */ + +static void +move_for_stack_reg (insn, regstack, pat) + rtx insn; + stack regstack; + rtx pat; +{ + rtx *src = get_true_reg (&SET_SRC (pat)); + rtx *dest = get_true_reg (&SET_DEST (pat)); + rtx note; + + if (STACK_REG_P (*src) && STACK_REG_P (*dest)) + { + /* Write from one stack reg to another. If SRC dies here, then + just change the register mapping and delete the insn. */ + + note = find_regno_note (insn, REG_DEAD, REGNO (*src)); + if (note) + { + int i; + + /* If this is a no-op move, there must not be a REG_DEAD note. */ + if (REGNO (*src) == REGNO (*dest)) + abort (); + + for (i = regstack->top; i >= 0; i--) + if (regstack->reg[i] == REGNO (*src)) + break; + + /* The source must be live, and the dest must be dead. */ + if (i < 0 || get_hard_regnum (regstack, *dest) >= FIRST_STACK_REG) + abort (); + + /* It is possible that the dest is unused after this insn. + If so, just pop the src. */ + + if (find_regno_note (insn, REG_UNUSED, REGNO (*dest))) + { + emit_pop_insn (insn, regstack, *src, emit_insn_after); + + delete_insn_for_stacker (insn); + return; + } + + regstack->reg[i] = REGNO (*dest); + + SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); + CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src)); + + delete_insn_for_stacker (insn); + + return; + } + + /* The source reg does not die. */ + + /* If this appears to be a no-op move, delete it, or else it + will confuse the machine description output patterns. But if + it is REG_UNUSED, we must pop the reg now, as per-insn processing + for REG_UNUSED will not work for deleted insns. */ + + if (REGNO (*src) == REGNO (*dest)) + { + if (find_regno_note (insn, REG_UNUSED, REGNO (*dest))) + emit_pop_insn (insn, regstack, *dest, emit_insn_after); + + delete_insn_for_stacker (insn); + return; + } + + /* The destination ought to be dead */ + if (get_hard_regnum (regstack, *dest) >= FIRST_STACK_REG) + abort (); + + replace_reg (src, get_hard_regnum (regstack, *src)); + + regstack->reg[++regstack->top] = REGNO (*dest); + SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); + replace_reg (dest, FIRST_STACK_REG); + } + else if (STACK_REG_P (*src)) + { + /* Save from a stack reg to MEM, or possibly integer reg. Since + only top of stack may be saved, emit an exchange first if + needs be. */ + + emit_swap_insn (insn, regstack, *src); + + note = find_regno_note (insn, REG_DEAD, REGNO (*src)); + if (note) + { + replace_reg (&XEXP (note, 0), FIRST_STACK_REG); + regstack->top--; + CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src)); + } + + replace_reg (src, FIRST_STACK_REG); + } + else if (STACK_REG_P (*dest)) + { + /* Load from MEM, or possibly integer REG or constant, into the + stack regs. The actual target is always the top of the + stack. The stack mapping is changed to reflect that DEST is + now at top of stack. */ + + /* The destination ought to be dead */ + if (get_hard_regnum (regstack, *dest) >= FIRST_STACK_REG) + abort (); + + if (regstack->top >= REG_STACK_SIZE) + abort (); + + regstack->reg[++regstack->top] = REGNO (*dest); + SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); + replace_reg (dest, FIRST_STACK_REG); + } + else + abort (); +} + +void +swap_rtx_condition (pat) + rtx pat; +{ + register char *fmt; + register int i; + + if (GET_RTX_CLASS (GET_CODE (pat)) == '<') + { + PUT_CODE (pat, swap_condition (GET_CODE (pat))); + return; + } + + fmt = GET_RTX_FORMAT (GET_CODE (pat)); + for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + + for (j = XVECLEN (pat, i) - 1; j >= 0; j--) + swap_rtx_condition (XVECEXP (pat, i, j)); + } + else if (fmt[i] == 'e') + swap_rtx_condition (XEXP (pat, i)); + } +} + +/* Handle a comparison. Special care needs to be taken to avoid + causing comparisons that a 387 cannot do correctly, such as EQ. + + Also, a pop insn may need to be emitted. The 387 does have an + `fcompp' insn that can pop two regs, but it is sometimes too expensive + to do this - a `fcomp' followed by a `fstpl %st(0)' may be easier to + set up. */ + +static void +compare_for_stack_reg (insn, regstack, pat) + rtx insn; + stack regstack; + rtx pat; +{ + rtx *src1, *src2; + rtx src1_note, src2_note; + + src1 = get_true_reg (&XEXP (SET_SRC (pat), 0)); + src2 = get_true_reg (&XEXP (SET_SRC (pat), 1)); + + /* ??? If fxch turns out to be cheaper than fstp, give priority to + registers that die in this insn - move those to stack top first. */ + if (! STACK_REG_P (*src1) + || (STACK_REG_P (*src2) + && get_hard_regnum (regstack, *src2) == FIRST_STACK_REG)) + { + rtx temp, next; + + temp = XEXP (SET_SRC (pat), 0); + XEXP (SET_SRC (pat), 0) = XEXP (SET_SRC (pat), 1); + XEXP (SET_SRC (pat), 1) = temp; + + src1 = get_true_reg (&XEXP (SET_SRC (pat), 0)); + src2 = get_true_reg (&XEXP (SET_SRC (pat), 1)); + + next = next_cc0_user (insn); + if (next == NULL_RTX) + abort (); + + swap_rtx_condition (PATTERN (next)); + INSN_CODE (next) = -1; + INSN_CODE (insn) = -1; + } + + /* We will fix any death note later. */ + + src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); + + if (STACK_REG_P (*src2)) + src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); + else + src2_note = NULL_RTX; + + emit_swap_insn (insn, regstack, *src1); + + replace_reg (src1, FIRST_STACK_REG); + + if (STACK_REG_P (*src2)) + replace_reg (src2, get_hard_regnum (regstack, *src2)); + + if (src1_note) + { + CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (XEXP (src1_note, 0))); + replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); + regstack->top--; + } + + /* If the second operand dies, handle that. But if the operands are + the same stack register, don't bother, because only one death is + needed, and it was just handled. */ + + if (src2_note + && ! (STACK_REG_P (*src1) && STACK_REG_P (*src2) + && REGNO (*src1) == REGNO (*src2))) + { + /* As a special case, two regs may die in this insn if src2 is + next to top of stack and the top of stack also dies. Since + we have already popped src1, "next to top of stack" is really + at top (FIRST_STACK_REG) now. */ + + if (get_hard_regnum (regstack, XEXP (src2_note, 0)) == FIRST_STACK_REG + && src1_note) + { + CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (XEXP (src2_note, 0))); + replace_reg (&XEXP (src2_note, 0), FIRST_STACK_REG + 1); + regstack->top--; + } + else + { + /* The 386 can only represent death of the first operand in + the case handled above. In all other cases, emit a separate + pop and remove the death note from here. */ + + link_cc0_insns (insn); + + remove_regno_note (insn, REG_DEAD, REGNO (XEXP (src2_note, 0))); + + emit_pop_insn (insn, regstack, XEXP (src2_note, 0), + emit_insn_after); + } + } +} + +/* Substitute new registers in PAT, which is part of INSN. REGSTACK + is the current register layout. */ + +static void +subst_stack_regs_pat (insn, regstack, pat) + rtx insn; + stack regstack; + rtx pat; +{ + rtx *dest, *src; + rtx *src1 = (rtx *) NULL_PTR, *src2; + rtx src1_note, src2_note; + + if (GET_CODE (pat) != SET) + return; + + dest = get_true_reg (&SET_DEST (pat)); + src = get_true_reg (&SET_SRC (pat)); + + /* See if this is a `movM' pattern, and handle elsewhere if so. */ + + if (*dest != cc0_rtx + && (STACK_REG_P (*src) + || (STACK_REG_P (*dest) + && (GET_CODE (*src) == REG || GET_CODE (*src) == MEM + || GET_CODE (*src) == CONST_DOUBLE)))) + move_for_stack_reg (insn, regstack, pat); + else + switch (GET_CODE (SET_SRC (pat))) + { + case COMPARE: + compare_for_stack_reg (insn, regstack, pat); + break; + + case CALL: + regstack->reg[++regstack->top] = REGNO (*dest); + SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); + replace_reg (dest, FIRST_STACK_REG); + break; + + case REG: + /* This is a `tstM2' case. */ + if (*dest != cc0_rtx) + abort (); + + src1 = src; + + /* Fall through. */ + + case FLOAT_TRUNCATE: + case SQRT: + case ABS: + case NEG: + /* These insns only operate on the top of the stack. DEST might + be cc0_rtx if we're processing a tstM pattern. Also, it's + possible that the tstM case results in a REG_DEAD note on the + source. */ + + if (src1 == 0) + src1 = get_true_reg (&XEXP (SET_SRC (pat), 0)); + + emit_swap_insn (insn, regstack, *src1); + + src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); + + if (STACK_REG_P (*dest)) + replace_reg (dest, FIRST_STACK_REG); + + if (src1_note) + { + replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); + regstack->top--; + CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src1)); + } + + replace_reg (src1, FIRST_STACK_REG); + + break; + + case MINUS: + case DIV: + /* On i386, reversed forms of subM3 and divM3 exist for + MODE_FLOAT, so the same code that works for addM3 and mulM3 + can be used. */ + case MULT: + case PLUS: + /* These insns can accept the top of stack as a destination + from a stack reg or mem, or can use the top of stack as a + source and some other stack register (possibly top of stack) + as a destination. */ + + src1 = get_true_reg (&XEXP (SET_SRC (pat), 0)); + src2 = get_true_reg (&XEXP (SET_SRC (pat), 1)); + + /* We will fix any death note later. */ + + if (STACK_REG_P (*src1)) + src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); + else + src1_note = NULL_RTX; + if (STACK_REG_P (*src2)) + src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); + else + src2_note = NULL_RTX; + + /* If either operand is not a stack register, then the dest + must be top of stack. */ + + if (! STACK_REG_P (*src1) || ! STACK_REG_P (*src2)) + emit_swap_insn (insn, regstack, *dest); + else + { + /* Both operands are REG. If neither operand is already + at the top of stack, choose to make the one that is the dest + the new top of stack. */ + + int src1_hard_regnum, src2_hard_regnum; + + src1_hard_regnum = get_hard_regnum (regstack, *src1); + src2_hard_regnum = get_hard_regnum (regstack, *src2); + if (src1_hard_regnum == -1 || src2_hard_regnum == -1) + abort (); + + if (src1_hard_regnum != FIRST_STACK_REG + && src2_hard_regnum != FIRST_STACK_REG) + emit_swap_insn (insn, regstack, *dest); + } + + if (STACK_REG_P (*src1)) + replace_reg (src1, get_hard_regnum (regstack, *src1)); + if (STACK_REG_P (*src2)) + replace_reg (src2, get_hard_regnum (regstack, *src2)); + + if (src1_note) + { + /* If the register that dies is at the top of stack, then + the destination is somewhere else - merely substitute it. + But if the reg that dies is not at top of stack, then + move the top of stack to the dead reg, as though we had + done the insn and then a store-with-pop. */ + + if (REGNO (XEXP (src1_note, 0)) == regstack->reg[regstack->top]) + { + SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); + replace_reg (dest, get_hard_regnum (regstack, *dest)); + } + else + { + int regno = get_hard_regnum (regstack, XEXP (src1_note, 0)); + + SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); + replace_reg (dest, regno); + + regstack->reg[regstack->top - (regno - FIRST_STACK_REG)] + = regstack->reg[regstack->top]; + } + + CLEAR_HARD_REG_BIT (regstack->reg_set, + REGNO (XEXP (src1_note, 0))); + replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); + regstack->top--; + } + else if (src2_note) + { + if (REGNO (XEXP (src2_note, 0)) == regstack->reg[regstack->top]) + { + SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); + replace_reg (dest, get_hard_regnum (regstack, *dest)); + } + else + { + int regno = get_hard_regnum (regstack, XEXP (src2_note, 0)); + + SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); + replace_reg (dest, regno); + + regstack->reg[regstack->top - (regno - FIRST_STACK_REG)] + = regstack->reg[regstack->top]; + } + + CLEAR_HARD_REG_BIT (regstack->reg_set, + REGNO (XEXP (src2_note, 0))); + replace_reg (&XEXP (src2_note, 0), FIRST_STACK_REG); + regstack->top--; + } + else + { + SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); + replace_reg (dest, get_hard_regnum (regstack, *dest)); + } + + break; + + case UNSPEC: + switch (XINT (SET_SRC (pat), 1)) + { + case 1: /* sin */ + case 2: /* cos */ + /* These insns only operate on the top of the stack. */ + + src1 = get_true_reg (&XVECEXP (SET_SRC (pat), 0, 0)); + + emit_swap_insn (insn, regstack, *src1); + + src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); + + if (STACK_REG_P (*dest)) + replace_reg (dest, FIRST_STACK_REG); + + if (src1_note) + { + replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); + regstack->top--; + CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src1)); + } + + replace_reg (src1, FIRST_STACK_REG); + + break; + + default: + abort (); + } + break; + + default: + abort (); + } +} + +/* Substitute hard regnums for any stack regs in INSN, which has + N_INPUTS inputs and N_OUTPUTS outputs. REGSTACK is the stack info + before the insn, and is updated with changes made here. CONSTRAINTS is + an array of the constraint strings used in the asm statement. + + OPERANDS is an array of the operands, and OPERANDS_LOC is a + parallel array of where the operands were found. The output operands + all precede the input operands. + + There are several requirements and assumptions about the use of + stack-like regs in asm statements. These rules are enforced by + record_asm_stack_regs; see comments there for details. Any + asm_operands left in the RTL at this point may be assume to meet the + requirements, since record_asm_stack_regs removes any problem asm. */ + +static void +subst_asm_stack_regs (insn, regstack, operands, operands_loc, constraints, + n_inputs, n_outputs) + rtx insn; + stack regstack; + rtx *operands, **operands_loc; + char **constraints; + int n_inputs, n_outputs; +{ + int n_operands = n_inputs + n_outputs; + int first_input = n_outputs; + rtx body = PATTERN (insn); + + int *operand_matches = (int *) alloca (n_operands * sizeof (int *)); + enum reg_class *operand_class + = (enum reg_class *) alloca (n_operands * sizeof (enum reg_class *)); + + rtx *note_reg; /* Array of note contents */ + rtx **note_loc; /* Address of REG field of each note */ + enum reg_note *note_kind; /* The type of each note */ + + rtx *clobber_reg; + rtx **clobber_loc; + + struct stack_def temp_stack; + int n_notes; + int n_clobbers; + rtx note; + int i; + + /* Find out what the constraints required. If no constraint + alternative matches, that is a compiler bug: we should have caught + such an insn during the life analysis pass (and reload should have + caught it regardless). */ + + i = constrain_asm_operands (n_operands, operands, constraints, + operand_matches, operand_class); + if (i < 0) + abort (); + + /* Strip SUBREGs here to make the following code simpler. */ + for (i = 0; i < n_operands; i++) + if (GET_CODE (operands[i]) == SUBREG + && GET_CODE (SUBREG_REG (operands[i])) == REG) + { + operands_loc[i] = & SUBREG_REG (operands[i]); + operands[i] = SUBREG_REG (operands[i]); + } + + /* Set up NOTE_REG, NOTE_LOC and NOTE_KIND. */ + + for (i = 0, note = REG_NOTES (insn); note; note = XEXP (note, 1)) + i++; + + note_reg = (rtx *) alloca (i * sizeof (rtx)); + note_loc = (rtx **) alloca (i * sizeof (rtx *)); + note_kind = (enum reg_note *) alloca (i * sizeof (enum reg_note)); + + n_notes = 0; + for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) + { + rtx reg = XEXP (note, 0); + rtx *loc = & XEXP (note, 0); + + if (GET_CODE (reg) == SUBREG && GET_CODE (SUBREG_REG (reg)) == REG) + { + loc = & SUBREG_REG (reg); + reg = SUBREG_REG (reg); + } + + if (STACK_REG_P (reg) + && (REG_NOTE_KIND (note) == REG_DEAD + || REG_NOTE_KIND (note) == REG_UNUSED)) + { + note_reg[n_notes] = reg; + note_loc[n_notes] = loc; + note_kind[n_notes] = REG_NOTE_KIND (note); + n_notes++; + } + } + + /* Set up CLOBBER_REG and CLOBBER_LOC. */ + + n_clobbers = 0; + + if (GET_CODE (body) == PARALLEL) + { + clobber_reg = (rtx *) alloca (XVECLEN (body, 0) * sizeof (rtx *)); + clobber_loc = (rtx **) alloca (XVECLEN (body, 0) * sizeof (rtx **)); + + for (i = 0; i < XVECLEN (body, 0); i++) + if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) + { + rtx clobber = XVECEXP (body, 0, i); + rtx reg = XEXP (clobber, 0); + rtx *loc = & XEXP (clobber, 0); + + if (GET_CODE (reg) == SUBREG && GET_CODE (SUBREG_REG (reg)) == REG) + { + loc = & SUBREG_REG (reg); + reg = SUBREG_REG (reg); + } + + if (STACK_REG_P (reg)) + { + clobber_reg[n_clobbers] = reg; + clobber_loc[n_clobbers] = loc; + n_clobbers++; + } + } + } + + bcopy (regstack, &temp_stack, sizeof (temp_stack)); + + /* Put the input regs into the desired place in TEMP_STACK. */ + + for (i = first_input; i < first_input + n_inputs; i++) + if (STACK_REG_P (operands[i]) + && reg_class_subset_p (operand_class[i], FLOAT_REGS) + && operand_class[i] != FLOAT_REGS) + { + /* If an operand needs to be in a particular reg in + FLOAT_REGS, the constraint was either 't' or 'u'. Since + these constraints are for single register classes, and reload + guaranteed that operand[i] is already in that class, we can + just use REGNO (operands[i]) to know which actual reg this + operand needs to be in. */ + + int regno = get_hard_regnum (&temp_stack, operands[i]); + + if (regno < 0) + abort (); + + if (regno != REGNO (operands[i])) + { + /* operands[i] is not in the right place. Find it + and swap it with whatever is already in I's place. + K is where operands[i] is now. J is where it should + be. */ + int j, k, temp; + + k = temp_stack.top - (regno - FIRST_STACK_REG); + j = (temp_stack.top + - (REGNO (operands[i]) - FIRST_STACK_REG)); + + temp = temp_stack.reg[k]; + temp_stack.reg[k] = temp_stack.reg[j]; + temp_stack.reg[j] = temp; + } + } + + /* emit insns before INSN to make sure the reg-stack is in the right + order. */ + + change_stack (insn, regstack, &temp_stack, emit_insn_before); + + /* Make the needed input register substitutions. Do death notes and + clobbers too, because these are for inputs, not outputs. */ + + for (i = first_input; i < first_input + n_inputs; i++) + if (STACK_REG_P (operands[i])) + { + int regnum = get_hard_regnum (regstack, operands[i]); + + if (regnum < 0) + abort (); + + replace_reg (operands_loc[i], regnum); + } + + for (i = 0; i < n_notes; i++) + if (note_kind[i] == REG_DEAD) + { + int regnum = get_hard_regnum (regstack, note_reg[i]); + + if (regnum < 0) + abort (); + + replace_reg (note_loc[i], regnum); + } + + for (i = 0; i < n_clobbers; i++) + { + /* It's OK for a CLOBBER to reference a reg that is not live. + Don't try to replace it in that case. */ + int regnum = get_hard_regnum (regstack, clobber_reg[i]); + + if (regnum >= 0) + { + /* Sigh - clobbers always have QImode. But replace_reg knows + that these regs can't be MODE_INT and will abort. Just put + the right reg there without calling replace_reg. */ + + *clobber_loc[i] = FP_mode_reg[regnum][(int) DFmode]; + } + } + + /* Now remove from REGSTACK any inputs that the asm implicitly popped. */ + + for (i = first_input; i < first_input + n_inputs; i++) + if (STACK_REG_P (operands[i])) + { + /* An input reg is implicitly popped if it is tied to an + output, or if there is a CLOBBER for it. */ + int j; + + for (j = 0; j < n_clobbers; j++) + if (operands_match_p (clobber_reg[j], operands[i])) + break; + + if (j < n_clobbers || operand_matches[i] >= 0) + { + /* operands[i] might not be at the top of stack. But that's OK, + because all we need to do is pop the right number of regs + off of the top of the reg-stack. record_asm_stack_regs + guaranteed that all implicitly popped regs were grouped + at the top of the reg-stack. */ + + CLEAR_HARD_REG_BIT (regstack->reg_set, + regstack->reg[regstack->top]); + regstack->top--; + } + } + + /* Now add to REGSTACK any outputs that the asm implicitly pushed. + Note that there isn't any need to substitute register numbers. + ??? Explain why this is true. */ + + for (i = LAST_STACK_REG; i >= FIRST_STACK_REG; i--) + { + /* See if there is an output for this hard reg. */ + int j; + + for (j = 0; j < n_outputs; j++) + if (STACK_REG_P (operands[j]) && REGNO (operands[j]) == i) + { + regstack->reg[++regstack->top] = i; + SET_HARD_REG_BIT (regstack->reg_set, i); + break; + } + } + + /* Now emit a pop insn for any REG_UNUSED output, or any REG_DEAD + input that the asm didn't implicitly pop. If the asm didn't + implicitly pop an input reg, that reg will still be live. + + Note that we can't use find_regno_note here: the register numbers + in the death notes have already been substituted. */ + + for (i = 0; i < n_outputs; i++) + if (STACK_REG_P (operands[i])) + { + int j; + + for (j = 0; j < n_notes; j++) + if (REGNO (operands[i]) == REGNO (note_reg[j]) + && note_kind[j] == REG_UNUSED) + { + insn = emit_pop_insn (insn, regstack, operands[i], + emit_insn_after); + break; + } + } + + for (i = first_input; i < first_input + n_inputs; i++) + if (STACK_REG_P (operands[i])) + { + int j; + + for (j = 0; j < n_notes; j++) + if (REGNO (operands[i]) == REGNO (note_reg[j]) + && note_kind[j] == REG_DEAD + && TEST_HARD_REG_BIT (regstack->reg_set, REGNO (operands[i]))) + { + insn = emit_pop_insn (insn, regstack, operands[i], + emit_insn_after); + break; + } + } +} + +/* Substitute stack hard reg numbers for stack virtual registers in + INSN. Non-stack register numbers are not changed. REGSTACK is the + current stack content. Insns may be emitted as needed to arrange the + stack for the 387 based on the contents of the insn. */ + +static void +subst_stack_regs (insn, regstack) + rtx insn; + stack regstack; +{ + register rtx *note_link, note; + register int i; + int n_operands; + + if ((GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN) + || INSN_DELETED_P (insn)) + return; + + /* The stack should be empty at a call. */ + + if (GET_CODE (insn) == CALL_INSN) + for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) + if (TEST_HARD_REG_BIT (regstack->reg_set, i)) + abort (); + + /* Do the actual substitution if any stack regs are mentioned. + Since we only record whether entire insn mentions stack regs, and + subst_stack_regs_pat only works for patterns that contain stack regs, + we must check each pattern in a parallel here. A call_value_pop could + fail otherwise. */ + + if (GET_MODE (insn) == QImode) + { + n_operands = asm_noperands (PATTERN (insn)); + if (n_operands >= 0) + { + /* This insn is an `asm' with operands. Decode the operands, + decide how many are inputs, and do register substitution. + Any REG_UNUSED notes will be handled by subst_asm_stack_regs. */ + + rtx operands[MAX_RECOG_OPERANDS]; + rtx *operands_loc[MAX_RECOG_OPERANDS]; + rtx body = PATTERN (insn); + int n_inputs, n_outputs; + char **constraints + = (char **) alloca (n_operands * sizeof (char *)); + + decode_asm_operands (body, operands, operands_loc, + constraints, NULL_PTR); + get_asm_operand_lengths (body, n_operands, &n_inputs, &n_outputs); + subst_asm_stack_regs (insn, regstack, operands, operands_loc, + constraints, n_inputs, n_outputs); + return; + } + + if (GET_CODE (PATTERN (insn)) == PARALLEL) + for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) + { + if (stack_regs_mentioned_p (XVECEXP (PATTERN (insn), 0, i))) + subst_stack_regs_pat (insn, regstack, + XVECEXP (PATTERN (insn), 0, i)); + } + else + subst_stack_regs_pat (insn, regstack, PATTERN (insn)); + } + + /* subst_stack_regs_pat may have deleted a no-op insn. If so, any + REG_UNUSED will already have been dealt with, so just return. */ + + if (INSN_DELETED_P (insn)) + return; + + /* If there is a REG_UNUSED note on a stack register on this insn, + the indicated reg must be popped. The REG_UNUSED note is removed, + since the form of the newly emitted pop insn references the reg, + making it no longer `unset'. */ + + note_link = ®_NOTES(insn); + for (note = *note_link; note; note = XEXP (note, 1)) + if (REG_NOTE_KIND (note) == REG_UNUSED && STACK_REG_P (XEXP (note, 0))) + { + *note_link = XEXP (note, 1); + insn = emit_pop_insn (insn, regstack, XEXP (note, 0), emit_insn_after); + } + else + note_link = &XEXP (note, 1); +} + +/* Change the organization of the stack so that it fits a new basic + block. Some registers might have to be popped, but there can never be + a register live in the new block that is not now live. + + Insert any needed insns before or after INSN. WHEN is emit_insn_before + or emit_insn_after. OLD is the original stack layout, and NEW is + the desired form. OLD is updated to reflect the code emitted, ie, it + will be the same as NEW upon return. + + This function will not preserve block_end[]. But that information + is no longer needed once this has executed. */ + +static void +change_stack (insn, old, new, when) + rtx insn; + stack old; + stack new; + rtx (*when)(); +{ + int reg; + + /* We will be inserting new insns "backwards", by calling emit_insn_before. + If we are to insert after INSN, find the next insn, and insert before + it. */ + + if (when == emit_insn_after) + insn = NEXT_INSN (insn); + + /* Pop any registers that are not needed in the new block. */ + + for (reg = old->top; reg >= 0; reg--) + if (! TEST_HARD_REG_BIT (new->reg_set, old->reg[reg])) + emit_pop_insn (insn, old, FP_mode_reg[old->reg[reg]][(int) DFmode], + emit_insn_before); + + if (new->top == -2) + { + /* If the new block has never been processed, then it can inherit + the old stack order. */ + + new->top = old->top; + bcopy (old->reg, new->reg, sizeof (new->reg)); + } + else + { + /* This block has been entered before, and we must match the + previously selected stack order. */ + + /* By now, the only difference should be the order of the stack, + not their depth or liveliness. */ + + GO_IF_HARD_REG_EQUAL (old->reg_set, new->reg_set, win); + + abort (); + + win: + + if (old->top != new->top) + abort (); + + /* Loop here emitting swaps until the stack is correct. The + worst case number of swaps emitted is N + 2, where N is the + depth of the stack. In some cases, the reg at the top of + stack may be correct, but swapped anyway in order to fix + other regs. But since we never swap any other reg away from + its correct slot, this algorithm will converge. */ + + do + { + /* Swap the reg at top of stack into the position it is + supposed to be in, until the correct top of stack appears. */ + + while (old->reg[old->top] != new->reg[new->top]) + { + for (reg = new->top; reg >= 0; reg--) + if (new->reg[reg] == old->reg[old->top]) + break; + + if (reg == -1) + abort (); + + emit_swap_insn (insn, old, + FP_mode_reg[old->reg[reg]][(int) DFmode]); + } + + /* See if any regs remain incorrect. If so, bring an + incorrect reg to the top of stack, and let the while loop + above fix it. */ + + for (reg = new->top; reg >= 0; reg--) + if (new->reg[reg] != old->reg[reg]) + { + emit_swap_insn (insn, old, + FP_mode_reg[old->reg[reg]][(int) DFmode]); + break; + } + } while (reg >= 0); + + /* At this point there must be no differences. */ + + for (reg = old->top; reg >= 0; reg--) + if (old->reg[reg] != new->reg[reg]) + abort (); + } +} + +/* Check PAT, which points to RTL in INSN, for a LABEL_REF. If it is + found, ensure that a jump from INSN to the code_label to which the + label_ref points ends up with the same stack as that at the + code_label. Do this by inserting insns just before the code_label to + pop and rotate the stack until it is in the correct order. REGSTACK + is the order of the register stack in INSN. + + Any code that is emitted here must not be later processed as part + of any block, as it will already contain hard register numbers. */ + +static void +goto_block_pat (insn, regstack, pat) + rtx insn; + stack regstack; + rtx pat; +{ + rtx label; + rtx new_jump, new_label, new_barrier; + rtx *ref; + stack label_stack; + struct stack_def temp_stack; + int reg; + + if (GET_CODE (pat) != LABEL_REF) + { + int i, j; + char *fmt = GET_RTX_FORMAT (GET_CODE (pat)); + + for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + goto_block_pat (insn, regstack, XEXP (pat, i)); + if (fmt[i] == 'E') + for (j = 0; j < XVECLEN (pat, i); j++) + goto_block_pat (insn, regstack, XVECEXP (pat, i, j)); + } + return; + } + + label = XEXP (pat, 0); + if (GET_CODE (label) != CODE_LABEL) + abort (); + + /* First, see if in fact anything needs to be done to the stack at all. */ + + label_stack = &block_stack_in[BLOCK_NUM (label)]; + + if (label_stack->top == -2) + { + /* If the target block hasn't had a stack order selected, then + we need merely ensure that no pops are needed. */ + + for (reg = regstack->top; reg >= 0; reg--) + if (! TEST_HARD_REG_BIT (label_stack->reg_set, regstack->reg[reg])) + break; + + if (reg == -1) + { + /* change_stack will not emit any code in this case. */ + + change_stack (label, regstack, label_stack, emit_insn_after); + return; + } + } + else if (label_stack->top == regstack->top) + { + for (reg = label_stack->top; reg >= 0; reg--) + if (label_stack->reg[reg] != regstack->reg[reg]) + break; + + if (reg == -1) + return; + } + + /* At least one insn will need to be inserted before label. Insert + a jump around the code we are about to emit. Emit a label for the new + code, and point the original insn at this new label. We can't use + redirect_jump here, because we're using fld[4] of the code labels as + LABEL_REF chains, no NUSES counters. */ + + new_jump = emit_jump_insn_before (gen_jump (label), label); + record_label_references (new_jump, PATTERN (new_jump)); + JUMP_LABEL (new_jump) = label; + + new_barrier = emit_barrier_after (new_jump); + + new_label = gen_label_rtx (); + emit_label_after (new_label, new_barrier); + LABEL_REFS (new_label) = new_label; + + /* The old label_ref will no longer point to the code_label if now uses, + so strip the label_ref from the code_label's chain of references. */ + + for (ref = &LABEL_REFS (label); *ref != label; ref = &LABEL_NEXTREF (*ref)) + if (*ref == pat) + break; + + if (*ref == label) + abort (); + + *ref = LABEL_NEXTREF (*ref); + + XEXP (pat, 0) = new_label; + record_label_references (insn, PATTERN (insn)); + + if (JUMP_LABEL (insn) == label) + JUMP_LABEL (insn) = new_label; + + /* Now emit the needed code. */ + + temp_stack = *regstack; + + change_stack (new_label, &temp_stack, label_stack, emit_insn_after); +} + +/* Traverse all basic blocks in a function, converting the register + references in each insn from the "flat" register file that gcc uses, to + the stack-like registers the 387 uses. */ + +static void +convert_regs () +{ + register int block, reg; + register rtx insn, next; + struct stack_def regstack; + + for (block = 0; block < blocks; block++) + { + if (block_stack_in[block].top == -2) + { + /* This block has not been previously encountered. Choose a + default mapping for any stack regs live on entry */ + + block_stack_in[block].top = -1; + + for (reg = LAST_STACK_REG; reg >= FIRST_STACK_REG; reg--) + if (TEST_HARD_REG_BIT (block_stack_in[block].reg_set, reg)) + block_stack_in[block].reg[++block_stack_in[block].top] = reg; + } + + /* Process all insns in this block. Keep track of `next' here, + so that we don't process any insns emitted while making + substitutions in INSN. */ + + next = block_begin[block]; + regstack = block_stack_in[block]; + do + { + insn = next; + next = NEXT_INSN (insn); + + /* Don't bother processing unless there is a stack reg + mentioned. + + ??? For now, process CALL_INSNs too to make sure that the + stack regs are dead after a call. Remove this eventually. */ + + if (GET_MODE (insn) == QImode || GET_CODE (insn) == CALL_INSN) + subst_stack_regs (insn, ®stack); + + } while (insn != block_end[block]); + + /* Something failed if the stack life doesn't match. */ + + GO_IF_HARD_REG_EQUAL (regstack.reg_set, block_out_reg_set[block], win); + + abort (); + + win: + + /* Adjust the stack of this block on exit to match the stack of + the target block, or copy stack information into stack of + jump target if the target block's stack order hasn't been set + yet. */ + + if (GET_CODE (insn) == JUMP_INSN) + goto_block_pat (insn, ®stack, PATTERN (insn)); + + /* Likewise handle the case where we fall into the next block. */ + + if ((block < blocks - 1) && block_drops_in[block+1]) + change_stack (insn, ®stack, &block_stack_in[block+1], + emit_insn_after); + } + + /* If the last basic block is the end of a loop, and that loop has + regs live at its start, then the last basic block will have regs live + at its end that need to be popped before the function returns. */ + + for (reg = regstack.top; reg >= 0; reg--) + if (! current_function_returns_real + || regstack.reg[reg] != FIRST_STACK_REG) + insn = emit_pop_insn (insn, ®stack, + FP_mode_reg[regstack.reg[reg]][(int) DFmode], + emit_insn_after); +} + +/* Check expression PAT, which is in INSN, for label references. if + one is found, print the block number of destination to FILE. */ + +static void +print_blocks (file, insn, pat) + FILE *file; + rtx insn, pat; +{ + register RTX_CODE code = GET_CODE (pat); + register int i; + register char *fmt; + + if (code == LABEL_REF) + { + register rtx label = XEXP (pat, 0); + + if (GET_CODE (label) != CODE_LABEL) + abort (); + + fprintf (file, " %d", BLOCK_NUM (label)); + + return; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + print_blocks (file, insn, XEXP (pat, i)); + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (pat, i); j++) + print_blocks (file, insn, XVECEXP (pat, i, j)); + } + } +} + +/* Write information about stack registers and stack blocks into FILE. + This is part of making a debugging dump. */ +static void +dump_stack_info (file) + FILE *file; +{ + register int block; + + fprintf (file, "\n%d stack blocks.\n", blocks); + for (block = 0; block < blocks; block++) + { + register rtx head, jump, end; + register int regno; + + fprintf (file, "\nStack block %d: first insn %d, last %d.\n", + block, INSN_UID (block_begin[block]), + INSN_UID (block_end[block])); + + head = block_begin[block]; + + fprintf (file, "Reached from blocks: "); + if (GET_CODE (head) == CODE_LABEL) + for (jump = LABEL_REFS (head); + jump != head; + jump = LABEL_NEXTREF (jump)) + { + register int from_block = BLOCK_NUM (CONTAINING_INSN (jump)); + fprintf (file, " %d", from_block); + } + if (block_drops_in[block]) + fprintf (file, " previous"); + + fprintf (file, "\nlive stack registers on block entry: "); + for (regno = FIRST_STACK_REG; regno <= LAST_STACK_REG ; regno++) + { + if (TEST_HARD_REG_BIT (block_stack_in[block].reg_set, regno)) + fprintf (file, "%d ", regno); + } + + fprintf (file, "\nlive stack registers on block exit: "); + for (regno = FIRST_STACK_REG; regno <= LAST_STACK_REG ; regno++) + { + if (TEST_HARD_REG_BIT (block_out_reg_set[block], regno)) + fprintf (file, "%d ", regno); + } + + end = block_end[block]; + + fprintf (file, "\nJumps to blocks: "); + if (GET_CODE (end) == JUMP_INSN) + print_blocks (file, end, PATTERN (end)); + + if (block + 1 < blocks && block_drops_in[block+1]) + fprintf (file, " next"); + else if (block + 1 == blocks + || (GET_CODE (end) == JUMP_INSN + && GET_CODE (PATTERN (end)) == RETURN)) + fprintf (file, " return"); + + fprintf (file, "\n"); + } +} +#endif /* STACK_REGS */ diff --git a/gnu/usr.bin/cc/lib/regclass.c b/gnu/usr.bin/cc/lib/regclass.c new file mode 100644 index 000000000000..196035597246 --- /dev/null +++ b/gnu/usr.bin/cc/lib/regclass.c @@ -0,0 +1,1673 @@ +/* Compute register class preferences for pseudo-registers. + Copyright (C) 1987, 1988, 1991, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This file contains two passes of the compiler: reg_scan and reg_class. + It also defines some tables of information about the hardware registers + and a function init_reg_sets to initialize the tables. */ + +#include "config.h" +#include "rtl.h" +#include "hard-reg-set.h" +#include "flags.h" +#include "basic-block.h" +#include "regs.h" +#include "insn-config.h" +#include "recog.h" +#include "reload.h" +#include "real.h" + +#ifndef REGISTER_MOVE_COST +#define REGISTER_MOVE_COST(x, y) 2 +#endif + +#ifndef MEMORY_MOVE_COST +#define MEMORY_MOVE_COST(x) 4 +#endif + +/* If we have auto-increment or auto-decrement and we can have secondary + reloads, we are not allowed to use classes requiring secondary + reloads for psuedos auto-incremented since reload can't handle it. */ + +#ifdef AUTO_INC_DEC +#if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) +#define FORBIDDEN_INC_DEC_CLASSES +#endif +#endif + +/* Register tables used by many passes. */ + +/* Indexed by hard register number, contains 1 for registers + that are fixed use (stack pointer, pc, frame pointer, etc.). + These are the registers that cannot be used to allocate + a pseudo reg whose life does not cross calls. */ + +char fixed_regs[FIRST_PSEUDO_REGISTER]; + +/* Same info as a HARD_REG_SET. */ + +HARD_REG_SET fixed_reg_set; + +/* Data for initializing the above. */ + +static char initial_fixed_regs[] = FIXED_REGISTERS; + +/* Indexed by hard register number, contains 1 for registers + that are fixed use or are clobbered by function calls. + These are the registers that cannot be used to allocate + a pseudo reg whose life crosses calls. */ + +char call_used_regs[FIRST_PSEUDO_REGISTER]; + +/* Same info as a HARD_REG_SET. */ + +HARD_REG_SET call_used_reg_set; + +/* Data for initializing the above. */ + +static char initial_call_used_regs[] = CALL_USED_REGISTERS; + +/* Indexed by hard register number, contains 1 for registers that are + fixed use -- i.e. in fixed_regs -- or a function value return register + or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the + registers that cannot hold quantities across calls even if we are + willing to save and restore them. */ + +char call_fixed_regs[FIRST_PSEUDO_REGISTER]; + +/* The same info as a HARD_REG_SET. */ + +HARD_REG_SET call_fixed_reg_set; + +/* Number of non-fixed registers. */ + +int n_non_fixed_regs; + +/* Indexed by hard register number, contains 1 for registers + that are being used for global register decls. + These must be exempt from ordinary flow analysis + and are also considered fixed. */ + +char global_regs[FIRST_PSEUDO_REGISTER]; + +/* Table of register numbers in the order in which to try to use them. */ +#ifdef REG_ALLOC_ORDER +int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; +#endif + +/* For each reg class, a HARD_REG_SET saying which registers are in it. */ + +HARD_REG_SET reg_class_contents[N_REG_CLASSES]; + +/* The same information, but as an array of unsigned ints. We copy from + these unsigned ints to the table above. We do this so the tm.h files + do not have to be aware of the wordsize for machines with <= 64 regs. */ + +#define N_REG_INTS \ + ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) + +static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] + = REG_CLASS_CONTENTS; + +/* For each reg class, number of regs it contains. */ + +int reg_class_size[N_REG_CLASSES]; + +/* For each reg class, table listing all the containing classes. */ + +enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; + +/* For each reg class, table listing all the classes contained in it. */ + +enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; + +/* For each pair of reg classes, + a largest reg class contained in their union. */ + +enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; + +/* For each pair of reg classes, + the smallest reg class containing their union. */ + +enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; + +/* Array containing all of the register names */ + +char *reg_names[] = REGISTER_NAMES; + +/* Indexed by n, gives number of times (REG n) is set or clobbered. + This information remains valid for the rest of the compilation + of the current function; it is used to control register allocation. + + This information applies to both hard registers and pseudo registers, + unlike much of the information above. */ + +short *reg_n_sets; + +/* Maximum cost of moving from a register in one class to a register in + another class. Based on REGISTER_MOVE_COST. */ + +static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; + +/* Similar, but here we don't have to move if the first index is a subset + of the second so in that case the cost is zero. */ + +static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; + +#ifdef FORBIDDEN_INC_DEC_CLASSES + +/* These are the classes that regs which are auto-incremented or decremented + cannot be put in. */ + +static int forbidden_inc_dec_class[N_REG_CLASSES]; + +/* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec + context. */ + +static char *in_inc_dec; + +#endif /* FORBIDDEN_INC_DEC_CLASSES */ + +/* Function called only once to initialize the above data on reg usage. + Once this is done, various switches may override. */ + +void +init_reg_sets () +{ + register int i, j; + + /* First copy the register information from the initial int form into + the regsets. */ + + for (i = 0; i < N_REG_CLASSES; i++) + { + CLEAR_HARD_REG_SET (reg_class_contents[i]); + + for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) + if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] + & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) + SET_HARD_REG_BIT (reg_class_contents[i], j); + } + + bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); + bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); + bzero (global_regs, sizeof global_regs); + + /* Compute number of hard regs in each class. */ + + bzero (reg_class_size, sizeof reg_class_size); + for (i = 0; i < N_REG_CLASSES; i++) + for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) + if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) + reg_class_size[i]++; + + /* Initialize the table of subunions. + reg_class_subunion[I][J] gets the largest-numbered reg-class + that is contained in the union of classes I and J. */ + + for (i = 0; i < N_REG_CLASSES; i++) + { + for (j = 0; j < N_REG_CLASSES; j++) + { +#ifdef HARD_REG_SET + register /* Declare it register if it's a scalar. */ +#endif + HARD_REG_SET c; + register int k; + + COPY_HARD_REG_SET (c, reg_class_contents[i]); + IOR_HARD_REG_SET (c, reg_class_contents[j]); + for (k = 0; k < N_REG_CLASSES; k++) + { + GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, + subclass1); + continue; + + subclass1: + /* keep the largest subclass */ /* SPEE 900308 */ + GO_IF_HARD_REG_SUBSET (reg_class_contents[k], + reg_class_contents[(int) reg_class_subunion[i][j]], + subclass2); + reg_class_subunion[i][j] = (enum reg_class) k; + subclass2: + ; + } + } + } + + /* Initialize the table of superunions. + reg_class_superunion[I][J] gets the smallest-numbered reg-class + containing the union of classes I and J. */ + + for (i = 0; i < N_REG_CLASSES; i++) + { + for (j = 0; j < N_REG_CLASSES; j++) + { +#ifdef HARD_REG_SET + register /* Declare it register if it's a scalar. */ +#endif + HARD_REG_SET c; + register int k; + + COPY_HARD_REG_SET (c, reg_class_contents[i]); + IOR_HARD_REG_SET (c, reg_class_contents[j]); + for (k = 0; k < N_REG_CLASSES; k++) + GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); + + superclass: + reg_class_superunion[i][j] = (enum reg_class) k; + } + } + + /* Initialize the tables of subclasses and superclasses of each reg class. + First clear the whole table, then add the elements as they are found. */ + + for (i = 0; i < N_REG_CLASSES; i++) + { + for (j = 0; j < N_REG_CLASSES; j++) + { + reg_class_superclasses[i][j] = LIM_REG_CLASSES; + reg_class_subclasses[i][j] = LIM_REG_CLASSES; + } + } + + for (i = 0; i < N_REG_CLASSES; i++) + { + if (i == (int) NO_REGS) + continue; + + for (j = i + 1; j < N_REG_CLASSES; j++) + { + enum reg_class *p; + + GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], + subclass); + continue; + subclass: + /* Reg class I is a subclass of J. + Add J to the table of superclasses of I. */ + p = ®_class_superclasses[i][0]; + while (*p != LIM_REG_CLASSES) p++; + *p = (enum reg_class) j; + /* Add I to the table of superclasses of J. */ + p = ®_class_subclasses[j][0]; + while (*p != LIM_REG_CLASSES) p++; + *p = (enum reg_class) i; + } + } + + /* Initialize the move cost table. Find every subset of each class + and take the maximum cost of moving any subset to any other. */ + + for (i = 0; i < N_REG_CLASSES; i++) + for (j = 0; j < N_REG_CLASSES; j++) + { + int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); + enum reg_class *p1, *p2; + + for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) + if (*p2 != i) + cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); + + for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) + { + if (*p1 != j) + cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); + + for (p2 = ®_class_subclasses[j][0]; + *p2 != LIM_REG_CLASSES; p2++) + if (*p1 != *p2) + cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); + } + + move_cost[i][j] = cost; + + if (reg_class_subset_p (i, j)) + cost = 0; + + may_move_cost[i][j] = cost; + } +} + +/* After switches have been processed, which perhaps alter + `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ + +void +init_reg_sets_1 () +{ + register int i; + + /* This macro allows the fixed or call-used registers + to depend on target flags. */ + +#ifdef CONDITIONAL_REGISTER_USAGE + CONDITIONAL_REGISTER_USAGE; +#endif + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (global_regs[i]) + { + if (call_used_regs[i] && ! fixed_regs[i]) + warning ("call-clobbered register used for global register variable"); + fixed_regs[i] = 1; + /* Prevent saving/restoring of this reg. */ + call_used_regs[i] = 1; + } + + /* Initialize "constant" tables. */ + + CLEAR_HARD_REG_SET (fixed_reg_set); + CLEAR_HARD_REG_SET (call_used_reg_set); + CLEAR_HARD_REG_SET (call_fixed_reg_set); + + bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); +#ifdef STRUCT_VALUE_REGNUM + call_fixed_regs[STRUCT_VALUE_REGNUM] = 1; +#endif +#ifdef STATIC_CHAIN_REGNUM + call_fixed_regs[STATIC_CHAIN_REGNUM] = 1; +#endif + + n_non_fixed_regs = 0; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + if (FUNCTION_VALUE_REGNO_P (i)) + call_fixed_regs[i] = 1; + if (fixed_regs[i]) + SET_HARD_REG_BIT (fixed_reg_set, i); + else + n_non_fixed_regs++; + + if (call_used_regs[i]) + SET_HARD_REG_BIT (call_used_reg_set, i); + if (call_fixed_regs[i]) + SET_HARD_REG_BIT (call_fixed_reg_set, i); + } +} + +/* Specify the usage characteristics of the register named NAME. + It should be a fixed register if FIXED and a + call-used register if CALL_USED. */ + +void +fix_register (name, fixed, call_used) + char *name; + int fixed, call_used; +{ + int i; + + /* Decode the name and update the primary form of + the register info. */ + + if ((i = decode_reg_name (name)) >= 0) + { + fixed_regs[i] = fixed; + call_used_regs[i] = call_used; + } + else + { + warning ("unknown register name: %s", name); + } +} + +/* Now the data and code for the `regclass' pass, which happens + just before local-alloc. */ + +/* The `costs' struct records the cost of using a hard register of each class + and of using memory for each pseudo. We use this data to set up + register class preferences. */ + +struct costs +{ + int cost[N_REG_CLASSES]; + int mem_cost; +}; + +/* Record the cost of each class for each pseudo. */ + +static struct costs *costs; + +/* Record the same data by operand number, accumulated for each alternative + in an insn. The contribution to a pseudo is that of the minimum-cost + alternative. */ + +static struct costs op_costs[MAX_RECOG_OPERANDS]; + +/* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. + This is available after `regclass' is run. */ + +static char *prefclass; + +/* altclass[R] is a register class that we should use for allocating + pseudo number R if no register in the preferred class is available. + If no register in this class is available, memory is preferred. + + It might appear to be more general to have a bitmask of classes here, + but since it is recommended that there be a class corresponding to the + union of most major pair of classes, that generality is not required. + + This is available after `regclass' is run. */ + +static char *altclass; + +/* Record the depth of loops that we are in. */ + +static int loop_depth; + +/* Account for the fact that insns within a loop are executed very commonly, + but don't keep doing this as loops go too deep. */ + +static int loop_cost; + +static int copy_cost (); +static void record_reg_classes (); +static void record_address_regs (); + + +/* Return the reg_class in which pseudo reg number REGNO is best allocated. + This function is sometimes called before the info has been computed. + When that happens, just return GENERAL_REGS, which is innocuous. */ + +enum reg_class +reg_preferred_class (regno) + int regno; +{ + if (prefclass == 0) + return GENERAL_REGS; + return (enum reg_class) prefclass[regno]; +} + +enum reg_class +reg_alternate_class (regno) +{ + if (prefclass == 0) + return ALL_REGS; + + return (enum reg_class) altclass[regno]; +} + +/* This prevents dump_flow_info from losing if called + before regclass is run. */ + +void +regclass_init () +{ + prefclass = 0; +} + +/* This is a pass of the compiler that scans all instructions + and calculates the preferred class for each pseudo-register. + This information can be accessed later by calling `reg_preferred_class'. + This pass comes just before local register allocation. */ + +void +regclass (f, nregs) + rtx f; + int nregs; +{ +#ifdef REGISTER_CONSTRAINTS + register rtx insn; + register int i, j; + struct costs init_cost; + rtx set; + int pass; + + init_recog (); + + costs = (struct costs *) alloca (nregs * sizeof (struct costs)); + +#ifdef FORBIDDEN_INC_DEC_CLASSES + + in_inc_dec = (char *) alloca (nregs); + + /* Initialize information about which register classes can be used for + pseudos that are auto-incremented or auto-decremented. It would + seem better to put this in init_reg_sets, but we need to be able + to allocate rtx, which we can't do that early. */ + + for (i = 0; i < N_REG_CLASSES; i++) + { + rtx r = gen_rtx (REG, VOIDmode, 0); + enum machine_mode m; + + for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) + if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) + { + REGNO (r) = j; + + for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; + m = (enum machine_mode) ((int) m + 1)) + if (HARD_REGNO_MODE_OK (j, m)) + { + PUT_MODE (r, m); + if (0 +#ifdef SECONDARY_INPUT_RELOAD_CLASS + || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) + != NO_REGS) +#endif +#ifdef SECONDARY_OUTPUT_RELOAD_CLASS + || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) + != NO_REGS) +#endif + ) + forbidden_inc_dec_class[i] = 1; + } + } + } +#endif /* FORBIDDEN_INC_DEC_CLASSES */ + + init_cost.mem_cost = 10000; + for (i = 0; i < N_REG_CLASSES; i++) + init_cost.cost[i] = 10000; + + /* Normally we scan the insns once and determine the best class to use for + each register. However, if -fexpensive_optimizations are on, we do so + twice, the second time using the tentative best classes to guide the + selection. */ + + for (pass = 0; pass <= flag_expensive_optimizations; pass++) + { + /* Zero out our accumulation of the cost of each class for each reg. */ + + bzero (costs, nregs * sizeof (struct costs)); + +#ifdef FORBIDDEN_INC_DEC_CLASSES + bzero (in_inc_dec, nregs); +#endif + + loop_depth = 0, loop_cost = 1; + + /* Scan the instructions and record each time it would + save code to put a certain register in a certain class. */ + + for (insn = f; insn; insn = NEXT_INSN (insn)) + { + char *constraints[MAX_RECOG_OPERANDS]; + enum machine_mode modes[MAX_RECOG_OPERANDS]; + int nalternatives; + int noperands; + + /* Show that an insn inside a loop is likely to be executed three + times more than insns outside a loop. This is much more aggressive + than the assumptions made elsewhere and is being tried as an + experiment. */ + + if (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) + loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); + else if (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) + loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); + + else if ((GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) != USE + && GET_CODE (PATTERN (insn)) != CLOBBER + && GET_CODE (PATTERN (insn)) != ASM_INPUT) + || (GET_CODE (insn) == JUMP_INSN + && GET_CODE (PATTERN (insn)) != ADDR_VEC + && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) + || GET_CODE (insn) == CALL_INSN) + { + if (GET_CODE (insn) == INSN + && (noperands = asm_noperands (PATTERN (insn))) >= 0) + { + decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, + constraints, modes); + nalternatives = (noperands == 0 ? 0 + : n_occurrences (',', constraints[0]) + 1); + } + else + { + int insn_code_number = recog_memoized (insn); + rtx note; + + set = single_set (insn); + insn_extract (insn); + + nalternatives = insn_n_alternatives[insn_code_number]; + noperands = insn_n_operands[insn_code_number]; + + /* If this insn loads a parameter from its stack slot, then + it represents a savings, rather than a cost, if the + parameter is stored in memory. Record this fact. */ + + if (set != 0 && GET_CODE (SET_DEST (set)) == REG + && GET_CODE (SET_SRC (set)) == MEM + && (note = find_reg_note (insn, REG_EQUIV, + NULL_RTX)) != 0 + && GET_CODE (XEXP (note, 0)) == MEM) + { + costs[REGNO (SET_DEST (set))].mem_cost + -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set))) + * loop_cost); + record_address_regs (XEXP (SET_SRC (set), 0), + BASE_REG_CLASS, loop_cost * 2); + continue; + } + + /* Improve handling of two-address insns such as + (set X (ashift CONST Y)) where CONST must be made to + match X. Change it into two insns: (set X CONST) + (set X (ashift X Y)). If we left this for reloading, it + would probably get three insns because X and Y might go + in the same place. This prevents X and Y from receiving + the same hard reg. + + We can only do this if the modes of operands 0 and 1 + (which might not be the same) are tieable and we only need + do this during our first pass. */ + + if (pass == 0 && optimize + && noperands >= 3 + && insn_operand_constraint[insn_code_number][1][0] == '0' + && insn_operand_constraint[insn_code_number][1][1] == 0 + && CONSTANT_P (recog_operand[1]) + && ! rtx_equal_p (recog_operand[0], recog_operand[1]) + && ! rtx_equal_p (recog_operand[0], recog_operand[2]) + && GET_CODE (recog_operand[0]) == REG + && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), + insn_operand_mode[insn_code_number][1])) + { + rtx previnsn = prev_real_insn (insn); + rtx dest + = gen_lowpart (insn_operand_mode[insn_code_number][1], + recog_operand[0]); + rtx newinsn + = emit_insn_before (gen_move_insn (dest, + recog_operand[1]), + insn); + + /* If this insn was the start of a basic block, + include the new insn in that block. + We need not check for code_label here; + while a basic block can start with a code_label, + INSN could not be at the beginning of that block. */ + if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) + { + int b; + for (b = 0; b < n_basic_blocks; b++) + if (insn == basic_block_head[b]) + basic_block_head[b] = newinsn; + } + + /* This makes one more setting of new insns's dest. */ + reg_n_sets[REGNO (recog_operand[0])]++; + + *recog_operand_loc[1] = recog_operand[0]; + for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) + if (recog_dup_num[i] == 1) + *recog_dup_loc[i] = recog_operand[0]; + + insn = PREV_INSN (newinsn); + continue; + } + + for (i = 0; i < noperands; i++) + { + constraints[i] + = insn_operand_constraint[insn_code_number][i]; + modes[i] = insn_operand_mode[insn_code_number][i]; + } + } + + /* If we get here, we are set up to record the costs of all the + operands for this insn. Start by initializing the costs. + Then handle any address registers. Finally record the desired + classes for any pseudos, doing it twice if some pair of + operands are commutative. */ + + for (i = 0; i < noperands; i++) + { + op_costs[i] = init_cost; + + if (GET_CODE (recog_operand[i]) == SUBREG) + recog_operand[i] = SUBREG_REG (recog_operand[i]); + + if (GET_CODE (recog_operand[i]) == MEM) + record_address_regs (XEXP (recog_operand[i], 0), + BASE_REG_CLASS, loop_cost * 2); + else if (constraints[i][0] == 'p') + record_address_regs (recog_operand[i], + BASE_REG_CLASS, loop_cost * 2); + } + + /* Check for commutative in a separate loop so everything will + have been initialized. Don't bother doing anything if the + second operand is a constant since that is the case + for which the constraints should have been written. */ + + for (i = 0; i < noperands - 1; i++) + if (constraints[i][0] == '%' + && ! CONSTANT_P (recog_operand[i+1])) + { + char *xconstraints[MAX_RECOG_OPERANDS]; + int j; + + /* Handle commutative operands by swapping the constraints. + We assume the modes are the same. */ + + for (j = 0; j < noperands; j++) + xconstraints[j] = constraints[j]; + + xconstraints[i] = constraints[i+1]; + xconstraints[i+1] = constraints[i]; + record_reg_classes (nalternatives, noperands, + recog_operand, modes, xconstraints, + insn); + } + + record_reg_classes (nalternatives, noperands, recog_operand, + modes, constraints, insn); + + /* Now add the cost for each operand to the total costs for + its register. */ + + for (i = 0; i < noperands; i++) + if (GET_CODE (recog_operand[i]) == REG + && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) + { + int regno = REGNO (recog_operand[i]); + struct costs *p = &costs[regno], *q = &op_costs[i]; + + p->mem_cost += q->mem_cost * loop_cost; + for (j = 0; j < N_REG_CLASSES; j++) + p->cost[j] += q->cost[j] * loop_cost; + } + } + } + + /* Now for each register look at how desirable each class is + and find which class is preferred. Store that in + `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register + class any of whose registers is better than memory. */ + + if (pass == 0) + { + prefclass = (char *) oballoc (nregs); + altclass = (char *) oballoc (nregs); + } + + for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) + { + register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; + enum reg_class best = ALL_REGS, alt = NO_REGS; + /* This is an enum reg_class, but we call it an int + to save lots of casts. */ + register int class; + register struct costs *p = &costs[i]; + + for (class = (int) ALL_REGS - 1; class > 0; class--) + { + /* Ignore classes that are too small for this operand or + invalid for a operand that was auto-incremented. */ + if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) + > reg_class_size[class] +#ifdef FORBIDDEN_INC_DEC_CLASSES + || (in_inc_dec[i] && forbidden_inc_dec_class[class]) +#endif + ) + ; + else if (p->cost[class] < best_cost) + { + best_cost = p->cost[class]; + best = (enum reg_class) class; + } + else if (p->cost[class] == best_cost) + best = reg_class_subunion[(int)best][class]; + } + + /* Record the alternate register class; i.e., a class for which + every register in it is better than using memory. If adding a + class would make a smaller class (i.e., no union of just those + classes exists), skip that class. The major unions of classes + should be provided as a register class. Don't do this if we + will be doing it again later. */ + + if (pass == 1 || ! flag_expensive_optimizations) + for (class = 0; class < N_REG_CLASSES; class++) + if (p->cost[class] < p->mem_cost + && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] + > reg_class_size[(int) alt]) +#ifdef FORBIDDEN_INC_DEC_CLASSES + && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) +#endif + ) + alt = reg_class_subunion[(int) alt][class]; + + /* If we don't add any classes, nothing to try. */ + if (alt == best) + alt = (int) NO_REGS; + + /* We cast to (int) because (char) hits bugs in some compilers. */ + prefclass[i] = (int) best; + altclass[i] = (int) alt; + } + } +#endif /* REGISTER_CONSTRAINTS */ +} + +#ifdef REGISTER_CONSTRAINTS + +/* Record the cost of using memory or registers of various classes for + the operands in INSN. + + N_ALTS is the number of alternatives. + + N_OPS is the number of operands. + + OPS is an array of the operands. + + MODES are the modes of the operands, in case any are VOIDmode. + + CONSTRAINTS are the constraints to use for the operands. This array + is modified by this procedure. + + This procedure works alternative by alternative. For each alternative + we assume that we will be able to allocate all pseudos to their ideal + register class and calculate the cost of using that alternative. Then + we compute for each operand that is a pseudo-register, the cost of + having the pseudo allocated to each register class and using it in that + alternative. To this cost is added the cost of the alternative. + + The cost of each class for this insn is its lowest cost among all the + alternatives. */ + +static void +record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) + int n_alts; + int n_ops; + rtx *ops; + enum machine_mode *modes; + char **constraints; + rtx insn; +{ + int alt; + enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; + int i, j; + + /* By default, each operand is an input operand. */ + + for (i = 0; i < n_ops; i++) + op_types[i] = OP_READ; + + /* Process each alternative, each time minimizing an operand's cost with + the cost for each operand in that alternative. */ + + for (alt = 0; alt < n_alts; alt++) + { + struct costs this_op_costs[MAX_RECOG_OPERANDS]; + int alt_fail = 0; + int alt_cost = 0; + enum reg_class classes[MAX_RECOG_OPERANDS]; + int class; + + for (i = 0; i < n_ops; i++) + { + char *p = constraints[i]; + rtx op = ops[i]; + enum machine_mode mode = modes[i]; + int allows_mem = 0; + int win = 0; + char c; + + /* If this operand has no constraints at all, we can conclude + nothing about it since anything is valid. */ + + if (*p == 0) + { + if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) + bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); + + continue; + } + + if (*p == '%') + p++; + + /* If this alternative is only relevant when this operand + matches a previous operand, we do different things depending + on whether this operand is a pseudo-reg or not. */ + + if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) + { + j = p[0] - '0'; + classes[i] = classes[j]; + + if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) + { + /* If this matches the other operand, we have no added + cost. */ + if (rtx_equal_p (ops[j], op)) + ; + + /* If we can put the other operand into a register, add to + the cost of this alternative the cost to copy this + operand to the register used for the other operand. */ + + if (classes[j] != NO_REGS) + alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; + } + else if (GET_CODE (ops[j]) != REG + || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) + { + /* This op is a pseudo but the one it matches is not. */ + + /* If we can't put the other operand into a register, this + alternative can't be used. */ + + if (classes[j] == NO_REGS) + alt_fail = 1; + + /* Otherwise, add to the cost of this alternative the cost + to copy the other operand to the register used for this + operand. */ + + else + alt_cost += copy_cost (ops[j], mode, classes[j], 1); + } + else + { + /* The costs of this operand are the same as that of the + other operand. However, if we cannot tie them, this + alternative needs to do a copy, which is one + instruction. */ + + this_op_costs[i] = this_op_costs[j]; + if (! find_reg_note (insn, REG_DEAD, op)) + alt_cost += 2; + + /* This is in place of ordinary cost computation + for this operand. */ + continue; + } + } + + /* Scan all the constraint letters. See if the operand matches + any of the constraints. Collect the valid register classes + and see if this operand accepts memory. */ + + classes[i] = NO_REGS; + while (*p && (c = *p++) != ',') + switch (c) + { + case '=': + op_types[i] = OP_WRITE; + break; + + case '+': + op_types[i] = OP_READ_WRITE; + break; + + case '*': + /* Ignore the next letter for this pass. */ + p++; + break; + + case '%': + case '?': case '!': case '#': + case '&': + case '0': case '1': case '2': case '3': case '4': + case 'p': + break; + + case 'm': case 'o': case 'V': + /* It doesn't seem worth distinguishing between offsettable + and non-offsettable addresses here. */ + allows_mem = 1; + if (GET_CODE (op) == MEM) + win = 1; + break; + + case '<': + if (GET_CODE (op) == MEM + && (GET_CODE (XEXP (op, 0)) == PRE_DEC + || GET_CODE (XEXP (op, 0)) == POST_DEC)) + win = 1; + break; + + case '>': + if (GET_CODE (op) == MEM + && (GET_CODE (XEXP (op, 0)) == PRE_INC + || GET_CODE (XEXP (op, 0)) == POST_INC)) + win = 1; + break; + + case 'E': + /* Match any floating double constant, but only if + we can examine the bits of it reliably. */ + if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT + || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) + && GET_MODE (op) != VOIDmode && ! flag_pretend_float) + break; + if (GET_CODE (op) == CONST_DOUBLE) + win = 1; + break; + + case 'F': + if (GET_CODE (op) == CONST_DOUBLE) + win = 1; + break; + + case 'G': + case 'H': + if (GET_CODE (op) == CONST_DOUBLE + && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) + win = 1; + break; + + case 's': + if (GET_CODE (op) == CONST_INT + || (GET_CODE (op) == CONST_DOUBLE + && GET_MODE (op) == VOIDmode)) + break; + case 'i': + if (CONSTANT_P (op) +#ifdef LEGITIMATE_PIC_OPERAND_P + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) +#endif + ) + win = 1; + break; + + case 'n': + if (GET_CODE (op) == CONST_INT + || (GET_CODE (op) == CONST_DOUBLE + && GET_MODE (op) == VOIDmode)) + win = 1; + break; + + case 'I': + case 'J': + case 'K': + case 'L': + case 'M': + case 'N': + case 'O': + case 'P': + if (GET_CODE (op) == CONST_INT + && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) + win = 1; + break; + + case 'X': + win = 1; + break; + +#ifdef EXTRA_CONSTRAINT + case 'Q': + case 'R': + case 'S': + case 'T': + case 'U': + if (EXTRA_CONSTRAINT (op, c)) + win = 1; + break; +#endif + + case 'g': + if (GET_CODE (op) == MEM + || (CONSTANT_P (op) +#ifdef LEGITIMATE_PIC_OPERAND_P + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) +#endif + )) + win = 1; + allows_mem = 1; + case 'r': + classes[i] + = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; + break; + + default: + classes[i] + = reg_class_subunion[(int) classes[i]] + [(int) REG_CLASS_FROM_LETTER (c)]; + } + + constraints[i] = p; + + /* How we account for this operand now depends on whether it is a + pseudo register or not. If it is, we first check if any + register classes are valid. If not, we ignore this alternative, + since we want to assume that all pseudos get allocated for + register preferencing. If some register class is valid, compute + the costs of moving the pseudo into that class. */ + + if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) + { + if (classes[i] == NO_REGS) + alt_fail = 1; + else + { + struct costs *pp = &this_op_costs[i]; + + for (class = 0; class < N_REG_CLASSES; class++) + pp->cost[class] = may_move_cost[class][(int) classes[i]]; + + /* If the alternative actually allows memory, make things + a bit cheaper since we won't need an extra insn to + load it. */ + + pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem; + + /* If we have assigned a class to this register in our + first pass, add a cost to this alternative corresponding + to what we would add if this register were not in the + appropriate class. */ + + if (prefclass) + alt_cost + += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]]; + } + } + + /* Otherwise, if this alternative wins, either because we + have already determined that or if we have a hard register of + the proper class, there is no cost for this alternative. */ + + else if (win + || (GET_CODE (op) == REG + && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) + ; + + /* If registers are valid, the cost of this alternative includes + copying the object to and/or from a register. */ + + else if (classes[i] != NO_REGS) + { + if (op_types[i] != OP_WRITE) + alt_cost += copy_cost (op, mode, classes[i], 1); + + if (op_types[i] != OP_READ) + alt_cost += copy_cost (op, mode, classes[i], 0); + } + + /* The only other way this alternative can be used is if this is a + constant that could be placed into memory. */ + + else if (CONSTANT_P (op) && allows_mem) + alt_cost += MEMORY_MOVE_COST (mode); + else + alt_fail = 1; + } + + if (alt_fail) + continue; + + /* Finally, update the costs with the information we've calculated + about this alternative. */ + + for (i = 0; i < n_ops; i++) + if (GET_CODE (ops[i]) == REG + && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) + { + struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; + int scale = 1 + (op_types[i] == OP_READ_WRITE); + + pp->mem_cost = MIN (pp->mem_cost, + (qq->mem_cost + alt_cost) * scale); + + for (class = 0; class < N_REG_CLASSES; class++) + pp->cost[class] = MIN (pp->cost[class], + (qq->cost[class] + alt_cost) * scale); + } + } +} + +/* Compute the cost of loading X into (if TO_P is non-zero) or from (if + TO_P is zero) a register of class CLASS in mode MODE. + + X must not be a pseudo. */ + +static int +copy_cost (x, mode, class, to_p) + rtx x; + enum machine_mode mode; + enum reg_class class; + int to_p; +{ + enum reg_class secondary_class = NO_REGS; + + /* If X is a SCRATCH, there is actually nothing to move since we are + assuming optimal allocation. */ + + if (GET_CODE (x) == SCRATCH) + return 0; + + /* Get the class we will actually use for a reload. */ + class = PREFERRED_RELOAD_CLASS (x, class); + +#ifdef HAVE_SECONDARY_RELOADS + /* If we need a secondary reload (we assume here that we are using + the secondary reload as an intermediate, not a scratch register), the + cost is that to load the input into the intermediate register, then + to copy them. We use a special value of TO_P to avoid recursion. */ + +#ifdef SECONDARY_INPUT_RELOAD_CLASS + if (to_p == 1) + secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); +#endif + +#ifdef SECONDARY_OUTPUT_RELOAD_CLASS + if (! to_p) + secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); +#endif + + if (secondary_class != NO_REGS) + return (move_cost[(int) secondary_class][(int) class] + + copy_cost (x, mode, secondary_class, 2)); +#endif /* HAVE_SECONDARY_RELOADS */ + + /* For memory, use the memory move cost, for (hard) registers, use the + cost to move between the register classes, and use 2 for everything + else (constants). */ + + if (GET_CODE (x) == MEM || class == NO_REGS) + return MEMORY_MOVE_COST (mode); + + else if (GET_CODE (x) == REG) + return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; + + else + /* If this is a constant, we may eventually want to call rtx_cost here. */ + return 2; +} + +/* Record the pseudo registers we must reload into hard registers + in a subexpression of a memory address, X. + + CLASS is the class that the register needs to be in and is either + BASE_REG_CLASS or INDEX_REG_CLASS. + + SCALE is twice the amount to multiply the cost by (it is twice so we + can represent half-cost adjustments). */ + +static void +record_address_regs (x, class, scale) + rtx x; + enum reg_class class; + int scale; +{ + register enum rtx_code code = GET_CODE (x); + + switch (code) + { + case CONST_INT: + case CONST: + case CC0: + case PC: + case SYMBOL_REF: + case LABEL_REF: + return; + + case PLUS: + /* When we have an address that is a sum, + we must determine whether registers are "base" or "index" regs. + If there is a sum of two registers, we must choose one to be + the "base". Luckily, we can use the REGNO_POINTER_FLAG + to make a good choice most of the time. We only need to do this + on machines that can have two registers in an address and where + the base and index register classes are different. + + ??? This code used to set REGNO_POINTER_FLAG in some cases, but + that seems bogus since it should only be set when we are sure + the register is being used as a pointer. */ + + { + rtx arg0 = XEXP (x, 0); + rtx arg1 = XEXP (x, 1); + register enum rtx_code code0 = GET_CODE (arg0); + register enum rtx_code code1 = GET_CODE (arg1); + + /* Look inside subregs. */ + if (code0 == SUBREG) + arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); + if (code1 == SUBREG) + arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); + + /* If this machine only allows one register per address, it must + be in the first operand. */ + + if (MAX_REGS_PER_ADDRESS == 1) + record_address_regs (arg0, class, scale); + + /* If index and base registers are the same on this machine, just + record registers in any non-constant operands. We assume here, + as well as in the tests below, that all addresses are in + canonical form. */ + + else if (INDEX_REG_CLASS == BASE_REG_CLASS) + { + record_address_regs (arg0, class, scale); + if (! CONSTANT_P (arg1)) + record_address_regs (arg1, class, scale); + } + + /* If the second operand is a constant integer, it doesn't change + what class the first operand must be. */ + + else if (code1 == CONST_INT || code1 == CONST_DOUBLE) + record_address_regs (arg0, class, scale); + + /* If the second operand is a symbolic constant, the first operand + must be an index register. */ + + else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) + record_address_regs (arg0, INDEX_REG_CLASS, scale); + + /* If this the sum of two registers where the first is known to be a + pointer, it must be a base register with the second an index. */ + + else if (code0 == REG && code1 == REG + && REGNO_POINTER_FLAG (REGNO (arg0))) + { + record_address_regs (arg0, BASE_REG_CLASS, scale); + record_address_regs (arg1, INDEX_REG_CLASS, scale); + } + + /* If this is the sum of two registers and neither is known to + be a pointer, count equal chances that each might be a base + or index register. This case should be rare. */ + + else if (code0 == REG && code1 == REG + && ! REGNO_POINTER_FLAG (REGNO (arg0)) + && ! REGNO_POINTER_FLAG (REGNO (arg1))) + { + record_address_regs (arg0, BASE_REG_CLASS, scale / 2); + record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); + record_address_regs (arg1, BASE_REG_CLASS, scale / 2); + record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); + } + + /* In all other cases, the first operand is an index and the + second is the base. */ + + else + { + record_address_regs (arg0, INDEX_REG_CLASS, scale); + record_address_regs (arg1, BASE_REG_CLASS, scale); + } + } + break; + + case POST_INC: + case PRE_INC: + case POST_DEC: + case PRE_DEC: + /* Double the importance of a pseudo register that is incremented + or decremented, since it would take two extra insns + if it ends up in the wrong place. If the operand is a pseudo, + show it is being used in an INC_DEC context. */ + +#ifdef FORBIDDEN_INC_DEC_CLASSES + if (GET_CODE (XEXP (x, 0)) == REG + && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) + in_inc_dec[REGNO (XEXP (x, 0))] = 1; +#endif + + record_address_regs (XEXP (x, 0), class, 2 * scale); + break; + + case REG: + { + register struct costs *pp = &costs[REGNO (x)]; + register int i; + + pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2; + + for (i = 0; i < N_REG_CLASSES; i++) + pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; + } + break; + + default: + { + register char *fmt = GET_RTX_FORMAT (code); + register int i; + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + record_address_regs (XEXP (x, i), class, scale); + } + } +} +#endif /* REGISTER_CONSTRAINTS */ + +/* This is the `regscan' pass of the compiler, run just before cse + and again just before loop. + + It finds the first and last use of each pseudo-register + and records them in the vectors regno_first_uid, regno_last_uid + and counts the number of sets in the vector reg_n_sets. + + REPEAT is nonzero the second time this is called. */ + +/* Indexed by pseudo register number, gives uid of first insn using the reg + (as of the time reg_scan is called). */ + +int *regno_first_uid; + +/* Indexed by pseudo register number, gives uid of last insn using the reg + (as of the time reg_scan is called). */ + +int *regno_last_uid; + +/* Record the number of registers we used when we allocated the above two + tables. If we are called again with more than this, we must re-allocate + the tables. */ + +static int highest_regno_in_uid_map; + +/* Maximum number of parallel sets and clobbers in any insn in this fn. + Always at least 3, since the combiner could put that many togetherm + and we want this to remain correct for all the remaining passes. */ + +int max_parallel; + +void reg_scan_mark_refs (); + +void +reg_scan (f, nregs, repeat) + rtx f; + int nregs; + int repeat; +{ + register rtx insn; + + if (!repeat || nregs > highest_regno_in_uid_map) + { + /* Leave some spare space in case more regs are allocated. */ + highest_regno_in_uid_map = nregs + nregs / 20; + regno_first_uid + = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); + regno_last_uid + = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); + reg_n_sets + = (short *) oballoc (highest_regno_in_uid_map * sizeof (short)); + } + + bzero (regno_first_uid, highest_regno_in_uid_map * sizeof (int)); + bzero (regno_last_uid, highest_regno_in_uid_map * sizeof (int)); + bzero (reg_n_sets, highest_regno_in_uid_map * sizeof (short)); + + max_parallel = 3; + + for (insn = f; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == INSN + || GET_CODE (insn) == CALL_INSN + || GET_CODE (insn) == JUMP_INSN) + { + if (GET_CODE (PATTERN (insn)) == PARALLEL + && XVECLEN (PATTERN (insn), 0) > max_parallel) + max_parallel = XVECLEN (PATTERN (insn), 0); + reg_scan_mark_refs (PATTERN (insn), insn); + } +} + +void +reg_scan_mark_refs (x, insn) + rtx x; + rtx insn; +{ + register enum rtx_code code = GET_CODE (x); + register rtx dest; + register rtx note; + + switch (code) + { + case CONST_INT: + case CONST: + case CONST_DOUBLE: + case CC0: + case PC: + case SYMBOL_REF: + case LABEL_REF: + case ADDR_VEC: + case ADDR_DIFF_VEC: + return; + + case REG: + { + register int regno = REGNO (x); + + regno_last_uid[regno] = INSN_UID (insn); + if (regno_first_uid[regno] == 0) + regno_first_uid[regno] = INSN_UID (insn); + } + break; + + case SET: + /* Count a set of the destination if it is a register. */ + for (dest = SET_DEST (x); + GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART + || GET_CODE (dest) == ZERO_EXTEND; + dest = XEXP (dest, 0)) + ; + + if (GET_CODE (dest) == REG) + reg_n_sets[REGNO (dest)]++; + + /* If this is setting a pseudo from another pseudo or the sum of a + pseudo and a constant integer and the other pseudo is known to be + a pointer, set the destination to be a pointer as well. + + Likewise if it is setting the destination from an address or from a + value equivalent to an address or to the sum of an address and + something else. + + But don't do any of this if the pseudo corresponds to a user + variable since it should have already been set as a pointer based + on the type. */ + + if (GET_CODE (SET_DEST (x)) == REG + && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER + && ! REG_USERVAR_P (SET_DEST (x)) + && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) + && ((GET_CODE (SET_SRC (x)) == REG + && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) + || ((GET_CODE (SET_SRC (x)) == PLUS + || GET_CODE (SET_SRC (x)) == LO_SUM) + && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT + && GET_CODE (XEXP (SET_SRC (x), 0)) == REG + && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) + || GET_CODE (SET_SRC (x)) == CONST + || GET_CODE (SET_SRC (x)) == SYMBOL_REF + || GET_CODE (SET_SRC (x)) == LABEL_REF + || (GET_CODE (SET_SRC (x)) == HIGH + && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST + || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF + || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) + || ((GET_CODE (SET_SRC (x)) == PLUS + || GET_CODE (SET_SRC (x)) == LO_SUM) + && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST + || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF + || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) + || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 + && (GET_CODE (XEXP (note, 0)) == CONST + || GET_CODE (XEXP (note, 0)) == SYMBOL_REF + || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) + REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; + + /* ... fall through ... */ + + default: + { + register char *fmt = GET_RTX_FORMAT (code); + register int i; + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + reg_scan_mark_refs (XEXP (x, i), insn); + else if (fmt[i] == 'E' && XVEC (x, i) != 0) + { + register int j; + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + reg_scan_mark_refs (XVECEXP (x, i, j), insn); + } + } + } + } +} + +/* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 + is also in C2. */ + +int +reg_class_subset_p (c1, c2) + register enum reg_class c1; + register enum reg_class c2; +{ + if (c1 == c2) return 1; + + if (c2 == ALL_REGS) + win: + return 1; + GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], + reg_class_contents[(int)c2], + win); + return 0; +} + +/* Return nonzero if there is a register that is in both C1 and C2. */ + +int +reg_classes_intersect_p (c1, c2) + register enum reg_class c1; + register enum reg_class c2; +{ +#ifdef HARD_REG_SET + register +#endif + HARD_REG_SET c; + + if (c1 == c2) return 1; + + if (c1 == ALL_REGS || c2 == ALL_REGS) + return 1; + + COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); + AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); + + GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); + return 1; + + lose: + return 0; +} + diff --git a/gnu/usr.bin/cc/lib/regs.h b/gnu/usr.bin/cc/lib/regs.h new file mode 100644 index 000000000000..31158e728f31 --- /dev/null +++ b/gnu/usr.bin/cc/lib/regs.h @@ -0,0 +1,148 @@ +/* Define per-register tables for data flow info and register allocation. + Copyright (C) 1987 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + + +#define REG_BYTES(R) mode_size[(int) GET_MODE (R)] + +/* Get the number of consecutive hard regs required to hold the REG rtx R. + When something may be an explicit hard reg, REG_SIZE is the only + valid way to get this value. You cannot get it from the regno. */ + +#define REG_SIZE(R) \ + ((mode_size[(int) GET_MODE (R)] + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +/* Maximum register number used in this function, plus one. */ + +extern int max_regno; + +/* Maximum number of SCRATCH rtx's in each block of this function. */ + +extern int max_scratch; + +/* Indexed by n, gives number of times (REG n) is used or set. + References within loops may be counted more times. */ + +extern int *reg_n_refs; + +/* Indexed by n, gives number of times (REG n) is set. */ + +extern short *reg_n_sets; + +/* Indexed by N, gives number of insns in which register N dies. + Note that if register N is live around loops, it can die + in transitions between basic blocks, and that is not counted here. + So this is only a reliable indicator of how many regions of life there are + for registers that are contained in one basic block. */ + +extern short *reg_n_deaths; + +/* Get the number of consecutive words required to hold pseudo-reg N. */ + +#define PSEUDO_REGNO_SIZE(N) \ + ((GET_MODE_SIZE (PSEUDO_REGNO_MODE (N)) + UNITS_PER_WORD - 1) \ + / UNITS_PER_WORD) + +/* Get the number of bytes required to hold pseudo-reg N. */ + +#define PSEUDO_REGNO_BYTES(N) \ + GET_MODE_SIZE (PSEUDO_REGNO_MODE (N)) + +/* Get the machine mode of pseudo-reg N. */ + +#define PSEUDO_REGNO_MODE(N) GET_MODE (regno_reg_rtx[N]) + +/* Indexed by N, gives number of CALL_INSNS across which (REG n) is live. */ + +extern int *reg_n_calls_crossed; + +/* Total number of instructions at which (REG n) is live. + The larger this is, the less priority (REG n) gets for + allocation in a hard register (in global-alloc). + This is set in flow.c and remains valid for the rest of the compilation + of the function; it is used to control register allocation. + + local-alloc.c may alter this number to change the priority. + + Negative values are special. + -1 is used to mark a pseudo reg which has a constant or memory equivalent + and is used infrequently enough that it should not get a hard register. + -2 is used to mark a pseudo reg for a parameter, when a frame pointer + is not required. global.c makes an allocno for this but does + not try to assign a hard register to it. */ + +extern int *reg_live_length; + +/* Vector of substitutions of register numbers, + used to map pseudo regs into hardware regs. */ + +extern short *reg_renumber; + +/* Vector indexed by hardware reg + saying whether that reg is ever used. */ + +extern char regs_ever_live[FIRST_PSEUDO_REGISTER]; + +/* Vector indexed by hardware reg giving its name. */ + +extern char *reg_names[FIRST_PSEUDO_REGISTER]; + +/* Vector indexed by regno; gives uid of first insn using that reg. + This is computed by reg_scan for use by cse and loop. + It is sometimes adjusted for subsequent changes during loop, + but not adjusted by cse even if cse invalidates it. */ + +extern int *regno_first_uid; + +/* Vector indexed by regno; gives uid of last insn using that reg. + This is computed by reg_scan for use by cse and loop. + It is sometimes adjusted for subsequent changes during loop, + but not adjusted by cse even if cse invalidates it. + This is harmless since cse won't scan through a loop end. */ + +extern int *regno_last_uid; + +/* Vector indexed by regno; contains 1 for a register is considered a pointer. + Reloading, etc. will use a pointer register rather than a non-pointer + as the base register in an address, when there is a choice of two regs. */ + +extern char *regno_pointer_flag; +#define REGNO_POINTER_FLAG(REGNO) regno_pointer_flag[REGNO] + +/* List made of EXPR_LIST rtx's which gives pairs of pseudo registers + that have to go in the same hard reg. */ +extern rtx regs_may_share; + +/* Vector mapping pseudo regno into the REG rtx for that register. + This is computed by reg_scan. */ + +extern rtx *regno_reg_rtx; + +/* Flag set by local-alloc or global-alloc if they decide to allocate + something in a call-clobbered register. */ + +extern int caller_save_needed; + +/* Predicate to decide whether to give a hard reg to a pseudo which + is referenced REFS times and would need to be saved and restored + around a call CALLS times. */ + +#ifndef CALLER_SAVE_PROFITABLE +#define CALLER_SAVE_PROFITABLE(REFS, CALLS) (4 * (CALLS) < (REFS)) +#endif diff --git a/gnu/usr.bin/cc/lib/reload.c b/gnu/usr.bin/cc/lib/reload.c new file mode 100644 index 000000000000..868c96780fc3 --- /dev/null +++ b/gnu/usr.bin/cc/lib/reload.c @@ -0,0 +1,5435 @@ +/* Search an insn for pseudo regs that must be in hard regs and are not. + Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This file contains subroutines used only from the file reload1.c. + It knows how to scan one insn for operands and values + that need to be copied into registers to make valid code. + It also finds other operands and values which are valid + but for which equivalent values in registers exist and + ought to be used instead. + + Before processing the first insn of the function, call `init_reload'. + + To scan an insn, call `find_reloads'. This does two things: + 1. sets up tables describing which values must be reloaded + for this insn, and what kind of hard regs they must be reloaded into; + 2. optionally record the locations where those values appear in + the data, so they can be replaced properly later. + This is done only if the second arg to `find_reloads' is nonzero. + + The third arg to `find_reloads' specifies the number of levels + of indirect addressing supported by the machine. If it is zero, + indirect addressing is not valid. If it is one, (MEM (REG n)) + is valid even if (REG n) did not get a hard register; if it is two, + (MEM (MEM (REG n))) is also valid even if (REG n) did not get a + hard register, and similarly for higher values. + + Then you must choose the hard regs to reload those pseudo regs into, + and generate appropriate load insns before this insn and perhaps + also store insns after this insn. Set up the array `reload_reg_rtx' + to contain the REG rtx's for the registers you used. In some + cases `find_reloads' will return a nonzero value in `reload_reg_rtx' + for certain reloads. Then that tells you which register to use, + so you do not need to allocate one. But you still do need to add extra + instructions to copy the value into and out of that register. + + Finally you must call `subst_reloads' to substitute the reload reg rtx's + into the locations already recorded. + +NOTE SIDE EFFECTS: + + find_reloads can alter the operands of the instruction it is called on. + + 1. Two operands of any sort may be interchanged, if they are in a + commutative instruction. + This happens only if find_reloads thinks the instruction will compile + better that way. + + 2. Pseudo-registers that are equivalent to constants are replaced + with those constants if they are not in hard registers. + +1 happens every time find_reloads is called. +2 happens only when REPLACE is 1, which is only when +actually doing the reloads, not when just counting them. + + +Using a reload register for several reloads in one insn: + +When an insn has reloads, it is considered as having three parts: +the input reloads, the insn itself after reloading, and the output reloads. +Reloads of values used in memory addresses are often needed for only one part. + +When this is so, reload_when_needed records which part needs the reload. +Two reloads for different parts of the insn can share the same reload +register. + +When a reload is used for addresses in multiple parts, or when it is +an ordinary operand, it is classified as RELOAD_OTHER, and cannot share +a register with any other reload. */ + +#define REG_OK_STRICT + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "insn-codes.h" +#include "recog.h" +#include "reload.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "flags.h" +#include "real.h" + +#ifndef REGISTER_MOVE_COST +#define REGISTER_MOVE_COST(x, y) 2 +#endif + +/* The variables set up by `find_reloads' are: + + n_reloads number of distinct reloads needed; max reload # + 1 + tables indexed by reload number + reload_in rtx for value to reload from + reload_out rtx for where to store reload-reg afterward if nec + (often the same as reload_in) + reload_reg_class enum reg_class, saying what regs to reload into + reload_inmode enum machine_mode; mode this operand should have + when reloaded, on input. + reload_outmode enum machine_mode; mode this operand should have + when reloaded, on output. + reload_optional char, nonzero for an optional reload. + Optional reloads are ignored unless the + value is already sitting in a register. + reload_inc int, positive amount to increment or decrement by if + reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC. + Ignored otherwise (don't assume it is zero). + reload_in_reg rtx. A reg for which reload_in is the equivalent. + If reload_in is a symbol_ref which came from + reg_equiv_constant, then this is the pseudo + which has that symbol_ref as equivalent. + reload_reg_rtx rtx. This is the register to reload into. + If it is zero when `find_reloads' returns, + you must find a suitable register in the class + specified by reload_reg_class, and store here + an rtx for that register with mode from + reload_inmode or reload_outmode. + reload_nocombine char, nonzero if this reload shouldn't be + combined with another reload. + reload_opnum int, operand number being reloaded. This is + used to group related reloads and need not always + be equal to the actual operand number in the insn, + though it current will be; for in-out operands, it + is one of the two operand numbers. + reload_when_needed enum, classifies reload as needed either for + addressing an input reload, addressing an output, + for addressing a non-reloaded mem ref, + or for unspecified purposes (i.e., more than one + of the above). + reload_secondary_reload int, gives the reload number of a secondary + reload, when needed; otherwise -1 + reload_secondary_p int, 1 if this is a secondary register for one + or more reloads. + reload_secondary_icode enum insn_code, if a secondary reload is required, + gives the INSN_CODE that uses the secondary + reload as a scratch register, or CODE_FOR_nothing + if the secondary reload register is to be an + intermediate register. */ +int n_reloads; + +rtx reload_in[MAX_RELOADS]; +rtx reload_out[MAX_RELOADS]; +enum reg_class reload_reg_class[MAX_RELOADS]; +enum machine_mode reload_inmode[MAX_RELOADS]; +enum machine_mode reload_outmode[MAX_RELOADS]; +rtx reload_reg_rtx[MAX_RELOADS]; +char reload_optional[MAX_RELOADS]; +int reload_inc[MAX_RELOADS]; +rtx reload_in_reg[MAX_RELOADS]; +char reload_nocombine[MAX_RELOADS]; +int reload_opnum[MAX_RELOADS]; +enum reload_type reload_when_needed[MAX_RELOADS]; +int reload_secondary_reload[MAX_RELOADS]; +int reload_secondary_p[MAX_RELOADS]; +enum insn_code reload_secondary_icode[MAX_RELOADS]; + +/* All the "earlyclobber" operands of the current insn + are recorded here. */ +int n_earlyclobbers; +rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; + +int reload_n_operands; + +/* Replacing reloads. + + If `replace_reloads' is nonzero, then as each reload is recorded + an entry is made for it in the table `replacements'. + Then later `subst_reloads' can look through that table and + perform all the replacements needed. */ + +/* Nonzero means record the places to replace. */ +static int replace_reloads; + +/* Each replacement is recorded with a structure like this. */ +struct replacement +{ + rtx *where; /* Location to store in */ + rtx *subreg_loc; /* Location of SUBREG if WHERE is inside + a SUBREG; 0 otherwise. */ + int what; /* which reload this is for */ + enum machine_mode mode; /* mode it must have */ +}; + +static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; + +/* Number of replacements currently recorded. */ +static int n_replacements; + +/* Used to track what is modified by an operand. */ +struct decomposition +{ + int reg_flag; /* Nonzero if referencing a register. */ + int safe; /* Nonzero if this can't conflict with anything. */ + rtx base; /* Base adddress for MEM. */ + HOST_WIDE_INT start; /* Starting offset or register number. */ + HOST_WIDE_INT end; /* Endinf offset or register number. */ +}; + +/* MEM-rtx's created for pseudo-regs in stack slots not directly addressable; + (see reg_equiv_address). */ +static rtx memlocs[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; +static int n_memlocs; + +#ifdef SECONDARY_MEMORY_NEEDED + +/* Save MEMs needed to copy from one class of registers to another. One MEM + is used per mode, but normally only one or two modes are ever used. + + We keep two versions, before and after register elimination. The one + after register elimination is record separately for each operand. This + is done in case the address is not valid to be sure that we separately + reload each. */ + +static rtx secondary_memlocs[NUM_MACHINE_MODES]; +static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS]; +#endif + +/* The instruction we are doing reloads for; + so we can test whether a register dies in it. */ +static rtx this_insn; + +/* Nonzero if this instruction is a user-specified asm with operands. */ +static int this_insn_is_asm; + +/* If hard_regs_live_known is nonzero, + we can tell which hard regs are currently live, + at least enough to succeed in choosing dummy reloads. */ +static int hard_regs_live_known; + +/* Indexed by hard reg number, + element is nonegative if hard reg has been spilled. + This vector is passed to `find_reloads' as an argument + and is not changed here. */ +static short *static_reload_reg_p; + +/* Set to 1 in subst_reg_equivs if it changes anything. */ +static int subst_reg_equivs_changed; + +/* On return from push_reload, holds the reload-number for the OUT + operand, which can be different for that from the input operand. */ +static int output_reloadnum; + +static enum reg_class find_secondary_reload PROTO((rtx, enum reg_class, + enum machine_mode, int, + enum insn_code *, + enum machine_mode *, + enum reg_class *, + enum insn_code *, + enum machine_mode *)); +static int push_reload PROTO((rtx, rtx, rtx *, rtx *, enum reg_class, + enum machine_mode, enum machine_mode, + int, int, int, enum reload_type)); +static void push_replacement PROTO((rtx *, int, enum machine_mode)); +static void combine_reloads PROTO((void)); +static rtx find_dummy_reload PROTO((rtx, rtx, rtx *, rtx *, + enum reg_class, int)); +static int hard_reg_set_here_p PROTO((int, int, rtx)); +static struct decomposition decompose PROTO((rtx)); +static int immune_p PROTO((rtx, rtx, struct decomposition)); +static int alternative_allows_memconst PROTO((char *, int)); +static rtx find_reloads_toplev PROTO((rtx, int, enum reload_type, int, int)); +static rtx make_memloc PROTO((rtx, int)); +static int find_reloads_address PROTO((enum machine_mode, rtx *, rtx, rtx *, + int, enum reload_type, int)); +static rtx subst_reg_equivs PROTO((rtx)); +static rtx subst_indexed_address PROTO((rtx)); +static int find_reloads_address_1 PROTO((rtx, int, rtx *, int, + enum reload_type,int)); +static void find_reloads_address_part PROTO((rtx, rtx *, enum reg_class, + enum machine_mode, int, + enum reload_type, int)); +static int find_inc_amount PROTO((rtx, rtx)); + +#ifdef HAVE_SECONDARY_RELOADS + +/* Determine if any secondary reloads are needed for loading (if IN_P is + non-zero) or storing (if IN_P is zero) X to or from a reload register of + register class RELOAD_CLASS in mode RELOAD_MODE. + + Return the register class of a secondary reload register, or NO_REGS if + none. *PMODE is set to the mode that the register is required in. + If the reload register is needed as a scratch register instead of an + intermediate register, *PICODE is set to the insn_code of the insn to be + used to load or store the primary reload register; otherwise *PICODE + is set to CODE_FOR_nothing. + + In some cases (such as storing MQ into an external memory location on + the RT), both an intermediate register and a scratch register. In that + case, *PICODE is set to CODE_FOR_nothing, the class for the intermediate + register is returned, and the *PTERTIARY_... variables are set to describe + the scratch register. */ + +static enum reg_class +find_secondary_reload (x, reload_class, reload_mode, in_p, picode, pmode, + ptertiary_class, ptertiary_icode, ptertiary_mode) + rtx x; + enum reg_class reload_class; + enum machine_mode reload_mode; + int in_p; + enum insn_code *picode; + enum machine_mode *pmode; + enum reg_class *ptertiary_class; + enum insn_code *ptertiary_icode; + enum machine_mode *ptertiary_mode; +{ + enum reg_class class = NO_REGS; + enum machine_mode mode = reload_mode; + enum insn_code icode = CODE_FOR_nothing; + enum reg_class t_class = NO_REGS; + enum machine_mode t_mode = VOIDmode; + enum insn_code t_icode = CODE_FOR_nothing; + + /* If X is a pseudo-register that has an equivalent MEM (actually, if it + is still a pseudo-register by now, it *must* have an equivalent MEM + but we don't want to assume that), use that equivalent when seeing if + a secondary reload is needed since whether or not a reload is needed + might be sensitive to the form of the MEM. */ + + if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER + && reg_equiv_mem[REGNO (x)] != 0) + x = reg_equiv_mem[REGNO (x)]; + +#ifdef SECONDARY_INPUT_RELOAD_CLASS + if (in_p) + class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x); +#endif + +#ifdef SECONDARY_OUTPUT_RELOAD_CLASS + if (! in_p) + class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x); +#endif + + /* If we don't need any secondary registers, go away; the rest of the + values won't be used. */ + if (class == NO_REGS) + return NO_REGS; + + /* Get a possible insn to use. If the predicate doesn't accept X, don't + use the insn. */ + + icode = (in_p ? reload_in_optab[(int) reload_mode] + : reload_out_optab[(int) reload_mode]); + + if (icode != CODE_FOR_nothing + && insn_operand_predicate[(int) icode][in_p] + && (! (insn_operand_predicate[(int) icode][in_p]) (x, reload_mode))) + icode = CODE_FOR_nothing; + + /* If we will be using an insn, see if it can directly handle the reload + register we will be using. If it can, the secondary reload is for a + scratch register. If it can't, we will use the secondary reload for + an intermediate register and require a tertiary reload for the scratch + register. */ + + if (icode != CODE_FOR_nothing) + { + /* If IN_P is non-zero, the reload register will be the output in + operand 0. If IN_P is zero, the reload register will be the input + in operand 1. Outputs should have an initial "=", which we must + skip. */ + + char insn_letter = insn_operand_constraint[(int) icode][!in_p][in_p]; + enum reg_class insn_class + = (insn_letter == 'r' ? GENERAL_REGS + : REG_CLASS_FROM_LETTER (insn_letter)); + + if (insn_class == NO_REGS + || (in_p && insn_operand_constraint[(int) icode][!in_p][0] != '=') + /* The scratch register's constraint must start with "=&". */ + || insn_operand_constraint[(int) icode][2][0] != '=' + || insn_operand_constraint[(int) icode][2][1] != '&') + abort (); + + if (reg_class_subset_p (reload_class, insn_class)) + mode = insn_operand_mode[(int) icode][2]; + else + { + char t_letter = insn_operand_constraint[(int) icode][2][2]; + class = insn_class; + t_mode = insn_operand_mode[(int) icode][2]; + t_class = (t_letter == 'r' ? GENERAL_REGS + : REG_CLASS_FROM_LETTER (t_letter)); + t_icode = icode; + icode = CODE_FOR_nothing; + } + } + + *pmode = mode; + *picode = icode; + *ptertiary_class = t_class; + *ptertiary_mode = t_mode; + *ptertiary_icode = t_icode; + + return class; +} +#endif /* HAVE_SECONDARY_RELOADS */ + +#ifdef SECONDARY_MEMORY_NEEDED + +/* Return a memory location that will be used to copy X in mode MODE. + If we haven't already made a location for this mode in this insn, + call find_reloads_address on the location being returned. */ + +rtx +get_secondary_mem (x, mode, opnum, type) + rtx x; + enum machine_mode mode; + int opnum; + enum reload_type type; +{ + rtx loc; + int mem_valid; + + /* If MODE is narrower than a word, widen it. This is required because + most machines that require these memory locations do not support + short load and stores from all registers (e.g., FP registers). We could + possibly conditionalize this, but we lose nothing by doing the wider + mode. */ + + if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD) + mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0); + + /* If we already have made a MEM for this operand in MODE, return it. */ + if (secondary_memlocs_elim[(int) mode][opnum] != 0) + return secondary_memlocs_elim[(int) mode][opnum]; + + /* If this is the first time we've tried to get a MEM for this mode, + allocate a new one. `something_changed' in reload will get set + by noticing that the frame size has changed. */ + + if (secondary_memlocs[(int) mode] == 0) + { +#ifdef SECONDARY_MEMORY_NEEDED_RTX + secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode); +#else + secondary_memlocs[(int) mode] + = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); +#endif + } + + /* Get a version of the address doing any eliminations needed. If that + didn't give us a new MEM, make a new one if it isn't valid. */ + + loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX); + mem_valid = strict_memory_address_p (mode, XEXP (loc, 0)); + + if (! mem_valid && loc == secondary_memlocs[(int) mode]) + loc = copy_rtx (loc); + + /* The only time the call below will do anything is if the stack + offset is too large. In that case IND_LEVELS doesn't matter, so we + can just pass a zero. Adjust the type to be the address of the + corresponding object. If the address was valid, save the eliminated + address. If it wasn't valid, we need to make a reload each time, so + don't save it. */ + + if (! mem_valid) + { + type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS + : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS + : RELOAD_OTHER); + + find_reloads_address (mode, NULL_PTR, XEXP (loc, 0), &XEXP (loc, 0), + opnum, type, 0); + } + + secondary_memlocs_elim[(int) mode][opnum] = loc; + return loc; +} + +/* Clear any secondary memory locations we've made. */ + +void +clear_secondary_mem () +{ + bzero (secondary_memlocs, sizeof secondary_memlocs); +} +#endif /* SECONDARY_MEMORY_NEEDED */ + +/* Record one reload that needs to be performed. + IN is an rtx saying where the data are to be found before this instruction. + OUT says where they must be stored after the instruction. + (IN is zero for data not read, and OUT is zero for data not written.) + INLOC and OUTLOC point to the places in the instructions where + IN and OUT were found. + If IN and OUT are both non-zero, it means the same register must be used + to reload both IN and OUT. + + CLASS is a register class required for the reloaded data. + INMODE is the machine mode that the instruction requires + for the reg that replaces IN and OUTMODE is likewise for OUT. + + If IN is zero, then OUT's location and mode should be passed as + INLOC and INMODE. + + STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx. + + OPTIONAL nonzero means this reload does not need to be performed: + it can be discarded if that is more convenient. + + OPNUM and TYPE say what the purpose of this reload is. + + The return value is the reload-number for this reload. + + If both IN and OUT are nonzero, in some rare cases we might + want to make two separate reloads. (Actually we never do this now.) + Therefore, the reload-number for OUT is stored in + output_reloadnum when we return; the return value applies to IN. + Usually (presently always), when IN and OUT are nonzero, + the two reload-numbers are equal, but the caller should be careful to + distinguish them. */ + +static int +push_reload (in, out, inloc, outloc, class, + inmode, outmode, strict_low, optional, opnum, type) + register rtx in, out; + rtx *inloc, *outloc; + enum reg_class class; + enum machine_mode inmode, outmode; + int strict_low; + int optional; + int opnum; + enum reload_type type; +{ + register int i; + int dont_share = 0; + rtx *in_subreg_loc = 0, *out_subreg_loc = 0; + int secondary_reload = -1; + enum insn_code secondary_icode = CODE_FOR_nothing; + + /* Compare two RTX's. */ +#define MATCHES(x, y) \ + (x == y || (x != 0 && (GET_CODE (x) == REG \ + ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \ + : rtx_equal_p (x, y) && ! side_effects_p (x)))) + + /* Indicates if two reloads purposes are for similar enough things that we + can merge their reloads. */ +#define MERGABLE_RELOADS(when1, when2, op1, op2) \ + ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \ + || ((when1) == (when2) && (op1) == (op2)) \ + || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \ + || ((when1) == RELOAD_FOR_OPERAND_ADDRESS \ + && (when2) == RELOAD_FOR_OPERAND_ADDRESS) \ + || ((when1) == RELOAD_FOR_OTHER_ADDRESS \ + && (when2) == RELOAD_FOR_OTHER_ADDRESS)) + + /* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */ +#define MERGE_TO_OTHER(when1, when2, op1, op2) \ + ((when1) != (when2) \ + || ! ((op1) == (op2) \ + || (when1) == RELOAD_FOR_INPUT \ + || (when1) == RELOAD_FOR_OPERAND_ADDRESS \ + || (when1) == RELOAD_FOR_OTHER_ADDRESS)) + + /* INMODE and/or OUTMODE could be VOIDmode if no mode + has been specified for the operand. In that case, + use the operand's mode as the mode to reload. */ + if (inmode == VOIDmode && in != 0) + inmode = GET_MODE (in); + if (outmode == VOIDmode && out != 0) + outmode = GET_MODE (out); + + /* If IN is a pseudo register everywhere-equivalent to a constant, and + it is not in a hard register, reload straight from the constant, + since we want to get rid of such pseudo registers. + Often this is done earlier, but not always in find_reloads_address. */ + if (in != 0 && GET_CODE (in) == REG) + { + register int regno = REGNO (in); + + if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 + && reg_equiv_constant[regno] != 0) + in = reg_equiv_constant[regno]; + } + + /* Likewise for OUT. Of course, OUT will never be equivalent to + an actual constant, but it might be equivalent to a memory location + (in the case of a parameter). */ + if (out != 0 && GET_CODE (out) == REG) + { + register int regno = REGNO (out); + + if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 + && reg_equiv_constant[regno] != 0) + out = reg_equiv_constant[regno]; + } + + /* If we have a read-write operand with an address side-effect, + change either IN or OUT so the side-effect happens only once. */ + if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out)) + { + if (GET_CODE (XEXP (in, 0)) == POST_INC + || GET_CODE (XEXP (in, 0)) == POST_DEC) + in = gen_rtx (MEM, GET_MODE (in), XEXP (XEXP (in, 0), 0)); + if (GET_CODE (XEXP (in, 0)) == PRE_INC + || GET_CODE (XEXP (in, 0)) == PRE_DEC) + out = gen_rtx (MEM, GET_MODE (out), XEXP (XEXP (out, 0), 0)); + } + + /* If we are reloading a (SUBREG (MEM ...) ...) or (SUBREG constant ...), + really reload just the inside expression in its own mode. + If we have (SUBREG:M1 (REG:M2 ...) ...) with M1 wider than M2 and the + register is a pseudo, this will become the same as the above case. + Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where + either M1 is not valid for R or M2 is wider than a word but we only + need one word to store an M2-sized quantity in R. + (However, if OUT is nonzero, we need to reload the reg *and* + the subreg, so do nothing here, and let following statement handle it.) + + Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere; + we can't handle it here because CONST_INT does not indicate a mode. + + Similarly, we must reload the inside expression if we have a + STRICT_LOW_PART (presumably, in == out in the cas). + + Also reload the inner expression if it does not require a secondary + reload but the SUBREG does. */ + + if (in != 0 && GET_CODE (in) == SUBREG + && (GET_CODE (SUBREG_REG (in)) != REG + || strict_low + || (GET_CODE (SUBREG_REG (in)) == REG + && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER + && (GET_MODE_SIZE (inmode) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))) + || (REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER + /* The case where out is nonzero + is handled differently in the following statement. */ + && (out == 0 || SUBREG_WORD (in) == 0) + && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)), inmode) + || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) + > UNITS_PER_WORD) + && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) + / UNITS_PER_WORD) + != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), + GET_MODE (SUBREG_REG (in))))))) +#ifdef SECONDARY_INPUT_RELOAD_CLASS + || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS + && (SECONDARY_INPUT_RELOAD_CLASS (class, + GET_MODE (SUBREG_REG (in)), + SUBREG_REG (in)) + == NO_REGS)) +#endif + )) + { + in_subreg_loc = inloc; + inloc = &SUBREG_REG (in); + in = *inloc; +#if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined(BYTE_LOADS_SIGN_EXTEND) + if (GET_CODE (in) == MEM) + /* This is supposed to happen only for paradoxical subregs made by + combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ + if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode)) + abort (); +#endif + inmode = GET_MODE (in); + } + + /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where + either M1 is not valid for R or M2 is wider than a word but we only + need one word to store an M2-sized quantity in R. + + However, we must reload the inner reg *as well as* the subreg in + that case. */ + + if (in != 0 && GET_CODE (in) == SUBREG + && GET_CODE (SUBREG_REG (in)) == REG + && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER + && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)), inmode) + || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) + > UNITS_PER_WORD) + && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) + / UNITS_PER_WORD) + != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), + GET_MODE (SUBREG_REG (in))))))) + { + push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), NULL_PTR, + GENERAL_REGS, VOIDmode, VOIDmode, 0, 0, opnum, type); + } + + + /* Similarly for paradoxical and problematical SUBREGs on the output. + Note that there is no reason we need worry about the previous value + of SUBREG_REG (out); even if wider than out, + storing in a subreg is entitled to clobber it all + (except in the case of STRICT_LOW_PART, + and in that case the constraint should label it input-output.) */ + if (out != 0 && GET_CODE (out) == SUBREG + && (GET_CODE (SUBREG_REG (out)) != REG + || strict_low + || (GET_CODE (SUBREG_REG (out)) == REG + && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER + && (GET_MODE_SIZE (outmode) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))) + || (GET_CODE (SUBREG_REG (out)) == REG + && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER + && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (out)), outmode) + || (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) + > UNITS_PER_WORD) + && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) + / UNITS_PER_WORD) + != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), + GET_MODE (SUBREG_REG (out))))))) +#ifdef SECONDARY_OUTPUT_RELOAD_CLASS + || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS + && (SECONDARY_OUTPUT_RELOAD_CLASS (class, + GET_MODE (SUBREG_REG (out)), + SUBREG_REG (out)) + == NO_REGS)) +#endif + )) + { + out_subreg_loc = outloc; + outloc = &SUBREG_REG (out); + out = *outloc; +#if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined(BYTE_LOADS_SIGN_EXTEND) + if (GET_CODE (out) == MEM + && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode)) + abort (); +#endif + outmode = GET_MODE (out); + } + + /* If IN appears in OUT, we can't share any input-only reload for IN. */ + if (in != 0 && out != 0 && GET_CODE (out) == MEM + && (GET_CODE (in) == REG || GET_CODE (in) == MEM) + && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0))) + dont_share = 1; + + /* If IN is a SUBREG of a hard register, make a new REG. This + simplifies some of the cases below. */ + + if (in != 0 && GET_CODE (in) == SUBREG && GET_CODE (SUBREG_REG (in)) == REG + && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER) + in = gen_rtx (REG, GET_MODE (in), + REGNO (SUBREG_REG (in)) + SUBREG_WORD (in)); + + /* Similarly for OUT. */ + if (out != 0 && GET_CODE (out) == SUBREG + && GET_CODE (SUBREG_REG (out)) == REG + && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER) + out = gen_rtx (REG, GET_MODE (out), + REGNO (SUBREG_REG (out)) + SUBREG_WORD (out)); + + /* Narrow down the class of register wanted if that is + desirable on this machine for efficiency. */ + if (in != 0) + class = PREFERRED_RELOAD_CLASS (in, class); + + /* Output reloads may need analogous treatment, different in detail. */ +#ifdef PREFERRED_OUTPUT_RELOAD_CLASS + if (out != 0) + class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class); +#endif + + /* Make sure we use a class that can handle the actual pseudo + inside any subreg. For example, on the 386, QImode regs + can appear within SImode subregs. Although GENERAL_REGS + can handle SImode, QImode needs a smaller class. */ +#ifdef LIMIT_RELOAD_CLASS + if (in_subreg_loc) + class = LIMIT_RELOAD_CLASS (inmode, class); + else if (in != 0 && GET_CODE (in) == SUBREG) + class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class); + + if (out_subreg_loc) + class = LIMIT_RELOAD_CLASS (outmode, class); + if (out != 0 && GET_CODE (out) == SUBREG) + class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class); +#endif + + /* Verify that this class is at least possible for the mode that + is specified. */ + if (this_insn_is_asm) + { + enum machine_mode mode; + if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) + mode = inmode; + else + mode = outmode; + if (mode == VOIDmode) + { + error_for_asm (this_insn, "cannot reload integer constant operand in `asm'"); + mode = word_mode; + if (in != 0) + inmode = word_mode; + if (out != 0) + outmode = word_mode; + } + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (HARD_REGNO_MODE_OK (i, mode) + && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)) + { + int nregs = HARD_REGNO_NREGS (i, mode); + + int j; + for (j = 1; j < nregs; j++) + if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j)) + break; + if (j == nregs) + break; + } + if (i == FIRST_PSEUDO_REGISTER) + { + error_for_asm (this_insn, "impossible register constraint in `asm'"); + class = ALL_REGS; + } + } + + if (class == NO_REGS) + abort (); + + /* We can use an existing reload if the class is right + and at least one of IN and OUT is a match + and the other is at worst neutral. + (A zero compared against anything is neutral.) + + If SMALL_REGISTER_CLASSES, don't use existing reloads unless they are + for the same thing since that can cause us to need more reload registers + than we otherwise would. */ + + for (i = 0; i < n_reloads; i++) + if ((reg_class_subset_p (class, reload_reg_class[i]) + || reg_class_subset_p (reload_reg_class[i], class)) + /* If the existing reload has a register, it must fit our class. */ + && (reload_reg_rtx[i] == 0 + || TEST_HARD_REG_BIT (reg_class_contents[(int) class], + true_regnum (reload_reg_rtx[i]))) + && ((in != 0 && MATCHES (reload_in[i], in) && ! dont_share + && (out == 0 || reload_out[i] == 0 || MATCHES (reload_out[i], out))) + || + (out != 0 && MATCHES (reload_out[i], out) + && (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in)))) + && (reg_class_size[(int) class] == 1 +#ifdef SMALL_REGISTER_CLASSES + || 1 +#endif + ) + && MERGABLE_RELOADS (type, reload_when_needed[i], + opnum, reload_opnum[i])) + break; + + /* Reloading a plain reg for input can match a reload to postincrement + that reg, since the postincrement's value is the right value. + Likewise, it can match a preincrement reload, since we regard + the preincrementation as happening before any ref in this insn + to that register. */ + if (i == n_reloads) + for (i = 0; i < n_reloads; i++) + if ((reg_class_subset_p (class, reload_reg_class[i]) + || reg_class_subset_p (reload_reg_class[i], class)) + /* If the existing reload has a register, it must fit our class. */ + && (reload_reg_rtx[i] == 0 + || TEST_HARD_REG_BIT (reg_class_contents[(int) class], + true_regnum (reload_reg_rtx[i]))) + && out == 0 && reload_out[i] == 0 && reload_in[i] != 0 + && ((GET_CODE (in) == REG + && (GET_CODE (reload_in[i]) == POST_INC + || GET_CODE (reload_in[i]) == POST_DEC + || GET_CODE (reload_in[i]) == PRE_INC + || GET_CODE (reload_in[i]) == PRE_DEC) + && MATCHES (XEXP (reload_in[i], 0), in)) + || + (GET_CODE (reload_in[i]) == REG + && (GET_CODE (in) == POST_INC + || GET_CODE (in) == POST_DEC + || GET_CODE (in) == PRE_INC + || GET_CODE (in) == PRE_DEC) + && MATCHES (XEXP (in, 0), reload_in[i]))) + && (reg_class_size[(int) class] == 1 +#ifdef SMALL_REGISTER_CLASSES + || 1 +#endif + ) + && MERGABLE_RELOADS (type, reload_when_needed[i], + opnum, reload_opnum[i])) + { + /* Make sure reload_in ultimately has the increment, + not the plain register. */ + if (GET_CODE (in) == REG) + in = reload_in[i]; + break; + } + + if (i == n_reloads) + { +#ifdef HAVE_SECONDARY_RELOADS + enum reg_class secondary_class = NO_REGS; + enum reg_class secondary_out_class = NO_REGS; + enum machine_mode secondary_mode = inmode; + enum machine_mode secondary_out_mode = outmode; + enum insn_code secondary_icode; + enum insn_code secondary_out_icode = CODE_FOR_nothing; + enum reg_class tertiary_class = NO_REGS; + enum reg_class tertiary_out_class = NO_REGS; + enum machine_mode tertiary_mode; + enum machine_mode tertiary_out_mode; + enum insn_code tertiary_icode; + enum insn_code tertiary_out_icode = CODE_FOR_nothing; + int tertiary_reload = -1; + + /* See if we need a secondary reload register to move between + CLASS and IN or CLASS and OUT. Get the modes and icodes to + use for each of them if so. */ + +#ifdef SECONDARY_INPUT_RELOAD_CLASS + if (in != 0) + secondary_class + = find_secondary_reload (in, class, inmode, 1, &secondary_icode, + &secondary_mode, &tertiary_class, + &tertiary_icode, &tertiary_mode); +#endif + +#ifdef SECONDARY_OUTPUT_RELOAD_CLASS + if (out != 0 && GET_CODE (out) != SCRATCH) + secondary_out_class + = find_secondary_reload (out, class, outmode, 0, + &secondary_out_icode, &secondary_out_mode, + &tertiary_out_class, &tertiary_out_icode, + &tertiary_out_mode); +#endif + + /* We can only record one secondary and one tertiary reload. If both + IN and OUT need secondary reloads, we can only make an in-out + reload if neither need an insn and if the classes are compatible. + If they aren't, all we can do is abort since making two separate + reloads is invalid. */ + + if (secondary_class != NO_REGS && secondary_out_class != NO_REGS + && reg_class_subset_p (secondary_out_class, secondary_class)) + secondary_class = secondary_out_class; + + if (secondary_class != NO_REGS && secondary_out_class != NO_REGS + && (! reg_class_subset_p (secondary_class, secondary_out_class) + || secondary_icode != CODE_FOR_nothing + || secondary_out_icode != CODE_FOR_nothing)) + abort (); + + /* If we need a secondary reload for OUT but not IN, copy the + information. */ + if (secondary_class == NO_REGS && secondary_out_class != NO_REGS) + { + secondary_class = secondary_out_class; + secondary_icode = secondary_out_icode; + tertiary_class = tertiary_out_class; + tertiary_icode = tertiary_out_icode; + tertiary_mode = tertiary_out_mode; + } + + if (secondary_class != NO_REGS) + { + /* Secondary reloads don't conflict as badly as the primary object + being reload. Specifically, we can always treat them as + being for an input or output address and hence allowed to be + reused in the same manner such address components could be + reused. This is used as the reload_type for our secondary + reloads. */ + + enum reload_type secondary_type + = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS + : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS + : type); + + /* If we need a tertiary reload, see if we have one we can reuse + or else make one. */ + + if (tertiary_class != NO_REGS) + { + for (tertiary_reload = 0; tertiary_reload < n_reloads; + tertiary_reload++) + if (reload_secondary_p[tertiary_reload] + && (reg_class_subset_p (tertiary_class, + reload_reg_class[tertiary_reload]) + || reg_class_subset_p (reload_reg_class[tertiary_reload], + tertiary_class)) + && ((reload_inmode[tertiary_reload] == tertiary_mode) + || reload_inmode[tertiary_reload] == VOIDmode) + && ((reload_outmode[tertiary_reload] == tertiary_mode) + || reload_outmode[tertiary_reload] == VOIDmode) + && (reload_secondary_icode[tertiary_reload] + == CODE_FOR_nothing) + && (reg_class_size[(int) tertiary_class] == 1 +#ifdef SMALL_REGISTER_CLASSES + || 1 +#endif + ) + && MERGABLE_RELOADS (secondary_type, + reload_when_needed[tertiary_reload], + opnum, reload_opnum[tertiary_reload])) + { + if (tertiary_mode != VOIDmode) + reload_inmode[tertiary_reload] = tertiary_mode; + if (tertiary_out_mode != VOIDmode) + reload_outmode[tertiary_reload] = tertiary_mode; + if (reg_class_subset_p (tertiary_class, + reload_reg_class[tertiary_reload])) + reload_reg_class[tertiary_reload] = tertiary_class; + if (MERGE_TO_OTHER (secondary_type, + reload_when_needed[tertiary_reload], + opnum, + reload_opnum[tertiary_reload])) + reload_when_needed[tertiary_reload] = RELOAD_OTHER; + reload_opnum[tertiary_reload] + = MIN (reload_opnum[tertiary_reload], opnum); + reload_optional[tertiary_reload] &= optional; + reload_secondary_p[tertiary_reload] = 1; + } + + if (tertiary_reload == n_reloads) + { + /* We need to make a new tertiary reload for this register + class. */ + reload_in[tertiary_reload] = reload_out[tertiary_reload] = 0; + reload_reg_class[tertiary_reload] = tertiary_class; + reload_inmode[tertiary_reload] = tertiary_mode; + reload_outmode[tertiary_reload] = tertiary_mode; + reload_reg_rtx[tertiary_reload] = 0; + reload_optional[tertiary_reload] = optional; + reload_inc[tertiary_reload] = 0; + /* Maybe we could combine these, but it seems too tricky. */ + reload_nocombine[tertiary_reload] = 1; + reload_in_reg[tertiary_reload] = 0; + reload_opnum[tertiary_reload] = opnum; + reload_when_needed[tertiary_reload] = secondary_type; + reload_secondary_reload[tertiary_reload] = -1; + reload_secondary_icode[tertiary_reload] = CODE_FOR_nothing; + reload_secondary_p[tertiary_reload] = 1; + + n_reloads++; + i = n_reloads; + } + } + + /* See if we can reuse an existing secondary reload. */ + for (secondary_reload = 0; secondary_reload < n_reloads; + secondary_reload++) + if (reload_secondary_p[secondary_reload] + && (reg_class_subset_p (secondary_class, + reload_reg_class[secondary_reload]) + || reg_class_subset_p (reload_reg_class[secondary_reload], + secondary_class)) + && ((reload_inmode[secondary_reload] == secondary_mode) + || reload_inmode[secondary_reload] == VOIDmode) + && ((reload_outmode[secondary_reload] == secondary_out_mode) + || reload_outmode[secondary_reload] == VOIDmode) + && reload_secondary_reload[secondary_reload] == tertiary_reload + && reload_secondary_icode[secondary_reload] == tertiary_icode + && (reg_class_size[(int) secondary_class] == 1 +#ifdef SMALL_REGISTER_CLASSES + || 1 +#endif + ) + && MERGABLE_RELOADS (secondary_type, + reload_when_needed[secondary_reload], + opnum, reload_opnum[secondary_reload])) + { + if (secondary_mode != VOIDmode) + reload_inmode[secondary_reload] = secondary_mode; + if (secondary_out_mode != VOIDmode) + reload_outmode[secondary_reload] = secondary_out_mode; + if (reg_class_subset_p (secondary_class, + reload_reg_class[secondary_reload])) + reload_reg_class[secondary_reload] = secondary_class; + if (MERGE_TO_OTHER (secondary_type, + reload_when_needed[secondary_reload], + opnum, reload_opnum[secondary_reload])) + reload_when_needed[secondary_reload] = RELOAD_OTHER; + reload_opnum[secondary_reload] + = MIN (reload_opnum[secondary_reload], opnum); + reload_optional[secondary_reload] &= optional; + reload_secondary_p[secondary_reload] = 1; + } + + if (secondary_reload == n_reloads) + { + /* We need to make a new secondary reload for this register + class. */ + reload_in[secondary_reload] = reload_out[secondary_reload] = 0; + reload_reg_class[secondary_reload] = secondary_class; + reload_inmode[secondary_reload] = secondary_mode; + reload_outmode[secondary_reload] = secondary_out_mode; + reload_reg_rtx[secondary_reload] = 0; + reload_optional[secondary_reload] = optional; + reload_inc[secondary_reload] = 0; + /* Maybe we could combine these, but it seems too tricky. */ + reload_nocombine[secondary_reload] = 1; + reload_in_reg[secondary_reload] = 0; + reload_opnum[secondary_reload] = opnum; + reload_when_needed[secondary_reload] = secondary_type; + reload_secondary_reload[secondary_reload] = tertiary_reload; + reload_secondary_icode[secondary_reload] = tertiary_icode; + reload_secondary_p[secondary_reload] = 1; + + n_reloads++; + i = n_reloads; + +#ifdef SECONDARY_MEMORY_NEEDED + /* If we need a memory location to copy between the two + reload regs, set it up now. */ + + if (in != 0 && secondary_icode == CODE_FOR_nothing + && SECONDARY_MEMORY_NEEDED (secondary_class, class, inmode)) + get_secondary_mem (in, inmode, opnum, type); + + if (out != 0 && secondary_icode == CODE_FOR_nothing + && SECONDARY_MEMORY_NEEDED (class, secondary_class, outmode)) + get_secondary_mem (out, outmode, opnum, type); +#endif + } + } +#endif + + /* We found no existing reload suitable for re-use. + So add an additional reload. */ + + reload_in[i] = in; + reload_out[i] = out; + reload_reg_class[i] = class; + reload_inmode[i] = inmode; + reload_outmode[i] = outmode; + reload_reg_rtx[i] = 0; + reload_optional[i] = optional; + reload_inc[i] = 0; + reload_nocombine[i] = 0; + reload_in_reg[i] = inloc ? *inloc : 0; + reload_opnum[i] = opnum; + reload_when_needed[i] = type; + reload_secondary_reload[i] = secondary_reload; + reload_secondary_icode[i] = secondary_icode; + reload_secondary_p[i] = 0; + + n_reloads++; + +#ifdef SECONDARY_MEMORY_NEEDED + /* If a memory location is needed for the copy, make one. */ + if (in != 0 && GET_CODE (in) == REG + && REGNO (in) < FIRST_PSEUDO_REGISTER + && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), + class, inmode)) + get_secondary_mem (in, inmode, opnum, type); + + if (out != 0 && GET_CODE (out) == REG + && REGNO (out) < FIRST_PSEUDO_REGISTER + && SECONDARY_MEMORY_NEEDED (class, REGNO_REG_CLASS (REGNO (out)), + outmode)) + get_secondary_mem (out, outmode, opnum, type); +#endif + } + else + { + /* We are reusing an existing reload, + but we may have additional information for it. + For example, we may now have both IN and OUT + while the old one may have just one of them. */ + + if (inmode != VOIDmode) + reload_inmode[i] = inmode; + if (outmode != VOIDmode) + reload_outmode[i] = outmode; + if (in != 0) + reload_in[i] = in; + if (out != 0) + reload_out[i] = out; + if (reg_class_subset_p (class, reload_reg_class[i])) + reload_reg_class[i] = class; + reload_optional[i] &= optional; + if (MERGE_TO_OTHER (type, reload_when_needed[i], + opnum, reload_opnum[i])) + reload_when_needed[i] = RELOAD_OTHER; + reload_opnum[i] = MIN (reload_opnum[i], opnum); + } + + /* If the ostensible rtx being reload differs from the rtx found + in the location to substitute, this reload is not safe to combine + because we cannot reliably tell whether it appears in the insn. */ + + if (in != 0 && in != *inloc) + reload_nocombine[i] = 1; + +#if 0 + /* This was replaced by changes in find_reloads_address_1 and the new + function inc_for_reload, which go with a new meaning of reload_inc. */ + + /* If this is an IN/OUT reload in an insn that sets the CC, + it must be for an autoincrement. It doesn't work to store + the incremented value after the insn because that would clobber the CC. + So we must do the increment of the value reloaded from, + increment it, store it back, then decrement again. */ + if (out != 0 && sets_cc0_p (PATTERN (this_insn))) + { + out = 0; + reload_out[i] = 0; + reload_inc[i] = find_inc_amount (PATTERN (this_insn), in); + /* If we did not find a nonzero amount-to-increment-by, + that contradicts the belief that IN is being incremented + in an address in this insn. */ + if (reload_inc[i] == 0) + abort (); + } +#endif + + /* If we will replace IN and OUT with the reload-reg, + record where they are located so that substitution need + not do a tree walk. */ + + if (replace_reloads) + { + if (inloc != 0) + { + register struct replacement *r = &replacements[n_replacements++]; + r->what = i; + r->subreg_loc = in_subreg_loc; + r->where = inloc; + r->mode = inmode; + } + if (outloc != 0 && outloc != inloc) + { + register struct replacement *r = &replacements[n_replacements++]; + r->what = i; + r->where = outloc; + r->subreg_loc = out_subreg_loc; + r->mode = outmode; + } + } + + /* If this reload is just being introduced and it has both + an incoming quantity and an outgoing quantity that are + supposed to be made to match, see if either one of the two + can serve as the place to reload into. + + If one of them is acceptable, set reload_reg_rtx[i] + to that one. */ + + if (in != 0 && out != 0 && in != out && reload_reg_rtx[i] == 0) + { + reload_reg_rtx[i] = find_dummy_reload (in, out, inloc, outloc, + reload_reg_class[i], i); + + /* If the outgoing register already contains the same value + as the incoming one, we can dispense with loading it. + The easiest way to tell the caller that is to give a phony + value for the incoming operand (same as outgoing one). */ + if (reload_reg_rtx[i] == out + && (GET_CODE (in) == REG || CONSTANT_P (in)) + && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out), + static_reload_reg_p, i, inmode)) + reload_in[i] = out; + } + + /* If this is an input reload and the operand contains a register that + dies in this insn and is used nowhere else, see if it is the right class + to be used for this reload. Use it if so. (This occurs most commonly + in the case of paradoxical SUBREGs and in-out reloads). We cannot do + this if it is also an output reload that mentions the register unless + the output is a SUBREG that clobbers an entire register. + + Note that the operand might be one of the spill regs, if it is a + pseudo reg and we are in a block where spilling has not taken place. + But if there is no spilling in this block, that is OK. + An explicitly used hard reg cannot be a spill reg. */ + + if (reload_reg_rtx[i] == 0 && in != 0) + { + rtx note; + int regno; + + for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) + if (REG_NOTE_KIND (note) == REG_DEAD + && GET_CODE (XEXP (note, 0)) == REG + && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER + && reg_mentioned_p (XEXP (note, 0), in) + && ! refers_to_regno_for_reload_p (regno, + (regno + + HARD_REGNO_NREGS (regno, + inmode)), + PATTERN (this_insn), inloc) + /* If this is also an output reload, IN cannot be used as + the reload register if it is set in this insn unless IN + is also OUT. */ + && (out == 0 || in == out + || ! hard_reg_set_here_p (regno, + (regno + + HARD_REGNO_NREGS (regno, + inmode)), + PATTERN (this_insn))) + /* ??? Why is this code so different from the previous? + Is there any simple coherent way to describe the two together? + What's going on here. */ + && (in != out + || (GET_CODE (in) == SUBREG + && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1)) + / UNITS_PER_WORD) + == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) + + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) + /* Make sure the operand fits in the reg that dies. */ + && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) + && HARD_REGNO_MODE_OK (regno, inmode) + && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) + && HARD_REGNO_MODE_OK (regno, outmode) + && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) + && !fixed_regs[regno]) + { + reload_reg_rtx[i] = gen_rtx (REG, inmode, regno); + break; + } + } + + if (out) + output_reloadnum = i; + + return i; +} + +/* Record an additional place we must replace a value + for which we have already recorded a reload. + RELOADNUM is the value returned by push_reload + when the reload was recorded. + This is used in insn patterns that use match_dup. */ + +static void +push_replacement (loc, reloadnum, mode) + rtx *loc; + int reloadnum; + enum machine_mode mode; +{ + if (replace_reloads) + { + register struct replacement *r = &replacements[n_replacements++]; + r->what = reloadnum; + r->where = loc; + r->subreg_loc = 0; + r->mode = mode; + } +} + +/* Transfer all replacements that used to be in reload FROM to be in + reload TO. */ + +void +transfer_replacements (to, from) + int to, from; +{ + int i; + + for (i = 0; i < n_replacements; i++) + if (replacements[i].what == from) + replacements[i].what = to; +} + +/* If there is only one output reload, and it is not for an earlyclobber + operand, try to combine it with a (logically unrelated) input reload + to reduce the number of reload registers needed. + + This is safe if the input reload does not appear in + the value being output-reloaded, because this implies + it is not needed any more once the original insn completes. + + If that doesn't work, see we can use any of the registers that + die in this insn as a reload register. We can if it is of the right + class and does not appear in the value being output-reloaded. */ + +static void +combine_reloads () +{ + int i; + int output_reload = -1; + rtx note; + + /* Find the output reload; return unless there is exactly one + and that one is mandatory. */ + + for (i = 0; i < n_reloads; i++) + if (reload_out[i] != 0) + { + if (output_reload >= 0) + return; + output_reload = i; + } + + if (output_reload < 0 || reload_optional[output_reload]) + return; + + /* An input-output reload isn't combinable. */ + + if (reload_in[output_reload] != 0) + return; + + /* If this reload is for an earlyclobber operand, we can't do anything. */ + + for (i = 0; i < n_earlyclobbers; i++) + if (reload_out[output_reload] == reload_earlyclobbers[i]) + return; + + /* Check each input reload; can we combine it? */ + + for (i = 0; i < n_reloads; i++) + if (reload_in[i] && ! reload_optional[i] && ! reload_nocombine[i] + /* Life span of this reload must not extend past main insn. */ + && reload_when_needed[i] != RELOAD_FOR_OUTPUT_ADDRESS + && reload_when_needed[i] != RELOAD_OTHER + && (CLASS_MAX_NREGS (reload_reg_class[i], reload_inmode[i]) + == CLASS_MAX_NREGS (reload_reg_class[output_reload], + reload_outmode[output_reload])) + && reload_inc[i] == 0 + && reload_reg_rtx[i] == 0 + /* Don't combine two reloads with different secondary reloads. */ + && (reload_secondary_reload[i] == reload_secondary_reload[output_reload] + || reload_secondary_reload[i] == -1 + || reload_secondary_reload[output_reload] == -1) +#ifdef SECONDARY_MEMORY_NEEDED + /* Likewise for different secondary memory locations. */ + && (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]] == 0 + || secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]] == 0 + || rtx_equal_p (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]], + secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]])) +#endif +#ifdef SMALL_REGISTER_CLASSES + && reload_reg_class[i] == reload_reg_class[output_reload] +#else + && (reg_class_subset_p (reload_reg_class[i], + reload_reg_class[output_reload]) + || reg_class_subset_p (reload_reg_class[output_reload], + reload_reg_class[i])) +#endif + && (MATCHES (reload_in[i], reload_out[output_reload]) + /* Args reversed because the first arg seems to be + the one that we imagine being modified + while the second is the one that might be affected. */ + || (! reg_overlap_mentioned_for_reload_p (reload_out[output_reload], + reload_in[i]) + /* However, if the input is a register that appears inside + the output, then we also can't share. + Imagine (set (mem (reg 69)) (plus (reg 69) ...)). + If the same reload reg is used for both reg 69 and the + result to be stored in memory, then that result + will clobber the address of the memory ref. */ + && ! (GET_CODE (reload_in[i]) == REG + && reg_overlap_mentioned_for_reload_p (reload_in[i], + reload_out[output_reload])))) + && (reg_class_size[(int) reload_reg_class[i]] +#ifdef SMALL_REGISTER_CLASSES + || 1 +#endif + ) + /* We will allow making things slightly worse by combining an + input and an output, but no worse than that. */ + && (reload_when_needed[i] == RELOAD_FOR_INPUT + || reload_when_needed[i] == RELOAD_FOR_OUTPUT)) + { + int j; + + /* We have found a reload to combine with! */ + reload_out[i] = reload_out[output_reload]; + reload_outmode[i] = reload_outmode[output_reload]; + /* Mark the old output reload as inoperative. */ + reload_out[output_reload] = 0; + /* The combined reload is needed for the entire insn. */ + reload_when_needed[i] = RELOAD_OTHER; + /* If the output reload had a secondary reload, copy it. */ + if (reload_secondary_reload[output_reload] != -1) + reload_secondary_reload[i] = reload_secondary_reload[output_reload]; +#ifdef SECONDARY_MEMORY_NEEDED + /* Copy any secondary MEM. */ + if (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]] != 0) + secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]] + = secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]]; +#endif + /* If required, minimize the register class. */ + if (reg_class_subset_p (reload_reg_class[output_reload], + reload_reg_class[i])) + reload_reg_class[i] = reload_reg_class[output_reload]; + + /* Transfer all replacements from the old reload to the combined. */ + for (j = 0; j < n_replacements; j++) + if (replacements[j].what == output_reload) + replacements[j].what = i; + + return; + } + + /* If this insn has only one operand that is modified or written (assumed + to be the first), it must be the one corresponding to this reload. It + is safe to use anything that dies in this insn for that output provided + that it does not occur in the output (we already know it isn't an + earlyclobber. If this is an asm insn, give up. */ + + if (INSN_CODE (this_insn) == -1) + return; + + for (i = 1; i < insn_n_operands[INSN_CODE (this_insn)]; i++) + if (insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '=' + || insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '+') + return; + + /* See if some hard register that dies in this insn and is not used in + the output is the right class. Only works if the register we pick + up can fully hold our output reload. */ + for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) + if (REG_NOTE_KIND (note) == REG_DEAD + && GET_CODE (XEXP (note, 0)) == REG + && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0), + reload_out[output_reload]) + && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER + && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) + && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[output_reload]], + REGNO (XEXP (note, 0))) + && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) + <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0)))) + && ! fixed_regs[REGNO (XEXP (note, 0))]) + { + reload_reg_rtx[output_reload] = gen_rtx (REG, + reload_outmode[output_reload], + REGNO (XEXP (note, 0))); + return; + } +} + +/* Try to find a reload register for an in-out reload (expressions IN and OUT). + See if one of IN and OUT is a register that may be used; + this is desirable since a spill-register won't be needed. + If so, return the register rtx that proves acceptable. + + INLOC and OUTLOC are locations where IN and OUT appear in the insn. + CLASS is the register class required for the reload. + + If FOR_REAL is >= 0, it is the number of the reload, + and in some cases when it can be discovered that OUT doesn't need + to be computed, clear out reload_out[FOR_REAL]. + + If FOR_REAL is -1, this should not be done, because this call + is just to see if a register can be found, not to find and install it. */ + +static rtx +find_dummy_reload (real_in, real_out, inloc, outloc, class, for_real) + rtx real_in, real_out; + rtx *inloc, *outloc; + enum reg_class class; + int for_real; +{ + rtx in = real_in; + rtx out = real_out; + int in_offset = 0; + int out_offset = 0; + rtx value = 0; + + /* If operands exceed a word, we can't use either of them + unless they have the same size. */ + if (GET_MODE_SIZE (GET_MODE (real_out)) != GET_MODE_SIZE (GET_MODE (real_in)) + && (GET_MODE_SIZE (GET_MODE (real_out)) > UNITS_PER_WORD + || GET_MODE_SIZE (GET_MODE (real_in)) > UNITS_PER_WORD)) + return 0; + + /* Find the inside of any subregs. */ + while (GET_CODE (out) == SUBREG) + { + out_offset = SUBREG_WORD (out); + out = SUBREG_REG (out); + } + while (GET_CODE (in) == SUBREG) + { + in_offset = SUBREG_WORD (in); + in = SUBREG_REG (in); + } + + /* Narrow down the reg class, the same way push_reload will; + otherwise we might find a dummy now, but push_reload won't. */ + class = PREFERRED_RELOAD_CLASS (in, class); + + /* See if OUT will do. */ + if (GET_CODE (out) == REG + && REGNO (out) < FIRST_PSEUDO_REGISTER) + { + register int regno = REGNO (out) + out_offset; + int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_out)); + rtx saved_rtx; + + /* When we consider whether the insn uses OUT, + ignore references within IN. They don't prevent us + from copying IN into OUT, because those refs would + move into the insn that reloads IN. + + However, we only ignore IN in its role as this reload. + If the insn uses IN elsewhere and it contains OUT, + that counts. We can't be sure it's the "same" operand + so it might not go through this reload. */ + saved_rtx = *inloc; + *inloc = const0_rtx; + + if (regno < FIRST_PSEUDO_REGISTER + /* A fixed reg that can overlap other regs better not be used + for reloading in any way. */ +#ifdef OVERLAPPING_REGNO_P + && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno)) +#endif + && ! refers_to_regno_for_reload_p (regno, regno + nwords, + PATTERN (this_insn), outloc)) + { + int i; + for (i = 0; i < nwords; i++) + if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], + regno + i)) + break; + + if (i == nwords) + { + if (GET_CODE (real_out) == REG) + value = real_out; + else + value = gen_rtx (REG, GET_MODE (real_out), regno); + } + } + + *inloc = saved_rtx; + } + + /* Consider using IN if OUT was not acceptable + or if OUT dies in this insn (like the quotient in a divmod insn). + We can't use IN unless it is dies in this insn, + which means we must know accurately which hard regs are live. + Also, the result can't go in IN if IN is used within OUT. */ + if (hard_regs_live_known + && GET_CODE (in) == REG + && REGNO (in) < FIRST_PSEUDO_REGISTER + && (value == 0 + || find_reg_note (this_insn, REG_UNUSED, real_out)) + && find_reg_note (this_insn, REG_DEAD, real_in) + && !fixed_regs[REGNO (in)] + && HARD_REGNO_MODE_OK (REGNO (in), GET_MODE (out))) + { + register int regno = REGNO (in) + in_offset; + int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_in)); + + if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, NULL_PTR) + && ! hard_reg_set_here_p (regno, regno + nwords, + PATTERN (this_insn))) + { + int i; + for (i = 0; i < nwords; i++) + if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], + regno + i)) + break; + + if (i == nwords) + { + /* If we were going to use OUT as the reload reg + and changed our mind, it means OUT is a dummy that + dies here. So don't bother copying value to it. */ + if (for_real >= 0 && value == real_out) + reload_out[for_real] = 0; + if (GET_CODE (real_in) == REG) + value = real_in; + else + value = gen_rtx (REG, GET_MODE (real_in), regno); + } + } + } + + return value; +} + +/* This page contains subroutines used mainly for determining + whether the IN or an OUT of a reload can serve as the + reload register. */ + +/* Return 1 if expression X alters a hard reg in the range + from BEG_REGNO (inclusive) to END_REGNO (exclusive), + either explicitly or in the guise of a pseudo-reg allocated to REGNO. + X should be the body of an instruction. */ + +static int +hard_reg_set_here_p (beg_regno, end_regno, x) + register int beg_regno, end_regno; + rtx x; +{ + if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) + { + register rtx op0 = SET_DEST (x); + while (GET_CODE (op0) == SUBREG) + op0 = SUBREG_REG (op0); + if (GET_CODE (op0) == REG) + { + register int r = REGNO (op0); + /* See if this reg overlaps range under consideration. */ + if (r < end_regno + && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno) + return 1; + } + } + else if (GET_CODE (x) == PARALLEL) + { + register int i = XVECLEN (x, 0) - 1; + for (; i >= 0; i--) + if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i))) + return 1; + } + + return 0; +} + +/* Return 1 if ADDR is a valid memory address for mode MODE, + and check that each pseudo reg has the proper kind of + hard reg. */ + +int +strict_memory_address_p (mode, addr) + enum machine_mode mode; + register rtx addr; +{ + GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); + return 0; + + win: + return 1; +} + +/* Like rtx_equal_p except that it allows a REG and a SUBREG to match + if they are the same hard reg, and has special hacks for + autoincrement and autodecrement. + This is specifically intended for find_reloads to use + in determining whether two operands match. + X is the operand whose number is the lower of the two. + + The value is 2 if Y contains a pre-increment that matches + a non-incrementing address in X. */ + +/* ??? To be completely correct, we should arrange to pass + for X the output operand and for Y the input operand. + For now, we assume that the output operand has the lower number + because that is natural in (SET output (... input ...)). */ + +int +operands_match_p (x, y) + register rtx x, y; +{ + register int i; + register RTX_CODE code = GET_CODE (x); + register char *fmt; + int success_2; + + if (x == y) + return 1; + if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)) + && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG + && GET_CODE (SUBREG_REG (y)) == REG))) + { + register int j; + + if (code == SUBREG) + { + i = REGNO (SUBREG_REG (x)); + if (i >= FIRST_PSEUDO_REGISTER) + goto slow; + i += SUBREG_WORD (x); + } + else + i = REGNO (x); + + if (GET_CODE (y) == SUBREG) + { + j = REGNO (SUBREG_REG (y)); + if (j >= FIRST_PSEUDO_REGISTER) + goto slow; + j += SUBREG_WORD (y); + } + else + j = REGNO (y); + + /* On a WORDS_BIG_ENDIAN machine, point to the last register of a + multiple hard register group, so that for example (reg:DI 0) and + (reg:SI 1) will be considered the same register. */ + if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD + && i < FIRST_PSEUDO_REGISTER) + i += (GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD) - 1; + if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD + && j < FIRST_PSEUDO_REGISTER) + j += (GET_MODE_SIZE (GET_MODE (y)) / UNITS_PER_WORD) - 1; + + return i == j; + } + /* If two operands must match, because they are really a single + operand of an assembler insn, then two postincrements are invalid + because the assembler insn would increment only once. + On the other hand, an postincrement matches ordinary indexing + if the postincrement is the output operand. */ + if (code == POST_DEC || code == POST_INC) + return operands_match_p (XEXP (x, 0), y); + /* Two preincrements are invalid + because the assembler insn would increment only once. + On the other hand, an preincrement matches ordinary indexing + if the preincrement is the input operand. + In this case, return 2, since some callers need to do special + things when this happens. */ + if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC) + return operands_match_p (x, XEXP (y, 0)) ? 2 : 0; + + slow: + + /* Now we have disposed of all the cases + in which different rtx codes can match. */ + if (code != GET_CODE (y)) + return 0; + if (code == LABEL_REF) + return XEXP (x, 0) == XEXP (y, 0); + if (code == SYMBOL_REF) + return XSTR (x, 0) == XSTR (y, 0); + + /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ + + if (GET_MODE (x) != GET_MODE (y)) + return 0; + + /* Compare the elements. If any pair of corresponding elements + fail to match, return 0 for the whole things. */ + + success_2 = 0; + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + int val; + switch (fmt[i]) + { + case 'w': + if (XWINT (x, i) != XWINT (y, i)) + return 0; + break; + + case 'i': + if (XINT (x, i) != XINT (y, i)) + return 0; + break; + + case 'e': + val = operands_match_p (XEXP (x, i), XEXP (y, i)); + if (val == 0) + return 0; + /* If any subexpression returns 2, + we should return 2 if we are successful. */ + if (val == 2) + success_2 = 1; + break; + + case '0': + break; + + /* It is believed that rtx's at this level will never + contain anything but integers and other rtx's, + except for within LABEL_REFs and SYMBOL_REFs. */ + default: + abort (); + } + } + return 1 + success_2; +} + +/* Return the number of times character C occurs in string S. */ + +int +n_occurrences (c, s) + char c; + char *s; +{ + int n = 0; + while (*s) + n += (*s++ == c); + return n; +} + +/* Describe the range of registers or memory referenced by X. + If X is a register, set REG_FLAG and put the first register + number into START and the last plus one into END. + If X is a memory reference, put a base address into BASE + and a range of integer offsets into START and END. + If X is pushing on the stack, we can assume it causes no trouble, + so we set the SAFE field. */ + +static struct decomposition +decompose (x) + rtx x; +{ + struct decomposition val; + int all_const = 0; + + val.reg_flag = 0; + val.safe = 0; + if (GET_CODE (x) == MEM) + { + rtx base, offset = 0; + rtx addr = XEXP (x, 0); + + if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC + || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) + { + val.base = XEXP (addr, 0); + val.start = - GET_MODE_SIZE (GET_MODE (x)); + val.end = GET_MODE_SIZE (GET_MODE (x)); + val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; + return val; + } + + if (GET_CODE (addr) == CONST) + { + addr = XEXP (addr, 0); + all_const = 1; + } + if (GET_CODE (addr) == PLUS) + { + if (CONSTANT_P (XEXP (addr, 0))) + { + base = XEXP (addr, 1); + offset = XEXP (addr, 0); + } + else if (CONSTANT_P (XEXP (addr, 1))) + { + base = XEXP (addr, 0); + offset = XEXP (addr, 1); + } + } + + if (offset == 0) + { + base = addr; + offset = const0_rtx; + } + if (GET_CODE (offset) == CONST) + offset = XEXP (offset, 0); + if (GET_CODE (offset) == PLUS) + { + if (GET_CODE (XEXP (offset, 0)) == CONST_INT) + { + base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 1)); + offset = XEXP (offset, 0); + } + else if (GET_CODE (XEXP (offset, 1)) == CONST_INT) + { + base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 0)); + offset = XEXP (offset, 1); + } + else + { + base = gen_rtx (PLUS, GET_MODE (base), base, offset); + offset = const0_rtx; + } + } + else if (GET_CODE (offset) != CONST_INT) + { + base = gen_rtx (PLUS, GET_MODE (base), base, offset); + offset = const0_rtx; + } + + if (all_const && GET_CODE (base) == PLUS) + base = gen_rtx (CONST, GET_MODE (base), base); + + if (GET_CODE (offset) != CONST_INT) + abort (); + + val.start = INTVAL (offset); + val.end = val.start + GET_MODE_SIZE (GET_MODE (x)); + val.base = base; + return val; + } + else if (GET_CODE (x) == REG) + { + val.reg_flag = 1; + val.start = true_regnum (x); + if (val.start < 0) + { + /* A pseudo with no hard reg. */ + val.start = REGNO (x); + val.end = val.start + 1; + } + else + /* A hard reg. */ + val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); + } + else if (GET_CODE (x) == SUBREG) + { + if (GET_CODE (SUBREG_REG (x)) != REG) + /* This could be more precise, but it's good enough. */ + return decompose (SUBREG_REG (x)); + val.reg_flag = 1; + val.start = true_regnum (x); + if (val.start < 0) + return decompose (SUBREG_REG (x)); + else + /* A hard reg. */ + val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); + } + else if (CONSTANT_P (x) + /* This hasn't been assigned yet, so it can't conflict yet. */ + || GET_CODE (x) == SCRATCH) + val.safe = 1; + else + abort (); + return val; +} + +/* Return 1 if altering Y will not modify the value of X. + Y is also described by YDATA, which should be decompose (Y). */ + +static int +immune_p (x, y, ydata) + rtx x, y; + struct decomposition ydata; +{ + struct decomposition xdata; + + if (ydata.reg_flag) + return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, NULL_PTR); + if (ydata.safe) + return 1; + + if (GET_CODE (y) != MEM) + abort (); + /* If Y is memory and X is not, Y can't affect X. */ + if (GET_CODE (x) != MEM) + return 1; + + xdata = decompose (x); + + if (! rtx_equal_p (xdata.base, ydata.base)) + { + /* If bases are distinct symbolic constants, there is no overlap. */ + if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base)) + return 1; + /* Constants and stack slots never overlap. */ + if (CONSTANT_P (xdata.base) + && (ydata.base == frame_pointer_rtx + || ydata.base == stack_pointer_rtx)) + return 1; + if (CONSTANT_P (ydata.base) + && (xdata.base == frame_pointer_rtx + || xdata.base == stack_pointer_rtx)) + return 1; + /* If either base is variable, we don't know anything. */ + return 0; + } + + + return (xdata.start >= ydata.end || ydata.start >= xdata.end); +} + +/* Similar, but calls decompose. */ + +int +safe_from_earlyclobber (op, clobber) + rtx op, clobber; +{ + struct decomposition early_data; + + early_data = decompose (clobber); + return immune_p (op, clobber, early_data); +} + +/* Main entry point of this file: search the body of INSN + for values that need reloading and record them with push_reload. + REPLACE nonzero means record also where the values occur + so that subst_reloads can be used. + + IND_LEVELS says how many levels of indirection are supported by this + machine; a value of zero means that a memory reference is not a valid + memory address. + + LIVE_KNOWN says we have valid information about which hard + regs are live at each point in the program; this is true when + we are called from global_alloc but false when stupid register + allocation has been done. + + RELOAD_REG_P if nonzero is a vector indexed by hard reg number + which is nonnegative if the reg has been commandeered for reloading into. + It is copied into STATIC_RELOAD_REG_P and referenced from there + by various subroutines. */ + +void +find_reloads (insn, replace, ind_levels, live_known, reload_reg_p) + rtx insn; + int replace, ind_levels; + int live_known; + short *reload_reg_p; +{ +#ifdef REGISTER_CONSTRAINTS + + register int insn_code_number; + register int i, j; + int noperands; + /* These are the constraints for the insn. We don't change them. */ + char *constraints1[MAX_RECOG_OPERANDS]; + /* These start out as the constraints for the insn + and they are chewed up as we consider alternatives. */ + char *constraints[MAX_RECOG_OPERANDS]; + /* These are the preferred classes for an operand, or NO_REGS if it isn't + a register. */ + enum reg_class preferred_class[MAX_RECOG_OPERANDS]; + char pref_or_nothing[MAX_RECOG_OPERANDS]; + /* Nonzero for a MEM operand whose entire address needs a reload. */ + int address_reloaded[MAX_RECOG_OPERANDS]; + /* Value of enum reload_type to use for operand. */ + enum reload_type operand_type[MAX_RECOG_OPERANDS]; + /* Value of enum reload_type to use within address of operand. */ + enum reload_type address_type[MAX_RECOG_OPERANDS]; + /* Save the usage of each operand. */ + enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS]; + int no_input_reloads = 0, no_output_reloads = 0; + int n_alternatives; + int this_alternative[MAX_RECOG_OPERANDS]; + char this_alternative_win[MAX_RECOG_OPERANDS]; + char this_alternative_offmemok[MAX_RECOG_OPERANDS]; + char this_alternative_earlyclobber[MAX_RECOG_OPERANDS]; + int this_alternative_matches[MAX_RECOG_OPERANDS]; + int swapped; + int goal_alternative[MAX_RECOG_OPERANDS]; + int this_alternative_number; + int goal_alternative_number; + int operand_reloadnum[MAX_RECOG_OPERANDS]; + int goal_alternative_matches[MAX_RECOG_OPERANDS]; + int goal_alternative_matched[MAX_RECOG_OPERANDS]; + char goal_alternative_win[MAX_RECOG_OPERANDS]; + char goal_alternative_offmemok[MAX_RECOG_OPERANDS]; + char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS]; + int goal_alternative_swapped; + int best; + int commutative; + char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; + rtx substed_operand[MAX_RECOG_OPERANDS]; + rtx body = PATTERN (insn); + rtx set = single_set (insn); + int goal_earlyclobber, this_earlyclobber; + enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; + + this_insn = insn; + this_insn_is_asm = 0; /* Tentative. */ + n_reloads = 0; + n_replacements = 0; + n_memlocs = 0; + n_earlyclobbers = 0; + replace_reloads = replace; + hard_regs_live_known = live_known; + static_reload_reg_p = reload_reg_p; + + /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; + neither are insns that SET cc0. Insns that use CC0 are not allowed + to have any input reloads. */ + if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN) + no_output_reloads = 1; + +#ifdef HAVE_cc0 + if (reg_referenced_p (cc0_rtx, PATTERN (insn))) + no_input_reloads = 1; + if (reg_set_p (cc0_rtx, PATTERN (insn))) + no_output_reloads = 1; +#endif + +#ifdef SECONDARY_MEMORY_NEEDED + /* The eliminated forms of any secondary memory locations are per-insn, so + clear them out here. */ + + bzero (secondary_memlocs_elim, sizeof secondary_memlocs_elim); +#endif + + /* Find what kind of insn this is. NOPERANDS gets number of operands. + Make OPERANDS point to a vector of operand values. + Make OPERAND_LOCS point to a vector of pointers to + where the operands were found. + Fill CONSTRAINTS and CONSTRAINTS1 with pointers to the + constraint-strings for this insn. + Return if the insn needs no reload processing. */ + + switch (GET_CODE (body)) + { + case USE: + case CLOBBER: + case ASM_INPUT: + case ADDR_VEC: + case ADDR_DIFF_VEC: + return; + + case SET: + /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it + is cheap to move between them. If it is not, there may not be an insn + to do the copy, so we may need a reload. */ + if (GET_CODE (SET_DEST (body)) == REG + && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER + && GET_CODE (SET_SRC (body)) == REG + && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER + && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))), + REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2) + return; + case PARALLEL: + case ASM_OPERANDS: + reload_n_operands = noperands = asm_noperands (body); + if (noperands >= 0) + { + /* This insn is an `asm' with operands. */ + + insn_code_number = -1; + this_insn_is_asm = 1; + + /* expand_asm_operands makes sure there aren't too many operands. */ + if (noperands > MAX_RECOG_OPERANDS) + abort (); + + /* Now get the operand values and constraints out of the insn. */ + + decode_asm_operands (body, recog_operand, recog_operand_loc, + constraints, operand_mode); + if (noperands > 0) + { + bcopy (constraints, constraints1, noperands * sizeof (char *)); + n_alternatives = n_occurrences (',', constraints[0]) + 1; + for (i = 1; i < noperands; i++) + if (n_alternatives != n_occurrences (',', constraints[i]) + 1) + { + error_for_asm (insn, "operand constraints differ in number of alternatives"); + /* Avoid further trouble with this insn. */ + PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); + n_reloads = 0; + return; + } + } + break; + } + + default: + /* Ordinary insn: recognize it, get the operands via insn_extract + and get the constraints. */ + + insn_code_number = recog_memoized (insn); + if (insn_code_number < 0) + fatal_insn_not_found (insn); + + reload_n_operands = noperands = insn_n_operands[insn_code_number]; + n_alternatives = insn_n_alternatives[insn_code_number]; + /* Just return "no reloads" if insn has no operands with constraints. */ + if (n_alternatives == 0) + return; + insn_extract (insn); + for (i = 0; i < noperands; i++) + { + constraints[i] = constraints1[i] + = insn_operand_constraint[insn_code_number][i]; + operand_mode[i] = insn_operand_mode[insn_code_number][i]; + } + } + + if (noperands == 0) + return; + + commutative = -1; + + /* If we will need to know, later, whether some pair of operands + are the same, we must compare them now and save the result. + Reloading the base and index registers will clobber them + and afterward they will fail to match. */ + + for (i = 0; i < noperands; i++) + { + register char *p; + register int c; + + substed_operand[i] = recog_operand[i]; + p = constraints[i]; + + modified[i] = RELOAD_READ; + + /* Scan this operand's constraint to see if it is an output operand, + an in-out operand, is commutative, or should match another. */ + + while (c = *p++) + { + if (c == '=') + modified[i] = RELOAD_WRITE; + else if (c == '+') + modified[i] = RELOAD_READ_WRITE; + else if (c == '%') + { + /* The last operand should not be marked commutative. */ + if (i == noperands - 1) + { + if (this_insn_is_asm) + warning_for_asm (this_insn, + "`%%' constraint used with last operand"); + else + abort (); + } + else + commutative = i; + } + else if (c >= '0' && c <= '9') + { + c -= '0'; + operands_match[c][i] + = operands_match_p (recog_operand[c], recog_operand[i]); + + /* An operand may not match itself. */ + if (c == i) + { + if (this_insn_is_asm) + warning_for_asm (this_insn, + "operand %d has constraint %d", i, c); + else + abort (); + } + + /* If C can be commuted with C+1, and C might need to match I, + then C+1 might also need to match I. */ + if (commutative >= 0) + { + if (c == commutative || c == commutative + 1) + { + int other = c + (c == commutative ? 1 : -1); + operands_match[other][i] + = operands_match_p (recog_operand[other], recog_operand[i]); + } + if (i == commutative || i == commutative + 1) + { + int other = i + (i == commutative ? 1 : -1); + operands_match[c][other] + = operands_match_p (recog_operand[c], recog_operand[other]); + } + /* Note that C is supposed to be less than I. + No need to consider altering both C and I because in + that case we would alter one into the other. */ + } + } + } + } + + /* Examine each operand that is a memory reference or memory address + and reload parts of the addresses into index registers. + Also here any references to pseudo regs that didn't get hard regs + but are equivalent to constants get replaced in the insn itself + with those constants. Nobody will ever see them again. + + Finally, set up the preferred classes of each operand. */ + + for (i = 0; i < noperands; i++) + { + register RTX_CODE code = GET_CODE (recog_operand[i]); + + address_reloaded[i] = 0; + operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT + : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT + : RELOAD_OTHER); + address_type[i] + = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS + : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS + : RELOAD_OTHER); + + if (constraints[i][0] == 'p') + { + find_reloads_address (VOIDmode, NULL_PTR, + recog_operand[i], recog_operand_loc[i], + i, operand_type[i], ind_levels); + substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; + } + else if (code == MEM) + { + if (find_reloads_address (GET_MODE (recog_operand[i]), + recog_operand_loc[i], + XEXP (recog_operand[i], 0), + &XEXP (recog_operand[i], 0), + i, address_type[i], ind_levels)) + address_reloaded[i] = 1; + substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; + } + else if (code == SUBREG) + substed_operand[i] = recog_operand[i] = *recog_operand_loc[i] + = find_reloads_toplev (recog_operand[i], i, address_type[i], + ind_levels, + set != 0 + && &SET_DEST (set) == recog_operand_loc[i]); + else if (code == REG) + { + /* This is equivalent to calling find_reloads_toplev. + The code is duplicated for speed. + When we find a pseudo always equivalent to a constant, + we replace it by the constant. We must be sure, however, + that we don't try to replace it in the insn in which it + is being set. */ + register int regno = REGNO (recog_operand[i]); + if (reg_equiv_constant[regno] != 0 + && (set == 0 || &SET_DEST (set) != recog_operand_loc[i])) + substed_operand[i] = recog_operand[i] + = reg_equiv_constant[regno]; +#if 0 /* This might screw code in reload1.c to delete prior output-reload + that feeds this insn. */ + if (reg_equiv_mem[regno] != 0) + substed_operand[i] = recog_operand[i] + = reg_equiv_mem[regno]; +#endif + if (reg_equiv_address[regno] != 0) + { + /* If reg_equiv_address is not a constant address, copy it, + since it may be shared. */ + rtx address = reg_equiv_address[regno]; + + if (rtx_varies_p (address)) + address = copy_rtx (address); + + /* If this is an output operand, we must output a CLOBBER + after INSN so find_equiv_reg knows REGNO is being written. + Mark this insn specially, do we can put our output reloads + after it. */ + + if (modified[i] != RELOAD_READ) + PUT_MODE (emit_insn_after (gen_rtx (CLOBBER, VOIDmode, + recog_operand[i]), + insn), + DImode); + + *recog_operand_loc[i] = recog_operand[i] + = gen_rtx (MEM, GET_MODE (recog_operand[i]), address); + RTX_UNCHANGING_P (recog_operand[i]) + = RTX_UNCHANGING_P (regno_reg_rtx[regno]); + find_reloads_address (GET_MODE (recog_operand[i]), + recog_operand_loc[i], + XEXP (recog_operand[i], 0), + &XEXP (recog_operand[i], 0), + i, address_type[i], ind_levels); + substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; + } + } + /* If the operand is still a register (we didn't replace it with an + equivalent), get the preferred class to reload it into. */ + code = GET_CODE (recog_operand[i]); + preferred_class[i] + = ((code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) + ? reg_preferred_class (REGNO (recog_operand[i])) : NO_REGS); + pref_or_nothing[i] + = (code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER + && reg_alternate_class (REGNO (recog_operand[i])) == NO_REGS); + } + + /* If this is simply a copy from operand 1 to operand 0, merge the + preferred classes for the operands. */ + if (set != 0 && noperands >= 2 && recog_operand[0] == SET_DEST (set) + && recog_operand[1] == SET_SRC (set)) + { + preferred_class[0] = preferred_class[1] + = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]]; + pref_or_nothing[0] |= pref_or_nothing[1]; + pref_or_nothing[1] |= pref_or_nothing[0]; + } + + /* Now see what we need for pseudo-regs that didn't get hard regs + or got the wrong kind of hard reg. For this, we must consider + all the operands together against the register constraints. */ + + best = MAX_RECOG_OPERANDS + 300; + + swapped = 0; + goal_alternative_swapped = 0; + try_swapped: + + /* The constraints are made of several alternatives. + Each operand's constraint looks like foo,bar,... with commas + separating the alternatives. The first alternatives for all + operands go together, the second alternatives go together, etc. + + First loop over alternatives. */ + + for (this_alternative_number = 0; + this_alternative_number < n_alternatives; + this_alternative_number++) + { + /* Loop over operands for one constraint alternative. */ + /* LOSERS counts those that don't fit this alternative + and would require loading. */ + int losers = 0; + /* BAD is set to 1 if it some operand can't fit this alternative + even after reloading. */ + int bad = 0; + /* REJECT is a count of how undesirable this alternative says it is + if any reloading is required. If the alternative matches exactly + then REJECT is ignored, but otherwise it gets this much + counted against it in addition to the reloading needed. Each + ? counts three times here since we want the disparaging caused by + a bad register class to only count 1/3 as much. */ + int reject = 0; + + this_earlyclobber = 0; + + for (i = 0; i < noperands; i++) + { + register char *p = constraints[i]; + register int win = 0; + /* 0 => this operand can be reloaded somehow for this alternative */ + int badop = 1; + /* 0 => this operand can be reloaded if the alternative allows regs. */ + int winreg = 0; + int c; + register rtx operand = recog_operand[i]; + int offset = 0; + /* Nonzero means this is a MEM that must be reloaded into a reg + regardless of what the constraint says. */ + int force_reload = 0; + int offmemok = 0; + int earlyclobber = 0; + + /* If the operand is a SUBREG, extract + the REG or MEM (or maybe even a constant) within. + (Constants can occur as a result of reg_equiv_constant.) */ + + while (GET_CODE (operand) == SUBREG) + { + offset += SUBREG_WORD (operand); + operand = SUBREG_REG (operand); + /* Force reload if this is not a register or if there may may + be a problem accessing the register in the outer mode. */ + if (GET_CODE (operand) != REG +#if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND) + /* ??? The comment below clearly does not match the code. + What the code below actually does is set force_reload + for a paradoxical subreg of a pseudo. rms and kenner + can't see the point of doing this. */ + /* Nonparadoxical subreg of a pseudoreg. + Don't to load the full width if on this machine + we expected the fetch to extend. */ + || ((GET_MODE_SIZE (operand_mode[i]) + > GET_MODE_SIZE (GET_MODE (operand))) + && REGNO (operand) >= FIRST_PSEUDO_REGISTER) +#endif + /* Subreg of a hard reg which can't handle the subreg's mode + or which would handle that mode in the wrong number of + registers for subregging to work. */ + || (REGNO (operand) < FIRST_PSEUDO_REGISTER + && (! HARD_REGNO_MODE_OK (REGNO (operand), + operand_mode[i]) + || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD + && (GET_MODE_SIZE (GET_MODE (operand)) + > UNITS_PER_WORD) + && ((GET_MODE_SIZE (GET_MODE (operand)) + / UNITS_PER_WORD) + != HARD_REGNO_NREGS (REGNO (operand), + GET_MODE (operand))))))) + force_reload = 1; + } + + this_alternative[i] = (int) NO_REGS; + this_alternative_win[i] = 0; + this_alternative_offmemok[i] = 0; + this_alternative_earlyclobber[i] = 0; + this_alternative_matches[i] = -1; + + /* An empty constraint or empty alternative + allows anything which matched the pattern. */ + if (*p == 0 || *p == ',') + win = 1, badop = 0; + + /* Scan this alternative's specs for this operand; + set WIN if the operand fits any letter in this alternative. + Otherwise, clear BADOP if this operand could + fit some letter after reloads, + or set WINREG if this operand could fit after reloads + provided the constraint allows some registers. */ + + while (*p && (c = *p++) != ',') + switch (c) + { + case '=': + case '+': + case '*': + break; + + case '%': + /* The last operand should not be marked commutative. */ + if (i != noperands - 1) + commutative = i; + break; + + case '?': + reject += 3; + break; + + case '!': + reject = 300; + break; + + case '#': + /* Ignore rest of this alternative as far as + reloading is concerned. */ + while (*p && *p != ',') p++; + break; + + case '0': + case '1': + case '2': + case '3': + case '4': + c -= '0'; + this_alternative_matches[i] = c; + /* We are supposed to match a previous operand. + If we do, we win if that one did. + If we do not, count both of the operands as losers. + (This is too conservative, since most of the time + only a single reload insn will be needed to make + the two operands win. As a result, this alternative + may be rejected when it is actually desirable.) */ + if ((swapped && (c != commutative || i != commutative + 1)) + /* If we are matching as if two operands were swapped, + also pretend that operands_match had been computed + with swapped. + But if I is the second of those and C is the first, + don't exchange them, because operands_match is valid + only on one side of its diagonal. */ + ? (operands_match + [(c == commutative || c == commutative + 1) + ? 2*commutative + 1 - c : c] + [(i == commutative || i == commutative + 1) + ? 2*commutative + 1 - i : i]) + : operands_match[c][i]) + win = this_alternative_win[c]; + else + { + /* Operands don't match. */ + rtx value; + /* Retroactively mark the operand we had to match + as a loser, if it wasn't already. */ + if (this_alternative_win[c]) + losers++; + this_alternative_win[c] = 0; + if (this_alternative[c] == (int) NO_REGS) + bad = 1; + /* But count the pair only once in the total badness of + this alternative, if the pair can be a dummy reload. */ + value + = find_dummy_reload (recog_operand[i], recog_operand[c], + recog_operand_loc[i], recog_operand_loc[c], + this_alternative[c], -1); + + if (value != 0) + losers--; + } + /* This can be fixed with reloads if the operand + we are supposed to match can be fixed with reloads. */ + badop = 0; + this_alternative[i] = this_alternative[c]; + break; + + case 'p': + /* All necessary reloads for an address_operand + were handled in find_reloads_address. */ + this_alternative[i] = (int) ALL_REGS; + win = 1; + break; + + case 'm': + if (force_reload) + break; + if (GET_CODE (operand) == MEM + || (GET_CODE (operand) == REG + && REGNO (operand) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (operand)] < 0)) + win = 1; + if (CONSTANT_P (operand)) + badop = 0; + break; + + case '<': + if (GET_CODE (operand) == MEM + && ! address_reloaded[i] + && (GET_CODE (XEXP (operand, 0)) == PRE_DEC + || GET_CODE (XEXP (operand, 0)) == POST_DEC)) + win = 1; + break; + + case '>': + if (GET_CODE (operand) == MEM + && ! address_reloaded[i] + && (GET_CODE (XEXP (operand, 0)) == PRE_INC + || GET_CODE (XEXP (operand, 0)) == POST_INC)) + win = 1; + break; + + /* Memory operand whose address is not offsettable. */ + case 'V': + if (force_reload) + break; + if (GET_CODE (operand) == MEM + && ! (ind_levels ? offsettable_memref_p (operand) + : offsettable_nonstrict_memref_p (operand)) + /* Certain mem addresses will become offsettable + after they themselves are reloaded. This is important; + we don't want our own handling of unoffsettables + to override the handling of reg_equiv_address. */ + && !(GET_CODE (XEXP (operand, 0)) == REG + && (ind_levels == 0 + || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))) + win = 1; + break; + + /* Memory operand whose address is offsettable. */ + case 'o': + if (force_reload) + break; + if ((GET_CODE (operand) == MEM + /* If IND_LEVELS, find_reloads_address won't reload a + pseudo that didn't get a hard reg, so we have to + reject that case. */ + && (ind_levels ? offsettable_memref_p (operand) + : offsettable_nonstrict_memref_p (operand))) + /* Certain mem addresses will become offsettable + after they themselves are reloaded. This is important; + we don't want our own handling of unoffsettables + to override the handling of reg_equiv_address. */ + || (GET_CODE (operand) == MEM + && GET_CODE (XEXP (operand, 0)) == REG + && (ind_levels == 0 + || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)) + || (GET_CODE (operand) == REG + && REGNO (operand) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (operand)] < 0)) + win = 1; + if (CONSTANT_P (operand) || GET_CODE (operand) == MEM) + badop = 0; + offmemok = 1; + break; + + case '&': + /* Output operand that is stored before the need for the + input operands (and their index registers) is over. */ + earlyclobber = 1, this_earlyclobber = 1; + break; + + case 'E': + /* Match any floating double constant, but only if + we can examine the bits of it reliably. */ + if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT + || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) + && GET_MODE (operand) != VOIDmode && ! flag_pretend_float) + break; + if (GET_CODE (operand) == CONST_DOUBLE) + win = 1; + break; + + case 'F': + if (GET_CODE (operand) == CONST_DOUBLE) + win = 1; + break; + + case 'G': + case 'H': + if (GET_CODE (operand) == CONST_DOUBLE + && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c)) + win = 1; + break; + + case 's': + if (GET_CODE (operand) == CONST_INT + || (GET_CODE (operand) == CONST_DOUBLE + && GET_MODE (operand) == VOIDmode)) + break; + case 'i': + if (CONSTANT_P (operand) +#ifdef LEGITIMATE_PIC_OPERAND_P + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand)) +#endif + ) + win = 1; + break; + + case 'n': + if (GET_CODE (operand) == CONST_INT + || (GET_CODE (operand) == CONST_DOUBLE + && GET_MODE (operand) == VOIDmode)) + win = 1; + break; + + case 'I': + case 'J': + case 'K': + case 'L': + case 'M': + case 'N': + case 'O': + case 'P': + if (GET_CODE (operand) == CONST_INT + && CONST_OK_FOR_LETTER_P (INTVAL (operand), c)) + win = 1; + break; + + case 'X': + win = 1; + break; + + case 'g': + if (! force_reload + /* A PLUS is never a valid operand, but reload can make + it from a register when eliminating registers. */ + && GET_CODE (operand) != PLUS + /* A SCRATCH is not a valid operand. */ + && GET_CODE (operand) != SCRATCH +#ifdef LEGITIMATE_PIC_OPERAND_P + && (! CONSTANT_P (operand) + || ! flag_pic + || LEGITIMATE_PIC_OPERAND_P (operand)) +#endif + && (GENERAL_REGS == ALL_REGS + || GET_CODE (operand) != REG + || (REGNO (operand) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (operand)] < 0))) + win = 1; + /* Drop through into 'r' case */ + + case 'r': + this_alternative[i] + = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; + goto reg; + +#ifdef EXTRA_CONSTRAINT + case 'Q': + case 'R': + case 'S': + case 'T': + case 'U': + if (EXTRA_CONSTRAINT (operand, c)) + win = 1; + break; +#endif + + default: + this_alternative[i] + = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)]; + + reg: + if (GET_MODE (operand) == BLKmode) + break; + winreg = 1; + if (GET_CODE (operand) == REG + && reg_fits_class_p (operand, this_alternative[i], + offset, GET_MODE (recog_operand[i]))) + win = 1; + break; + } + + constraints[i] = p; + + /* If this operand could be handled with a reg, + and some reg is allowed, then this operand can be handled. */ + if (winreg && this_alternative[i] != (int) NO_REGS) + badop = 0; + + /* Record which operands fit this alternative. */ + this_alternative_earlyclobber[i] = earlyclobber; + if (win && ! force_reload) + this_alternative_win[i] = 1; + else + { + this_alternative_offmemok[i] = offmemok; + losers++; + if (badop) + bad = 1; + /* Alternative loses if it has no regs for a reg operand. */ + if (GET_CODE (operand) == REG + && this_alternative[i] == (int) NO_REGS + && this_alternative_matches[i] < 0) + bad = 1; + + /* Alternative loses if it requires a type of reload not + permitted for this insn. We can always reload SCRATCH + and objects with a REG_UNUSED note. */ + if (GET_CODE (operand) != SCRATCH + && modified[i] != RELOAD_READ && no_output_reloads + && ! find_reg_note (insn, REG_UNUSED, operand)) + bad = 1; + else if (modified[i] != RELOAD_WRITE && no_input_reloads) + bad = 1; + + /* We prefer to reload pseudos over reloading other things, + since such reloads may be able to be eliminated later. + If we are reloading a SCRATCH, we won't be generating any + insns, just using a register, so it is also preferred. + So bump REJECT in other cases. */ + if (GET_CODE (operand) != REG && GET_CODE (operand) != SCRATCH) + reject++; + } + + /* If this operand is a pseudo register that didn't get a hard + reg and this alternative accepts some register, see if the + class that we want is a subset of the preferred class for this + register. If not, but it intersects that class, use the + preferred class instead. If it does not intersect the preferred + class, show that usage of this alternative should be discouraged; + it will be discouraged more still if the register is `preferred + or nothing'. We do this because it increases the chance of + reusing our spill register in a later insn and avoiding a pair + of memory stores and loads. + + Don't bother with this if this alternative will accept this + operand. + + Don't do this for a multiword operand, if + we have to worry about small classes, because making reg groups + harder to allocate is asking for trouble. + + Don't do this if the preferred class has only one register + because we might otherwise exhaust the class. */ + + + if (! win && this_alternative[i] != (int) NO_REGS +#ifdef SMALL_REGISTER_CLASSES + && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD +#endif + && reg_class_size[(int) preferred_class[i]] > 1) + { + if (! reg_class_subset_p (this_alternative[i], + preferred_class[i])) + { + /* Since we don't have a way of forming the intersection, + we just do something special if the preferred class + is a subset of the class we have; that's the most + common case anyway. */ + if (reg_class_subset_p (preferred_class[i], + this_alternative[i])) + this_alternative[i] = (int) preferred_class[i]; + else + reject += (1 + pref_or_nothing[i]); + } + } + } + + /* Now see if any output operands that are marked "earlyclobber" + in this alternative conflict with any input operands + or any memory addresses. */ + + for (i = 0; i < noperands; i++) + if (this_alternative_earlyclobber[i] + && this_alternative_win[i]) + { + struct decomposition early_data; + + early_data = decompose (recog_operand[i]); + + if (modified[i] == RELOAD_READ) + { + if (this_insn_is_asm) + warning_for_asm (this_insn, + "`&' constraint used with input operand"); + else + abort (); + continue; + } + + if (this_alternative[i] == NO_REGS) + { + this_alternative_earlyclobber[i] = 0; + if (this_insn_is_asm) + error_for_asm (this_insn, + "`&' constraint used with no register class"); + else + abort (); + } + + for (j = 0; j < noperands; j++) + /* Is this an input operand or a memory ref? */ + if ((GET_CODE (recog_operand[j]) == MEM + || modified[j] != RELOAD_WRITE) + && j != i + /* Ignore things like match_operator operands. */ + && *constraints1[j] != 0 + /* Don't count an input operand that is constrained to match + the early clobber operand. */ + && ! (this_alternative_matches[j] == i + && rtx_equal_p (recog_operand[i], recog_operand[j])) + /* Is it altered by storing the earlyclobber operand? */ + && !immune_p (recog_operand[j], recog_operand[i], early_data)) + { + /* If the output is in a single-reg class, + it's costly to reload it, so reload the input instead. */ + if (reg_class_size[this_alternative[i]] == 1 + && (GET_CODE (recog_operand[j]) == REG + || GET_CODE (recog_operand[j]) == SUBREG)) + { + losers++; + this_alternative_win[j] = 0; + } + else + break; + } + /* If an earlyclobber operand conflicts with something, + it must be reloaded, so request this and count the cost. */ + if (j != noperands) + { + losers++; + this_alternative_win[i] = 0; + for (j = 0; j < noperands; j++) + if (this_alternative_matches[j] == i + && this_alternative_win[j]) + { + this_alternative_win[j] = 0; + losers++; + } + } + } + + /* If one alternative accepts all the operands, no reload required, + choose that alternative; don't consider the remaining ones. */ + if (losers == 0) + { + /* Unswap these so that they are never swapped at `finish'. */ + if (commutative >= 0) + { + recog_operand[commutative] = substed_operand[commutative]; + recog_operand[commutative + 1] + = substed_operand[commutative + 1]; + } + for (i = 0; i < noperands; i++) + { + goal_alternative_win[i] = 1; + goal_alternative[i] = this_alternative[i]; + goal_alternative_offmemok[i] = this_alternative_offmemok[i]; + goal_alternative_matches[i] = this_alternative_matches[i]; + goal_alternative_earlyclobber[i] + = this_alternative_earlyclobber[i]; + } + goal_alternative_number = this_alternative_number; + goal_alternative_swapped = swapped; + goal_earlyclobber = this_earlyclobber; + goto finish; + } + + /* REJECT, set by the ! and ? constraint characters and when a register + would be reloaded into a non-preferred class, discourages the use of + this alternative for a reload goal. REJECT is incremented by three + for each ? and one for each non-preferred class. */ + losers = losers * 3 + reject; + + /* If this alternative can be made to work by reloading, + and it needs less reloading than the others checked so far, + record it as the chosen goal for reloading. */ + if (! bad && best > losers) + { + for (i = 0; i < noperands; i++) + { + goal_alternative[i] = this_alternative[i]; + goal_alternative_win[i] = this_alternative_win[i]; + goal_alternative_offmemok[i] = this_alternative_offmemok[i]; + goal_alternative_matches[i] = this_alternative_matches[i]; + goal_alternative_earlyclobber[i] + = this_alternative_earlyclobber[i]; + } + goal_alternative_swapped = swapped; + best = losers; + goal_alternative_number = this_alternative_number; + goal_earlyclobber = this_earlyclobber; + } + } + + /* If insn is commutative (it's safe to exchange a certain pair of operands) + then we need to try each alternative twice, + the second time matching those two operands + as if we had exchanged them. + To do this, really exchange them in operands. + + If we have just tried the alternatives the second time, + return operands to normal and drop through. */ + + if (commutative >= 0) + { + swapped = !swapped; + if (swapped) + { + register enum reg_class tclass; + register int t; + + recog_operand[commutative] = substed_operand[commutative + 1]; + recog_operand[commutative + 1] = substed_operand[commutative]; + + tclass = preferred_class[commutative]; + preferred_class[commutative] = preferred_class[commutative + 1]; + preferred_class[commutative + 1] = tclass; + + t = pref_or_nothing[commutative]; + pref_or_nothing[commutative] = pref_or_nothing[commutative + 1]; + pref_or_nothing[commutative + 1] = t; + + bcopy (constraints1, constraints, noperands * sizeof (char *)); + goto try_swapped; + } + else + { + recog_operand[commutative] = substed_operand[commutative]; + recog_operand[commutative + 1] = substed_operand[commutative + 1]; + } + } + + /* The operands don't meet the constraints. + goal_alternative describes the alternative + that we could reach by reloading the fewest operands. + Reload so as to fit it. */ + + if (best == MAX_RECOG_OPERANDS + 300) + { + /* No alternative works with reloads?? */ + if (insn_code_number >= 0) + abort (); + error_for_asm (insn, "inconsistent operand constraints in an `asm'"); + /* Avoid further trouble with this insn. */ + PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); + n_reloads = 0; + return; + } + + /* Jump to `finish' from above if all operands are valid already. + In that case, goal_alternative_win is all 1. */ + finish: + + /* Right now, for any pair of operands I and J that are required to match, + with I < J, + goal_alternative_matches[J] is I. + Set up goal_alternative_matched as the inverse function: + goal_alternative_matched[I] = J. */ + + for (i = 0; i < noperands; i++) + goal_alternative_matched[i] = -1; + + for (i = 0; i < noperands; i++) + if (! goal_alternative_win[i] + && goal_alternative_matches[i] >= 0) + goal_alternative_matched[goal_alternative_matches[i]] = i; + + /* If the best alternative is with operands 1 and 2 swapped, + consider them swapped before reporting the reloads. Update the + operand numbers of any reloads already pushed. */ + + if (goal_alternative_swapped) + { + register rtx tem; + + tem = substed_operand[commutative]; + substed_operand[commutative] = substed_operand[commutative + 1]; + substed_operand[commutative + 1] = tem; + tem = recog_operand[commutative]; + recog_operand[commutative] = recog_operand[commutative + 1]; + recog_operand[commutative + 1] = tem; + + for (i = 0; i < n_reloads; i++) + { + if (reload_opnum[i] == commutative) + reload_opnum[i] = commutative + 1; + else if (reload_opnum[i] == commutative + 1) + reload_opnum[i] = commutative; + } + } + + /* Perform whatever substitutions on the operands we are supposed + to make due to commutativity or replacement of registers + with equivalent constants or memory slots. */ + + for (i = 0; i < noperands; i++) + { + *recog_operand_loc[i] = substed_operand[i]; + /* While we are looping on operands, initialize this. */ + operand_reloadnum[i] = -1; + + /* If this is an earlyclobber operand, we need to widen the scope. + The reload must remain valid from the start of the insn being + reloaded until after the operand is stored into its destination. + We approximate this with RELOAD_OTHER even though we know that we + do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads. + + One special case that is worth checking is when we have an + output that is earlyclobber but isn't used past the insn (typically + a SCRATCH). In this case, we only need have the reload live + through the insn itself, but not for any of our input or output + reloads. + + In any case, anything needed to address this operand can remain + however they were previously categorized. */ + + if (goal_alternative_earlyclobber[i]) + operand_type[i] + = (find_reg_note (insn, REG_UNUSED, recog_operand[i]) + ? RELOAD_FOR_INSN : RELOAD_OTHER); + } + + /* Any constants that aren't allowed and can't be reloaded + into registers are here changed into memory references. */ + for (i = 0; i < noperands; i++) + if (! goal_alternative_win[i] + && CONSTANT_P (recog_operand[i]) + && (PREFERRED_RELOAD_CLASS (recog_operand[i], + (enum reg_class) goal_alternative[i]) + == NO_REGS) + && operand_mode[i] != VOIDmode) + { + *recog_operand_loc[i] = recog_operand[i] + = find_reloads_toplev (force_const_mem (operand_mode[i], + recog_operand[i]), + i, address_type[i], ind_levels, 0); + if (alternative_allows_memconst (constraints1[i], + goal_alternative_number)) + goal_alternative_win[i] = 1; + } + + /* Now record reloads for all the operands that need them. */ + for (i = 0; i < noperands; i++) + if (! goal_alternative_win[i]) + { + /* Operands that match previous ones have already been handled. */ + if (goal_alternative_matches[i] >= 0) + ; + /* Handle an operand with a nonoffsettable address + appearing where an offsettable address will do + by reloading the address into a base register. */ + else if (goal_alternative_matched[i] == -1 + && goal_alternative_offmemok[i] + && GET_CODE (recog_operand[i]) == MEM) + { + operand_reloadnum[i] + = push_reload (XEXP (recog_operand[i], 0), NULL_RTX, + &XEXP (recog_operand[i], 0), NULL_PTR, + BASE_REG_CLASS, GET_MODE (XEXP (recog_operand[i], 0)), + VOIDmode, 0, 0, i, RELOAD_FOR_INPUT); + reload_inc[operand_reloadnum[i]] + = GET_MODE_SIZE (GET_MODE (recog_operand[i])); + + /* If this operand is an output, we will have made any + reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but + now we are treating part of the operand as an input, so + we must change these to RELOAD_FOR_INPUT_ADDRESS. */ + + if (operand_type[i] == RELOAD_FOR_OUTPUT) + for (j = 0; j < n_reloads; j++) + if (reload_opnum[j] == i + && reload_when_needed[j] == RELOAD_FOR_OUTPUT_ADDRESS) + reload_when_needed[j] = RELOAD_FOR_INPUT_ADDRESS; + } + else if (goal_alternative_matched[i] == -1) + operand_reloadnum[i] = + push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, + modified[i] != RELOAD_READ ? recog_operand[i] : 0, + (modified[i] != RELOAD_WRITE ? + recog_operand_loc[i] : 0), + modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0, + (enum reg_class) goal_alternative[i], + (modified[i] == RELOAD_WRITE + ? VOIDmode : operand_mode[i]), + (modified[i] == RELOAD_READ + ? VOIDmode : operand_mode[i]), + (insn_code_number < 0 ? 0 + : insn_operand_strict_low[insn_code_number][i]), + 0, i, operand_type[i]); + /* In a matching pair of operands, one must be input only + and the other must be output only. + Pass the input operand as IN and the other as OUT. */ + else if (modified[i] == RELOAD_READ + && modified[goal_alternative_matched[i]] == RELOAD_WRITE) + { + operand_reloadnum[i] + = push_reload (recog_operand[i], + recog_operand[goal_alternative_matched[i]], + recog_operand_loc[i], + recog_operand_loc[goal_alternative_matched[i]], + (enum reg_class) goal_alternative[i], + operand_mode[i], + operand_mode[goal_alternative_matched[i]], + 0, 0, i, RELOAD_OTHER); + operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum; + } + else if (modified[i] == RELOAD_WRITE + && modified[goal_alternative_matched[i]] == RELOAD_READ) + { + operand_reloadnum[goal_alternative_matched[i]] + = push_reload (recog_operand[goal_alternative_matched[i]], + recog_operand[i], + recog_operand_loc[goal_alternative_matched[i]], + recog_operand_loc[i], + (enum reg_class) goal_alternative[i], + operand_mode[goal_alternative_matched[i]], + operand_mode[i], + 0, 0, i, RELOAD_OTHER); + operand_reloadnum[i] = output_reloadnum; + } + else if (insn_code_number >= 0) + abort (); + else + { + error_for_asm (insn, "inconsistent operand constraints in an `asm'"); + /* Avoid further trouble with this insn. */ + PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); + n_reloads = 0; + return; + } + } + else if (goal_alternative_matched[i] < 0 + && goal_alternative_matches[i] < 0 + && optimize) + { + /* For each non-matching operand that's a MEM or a pseudo-register + that didn't get a hard register, make an optional reload. + This may get done even if the insn needs no reloads otherwise. */ + + rtx operand = recog_operand[i]; + + while (GET_CODE (operand) == SUBREG) + operand = XEXP (operand, 0); + if ((GET_CODE (operand) == MEM + || (GET_CODE (operand) == REG + && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) + && (enum reg_class) goal_alternative[i] != NO_REGS + && ! no_input_reloads + /* Optional output reloads don't do anything and we mustn't + make in-out reloads on insns that are not permitted output + reloads. */ + && (modified[i] == RELOAD_READ + || (modified[i] == RELOAD_READ_WRITE && ! no_output_reloads))) + operand_reloadnum[i] + = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, + modified[i] != RELOAD_READ ? recog_operand[i] : 0, + (modified[i] != RELOAD_WRITE + ? recog_operand_loc[i] : 0), + (modified[i] != RELOAD_READ + ? recog_operand_loc[i] : 0), + (enum reg_class) goal_alternative[i], + (modified[i] == RELOAD_WRITE + ? VOIDmode : operand_mode[i]), + (modified[i] == RELOAD_READ + ? VOIDmode : operand_mode[i]), + (insn_code_number < 0 ? 0 + : insn_operand_strict_low[insn_code_number][i]), + 1, i, operand_type[i]); + } + else if (goal_alternative_matches[i] >= 0 + && goal_alternative_win[goal_alternative_matches[i]] + && modified[i] == RELOAD_READ + && modified[goal_alternative_matches[i]] == RELOAD_WRITE + && ! no_input_reloads && ! no_output_reloads + && optimize) + { + /* Similarly, make an optional reload for a pair of matching + objects that are in MEM or a pseudo that didn't get a hard reg. */ + + rtx operand = recog_operand[i]; + + while (GET_CODE (operand) == SUBREG) + operand = XEXP (operand, 0); + if ((GET_CODE (operand) == MEM + || (GET_CODE (operand) == REG + && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) + && ((enum reg_class) goal_alternative[goal_alternative_matches[i]] + != NO_REGS)) + operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]] + = push_reload (recog_operand[goal_alternative_matches[i]], + recog_operand[i], + recog_operand_loc[goal_alternative_matches[i]], + recog_operand_loc[i], + (enum reg_class) goal_alternative[goal_alternative_matches[i]], + operand_mode[goal_alternative_matches[i]], + operand_mode[i], + 0, 1, goal_alternative_matches[i], RELOAD_OTHER); + } + + /* Record the values of the earlyclobber operands for the caller. */ + if (goal_earlyclobber) + for (i = 0; i < noperands; i++) + if (goal_alternative_earlyclobber[i]) + reload_earlyclobbers[n_earlyclobbers++] = recog_operand[i]; + + /* If this insn pattern contains any MATCH_DUP's, make sure that + they will be substituted if the operands they match are substituted. + Also do now any substitutions we already did on the operands. + + Don't do this if we aren't making replacements because we might be + propagating things allocated by frame pointer elimination into places + it doesn't expect. */ + + if (insn_code_number >= 0 && replace) + for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) + { + int opno = recog_dup_num[i]; + *recog_dup_loc[i] = *recog_operand_loc[opno]; + if (operand_reloadnum[opno] >= 0) + push_replacement (recog_dup_loc[i], operand_reloadnum[opno], + insn_operand_mode[insn_code_number][opno]); + } + +#if 0 + /* This loses because reloading of prior insns can invalidate the equivalence + (or at least find_equiv_reg isn't smart enough to find it any more), + causing this insn to need more reload regs than it needed before. + It may be too late to make the reload regs available. + Now this optimization is done safely in choose_reload_regs. */ + + /* For each reload of a reg into some other class of reg, + search for an existing equivalent reg (same value now) in the right class. + We can use it as long as we don't need to change its contents. */ + for (i = 0; i < n_reloads; i++) + if (reload_reg_rtx[i] == 0 + && reload_in[i] != 0 + && GET_CODE (reload_in[i]) == REG + && reload_out[i] == 0) + { + reload_reg_rtx[i] + = find_equiv_reg (reload_in[i], insn, reload_reg_class[i], -1, + static_reload_reg_p, 0, reload_inmode[i]); + /* Prevent generation of insn to load the value + because the one we found already has the value. */ + if (reload_reg_rtx[i]) + reload_in[i] = reload_reg_rtx[i]; + } +#endif + + /* Perhaps an output reload can be combined with another + to reduce needs by one. */ + if (!goal_earlyclobber) + combine_reloads (); + + /* If we have a pair of reloads for parts of an address, they are reloading + the same object, the operands themselves were not reloaded, and they + are for two operands that are supposed to match, merge the reloads and + change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */ + + for (i = 0; i < n_reloads; i++) + { + int k; + + for (j = i + 1; j < n_reloads; j++) + if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS + || reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS) + && (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS + || reload_when_needed[j] == RELOAD_FOR_OUTPUT_ADDRESS) + && rtx_equal_p (reload_in[i], reload_in[j]) + && (operand_reloadnum[reload_opnum[i]] < 0 + || reload_optional[operand_reloadnum[reload_opnum[i]]]) + && (operand_reloadnum[reload_opnum[j]] < 0 + || reload_optional[operand_reloadnum[reload_opnum[j]]]) + && (goal_alternative_matches[reload_opnum[i]] == reload_opnum[j] + || (goal_alternative_matches[reload_opnum[j]] + == reload_opnum[i]))) + { + for (k = 0; k < n_replacements; k++) + if (replacements[k].what == j) + replacements[k].what = i; + + reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; + reload_in[j] = 0; + } + } + + /* Scan all the reloads and update their type. + If a reload is for the address of an operand and we didn't reload + that operand, change the type. Similarly, change the operand number + of a reload when two operands match. If a reload is optional, treat it + as though the operand isn't reloaded. + + ??? This latter case is somewhat odd because if we do the optional + reload, it means the object is hanging around. Thus we need only + do the address reload if the optional reload was NOT done. + + Change secondary reloads to be the address type of their operand, not + the normal type. + + If an operand's reload is now RELOAD_OTHER, change any + RELOAD_FOR_INPUT_ADDRESS reloads of that operand to + RELOAD_FOR_OTHER_ADDRESS. */ + + for (i = 0; i < n_reloads; i++) + { + if (reload_secondary_p[i] + && reload_when_needed[i] == operand_type[reload_opnum[i]]) + reload_when_needed[i] = address_type[reload_opnum[i]]; + + if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS + || reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS) + && (operand_reloadnum[reload_opnum[i]] < 0 + || reload_optional[operand_reloadnum[reload_opnum[i]]])) + reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; + + if (reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS + && operand_reloadnum[reload_opnum[i]] >= 0 + && (reload_when_needed[operand_reloadnum[reload_opnum[i]]] + == RELOAD_OTHER)) + reload_when_needed[i] = RELOAD_FOR_OTHER_ADDRESS; + + if (goal_alternative_matches[reload_opnum[i]] >= 0) + reload_opnum[i] = goal_alternative_matches[reload_opnum[i]]; + } + + /* See if we have any reloads that are now allowed to be merged + because we've changed when the reload is needed to + RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only + check for the most common cases. */ + + for (i = 0; i < n_reloads; i++) + if (reload_in[i] != 0 && reload_out[i] == 0 + && (reload_when_needed[i] == RELOAD_FOR_OPERAND_ADDRESS + || reload_when_needed[i] == RELOAD_FOR_OTHER_ADDRESS)) + for (j = 0; j < n_reloads; j++) + if (i != j && reload_in[j] != 0 && reload_out[j] == 0 + && reload_when_needed[j] == reload_when_needed[i] + && MATCHES (reload_in[i], reload_in[j])) + { + reload_opnum[i] = MIN (reload_opnum[i], reload_opnum[j]); + transfer_replacements (i, j); + reload_in[j] = 0; + } + +#else /* no REGISTER_CONSTRAINTS */ + int noperands; + int insn_code_number; + int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */ + register int i; + rtx body = PATTERN (insn); + + n_reloads = 0; + n_replacements = 0; + n_earlyclobbers = 0; + replace_reloads = replace; + this_insn = insn; + + /* Find what kind of insn this is. NOPERANDS gets number of operands. + Store the operand values in RECOG_OPERAND and the locations + of the words in the insn that point to them in RECOG_OPERAND_LOC. + Return if the insn needs no reload processing. */ + + switch (GET_CODE (body)) + { + case USE: + case CLOBBER: + case ASM_INPUT: + case ADDR_VEC: + case ADDR_DIFF_VEC: + return; + + case PARALLEL: + case SET: + noperands = asm_noperands (body); + if (noperands >= 0) + { + /* This insn is an `asm' with operands. + First, find out how many operands, and allocate space. */ + + insn_code_number = -1; + /* ??? This is a bug! ??? + Give up and delete this insn if it has too many operands. */ + if (noperands > MAX_RECOG_OPERANDS) + abort (); + + /* Now get the operand values out of the insn. */ + + decode_asm_operands (body, recog_operand, recog_operand_loc, + NULL_PTR, NULL_PTR); + break; + } + + default: + /* Ordinary insn: recognize it, allocate space for operands and + constraints, and get them out via insn_extract. */ + + insn_code_number = recog_memoized (insn); + noperands = insn_n_operands[insn_code_number]; + insn_extract (insn); + } + + if (noperands == 0) + return; + + for (i = 0; i < noperands; i++) + { + register RTX_CODE code = GET_CODE (recog_operand[i]); + int is_set_dest = GET_CODE (body) == SET && (i == 0); + + if (insn_code_number >= 0) + if (insn_operand_address_p[insn_code_number][i]) + find_reloads_address (VOIDmode, NULL_PTR, + recog_operand[i], recog_operand_loc[i], + i, RELOAD_FOR_INPUT, ind_levels); + + /* In these cases, we can't tell if the operand is an input + or an output, so be conservative. In practice it won't be + problem. */ + + if (code == MEM) + find_reloads_address (GET_MODE (recog_operand[i]), + recog_operand_loc[i], + XEXP (recog_operand[i], 0), + &XEXP (recog_operand[i], 0), + i, RELOAD_OTHER, ind_levels); + if (code == SUBREG) + recog_operand[i] = *recog_operand_loc[i] + = find_reloads_toplev (recog_operand[i], i, RELOAD_OTHER, + ind_levels, is_set_dest); + if (code == REG) + { + register int regno = REGNO (recog_operand[i]); + if (reg_equiv_constant[regno] != 0 && !is_set_dest) + recog_operand[i] = *recog_operand_loc[i] + = reg_equiv_constant[regno]; +#if 0 /* This might screw code in reload1.c to delete prior output-reload + that feeds this insn. */ + if (reg_equiv_mem[regno] != 0) + recog_operand[i] = *recog_operand_loc[i] + = reg_equiv_mem[regno]; +#endif + } + } + + /* Perhaps an output reload can be combined with another + to reduce needs by one. */ + if (!goal_earlyclobber) + combine_reloads (); +#endif /* no REGISTER_CONSTRAINTS */ +} + +/* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT + accepts a memory operand with constant address. */ + +static int +alternative_allows_memconst (constraint, altnum) + char *constraint; + int altnum; +{ + register int c; + /* Skip alternatives before the one requested. */ + while (altnum > 0) + { + while (*constraint++ != ','); + altnum--; + } + /* Scan the requested alternative for 'm' or 'o'. + If one of them is present, this alternative accepts memory constants. */ + while ((c = *constraint++) && c != ',' && c != '#') + if (c == 'm' || c == 'o') + return 1; + return 0; +} + +/* Scan X for memory references and scan the addresses for reloading. + Also checks for references to "constant" regs that we want to eliminate + and replaces them with the values they stand for. + We may alter X destructively if it contains a reference to such. + If X is just a constant reg, we return the equivalent value + instead of X. + + IND_LEVELS says how many levels of indirect addressing this machine + supports. + + OPNUM and TYPE identify the purpose of the reload. + + IS_SET_DEST is true if X is the destination of a SET, which is not + appropriate to be replaced by a constant. */ + +static rtx +find_reloads_toplev (x, opnum, type, ind_levels, is_set_dest) + rtx x; + int opnum; + enum reload_type type; + int ind_levels; + int is_set_dest; +{ + register RTX_CODE code = GET_CODE (x); + + register char *fmt = GET_RTX_FORMAT (code); + register int i; + + if (code == REG) + { + /* This code is duplicated for speed in find_reloads. */ + register int regno = REGNO (x); + if (reg_equiv_constant[regno] != 0 && !is_set_dest) + x = reg_equiv_constant[regno]; +#if 0 +/* This creates (subreg (mem...)) which would cause an unnecessary + reload of the mem. */ + else if (reg_equiv_mem[regno] != 0) + x = reg_equiv_mem[regno]; +#endif + else if (reg_equiv_address[regno] != 0) + { + /* If reg_equiv_address varies, it may be shared, so copy it. */ + rtx addr = reg_equiv_address[regno]; + + if (rtx_varies_p (addr)) + addr = copy_rtx (addr); + + x = gen_rtx (MEM, GET_MODE (x), addr); + RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); + find_reloads_address (GET_MODE (x), NULL_PTR, + XEXP (x, 0), + &XEXP (x, 0), opnum, type, ind_levels); + } + return x; + } + if (code == MEM) + { + rtx tem = x; + find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0), + opnum, type, ind_levels); + return tem; + } + + if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG) + { + /* Check for SUBREG containing a REG that's equivalent to a constant. + If the constant has a known value, truncate it right now. + Similarly if we are extracting a single-word of a multi-word + constant. If the constant is symbolic, allow it to be substituted + normally. push_reload will strip the subreg later. If the + constant is VOIDmode, abort because we will lose the mode of + the register (this should never happen because one of the cases + above should handle it). */ + + register int regno = REGNO (SUBREG_REG (x)); + rtx tem; + + if (subreg_lowpart_p (x) + && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 + && reg_equiv_constant[regno] != 0 + && (tem = gen_lowpart_common (GET_MODE (x), + reg_equiv_constant[regno])) != 0) + return tem; + + if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD + && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 + && reg_equiv_constant[regno] != 0 + && (tem = operand_subword (reg_equiv_constant[regno], + SUBREG_WORD (x), 0, + GET_MODE (SUBREG_REG (x)))) != 0) + return tem; + + if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 + && reg_equiv_constant[regno] != 0 + && GET_MODE (reg_equiv_constant[regno]) == VOIDmode) + abort (); + + /* If the subreg contains a reg that will be converted to a mem, + convert the subreg to a narrower memref now. + Otherwise, we would get (subreg (mem ...) ...), + which would force reload of the mem. + + We also need to do this if there is an equivalent MEM that is + not offsettable. In that case, alter_subreg would produce an + invalid address on big-endian machines. + + For machines that extend byte loads, we must not reload using + a wider mode if we have a paradoxical SUBREG. find_reloads will + force a reload in that case. So we should not do anything here. */ + + else if (regno >= FIRST_PSEUDO_REGISTER +#if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND) + && (GET_MODE_SIZE (GET_MODE (x)) + <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) +#endif + && (reg_equiv_address[regno] != 0 + || (reg_equiv_mem[regno] != 0 + && (! strict_memory_address_p (GET_MODE (x), + XEXP (reg_equiv_mem[regno], 0)) + || ! offsettable_memref_p (reg_equiv_mem[regno]))))) + { + int offset = SUBREG_WORD (x) * UNITS_PER_WORD; + rtx addr = (reg_equiv_address[regno] ? reg_equiv_address[regno] + : XEXP (reg_equiv_mem[regno], 0)); +#if BYTES_BIG_ENDIAN + int size; + size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))); + offset += MIN (size, UNITS_PER_WORD); + size = GET_MODE_SIZE (GET_MODE (x)); + offset -= MIN (size, UNITS_PER_WORD); +#endif + addr = plus_constant (addr, offset); + x = gen_rtx (MEM, GET_MODE (x), addr); + RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); + find_reloads_address (GET_MODE (x), NULL_PTR, + XEXP (x, 0), + &XEXP (x, 0), opnum, type, ind_levels); + } + + } + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + XEXP (x, i) = find_reloads_toplev (XEXP (x, i), opnum, type, + ind_levels, is_set_dest); + } + return x; +} + +/* Return a mem ref for the memory equivalent of reg REGNO. + This mem ref is not shared with anything. */ + +static rtx +make_memloc (ad, regno) + rtx ad; + int regno; +{ + register int i; + rtx tem = reg_equiv_address[regno]; + +#if 0 /* We cannot safely reuse a memloc made here; + if the pseudo appears twice, and its mem needs a reload, + it gets two separate reloads assigned, but it only + gets substituted with the second of them; + then it can get used before that reload reg gets loaded up. */ + for (i = 0; i < n_memlocs; i++) + if (rtx_equal_p (tem, XEXP (memlocs[i], 0))) + return memlocs[i]; +#endif + + /* If TEM might contain a pseudo, we must copy it to avoid + modifying it when we do the substitution for the reload. */ + if (rtx_varies_p (tem)) + tem = copy_rtx (tem); + + tem = gen_rtx (MEM, GET_MODE (ad), tem); + RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); + memlocs[n_memlocs++] = tem; + return tem; +} + +/* Record all reloads needed for handling memory address AD + which appears in *LOC in a memory reference to mode MODE + which itself is found in location *MEMREFLOC. + Note that we take shortcuts assuming that no multi-reg machine mode + occurs as part of an address. + + OPNUM and TYPE specify the purpose of this reload. + + IND_LEVELS says how many levels of indirect addressing this machine + supports. + + Value is nonzero if this address is reloaded or replaced as a whole. + This is interesting to the caller if the address is an autoincrement. + + Note that there is no verification that the address will be valid after + this routine does its work. Instead, we rely on the fact that the address + was valid when reload started. So we need only undo things that reload + could have broken. These are wrong register types, pseudos not allocated + to a hard register, and frame pointer elimination. */ + +static int +find_reloads_address (mode, memrefloc, ad, loc, opnum, type, ind_levels) + enum machine_mode mode; + rtx *memrefloc; + rtx ad; + rtx *loc; + int opnum; + enum reload_type type; + int ind_levels; +{ + register int regno; + rtx tem; + + /* If the address is a register, see if it is a legitimate address and + reload if not. We first handle the cases where we need not reload + or where we must reload in a non-standard way. */ + + if (GET_CODE (ad) == REG) + { + regno = REGNO (ad); + + if (reg_equiv_constant[regno] != 0 + && strict_memory_address_p (mode, reg_equiv_constant[regno])) + { + *loc = ad = reg_equiv_constant[regno]; + return 1; + } + + else if (reg_equiv_address[regno] != 0) + { + tem = make_memloc (ad, regno); + find_reloads_address (GET_MODE (tem), NULL_PTR, XEXP (tem, 0), + &XEXP (tem, 0), opnum, type, ind_levels); + push_reload (tem, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS, + GET_MODE (ad), VOIDmode, 0, 0, + opnum, type); + return 1; + } + + /* We can avoid a reload if the register's equivalent memory expression + is valid as an indirect memory address. */ + + else if (reg_equiv_mem[regno] != 0 && ind_levels > 0 + && strict_memory_address_p (mode, reg_equiv_mem[regno])) + return 0; + + /* The only remaining case where we can avoid a reload is if this is a + hard register that is valid as a base register and which is not the + subject of a CLOBBER in this insn. */ + + else if (regno < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P (regno) + && ! regno_clobbered_p (regno, this_insn)) + return 0; + + /* If we do not have one of the cases above, we must do the reload. */ + push_reload (ad, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS, + GET_MODE (ad), VOIDmode, 0, 0, opnum, type); + return 1; + } + + if (strict_memory_address_p (mode, ad)) + { + /* The address appears valid, so reloads are not needed. + But the address may contain an eliminable register. + This can happen because a machine with indirect addressing + may consider a pseudo register by itself a valid address even when + it has failed to get a hard reg. + So do a tree-walk to find and eliminate all such regs. */ + + /* But first quickly dispose of a common case. */ + if (GET_CODE (ad) == PLUS + && GET_CODE (XEXP (ad, 1)) == CONST_INT + && GET_CODE (XEXP (ad, 0)) == REG + && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0) + return 0; + + subst_reg_equivs_changed = 0; + *loc = subst_reg_equivs (ad); + + if (! subst_reg_equivs_changed) + return 0; + + /* Check result for validity after substitution. */ + if (strict_memory_address_p (mode, ad)) + return 0; + } + + /* The address is not valid. We have to figure out why. One possibility + is that it is itself a MEM. This can happen when the frame pointer is + being eliminated, a pseudo is not allocated to a hard register, and the + offset between the frame and stack pointers is not its initial value. + In that case the pseudo will have been replaced by a MEM referring to + the stack pointer. */ + if (GET_CODE (ad) == MEM) + { + /* First ensure that the address in this MEM is valid. Then, unless + indirect addresses are valid, reload the MEM into a register. */ + tem = ad; + find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0), + opnum, type, ind_levels == 0 ? 0 : ind_levels - 1); + + /* If tem was changed, then we must create a new memory reference to + hold it and store it back into memrefloc. */ + if (tem != ad && memrefloc) + { + *memrefloc = copy_rtx (*memrefloc); + copy_replacements (tem, XEXP (*memrefloc, 0)); + loc = &XEXP (*memrefloc, 0); + } + + /* Check similar cases as for indirect addresses as above except + that we can allow pseudos and a MEM since they should have been + taken care of above. */ + + if (ind_levels == 0 + || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok) + || GET_CODE (XEXP (tem, 0)) == MEM + || ! (GET_CODE (XEXP (tem, 0)) == REG + || (GET_CODE (XEXP (tem, 0)) == PLUS + && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG + && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT))) + { + /* Must use TEM here, not AD, since it is the one that will + have any subexpressions reloaded, if needed. */ + push_reload (tem, NULL_RTX, loc, NULL_PTR, + BASE_REG_CLASS, GET_MODE (tem), VOIDmode, 0, + 0, opnum, type); + return 1; + } + else + return 0; + } + + /* If we have address of a stack slot but it's not valid + (displacement is too large), compute the sum in a register. */ + else if (GET_CODE (ad) == PLUS + && (XEXP (ad, 0) == frame_pointer_rtx +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + || XEXP (ad, 0) == arg_pointer_rtx +#endif + || XEXP (ad, 0) == stack_pointer_rtx) + && GET_CODE (XEXP (ad, 1)) == CONST_INT) + { + /* Unshare the MEM rtx so we can safely alter it. */ + if (memrefloc) + { + rtx oldref = *memrefloc; + *memrefloc = copy_rtx (*memrefloc); + loc = &XEXP (*memrefloc, 0); + } + if (double_reg_address_ok) + { + /* Unshare the sum as well. */ + *loc = ad = copy_rtx (ad); + /* Reload the displacement into an index reg. + We assume the frame pointer or arg pointer is a base reg. */ + find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), + INDEX_REG_CLASS, GET_MODE (ad), opnum, + type, ind_levels); + } + else + { + /* If the sum of two regs is not necessarily valid, + reload the sum into a base reg. + That will at least work. */ + find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, + opnum, type, ind_levels); + } + return 1; + } + + /* If we have an indexed stack slot, there are three possible reasons why + it might be invalid: The index might need to be reloaded, the address + might have been made by frame pointer elimination and hence have a + constant out of range, or both reasons might apply. + + We can easily check for an index needing reload, but even if that is the + case, we might also have an invalid constant. To avoid making the + conservative assumption and requiring two reloads, we see if this address + is valid when not interpreted strictly. If it is, the only problem is + that the index needs a reload and find_reloads_address_1 will take care + of it. + + There is still a case when we might generate an extra reload, + however. In certain cases eliminate_regs will return a MEM for a REG + (see the code there for details). In those cases, memory_address_p + applied to our address will return 0 so we will think that our offset + must be too large. But it might indeed be valid and the only problem + is that a MEM is present where a REG should be. This case should be + very rare and there doesn't seem to be any way to avoid it. + + If we decide to do something here, it must be that + `double_reg_address_ok' is true and that this address rtl was made by + eliminate_regs. We generate a reload of the fp/sp/ap + constant and + rework the sum so that the reload register will be added to the index. + This is safe because we know the address isn't shared. + + We check for fp/ap/sp as both the first and second operand of the + innermost PLUS. */ + + else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT + && GET_CODE (XEXP (ad, 0)) == PLUS + && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx +#endif + || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx) + && ! memory_address_p (mode, ad)) + { + *loc = ad = gen_rtx (PLUS, GET_MODE (ad), + plus_constant (XEXP (XEXP (ad, 0), 0), + INTVAL (XEXP (ad, 1))), + XEXP (XEXP (ad, 0), 1)); + find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS, + GET_MODE (ad), opnum, type, ind_levels); + find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), opnum, type, 0); + + return 1; + } + + else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT + && GET_CODE (XEXP (ad, 0)) == PLUS + && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx +#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM + || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx +#endif + || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx) + && ! memory_address_p (mode, ad)) + { + *loc = ad = gen_rtx (PLUS, GET_MODE (ad), + plus_constant (XEXP (XEXP (ad, 0), 1), + INTVAL (XEXP (ad, 1))), + XEXP (XEXP (ad, 0), 0)); + find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS, + GET_MODE (ad), opnum, type, ind_levels); + find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), opnum, type, 0); + + return 1; + } + + /* See if address becomes valid when an eliminable register + in a sum is replaced. */ + + tem = ad; + if (GET_CODE (ad) == PLUS) + tem = subst_indexed_address (ad); + if (tem != ad && strict_memory_address_p (mode, tem)) + { + /* Ok, we win that way. Replace any additional eliminable + registers. */ + + subst_reg_equivs_changed = 0; + tem = subst_reg_equivs (tem); + + /* Make sure that didn't make the address invalid again. */ + + if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem)) + { + *loc = tem; + return 0; + } + } + + /* If constants aren't valid addresses, reload the constant address + into a register. */ + if (CONSTANT_P (ad) && ! strict_memory_address_p (mode, ad)) + { + /* If AD is in address in the constant pool, the MEM rtx may be shared. + Unshare it so we can safely alter it. */ + if (memrefloc && GET_CODE (ad) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (ad)) + { + rtx oldref = *memrefloc; + *memrefloc = copy_rtx (*memrefloc); + loc = &XEXP (*memrefloc, 0); + } + + find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, opnum, type, + ind_levels); + return 1; + } + + return find_reloads_address_1 (ad, 0, loc, opnum, type, ind_levels); +} + +/* Find all pseudo regs appearing in AD + that are eliminable in favor of equivalent values + and do not have hard regs; replace them by their equivalents. */ + +static rtx +subst_reg_equivs (ad) + rtx ad; +{ + register RTX_CODE code = GET_CODE (ad); + register int i; + register char *fmt; + + switch (code) + { + case HIGH: + case CONST_INT: + case CONST: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case PC: + case CC0: + return ad; + + case REG: + { + register int regno = REGNO (ad); + + if (reg_equiv_constant[regno] != 0) + { + subst_reg_equivs_changed = 1; + return reg_equiv_constant[regno]; + } + } + return ad; + + case PLUS: + /* Quickly dispose of a common case. */ + if (XEXP (ad, 0) == frame_pointer_rtx + && GET_CODE (XEXP (ad, 1)) == CONST_INT) + return ad; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i)); + return ad; +} + +/* Compute the sum of X and Y, making canonicalizations assumed in an + address, namely: sum constant integers, surround the sum of two + constants with a CONST, put the constant as the second operand, and + group the constant on the outermost sum. + + This routine assumes both inputs are already in canonical form. */ + +rtx +form_sum (x, y) + rtx x, y; +{ + rtx tem; + enum machine_mode mode = GET_MODE (x); + + if (mode == VOIDmode) + mode = GET_MODE (y); + + if (mode == VOIDmode) + mode = Pmode; + + if (GET_CODE (x) == CONST_INT) + return plus_constant (y, INTVAL (x)); + else if (GET_CODE (y) == CONST_INT) + return plus_constant (x, INTVAL (y)); + else if (CONSTANT_P (x)) + tem = x, x = y, y = tem; + + if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) + return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); + + /* Note that if the operands of Y are specified in the opposite + order in the recursive calls below, infinite recursion will occur. */ + if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) + return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); + + /* If both constant, encapsulate sum. Otherwise, just form sum. A + constant will have been placed second. */ + if (CONSTANT_P (x) && CONSTANT_P (y)) + { + if (GET_CODE (x) == CONST) + x = XEXP (x, 0); + if (GET_CODE (y) == CONST) + y = XEXP (y, 0); + + return gen_rtx (CONST, VOIDmode, gen_rtx (PLUS, mode, x, y)); + } + + return gen_rtx (PLUS, mode, x, y); +} + +/* If ADDR is a sum containing a pseudo register that should be + replaced with a constant (from reg_equiv_constant), + return the result of doing so, and also apply the associative + law so that the result is more likely to be a valid address. + (But it is not guaranteed to be one.) + + Note that at most one register is replaced, even if more are + replaceable. Also, we try to put the result into a canonical form + so it is more likely to be a valid address. + + In all other cases, return ADDR. */ + +static rtx +subst_indexed_address (addr) + rtx addr; +{ + rtx op0 = 0, op1 = 0, op2 = 0; + rtx tem; + int regno; + + if (GET_CODE (addr) == PLUS) + { + /* Try to find a register to replace. */ + op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0; + if (GET_CODE (op0) == REG + && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER + && reg_renumber[regno] < 0 + && reg_equiv_constant[regno] != 0) + op0 = reg_equiv_constant[regno]; + else if (GET_CODE (op1) == REG + && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER + && reg_renumber[regno] < 0 + && reg_equiv_constant[regno] != 0) + op1 = reg_equiv_constant[regno]; + else if (GET_CODE (op0) == PLUS + && (tem = subst_indexed_address (op0)) != op0) + op0 = tem; + else if (GET_CODE (op1) == PLUS + && (tem = subst_indexed_address (op1)) != op1) + op1 = tem; + else + return addr; + + /* Pick out up to three things to add. */ + if (GET_CODE (op1) == PLUS) + op2 = XEXP (op1, 1), op1 = XEXP (op1, 0); + else if (GET_CODE (op0) == PLUS) + op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); + + /* Compute the sum. */ + if (op2 != 0) + op1 = form_sum (op1, op2); + if (op1 != 0) + op0 = form_sum (op0, op1); + + return op0; + } + return addr; +} + +/* Record the pseudo registers we must reload into hard registers + in a subexpression of a would-be memory address, X. + (This function is not called if the address we find is strictly valid.) + CONTEXT = 1 means we are considering regs as index regs, + = 0 means we are considering them as base regs. + + OPNUM and TYPE specify the purpose of any reloads made. + + IND_LEVELS says how many levels of indirect addressing are + supported at this point in the address. + + We return nonzero if X, as a whole, is reloaded or replaced. */ + +/* Note that we take shortcuts assuming that no multi-reg machine mode + occurs as part of an address. + Also, this is not fully machine-customizable; it works for machines + such as vaxes and 68000's and 32000's, but other possible machines + could have addressing modes that this does not handle right. */ + +static int +find_reloads_address_1 (x, context, loc, opnum, type, ind_levels) + rtx x; + int context; + rtx *loc; + int opnum; + enum reload_type type; + int ind_levels; +{ + register RTX_CODE code = GET_CODE (x); + + if (code == PLUS) + { + register rtx op0 = XEXP (x, 0); + register rtx op1 = XEXP (x, 1); + register RTX_CODE code0 = GET_CODE (op0); + register RTX_CODE code1 = GET_CODE (op1); + if (code0 == MULT || code0 == SIGN_EXTEND || code1 == MEM) + { + find_reloads_address_1 (op0, 1, &XEXP (x, 0), opnum, type, + ind_levels); + find_reloads_address_1 (op1, 0, &XEXP (x, 1), opnum, type, + ind_levels); + } + else if (code1 == MULT || code1 == SIGN_EXTEND || code0 == MEM) + { + find_reloads_address_1 (op0, 0, &XEXP (x, 0), opnum, type, + ind_levels); + find_reloads_address_1 (op1, 1, &XEXP (x, 1), opnum, type, + ind_levels); + } + else if (code0 == CONST_INT || code0 == CONST + || code0 == SYMBOL_REF || code0 == LABEL_REF) + find_reloads_address_1 (op1, 0, &XEXP (x, 1), opnum, type, ind_levels); + else if (code1 == CONST_INT || code1 == CONST + || code1 == SYMBOL_REF || code1 == LABEL_REF) + find_reloads_address_1 (op0, 0, &XEXP (x, 0), opnum, type, ind_levels); + else if (code0 == REG && code1 == REG) + { + if (REG_OK_FOR_INDEX_P (op0) + && REG_OK_FOR_BASE_P (op1)) + return 0; + else if (REG_OK_FOR_INDEX_P (op1) + && REG_OK_FOR_BASE_P (op0)) + return 0; + else if (REG_OK_FOR_BASE_P (op1)) + find_reloads_address_1 (op0, 1, &XEXP (x, 0), opnum, type, + ind_levels); + else if (REG_OK_FOR_BASE_P (op0)) + find_reloads_address_1 (op1, 1, &XEXP (x, 1), opnum, type, + ind_levels); + else if (REG_OK_FOR_INDEX_P (op1)) + find_reloads_address_1 (op0, 0, &XEXP (x, 0), opnum, type, + ind_levels); + else if (REG_OK_FOR_INDEX_P (op0)) + find_reloads_address_1 (op1, 0, &XEXP (x, 1), opnum, type, + ind_levels); + else + { + find_reloads_address_1 (op0, 1, &XEXP (x, 0), opnum, type, + ind_levels); + find_reloads_address_1 (op1, 0, &XEXP (x, 1), opnum, type, + ind_levels); + } + } + else if (code0 == REG) + { + find_reloads_address_1 (op0, 1, &XEXP (x, 0), opnum, type, + ind_levels); + find_reloads_address_1 (op1, 0, &XEXP (x, 1), opnum, type, + ind_levels); + } + else if (code1 == REG) + { + find_reloads_address_1 (op1, 1, &XEXP (x, 1), opnum, type, + ind_levels); + find_reloads_address_1 (op0, 0, &XEXP (x, 0), opnum, type, + ind_levels); + } + } + else if (code == POST_INC || code == POST_DEC + || code == PRE_INC || code == PRE_DEC) + { + if (GET_CODE (XEXP (x, 0)) == REG) + { + register int regno = REGNO (XEXP (x, 0)); + int value = 0; + rtx x_orig = x; + + /* A register that is incremented cannot be constant! */ + if (regno >= FIRST_PSEUDO_REGISTER + && reg_equiv_constant[regno] != 0) + abort (); + + /* Handle a register that is equivalent to a memory location + which cannot be addressed directly. */ + if (reg_equiv_address[regno] != 0) + { + rtx tem = make_memloc (XEXP (x, 0), regno); + /* First reload the memory location's address. */ + find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0), + &XEXP (tem, 0), opnum, type, ind_levels); + /* Put this inside a new increment-expression. */ + x = gen_rtx (GET_CODE (x), GET_MODE (x), tem); + /* Proceed to reload that, as if it contained a register. */ + } + + /* If we have a hard register that is ok as an index, + don't make a reload. If an autoincrement of a nice register + isn't "valid", it must be that no autoincrement is "valid". + If that is true and something made an autoincrement anyway, + this must be a special context where one is allowed. + (For example, a "push" instruction.) + We can't improve this address, so leave it alone. */ + + /* Otherwise, reload the autoincrement into a suitable hard reg + and record how much to increment by. */ + + if (reg_renumber[regno] >= 0) + regno = reg_renumber[regno]; + if ((regno >= FIRST_PSEUDO_REGISTER + || !(context ? REGNO_OK_FOR_INDEX_P (regno) + : REGNO_OK_FOR_BASE_P (regno)))) + { + register rtx link; + + int reloadnum + = push_reload (x, NULL_RTX, loc, NULL_PTR, + context ? INDEX_REG_CLASS : BASE_REG_CLASS, + GET_MODE (x), GET_MODE (x), VOIDmode, 0, + opnum, type); + reload_inc[reloadnum] + = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0)); + + value = 1; + +#ifdef AUTO_INC_DEC + /* Update the REG_INC notes. */ + + for (link = REG_NOTES (this_insn); + link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_INC + && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0))) + push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); +#endif + } + return value; + } + else if (GET_CODE (XEXP (x, 0)) == MEM) + { + /* This is probably the result of a substitution, by eliminate_regs, + of an equivalent address for a pseudo that was not allocated to a + hard register. Verify that the specified address is valid and + reload it into a register. */ + rtx tem = XEXP (x, 0); + register rtx link; + int reloadnum; + + /* Since we know we are going to reload this item, don't decrement + for the indirection level. + + Note that this is actually conservative: it would be slightly + more efficient to use the value of SPILL_INDIRECT_LEVELS from + reload1.c here. */ + find_reloads_address (GET_MODE (x), &XEXP (x, 0), + XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0), + opnum, type, ind_levels); + + reloadnum = push_reload (x, NULL_RTX, loc, NULL_PTR, + context ? INDEX_REG_CLASS : BASE_REG_CLASS, + GET_MODE (x), VOIDmode, 0, 0, opnum, type); + reload_inc[reloadnum] + = find_inc_amount (PATTERN (this_insn), XEXP (x, 0)); + + link = FIND_REG_INC_NOTE (this_insn, tem); + if (link != 0) + push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); + + return 1; + } + } + else if (code == MEM) + { + /* This is probably the result of a substitution, by eliminate_regs, + of an equivalent address for a pseudo that was not allocated to a + hard register. Verify that the specified address is valid and reload + it into a register. + + Since we know we are going to reload this item, don't decrement + for the indirection level. + + Note that this is actually conservative: it would be slightly more + efficient to use the value of SPILL_INDIRECT_LEVELS from + reload1.c here. */ + + find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), + opnum, type, ind_levels); + + push_reload (*loc, NULL_RTX, loc, NULL_PTR, + context ? INDEX_REG_CLASS : BASE_REG_CLASS, + GET_MODE (x), VOIDmode, 0, 0, opnum, type); + return 1; + } + else if (code == REG) + { + register int regno = REGNO (x); + + if (reg_equiv_constant[regno] != 0) + { + find_reloads_address_part (reg_equiv_constant[regno], loc, + (context ? INDEX_REG_CLASS + : BASE_REG_CLASS), + GET_MODE (x), opnum, type, ind_levels); + return 1; + } + +#if 0 /* This might screw code in reload1.c to delete prior output-reload + that feeds this insn. */ + if (reg_equiv_mem[regno] != 0) + { + push_reload (reg_equiv_mem[regno], NULL_RTX, loc, NULL_PTR, + context ? INDEX_REG_CLASS : BASE_REG_CLASS, + GET_MODE (x), VOIDmode, 0, 0, opnum, type); + return 1; + } +#endif + if (reg_equiv_address[regno] != 0) + { + x = make_memloc (x, regno); + find_reloads_address (GET_MODE (x), 0, XEXP (x, 0), &XEXP (x, 0), + opnum, type, ind_levels); + } + + if (reg_renumber[regno] >= 0) + regno = reg_renumber[regno]; + if ((regno >= FIRST_PSEUDO_REGISTER + || !(context ? REGNO_OK_FOR_INDEX_P (regno) + : REGNO_OK_FOR_BASE_P (regno)))) + { + push_reload (x, NULL_RTX, loc, NULL_PTR, + context ? INDEX_REG_CLASS : BASE_REG_CLASS, + GET_MODE (x), VOIDmode, 0, 0, opnum, type); + return 1; + } + + /* If a register appearing in an address is the subject of a CLOBBER + in this insn, reload it into some other register to be safe. + The CLOBBER is supposed to make the register unavailable + from before this insn to after it. */ + if (regno_clobbered_p (regno, this_insn)) + { + push_reload (x, NULL_RTX, loc, NULL_PTR, + context ? INDEX_REG_CLASS : BASE_REG_CLASS, + GET_MODE (x), VOIDmode, 0, 0, opnum, type); + return 1; + } + } + else + { + register char *fmt = GET_RTX_FORMAT (code); + register int i; + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + find_reloads_address_1 (XEXP (x, i), context, &XEXP (x, i), + opnum, type, ind_levels); + } + } + + return 0; +} + +/* X, which is found at *LOC, is a part of an address that needs to be + reloaded into a register of class CLASS. If X is a constant, or if + X is a PLUS that contains a constant, check that the constant is a + legitimate operand and that we are supposed to be able to load + it into the register. + + If not, force the constant into memory and reload the MEM instead. + + MODE is the mode to use, in case X is an integer constant. + + OPNUM and TYPE describe the purpose of any reloads made. + + IND_LEVELS says how many levels of indirect addressing this machine + supports. */ + +static void +find_reloads_address_part (x, loc, class, mode, opnum, type, ind_levels) + rtx x; + rtx *loc; + enum reg_class class; + enum machine_mode mode; + int opnum; + enum reload_type type; + int ind_levels; +{ + if (CONSTANT_P (x) + && (! LEGITIMATE_CONSTANT_P (x) + || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS)) + { + rtx tem = x = force_const_mem (mode, x); + find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), + opnum, type, ind_levels); + } + + else if (GET_CODE (x) == PLUS + && CONSTANT_P (XEXP (x, 1)) + && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) + || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS)) + { + rtx tem = force_const_mem (GET_MODE (x), XEXP (x, 1)); + + x = gen_rtx (PLUS, GET_MODE (x), XEXP (x, 0), tem); + find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), + opnum, type, ind_levels); + } + + push_reload (x, NULL_RTX, loc, NULL_PTR, class, + mode, VOIDmode, 0, 0, opnum, type); +} + +/* Substitute into the current INSN the registers into which we have reloaded + the things that need reloading. The array `replacements' + says contains the locations of all pointers that must be changed + and says what to replace them with. + + Return the rtx that X translates into; usually X, but modified. */ + +void +subst_reloads () +{ + register int i; + + for (i = 0; i < n_replacements; i++) + { + register struct replacement *r = &replacements[i]; + register rtx reloadreg = reload_reg_rtx[r->what]; + if (reloadreg) + { + /* Encapsulate RELOADREG so its machine mode matches what + used to be there. */ + if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode) + reloadreg = gen_lowpart_common (r->mode, reloadreg); + + /* If we are putting this into a SUBREG and RELOADREG is a + SUBREG, we would be making nested SUBREGs, so we have to fix + this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */ + + if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG) + { + if (GET_MODE (*r->subreg_loc) + == GET_MODE (SUBREG_REG (reloadreg))) + *r->subreg_loc = SUBREG_REG (reloadreg); + else + { + *r->where = SUBREG_REG (reloadreg); + SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg); + } + } + else + *r->where = reloadreg; + } + /* If reload got no reg and isn't optional, something's wrong. */ + else if (! reload_optional[r->what]) + abort (); + } +} + +/* Make a copy of any replacements being done into X and move those copies + to locations in Y, a copy of X. We only look at the highest level of + the RTL. */ + +void +copy_replacements (x, y) + rtx x; + rtx y; +{ + int i, j; + enum rtx_code code = GET_CODE (x); + char *fmt = GET_RTX_FORMAT (code); + struct replacement *r; + + /* We can't support X being a SUBREG because we might then need to know its + location if something inside it was replaced. */ + if (code == SUBREG) + abort (); + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + for (j = 0; j < n_replacements; j++) + { + if (replacements[j].subreg_loc == &XEXP (x, i)) + { + r = &replacements[n_replacements++]; + r->where = replacements[j].where; + r->subreg_loc = &XEXP (y, i); + r->what = replacements[j].what; + r->mode = replacements[j].mode; + } + else if (replacements[j].where == &XEXP (x, i)) + { + r = &replacements[n_replacements++]; + r->where = &XEXP (y, i); + r->subreg_loc = 0; + r->what = replacements[j].what; + r->mode = replacements[j].mode; + } + } +} + +/* If LOC was scheduled to be replaced by something, return the replacement. + Otherwise, return *LOC. */ + +rtx +find_replacement (loc) + rtx *loc; +{ + struct replacement *r; + + for (r = &replacements[0]; r < &replacements[n_replacements]; r++) + { + rtx reloadreg = reload_reg_rtx[r->what]; + + if (reloadreg && r->where == loc) + { + if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) + reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg)); + + return reloadreg; + } + else if (reloadreg && r->subreg_loc == loc) + { + /* RELOADREG must be either a REG or a SUBREG. + + ??? Is it actually still ever a SUBREG? If so, why? */ + + if (GET_CODE (reloadreg) == REG) + return gen_rtx (REG, GET_MODE (*loc), + REGNO (reloadreg) + SUBREG_WORD (*loc)); + else if (GET_MODE (reloadreg) == GET_MODE (*loc)) + return reloadreg; + else + return gen_rtx (SUBREG, GET_MODE (*loc), SUBREG_REG (reloadreg), + SUBREG_WORD (reloadreg) + SUBREG_WORD (*loc)); + } + } + + return *loc; +} + +/* Return nonzero if register in range [REGNO, ENDREGNO) + appears either explicitly or implicitly in X + other than being stored into. + + References contained within the substructure at LOC do not count. + LOC may be zero, meaning don't ignore anything. + + This is similar to refers_to_regno_p in rtlanal.c except that we + look at equivalences for pseudos that didn't get hard registers. */ + +int +refers_to_regno_for_reload_p (regno, endregno, x, loc) + int regno, endregno; + rtx x; + rtx *loc; +{ + register int i; + register RTX_CODE code; + register char *fmt; + + if (x == 0) + return 0; + + repeat: + code = GET_CODE (x); + + switch (code) + { + case REG: + i = REGNO (x); + + /* If this is a pseudo, a hard register must not have been allocated. + X must therefore either be a constant or be in memory. */ + if (i >= FIRST_PSEUDO_REGISTER) + { + if (reg_equiv_memory_loc[i]) + return refers_to_regno_for_reload_p (regno, endregno, + reg_equiv_memory_loc[i], + NULL_PTR); + + if (reg_equiv_constant[i]) + return 0; + + abort (); + } + + return (endregno > i + && regno < i + (i < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (i, GET_MODE (x)) + : 1)); + + case SUBREG: + /* If this is a SUBREG of a hard reg, we can see exactly which + registers are being modified. Otherwise, handle normally. */ + if (GET_CODE (SUBREG_REG (x)) == REG + && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) + { + int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); + int inner_endregno + = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); + + return endregno > inner_regno && regno < inner_endregno; + } + break; + + case CLOBBER: + case SET: + if (&SET_DEST (x) != loc + /* Note setting a SUBREG counts as referring to the REG it is in for + a pseudo but not for hard registers since we can + treat each word individually. */ + && ((GET_CODE (SET_DEST (x)) == SUBREG + && loc != &SUBREG_REG (SET_DEST (x)) + && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG + && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER + && refers_to_regno_for_reload_p (regno, endregno, + SUBREG_REG (SET_DEST (x)), + loc)) + || (GET_CODE (SET_DEST (x)) != REG + && refers_to_regno_for_reload_p (regno, endregno, + SET_DEST (x), loc)))) + return 1; + + if (code == CLOBBER || loc == &SET_SRC (x)) + return 0; + x = SET_SRC (x); + goto repeat; + } + + /* X does not match, so try its subexpressions. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e' && loc != &XEXP (x, i)) + { + if (i == 0) + { + x = XEXP (x, 0); + goto repeat; + } + else + if (refers_to_regno_for_reload_p (regno, endregno, + XEXP (x, i), loc)) + return 1; + } + else if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (x, i) - 1; j >=0; j--) + if (loc != &XVECEXP (x, i, j) + && refers_to_regno_for_reload_p (regno, endregno, + XVECEXP (x, i, j), loc)) + return 1; + } + } + return 0; +} + +/* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, + we check if any register number in X conflicts with the relevant register + numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN + contains a MEM (we don't bother checking for memory addresses that can't + conflict because we expect this to be a rare case. + + This function is similar to reg_overlap_mention_p in rtlanal.c except + that we look at equivalences for pseudos that didn't get hard registers. */ + +int +reg_overlap_mentioned_for_reload_p (x, in) + rtx x, in; +{ + int regno, endregno; + + if (GET_CODE (x) == SUBREG) + { + regno = REGNO (SUBREG_REG (x)); + if (regno < FIRST_PSEUDO_REGISTER) + regno += SUBREG_WORD (x); + } + else if (GET_CODE (x) == REG) + { + regno = REGNO (x); + + /* If this is a pseudo, it must not have been assigned a hard register. + Therefore, it must either be in memory or be a constant. */ + + if (regno >= FIRST_PSEUDO_REGISTER) + { + if (reg_equiv_memory_loc[regno]) + return refers_to_mem_for_reload_p (in); + else if (reg_equiv_constant[regno]) + return 0; + abort (); + } + } + else if (CONSTANT_P (x)) + return 0; + else if (GET_CODE (x) == MEM) + return refers_to_mem_for_reload_p (in); + else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC + || GET_CODE (x) == CC0) + return reg_mentioned_p (x, in); + else + abort (); + + endregno = regno + (regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); + + return refers_to_regno_for_reload_p (regno, endregno, in, NULL_PTR); +} + +/* Return nonzero if anything in X contains a MEM. Look also for pseudo + registers. */ + +int +refers_to_mem_for_reload_p (x) + rtx x; +{ + char *fmt; + int i; + + if (GET_CODE (x) == MEM) + return 1; + + if (GET_CODE (x) == REG) + return (REGNO (x) >= FIRST_PSEUDO_REGISTER + && reg_equiv_memory_loc[REGNO (x)]); + + fmt = GET_RTX_FORMAT (GET_CODE (x)); + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) + if (fmt[i] == 'e' + && (GET_CODE (XEXP (x, i)) == MEM + || refers_to_mem_for_reload_p (XEXP (x, i)))) + return 1; + + return 0; +} + +/* Check the insns before INSN to see if there is a suitable register + containing the same value as GOAL. + If OTHER is -1, look for a register in class CLASS. + Otherwise, just see if register number OTHER shares GOAL's value. + + Return an rtx for the register found, or zero if none is found. + + If RELOAD_REG_P is (short *)1, + we reject any hard reg that appears in reload_reg_rtx + because such a hard reg is also needed coming into this insn. + + If RELOAD_REG_P is any other nonzero value, + it is a vector indexed by hard reg number + and we reject any hard reg whose element in the vector is nonnegative + as well as any that appears in reload_reg_rtx. + + If GOAL is zero, then GOALREG is a register number; we look + for an equivalent for that register. + + MODE is the machine mode of the value we want an equivalence for. + If GOAL is nonzero and not VOIDmode, then it must have mode MODE. + + This function is used by jump.c as well as in the reload pass. + + If GOAL is the sum of the stack pointer and a constant, we treat it + as if it were a constant except that sp is required to be unchanging. */ + +rtx +find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode) + register rtx goal; + rtx insn; + enum reg_class class; + register int other; + short *reload_reg_p; + int goalreg; + enum machine_mode mode; +{ + register rtx p = insn; + rtx goaltry, valtry, value, where; + register rtx pat; + register int regno = -1; + int valueno; + int goal_mem = 0; + int goal_const = 0; + int goal_mem_addr_varies = 0; + int need_stable_sp = 0; + int nregs; + int valuenregs; + + if (goal == 0) + regno = goalreg; + else if (GET_CODE (goal) == REG) + regno = REGNO (goal); + else if (GET_CODE (goal) == MEM) + { + enum rtx_code code = GET_CODE (XEXP (goal, 0)); + if (MEM_VOLATILE_P (goal)) + return 0; + if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT) + return 0; + /* An address with side effects must be reexecuted. */ + switch (code) + { + case POST_INC: + case PRE_INC: + case POST_DEC: + case PRE_DEC: + return 0; + } + goal_mem = 1; + } + else if (CONSTANT_P (goal)) + goal_const = 1; + else if (GET_CODE (goal) == PLUS + && XEXP (goal, 0) == stack_pointer_rtx + && CONSTANT_P (XEXP (goal, 1))) + goal_const = need_stable_sp = 1; + else + return 0; + + /* On some machines, certain regs must always be rejected + because they don't behave the way ordinary registers do. */ + +#ifdef OVERLAPPING_REGNO_P + if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER + && OVERLAPPING_REGNO_P (regno)) + return 0; +#endif + + /* Scan insns back from INSN, looking for one that copies + a value into or out of GOAL. + Stop and give up if we reach a label. */ + + while (1) + { + p = PREV_INSN (p); + if (p == 0 || GET_CODE (p) == CODE_LABEL) + return 0; + if (GET_CODE (p) == INSN + /* If we don't want spill regs ... */ + && (! (reload_reg_p != 0 + && reload_reg_p != (short *) (HOST_WIDE_INT) 1) + /* ... then ignore insns introduced by reload; they aren't useful + and can cause results in reload_as_needed to be different + from what they were when calculating the need for spills. + If we notice an input-reload insn here, we will reject it below, + but it might hide a usable equivalent. That makes bad code. + It may even abort: perhaps no reg was spilled for this insn + because it was assumed we would find that equivalent. */ + || INSN_UID (p) < reload_first_uid)) + { + rtx tem; + pat = single_set (p); + /* First check for something that sets some reg equal to GOAL. */ + if (pat != 0 + && ((regno >= 0 + && true_regnum (SET_SRC (pat)) == regno + && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) + || + (regno >= 0 + && true_regnum (SET_DEST (pat)) == regno + && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0) + || + (goal_const && rtx_equal_p (SET_SRC (pat), goal) + && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) + || (goal_mem + && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0 + && rtx_renumbered_equal_p (goal, SET_SRC (pat))) + || (goal_mem + && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0 + && rtx_renumbered_equal_p (goal, SET_DEST (pat))) + /* If we are looking for a constant, + and something equivalent to that constant was copied + into a reg, we can use that reg. */ + || (goal_const && (tem = find_reg_note (p, REG_EQUIV, + NULL_RTX)) + && rtx_equal_p (XEXP (tem, 0), goal) + && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) + || (goal_const && (tem = find_reg_note (p, REG_EQUIV, + NULL_RTX)) + && GET_CODE (SET_DEST (pat)) == REG + && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE + && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT + && GET_CODE (goal) == CONST_INT + && 0 != (goaltry = operand_subword (XEXP (tem, 0), 0, 0, + VOIDmode)) + && rtx_equal_p (goal, goaltry) + && (valtry = operand_subword (SET_DEST (pat), 0, 0, + VOIDmode)) + && (valueno = true_regnum (valtry)) >= 0) + || (goal_const && (tem = find_reg_note (p, REG_EQUIV, + NULL_RTX)) + && GET_CODE (SET_DEST (pat)) == REG + && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE + && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT + && GET_CODE (goal) == CONST_INT + && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0, + VOIDmode)) + && rtx_equal_p (goal, goaltry) + && (valtry + = operand_subword (SET_DEST (pat), 1, 0, VOIDmode)) + && (valueno = true_regnum (valtry)) >= 0))) + if (other >= 0 + ? valueno == other + : ((unsigned) valueno < FIRST_PSEUDO_REGISTER + && TEST_HARD_REG_BIT (reg_class_contents[(int) class], + valueno))) + { + value = valtry; + where = p; + break; + } + } + } + + /* We found a previous insn copying GOAL into a suitable other reg VALUE + (or copying VALUE into GOAL, if GOAL is also a register). + Now verify that VALUE is really valid. */ + + /* VALUENO is the register number of VALUE; a hard register. */ + + /* Don't try to re-use something that is killed in this insn. We want + to be able to trust REG_UNUSED notes. */ + if (find_reg_note (where, REG_UNUSED, value)) + return 0; + + /* If we propose to get the value from the stack pointer or if GOAL is + a MEM based on the stack pointer, we need a stable SP. */ + if (valueno == STACK_POINTER_REGNUM + || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx, + goal))) + need_stable_sp = 1; + + /* Reject VALUE if the copy-insn moved the wrong sort of datum. */ + if (GET_MODE (value) != mode) + return 0; + + /* Reject VALUE if it was loaded from GOAL + and is also a register that appears in the address of GOAL. */ + + if (goal_mem && value == SET_DEST (PATTERN (where)) + && refers_to_regno_for_reload_p (valueno, + (valueno + + HARD_REGNO_NREGS (valueno, mode)), + goal, NULL_PTR)) + return 0; + + /* Reject registers that overlap GOAL. */ + + if (!goal_mem && !goal_const + && regno + HARD_REGNO_NREGS (regno, mode) > valueno + && regno < valueno + HARD_REGNO_NREGS (valueno, mode)) + return 0; + + /* Reject VALUE if it is one of the regs reserved for reloads. + Reload1 knows how to reuse them anyway, and it would get + confused if we allocated one without its knowledge. + (Now that insns introduced by reload are ignored above, + this case shouldn't happen, but I'm not positive.) */ + + if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1 + && reload_reg_p[valueno] >= 0) + return 0; + + /* On some machines, certain regs must always be rejected + because they don't behave the way ordinary registers do. */ + +#ifdef OVERLAPPING_REGNO_P + if (OVERLAPPING_REGNO_P (valueno)) + return 0; +#endif + + nregs = HARD_REGNO_NREGS (regno, mode); + valuenregs = HARD_REGNO_NREGS (valueno, mode); + + /* Reject VALUE if it is a register being used for an input reload + even if it is not one of those reserved. */ + + if (reload_reg_p != 0) + { + int i; + for (i = 0; i < n_reloads; i++) + if (reload_reg_rtx[i] != 0 && reload_in[i]) + { + int regno1 = REGNO (reload_reg_rtx[i]); + int nregs1 = HARD_REGNO_NREGS (regno1, + GET_MODE (reload_reg_rtx[i])); + if (regno1 < valueno + valuenregs + && regno1 + nregs1 > valueno) + return 0; + } + } + + if (goal_mem) + /* We must treat frame pointer as varying here, + since it can vary--in a nonlocal goto as generated by expand_goto. */ + goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0)); + + /* Now verify that the values of GOAL and VALUE remain unaltered + until INSN is reached. */ + + p = insn; + while (1) + { + p = PREV_INSN (p); + if (p == where) + return value; + + /* Don't trust the conversion past a function call + if either of the two is in a call-clobbered register, or memory. */ + if (GET_CODE (p) == CALL_INSN + && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER + && call_used_regs[regno]) + || + (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER + && call_used_regs[valueno]) + || + goal_mem + || need_stable_sp)) + return 0; + +#ifdef INSN_CLOBBERS_REGNO_P + if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER + && INSN_CLOBBERS_REGNO_P (p, valueno)) + || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER + && INSN_CLOBBERS_REGNO_P (p, regno))) + return 0; +#endif + + if (GET_RTX_CLASS (GET_CODE (p)) == 'i') + { + /* If this insn P stores in either GOAL or VALUE, return 0. + If GOAL is a memory ref and this insn writes memory, return 0. + If GOAL is a memory ref and its address is not constant, + and this insn P changes a register used in GOAL, return 0. */ + + pat = PATTERN (p); + if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) + { + register rtx dest = SET_DEST (pat); + while (GET_CODE (dest) == SUBREG + || GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == SIGN_EXTRACT + || GET_CODE (dest) == STRICT_LOW_PART) + dest = XEXP (dest, 0); + if (GET_CODE (dest) == REG) + { + register int xregno = REGNO (dest); + int xnregs; + if (REGNO (dest) < FIRST_PSEUDO_REGISTER) + xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); + else + xnregs = 1; + if (xregno < regno + nregs && xregno + xnregs > regno) + return 0; + if (xregno < valueno + valuenregs + && xregno + xnregs > valueno) + return 0; + if (goal_mem_addr_varies + && reg_overlap_mentioned_for_reload_p (dest, goal)) + return 0; + } + else if (goal_mem && GET_CODE (dest) == MEM + && ! push_operand (dest, GET_MODE (dest))) + return 0; + else if (need_stable_sp && push_operand (dest, GET_MODE (dest))) + return 0; + } + else if (GET_CODE (pat) == PARALLEL) + { + register int i; + for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) + { + register rtx v1 = XVECEXP (pat, 0, i); + if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER) + { + register rtx dest = SET_DEST (v1); + while (GET_CODE (dest) == SUBREG + || GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == SIGN_EXTRACT + || GET_CODE (dest) == STRICT_LOW_PART) + dest = XEXP (dest, 0); + if (GET_CODE (dest) == REG) + { + register int xregno = REGNO (dest); + int xnregs; + if (REGNO (dest) < FIRST_PSEUDO_REGISTER) + xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); + else + xnregs = 1; + if (xregno < regno + nregs + && xregno + xnregs > regno) + return 0; + if (xregno < valueno + valuenregs + && xregno + xnregs > valueno) + return 0; + if (goal_mem_addr_varies + && reg_overlap_mentioned_for_reload_p (dest, + goal)) + return 0; + } + else if (goal_mem && GET_CODE (dest) == MEM + && ! push_operand (dest, GET_MODE (dest))) + return 0; + else if (need_stable_sp + && push_operand (dest, GET_MODE (dest))) + return 0; + } + } + } + +#ifdef AUTO_INC_DEC + /* If this insn auto-increments or auto-decrements + either regno or valueno, return 0 now. + If GOAL is a memory ref and its address is not constant, + and this insn P increments a register used in GOAL, return 0. */ + { + register rtx link; + + for (link = REG_NOTES (p); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_INC + && GET_CODE (XEXP (link, 0)) == REG) + { + register int incno = REGNO (XEXP (link, 0)); + if (incno < regno + nregs && incno >= regno) + return 0; + if (incno < valueno + valuenregs && incno >= valueno) + return 0; + if (goal_mem_addr_varies + && reg_overlap_mentioned_for_reload_p (XEXP (link, 0), + goal)) + return 0; + } + } +#endif + } + } +} + +/* Find a place where INCED appears in an increment or decrement operator + within X, and return the amount INCED is incremented or decremented by. + The value is always positive. */ + +static int +find_inc_amount (x, inced) + rtx x, inced; +{ + register enum rtx_code code = GET_CODE (x); + register char *fmt; + register int i; + + if (code == MEM) + { + register rtx addr = XEXP (x, 0); + if ((GET_CODE (addr) == PRE_DEC + || GET_CODE (addr) == POST_DEC + || GET_CODE (addr) == PRE_INC + || GET_CODE (addr) == POST_INC) + && XEXP (addr, 0) == inced) + return GET_MODE_SIZE (GET_MODE (x)); + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + { + register int tem = find_inc_amount (XEXP (x, i), inced); + if (tem != 0) + return tem; + } + if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + { + register int tem = find_inc_amount (XVECEXP (x, i, j), inced); + if (tem != 0) + return tem; + } + } + } + + return 0; +} + +/* Return 1 if register REGNO is the subject of a clobber in insn INSN. */ + +int +regno_clobbered_p (regno, insn) + int regno; + rtx insn; +{ + if (GET_CODE (PATTERN (insn)) == CLOBBER + && GET_CODE (XEXP (PATTERN (insn), 0)) == REG) + return REGNO (XEXP (PATTERN (insn), 0)) == regno; + + if (GET_CODE (PATTERN (insn)) == PARALLEL) + { + int i = XVECLEN (PATTERN (insn), 0) - 1; + + for (; i >= 0; i--) + { + rtx elt = XVECEXP (PATTERN (insn), 0, i); + if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG + && REGNO (XEXP (elt, 0)) == regno) + return 1; + } + } + + return 0; +} diff --git a/gnu/usr.bin/cc/lib/reload.h b/gnu/usr.bin/cc/lib/reload.h new file mode 100644 index 000000000000..93de26a0dc94 --- /dev/null +++ b/gnu/usr.bin/cc/lib/reload.h @@ -0,0 +1,247 @@ +/* Communication between reload.c and reload1.c. + Copyright (C) 1987, 1991, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* Add prototype support. */ +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif + +#ifndef STDIO_PROTO +#ifdef BUFSIZ +#define STDIO_PROTO(ARGS) PROTO(ARGS) +#else +#define STDIO_PROTO(ARGS) () +#endif +#endif + +/* If secondary reloads are the same for inputs and outputs, define those + macros here. */ + +#ifdef SECONDARY_RELOAD_CLASS +#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ + SECONDARY_RELOAD_CLASS (CLASS, MODE, X) +#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ + SECONDARY_RELOAD_CLASS (CLASS, MODE, X) +#endif + +/* If either macro is defined, show that we need secondary reloads. */ +#if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) +#define HAVE_SECONDARY_RELOADS +#endif + +/* See reload.c and reload1.c for comments on these variables. */ + +/* Maximum number of reloads we can need. */ +#define MAX_RELOADS (2 * MAX_RECOG_OPERANDS * (MAX_REGS_PER_ADDRESS + 1)) + +extern rtx reload_in[MAX_RELOADS]; +extern rtx reload_out[MAX_RELOADS]; +extern rtx reload_in_reg[MAX_RELOADS]; +extern enum reg_class reload_reg_class[MAX_RELOADS]; +extern enum machine_mode reload_inmode[MAX_RELOADS]; +extern enum machine_mode reload_outmode[MAX_RELOADS]; +extern char reload_optional[MAX_RELOADS]; +extern int reload_inc[MAX_RELOADS]; +extern int reload_opnum[MAX_RELOADS]; +extern int reload_secondary_reload[MAX_RELOADS]; +extern int reload_secondary_p[MAX_RELOADS]; +#ifdef MAX_INSN_CODE +extern enum insn_code reload_secondary_icode[MAX_RELOADS]; +#endif +extern int n_reloads; + +extern rtx reload_reg_rtx[MAX_RELOADS]; + +/* Encode the usage of a reload. The following codes are supported: + + RELOAD_FOR_INPUT reload of an input operand + RELOAD_FOR_OUTPUT likewise, for output + RELOAD_FOR_INSN a reload that must not conflict with anything + used in the insn, but may conflict with + something used before or after the insn + RELOAD_FOR_INPUT_ADDRESS reload for parts of the address of an object + that is an input reload + RELOAD_FOR_OUTPUT_ADDRESS likewise, for output reload + RELOAD_FOR_OPERAND_ADDRESS reload for the address of a non-reloaded + operand; these don't conflict with + any other addresses. + RELOAD_OTHER none of the above, usually multiple uses + RELOAD_FOR_OTHER_ADDRESS reload for part of the address of an input + that is marked RELOAD_OTHER. + + This used to be "enum reload_when_needed" but some debuggers have trouble + with an enum tag and variable of the same name. */ + +enum reload_type +{ + RELOAD_FOR_INPUT, RELOAD_FOR_OUTPUT, RELOAD_FOR_INSN, + RELOAD_FOR_INPUT_ADDRESS, RELOAD_FOR_OUTPUT_ADDRESS, + RELOAD_FOR_OPERAND_ADDRESS, RELOAD_OTHER, RELOAD_FOR_OTHER_ADDRESS +}; + +extern enum reload_type reload_when_needed[MAX_RELOADS]; + +extern rtx *reg_equiv_constant; +extern rtx *reg_equiv_memory_loc; +extern rtx *reg_equiv_address; +extern rtx *reg_equiv_mem; + +/* All the "earlyclobber" operands of the current insn + are recorded here. */ +extern int n_earlyclobbers; +extern rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; + +/* Save the number of operands. */ +extern int reload_n_operands; + +/* First uid used by insns created by reload in this function. + Used in find_equiv_reg. */ +extern int reload_first_uid; + +/* Nonzero if indirect addressing is supported when the innermost MEM is + of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to + which these are valid is the same as spill_indirect_levels, above. */ + +extern char indirect_symref_ok; + +/* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ +extern char double_reg_address_ok; + +#ifdef MAX_INSN_CODE +/* These arrays record the insn_code of insns that may be needed to + perform input and output reloads of special objects. They provide a + place to pass a scratch register. */ +extern enum insn_code reload_in_optab[]; +extern enum insn_code reload_out_optab[]; +#endif + +/* Functions from reload.c: */ + +/* Return a memory location that will be used to copy X in mode MODE. + If we haven't already made a location for this mode in this insn, + call find_reloads_address on the location being returned. */ +extern rtx get_secondary_mem PROTO((rtx, enum machine_mode, + int, enum reload_type)); + +/* Clear any secondary memory locations we've made. */ +extern void clear_secondary_mem PROTO((void)); + +/* Transfer all replacements that used to be in reload FROM to be in + reload TO. */ +extern void transfer_replacements PROTO((int, int)); + +/* Return 1 if ADDR is a valid memory address for mode MODE, + and check that each pseudo reg has the proper kind of + hard reg. */ +extern int strict_memory_address_p PROTO((enum machine_mode, rtx)); + +/* Like rtx_equal_p except that it allows a REG and a SUBREG to match + if they are the same hard reg, and has special hacks for + autoincrement and autodecrement. */ +extern int operands_match_p PROTO((rtx, rtx)); + +/* Return the number of times character C occurs in string S. */ +extern int n_occurrences PROTO((int, char *)); + +/* Return 1 if altering OP will not modify the value of CLOBBER. */ +extern int safe_from_earlyclobber PROTO((rtx, rtx)); + +/* Search the body of INSN for values that need reloading and record them + with push_reload. REPLACE nonzero means record also where the values occur + so that subst_reloads can be used. */ +extern void find_reloads PROTO((rtx, int, int, int, short *)); + +/* Compute the sum of X and Y, making canonicalizations assumed in an + address, namely: sum constant integers, surround the sum of two + constants with a CONST, put the constant as the second operand, and + group the constant on the outermost sum. */ +extern rtx form_sum PROTO((rtx, rtx)); + +/* Substitute into the current INSN the registers into which we have reloaded + the things that need reloading. */ +extern void subst_reloads PROTO((void)); + +/* Make a copy of any replacements being done into X and move those copies + to locations in Y, a copy of X. We only look at the highest level of + the RTL. */ +extern void copy_replacements PROTO((rtx, rtx)); + +/* If LOC was scheduled to be replaced by something, return the replacement. + Otherwise, return *LOC. */ +extern rtx find_replacement PROTO((rtx *)); + +/* Return nonzero if register in range [REGNO, ENDREGNO) + appears either explicitly or implicitly in X + other than being stored into. */ +extern int refers_to_regno_for_reload_p PROTO((int, int, rtx, rtx *)); + +/* Nonzero if modifying X will affect IN. */ +extern int reg_overlap_mentioned_for_reload_p PROTO((rtx, rtx)); + +/* Return nonzero if anything in X contains a MEM. Look also for pseudo + registers. */ +extern int refers_to_mem_for_reload_p PROTO((rtx)); + +/* Check the insns before INSN to see if there is a suitable register + containing the same value as GOAL. */ +extern rtx find_equiv_reg PROTO((rtx, rtx, enum reg_class, int, short *, + int, enum machine_mode)); + +/* Return 1 if register REGNO is the subject of a clobber in insn INSN. */ +extern int regno_clobbered_p PROTO((int, rtx)); + + +/* Functions in reload1.c: */ + +/* Initialize the reload pass once per compilation. */ +extern void init_reload PROTO((void)); + +/* The reload pass itself. */ +extern int reload STDIO_PROTO((rtx, int, FILE *)); + +/* Mark the slots in regs_ever_live for the hard regs + used by pseudo-reg number REGNO. */ +extern void mark_home_live PROTO((int)); + +/* Scan X and replace any eliminable registers (such as fp) with a + replacement (such as sp), plus an offset. */ +extern rtx eliminate_regs PROTO((rtx, enum machine_mode, rtx)); + +/* Emit code to perform an input reload of IN to RELOADREG. IN is from + operand OPNUM with reload type TYPE. */ +extern rtx gen_input_reload PROTO((rtx, rtx, int, enum reload_type)); + +/* Functions in caller-save.c: */ + +/* Initialize for caller-save. */ +extern void init_caller_save PROTO((void)); + +/* Initialize save areas by showing that we haven't allocated any yet. */ +extern void init_save_areas PROTO((void)); + +/* Allocate save areas for any hard registers that might need saving. */ +extern int setup_save_areas PROTO((int *)); + +/* Find the places where hard regs are live across calls and save them. */ +extern void save_call_clobbered_regs PROTO((enum machine_mode)); diff --git a/gnu/usr.bin/cc/lib/reload1.c b/gnu/usr.bin/cc/lib/reload1.c new file mode 100644 index 000000000000..87076c8a011a --- /dev/null +++ b/gnu/usr.bin/cc/lib/reload1.c @@ -0,0 +1,6774 @@ +/* Reload pseudo regs into hard regs for insns that require hard regs. + Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include +#include "config.h" +#include "rtl.h" +#include "obstack.h" +#include "insn-config.h" +#include "insn-flags.h" +#include "insn-codes.h" +#include "flags.h" +#include "expr.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "reload.h" +#include "recog.h" +#include "basic-block.h" +#include "output.h" + +/* This file contains the reload pass of the compiler, which is + run after register allocation has been done. It checks that + each insn is valid (operands required to be in registers really + are in registers of the proper class) and fixes up invalid ones + by copying values temporarily into registers for the insns + that need them. + + The results of register allocation are described by the vector + reg_renumber; the insns still contain pseudo regs, but reg_renumber + can be used to find which hard reg, if any, a pseudo reg is in. + + The technique we always use is to free up a few hard regs that are + called ``reload regs'', and for each place where a pseudo reg + must be in a hard reg, copy it temporarily into one of the reload regs. + + All the pseudos that were formerly allocated to the hard regs that + are now in use as reload regs must be ``spilled''. This means + that they go to other hard regs, or to stack slots if no other + available hard regs can be found. Spilling can invalidate more + insns, requiring additional need for reloads, so we must keep checking + until the process stabilizes. + + For machines with different classes of registers, we must keep track + of the register class needed for each reload, and make sure that + we allocate enough reload registers of each class. + + The file reload.c contains the code that checks one insn for + validity and reports the reloads that it needs. This file + is in charge of scanning the entire rtl code, accumulating the + reload needs, spilling, assigning reload registers to use for + fixing up each insn, and generating the new insns to copy values + into the reload registers. */ + + +#ifndef REGISTER_MOVE_COST +#define REGISTER_MOVE_COST(x, y) 2 +#endif + +#ifndef MEMORY_MOVE_COST +#define MEMORY_MOVE_COST(x) 4 +#endif + +/* During reload_as_needed, element N contains a REG rtx for the hard reg + into which reg N has been reloaded (perhaps for a previous insn). */ +static rtx *reg_last_reload_reg; + +/* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn + for an output reload that stores into reg N. */ +static char *reg_has_output_reload; + +/* Indicates which hard regs are reload-registers for an output reload + in the current insn. */ +static HARD_REG_SET reg_is_output_reload; + +/* Element N is the constant value to which pseudo reg N is equivalent, + or zero if pseudo reg N is not equivalent to a constant. + find_reloads looks at this in order to replace pseudo reg N + with the constant it stands for. */ +rtx *reg_equiv_constant; + +/* Element N is a memory location to which pseudo reg N is equivalent, + prior to any register elimination (such as frame pointer to stack + pointer). Depending on whether or not it is a valid address, this value + is transferred to either reg_equiv_address or reg_equiv_mem. */ +rtx *reg_equiv_memory_loc; + +/* Element N is the address of stack slot to which pseudo reg N is equivalent. + This is used when the address is not valid as a memory address + (because its displacement is too big for the machine.) */ +rtx *reg_equiv_address; + +/* Element N is the memory slot to which pseudo reg N is equivalent, + or zero if pseudo reg N is not equivalent to a memory slot. */ +rtx *reg_equiv_mem; + +/* Widest width in which each pseudo reg is referred to (via subreg). */ +static int *reg_max_ref_width; + +/* Element N is the insn that initialized reg N from its equivalent + constant or memory slot. */ +static rtx *reg_equiv_init; + +/* During reload_as_needed, element N contains the last pseudo regno + reloaded into the Nth reload register. This vector is in parallel + with spill_regs. If that pseudo reg occupied more than one register, + reg_reloaded_contents points to that pseudo for each spill register in + use; all of these must remain set for an inheritance to occur. */ +static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; + +/* During reload_as_needed, element N contains the insn for which + the Nth reload register was last used. This vector is in parallel + with spill_regs, and its contents are significant only when + reg_reloaded_contents is significant. */ +static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; + +/* Number of spill-regs so far; number of valid elements of spill_regs. */ +static int n_spills; + +/* In parallel with spill_regs, contains REG rtx's for those regs. + Holds the last rtx used for any given reg, or 0 if it has never + been used for spilling yet. This rtx is reused, provided it has + the proper mode. */ +static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; + +/* In parallel with spill_regs, contains nonzero for a spill reg + that was stored after the last time it was used. + The precise value is the insn generated to do the store. */ +static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; + +/* This table is the inverse mapping of spill_regs: + indexed by hard reg number, + it contains the position of that reg in spill_regs, + or -1 for something that is not in spill_regs. */ +static short spill_reg_order[FIRST_PSEUDO_REGISTER]; + +/* This reg set indicates registers that may not be used for retrying global + allocation. The registers that may not be used include all spill registers + and the frame pointer (if we are using one). */ +HARD_REG_SET forbidden_regs; + +/* This reg set indicates registers that are not good for spill registers. + They will not be used to complete groups of spill registers. This includes + all fixed registers, registers that may be eliminated, and, if + SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl. + + (spill_reg_order prevents these registers from being used to start a + group.) */ +static HARD_REG_SET bad_spill_regs; + +/* Describes order of use of registers for reloading + of spilled pseudo-registers. `spills' is the number of + elements that are actually valid; new ones are added at the end. */ +static short spill_regs[FIRST_PSEUDO_REGISTER]; + +/* Describes order of preference for putting regs into spill_regs. + Contains the numbers of all the hard regs, in order most preferred first. + This order is different for each function. + It is set up by order_regs_for_reload. + Empty elements at the end contain -1. */ +static short potential_reload_regs[FIRST_PSEUDO_REGISTER]; + +/* 1 for a hard register that appears explicitly in the rtl + (for example, function value registers, special registers + used by insns, structure value pointer registers). */ +static char regs_explicitly_used[FIRST_PSEUDO_REGISTER]; + +/* Indicates if a register was counted against the need for + groups. 0 means it can count against max_nongroup instead. */ +static HARD_REG_SET counted_for_groups; + +/* Indicates if a register was counted against the need for + non-groups. 0 means it can become part of a new group. + During choose_reload_regs, 1 here means don't use this reg + as part of a group, even if it seems to be otherwise ok. */ +static HARD_REG_SET counted_for_nongroups; + +/* Indexed by pseudo reg number N, + says may not delete stores into the real (memory) home of pseudo N. + This is set if we already substituted a memory equivalent in some uses, + which happens when we have to eliminate the fp from it. */ +static char *cannot_omit_stores; + +/* Nonzero if indirect addressing is supported on the machine; this means + that spilling (REG n) does not require reloading it into a register in + order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The + value indicates the level of indirect addressing supported, e.g., two + means that (MEM (MEM (REG n))) is also valid if (REG n) does not get + a hard register. */ + +static char spill_indirect_levels; + +/* Nonzero if indirect addressing is supported when the innermost MEM is + of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to + which these are valid is the same as spill_indirect_levels, above. */ + +char indirect_symref_ok; + +/* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ + +char double_reg_address_ok; + +/* Record the stack slot for each spilled hard register. */ + +static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; + +/* Width allocated so far for that stack slot. */ + +static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; + +/* Indexed by register class and basic block number, nonzero if there is + any need for a spill register of that class in that basic block. + The pointer is 0 if we did stupid allocation and don't know + the structure of basic blocks. */ + +char *basic_block_needs[N_REG_CLASSES]; + +/* First uid used by insns created by reload in this function. + Used in find_equiv_reg. */ +int reload_first_uid; + +/* Flag set by local-alloc or global-alloc if anything is live in + a call-clobbered reg across calls. */ + +int caller_save_needed; + +/* Set to 1 while reload_as_needed is operating. + Required by some machines to handle any generated moves differently. */ + +int reload_in_progress = 0; + +/* These arrays record the insn_code of insns that may be needed to + perform input and output reloads of special objects. They provide a + place to pass a scratch register. */ + +enum insn_code reload_in_optab[NUM_MACHINE_MODES]; +enum insn_code reload_out_optab[NUM_MACHINE_MODES]; + +/* This obstack is used for allocation of rtl during register elimination. + The allocated storage can be freed once find_reloads has processed the + insn. */ + +struct obstack reload_obstack; +char *reload_firstobj; + +#define obstack_chunk_alloc xmalloc +#define obstack_chunk_free free + +/* List of labels that must never be deleted. */ +extern rtx forced_labels; + +/* This structure is used to record information about register eliminations. + Each array entry describes one possible way of eliminating a register + in favor of another. If there is more than one way of eliminating a + particular register, the most preferred should be specified first. */ + +static struct elim_table +{ + int from; /* Register number to be eliminated. */ + int to; /* Register number used as replacement. */ + int initial_offset; /* Initial difference between values. */ + int can_eliminate; /* Non-zero if this elimination can be done. */ + int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over + insns made by reload. */ + int offset; /* Current offset between the two regs. */ + int max_offset; /* Maximum offset between the two regs. */ + int previous_offset; /* Offset at end of previous insn. */ + int ref_outside_mem; /* "to" has been referenced outside a MEM. */ + rtx from_rtx; /* REG rtx for the register to be eliminated. + We cannot simply compare the number since + we might then spuriously replace a hard + register corresponding to a pseudo + assigned to the reg to be eliminated. */ + rtx to_rtx; /* REG rtx for the replacement. */ +} reg_eliminate[] = + +/* If a set of eliminable registers was specified, define the table from it. + Otherwise, default to the normal case of the frame pointer being + replaced by the stack pointer. */ + +#ifdef ELIMINABLE_REGS + ELIMINABLE_REGS; +#else + {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; +#endif + +#define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0]) + +/* Record the number of pending eliminations that have an offset not equal + to their initial offset. If non-zero, we use a new copy of each + replacement result in any insns encountered. */ +static int num_not_at_initial_offset; + +/* Count the number of registers that we may be able to eliminate. */ +static int num_eliminable; + +/* For each label, we record the offset of each elimination. If we reach + a label by more than one path and an offset differs, we cannot do the + elimination. This information is indexed by the number of the label. + The first table is an array of flags that records whether we have yet + encountered a label and the second table is an array of arrays, one + entry in the latter array for each elimination. */ + +static char *offsets_known_at; +static int (*offsets_at)[NUM_ELIMINABLE_REGS]; + +/* Number of labels in the current function. */ + +static int num_labels; + +struct hard_reg_n_uses { int regno; int uses; }; + +static int possible_group_p PROTO((int, int *)); +static void count_possible_groups PROTO((int *, enum machine_mode *, + int *)); +static int modes_equiv_for_class_p PROTO((enum machine_mode, + enum machine_mode, + enum reg_class)); +static void spill_failure PROTO((rtx)); +static int new_spill_reg PROTO((int, int, int *, int *, int, + FILE *)); +static void delete_dead_insn PROTO((rtx)); +static void alter_reg PROTO((int, int)); +static void set_label_offsets PROTO((rtx, rtx, int)); +static int eliminate_regs_in_insn PROTO((rtx, int)); +static void mark_not_eliminable PROTO((rtx, rtx)); +static int spill_hard_reg PROTO((int, int, FILE *, int)); +static void scan_paradoxical_subregs PROTO((rtx)); +static int hard_reg_use_compare PROTO((struct hard_reg_n_uses *, + struct hard_reg_n_uses *)); +static void order_regs_for_reload PROTO((void)); +static void reload_as_needed PROTO((rtx, int)); +static void forget_old_reloads_1 PROTO((rtx, rtx)); +static int reload_reg_class_lower PROTO((short *, short *)); +static void mark_reload_reg_in_use PROTO((int, int, enum reload_type, + enum machine_mode)); +static void clear_reload_reg_in_use PROTO((int, int, enum reload_type, + enum machine_mode)); +static int reload_reg_free_p PROTO((int, int, enum reload_type)); +static int reload_reg_free_before_p PROTO((int, int, enum reload_type)); +static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type)); +static int allocate_reload_reg PROTO((int, rtx, int, int)); +static void choose_reload_regs PROTO((rtx, rtx)); +static void merge_assigned_reloads PROTO((rtx)); +static void emit_reload_insns PROTO((rtx)); +static void delete_output_reload PROTO((rtx, int, rtx)); +static void inc_for_reload PROTO((rtx, rtx, int)); +static int constraint_accepts_reg_p PROTO((char *, rtx)); +static int count_occurrences PROTO((rtx, rtx)); + +/* Initialize the reload pass once per compilation. */ + +void +init_reload () +{ + register int i; + + /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. + Set spill_indirect_levels to the number of levels such addressing is + permitted, zero if it is not permitted at all. */ + + register rtx tem + = gen_rtx (MEM, Pmode, + gen_rtx (PLUS, Pmode, + gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1), + GEN_INT (4))); + spill_indirect_levels = 0; + + while (memory_address_p (QImode, tem)) + { + spill_indirect_levels++; + tem = gen_rtx (MEM, Pmode, tem); + } + + /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ + + tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo")); + indirect_symref_ok = memory_address_p (QImode, tem); + + /* See if reg+reg is a valid (and offsettable) address. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + tem = gen_rtx (PLUS, Pmode, + gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM), + gen_rtx (REG, Pmode, i)); + /* This way, we make sure that reg+reg is an offsettable address. */ + tem = plus_constant (tem, 4); + + if (memory_address_p (QImode, tem)) + { + double_reg_address_ok = 1; + break; + } + } + + /* Initialize obstack for our rtl allocation. */ + gcc_obstack_init (&reload_obstack); + reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); +} + +/* Main entry point for the reload pass. + + FIRST is the first insn of the function being compiled. + + GLOBAL nonzero means we were called from global_alloc + and should attempt to reallocate any pseudoregs that we + displace from hard regs we will use for reloads. + If GLOBAL is zero, we do not have enough information to do that, + so any pseudo reg that is spilled must go to the stack. + + DUMPFILE is the global-reg debugging dump file stream, or 0. + If it is nonzero, messages are written to it to describe + which registers are seized as reload regs, which pseudo regs + are spilled from them, and where the pseudo regs are reallocated to. + + Return value is nonzero if reload failed + and we must not do any more for this function. */ + +int +reload (first, global, dumpfile) + rtx first; + int global; + FILE *dumpfile; +{ + register int class; + register int i, j; + register rtx insn; + register struct elim_table *ep; + + int something_changed; + int something_needs_reloads; + int something_needs_elimination; + int new_basic_block_needs; + enum reg_class caller_save_spill_class = NO_REGS; + int caller_save_group_size = 1; + + /* Nonzero means we couldn't get enough spill regs. */ + int failure = 0; + + /* The basic block number currently being processed for INSN. */ + int this_block; + + /* Make sure even insns with volatile mem refs are recognizable. */ + init_recog (); + + /* Enable find_equiv_reg to distinguish insns made by reload. */ + reload_first_uid = get_max_uid (); + + for (i = 0; i < N_REG_CLASSES; i++) + basic_block_needs[i] = 0; + +#ifdef SECONDARY_MEMORY_NEEDED + /* Initialize the secondary memory table. */ + clear_secondary_mem (); +#endif + + /* Remember which hard regs appear explicitly + before we merge into `regs_ever_live' the ones in which + pseudo regs have been allocated. */ + bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live); + + /* We don't have a stack slot for any spill reg yet. */ + bzero (spill_stack_slot, sizeof spill_stack_slot); + bzero (spill_stack_slot_width, sizeof spill_stack_slot_width); + + /* Initialize the save area information for caller-save, in case some + are needed. */ + init_save_areas (); + + /* Compute which hard registers are now in use + as homes for pseudo registers. + This is done here rather than (eg) in global_alloc + because this point is reached even if not optimizing. */ + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + mark_home_live (i); + + /* Make sure that the last insn in the chain + is not something that needs reloading. */ + emit_note (NULL_PTR, NOTE_INSN_DELETED); + + /* Find all the pseudo registers that didn't get hard regs + but do have known equivalent constants or memory slots. + These include parameters (known equivalent to parameter slots) + and cse'd or loop-moved constant memory addresses. + + Record constant equivalents in reg_equiv_constant + so they will be substituted by find_reloads. + Record memory equivalents in reg_mem_equiv so they can + be substituted eventually by altering the REG-rtx's. */ + + reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx)); + bzero (reg_equiv_constant, max_regno * sizeof (rtx)); + reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx)); + bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx)); + reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx)); + bzero (reg_equiv_mem, max_regno * sizeof (rtx)); + reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx)); + bzero (reg_equiv_init, max_regno * sizeof (rtx)); + reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx)); + bzero (reg_equiv_address, max_regno * sizeof (rtx)); + reg_max_ref_width = (int *) alloca (max_regno * sizeof (int)); + bzero (reg_max_ref_width, max_regno * sizeof (int)); + cannot_omit_stores = (char *) alloca (max_regno); + bzero (cannot_omit_stores, max_regno); + + /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. + Also find all paradoxical subregs + and find largest such for each pseudo. */ + + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + rtx set = single_set (insn); + + if (set != 0 && GET_CODE (SET_DEST (set)) == REG) + { + rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); + if (note +#ifdef LEGITIMATE_PIC_OPERAND_P + && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic + || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))) +#endif + ) + { + rtx x = XEXP (note, 0); + i = REGNO (SET_DEST (set)); + if (i > LAST_VIRTUAL_REGISTER) + { + if (GET_CODE (x) == MEM) + reg_equiv_memory_loc[i] = x; + else if (CONSTANT_P (x)) + { + if (LEGITIMATE_CONSTANT_P (x)) + reg_equiv_constant[i] = x; + else + reg_equiv_memory_loc[i] + = force_const_mem (GET_MODE (SET_DEST (set)), x); + } + else + continue; + + /* If this register is being made equivalent to a MEM + and the MEM is not SET_SRC, the equivalencing insn + is one with the MEM as a SET_DEST and it occurs later. + So don't mark this insn now. */ + if (GET_CODE (x) != MEM + || rtx_equal_p (SET_SRC (set), x)) + reg_equiv_init[i] = insn; + } + } + } + + /* If this insn is setting a MEM from a register equivalent to it, + this is the equivalencing insn. */ + else if (set && GET_CODE (SET_DEST (set)) == MEM + && GET_CODE (SET_SRC (set)) == REG + && reg_equiv_memory_loc[REGNO (SET_SRC (set))] + && rtx_equal_p (SET_DEST (set), + reg_equiv_memory_loc[REGNO (SET_SRC (set))])) + reg_equiv_init[REGNO (SET_SRC (set))] = insn; + + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + scan_paradoxical_subregs (PATTERN (insn)); + } + + /* Does this function require a frame pointer? */ + + frame_pointer_needed = (! flag_omit_frame_pointer +#ifdef EXIT_IGNORE_STACK + /* ?? If EXIT_IGNORE_STACK is set, we will not save + and restore sp for alloca. So we can't eliminate + the frame pointer in that case. At some point, + we should improve this by emitting the + sp-adjusting insns for this case. */ + || (current_function_calls_alloca + && EXIT_IGNORE_STACK) +#endif + || FRAME_POINTER_REQUIRED); + + num_eliminable = 0; + + /* Initialize the table of registers to eliminate. The way we do this + depends on how the eliminable registers were defined. */ +#ifdef ELIMINABLE_REGS + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + { + ep->can_eliminate = ep->can_eliminate_previous + = (CAN_ELIMINATE (ep->from, ep->to) + && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed)); + } +#else + reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous + = ! frame_pointer_needed; +#endif + + /* Count the number of eliminable registers and build the FROM and TO + REG rtx's. Note that code in gen_rtx will cause, e.g., + gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. + We depend on this. */ + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + { + num_eliminable += ep->can_eliminate; + ep->from_rtx = gen_rtx (REG, Pmode, ep->from); + ep->to_rtx = gen_rtx (REG, Pmode, ep->to); + } + + num_labels = max_label_num () - get_first_label_num (); + + /* Allocate the tables used to store offset information at labels. */ + offsets_known_at = (char *) alloca (num_labels); + offsets_at + = (int (*)[NUM_ELIMINABLE_REGS]) + alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); + + offsets_known_at -= get_first_label_num (); + offsets_at -= get_first_label_num (); + + /* Alter each pseudo-reg rtx to contain its hard reg number. + Assign stack slots to the pseudos that lack hard regs or equivalents. + Do not touch virtual registers. */ + + for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) + alter_reg (i, -1); + + /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here + because the stack size may be a part of the offset computation for + register elimination. */ + assign_stack_local (BLKmode, 0, 0); + + /* If we have some registers we think can be eliminated, scan all insns to + see if there is an insn that sets one of these registers to something + other than itself plus a constant. If so, the register cannot be + eliminated. Doing this scan here eliminates an extra pass through the + main reload loop in the most common case where register elimination + cannot be done. */ + for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN + || GET_CODE (insn) == CALL_INSN) + note_stores (PATTERN (insn), mark_not_eliminable); + +#ifndef REGISTER_CONSTRAINTS + /* If all the pseudo regs have hard regs, + except for those that are never referenced, + we know that no reloads are needed. */ + /* But that is not true if there are register constraints, since + in that case some pseudos might be in the wrong kind of hard reg. */ + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (reg_renumber[i] == -1 && reg_n_refs[i] != 0) + break; + + if (i == max_regno && num_eliminable == 0 && ! caller_save_needed) + return; +#endif + + /* Compute the order of preference for hard registers to spill. + Store them by decreasing preference in potential_reload_regs. */ + + order_regs_for_reload (); + + /* So far, no hard regs have been spilled. */ + n_spills = 0; + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + spill_reg_order[i] = -1; + + /* On most machines, we can't use any register explicitly used in the + rtl as a spill register. But on some, we have to. Those will have + taken care to keep the life of hard regs as short as possible. */ + +#ifdef SMALL_REGISTER_CLASSES + CLEAR_HARD_REG_SET (forbidden_regs); +#else + COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs); +#endif + + /* Spill any hard regs that we know we can't eliminate. */ + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + if (! ep->can_eliminate) + { + spill_hard_reg (ep->from, global, dumpfile, 1); + regs_ever_live[ep->from] = 1; + } + + if (global) + for (i = 0; i < N_REG_CLASSES; i++) + { + basic_block_needs[i] = (char *)alloca (n_basic_blocks); + bzero (basic_block_needs[i], n_basic_blocks); + } + + /* From now on, we need to emit any moves without making new pseudos. */ + reload_in_progress = 1; + + /* This loop scans the entire function each go-round + and repeats until one repetition spills no additional hard regs. */ + + /* This flag is set when a pseudo reg is spilled, + to require another pass. Note that getting an additional reload + reg does not necessarily imply any pseudo reg was spilled; + sometimes we find a reload reg that no pseudo reg was allocated in. */ + something_changed = 1; + /* This flag is set if there are any insns that require reloading. */ + something_needs_reloads = 0; + /* This flag is set if there are any insns that require register + eliminations. */ + something_needs_elimination = 0; + while (something_changed) + { + rtx after_call = 0; + + /* For each class, number of reload regs needed in that class. + This is the maximum over all insns of the needs in that class + of the individual insn. */ + int max_needs[N_REG_CLASSES]; + /* For each class, size of group of consecutive regs + that is needed for the reloads of this class. */ + int group_size[N_REG_CLASSES]; + /* For each class, max number of consecutive groups needed. + (Each group contains group_size[CLASS] consecutive registers.) */ + int max_groups[N_REG_CLASSES]; + /* For each class, max number needed of regs that don't belong + to any of the groups. */ + int max_nongroups[N_REG_CLASSES]; + /* For each class, the machine mode which requires consecutive + groups of regs of that class. + If two different modes ever require groups of one class, + they must be the same size and equally restrictive for that class, + otherwise we can't handle the complexity. */ + enum machine_mode group_mode[N_REG_CLASSES]; + /* Record the insn where each maximum need is first found. */ + rtx max_needs_insn[N_REG_CLASSES]; + rtx max_groups_insn[N_REG_CLASSES]; + rtx max_nongroups_insn[N_REG_CLASSES]; + rtx x; + int starting_frame_size = get_frame_size (); + static char *reg_class_names[] = REG_CLASS_NAMES; + + something_changed = 0; + bzero (max_needs, sizeof max_needs); + bzero (max_groups, sizeof max_groups); + bzero (max_nongroups, sizeof max_nongroups); + bzero (max_needs_insn, sizeof max_needs_insn); + bzero (max_groups_insn, sizeof max_groups_insn); + bzero (max_nongroups_insn, sizeof max_nongroups_insn); + bzero (group_size, sizeof group_size); + for (i = 0; i < N_REG_CLASSES; i++) + group_mode[i] = VOIDmode; + + /* Keep track of which basic blocks are needing the reloads. */ + this_block = 0; + + /* Remember whether any element of basic_block_needs + changes from 0 to 1 in this pass. */ + new_basic_block_needs = 0; + + /* Reset all offsets on eliminable registers to their initial values. */ +#ifdef ELIMINABLE_REGS + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + { + INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); + ep->previous_offset = ep->offset + = ep->max_offset = ep->initial_offset; + } +#else +#ifdef INITIAL_FRAME_POINTER_OFFSET + INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset); +#else + if (!FRAME_POINTER_REQUIRED) + abort (); + reg_eliminate[0].initial_offset = 0; +#endif + reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset + = reg_eliminate[0].offset = reg_eliminate[0].initial_offset; +#endif + + num_not_at_initial_offset = 0; + + bzero (&offsets_known_at[get_first_label_num ()], num_labels); + + /* Set a known offset for each forced label to be at the initial offset + of each elimination. We do this because we assume that all + computed jumps occur from a location where each elimination is + at its initial offset. */ + + for (x = forced_labels; x; x = XEXP (x, 1)) + if (XEXP (x, 0)) + set_label_offsets (XEXP (x, 0), NULL_RTX, 1); + + /* For each pseudo register that has an equivalent location defined, + try to eliminate any eliminable registers (such as the frame pointer) + assuming initial offsets for the replacement register, which + is the normal case. + + If the resulting location is directly addressable, substitute + the MEM we just got directly for the old REG. + + If it is not addressable but is a constant or the sum of a hard reg + and constant, it is probably not addressable because the constant is + out of range, in that case record the address; we will generate + hairy code to compute the address in a register each time it is + needed. + + If the location is not addressable, but does not have one of the + above forms, assign a stack slot. We have to do this to avoid the + potential of producing lots of reloads if, e.g., a location involves + a pseudo that didn't get a hard register and has an equivalent memory + location that also involves a pseudo that didn't get a hard register. + + Perhaps at some point we will improve reload_when_needed handling + so this problem goes away. But that's very hairy. */ + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) + { + rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); + + if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), + XEXP (x, 0))) + reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; + else if (CONSTANT_P (XEXP (x, 0)) + || (GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG + && (REGNO (XEXP (XEXP (x, 0), 0)) + < FIRST_PSEUDO_REGISTER) + && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) + reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; + else + { + /* Make a new stack slot. Then indicate that something + changed so we go back and recompute offsets for + eliminable registers because the allocation of memory + below might change some offset. reg_equiv_{mem,address} + will be set up for this pseudo on the next pass around + the loop. */ + reg_equiv_memory_loc[i] = 0; + reg_equiv_init[i] = 0; + alter_reg (i, -1); + something_changed = 1; + } + } + + /* If we allocated another pseudo to the stack, redo elimination + bookkeeping. */ + if (something_changed) + continue; + + /* If caller-saves needs a group, initialize the group to include + the size and mode required for caller-saves. */ + + if (caller_save_group_size > 1) + { + group_mode[(int) caller_save_spill_class] = Pmode; + group_size[(int) caller_save_spill_class] = caller_save_group_size; + } + + /* Compute the most additional registers needed by any instruction. + Collect information separately for each class of regs. */ + + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + if (global && this_block + 1 < n_basic_blocks + && insn == basic_block_head[this_block+1]) + ++this_block; + + /* If this is a label, a JUMP_INSN, or has REG_NOTES (which + might include REG_LABEL), we need to see what effects this + has on the known offsets at labels. */ + + if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN + || (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && REG_NOTES (insn) != 0)) + set_label_offsets (insn, insn, 0); + + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + /* Nonzero means don't use a reload reg that overlaps + the place where a function value can be returned. */ + rtx avoid_return_reg = 0; + + rtx old_body = PATTERN (insn); + int old_code = INSN_CODE (insn); + rtx old_notes = REG_NOTES (insn); + int did_elimination = 0; + int max_total_input_groups = 0, max_total_output_groups = 0; + + /* To compute the number of reload registers of each class + needed for an insn, we must similate what choose_reload_regs + can do. We do this by splitting an insn into an "input" and + an "output" part. RELOAD_OTHER reloads are used in both. + The input part uses those reloads, RELOAD_FOR_INPUT reloads, + which must be live over the entire input section of reloads, + and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and + RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the + inputs. + + The registers needed for output are RELOAD_OTHER and + RELOAD_FOR_OUTPUT, which are live for the entire output + portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS + reloads for each operand. + + The total number of registers needed is the maximum of the + inputs and outputs. */ + + /* These just count RELOAD_OTHER. */ + int insn_needs[N_REG_CLASSES]; + int insn_groups[N_REG_CLASSES]; + int insn_total_groups = 0; + + /* Count RELOAD_FOR_INPUT reloads. */ + int insn_needs_for_inputs[N_REG_CLASSES]; + int insn_groups_for_inputs[N_REG_CLASSES]; + int insn_total_groups_for_inputs = 0; + + /* Count RELOAD_FOR_OUTPUT reloads. */ + int insn_needs_for_outputs[N_REG_CLASSES]; + int insn_groups_for_outputs[N_REG_CLASSES]; + int insn_total_groups_for_outputs = 0; + + /* Count RELOAD_FOR_INSN reloads. */ + int insn_needs_for_insn[N_REG_CLASSES]; + int insn_groups_for_insn[N_REG_CLASSES]; + int insn_total_groups_for_insn = 0; + + /* Count RELOAD_FOR_OTHER_ADDRESS reloads. */ + int insn_needs_for_other_addr[N_REG_CLASSES]; + int insn_groups_for_other_addr[N_REG_CLASSES]; + int insn_total_groups_for_other_addr = 0; + + /* Count RELOAD_FOR_INPUT_ADDRESS reloads. */ + int insn_needs_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES]; + int insn_groups_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES]; + int insn_total_groups_for_in_addr[MAX_RECOG_OPERANDS]; + + /* Count RELOAD_FOR_OUTPUT_ADDRESS reloads. */ + int insn_needs_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES]; + int insn_groups_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES]; + int insn_total_groups_for_out_addr[MAX_RECOG_OPERANDS]; + + /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */ + int insn_needs_for_op_addr[N_REG_CLASSES]; + int insn_groups_for_op_addr[N_REG_CLASSES]; + int insn_total_groups_for_op_addr = 0; + +#if 0 /* This wouldn't work nowadays, since optimize_bit_field + looks for non-strict memory addresses. */ + /* Optimization: a bit-field instruction whose field + happens to be a byte or halfword in memory + can be changed to a move instruction. */ + + if (GET_CODE (PATTERN (insn)) == SET) + { + rtx dest = SET_DEST (PATTERN (insn)); + rtx src = SET_SRC (PATTERN (insn)); + + if (GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == SIGN_EXTRACT) + optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem); + if (GET_CODE (src) == ZERO_EXTRACT + || GET_CODE (src) == SIGN_EXTRACT) + optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem); + } +#endif + + /* If needed, eliminate any eliminable registers. */ + if (num_eliminable) + did_elimination = eliminate_regs_in_insn (insn, 0); + +#ifdef SMALL_REGISTER_CLASSES + /* Set avoid_return_reg if this is an insn + that might use the value of a function call. */ + if (GET_CODE (insn) == CALL_INSN) + { + if (GET_CODE (PATTERN (insn)) == SET) + after_call = SET_DEST (PATTERN (insn)); + else if (GET_CODE (PATTERN (insn)) == PARALLEL + && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) + after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); + else + after_call = 0; + } + else if (after_call != 0 + && !(GET_CODE (PATTERN (insn)) == SET + && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)) + { + if (reg_mentioned_p (after_call, PATTERN (insn))) + avoid_return_reg = after_call; + after_call = 0; + } +#endif /* SMALL_REGISTER_CLASSES */ + + /* Analyze the instruction. */ + find_reloads (insn, 0, spill_indirect_levels, global, + spill_reg_order); + + /* Remember for later shortcuts which insns had any reloads or + register eliminations. + + One might think that it would be worthwhile to mark insns + that need register replacements but not reloads, but this is + not safe because find_reloads may do some manipulation of + the insn (such as swapping commutative operands), which would + be lost when we restore the old pattern after register + replacement. So the actions of find_reloads must be redone in + subsequent passes or in reload_as_needed. + + However, it is safe to mark insns that need reloads + but not register replacement. */ + + PUT_MODE (insn, (did_elimination ? QImode + : n_reloads ? HImode + : GET_MODE (insn) == DImode ? DImode + : VOIDmode)); + + /* Discard any register replacements done. */ + if (did_elimination) + { + obstack_free (&reload_obstack, reload_firstobj); + PATTERN (insn) = old_body; + INSN_CODE (insn) = old_code; + REG_NOTES (insn) = old_notes; + something_needs_elimination = 1; + } + + /* If this insn has no reloads, we need not do anything except + in the case of a CALL_INSN when we have caller-saves and + caller-save needs reloads. */ + + if (n_reloads == 0 + && ! (GET_CODE (insn) == CALL_INSN + && caller_save_spill_class != NO_REGS)) + continue; + + something_needs_reloads = 1; + + for (i = 0; i < N_REG_CLASSES; i++) + { + insn_needs[i] = 0, insn_groups[i] = 0; + insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0; + insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0; + insn_needs_for_insn[i] = 0, insn_groups_for_insn[i] = 0; + insn_needs_for_op_addr[i] = 0, insn_groups_for_op_addr[i] = 0; + insn_needs_for_other_addr[i] = 0; + insn_groups_for_other_addr[i] = 0; + } + + for (i = 0; i < reload_n_operands; i++) + { + insn_total_groups_for_in_addr[i] = 0; + insn_total_groups_for_out_addr[i] = 0; + + for (j = 0; j < N_REG_CLASSES; j++) + { + insn_needs_for_in_addr[i][j] = 0; + insn_needs_for_out_addr[i][j] = 0; + insn_groups_for_in_addr[i][j] = 0; + insn_groups_for_out_addr[i][j] = 0; + } + } + + /* Count each reload once in every class + containing the reload's own class. */ + + for (i = 0; i < n_reloads; i++) + { + register enum reg_class *p; + enum reg_class class = reload_reg_class[i]; + int size; + enum machine_mode mode; + int *this_groups; + int *this_needs; + int *this_total_groups; + + /* Don't count the dummy reloads, for which one of the + regs mentioned in the insn can be used for reloading. + Don't count optional reloads. + Don't count reloads that got combined with others. */ + if (reload_reg_rtx[i] != 0 + || reload_optional[i] != 0 + || (reload_out[i] == 0 && reload_in[i] == 0 + && ! reload_secondary_p[i])) + continue; + + /* Show that a reload register of this class is needed + in this basic block. We do not use insn_needs and + insn_groups because they are overly conservative for + this purpose. */ + if (global && ! basic_block_needs[(int) class][this_block]) + { + basic_block_needs[(int) class][this_block] = 1; + new_basic_block_needs = 1; + } + + /* Decide which time-of-use to count this reload for. */ + switch (reload_when_needed[i]) + { + case RELOAD_OTHER: + this_needs = insn_needs; + this_groups = insn_groups; + this_total_groups = &insn_total_groups; + break; + + case RELOAD_FOR_INPUT: + this_needs = insn_needs_for_inputs; + this_groups = insn_groups_for_inputs; + this_total_groups = &insn_total_groups_for_inputs; + break; + + case RELOAD_FOR_OUTPUT: + this_needs = insn_needs_for_outputs; + this_groups = insn_groups_for_outputs; + this_total_groups = &insn_total_groups_for_outputs; + break; + + case RELOAD_FOR_INSN: + this_needs = insn_needs_for_insn; + this_groups = insn_groups_for_outputs; + this_total_groups = &insn_total_groups_for_insn; + break; + + case RELOAD_FOR_OTHER_ADDRESS: + this_needs = insn_needs_for_other_addr; + this_groups = insn_groups_for_other_addr; + this_total_groups = &insn_total_groups_for_other_addr; + break; + + case RELOAD_FOR_INPUT_ADDRESS: + this_needs = insn_needs_for_in_addr[reload_opnum[i]]; + this_groups = insn_groups_for_in_addr[reload_opnum[i]]; + this_total_groups + = &insn_total_groups_for_in_addr[reload_opnum[i]]; + break; + + case RELOAD_FOR_OUTPUT_ADDRESS: + this_needs = insn_needs_for_out_addr[reload_opnum[i]]; + this_groups = insn_groups_for_out_addr[reload_opnum[i]]; + this_total_groups + = &insn_total_groups_for_out_addr[reload_opnum[i]]; + break; + + case RELOAD_FOR_OPERAND_ADDRESS: + this_needs = insn_needs_for_op_addr; + this_groups = insn_groups_for_op_addr; + this_total_groups = &insn_total_groups_for_op_addr; + break; + } + + mode = reload_inmode[i]; + if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode)) + mode = reload_outmode[i]; + size = CLASS_MAX_NREGS (class, mode); + if (size > 1) + { + enum machine_mode other_mode, allocate_mode; + + /* Count number of groups needed separately from + number of individual regs needed. */ + this_groups[(int) class]++; + p = reg_class_superclasses[(int) class]; + while (*p != LIM_REG_CLASSES) + this_groups[(int) *p++]++; + (*this_total_groups)++; + + /* Record size and mode of a group of this class. */ + /* If more than one size group is needed, + make all groups the largest needed size. */ + if (group_size[(int) class] < size) + { + other_mode = group_mode[(int) class]; + allocate_mode = mode; + + group_size[(int) class] = size; + group_mode[(int) class] = mode; + } + else + { + other_mode = mode; + allocate_mode = group_mode[(int) class]; + } + + /* Crash if two dissimilar machine modes both need + groups of consecutive regs of the same class. */ + + if (other_mode != VOIDmode + && other_mode != allocate_mode + && ! modes_equiv_for_class_p (allocate_mode, + other_mode, + class)) + abort (); + } + else if (size == 1) + { + this_needs[(int) class] += 1; + p = reg_class_superclasses[(int) class]; + while (*p != LIM_REG_CLASSES) + this_needs[(int) *p++] += 1; + } + else + abort (); + } + + /* All reloads have been counted for this insn; + now merge the various times of use. + This sets insn_needs, etc., to the maximum total number + of registers needed at any point in this insn. */ + + for (i = 0; i < N_REG_CLASSES; i++) + { + int in_max, out_max; + + for (in_max = 0, out_max = 0, j = 0; + j < reload_n_operands; j++) + { + in_max = MAX (in_max, insn_needs_for_in_addr[j][i]); + out_max = MAX (out_max, insn_needs_for_out_addr[j][i]); + } + + /* RELOAD_FOR_INSN reloads conflict with inputs, outputs, + and operand addresses but not things used to reload them. + Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads don't + conflict with things needed to reload inputs or + outputs. */ + + in_max = MAX (in_max, insn_needs_for_op_addr[i]); + out_max = MAX (out_max, insn_needs_for_insn[i]); + + insn_needs_for_inputs[i] + = MAX (insn_needs_for_inputs[i] + + insn_needs_for_op_addr[i] + + insn_needs_for_insn[i], + in_max + insn_needs_for_inputs[i]); + + insn_needs_for_outputs[i] += out_max; + insn_needs[i] += MAX (MAX (insn_needs_for_inputs[i], + insn_needs_for_outputs[i]), + insn_needs_for_other_addr[i]); + + for (in_max = 0, out_max = 0, j = 0; + j < reload_n_operands; j++) + { + in_max = MAX (in_max, insn_groups_for_in_addr[j][i]); + out_max = MAX (out_max, insn_groups_for_out_addr[j][i]); + } + + in_max = MAX (in_max, insn_groups_for_op_addr[i]); + out_max = MAX (out_max, insn_groups_for_insn[i]); + + insn_groups_for_inputs[i] + = MAX (insn_groups_for_inputs[i] + + insn_groups_for_op_addr[i] + + insn_groups_for_insn[i], + in_max + insn_groups_for_inputs[i]); + + insn_groups_for_outputs[i] += out_max; + insn_groups[i] += MAX (MAX (insn_groups_for_inputs[i], + insn_groups_for_outputs[i]), + insn_groups_for_other_addr[i]); + } + + for (i = 0; i < reload_n_operands; i++) + { + max_total_input_groups + = MAX (max_total_input_groups, + insn_total_groups_for_in_addr[i]); + max_total_output_groups + = MAX (max_total_output_groups, + insn_total_groups_for_out_addr[i]); + } + + max_total_input_groups = MAX (max_total_input_groups, + insn_total_groups_for_op_addr); + max_total_output_groups = MAX (max_total_output_groups, + insn_total_groups_for_insn); + + insn_total_groups_for_inputs + = MAX (max_total_input_groups + insn_total_groups_for_op_addr + + insn_total_groups_for_insn, + max_total_input_groups + insn_total_groups_for_inputs); + + insn_total_groups_for_outputs += max_total_output_groups; + + insn_total_groups += MAX (MAX (insn_total_groups_for_outputs, + insn_total_groups_for_inputs), + insn_total_groups_for_other_addr); + + /* If this is a CALL_INSN and caller-saves will need + a spill register, act as if the spill register is + needed for this insn. However, the spill register + can be used by any reload of this insn, so we only + need do something if no need for that class has + been recorded. + + The assumption that every CALL_INSN will trigger a + caller-save is highly conservative, however, the number + of cases where caller-saves will need a spill register but + a block containing a CALL_INSN won't need a spill register + of that class should be quite rare. + + If a group is needed, the size and mode of the group will + have been set up at the beginning of this loop. */ + + if (GET_CODE (insn) == CALL_INSN + && caller_save_spill_class != NO_REGS) + { + int *caller_save_needs + = (caller_save_group_size > 1 ? insn_groups : insn_needs); + + if (caller_save_needs[(int) caller_save_spill_class] == 0) + { + register enum reg_class *p + = reg_class_superclasses[(int) caller_save_spill_class]; + + caller_save_needs[(int) caller_save_spill_class]++; + + while (*p != LIM_REG_CLASSES) + caller_save_needs[(int) *p++] += 1; + } + + if (caller_save_group_size > 1) + insn_total_groups = MAX (insn_total_groups, 1); + + + /* Show that this basic block will need a register of + this class. */ + + if (global + && ! (basic_block_needs[(int) caller_save_spill_class] + [this_block])) + { + basic_block_needs[(int) caller_save_spill_class] + [this_block] = 1; + new_basic_block_needs = 1; + } + } + +#ifdef SMALL_REGISTER_CLASSES + /* If this insn stores the value of a function call, + and that value is in a register that has been spilled, + and if the insn needs a reload in a class + that might use that register as the reload register, + then add add an extra need in that class. + This makes sure we have a register available that does + not overlap the return value. */ + if (avoid_return_reg) + { + int regno = REGNO (avoid_return_reg); + int nregs + = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); + int r; + int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES]; + + /* First compute the "basic needs", which counts a + need only in the smallest class in which it + is required. */ + + bcopy (insn_needs, basic_needs, sizeof basic_needs); + bcopy (insn_groups, basic_groups, sizeof basic_groups); + + for (i = 0; i < N_REG_CLASSES; i++) + { + enum reg_class *p; + + if (basic_needs[i] >= 0) + for (p = reg_class_superclasses[i]; + *p != LIM_REG_CLASSES; p++) + basic_needs[(int) *p] -= basic_needs[i]; + + if (basic_groups[i] >= 0) + for (p = reg_class_superclasses[i]; + *p != LIM_REG_CLASSES; p++) + basic_groups[(int) *p] -= basic_groups[i]; + } + + /* Now count extra regs if there might be a conflict with + the return value register. + + ??? This is not quite correct because we don't properly + handle the case of groups, but if we end up doing + something wrong, it either will end up not mattering or + we will abort elsewhere. */ + + for (r = regno; r < regno + nregs; r++) + if (spill_reg_order[r] >= 0) + for (i = 0; i < N_REG_CLASSES; i++) + if (TEST_HARD_REG_BIT (reg_class_contents[i], r)) + { + if (basic_needs[i] > 0 || basic_groups[i] > 0) + { + enum reg_class *p; + + insn_needs[i]++; + p = reg_class_superclasses[i]; + while (*p != LIM_REG_CLASSES) + insn_needs[(int) *p++]++; + } + } + } +#endif /* SMALL_REGISTER_CLASSES */ + + /* For each class, collect maximum need of any insn. */ + + for (i = 0; i < N_REG_CLASSES; i++) + { + if (max_needs[i] < insn_needs[i]) + { + max_needs[i] = insn_needs[i]; + max_needs_insn[i] = insn; + } + if (max_groups[i] < insn_groups[i]) + { + max_groups[i] = insn_groups[i]; + max_groups_insn[i] = insn; + } + if (insn_total_groups > 0) + if (max_nongroups[i] < insn_needs[i]) + { + max_nongroups[i] = insn_needs[i]; + max_nongroups_insn[i] = insn; + } + } + } + /* Note that there is a continue statement above. */ + } + + /* If we allocated any new memory locations, make another pass + since it might have changed elimination offsets. */ + if (starting_frame_size != get_frame_size ()) + something_changed = 1; + + if (dumpfile) + for (i = 0; i < N_REG_CLASSES; i++) + { + if (max_needs[i] > 0) + fprintf (dumpfile, + ";; Need %d reg%s of class %s (for insn %d).\n", + max_needs[i], max_needs[i] == 1 ? "" : "s", + reg_class_names[i], INSN_UID (max_needs_insn[i])); + if (max_nongroups[i] > 0) + fprintf (dumpfile, + ";; Need %d nongroup reg%s of class %s (for insn %d).\n", + max_nongroups[i], max_nongroups[i] == 1 ? "" : "s", + reg_class_names[i], INSN_UID (max_nongroups_insn[i])); + if (max_groups[i] > 0) + fprintf (dumpfile, + ";; Need %d group%s (%smode) of class %s (for insn %d).\n", + max_groups[i], max_groups[i] == 1 ? "" : "s", + mode_name[(int) group_mode[i]], + reg_class_names[i], INSN_UID (max_groups_insn[i])); + } + + /* If we have caller-saves, set up the save areas and see if caller-save + will need a spill register. */ + + if (caller_save_needed + && ! setup_save_areas (&something_changed) + && caller_save_spill_class == NO_REGS) + { + /* The class we will need depends on whether the machine + supports the sum of two registers for an address; see + find_address_reloads for details. */ + + caller_save_spill_class + = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS; + caller_save_group_size + = CLASS_MAX_NREGS (caller_save_spill_class, Pmode); + something_changed = 1; + } + + /* See if anything that happened changes which eliminations are valid. + For example, on the Sparc, whether or not the frame pointer can + be eliminated can depend on what registers have been used. We need + not check some conditions again (such as flag_omit_frame_pointer) + since they can't have changed. */ + + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) +#ifdef ELIMINABLE_REGS + || ! CAN_ELIMINATE (ep->from, ep->to) +#endif + ) + ep->can_eliminate = 0; + + /* Look for the case where we have discovered that we can't replace + register A with register B and that means that we will now be + trying to replace register A with register C. This means we can + no longer replace register C with register B and we need to disable + such an elimination, if it exists. This occurs often with A == ap, + B == sp, and C == fp. */ + + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + { + struct elim_table *op; + register int new_to = -1; + + if (! ep->can_eliminate && ep->can_eliminate_previous) + { + /* Find the current elimination for ep->from, if there is a + new one. */ + for (op = reg_eliminate; + op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) + if (op->from == ep->from && op->can_eliminate) + { + new_to = op->to; + break; + } + + /* See if there is an elimination of NEW_TO -> EP->TO. If so, + disable it. */ + for (op = reg_eliminate; + op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) + if (op->from == new_to && op->to == ep->to) + op->can_eliminate = 0; + } + } + + /* See if any registers that we thought we could eliminate the previous + time are no longer eliminable. If so, something has changed and we + must spill the register. Also, recompute the number of eliminable + registers and see if the frame pointer is needed; it is if there is + no elimination of the frame pointer that we can perform. */ + + frame_pointer_needed = 1; + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + { + if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM) + frame_pointer_needed = 0; + + if (! ep->can_eliminate && ep->can_eliminate_previous) + { + ep->can_eliminate_previous = 0; + spill_hard_reg (ep->from, global, dumpfile, 1); + regs_ever_live[ep->from] = 1; + something_changed = 1; + num_eliminable--; + } + } + + /* If all needs are met, we win. */ + + for (i = 0; i < N_REG_CLASSES; i++) + if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0) + break; + if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed) + break; + + /* Not all needs are met; must spill some hard regs. */ + + /* Put all registers spilled so far back in potential_reload_regs, but + put them at the front, since we've already spilled most of the + psuedos in them (we might have left some pseudos unspilled if they + were in a block that didn't need any spill registers of a conflicting + class. We used to try to mark off the need for those registers, + but doing so properly is very complex and reallocating them is the + simpler approach. First, "pack" potential_reload_regs by pushing + any nonnegative entries towards the end. That will leave room + for the registers we already spilled. + + Also, undo the marking of the spill registers from the last time + around in FORBIDDEN_REGS since we will be probably be allocating + them again below. + + ??? It is theoretically possible that we might end up not using one + of our previously-spilled registers in this allocation, even though + they are at the head of the list. It's not clear what to do about + this, but it was no better before, when we marked off the needs met + by the previously-spilled registers. With the current code, globals + can be allocated into these registers, but locals cannot. */ + + if (n_spills) + { + for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) + if (potential_reload_regs[i] != -1) + potential_reload_regs[j--] = potential_reload_regs[i]; + + for (i = 0; i < n_spills; i++) + { + potential_reload_regs[i] = spill_regs[i]; + spill_reg_order[spill_regs[i]] = -1; + CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]); + } + + n_spills = 0; + } + + /* Now find more reload regs to satisfy the remaining need + Do it by ascending class number, since otherwise a reg + might be spilled for a big class and might fail to count + for a smaller class even though it belongs to that class. + + Count spilled regs in `spills', and add entries to + `spill_regs' and `spill_reg_order'. + + ??? Note there is a problem here. + When there is a need for a group in a high-numbered class, + and also need for non-group regs that come from a lower class, + the non-group regs are chosen first. If there aren't many regs, + they might leave no room for a group. + + This was happening on the 386. To fix it, we added the code + that calls possible_group_p, so that the lower class won't + break up the last possible group. + + Really fixing the problem would require changes above + in counting the regs already spilled, and in choose_reload_regs. + It might be hard to avoid introducing bugs there. */ + + CLEAR_HARD_REG_SET (counted_for_groups); + CLEAR_HARD_REG_SET (counted_for_nongroups); + + for (class = 0; class < N_REG_CLASSES; class++) + { + /* First get the groups of registers. + If we got single registers first, we might fragment + possible groups. */ + while (max_groups[class] > 0) + { + /* If any single spilled regs happen to form groups, + count them now. Maybe we don't really need + to spill another group. */ + count_possible_groups (group_size, group_mode, max_groups); + + if (max_groups[class] <= 0) + break; + + /* Groups of size 2 (the only groups used on most machines) + are treated specially. */ + if (group_size[class] == 2) + { + /* First, look for a register that will complete a group. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + int other; + + j = potential_reload_regs[i]; + if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j) + && + ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0) + && TEST_HARD_REG_BIT (reg_class_contents[class], j) + && TEST_HARD_REG_BIT (reg_class_contents[class], other) + && HARD_REGNO_MODE_OK (other, group_mode[class]) + && ! TEST_HARD_REG_BIT (counted_for_nongroups, + other) + /* We don't want one part of another group. + We could get "two groups" that overlap! */ + && ! TEST_HARD_REG_BIT (counted_for_groups, other)) + || + (j < FIRST_PSEUDO_REGISTER - 1 + && (other = j + 1, spill_reg_order[other] >= 0) + && TEST_HARD_REG_BIT (reg_class_contents[class], j) + && TEST_HARD_REG_BIT (reg_class_contents[class], other) + && HARD_REGNO_MODE_OK (j, group_mode[class]) + && ! TEST_HARD_REG_BIT (counted_for_nongroups, + other) + && ! TEST_HARD_REG_BIT (counted_for_groups, + other)))) + { + register enum reg_class *p; + + /* We have found one that will complete a group, + so count off one group as provided. */ + max_groups[class]--; + p = reg_class_superclasses[class]; + while (*p != LIM_REG_CLASSES) + max_groups[(int) *p++]--; + + /* Indicate both these regs are part of a group. */ + SET_HARD_REG_BIT (counted_for_groups, j); + SET_HARD_REG_BIT (counted_for_groups, other); + break; + } + } + /* We can't complete a group, so start one. */ + if (i == FIRST_PSEUDO_REGISTER) + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + int k; + j = potential_reload_regs[i]; + /* Verify that J+1 is a potential reload reg. */ + for (k = 0; k < FIRST_PSEUDO_REGISTER; k++) + if (potential_reload_regs[k] == j + 1) + break; + if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER + && k < FIRST_PSEUDO_REGISTER + && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0 + && TEST_HARD_REG_BIT (reg_class_contents[class], j) + && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1) + && HARD_REGNO_MODE_OK (j, group_mode[class]) + && ! TEST_HARD_REG_BIT (counted_for_nongroups, + j + 1) + && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)) + break; + } + + /* I should be the index in potential_reload_regs + of the new reload reg we have found. */ + + if (i >= FIRST_PSEUDO_REGISTER) + { + /* There are no groups left to spill. */ + spill_failure (max_groups_insn[class]); + failure = 1; + goto failed; + } + else + something_changed + |= new_spill_reg (i, class, max_needs, NULL_PTR, + global, dumpfile); + } + else + { + /* For groups of more than 2 registers, + look for a sufficient sequence of unspilled registers, + and spill them all at once. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + int k; + + j = potential_reload_regs[i]; + if (j >= 0 + && j + group_size[class] <= FIRST_PSEUDO_REGISTER + && HARD_REGNO_MODE_OK (j, group_mode[class])) + { + /* Check each reg in the sequence. */ + for (k = 0; k < group_size[class]; k++) + if (! (spill_reg_order[j + k] < 0 + && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k) + && TEST_HARD_REG_BIT (reg_class_contents[class], j + k))) + break; + /* We got a full sequence, so spill them all. */ + if (k == group_size[class]) + { + register enum reg_class *p; + for (k = 0; k < group_size[class]; k++) + { + int idx; + SET_HARD_REG_BIT (counted_for_groups, j + k); + for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) + if (potential_reload_regs[idx] == j + k) + break; + something_changed + |= new_spill_reg (idx, class, + max_needs, NULL_PTR, + global, dumpfile); + } + + /* We have found one that will complete a group, + so count off one group as provided. */ + max_groups[class]--; + p = reg_class_superclasses[class]; + while (*p != LIM_REG_CLASSES) + max_groups[(int) *p++]--; + + break; + } + } + } + /* We couldn't find any registers for this reload. + Avoid going into an infinite loop. */ + if (i >= FIRST_PSEUDO_REGISTER) + { + /* There are no groups left. */ + spill_failure (max_groups_insn[class]); + failure = 1; + goto failed; + } + } + } + + /* Now similarly satisfy all need for single registers. */ + + while (max_needs[class] > 0 || max_nongroups[class] > 0) + { +#ifdef SMALL_REGISTER_CLASSES + /* This should be right for all machines, but only the 386 + is known to need it, so this conditional plays safe. + ??? For 2.5, try making this unconditional. */ + /* If we spilled enough regs, but they weren't counted + against the non-group need, see if we can count them now. + If so, we can avoid some actual spilling. */ + if (max_needs[class] <= 0 && max_nongroups[class] > 0) + for (i = 0; i < n_spills; i++) + if (TEST_HARD_REG_BIT (reg_class_contents[class], + spill_regs[i]) + && !TEST_HARD_REG_BIT (counted_for_groups, + spill_regs[i]) + && !TEST_HARD_REG_BIT (counted_for_nongroups, + spill_regs[i]) + && max_nongroups[class] > 0) + { + register enum reg_class *p; + + SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]); + max_nongroups[class]--; + p = reg_class_superclasses[class]; + while (*p != LIM_REG_CLASSES) + max_nongroups[(int) *p++]--; + } + if (max_needs[class] <= 0 && max_nongroups[class] <= 0) + break; +#endif + + /* Consider the potential reload regs that aren't + yet in use as reload regs, in order of preference. + Find the most preferred one that's in this class. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (potential_reload_regs[i] >= 0 + && TEST_HARD_REG_BIT (reg_class_contents[class], + potential_reload_regs[i]) + /* If this reg will not be available for groups, + pick one that does not foreclose possible groups. + This is a kludge, and not very general, + but it should be sufficient to make the 386 work, + and the problem should not occur on machines with + more registers. */ + && (max_nongroups[class] == 0 + || possible_group_p (potential_reload_regs[i], max_groups))) + break; + + /* If we couldn't get a register, try to get one even if we + might foreclose possible groups. This may cause problems + later, but that's better than aborting now, since it is + possible that we will, in fact, be able to form the needed + group even with this allocation. */ + + if (i >= FIRST_PSEUDO_REGISTER + && (asm_noperands (max_needs[class] > 0 + ? max_needs_insn[class] + : max_nongroups_insn[class]) + < 0)) + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (potential_reload_regs[i] >= 0 + && TEST_HARD_REG_BIT (reg_class_contents[class], + potential_reload_regs[i])) + break; + + /* I should be the index in potential_reload_regs + of the new reload reg we have found. */ + + if (i >= FIRST_PSEUDO_REGISTER) + { + /* There are no possible registers left to spill. */ + spill_failure (max_needs[class] > 0 ? max_needs_insn[class] + : max_nongroups_insn[class]); + failure = 1; + goto failed; + } + else + something_changed + |= new_spill_reg (i, class, max_needs, max_nongroups, + global, dumpfile); + } + } + } + + /* If global-alloc was run, notify it of any register eliminations we have + done. */ + if (global) + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + if (ep->can_eliminate) + mark_elimination (ep->from, ep->to); + + /* Insert code to save and restore call-clobbered hard regs + around calls. Tell if what mode to use so that we will process + those insns in reload_as_needed if we have to. */ + + if (caller_save_needed) + save_call_clobbered_regs (num_eliminable ? QImode + : caller_save_spill_class != NO_REGS ? HImode + : VOIDmode); + + /* If a pseudo has no hard reg, delete the insns that made the equivalence. + If that insn didn't set the register (i.e., it copied the register to + memory), just delete that insn instead of the equivalencing insn plus + anything now dead. If we call delete_dead_insn on that insn, we may + delete the insn that actually sets the register if the register die + there and that is incorrect. */ + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0 + && GET_CODE (reg_equiv_init[i]) != NOTE) + { + if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i]))) + delete_dead_insn (reg_equiv_init[i]); + else + { + PUT_CODE (reg_equiv_init[i], NOTE); + NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0; + NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED; + } + } + + /* Use the reload registers where necessary + by generating move instructions to move the must-be-register + values into or out of the reload registers. */ + + if (something_needs_reloads || something_needs_elimination + || (caller_save_needed && num_eliminable) + || caller_save_spill_class != NO_REGS) + reload_as_needed (first, global); + + /* If we were able to eliminate the frame pointer, show that it is no + longer live at the start of any basic block. If it ls live by + virtue of being in a pseudo, that pseudo will be marked live + and hence the frame pointer will be known to be live via that + pseudo. */ + + if (! frame_pointer_needed) + for (i = 0; i < n_basic_blocks; i++) + basic_block_live_at_start[i][FRAME_POINTER_REGNUM / REGSET_ELT_BITS] + &= ~ ((REGSET_ELT_TYPE) 1 << (FRAME_POINTER_REGNUM % REGSET_ELT_BITS)); + + /* Come here (with failure set nonzero) if we can't get enough spill regs + and we decide not to abort about it. */ + failed: + + reload_in_progress = 0; + + /* Now eliminate all pseudo regs by modifying them into + their equivalent memory references. + The REG-rtx's for the pseudos are modified in place, + so all insns that used to refer to them now refer to memory. + + For a reg that has a reg_equiv_address, all those insns + were changed by reloading so that no insns refer to it any longer; + but the DECL_RTL of a variable decl may refer to it, + and if so this causes the debugging info to mention the variable. */ + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + { + rtx addr = 0; + int in_struct = 0; + if (reg_equiv_mem[i]) + { + addr = XEXP (reg_equiv_mem[i], 0); + in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]); + } + if (reg_equiv_address[i]) + addr = reg_equiv_address[i]; + if (addr) + { + if (reg_renumber[i] < 0) + { + rtx reg = regno_reg_rtx[i]; + XEXP (reg, 0) = addr; + REG_USERVAR_P (reg) = 0; + MEM_IN_STRUCT_P (reg) = in_struct; + PUT_CODE (reg, MEM); + } + else if (reg_equiv_mem[i]) + XEXP (reg_equiv_mem[i], 0) = addr; + } + } + +#ifdef PRESERVE_DEATH_INFO_REGNO_P + /* Make a pass over all the insns and remove death notes for things that + are no longer registers or no longer die in the insn (e.g., an input + and output pseudo being tied). */ + + for (insn = first; insn; insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + rtx note, next; + + for (note = REG_NOTES (insn); note; note = next) + { + next = XEXP (note, 1); + if (REG_NOTE_KIND (note) == REG_DEAD + && (GET_CODE (XEXP (note, 0)) != REG + || reg_set_p (XEXP (note, 0), PATTERN (insn)))) + remove_note (insn, note); + } + } +#endif + + /* Indicate that we no longer have known memory locations or constants. */ + reg_equiv_constant = 0; + reg_equiv_memory_loc = 0; + + return failure; +} + +/* Nonzero if, after spilling reg REGNO for non-groups, + it will still be possible to find a group if we still need one. */ + +static int +possible_group_p (regno, max_groups) + int regno; + int *max_groups; +{ + int i; + int class = (int) NO_REGS; + + for (i = 0; i < (int) N_REG_CLASSES; i++) + if (max_groups[i] > 0) + { + class = i; + break; + } + + if (class == (int) NO_REGS) + return 1; + + /* Consider each pair of consecutive registers. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++) + { + /* Ignore pairs that include reg REGNO. */ + if (i == regno || i + 1 == regno) + continue; + + /* Ignore pairs that are outside the class that needs the group. + ??? Here we fail to handle the case where two different classes + independently need groups. But this never happens with our + current machine descriptions. */ + if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i) + && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1))) + continue; + + /* A pair of consecutive regs we can still spill does the trick. */ + if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0 + && ! TEST_HARD_REG_BIT (bad_spill_regs, i) + && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)) + return 1; + + /* A pair of one already spilled and one we can spill does it + provided the one already spilled is not otherwise reserved. */ + if (spill_reg_order[i] < 0 + && ! TEST_HARD_REG_BIT (bad_spill_regs, i) + && spill_reg_order[i + 1] >= 0 + && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1) + && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1)) + return 1; + if (spill_reg_order[i + 1] < 0 + && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1) + && spill_reg_order[i] >= 0 + && ! TEST_HARD_REG_BIT (counted_for_groups, i) + && ! TEST_HARD_REG_BIT (counted_for_nongroups, i)) + return 1; + } + + return 0; +} + +/* Count any groups that can be formed from the registers recently spilled. + This is done class by class, in order of ascending class number. */ + +static void +count_possible_groups (group_size, group_mode, max_groups) + int *group_size; + enum machine_mode *group_mode; + int *max_groups; +{ + int i; + /* Now find all consecutive groups of spilled registers + and mark each group off against the need for such groups. + But don't count them against ordinary need, yet. */ + + for (i = 0; i < N_REG_CLASSES; i++) + if (group_size[i] > 1) + { + HARD_REG_SET new; + int j; + + CLEAR_HARD_REG_SET (new); + + /* Make a mask of all the regs that are spill regs in class I. */ + for (j = 0; j < n_spills; j++) + if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j]) + && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j]) + && ! TEST_HARD_REG_BIT (counted_for_nongroups, + spill_regs[j])) + SET_HARD_REG_BIT (new, spill_regs[j]); + + /* Find each consecutive group of them. */ + for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++) + if (TEST_HARD_REG_BIT (new, j) + && j + group_size[i] <= FIRST_PSEUDO_REGISTER + /* Next line in case group-mode for this class + demands an even-odd pair. */ + && HARD_REGNO_MODE_OK (j, group_mode[i])) + { + int k; + for (k = 1; k < group_size[i]; k++) + if (! TEST_HARD_REG_BIT (new, j + k)) + break; + if (k == group_size[i]) + { + /* We found a group. Mark it off against this class's + need for groups, and against each superclass too. */ + register enum reg_class *p; + max_groups[i]--; + p = reg_class_superclasses[i]; + while (*p != LIM_REG_CLASSES) + max_groups[(int) *p++]--; + /* Don't count these registers again. */ + for (k = 0; k < group_size[i]; k++) + SET_HARD_REG_BIT (counted_for_groups, j + k); + } + /* Skip to the last reg in this group. When j is incremented + above, it will then point to the first reg of the next + possible group. */ + j += k - 1; + } + } + +} + +/* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is + another mode that needs to be reloaded for the same register class CLASS. + If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail. + ALLOCATE_MODE will never be smaller than OTHER_MODE. + + This code used to also fail if any reg in CLASS allows OTHER_MODE but not + ALLOCATE_MODE. This test is unnecessary, because we will never try to put + something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this + causes unnecessary failures on machines requiring alignment of register + groups when the two modes are different sizes, because the larger mode has + more strict alignment rules than the smaller mode. */ + +static int +modes_equiv_for_class_p (allocate_mode, other_mode, class) + enum machine_mode allocate_mode, other_mode; + enum reg_class class; +{ + register int regno; + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + { + if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) + && HARD_REGNO_MODE_OK (regno, allocate_mode) + && ! HARD_REGNO_MODE_OK (regno, other_mode)) + return 0; + } + return 1; +} + +/* Handle the failure to find a register to spill. + INSN should be one of the insns which needed this particular spill reg. */ + +static void +spill_failure (insn) + rtx insn; +{ + if (asm_noperands (PATTERN (insn)) >= 0) + error_for_asm (insn, "`asm' needs too many reloads"); + else + abort (); +} + +/* Add a new register to the tables of available spill-registers + (as well as spilling all pseudos allocated to the register). + I is the index of this register in potential_reload_regs. + CLASS is the regclass whose need is being satisfied. + MAX_NEEDS and MAX_NONGROUPS are the vectors of needs, + so that this register can count off against them. + MAX_NONGROUPS is 0 if this register is part of a group. + GLOBAL and DUMPFILE are the same as the args that `reload' got. */ + +static int +new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile) + int i; + int class; + int *max_needs; + int *max_nongroups; + int global; + FILE *dumpfile; +{ + register enum reg_class *p; + int val; + int regno = potential_reload_regs[i]; + + if (i >= FIRST_PSEUDO_REGISTER) + abort (); /* Caller failed to find any register. */ + + if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno)) + fatal ("fixed or forbidden register was spilled.\n\ +This may be due to a compiler bug or to impossible asm statements."); + + /* Make reg REGNO an additional reload reg. */ + + potential_reload_regs[i] = -1; + spill_regs[n_spills] = regno; + spill_reg_order[regno] = n_spills; + if (dumpfile) + fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]); + + /* Clear off the needs we just satisfied. */ + + max_needs[class]--; + p = reg_class_superclasses[class]; + while (*p != LIM_REG_CLASSES) + max_needs[(int) *p++]--; + + if (max_nongroups && max_nongroups[class] > 0) + { + SET_HARD_REG_BIT (counted_for_nongroups, regno); + max_nongroups[class]--; + p = reg_class_superclasses[class]; + while (*p != LIM_REG_CLASSES) + max_nongroups[(int) *p++]--; + } + + /* Spill every pseudo reg that was allocated to this reg + or to something that overlaps this reg. */ + + val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0); + + /* If there are some registers still to eliminate and this register + wasn't ever used before, additional stack space may have to be + allocated to store this register. Thus, we may have changed the offset + between the stack and frame pointers, so mark that something has changed. + (If new pseudos were spilled, thus requiring more space, VAL would have + been set non-zero by the call to spill_hard_reg above since additional + reloads may be needed in that case. + + One might think that we need only set VAL to 1 if this is a call-used + register. However, the set of registers that must be saved by the + prologue is not identical to the call-used set. For example, the + register used by the call insn for the return PC is a call-used register, + but must be saved by the prologue. */ + if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]]) + val = 1; + + regs_ever_live[spill_regs[n_spills]] = 1; + n_spills++; + + return val; +} + +/* Delete an unneeded INSN and any previous insns who sole purpose is loading + data that is dead in INSN. */ + +static void +delete_dead_insn (insn) + rtx insn; +{ + rtx prev = prev_real_insn (insn); + rtx prev_dest; + + /* If the previous insn sets a register that dies in our insn, delete it + too. */ + if (prev && GET_CODE (PATTERN (prev)) == SET + && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) + && reg_mentioned_p (prev_dest, PATTERN (insn)) + && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))) + delete_dead_insn (prev); + + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; +} + +/* Modify the home of pseudo-reg I. + The new home is present in reg_renumber[I]. + + FROM_REG may be the hard reg that the pseudo-reg is being spilled from; + or it may be -1, meaning there is none or it is not relevant. + This is used so that all pseudos spilled from a given hard reg + can share one stack slot. */ + +static void +alter_reg (i, from_reg) + register int i; + int from_reg; +{ + /* When outputting an inline function, this can happen + for a reg that isn't actually used. */ + if (regno_reg_rtx[i] == 0) + return; + + /* If the reg got changed to a MEM at rtl-generation time, + ignore it. */ + if (GET_CODE (regno_reg_rtx[i]) != REG) + return; + + /* Modify the reg-rtx to contain the new hard reg + number or else to contain its pseudo reg number. */ + REGNO (regno_reg_rtx[i]) + = reg_renumber[i] >= 0 ? reg_renumber[i] : i; + + /* If we have a pseudo that is needed but has no hard reg or equivalent, + allocate a stack slot for it. */ + + if (reg_renumber[i] < 0 + && reg_n_refs[i] > 0 + && reg_equiv_constant[i] == 0 + && reg_equiv_memory_loc[i] == 0) + { + register rtx x; + int inherent_size = PSEUDO_REGNO_BYTES (i); + int total_size = MAX (inherent_size, reg_max_ref_width[i]); + int adjust = 0; + + /* Each pseudo reg has an inherent size which comes from its own mode, + and a total size which provides room for paradoxical subregs + which refer to the pseudo reg in wider modes. + + We can use a slot already allocated if it provides both + enough inherent space and enough total space. + Otherwise, we allocate a new slot, making sure that it has no less + inherent space, and no less total space, then the previous slot. */ + if (from_reg == -1) + { + /* No known place to spill from => no slot to reuse. */ + x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1); +#if BYTES_BIG_ENDIAN + /* Cancel the big-endian correction done in assign_stack_local. + Get the address of the beginning of the slot. + This is so we can do a big-endian correction unconditionally + below. */ + adjust = inherent_size - total_size; +#endif + } + /* Reuse a stack slot if possible. */ + else if (spill_stack_slot[from_reg] != 0 + && spill_stack_slot_width[from_reg] >= total_size + && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) + >= inherent_size)) + x = spill_stack_slot[from_reg]; + /* Allocate a bigger slot. */ + else + { + /* Compute maximum size needed, both for inherent size + and for total size. */ + enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); + if (spill_stack_slot[from_reg]) + { + if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) + > inherent_size) + mode = GET_MODE (spill_stack_slot[from_reg]); + if (spill_stack_slot_width[from_reg] > total_size) + total_size = spill_stack_slot_width[from_reg]; + } + /* Make a slot with that size. */ + x = assign_stack_local (mode, total_size, -1); +#if BYTES_BIG_ENDIAN + /* Cancel the big-endian correction done in assign_stack_local. + Get the address of the beginning of the slot. + This is so we can do a big-endian correction unconditionally + below. */ + adjust = GET_MODE_SIZE (mode) - total_size; +#endif + spill_stack_slot[from_reg] = x; + spill_stack_slot_width[from_reg] = total_size; + } + +#if BYTES_BIG_ENDIAN + /* On a big endian machine, the "address" of the slot + is the address of the low part that fits its inherent mode. */ + if (inherent_size < total_size) + adjust += (total_size - inherent_size); +#endif /* BYTES_BIG_ENDIAN */ + + /* If we have any adjustment to make, or if the stack slot is the + wrong mode, make a new stack slot. */ + if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i])) + { + x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]), + plus_constant (XEXP (x, 0), adjust)); + RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); + } + + /* Save the stack slot for later. */ + reg_equiv_memory_loc[i] = x; + } +} + +/* Mark the slots in regs_ever_live for the hard regs + used by pseudo-reg number REGNO. */ + +void +mark_home_live (regno) + int regno; +{ + register int i, lim; + i = reg_renumber[regno]; + if (i < 0) + return; + lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); + while (i < lim) + regs_ever_live[i++] = 1; +} + +/* This function handles the tracking of elimination offsets around branches. + + X is a piece of RTL being scanned. + + INSN is the insn that it came from, if any. + + INITIAL_P is non-zero if we are to set the offset to be the initial + offset and zero if we are setting the offset of the label to be the + current offset. */ + +static void +set_label_offsets (x, insn, initial_p) + rtx x; + rtx insn; + int initial_p; +{ + enum rtx_code code = GET_CODE (x); + rtx tem; + int i; + struct elim_table *p; + + switch (code) + { + case LABEL_REF: + if (LABEL_REF_NONLOCAL_P (x)) + return; + + x = XEXP (x, 0); + + /* ... fall through ... */ + + case CODE_LABEL: + /* If we know nothing about this label, set the desired offsets. Note + that this sets the offset at a label to be the offset before a label + if we don't know anything about the label. This is not correct for + the label after a BARRIER, but is the best guess we can make. If + we guessed wrong, we will suppress an elimination that might have + been possible had we been able to guess correctly. */ + + if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) + { + for (i = 0; i < NUM_ELIMINABLE_REGS; i++) + offsets_at[CODE_LABEL_NUMBER (x)][i] + = (initial_p ? reg_eliminate[i].initial_offset + : reg_eliminate[i].offset); + offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; + } + + /* Otherwise, if this is the definition of a label and it is + preceded by a BARRIER, set our offsets to the known offset of + that label. */ + + else if (x == insn + && (tem = prev_nonnote_insn (insn)) != 0 + && GET_CODE (tem) == BARRIER) + { + num_not_at_initial_offset = 0; + for (i = 0; i < NUM_ELIMINABLE_REGS; i++) + { + reg_eliminate[i].offset = reg_eliminate[i].previous_offset + = offsets_at[CODE_LABEL_NUMBER (x)][i]; + if (reg_eliminate[i].can_eliminate + && (reg_eliminate[i].offset + != reg_eliminate[i].initial_offset)) + num_not_at_initial_offset++; + } + } + + else + /* If neither of the above cases is true, compare each offset + with those previously recorded and suppress any eliminations + where the offsets disagree. */ + + for (i = 0; i < NUM_ELIMINABLE_REGS; i++) + if (offsets_at[CODE_LABEL_NUMBER (x)][i] + != (initial_p ? reg_eliminate[i].initial_offset + : reg_eliminate[i].offset)) + reg_eliminate[i].can_eliminate = 0; + + return; + + case JUMP_INSN: + set_label_offsets (PATTERN (insn), insn, initial_p); + + /* ... fall through ... */ + + case INSN: + case CALL_INSN: + /* Any labels mentioned in REG_LABEL notes can be branched to indirectly + and hence must have all eliminations at their initial offsets. */ + for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) + if (REG_NOTE_KIND (tem) == REG_LABEL) + set_label_offsets (XEXP (tem, 0), insn, 1); + return; + + case ADDR_VEC: + case ADDR_DIFF_VEC: + /* Each of the labels in the address vector must be at their initial + offsets. We want the first first for ADDR_VEC and the second + field for ADDR_DIFF_VEC. */ + + for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++) + set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), + insn, initial_p); + return; + + case SET: + /* We only care about setting PC. If the source is not RETURN, + IF_THEN_ELSE, or a label, disable any eliminations not at + their initial offsets. Similarly if any arm of the IF_THEN_ELSE + isn't one of those possibilities. For branches to a label, + call ourselves recursively. + + Note that this can disable elimination unnecessarily when we have + a non-local goto since it will look like a non-constant jump to + someplace in the current function. This isn't a significant + problem since such jumps will normally be when all elimination + pairs are back to their initial offsets. */ + + if (SET_DEST (x) != pc_rtx) + return; + + switch (GET_CODE (SET_SRC (x))) + { + case PC: + case RETURN: + return; + + case LABEL_REF: + set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); + return; + + case IF_THEN_ELSE: + tem = XEXP (SET_SRC (x), 1); + if (GET_CODE (tem) == LABEL_REF) + set_label_offsets (XEXP (tem, 0), insn, initial_p); + else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) + break; + + tem = XEXP (SET_SRC (x), 2); + if (GET_CODE (tem) == LABEL_REF) + set_label_offsets (XEXP (tem, 0), insn, initial_p); + else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) + break; + return; + } + + /* If we reach here, all eliminations must be at their initial + offset because we are doing a jump to a variable address. */ + for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) + if (p->offset != p->initial_offset) + p->can_eliminate = 0; + } +} + +/* Used for communication between the next two function to properly share + the vector for an ASM_OPERANDS. */ + +static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec; + +/* Scan X and replace any eliminable registers (such as fp) with a + replacement (such as sp), plus an offset. + + MEM_MODE is the mode of an enclosing MEM. We need this to know how + much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a + MEM, we are allowed to replace a sum of a register and the constant zero + with the register, which we cannot do outside a MEM. In addition, we need + to record the fact that a register is referenced outside a MEM. + + If INSN is nonzero, it is the insn containing X. If we replace a REG + in a SET_DEST with an equivalent MEM and INSN is non-zero, write a + CLOBBER of the pseudo after INSN so find_equiv_regs will know that + that the REG is being modified. + + If we see a modification to a register we know about, take the + appropriate action (see case SET, below). + + REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had + replacements done assuming all offsets are at their initial values. If + they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we + encounter, return the actual location so that find_reloads will do + the proper thing. */ + +rtx +eliminate_regs (x, mem_mode, insn) + rtx x; + enum machine_mode mem_mode; + rtx insn; +{ + enum rtx_code code = GET_CODE (x); + struct elim_table *ep; + int regno; + rtx new; + int i, j; + char *fmt; + int copied = 0; + + switch (code) + { + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case CODE_LABEL: + case PC: + case CC0: + case ASM_INPUT: + case ADDR_VEC: + case ADDR_DIFF_VEC: + case RETURN: + return x; + + case REG: + regno = REGNO (x); + + /* First handle the case where we encounter a bare register that + is eliminable. Replace it with a PLUS. */ + if (regno < FIRST_PSEUDO_REGISTER) + { + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; + ep++) + if (ep->from_rtx == x && ep->can_eliminate) + { + if (! mem_mode) + ep->ref_outside_mem = 1; + return plus_constant (ep->to_rtx, ep->previous_offset); + } + + } + else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno] + && (reg_equiv_address[regno] || num_not_at_initial_offset)) + { + /* In this case, find_reloads would attempt to either use an + incorrect address (if something is not at its initial offset) + or substitute an replaced address into an insn (which loses + if the offset is changed by some later action). So we simply + return the replaced stack slot (assuming it is changed by + elimination) and ignore the fact that this is actually a + reference to the pseudo. Ensure we make a copy of the + address in case it is shared. */ + new = eliminate_regs (reg_equiv_memory_loc[regno], + mem_mode, NULL_RTX); + if (new != reg_equiv_memory_loc[regno]) + { + cannot_omit_stores[regno] = 1; + return copy_rtx (new); + } + } + return x; + + case PLUS: + /* If this is the sum of an eliminable register and a constant, rework + the sum. */ + if (GET_CODE (XEXP (x, 0)) == REG + && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER + && CONSTANT_P (XEXP (x, 1))) + { + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; + ep++) + if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) + { + if (! mem_mode) + ep->ref_outside_mem = 1; + + /* The only time we want to replace a PLUS with a REG (this + occurs when the constant operand of the PLUS is the negative + of the offset) is when we are inside a MEM. We won't want + to do so at other times because that would change the + structure of the insn in a way that reload can't handle. + We special-case the commonest situation in + eliminate_regs_in_insn, so just replace a PLUS with a + PLUS here, unless inside a MEM. */ + if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) == - ep->previous_offset) + return ep->to_rtx; + else + return gen_rtx (PLUS, Pmode, ep->to_rtx, + plus_constant (XEXP (x, 1), + ep->previous_offset)); + } + + /* If the register is not eliminable, we are done since the other + operand is a constant. */ + return x; + } + + /* If this is part of an address, we want to bring any constant to the + outermost PLUS. We will do this by doing register replacement in + our operands and seeing if a constant shows up in one of them. + + We assume here this is part of an address (or a "load address" insn) + since an eliminable register is not likely to appear in any other + context. + + If we have (plus (eliminable) (reg)), we want to produce + (plus (plus (replacement) (reg) (const))). If this was part of a + normal add insn, (plus (replacement) (reg)) will be pushed as a + reload. This is the desired action. */ + + { + rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); + rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX); + + if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) + { + /* If one side is a PLUS and the other side is a pseudo that + didn't get a hard register but has a reg_equiv_constant, + we must replace the constant here since it may no longer + be in the position of any operand. */ + if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG + && REGNO (new1) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (new1)] < 0 + && reg_equiv_constant != 0 + && reg_equiv_constant[REGNO (new1)] != 0) + new1 = reg_equiv_constant[REGNO (new1)]; + else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG + && REGNO (new0) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (new0)] < 0 + && reg_equiv_constant[REGNO (new0)] != 0) + new0 = reg_equiv_constant[REGNO (new0)]; + + new = form_sum (new0, new1); + + /* As above, if we are not inside a MEM we do not want to + turn a PLUS into something else. We might try to do so here + for an addition of 0 if we aren't optimizing. */ + if (! mem_mode && GET_CODE (new) != PLUS) + return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx); + else + return new; + } + } + return x; + + case EXPR_LIST: + /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ + if (XEXP (x, 0)) + { + new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); + if (new != XEXP (x, 0)) + x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1)); + } + + /* ... fall through ... */ + + case INSN_LIST: + /* Now do eliminations in the rest of the chain. If this was + an EXPR_LIST, this might result in allocating more memory than is + strictly needed, but it simplifies the code. */ + if (XEXP (x, 1)) + { + new = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX); + if (new != XEXP (x, 1)) + return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new); + } + return x; + + case CALL: + case COMPARE: + case MINUS: + case MULT: + case DIV: case UDIV: + case MOD: case UMOD: + case AND: case IOR: case XOR: + case LSHIFT: case ASHIFT: case ROTATE: + case ASHIFTRT: case LSHIFTRT: case ROTATERT: + case NE: case EQ: + case GE: case GT: case GEU: case GTU: + case LE: case LT: case LEU: case LTU: + { + rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); + rtx new1 + = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX) : 0; + + if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) + return gen_rtx (code, GET_MODE (x), new0, new1); + } + return x; + + case PRE_INC: + case POST_INC: + case PRE_DEC: + case POST_DEC: + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + if (ep->to_rtx == XEXP (x, 0)) + { + int size = GET_MODE_SIZE (mem_mode); + + /* If more bytes than MEM_MODE are pushed, account for them. */ +#ifdef PUSH_ROUNDING + if (ep->to_rtx == stack_pointer_rtx) + size = PUSH_ROUNDING (size); +#endif + if (code == PRE_DEC || code == POST_DEC) + ep->offset += size; + else + ep->offset -= size; + } + + /* Fall through to generic unary operation case. */ + case USE: + case STRICT_LOW_PART: + case NEG: case NOT: + case SIGN_EXTEND: case ZERO_EXTEND: + case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: + case FLOAT: case FIX: + case UNSIGNED_FIX: case UNSIGNED_FLOAT: + case ABS: + case SQRT: + case FFS: + new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); + if (new != XEXP (x, 0)) + return gen_rtx (code, GET_MODE (x), new); + return x; + + case SUBREG: + /* Similar to above processing, but preserve SUBREG_WORD. + Convert (subreg (mem)) to (mem) if not paradoxical. + Also, if we have a non-paradoxical (subreg (pseudo)) and the + pseudo didn't get a hard reg, we must replace this with the + eliminated version of the memory location because push_reloads + may do the replacement in certain circumstances. */ + if (GET_CODE (SUBREG_REG (x)) == REG + && (GET_MODE_SIZE (GET_MODE (x)) + <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) + && reg_equiv_memory_loc != 0 + && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) + { + new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))], + mem_mode, NULL_RTX); + + /* If we didn't change anything, we must retain the pseudo. */ + if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))]) + new = XEXP (x, 0); + else + /* Otherwise, ensure NEW isn't shared in case we have to reload + it. */ + new = copy_rtx (new); + } + else + new = eliminate_regs (SUBREG_REG (x), mem_mode, NULL_RTX); + + if (new != XEXP (x, 0)) + { + if (GET_CODE (new) == MEM + && (GET_MODE_SIZE (GET_MODE (x)) + <= GET_MODE_SIZE (GET_MODE (new))) +#if defined(BYTES_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND) + /* On these machines we will be reloading what is + inside the SUBREG if it originally was a pseudo and + the inner and outer modes are both a word or + smaller. So leave the SUBREG then. */ + && ! (GET_CODE (SUBREG_REG (x)) == REG + && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD + && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD) +#endif + ) + { + int offset = SUBREG_WORD (x) * UNITS_PER_WORD; + enum machine_mode mode = GET_MODE (x); + +#if BYTES_BIG_ENDIAN + offset += (MIN (UNITS_PER_WORD, + GET_MODE_SIZE (GET_MODE (new))) + - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); +#endif + + PUT_MODE (new, mode); + XEXP (new, 0) = plus_constant (XEXP (new, 0), offset); + return new; + } + else + return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x)); + } + + return x; + + case CLOBBER: + /* If clobbering a register that is the replacement register for an + elimination we still think can be performed, note that it cannot + be performed. Otherwise, we need not be concerned about it. */ + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + if (ep->to_rtx == XEXP (x, 0)) + ep->can_eliminate = 0; + + new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); + if (new != XEXP (x, 0)) + return gen_rtx (code, GET_MODE (x), new); + return x; + + case ASM_OPERANDS: + { + rtx *temp_vec; + /* Properly handle sharing input and constraint vectors. */ + if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec) + { + /* When we come to a new vector not seen before, + scan all its elements; keep the old vector if none + of them changes; otherwise, make a copy. */ + old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x); + temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx)); + for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) + temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i), + mem_mode, NULL_RTX); + + for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) + if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i)) + break; + + if (i == ASM_OPERANDS_INPUT_LENGTH (x)) + new_asm_operands_vec = old_asm_operands_vec; + else + new_asm_operands_vec + = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec); + } + + /* If we had to copy the vector, copy the entire ASM_OPERANDS. */ + if (new_asm_operands_vec == old_asm_operands_vec) + return x; + + new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x), + ASM_OPERANDS_OUTPUT_CONSTRAINT (x), + ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec, + ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x), + ASM_OPERANDS_SOURCE_FILE (x), + ASM_OPERANDS_SOURCE_LINE (x)); + new->volatil = x->volatil; + return new; + } + + case SET: + /* Check for setting a register that we know about. */ + if (GET_CODE (SET_DEST (x)) == REG) + { + /* See if this is setting the replacement register for an + elimination. + + If DEST is the frame pointer, we do nothing because we assume that + all assignments to the frame pointer are for non-local gotos and + are being done at a time when they are valid and do not disturb + anything else. Some machines want to eliminate a fake argument + pointer with either the frame or stack pointer. Assignments to + the frame pointer must not prevent this elimination. */ + + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; + ep++) + if (ep->to_rtx == SET_DEST (x) + && SET_DEST (x) != frame_pointer_rtx) + { + /* If it is being incremented, adjust the offset. Otherwise, + this elimination can't be done. */ + rtx src = SET_SRC (x); + + if (GET_CODE (src) == PLUS + && XEXP (src, 0) == SET_DEST (x) + && GET_CODE (XEXP (src, 1)) == CONST_INT) + ep->offset -= INTVAL (XEXP (src, 1)); + else + ep->can_eliminate = 0; + } + + /* Now check to see we are assigning to a register that can be + eliminated. If so, it must be as part of a PARALLEL, since we + will not have been called if this is a single SET. So indicate + that we can no longer eliminate this reg. */ + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; + ep++) + if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate) + ep->can_eliminate = 0; + } + + /* Now avoid the loop below in this common case. */ + { + rtx new0 = eliminate_regs (SET_DEST (x), 0, NULL_RTX); + rtx new1 = eliminate_regs (SET_SRC (x), 0, NULL_RTX); + + /* If SET_DEST changed from a REG to a MEM and INSN is non-zero, + write a CLOBBER insn. */ + if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM + && insn != 0) + emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn); + + if (new0 != SET_DEST (x) || new1 != SET_SRC (x)) + return gen_rtx (SET, VOIDmode, new0, new1); + } + + return x; + + case MEM: + /* Our only special processing is to pass the mode of the MEM to our + recursive call and copy the flags. While we are here, handle this + case more efficiently. */ + new = eliminate_regs (XEXP (x, 0), GET_MODE (x), NULL_RTX); + if (new != XEXP (x, 0)) + { + new = gen_rtx (MEM, GET_MODE (x), new); + new->volatil = x->volatil; + new->unchanging = x->unchanging; + new->in_struct = x->in_struct; + return new; + } + else + return x; + } + + /* Process each of our operands recursively. If any have changed, make a + copy of the rtx. */ + fmt = GET_RTX_FORMAT (code); + for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) + { + if (*fmt == 'e') + { + new = eliminate_regs (XEXP (x, i), mem_mode, NULL_RTX); + if (new != XEXP (x, i) && ! copied) + { + rtx new_x = rtx_alloc (code); + bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld) + + (sizeof (new_x->fld[0]) + * GET_RTX_LENGTH (code)))); + x = new_x; + copied = 1; + } + XEXP (x, i) = new; + } + else if (*fmt == 'E') + { + int copied_vec = 0; + for (j = 0; j < XVECLEN (x, i); j++) + { + new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); + if (new != XVECEXP (x, i, j) && ! copied_vec) + { + rtvec new_v = gen_rtvec_v (XVECLEN (x, i), + &XVECEXP (x, i, 0)); + if (! copied) + { + rtx new_x = rtx_alloc (code); + bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld) + + (sizeof (new_x->fld[0]) + * GET_RTX_LENGTH (code)))); + x = new_x; + copied = 1; + } + XVEC (x, i) = new_v; + copied_vec = 1; + } + XVECEXP (x, i, j) = new; + } + } + } + + return x; +} + +/* Scan INSN and eliminate all eliminable registers in it. + + If REPLACE is nonzero, do the replacement destructively. Also + delete the insn as dead it if it is setting an eliminable register. + + If REPLACE is zero, do all our allocations in reload_obstack. + + If no eliminations were done and this insn doesn't require any elimination + processing (these are not identical conditions: it might be updating sp, + but not referencing fp; this needs to be seen during reload_as_needed so + that the offset between fp and sp can be taken into consideration), zero + is returned. Otherwise, 1 is returned. */ + +static int +eliminate_regs_in_insn (insn, replace) + rtx insn; + int replace; +{ + rtx old_body = PATTERN (insn); + rtx new_body; + int val = 0; + struct elim_table *ep; + + if (! replace) + push_obstacks (&reload_obstack, &reload_obstack); + + if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG + && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER) + { + /* Check for setting an eliminable register. */ + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate) + { + /* In this case this insn isn't serving a useful purpose. We + will delete it in reload_as_needed once we know that this + elimination is, in fact, being done. + + If REPLACE isn't set, we can't delete this insn, but neededn't + process it since it won't be used unless something changes. */ + if (replace) + delete_dead_insn (insn); + val = 1; + goto done; + } + + /* Check for (set (reg) (plus (reg from) (offset))) where the offset + in the insn is the negative of the offset in FROM. Substitute + (set (reg) (reg to)) for the insn and change its code. + + We have to do this here, rather than in eliminate_regs, do that we can + change the insn code. */ + + if (GET_CODE (SET_SRC (old_body)) == PLUS + && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG + && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT) + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; + ep++) + if (ep->from_rtx == XEXP (SET_SRC (old_body), 0) + && ep->can_eliminate) + { + /* We must stop at the first elimination that will be used. + If this one would replace the PLUS with a REG, do it + now. Otherwise, quit the loop and let eliminate_regs + do its normal replacement. */ + if (ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1))) + { + PATTERN (insn) = gen_rtx (SET, VOIDmode, + SET_DEST (old_body), ep->to_rtx); + INSN_CODE (insn) = -1; + val = 1; + goto done; + } + + break; + } + } + + old_asm_operands_vec = 0; + + /* Replace the body of this insn with a substituted form. If we changed + something, return non-zero. If this is the final call for this + insn (REPLACE is non-zero), do the elimination in REG_NOTES as well. + + If we are replacing a body that was a (set X (plus Y Z)), try to + re-recognize the insn. We do this in case we had a simple addition + but now can do this as a load-address. This saves an insn in this + common case. */ + + new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX); + if (new_body != old_body) + { + /* If we aren't replacing things permanently and we changed something, + make another copy to ensure that all the RTL is new. Otherwise + things can go wrong if find_reload swaps commutative operands + and one is inside RTL that has been copied while the other is not. */ + + /* Don't copy an asm_operands because (1) there's no need and (2) + copy_rtx can't do it properly when there are multiple outputs. */ + if (! replace && asm_noperands (old_body) < 0) + new_body = copy_rtx (new_body); + + /* If we had a move insn but now we don't, rerecognize it. */ + if ((GET_CODE (old_body) == SET && GET_CODE (SET_SRC (old_body)) == REG + && (GET_CODE (new_body) != SET + || GET_CODE (SET_SRC (new_body)) != REG)) + /* If this was an add insn before, rerecognize. */ + || + (GET_CODE (old_body) == SET + && GET_CODE (SET_SRC (old_body)) == PLUS)) + { + if (! validate_change (insn, &PATTERN (insn), new_body, 0)) + /* If recognition fails, store the new body anyway. + It's normal to have recognition failures here + due to bizarre memory addresses; reloading will fix them. */ + PATTERN (insn) = new_body; + } + else + PATTERN (insn) = new_body; + + if (replace && REG_NOTES (insn)) + REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, NULL_RTX); + val = 1; + } + + /* Loop through all elimination pairs. See if any have changed and + recalculate the number not at initial offset. + + Compute the maximum offset (minimum offset if the stack does not + grow downward) for each elimination pair. + + We also detect a cases where register elimination cannot be done, + namely, if a register would be both changed and referenced outside a MEM + in the resulting insn since such an insn is often undefined and, even if + not, we cannot know what meaning will be given to it. Note that it is + valid to have a register used in an address in an insn that changes it + (presumably with a pre- or post-increment or decrement). + + If anything changes, return nonzero. */ + + num_not_at_initial_offset = 0; + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) + { + if (ep->previous_offset != ep->offset && ep->ref_outside_mem) + ep->can_eliminate = 0; + + ep->ref_outside_mem = 0; + + if (ep->previous_offset != ep->offset) + val = 1; + + ep->previous_offset = ep->offset; + if (ep->can_eliminate && ep->offset != ep->initial_offset) + num_not_at_initial_offset++; + +#ifdef STACK_GROWS_DOWNWARD + ep->max_offset = MAX (ep->max_offset, ep->offset); +#else + ep->max_offset = MIN (ep->max_offset, ep->offset); +#endif + } + + done: + if (! replace) + pop_obstacks (); + + return val; +} + +/* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register + replacement we currently believe is valid, mark it as not eliminable if X + modifies DEST in any way other than by adding a constant integer to it. + + If DEST is the frame pointer, we do nothing because we assume that + all assignments to the frame pointer are nonlocal gotos and are being done + at a time when they are valid and do not disturb anything else. + Some machines want to eliminate a fake argument pointer with either the + frame or stack pointer. Assignments to the frame pointer must not prevent + this elimination. + + Called via note_stores from reload before starting its passes to scan + the insns of the function. */ + +static void +mark_not_eliminable (dest, x) + rtx dest; + rtx x; +{ + register int i; + + /* A SUBREG of a hard register here is just changing its mode. We should + not see a SUBREG of an eliminable hard register, but check just in + case. */ + if (GET_CODE (dest) == SUBREG) + dest = SUBREG_REG (dest); + + if (dest == frame_pointer_rtx) + return; + + for (i = 0; i < NUM_ELIMINABLE_REGS; i++) + if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx + && (GET_CODE (x) != SET + || GET_CODE (SET_SRC (x)) != PLUS + || XEXP (SET_SRC (x), 0) != dest + || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) + { + reg_eliminate[i].can_eliminate_previous + = reg_eliminate[i].can_eliminate = 0; + num_eliminable--; + } +} + +/* Kick all pseudos out of hard register REGNO. + If GLOBAL is nonzero, try to find someplace else to put them. + If DUMPFILE is nonzero, log actions taken on that file. + + If CANT_ELIMINATE is nonzero, it means that we are doing this spill + because we found we can't eliminate some register. In the case, no pseudos + are allowed to be in the register, even if they are only in a block that + doesn't require spill registers, unlike the case when we are spilling this + hard reg to produce another spill register. + + Return nonzero if any pseudos needed to be kicked out. */ + +static int +spill_hard_reg (regno, global, dumpfile, cant_eliminate) + register int regno; + int global; + FILE *dumpfile; + int cant_eliminate; +{ + int something_changed = 0; + register int i; + + SET_HARD_REG_BIT (forbidden_regs, regno); + + /* Spill every pseudo reg that was allocated to this reg + or to something that overlaps this reg. */ + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (reg_renumber[i] >= 0 + && reg_renumber[i] <= regno + && (reg_renumber[i] + + HARD_REGNO_NREGS (reg_renumber[i], + PSEUDO_REGNO_MODE (i)) + > regno)) + { + enum reg_class class = REGNO_REG_CLASS (regno); + + /* If this register belongs solely to a basic block which needed no + spilling of any class that this register is contained in, + leave it be, unless we are spilling this register because + it was a hard register that can't be eliminated. */ + + if (! cant_eliminate + && basic_block_needs[0] + && reg_basic_block[i] >= 0 + && basic_block_needs[(int) class][reg_basic_block[i]] == 0) + { + enum reg_class *p; + + for (p = reg_class_superclasses[(int) class]; + *p != LIM_REG_CLASSES; p++) + if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0) + break; + + if (*p == LIM_REG_CLASSES) + continue; + } + + /* Mark it as no longer having a hard register home. */ + reg_renumber[i] = -1; + /* We will need to scan everything again. */ + something_changed = 1; + if (global) + retry_global_alloc (i, forbidden_regs); + + alter_reg (i, regno); + if (dumpfile) + { + if (reg_renumber[i] == -1) + fprintf (dumpfile, " Register %d now on stack.\n\n", i); + else + fprintf (dumpfile, " Register %d now in %d.\n\n", + i, reg_renumber[i]); + } + } + + return something_changed; +} + +/* Find all paradoxical subregs within X and update reg_max_ref_width. */ + +static void +scan_paradoxical_subregs (x) + register rtx x; +{ + register int i; + register char *fmt; + register enum rtx_code code = GET_CODE (x); + + switch (code) + { + case CONST_INT: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + case CONST_DOUBLE: + case CC0: + case PC: + case REG: + case USE: + case CLOBBER: + return; + + case SUBREG: + if (GET_CODE (SUBREG_REG (x)) == REG + && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) + reg_max_ref_width[REGNO (SUBREG_REG (x))] + = GET_MODE_SIZE (GET_MODE (x)); + return; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + scan_paradoxical_subregs (XEXP (x, i)); + else if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (x, i) - 1; j >=0; j--) + scan_paradoxical_subregs (XVECEXP (x, i, j)); + } + } +} + +static int +hard_reg_use_compare (p1, p2) + struct hard_reg_n_uses *p1, *p2; +{ + int tem = p1->uses - p2->uses; + if (tem != 0) return tem; + /* If regs are equally good, sort by regno, + so that the results of qsort leave nothing to chance. */ + return p1->regno - p2->regno; +} + +/* Choose the order to consider regs for use as reload registers + based on how much trouble would be caused by spilling one. + Store them in order of decreasing preference in potential_reload_regs. */ + +static void +order_regs_for_reload () +{ + register int i; + register int o = 0; + int large = 0; + + struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER]; + + CLEAR_HARD_REG_SET (bad_spill_regs); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + potential_reload_regs[i] = -1; + + /* Count number of uses of each hard reg by pseudo regs allocated to it + and then order them by decreasing use. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + hard_reg_n_uses[i].uses = 0; + hard_reg_n_uses[i].regno = i; + } + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + { + int regno = reg_renumber[i]; + if (regno >= 0) + { + int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i)); + while (regno < lim) + hard_reg_n_uses[regno++].uses += reg_n_refs[i]; + } + large += reg_n_refs[i]; + } + + /* Now fixed registers (which cannot safely be used for reloading) + get a very high use count so they will be considered least desirable. + Registers used explicitly in the rtl code are almost as bad. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + if (fixed_regs[i]) + { + hard_reg_n_uses[i].uses += 2 * large + 2; + SET_HARD_REG_BIT (bad_spill_regs, i); + } + else if (regs_explicitly_used[i]) + { + hard_reg_n_uses[i].uses += large + 1; +#ifndef SMALL_REGISTER_CLASSES + /* ??? We are doing this here because of the potential that + bad code may be generated if a register explicitly used in + an insn was used as a spill register for that insn. But + not using these are spill registers may lose on some machine. + We'll have to see how this works out. */ + SET_HARD_REG_BIT (bad_spill_regs, i); +#endif + } + } + hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2; + SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM); + +#ifdef ELIMINABLE_REGS + /* If registers other than the frame pointer are eliminable, mark them as + poor choices. */ + for (i = 0; i < NUM_ELIMINABLE_REGS; i++) + { + hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2; + SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from); + } +#endif + + /* Prefer registers not so far used, for use in temporary loading. + Among them, if REG_ALLOC_ORDER is defined, use that order. + Otherwise, prefer registers not preserved by calls. */ + +#ifdef REG_ALLOC_ORDER + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + int regno = reg_alloc_order[i]; + + if (hard_reg_n_uses[regno].uses == 0) + potential_reload_regs[o++] = regno; + } +#else + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]) + potential_reload_regs[o++] = i; + } + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]) + potential_reload_regs[o++] = i; + } +#endif + + qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER, + sizeof hard_reg_n_uses[0], hard_reg_use_compare); + + /* Now add the regs that are already used, + preferring those used less often. The fixed and otherwise forbidden + registers will be at the end of this list. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (hard_reg_n_uses[i].uses != 0) + potential_reload_regs[o++] = hard_reg_n_uses[i].regno; +} + +/* Reload pseudo-registers into hard regs around each insn as needed. + Additional register load insns are output before the insn that needs it + and perhaps store insns after insns that modify the reloaded pseudo reg. + + reg_last_reload_reg and reg_reloaded_contents keep track of + which registers are already available in reload registers. + We update these for the reloads that we perform, + as the insns are scanned. */ + +static void +reload_as_needed (first, live_known) + rtx first; + int live_known; +{ + register rtx insn; + register int i; + int this_block = 0; + rtx x; + rtx after_call = 0; + + bzero (spill_reg_rtx, sizeof spill_reg_rtx); + reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx)); + bzero (reg_last_reload_reg, max_regno * sizeof (rtx)); + reg_has_output_reload = (char *) alloca (max_regno); + for (i = 0; i < n_spills; i++) + { + reg_reloaded_contents[i] = -1; + reg_reloaded_insn[i] = 0; + } + + /* Reset all offsets on eliminable registers to their initial values. */ +#ifdef ELIMINABLE_REGS + for (i = 0; i < NUM_ELIMINABLE_REGS; i++) + { + INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to, + reg_eliminate[i].initial_offset); + reg_eliminate[i].previous_offset + = reg_eliminate[i].offset = reg_eliminate[i].initial_offset; + } +#else + INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset); + reg_eliminate[0].previous_offset + = reg_eliminate[0].offset = reg_eliminate[0].initial_offset; +#endif + + num_not_at_initial_offset = 0; + + for (insn = first; insn;) + { + register rtx next = NEXT_INSN (insn); + + /* Notice when we move to a new basic block. */ + if (live_known && this_block + 1 < n_basic_blocks + && insn == basic_block_head[this_block+1]) + ++this_block; + + /* If we pass a label, copy the offsets from the label information + into the current offsets of each elimination. */ + if (GET_CODE (insn) == CODE_LABEL) + { + num_not_at_initial_offset = 0; + for (i = 0; i < NUM_ELIMINABLE_REGS; i++) + { + reg_eliminate[i].offset = reg_eliminate[i].previous_offset + = offsets_at[CODE_LABEL_NUMBER (insn)][i]; + if (reg_eliminate[i].can_eliminate + && (reg_eliminate[i].offset + != reg_eliminate[i].initial_offset)) + num_not_at_initial_offset++; + } + } + + else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + rtx avoid_return_reg = 0; + +#ifdef SMALL_REGISTER_CLASSES + /* Set avoid_return_reg if this is an insn + that might use the value of a function call. */ + if (GET_CODE (insn) == CALL_INSN) + { + if (GET_CODE (PATTERN (insn)) == SET) + after_call = SET_DEST (PATTERN (insn)); + else if (GET_CODE (PATTERN (insn)) == PARALLEL + && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) + after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); + else + after_call = 0; + } + else if (after_call != 0 + && !(GET_CODE (PATTERN (insn)) == SET + && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)) + { + if (reg_mentioned_p (after_call, PATTERN (insn))) + avoid_return_reg = after_call; + after_call = 0; + } +#endif /* SMALL_REGISTER_CLASSES */ + + /* If this is a USE and CLOBBER of a MEM, ensure that any + references to eliminable registers have been removed. */ + + if ((GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER) + && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) + XEXP (XEXP (PATTERN (insn), 0), 0) + = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), + GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX); + + /* If we need to do register elimination processing, do so. + This might delete the insn, in which case we are done. */ + if (num_eliminable && GET_MODE (insn) == QImode) + { + eliminate_regs_in_insn (insn, 1); + if (GET_CODE (insn) == NOTE) + { + insn = next; + continue; + } + } + + if (GET_MODE (insn) == VOIDmode) + n_reloads = 0; + /* First find the pseudo regs that must be reloaded for this insn. + This info is returned in the tables reload_... (see reload.h). + Also modify the body of INSN by substituting RELOAD + rtx's for those pseudo regs. */ + else + { + bzero (reg_has_output_reload, max_regno); + CLEAR_HARD_REG_SET (reg_is_output_reload); + + find_reloads (insn, 1, spill_indirect_levels, live_known, + spill_reg_order); + } + + if (n_reloads > 0) + { + rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn); + rtx p; + int class; + + /* If this block has not had spilling done for a + particular clas and we have any non-optionals that need a + spill reg in that class, abort. */ + + for (class = 0; class < N_REG_CLASSES; class++) + if (basic_block_needs[class] != 0 + && basic_block_needs[class][this_block] == 0) + for (i = 0; i < n_reloads; i++) + if (class == (int) reload_reg_class[i] + && reload_reg_rtx[i] == 0 + && ! reload_optional[i] + && (reload_in[i] != 0 || reload_out[i] != 0 + || reload_secondary_p[i] != 0)) + abort (); + + /* Now compute which reload regs to reload them into. Perhaps + reusing reload regs from previous insns, or else output + load insns to reload them. Maybe output store insns too. + Record the choices of reload reg in reload_reg_rtx. */ + choose_reload_regs (insn, avoid_return_reg); + +#ifdef SMALL_REGISTER_CLASSES + /* Merge any reloads that we didn't combine for fear of + increasing the number of spill registers needed but now + discover can be safely merged. */ + merge_assigned_reloads (insn); +#endif + + /* Generate the insns to reload operands into or out of + their reload regs. */ + emit_reload_insns (insn); + + /* Substitute the chosen reload regs from reload_reg_rtx + into the insn's body (or perhaps into the bodies of other + load and store insn that we just made for reloading + and that we moved the structure into). */ + subst_reloads (); + + /* If this was an ASM, make sure that all the reload insns + we have generated are valid. If not, give an error + and delete them. */ + + if (asm_noperands (PATTERN (insn)) >= 0) + for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) + if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i' + && (recog_memoized (p) < 0 + || (insn_extract (p), + ! constrain_operands (INSN_CODE (p), 1)))) + { + error_for_asm (insn, + "`asm' operand requires impossible reload"); + PUT_CODE (p, NOTE); + NOTE_SOURCE_FILE (p) = 0; + NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; + } + } + /* Any previously reloaded spilled pseudo reg, stored in this insn, + is no longer validly lying around to save a future reload. + Note that this does not detect pseudos that were reloaded + for this insn in order to be stored in + (obeying register constraints). That is correct; such reload + registers ARE still valid. */ + note_stores (PATTERN (insn), forget_old_reloads_1); + + /* There may have been CLOBBER insns placed after INSN. So scan + between INSN and NEXT and use them to forget old reloads. */ + for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x)) + if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) + note_stores (PATTERN (x), forget_old_reloads_1); + +#ifdef AUTO_INC_DEC + /* Likewise for regs altered by auto-increment in this insn. + But note that the reg-notes are not changed by reloading: + they still contain the pseudo-regs, not the spill regs. */ + for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) + if (REG_NOTE_KIND (x) == REG_INC) + { + /* See if this pseudo reg was reloaded in this insn. + If so, its last-reload info is still valid + because it is based on this insn's reload. */ + for (i = 0; i < n_reloads; i++) + if (reload_out[i] == XEXP (x, 0)) + break; + + if (i == n_reloads) + forget_old_reloads_1 (XEXP (x, 0), NULL_RTX); + } +#endif + } + /* A reload reg's contents are unknown after a label. */ + if (GET_CODE (insn) == CODE_LABEL) + for (i = 0; i < n_spills; i++) + { + reg_reloaded_contents[i] = -1; + reg_reloaded_insn[i] = 0; + } + + /* Don't assume a reload reg is still good after a call insn + if it is a call-used reg. */ + else if (GET_CODE (insn) == CALL_INSN) + for (i = 0; i < n_spills; i++) + if (call_used_regs[spill_regs[i]]) + { + reg_reloaded_contents[i] = -1; + reg_reloaded_insn[i] = 0; + } + + /* In case registers overlap, allow certain insns to invalidate + particular hard registers. */ + +#ifdef INSN_CLOBBERS_REGNO_P + for (i = 0 ; i < n_spills ; i++) + if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i])) + { + reg_reloaded_contents[i] = -1; + reg_reloaded_insn[i] = 0; + } +#endif + + insn = next; + +#ifdef USE_C_ALLOCA + alloca (0); +#endif + } +} + +/* Discard all record of any value reloaded from X, + or reloaded in X from someplace else; + unless X is an output reload reg of the current insn. + + X may be a hard reg (the reload reg) + or it may be a pseudo reg that was reloaded from. */ + +static void +forget_old_reloads_1 (x, ignored) + rtx x; + rtx ignored; +{ + register int regno; + int nr; + int offset = 0; + + /* note_stores does give us subregs of hard regs. */ + while (GET_CODE (x) == SUBREG) + { + offset += SUBREG_WORD (x); + x = SUBREG_REG (x); + } + + if (GET_CODE (x) != REG) + return; + + regno = REGNO (x) + offset; + + if (regno >= FIRST_PSEUDO_REGISTER) + nr = 1; + else + { + int i; + nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); + /* Storing into a spilled-reg invalidates its contents. + This can happen if a block-local pseudo is allocated to that reg + and it wasn't spilled because this block's total need is 0. + Then some insn might have an optional reload and use this reg. */ + for (i = 0; i < nr; i++) + if (spill_reg_order[regno + i] >= 0 + /* But don't do this if the reg actually serves as an output + reload reg in the current instruction. */ + && (n_reloads == 0 + || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))) + { + reg_reloaded_contents[spill_reg_order[regno + i]] = -1; + reg_reloaded_insn[spill_reg_order[regno + i]] = 0; + } + } + + /* Since value of X has changed, + forget any value previously copied from it. */ + + while (nr-- > 0) + /* But don't forget a copy if this is the output reload + that establishes the copy's validity. */ + if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) + reg_last_reload_reg[regno + nr] = 0; +} + +/* For each reload, the mode of the reload register. */ +static enum machine_mode reload_mode[MAX_RELOADS]; + +/* For each reload, the largest number of registers it will require. */ +static int reload_nregs[MAX_RELOADS]; + +/* Comparison function for qsort to decide which of two reloads + should be handled first. *P1 and *P2 are the reload numbers. */ + +static int +reload_reg_class_lower (p1, p2) + short *p1, *p2; +{ + register int r1 = *p1, r2 = *p2; + register int t; + + /* Consider required reloads before optional ones. */ + t = reload_optional[r1] - reload_optional[r2]; + if (t != 0) + return t; + + /* Count all solitary classes before non-solitary ones. */ + t = ((reg_class_size[(int) reload_reg_class[r2]] == 1) + - (reg_class_size[(int) reload_reg_class[r1]] == 1)); + if (t != 0) + return t; + + /* Aside from solitaires, consider all multi-reg groups first. */ + t = reload_nregs[r2] - reload_nregs[r1]; + if (t != 0) + return t; + + /* Consider reloads in order of increasing reg-class number. */ + t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2]; + if (t != 0) + return t; + + /* If reloads are equally urgent, sort by reload number, + so that the results of qsort leave nothing to chance. */ + return r1 - r2; +} + +/* The following HARD_REG_SETs indicate when each hard register is + used for a reload of various parts of the current insn. */ + +/* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ +static HARD_REG_SET reload_reg_used; +/* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ +static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; +/* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ +static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; +/* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ +static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; +/* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ +static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; +/* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ +static HARD_REG_SET reload_reg_used_in_op_addr; +/* If reg is in use for a RELOAD_FOR_INSN reload. */ +static HARD_REG_SET reload_reg_used_in_insn; +/* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ +static HARD_REG_SET reload_reg_used_in_other_addr; + +/* If reg is in use as a reload reg for any sort of reload. */ +static HARD_REG_SET reload_reg_used_at_all; + +/* If reg is use as an inherited reload. We just mark the first register + in the group. */ +static HARD_REG_SET reload_reg_used_for_inherit; + +/* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and + TYPE. MODE is used to indicate how many consecutive regs are + actually used. */ + +static void +mark_reload_reg_in_use (regno, opnum, type, mode) + int regno; + int opnum; + enum reload_type type; + enum machine_mode mode; +{ + int nregs = HARD_REGNO_NREGS (regno, mode); + int i; + + for (i = regno; i < nregs + regno; i++) + { + switch (type) + { + case RELOAD_OTHER: + SET_HARD_REG_BIT (reload_reg_used, i); + break; + + case RELOAD_FOR_INPUT_ADDRESS: + SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); + break; + + case RELOAD_FOR_OUTPUT_ADDRESS: + SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); + break; + + case RELOAD_FOR_OPERAND_ADDRESS: + SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); + break; + + case RELOAD_FOR_OTHER_ADDRESS: + SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); + break; + + case RELOAD_FOR_INPUT: + SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); + break; + + case RELOAD_FOR_OUTPUT: + SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); + break; + + case RELOAD_FOR_INSN: + SET_HARD_REG_BIT (reload_reg_used_in_insn, i); + break; + } + + SET_HARD_REG_BIT (reload_reg_used_at_all, i); + } +} + +/* Similarly, but show REGNO is no longer in use for a reload. */ + +static void +clear_reload_reg_in_use (regno, opnum, type, mode) + int regno; + int opnum; + enum reload_type type; + enum machine_mode mode; +{ + int nregs = HARD_REGNO_NREGS (regno, mode); + int i; + + for (i = regno; i < nregs + regno; i++) + { + switch (type) + { + case RELOAD_OTHER: + CLEAR_HARD_REG_BIT (reload_reg_used, i); + break; + + case RELOAD_FOR_INPUT_ADDRESS: + CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); + break; + + case RELOAD_FOR_OUTPUT_ADDRESS: + CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); + break; + + case RELOAD_FOR_OPERAND_ADDRESS: + CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i); + break; + + case RELOAD_FOR_OTHER_ADDRESS: + CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i); + break; + + case RELOAD_FOR_INPUT: + CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); + break; + + case RELOAD_FOR_OUTPUT: + CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); + break; + + case RELOAD_FOR_INSN: + CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i); + break; + } + } +} + +/* 1 if reg REGNO is free as a reload reg for a reload of the sort + specified by OPNUM and TYPE. */ + +static int +reload_reg_free_p (regno, opnum, type) + int regno; + int opnum; + enum reload_type type; +{ + int i; + + /* In use for a RELOAD_OTHER means it's not available for anything except + RELOAD_FOR_OTHER_ADDRESS. Recall that RELOAD_FOR_OTHER_ADDRESS is known + to be used only for inputs. */ + + if (type != RELOAD_FOR_OTHER_ADDRESS + && TEST_HARD_REG_BIT (reload_reg_used, regno)) + return 0; + + switch (type) + { + case RELOAD_OTHER: + /* In use for anything means not available for a RELOAD_OTHER. */ + return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno); + + /* The other kinds of use can sometimes share a register. */ + case RELOAD_FOR_INPUT: + if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) + return 0; + + /* If it is used for some other input, can't use it. */ + for (i = 0; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) + return 0; + + /* If it is used in a later operand's address, can't use it. */ + for (i = opnum + 1; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)) + return 0; + + return 1; + + case RELOAD_FOR_INPUT_ADDRESS: + /* Can't use a register if it is used for an input address for this + operand or used as an input in an earlier one. */ + if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)) + return 0; + + for (i = 0; i < opnum; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) + return 0; + + return 1; + + case RELOAD_FOR_OUTPUT_ADDRESS: + /* Can't use a register if it is used for an output address for this + operand or used as an output in this or a later operand. */ + if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) + return 0; + + for (i = opnum; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) + return 0; + + return 1; + + case RELOAD_FOR_OPERAND_ADDRESS: + for (i = 0; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) + return 0; + + return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) + && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); + + case RELOAD_FOR_OUTPUT: + /* This cannot share a register with RELOAD_FOR_INSN reloads, other + outputs, or an operand address for this or an earlier output. */ + if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) + return 0; + + for (i = 0; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) + return 0; + + for (i = 0; i <= opnum; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)) + return 0; + + return 1; + + case RELOAD_FOR_INSN: + for (i = 0; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) + return 0; + + return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) + && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); + + case RELOAD_FOR_OTHER_ADDRESS: + return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); + } + abort (); +} + +/* Return 1 if the value in reload reg REGNO, as used by a reload + needed for the part of the insn specified by OPNUM and TYPE, + is not in use for a reload in any prior part of the insn. + + We can assume that the reload reg was already tested for availability + at the time it is needed, and we should not check this again, + in case the reg has already been marked in use. */ + +static int +reload_reg_free_before_p (regno, opnum, type) + int regno; + int opnum; + enum reload_type type; +{ + int i; + + switch (type) + { + case RELOAD_FOR_OTHER_ADDRESS: + /* These always come first. */ + return 1; + + case RELOAD_OTHER: + return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); + + /* If this use is for part of the insn, + check the reg is not in use for any prior part. It is tempting + to try to do this by falling through from objecs that occur + later in the insn to ones that occur earlier, but that will not + correctly take into account the fact that here we MUST ignore + things that would prevent the register from being allocated in + the first place, since we know that it was allocated. */ + + case RELOAD_FOR_OUTPUT_ADDRESS: + /* Earlier reloads are for earlier outputs or their addresses, + any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any + RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with + RELOAD_OTHER).. */ + for (i = 0; i < opnum; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) + return 0; + + if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) + return 0; + + for (i = 0; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) + return 0; + + return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) + && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) + && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); + + case RELOAD_FOR_OUTPUT: + /* This can't be used in the output address for this operand and + anything that can't be used for it, except that we've already + tested for RELOAD_FOR_INSN objects. */ + + if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) + return 0; + + for (i = 0; i < opnum; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) + return 0; + + for (i = 0; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) + return 0; + + return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); + + case RELOAD_FOR_OPERAND_ADDRESS: + case RELOAD_FOR_INSN: + /* These can't conflict with inputs, or each other, so all we have to + test is input addresses and the addresses of OTHER items. */ + + for (i = 0; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)) + return 0; + + return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); + + case RELOAD_FOR_INPUT: + /* The only things earlier are the address for this and + earlier inputs, other inputs (which we know we don't conflict + with), and addresses of RELOAD_OTHER objects. */ + + for (i = 0; i <= opnum; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)) + return 0; + + return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); + + case RELOAD_FOR_INPUT_ADDRESS: + /* Similarly, all we have to check is for use in earlier inputs' + addresses. */ + for (i = 0; i < opnum; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)) + return 0; + + return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); + } + abort (); +} + +/* Return 1 if the value in reload reg REGNO, as used by a reload + needed for the part of the insn specified by OPNUM and TYPE, + is still available in REGNO at the end of the insn. + + We can assume that the reload reg was already tested for availability + at the time it is needed, and we should not check this again, + in case the reg has already been marked in use. */ + +static int +reload_reg_reaches_end_p (regno, opnum, type) + int regno; + int opnum; + enum reload_type type; +{ + int i; + + switch (type) + { + case RELOAD_OTHER: + /* Since a RELOAD_OTHER reload claims the reg for the entire insn, + its value must reach the end. */ + return 1; + + /* If this use is for part of the insn, + its value reaches if no subsequent part uses the same register. + Just like the above function, don't try to do this with lots + of fallthroughs. */ + + case RELOAD_FOR_OTHER_ADDRESS: + /* Here we check for everything else, since these don't conflict + with anything else and everything comes later. */ + + for (i = 0; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) + return 0; + + return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) + && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) + && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); + + case RELOAD_FOR_INPUT_ADDRESS: + /* Similar, except that we check only for this and subsequent inputs + and the address of only subsequent inputs and we do not need + to check for RELOAD_OTHER objects since they are known not to + conflict. */ + + for (i = opnum; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) + return 0; + + for (i = opnum + 1; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)) + return 0; + + for (i = 0; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) + return 0; + + return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) + && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)); + + case RELOAD_FOR_INPUT: + /* Similar to input address, except we start at the next operand for + both input and input address and we do not check for + RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these + would conflict. */ + + for (i = opnum + 1; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) + return 0; + + /* ... fall through ... */ + + case RELOAD_FOR_OPERAND_ADDRESS: + /* Check outputs and their addresses. */ + + for (i = 0; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) + || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) + return 0; + + return 1; + + case RELOAD_FOR_INSN: + /* These conflict with other outputs with with RELOAD_OTHER. So + we need only check for output addresses. */ + + opnum = -1; + + /* ... fall through ... */ + + case RELOAD_FOR_OUTPUT: + case RELOAD_FOR_OUTPUT_ADDRESS: + /* We already know these can't conflict with a later output. So the + only thing to check are later output addresses. */ + for (i = opnum + 1; i < reload_n_operands; i++) + if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)) + return 0; + + return 1; + } + + abort (); +} + +/* Vector of reload-numbers showing the order in which the reloads should + be processed. */ +short reload_order[MAX_RELOADS]; + +/* Indexed by reload number, 1 if incoming value + inherited from previous insns. */ +char reload_inherited[MAX_RELOADS]; + +/* For an inherited reload, this is the insn the reload was inherited from, + if we know it. Otherwise, this is 0. */ +rtx reload_inheritance_insn[MAX_RELOADS]; + +/* If non-zero, this is a place to get the value of the reload, + rather than using reload_in. */ +rtx reload_override_in[MAX_RELOADS]; + +/* For each reload, the index in spill_regs of the spill register used, + or -1 if we did not need one of the spill registers for this reload. */ +int reload_spill_index[MAX_RELOADS]; + +/* Index of last register assigned as a spill register. We allocate in + a round-robin fashio. */ + +static int last_spill_reg = 0; + +/* Find a spill register to use as a reload register for reload R. + LAST_RELOAD is non-zero if this is the last reload for the insn being + processed. + + Set reload_reg_rtx[R] to the register allocated. + + If NOERROR is nonzero, we return 1 if successful, + or 0 if we couldn't find a spill reg and we didn't change anything. */ + +static int +allocate_reload_reg (r, insn, last_reload, noerror) + int r; + rtx insn; + int last_reload; + int noerror; +{ + int i; + int pass; + int count; + rtx new; + int regno; + + /* If we put this reload ahead, thinking it is a group, + then insist on finding a group. Otherwise we can grab a + reg that some other reload needs. + (That can happen when we have a 68000 DATA_OR_FP_REG + which is a group of data regs or one fp reg.) + We need not be so restrictive if there are no more reloads + for this insn. + + ??? Really it would be nicer to have smarter handling + for that kind of reg class, where a problem like this is normal. + Perhaps those classes should be avoided for reloading + by use of more alternatives. */ + + int force_group = reload_nregs[r] > 1 && ! last_reload; + + /* If we want a single register and haven't yet found one, + take any reg in the right class and not in use. + If we want a consecutive group, here is where we look for it. + + We use two passes so we can first look for reload regs to + reuse, which are already in use for other reloads in this insn, + and only then use additional registers. + I think that maximizing reuse is needed to make sure we don't + run out of reload regs. Suppose we have three reloads, and + reloads A and B can share regs. These need two regs. + Suppose A and B are given different regs. + That leaves none for C. */ + for (pass = 0; pass < 2; pass++) + { + /* I is the index in spill_regs. + We advance it round-robin between insns to use all spill regs + equally, so that inherited reloads have a chance + of leapfrogging each other. */ + + for (count = 0, i = last_spill_reg; count < n_spills; count++) + { + int class = (int) reload_reg_class[r]; + + i = (i + 1) % n_spills; + + if (reload_reg_free_p (spill_regs[i], reload_opnum[r], + reload_when_needed[r]) + && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i]) + && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r]) + /* Look first for regs to share, then for unshared. But + don't share regs used for inherited reloads; they are + the ones we want to preserve. */ + && (pass + || (TEST_HARD_REG_BIT (reload_reg_used_at_all, + spill_regs[i]) + && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, + spill_regs[i])))) + { + int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]); + /* Avoid the problem where spilling a GENERAL_OR_FP_REG + (on 68000) got us two FP regs. If NR is 1, + we would reject both of them. */ + if (force_group) + nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]); + /* If we need only one reg, we have already won. */ + if (nr == 1) + { + /* But reject a single reg if we demand a group. */ + if (force_group) + continue; + break; + } + /* Otherwise check that as many consecutive regs as we need + are available here. + Also, don't use for a group registers that are + needed for nongroups. */ + if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i])) + while (nr > 1) + { + regno = spill_regs[i] + nr - 1; + if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) + && spill_reg_order[regno] >= 0 + && reload_reg_free_p (regno, reload_opnum[r], + reload_when_needed[r]) + && ! TEST_HARD_REG_BIT (counted_for_nongroups, + regno))) + break; + nr--; + } + if (nr == 1) + break; + } + } + + /* If we found something on pass 1, omit pass 2. */ + if (count < n_spills) + break; + } + + /* We should have found a spill register by now. */ + if (count == n_spills) + { + if (noerror) + return 0; + goto failure; + } + + /* I is the index in SPILL_REG_RTX of the reload register we are to + allocate. Get an rtx for it and find its register number. */ + + new = spill_reg_rtx[i]; + + if (new == 0 || GET_MODE (new) != reload_mode[r]) + spill_reg_rtx[i] = new + = gen_rtx (REG, reload_mode[r], spill_regs[i]); + + regno = true_regnum (new); + + /* Detect when the reload reg can't hold the reload mode. + This used to be one `if', but Sequent compiler can't handle that. */ + if (HARD_REGNO_MODE_OK (regno, reload_mode[r])) + { + enum machine_mode test_mode = VOIDmode; + if (reload_in[r]) + test_mode = GET_MODE (reload_in[r]); + /* If reload_in[r] has VOIDmode, it means we will load it + in whatever mode the reload reg has: to wit, reload_mode[r]. + We have already tested that for validity. */ + /* Aside from that, we need to test that the expressions + to reload from or into have modes which are valid for this + reload register. Otherwise the reload insns would be invalid. */ + if (! (reload_in[r] != 0 && test_mode != VOIDmode + && ! HARD_REGNO_MODE_OK (regno, test_mode))) + if (! (reload_out[r] != 0 + && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r])))) + { + /* The reg is OK. */ + last_spill_reg = i; + + /* Mark as in use for this insn the reload regs we use + for this. */ + mark_reload_reg_in_use (spill_regs[i], reload_opnum[r], + reload_when_needed[r], reload_mode[r]); + + reload_reg_rtx[r] = new; + reload_spill_index[r] = i; + return 1; + } + } + + /* The reg is not OK. */ + if (noerror) + return 0; + + failure: + if (asm_noperands (PATTERN (insn)) < 0) + /* It's the compiler's fault. */ + abort (); + + /* It's the user's fault; the operand's mode and constraint + don't match. Disable this reload so we don't crash in final. */ + error_for_asm (insn, + "`asm' operand constraint incompatible with operand size"); + reload_in[r] = 0; + reload_out[r] = 0; + reload_reg_rtx[r] = 0; + reload_optional[r] = 1; + reload_secondary_p[r] = 1; + + return 1; +} + +/* Assign hard reg targets for the pseudo-registers we must reload + into hard regs for this insn. + Also output the instructions to copy them in and out of the hard regs. + + For machines with register classes, we are responsible for + finding a reload reg in the proper class. */ + +static void +choose_reload_regs (insn, avoid_return_reg) + rtx insn; + rtx avoid_return_reg; +{ + register int i, j; + int max_group_size = 1; + enum reg_class group_class = NO_REGS; + int inheritance; + + rtx save_reload_reg_rtx[MAX_RELOADS]; + char save_reload_inherited[MAX_RELOADS]; + rtx save_reload_inheritance_insn[MAX_RELOADS]; + rtx save_reload_override_in[MAX_RELOADS]; + int save_reload_spill_index[MAX_RELOADS]; + HARD_REG_SET save_reload_reg_used; + HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; + HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; + HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS]; + HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS]; + HARD_REG_SET save_reload_reg_used_in_op_addr; + HARD_REG_SET save_reload_reg_used_in_insn; + HARD_REG_SET save_reload_reg_used_in_other_addr; + HARD_REG_SET save_reload_reg_used_at_all; + + bzero (reload_inherited, MAX_RELOADS); + bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx)); + bzero (reload_override_in, MAX_RELOADS * sizeof (rtx)); + + CLEAR_HARD_REG_SET (reload_reg_used); + CLEAR_HARD_REG_SET (reload_reg_used_at_all); + CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); + CLEAR_HARD_REG_SET (reload_reg_used_in_insn); + CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); + + for (i = 0; i < reload_n_operands; i++) + { + CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); + CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); + CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); + CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); + } + +#ifdef SMALL_REGISTER_CLASSES + /* Don't bother with avoiding the return reg + if we have no mandatory reload that could use it. */ + if (avoid_return_reg) + { + int do_avoid = 0; + int regno = REGNO (avoid_return_reg); + int nregs + = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); + int r; + + for (r = regno; r < regno + nregs; r++) + if (spill_reg_order[r] >= 0) + for (j = 0; j < n_reloads; j++) + if (!reload_optional[j] && reload_reg_rtx[j] == 0 + && (reload_in[j] != 0 || reload_out[j] != 0 + || reload_secondary_p[j]) + && + TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r)) + do_avoid = 1; + if (!do_avoid) + avoid_return_reg = 0; + } +#endif /* SMALL_REGISTER_CLASSES */ + +#if 0 /* Not needed, now that we can always retry without inheritance. */ + /* See if we have more mandatory reloads than spill regs. + If so, then we cannot risk optimizations that could prevent + reloads from sharing one spill register. + + Since we will try finding a better register than reload_reg_rtx + unless it is equal to reload_in or reload_out, count such reloads. */ + + { + int tem = 0; +#ifdef SMALL_REGISTER_CLASSES + int tem = (avoid_return_reg != 0); +#endif + for (j = 0; j < n_reloads; j++) + if (! reload_optional[j] + && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j]) + && (reload_reg_rtx[j] == 0 + || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j]) + && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j])))) + tem++; + if (tem > n_spills) + must_reuse = 1; + } +#endif + +#ifdef SMALL_REGISTER_CLASSES + /* Don't use the subroutine call return reg for a reload + if we are supposed to avoid it. */ + if (avoid_return_reg) + { + int regno = REGNO (avoid_return_reg); + int nregs + = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); + int r; + + for (r = regno; r < regno + nregs; r++) + if (spill_reg_order[r] >= 0) + SET_HARD_REG_BIT (reload_reg_used, r); + } +#endif /* SMALL_REGISTER_CLASSES */ + + /* In order to be certain of getting the registers we need, + we must sort the reloads into order of increasing register class. + Then our grabbing of reload registers will parallel the process + that provided the reload registers. + + Also note whether any of the reloads wants a consecutive group of regs. + If so, record the maximum size of the group desired and what + register class contains all the groups needed by this insn. */ + + for (j = 0; j < n_reloads; j++) + { + reload_order[j] = j; + reload_spill_index[j] = -1; + + reload_mode[j] + = (reload_inmode[j] == VOIDmode + || (GET_MODE_SIZE (reload_outmode[j]) + > GET_MODE_SIZE (reload_inmode[j]))) + ? reload_outmode[j] : reload_inmode[j]; + + reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]); + + if (reload_nregs[j] > 1) + { + max_group_size = MAX (reload_nregs[j], max_group_size); + group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class]; + } + + /* If we have already decided to use a certain register, + don't use it in another way. */ + if (reload_reg_rtx[j]) + mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j], + reload_when_needed[j], reload_mode[j]); + } + + if (n_reloads > 1) + qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); + + bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx); + bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited); + bcopy (reload_inheritance_insn, save_reload_inheritance_insn, + sizeof reload_inheritance_insn); + bcopy (reload_override_in, save_reload_override_in, + sizeof reload_override_in); + bcopy (reload_spill_index, save_reload_spill_index, + sizeof reload_spill_index); + COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used); + COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all); + COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr, + reload_reg_used_in_op_addr); + COPY_HARD_REG_SET (save_reload_reg_used_in_insn, + reload_reg_used_in_insn); + COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr, + reload_reg_used_in_other_addr); + + for (i = 0; i < reload_n_operands; i++) + { + COPY_HARD_REG_SET (save_reload_reg_used_in_output[i], + reload_reg_used_in_output[i]); + COPY_HARD_REG_SET (save_reload_reg_used_in_input[i], + reload_reg_used_in_input[i]); + COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i], + reload_reg_used_in_input_addr[i]); + COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i], + reload_reg_used_in_output_addr[i]); + } + + /* If -O, try first with inheritance, then turning it off. + If not -O, don't do inheritance. + Using inheritance when not optimizing leads to paradoxes + with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves + because one side of the comparison might be inherited. */ + + for (inheritance = optimize > 0; inheritance >= 0; inheritance--) + { + /* Process the reloads in order of preference just found. + Beyond this point, subregs can be found in reload_reg_rtx. + + This used to look for an existing reloaded home for all + of the reloads, and only then perform any new reloads. + But that could lose if the reloads were done out of reg-class order + because a later reload with a looser constraint might have an old + home in a register needed by an earlier reload with a tighter constraint. + + To solve this, we make two passes over the reloads, in the order + described above. In the first pass we try to inherit a reload + from a previous insn. If there is a later reload that needs a + class that is a proper subset of the class being processed, we must + also allocate a spill register during the first pass. + + Then make a second pass over the reloads to allocate any reloads + that haven't been given registers yet. */ + + CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); + + for (j = 0; j < n_reloads; j++) + { + register int r = reload_order[j]; + + /* Ignore reloads that got marked inoperative. */ + if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r]) + continue; + + /* If find_reloads chose a to use reload_in or reload_out as a reload + register, we don't need to chose one. Otherwise, try even if it found + one since we might save an insn if we find the value lying around. */ + if (reload_in[r] != 0 && reload_reg_rtx[r] != 0 + && (rtx_equal_p (reload_in[r], reload_reg_rtx[r]) + || rtx_equal_p (reload_out[r], reload_reg_rtx[r]))) + continue; + +#if 0 /* No longer needed for correct operation. + It might give better code, or might not; worth an experiment? */ + /* If this is an optional reload, we can't inherit from earlier insns + until we are sure that any non-optional reloads have been allocated. + The following code takes advantage of the fact that optional reloads + are at the end of reload_order. */ + if (reload_optional[r] != 0) + for (i = 0; i < j; i++) + if ((reload_out[reload_order[i]] != 0 + || reload_in[reload_order[i]] != 0 + || reload_secondary_p[reload_order[i]]) + && ! reload_optional[reload_order[i]] + && reload_reg_rtx[reload_order[i]] == 0) + allocate_reload_reg (reload_order[i], insn, 0, inheritance); +#endif + + /* First see if this pseudo is already available as reloaded + for a previous insn. We cannot try to inherit for reloads + that are smaller than the maximum number of registers needed + for groups unless the register we would allocate cannot be used + for the groups. + + We could check here to see if this is a secondary reload for + an object that is already in a register of the desired class. + This would avoid the need for the secondary reload register. + But this is complex because we can't easily determine what + objects might want to be loaded via this reload. So let a register + be allocated here. In `emit_reload_insns' we suppress one of the + loads in the case described above. */ + + if (inheritance) + { + register int regno = -1; + enum machine_mode mode; + + if (reload_in[r] == 0) + ; + else if (GET_CODE (reload_in[r]) == REG) + { + regno = REGNO (reload_in[r]); + mode = GET_MODE (reload_in[r]); + } + else if (GET_CODE (reload_in_reg[r]) == REG) + { + regno = REGNO (reload_in_reg[r]); + mode = GET_MODE (reload_in_reg[r]); + } +#if 0 + /* This won't work, since REGNO can be a pseudo reg number. + Also, it takes much more hair to keep track of all the things + that can invalidate an inherited reload of part of a pseudoreg. */ + else if (GET_CODE (reload_in[r]) == SUBREG + && GET_CODE (SUBREG_REG (reload_in[r])) == REG) + regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]); +#endif + + if (regno >= 0 && reg_last_reload_reg[regno] != 0) + { + i = spill_reg_order[REGNO (reg_last_reload_reg[regno])]; + + if (reg_reloaded_contents[i] == regno + && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])) + >= GET_MODE_SIZE (mode)) + && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r]) + && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], + spill_regs[i]) + && (reload_nregs[r] == max_group_size + || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], + spill_regs[i])) + && reload_reg_free_p (spill_regs[i], reload_opnum[r], + reload_when_needed[r]) + && reload_reg_free_before_p (spill_regs[i], + reload_opnum[r], + reload_when_needed[r])) + { + /* If a group is needed, verify that all the subsequent + registers still have their values intact. */ + int nr + = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]); + int k; + + for (k = 1; k < nr; k++) + if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] + != regno) + break; + + if (k == nr) + { + int i1; + + /* We found a register that contains the + value we need. If this register is the + same as an `earlyclobber' operand of the + current insn, just mark it as a place to + reload from since we can't use it as the + reload register itself. */ + + for (i1 = 0; i1 < n_earlyclobbers; i1++) + if (reg_overlap_mentioned_for_reload_p + (reg_last_reload_reg[regno], + reload_earlyclobbers[i1])) + break; + + if (i1 != n_earlyclobbers + /* Don't really use the inherited spill reg + if we need it wider than we've got it. */ + || (GET_MODE_SIZE (reload_mode[r]) + > GET_MODE_SIZE (mode))) + reload_override_in[r] = reg_last_reload_reg[regno]; + else + { + /* We can use this as a reload reg. */ + /* Mark the register as in use for this part of + the insn. */ + mark_reload_reg_in_use (spill_regs[i], + reload_opnum[r], + reload_when_needed[r], + reload_mode[r]); + reload_reg_rtx[r] = reg_last_reload_reg[regno]; + reload_inherited[r] = 1; + reload_inheritance_insn[r] + = reg_reloaded_insn[i]; + reload_spill_index[r] = i; + SET_HARD_REG_BIT (reload_reg_used_for_inherit, + spill_regs[i]); + } + } + } + } + } + + /* Here's another way to see if the value is already lying around. */ + if (inheritance + && reload_in[r] != 0 + && ! reload_inherited[r] + && reload_out[r] == 0 + && (CONSTANT_P (reload_in[r]) + || GET_CODE (reload_in[r]) == PLUS + || GET_CODE (reload_in[r]) == REG + || GET_CODE (reload_in[r]) == MEM) + && (reload_nregs[r] == max_group_size + || ! reg_classes_intersect_p (reload_reg_class[r], group_class))) + { + register rtx equiv + = find_equiv_reg (reload_in[r], insn, reload_reg_class[r], + -1, NULL_PTR, 0, reload_mode[r]); + int regno; + + if (equiv != 0) + { + if (GET_CODE (equiv) == REG) + regno = REGNO (equiv); + else if (GET_CODE (equiv) == SUBREG) + { + regno = REGNO (SUBREG_REG (equiv)); + if (regno < FIRST_PSEUDO_REGISTER) + regno += SUBREG_WORD (equiv); + } + else + abort (); + } + + /* If we found a spill reg, reject it unless it is free + and of the desired class. */ + if (equiv != 0 + && ((spill_reg_order[regno] >= 0 + && ! reload_reg_free_before_p (regno, reload_opnum[r], + reload_when_needed[r])) + || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], + regno))) + equiv = 0; + + if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)) + equiv = 0; + + if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r])) + equiv = 0; + + /* We found a register that contains the value we need. + If this register is the same as an `earlyclobber' operand + of the current insn, just mark it as a place to reload from + since we can't use it as the reload register itself. */ + + if (equiv != 0) + for (i = 0; i < n_earlyclobbers; i++) + if (reg_overlap_mentioned_for_reload_p (equiv, + reload_earlyclobbers[i])) + { + reload_override_in[r] = equiv; + equiv = 0; + break; + } + + /* JRV: If the equiv register we have found is explicitly + clobbered in the current insn, mark but don't use, as above. */ + + if (equiv != 0 && regno_clobbered_p (regno, insn)) + { + reload_override_in[r] = equiv; + equiv = 0; + } + + /* If we found an equivalent reg, say no code need be generated + to load it, and use it as our reload reg. */ + if (equiv != 0 && regno != FRAME_POINTER_REGNUM) + { + reload_reg_rtx[r] = equiv; + reload_inherited[r] = 1; + /* If it is a spill reg, + mark the spill reg as in use for this insn. */ + i = spill_reg_order[regno]; + if (i >= 0) + { + mark_reload_reg_in_use (regno, reload_opnum[r], + reload_when_needed[r], + reload_mode[r]); + SET_HARD_REG_BIT (reload_reg_used_for_inherit, regno); + } + } + } + + /* If we found a register to use already, or if this is an optional + reload, we are done. */ + if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0) + continue; + +#if 0 /* No longer needed for correct operation. Might or might not + give better code on the average. Want to experiment? */ + + /* See if there is a later reload that has a class different from our + class that intersects our class or that requires less register + than our reload. If so, we must allocate a register to this + reload now, since that reload might inherit a previous reload + and take the only available register in our class. Don't do this + for optional reloads since they will force all previous reloads + to be allocated. Also don't do this for reloads that have been + turned off. */ + + for (i = j + 1; i < n_reloads; i++) + { + int s = reload_order[i]; + + if ((reload_in[s] == 0 && reload_out[s] == 0 + && ! reload_secondary_p[s]) + || reload_optional[s]) + continue; + + if ((reload_reg_class[s] != reload_reg_class[r] + && reg_classes_intersect_p (reload_reg_class[r], + reload_reg_class[s])) + || reload_nregs[s] < reload_nregs[r]) + break; + } + + if (i == n_reloads) + continue; + + allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance); +#endif + } + + /* Now allocate reload registers for anything non-optional that + didn't get one yet. */ + for (j = 0; j < n_reloads; j++) + { + register int r = reload_order[j]; + + /* Ignore reloads that got marked inoperative. */ + if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r]) + continue; + + /* Skip reloads that already have a register allocated or are + optional. */ + if (reload_reg_rtx[r] != 0 || reload_optional[r]) + continue; + + if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance)) + break; + } + + /* If that loop got all the way, we have won. */ + if (j == n_reloads) + break; + + fail: + /* Loop around and try without any inheritance. */ + /* First undo everything done by the failed attempt + to allocate with inheritance. */ + bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx); + bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited); + bcopy (save_reload_inheritance_insn, reload_inheritance_insn, + sizeof reload_inheritance_insn); + bcopy (save_reload_override_in, reload_override_in, + sizeof reload_override_in); + bcopy (save_reload_spill_index, reload_spill_index, + sizeof reload_spill_index); + COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used); + COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all); + COPY_HARD_REG_SET (reload_reg_used_in_op_addr, + save_reload_reg_used_in_op_addr); + COPY_HARD_REG_SET (reload_reg_used_in_insn, + save_reload_reg_used_in_insn); + COPY_HARD_REG_SET (reload_reg_used_in_other_addr, + save_reload_reg_used_in_other_addr); + + for (i = 0; i < reload_n_operands; i++) + { + COPY_HARD_REG_SET (reload_reg_used_in_input[i], + save_reload_reg_used_in_input[i]); + COPY_HARD_REG_SET (reload_reg_used_in_output[i], + save_reload_reg_used_in_output[i]); + COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i], + save_reload_reg_used_in_input_addr[i]); + COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i], + save_reload_reg_used_in_output_addr[i]); + } + } + + /* If we thought we could inherit a reload, because it seemed that + nothing else wanted the same reload register earlier in the insn, + verify that assumption, now that all reloads have been assigned. */ + + for (j = 0; j < n_reloads; j++) + { + register int r = reload_order[j]; + + if (reload_inherited[r] && reload_reg_rtx[r] != 0 + && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]), + reload_opnum[r], + reload_when_needed[r])) + reload_inherited[r] = 0; + + /* If we found a better place to reload from, + validate it in the same fashion, if it is a reload reg. */ + if (reload_override_in[r] + && (GET_CODE (reload_override_in[r]) == REG + || GET_CODE (reload_override_in[r]) == SUBREG)) + { + int regno = true_regnum (reload_override_in[r]); + if (spill_reg_order[regno] >= 0 + && ! reload_reg_free_before_p (regno, reload_opnum[r], + reload_when_needed[r])) + reload_override_in[r] = 0; + } + } + + /* Now that reload_override_in is known valid, + actually override reload_in. */ + for (j = 0; j < n_reloads; j++) + if (reload_override_in[j]) + reload_in[j] = reload_override_in[j]; + + /* If this reload won't be done because it has been cancelled or is + optional and not inherited, clear reload_reg_rtx so other + routines (such as subst_reloads) don't get confused. */ + for (j = 0; j < n_reloads; j++) + if (reload_reg_rtx[j] != 0 + && ((reload_optional[j] && ! reload_inherited[j]) + || (reload_in[j] == 0 && reload_out[j] == 0 + && ! reload_secondary_p[j]))) + { + int regno = true_regnum (reload_reg_rtx[j]); + + if (spill_reg_order[regno] >= 0) + clear_reload_reg_in_use (regno, reload_opnum[j], + reload_when_needed[j], reload_mode[j]); + reload_reg_rtx[j] = 0; + } + + /* Record which pseudos and which spill regs have output reloads. */ + for (j = 0; j < n_reloads; j++) + { + register int r = reload_order[j]; + + i = reload_spill_index[r]; + + /* I is nonneg if this reload used one of the spill regs. + If reload_reg_rtx[r] is 0, this is an optional reload + that we opted to ignore. */ + if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG + && reload_reg_rtx[r] != 0) + { + register int nregno = REGNO (reload_out[r]); + int nr = 1; + + if (nregno < FIRST_PSEUDO_REGISTER) + nr = HARD_REGNO_NREGS (nregno, reload_mode[r]); + + while (--nr >= 0) + reg_has_output_reload[nregno + nr] = 1; + + if (i >= 0) + { + nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]); + while (--nr >= 0) + SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr); + } + + if (reload_when_needed[r] != RELOAD_OTHER + && reload_when_needed[r] != RELOAD_FOR_OUTPUT + && reload_when_needed[r] != RELOAD_FOR_INSN) + abort (); + } + } +} + +/* If SMALL_REGISTER_CLASSES are defined, we may not have merged two + reloads of the same item for fear that we might not have enough reload + registers. However, normally they will get the same reload register + and hence actually need not be loaded twice. + + Here we check for the most common case of this phenomenon: when we have + a number of reloads for the same object, each of which were allocated + the same reload_reg_rtx, that reload_reg_rtx is not used for any other + reload, and is not modified in the insn itself. If we find such, + merge all the reloads and set the resulting reload to RELOAD_OTHER. + This will not increase the number of spill registers needed and will + prevent redundant code. */ + +#ifdef SMALL_REGISTER_CLASSES + +static void +merge_assigned_reloads (insn) + rtx insn; +{ + int i, j; + + /* Scan all the reloads looking for ones that only load values and + are not already RELOAD_OTHER and ones whose reload_reg_rtx are + assigned and not modified by INSN. */ + + for (i = 0; i < n_reloads; i++) + { + if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER + || reload_out[i] != 0 || reload_reg_rtx[i] == 0 + || reg_set_p (reload_reg_rtx[i], insn)) + continue; + + /* Look at all other reloads. Ensure that the only use of this + reload_reg_rtx is in a reload that just loads the same value + as we do. Note that any secondary reloads must be of the identical + class since the values, modes, and result registers are the + same, so we need not do anything with any secondary reloads. */ + + for (j = 0; j < n_reloads; j++) + { + if (i == j || reload_reg_rtx[j] == 0 + || ! reg_overlap_mentioned_p (reload_reg_rtx[j], + reload_reg_rtx[i])) + continue; + + /* If the reload regs aren't exactly the same (e.g, different modes) + or if the values are different, we can't merge anything with this + reload register. */ + + if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]) + || reload_out[j] != 0 || reload_in[j] == 0 + || ! rtx_equal_p (reload_in[i], reload_in[j])) + break; + } + + /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if + we, in fact, found any matching reloads. */ + + if (j == n_reloads) + { + for (j = 0; j < n_reloads; j++) + if (i != j && reload_reg_rtx[j] != 0 + && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])) + { + reload_when_needed[i] = RELOAD_OTHER; + reload_in[j] = 0; + transfer_replacements (i, j); + } + + /* If this is now RELOAD_OTHER, look for any reloads that load + parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS + if they were for inputs, RELOAD_OTHER for outputs. Note that + this test is equivalent to looking for reloads for this operand + number. */ + + if (reload_when_needed[i] == RELOAD_OTHER) + for (j = 0; j < n_reloads; j++) + if (reload_in[j] != 0 + && reload_when_needed[i] != RELOAD_OTHER + && reg_overlap_mentioned_for_reload_p (reload_in[j], + reload_in[i])) + reload_when_needed[j] + = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS + ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER; + } + } +} +#endif /* SMALL_RELOAD_CLASSES */ + +/* Output insns to reload values in and out of the chosen reload regs. */ + +static void +emit_reload_insns (insn) + rtx insn; +{ + register int j; + rtx input_reload_insns[MAX_RECOG_OPERANDS]; + rtx other_input_address_reload_insns = 0; + rtx other_input_reload_insns = 0; + rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; + rtx output_reload_insns[MAX_RECOG_OPERANDS]; + rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; + rtx operand_reload_insns = 0; + rtx following_insn = NEXT_INSN (insn); + rtx before_insn = insn; + int special; + /* Values to be put in spill_reg_store are put here first. */ + rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; + + for (j = 0; j < reload_n_operands; j++) + input_reload_insns[j] = input_address_reload_insns[j] + = output_reload_insns[j] = output_address_reload_insns[j] = 0; + + /* If this is a CALL_INSN preceded by USE insns, any reload insns + must go in front of the first USE insn, not in front of INSN. */ + + if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN + && GET_CODE (PATTERN (PREV_INSN (insn))) == USE) + while (GET_CODE (PREV_INSN (before_insn)) == INSN + && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE) + before_insn = PREV_INSN (before_insn); + + /* If INSN is followed by any CLOBBER insns made by find_reloads, + put our reloads after them since they may otherwise be + misinterpreted. */ + + while (GET_CODE (following_insn) == INSN + && GET_MODE (following_insn) == DImode + && GET_CODE (PATTERN (following_insn)) == CLOBBER + && NEXT_INSN (following_insn) != 0) + following_insn = NEXT_INSN (following_insn); + + /* Now output the instructions to copy the data into and out of the + reload registers. Do these in the order that the reloads were reported, + since reloads of base and index registers precede reloads of operands + and the operands may need the base and index registers reloaded. */ + + for (j = 0; j < n_reloads; j++) + { + register rtx old; + rtx oldequiv_reg = 0; + rtx store_insn = 0; + + old = reload_in[j]; + if (old != 0 && ! reload_inherited[j] + && ! rtx_equal_p (reload_reg_rtx[j], old) + && reload_reg_rtx[j] != 0) + { + register rtx reloadreg = reload_reg_rtx[j]; + rtx oldequiv = 0; + enum machine_mode mode; + rtx *where; + + /* Determine the mode to reload in. + This is very tricky because we have three to choose from. + There is the mode the insn operand wants (reload_inmode[J]). + There is the mode of the reload register RELOADREG. + There is the intrinsic mode of the operand, which we could find + by stripping some SUBREGs. + It turns out that RELOADREG's mode is irrelevant: + we can change that arbitrarily. + + Consider (SUBREG:SI foo:QI) as an operand that must be SImode; + then the reload reg may not support QImode moves, so use SImode. + If foo is in memory due to spilling a pseudo reg, this is safe, + because the QImode value is in the least significant part of a + slot big enough for a SImode. If foo is some other sort of + memory reference, then it is impossible to reload this case, + so previous passes had better make sure this never happens. + + Then consider a one-word union which has SImode and one of its + members is a float, being fetched as (SUBREG:SF union:SI). + We must fetch that as SFmode because we could be loading into + a float-only register. In this case OLD's mode is correct. + + Consider an immediate integer: it has VOIDmode. Here we need + to get a mode from something else. + + In some cases, there is a fourth mode, the operand's + containing mode. If the insn specifies a containing mode for + this operand, it overrides all others. + + I am not sure whether the algorithm here is always right, + but it does the right things in those cases. */ + + mode = GET_MODE (old); + if (mode == VOIDmode) + mode = reload_inmode[j]; + +#ifdef SECONDARY_INPUT_RELOAD_CLASS + /* If we need a secondary register for this operation, see if + the value is already in a register in that class. Don't + do this if the secondary register will be used as a scratch + register. */ + + if (reload_secondary_reload[j] >= 0 + && reload_secondary_icode[j] == CODE_FOR_nothing + && optimize) + oldequiv + = find_equiv_reg (old, insn, + reload_reg_class[reload_secondary_reload[j]], + -1, NULL_PTR, 0, mode); +#endif + + /* If reloading from memory, see if there is a register + that already holds the same value. If so, reload from there. + We can pass 0 as the reload_reg_p argument because + any other reload has either already been emitted, + in which case find_equiv_reg will see the reload-insn, + or has yet to be emitted, in which case it doesn't matter + because we will use this equiv reg right away. */ + + if (oldequiv == 0 && optimize + && (GET_CODE (old) == MEM + || (GET_CODE (old) == REG + && REGNO (old) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (old)] < 0))) + oldequiv = find_equiv_reg (old, insn, ALL_REGS, + -1, NULL_PTR, 0, mode); + + if (oldequiv) + { + int regno = true_regnum (oldequiv); + + /* If OLDEQUIV is a spill register, don't use it for this + if any other reload needs it at an earlier stage of this insn + or at this stage. */ + if (spill_reg_order[regno] >= 0 + && (! reload_reg_free_p (regno, reload_opnum[j], + reload_when_needed[j]) + || ! reload_reg_free_before_p (regno, reload_opnum[j], + reload_when_needed[j]))) + oldequiv = 0; + + /* If OLDEQUIV is not a spill register, + don't use it if any other reload wants it. */ + if (spill_reg_order[regno] < 0) + { + int k; + for (k = 0; k < n_reloads; k++) + if (reload_reg_rtx[k] != 0 && k != j + && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k], + oldequiv)) + { + oldequiv = 0; + break; + } + } + + /* If it is no cheaper to copy from OLDEQUIV into the + reload register than it would be to move from memory, + don't use it. Likewise, if we need a secondary register + or memory. */ + + if (oldequiv != 0 + && ((REGNO_REG_CLASS (regno) != reload_reg_class[j] + && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno), + reload_reg_class[j]) + >= MEMORY_MOVE_COST (mode))) +#ifdef SECONDARY_INPUT_RELOAD_CLASS + || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j], + mode, oldequiv) + != NO_REGS) +#endif +#ifdef SECONDARY_MEMORY_NEEDED + || SECONDARY_MEMORY_NEEDED (reload_reg_class[j], + REGNO_REG_CLASS (regno), + mode) +#endif + )) + oldequiv = 0; + } + + if (oldequiv == 0) + oldequiv = old; + else if (GET_CODE (oldequiv) == REG) + oldequiv_reg = oldequiv; + else if (GET_CODE (oldequiv) == SUBREG) + oldequiv_reg = SUBREG_REG (oldequiv); + + /* Encapsulate both RELOADREG and OLDEQUIV into that mode, + then load RELOADREG from OLDEQUIV. */ + + if (GET_MODE (reloadreg) != mode) + reloadreg = gen_lowpart_common (mode, reloadreg); + while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) + oldequiv = SUBREG_REG (oldequiv); + if (GET_MODE (oldequiv) != VOIDmode + && mode != GET_MODE (oldequiv)) + oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0); + + /* Switch to the right place to emit the reload insns. */ + switch (reload_when_needed[j]) + { + case RELOAD_OTHER: + where = &other_input_reload_insns; + break; + case RELOAD_FOR_INPUT: + where = &input_reload_insns[reload_opnum[j]]; + break; + case RELOAD_FOR_INPUT_ADDRESS: + where = &input_address_reload_insns[reload_opnum[j]]; + break; + case RELOAD_FOR_OUTPUT_ADDRESS: + where = &output_address_reload_insns[reload_opnum[j]]; + break; + case RELOAD_FOR_OPERAND_ADDRESS: + where = &operand_reload_insns; + break; + case RELOAD_FOR_OTHER_ADDRESS: + where = &other_input_address_reload_insns; + break; + default: + abort (); + } + + push_to_sequence (*where); + special = 0; + + /* Auto-increment addresses must be reloaded in a special way. */ + if (GET_CODE (oldequiv) == POST_INC + || GET_CODE (oldequiv) == POST_DEC + || GET_CODE (oldequiv) == PRE_INC + || GET_CODE (oldequiv) == PRE_DEC) + { + /* We are not going to bother supporting the case where a + incremented register can't be copied directly from + OLDEQUIV since this seems highly unlikely. */ + if (reload_secondary_reload[j] >= 0) + abort (); + /* Prevent normal processing of this reload. */ + special = 1; + /* Output a special code sequence for this case. */ + inc_for_reload (reloadreg, oldequiv, reload_inc[j]); + } + + /* If we are reloading a pseudo-register that was set by the previous + insn, see if we can get rid of that pseudo-register entirely + by redirecting the previous insn into our reload register. */ + + else if (optimize && GET_CODE (old) == REG + && REGNO (old) >= FIRST_PSEUDO_REGISTER + && dead_or_set_p (insn, old) + /* This is unsafe if some other reload + uses the same reg first. */ + && reload_reg_free_before_p (REGNO (reloadreg), + reload_opnum[j], + reload_when_needed[j])) + { + rtx temp = PREV_INSN (insn); + while (temp && GET_CODE (temp) == NOTE) + temp = PREV_INSN (temp); + if (temp + && GET_CODE (temp) == INSN + && GET_CODE (PATTERN (temp)) == SET + && SET_DEST (PATTERN (temp)) == old + /* Make sure we can access insn_operand_constraint. */ + && asm_noperands (PATTERN (temp)) < 0 + /* This is unsafe if prev insn rejects our reload reg. */ + && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0], + reloadreg) + /* This is unsafe if operand occurs more than once in current + insn. Perhaps some occurrences aren't reloaded. */ + && count_occurrences (PATTERN (insn), old) == 1 + /* Don't risk splitting a matching pair of operands. */ + && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) + { + /* Store into the reload register instead of the pseudo. */ + SET_DEST (PATTERN (temp)) = reloadreg; + /* If these are the only uses of the pseudo reg, + pretend for GDB it lives in the reload reg we used. */ + if (reg_n_deaths[REGNO (old)] == 1 + && reg_n_sets[REGNO (old)] == 1) + { + reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]); + alter_reg (REGNO (old), -1); + } + special = 1; + } + } + + /* We can't do that, so output an insn to load RELOADREG. */ + + if (! special) + { +#ifdef SECONDARY_INPUT_RELOAD_CLASS + rtx second_reload_reg = 0; + enum insn_code icode; + + /* If we have a secondary reload, pick up the secondary register + and icode, if any. If OLDEQUIV and OLD are different or + if this is an in-out reload, recompute whether or not we + still need a secondary register and what the icode should + be. If we still need a secondary register and the class or + icode is different, go back to reloading from OLD if using + OLDEQUIV means that we got the wrong type of register. We + cannot have different class or icode due to an in-out reload + because we don't make such reloads when both the input and + output need secondary reload registers. */ + + if (reload_secondary_reload[j] >= 0) + { + int secondary_reload = reload_secondary_reload[j]; + rtx real_oldequiv = oldequiv; + rtx real_old = old; + + /* If OLDEQUIV is a pseudo with a MEM, get the real MEM + and similarly for OLD. + See comments in find_secondary_reload in reload.c. */ + if (GET_CODE (oldequiv) == REG + && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER + && reg_equiv_mem[REGNO (oldequiv)] != 0) + real_oldequiv = reg_equiv_mem[REGNO (oldequiv)]; + + if (GET_CODE (old) == REG + && REGNO (old) >= FIRST_PSEUDO_REGISTER + && reg_equiv_mem[REGNO (old)] != 0) + real_old = reg_equiv_mem[REGNO (old)]; + + second_reload_reg = reload_reg_rtx[secondary_reload]; + icode = reload_secondary_icode[j]; + + if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) + || (reload_in[j] != 0 && reload_out[j] != 0)) + { + enum reg_class new_class + = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j], + mode, real_oldequiv); + + if (new_class == NO_REGS) + second_reload_reg = 0; + else + { + enum insn_code new_icode; + enum machine_mode new_mode; + + if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], + REGNO (second_reload_reg))) + oldequiv = old, real_oldequiv = real_old; + else + { + new_icode = reload_in_optab[(int) mode]; + if (new_icode != CODE_FOR_nothing + && ((insn_operand_predicate[(int) new_icode][0] + && ! ((*insn_operand_predicate[(int) new_icode][0]) + (reloadreg, mode))) + || (insn_operand_predicate[(int) new_icode][1] + && ! ((*insn_operand_predicate[(int) new_icode][1]) + (real_oldequiv, mode))))) + new_icode = CODE_FOR_nothing; + + if (new_icode == CODE_FOR_nothing) + new_mode = mode; + else + new_mode = insn_operand_mode[(int) new_icode][2]; + + if (GET_MODE (second_reload_reg) != new_mode) + { + if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), + new_mode)) + oldequiv = old, real_oldequiv = real_old; + else + second_reload_reg + = gen_rtx (REG, new_mode, + REGNO (second_reload_reg)); + } + } + } + } + + /* If we still need a secondary reload register, check + to see if it is being used as a scratch or intermediate + register and generate code appropriately. If we need + a scratch register, use REAL_OLDEQUIV since the form of + the insn may depend on the actual address if it is + a MEM. */ + + if (second_reload_reg) + { + if (icode != CODE_FOR_nothing) + { + emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, + second_reload_reg)); + special = 1; + } + else + { + /* See if we need a scratch register to load the + intermediate register (a tertiary reload). */ + enum insn_code tertiary_icode + = reload_secondary_icode[secondary_reload]; + + if (tertiary_icode != CODE_FOR_nothing) + { + rtx third_reload_reg + = reload_reg_rtx[reload_secondary_reload[secondary_reload]]; + + emit_insn ((GEN_FCN (tertiary_icode) + (second_reload_reg, real_oldequiv, + third_reload_reg))); + } + else + gen_input_reload (second_reload_reg, oldequiv, + reload_opnum[j], + reload_when_needed[j]); + + oldequiv = second_reload_reg; + } + } + } +#endif + + if (! special) + gen_input_reload (reloadreg, oldequiv, reload_opnum[j], + reload_when_needed[j]); + +#if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P) + /* We may have to make a REG_DEAD note for the secondary reload + register in the insns we just made. Find the last insn that + mentioned the register. */ + if (! special && second_reload_reg + && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg))) + { + rtx prev; + + for (prev = get_last_insn (); prev; + prev = PREV_INSN (prev)) + if (GET_RTX_CLASS (GET_CODE (prev) == 'i') + && reg_overlap_mentioned_for_reload_p (second_reload_reg, + PATTERN (prev))) + { + REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD, + second_reload_reg, + REG_NOTES (prev)); + break; + } + } +#endif + } + + /* End this sequence. */ + *where = get_insns (); + end_sequence (); + } + + /* Add a note saying the input reload reg + dies in this insn, if anyone cares. */ +#ifdef PRESERVE_DEATH_INFO_REGNO_P + if (old != 0 + && reload_reg_rtx[j] != old + && reload_reg_rtx[j] != 0 + && reload_out[j] == 0 + && ! reload_inherited[j] + && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))) + { + register rtx reloadreg = reload_reg_rtx[j]; + +#if 0 + /* We can't abort here because we need to support this for sched.c. + It's not terrible to miss a REG_DEAD note, but we should try + to figure out how to do this correctly. */ + /* The code below is incorrect for address-only reloads. */ + if (reload_when_needed[j] != RELOAD_OTHER + && reload_when_needed[j] != RELOAD_FOR_INPUT) + abort (); +#endif + + /* Add a death note to this insn, for an input reload. */ + + if ((reload_when_needed[j] == RELOAD_OTHER + || reload_when_needed[j] == RELOAD_FOR_INPUT) + && ! dead_or_set_p (insn, reloadreg)) + REG_NOTES (insn) + = gen_rtx (EXPR_LIST, REG_DEAD, + reloadreg, REG_NOTES (insn)); + } + + /* When we inherit a reload, the last marked death of the reload reg + may no longer really be a death. */ + if (reload_reg_rtx[j] != 0 + && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])) + && reload_inherited[j]) + { + /* Handle inheriting an output reload. + Remove the death note from the output reload insn. */ + if (reload_spill_index[j] >= 0 + && GET_CODE (reload_in[j]) == REG + && spill_reg_store[reload_spill_index[j]] != 0 + && find_regno_note (spill_reg_store[reload_spill_index[j]], + REG_DEAD, REGNO (reload_reg_rtx[j]))) + remove_death (REGNO (reload_reg_rtx[j]), + spill_reg_store[reload_spill_index[j]]); + /* Likewise for input reloads that were inherited. */ + else if (reload_spill_index[j] >= 0 + && GET_CODE (reload_in[j]) == REG + && spill_reg_store[reload_spill_index[j]] == 0 + && reload_inheritance_insn[j] != 0 + && find_regno_note (reload_inheritance_insn[j], REG_DEAD, + REGNO (reload_reg_rtx[j]))) + remove_death (REGNO (reload_reg_rtx[j]), + reload_inheritance_insn[j]); + else + { + rtx prev; + + /* We got this register from find_equiv_reg. + Search back for its last death note and get rid of it. + But don't search back too far. + Don't go past a place where this reg is set, + since a death note before that remains valid. */ + for (prev = PREV_INSN (insn); + prev && GET_CODE (prev) != CODE_LABEL; + prev = PREV_INSN (prev)) + if (GET_RTX_CLASS (GET_CODE (prev)) == 'i' + && dead_or_set_p (prev, reload_reg_rtx[j])) + { + if (find_regno_note (prev, REG_DEAD, + REGNO (reload_reg_rtx[j]))) + remove_death (REGNO (reload_reg_rtx[j]), prev); + break; + } + } + } + + /* We might have used find_equiv_reg above to choose an alternate + place from which to reload. If so, and it died, we need to remove + that death and move it to one of the insns we just made. */ + + if (oldequiv_reg != 0 + && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg))) + { + rtx prev, prev1; + + for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL; + prev = PREV_INSN (prev)) + if (GET_RTX_CLASS (GET_CODE (prev)) == 'i' + && dead_or_set_p (prev, oldequiv_reg)) + { + if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg))) + { + for (prev1 = this_reload_insn; + prev1; prev1 = PREV_INSN (prev1)) + if (GET_RTX_CLASS (GET_CODE (prev1) == 'i') + && reg_overlap_mentioned_for_reload_p (oldequiv_reg, + PATTERN (prev1))) + { + REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD, + oldequiv_reg, + REG_NOTES (prev1)); + break; + } + remove_death (REGNO (oldequiv_reg), prev); + } + break; + } + } +#endif + + /* If we are reloading a register that was recently stored in with an + output-reload, see if we can prove there was + actually no need to store the old value in it. */ + + if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0 + && reload_in[j] != 0 + && GET_CODE (reload_in[j]) == REG +#if 0 + /* There doesn't seem to be any reason to restrict this to pseudos + and doing so loses in the case where we are copying from a + register of the wrong class. */ + && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER +#endif + && spill_reg_store[reload_spill_index[j]] != 0 + /* This is unsafe if some other reload uses the same reg first. */ + && reload_reg_free_before_p (spill_regs[reload_spill_index[j]], + reload_opnum[j], reload_when_needed[j]) + && dead_or_set_p (insn, reload_in[j]) + /* This is unsafe if operand occurs more than once in current + insn. Perhaps some occurrences weren't reloaded. */ + && count_occurrences (PATTERN (insn), reload_in[j]) == 1) + delete_output_reload (insn, j, + spill_reg_store[reload_spill_index[j]]); + + /* Input-reloading is done. Now do output-reloading, + storing the value from the reload-register after the main insn + if reload_out[j] is nonzero. + + ??? At some point we need to support handling output reloads of + JUMP_INSNs or insns that set cc0. */ + old = reload_out[j]; + if (old != 0 + && reload_reg_rtx[j] != old + && reload_reg_rtx[j] != 0) + { + register rtx reloadreg = reload_reg_rtx[j]; + register rtx second_reloadreg = 0; + rtx note, p; + enum machine_mode mode; + int special = 0; + + /* An output operand that dies right away does need a reload, + but need not be copied from it. Show the new location in the + REG_UNUSED note. */ + if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) + && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) + { + XEXP (note, 0) = reload_reg_rtx[j]; + continue; + } + else if (GET_CODE (old) == SCRATCH) + /* If we aren't optimizing, there won't be a REG_UNUSED note, + but we don't want to make an output reload. */ + continue; + +#if 0 + /* Strip off of OLD any size-increasing SUBREGs such as + (SUBREG:SI foo:QI 0). */ + + while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0 + && (GET_MODE_SIZE (GET_MODE (old)) + > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old))))) + old = SUBREG_REG (old); +#endif + + /* If is a JUMP_INSN, we can't support output reloads yet. */ + if (GET_CODE (insn) == JUMP_INSN) + abort (); + + push_to_sequence (output_reload_insns[reload_opnum[j]]); + + /* Determine the mode to reload in. + See comments above (for input reloading). */ + + mode = GET_MODE (old); + if (mode == VOIDmode) + { + /* VOIDmode should never happen for an output. */ + if (asm_noperands (PATTERN (insn)) < 0) + /* It's the compiler's fault. */ + abort (); + error_for_asm (insn, "output operand is constant in `asm'"); + /* Prevent crash--use something we know is valid. */ + mode = word_mode; + old = gen_rtx (REG, mode, REGNO (reloadreg)); + } + + if (GET_MODE (reloadreg) != mode) + reloadreg = gen_lowpart_common (mode, reloadreg); + +#ifdef SECONDARY_OUTPUT_RELOAD_CLASS + + /* If we need two reload regs, set RELOADREG to the intermediate + one, since it will be stored into OUT. We might need a secondary + register only for an input reload, so check again here. */ + + if (reload_secondary_reload[j] >= 0) + { + rtx real_old = old; + + if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER + && reg_equiv_mem[REGNO (old)] != 0) + real_old = reg_equiv_mem[REGNO (old)]; + + if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j], + mode, real_old) + != NO_REGS)) + { + second_reloadreg = reloadreg; + reloadreg = reload_reg_rtx[reload_secondary_reload[j]]; + + /* See if RELOADREG is to be used as a scratch register + or as an intermediate register. */ + if (reload_secondary_icode[j] != CODE_FOR_nothing) + { + emit_insn ((GEN_FCN (reload_secondary_icode[j]) + (real_old, second_reloadreg, reloadreg))); + special = 1; + } + else + { + /* See if we need both a scratch and intermediate reload + register. */ + int secondary_reload = reload_secondary_reload[j]; + enum insn_code tertiary_icode + = reload_secondary_icode[secondary_reload]; + rtx pat; + + if (GET_MODE (reloadreg) != mode) + reloadreg = gen_rtx (REG, mode, REGNO (reloadreg)); + + if (tertiary_icode != CODE_FOR_nothing) + { + rtx third_reloadreg + = reload_reg_rtx[reload_secondary_reload[secondary_reload]]; + pat = (GEN_FCN (tertiary_icode) + (reloadreg, second_reloadreg, third_reloadreg)); + } +#ifdef SECONDARY_MEMORY_NEEDED + /* If we need a memory location to do the move, do it that way. */ + else if (GET_CODE (reloadreg) == REG + && REGNO (reloadreg) < FIRST_PSEUDO_REGISTER + && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg)), + REGNO_REG_CLASS (REGNO (second_reloadreg)), + GET_MODE (second_reloadreg))) + { + /* Get the memory to use and rewrite both registers + to its mode. */ + rtx loc + = get_secondary_mem (reloadreg, + GET_MODE (second_reloadreg), + reload_opnum[j], + reload_when_needed[j]); + rtx tmp_reloadreg; + + if (GET_MODE (loc) != GET_MODE (second_reloadreg)) + second_reloadreg = gen_rtx (REG, GET_MODE (loc), + REGNO (second_reloadreg)); + + if (GET_MODE (loc) != GET_MODE (reloadreg)) + tmp_reloadreg = gen_rtx (REG, GET_MODE (loc), + REGNO (reloadreg)); + else + tmp_reloadreg = reloadreg; + + emit_move_insn (loc, second_reloadreg); + pat = gen_move_insn (tmp_reloadreg, loc); + } +#endif + else + pat = gen_move_insn (reloadreg, second_reloadreg); + + emit_insn (pat); + } + } + } +#endif + + /* Output the last reload insn. */ + if (! special) + { +#ifdef SECONDARY_MEMORY_NEEDED + /* If we need a memory location to do the move, do it that way. */ + if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER + && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)), + REGNO_REG_CLASS (REGNO (reloadreg)), + GET_MODE (reloadreg))) + { + /* Get the memory to use and rewrite both registers to + its mode. */ + rtx loc = get_secondary_mem (old, GET_MODE (reloadreg), + reload_opnum[j], + reload_when_needed[j]); + + if (GET_MODE (loc) != GET_MODE (reloadreg)) + reloadreg = gen_rtx (REG, GET_MODE (loc), + REGNO (reloadreg)); + + if (GET_MODE (loc) != GET_MODE (old)) + old = gen_rtx (REG, GET_MODE (loc), REGNO (old)); + + emit_insn (gen_move_insn (loc, reloadreg)); + emit_insn (gen_move_insn (old, loc)); + } + else +#endif + emit_insn (gen_move_insn (old, reloadreg)); + } + +#ifdef PRESERVE_DEATH_INFO_REGNO_P + /* If final will look at death notes for this reg, + put one on the last output-reload insn to use it. Similarly + for any secondary register. */ + if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg))) + for (p = get_last_insn (); p; p = PREV_INSN (p)) + if (GET_RTX_CLASS (GET_CODE (p)) == 'i' + && reg_overlap_mentioned_for_reload_p (reloadreg, + PATTERN (p))) + REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD, + reloadreg, REG_NOTES (p)); + +#ifdef SECONDARY_OUTPUT_RELOAD_CLASS + if (! special + && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg))) + for (p = get_last_insn (); p; p = PREV_INSN (p)) + if (GET_RTX_CLASS (GET_CODE (p)) == 'i' + && reg_overlap_mentioned_for_reload_p (second_reloadreg, + PATTERN (p))) + REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD, + second_reloadreg, REG_NOTES (p)); +#endif +#endif + /* Look at all insns we emitted, just to be safe. */ + for (p = get_insns (); p; p = NEXT_INSN (p)) + if (GET_RTX_CLASS (GET_CODE (p)) == 'i') + { + /* If this output reload doesn't come from a spill reg, + clear any memory of reloaded copies of the pseudo reg. + If this output reload comes from a spill reg, + reg_has_output_reload will make this do nothing. */ + note_stores (PATTERN (p), forget_old_reloads_1); + + if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p))) + store_insn = p; + } + + output_reload_insns[reload_opnum[j]] = get_insns (); + end_sequence (); + + } + + if (reload_spill_index[j] >= 0) + new_spill_reg_store[reload_spill_index[j]] = store_insn; + } + + /* Now write all the insns we made for reloads in the order expected by + the allocation functions. Prior to the insn being reloaded, we write + the following reloads: + + RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. + + RELOAD_OTHER reloads. + + For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by + the RELOAD_FOR_INPUT reload for the operand. + + RELOAD_FOR_OPERAND_ADDRESS reloads. + + After the insn being reloaded, we write the following: + + For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by + the RELOAD_FOR_OUTPUT reload for that operand. */ + + emit_insns_before (other_input_address_reload_insns, before_insn); + emit_insns_before (other_input_reload_insns, before_insn); + + for (j = 0; j < reload_n_operands; j++) + { + emit_insns_before (input_address_reload_insns[j], before_insn); + emit_insns_before (input_reload_insns[j], before_insn); + } + + emit_insns_before (operand_reload_insns, before_insn); + + for (j = 0; j < reload_n_operands; j++) + { + emit_insns_before (output_address_reload_insns[j], following_insn); + emit_insns_before (output_reload_insns[j], following_insn); + } + + /* Move death notes from INSN + to output-operand-address and output reload insns. */ +#ifdef PRESERVE_DEATH_INFO_REGNO_P + { + rtx insn1; + /* Loop over those insns, last ones first. */ + for (insn1 = PREV_INSN (following_insn); insn1 != insn; + insn1 = PREV_INSN (insn1)) + if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET) + { + rtx source = SET_SRC (PATTERN (insn1)); + rtx dest = SET_DEST (PATTERN (insn1)); + + /* The note we will examine next. */ + rtx reg_notes = REG_NOTES (insn); + /* The place that pointed to this note. */ + rtx *prev_reg_note = ®_NOTES (insn); + + /* If the note is for something used in the source of this + reload insn, or in the output address, move the note. */ + while (reg_notes) + { + rtx next_reg_notes = XEXP (reg_notes, 1); + if (REG_NOTE_KIND (reg_notes) == REG_DEAD + && GET_CODE (XEXP (reg_notes, 0)) == REG + && ((GET_CODE (dest) != REG + && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0), + dest)) + || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0), + source))) + { + *prev_reg_note = next_reg_notes; + XEXP (reg_notes, 1) = REG_NOTES (insn1); + REG_NOTES (insn1) = reg_notes; + } + else + prev_reg_note = &XEXP (reg_notes, 1); + + reg_notes = next_reg_notes; + } + } + } +#endif + + /* For all the spill regs newly reloaded in this instruction, + record what they were reloaded from, so subsequent instructions + can inherit the reloads. + + Update spill_reg_store for the reloads of this insn. + Copy the elements that were updated in the loop above. */ + + for (j = 0; j < n_reloads; j++) + { + register int r = reload_order[j]; + register int i = reload_spill_index[r]; + + /* I is nonneg if this reload used one of the spill regs. + If reload_reg_rtx[r] is 0, this is an optional reload + that we opted to ignore. + + Also ignore reloads that don't reach the end of the insn, + since we will eventually see the one that does. */ + + if (i >= 0 && reload_reg_rtx[r] != 0 + && reload_reg_reaches_end_p (spill_regs[i], reload_opnum[r], + reload_when_needed[r])) + { + /* First, clear out memory of what used to be in this spill reg. + If consecutive registers are used, clear them all. */ + int nr + = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r])); + int k; + + for (k = 0; k < nr; k++) + { + reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1; + reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0; + } + + /* Maybe the spill reg contains a copy of reload_out. */ + if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG) + { + register int nregno = REGNO (reload_out[r]); + int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 + : HARD_REGNO_NREGS (nregno, + GET_MODE (reload_reg_rtx[r]))); + + spill_reg_store[i] = new_spill_reg_store[i]; + reg_last_reload_reg[nregno] = reload_reg_rtx[r]; + + /* If NREGNO is a hard register, it may occupy more than + one register. If it does, say what is in the + rest of the registers assuming that both registers + agree on how many words the object takes. If not, + invalidate the subsequent registers. */ + + if (nregno < FIRST_PSEUDO_REGISTER) + for (k = 1; k < nnr; k++) + reg_last_reload_reg[nregno + k] + = (nr == nnr ? gen_rtx (REG, word_mode, + REGNO (reload_reg_rtx[r]) + k) + : 0); + + /* Now do the inverse operation. */ + for (k = 0; k < nr; k++) + { + reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] + = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno + : nregno + k); + reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn; + } + } + + /* Maybe the spill reg contains a copy of reload_in. Only do + something if there will not be an output reload for + the register being reloaded. */ + else if (reload_out[r] == 0 + && reload_in[r] != 0 + && ((GET_CODE (reload_in[r]) == REG + && ! reg_has_output_reload[REGNO (reload_in[r])] + || (GET_CODE (reload_in_reg[r]) == REG + && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))) + { + register int nregno; + int nnr; + + if (GET_CODE (reload_in[r]) == REG) + nregno = REGNO (reload_in[r]); + else + nregno = REGNO (reload_in_reg[r]); + + nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 + : HARD_REGNO_NREGS (nregno, + GET_MODE (reload_reg_rtx[r]))); + + reg_last_reload_reg[nregno] = reload_reg_rtx[r]; + + if (nregno < FIRST_PSEUDO_REGISTER) + for (k = 1; k < nnr; k++) + reg_last_reload_reg[nregno + k] + = (nr == nnr ? gen_rtx (REG, word_mode, + REGNO (reload_reg_rtx[r]) + k) + : 0); + + /* Unless we inherited this reload, show we haven't + recently done a store. */ + if (! reload_inherited[r]) + spill_reg_store[i] = 0; + + for (k = 0; k < nr; k++) + { + reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] + = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno + : nregno + k); + reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] + = insn; + } + } + } + + /* The following if-statement was #if 0'd in 1.34 (or before...). + It's reenabled in 1.35 because supposedly nothing else + deals with this problem. */ + + /* If a register gets output-reloaded from a non-spill register, + that invalidates any previous reloaded copy of it. + But forget_old_reloads_1 won't get to see it, because + it thinks only about the original insn. So invalidate it here. */ + if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG) + { + register int nregno = REGNO (reload_out[r]); + reg_last_reload_reg[nregno] = 0; + } + } +} + +/* Emit code to perform an input reload of IN to RELOADREG. IN is from + operand OPNUM with reload type TYPE. + + Returns first insn emitted. */ + +rtx +gen_input_reload (reloadreg, in, opnum, type) + rtx reloadreg; + rtx in; + int opnum; + enum reload_type type; +{ + rtx last = get_last_insn (); + + /* How to do this reload can get quite tricky. Normally, we are being + asked to reload a simple operand, such as a MEM, a constant, or a pseudo + register that didn't get a hard register. In that case we can just + call emit_move_insn. + + We can also be asked to reload a PLUS that adds either two registers, or + a register and a constant or MEM, or a MEM and a constant. This can + occur during frame pointer elimination and while reloading addresses. + This case is handled by trying to emit a single insn + to perform the add. If it is not valid, we use a two insn sequence. + + Finally, we could be called to handle an 'o' constraint by putting + an address into a register. In that case, we first try to do this + with a named pattern of "reload_load_address". If no such pattern + exists, we just emit a SET insn and hope for the best (it will normally + be valid on machines that use 'o'). + + This entire process is made complex because reload will never + process the insns we generate here and so we must ensure that + they will fit their constraints and also by the fact that parts of + IN might be being reloaded separately and replaced with spill registers. + Because of this, we are, in some sense, just guessing the right approach + here. The one listed above seems to work. + + ??? At some point, this whole thing needs to be rethought. */ + + if (GET_CODE (in) == PLUS + && ((GET_CODE (XEXP (in, 0)) == REG + && (GET_CODE (XEXP (in, 1)) == REG + || CONSTANT_P (XEXP (in, 1)) + || GET_CODE (XEXP (in, 1)) == MEM)) + || (GET_CODE (XEXP (in, 0)) == MEM + && CONSTANT_P (XEXP (in, 1))))) + { + /* We need to compute the sum of what is either a register and a + constant, a register and memory, a hard register and a pseudo + register, or memory and a constant and put it into the reload + register. The best possible way of doing this is if the machine + has a three-operand ADD insn that accepts the required operands. + + The simplest approach is to try to generate such an insn and see if it + is recognized and matches its constraints. If so, it can be used. + + It might be better not to actually emit the insn unless it is valid, + but we need to pass the insn as an operand to `recog' and + `insn_extract' and it is simpler to emit and then delete the insn if + not valid than to dummy things up. */ + + rtx op0, op1, tem, insn; + int code; + + op0 = find_replacement (&XEXP (in, 0)); + op1 = find_replacement (&XEXP (in, 1)); + + /* Since constraint checking is strict, commutativity won't be + checked, so we need to do that here to avoid spurious failure + if the add instruction is two-address and the second operand + of the add is the same as the reload reg, which is frequently + the case. If the insn would be A = B + A, rearrange it so + it will be A = A + B as constrain_operands expects. */ + + if (GET_CODE (XEXP (in, 1)) == REG + && REGNO (reloadreg) == REGNO (XEXP (in, 1))) + tem = op0, op0 = op1, op1 = tem; + + if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) + in = gen_rtx (PLUS, GET_MODE (in), op0, op1); + + insn = emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in)); + code = recog_memoized (insn); + + if (code >= 0) + { + insn_extract (insn); + /* We want constrain operands to treat this insn strictly in + its validity determination, i.e., the way it would after reload + has completed. */ + if (constrain_operands (code, 1)) + return insn; + } + + delete_insns_since (last); + + /* If that failed, we must use a conservative two-insn sequence. + use move to copy constant, MEM, or pseudo register to the reload + register since "move" will be able to handle an arbitrary operand, + unlike add which can't, in general. Then add the registers. + + If there is another way to do this for a specific machine, a + DEFINE_PEEPHOLE should be specified that recognizes the sequence + we emit below. */ + + if (CONSTANT_P (op1) || GET_CODE (op1) == MEM + || (GET_CODE (op1) == REG + && REGNO (op1) >= FIRST_PSEUDO_REGISTER)) + tem = op0, op0 = op1, op1 = tem; + + emit_insn (gen_move_insn (reloadreg, op0)); + + /* If OP0 and OP1 are the same, we can use RELOADREG for OP1. + This fixes a problem on the 32K where the stack pointer cannot + be used as an operand of an add insn. */ + + if (rtx_equal_p (op0, op1)) + op1 = reloadreg; + + emit_insn (gen_add2_insn (reloadreg, op1)); + } + +#ifdef SECONDARY_MEMORY_NEEDED + /* If we need a memory location to do the move, do it that way. */ + else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER + && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), + REGNO_REG_CLASS (REGNO (reloadreg)), + GET_MODE (reloadreg))) + { + /* Get the memory to use and rewrite both registers to its mode. */ + rtx loc = get_secondary_mem (in, GET_MODE (reloadreg), opnum, type); + + if (GET_MODE (loc) != GET_MODE (reloadreg)) + reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg)); + + if (GET_MODE (loc) != GET_MODE (in)) + in = gen_rtx (REG, GET_MODE (loc), REGNO (in)); + + emit_insn (gen_move_insn (loc, in)); + emit_insn (gen_move_insn (reloadreg, loc)); + } +#endif + + /* If IN is a simple operand, use gen_move_insn. */ + else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) + emit_insn (gen_move_insn (reloadreg, in)); + +#ifdef HAVE_reload_load_address + else if (HAVE_reload_load_address) + emit_insn (gen_reload_load_address (reloadreg, in)); +#endif + + /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */ + else + emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in)); + + /* Return the first insn emitted. + We can not just return get_last_insn, because there may have + been multiple instructions emitted. Also note that gen_move_insn may + emit more than one insn itself, so we can not assume that there is one + insn emitted per emit_insn_before call. */ + + return last ? NEXT_INSN (last) : get_insns (); +} + +/* Delete a previously made output-reload + whose result we now believe is not needed. + First we double-check. + + INSN is the insn now being processed. + OUTPUT_RELOAD_INSN is the insn of the output reload. + J is the reload-number for this insn. */ + +static void +delete_output_reload (insn, j, output_reload_insn) + rtx insn; + int j; + rtx output_reload_insn; +{ + register rtx i1; + + /* Get the raw pseudo-register referred to. */ + + rtx reg = reload_in[j]; + while (GET_CODE (reg) == SUBREG) + reg = SUBREG_REG (reg); + + /* If the pseudo-reg we are reloading is no longer referenced + anywhere between the store into it and here, + and no jumps or labels intervene, then the value can get + here through the reload reg alone. + Otherwise, give up--return. */ + for (i1 = NEXT_INSN (output_reload_insn); + i1 != insn; i1 = NEXT_INSN (i1)) + { + if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) + return; + if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) + && reg_mentioned_p (reg, PATTERN (i1))) + return; + } + + if (cannot_omit_stores[REGNO (reg)]) + return; + + /* If this insn will store in the pseudo again, + the previous store can be removed. */ + if (reload_out[j] == reload_in[j]) + delete_insn (output_reload_insn); + + /* See if the pseudo reg has been completely replaced + with reload regs. If so, delete the store insn + and forget we had a stack slot for the pseudo. */ + else if (reg_n_deaths[REGNO (reg)] == 1 + && reg_basic_block[REGNO (reg)] >= 0 + && find_regno_note (insn, REG_DEAD, REGNO (reg))) + { + rtx i2; + + /* We know that it was used only between here + and the beginning of the current basic block. + (We also know that the last use before INSN was + the output reload we are thinking of deleting, but never mind that.) + Search that range; see if any ref remains. */ + for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) + { + rtx set = single_set (i2); + + /* Uses which just store in the pseudo don't count, + since if they are the only uses, they are dead. */ + if (set != 0 && SET_DEST (set) == reg) + continue; + if (GET_CODE (i2) == CODE_LABEL + || GET_CODE (i2) == JUMP_INSN) + break; + if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) + && reg_mentioned_p (reg, PATTERN (i2))) + /* Some other ref remains; + we can't do anything. */ + return; + } + + /* Delete the now-dead stores into this pseudo. */ + for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) + { + rtx set = single_set (i2); + + if (set != 0 && SET_DEST (set) == reg) + delete_insn (i2); + if (GET_CODE (i2) == CODE_LABEL + || GET_CODE (i2) == JUMP_INSN) + break; + } + + /* For the debugging info, + say the pseudo lives in this reload reg. */ + reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]); + alter_reg (REGNO (reg), -1); + } +} + +/* Output reload-insns to reload VALUE into RELOADREG. + VALUE is an autoincrement or autodecrement RTX whose operand + is a register or memory location; + so reloading involves incrementing that location. + + INC_AMOUNT is the number to increment or decrement by (always positive). + This cannot be deduced from VALUE. */ + +static void +inc_for_reload (reloadreg, value, inc_amount) + rtx reloadreg; + rtx value; + int inc_amount; +{ + /* REG or MEM to be copied and incremented. */ + rtx incloc = XEXP (value, 0); + /* Nonzero if increment after copying. */ + int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); + rtx last; + rtx inc; + rtx add_insn; + int code; + + /* No hard register is equivalent to this register after + inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, + we could inc/dec that register as well (maybe even using it for + the source), but I'm not sure it's worth worrying about. */ + if (GET_CODE (incloc) == REG) + reg_last_reload_reg[REGNO (incloc)] = 0; + + if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) + inc_amount = - inc_amount; + + inc = GEN_INT (inc_amount); + + /* If this is post-increment, first copy the location to the reload reg. */ + if (post) + emit_insn (gen_move_insn (reloadreg, incloc)); + + /* See if we can directly increment INCLOC. Use a method similar to that + in gen_input_reload. */ + + last = get_last_insn (); + add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc, + gen_rtx (PLUS, GET_MODE (incloc), + incloc, inc))); + + code = recog_memoized (add_insn); + if (code >= 0) + { + insn_extract (add_insn); + if (constrain_operands (code, 1)) + { + /* If this is a pre-increment and we have incremented the value + where it lives, copy the incremented value to RELOADREG to + be used as an address. */ + + if (! post) + emit_insn (gen_move_insn (reloadreg, incloc)); + + return; + } + } + + delete_insns_since (last); + + /* If couldn't do the increment directly, must increment in RELOADREG. + The way we do this depends on whether this is pre- or post-increment. + For pre-increment, copy INCLOC to the reload register, increment it + there, then save back. */ + + if (! post) + { + emit_insn (gen_move_insn (reloadreg, incloc)); + emit_insn (gen_add2_insn (reloadreg, inc)); + emit_insn (gen_move_insn (incloc, reloadreg)); + } + else + { + /* Postincrement. + Because this might be a jump insn or a compare, and because RELOADREG + may not be available after the insn in an input reload, we must do + the incrementation before the insn being reloaded for. + + We have already copied INCLOC to RELOADREG. Increment the copy in + RELOADREG, save that back, then decrement RELOADREG so it has + the original value. */ + + emit_insn (gen_add2_insn (reloadreg, inc)); + emit_insn (gen_move_insn (incloc, reloadreg)); + emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); + } + + return; +} + +/* Return 1 if we are certain that the constraint-string STRING allows + the hard register REG. Return 0 if we can't be sure of this. */ + +static int +constraint_accepts_reg_p (string, reg) + char *string; + rtx reg; +{ + int value = 0; + int regno = true_regnum (reg); + int c; + + /* Initialize for first alternative. */ + value = 0; + /* Check that each alternative contains `g' or `r'. */ + while (1) + switch (c = *string++) + { + case 0: + /* If an alternative lacks `g' or `r', we lose. */ + return value; + case ',': + /* If an alternative lacks `g' or `r', we lose. */ + if (value == 0) + return 0; + /* Initialize for next alternative. */ + value = 0; + break; + case 'g': + case 'r': + /* Any general reg wins for this alternative. */ + if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) + value = 1; + break; + default: + /* Any reg in specified class wins for this alternative. */ + { + enum reg_class class = REG_CLASS_FROM_LETTER (c); + + if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)) + value = 1; + } + } +} + +/* Return the number of places FIND appears within X, but don't count + an occurrence if some SET_DEST is FIND. */ + +static int +count_occurrences (x, find) + register rtx x, find; +{ + register int i, j; + register enum rtx_code code; + register char *format_ptr; + int count; + + if (x == find) + return 1; + if (x == 0) + return 0; + + code = GET_CODE (x); + + switch (code) + { + case REG: + case QUEUED: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CODE_LABEL: + case PC: + case CC0: + return 0; + + case SET: + if (SET_DEST (x) == find) + return count_occurrences (SET_SRC (x), find); + break; + } + + format_ptr = GET_RTX_FORMAT (code); + count = 0; + + for (i = 0; i < GET_RTX_LENGTH (code); i++) + { + switch (*format_ptr++) + { + case 'e': + count += count_occurrences (XEXP (x, i), find); + break; + + case 'E': + if (XVEC (x, i) != NULL) + { + for (j = 0; j < XVECLEN (x, i); j++) + count += count_occurrences (XVECEXP (x, i, j), find); + } + break; + } + } + return count; +} diff --git a/gnu/usr.bin/cc/lib/reorg.c b/gnu/usr.bin/cc/lib/reorg.c new file mode 100644 index 000000000000..3b6b20585d3f --- /dev/null +++ b/gnu/usr.bin/cc/lib/reorg.c @@ -0,0 +1,4115 @@ +/* Perform instruction reorganizations for delay slot filling. + Copyright (C) 1992, 1993 Free Software Foundation, Inc. + Contributed by Richard Kenner (kenner@nyu.edu). + Hacked by Michael Tiemann (tiemann@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Instruction reorganization pass. + + This pass runs after register allocation and final jump + optimization. It should be the last pass to run before peephole. + It serves primarily to fill delay slots of insns, typically branch + and call insns. Other insns typically involve more complicated + interactions of data dependencies and resource constraints, and + are better handled by scheduling before register allocation (by the + function `schedule_insns'). + + The Branch Penalty is the number of extra cycles that are needed to + execute a branch insn. On an ideal machine, branches take a single + cycle, and the Branch Penalty is 0. Several RISC machines approach + branch delays differently: + + The MIPS and AMD 29000 have a single branch delay slot. Most insns + (except other branches) can be used to fill this slot. When the + slot is filled, two insns execute in two cycles, reducing the + branch penalty to zero. + + The Motorola 88000 conditionally exposes its branch delay slot, + so code is shorter when it is turned off, but will run faster + when useful insns are scheduled there. + + The IBM ROMP has two forms of branch and call insns, both with and + without a delay slot. Much like the 88k, insns not using the delay + slot can be shorted (2 bytes vs. 4 bytes), but will run slowed. + + The SPARC always has a branch delay slot, but its effects can be + annulled when the branch is not taken. This means that failing to + find other sources of insns, we can hoist an insn from the branch + target that would only be safe to execute knowing that the branch + is taken. + + The HP-PA always has a branch delay slot. For unconditional branches + its effects can be annulled when the branch is taken. The effects + of the delay slot in a conditional branch can be nullified for forward + taken branches, or for untaken backward branches. This means + we can hoist insns from the fall-through path for forward branches or + steal insns from the target of backward branches. + + Three techniques for filling delay slots have been implemented so far: + + (1) `fill_simple_delay_slots' is the simplest, most efficient way + to fill delay slots. This pass first looks for insns which come + from before the branch and which are safe to execute after the + branch. Then it searches after the insn requiring delay slots or, + in the case of a branch, for insns that are after the point at + which the branch merges into the fallthrough code, if such a point + exists. When such insns are found, the branch penalty decreases + and no code expansion takes place. + + (2) `fill_eager_delay_slots' is more complicated: it is used for + scheduling conditional jumps, or for scheduling jumps which cannot + be filled using (1). A machine need not have annulled jumps to use + this strategy, but it helps (by keeping more options open). + `fill_eager_delay_slots' tries to guess the direction the branch + will go; if it guesses right 100% of the time, it can reduce the + branch penalty as much as `fill_simple_delay_slots' does. If it + guesses wrong 100% of the time, it might as well schedule nops (or + on the m88k, unexpose the branch slot). When + `fill_eager_delay_slots' takes insns from the fall-through path of + the jump, usually there is no code expansion; when it takes insns + from the branch target, there is code expansion if it is not the + only way to reach that target. + + (3) `relax_delay_slots' uses a set of rules to simplify code that + has been reorganized by (1) and (2). It finds cases where + conditional test can be eliminated, jumps can be threaded, extra + insns can be eliminated, etc. It is the job of (1) and (2) to do a + good job of scheduling locally; `relax_delay_slots' takes care of + making the various individual schedules work well together. It is + especially tuned to handle the control flow interactions of branch + insns. It does nothing for insns with delay slots that do not + branch. + + On machines that use CC0, we are very conservative. We will not make + a copy of an insn involving CC0 since we want to maintain a 1-1 + correspondence between the insn that sets and uses CC0. The insns are + allowed to be separated by placing an insn that sets CC0 (but not an insn + that uses CC0; we could do this, but it doesn't seem worthwhile) in a + delay slot. In that case, we point each insn at the other with REG_CC_USER + and REG_CC_SETTER notes. Note that these restrictions affect very few + machines because most RISC machines with delay slots will not use CC0 + (the RT is the only known exception at this point). + + Not yet implemented: + + The Acorn Risc Machine can conditionally execute most insns, so + it is profitable to move single insns into a position to execute + based on the condition code of the previous insn. + + The HP-PA can conditionally nullify insns, providing a similar + effect to the ARM, differing mostly in which insn is "in charge". */ + +#include +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "conditions.h" +#include "hard-reg-set.h" +#include "basic-block.h" +#include "regs.h" +#include "insn-flags.h" +#include "recog.h" +#include "flags.h" +#include "output.h" +#include "obstack.h" +#include "insn-attr.h" + +#ifdef DELAY_SLOTS + +#define obstack_chunk_alloc xmalloc +#define obstack_chunk_free free + +#ifndef ANNUL_IFTRUE_SLOTS +#define eligible_for_annul_true(INSN, SLOTS, TRIAL, FLAGS) 0 +#endif +#ifndef ANNUL_IFFALSE_SLOTS +#define eligible_for_annul_false(INSN, SLOTS, TRIAL, FLAGS) 0 +#endif + +/* Insns which have delay slots that have not yet been filled. */ + +static struct obstack unfilled_slots_obstack; +static rtx *unfilled_firstobj; + +/* Define macros to refer to the first and last slot containing unfilled + insns. These are used because the list may move and its address + should be recomputed at each use. */ + +#define unfilled_slots_base \ + ((rtx *) obstack_base (&unfilled_slots_obstack)) + +#define unfilled_slots_next \ + ((rtx *) obstack_next_free (&unfilled_slots_obstack)) + +/* This structure is used to indicate which hardware resources are set or + needed by insns so far. */ + +struct resources +{ + char memory; /* Insn sets or needs a memory location. */ + char volatil; /* Insn sets or needs a volatile memory loc. */ + char cc; /* Insn sets or needs the condition codes. */ + HARD_REG_SET regs; /* Which registers are set or needed. */ +}; + +/* Macro to clear all resources. */ +#define CLEAR_RESOURCE(RES) \ + do { (RES)->memory = (RES)->volatil = (RES)->cc = 0; \ + CLEAR_HARD_REG_SET ((RES)->regs); } while (0) + +/* Indicates what resources are required at the beginning of the epilogue. */ +static struct resources start_of_epilogue_needs; + +/* Indicates what resources are required at function end. */ +static struct resources end_of_function_needs; + +/* Points to the label before the end of the function. */ +static rtx end_of_function_label; + +/* This structure is used to record liveness information at the targets or + fallthrough insns of branches. We will most likely need the information + at targets again, so save them in a hash table rather than recomputing them + each time. */ + +struct target_info +{ + int uid; /* INSN_UID of target. */ + struct target_info *next; /* Next info for same hash bucket. */ + HARD_REG_SET live_regs; /* Registers live at target. */ + int block; /* Basic block number containing target. */ + int bb_tick; /* Generation count of basic block info. */ +}; + +#define TARGET_HASH_PRIME 257 + +/* Define the hash table itself. */ +static struct target_info **target_hash_table; + +/* For each basic block, we maintain a generation number of its basic + block info, which is updated each time we move an insn from the + target of a jump. This is the generation number indexed by block + number. */ + +static int *bb_ticks; + +/* Mapping between INSN_UID's and position in the code since INSN_UID's do + not always monotonically increase. */ +static int *uid_to_ruid; + +/* Highest valid index in `uid_to_ruid'. */ +static int max_uid; + +static void mark_referenced_resources PROTO((rtx, struct resources *, int)); +static void mark_set_resources PROTO((rtx, struct resources *, int, int)); +static int stop_search_p PROTO((rtx, int)); +static int resource_conflicts_p PROTO((struct resources *, + struct resources *)); +static int insn_references_resource_p PROTO((rtx, struct resources *, int)); +static int insn_sets_resources_p PROTO((rtx, struct resources *, int)); +static rtx find_end_label PROTO((void)); +static rtx emit_delay_sequence PROTO((rtx, rtx, int, int)); +static rtx add_to_delay_list PROTO((rtx, rtx)); +static void delete_from_delay_slot PROTO((rtx)); +static void delete_scheduled_jump PROTO((rtx)); +static void note_delay_statistics PROTO((int, int)); +static rtx optimize_skip PROTO((rtx)); +static int get_jump_flags PROTO((rtx, rtx)); +static int rare_destination PROTO((rtx)); +static int mostly_true_jump PROTO((rtx, rtx)); +static rtx get_branch_condition PROTO((rtx, rtx)); +static int condition_dominates_p PROTO((rtx, rtx)); +static rtx steal_delay_list_from_target PROTO((rtx, rtx, rtx, rtx, + struct resources *, + struct resources *, + struct resources *, + int, int *, int *, rtx *)); +static rtx steal_delay_list_from_fallthrough PROTO((rtx, rtx, rtx, rtx, + struct resources *, + struct resources *, + struct resources *, + int, int *, int *)); +static void try_merge_delay_insns PROTO((rtx, rtx)); +static int redundant_insn_p PROTO((rtx, rtx, rtx)); +static int own_thread_p PROTO((rtx, rtx, int)); +static int find_basic_block PROTO((rtx)); +static void update_block PROTO((rtx, rtx)); +static int reorg_redirect_jump PROTO((rtx, rtx)); +static void update_reg_dead_notes PROTO((rtx, rtx)); +static void update_live_status PROTO((rtx, rtx)); +static rtx next_insn_no_annul PROTO((rtx)); +static void mark_target_live_regs PROTO((rtx, struct resources *)); +static void fill_simple_delay_slots PROTO((rtx, int)); +static rtx fill_slots_from_thread PROTO((rtx, rtx, rtx, rtx, int, int, + int, int, int, int *)); +static void fill_eager_delay_slots PROTO((rtx)); +static void relax_delay_slots PROTO((rtx)); +static void make_return_insns PROTO((rtx)); + +/* Given X, some rtl, and RES, a pointer to a `struct resource', mark + which resources are references by the insn. If INCLUDE_CALLED_ROUTINE + is TRUE, resources used by the called routine will be included for + CALL_INSNs. */ + +static void +mark_referenced_resources (x, res, include_delayed_effects) + register rtx x; + register struct resources *res; + register int include_delayed_effects; +{ + register enum rtx_code code = GET_CODE (x); + register int i, j; + register char *format_ptr; + + /* Handle leaf items for which we set resource flags. Also, special-case + CALL, SET and CLOBBER operators. */ + switch (code) + { + case CONST: + case CONST_INT: + case CONST_DOUBLE: + case PC: + case SYMBOL_REF: + case LABEL_REF: + return; + + case SUBREG: + if (GET_CODE (SUBREG_REG (x)) != REG) + mark_referenced_resources (SUBREG_REG (x), res, 0); + else + { + int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); + int last_regno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); + for (i = regno; i < last_regno; i++) + SET_HARD_REG_BIT (res->regs, i); + } + return; + + case REG: + for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++) + SET_HARD_REG_BIT (res->regs, REGNO (x) + i); + return; + + case MEM: + /* If this memory shouldn't change, it really isn't referencing + memory. */ + if (! RTX_UNCHANGING_P (x)) + res->memory = 1; + res->volatil = MEM_VOLATILE_P (x); + + /* Mark registers used to access memory. */ + mark_referenced_resources (XEXP (x, 0), res, 0); + return; + + case CC0: + res->cc = 1; + return; + + case UNSPEC_VOLATILE: + case ASM_INPUT: + /* Traditional asm's are always volatile. */ + res->volatil = 1; + return; + + case ASM_OPERANDS: + res->volatil = MEM_VOLATILE_P (x); + + /* For all ASM_OPERANDS, we must traverse the vector of input operands. + We can not just fall through here since then we would be confused + by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate + traditional asms unlike their normal usage. */ + + for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) + mark_referenced_resources (ASM_OPERANDS_INPUT (x, i), res, 0); + return; + + case CALL: + /* The first operand will be a (MEM (xxx)) but doesn't really reference + memory. The second operand may be referenced, though. */ + mark_referenced_resources (XEXP (XEXP (x, 0), 0), res, 0); + mark_referenced_resources (XEXP (x, 1), res, 0); + return; + + case SET: + /* Usually, the first operand of SET is set, not referenced. But + registers used to access memory are referenced. SET_DEST is + also referenced if it is a ZERO_EXTRACT or SIGN_EXTRACT. */ + + mark_referenced_resources (SET_SRC (x), res, 0); + + x = SET_DEST (x); + if (GET_CODE (x) == SIGN_EXTRACT || GET_CODE (x) == ZERO_EXTRACT) + mark_referenced_resources (x, res, 0); + else if (GET_CODE (x) == SUBREG) + x = SUBREG_REG (x); + if (GET_CODE (x) == MEM) + mark_referenced_resources (XEXP (x, 0), res, 0); + return; + + case CLOBBER: + return; + + case CALL_INSN: + if (include_delayed_effects) + { + /* A CALL references memory, the frame pointer if it exists, the + stack pointer, any global registers and any registers given in + USE insns immediately in front of the CALL. + + However, we may have moved some of the parameter loading insns + into the delay slot of this CALL. If so, the USE's for them + don't count and should be skipped. */ + rtx insn = PREV_INSN (x); + rtx sequence = 0; + int seq_size = 0; + int i; + + /* If we are part of a delay slot sequence, point at the SEQUENCE. */ + if (NEXT_INSN (insn) != x) + { + sequence = PATTERN (NEXT_INSN (insn)); + seq_size = XVECLEN (sequence, 0); + if (GET_CODE (sequence) != SEQUENCE) + abort (); + } + + res->memory = 1; + SET_HARD_REG_BIT (res->regs, STACK_POINTER_REGNUM); + if (frame_pointer_needed) + SET_HARD_REG_BIT (res->regs, FRAME_POINTER_REGNUM); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (global_regs[i]) + SET_HARD_REG_BIT (res->regs, i); + + /* Skip any labels between the CALL_INSN and possible USE insns. */ + while (GET_CODE (insn) == CODE_LABEL) + insn = PREV_INSN (insn); + + for ( ; (insn && GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == USE); + insn = PREV_INSN (insn)) + { + for (i = 1; i < seq_size; i++) + { + rtx slot_pat = PATTERN (XVECEXP (sequence, 0, i)); + if (GET_CODE (slot_pat) == SET + && rtx_equal_p (SET_DEST (slot_pat), + XEXP (PATTERN (insn), 0))) + break; + } + if (i >= seq_size) + mark_referenced_resources (XEXP (PATTERN (insn), 0), res, 0); + } + } + + /* ... fall through to other INSN processing ... */ + + case INSN: + case JUMP_INSN: + +#ifdef INSN_REFERENCES_ARE_DELAYED + if (! include_delayed_effects + && INSN_REFERENCES_ARE_DELAYED (x)) + return; +#endif + + /* No special processing, just speed up. */ + mark_referenced_resources (PATTERN (x), res, include_delayed_effects); + return; + } + + /* Process each sub-expression and flag what it needs. */ + format_ptr = GET_RTX_FORMAT (code); + for (i = 0; i < GET_RTX_LENGTH (code); i++) + switch (*format_ptr++) + { + case 'e': + mark_referenced_resources (XEXP (x, i), res, include_delayed_effects); + break; + + case 'E': + for (j = 0; j < XVECLEN (x, i); j++) + mark_referenced_resources (XVECEXP (x, i, j), res, + include_delayed_effects); + break; + } +} + +/* Given X, a part of an insn, and a pointer to a `struct resource', RES, + indicate which resources are modified by the insn. If INCLUDE_CALLED_ROUTINE + is nonzero, also mark resources potentially set by the called routine. + + If IN_DEST is nonzero, it means we are inside a SET. Otherwise, + objects are being referenced instead of set. + + We never mark the insn as modifying the condition code unless it explicitly + SETs CC0 even though this is not totally correct. The reason for this is + that we require a SET of CC0 to immediately precede the reference to CC0. + So if some other insn sets CC0 as a side-effect, we know it cannot affect + our computation and thus may be placed in a delay slot. */ + +static void +mark_set_resources (x, res, in_dest, include_delayed_effects) + register rtx x; + register struct resources *res; + int in_dest; + int include_delayed_effects; +{ + register enum rtx_code code; + register int i, j; + register char *format_ptr; + + restart: + + code = GET_CODE (x); + + switch (code) + { + case NOTE: + case BARRIER: + case CODE_LABEL: + case USE: + case CONST_INT: + case CONST_DOUBLE: + case LABEL_REF: + case SYMBOL_REF: + case CONST: + case PC: + /* These don't set any resources. */ + return; + + case CC0: + if (in_dest) + res->cc = 1; + return; + + case CALL_INSN: + /* Called routine modifies the condition code, memory, any registers + that aren't saved across calls, global registers and anything + explicitly CLOBBERed immediately after the CALL_INSN. */ + + if (include_delayed_effects) + { + rtx next = NEXT_INSN (x); + + res->cc = res->memory = 1; + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (call_used_regs[i] || global_regs[i]) + SET_HARD_REG_BIT (res->regs, i); + + /* Skip any possible labels between the CALL_INSN and CLOBBERs. */ + while (GET_CODE (next) == CODE_LABEL) + next = NEXT_INSN (next); + + for (; (next && GET_CODE (next) == INSN + && GET_CODE (PATTERN (next)) == CLOBBER); + next = NEXT_INSN (next)) + mark_set_resources (XEXP (PATTERN (next), 0), res, 1, 0); + } + + /* ... and also what it's RTL says it modifies, if anything. */ + + case JUMP_INSN: + case INSN: + + /* An insn consisting of just a CLOBBER (or USE) is just for flow + and doesn't actually do anything, so we ignore it. */ + +#ifdef INSN_SETS_ARE_DELAYED + if (! include_delayed_effects + && INSN_SETS_ARE_DELAYED (x)) + return; +#endif + + x = PATTERN (x); + if (GET_CODE (x) != USE && GET_CODE (x) != CLOBBER) + goto restart; + return; + + case SET: + /* If the source of a SET is a CALL, this is actually done by + the called routine. So only include it if we are to include the + effects of the calling routine. */ + + mark_set_resources (SET_DEST (x), res, + (include_delayed_effects + || GET_CODE (SET_SRC (x)) != CALL), + 0); + + mark_set_resources (SET_SRC (x), res, 0, 0); + return; + + case CLOBBER: + mark_set_resources (XEXP (x, 0), res, 1, 0); + return; + + case SEQUENCE: + for (i = 0; i < XVECLEN (x, 0); i++) + if (! (INSN_ANNULLED_BRANCH_P (XVECEXP (x, 0, 0)) + && INSN_FROM_TARGET_P (XVECEXP (x, 0, i)))) + mark_set_resources (XVECEXP (x, 0, i), res, 0, + include_delayed_effects); + return; + + case POST_INC: + case PRE_INC: + case POST_DEC: + case PRE_DEC: + mark_set_resources (XEXP (x, 0), res, 1, 0); + return; + + case ZERO_EXTRACT: + mark_set_resources (XEXP (x, 0), res, in_dest, 0); + mark_set_resources (XEXP (x, 1), res, 0, 0); + mark_set_resources (XEXP (x, 2), res, 0, 0); + return; + + case MEM: + if (in_dest) + { + res->memory = 1; + res->volatil = MEM_VOLATILE_P (x); + } + + mark_set_resources (XEXP (x, 0), res, 0, 0); + return; + + case REG: + if (in_dest) + for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++) + SET_HARD_REG_BIT (res->regs, REGNO (x) + i); + return; + } + + /* Process each sub-expression and flag what it needs. */ + format_ptr = GET_RTX_FORMAT (code); + for (i = 0; i < GET_RTX_LENGTH (code); i++) + switch (*format_ptr++) + { + case 'e': + mark_set_resources (XEXP (x, i), res, in_dest, include_delayed_effects); + break; + + case 'E': + for (j = 0; j < XVECLEN (x, i); j++) + mark_set_resources (XVECEXP (x, i, j), res, in_dest, + include_delayed_effects); + break; + } +} + +/* Return TRUE if this insn should stop the search for insn to fill delay + slots. LABELS_P indicates that labels should terminate the search. + In all cases, jumps terminate the search. */ + +static int +stop_search_p (insn, labels_p) + rtx insn; + int labels_p; +{ + if (insn == 0) + return 1; + + switch (GET_CODE (insn)) + { + case NOTE: + case CALL_INSN: + return 0; + + case CODE_LABEL: + return labels_p; + + case JUMP_INSN: + case BARRIER: + return 1; + + case INSN: + /* OK unless it contains a delay slot or is an `asm' insn of some type. + We don't know anything about these. */ + return (GET_CODE (PATTERN (insn)) == SEQUENCE + || GET_CODE (PATTERN (insn)) == ASM_INPUT + || asm_noperands (PATTERN (insn)) >= 0); + + default: + abort (); + } +} + +/* Return TRUE if any resources are marked in both RES1 and RES2 or if either + resource set contains a volatile memory reference. Otherwise, return FALSE. */ + +static int +resource_conflicts_p (res1, res2) + struct resources *res1, *res2; +{ + if ((res1->cc && res2->cc) || (res1->memory && res2->memory) + || res1->volatil || res2->volatil) + return 1; + +#ifdef HARD_REG_SET + return (res1->regs & res2->regs) != HARD_CONST (0); +#else + { + int i; + + for (i = 0; i < HARD_REG_SET_LONGS; i++) + if ((res1->regs[i] & res2->regs[i]) != 0) + return 1; + return 0; + } +#endif +} + +/* Return TRUE if any resource marked in RES, a `struct resources', is + referenced by INSN. If INCLUDE_CALLED_ROUTINE is set, return if the called + routine is using those resources. + + We compute this by computing all the resources referenced by INSN and + seeing if this conflicts with RES. It might be faster to directly check + ourselves, and this is the way it used to work, but it means duplicating + a large block of complex code. */ + +static int +insn_references_resource_p (insn, res, include_delayed_effects) + register rtx insn; + register struct resources *res; + int include_delayed_effects; +{ + struct resources insn_res; + + CLEAR_RESOURCE (&insn_res); + mark_referenced_resources (insn, &insn_res, include_delayed_effects); + return resource_conflicts_p (&insn_res, res); +} + +/* Return TRUE if INSN modifies resources that are marked in RES. + INCLUDE_CALLED_ROUTINE is set if the actions of that routine should be + included. CC0 is only modified if it is explicitly set; see comments + in front of mark_set_resources for details. */ + +static int +insn_sets_resource_p (insn, res, include_delayed_effects) + register rtx insn; + register struct resources *res; + int include_delayed_effects; +{ + struct resources insn_sets; + + CLEAR_RESOURCE (&insn_sets); + mark_set_resources (insn, &insn_sets, 0, include_delayed_effects); + return resource_conflicts_p (&insn_sets, res); +} + +/* Find a label at the end of the function or before a RETURN. If there is + none, make one. */ + +static rtx +find_end_label () +{ + rtx insn; + + /* If we found one previously, return it. */ + if (end_of_function_label) + return end_of_function_label; + + /* Otherwise, see if there is a label at the end of the function. If there + is, it must be that RETURN insns aren't needed, so that is our return + label and we don't have to do anything else. */ + + insn = get_last_insn (); + while (GET_CODE (insn) == NOTE + || (GET_CODE (insn) == INSN + && (GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER))) + insn = PREV_INSN (insn); + + if (GET_CODE (insn) == CODE_LABEL) + end_of_function_label = insn; + else + { + /* Otherwise, make a new label and emit a RETURN and BARRIER, + if needed. */ + end_of_function_label = gen_label_rtx (); + LABEL_NUSES (end_of_function_label) = 0; + emit_label (end_of_function_label); +#ifdef HAVE_return + if (HAVE_return) + { + /* The return we make may have delay slots too. */ + rtx insn = gen_return (); + insn = emit_jump_insn (insn); + emit_barrier (); + if (num_delay_slots (insn) > 0) + obstack_ptr_grow (&unfilled_slots_obstack, insn); + } +#endif + } + + /* Show one additional use for this label so it won't go away until + we are done. */ + ++LABEL_NUSES (end_of_function_label); + + return end_of_function_label; +} + +/* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace + the pattern of INSN with the SEQUENCE. + + Chain the insns so that NEXT_INSN of each insn in the sequence points to + the next and NEXT_INSN of the last insn in the sequence points to + the first insn after the sequence. Similarly for PREV_INSN. This makes + it easier to scan all insns. + + Returns the SEQUENCE that replaces INSN. */ + +static rtx +emit_delay_sequence (insn, list, length, avail) + rtx insn; + rtx list; + int length; + int avail; +{ + register int i = 1; + register rtx li; + int had_barrier = 0; + + /* Allocate the the rtvec to hold the insns and the SEQUENCE. */ + rtvec seqv = rtvec_alloc (length + 1); + rtx seq = gen_rtx (SEQUENCE, VOIDmode, seqv); + rtx seq_insn = make_insn_raw (seq); + rtx first = get_insns (); + rtx last = get_last_insn (); + + /* Make a copy of the insn having delay slots. */ + rtx delay_insn = copy_rtx (insn); + + /* If INSN is followed by a BARRIER, delete the BARRIER since it will only + confuse further processing. Update LAST in case it was the last insn. + We will put the BARRIER back in later. */ + if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == BARRIER) + { + delete_insn (NEXT_INSN (insn)); + last = get_last_insn (); + had_barrier = 1; + } + + /* Splice our SEQUENCE into the insn stream where INSN used to be. */ + NEXT_INSN (seq_insn) = NEXT_INSN (insn); + PREV_INSN (seq_insn) = PREV_INSN (insn); + + if (insn == last) + set_new_first_and_last_insn (first, seq_insn); + else + PREV_INSN (NEXT_INSN (seq_insn)) = seq_insn; + + if (insn == first) + set_new_first_and_last_insn (seq_insn, last); + else + NEXT_INSN (PREV_INSN (seq_insn)) = seq_insn; + + /* Build our SEQUENCE and rebuild the insn chain. */ + XVECEXP (seq, 0, 0) = delay_insn; + INSN_DELETED_P (delay_insn) = 0; + PREV_INSN (delay_insn) = PREV_INSN (seq_insn); + + for (li = list; li; li = XEXP (li, 1), i++) + { + rtx tem = XEXP (li, 0); + rtx note; + + /* Show that this copy of the insn isn't deleted. */ + INSN_DELETED_P (tem) = 0; + + XVECEXP (seq, 0, i) = tem; + PREV_INSN (tem) = XVECEXP (seq, 0, i - 1); + NEXT_INSN (XVECEXP (seq, 0, i - 1)) = tem; + + /* Remove any REG_DEAD notes because we can't rely on them now + that the insn has been moved. */ + for (note = REG_NOTES (tem); note; note = XEXP (note, 1)) + if (REG_NOTE_KIND (note) == REG_DEAD) + XEXP (note, 0) = const0_rtx; + } + + NEXT_INSN (XVECEXP (seq, 0, length)) = NEXT_INSN (seq_insn); + + /* If the previous insn is a SEQUENCE, update the NEXT_INSN pointer on the + last insn in that SEQUENCE to point to us. Similarly for the first + insn in the following insn if it is a SEQUENCE. */ + + if (PREV_INSN (seq_insn) && GET_CODE (PREV_INSN (seq_insn)) == INSN + && GET_CODE (PATTERN (PREV_INSN (seq_insn))) == SEQUENCE) + NEXT_INSN (XVECEXP (PATTERN (PREV_INSN (seq_insn)), 0, + XVECLEN (PATTERN (PREV_INSN (seq_insn)), 0) - 1)) + = seq_insn; + + if (NEXT_INSN (seq_insn) && GET_CODE (NEXT_INSN (seq_insn)) == INSN + && GET_CODE (PATTERN (NEXT_INSN (seq_insn))) == SEQUENCE) + PREV_INSN (XVECEXP (PATTERN (NEXT_INSN (seq_insn)), 0, 0)) = seq_insn; + + /* If there used to be a BARRIER, put it back. */ + if (had_barrier) + emit_barrier_after (seq_insn); + + if (i != length + 1) + abort (); + + return seq_insn; +} + +/* Add INSN to DELAY_LIST and return the head of the new list. The list must + be in the order in which the insns are to be executed. */ + +static rtx +add_to_delay_list (insn, delay_list) + rtx insn; + rtx delay_list; +{ + /* If we have an empty list, just make a new list element. If + INSN has it's block number recorded, clear it since we may + be moving the insn to a new block. */ + + if (delay_list == 0) + { + struct target_info *tinfo; + + for (tinfo = target_hash_table[INSN_UID (insn) % TARGET_HASH_PRIME]; + tinfo; tinfo = tinfo->next) + if (tinfo->uid == INSN_UID (insn)) + break; + + if (tinfo) + tinfo->block = -1; + + return gen_rtx (INSN_LIST, VOIDmode, insn, NULL_RTX); + } + + /* Otherwise this must be an INSN_LIST. Add INSN to the end of the + list. */ + XEXP (delay_list, 1) = add_to_delay_list (insn, XEXP (delay_list, 1)); + + return delay_list; +} + +/* Delete INSN from the the delay slot of the insn that it is in. This may + produce an insn without anything in its delay slots. */ + +static void +delete_from_delay_slot (insn) + rtx insn; +{ + rtx trial, seq_insn, seq, prev; + rtx delay_list = 0; + int i; + + /* We first must find the insn containing the SEQUENCE with INSN in its + delay slot. Do this by finding an insn, TRIAL, where + PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */ + + for (trial = insn; + PREV_INSN (NEXT_INSN (trial)) == trial; + trial = NEXT_INSN (trial)) + ; + + seq_insn = PREV_INSN (NEXT_INSN (trial)); + seq = PATTERN (seq_insn); + + /* Create a delay list consisting of all the insns other than the one + we are deleting (unless we were the only one). */ + if (XVECLEN (seq, 0) > 2) + for (i = 1; i < XVECLEN (seq, 0); i++) + if (XVECEXP (seq, 0, i) != insn) + delay_list = add_to_delay_list (XVECEXP (seq, 0, i), delay_list); + + /* Delete the old SEQUENCE, re-emit the insn that used to have the delay + list, and rebuild the delay list if non-empty. */ + prev = PREV_INSN (seq_insn); + trial = XVECEXP (seq, 0, 0); + delete_insn (seq_insn); + add_insn_after (trial, prev); + + if (GET_CODE (trial) == JUMP_INSN + && (simplejump_p (trial) || GET_CODE (PATTERN (trial)) == RETURN)) + emit_barrier_after (trial); + + /* If there are any delay insns, remit them. Otherwise clear the + annul flag. */ + if (delay_list) + trial = emit_delay_sequence (trial, delay_list, XVECLEN (seq, 0) - 2, 0); + else + INSN_ANNULLED_BRANCH_P (trial) = 0; + + INSN_FROM_TARGET_P (insn) = 0; + + /* Show we need to fill this insn again. */ + obstack_ptr_grow (&unfilled_slots_obstack, trial); +} + +/* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down + the insn that sets CC0 for it and delete it too. */ + +static void +delete_scheduled_jump (insn) + rtx insn; +{ + /* Delete the insn that sets cc0 for us. On machines without cc0, we could + delete the insn that sets the condition code, but it is hard to find it. + Since this case is rare anyway, don't bother trying; there would likely + be other insns that became dead anyway, which we wouldn't know to + delete. */ + +#ifdef HAVE_cc0 + if (reg_mentioned_p (cc0_rtx, insn)) + { + rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); + + /* If a reg-note was found, it points to an insn to set CC0. This + insn is in the delay list of some other insn. So delete it from + the delay list it was in. */ + if (note) + { + if (! FIND_REG_INC_NOTE (XEXP (note, 0), NULL_RTX) + && sets_cc0_p (PATTERN (XEXP (note, 0))) == 1) + delete_from_delay_slot (XEXP (note, 0)); + } + else + { + /* The insn setting CC0 is our previous insn, but it may be in + a delay slot. It will be the last insn in the delay slot, if + it is. */ + rtx trial = previous_insn (insn); + if (GET_CODE (trial) == NOTE) + trial = prev_nonnote_insn (trial); + if (sets_cc0_p (PATTERN (trial)) != 1 + || FIND_REG_INC_NOTE (trial, 0)) + return; + if (PREV_INSN (NEXT_INSN (trial)) == trial) + delete_insn (trial); + else + delete_from_delay_slot (trial); + } + } +#endif + + delete_insn (insn); +} + +/* Counters for delay-slot filling. */ + +#define NUM_REORG_FUNCTIONS 2 +#define MAX_DELAY_HISTOGRAM 3 +#define MAX_REORG_PASSES 2 + +static int num_insns_needing_delays[NUM_REORG_FUNCTIONS][MAX_REORG_PASSES]; + +static int num_filled_delays[NUM_REORG_FUNCTIONS][MAX_DELAY_HISTOGRAM+1][MAX_REORG_PASSES]; + +static int reorg_pass_number; + +static void +note_delay_statistics (slots_filled, index) + int slots_filled, index; +{ + num_insns_needing_delays[index][reorg_pass_number]++; + if (slots_filled > MAX_DELAY_HISTOGRAM) + slots_filled = MAX_DELAY_HISTOGRAM; + num_filled_delays[index][slots_filled][reorg_pass_number]++; +} + +#if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS) + +/* Optimize the following cases: + + 1. When a conditional branch skips over only one instruction, + use an annulling branch and put that insn in the delay slot. + Use either a branch that annuls when the condition if true or + invert the test with a branch that annuls when the condition is + false. This saves insns, since otherwise we must copy an insn + from the L1 target. + + (orig) (skip) (otherwise) + Bcc.n L1 Bcc',a L1 Bcc,a L1' + insn insn insn2 + L1: L1: L1: + insn2 insn2 insn2 + insn3 insn3 L1': + insn3 + + 2. When a conditional branch skips over only one instruction, + and after that, it unconditionally branches somewhere else, + perform the similar optimization. This saves executing the + second branch in the case where the inverted condition is true. + + Bcc.n L1 Bcc',a L2 + insn insn + L1: L1: + Bra L2 Bra L2 + + INSN is a JUMP_INSN. + + This should be expanded to skip over N insns, where N is the number + of delay slots required. */ + +static rtx +optimize_skip (insn) + register rtx insn; +{ + register rtx trial = next_nonnote_insn (insn); + rtx next_trial = next_active_insn (trial); + rtx delay_list = 0; + rtx target_label; + int flags; + + flags = get_jump_flags (insn, JUMP_LABEL (insn)); + + if (trial == 0 + || GET_CODE (trial) != INSN + || GET_CODE (PATTERN (trial)) == SEQUENCE + || recog_memoized (trial) < 0 + || (! eligible_for_annul_false (insn, 0, trial, flags) + && ! eligible_for_annul_true (insn, 0, trial, flags))) + return 0; + + /* There are two cases where we are just executing one insn (we assume + here that a branch requires only one insn; this should be generalized + at some point): Where the branch goes around a single insn or where + we have one insn followed by a branch to the same label we branch to. + In both of these cases, inverting the jump and annulling the delay + slot give the same effect in fewer insns. */ + if ((next_trial == next_active_insn (JUMP_LABEL (insn))) + || (next_trial != 0 + && GET_CODE (next_trial) == JUMP_INSN + && JUMP_LABEL (insn) == JUMP_LABEL (next_trial) + && (simplejump_p (next_trial) + || GET_CODE (PATTERN (next_trial)) == RETURN))) + { + if (eligible_for_annul_false (insn, 0, trial, flags)) + { + if (invert_jump (insn, JUMP_LABEL (insn))) + INSN_FROM_TARGET_P (trial) = 1; + else if (! eligible_for_annul_true (insn, 0, trial, flags)) + return 0; + } + + delay_list = add_to_delay_list (trial, NULL_RTX); + next_trial = next_active_insn (trial); + update_block (trial, trial); + delete_insn (trial); + + /* Also, if we are targeting an unconditional + branch, thread our jump to the target of that branch. Don't + change this into a RETURN here, because it may not accept what + we have in the delay slot. We'll fix this up later. */ + if (next_trial && GET_CODE (next_trial) == JUMP_INSN + && (simplejump_p (next_trial) + || GET_CODE (PATTERN (next_trial)) == RETURN)) + { + target_label = JUMP_LABEL (next_trial); + if (target_label == 0) + target_label = find_end_label (); + reorg_redirect_jump (insn, target_label); + } + + INSN_ANNULLED_BRANCH_P (insn) = 1; + } + + return delay_list; +} +#endif + + +/* Encode and return branch direction and prediction information for + INSN assuming it will jump to LABEL. + + Non conditional branches return no direction information and + are predicted as very likely taken. */ +static int +get_jump_flags (insn, label) + rtx insn, label; +{ + int flags; + + /* get_jump_flags can be passed any insn with delay slots, these may + be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch + direction information, and only if they are conditional jumps. + + If LABEL is zero, then there is no way to determine the branch + direction. */ + if (GET_CODE (insn) == JUMP_INSN + && condjump_p (insn) + && INSN_UID (insn) <= max_uid + && label != 0 + && INSN_UID (label) <= max_uid) + flags + = (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)]) + ? ATTR_FLAG_forward : ATTR_FLAG_backward; + /* No valid direction information. */ + else + flags = 0; + + /* If insn is a conditional branch call mostly_true_jump to get + determine the branch prediction. + + Non conditional branches are predicted as very likely taken. */ + if (GET_CODE (insn) == JUMP_INSN + && condjump_p (insn)) + { + int prediction; + + prediction = mostly_true_jump (insn, get_branch_condition (insn, label)); + switch (prediction) + { + case 2: + flags |= (ATTR_FLAG_very_likely | ATTR_FLAG_likely); + break; + case 1: + flags |= ATTR_FLAG_likely; + break; + case 0: + flags |= ATTR_FLAG_unlikely; + break; + case -1: + flags |= (ATTR_FLAG_very_unlikely | ATTR_FLAG_unlikely); + break; + + default: + abort(); + } + } + else + flags |= (ATTR_FLAG_very_likely | ATTR_FLAG_likely); + + return flags; +} + +/* Return 1 if DEST is a destination that will be branched to rarely (the + return point of a function); return 2 if DEST will be branched to very + rarely (a call to a function that doesn't return). Otherwise, + return 0. */ + +static int +rare_destination (insn) + rtx insn; +{ + int jump_count = 0; + + for (; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) + insn = XVECEXP (PATTERN (insn), 0, 0); + + switch (GET_CODE (insn)) + { + case CODE_LABEL: + return 0; + case BARRIER: + /* A BARRIER can either be after a JUMP_INSN or a CALL_INSN. We + don't scan past JUMP_INSNs, so any barrier we find here must + have been after a CALL_INSN and hence mean the call doesn't + return. */ + return 2; + case JUMP_INSN: + if (GET_CODE (PATTERN (insn)) == RETURN) + return 1; + else if (simplejump_p (insn) + && jump_count++ < 10) + insn = JUMP_LABEL (insn); + else + return 0; + } + } + + /* If we got here it means we hit the end of the function. So this + is an unlikely destination. */ + + return 1; +} + +/* Return truth value of the statement that this branch + is mostly taken. If we think that the branch is extremely likely + to be taken, we return 2. If the branch is slightly more likely to be + taken, return 1. If the branch is slightly less likely to be taken, + return 0 and if the branch is highly unlikely to be taken, return -1. + + CONDITION, if non-zero, is the condition that JUMP_INSN is testing. */ + +static int +mostly_true_jump (jump_insn, condition) + rtx jump_insn, condition; +{ + rtx target_label = JUMP_LABEL (jump_insn); + rtx insn; + int rare_dest = rare_destination (target_label); + int rare_fallthrough = rare_destination (NEXT_INSN (jump_insn)); + + /* If this is a branch outside a loop, it is highly unlikely. */ + if (GET_CODE (PATTERN (jump_insn)) == SET + && GET_CODE (SET_SRC (PATTERN (jump_insn))) == IF_THEN_ELSE + && ((GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 1)) == LABEL_REF + && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 1))) + || (GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 2)) == LABEL_REF + && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 2))))) + return -1; + + if (target_label) + { + /* If this is the test of a loop, it is very likely true. We scan + backwards from the target label. If we find a NOTE_INSN_LOOP_BEG + before the next real insn, we assume the branch is to the top of + the loop. */ + for (insn = PREV_INSN (target_label); + insn && GET_CODE (insn) == NOTE; + insn = PREV_INSN (insn)) + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) + return 2; + + /* If this is a jump to the test of a loop, it is likely true. We scan + forwards from the target label. If we find a NOTE_INSN_LOOP_VTOP + before the next real insn, we assume the branch is to the loop branch + test. */ + for (insn = NEXT_INSN (target_label); + insn && GET_CODE (insn) == NOTE; + insn = PREV_INSN (insn)) + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_VTOP) + return 1; + } + + /* Look at the relative rarities of the fallthough and destination. If + they differ, we can predict the branch that way. */ + + switch (rare_fallthrough - rare_dest) + { + case -2: + return -1; + case -1: + return 0; + case 0: + break; + case 1: + return 1; + case 2: + return 2; + } + + /* If we couldn't figure out what this jump was, assume it won't be + taken. This should be rare. */ + if (condition == 0) + return 0; + + /* EQ tests are usually false and NE tests are usually true. Also, + most quantities are positive, so we can make the appropriate guesses + about signed comparisons against zero. */ + switch (GET_CODE (condition)) + { + case CONST_INT: + /* Unconditional branch. */ + return 1; + case EQ: + return 0; + case NE: + return 1; + case LE: + case LT: + if (XEXP (condition, 1) == const0_rtx) + return 0; + break; + case GE: + case GT: + if (XEXP (condition, 1) == const0_rtx) + return 1; + break; + } + + /* Predict backward branches usually take, forward branches usually not. If + we don't know whether this is forward or backward, assume the branch + will be taken, since most are. */ + return (target_label == 0 || INSN_UID (jump_insn) > max_uid + || INSN_UID (target_label) > max_uid + || (uid_to_ruid[INSN_UID (jump_insn)] + > uid_to_ruid[INSN_UID (target_label)]));; +} + +/* Return the condition under which INSN will branch to TARGET. If TARGET + is zero, return the condition under which INSN will return. If INSN is + an unconditional branch, return const_true_rtx. If INSN isn't a simple + type of jump, or it doesn't go to TARGET, return 0. */ + +static rtx +get_branch_condition (insn, target) + rtx insn; + rtx target; +{ + rtx pat = PATTERN (insn); + rtx src; + + if (GET_CODE (pat) == RETURN) + return target == 0 ? const_true_rtx : 0; + + else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx) + return 0; + + src = SET_SRC (pat); + if (GET_CODE (src) == LABEL_REF && XEXP (src, 0) == target) + return const_true_rtx; + + else if (GET_CODE (src) == IF_THEN_ELSE + && ((target == 0 && GET_CODE (XEXP (src, 1)) == RETURN) + || (GET_CODE (XEXP (src, 1)) == LABEL_REF + && XEXP (XEXP (src, 1), 0) == target)) + && XEXP (src, 2) == pc_rtx) + return XEXP (src, 0); + + else if (GET_CODE (src) == IF_THEN_ELSE + && ((target == 0 && GET_CODE (XEXP (src, 2)) == RETURN) + || (GET_CODE (XEXP (src, 2)) == LABEL_REF + && XEXP (XEXP (src, 2), 0) == target)) + && XEXP (src, 1) == pc_rtx) + return gen_rtx (reverse_condition (GET_CODE (XEXP (src, 0))), + GET_MODE (XEXP (src, 0)), + XEXP (XEXP (src, 0), 0), XEXP (XEXP (src, 0), 1)); + + return 0; +} + +/* Return non-zero if CONDITION is more strict than the condition of + INSN, i.e., if INSN will always branch if CONDITION is true. */ + +static int +condition_dominates_p (condition, insn) + rtx condition; + rtx insn; +{ + rtx other_condition = get_branch_condition (insn, JUMP_LABEL (insn)); + enum rtx_code code = GET_CODE (condition); + enum rtx_code other_code; + + if (rtx_equal_p (condition, other_condition) + || other_condition == const_true_rtx) + return 1; + + else if (condition == const_true_rtx || other_condition == 0) + return 0; + + other_code = GET_CODE (other_condition); + if (GET_RTX_LENGTH (code) != 2 || GET_RTX_LENGTH (other_code) != 2 + || ! rtx_equal_p (XEXP (condition, 0), XEXP (other_condition, 0)) + || ! rtx_equal_p (XEXP (condition, 1), XEXP (other_condition, 1))) + return 0; + + return comparison_dominates_p (code, other_code); +} + +/* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that + the condition tested by INSN is CONDITION and the resources shown in + OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns + from SEQ's delay list, in addition to whatever insns it may execute + (in DELAY_LIST). SETS and NEEDED are denote resources already set and + needed while searching for delay slot insns. Return the concatenated + delay list if possible, otherwise, return 0. + + SLOTS_TO_FILL is the total number of slots required by INSN, and + PSLOTS_FILLED points to the number filled so far (also the number of + insns in DELAY_LIST). It is updated with the number that have been + filled from the SEQUENCE, if any. + + PANNUL_P points to a non-zero value if we already know that we need + to annul INSN. If this routine determines that annulling is needed, + it may set that value non-zero. + + PNEW_THREAD points to a location that is to receive the place at which + execution should continue. */ + +static rtx +steal_delay_list_from_target (insn, condition, seq, delay_list, + sets, needed, other_needed, + slots_to_fill, pslots_filled, pannul_p, + pnew_thread) + rtx insn, condition; + rtx seq; + rtx delay_list; + struct resources *sets, *needed, *other_needed; + int slots_to_fill; + int *pslots_filled; + int *pannul_p; + rtx *pnew_thread; +{ + rtx temp; + int slots_remaining = slots_to_fill - *pslots_filled; + int total_slots_filled = *pslots_filled; + rtx new_delay_list = 0; + int must_annul = *pannul_p; + int i; + + /* We can't do anything if there are more delay slots in SEQ than we + can handle, or if we don't know that it will be a taken branch. + + We know that it will be a taken branch if it is either an unconditional + branch or a conditional branch with a stricter branch condition. */ + + if (XVECLEN (seq, 0) - 1 > slots_remaining + || ! condition_dominates_p (condition, XVECEXP (seq, 0, 0))) + return delay_list; + + for (i = 1; i < XVECLEN (seq, 0); i++) + { + rtx trial = XVECEXP (seq, 0, i); + int flags; + + if (insn_references_resource_p (trial, sets, 0) + || insn_sets_resource_p (trial, needed, 0) + || insn_sets_resource_p (trial, sets, 0) +#ifdef HAVE_cc0 + /* If TRIAL sets CC0, we can't copy it, so we can't steal this + delay list. */ + || find_reg_note (trial, REG_CC_USER, NULL_RTX) +#endif + /* If TRIAL is from the fallthrough code of an annulled branch insn + in SEQ, we cannot use it. */ + || (INSN_ANNULLED_BRANCH_P (XVECEXP (seq, 0, 0)) + && ! INSN_FROM_TARGET_P (trial))) + return delay_list; + + /* If this insn was already done (usually in a previous delay slot), + pretend we put it in our delay slot. */ + if (redundant_insn_p (trial, insn, new_delay_list)) + continue; + + /* We will end up re-vectoring this branch, so compute flags + based on jumping to the new label. */ + flags = get_jump_flags (insn, JUMP_LABEL (XVECEXP (seq, 0, 0))); + + if (! must_annul + && ((condition == const_true_rtx + || (! insn_sets_resource_p (trial, other_needed, 0) + && ! may_trap_p (PATTERN (trial))))) + ? eligible_for_delay (insn, total_slots_filled, trial, flags) + : (must_annul = 1, + eligible_for_annul_false (insn, total_slots_filled, trial, flags))) + { + temp = copy_rtx (trial); + INSN_FROM_TARGET_P (temp) = 1; + new_delay_list = add_to_delay_list (temp, new_delay_list); + total_slots_filled++; + + if (--slots_remaining == 0) + break; + } + else + return delay_list; + } + + /* Show the place to which we will be branching. */ + *pnew_thread = next_active_insn (JUMP_LABEL (XVECEXP (seq, 0, 0))); + + /* Add any new insns to the delay list and update the count of the + number of slots filled. */ + *pslots_filled = total_slots_filled; + *pannul_p = must_annul; + + if (delay_list == 0) + return new_delay_list; + + for (temp = new_delay_list; temp; temp = XEXP (temp, 1)) + delay_list = add_to_delay_list (XEXP (temp, 0), delay_list); + + return delay_list; +} + +/* Similar to steal_delay_list_from_target except that SEQ is on the + fallthrough path of INSN. Here we only do something if the delay insn + of SEQ is an unconditional branch. In that case we steal its delay slot + for INSN since unconditional branches are much easier to fill. */ + +static rtx +steal_delay_list_from_fallthrough (insn, condition, seq, + delay_list, sets, needed, other_needed, + slots_to_fill, pslots_filled, pannul_p) + rtx insn, condition; + rtx seq; + rtx delay_list; + struct resources *sets, *needed, *other_needed; + int slots_to_fill; + int *pslots_filled; + int *pannul_p; +{ + int i; + int flags; + + flags = get_jump_flags (insn, JUMP_LABEL (insn)); + + /* We can't do anything if SEQ's delay insn isn't an + unconditional branch. */ + + if (! simplejump_p (XVECEXP (seq, 0, 0)) + && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) != RETURN) + return delay_list; + + for (i = 1; i < XVECLEN (seq, 0); i++) + { + rtx trial = XVECEXP (seq, 0, i); + + /* If TRIAL sets CC0, stealing it will move it too far from the use + of CC0. */ + if (insn_references_resource_p (trial, sets, 0) + || insn_sets_resource_p (trial, needed, 0) + || insn_sets_resource_p (trial, sets, 0) +#ifdef HAVE_cc0 + || sets_cc0_p (PATTERN (trial)) +#endif + ) + + break; + + /* If this insn was already done, we don't need it. */ + if (redundant_insn_p (trial, insn, delay_list)) + { + delete_from_delay_slot (trial); + continue; + } + + if (! *pannul_p + && ((condition == const_true_rtx + || (! insn_sets_resource_p (trial, other_needed, 0) + && ! may_trap_p (PATTERN (trial))))) + ? eligible_for_delay (insn, *pslots_filled, trial, flags) + : (*pannul_p = 1, + eligible_for_annul_true (insn, *pslots_filled, trial, flags))) + { + delete_from_delay_slot (trial); + delay_list = add_to_delay_list (trial, delay_list); + + if (++(*pslots_filled) == slots_to_fill) + break; + } + else + break; + } + + return delay_list; +} + +/* Try merging insns starting at THREAD which match exactly the insns in + INSN's delay list. + + If all insns were matched and the insn was previously annulling, the + annul bit will be cleared. + + For each insn that is merged, if the branch is or will be non-annulling, + we delete the merged insn. */ + +static void +try_merge_delay_insns (insn, thread) + rtx insn, thread; +{ + rtx trial, next_trial; + rtx delay_insn = XVECEXP (PATTERN (insn), 0, 0); + int annul_p = INSN_ANNULLED_BRANCH_P (delay_insn); + int slot_number = 1; + int num_slots = XVECLEN (PATTERN (insn), 0); + rtx next_to_match = XVECEXP (PATTERN (insn), 0, slot_number); + struct resources set, needed; + rtx merged_insns = 0; + int i; + int flags; + + flags = get_jump_flags (insn, JUMP_LABEL (insn)); + + CLEAR_RESOURCE (&needed); + CLEAR_RESOURCE (&set); + + /* If this is not an annulling branch, take into account anything needed in + NEXT_TO_MATCH. This prevents two increments from being incorrectly + folded into one. If we are annulling, this would be the correct + thing to do. (The alternative, looking at things set in NEXT_TO_MATCH + will essentially disable this optimization. This method is somewhat of + a kludge, but I don't see a better way.) */ + if (! annul_p) + mark_referenced_resources (next_to_match, &needed, 1); + + for (trial = thread; !stop_search_p (trial, 1); trial = next_trial) + { + rtx pat = PATTERN (trial); + + next_trial = next_nonnote_insn (trial); + + /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */ + if (GET_CODE (trial) == INSN + && (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)) + continue; + + if (GET_CODE (next_to_match) == GET_CODE (trial) +#ifdef HAVE_cc0 + /* We can't share an insn that sets cc0. */ + && ! sets_cc0_p (pat) +#endif + && ! insn_references_resource_p (trial, &set, 1) + && ! insn_sets_resource_p (trial, &set, 1) + && ! insn_sets_resource_p (trial, &needed, 1) + && (trial = try_split (pat, trial, 0)) != 0 + && rtx_equal_p (PATTERN (next_to_match), PATTERN (trial)) + /* Have to test this condition if annul condition is different + from (and less restrictive than) non-annulling one. */ + && eligible_for_delay (delay_insn, slot_number - 1, trial, flags)) + { + next_trial = next_nonnote_insn (trial); + + if (! annul_p) + { + update_block (trial, thread); + delete_insn (trial); + INSN_FROM_TARGET_P (next_to_match) = 0; + } + else + merged_insns = gen_rtx (INSN_LIST, VOIDmode, trial, merged_insns); + + if (++slot_number == num_slots) + break; + + next_to_match = XVECEXP (PATTERN (insn), 0, slot_number); + if (! annul_p) + mark_referenced_resources (next_to_match, &needed, 1); + } + + mark_set_resources (trial, &set, 0, 1); + mark_referenced_resources (trial, &needed, 1); + } + + /* See if we stopped on a filled insn. If we did, try to see if its + delay slots match. */ + if (slot_number != num_slots + && trial && GET_CODE (trial) == INSN + && GET_CODE (PATTERN (trial)) == SEQUENCE + && ! INSN_ANNULLED_BRANCH_P (XVECEXP (PATTERN (trial), 0, 0))) + { + rtx pat = PATTERN (trial); + + for (i = 1; i < XVECLEN (pat, 0); i++) + { + rtx dtrial = XVECEXP (pat, 0, i); + + if (! insn_references_resource_p (dtrial, &set, 1) + && ! insn_sets_resource_p (dtrial, &set, 1) + && ! insn_sets_resource_p (dtrial, &needed, 1) +#ifdef HAVE_cc0 + && ! sets_cc0_p (PATTERN (dtrial)) +#endif + && rtx_equal_p (PATTERN (next_to_match), PATTERN (dtrial)) + && eligible_for_delay (delay_insn, slot_number - 1, dtrial, flags)) + { + if (! annul_p) + { + update_block (dtrial, thread); + delete_from_delay_slot (dtrial); + INSN_FROM_TARGET_P (next_to_match) = 0; + } + else + merged_insns = gen_rtx (INSN_LIST, SImode, dtrial, + merged_insns); + + if (++slot_number == num_slots) + break; + + next_to_match = XVECEXP (PATTERN (insn), 0, slot_number); + } + } + } + + /* If all insns in the delay slot have been matched and we were previously + annulling the branch, we need not any more. In that case delete all the + merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn the + the delay list so that we know that it isn't only being used at the + target. */ + if (next_to_match == 0 && annul_p) + { + for (; merged_insns; merged_insns = XEXP (merged_insns, 1)) + { + if (GET_MODE (merged_insns) == SImode) + { + update_block (XEXP (merged_insns, 0), thread); + delete_from_delay_slot (XEXP (merged_insns, 0)); + } + else + { + update_block (XEXP (merged_insns, 0), thread); + delete_insn (XEXP (merged_insns, 0)); + } + } + + INSN_ANNULLED_BRANCH_P (delay_insn) = 0; + + for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) + INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) = 0; + } +} + +/* See if INSN is redundant with an insn in front of TARGET. Often this + is called when INSN is a candidate for a delay slot of TARGET. + DELAY_LIST are insns that will be placed in delay slots of TARGET in front + of INSN. Often INSN will be redundant with an insn in a delay slot of + some previous insn. This happens when we have a series of branches to the + same label; in that case the first insn at the target might want to go + into each of the delay slots. + + If we are not careful, this routine can take up a significant fraction + of the total compilation time (4%), but only wins rarely. Hence we + speed this routine up by making two passes. The first pass goes back + until it hits a label and sees if it find an insn with an identical + pattern. Only in this (relatively rare) event does it check for + data conflicts. + + We do not split insns we encounter. This could cause us not to find a + redundant insn, but the cost of splitting seems greater than the possible + gain in rare cases. */ + +static int +redundant_insn_p (insn, target, delay_list) + rtx insn; + rtx target; + rtx delay_list; +{ + rtx target_main = target; + rtx ipat = PATTERN (insn); + rtx trial, pat; + struct resources needed, set; + int i; + + /* Scan backwards looking for a match. */ + for (trial = PREV_INSN (target); trial; trial = PREV_INSN (trial)) + { + if (GET_CODE (trial) == CODE_LABEL) + return 0; + + if (GET_RTX_CLASS (GET_CODE (trial)) != 'i') + continue; + + pat = PATTERN (trial); + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + continue; + + if (GET_CODE (pat) == SEQUENCE) + { + /* Stop for a CALL and its delay slots because it is difficult to + track its resource needs correctly. */ + if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL_INSN) + return 0; + + /* Stop for an INSN or JUMP_INSN with delayed effects and its delay + slots because it is difficult to track its resource needs + correctly. */ + +#ifdef INSN_SETS_ARE_DELAYED + if (INSN_SETS_ARE_DELAYED (XVECEXP (pat, 0, 0))) + return 0; +#endif + +#ifdef INSN_REFERENCES_ARE_DELAYED + if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat, 0, 0))) + return 0; +#endif + + /* See if any of the insns in the delay slot match, updating + resource requirements as we go. */ + for (i = XVECLEN (pat, 0) - 1; i > 0; i--) + if (GET_CODE (XVECEXP (pat, 0, i)) == GET_CODE (insn) + && rtx_equal_p (PATTERN (XVECEXP (pat, 0, i)), ipat)) + break; + + /* If found a match, exit this loop early. */ + if (i > 0) + break; + } + + else if (GET_CODE (trial) == GET_CODE (insn) && rtx_equal_p (pat, ipat)) + break; + } + + /* If we didn't find an insn that matches, return 0. */ + if (trial == 0) + return 0; + + /* See what resources this insn sets and needs. If they overlap, or + if this insn references CC0, it can't be redundant. */ + + CLEAR_RESOURCE (&needed); + CLEAR_RESOURCE (&set); + mark_set_resources (insn, &set, 0, 1); + mark_referenced_resources (insn, &needed, 1); + + /* If TARGET is a SEQUENCE, get the main insn. */ + if (GET_CODE (target) == INSN && GET_CODE (PATTERN (target)) == SEQUENCE) + target_main = XVECEXP (PATTERN (target), 0, 0); + + if (resource_conflicts_p (&needed, &set) +#ifdef HAVE_cc0 + || reg_mentioned_p (cc0_rtx, ipat) +#endif + /* The insn requiring the delay may not set anything needed or set by + INSN. */ + || insn_sets_resource_p (target_main, &needed, 1) + || insn_sets_resource_p (target_main, &set, 1)) + return 0; + + /* Insns we pass may not set either NEEDED or SET, so merge them for + simpler tests. */ + needed.memory |= set.memory; + IOR_HARD_REG_SET (needed.regs, set.regs); + + /* This insn isn't redundant if it conflicts with an insn that either is + or will be in a delay slot of TARGET. */ + + while (delay_list) + { + if (insn_sets_resource_p (XEXP (delay_list, 0), &needed, 1)) + return 0; + delay_list = XEXP (delay_list, 1); + } + + if (GET_CODE (target) == INSN && GET_CODE (PATTERN (target)) == SEQUENCE) + for (i = 1; i < XVECLEN (PATTERN (target), 0); i++) + if (insn_sets_resource_p (XVECEXP (PATTERN (target), 0, i), &needed, 1)) + return 0; + + /* Scan backwards until we reach a label or an insn that uses something + INSN sets or sets something insn uses or sets. */ + + for (trial = PREV_INSN (target); + trial && GET_CODE (trial) != CODE_LABEL; + trial = PREV_INSN (trial)) + { + if (GET_CODE (trial) != INSN && GET_CODE (trial) != CALL_INSN + && GET_CODE (trial) != JUMP_INSN) + continue; + + pat = PATTERN (trial); + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + continue; + + if (GET_CODE (pat) == SEQUENCE) + { + /* If this is a CALL_INSN and its delay slots, it is hard to track + the resource needs properly, so give up. */ + if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL_INSN) + return 0; + + /* If this this is an INSN or JUMP_INSN with delayed effects, it + is hard to track the resource needs properly, so give up. */ + +#ifdef INSN_SETS_ARE_DELAYED + if (INSN_SETS_ARE_DELAYED (XVECEXP (pat, 0, 0))) + return 0; +#endif + +#ifdef INSN_REFERENCES_ARE_DELAYED + if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat, 0, 0))) + return 0; +#endif + + /* See if any of the insns in the delay slot match, updating + resource requirements as we go. */ + for (i = XVECLEN (pat, 0) - 1; i > 0; i--) + { + rtx candidate = XVECEXP (pat, 0, i); + + /* If an insn will be annulled if the branch is false, it isn't + considered as a possible duplicate insn. */ + if (rtx_equal_p (PATTERN (candidate), ipat) + && ! (INSN_ANNULLED_BRANCH_P (XVECEXP (pat, 0, 0)) + && INSN_FROM_TARGET_P (candidate))) + { + /* Show that this insn will be used in the sequel. */ + INSN_FROM_TARGET_P (candidate) = 0; + return 1; + } + + /* Unless this is an annulled insn from the target of a branch, + we must stop if it sets anything needed or set by INSN. */ + if ((! INSN_ANNULLED_BRANCH_P (XVECEXP (pat, 0, 0)) + || ! INSN_FROM_TARGET_P (candidate)) + && insn_sets_resource_p (candidate, &needed, 1)) + return 0; + } + + + /* If the insn requiring the delay slot conflicts with INSN, we + must stop. */ + if (insn_sets_resource_p (XVECEXP (pat, 0, 0), &needed, 1)) + return 0; + } + else + { + /* See if TRIAL is the same as INSN. */ + pat = PATTERN (trial); + if (rtx_equal_p (pat, ipat)) + return 1; + + /* Can't go any further if TRIAL conflicts with INSN. */ + if (insn_sets_resource_p (trial, &needed, 1)) + return 0; + } + } + + return 0; +} + +/* Return 1 if THREAD can only be executed in one way. If LABEL is non-zero, + it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH + is non-zero, we are allowed to fall into this thread; otherwise, we are + not. + + If LABEL is used more than one or we pass a label other than LABEL before + finding an active insn, we do not own this thread. */ + +static int +own_thread_p (thread, label, allow_fallthrough) + rtx thread; + rtx label; + int allow_fallthrough; +{ + rtx active_insn; + rtx insn; + + /* We don't own the function end. */ + if (thread == 0) + return 0; + + /* Get the first active insn, or THREAD, if it is an active insn. */ + active_insn = next_active_insn (PREV_INSN (thread)); + + for (insn = thread; insn != active_insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == CODE_LABEL + && (insn != label || LABEL_NUSES (insn) != 1)) + return 0; + + if (allow_fallthrough) + return 1; + + /* Ensure that we reach a BARRIER before any insn or label. */ + for (insn = prev_nonnote_insn (thread); + insn == 0 || GET_CODE (insn) != BARRIER; + insn = prev_nonnote_insn (insn)) + if (insn == 0 + || GET_CODE (insn) == CODE_LABEL + || (GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) != USE + && GET_CODE (PATTERN (insn)) != CLOBBER)) + return 0; + + return 1; +} + +/* Find the number of the basic block that starts closest to INSN. Return -1 + if we couldn't find such a basic block. */ + +static int +find_basic_block (insn) + rtx insn; +{ + int i; + + /* Scan backwards to the previous BARRIER. Then see if we can find a + label that starts a basic block. Return the basic block number. */ + + for (insn = prev_nonnote_insn (insn); + insn && GET_CODE (insn) != BARRIER; + insn = prev_nonnote_insn (insn)) + ; + + /* The start of the function is basic block zero. */ + if (insn == 0) + return 0; + + /* See if any of the upcoming CODE_LABELs start a basic block. If we reach + anything other than a CODE_LABEL or note, we can't find this code. */ + for (insn = next_nonnote_insn (insn); + insn && GET_CODE (insn) == CODE_LABEL; + insn = next_nonnote_insn (insn)) + { + for (i = 0; i < n_basic_blocks; i++) + if (insn == basic_block_head[i]) + return i; + } + + return -1; +} + +/* Called when INSN is being moved from a location near the target of a jump. + We leave a marker of the form (use (INSN)) immediately in front + of WHERE for mark_target_live_regs. These markers will be deleted when + reorg finishes. + + We used to try to update the live status of registers if WHERE is at + the start of a basic block, but that can't work since we may remove a + BARRIER in relax_delay_slots. */ + +static void +update_block (insn, where) + rtx insn; + rtx where; +{ + int b; + + /* Ignore if this was in a delay slot and it came from the target of + a branch. */ + if (INSN_FROM_TARGET_P (insn)) + return; + + emit_insn_before (gen_rtx (USE, VOIDmode, insn), where); + + /* INSN might be making a value live in a block where it didn't use to + be. So recompute liveness information for this block. */ + + b = find_basic_block (insn); + if (b != -1) + bb_ticks[b]++; +} + +/* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for + the basic block containing the jump. */ + +static int +reorg_redirect_jump (jump, nlabel) + rtx jump; + rtx nlabel; +{ + int b = find_basic_block (jump); + + if (b != -1) + bb_ticks[b]++; + + return redirect_jump (jump, nlabel); +} + +/* Called when INSN is being moved forward into a delay slot of DELAYED_INSN. + We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes + that reference values used in INSN. If we find one, then we move the + REG_DEAD note to INSN. + + This is needed to handle the case where an later insn (after INSN) has a + REG_DEAD note for a register used by INSN, and this later insn subsequently + gets moved before a CODE_LABEL because it is a redundant insn. In this + case, mark_target_live_regs may be confused into thinking the register + is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */ + +static void +update_reg_dead_notes (insn, delayed_insn) + rtx insn, delayed_insn; +{ + rtx p, link, next; + + for (p = next_nonnote_insn (insn); p != delayed_insn; + p = next_nonnote_insn (p)) + for (link = REG_NOTES (p); link; link = next) + { + next = XEXP (link, 1); + + if (REG_NOTE_KIND (link) != REG_DEAD + || GET_CODE (XEXP (link, 0)) != REG) + continue; + + if (reg_referenced_p (XEXP (link, 0), PATTERN (insn))) + { + /* Move the REG_DEAD note from P to INSN. */ + remove_note (p, link); + XEXP (link, 1) = REG_NOTES (insn); + REG_NOTES (insn) = link; + } + } +} + +/* Marks registers possibly live at the current place being scanned by + mark_target_live_regs. Used only by next two function. */ + +static HARD_REG_SET current_live_regs; + +/* Marks registers for which we have seen a REG_DEAD note but no assignment. + Also only used by the next two functions. */ + +static HARD_REG_SET pending_dead_regs; + +/* Utility function called from mark_target_live_regs via note_stores. + It deadens any CLOBBERed registers and livens any SET registers. */ + +static void +update_live_status (dest, x) + rtx dest; + rtx x; +{ + int first_regno, last_regno; + int i; + + if (GET_CODE (dest) != REG + && (GET_CODE (dest) != SUBREG || GET_CODE (SUBREG_REG (dest)) != REG)) + return; + + if (GET_CODE (dest) == SUBREG) + first_regno = REGNO (SUBREG_REG (dest)) + SUBREG_WORD (dest); + else + first_regno = REGNO (dest); + + last_regno = first_regno + HARD_REGNO_NREGS (first_regno, GET_MODE (dest)); + + if (GET_CODE (x) == CLOBBER) + for (i = first_regno; i < last_regno; i++) + CLEAR_HARD_REG_BIT (current_live_regs, i); + else + for (i = first_regno; i < last_regno; i++) + { + SET_HARD_REG_BIT (current_live_regs, i); + CLEAR_HARD_REG_BIT (pending_dead_regs, i); + } +} + +/* Similar to next_insn, but ignores insns in the delay slots of + an annulled branch. */ + +static rtx +next_insn_no_annul (insn) + rtx insn; +{ + if (insn) + { + /* If INSN is an annulled branch, skip any insns from the target + of the branch. */ + if (INSN_ANNULLED_BRANCH_P (insn) + && NEXT_INSN (PREV_INSN (insn)) != insn) + while (INSN_FROM_TARGET_P (NEXT_INSN (insn))) + insn = NEXT_INSN (insn); + + insn = NEXT_INSN (insn); + if (insn && GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == SEQUENCE) + insn = XVECEXP (PATTERN (insn), 0, 0); + } + + return insn; +} + +/* Set the resources that are live at TARGET. + + If TARGET is zero, we refer to the end of the current function and can + return our precomputed value. + + Otherwise, we try to find out what is live by consulting the basic block + information. This is tricky, because we must consider the actions of + reload and jump optimization, which occur after the basic block information + has been computed. + + Accordingly, we proceed as follows:: + + We find the previous BARRIER and look at all immediately following labels + (with no intervening active insns) to see if any of them start a basic + block. If we hit the start of the function first, we use block 0. + + Once we have found a basic block and a corresponding first insns, we can + accurately compute the live status from basic_block_live_regs and + reg_renumber. (By starting at a label following a BARRIER, we are immune + to actions taken by reload and jump.) Then we scan all insns between + that point and our target. For each CLOBBER (or for call-clobbered regs + when we pass a CALL_INSN), mark the appropriate registers are dead. For + a SET, mark them as live. + + We have to be careful when using REG_DEAD notes because they are not + updated by such things as find_equiv_reg. So keep track of registers + marked as dead that haven't been assigned to, and mark them dead at the + next CODE_LABEL since reload and jump won't propagate values across labels. + + If we cannot find the start of a basic block (should be a very rare + case, if it can happen at all), mark everything as potentially live. + + Next, scan forward from TARGET looking for things set or clobbered + before they are used. These are not live. + + Because we can be called many times on the same target, save our results + in a hash table indexed by INSN_UID. */ + +static void +mark_target_live_regs (target, res) + rtx target; + struct resources *res; +{ + int b = -1; + int i; + struct target_info *tinfo; + rtx insn, next; + rtx jump_insn = 0; + rtx jump_target; + HARD_REG_SET scratch; + struct resources set, needed; + int jump_count = 0; + + /* Handle end of function. */ + if (target == 0) + { + *res = end_of_function_needs; + return; + } + + /* We have to assume memory is needed, but the CC isn't. */ + res->memory = 1; + res->volatil = 0; + res->cc = 0; + + /* See if we have computed this value already. */ + for (tinfo = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME]; + tinfo; tinfo = tinfo->next) + if (tinfo->uid == INSN_UID (target)) + break; + + /* Start by getting the basic block number. If we have saved information, + we can get it from there unless the insn at the start of the basic block + has been deleted. */ + if (tinfo && tinfo->block != -1 + && ! INSN_DELETED_P (basic_block_head[tinfo->block])) + b = tinfo->block; + + if (b == -1) + b = find_basic_block (target); + + if (tinfo) + { + /* If the information is up-to-date, use it. Otherwise, we will + update it below. */ + if (b == tinfo->block && b != -1 && tinfo->bb_tick == bb_ticks[b]) + { + COPY_HARD_REG_SET (res->regs, tinfo->live_regs); + return; + } + } + else + { + /* Allocate a place to put our results and chain it into the + hash table. */ + tinfo = (struct target_info *) oballoc (sizeof (struct target_info)); + tinfo->uid = INSN_UID (target); + tinfo->block = b; + tinfo->next = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME]; + target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME] = tinfo; + } + + CLEAR_HARD_REG_SET (pending_dead_regs); + + /* If we found a basic block, get the live registers from it and update + them with anything set or killed between its start and the insn before + TARGET. Otherwise, we must assume everything is live. */ + if (b != -1) + { + regset regs_live = basic_block_live_at_start[b]; + int offset, j; + REGSET_ELT_TYPE bit; + int regno; + rtx start_insn, stop_insn; + + /* Compute hard regs live at start of block -- this is the real hard regs + marked live, plus live pseudo regs that have been renumbered to + hard regs. */ + +#ifdef HARD_REG_SET + current_live_regs = *regs_live; +#else + COPY_HARD_REG_SET (current_live_regs, regs_live); +#endif + + for (offset = 0, i = 0; offset < regset_size; offset++) + { + if (regs_live[offset] == 0) + i += REGSET_ELT_BITS; + else + for (bit = 1; bit && i < max_regno; bit <<= 1, i++) + if ((regs_live[offset] & bit) + && (regno = reg_renumber[i]) >= 0) + for (j = regno; + j < regno + HARD_REGNO_NREGS (regno, + PSEUDO_REGNO_MODE (i)); + j++) + SET_HARD_REG_BIT (current_live_regs, j); + } + + /* Get starting and ending insn, handling the case where each might + be a SEQUENCE. */ + start_insn = (b == 0 ? get_insns () : basic_block_head[b]); + stop_insn = target; + + if (GET_CODE (start_insn) == INSN + && GET_CODE (PATTERN (start_insn)) == SEQUENCE) + start_insn = XVECEXP (PATTERN (start_insn), 0, 0); + + if (GET_CODE (stop_insn) == INSN + && GET_CODE (PATTERN (stop_insn)) == SEQUENCE) + stop_insn = next_insn (PREV_INSN (stop_insn)); + + for (insn = start_insn; insn != stop_insn; + insn = next_insn_no_annul (insn)) + { + rtx link; + rtx real_insn = insn; + + /* If this insn is from the target of a branch, it isn't going to + be used in the sequel. If it is used in both cases, this + test will not be true. */ + if (INSN_FROM_TARGET_P (insn)) + continue; + + /* If this insn is a USE made by update_block, we care about the + underlying insn. */ + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE + && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i') + real_insn = XEXP (PATTERN (insn), 0); + + if (GET_CODE (real_insn) == CALL_INSN) + { + /* CALL clobbers all call-used regs that aren't fixed except + sp, ap, and fp. Do this before setting the result of the + call live. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (call_used_regs[i] + && i != STACK_POINTER_REGNUM && i != FRAME_POINTER_REGNUM + && i != ARG_POINTER_REGNUM +#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM + && ! (i == ARG_POINTER_REGNUM && fixed_regs[i]) +#endif +#ifdef PIC_OFFSET_TABLE_REGNUM + && ! (i == PIC_OFFSET_TABLE_REGNUM && flag_pic) +#endif + ) + CLEAR_HARD_REG_BIT (current_live_regs, i); + + /* A CALL_INSN sets any global register live, since it may + have been modified by the call. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (global_regs[i]) + SET_HARD_REG_BIT (current_live_regs, i); + } + + /* Mark anything killed in an insn to be deadened at the next + label. Ignore USE insns; the only REG_DEAD notes will be for + parameters. But they might be early. A CALL_INSN will usually + clobber registers used for parameters. It isn't worth bothering + with the unlikely case when it won't. */ + if ((GET_CODE (real_insn) == INSN + && GET_CODE (PATTERN (real_insn)) != USE) + || GET_CODE (real_insn) == JUMP_INSN + || GET_CODE (real_insn) == CALL_INSN) + { + for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_DEAD + && GET_CODE (XEXP (link, 0)) == REG + && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER) + { + int first_regno = REGNO (XEXP (link, 0)); + int last_regno + = (first_regno + + HARD_REGNO_NREGS (first_regno, + GET_MODE (XEXP (link, 0)))); + + for (i = first_regno; i < last_regno; i++) + SET_HARD_REG_BIT (pending_dead_regs, i); + } + + note_stores (PATTERN (real_insn), update_live_status); + + /* If any registers were unused after this insn, kill them. + These notes will always be accurate. */ + for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == REG_UNUSED + && GET_CODE (XEXP (link, 0)) == REG + && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER) + { + int first_regno = REGNO (XEXP (link, 0)); + int last_regno + = (first_regno + + HARD_REGNO_NREGS (first_regno, + GET_MODE (XEXP (link, 0)))); + + for (i = first_regno; i < last_regno; i++) + CLEAR_HARD_REG_BIT (current_live_regs, i); + } + } + + else if (GET_CODE (real_insn) == CODE_LABEL) + { + /* A label clobbers the pending dead registers since neither + reload nor jump will propagate a value across a label. */ + AND_COMPL_HARD_REG_SET (current_live_regs, pending_dead_regs); + CLEAR_HARD_REG_SET (pending_dead_regs); + } + + /* The beginning of the epilogue corresponds to the end of the + RTL chain when there are no epilogue insns. Certain resources + are implicitly required at that point. */ + else if (GET_CODE (real_insn) == NOTE + && NOTE_LINE_NUMBER (real_insn) == NOTE_INSN_EPILOGUE_BEG) + IOR_HARD_REG_SET (current_live_regs, start_of_epilogue_needs.regs); + } + + COPY_HARD_REG_SET (res->regs, current_live_regs); + tinfo->block = b; + tinfo->bb_tick = bb_ticks[b]; + } + else + /* We didn't find the start of a basic block. Assume everything + in use. This should happen only extremely rarely. */ + SET_HARD_REG_SET (res->regs); + + /* Now step forward from TARGET looking for registers that are set before + they are used. These are dead. If we pass a label, any pending dead + registers that weren't yet used can be made dead. Stop when we pass a + conditional JUMP_INSN; follow the first few unconditional branches. */ + + CLEAR_RESOURCE (&set); + CLEAR_RESOURCE (&needed); + + for (insn = target; insn; insn = next) + { + rtx this_jump_insn = insn; + + next = NEXT_INSN (insn); + switch (GET_CODE (insn)) + { + case CODE_LABEL: + AND_COMPL_HARD_REG_SET (pending_dead_regs, needed.regs); + AND_COMPL_HARD_REG_SET (res->regs, pending_dead_regs); + CLEAR_HARD_REG_SET (pending_dead_regs); + continue; + + case BARRIER: + case NOTE: + continue; + + case INSN: + if (GET_CODE (PATTERN (insn)) == USE) + { + /* If INSN is a USE made by update_block, we care about the + underlying insn. Any registers set by the underlying insn + are live since the insn is being done somewhere else. */ + if (GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i') + mark_set_resources (XEXP (PATTERN (insn), 0), res, 0, 1); + + /* All other USE insns are to be ignored. */ + continue; + } + else if (GET_CODE (PATTERN (insn)) == CLOBBER) + continue; + else if (GET_CODE (PATTERN (insn)) == SEQUENCE) + { + /* An unconditional jump can be used to fill the delay slot + of a call, so search for a JUMP_INSN in any position. */ + for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) + { + this_jump_insn = XVECEXP (PATTERN (insn), 0, i); + if (GET_CODE (this_jump_insn) == JUMP_INSN) + break; + } + } + } + + if (GET_CODE (this_jump_insn) == JUMP_INSN) + { + if (jump_count++ < 10 + && (simplejump_p (this_jump_insn) + || GET_CODE (PATTERN (this_jump_insn)) == RETURN)) + { + next = next_active_insn (JUMP_LABEL (this_jump_insn)); + if (jump_insn == 0) + { + jump_insn = insn; + jump_target = JUMP_LABEL (this_jump_insn); + } + } + else + break; + } + + mark_referenced_resources (insn, &needed, 1); + mark_set_resources (insn, &set, 0, 1); + + COPY_HARD_REG_SET (scratch, set.regs); + AND_COMPL_HARD_REG_SET (scratch, needed.regs); + AND_COMPL_HARD_REG_SET (res->regs, scratch); + } + + /* If we hit an unconditional branch, we have another way of finding out + what is live: we can see what is live at the branch target and include + anything used but not set before the branch. The only things that are + live are those that are live using the above test and the test below. + + Don't try this if we expired our jump count above, since that would + mean there may be an infinite loop in the function being compiled. */ + + if (jump_insn && jump_count < 10) + { + struct resources new_resources; + rtx stop_insn = next_active_insn (jump_insn); + + mark_target_live_regs (next_active_insn (jump_target), &new_resources); + CLEAR_RESOURCE (&set); + CLEAR_RESOURCE (&needed); + + /* Include JUMP_INSN in the needed registers. */ + for (insn = target; insn != stop_insn; insn = next_active_insn (insn)) + { + mark_referenced_resources (insn, &needed, 1); + + COPY_HARD_REG_SET (scratch, needed.regs); + AND_COMPL_HARD_REG_SET (scratch, set.regs); + IOR_HARD_REG_SET (new_resources.regs, scratch); + + mark_set_resources (insn, &set, 0, 1); + } + + AND_HARD_REG_SET (res->regs, new_resources.regs); + } + + COPY_HARD_REG_SET (tinfo->live_regs, res->regs); +} + +/* Scan a function looking for insns that need a delay slot and find insns to + put into the delay slot. + + NON_JUMPS_P is non-zero if we are to only try to fill non-jump insns (such + as calls). We do these first since we don't want jump insns (that are + easier to fill) to get the only insns that could be used for non-jump insns. + When it is zero, only try to fill JUMP_INSNs. + + When slots are filled in this manner, the insns (including the + delay_insn) are put together in a SEQUENCE rtx. In this fashion, + it is possible to tell whether a delay slot has really been filled + or not. `final' knows how to deal with this, by communicating + through FINAL_SEQUENCE. */ + +static void +fill_simple_delay_slots (first, non_jumps_p) + rtx first; + int non_jumps_p; +{ + register rtx insn, pat, trial, next_trial; + register int i, j; + int num_unfilled_slots = unfilled_slots_next - unfilled_slots_base; + struct resources needed, set; + register int slots_to_fill, slots_filled; + rtx delay_list; + + for (i = 0; i < num_unfilled_slots; i++) + { + int flags; + /* Get the next insn to fill. If it has already had any slots assigned, + we can't do anything with it. Maybe we'll improve this later. */ + + insn = unfilled_slots_base[i]; + if (insn == 0 + || INSN_DELETED_P (insn) + || (GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == SEQUENCE) + || (GET_CODE (insn) == JUMP_INSN && non_jumps_p) + || (GET_CODE (insn) != JUMP_INSN && ! non_jumps_p)) + continue; + + flags = get_jump_flags (insn, JUMP_LABEL (insn)); + slots_to_fill = num_delay_slots (insn); + if (slots_to_fill == 0) + abort (); + + /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL + says how many. After initialization, first try optimizing + + call _foo call _foo + nop add %o7,.-L1,%o7 + b,a L1 + nop + + If this case applies, the delay slot of the call is filled with + the unconditional jump. This is done first to avoid having the + delay slot of the call filled in the backward scan. Also, since + the unconditional jump is likely to also have a delay slot, that + insn must exist when it is subsequently scanned. */ + + slots_filled = 0; + delay_list = 0; + + if (GET_CODE (insn) == CALL_INSN + && (trial = next_active_insn (insn)) + && GET_CODE (trial) == JUMP_INSN + && simplejump_p (trial) + && eligible_for_delay (insn, slots_filled, trial, flags) + && no_labels_between_p (insn, trial)) + { + slots_filled++; + delay_list = add_to_delay_list (trial, delay_list); + /* Remove the unconditional jump from consideration for delay slot + filling and unthread it. */ + if (unfilled_slots_base[i + 1] == trial) + unfilled_slots_base[i + 1] = 0; + { + rtx next = NEXT_INSN (trial); + rtx prev = PREV_INSN (trial); + if (prev) + NEXT_INSN (prev) = next; + if (next) + PREV_INSN (next) = prev; + } + } + + /* Now, scan backwards from the insn to search for a potential + delay-slot candidate. Stop searching when a label or jump is hit. + + For each candidate, if it is to go into the delay slot (moved + forward in execution sequence), it must not need or set any resources + that were set by later insns and must not set any resources that + are needed for those insns. + + The delay slot insn itself sets resources unless it is a call + (in which case the called routine, not the insn itself, is doing + the setting). */ + + if (slots_filled < slots_to_fill) + { + CLEAR_RESOURCE (&needed); + CLEAR_RESOURCE (&set); + mark_set_resources (insn, &set, 0, 0); + mark_referenced_resources (insn, &needed, 0); + + for (trial = prev_nonnote_insn (insn); ! stop_search_p (trial, 1); + trial = next_trial) + { + next_trial = prev_nonnote_insn (trial); + + /* This must be an INSN or CALL_INSN. */ + pat = PATTERN (trial); + + /* USE and CLOBBER at this level was just for flow; ignore it. */ + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + continue; + + /* Check for resource conflict first, to avoid unnecessary + splitting. */ + if (! insn_references_resource_p (trial, &set, 1) + && ! insn_sets_resource_p (trial, &set, 1) + && ! insn_sets_resource_p (trial, &needed, 1) +#ifdef HAVE_cc0 + /* Can't separate set of cc0 from its use. */ + && ! (reg_mentioned_p (cc0_rtx, pat) + && ! sets_cc0_p (cc0_rtx, pat)) +#endif + ) + { + trial = try_split (pat, trial, 1); + next_trial = prev_nonnote_insn (trial); + if (eligible_for_delay (insn, slots_filled, trial, flags)) + { + /* In this case, we are searching backward, so if we + find insns to put on the delay list, we want + to put them at the head, rather than the + tail, of the list. */ + + update_reg_dead_notes (trial, insn); + delay_list = gen_rtx (INSN_LIST, VOIDmode, + trial, delay_list); + update_block (trial, trial); + delete_insn (trial); + if (slots_to_fill == ++slots_filled) + break; + continue; + } + } + + mark_set_resources (trial, &set, 0, 1); + mark_referenced_resources (trial, &needed, 1); + } + } + + /* If all needed slots haven't been filled, we come here. */ + + /* Try to optimize case of jumping around a single insn. */ +#if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS) + if (slots_filled != slots_to_fill + && delay_list == 0 + && GET_CODE (insn) == JUMP_INSN && condjump_p (insn)) + { + delay_list = optimize_skip (insn); + if (delay_list) + slots_filled += 1; + } +#endif + + /* Try to get insns from beyond the insn needing the delay slot. + These insns can neither set or reference resources set in insns being + skipped, cannot set resources in the insn being skipped, and, if this + is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the + call might not return). + + If this is a conditional jump, see if it merges back to us early + enough for us to pick up insns from the merge point. Don't do + this if there is another branch to our label unless we pass all of + them. + + Another similar merge is if we jump to the same place that a + later unconditional jump branches to. In that case, we don't + care about the number of uses of our label. */ + + if (slots_filled != slots_to_fill + && (GET_CODE (insn) != JUMP_INSN + || (condjump_p (insn) && ! simplejump_p (insn) + && JUMP_LABEL (insn) != 0))) + { + rtx target = 0; + int maybe_never = 0; + int passed_label = 0; + int target_uses; + struct resources needed_at_jump; + + CLEAR_RESOURCE (&needed); + CLEAR_RESOURCE (&set); + + if (GET_CODE (insn) == CALL_INSN) + { + mark_set_resources (insn, &set, 0, 1); + mark_referenced_resources (insn, &needed, 1); + maybe_never = 1; + } + else + { + mark_set_resources (insn, &set, 0, 1); + mark_referenced_resources (insn, &needed, 1); + if (GET_CODE (insn) == JUMP_INSN) + { + /* Get our target and show how many more uses we want to + see before we hit the label. */ + target = JUMP_LABEL (insn); + target_uses = LABEL_NUSES (target) - 1; + } + + } + + for (trial = next_nonnote_insn (insn); trial; trial = next_trial) + { + rtx pat, trial_delay; + + next_trial = next_nonnote_insn (trial); + + if (GET_CODE (trial) == CODE_LABEL) + { + passed_label = 1; + + /* If this is our target, see if we have seen all its uses. + If so, indicate we have passed our target and ignore it. + All other labels cause us to stop our search. */ + if (trial == target && target_uses == 0) + { + target = 0; + continue; + } + else + break; + } + else if (GET_CODE (trial) == BARRIER) + break; + + /* We must have an INSN, JUMP_INSN, or CALL_INSN. */ + pat = PATTERN (trial); + + /* Stand-alone USE and CLOBBER are just for flow. */ + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + continue; + + /* If this already has filled delay slots, get the insn needing + the delay slots. */ + if (GET_CODE (pat) == SEQUENCE) + trial_delay = XVECEXP (pat, 0, 0); + else + trial_delay = trial; + + /* If this is a jump insn to our target, indicate that we have + seen another jump to it. If we aren't handling a conditional + jump, stop our search. Otherwise, compute the needs at its + target and add them to NEEDED. */ + if (GET_CODE (trial_delay) == JUMP_INSN) + { + if (target == 0) + break; + else if (JUMP_LABEL (trial_delay) == target) + target_uses--; + else + { + mark_target_live_regs + (next_active_insn (JUMP_LABEL (trial_delay)), + &needed_at_jump); + needed.memory |= needed_at_jump.memory; + IOR_HARD_REG_SET (needed.regs, needed_at_jump.regs); + } + } + + /* See if we have a resource problem before we try to + split. */ + if (target == 0 + && GET_CODE (pat) != SEQUENCE + && ! insn_references_resource_p (trial, &set, 1) + && ! insn_sets_resource_p (trial, &set, 1) + && ! insn_sets_resource_p (trial, &needed, 1) +#ifdef HAVE_cc0 + && ! (reg_mentioned_p (cc0_rtx, pat) && ! sets_cc0_p (pat)) +#endif + && ! (maybe_never && may_trap_p (pat)) + && (trial = try_split (pat, trial, 0)) + && eligible_for_delay (insn, slots_filled, trial, flags)) + { + next_trial = next_nonnote_insn (trial); + delay_list = add_to_delay_list (trial, delay_list); + +#ifdef HAVE_cc0 + if (reg_mentioned_p (cc0_rtx, pat)) + link_cc0_insns (trial); +#endif + + if (passed_label) + update_block (trial, trial); + delete_insn (trial); + if (slots_to_fill == ++slots_filled) + break; + continue; + } + + mark_set_resources (trial, &set, 0, 1); + mark_referenced_resources (trial, &needed, 1); + + /* Ensure we don't put insns between the setting of cc and the + comparison by moving a setting of cc into an earlier delay + slot since these insns could clobber the condition code. */ + set.cc = 1; + + /* If this is a call or jump, we might not get here. */ + if (GET_CODE (trial) == CALL_INSN + || GET_CODE (trial) == JUMP_INSN) + maybe_never = 1; + } + + /* If there are slots left to fill and our search was stopped by an + unconditional branch, try the insn at the branch target. We can + redirect the branch if it works. */ + if (slots_to_fill != slots_filled + && trial + && GET_CODE (trial) == JUMP_INSN + && simplejump_p (trial) + && (target == 0 || JUMP_LABEL (trial) == target) + && (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0 + && ! (GET_CODE (next_trial) == INSN + && GET_CODE (PATTERN (next_trial)) == SEQUENCE) + && ! insn_references_resource_p (next_trial, &set, 1) + && ! insn_sets_resource_p (next_trial, &set, 1) + && ! insn_sets_resource_p (next_trial, &needed, 1) +#ifdef HAVE_cc0 + && ! reg_mentioned_p (cc0_rtx, PATTERN (next_trial)) +#endif + && ! (maybe_never && may_trap_p (PATTERN (next_trial))) + && (next_trial = try_split (PATTERN (next_trial), next_trial, 0)) + && eligible_for_delay (insn, slots_filled, next_trial, flags)) + { + rtx new_label = next_active_insn (next_trial); + + if (new_label != 0) + new_label = get_label_before (new_label); + + delay_list + = add_to_delay_list (copy_rtx (next_trial), delay_list); + slots_filled++; + reorg_redirect_jump (trial, new_label); + + /* If we merged because we both jumped to the same place, + redirect the original insn also. */ + if (target) + reorg_redirect_jump (insn, new_label); + } + } + + if (delay_list) + unfilled_slots_base[i] + = emit_delay_sequence (insn, delay_list, + slots_filled, slots_to_fill); + + if (slots_to_fill == slots_filled) + unfilled_slots_base[i] = 0; + + note_delay_statistics (slots_filled, 0); + } + +#ifdef DELAY_SLOTS_FOR_EPILOGUE + /* See if the epilogue needs any delay slots. Try to fill them if so. + The only thing we can do is scan backwards from the end of the + function. If we did this in a previous pass, it is incorrect to do it + again. */ + if (current_function_epilogue_delay_list) + return; + + slots_to_fill = DELAY_SLOTS_FOR_EPILOGUE; + if (slots_to_fill == 0) + return; + + slots_filled = 0; + CLEAR_RESOURCE (&needed); + CLEAR_RESOURCE (&set); + + for (trial = get_last_insn (); ! stop_search_p (trial, 1); + trial = PREV_INSN (trial)) + { + if (GET_CODE (trial) == NOTE) + continue; + pat = PATTERN (trial); + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + continue; + + if (! insn_references_resource_p (trial, &set, 1) + && ! insn_sets_resource_p (trial, &needed, 1) +#ifdef HAVE_cc0 + /* Don't want to mess with cc0 here. */ + && ! reg_mentioned_p (cc0_rtx, pat) +#endif + ) + { + trial = try_split (pat, trial, 1); + if (ELIGIBLE_FOR_EPILOGUE_DELAY (trial, slots_filled)) + { + /* Here as well we are searching backward, so put the + insns we find on the head of the list. */ + + current_function_epilogue_delay_list + = gen_rtx (INSN_LIST, VOIDmode, trial, + current_function_epilogue_delay_list); + mark_referenced_resources (trial, &end_of_function_needs, 1); + update_block (trial, trial); + delete_insn (trial); + + /* Clear deleted bit so final.c will output the insn. */ + INSN_DELETED_P (trial) = 0; + + if (slots_to_fill == ++slots_filled) + break; + continue; + } + } + + mark_set_resources (trial, &set, 0, 1); + mark_referenced_resources (trial, &needed, 1); + } + + note_delay_statistics (slots_filled, 0); +#endif +} + +/* Try to find insns to place in delay slots. + + INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION + or is an unconditional branch if CONDITION is const_true_rtx. + *PSLOTS_FILLED is updated with the number of slots that we have filled. + + THREAD is a flow-of-control, either the insns to be executed if the + branch is true or if the branch is false, THREAD_IF_TRUE says which. + + OPPOSITE_THREAD is the thread in the opposite direction. It is used + to see if any potential delay slot insns set things needed there. + + LIKELY is non-zero if it is extremely likely that the branch will be + taken and THREAD_IF_TRUE is set. This is used for the branch at the + end of a loop back up to the top. + + OWN_THREAD and OWN_OPPOSITE_THREAD are true if we are the only user of the + thread. I.e., it is the fallthrough code of our jump or the target of the + jump when we are the only jump going there. + + If OWN_THREAD is false, it must be the "true" thread of a jump. In that + case, we can only take insns from the head of the thread for our delay + slot. We then adjust the jump to point after the insns we have taken. */ + +static rtx +fill_slots_from_thread (insn, condition, thread, opposite_thread, likely, + thread_if_true, own_thread, own_opposite_thread, + slots_to_fill, pslots_filled) + rtx insn; + rtx condition; + rtx thread, opposite_thread; + int likely; + int thread_if_true; + int own_thread, own_opposite_thread; + int slots_to_fill, *pslots_filled; +{ + rtx new_thread; + rtx delay_list = 0; + struct resources opposite_needed, set, needed; + rtx trial; + int lose = 0; + int must_annul = 0; + int flags; + + /* Validate our arguments. */ + if ((condition == const_true_rtx && ! thread_if_true) + || (! own_thread && ! thread_if_true)) + abort (); + + flags = get_jump_flags (insn, JUMP_LABEL (insn)); + + /* If our thread is the end of subroutine, we can't get any delay + insns from that. */ + if (thread == 0) + return 0; + + /* If this is an unconditional branch, nothing is needed at the + opposite thread. Otherwise, compute what is needed there. */ + if (condition == const_true_rtx) + CLEAR_RESOURCE (&opposite_needed); + else + mark_target_live_regs (opposite_thread, &opposite_needed); + + /* If the insn at THREAD can be split, do it here to avoid having to + update THREAD and NEW_THREAD if it is done in the loop below. Also + initialize NEW_THREAD. */ + + new_thread = thread = try_split (PATTERN (thread), thread, 0); + + /* Scan insns at THREAD. We are looking for an insn that can be removed + from THREAD (it neither sets nor references resources that were set + ahead of it and it doesn't set anything needs by the insns ahead of + it) and that either can be placed in an annulling insn or aren't + needed at OPPOSITE_THREAD. */ + + CLEAR_RESOURCE (&needed); + CLEAR_RESOURCE (&set); + + /* If we do not own this thread, we must stop as soon as we find + something that we can't put in a delay slot, since all we can do + is branch into THREAD at a later point. Therefore, labels stop + the search if this is not the `true' thread. */ + + for (trial = thread; + ! stop_search_p (trial, ! thread_if_true) && (! lose || own_thread); + trial = next_nonnote_insn (trial)) + { + rtx pat, old_trial; + + /* If we have passed a label, we no longer own this thread. */ + if (GET_CODE (trial) == CODE_LABEL) + { + own_thread = 0; + continue; + } + + pat = PATTERN (trial); + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + continue; + + /* If TRIAL conflicts with the insns ahead of it, we lose. Also, + don't separate or copy insns that set and use CC0. */ + if (! insn_references_resource_p (trial, &set, 1) + && ! insn_sets_resource_p (trial, &set, 1) + && ! insn_sets_resource_p (trial, &needed, 1) +#ifdef HAVE_cc0 + && ! (reg_mentioned_p (cc0_rtx, pat) + && (! own_thread || ! sets_cc0_p (pat))) +#endif + ) + { + /* If TRIAL is redundant with some insn before INSN, we don't + actually need to add it to the delay list; we can merely pretend + we did. */ + if (redundant_insn_p (trial, insn, delay_list)) + { + if (own_thread) + { + update_block (trial, thread); + delete_insn (trial); + } + else + new_thread = next_active_insn (trial); + + continue; + } + + /* There are two ways we can win: If TRIAL doesn't set anything + needed at the opposite thread and can't trap, or if it can + go into an annulled delay slot. */ + if (condition == const_true_rtx + || (! insn_sets_resource_p (trial, &opposite_needed, 1) + && ! may_trap_p (pat))) + { + old_trial = trial; + trial = try_split (pat, trial, 0); + if (new_thread == old_trial) + new_thread = trial; + pat = PATTERN (trial); + if (eligible_for_delay (insn, *pslots_filled, trial, flags)) + goto winner; + } + else if (0 +#ifdef ANNUL_IFTRUE_SLOTS + || ! thread_if_true +#endif +#ifdef ANNUL_IFFALSE_SLOTS + || thread_if_true +#endif + ) + { + old_trial = trial; + trial = try_split (pat, trial, 0); + if (new_thread == old_trial) + new_thread = trial; + pat = PATTERN (trial); + if ((thread_if_true + ? eligible_for_annul_false (insn, *pslots_filled, trial, flags) + : eligible_for_annul_true (insn, *pslots_filled, trial, flags))) + { + rtx temp; + + must_annul = 1; + winner: + +#ifdef HAVE_cc0 + if (reg_mentioned_p (cc0_rtx, pat)) + link_cc0_insns (trial); +#endif + + /* If we own this thread, delete the insn. If this is the + destination of a branch, show that a basic block status + may have been updated. In any case, mark the new + starting point of this thread. */ + if (own_thread) + { + update_block (trial, thread); + delete_insn (trial); + } + else + new_thread = next_active_insn (trial); + + temp = own_thread ? trial : copy_rtx (trial); + if (thread_if_true) + INSN_FROM_TARGET_P (temp) = 1; + + delay_list = add_to_delay_list (temp, delay_list); + + if (slots_to_fill == ++(*pslots_filled)) + { + /* Even though we have filled all the slots, we + may be branching to a location that has a + redundant insn. Skip any if so. */ + while (new_thread && ! own_thread + && ! insn_sets_resource_p (new_thread, &set, 1) + && ! insn_sets_resource_p (new_thread, &needed, 1) + && ! insn_references_resource_p (new_thread, + &set, 1) + && redundant_insn_p (new_thread, insn, + delay_list)) + new_thread = next_active_insn (new_thread); + break; + } + + continue; + } + } + } + + /* This insn can't go into a delay slot. */ + lose = 1; + mark_set_resources (trial, &set, 0, 1); + mark_referenced_resources (trial, &needed, 1); + + /* Ensure we don't put insns between the setting of cc and the comparison + by moving a setting of cc into an earlier delay slot since these insns + could clobber the condition code. */ + set.cc = 1; + + /* If this insn is a register-register copy and the next insn has + a use of our destination, change it to use our source. That way, + it will become a candidate for our delay slot the next time + through this loop. This case occurs commonly in loops that + scan a list. + + We could check for more complex cases than those tested below, + but it doesn't seem worth it. It might also be a good idea to try + to swap the two insns. That might do better. + + We can't do this if the next insn modifies our source, because that + would make the replacement into the insn invalid. This also + prevents updating the contents of a PRE_INC. */ + + if (GET_CODE (trial) == INSN && GET_CODE (pat) == SET + && GET_CODE (SET_SRC (pat)) == REG + && GET_CODE (SET_DEST (pat)) == REG) + { + rtx next = next_nonnote_insn (trial); + + if (next && GET_CODE (next) == INSN + && GET_CODE (PATTERN (next)) != USE + && ! reg_set_p (SET_DEST (pat), next) + && reg_referenced_p (SET_DEST (pat), PATTERN (next))) + validate_replace_rtx (SET_DEST (pat), SET_SRC (pat), next); + } + } + + /* If we stopped on a branch insn that has delay slots, see if we can + steal some of the insns in those slots. */ + if (trial && GET_CODE (trial) == INSN + && GET_CODE (PATTERN (trial)) == SEQUENCE + && GET_CODE (XVECEXP (PATTERN (trial), 0, 0)) == JUMP_INSN) + { + /* If this is the `true' thread, we will want to follow the jump, + so we can only do this if we have taken everything up to here. */ + if (thread_if_true && trial == new_thread) + delay_list + = steal_delay_list_from_target (insn, condition, PATTERN (trial), + delay_list, &set, &needed, + &opposite_needed, slots_to_fill, + pslots_filled, &must_annul, + &new_thread); + else if (! thread_if_true) + delay_list + = steal_delay_list_from_fallthrough (insn, condition, + PATTERN (trial), + delay_list, &set, &needed, + &opposite_needed, slots_to_fill, + pslots_filled, &must_annul); + } + + /* If we haven't found anything for this delay slot and it is very + likely that the branch will be taken, see if the insn at our target + increments or decrements a register with an increment that does not + depend on the destination register. If so, try to place the opposite + arithmetic insn after the jump insn and put the arithmetic insn in the + delay slot. If we can't do this, return. */ + if (delay_list == 0 && likely && new_thread && GET_CODE (new_thread) == INSN) + { + rtx pat = PATTERN (new_thread); + rtx dest; + rtx src; + + trial = new_thread; + pat = PATTERN (trial); + + if (GET_CODE (trial) != INSN || GET_CODE (pat) != SET + || ! eligible_for_delay (insn, 0, trial, flags)) + return 0; + + dest = SET_DEST (pat), src = SET_SRC (pat); + if ((GET_CODE (src) == PLUS || GET_CODE (src) == MINUS) + && rtx_equal_p (XEXP (src, 0), dest) + && ! reg_overlap_mentioned_p (dest, XEXP (src, 1))) + { + rtx other = XEXP (src, 1); + rtx new_arith; + rtx ninsn; + + /* If this is a constant adjustment, use the same code with + the negated constant. Otherwise, reverse the sense of the + arithmetic. */ + if (GET_CODE (other) == CONST_INT) + new_arith = gen_rtx (GET_CODE (src), GET_MODE (src), dest, + negate_rtx (GET_MODE (src), other)); + else + new_arith = gen_rtx (GET_CODE (src) == PLUS ? MINUS : PLUS, + GET_MODE (src), dest, other); + + ninsn = emit_insn_after (gen_rtx (SET, VOIDmode, dest, new_arith), + insn); + + if (recog_memoized (ninsn) < 0 + || (insn_extract (ninsn), + ! constrain_operands (INSN_CODE (ninsn), 1))) + { + delete_insn (ninsn); + return 0; + } + + if (own_thread) + { + update_block (trial, thread); + delete_insn (trial); + } + else + new_thread = next_active_insn (trial); + + ninsn = own_thread ? trial : copy_rtx (trial); + if (thread_if_true) + INSN_FROM_TARGET_P (ninsn) = 1; + + delay_list = add_to_delay_list (ninsn, NULL_RTX); + (*pslots_filled)++; + } + } + + if (delay_list && must_annul) + INSN_ANNULLED_BRANCH_P (insn) = 1; + + /* If we are to branch into the middle of this thread, find an appropriate + label or make a new one if none, and redirect INSN to it. If we hit the + end of the function, use the end-of-function label. */ + if (new_thread != thread) + { + rtx label; + + if (! thread_if_true) + abort (); + + if (new_thread && GET_CODE (new_thread) == JUMP_INSN + && (simplejump_p (new_thread) + || GET_CODE (PATTERN (new_thread)) == RETURN)) + new_thread = follow_jumps (JUMP_LABEL (new_thread)); + + if (new_thread == 0) + label = find_end_label (); + else if (GET_CODE (new_thread) == CODE_LABEL) + label = new_thread; + else + label = get_label_before (new_thread); + + reorg_redirect_jump (insn, label); + } + + return delay_list; +} + +/* Make another attempt to find insns to place in delay slots. + + We previously looked for insns located in front of the delay insn + and, for non-jump delay insns, located behind the delay insn. + + Here only try to schedule jump insns and try to move insns from either + the target or the following insns into the delay slot. If annulling is + supported, we will be likely to do this. Otherwise, we can do this only + if safe. */ + +static void +fill_eager_delay_slots (first) + rtx first; +{ + register rtx insn; + register int i; + int num_unfilled_slots = unfilled_slots_next - unfilled_slots_base; + + for (i = 0; i < num_unfilled_slots; i++) + { + rtx condition; + rtx target_label, insn_at_target, fallthrough_insn; + rtx delay_list = 0; + int own_target; + int own_fallthrough; + int prediction, slots_to_fill, slots_filled; + + insn = unfilled_slots_base[i]; + if (insn == 0 + || INSN_DELETED_P (insn) + || GET_CODE (insn) != JUMP_INSN + || ! condjump_p (insn)) + continue; + + slots_to_fill = num_delay_slots (insn); + if (slots_to_fill == 0) + abort (); + + slots_filled = 0; + target_label = JUMP_LABEL (insn); + condition = get_branch_condition (insn, target_label); + + if (condition == 0) + continue; + + /* Get the next active fallthough and target insns and see if we own + them. Then see whether the branch is likely true. We don't need + to do a lot of this for unconditional branches. */ + + insn_at_target = next_active_insn (target_label); + own_target = own_thread_p (target_label, target_label, 0); + + if (condition == const_true_rtx) + { + own_fallthrough = 0; + fallthrough_insn = 0; + prediction = 2; + } + else + { + fallthrough_insn = next_active_insn (insn); + own_fallthrough = own_thread_p (NEXT_INSN (insn), NULL_RTX, 1); + prediction = mostly_true_jump (insn, condition); + } + + /* If this insn is expected to branch, first try to get insns from our + target, then our fallthrough insns. If it is not, expected to branch, + try the other order. */ + + if (prediction > 0) + { + delay_list + = fill_slots_from_thread (insn, condition, insn_at_target, + fallthrough_insn, prediction == 2, 1, + own_target, own_fallthrough, + slots_to_fill, &slots_filled); + + if (delay_list == 0 && own_fallthrough) + { + /* Even though we didn't find anything for delay slots, + we might have found a redundant insn which we deleted + from the thread that was filled. So we have to recompute + the next insn at the target. */ + target_label = JUMP_LABEL (insn); + insn_at_target = next_active_insn (target_label); + + delay_list + = fill_slots_from_thread (insn, condition, fallthrough_insn, + insn_at_target, 0, 0, + own_fallthrough, own_target, + slots_to_fill, &slots_filled); + } + } + else + { + if (own_fallthrough) + delay_list + = fill_slots_from_thread (insn, condition, fallthrough_insn, + insn_at_target, 0, 0, + own_fallthrough, own_target, + slots_to_fill, &slots_filled); + + if (delay_list == 0) + delay_list + = fill_slots_from_thread (insn, condition, insn_at_target, + next_active_insn (insn), 0, 1, + own_target, own_fallthrough, + slots_to_fill, &slots_filled); + } + + if (delay_list) + unfilled_slots_base[i] + = emit_delay_sequence (insn, delay_list, + slots_filled, slots_to_fill); + + if (slots_to_fill == slots_filled) + unfilled_slots_base[i] = 0; + + note_delay_statistics (slots_filled, 1); + } +} + +/* Once we have tried two ways to fill a delay slot, make a pass over the + code to try to improve the results and to do such things as more jump + threading. */ + +static void +relax_delay_slots (first) + rtx first; +{ + register rtx insn, next, pat; + register rtx trial, delay_insn, target_label; + + /* Look at every JUMP_INSN and see if we can improve it. */ + for (insn = first; insn; insn = next) + { + rtx other; + + next = next_active_insn (insn); + + /* If this is a jump insn, see if it now jumps to a jump, jumps to + the next insn, or jumps to a label that is not the last of a + group of consecutive labels. */ + if (GET_CODE (insn) == JUMP_INSN + && condjump_p (insn) + && (target_label = JUMP_LABEL (insn)) != 0) + { + target_label = follow_jumps (target_label); + target_label = prev_label (next_active_insn (target_label)); + + if (target_label == 0) + target_label = find_end_label (); + + if (next_active_insn (target_label) == next) + { + delete_jump (insn); + continue; + } + + if (target_label != JUMP_LABEL (insn)) + reorg_redirect_jump (insn, target_label); + + /* See if this jump branches around a unconditional jump. + If so, invert this jump and point it to the target of the + second jump. */ + if (next && GET_CODE (next) == JUMP_INSN + && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN) + && next_active_insn (target_label) == next_active_insn (next) + && no_labels_between_p (insn, next)) + { + rtx label = JUMP_LABEL (next); + + /* Be careful how we do this to avoid deleting code or + labels that are momentarily dead. See similar optimization + in jump.c. + + We also need to ensure we properly handle the case when + invert_jump fails. */ + + ++LABEL_NUSES (target_label); + if (label) + ++LABEL_NUSES (label); + + if (invert_jump (insn, label)) + { + delete_insn (next); + next = insn; + } + + if (label) + --LABEL_NUSES (label); + + if (--LABEL_NUSES (target_label) == 0) + delete_insn (target_label); + + continue; + } + } + + /* If this is an unconditional jump and the previous insn is a + conditional jump, try reversing the condition of the previous + insn and swapping our targets. The next pass might be able to + fill the slots. + + Don't do this if we expect the conditional branch to be true, because + we would then be making the more common case longer. */ + + if (GET_CODE (insn) == JUMP_INSN + && (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN) + && (other = prev_active_insn (insn)) != 0 + && condjump_p (other) + && no_labels_between_p (other, insn) + && 0 < mostly_true_jump (other, + get_branch_condition (other, + JUMP_LABEL (other)))) + { + rtx other_target = JUMP_LABEL (other); + target_label = JUMP_LABEL (insn); + + /* Increment the count of OTHER_TARGET, so it doesn't get deleted + as we move the label. */ + if (other_target) + ++LABEL_NUSES (other_target); + + if (invert_jump (other, target_label)) + reorg_redirect_jump (insn, other_target); + + if (other_target) + --LABEL_NUSES (other_target); + } + + /* Now look only at cases where we have filled a delay slot. */ + if (GET_CODE (insn) != INSN + || GET_CODE (PATTERN (insn)) != SEQUENCE) + continue; + + pat = PATTERN (insn); + delay_insn = XVECEXP (pat, 0, 0); + + /* See if the first insn in the delay slot is redundant with some + previous insn. Remove it from the delay slot if so; then set up + to reprocess this insn. */ + if (redundant_insn_p (XVECEXP (pat, 0, 1), delay_insn, 0)) + { + delete_from_delay_slot (XVECEXP (pat, 0, 1)); + next = prev_active_insn (next); + continue; + } + + /* Now look only at the cases where we have a filled JUMP_INSN. */ + if (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) != JUMP_INSN + || ! condjump_p (XVECEXP (PATTERN (insn), 0, 0))) + continue; + + target_label = JUMP_LABEL (delay_insn); + + if (target_label) + { + /* If this jump goes to another unconditional jump, thread it, but + don't convert a jump into a RETURN here. */ + trial = follow_jumps (target_label); + trial = prev_label (next_active_insn (trial)); + if (trial == 0 && target_label != 0) + trial = find_end_label (); + + if (trial != target_label) + { + reorg_redirect_jump (delay_insn, trial); + target_label = trial; + } + + /* If the first insn at TARGET_LABEL is redundant with a previous + insn, redirect the jump to the following insn process again. */ + trial = next_active_insn (target_label); + if (trial && GET_CODE (PATTERN (trial)) != SEQUENCE + && redundant_insn_p (trial, insn, 0)) + { + trial = next_active_insn (trial); + if (trial == 0) + target_label = find_end_label (); + else + target_label = get_label_before (trial); + reorg_redirect_jump (delay_insn, target_label); + next = insn; + continue; + } + + /* Similarly, if it is an unconditional jump with one insn in its + delay list and that insn is redundant, thread the jump. */ + if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE + && XVECLEN (PATTERN (trial), 0) == 2 + && GET_CODE (XVECEXP (PATTERN (trial), 0, 0)) == JUMP_INSN + && (simplejump_p (XVECEXP (PATTERN (trial), 0, 0)) + || GET_CODE (PATTERN (XVECEXP (PATTERN (trial), 0, 0))) == RETURN) + && redundant_insn_p (XVECEXP (PATTERN (trial), 0, 1), insn, 0)) + { + target_label = JUMP_LABEL (XVECEXP (PATTERN (trial), 0, 0)); + if (target_label == 0) + target_label = find_end_label (); + reorg_redirect_jump (delay_insn, target_label); + next = insn; + continue; + } + } + + if (! INSN_ANNULLED_BRANCH_P (delay_insn) + && prev_active_insn (target_label) == insn +#ifdef HAVE_cc0 + /* If the last insn in the delay slot sets CC0 for some insn, + various code assumes that it is in a delay slot. We could + put it back where it belonged and delete the register notes, + but it doesn't seem worthwhile in this uncommon case. */ + && ! find_reg_note (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1), + REG_CC_USER, NULL_RTX) +#endif + ) + { + int i; + + /* All this insn does is execute its delay list and jump to the + following insn. So delete the jump and just execute the delay + list insns. + + We do this by deleting the INSN containing the SEQUENCE, then + re-emitting the insns separately, and then deleting the jump. + This allows the count of the jump target to be properly + decremented. */ + + /* Clear the from target bit, since these insns are no longer + in delay slots. */ + for (i = 0; i < XVECLEN (pat, 0); i++) + INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)) = 0; + + trial = PREV_INSN (insn); + delete_insn (insn); + emit_insn_after (pat, trial); + delete_scheduled_jump (delay_insn); + continue; + } + + /* See if this is an unconditional jump around a single insn which is + identical to the one in its delay slot. In this case, we can just + delete the branch and the insn in its delay slot. */ + if (next && GET_CODE (next) == INSN + && prev_label (next_active_insn (next)) == target_label + && simplejump_p (insn) + && XVECLEN (pat, 0) == 2 + && rtx_equal_p (PATTERN (next), PATTERN (XVECEXP (pat, 0, 1)))) + { + delete_insn (insn); + continue; + } + + /* See if this jump (with its delay slots) branches around another + jump (without delay slots). If so, invert this jump and point + it to the target of the second jump. We cannot do this for + annulled jumps, though. Again, don't convert a jump to a RETURN + here. */ + if (! INSN_ANNULLED_BRANCH_P (delay_insn) + && next && GET_CODE (next) == JUMP_INSN + && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN) + && next_active_insn (target_label) == next_active_insn (next) + && no_labels_between_p (insn, next)) + { + rtx label = JUMP_LABEL (next); + rtx old_label = JUMP_LABEL (delay_insn); + + if (label == 0) + label = find_end_label (); + + /* Be careful how we do this to avoid deleting code or labels + that are momentarily dead. See similar optimization in jump.c */ + if (old_label) + ++LABEL_NUSES (old_label); + + if (invert_jump (delay_insn, label)) + { + delete_insn (next); + next = insn; + } + + if (old_label && --LABEL_NUSES (old_label) == 0) + delete_insn (old_label); + continue; + } + + /* If we own the thread opposite the way this insn branches, see if we + can merge its delay slots with following insns. */ + if (INSN_FROM_TARGET_P (XVECEXP (pat, 0, 1)) + && own_thread_p (NEXT_INSN (insn), 0, 1)) + try_merge_delay_insns (insn, next); + else if (! INSN_FROM_TARGET_P (XVECEXP (pat, 0, 1)) + && own_thread_p (target_label, target_label, 0)) + try_merge_delay_insns (insn, next_active_insn (target_label)); + + /* If we get here, we haven't deleted INSN. But we may have deleted + NEXT, so recompute it. */ + next = next_active_insn (insn); + } +} + +#ifdef HAVE_return + +/* Look for filled jumps to the end of function label. We can try to convert + them into RETURN insns if the insns in the delay slot are valid for the + RETURN as well. */ + +static void +make_return_insns (first) + rtx first; +{ + rtx insn, jump_insn, pat; + rtx real_return_label = end_of_function_label; + int slots, i; + + /* See if there is a RETURN insn in the function other than the one we + made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change + into a RETURN to jump to it. */ + for (insn = first; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) == RETURN) + { + real_return_label = get_label_before (insn); + break; + } + + /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it + was equal to END_OF_FUNCTION_LABEL. */ + LABEL_NUSES (real_return_label)++; + + /* Clear the list of insns to fill so we can use it. */ + obstack_free (&unfilled_slots_obstack, unfilled_firstobj); + + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + int flags; + + /* Only look at filled JUMP_INSNs that go to the end of function + label. */ + if (GET_CODE (insn) != INSN + || GET_CODE (PATTERN (insn)) != SEQUENCE + || GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) != JUMP_INSN + || JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) != end_of_function_label) + continue; + + pat = PATTERN (insn); + jump_insn = XVECEXP (pat, 0, 0); + + /* If we can't make the jump into a RETURN, redirect it to the best + RETURN and go on to the next insn. */ + if (! reorg_redirect_jump (jump_insn, NULL_RTX)) + { + reorg_redirect_jump (jump_insn, real_return_label); + continue; + } + + /* See if this RETURN can accept the insns current in its delay slot. + It can if it has more or an equal number of slots and the contents + of each is valid. */ + + flags = get_jump_flags (jump_insn, JUMP_LABEL (jump_insn)); + slots = num_delay_slots (jump_insn); + if (slots >= XVECLEN (pat, 0) - 1) + { + for (i = 1; i < XVECLEN (pat, 0); i++) + if (! ( +#ifdef ANNUL_IFFALSE_SLOTS + (INSN_ANNULLED_BRANCH_P (jump_insn) + && INSN_FROM_TARGET_P (XVECEXP (pat, 0, i))) + ? eligible_for_annul_false (jump_insn, i - 1, + XVECEXP (pat, 0, i), flags) : +#endif +#ifdef ANNUL_IFTRUE_SLOTS + (INSN_ANNULLED_BRANCH_P (jump_insn) + && ! INSN_FROM_TARGET_P (XVECEXP (pat, 0, i))) + ? eligible_for_annul_true (jump_insn, i - 1, + XVECEXP (pat, 0, i), flags) : +#endif + eligible_for_delay (jump_insn, i -1, XVECEXP (pat, 0, i), flags))) + break; + } + else + i = 0; + + if (i == XVECLEN (pat, 0)) + continue; + + /* We have to do something with this insn. If it is an unconditional + RETURN, delete the SEQUENCE and output the individual insns, + followed by the RETURN. Then set things up so we try to find + insns for its delay slots, if it needs some. */ + if (GET_CODE (PATTERN (jump_insn)) == RETURN) + { + rtx prev = PREV_INSN (insn); + + delete_insn (insn); + for (i = 1; i < XVECLEN (pat, 0); i++) + prev = emit_insn_after (PATTERN (XVECEXP (pat, 0, i)), prev); + + insn = emit_jump_insn_after (PATTERN (jump_insn), prev); + emit_barrier_after (insn); + + if (slots) + obstack_ptr_grow (&unfilled_slots_obstack, insn); + } + else + /* It is probably more efficient to keep this with its current + delay slot as a branch to a RETURN. */ + reorg_redirect_jump (jump_insn, real_return_label); + } + + /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any + new delay slots we have created. */ + if (--LABEL_NUSES (real_return_label) == 0) + delete_insn (real_return_label); + + fill_simple_delay_slots (first, 1); + fill_simple_delay_slots (first, 0); +} +#endif + +/* Try to find insns to place in delay slots. */ + +void +dbr_schedule (first, file) + rtx first; + FILE *file; +{ + rtx insn, next, epilogue_insn = 0; + int i; +#if 0 + int old_flag_no_peephole = flag_no_peephole; + + /* Execute `final' once in prescan mode to delete any insns that won't be + used. Don't let final try to do any peephole optimization--it will + ruin dataflow information for this pass. */ + + flag_no_peephole = 1; + final (first, 0, NO_DEBUG, 1, 1); + flag_no_peephole = old_flag_no_peephole; +#endif + + /* If the current function has no insns other than the prologue and + epilogue, then do not try to fill any delay slots. */ + if (n_basic_blocks == 0) + return; + + /* Find the highest INSN_UID and allocate and initialize our map from + INSN_UID's to position in code. */ + for (max_uid = 0, insn = first; insn; insn = NEXT_INSN (insn)) + { + if (INSN_UID (insn) > max_uid) + max_uid = INSN_UID (insn); + if (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_EPILOGUE_BEG) + epilogue_insn = insn; + } + + uid_to_ruid = (int *) alloca ((max_uid + 1) * sizeof (int *)); + for (i = 0, insn = first; insn; i++, insn = NEXT_INSN (insn)) + uid_to_ruid[INSN_UID (insn)] = i; + + /* Initialize the list of insns that need filling. */ + if (unfilled_firstobj == 0) + { + gcc_obstack_init (&unfilled_slots_obstack); + unfilled_firstobj = (rtx *) obstack_alloc (&unfilled_slots_obstack, 0); + } + + for (insn = next_active_insn (first); insn; insn = next_active_insn (insn)) + { + rtx target; + + INSN_ANNULLED_BRANCH_P (insn) = 0; + INSN_FROM_TARGET_P (insn) = 0; + + /* Skip vector tables. We can't get attributes for them. */ + if (GET_CODE (insn) == JUMP_INSN + && (GET_CODE (PATTERN (insn)) == ADDR_VEC + || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)) + continue; + + if (num_delay_slots (insn) > 0) + obstack_ptr_grow (&unfilled_slots_obstack, insn); + + /* Ensure all jumps go to the last of a set of consecutive labels. */ + if (GET_CODE (insn) == JUMP_INSN && condjump_p (insn) + && JUMP_LABEL (insn) != 0 + && ((target = prev_label (next_active_insn (JUMP_LABEL (insn)))) + != JUMP_LABEL (insn))) + redirect_jump (insn, target); + } + + /* Indicate what resources are required to be valid at the end of the current + function. The condition code never is and memory always is. If the + frame pointer is needed, it is and so is the stack pointer unless + EXIT_IGNORE_STACK is non-zero. If the frame pointer is not needed, the + stack pointer is. Registers used to return the function value are + needed. Registers holding global variables are needed. */ + + end_of_function_needs.cc = 0; + end_of_function_needs.memory = 1; + CLEAR_HARD_REG_SET (end_of_function_needs.regs); + + if (frame_pointer_needed) + { + SET_HARD_REG_BIT (end_of_function_needs.regs, FRAME_POINTER_REGNUM); +#ifdef EXIT_IGNORE_STACK + if (! EXIT_IGNORE_STACK) +#endif + SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM); + } + else + SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM); + + if (current_function_return_rtx != 0 + && GET_CODE (current_function_return_rtx) == REG) + mark_referenced_resources (current_function_return_rtx, + &end_of_function_needs, 1); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (global_regs[i]) + SET_HARD_REG_BIT (end_of_function_needs.regs, i); + + /* The registers required to be live at the end of the function are + represented in the flow information as being dead just prior to + reaching the end of the function. For example, the return of a value + might be represented by a USE of the return register immediately + followed by an unconditional jump to the return label where the + return label is the end of the RTL chain. The end of the RTL chain + is then taken to mean that the return register is live. + + This sequence is no longer maintained when epilogue instructions are + added to the RTL chain. To reconstruct the original meaning, the + start of the epilogue (NOTE_INSN_EPILOGUE_BEG) is regarded as the + point where these registers become live (start_of_epilogue_needs). + If epilogue instructions are present, the registers set by those + instructions won't have been processed by flow. Thus, those + registers are additionally required at the end of the RTL chain + (end_of_function_needs). */ + + start_of_epilogue_needs = end_of_function_needs; + + while (epilogue_insn = next_nonnote_insn (epilogue_insn)) + mark_set_resources (epilogue_insn, &end_of_function_needs, 0, 1); + + /* Show we haven't computed an end-of-function label yet. */ + end_of_function_label = 0; + + /* Allocate and initialize the tables used by mark_target_live_regs. */ + target_hash_table + = (struct target_info **) alloca ((TARGET_HASH_PRIME + * sizeof (struct target_info *))); + bzero (target_hash_table, TARGET_HASH_PRIME * sizeof (struct target_info *)); + + bb_ticks = (int *) alloca (n_basic_blocks * sizeof (int)); + bzero (bb_ticks, n_basic_blocks * sizeof (int)); + + /* Initialize the statistics for this function. */ + bzero (num_insns_needing_delays, sizeof num_insns_needing_delays); + bzero (num_filled_delays, sizeof num_filled_delays); + + /* Now do the delay slot filling. Try everything twice in case earlier + changes make more slots fillable. */ + + for (reorg_pass_number = 0; + reorg_pass_number < MAX_REORG_PASSES; + reorg_pass_number++) + { + fill_simple_delay_slots (first, 1); + fill_simple_delay_slots (first, 0); + fill_eager_delay_slots (first); + relax_delay_slots (first); + } + + /* Delete any USE insns made by update_block; subsequent passes don't need + them or know how to deal with them. */ + for (insn = first; insn; insn = next) + { + next = NEXT_INSN (insn); + + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE + && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i') + next = delete_insn (insn); + } + + /* If we made an end of function label, indicate that it is now + safe to delete it by undoing our prior adjustment to LABEL_NUSES. + If it is now unused, delete it. */ + if (end_of_function_label && --LABEL_NUSES (end_of_function_label) == 0) + delete_insn (end_of_function_label); + +#ifdef HAVE_return + if (HAVE_return && end_of_function_label != 0) + make_return_insns (first); +#endif + + obstack_free (&unfilled_slots_obstack, unfilled_firstobj); + + /* It is not clear why the line below is needed, but it does seem to be. */ + unfilled_firstobj = (rtx *) obstack_alloc (&unfilled_slots_obstack, 0); + + /* Reposition the prologue and epilogue notes in case we moved the + prologue/epilogue insns. */ + reposition_prologue_and_epilogue_notes (first); + + if (file) + { + register int i, j, need_comma; + + for (reorg_pass_number = 0; + reorg_pass_number < MAX_REORG_PASSES; + reorg_pass_number++) + { + fprintf (file, ";; Reorg pass #%d:\n", reorg_pass_number + 1); + for (i = 0; i < NUM_REORG_FUNCTIONS; i++) + { + need_comma = 0; + fprintf (file, ";; Reorg function #%d\n", i); + + fprintf (file, ";; %d insns needing delay slots\n;; ", + num_insns_needing_delays[i][reorg_pass_number]); + + for (j = 0; j < MAX_DELAY_HISTOGRAM; j++) + if (num_filled_delays[i][j][reorg_pass_number]) + { + if (need_comma) + fprintf (file, ", "); + need_comma = 1; + fprintf (file, "%d got %d delays", + num_filled_delays[i][j][reorg_pass_number], j); + } + fprintf (file, "\n"); + } + } + } +} +#endif /* DELAY_SLOTS */ diff --git a/gnu/usr.bin/cc/lib/rtl.c b/gnu/usr.bin/cc/lib/rtl.c new file mode 100644 index 000000000000..ac1979fc51da --- /dev/null +++ b/gnu/usr.bin/cc/lib/rtl.c @@ -0,0 +1,860 @@ +/* Allocate and read RTL for GNU C Compiler. + Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include +#include +#include "rtl.h" +#include "real.h" + +#include "obstack.h" +#define obstack_chunk_alloc xmalloc +#define obstack_chunk_free free + +/* Obstack used for allocating RTL objects. + Between functions, this is the permanent_obstack. + While parsing and expanding a function, this is maybepermanent_obstack + so we can save it if it is an inline function. + During optimization and output, this is function_obstack. */ + +extern struct obstack *rtl_obstack; + +#if HOST_BITS_PER_WIDE_INT != HOST_BITS_PER_INT +extern long atol(); +#endif + +/* Indexed by rtx code, gives number of operands for an rtx with that code. + Does NOT include rtx header data (code and links). + This array is initialized in init_rtl. */ + +int rtx_length[NUM_RTX_CODE + 1]; + +/* Indexed by rtx code, gives the name of that kind of rtx, as a C string. */ + +#define DEF_RTL_EXPR(ENUM, NAME, FORMAT, CLASS) NAME , + +char *rtx_name[] = { +#include "rtl.def" /* rtl expressions are documented here */ +}; + +#undef DEF_RTL_EXPR + +/* Indexed by machine mode, gives the name of that machine mode. + This name does not include the letters "mode". */ + +#define DEF_MACHMODE(SYM, NAME, CLASS, SIZE, UNIT, WIDER) NAME, + +char *mode_name[(int) MAX_MACHINE_MODE] = { +#include "machmode.def" + +#ifdef EXTRA_CC_MODES + EXTRA_CC_NAMES +#endif + +}; + +#undef DEF_MACHMODE + +/* Indexed by machine mode, gives the length of the mode, in bytes. + GET_MODE_CLASS uses this. */ + +#define DEF_MACHMODE(SYM, NAME, CLASS, SIZE, UNIT, WIDER) CLASS, + +enum mode_class mode_class[(int) MAX_MACHINE_MODE] = { +#include "machmode.def" +}; + +#undef DEF_MACHMODE + +/* Indexed by machine mode, gives the length of the mode, in bytes. + GET_MODE_SIZE uses this. */ + +#define DEF_MACHMODE(SYM, NAME, CLASS, SIZE, UNIT, WIDER) SIZE, + +int mode_size[(int) MAX_MACHINE_MODE] = { +#include "machmode.def" +}; + +#undef DEF_MACHMODE + +/* Indexed by machine mode, gives the length of the mode's subunit. + GET_MODE_UNIT_SIZE uses this. */ + +#define DEF_MACHMODE(SYM, NAME, CLASS, SIZE, UNIT, WIDER) UNIT, + +int mode_unit_size[(int) MAX_MACHINE_MODE] = { +#include "machmode.def" /* machine modes are documented here */ +}; + +#undef DEF_MACHMODE + +/* Indexed by machine mode, gives next wider natural mode + (QI -> HI -> SI -> DI, etc.) Widening multiply instructions + use this. */ + +#define DEF_MACHMODE(SYM, NAME, CLASS, SIZE, UNIT, WIDER) \ + (enum machine_mode) WIDER, + +enum machine_mode mode_wider_mode[(int) MAX_MACHINE_MODE] = { +#include "machmode.def" /* machine modes are documented here */ +}; + +#undef DEF_MACHMODE + +/* Indexed by mode class, gives the narrowest mode for each class. */ + +enum machine_mode class_narrowest_mode[(int) MAX_MODE_CLASS]; + +/* Commonly used modes. */ + +enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT */ +enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD */ + +/* Indexed by rtx code, gives a sequence of operand-types for + rtx's of that code. The sequence is a C string in which + each character describes one operand. */ + +char *rtx_format[] = { + /* "*" undefined. + can cause a warning message + "0" field is unused (or used in a phase-dependent manner) + prints nothing + "i" an integer + prints the integer + "n" like "i", but prints entries from `note_insn_name' + "w" an integer of width HOST_BITS_PER_WIDE_INT + prints the integer + "s" a pointer to a string + prints the string + "S" like "s", but optional: + the containing rtx may end before this operand + "e" a pointer to an rtl expression + prints the expression + "E" a pointer to a vector that points to a number of rtl expressions + prints a list of the rtl expressions + "V" like "E", but optional: + the containing rtx may end before this operand + "u" a pointer to another insn + prints the uid of the insn. */ + +#define DEF_RTL_EXPR(ENUM, NAME, FORMAT, CLASS) FORMAT , +#include "rtl.def" /* rtl expressions are defined here */ +#undef DEF_RTL_EXPR +}; + +/* Indexed by rtx code, gives a character representing the "class" of + that rtx code. See rtl.def for documentation on the defined classes. */ + +char rtx_class[] = { +#define DEF_RTL_EXPR(ENUM, NAME, FORMAT, CLASS) CLASS, +#include "rtl.def" /* rtl expressions are defined here */ +#undef DEF_RTL_EXPR +}; + +/* Names for kinds of NOTEs and REG_NOTEs. */ + +char *note_insn_name[] = { 0 , "NOTE_INSN_DELETED", + "NOTE_INSN_BLOCK_BEG", "NOTE_INSN_BLOCK_END", + "NOTE_INSN_LOOP_BEG", "NOTE_INSN_LOOP_END", + "NOTE_INSN_FUNCTION_END", "NOTE_INSN_SETJMP", + "NOTE_INSN_LOOP_CONT", "NOTE_INSN_LOOP_VTOP", + "NOTE_INSN_PROLOGUE_END", "NOTE_INSN_EPILOGUE_BEG", + "NOTE_INSN_DELETED_LABEL", "NOTE_INSN_FUNCTION_BEG"}; + +char *reg_note_name[] = { "", "REG_DEAD", "REG_INC", "REG_EQUIV", "REG_WAS_0", + "REG_EQUAL", "REG_RETVAL", "REG_LIBCALL", + "REG_NONNEG", "REG_NO_CONFLICT", "REG_UNUSED", + "REG_CC_SETTER", "REG_CC_USER", "REG_LABEL", + "REG_DEP_ANTI", "REG_DEP_OUTPUT" }; + +/* Allocate an rtx vector of N elements. + Store the length, and initialize all elements to zero. */ + +rtvec +rtvec_alloc (n) + int n; +{ + rtvec rt; + int i; + + rt = (rtvec) obstack_alloc (rtl_obstack, + sizeof (struct rtvec_def) + + (( n - 1) * sizeof (rtunion))); + + /* clear out the vector */ + PUT_NUM_ELEM(rt, n); + for (i=0; i < n; i++) + rt->elem[i].rtvec = NULL; /* @@ not portable due to rtunion */ + + return rt; +} + +/* Allocate an rtx of code CODE. The CODE is stored in the rtx; + all the rest is initialized to zero. */ + +rtx +rtx_alloc (code) + RTX_CODE code; +{ + rtx rt; + register struct obstack *ob = rtl_obstack; + register int nelts = GET_RTX_LENGTH (code); + register int length = sizeof (struct rtx_def) + + (nelts - 1) * sizeof (rtunion); + + /* This function is called more than any other in GCC, + so we manipulate the obstack directly. + + Even though rtx objects are word aligned, we may be sharing an obstack + with tree nodes, which may have to be double-word aligned. So align + our length to the alignment mask in the obstack. */ + + length = (length + ob->alignment_mask) & ~ ob->alignment_mask; + + if (ob->chunk_limit - ob->next_free < length) + _obstack_newchunk (ob, length); + rt = (rtx)ob->object_base; + ob->next_free += length; + ob->object_base = ob->next_free; + + /* We want to clear everything up to the FLD array. Normally, this is + one int, but we don't want to assume that and it isn't very portable + anyway; this is. */ + + length = (sizeof (struct rtx_def) - sizeof (rtunion) - 1) / sizeof (int); + for (; length >= 0; length--) + ((int *) rt)[length] = 0; + + PUT_CODE (rt, code); + + return rt; +} + +/* Create a new copy of an rtx. + Recursively copies the operands of the rtx, + except for those few rtx codes that are sharable. */ + +rtx +copy_rtx (orig) + register rtx orig; +{ + register rtx copy; + register int i, j; + register RTX_CODE code; + register char *format_ptr; + + code = GET_CODE (orig); + + switch (code) + { + case REG: + case QUEUED: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CODE_LABEL: + case PC: + case CC0: + case SCRATCH: + /* SCRATCH must be shared because they represent distinct values. */ + return orig; + + case CONST: + /* CONST can be shared if it contains a SYMBOL_REF. If it contains + a LABEL_REF, it isn't sharable. */ + if (GET_CODE (XEXP (orig, 0)) == PLUS + && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF + && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) + return orig; + break; + + /* A MEM with a constant address is not sharable. The problem is that + the constant address may need to be reloaded. If the mem is shared, + then reloading one copy of this mem will cause all copies to appear + to have been reloaded. */ + } + + copy = rtx_alloc (code); + PUT_MODE (copy, GET_MODE (orig)); + copy->in_struct = orig->in_struct; + copy->volatil = orig->volatil; + copy->unchanging = orig->unchanging; + copy->integrated = orig->integrated; + + format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); + + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) + { + switch (*format_ptr++) + { + case 'e': + XEXP (copy, i) = XEXP (orig, i); + if (XEXP (orig, i) != NULL) + XEXP (copy, i) = copy_rtx (XEXP (orig, i)); + break; + + case '0': + case 'u': + XEXP (copy, i) = XEXP (orig, i); + break; + + case 'E': + case 'V': + XVEC (copy, i) = XVEC (orig, i); + if (XVEC (orig, i) != NULL) + { + XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); + for (j = 0; j < XVECLEN (copy, i); j++) + XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j)); + } + break; + + case 'w': + XWINT (copy, i) = XWINT (orig, i); + break; + + case 'i': + XINT (copy, i) = XINT (orig, i); + break; + + case 's': + case 'S': + XSTR (copy, i) = XSTR (orig, i); + break; + + default: + abort (); + } + } + return copy; +} + +/* Similar to `copy_rtx' except that if MAY_SHARE is present, it is + placed in the result directly, rather than being copied. */ + +rtx +copy_most_rtx (orig, may_share) + register rtx orig; + register rtx may_share; +{ + register rtx copy; + register int i, j; + register RTX_CODE code; + register char *format_ptr; + + if (orig == may_share) + return orig; + + code = GET_CODE (orig); + + switch (code) + { + case REG: + case QUEUED: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CODE_LABEL: + case PC: + case CC0: + return orig; + } + + copy = rtx_alloc (code); + PUT_MODE (copy, GET_MODE (orig)); + copy->in_struct = orig->in_struct; + copy->volatil = orig->volatil; + copy->unchanging = orig->unchanging; + copy->integrated = orig->integrated; + + format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); + + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) + { + switch (*format_ptr++) + { + case 'e': + XEXP (copy, i) = XEXP (orig, i); + if (XEXP (orig, i) != NULL && XEXP (orig, i) != may_share) + XEXP (copy, i) = copy_most_rtx (XEXP (orig, i), may_share); + break; + + case '0': + case 'u': + XEXP (copy, i) = XEXP (orig, i); + break; + + case 'E': + case 'V': + XVEC (copy, i) = XVEC (orig, i); + if (XVEC (orig, i) != NULL) + { + XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); + for (j = 0; j < XVECLEN (copy, i); j++) + XVECEXP (copy, i, j) + = copy_most_rtx (XVECEXP (orig, i, j), may_share); + } + break; + + case 'w': + XWINT (copy, i) = XWINT (orig, i); + break; + + case 'n': + case 'i': + XINT (copy, i) = XINT (orig, i); + break; + + case 's': + case 'S': + XSTR (copy, i) = XSTR (orig, i); + break; + + default: + abort (); + } + } + return copy; +} + +/* Subroutines of read_rtx. */ + +/* Dump code after printing a message. Used when read_rtx finds + invalid data. */ + +static void +dump_and_abort (expected_c, actual_c, infile) + int expected_c, actual_c; + FILE *infile; +{ + int c, i; + + if (expected_c >= 0) + fprintf (stderr, + "Expected character %c. Found character %c.", + expected_c, actual_c); + fprintf (stderr, " At file position: %ld\n", ftell (infile)); + fprintf (stderr, "Following characters are:\n\t"); + for (i = 0; i < 200; i++) + { + c = getc (infile); + if (EOF == c) break; + putc (c, stderr); + } + fprintf (stderr, "Aborting.\n"); + abort (); +} + +/* Read chars from INFILE until a non-whitespace char + and return that. Comments, both Lisp style and C style, + are treated as whitespace. + Tools such as genflags use this function. */ + +int +read_skip_spaces (infile) + FILE *infile; +{ + register int c; + while (c = getc (infile)) + { + if (c == ' ' || c == '\n' || c == '\t' || c == '\f') + ; + else if (c == ';') + { + while ((c = getc (infile)) && c != '\n') ; + } + else if (c == '/') + { + register int prevc; + c = getc (infile); + if (c != '*') + dump_and_abort ('*', c, infile); + + prevc = 0; + while (c = getc (infile)) + { + if (prevc == '*' && c == '/') + break; + prevc = c; + } + } + else break; + } + return c; +} + +/* Read an rtx code name into the buffer STR[]. + It is terminated by any of the punctuation chars of rtx printed syntax. */ + +static void +read_name (str, infile) + char *str; + FILE *infile; +{ + register char *p; + register int c; + + c = read_skip_spaces(infile); + + p = str; + while (1) + { + if (c == ' ' || c == '\n' || c == '\t' || c == '\f') + break; + if (c == ':' || c == ')' || c == ']' || c == '"' || c == '/' + || c == '(' || c == '[') + { + ungetc (c, infile); + break; + } + *p++ = c; + c = getc (infile); + } + if (p == str) + { + fprintf (stderr, "missing name or number"); + dump_and_abort (-1, -1, infile); + } + + *p = 0; +} + +/* Read an rtx in printed representation from INFILE + and return an actual rtx in core constructed accordingly. + read_rtx is not used in the compiler proper, but rather in + the utilities gen*.c that construct C code from machine descriptions. */ + +rtx +read_rtx (infile) + FILE *infile; +{ + register int i, j, list_counter; + RTX_CODE tmp_code; + register char *format_ptr; + /* tmp_char is a buffer used for reading decimal integers + and names of rtx types and machine modes. + Therefore, 256 must be enough. */ + char tmp_char[256]; + rtx return_rtx; + register int c; + int tmp_int; + HOST_WIDE_INT tmp_wide; + + /* Linked list structure for making RTXs: */ + struct rtx_list + { + struct rtx_list *next; + rtx value; /* Value of this node... */ + }; + + c = read_skip_spaces (infile); /* Should be open paren. */ + if (c != '(') + dump_and_abort ('(', c, infile); + + read_name (tmp_char, infile); + + tmp_code = UNKNOWN; + + for (i=0; i < NUM_RTX_CODE; i++) /* @@ might speed this search up */ + { + if (!(strcmp (tmp_char, GET_RTX_NAME (i)))) + { + tmp_code = (RTX_CODE) i; /* get value for name */ + break; + } + } + if (tmp_code == UNKNOWN) + { + fprintf (stderr, + "Unknown rtx read in rtl.read_rtx(). Code name was %s .", + tmp_char); + } + /* (NIL) stands for an expression that isn't there. */ + if (tmp_code == NIL) + { + /* Discard the closeparen. */ + while ((c = getc (infile)) && c != ')'); + return 0; + } + + return_rtx = rtx_alloc (tmp_code); /* if we end up with an insn expression + then we free this space below. */ + format_ptr = GET_RTX_FORMAT (GET_CODE (return_rtx)); + + /* If what follows is `: mode ', read it and + store the mode in the rtx. */ + + i = read_skip_spaces (infile); + if (i == ':') + { + register int k; + read_name (tmp_char, infile); + for (k = 0; k < NUM_MACHINE_MODES; k++) + if (!strcmp (GET_MODE_NAME (k), tmp_char)) + break; + + PUT_MODE (return_rtx, (enum machine_mode) k ); + } + else + ungetc (i, infile); + + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (return_rtx)); i++) + switch (*format_ptr++) + { + /* 0 means a field for internal use only. + Don't expect it to be present in the input. */ + case '0': + break; + + case 'e': + case 'u': + XEXP (return_rtx, i) = read_rtx (infile); + break; + + case 'V': + /* 'V' is an optional vector: if a closeparen follows, + just store NULL for this element. */ + c = read_skip_spaces (infile); + ungetc (c, infile); + if (c == ')') + { + XVEC (return_rtx, i) = 0; + break; + } + /* Now process the vector. */ + + case 'E': + { + register struct rtx_list *next_rtx, *rtx_list_link; + struct rtx_list *list_rtx; + + c = read_skip_spaces (infile); + if (c != '[') + dump_and_abort ('[', c, infile); + + /* add expressions to a list, while keeping a count */ + next_rtx = NULL; + list_counter = 0; + while ((c = read_skip_spaces (infile)) && c != ']') + { + ungetc (c, infile); + list_counter++; + rtx_list_link = (struct rtx_list *) + alloca (sizeof (struct rtx_list)); + rtx_list_link->value = read_rtx (infile); + if (next_rtx == 0) + list_rtx = rtx_list_link; + else + next_rtx->next = rtx_list_link; + next_rtx = rtx_list_link; + rtx_list_link->next = 0; + } + /* get vector length and allocate it */ + XVEC (return_rtx, i) = (list_counter + ? rtvec_alloc (list_counter) : NULL_RTVEC); + if (list_counter > 0) + { + next_rtx = list_rtx; + for (j = 0; j < list_counter; j++, + next_rtx = next_rtx->next) + XVECEXP (return_rtx, i, j) = next_rtx->value; + } + /* close bracket gotten */ + } + break; + + case 'S': + /* 'S' is an optional string: if a closeparen follows, + just store NULL for this element. */ + c = read_skip_spaces (infile); + ungetc (c, infile); + if (c == ')') + { + XSTR (return_rtx, i) = 0; + break; + } + + case 's': + { + int saw_paren = 0; + register char *stringbuf; + int stringbufsize; + + c = read_skip_spaces (infile); + if (c == '(') + { + saw_paren = 1; + c = read_skip_spaces (infile); + } + if (c != '"') + dump_and_abort ('"', c, infile); + + while (1) + { + c = getc (infile); /* Read the string */ + if (c == '\\') + { + c = getc (infile); /* Read the string */ + /* \; makes stuff for a C string constant containing + newline and tab. */ + if (c == ';') + { + obstack_grow (rtl_obstack, "\\n\\t", 4); + continue; + } + } + else if (c == '"') + break; + + obstack_1grow (rtl_obstack, c); + } + + obstack_1grow (rtl_obstack, 0); + stringbuf = (char *) obstack_finish (rtl_obstack); + + if (saw_paren) + { + c = read_skip_spaces (infile); + if (c != ')') + dump_and_abort (')', c, infile); + } + XSTR (return_rtx, i) = stringbuf; + } + break; + + case 'w': + read_name (tmp_char, infile); +#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT + tmp_wide = atoi (tmp_char); +#else + tmp_wide = atol (tmp_char); +#endif + XWINT (return_rtx, i) = tmp_wide; + break; + + case 'i': + case 'n': + read_name (tmp_char, infile); + tmp_int = atoi (tmp_char); + XINT (return_rtx, i) = tmp_int; + break; + + default: + fprintf (stderr, + "switch format wrong in rtl.read_rtx(). format was: %c.\n", + format_ptr[-1]); + fprintf (stderr, "\tfile position: %ld\n", ftell (infile)); + abort (); + } + + c = read_skip_spaces (infile); + if (c != ')') + dump_and_abort (')', c, infile); + + return return_rtx; +} + +/* This is called once per compilation, before any rtx's are constructed. + It initializes the vector `rtx_length', the extra CC modes, if any, + and computes certain commonly-used modes. */ + +void +init_rtl () +{ + int min_class_size[(int) MAX_MODE_CLASS]; + enum machine_mode mode; + int i; + + for (i = 0; i < NUM_RTX_CODE; i++) + rtx_length[i] = strlen (rtx_format[i]); + + /* Make CONST_DOUBLE bigger, if real values are bigger than + it normally expects to have room for. + Note that REAL_VALUE_TYPE is not defined by default, + since tree.h is not included. But the default dfn as `double' + would do no harm. */ +#ifdef REAL_VALUE_TYPE + i = sizeof (REAL_VALUE_TYPE) / sizeof (rtunion) + 2; + if (rtx_length[(int) CONST_DOUBLE] < i) + { + char *s = (char *) xmalloc (i + 1); + rtx_length[(int) CONST_DOUBLE] = i; + rtx_format[(int) CONST_DOUBLE] = s; + *s++ = 'e'; + *s++ = '0'; + /* Set the GET_RTX_FORMAT of CONST_DOUBLE to a string + of as many `w's as we now have elements. Subtract two from + the size to account for the 'e' and the '0'. */ + for (i = 2; i < rtx_length[(int) CONST_DOUBLE]; i++) + *s++ = 'w'; + *s++ = 0; + } +#endif + +#ifdef EXTRA_CC_MODES + for (i = (int) CCmode + 1; i < (int) MAX_MACHINE_MODE; i++) + { + mode_class[i] = MODE_CC; + mode_size[i] = mode_size[(int) CCmode]; + mode_unit_size[i] = mode_unit_size[(int) CCmode]; + mode_wider_mode[i - 1] = (enum machine_mode) i; + mode_wider_mode[i] = VOIDmode; + } +#endif + + /* Find the narrowest mode for each class and compute the word and byte + modes. */ + + for (i = 0; i < (int) MAX_MODE_CLASS; i++) + min_class_size[i] = 1000; + + byte_mode = VOIDmode; + word_mode = VOIDmode; + + for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; + mode = (enum machine_mode) ((int) mode + 1)) + { + if (GET_MODE_SIZE (mode) < min_class_size[(int) GET_MODE_CLASS (mode)]) + { + class_narrowest_mode[(int) GET_MODE_CLASS (mode)] = mode; + min_class_size[(int) GET_MODE_CLASS (mode)] = GET_MODE_SIZE (mode); + } + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_BITSIZE (mode) == BITS_PER_UNIT + && byte_mode == VOIDmode) + byte_mode = mode; + + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_BITSIZE (mode) == BITS_PER_WORD + && word_mode == VOIDmode) + word_mode = mode; + } +} + +#ifdef memset +gcc_memset (dest, value, len) + char *dest; + int value; + int len; +{ + while (len-- > 0) + *dest++ = value; +} +#endif /* memset */ diff --git a/gnu/usr.bin/cc/lib/rtl.def b/gnu/usr.bin/cc/lib/rtl.def new file mode 100644 index 000000000000..1585ea38455b --- /dev/null +++ b/gnu/usr.bin/cc/lib/rtl.def @@ -0,0 +1,760 @@ +/* This file contains the definitions and documentation for the + Register Transfer Expressions (rtx's) that make up the + Register Transfer Language (rtl) used in the Back End of the GNU compiler. + Copyright (C) 1987-1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* Expression definitions and descriptions for all targets are in this file. + Some will not be used for some targets. + + The fields in the cpp macro call "DEF_RTL_EXPR()" + are used to create declarations in the C source of the compiler. + + The fields are: + + 1. The internal name of the rtx used in the C source. + It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". + By convention these are in UPPER_CASE. + + 2. The name of the rtx in the external ASCII format read by + read_rtx(), and printed by print_rtx(). + These names are stored in rtx_name[]. + By convention these are the internal (field 1) names in lower_case. + + 3. The print format, and type of each rtx->fld[] (field) in this rtx. + These formats are stored in rtx_format[]. + The meaning of the formats is documented in front of this array in rtl.c + + 4. The class of the rtx. These are stored in rtx_class and are accessed + via the GET_RTX_CLASS macro. They are defined as follows: + + "o" an rtx code that can be used to represent an object (e.g, REG, MEM) + "<" an rtx code for a comparison (e.g, EQ, NE, LT) + "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT) + "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT) + "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) + "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) + "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) + "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) + "m" an rtx code for something that matches in insns (e.g, MATCH_DUP) + "x" everything else + + */ + +/* --------------------------------------------------------------------- + Expressions (and "meta" expressions) used for structuring the + rtl representation of a program. + --------------------------------------------------------------------- */ + +/* an expression code name unknown to the reader */ +DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x') + +/* (NIL) is used by rtl reader and printer to represent a null pointer. */ + +DEF_RTL_EXPR(NIL, "nil", "*", 'x') + +/* --------------------------------------------------------------------- + Expressions used in constructing lists. + --------------------------------------------------------------------- */ + +/* a linked list of expressions */ +DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x') + +/* a linked list of instructions. + The insns are represented in print by their uids. */ +DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x') + +/* ---------------------------------------------------------------------- + Expression types for machine descriptions. + These do not appear in actual rtl code in the compiler. + ---------------------------------------------------------------------- */ + +/* Appears only in machine descriptions. + Means use the function named by the second arg (the string) + as a predicate; if matched, store the structure that was matched + in the operand table at index specified by the first arg (the integer). + If the second arg is the null string, the structure is just stored. + + A third string argument indicates to the register allocator restrictions + on where the operand can be allocated. + + If the target needs no restriction on any instruction this field should + be the null string. + + The string is prepended by: + '=' to indicate the operand is only written to. + '+' to indicate the operand is both read and written to. + + Each character in the string represents an allocatable class for an operand. + 'g' indicates the operand can be any valid class. + 'i' indicates the operand can be immediate (in the instruction) data. + 'r' indicates the operand can be in a register. + 'm' indicates the operand can be in memory. + 'o' a subset of the 'm' class. Those memory addressing modes that + can be offset at compile time (have a constant added to them). + + Other characters indicate target dependent operand classes and + are described in each target's machine description. + + For instructions with more than one operand, sets of classes can be + separated by a comma to indicate the appropriate multi-operand constraints. + There must be a 1 to 1 correspondence between these sets of classes in + all operands for an instruction. + */ +DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm') + +/* Appears only in machine descriptions. + Means match a SCRATCH or a register. When used to generate rtl, a + SCRATCH is generated. As for MATCH_OPERAND, the mode specifies + the desired mode and the first argument is the operand number. + The second argument is the constraint. */ +DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm') + +/* Appears only in machine descriptions. + Means match only something equal to what is stored in the operand table + at the index specified by the argument. */ +DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm') + +/* Appears only in machine descriptions. + Means apply a predicate, AND match recursively the operands of the rtx. + Operand 0 is the operand-number, as in match_operand. + Operand 1 is a predicate to apply (as a string, a function name). + Operand 2 is a vector of expressions, each of which must match + one subexpression of the rtx this construct is matching. */ +DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm') + +/* Appears only in machine descriptions. + Means to match a PARALLEL of arbitrary length. The predicate is applied + to the PARALLEL and the initial expressions in the PARALLEL are matched. + Operand 0 is the operand-number, as in match_operand. + Operand 1 is a predicate to apply to the PARALLEL. + Operand 2 is a vector of expressions, each of which must match the + corresponding element in the PARALLEL. */ +DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm') + +/* Appears only in machine descriptions. + Means match only something equal to what is stored in the operand table + at the index specified by the argument. For MATCH_OPERATOR. */ +DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm') + +/* Appears only in machine descriptions. + Means match only something equal to what is stored in the operand table + at the index specified by the argument. For MATCH_PARALLEL. */ +DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm') + +/* Appears only in machine descriptions. + Defines the pattern for one kind of instruction. + Operand: + 0: names this instruction. + If the name is the null string, the instruction is in the + machine description just to be recognized, and will never be emitted by + the tree to rtl expander. + 1: is the pattern. + 2: is a string which is a C expression + giving an additional condition for recognizing this pattern. + A null string means no extra condition. + 3: is the action to execute if this pattern is matched. + If this assembler code template starts with a * then it is a fragment of + C code to run to decide on a template to use. Otherwise, it is the + template to use. + 4: optionally, a vector of attributes for this insn. + */ +DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x') + +/* Definition of a peephole optimization. + 1st operand: vector of insn patterns to match + 2nd operand: C expression that must be true + 3rd operand: template or C code to produce assembler output. + 4: optionally, a vector of attributes for this insn. + */ +DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x') + +/* Definition of a split operation. + 1st operand: insn pattern to match + 2nd operand: C expression that must be true + 3rd operand: vector of insn patterns to place into a SEQUENCE + 4th operand: optionally, some C code to execute before generating the + insns. This might, for example, create some RTX's and store them in + elements of `recog_operand' for use by the vector of insn-patterns. + (`operands' is an alias here for `recog_operand'). */ +DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x') + +/* Definition of a combiner pattern. + Operands not defined yet. */ +DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x') + +/* Define how to generate multiple insns for a standard insn name. + 1st operand: the insn name. + 2nd operand: vector of insn-patterns. + Use match_operand to substitute an element of `recog_operand'. + 3rd operand: C expression that must be true for this to be available. + This may not test any operands. + 4th operand: Extra C code to execute before generating the insns. + This might, for example, create some RTX's and store them in + elements of `recog_operand' for use by the vector of insn-patterns. + (`operands' is an alias here for `recog_operand'). */ +DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x') + +/* Define a requirement for delay slots. + 1st operand: Condition involving insn attributes that, if true, + indicates that the insn requires the number of delay slots + shown. + 2nd operand: Vector whose length is the three times the number of delay + slots required. + Each entry gives three conditions, each involving attributes. + The first must be true for an insn to occupy that delay slot + location. The second is true for all insns that can be + annulled if the branch is true and the third is true for all + insns that can be annulled if the branch is false. + + Multiple DEFINE_DELAYs may be present. They indicate differing + requirements for delay slots. */ +DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x') + +/* Define a set of insns that requires a function unit. This means that + these insns produce their result after a delay and that there may be + restrictions on the number of insns of this type that can be scheduled + simultaneously. + + More than one DEFINE_FUNCTION_UNIT can be specified for a function unit. + Each gives a set of operations and associated delays. The first three + operands must be the same for each operation for the same function unit. + + All delays are specified in cycles. + + 1st operand: Name of function unit (mostly for documentation) + 2nd operand: Number of identical function units in CPU + 3rd operand: Total number of simultaneous insns that can execute on this + function unit; 0 if unlimited. + 4th operand: Condition involving insn attribute, that, if true, specifies + those insns that this expression applies to. + 5th operand: Constant delay after which insn result will be + available. + 6th operand: Delay until next insn can be scheduled on the function unit + executing this operation. The meaning depends on whether or + not the next operand is supplied. + 7th operand: If this operand is not specified, the 6th operand gives the + number of cycles after the instruction matching the 4th + operand begins using the function unit until a subsequent + insn can begin. A value of zero should be used for a + unit with no issue constraints. If only one operation can + be executed a time and the unit is busy for the entire time, + the 3rd operand should be specified as 1, the 6th operand + sould be specified as 0, and the 7th operand should not + be specified. + + If this operand is specified, it is a list of attribute + expressions. If an insn for which any of these expressions + is true is currently executing on the function unit, the + issue delay will be given by the 6th operand. Otherwise, + the insn can be immediately scheduled (subject to the limit + on the number of simultaneous operations executing on the + unit.) */ +DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x') + +/* Define attribute computation for `asm' instructions. */ +DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' ) + +/* SEQUENCE appears in the result of a `gen_...' function + for a DEFINE_EXPAND that wants to make several insns. + Its elements are the bodies of the insns that should be made. + `emit_insn' takes the SEQUENCE apart and makes separate insns. */ +DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x') + +/* Refers to the address of its argument. + This appears only in machine descriptions, indicating that + any expression that would be acceptable as the operand of MEM + should be matched. */ +DEF_RTL_EXPR(ADDRESS, "address", "e", 'm') + +/* ---------------------------------------------------------------------- + Expressions used for insn attributes. These also do not appear in + actual rtl code in the compiler. + ---------------------------------------------------------------------- */ + +/* Definition of an insn attribute. + 1st operand: name of the attribute + 2nd operand: comma-separated list of possible attribute values + 3rd operand: expression for the default value of the attribute. */ +DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x') + +/* Marker for the name of an attribute. */ +DEF_RTL_EXPR(ATTR, "attr", "s", 'x') + +/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and + in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that + pattern. + + (set_attr "name" "value") is equivalent to + (set (attr "name") (const_string "value")) */ +DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x') + +/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to + specify that attribute values are to be assigned according to the + alternative matched. + + The following three expressions are equivalent: + + (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") + (eq_attrq "alternative" "2") (const_string "a2")] + (const_string "a3"))) + (set_attr_alternative "att" [(const_string "a1") (const_string "a2") + (const_string "a3")]) + (set_attr "att" "a1,a2,a3") + */ +DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x') + +/* A conditional expression true if the value of the specified attribute of + the current insn equals the specified value. The first operand is the + attribute name and the second is the comparison value. */ +DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x') + +/* A conditional expression which is true if the specified flag is + true for the insn being scheduled in reorg. + + genattr.c defines the following flags which can be tested by + (attr_flag "foo") expressions in eligible_for_delay. + + forward, backward, very_likely, likely, very_unlikely, and unlikely. */ + +DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x') + +/* ---------------------------------------------------------------------- + Expression types used for things in the instruction chain. + + All formats must start with "iuu" to handle the chain. + Each insn expression holds an rtl instruction and its semantics + during back-end processing. + See macros's in "rtl.h" for the meaning of each rtx->fld[]. + + ---------------------------------------------------------------------- */ + +/* An instruction that cannot jump. */ +DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i') + +/* An instruction that can possibly jump. + Fields ( rtx->fld[] ) have exact same meaning as INSN's. */ +DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i') + +/* An instruction that can possibly call a subroutine + but which will not change which instruction comes next + in the current function. + Fields ( rtx->fld[] ) have exact same meaning as INSN's. */ +DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueiee", 'i') + +/* A marker that indicates that control will not flow through. */ +DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x') + +/* Holds a label that is followed by instructions. + Operand: + 3: is a number that is unique in the entire compilation. + 4: is the user-given name of the label, if any. + 5: is used in jump.c for the use-count of the label. + and in flow.c to point to the chain of label_ref's to this label. */ +DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuis0", 'x') + +/* Say where in the code a source line starts, for symbol table's sake. + Contains a filename and a line number. Line numbers <= 0 are special: + 0 is used in a dummy placed at the front of every function + just so there will never be a need to delete the first insn; + -1 indicates a dummy; insns to be deleted by flow analysis and combining + are really changed to NOTEs with a number of -1. + -2 means beginning of a name binding contour; output N_LBRAC. + -3 means end of a contour; output N_RBRAC. */ +DEF_RTL_EXPR(NOTE, "note", "iuusn", 'x') + +/* INLINE_HEADER is use by inline function machinery. The information + it contains helps to build the mapping function between the rtx's of + the function to be inlined and the current function being expanded. */ + +DEF_RTL_EXPR(INLINE_HEADER, "inline_header", "iuuuiiiiiieiiEe", 'x') + +/* ---------------------------------------------------------------------- + Top level constituents of INSN, JUMP_INSN and CALL_INSN. + ---------------------------------------------------------------------- */ + +/* Several operations to be done in parallel. */ +DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x') + +/* A string that is passed through to the assembler as input. + One can obviously pass comments through by using the + assembler comment syntax. + These occur in an insn all by themselves as the PATTERN. + They also appear inside an ASM_OPERANDS + as a convenient way to hold a string. */ +DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x') + +/* An assembler instruction with operands. + 1st operand is the instruction template. + 2nd operand is the constraint for the output. + 3rd operand is the number of the output this expression refers to. + When an insn stores more than one value, a separate ASM_OPERANDS + is made for each output; this integer distinguishes them. + 4th is a vector of values of input operands. + 5th is a vector of modes and constraints for the input operands. + Each element is an ASM_INPUT containing a constraint string + and whose mode indicates the mode of the input operand. + 6th is the name of the containing source file. + 7th is the source line number. */ +DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x') + +/* A machine-specific operation. + 1st operand is a vector of operands being used by the operation so that + any needed reloads can be done. + 2nd operand is a unique value saying which of a number of machine-specific + operations is to be performed. + (Note that the vector must be the first operand because of the way that + genrecog.c record positions within an insn.) + This can occur all by itself in a PATTERN, as a component of a PARALLEL, + or inside an expression. */ +DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x') + +/* Similar, but a volatile operation and one which may trap. */ +DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x') + +/* Vector of addresses, stored as full words. */ +/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ +DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x') + +/* Vector of address differences X0 - BASE, X1 - BASE, ... + First operand is BASE; the vector contains the X's. + The machine mode of this rtx says how much space to leave + for each difference. */ +DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eE", 'x') + +/* ---------------------------------------------------------------------- + At the top level of an instruction (perhaps under PARALLEL). + ---------------------------------------------------------------------- */ + +/* Assignment. + Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. + Operand 2 is the value stored there. + ALL assignment must use SET. + Instructions that do multiple assignments must use multiple SET, + under PARALLEL. */ +DEF_RTL_EXPR(SET, "set", "ee", 'x') + +/* Indicate something is used in a way that we don't want to explain. + For example, subroutine calls will use the register + in which the static chain is passed. */ +DEF_RTL_EXPR(USE, "use", "e", 'x') + +/* Indicate something is clobbered in a way that we don't want to explain. + For example, subroutine calls will clobber some physical registers + (the ones that are by convention not saved). */ +DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x') + +/* Call a subroutine. + Operand 1 is the address to call. + Operand 2 is the number of arguments. */ + +DEF_RTL_EXPR(CALL, "call", "ee", 'x') + +/* Return from a subroutine. */ + +DEF_RTL_EXPR(RETURN, "return", "", 'x') + +/* Conditional trap. + Operand 1 is the condition. + Operand 2 is the trap code. + For an unconditional trap, make the condition (const_int 1). */ +DEF_RTL_EXPR(TRAP_IF, "trap_if", "ei", 'x') + +/* ---------------------------------------------------------------------- + Primitive values for use in expressions. + ---------------------------------------------------------------------- */ + +/* numeric integer constant */ +DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o') + +/* numeric double constant. + Operand 0 is the MEM that stores this constant in memory, + or various other things (see comments at immed_double_const in varasm.c). + Operand 1 is a chain of all CONST_DOUBLEs in use in the current function. + Remaining operands hold the actual value. + The number of operands may be more than 2 if cross-compiling; + see init_rtl. */ +DEF_RTL_EXPR(CONST_DOUBLE, "const_double", "e0ww", 'o') + +/* String constant. Used only for attributes right now. */ +DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o') + +/* This is used to encapsulate an expression whose value is constant + (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be + recognized as a constant operand rather than by arithmetic instructions. */ + +DEF_RTL_EXPR(CONST, "const", "e", 'o') + +/* program counter. Ordinary jumps are represented + by a SET whose first operand is (PC). */ +DEF_RTL_EXPR(PC, "pc", "", 'o') + +/* A register. The "operand" is the register number, accessed + with the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER + than a hardware register is being referred to. */ +DEF_RTL_EXPR(REG, "reg", "i", 'o') + +/* A scratch register. This represents a register used only within a + single insn. It will be turned into a REG during register allocation + or reload unless the constraint indicates that the register won't be + needed, in which case it can remain a SCRATCH. This code is + marked as having one operand so it can be turned into a REG. */ +DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o') + +/* One word of a multi-word value. + The first operand is the complete value; the second says which word. + The WORDS_BIG_ENDIAN flag controls whether word number 0 + (as numbered in a SUBREG) is the most or least significant word. + + This is also used to refer to a value in a different machine mode. + For example, it can be used to refer to a SImode value as if it were + Qimode, or vice versa. Then the word number is always 0. */ +DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x') + +/* This one-argument rtx is used for move instructions + that are guaranteed to alter only the low part of a destination. + Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) + has an unspecified effect on the high part of REG, + but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) + is guaranteed to alter only the bits of REG that are in HImode. + + The actual instruction used is probably the same in both cases, + but the register constraints may be tighter when STRICT_LOW_PART + is in use. */ + +DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x') + +/* A memory location; operand is the address. + Can be nested inside a VOLATILE. */ +DEF_RTL_EXPR(MEM, "mem", "e", 'o') + +/* Reference to an assembler label in the code for this function. + The operand is a CODE_LABEL found in the insn chain. + The unprinted fields 1 and 2 are used in flow.c for the + LABEL_NEXTREF and CONTAINING_INSN. */ +DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o') + +/* Reference to a named label: the string that is the first operand, + with `_' added implicitly in front. + Exception: if the first character explicitly given is `*', + to give it to the assembler, remove the `*' and do not add `_'. */ +DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o') + +/* The condition code register is represented, in our imagination, + as a register holding a value that can be compared to zero. + In fact, the machine has already compared them and recorded the + results; but instructions that look at the condition code + pretend to be looking at the entire value and comparing it. */ +DEF_RTL_EXPR(CC0, "cc0", "", 'o') + +/* ===================================================================== + A QUEUED expression really points to a member of the queue of instructions + to be output later for postincrement/postdecrement. + QUEUED expressions never become part of instructions. + When a QUEUED expression would be put into an instruction, + instead either the incremented variable or a copy of its previous + value is used. + + Operands are: + 0. the variable to be incremented (a REG rtx). + 1. the incrementing instruction, or 0 if it hasn't been output yet. + 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet. + 3. the body to use for the incrementing instruction + 4. the next QUEUED expression in the queue. + ====================================================================== */ + +DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x') + +/* ---------------------------------------------------------------------- + Expressions for operators in an rtl pattern + ---------------------------------------------------------------------- */ + +/* if_then_else. This is used in representing ordinary + conditional jump instructions. + Operand: + 0: condition + 1: then expr + 2: else expr */ +DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3') + +/* General conditional. The first operand is a vector composed of pairs of + expressions. The first element of each pair is evaluated, in turn. + The value of the conditional is the second expression of the first pair + whose first expression evaluates non-zero. If none of the expressions is + true, the second operand will be used as the value of the conditional. + + This should be replaced with use of IF_THEN_ELSE. */ +DEF_RTL_EXPR(COND, "cond", "Ee", 'x') + +/* Comparison, produces a condition code result. */ +DEF_RTL_EXPR(COMPARE, "compare", "ee", '2') + +/* plus */ +DEF_RTL_EXPR(PLUS, "plus", "ee", 'c') + +/* Operand 0 minus operand 1. */ +DEF_RTL_EXPR(MINUS, "minus", "ee", '2') + +/* Minus operand 0. */ +DEF_RTL_EXPR(NEG, "neg", "e", '1') + +DEF_RTL_EXPR(MULT, "mult", "ee", 'c') + +/* Operand 0 divided by operand 1. */ +DEF_RTL_EXPR(DIV, "div", "ee", '2') +/* Remainder of operand 0 divided by operand 1. */ +DEF_RTL_EXPR(MOD, "mod", "ee", '2') + +/* Unsigned divide and remainder. */ +DEF_RTL_EXPR(UDIV, "udiv", "ee", '2') +DEF_RTL_EXPR(UMOD, "umod", "ee", '2') + +/* Bitwise operations. */ +DEF_RTL_EXPR(AND, "and", "ee", 'c') + +DEF_RTL_EXPR(IOR, "ior", "ee", 'c') + +DEF_RTL_EXPR(XOR, "xor", "ee", 'c') + +DEF_RTL_EXPR(NOT, "not", "e", '1') + +/* Operand: + 0: value to be shifted. + 1: number of bits. + ASHIFT and LSHIFT are distinguished because on some machines + these allow a negative operand and shift right in that case. */ +DEF_RTL_EXPR(LSHIFT, "lshift", "ee", '2') +DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') +DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') + +/* Right shift operations, for machines where these are not the same + as left shifting with a negative argument. */ + +DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') +DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') +DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') + +/* Minimum and maximum values of two operands. We need both signed and + unsigned forms. (We cannot use MIN for SMIN because it conflicts + with a macro of the same name.) */ + +DEF_RTL_EXPR(SMIN, "smin", "ee", 'c') +DEF_RTL_EXPR(SMAX, "smax", "ee", 'c') +DEF_RTL_EXPR(UMIN, "umin", "ee", 'c') +DEF_RTL_EXPR(UMAX, "umax", "ee", 'c') + +/* These unary operations are used to represent incrementation + and decrementation as they occur in memory addresses. + The amount of increment or decrement are not represented + because they can be understood from the machine-mode of the + containing MEM. These operations exist in only two cases: + 1. pushes onto the stack. + 2. created automatically by the life_analysis pass in flow.c. */ +DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x') +DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x') +DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x') +DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x') + +/* Comparison operations. The ordered comparisons exist in two + flavors, signed and unsigned. */ +DEF_RTL_EXPR(NE, "ne", "ee", '<') +DEF_RTL_EXPR(EQ, "eq", "ee", '<') +DEF_RTL_EXPR(GE, "ge", "ee", '<') +DEF_RTL_EXPR(GT, "gt", "ee", '<') +DEF_RTL_EXPR(LE, "le", "ee", '<') +DEF_RTL_EXPR(LT, "lt", "ee", '<') +DEF_RTL_EXPR(GEU, "geu", "ee", '<') +DEF_RTL_EXPR(GTU, "gtu", "ee", '<') +DEF_RTL_EXPR(LEU, "leu", "ee", '<') +DEF_RTL_EXPR(LTU, "ltu", "ee", '<') + +/* Represents the result of sign-extending the sole operand. + The machine modes of the operand and of the SIGN_EXTEND expression + determine how much sign-extension is going on. */ +DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1') + +/* Similar for zero-extension (such as unsigned short to int). */ +DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1') + +/* Similar but here the operand has a wider mode. */ +DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1') + +/* Similar for extending floating-point values (such as SFmode to DFmode). */ +DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1') +DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1') + +/* Conversion of fixed point operand to floating point value. */ +DEF_RTL_EXPR(FLOAT, "float", "e", '1') + +/* With fixed-point machine mode: + Conversion of floating point operand to fixed point value. + Value is defined only when the operand's value is an integer. + With floating-point machine mode (and operand with same mode): + Operand is rounded toward zero to produce an integer value + represented in floating point. */ +DEF_RTL_EXPR(FIX, "fix", "e", '1') + +/* Conversion of unsigned fixed point operand to floating point value. */ +DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1') + +/* With fixed-point machine mode: + Conversion of floating point operand to *unsigned* fixed point value. + Value is defined only when the operand's value is an integer. */ +DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1') + +/* Absolute value */ +DEF_RTL_EXPR(ABS, "abs", "e", '1') + +/* Square root */ +DEF_RTL_EXPR(SQRT, "sqrt", "e", '1') + +/* Find first bit that is set. + Value is 1 + number of trailing zeros in the arg., + or 0 if arg is 0. */ +DEF_RTL_EXPR(FFS, "ffs", "e", '1') + +/* Reference to a signed bit-field of specified size and position. + Operand 0 is the memory unit (usually SImode or QImode) which + contains the field's first bit. Operand 1 is the width, in bits. + Operand 2 is the number of bits in the memory unit before the + first bit of this field. + If BITS_BIG_ENDIAN is defined, the first bit is the msb and + operand 2 counts from the msb of the memory unit. + Otherwise, the first bit is the lsb and operand 2 counts from + the lsb of the memory unit. */ +DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b') + +/* Similar for unsigned bit-field. */ +DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b') + +/* For RISC machines. These save memory when splitting insns. */ + +/* HIGH are the high-order bits of a constant expression. */ +DEF_RTL_EXPR(HIGH, "high", "e", 'o') + +/* LO_SUM is the sum of a register and the low-order bits + of a constant expression. */ +DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o') + +/* +Local variables: +mode:c +version-control: t +End: +*/ diff --git a/gnu/usr.bin/cc/lib/rtl.h b/gnu/usr.bin/cc/lib/rtl.h new file mode 100644 index 000000000000..72eac9cf880a --- /dev/null +++ b/gnu/usr.bin/cc/lib/rtl.h @@ -0,0 +1,917 @@ +/* Register Transfer Language (RTL) definitions for GNU C-Compiler + Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "machmode.h" + +#undef FFS /* Some systems predefine this symbol; don't let it interfere. */ +#undef FLOAT /* Likewise. */ +#undef ABS /* Likewise. */ +#undef PC /* Likewise. */ + +/* Register Transfer Language EXPRESSIONS CODES */ + +#define RTX_CODE enum rtx_code +enum rtx_code { + +#define DEF_RTL_EXPR(ENUM, NAME, FORMAT, CLASS) ENUM , +#include "rtl.def" /* rtl expressions are documented here */ +#undef DEF_RTL_EXPR + + LAST_AND_UNUSED_RTX_CODE}; /* A convenient way to get a value for + NUM_RTX_CODE. + Assumes default enum value assignment. */ + +#define NUM_RTX_CODE ((int)LAST_AND_UNUSED_RTX_CODE) + /* The cast here, saves many elsewhere. */ + +extern int rtx_length[]; +#define GET_RTX_LENGTH(CODE) (rtx_length[(int)(CODE)]) + +extern char *rtx_name[]; +#define GET_RTX_NAME(CODE) (rtx_name[(int)(CODE)]) + +extern char *rtx_format[]; +#define GET_RTX_FORMAT(CODE) (rtx_format[(int)(CODE)]) + +extern char rtx_class[]; +#define GET_RTX_CLASS(CODE) (rtx_class[(int)(CODE)]) + +/* Common union for an element of an rtx. */ + +typedef union rtunion_def +{ + HOST_WIDE_INT rtwint; + int rtint; + char *rtstr; + struct rtx_def *rtx; + struct rtvec_def *rtvec; + enum machine_mode rttype; +} rtunion; + +/* RTL expression ("rtx"). */ + +typedef struct rtx_def +{ +#ifdef ONLY_INT_FIELDS +#ifdef CODE_FIELD_BUG + unsigned int code : 16; +#else + unsigned short code; +#endif +#else + /* The kind of expression this is. */ + enum rtx_code code : 16; +#endif + /* The kind of value the expression has. */ +#ifdef ONLY_INT_FIELDS + int mode : 8; +#else + enum machine_mode mode : 8; +#endif + /* 1 in an INSN if it can alter flow of control + within this function. Not yet used! */ + unsigned int jump : 1; + /* 1 in an INSN if it can call another function. Not yet used! */ + unsigned int call : 1; + /* 1 in a MEM or REG if value of this expression will never change + during the current function, even though it is not + manifestly constant. + 1 in a SUBREG if it is from a promoted variable that is unsigned. + 1 in a SYMBOL_REF if it addresses something in the per-function + constants pool. + 1 in a CALL_INSN if it is a const call. + 1 in a JUMP_INSN if it is a branch that should be annulled. Valid from + reorg until end of compilation; cleared before used. */ + unsigned int unchanging : 1; + /* 1 in a MEM expression if contents of memory are volatile. + 1 in an INSN, CALL_INSN, JUMP_INSN, CODE_LABEL or BARRIER + if it is deleted. + 1 in a REG expression if corresponds to a variable declared by the user. + 0 for an internally generated temporary. + In a SYMBOL_REF, this flag is used for machine-specific purposes. + In a LABEL_REF or in a REG_LABEL note, this is LABEL_REF_NONLOCAL_P. */ + unsigned int volatil : 1; + /* 1 in a MEM referring to a field of a structure (not a union!). + 0 if the MEM was a variable or the result of a * operator in C; + 1 if it was the result of a . or -> operator (on a struct) in C. + 1 in a REG if the register is used only in exit code a loop. + 1 in a SUBREG expression if was generated from a variable with a + promoted mode. + 1 in a CODE_LABEL if the label is used for nonlocal gotos + and must not be deleted even if its count is zero. + 1 in a LABEL_REF if this is a reference to a label outside the + current loop. + 1 in an INSN, JUMP_INSN, or CALL_INSN if this insn must be scheduled + together with the preceding insn. Valid only within sched. + 1 in an INSN, JUMP_INSN, or CALL_INSN if insn is in a delay slot and + from the target of a branch. Valid from reorg until end of compilation; + cleared before used. */ + unsigned int in_struct : 1; + /* 1 if this rtx is used. This is used for copying shared structure. + See `unshare_all_rtl'. + In a REG, this is not needed for that purpose, and used instead + in `leaf_renumber_regs_insn'. + In a SYMBOL_REF, means that emit_library_call + has used it as the function. */ + unsigned int used : 1; + /* Nonzero if this rtx came from procedure integration. + In a REG, nonzero means this reg refers to the return value + of the current function. */ + unsigned integrated : 1; + /* The first element of the operands of this rtx. + The number of operands and their types are controlled + by the `code' field, according to rtl.def. */ + rtunion fld[1]; +} *rtx; + +/* Add prototype support. */ +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif + +#define NULL_RTX (rtx) 0 + +/* Define a generic NULL if one hasn't already been defined. */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef GENERIC_PTR +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define GENERIC_PTR void * +#else +#define GENERIC_PTR char * +#endif +#endif + +#ifndef NULL_PTR +#define NULL_PTR ((GENERIC_PTR)0) +#endif + +/* Define macros to access the `code' field of the rtx. */ + +#ifdef SHORT_ENUM_BUG +#define GET_CODE(RTX) ((enum rtx_code) ((RTX)->code)) +#define PUT_CODE(RTX, CODE) ((RTX)->code = ((short) (CODE))) +#else +#define GET_CODE(RTX) ((RTX)->code) +#define PUT_CODE(RTX, CODE) ((RTX)->code = (CODE)) +#endif + +#define GET_MODE(RTX) ((RTX)->mode) +#define PUT_MODE(RTX, MODE) ((RTX)->mode = (MODE)) + +#define RTX_INTEGRATED_P(RTX) ((RTX)->integrated) +#define RTX_UNCHANGING_P(RTX) ((RTX)->unchanging) + +/* RTL vector. These appear inside RTX's when there is a need + for a variable number of things. The principle use is inside + PARALLEL expressions. */ + +typedef struct rtvec_def{ + unsigned num_elem; /* number of elements */ + rtunion elem[1]; +} *rtvec; + +#define NULL_RTVEC (rtvec) 0 + +#define GET_NUM_ELEM(RTVEC) ((RTVEC)->num_elem) +#define PUT_NUM_ELEM(RTVEC, NUM) ((RTVEC)->num_elem = (unsigned) NUM) + +#define RTVEC_ELT(RTVEC, I) ((RTVEC)->elem[(I)].rtx) + +/* 1 if X is a REG. */ + +#define REG_P(X) (GET_CODE (X) == REG) + +/* 1 if X is a constant value that is an integer. */ + +#define CONSTANT_P(X) \ + (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE \ + || GET_CODE (X) == CONST || GET_CODE (X) == HIGH) + +/* General accessor macros for accessing the fields of an rtx. */ + +#define XEXP(RTX, N) ((RTX)->fld[N].rtx) +#define XINT(RTX, N) ((RTX)->fld[N].rtint) +#define XWINT(RTX, N) ((RTX)->fld[N].rtwint) +#define XSTR(RTX, N) ((RTX)->fld[N].rtstr) +#define XVEC(RTX, N) ((RTX)->fld[N].rtvec) +#define XVECLEN(RTX, N) ((RTX)->fld[N].rtvec->num_elem) +#define XVECEXP(RTX,N,M)((RTX)->fld[N].rtvec->elem[M].rtx) + +/* ACCESS MACROS for particular fields of insns. */ + +/* Holds a unique number for each insn. + These are not necessarily sequentially increasing. */ +#define INSN_UID(INSN) ((INSN)->fld[0].rtint) + +/* Chain insns together in sequence. */ +#define PREV_INSN(INSN) ((INSN)->fld[1].rtx) +#define NEXT_INSN(INSN) ((INSN)->fld[2].rtx) + +/* The body of an insn. */ +#define PATTERN(INSN) ((INSN)->fld[3].rtx) + +/* Code number of instruction, from when it was recognized. + -1 means this instruction has not been recognized yet. */ +#define INSN_CODE(INSN) ((INSN)->fld[4].rtint) + +/* Set up in flow.c; empty before then. + Holds a chain of INSN_LIST rtx's whose first operands point at + previous insns with direct data-flow connections to this one. + That means that those insns set variables whose next use is in this insn. + They are always in the same basic block as this insn. */ +#define LOG_LINKS(INSN) ((INSN)->fld[5].rtx) + +/* 1 if insn has been deleted. */ +#define INSN_DELETED_P(INSN) ((INSN)->volatil) + +/* 1 if insn is a call to a const function. */ +#define CONST_CALL_P(INSN) ((INSN)->unchanging) + +/* 1 if insn is a branch that should not unconditionally execute its + delay slots, i.e., it is an annulled branch. */ +#define INSN_ANNULLED_BRANCH_P(INSN) ((INSN)->unchanging) + +/* 1 if insn is in a delay slot and is from the target of the branch. If + the branch insn has INSN_ANNULLED_BRANCH_P set, this insn should only be + executed if the branch is taken. For annulled branches with this bit + clear, the insn should be executed only if the branch is not taken. */ +#define INSN_FROM_TARGET_P(INSN) ((INSN)->in_struct) + +/* Holds a list of notes on what this insn does to various REGs. + It is a chain of EXPR_LIST rtx's, where the second operand + is the chain pointer and the first operand is the REG being described. + The mode field of the EXPR_LIST contains not a real machine mode + but a value that says what this note says about the REG: + REG_DEAD means that the value in REG dies in this insn (i.e., it is + not needed past this insn). If REG is set in this insn, the REG_DEAD + note may, but need not, be omitted. + REG_INC means that the REG is autoincremented or autodecremented. + REG_EQUIV describes the insn as a whole; it says that the + insn sets a register to a constant value or to be equivalent to + a memory address. If the + register is spilled to the stack then the constant value + should be substituted for it. The contents of the REG_EQUIV + is the constant value or memory address, which may be different + from the source of the SET although it has the same value. + REG_EQUAL is like REG_EQUIV except that the destination + is only momentarily equal to the specified rtx. Therefore, it + cannot be used for substitution; but it can be used for cse. + REG_RETVAL means that this insn copies the return-value of + a library call out of the hard reg for return values. This note + is actually an INSN_LIST and it points to the first insn involved + in setting up arguments for the call. flow.c uses this to delete + the entire library call when its result is dead. + REG_LIBCALL is the inverse of REG_RETVAL: it goes on the first insn + of the library call and points at the one that has the REG_RETVAL. + REG_WAS_0 says that the register set in this insn held 0 before the insn. + The contents of the note is the insn that stored the 0. + If that insn is deleted or patched to a NOTE, the REG_WAS_0 is inoperative. + The REG_WAS_0 note is actually an INSN_LIST, not an EXPR_LIST. + REG_NONNEG means that the register is always nonnegative during + the containing loop. This is used in branches so that decrement and + branch instructions terminating on zero can be matched. There must be + an insn pattern in the md file named `decrement_and_branch_until_zero' + or else this will never be added to any instructions. + REG_NO_CONFLICT means there is no conflict *after this insn* + between the register in the note and the destination of this insn. + REG_UNUSED identifies a register set in this insn and never used. + REG_CC_SETTER and REG_CC_USER link a pair of insns that set and use + CC0, respectively. Normally, these are required to be consecutive insns, + but we permit putting a cc0-setting insn in the delay slot of a branch + as long as only one copy of the insn exists. In that case, these notes + point from one to the other to allow code generation to determine what + any require information and to properly update CC_STATUS. + REG_LABEL points to a CODE_LABEL. Used by non-JUMP_INSNs to + say that the CODE_LABEL contained in the REG_LABEL note is used + by the insn. + REG_DEP_ANTI is used in LOG_LINKS which represent anti (write after read) + dependencies. REG_DEP_OUTPUT is used in LOG_LINKS which represent output + (write after write) dependencies. Data dependencies, which are the only + type of LOG_LINK created by flow, are represented by a 0 reg note kind. */ + +#define REG_NOTES(INSN) ((INSN)->fld[6].rtx) + +/* Don't forget to change reg_note_name in rtl.c. */ +enum reg_note { REG_DEAD = 1, REG_INC = 2, REG_EQUIV = 3, REG_WAS_0 = 4, + REG_EQUAL = 5, REG_RETVAL = 6, REG_LIBCALL = 7, + REG_NONNEG = 8, REG_NO_CONFLICT = 9, REG_UNUSED = 10, + REG_CC_SETTER = 11, REG_CC_USER = 12, REG_LABEL = 13, + REG_DEP_ANTI = 14, REG_DEP_OUTPUT = 15 }; + +/* Define macros to extract and insert the reg-note kind in an EXPR_LIST. */ +#define REG_NOTE_KIND(LINK) ((enum reg_note) GET_MODE (LINK)) +#define PUT_REG_NOTE_KIND(LINK,KIND) PUT_MODE(LINK, (enum machine_mode) (KIND)) + +/* Names for REG_NOTE's in EXPR_LIST insn's. */ + +extern char *reg_note_name[]; +#define GET_REG_NOTE_NAME(MODE) (reg_note_name[(int)(MODE)]) + +/* The label-number of a code-label. The assembler label + is made from `L' and the label-number printed in decimal. + Label numbers are unique in a compilation. */ +#define CODE_LABEL_NUMBER(INSN) ((INSN)->fld[3].rtint) + +#define LINE_NUMBER NOTE + +/* In a NOTE that is a line number, this is a string for the file name + that the line is in. We use the same field to record block numbers + temporarily in NOTE_INSN_BLOCK_BEG and NOTE_INSN_BLOCK_END notes. + (We avoid lots of casts between ints and pointers if we use a + different macro for the bock number.) */ + +#define NOTE_SOURCE_FILE(INSN) ((INSN)->fld[3].rtstr) +#define NOTE_BLOCK_NUMBER(INSN) ((INSN)->fld[3].rtint) + +/* In a NOTE that is a line number, this is the line number. + Other kinds of NOTEs are identified by negative numbers here. */ +#define NOTE_LINE_NUMBER(INSN) ((INSN)->fld[4].rtint) + +/* Codes that appear in the NOTE_LINE_NUMBER field + for kinds of notes that are not line numbers. + + Notice that we do not try to use zero here for any of + the special note codes because sometimes the source line + actually can be zero! This happens (for example) when we + are generating code for the per-translation-unit constructor + and destructor routines for some C++ translation unit. + + If you should change any of the following values, or if you + should add a new value here, don't forget to change the + note_insn_name array in rtl.c. */ + +/* This note is used to get rid of an insn + when it isn't safe to patch the insn out of the chain. */ +#define NOTE_INSN_DELETED -1 +#define NOTE_INSN_BLOCK_BEG -2 +#define NOTE_INSN_BLOCK_END -3 +#define NOTE_INSN_LOOP_BEG -4 +#define NOTE_INSN_LOOP_END -5 +/* This kind of note is generated at the end of the function body, + just before the return insn or return label. + In an optimizing compilation it is deleted by the first jump optimization, + after enabling that optimizer to determine whether control can fall + off the end of the function body without a return statement. */ +#define NOTE_INSN_FUNCTION_END -6 +/* This kind of note is generated just after each call to `setjmp', et al. */ +#define NOTE_INSN_SETJMP -7 +/* Generated at the place in a loop that `continue' jumps to. */ +#define NOTE_INSN_LOOP_CONT -8 +/* Generated at the start of a duplicated exit test. */ +#define NOTE_INSN_LOOP_VTOP -9 +/* This marks the point immediately after the last prologue insn. */ +#define NOTE_INSN_PROLOGUE_END -10 +/* This marks the point immediately prior to the first epilogue insn. */ +#define NOTE_INSN_EPILOGUE_BEG -11 +/* Generated in place of user-declared labels when they are deleted. */ +#define NOTE_INSN_DELETED_LABEL -12 +/* This note indicates the start of the real body of the function, + i.e. the point just after all of the parms have been moved into + their homes, etc. */ +#define NOTE_INSN_FUNCTION_BEG -13 + + +#if 0 /* These are not used, and I don't know what they were for. --rms. */ +#define NOTE_DECL_NAME(INSN) ((INSN)->fld[3].rtstr) +#define NOTE_DECL_CODE(INSN) ((INSN)->fld[4].rtint) +#define NOTE_DECL_RTL(INSN) ((INSN)->fld[5].rtx) +#define NOTE_DECL_IDENTIFIER(INSN) ((INSN)->fld[6].rtint) +#define NOTE_DECL_TYPE(INSN) ((INSN)->fld[7].rtint) +#endif /* 0 */ + +/* Names for NOTE insn's other than line numbers. */ + +extern char *note_insn_name[]; +#define GET_NOTE_INSN_NAME(NOTE_CODE) (note_insn_name[-(NOTE_CODE)]) + +/* The name of a label, in case it corresponds to an explicit label + in the input source code. */ +#define LABEL_NAME(LABEL) ((LABEL)->fld[4].rtstr) + +/* In jump.c, each label contains a count of the number + of LABEL_REFs that point at it, so unused labels can be deleted. */ +#define LABEL_NUSES(LABEL) ((LABEL)->fld[5].rtint) + +/* In jump.c, each JUMP_INSN can point to a label that it can jump to, + so that if the JUMP_INSN is deleted, the label's LABEL_NUSES can + be decremented and possibly the label can be deleted. */ +#define JUMP_LABEL(INSN) ((INSN)->fld[7].rtx) + +/* Once basic blocks are found in flow.c, + each CODE_LABEL starts a chain that goes through + all the LABEL_REFs that jump to that label. + The chain eventually winds up at the CODE_LABEL; it is circular. */ +#define LABEL_REFS(LABEL) ((LABEL)->fld[5].rtx) + +/* This is the field in the LABEL_REF through which the circular chain + of references to a particular label is linked. + This chain is set up in flow.c. */ + +#define LABEL_NEXTREF(REF) ((REF)->fld[1].rtx) + +/* Once basic blocks are found in flow.c, + Each LABEL_REF points to its containing instruction with this field. */ + +#define CONTAINING_INSN(RTX) ((RTX)->fld[2].rtx) + +/* For a REG rtx, REGNO extracts the register number. */ + +#define REGNO(RTX) ((RTX)->fld[0].rtint) + +/* For a REG rtx, REG_FUNCTION_VALUE_P is nonzero if the reg + is the current function's return value. */ + +#define REG_FUNCTION_VALUE_P(RTX) ((RTX)->integrated) + +/* 1 in a REG rtx if it corresponds to a variable declared by the user. */ +#define REG_USERVAR_P(RTX) ((RTX)->volatil) + +/* For a CONST_INT rtx, INTVAL extracts the integer. */ + +#define INTVAL(RTX) ((RTX)->fld[0].rtwint) + +/* For a SUBREG rtx, SUBREG_REG extracts the value we want a subreg of. + SUBREG_WORD extracts the word-number. */ + +#define SUBREG_REG(RTX) ((RTX)->fld[0].rtx) +#define SUBREG_WORD(RTX) ((RTX)->fld[1].rtint) + +/* 1 if the REG contained in SUBREG_REG is already known to be + sign- or zero-extended from the mode of the SUBREG to the mode of + the reg. SUBREG_PROMOTED_UNSIGNED_P gives the signedness of the + extension. + + When used as a LHS, is means that this extension must be done + when assigning to SUBREG_REG. */ + +#define SUBREG_PROMOTED_VAR_P(RTX) ((RTX)->in_struct) +#define SUBREG_PROMOTED_UNSIGNED_P(RTX) ((RTX)->unchanging) + +/* Access various components of an ASM_OPERANDS rtx. */ + +#define ASM_OPERANDS_TEMPLATE(RTX) XSTR ((RTX), 0) +#define ASM_OPERANDS_OUTPUT_CONSTRAINT(RTX) XSTR ((RTX), 1) +#define ASM_OPERANDS_OUTPUT_IDX(RTX) XINT ((RTX), 2) +#define ASM_OPERANDS_INPUT_VEC(RTX) XVEC ((RTX), 3) +#define ASM_OPERANDS_INPUT_CONSTRAINT_VEC(RTX) XVEC ((RTX), 4) +#define ASM_OPERANDS_INPUT(RTX, N) XVECEXP ((RTX), 3, (N)) +#define ASM_OPERANDS_INPUT_LENGTH(RTX) XVECLEN ((RTX), 3) +#define ASM_OPERANDS_INPUT_CONSTRAINT(RTX, N) XSTR (XVECEXP ((RTX), 4, (N)), 0) +#define ASM_OPERANDS_INPUT_MODE(RTX, N) GET_MODE (XVECEXP ((RTX), 4, (N))) +#define ASM_OPERANDS_SOURCE_FILE(RTX) XSTR ((RTX), 5) +#define ASM_OPERANDS_SOURCE_LINE(RTX) XINT ((RTX), 6) + +/* For a MEM rtx, 1 if it's a volatile reference. + Also in an ASM_OPERANDS rtx. */ +#define MEM_VOLATILE_P(RTX) ((RTX)->volatil) + +/* For a MEM rtx, 1 if it refers to a structure or union component. */ +#define MEM_IN_STRUCT_P(RTX) ((RTX)->in_struct) + +/* For a LABEL_REF, 1 means that this reference is to a label outside the + loop containing the reference. */ +#define LABEL_OUTSIDE_LOOP_P(RTX) ((RTX)->in_struct) + +/* For a LABEL_REF, 1 means it is for a nonlocal label. */ +/* Likewise in an EXPR_LIST for a REG_LABEL note. */ +#define LABEL_REF_NONLOCAL_P(RTX) ((RTX)->volatil) + +/* For a CODE_LABEL, 1 means always consider this label to be needed. */ +#define LABEL_PRESERVE_P(RTX) ((RTX)->in_struct) + +/* For a REG, 1 means the register is used only in an exit test of a loop. */ +#define REG_LOOP_TEST_P(RTX) ((RTX)->in_struct) + +/* During sched, for an insn, 1 means that the insn must be scheduled together + with the preceding insn. */ +#define SCHED_GROUP_P(INSN) ((INSN)->in_struct) + +/* During sched, for the LOG_LINKS of an insn, these cache the adjusted + cost of the dependence link. The cost of executing an instruction + may vary based on how the results are used. LINK_COST_ZERO is 1 when + the cost through the link varies and is unchanged (i.e., the link has + zero additional cost). LINK_COST_FREE is 1 when the cost through the + link is zero (i.e., the link makes the cost free). In other cases, + the adjustment to the cost is recomputed each time it is needed. */ +#define LINK_COST_ZERO(X) ((X)->jump) +#define LINK_COST_FREE(X) ((X)->call) + +/* For a SET rtx, SET_DEST is the place that is set + and SET_SRC is the value it is set to. */ +#define SET_DEST(RTX) ((RTX)->fld[0].rtx) +#define SET_SRC(RTX) ((RTX)->fld[1].rtx) + +/* For a TRAP_IF rtx, TRAP_CONDITION is an expression. */ +#define TRAP_CONDITION(RTX) ((RTX)->fld[0].rtx) + +/* 1 in a SYMBOL_REF if it addresses this function's constants pool. */ +#define CONSTANT_POOL_ADDRESS_P(RTX) ((RTX)->unchanging) + +/* Flag in a SYMBOL_REF for machine-specific purposes. */ +#define SYMBOL_REF_FLAG(RTX) ((RTX)->volatil) + +/* 1 means a SYMBOL_REF has been the library function in emit_library_call. */ +#define SYMBOL_REF_USED(RTX) ((RTX)->used) + +/* For an INLINE_HEADER rtx, FIRST_FUNCTION_INSN is the first insn + of the function that is not involved in copying parameters to + pseudo-registers. FIRST_PARM_INSN is the very first insn of + the function, including the parameter copying. + We keep this around in case we must splice + this function into the assembly code at the end of the file. + FIRST_LABELNO is the first label number used by the function (inclusive). + LAST_LABELNO is the last label used by the function (exclusive). + MAX_REGNUM is the largest pseudo-register used by that function. + FUNCTION_ARGS_SIZE is the size of the argument block in the stack. + POPS_ARGS is the number of bytes of input arguments popped by the function + STACK_SLOT_LIST is the list of stack slots. + FUNCTION_FLAGS are where single-bit flags are saved. + OUTGOING_ARGS_SIZE is the size of the largest outgoing stack parameter list. + ORIGINAL_ARG_VECTOR is a vector of the original DECL_RTX values + for the function arguments. + ORIGINAL_DECL_INITIAL is a pointer to the original DECL_INITIAL for the + function. + + We want this to lay down like an INSN. The PREV_INSN field + is always NULL. The NEXT_INSN field always points to the + first function insn of the function being squirreled away. */ + +#define FIRST_FUNCTION_INSN(RTX) ((RTX)->fld[2].rtx) +#define FIRST_PARM_INSN(RTX) ((RTX)->fld[3].rtx) +#define FIRST_LABELNO(RTX) ((RTX)->fld[4].rtint) +#define LAST_LABELNO(RTX) ((RTX)->fld[5].rtint) +#define MAX_PARMREG(RTX) ((RTX)->fld[6].rtint) +#define MAX_REGNUM(RTX) ((RTX)->fld[7].rtint) +#define FUNCTION_ARGS_SIZE(RTX) ((RTX)->fld[8].rtint) +#define POPS_ARGS(RTX) ((RTX)->fld[9].rtint) +#define STACK_SLOT_LIST(RTX) ((RTX)->fld[10].rtx) +#define FUNCTION_FLAGS(RTX) ((RTX)->fld[11].rtint) +#define OUTGOING_ARGS_SIZE(RTX) ((RTX)->fld[12].rtint) +#define ORIGINAL_ARG_VECTOR(RTX) ((RTX)->fld[13].rtvec) +#define ORIGINAL_DECL_INITIAL(RTX) ((RTX)->fld[14].rtx) + +/* In FUNCTION_FLAGS we save some variables computed when emitting the code + for the function and which must be `or'ed into the current flag values when + insns from that function are being inlined. */ + +/* These ought to be an enum, but non-ANSI compilers don't like that. */ +#define FUNCTION_FLAGS_CALLS_ALLOCA 01 +#define FUNCTION_FLAGS_CALLS_SETJMP 02 +#define FUNCTION_FLAGS_RETURNS_STRUCT 04 +#define FUNCTION_FLAGS_RETURNS_PCC_STRUCT 010 +#define FUNCTION_FLAGS_NEEDS_CONTEXT 020 +#define FUNCTION_FLAGS_HAS_NONLOCAL_LABEL 040 +#define FUNCTION_FLAGS_RETURNS_POINTER 0100 +#define FUNCTION_FLAGS_USES_CONST_POOL 0200 +#define FUNCTION_FLAGS_CALLS_LONGJMP 0400 +#define FUNCTION_FLAGS_USES_PIC_OFFSET_TABLE 01000 + +/* Define a macro to look for REG_INC notes, + but save time on machines where they never exist. */ + +/* Don't continue this line--convex cc version 4.1 would lose. */ +#if (defined (HAVE_PRE_INCREMENT) || defined (HAVE_PRE_DECREMENT) || defined (HAVE_POST_INCREMENT) || defined (HAVE_POST_DECREMENT)) +#define FIND_REG_INC_NOTE(insn, reg) (find_reg_note ((insn), REG_INC, (reg))) +#else +#define FIND_REG_INC_NOTE(insn, reg) 0 +#endif + +/* Indicate whether the machine has any sort of auto increment addressing. + If not, we can avoid checking for REG_INC notes. */ + +/* Don't continue this line--convex cc version 4.1 would lose. */ +#if (defined (HAVE_PRE_INCREMENT) || defined (HAVE_PRE_DECREMENT) || defined (HAVE_POST_INCREMENT) || defined (HAVE_POST_DECREMENT)) +#define AUTO_INC_DEC +#endif + +/* Generally useful functions. */ + +/* The following functions accept a wide integer argument. Rather than + having to cast on every function call, we use a macro instead, that is + defined here and in tree.h. */ + +#ifndef exact_log2 +#define exact_log2(N) exact_log2_wide ((HOST_WIDE_INT) (N)) +#define floor_log2(N) floor_log2_wide ((HOST_WIDE_INT) (N)) +#endif + +#define plus_constant(X,C) plus_constant_wide (X, (HOST_WIDE_INT) (C)) + +#define plus_constant_for_output(X,C) \ + plus_constant_for_output_wide (X, (HOST_WIDE_INT) (C)) + +extern rtx plus_constant_wide PROTO((rtx, HOST_WIDE_INT)); +extern rtx plus_constant_for_output_wide PROTO((rtx, HOST_WIDE_INT)); + +#define GEN_INT(N) gen_rtx (CONST_INT, VOIDmode, (N)) + +#if 0 +/* We cannot define prototypes for the variable argument functions, + since they have not been ANSI-fied, and an ANSI compiler would + complain when compiling the definition of these functions. */ + +extern rtx gen_rtx PROTO((enum rtx_code, enum machine_mode, ...)); +extern rtvec gen_rtvec PROTO((int, ...)); + +#else +extern rtx gen_rtx (); +extern rtvec gen_rtvec (); +#endif + +#ifdef BUFSIZ /* stdio.h has been included */ +extern rtx read_rtx PROTO((FILE *)); +#else +extern rtx read_rtx (); +#endif + +#if 0 +/* At present, don't prototype xrealloc, since all of the callers don't + cast their pointers to char *, and all of the xrealloc's don't use + void * yet. */ +extern char *xmalloc PROTO((size_t)); +extern char *xrealloc PROTO((void *, size_t)); +#else +extern char *xmalloc (); +extern char *xrealloc (); +#endif + +extern char *oballoc PROTO((int)); +extern char *permalloc PROTO((int)); +extern void free PROTO((void *)); +extern rtx rtx_alloc PROTO((RTX_CODE)); +extern rtvec rtvec_alloc PROTO((int)); +extern rtx find_reg_note PROTO((rtx, enum reg_note, rtx)); +extern rtx find_regno_note PROTO((rtx, enum reg_note, int)); +extern HOST_WIDE_INT get_integer_term PROTO((rtx)); +extern rtx get_related_value PROTO((rtx)); +extern rtx single_set PROTO((rtx)); +extern rtx find_last_value PROTO((rtx, rtx *, rtx)); +extern rtx copy_rtx PROTO((rtx)); +extern rtx copy_rtx_if_shared PROTO((rtx)); +extern rtx copy_most_rtx PROTO((rtx, rtx)); +extern rtx replace_rtx PROTO((rtx, rtx, rtx)); +extern rtvec gen_rtvec_v PROTO((int, rtx *)); +extern rtx gen_reg_rtx PROTO((enum machine_mode)); +extern rtx gen_label_rtx PROTO((void)); +extern rtx gen_inline_header_rtx PROTO((rtx, rtx, int, int, int, int, int, int, rtx, int, int, rtvec, rtx)); +extern rtx gen_lowpart_common PROTO((enum machine_mode, rtx)); +extern rtx gen_lowpart PROTO((enum machine_mode, rtx)); +extern rtx gen_lowpart_if_possible PROTO((enum machine_mode, rtx)); +extern rtx gen_highpart PROTO((enum machine_mode, rtx)); +extern rtx gen_realpart PROTO((enum machine_mode, rtx)); +extern rtx gen_imagpart PROTO((enum machine_mode, rtx)); +extern rtx operand_subword PROTO((rtx, int, int, enum machine_mode)); +extern rtx operand_subword_force PROTO((rtx, int, enum machine_mode)); +extern int subreg_lowpart_p PROTO((rtx)); +extern rtx make_safe_from PROTO((rtx, rtx)); +extern rtx memory_address PROTO((enum machine_mode, rtx)); +extern rtx get_insns PROTO((void)); +extern rtx get_last_insn PROTO((void)); +extern rtx get_last_insn_anywhere PROTO((void)); +extern void start_sequence PROTO((void)); +extern void push_to_sequence PROTO((rtx)); +extern void end_sequence PROTO((void)); +extern rtx gen_sequence PROTO((void)); +extern rtx immed_double_const PROTO((HOST_WIDE_INT, HOST_WIDE_INT, enum machine_mode)); +extern rtx force_const_mem PROTO((enum machine_mode, rtx)); +extern rtx force_reg PROTO((enum machine_mode, rtx)); +extern rtx get_pool_constant PROTO((rtx)); +extern enum machine_mode get_pool_mode PROTO((rtx)); +extern int get_pool_offset PROTO((rtx)); +extern rtx simplify_subtraction PROTO((rtx)); +extern rtx assign_stack_local PROTO((enum machine_mode, int, int)); +extern rtx assign_stack_temp PROTO((enum machine_mode, int, int)); +extern rtx protect_from_queue PROTO((rtx, int)); +extern void emit_queue PROTO((void)); +extern rtx emit_move_insn PROTO((rtx, rtx)); +extern rtx emit_insn_before PROTO((rtx, rtx)); +extern rtx emit_jump_insn_before PROTO((rtx, rtx)); +extern rtx emit_call_insn_before PROTO((rtx, rtx)); +extern rtx emit_barrier_before PROTO((rtx)); +extern rtx emit_note_before PROTO((int, rtx)); +extern rtx emit_insn_after PROTO((rtx, rtx)); +extern rtx emit_jump_insn_after PROTO((rtx, rtx)); +extern rtx emit_barrier_after PROTO((rtx)); +extern rtx emit_label_after PROTO((rtx, rtx)); +extern rtx emit_note_after PROTO((int, rtx)); +extern rtx emit_line_note_after PROTO((char *, int, rtx)); +extern rtx emit_insn PROTO((rtx)); +extern rtx emit_insns PROTO((rtx)); +extern rtx emit_insns_before PROTO((rtx, rtx)); +extern rtx emit_jump_insn PROTO((rtx)); +extern rtx emit_call_insn PROTO((rtx)); +extern rtx emit_label PROTO((rtx)); +extern rtx emit_barrier PROTO((void)); +extern rtx emit_line_note PROTO((char *, int)); +extern rtx emit_note PROTO((char *, int)); +extern rtx emit_line_note_force PROTO((char *, int)); +extern rtx make_insn_raw PROTO((rtx)); +extern rtx previous_insn PROTO((rtx)); +extern rtx next_insn PROTO((rtx)); +extern rtx prev_nonnote_insn PROTO((rtx)); +extern rtx next_nonnote_insn PROTO((rtx)); +extern rtx prev_real_insn PROTO((rtx)); +extern rtx next_real_insn PROTO((rtx)); +extern rtx prev_active_insn PROTO((rtx)); +extern rtx next_active_insn PROTO((rtx)); +extern rtx prev_label PROTO((rtx)); +extern rtx next_label PROTO((rtx)); +extern rtx next_cc0_user PROTO((rtx)); +extern rtx prev_cc0_setter PROTO((rtx)); +extern rtx reg_set_last PROTO((rtx, rtx)); +extern rtx next_nondeleted_insn PROTO((rtx)); +extern enum rtx_code reverse_condition PROTO((enum rtx_code)); +extern enum rtx_code swap_condition PROTO((enum rtx_code)); +extern enum rtx_code unsigned_condition PROTO((enum rtx_code)); +extern enum rtx_code signed_condition PROTO((enum rtx_code)); +extern rtx find_equiv_reg PROTO((rtx, rtx, enum reg_class, int, short *, int, enum machine_mode)); +extern rtx squeeze_notes PROTO((rtx, rtx)); +extern rtx delete_insn PROTO((rtx)); +extern void delete_jump PROTO((rtx)); +extern rtx get_label_before PROTO((rtx)); +extern rtx get_label_after PROTO((rtx)); +extern rtx follow_jumps PROTO((rtx)); +extern rtx adj_offsettable_operand PROTO((rtx, int)); +extern rtx try_split PROTO((rtx, rtx, int)); +extern rtx split_insns PROTO((rtx, rtx)); +extern rtx simplify_unary_operation PROTO((enum rtx_code, enum machine_mode, rtx, enum machine_mode)); +extern rtx simplify_binary_operation PROTO((enum rtx_code, enum machine_mode, rtx, rtx)); +extern rtx simplify_ternary_operation PROTO((enum rtx_code, enum machine_mode, enum machine_mode, rtx, rtx, rtx)); +extern rtx simplify_relational_operation PROTO((enum rtx_code, enum machine_mode, rtx, rtx)); +extern rtx nonlocal_label_rtx_list PROTO((void)); +extern rtx gen_move_insn PROTO((rtx, rtx)); +extern rtx gen_jump PROTO((rtx)); +extern rtx gen_beq PROTO((rtx)); +extern rtx gen_bge PROTO((rtx)); +extern rtx gen_ble PROTO((rtx)); +extern rtx eliminate_constant_term PROTO((rtx, rtx *)); +extern rtx expand_complex_abs PROTO((enum machine_mode, rtx, rtx, int)); + +/* Maximum number of parallel sets and clobbers in any insn in this fn. + Always at least 3, since the combiner could put that many togetherm + and we want this to remain correct for all the remaining passes. */ + +extern int max_parallel; + +extern int asm_noperands PROTO((rtx)); +extern char *decode_asm_operands PROTO((rtx, rtx *, rtx **, char **, enum machine_mode *)); + +extern enum reg_class reg_preferred_class PROTO((int)); +extern enum reg_class reg_alternate_class PROTO((int)); + +extern rtx get_first_nonparm_insn PROTO((void)); + +/* Standard pieces of rtx, to be substituted directly into things. */ +extern rtx pc_rtx; +extern rtx cc0_rtx; +extern rtx const0_rtx; +extern rtx const1_rtx; +extern rtx const2_rtx; +extern rtx constm1_rtx; +extern rtx const_true_rtx; + +extern rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; + +/* Returns a constant 0 rtx in mode MODE. Integer modes are treated the + same as VOIDmode. */ + +#define CONST0_RTX(MODE) (const_tiny_rtx[0][(int) (MODE)]) + +/* Likewise, for the constants 1 and 2. */ + +#define CONST1_RTX(MODE) (const_tiny_rtx[1][(int) (MODE)]) +#define CONST2_RTX(MODE) (const_tiny_rtx[2][(int) (MODE)]) + +/* All references to certain hard regs, except those created + by allocating pseudo regs into them (when that's possible), + go through these unique rtx objects. */ +extern rtx stack_pointer_rtx; +extern rtx frame_pointer_rtx; +extern rtx arg_pointer_rtx; +extern rtx pic_offset_table_rtx; +extern rtx struct_value_rtx; +extern rtx struct_value_incoming_rtx; +extern rtx static_chain_rtx; +extern rtx static_chain_incoming_rtx; + +/* Virtual registers are used during RTL generation to refer to locations into + the stack frame when the actual location isn't known until RTL generation + is complete. The routine instantiate_virtual_regs replaces these with + the proper value, which is normally {frame,arg,stack}_pointer_rtx plus + a constant. */ + +#define FIRST_VIRTUAL_REGISTER (FIRST_PSEUDO_REGISTER) + +/* This points to the first word of the incoming arguments passed on the stack, + either by the caller or by the callee when pretending it was passed by the + caller. */ + +extern rtx virtual_incoming_args_rtx; + +#define VIRTUAL_INCOMING_ARGS_REGNUM (FIRST_VIRTUAL_REGISTER) + +/* If FRAME_GROWS_DOWNWARDS, this points to immediately above the first + variable on the stack. Otherwise, it points to the first variable on + the stack. */ + +extern rtx virtual_stack_vars_rtx; + +#define VIRTUAL_STACK_VARS_REGNUM ((FIRST_VIRTUAL_REGISTER) + 1) + +/* This points to the location of dynamically-allocated memory on the stack + immediately after the stack pointer has been adjusted by the amount + desired. */ + +extern rtx virtual_stack_dynamic_rtx; + +#define VIRTUAL_STACK_DYNAMIC_REGNUM ((FIRST_VIRTUAL_REGISTER) + 2) + +/* This points to the location in the stack at which outgoing arguments should + be written when the stack is pre-pushed (arguments pushed using push + insns always use sp). */ + +extern rtx virtual_outgoing_args_rtx; + +#define VIRTUAL_OUTGOING_ARGS_REGNUM ((FIRST_VIRTUAL_REGISTER) + 3) + +#define LAST_VIRTUAL_REGISTER ((FIRST_VIRTUAL_REGISTER) + 3) + +extern rtx find_next_ref PROTO((rtx, rtx)); +extern rtx *find_single_use PROTO((rtx, rtx, rtx *)); + +/* It is hard to write the prototype for expand_expr, since it needs + expr.h to be included for the enumeration. */ + +extern rtx expand_expr (); +extern rtx immed_real_const_1(); + +#ifdef TREE_CODE +/* rtl.h and tree.h were included. */ +extern rtx output_constant_def PROTO((tree)); +extern rtx immed_real_const PROTO((tree)); +extern rtx immed_real_const_1 PROTO((REAL_VALUE_TYPE, enum machine_mode)); +extern tree make_tree PROTO((tree, rtx)); + +#else +extern rtx output_constant_def (); +extern rtx immed_real_const (); +extern rtx immed_real_const_1 (); +#endif + +/* Define a default value for STORE_FLAG_VALUE. */ + +#ifndef STORE_FLAG_VALUE +#define STORE_FLAG_VALUE 1 +#endif + +/* Nonzero after end of reload pass. + Set to 1 or 0 by toplev.c. */ + +extern int reload_completed; + +/* Set to 1 while reload_as_needed is operating. + Required by some machines to handle any generated moves differently. */ + +extern int reload_in_progress; + +/* If this is nonzero, we do not bother generating VOLATILE + around volatile memory references, and we are willing to + output indirect addresses. If cse is to follow, we reject + indirect addresses so a useful potential cse is generated; + if it is used only once, instruction combination will produce + the same indirect address eventually. */ +extern int cse_not_expected; + +/* Indexed by pseudo register number, gives the rtx for that pseudo. + Allocated in parallel with regno_pointer_flag. */ +extern rtx *regno_reg_rtx; + +/* Translates rtx code to tree code, for those codes needed by + REAL_ARITHMETIC. */ +extern int rtx_to_tree_code (); diff --git a/gnu/usr.bin/cc/lib/rtlanal.c b/gnu/usr.bin/cc/lib/rtlanal.c new file mode 100644 index 000000000000..549f9054f6ec --- /dev/null +++ b/gnu/usr.bin/cc/lib/rtlanal.c @@ -0,0 +1,1594 @@ +/* Analyze RTL for C-Compiler + Copyright (C) 1987, 1988, 1991, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include "rtl.h" + +void note_stores (); +int reg_set_p (); + +/* Bit flags that specify the machine subtype we are compiling for. + Bits are tested using macros TARGET_... defined in the tm.h file + and set by `-m...' switches. Must be defined in rtlanal.c. */ + +int target_flags; + +/* Return 1 if the value of X is unstable + (would be different at a different point in the program). + The frame pointer, arg pointer, etc. are considered stable + (within one function) and so is anything marked `unchanging'. */ + +int +rtx_unstable_p (x) + rtx x; +{ + register RTX_CODE code = GET_CODE (x); + register int i; + register char *fmt; + + if (code == MEM) + return ! RTX_UNCHANGING_P (x); + + if (code == QUEUED) + return 1; + + if (code == CONST || code == CONST_INT) + return 0; + + if (code == REG) + return ! (REGNO (x) == FRAME_POINTER_REGNUM + || REGNO (x) == ARG_POINTER_REGNUM + || RTX_UNCHANGING_P (x)); + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + if (rtx_unstable_p (XEXP (x, i))) + return 1; + return 0; +} + +/* Return 1 if X has a value that can vary even between two + executions of the program. 0 means X can be compared reliably + against certain constants or near-constants. + The frame pointer and the arg pointer are considered constant. */ + +int +rtx_varies_p (x) + rtx x; +{ + register RTX_CODE code = GET_CODE (x); + register int i; + register char *fmt; + + switch (code) + { + case MEM: + case QUEUED: + return 1; + + case CONST: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + return 0; + + case REG: + /* Note that we have to test for the actual rtx used for the frame + and arg pointers and not just the register number in case we have + eliminated the frame and/or arg pointer and are using it + for pseudos. */ + return ! (x == frame_pointer_rtx || x == arg_pointer_rtx); + + case LO_SUM: + /* The operand 0 of a LO_SUM is considered constant + (in fact is it related specifically to operand 1). */ + return rtx_varies_p (XEXP (x, 1)); + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + if (rtx_varies_p (XEXP (x, i))) + return 1; + return 0; +} + +/* Return 0 if the use of X as an address in a MEM can cause a trap. */ + +int +rtx_addr_can_trap_p (x) + register rtx x; +{ + register enum rtx_code code = GET_CODE (x); + + switch (code) + { + case SYMBOL_REF: + case LABEL_REF: + /* SYMBOL_REF is problematic due to the possible presence of + a #pragma weak, but to say that loads from symbols can trap is + *very* costly. It's not at all clear what's best here. For + now, we ignore the impact of #pragma weak. */ + return 0; + + case REG: + /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */ + return ! (x == frame_pointer_rtx || x == stack_pointer_rtx + || x == arg_pointer_rtx); + + case CONST: + return rtx_addr_can_trap_p (XEXP (x, 0)); + + case PLUS: + /* An address is assumed not to trap if it is an address that can't + trap plus a constant integer. */ + return (rtx_addr_can_trap_p (XEXP (x, 0)) + || GET_CODE (XEXP (x, 1)) != CONST_INT); + + case LO_SUM: + return rtx_addr_can_trap_p (XEXP (x, 1)); + } + + /* If it isn't one of the case above, it can cause a trap. */ + return 1; +} + +/* Return 1 if X refers to a memory location whose address + cannot be compared reliably with constant addresses, + or if X refers to a BLKmode memory object. */ + +int +rtx_addr_varies_p (x) + rtx x; +{ + register enum rtx_code code; + register int i; + register char *fmt; + + if (x == 0) + return 0; + + code = GET_CODE (x); + if (code == MEM) + return GET_MODE (x) == BLKmode || rtx_varies_p (XEXP (x, 0)); + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + if (rtx_addr_varies_p (XEXP (x, i))) + return 1; + return 0; +} + +/* Return the value of the integer term in X, if one is apparent; + otherwise return 0. + Only obvious integer terms are detected. + This is used in cse.c with the `related_value' field.*/ + +HOST_WIDE_INT +get_integer_term (x) + rtx x; +{ + if (GET_CODE (x) == CONST) + x = XEXP (x, 0); + + if (GET_CODE (x) == MINUS + && GET_CODE (XEXP (x, 1)) == CONST_INT) + return - INTVAL (XEXP (x, 1)); + if (GET_CODE (x) == PLUS + && GET_CODE (XEXP (x, 1)) == CONST_INT) + return INTVAL (XEXP (x, 1)); + return 0; +} + +/* If X is a constant, return the value sans apparent integer term; + otherwise return 0. + Only obvious integer terms are detected. */ + +rtx +get_related_value (x) + rtx x; +{ + if (GET_CODE (x) != CONST) + return 0; + x = XEXP (x, 0); + if (GET_CODE (x) == PLUS + && GET_CODE (XEXP (x, 1)) == CONST_INT) + return XEXP (x, 0); + else if (GET_CODE (x) == MINUS + && GET_CODE (XEXP (x, 1)) == CONST_INT) + return XEXP (x, 0); + return 0; +} + +/* Nonzero if register REG appears somewhere within IN. + Also works if REG is not a register; in this case it checks + for a subexpression of IN that is Lisp "equal" to REG. */ + +int +reg_mentioned_p (reg, in) + register rtx reg, in; +{ + register char *fmt; + register int i; + register enum rtx_code code; + + if (in == 0) + return 0; + + if (reg == in) + return 1; + + if (GET_CODE (in) == LABEL_REF) + return reg == XEXP (in, 0); + + code = GET_CODE (in); + + switch (code) + { + /* Compare registers by number. */ + case REG: + return GET_CODE (reg) == REG && REGNO (in) == REGNO (reg); + + /* These codes have no constituent expressions + and are unique. */ + case SCRATCH: + case CC0: + case PC: + return 0; + + case CONST_INT: + return GET_CODE (reg) == CONST_INT && INTVAL (in) == INTVAL (reg); + + case CONST_DOUBLE: + /* These are kept unique for a given value. */ + return 0; + } + + if (GET_CODE (reg) == code && rtx_equal_p (reg, in)) + return 1; + + fmt = GET_RTX_FORMAT (code); + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (in, i) - 1; j >= 0; j--) + if (reg_mentioned_p (reg, XVECEXP (in, i, j))) + return 1; + } + else if (fmt[i] == 'e' + && reg_mentioned_p (reg, XEXP (in, i))) + return 1; + } + return 0; +} + +/* Return 1 if in between BEG and END, exclusive of BEG and END, there is + no CODE_LABEL insn. */ + +int +no_labels_between_p (beg, end) + rtx beg, end; +{ + register rtx p; + for (p = NEXT_INSN (beg); p != end; p = NEXT_INSN (p)) + if (GET_CODE (p) == CODE_LABEL) + return 0; + return 1; +} + +/* Nonzero if register REG is used in an insn between + FROM_INSN and TO_INSN (exclusive of those two). */ + +int +reg_used_between_p (reg, from_insn, to_insn) + rtx reg, from_insn, to_insn; +{ + register rtx insn; + + if (from_insn == to_insn) + return 0; + + for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_overlap_mentioned_p (reg, PATTERN (insn))) + return 1; + return 0; +} + +/* Nonzero if the old value of X, a register, is referenced in BODY. If X + is entirely replaced by a new value and the only use is as a SET_DEST, + we do not consider it a reference. */ + +int +reg_referenced_p (x, body) + rtx x; + rtx body; +{ + int i; + + switch (GET_CODE (body)) + { + case SET: + if (reg_overlap_mentioned_p (x, SET_SRC (body))) + return 1; + + /* If the destination is anything other than CC0, PC, a REG or a SUBREG + of a REG that occupies all of the REG, the insn references X if + it is mentioned in the destination. */ + if (GET_CODE (SET_DEST (body)) != CC0 + && GET_CODE (SET_DEST (body)) != PC + && GET_CODE (SET_DEST (body)) != REG + && ! (GET_CODE (SET_DEST (body)) == SUBREG + && GET_CODE (SUBREG_REG (SET_DEST (body))) == REG + && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body)))) + + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) + == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body))) + + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) + && reg_overlap_mentioned_p (x, SET_DEST (body))) + return 1; + break; + + case ASM_OPERANDS: + for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--) + if (reg_overlap_mentioned_p (x, ASM_OPERANDS_INPUT (body, i))) + return 1; + break; + + case CALL: + case USE: + return reg_overlap_mentioned_p (x, body); + + case TRAP_IF: + return reg_overlap_mentioned_p (x, TRAP_CONDITION (body)); + + case UNSPEC: + case UNSPEC_VOLATILE: + case PARALLEL: + for (i = XVECLEN (body, 0) - 1; i >= 0; i--) + if (reg_referenced_p (x, XVECEXP (body, 0, i))) + return 1; + break; + } + + return 0; +} + +/* Nonzero if register REG is referenced in an insn between + FROM_INSN and TO_INSN (exclusive of those two). Sets of REG do + not count. */ + +int +reg_referenced_between_p (reg, from_insn, to_insn) + rtx reg, from_insn, to_insn; +{ + register rtx insn; + + if (from_insn == to_insn) + return 0; + + for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_referenced_p (reg, PATTERN (insn))) + return 1; + return 0; +} + +/* Nonzero if register REG is set or clobbered in an insn between + FROM_INSN and TO_INSN (exclusive of those two). */ + +int +reg_set_between_p (reg, from_insn, to_insn) + rtx reg, from_insn, to_insn; +{ + register rtx insn; + + if (from_insn == to_insn) + return 0; + + for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_set_p (reg, insn)) + return 1; + return 0; +} + +/* Internals of reg_set_between_p. */ + +static rtx reg_set_reg; +static int reg_set_flag; + +void +reg_set_p_1 (x) + rtx x; +{ + /* We don't want to return 1 if X is a MEM that contains a register + within REG_SET_REG. */ + + if ((GET_CODE (x) != MEM) + && reg_overlap_mentioned_p (reg_set_reg, x)) + reg_set_flag = 1; +} + +int +reg_set_p (reg, insn) + rtx reg, insn; +{ + rtx body = insn; + + /* We can be passed an insn or part of one. If we are passed an insn, + check if a side-effect of the insn clobbers REG. */ + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + if (FIND_REG_INC_NOTE (insn, reg) + || (GET_CODE (insn) == CALL_INSN + /* We'd like to test call_used_regs here, but rtlanal.c can't + reference that variable due to its use in genattrtab. So + we'll just be more conservative. */ + && ((GET_CODE (reg) == REG + && REGNO (reg) < FIRST_PSEUDO_REGISTER) + || GET_CODE (reg) == MEM))) + return 1; + + body = PATTERN (insn); + } + + reg_set_reg = reg; + reg_set_flag = 0; + note_stores (body, reg_set_p_1); + return reg_set_flag; +} + +/* Similar to reg_set_between_p, but check all registers in X. Return 0 + only if none of them are modified between START and END. Return 1 if + X contains a MEM; this routine does not perform any memory aliasing. */ + +int +modified_between_p (x, start, end) + rtx x; + rtx start, end; +{ + enum rtx_code code = GET_CODE (x); + char *fmt; + int i; + + switch (code) + { + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + return 0; + + case PC: + case CC0: + return 1; + + case MEM: + /* If the memory is not constant, assume it is modified. If it is + constant, we still have to check the address. */ + if (! RTX_UNCHANGING_P (x)) + return 1; + break; + + case REG: + return reg_set_between_p (x, start, end); + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e' + && modified_between_p (XEXP (x, i), start, end)) + return 1; + + return 0; +} + +/* Given an INSN, return a SET expression if this insn has only a single SET. + It may also have CLOBBERs, USEs, or SET whose output + will not be used, which we ignore. */ + +rtx +single_set (insn) + rtx insn; +{ + rtx set; + int i; + + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + return 0; + + if (GET_CODE (PATTERN (insn)) == SET) + return PATTERN (insn); + + else if (GET_CODE (PATTERN (insn)) == PARALLEL) + { + for (i = 0, set = 0; i < XVECLEN (PATTERN (insn), 0); i++) + if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET + && (! find_reg_note (insn, REG_UNUSED, + SET_DEST (XVECEXP (PATTERN (insn), 0, i))) + || side_effects_p (XVECEXP (PATTERN (insn), 0, i)))) + { + if (set) + return 0; + else + set = XVECEXP (PATTERN (insn), 0, i); + } + return set; + } + + return 0; +} + +/* Return the last thing that X was assigned from before *PINSN. Verify that + the object is not modified up to VALID_TO. If it was, if we hit + a partial assignment to X, or hit a CODE_LABEL first, return X. If we + found an assignment, update *PINSN to point to it. */ + +rtx +find_last_value (x, pinsn, valid_to) + rtx x; + rtx *pinsn; + rtx valid_to; +{ + rtx p; + + for (p = PREV_INSN (*pinsn); p && GET_CODE (p) != CODE_LABEL; + p = PREV_INSN (p)) + if (GET_RTX_CLASS (GET_CODE (p)) == 'i') + { + rtx set = single_set (p); + rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX); + + if (set && rtx_equal_p (x, SET_DEST (set))) + { + rtx src = SET_SRC (set); + + if (note && GET_CODE (XEXP (note, 0)) != EXPR_LIST) + src = XEXP (note, 0); + + if (! modified_between_p (src, PREV_INSN (p), valid_to) + /* Reject hard registers because we don't usually want + to use them; we'd rather use a pseudo. */ + && ! (GET_CODE (src) == REG + && REGNO (src) < FIRST_PSEUDO_REGISTER)) + { + *pinsn = p; + return src; + } + } + + /* If set in non-simple way, we don't have a value. */ + if (reg_set_p (x, p)) + break; + } + + return x; +} + +/* Return nonzero if register in range [REGNO, ENDREGNO) + appears either explicitly or implicitly in X + other than being stored into. + + References contained within the substructure at LOC do not count. + LOC may be zero, meaning don't ignore anything. */ + +int +refers_to_regno_p (regno, endregno, x, loc) + int regno, endregno; + rtx x; + rtx *loc; +{ + register int i; + register RTX_CODE code; + register char *fmt; + + repeat: + /* The contents of a REG_NONNEG note is always zero, so we must come here + upon repeat in case the last REG_NOTE is a REG_NONNEG note. */ + if (x == 0) + return 0; + + code = GET_CODE (x); + + switch (code) + { + case REG: + i = REGNO (x); + return (endregno > i + && regno < i + (i < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (i, GET_MODE (x)) + : 1)); + + case SUBREG: + /* If this is a SUBREG of a hard reg, we can see exactly which + registers are being modified. Otherwise, handle normally. */ + if (GET_CODE (SUBREG_REG (x)) == REG + && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) + { + int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); + int inner_endregno + = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); + + return endregno > inner_regno && regno < inner_endregno; + } + break; + + case CLOBBER: + case SET: + if (&SET_DEST (x) != loc + /* Note setting a SUBREG counts as referring to the REG it is in for + a pseudo but not for hard registers since we can + treat each word individually. */ + && ((GET_CODE (SET_DEST (x)) == SUBREG + && loc != &SUBREG_REG (SET_DEST (x)) + && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG + && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER + && refers_to_regno_p (regno, endregno, + SUBREG_REG (SET_DEST (x)), loc)) + || (GET_CODE (SET_DEST (x)) != REG + && refers_to_regno_p (regno, endregno, SET_DEST (x), loc)))) + return 1; + + if (code == CLOBBER || loc == &SET_SRC (x)) + return 0; + x = SET_SRC (x); + goto repeat; + } + + /* X does not match, so try its subexpressions. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e' && loc != &XEXP (x, i)) + { + if (i == 0) + { + x = XEXP (x, 0); + goto repeat; + } + else + if (refers_to_regno_p (regno, endregno, XEXP (x, i), loc)) + return 1; + } + else if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (x, i) - 1; j >=0; j--) + if (loc != &XVECEXP (x, i, j) + && refers_to_regno_p (regno, endregno, XVECEXP (x, i, j), loc)) + return 1; + } + } + return 0; +} + +/* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, + we check if any register number in X conflicts with the relevant register + numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN + contains a MEM (we don't bother checking for memory addresses that can't + conflict because we expect this to be a rare case. */ + +int +reg_overlap_mentioned_p (x, in) + rtx x, in; +{ + int regno, endregno; + + if (GET_CODE (x) == SUBREG) + { + regno = REGNO (SUBREG_REG (x)); + if (regno < FIRST_PSEUDO_REGISTER) + regno += SUBREG_WORD (x); + } + else if (GET_CODE (x) == REG) + regno = REGNO (x); + else if (CONSTANT_P (x)) + return 0; + else if (GET_CODE (x) == MEM) + { + char *fmt; + int i; + + if (GET_CODE (in) == MEM) + return 1; + + fmt = GET_RTX_FORMAT (GET_CODE (in)); + + for (i = GET_RTX_LENGTH (GET_CODE (in)) - 1; i >= 0; i--) + if (fmt[i] == 'e' && reg_overlap_mentioned_p (x, XEXP (in, i))) + return 1; + + return 0; + } + else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC + || GET_CODE (x) == CC0) + return reg_mentioned_p (x, in); + else + abort (); + + endregno = regno + (regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); + + return refers_to_regno_p (regno, endregno, in, NULL_PTR); +} + +/* Used for communications between the next few functions. */ + +static int reg_set_last_unknown; +static rtx reg_set_last_value; +static int reg_set_last_first_regno, reg_set_last_last_regno; + +/* Called via note_stores from reg_set_last. */ + +static void +reg_set_last_1 (x, pat) + rtx x; + rtx pat; +{ + int first, last; + + /* If X is not a register, or is not one in the range we care + about, ignore. */ + if (GET_CODE (x) != REG) + return; + + first = REGNO (x); + last = first + (first < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (first, GET_MODE (x)) : 1); + + if (first >= reg_set_last_last_regno + || last <= reg_set_last_first_regno) + return; + + /* If this is a CLOBBER or is some complex LHS, or doesn't modify + exactly the registers we care about, show we don't know the value. */ + if (GET_CODE (pat) == CLOBBER || SET_DEST (pat) != x + || first != reg_set_last_first_regno + || last != reg_set_last_last_regno) + reg_set_last_unknown = 1; + else + reg_set_last_value = SET_SRC (pat); +} + +/* Return the last value to which REG was set prior to INSN. If we can't + find it easily, return 0. + + We only return a REG, SUBREG, or constant because it is too hard to + check if a MEM remains unchanged. */ + +rtx +reg_set_last (x, insn) + rtx x; + rtx insn; +{ + rtx orig_insn = insn; + + reg_set_last_first_regno = REGNO (x); + + reg_set_last_last_regno + = reg_set_last_first_regno + + (reg_set_last_first_regno < FIRST_PSEUDO_REGISTER + ? HARD_REGNO_NREGS (reg_set_last_first_regno, GET_MODE (x)) : 1); + + reg_set_last_unknown = 0; + reg_set_last_value = 0; + + /* Scan backwards until reg_set_last_1 changed one of the above flags. + Stop when we reach a label or X is a hard reg and we reach a + CALL_INSN (if reg_set_last_last_regno is a hard reg). + + If we find a set of X, ensure that its SET_SRC remains unchanged. */ + + /* We compare with <= here, because reg_set_last_last_regno + is actually the number of the first reg *not* in X. */ + for (; + insn && GET_CODE (insn) != CODE_LABEL + && ! (GET_CODE (insn) == CALL_INSN + && reg_set_last_last_regno <= FIRST_PSEUDO_REGISTER); + insn = PREV_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + note_stores (PATTERN (insn), reg_set_last_1); + if (reg_set_last_unknown) + return 0; + else if (reg_set_last_value) + { + if (CONSTANT_P (reg_set_last_value) + || ((GET_CODE (reg_set_last_value) == REG + || GET_CODE (reg_set_last_value) == SUBREG) + && ! reg_set_between_p (reg_set_last_value, + NEXT_INSN (insn), orig_insn))) + return reg_set_last_value; + else + return 0; + } + } + + return 0; +} + +/* This is 1 until after reload pass. */ +int rtx_equal_function_value_matters; + +/* Return 1 if X and Y are identical-looking rtx's. + This is the Lisp function EQUAL for rtx arguments. */ + +int +rtx_equal_p (x, y) + rtx x, y; +{ + register int i; + register int j; + register enum rtx_code code; + register char *fmt; + + if (x == y) + return 1; + if (x == 0 || y == 0) + return 0; + + code = GET_CODE (x); + /* Rtx's of different codes cannot be equal. */ + if (code != GET_CODE (y)) + return 0; + + /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. + (REG:SI x) and (REG:HI x) are NOT equivalent. */ + + if (GET_MODE (x) != GET_MODE (y)) + return 0; + + /* REG, LABEL_REF, and SYMBOL_REF can be compared nonrecursively. */ + + if (code == REG) + /* Until rtl generation is complete, don't consider a reference to the + return register of the current function the same as the return from a + called function. This eases the job of function integration. Once the + distinction is no longer needed, they can be considered equivalent. */ + return (REGNO (x) == REGNO (y) + && (! rtx_equal_function_value_matters + || REG_FUNCTION_VALUE_P (x) == REG_FUNCTION_VALUE_P (y))); + else if (code == LABEL_REF) + return XEXP (x, 0) == XEXP (y, 0); + else if (code == SYMBOL_REF) + return XSTR (x, 0) == XSTR (y, 0); + else if (code == SCRATCH || code == CONST_DOUBLE) + return 0; + + /* Compare the elements. If any pair of corresponding elements + fail to match, return 0 for the whole things. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + switch (fmt[i]) + { + case 'w': + if (XWINT (x, i) != XWINT (y, i)) + return 0; + break; + + case 'n': + case 'i': + if (XINT (x, i) != XINT (y, i)) + return 0; + break; + + case 'V': + case 'E': + /* Two vectors must have the same length. */ + if (XVECLEN (x, i) != XVECLEN (y, i)) + return 0; + + /* And the corresponding elements must match. */ + for (j = 0; j < XVECLEN (x, i); j++) + if (rtx_equal_p (XVECEXP (x, i, j), XVECEXP (y, i, j)) == 0) + return 0; + break; + + case 'e': + if (rtx_equal_p (XEXP (x, i), XEXP (y, i)) == 0) + return 0; + break; + + case 'S': + case 's': + if (strcmp (XSTR (x, i), XSTR (y, i))) + return 0; + break; + + case 'u': + /* These are just backpointers, so they don't matter. */ + break; + + case '0': + break; + + /* It is believed that rtx's at this level will never + contain anything but integers and other rtx's, + except for within LABEL_REFs and SYMBOL_REFs. */ + default: + abort (); + } + } + return 1; +} + +/* Call FUN on each register or MEM that is stored into or clobbered by X. + (X would be the pattern of an insn). + FUN receives two arguments: + the REG, MEM, CC0 or PC being stored in or clobbered, + the SET or CLOBBER rtx that does the store. + + If the item being stored in or clobbered is a SUBREG of a hard register, + the SUBREG will be passed. */ + +void +note_stores (x, fun) + register rtx x; + void (*fun) (); +{ + if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)) + { + register rtx dest = SET_DEST (x); + while ((GET_CODE (dest) == SUBREG + && (GET_CODE (SUBREG_REG (dest)) != REG + || REGNO (SUBREG_REG (dest)) >= FIRST_PSEUDO_REGISTER)) + || GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == SIGN_EXTRACT + || GET_CODE (dest) == STRICT_LOW_PART) + dest = XEXP (dest, 0); + (*fun) (dest, x); + } + else if (GET_CODE (x) == PARALLEL) + { + register int i; + for (i = XVECLEN (x, 0) - 1; i >= 0; i--) + { + register rtx y = XVECEXP (x, 0, i); + if (GET_CODE (y) == SET || GET_CODE (y) == CLOBBER) + { + register rtx dest = SET_DEST (y); + while ((GET_CODE (dest) == SUBREG + && (GET_CODE (SUBREG_REG (dest)) != REG + || (REGNO (SUBREG_REG (dest)) + >= FIRST_PSEUDO_REGISTER))) + || GET_CODE (dest) == ZERO_EXTRACT + || GET_CODE (dest) == SIGN_EXTRACT + || GET_CODE (dest) == STRICT_LOW_PART) + dest = XEXP (dest, 0); + (*fun) (dest, y); + } + } + } +} + +/* Return nonzero if X's old contents don't survive after INSN. + This will be true if X is (cc0) or if X is a register and + X dies in INSN or because INSN entirely sets X. + + "Entirely set" means set directly and not through a SUBREG, + ZERO_EXTRACT or SIGN_EXTRACT, so no trace of the old contents remains. + Likewise, REG_INC does not count. + + REG may be a hard or pseudo reg. Renumbering is not taken into account, + but for this use that makes no difference, since regs don't overlap + during their lifetimes. Therefore, this function may be used + at any time after deaths have been computed (in flow.c). + + If REG is a hard reg that occupies multiple machine registers, this + function will only return 1 if each of those registers will be replaced + by INSN. */ + +int +dead_or_set_p (insn, x) + rtx insn; + rtx x; +{ + register int regno, last_regno; + register int i; + + /* Can't use cc0_rtx below since this file is used by genattrtab.c. */ + if (GET_CODE (x) == CC0) + return 1; + + if (GET_CODE (x) != REG) + abort (); + + regno = REGNO (x); + last_regno = (regno >= FIRST_PSEUDO_REGISTER ? regno + : regno + HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1); + + for (i = regno; i <= last_regno; i++) + if (! dead_or_set_regno_p (insn, i)) + return 0; + + return 1; +} + +/* Utility function for dead_or_set_p to check an individual register. Also + called from flow.c. */ + +int +dead_or_set_regno_p (insn, test_regno) + rtx insn; + int test_regno; +{ + int regno, endregno; + rtx link; + + /* See if there is a death note for something that includes TEST_REGNO. */ + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + { + if (REG_NOTE_KIND (link) != REG_DEAD || GET_CODE (XEXP (link, 0)) != REG) + continue; + + regno = REGNO (XEXP (link, 0)); + endregno = (regno >= FIRST_PSEUDO_REGISTER ? regno + 1 + : regno + HARD_REGNO_NREGS (regno, + GET_MODE (XEXP (link, 0)))); + + if (test_regno >= regno && test_regno < endregno) + return 1; + } + + if (GET_CODE (PATTERN (insn)) == SET) + { + rtx dest = SET_DEST (PATTERN (insn)); + + /* A value is totally replaced if it is the destination or the + destination is a SUBREG of REGNO that does not change the number of + words in it. */ + if (GET_CODE (dest) == SUBREG + && (((GET_MODE_SIZE (GET_MODE (dest)) + + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) + + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) + dest = SUBREG_REG (dest); + + if (GET_CODE (dest) != REG) + return 0; + + regno = REGNO (dest); + endregno = (regno >= FIRST_PSEUDO_REGISTER ? regno + 1 + : regno + HARD_REGNO_NREGS (regno, GET_MODE (dest))); + + return (test_regno >= regno && test_regno < endregno); + } + else if (GET_CODE (PATTERN (insn)) == PARALLEL) + { + register int i; + + for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) + { + rtx body = XVECEXP (PATTERN (insn), 0, i); + + if (GET_CODE (body) == SET || GET_CODE (body) == CLOBBER) + { + rtx dest = SET_DEST (body); + + if (GET_CODE (dest) == SUBREG + && (((GET_MODE_SIZE (GET_MODE (dest)) + + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) + + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) + dest = SUBREG_REG (dest); + + if (GET_CODE (dest) != REG) + continue; + + regno = REGNO (dest); + endregno = (regno >= FIRST_PSEUDO_REGISTER ? regno + 1 + : regno + HARD_REGNO_NREGS (regno, GET_MODE (dest))); + + if (test_regno >= regno && test_regno < endregno) + return 1; + } + } + } + + return 0; +} + +/* Return the reg-note of kind KIND in insn INSN, if there is one. + If DATUM is nonzero, look for one whose datum is DATUM. */ + +rtx +find_reg_note (insn, kind, datum) + rtx insn; + enum reg_note kind; + rtx datum; +{ + register rtx link; + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == kind + && (datum == 0 || datum == XEXP (link, 0))) + return link; + return 0; +} + +/* Return the reg-note of kind KIND in insn INSN which applies to register + number REGNO, if any. Return 0 if there is no such reg-note. Note that + the REGNO of this NOTE need not be REGNO if REGNO is a hard register; + it might be the case that the note overlaps REGNO. */ + +rtx +find_regno_note (insn, kind, regno) + rtx insn; + enum reg_note kind; + int regno; +{ + register rtx link; + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (REG_NOTE_KIND (link) == kind + /* Verify that it is a register, so that scratch and MEM won't cause a + problem here. */ + && GET_CODE (XEXP (link, 0)) == REG + && REGNO (XEXP (link, 0)) <= regno + && ((REGNO (XEXP (link, 0)) + + (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1 + : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)), + GET_MODE (XEXP (link, 0))))) + > regno)) + return link; + return 0; +} + +/* Remove register note NOTE from the REG_NOTES of INSN. */ + +void +remove_note (insn, note) + register rtx note; + register rtx insn; +{ + register rtx link; + + if (REG_NOTES (insn) == note) + { + REG_NOTES (insn) = XEXP (note, 1); + return; + } + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + if (XEXP (link, 1) == note) + { + XEXP (link, 1) = XEXP (note, 1); + return; + } + + abort (); +} + +/* Nonzero if X contains any volatile memory references + UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */ + +int +volatile_refs_p (x) + rtx x; +{ + register RTX_CODE code; + + code = GET_CODE (x); + switch (code) + { + case LABEL_REF: + case SYMBOL_REF: + case CONST_INT: + case CONST: + case CONST_DOUBLE: + case CC0: + case PC: + case REG: + case SCRATCH: + case CLOBBER: + case ASM_INPUT: + case ADDR_VEC: + case ADDR_DIFF_VEC: + return 0; + + case CALL: + case UNSPEC_VOLATILE: + /* case TRAP_IF: This isn't clear yet. */ + return 1; + + case MEM: + case ASM_OPERANDS: + if (MEM_VOLATILE_P (x)) + return 1; + } + + /* Recursively scan the operands of this expression. */ + + { + register char *fmt = GET_RTX_FORMAT (code); + register int i; + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + { + if (volatile_refs_p (XEXP (x, i))) + return 1; + } + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + if (volatile_refs_p (XVECEXP (x, i, j))) + return 1; + } + } + } + return 0; +} + +/* Similar to above, except that it also rejects register pre- and post- + incrementing. */ + +int +side_effects_p (x) + rtx x; +{ + register RTX_CODE code; + + code = GET_CODE (x); + switch (code) + { + case LABEL_REF: + case SYMBOL_REF: + case CONST_INT: + case CONST: + case CONST_DOUBLE: + case CC0: + case PC: + case REG: + case SCRATCH: + case ASM_INPUT: + case ADDR_VEC: + case ADDR_DIFF_VEC: + return 0; + + case CLOBBER: + /* Reject CLOBBER with a non-VOID mode. These are made by combine.c + when some combination can't be done. If we see one, don't think + that we can simplify the expression. */ + return (GET_MODE (x) != VOIDmode); + + case PRE_INC: + case PRE_DEC: + case POST_INC: + case POST_DEC: + case CALL: + case UNSPEC_VOLATILE: + /* case TRAP_IF: This isn't clear yet. */ + return 1; + + case MEM: + case ASM_OPERANDS: + if (MEM_VOLATILE_P (x)) + return 1; + } + + /* Recursively scan the operands of this expression. */ + + { + register char *fmt = GET_RTX_FORMAT (code); + register int i; + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + { + if (side_effects_p (XEXP (x, i))) + return 1; + } + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + if (side_effects_p (XVECEXP (x, i, j))) + return 1; + } + } + } + return 0; +} + +/* Return nonzero if evaluating rtx X might cause a trap. */ + +int +may_trap_p (x) + rtx x; +{ + int i; + enum rtx_code code; + char *fmt; + + if (x == 0) + return 0; + code = GET_CODE (x); + switch (code) + { + /* Handle these cases quickly. */ + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case CONST: + case PC: + case CC0: + case REG: + case SCRATCH: + return 0; + + /* Conditional trap can trap! */ + case UNSPEC_VOLATILE: + case TRAP_IF: + return 1; + + /* Memory ref can trap unless it's a static var or a stack slot. */ + case MEM: + return rtx_addr_can_trap_p (XEXP (x, 0)); + + /* Division by a non-constant might trap. */ + case DIV: + case MOD: + case UDIV: + case UMOD: + if (! CONSTANT_P (XEXP (x, 1))) + return 1; + /* This was const0_rtx, but by not using that, + we can link this file into other programs. */ + if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0) + return 1; + default: + /* Any floating arithmetic may trap. */ + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) + return 1; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + { + if (may_trap_p (XEXP (x, i))) + return 1; + } + else if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + if (may_trap_p (XVECEXP (x, i, j))) + return 1; + } + } + return 0; +} + +/* Return nonzero if X contains a comparison that is not either EQ or NE, + i.e., an inequality. */ + +int +inequality_comparisons_p (x) + rtx x; +{ + register char *fmt; + register int len, i; + register enum rtx_code code = GET_CODE (x); + + switch (code) + { + case REG: + case SCRATCH: + case PC: + case CC0: + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case LABEL_REF: + case SYMBOL_REF: + return 0; + + case LT: + case LTU: + case GT: + case GTU: + case LE: + case LEU: + case GE: + case GEU: + return 1; + } + + len = GET_RTX_LENGTH (code); + fmt = GET_RTX_FORMAT (code); + + for (i = 0; i < len; i++) + { + if (fmt[i] == 'e') + { + if (inequality_comparisons_p (XEXP (x, i))) + return 1; + } + else if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + if (inequality_comparisons_p (XVECEXP (x, i, j))) + return 1; + } + } + + return 0; +} + +/* Replace any occurrence of FROM in X with TO. + + Note that copying is not done so X must not be shared unless all copies + are to be modified. */ + +rtx +replace_rtx (x, from, to) + rtx x, from, to; +{ + register int i, j; + register char *fmt; + + if (x == from) + return to; + + /* Allow this function to make replacements in EXPR_LISTs. */ + if (x == 0) + return 0; + + fmt = GET_RTX_FORMAT (GET_CODE (x)); + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + XEXP (x, i) = replace_rtx (XEXP (x, i), from, to); + else if (fmt[i] == 'E') + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + XVECEXP (x, i, j) = replace_rtx (XVECEXP (x, i, j), from, to); + } + + return x; +} + +/* Throughout the rtx X, replace many registers according to REG_MAP. + Return the replacement for X (which may be X with altered contents). + REG_MAP[R] is the replacement for register R, or 0 for don't replace. + NREGS is the length of REG_MAP; regs >= NREGS are not mapped. + + We only support REG_MAP entries of REG or SUBREG. Also, hard registers + should not be mapped to pseudos or vice versa since validate_change + is not called. + + If REPLACE_DEST is 1, replacements are also done in destinations; + otherwise, only sources are replaced. */ + +rtx +replace_regs (x, reg_map, nregs, replace_dest) + rtx x; + rtx *reg_map; + int nregs; + int replace_dest; +{ + register enum rtx_code code; + register int i; + register char *fmt; + + if (x == 0) + return x; + + code = GET_CODE (x); + switch (code) + { + case SCRATCH: + case PC: + case CC0: + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + return x; + + case REG: + /* Verify that the register has an entry before trying to access it. */ + if (REGNO (x) < nregs && reg_map[REGNO (x)] != 0) + return reg_map[REGNO (x)]; + return x; + + case SUBREG: + /* Prevent making nested SUBREGs. */ + if (GET_CODE (SUBREG_REG (x)) == REG && REGNO (SUBREG_REG (x)) < nregs + && reg_map[REGNO (SUBREG_REG (x))] != 0 + && GET_CODE (reg_map[REGNO (SUBREG_REG (x))]) == SUBREG) + { + rtx map_val = reg_map[REGNO (SUBREG_REG (x))]; + rtx map_inner = SUBREG_REG (map_val); + + if (GET_MODE (x) == GET_MODE (map_inner)) + return map_inner; + else + { + /* We cannot call gen_rtx here since we may be linked with + genattrtab.c. */ + /* Let's try clobbering the incoming SUBREG and see + if this is really safe. */ + SUBREG_REG (x) = map_inner; + SUBREG_WORD (x) += SUBREG_WORD (map_val); + return x; +#if 0 + rtx new = rtx_alloc (SUBREG); + PUT_MODE (new, GET_MODE (x)); + SUBREG_REG (new) = map_inner; + SUBREG_WORD (new) = SUBREG_WORD (x) + SUBREG_WORD (map_val); +#endif + } + } + break; + + case SET: + if (replace_dest) + SET_DEST (x) = replace_regs (SET_DEST (x), reg_map, nregs, 0); + + else if (GET_CODE (SET_DEST (x)) == MEM + || GET_CODE (SET_DEST (x)) == STRICT_LOW_PART) + /* Even if we are not to replace destinations, replace register if it + is CONTAINED in destination (destination is memory or + STRICT_LOW_PART). */ + XEXP (SET_DEST (x), 0) = replace_regs (XEXP (SET_DEST (x), 0), + reg_map, nregs, 0); + else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT) + /* Similarly, for ZERO_EXTRACT we replace all operands. */ + break; + + SET_SRC (x) = replace_regs (SET_SRC (x), reg_map, nregs, 0); + return x; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + XEXP (x, i) = replace_regs (XEXP (x, i), reg_map, nregs, replace_dest); + if (fmt[i] == 'E') + { + register int j; + for (j = 0; j < XVECLEN (x, i); j++) + XVECEXP (x, i, j) = replace_regs (XVECEXP (x, i, j), reg_map, + nregs, replace_dest); + } + } + return x; +} diff --git a/gnu/usr.bin/cc/lib/sched.c b/gnu/usr.bin/cc/lib/sched.c new file mode 100644 index 000000000000..2fec9bcf9bbb --- /dev/null +++ b/gnu/usr.bin/cc/lib/sched.c @@ -0,0 +1,4675 @@ +/* Instruction scheduling pass. + Copyright (C) 1992 Free Software Foundation, Inc. + Contributed by Michael Tiemann (tiemann@cygnus.com) + Enhanced by, and currently maintained by, Jim Wilson (wilson@cygnus.com) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Instruction scheduling pass. + + This pass implements list scheduling within basic blocks. It is + run after flow analysis, but before register allocation. The + scheduler works as follows: + + We compute insn priorities based on data dependencies. Flow + analysis only creates a fraction of the data-dependencies we must + observe: namely, only those dependencies which the combiner can be + expected to use. For this pass, we must therefore create the + remaining dependencies we need to observe: register dependencies, + memory dependencies, dependencies to keep function calls in order, + and the dependence between a conditional branch and the setting of + condition codes are all dealt with here. + + The scheduler first traverses the data flow graph, starting with + the last instruction, and proceeding to the first, assigning + values to insn_priority as it goes. This sorts the instructions + topologically by data dependence. + + Once priorities have been established, we order the insns using + list scheduling. This works as follows: starting with a list of + all the ready insns, and sorted according to priority number, we + schedule the insn from the end of the list by placing its + predecessors in the list according to their priority order. We + consider this insn scheduled by setting the pointer to the "end" of + the list to point to the previous insn. When an insn has no + predecessors, we either queue it until sufficient time has elapsed + or add it to the ready list. As the instructions are scheduled or + when stalls are introduced, the queue advances and dumps insns into + the ready list. When all insns down to the lowest priority have + been scheduled, the critical path of the basic block has been made + as short as possible. The remaining insns are then scheduled in + remaining slots. + + Function unit conflicts are resolved during reverse list scheduling + by tracking the time when each insn is committed to the schedule + and from that, the time the function units it uses must be free. + As insns on the ready list are considered for scheduling, those + that would result in a blockage of the already committed insns are + queued until no blockage will result. Among the remaining insns on + the ready list to be considered, the first one with the largest + potential for causing a subsequent blockage is chosen. + + The following list shows the order in which we want to break ties + among insns in the ready list: + + 1. choose insn with lowest conflict cost, ties broken by + 2. choose insn with the longest path to end of bb, ties broken by + 3. choose insn that kills the most registers, ties broken by + 4. choose insn that conflicts with the most ready insns, or finally + 5. choose insn with lowest UID. + + Memory references complicate matters. Only if we can be certain + that memory references are not part of the data dependency graph + (via true, anti, or output dependence), can we move operations past + memory references. To first approximation, reads can be done + independently, while writes introduce dependencies. Better + approximations will yield fewer dependencies. + + Dependencies set up by memory references are treated in exactly the + same way as other dependencies, by using LOG_LINKS. + + Having optimized the critical path, we may have also unduly + extended the lifetimes of some registers. If an operation requires + that constants be loaded into registers, it is certainly desirable + to load those constants as early as necessary, but no earlier. + I.e., it will not do to load up a bunch of registers at the + beginning of a basic block only to use them at the end, if they + could be loaded later, since this may result in excessive register + utilization. + + Note that since branches are never in basic blocks, but only end + basic blocks, this pass will not do any branch scheduling. But + that is ok, since we can use GNU's delayed branch scheduling + pass to take care of this case. + + Also note that no further optimizations based on algebraic identities + are performed, so this pass would be a good one to perform instruction + splitting, such as breaking up a multiply instruction into shifts + and adds where that is profitable. + + Given the memory aliasing analysis that this pass should perform, + it should be possible to remove redundant stores to memory, and to + load values from registers instead of hitting memory. + + This pass must update information that subsequent passes expect to be + correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths, + reg_n_calls_crossed, and reg_live_length. Also, basic_block_head, + basic_block_end. + + The information in the line number notes is carefully retained by this + pass. All other NOTE insns are grouped in their same relative order at + the beginning of basic blocks that have been scheduled. */ + +#include +#include "config.h" +#include "rtl.h" +#include "basic-block.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "flags.h" +#include "insn-config.h" +#include "insn-attr.h" + +#ifdef INSN_SCHEDULING +/* Arrays set up by scheduling for the same respective purposes as + similar-named arrays set up by flow analysis. We work with these + arrays during the scheduling pass so we can compare values against + unscheduled code. + + Values of these arrays are copied at the end of this pass into the + arrays set up by flow analysis. */ +static short *sched_reg_n_deaths; +static int *sched_reg_n_calls_crossed; +static int *sched_reg_live_length; + +/* Element N is the next insn that sets (hard or pseudo) register + N within the current basic block; or zero, if there is no + such insn. Needed for new registers which may be introduced + by splitting insns. */ +static rtx *reg_last_uses; +static rtx *reg_last_sets; + +/* Vector indexed by INSN_UID giving the original ordering of the insns. */ +static int *insn_luid; +#define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)]) + +/* Vector indexed by INSN_UID giving each instruction a priority. */ +static int *insn_priority; +#define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)]) + +static short *insn_costs; +#define INSN_COST(INSN) insn_costs[INSN_UID (INSN)] + +/* Vector indexed by INSN_UID giving an encoding of the function units + used. */ +static short *insn_units; +#define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)] + +/* Vector indexed by INSN_UID giving an encoding of the blockage range + function. The unit and the range are encoded. */ +static unsigned int *insn_blockage; +#define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)] +#define UNIT_BITS 5 +#define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1) +#define ENCODE_BLOCKAGE(U,R) \ + ((((U) << UNIT_BITS) << BLOCKAGE_BITS \ + | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \ + | MAX_BLOCKAGE_COST (R)) +#define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS)) +#define BLOCKAGE_RANGE(B) \ + (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \ + | (B) & BLOCKAGE_MASK) + +/* Encodings of the `_unit_blockage_range' function. */ +#define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2)) +#define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1)) + +#define DONE_PRIORITY -1 +#define MAX_PRIORITY 0x7fffffff +#define TAIL_PRIORITY 0x7ffffffe +#define LAUNCH_PRIORITY 0x7f000001 +#define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0) +#define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0) + +/* Vector indexed by INSN_UID giving number of insns referring to this insn. */ +static int *insn_ref_count; +#define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)]) + +/* Vector indexed by INSN_UID giving line-number note in effect for each + insn. For line-number notes, this indicates whether the note may be + reused. */ +static rtx *line_note; +#define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)]) + +/* Vector indexed by basic block number giving the starting line-number + for each basic block. */ +static rtx *line_note_head; + +/* List of important notes we must keep around. This is a pointer to the + last element in the list. */ +static rtx note_list; + +/* Regsets telling whether a given register is live or dead before the last + scheduled insn. Must scan the instructions once before scheduling to + determine what registers are live or dead at the end of the block. */ +static regset bb_dead_regs; +static regset bb_live_regs; + +/* Regset telling whether a given register is live after the insn currently + being scheduled. Before processing an insn, this is equal to bb_live_regs + above. This is used so that we can find registers that are newly born/dead + after processing an insn. */ +static regset old_live_regs; + +/* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns + during the initial scan and reused later. If there are not exactly as + many REG_DEAD notes in the post scheduled code as there were in the + prescheduled code then we trigger an abort because this indicates a bug. */ +static rtx dead_notes; + +/* Queues, etc. */ + +/* An instruction is ready to be scheduled when all insns following it + have already been scheduled. It is important to ensure that all + insns which use its result will not be executed until its result + has been computed. An insn is maintained in one of four structures: + + (P) the "Pending" set of insns which cannot be scheduled until + their dependencies have been satisfied. + (Q) the "Queued" set of insns that can be scheduled when sufficient + time has passed. + (R) the "Ready" list of unscheduled, uncommitted insns. + (S) the "Scheduled" list of insns. + + Initially, all insns are either "Pending" or "Ready" depending on + whether their dependencies are satisfied. + + Insns move from the "Ready" list to the "Scheduled" list as they + are committed to the schedule. As this occurs, the insns in the + "Pending" list have their dependencies satisfied and move to either + the "Ready" list or the "Queued" set depending on whether + sufficient time has passed to make them ready. As time passes, + insns move from the "Queued" set to the "Ready" list. Insns may + move from the "Ready" list to the "Queued" set if they are blocked + due to a function unit conflict. + + The "Pending" list (P) are the insns in the LOG_LINKS of the unscheduled + insns, i.e., those that are ready, queued, and pending. + The "Queued" set (Q) is implemented by the variable `insn_queue'. + The "Ready" list (R) is implemented by the variables `ready' and + `n_ready'. + The "Scheduled" list (S) is the new insn chain built by this pass. + + The transition (R->S) is implemented in the scheduling loop in + `schedule_block' when the best insn to schedule is chosen. + The transition (R->Q) is implemented in `schedule_select' when an + insn is found to to have a function unit conflict with the already + committed insns. + The transitions (P->R and P->Q) are implemented in `schedule_insn' as + insns move from the ready list to the scheduled list. + The transition (Q->R) is implemented at the top of the scheduling + loop in `schedule_block' as time passes or stalls are introduced. */ + +/* Implement a circular buffer to delay instructions until sufficient + time has passed. INSN_QUEUE_SIZE is a power of two larger than + MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the + longest time an isnsn may be queued. */ +static rtx insn_queue[INSN_QUEUE_SIZE]; +static int q_ptr = 0; +static int q_size = 0; +#define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1)) +#define NEXT_Q_AFTER(X,C) (((X)+C) & (INSN_QUEUE_SIZE-1)) + +/* Vector indexed by INSN_UID giving the minimum clock tick at which + the insn becomes ready. This is used to note timing constraints for + insns in the pending list. */ +static int *insn_tick; +#define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)]) + +/* Forward declarations. */ +static void sched_analyze_2 (); +static void schedule_block (); + +/* Main entry point of this file. */ +void schedule_insns (); +#endif /* INSN_SCHEDULING */ + +#define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X))) + +/* Vector indexed by N giving the initial (unchanging) value known + for pseudo-register N. */ +static rtx *reg_known_value; + +/* Vector recording for each reg_known_value whether it is due to a + REG_EQUIV note. Future passes (viz., reload) may replace the + pseudo with the equivalent expression and so we account for the + dependences that would be introduced if that happens. */ +/* ??? This is a problem only on the Convex. The REG_EQUIV notes created in + assign_parms mention the arg pointer, and there are explicit insns in the + RTL that modify the arg pointer. Thus we must ensure that such insns don't + get scheduled across each other because that would invalidate the REG_EQUIV + notes. One could argue that the REG_EQUIV notes are wrong, but solving + the problem in the scheduler will likely give better code, so we do it + here. */ +static char *reg_known_equiv_p; + +/* Indicates number of valid entries in reg_known_value. */ +static int reg_known_value_size; + +static rtx +canon_rtx (x) + rtx x; +{ + if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER + && REGNO (x) <= reg_known_value_size) + return reg_known_value[REGNO (x)]; + else if (GET_CODE (x) == PLUS) + { + rtx x0 = canon_rtx (XEXP (x, 0)); + rtx x1 = canon_rtx (XEXP (x, 1)); + + if (x0 != XEXP (x, 0) || x1 != XEXP (x, 1)) + { + /* We can tolerate LO_SUMs being offset here; these + rtl are used for nothing other than comparisons. */ + if (GET_CODE (x0) == CONST_INT) + return plus_constant_for_output (x1, INTVAL (x0)); + else if (GET_CODE (x1) == CONST_INT) + return plus_constant_for_output (x0, INTVAL (x1)); + return gen_rtx (PLUS, GET_MODE (x), x0, x1); + } + } + return x; +} + +/* Set up all info needed to perform alias analysis on memory references. */ + +void +init_alias_analysis () +{ + int maxreg = max_reg_num (); + rtx insn; + rtx note; + rtx set; + + reg_known_value_size = maxreg; + + reg_known_value + = (rtx *) oballoc ((maxreg-FIRST_PSEUDO_REGISTER) * sizeof (rtx)) + - FIRST_PSEUDO_REGISTER; + bzero (reg_known_value+FIRST_PSEUDO_REGISTER, + (maxreg-FIRST_PSEUDO_REGISTER) * sizeof (rtx)); + + reg_known_equiv_p + = (char *) oballoc ((maxreg-FIRST_PSEUDO_REGISTER) * sizeof (char)) + - FIRST_PSEUDO_REGISTER; + bzero (reg_known_equiv_p+FIRST_PSEUDO_REGISTER, + (maxreg-FIRST_PSEUDO_REGISTER) * sizeof (char)); + + /* Fill in the entries with known constant values. */ + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + if ((set = single_set (insn)) != 0 + && GET_CODE (SET_DEST (set)) == REG + && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER + && (((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 + && reg_n_sets[REGNO (SET_DEST (set))] == 1) + || (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != 0) + && GET_CODE (XEXP (note, 0)) != EXPR_LIST) + { + int regno = REGNO (SET_DEST (set)); + reg_known_value[regno] = XEXP (note, 0); + reg_known_equiv_p[regno] = REG_NOTE_KIND (note) == REG_EQUIV; + } + + /* Fill in the remaining entries. */ + while (--maxreg >= FIRST_PSEUDO_REGISTER) + if (reg_known_value[maxreg] == 0) + reg_known_value[maxreg] = regno_reg_rtx[maxreg]; +} + +/* Return 1 if X and Y are identical-looking rtx's. + + We use the data in reg_known_value above to see if two registers with + different numbers are, in fact, equivalent. */ + +static int +rtx_equal_for_memref_p (x, y) + rtx x, y; +{ + register int i; + register int j; + register enum rtx_code code; + register char *fmt; + + if (x == 0 && y == 0) + return 1; + if (x == 0 || y == 0) + return 0; + x = canon_rtx (x); + y = canon_rtx (y); + + if (x == y) + return 1; + + code = GET_CODE (x); + /* Rtx's of different codes cannot be equal. */ + if (code != GET_CODE (y)) + return 0; + + /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. + (REG:SI x) and (REG:HI x) are NOT equivalent. */ + + if (GET_MODE (x) != GET_MODE (y)) + return 0; + + /* REG, LABEL_REF, and SYMBOL_REF can be compared nonrecursively. */ + + if (code == REG) + return REGNO (x) == REGNO (y); + if (code == LABEL_REF) + return XEXP (x, 0) == XEXP (y, 0); + if (code == SYMBOL_REF) + return XSTR (x, 0) == XSTR (y, 0); + + /* Compare the elements. If any pair of corresponding elements + fail to match, return 0 for the whole things. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + switch (fmt[i]) + { + case 'w': + if (XWINT (x, i) != XWINT (y, i)) + return 0; + break; + + case 'n': + case 'i': + if (XINT (x, i) != XINT (y, i)) + return 0; + break; + + case 'V': + case 'E': + /* Two vectors must have the same length. */ + if (XVECLEN (x, i) != XVECLEN (y, i)) + return 0; + + /* And the corresponding elements must match. */ + for (j = 0; j < XVECLEN (x, i); j++) + if (rtx_equal_for_memref_p (XVECEXP (x, i, j), XVECEXP (y, i, j)) == 0) + return 0; + break; + + case 'e': + if (rtx_equal_for_memref_p (XEXP (x, i), XEXP (y, i)) == 0) + return 0; + break; + + case 'S': + case 's': + if (strcmp (XSTR (x, i), XSTR (y, i))) + return 0; + break; + + case 'u': + /* These are just backpointers, so they don't matter. */ + break; + + case '0': + break; + + /* It is believed that rtx's at this level will never + contain anything but integers and other rtx's, + except for within LABEL_REFs and SYMBOL_REFs. */ + default: + abort (); + } + } + return 1; +} + +/* Given an rtx X, find a SYMBOL_REF or LABEL_REF within + X and return it, or return 0 if none found. */ + +static rtx +find_symbolic_term (x) + rtx x; +{ + register int i; + register enum rtx_code code; + register char *fmt; + + code = GET_CODE (x); + if (code == SYMBOL_REF || code == LABEL_REF) + return x; + if (GET_RTX_CLASS (code) == 'o') + return 0; + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + rtx t; + + if (fmt[i] == 'e') + { + t = find_symbolic_term (XEXP (x, i)); + if (t != 0) + return t; + } + else if (fmt[i] == 'E') + break; + } + return 0; +} + +/* Return nonzero if X and Y (memory addresses) could reference the + same location in memory. C is an offset accumulator. When + C is nonzero, we are testing aliases between X and Y + C. + XSIZE is the size in bytes of the X reference, + similarly YSIZE is the size in bytes for Y. + + If XSIZE or YSIZE is zero, we do not know the amount of memory being + referenced (the reference was BLKmode), so make the most pessimistic + assumptions. + + We recognize the following cases of non-conflicting memory: + + (1) addresses involving the frame pointer cannot conflict + with addresses involving static variables. + (2) static variables with different addresses cannot conflict. + + Nice to notice that varying addresses cannot conflict with fp if no + local variables had their addresses taken, but that's too hard now. */ + +/* ??? In Fortran, references to a array parameter can never conflict with + another array parameter. */ + +static int +memrefs_conflict_p (xsize, x, ysize, y, c) + rtx x, y; + int xsize, ysize; + HOST_WIDE_INT c; +{ + if (GET_CODE (x) == HIGH) + x = XEXP (x, 0); + else if (GET_CODE (x) == LO_SUM) + x = XEXP (x, 1); + else + x = canon_rtx (x); + if (GET_CODE (y) == HIGH) + y = XEXP (y, 0); + else if (GET_CODE (y) == LO_SUM) + y = XEXP (y, 1); + else + y = canon_rtx (y); + + if (rtx_equal_for_memref_p (x, y)) + return (xsize == 0 || ysize == 0 || + (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0)); + + if (y == frame_pointer_rtx || y == stack_pointer_rtx) + { + rtx t = y; + int tsize = ysize; + y = x; ysize = xsize; + x = t; xsize = tsize; + } + + if (x == frame_pointer_rtx || x == stack_pointer_rtx) + { + rtx y1; + + if (CONSTANT_P (y)) + return 0; + + if (GET_CODE (y) == PLUS + && canon_rtx (XEXP (y, 0)) == x + && (y1 = canon_rtx (XEXP (y, 1))) + && GET_CODE (y1) == CONST_INT) + { + c += INTVAL (y1); + return (xsize == 0 || ysize == 0 + || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0)); + } + + if (GET_CODE (y) == PLUS + && (y1 = canon_rtx (XEXP (y, 0))) + && CONSTANT_P (y1)) + return 0; + + return 1; + } + + if (GET_CODE (x) == PLUS) + { + /* The fact that X is canonicalized means that this + PLUS rtx is canonicalized. */ + rtx x0 = XEXP (x, 0); + rtx x1 = XEXP (x, 1); + + if (GET_CODE (y) == PLUS) + { + /* The fact that Y is canonicalized means that this + PLUS rtx is canonicalized. */ + rtx y0 = XEXP (y, 0); + rtx y1 = XEXP (y, 1); + + if (rtx_equal_for_memref_p (x1, y1)) + return memrefs_conflict_p (xsize, x0, ysize, y0, c); + if (rtx_equal_for_memref_p (x0, y0)) + return memrefs_conflict_p (xsize, x1, ysize, y1, c); + if (GET_CODE (x1) == CONST_INT) + if (GET_CODE (y1) == CONST_INT) + return memrefs_conflict_p (xsize, x0, ysize, y0, + c - INTVAL (x1) + INTVAL (y1)); + else + return memrefs_conflict_p (xsize, x0, ysize, y, c - INTVAL (x1)); + else if (GET_CODE (y1) == CONST_INT) + return memrefs_conflict_p (xsize, x, ysize, y0, c + INTVAL (y1)); + + /* Handle case where we cannot understand iteration operators, + but we notice that the base addresses are distinct objects. */ + x = find_symbolic_term (x); + if (x == 0) + return 1; + y = find_symbolic_term (y); + if (y == 0) + return 1; + return rtx_equal_for_memref_p (x, y); + } + else if (GET_CODE (x1) == CONST_INT) + return memrefs_conflict_p (xsize, x0, ysize, y, c - INTVAL (x1)); + } + else if (GET_CODE (y) == PLUS) + { + /* The fact that Y is canonicalized means that this + PLUS rtx is canonicalized. */ + rtx y0 = XEXP (y, 0); + rtx y1 = XEXP (y, 1); + + if (GET_CODE (y1) == CONST_INT) + return memrefs_conflict_p (xsize, x, ysize, y0, c + INTVAL (y1)); + else + return 1; + } + + if (GET_CODE (x) == GET_CODE (y)) + switch (GET_CODE (x)) + { + case MULT: + { + /* Handle cases where we expect the second operands to be the + same, and check only whether the first operand would conflict + or not. */ + rtx x0, y0; + rtx x1 = canon_rtx (XEXP (x, 1)); + rtx y1 = canon_rtx (XEXP (y, 1)); + if (! rtx_equal_for_memref_p (x1, y1)) + return 1; + x0 = canon_rtx (XEXP (x, 0)); + y0 = canon_rtx (XEXP (y, 0)); + if (rtx_equal_for_memref_p (x0, y0)) + return (xsize == 0 || ysize == 0 + || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0)); + + /* Can't properly adjust our sizes. */ + if (GET_CODE (x1) != CONST_INT) + return 1; + xsize /= INTVAL (x1); + ysize /= INTVAL (x1); + c /= INTVAL (x1); + return memrefs_conflict_p (xsize, x0, ysize, y0, c); + } + } + + if (CONSTANT_P (x)) + { + if (GET_CODE (x) == CONST_INT && GET_CODE (y) == CONST_INT) + { + c += (INTVAL (y) - INTVAL (x)); + return (xsize == 0 || ysize == 0 + || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0)); + } + + if (GET_CODE (x) == CONST) + { + if (GET_CODE (y) == CONST) + return memrefs_conflict_p (xsize, canon_rtx (XEXP (x, 0)), + ysize, canon_rtx (XEXP (y, 0)), c); + else + return memrefs_conflict_p (xsize, canon_rtx (XEXP (x, 0)), + ysize, y, c); + } + if (GET_CODE (y) == CONST) + return memrefs_conflict_p (xsize, x, ysize, + canon_rtx (XEXP (y, 0)), c); + + if (CONSTANT_P (y)) + return (rtx_equal_for_memref_p (x, y) + && (xsize == 0 || ysize == 0 + || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0))); + + return 1; + } + return 1; +} + +/* Functions to compute memory dependencies. + + Since we process the insns in execution order, we can build tables + to keep track of what registers are fixed (and not aliased), what registers + are varying in known ways, and what registers are varying in unknown + ways. + + If both memory references are volatile, then there must always be a + dependence between the two references, since their order can not be + changed. A volatile and non-volatile reference can be interchanged + though. + + A MEM_IN_STRUCT reference at a non-QImode varying address can never + conflict with a non-MEM_IN_STRUCT reference at a fixed address. We must + allow QImode aliasing because the ANSI C standard allows character + pointers to alias anything. We are assuming that characters are + always QImode here. */ + +/* Read dependence: X is read after read in MEM takes place. There can + only be a dependence here if both reads are volatile. */ + +int +read_dependence (mem, x) + rtx mem; + rtx x; +{ + return MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem); +} + +/* True dependence: X is read after store in MEM takes place. */ + +int +true_dependence (mem, x) + rtx mem; + rtx x; +{ + /* If X is an unchanging read, then it can't possibly conflict with any + non-unchanging store. It may conflict with an unchanging write though, + because there may be a single store to this address to initialize it. + Just fall through to the code below to resolve the case where we have + both an unchanging read and an unchanging write. This won't handle all + cases optimally, but the possible performance loss should be + negligible. */ + if (RTX_UNCHANGING_P (x) && ! RTX_UNCHANGING_P (mem)) + return 0; + + return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem)) + || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0), + SIZE_FOR_MODE (x), XEXP (x, 0), 0) + && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem) + && GET_MODE (mem) != QImode + && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x)) + && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x) + && GET_MODE (x) != QImode + && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem)))); +} + +/* Anti dependence: X is written after read in MEM takes place. */ + +int +anti_dependence (mem, x) + rtx mem; + rtx x; +{ + /* If MEM is an unchanging read, then it can't possibly conflict with + the store to X, because there is at most one store to MEM, and it must + have occured somewhere before MEM. */ + if (RTX_UNCHANGING_P (mem)) + return 0; + + return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem)) + || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0), + SIZE_FOR_MODE (x), XEXP (x, 0), 0) + && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem) + && GET_MODE (mem) != QImode + && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x)) + && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x) + && GET_MODE (x) != QImode + && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem)))); +} + +/* Output dependence: X is written after store in MEM takes place. */ + +int +output_dependence (mem, x) + rtx mem; + rtx x; +{ + return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem)) + || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0), + SIZE_FOR_MODE (x), XEXP (x, 0), 0) + && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem) + && GET_MODE (mem) != QImode + && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x)) + && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x) + && GET_MODE (x) != QImode + && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem)))); +} + +/* Helper functions for instruction scheduling. */ + +/* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the + LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type + of dependence that this link represents. */ + +void +add_dependence (insn, elem, dep_type) + rtx insn; + rtx elem; + enum reg_note dep_type; +{ + rtx link, next; + + /* Don't depend an insn on itself. */ + if (insn == elem) + return; + + /* If elem is part of a sequence that must be scheduled together, then + make the dependence point to the last insn of the sequence. + When HAVE_cc0, it is possible for NOTEs to exist between users and + setters of the condition codes, so we must skip past notes here. + Otherwise, NOTEs are impossible here. */ + + next = NEXT_INSN (elem); + +#ifdef HAVE_cc0 + while (next && GET_CODE (next) == NOTE) + next = NEXT_INSN (next); +#endif + + if (next && SCHED_GROUP_P (next)) + { + /* Notes will never intervene here though, so don't bother checking + for them. */ + /* We must reject CODE_LABELs, so that we don't get confused by one + that has LABEL_PRESERVE_P set, which is represented by the same + bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be + SCHED_GROUP_P. */ + while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next)) + && GET_CODE (NEXT_INSN (next)) != CODE_LABEL) + next = NEXT_INSN (next); + + /* Again, don't depend an insn on itself. */ + if (insn == next) + return; + + /* Make the dependence to NEXT, the last insn of the group, instead + of the original ELEM. */ + elem = next; + } + + /* Check that we don't already have this dependence. */ + for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) + if (XEXP (link, 0) == elem) + { + /* If this is a more restrictive type of dependence than the existing + one, then change the existing dependence to this type. */ + if ((int) dep_type < (int) REG_NOTE_KIND (link)) + PUT_REG_NOTE_KIND (link, dep_type); + return; + } + /* Might want to check one level of transitivity to save conses. */ + + link = rtx_alloc (INSN_LIST); + /* Insn dependency, not data dependency. */ + PUT_REG_NOTE_KIND (link, dep_type); + XEXP (link, 0) = elem; + XEXP (link, 1) = LOG_LINKS (insn); + LOG_LINKS (insn) = link; +} + +/* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS + of INSN. Abort if not found. */ +void +remove_dependence (insn, elem) + rtx insn; + rtx elem; +{ + rtx prev, link; + int found = 0; + + for (prev = 0, link = LOG_LINKS (insn); link; + prev = link, link = XEXP (link, 1)) + { + if (XEXP (link, 0) == elem) + { + if (prev) + XEXP (prev, 1) = XEXP (link, 1); + else + LOG_LINKS (insn) = XEXP (link, 1); + found = 1; + } + } + + if (! found) + abort (); + return; +} + +#ifndef INSN_SCHEDULING +void schedule_insns () {} +#else +#ifndef __GNUC__ +#define __inline +#endif + +/* Computation of memory dependencies. */ + +/* The *_insns and *_mems are paired lists. Each pending memory operation + will have a pointer to the MEM rtx on one list and a pointer to the + containing insn on the other list in the same place in the list. */ + +/* We can't use add_dependence like the old code did, because a single insn + may have multiple memory accesses, and hence needs to be on the list + once for each memory access. Add_dependence won't let you add an insn + to a list more than once. */ + +/* An INSN_LIST containing all insns with pending read operations. */ +static rtx pending_read_insns; + +/* An EXPR_LIST containing all MEM rtx's which are pending reads. */ +static rtx pending_read_mems; + +/* An INSN_LIST containing all insns with pending write operations. */ +static rtx pending_write_insns; + +/* An EXPR_LIST containing all MEM rtx's which are pending writes. */ +static rtx pending_write_mems; + +/* Indicates the combined length of the two pending lists. We must prevent + these lists from ever growing too large since the number of dependencies + produced is at least O(N*N), and execution time is at least O(4*N*N), as + a function of the length of these pending lists. */ + +static int pending_lists_length; + +/* An INSN_LIST containing all INSN_LISTs allocated but currently unused. */ + +static rtx unused_insn_list; + +/* An EXPR_LIST containing all EXPR_LISTs allocated but currently unused. */ + +static rtx unused_expr_list; + +/* The last insn upon which all memory references must depend. + This is an insn which flushed the pending lists, creating a dependency + between it and all previously pending memory references. This creates + a barrier (or a checkpoint) which no memory reference is allowed to cross. + + This includes all non constant CALL_INSNs. When we do interprocedural + alias analysis, this restriction can be relaxed. + This may also be an INSN that writes memory if the pending lists grow + too large. */ + +static rtx last_pending_memory_flush; + +/* The last function call we have seen. All hard regs, and, of course, + the last function call, must depend on this. */ + +static rtx last_function_call; + +/* The LOG_LINKS field of this is a list of insns which use a pseudo register + that does not already cross a call. We create dependencies between each + of those insn and the next call insn, to ensure that they won't cross a call + after scheduling is done. */ + +static rtx sched_before_next_call; + +/* Pointer to the last instruction scheduled. Used by rank_for_schedule, + so that insns independent of the last scheduled insn will be preferred + over dependent instructions. */ + +static rtx last_scheduled_insn; + +/* Process an insn's memory dependencies. There are four kinds of + dependencies: + + (0) read dependence: read follows read + (1) true dependence: read follows write + (2) anti dependence: write follows read + (3) output dependence: write follows write + + We are careful to build only dependencies which actually exist, and + use transitivity to avoid building too many links. */ + +/* Return the INSN_LIST containing INSN in LIST, or NULL + if LIST does not contain INSN. */ + +__inline static rtx +find_insn_list (insn, list) + rtx insn; + rtx list; +{ + while (list) + { + if (XEXP (list, 0) == insn) + return list; + list = XEXP (list, 1); + } + return 0; +} + +/* Compute the function units used by INSN. This caches the value + returned by function_units_used. A function unit is encoded as the + unit number if the value is non-negative and the compliment of a + mask if the value is negative. A function unit index is the + non-negative encoding. */ + +__inline static int +insn_unit (insn) + rtx insn; +{ + register int unit = INSN_UNIT (insn); + + if (unit == 0) + { + recog_memoized (insn); + + /* A USE insn, or something else we don't need to understand. + We can't pass these directly to function_units_used because it will + trigger a fatal error for unrecognizable insns. */ + if (INSN_CODE (insn) < 0) + unit = -1; + else + { + unit = function_units_used (insn); + /* Increment non-negative values so we can cache zero. */ + if (unit >= 0) unit++; + } + /* We only cache 16 bits of the result, so if the value is out of + range, don't cache it. */ + if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT + || unit >= 0 + || (~unit & ((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0) + INSN_UNIT (insn) = unit; + } + return (unit > 0 ? unit - 1 : unit); +} + +/* Compute the blockage range for executing INSN on UNIT. This caches + the value returned by the blockage_range_function for the unit. + These values are encoded in an int where the upper half gives the + minimum value and the lower half gives the maximum value. */ + +__inline static unsigned int +blockage_range (unit, insn) + int unit; + rtx insn; +{ + unsigned int blockage = INSN_BLOCKAGE (insn); + unsigned int range; + + if (UNIT_BLOCKED (blockage) != unit + 1) + { + range = function_units[unit].blockage_range_function (insn); + /* We only cache the blockage range for one unit and then only if + the values fit. */ + if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS) + INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range); + } + else + range = BLOCKAGE_RANGE (blockage); + + return range; +} + +/* A vector indexed by function unit instance giving the last insn to use + the unit. The value of the function unit instance index for unit U + instance I is (U + I * FUNCTION_UNITS_SIZE). */ +static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; + +/* A vector indexed by function unit instance giving the minimum time when + the unit will unblock based on the maximum blockage cost. */ +static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; + +/* A vector indexed by function unit number giving the number of insns + that remain to use the unit. */ +static int unit_n_insns[FUNCTION_UNITS_SIZE]; + +/* Reset the function unit state to the null state. */ + +static void +clear_units () +{ + int unit; + + bzero (unit_last_insn, sizeof (unit_last_insn)); + bzero (unit_tick, sizeof (unit_tick)); + bzero (unit_n_insns, sizeof (unit_n_insns)); +} + +/* Record an insn as one that will use the units encoded by UNIT. */ + +__inline static void +prepare_unit (unit) + int unit; +{ + int i; + + if (unit >= 0) + unit_n_insns[unit]++; + else + for (i = 0, unit = ~unit; unit; i++, unit >>= 1) + if ((unit & 1) != 0) + prepare_unit (i); +} + +/* Return the actual hazard cost of executing INSN on the unit UNIT, + instance INSTANCE at time CLOCK if the previous actual hazard cost + was COST. */ + +__inline static int +actual_hazard_this_instance (unit, instance, insn, clock, cost) + int unit, instance, clock, cost; + rtx insn; +{ + int i; + int tick = unit_tick[instance]; + + if (tick - clock > cost) + { + /* The scheduler is operating in reverse, so INSN is the executing + insn and the unit's last insn is the candidate insn. We want a + more exact measure of the blockage if we execute INSN at CLOCK + given when we committed the execution of the unit's last insn. + + The blockage value is given by either the unit's max blockage + constant, blockage range function, or blockage function. Use + the most exact form for the given unit. */ + + if (function_units[unit].blockage_range_function) + { + if (function_units[unit].blockage_function) + tick += (function_units[unit].blockage_function + (insn, unit_last_insn[instance]) + - function_units[unit].max_blockage); + else + tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn)) + - function_units[unit].max_blockage); + } + if (tick - clock > cost) + cost = tick - clock; + } + return cost; +} + +/* Record INSN as having begun execution on the units encoded by UNIT at + time CLOCK. */ + +__inline static void +schedule_unit (unit, insn, clock) + int unit, clock; + rtx insn; +{ + int i; + + if (unit >= 0) + { + int instance = unit; +#if MAX_MULTIPLICITY > 1 + /* Find the first free instance of the function unit and use that + one. We assume that one is free. */ + for (i = function_units[unit].multiplicity - 1; i > 0; i--) + { + if (! actual_hazard_this_instance (unit, instance, insn, clock, 0)) + break; + instance += FUNCTION_UNITS_SIZE; + } +#endif + unit_last_insn[instance] = insn; + unit_tick[instance] = (clock + function_units[unit].max_blockage); + } + else + for (i = 0, unit = ~unit; unit; i++, unit >>= 1) + if ((unit & 1) != 0) + schedule_unit (i, insn, clock); +} + +/* Return the actual hazard cost of executing INSN on the units encoded by + UNIT at time CLOCK if the previous actual hazard cost was COST. */ + +__inline static int +actual_hazard (unit, insn, clock, cost) + int unit, clock, cost; + rtx insn; +{ + int i; + + if (unit >= 0) + { + /* Find the instance of the function unit with the minimum hazard. */ + int instance = unit; + int best = instance; + int best_cost = actual_hazard_this_instance (unit, instance, insn, + clock, cost); + int this_cost; + +#if MAX_MULTIPLICITY > 1 + if (best_cost > cost) + { + for (i = function_units[unit].multiplicity - 1; i > 0; i--) + { + instance += FUNCTION_UNITS_SIZE; + this_cost = actual_hazard_this_instance (unit, instance, insn, + clock, cost); + if (this_cost < best_cost) + { + best = instance; + best_cost = this_cost; + if (this_cost <= cost) + break; + } + } + } +#endif + cost = MAX (cost, best_cost); + } + else + for (i = 0, unit = ~unit; unit; i++, unit >>= 1) + if ((unit & 1) != 0) + cost = actual_hazard (i, insn, clock, cost); + + return cost; +} + +/* Return the potential hazard cost of executing an instruction on the + units encoded by UNIT if the previous potential hazard cost was COST. + An insn with a large blockage time is chosen in preference to one + with a smaller time; an insn that uses a unit that is more likely + to be used is chosen in preference to one with a unit that is less + used. We are trying to minimize a subsequent actual hazard. */ + +__inline static int +potential_hazard (unit, insn, cost) + int unit, cost; + rtx insn; +{ + int i, ncost; + unsigned int minb, maxb; + + if (unit >= 0) + { + minb = maxb = function_units[unit].max_blockage; + if (maxb > 1) + { + if (function_units[unit].blockage_range_function) + { + maxb = minb = blockage_range (unit, insn); + maxb = MAX_BLOCKAGE_COST (maxb); + minb = MIN_BLOCKAGE_COST (minb); + } + + if (maxb > 1) + { + /* Make the number of instructions left dominate. Make the + minimum delay dominate the maximum delay. If all these + are the same, use the unit number to add an arbitrary + ordering. Other terms can be added. */ + ncost = minb * 0x40 + maxb; + ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit; + if (ncost > cost) + cost = ncost; + } + } + } + else + for (i = 0, unit = ~unit; unit; i++, unit >>= 1) + if ((unit & 1) != 0) + cost = potential_hazard (i, insn, cost); + + return cost; +} + +/* Compute cost of executing INSN given the dependence LINK on the insn USED. + This is the number of virtual cycles taken between instruction issue and + instruction results. */ + +__inline static int +insn_cost (insn, link, used) + rtx insn, link, used; +{ + register int cost = INSN_COST (insn); + + if (cost == 0) + { + recog_memoized (insn); + + /* A USE insn, or something else we don't need to understand. + We can't pass these directly to result_ready_cost because it will + trigger a fatal error for unrecognizable insns. */ + if (INSN_CODE (insn) < 0) + { + INSN_COST (insn) = 1; + return 1; + } + else + { + cost = result_ready_cost (insn); + + if (cost < 1) + cost = 1; + + INSN_COST (insn) = cost; + } + } + + /* A USE insn should never require the value used to be computed. This + allows the computation of a function's result and parameter values to + overlap the return and call. */ + recog_memoized (used); + if (INSN_CODE (used) < 0) + LINK_COST_FREE (link) = 1; + + /* If some dependencies vary the cost, compute the adjustment. Most + commonly, the adjustment is complete: either the cost is ignored + (in the case of an output- or anti-dependence), or the cost is + unchanged. These values are cached in the link as LINK_COST_FREE + and LINK_COST_ZERO. */ + + if (LINK_COST_FREE (link)) + cost = 1; +#ifdef ADJUST_COST + else if (! LINK_COST_ZERO (link)) + { + int ncost = cost; + + ADJUST_COST (used, link, insn, ncost); + if (ncost <= 1) + LINK_COST_FREE (link) = ncost = 1; + if (cost == ncost) + LINK_COST_ZERO (link) = 1; + cost = ncost; + } +#endif + return cost; +} + +/* Compute the priority number for INSN. */ + +static int +priority (insn) + rtx insn; +{ + if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + int prev_priority; + int max_priority; + int this_priority = INSN_PRIORITY (insn); + rtx prev; + + if (this_priority > 0) + return this_priority; + + max_priority = 1; + + /* Nonzero if these insns must be scheduled together. */ + if (SCHED_GROUP_P (insn)) + { + prev = insn; + while (SCHED_GROUP_P (prev)) + { + prev = PREV_INSN (prev); + INSN_REF_COUNT (prev) += 1; + } + } + + for (prev = LOG_LINKS (insn); prev; prev = XEXP (prev, 1)) + { + rtx x = XEXP (prev, 0); + + /* A dependence pointing to a note is always obsolete, because + sched_analyze_insn will have created any necessary new dependences + which replace it. Notes can be created when instructions are + deleted by insn splitting, or by register allocation. */ + if (GET_CODE (x) == NOTE) + { + remove_dependence (insn, x); + continue; + } + + /* Clear the link cost adjustment bits. */ + LINK_COST_FREE (prev) = 0; +#ifdef ADJUST_COST + LINK_COST_ZERO (prev) = 0; +#endif + + /* This priority calculation was chosen because it results in the + least instruction movement, and does not hurt the performance + of the resulting code compared to the old algorithm. + This makes the sched algorithm more stable, which results + in better code, because there is less register pressure, + cross jumping is more likely to work, and debugging is easier. + + When all instructions have a latency of 1, there is no need to + move any instructions. Subtracting one here ensures that in such + cases all instructions will end up with a priority of one, and + hence no scheduling will be done. + + The original code did not subtract the one, and added the + insn_cost of the current instruction to its priority (e.g. + move the insn_cost call down to the end). */ + + if (REG_NOTE_KIND (prev) == 0) + /* Data dependence. */ + prev_priority = priority (x) + insn_cost (x, prev, insn) - 1; + else + /* Anti or output dependence. Don't add the latency of this + insn's result, because it isn't being used. */ + prev_priority = priority (x); + + if (prev_priority > max_priority) + max_priority = prev_priority; + INSN_REF_COUNT (x) += 1; + } + + prepare_unit (insn_unit (insn)); + INSN_PRIORITY (insn) = max_priority; + return INSN_PRIORITY (insn); + } + return 0; +} + +/* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add + them to the unused_*_list variables, so that they can be reused. */ + +static void +free_pending_lists () +{ + register rtx link, prev_link; + + if (pending_read_insns) + { + prev_link = pending_read_insns; + link = XEXP (prev_link, 1); + + while (link) + { + prev_link = link; + link = XEXP (link, 1); + } + + XEXP (prev_link, 1) = unused_insn_list; + unused_insn_list = pending_read_insns; + pending_read_insns = 0; + } + + if (pending_write_insns) + { + prev_link = pending_write_insns; + link = XEXP (prev_link, 1); + + while (link) + { + prev_link = link; + link = XEXP (link, 1); + } + + XEXP (prev_link, 1) = unused_insn_list; + unused_insn_list = pending_write_insns; + pending_write_insns = 0; + } + + if (pending_read_mems) + { + prev_link = pending_read_mems; + link = XEXP (prev_link, 1); + + while (link) + { + prev_link = link; + link = XEXP (link, 1); + } + + XEXP (prev_link, 1) = unused_expr_list; + unused_expr_list = pending_read_mems; + pending_read_mems = 0; + } + + if (pending_write_mems) + { + prev_link = pending_write_mems; + link = XEXP (prev_link, 1); + + while (link) + { + prev_link = link; + link = XEXP (link, 1); + } + + XEXP (prev_link, 1) = unused_expr_list; + unused_expr_list = pending_write_mems; + pending_write_mems = 0; + } +} + +/* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST. + The MEM is a memory reference contained within INSN, which we are saving + so that we can do memory aliasing on it. */ + +static void +add_insn_mem_dependence (insn_list, mem_list, insn, mem) + rtx *insn_list, *mem_list, insn, mem; +{ + register rtx link; + + if (unused_insn_list) + { + link = unused_insn_list; + unused_insn_list = XEXP (link, 1); + } + else + link = rtx_alloc (INSN_LIST); + XEXP (link, 0) = insn; + XEXP (link, 1) = *insn_list; + *insn_list = link; + + if (unused_expr_list) + { + link = unused_expr_list; + unused_expr_list = XEXP (link, 1); + } + else + link = rtx_alloc (EXPR_LIST); + XEXP (link, 0) = mem; + XEXP (link, 1) = *mem_list; + *mem_list = link; + + pending_lists_length++; +} + +/* Make a dependency between every memory reference on the pending lists + and INSN, thus flushing the pending lists. */ + +static void +flush_pending_lists (insn) + rtx insn; +{ + rtx link; + + while (pending_read_insns) + { + add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI); + + link = pending_read_insns; + pending_read_insns = XEXP (pending_read_insns, 1); + XEXP (link, 1) = unused_insn_list; + unused_insn_list = link; + + link = pending_read_mems; + pending_read_mems = XEXP (pending_read_mems, 1); + XEXP (link, 1) = unused_expr_list; + unused_expr_list = link; + } + while (pending_write_insns) + { + add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI); + + link = pending_write_insns; + pending_write_insns = XEXP (pending_write_insns, 1); + XEXP (link, 1) = unused_insn_list; + unused_insn_list = link; + + link = pending_write_mems; + pending_write_mems = XEXP (pending_write_mems, 1); + XEXP (link, 1) = unused_expr_list; + unused_expr_list = link; + } + pending_lists_length = 0; + + if (last_pending_memory_flush) + add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI); + + last_pending_memory_flush = insn; +} + +/* Analyze a single SET or CLOBBER rtx, X, creating all dependencies generated + by the write to the destination of X, and reads of everything mentioned. */ + +static void +sched_analyze_1 (x, insn) + rtx x; + rtx insn; +{ + register int regno; + register rtx dest = SET_DEST (x); + + if (dest == 0) + return; + + while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG + || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) + { + if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) + { + /* The second and third arguments are values read by this insn. */ + sched_analyze_2 (XEXP (dest, 1), insn); + sched_analyze_2 (XEXP (dest, 2), insn); + } + dest = SUBREG_REG (dest); + } + + if (GET_CODE (dest) == REG) + { + register int offset, bit, i; + + regno = REGNO (dest); + + /* A hard reg in a wide mode may really be multiple registers. + If so, mark all of them just like the first. */ + if (regno < FIRST_PSEUDO_REGISTER) + { + i = HARD_REGNO_NREGS (regno, GET_MODE (dest)); + while (--i >= 0) + { + rtx u; + + for (u = reg_last_uses[regno+i]; u; u = XEXP (u, 1)) + add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); + reg_last_uses[regno + i] = 0; + if (reg_last_sets[regno + i]) + add_dependence (insn, reg_last_sets[regno + i], + REG_DEP_OUTPUT); + reg_last_sets[regno + i] = insn; + if ((call_used_regs[i] || global_regs[i]) + && last_function_call) + /* Function calls clobber all call_used regs. */ + add_dependence (insn, last_function_call, REG_DEP_ANTI); + } + } + else + { + rtx u; + + for (u = reg_last_uses[regno]; u; u = XEXP (u, 1)) + add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); + reg_last_uses[regno] = 0; + if (reg_last_sets[regno]) + add_dependence (insn, reg_last_sets[regno], REG_DEP_OUTPUT); + reg_last_sets[regno] = insn; + + /* Pseudos that are REG_EQUIV to something may be replaced + by that during reloading. We need only add dependencies for + the address in the REG_EQUIV note. */ + if (! reload_completed + && reg_known_equiv_p[regno] + && GET_CODE (reg_known_value[regno]) == MEM) + sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); + + /* Don't let it cross a call after scheduling if it doesn't + already cross one. */ + if (reg_n_calls_crossed[regno] == 0 && last_function_call) + add_dependence (insn, last_function_call, REG_DEP_ANTI); + } + } + else if (GET_CODE (dest) == MEM) + { + /* Writing memory. */ + + if (pending_lists_length > 32) + { + /* Flush all pending reads and writes to prevent the pending lists + from getting any larger. Insn scheduling runs too slowly when + these lists get long. The number 32 was chosen because it + seems like a reasonable number. When compiling GCC with itself, + this flush occurs 8 times for sparc, and 10 times for m88k using + the number 32. */ + flush_pending_lists (insn); + } + else + { + rtx pending, pending_mem; + + pending = pending_read_insns; + pending_mem = pending_read_mems; + while (pending) + { + /* If a dependency already exists, don't create a new one. */ + if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn))) + if (anti_dependence (XEXP (pending_mem, 0), dest)) + add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); + + pending = XEXP (pending, 1); + pending_mem = XEXP (pending_mem, 1); + } + + pending = pending_write_insns; + pending_mem = pending_write_mems; + while (pending) + { + /* If a dependency already exists, don't create a new one. */ + if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn))) + if (output_dependence (XEXP (pending_mem, 0), dest)) + add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT); + + pending = XEXP (pending, 1); + pending_mem = XEXP (pending_mem, 1); + } + + if (last_pending_memory_flush) + add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI); + + add_insn_mem_dependence (&pending_write_insns, &pending_write_mems, + insn, dest); + } + sched_analyze_2 (XEXP (dest, 0), insn); + } + + /* Analyze reads. */ + if (GET_CODE (x) == SET) + sched_analyze_2 (SET_SRC (x), insn); +} + +/* Analyze the uses of memory and registers in rtx X in INSN. */ + +static void +sched_analyze_2 (x, insn) + rtx x; + rtx insn; +{ + register int i; + register int j; + register enum rtx_code code; + register char *fmt; + + if (x == 0) + return; + + code = GET_CODE (x); + + switch (code) + { + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CONST: + case LABEL_REF: + /* Ignore constants. Note that we must handle CONST_DOUBLE here + because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but + this does not mean that this insn is using cc0. */ + return; + +#ifdef HAVE_cc0 + case CC0: + { + rtx link, prev; + + /* There may be a note before this insn now, but all notes will + be removed before we actually try to schedule the insns, so + it won't cause a problem later. We must avoid it here though. */ + + /* User of CC0 depends on immediately preceding insn. */ + SCHED_GROUP_P (insn) = 1; + + /* Make a copy of all dependencies on the immediately previous insn, + and add to this insn. This is so that all the dependencies will + apply to the group. Remove an explicit dependence on this insn + as SCHED_GROUP_P now represents it. */ + + prev = PREV_INSN (insn); + while (GET_CODE (prev) == NOTE) + prev = PREV_INSN (prev); + + if (find_insn_list (prev, LOG_LINKS (insn))) + remove_dependence (insn, prev); + + for (link = LOG_LINKS (prev); link; link = XEXP (link, 1)) + add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); + + return; + } +#endif + + case REG: + { + int regno = REGNO (x); + if (regno < FIRST_PSEUDO_REGISTER) + { + int i; + + i = HARD_REGNO_NREGS (regno, GET_MODE (x)); + while (--i >= 0) + { + reg_last_uses[regno + i] + = gen_rtx (INSN_LIST, VOIDmode, + insn, reg_last_uses[regno + i]); + if (reg_last_sets[regno + i]) + add_dependence (insn, reg_last_sets[regno + i], 0); + if ((call_used_regs[regno + i] || global_regs[regno + i]) + && last_function_call) + /* Function calls clobber all call_used regs. */ + add_dependence (insn, last_function_call, REG_DEP_ANTI); + } + } + else + { + reg_last_uses[regno] + = gen_rtx (INSN_LIST, VOIDmode, insn, reg_last_uses[regno]); + if (reg_last_sets[regno]) + add_dependence (insn, reg_last_sets[regno], 0); + + /* Pseudos that are REG_EQUIV to something may be replaced + by that during reloading. We need only add dependencies for + the address in the REG_EQUIV note. */ + if (! reload_completed + && reg_known_equiv_p[regno] + && GET_CODE (reg_known_value[regno]) == MEM) + sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); + + /* If the register does not already cross any calls, then add this + insn to the sched_before_next_call list so that it will still + not cross calls after scheduling. */ + if (reg_n_calls_crossed[regno] == 0) + add_dependence (sched_before_next_call, insn, REG_DEP_ANTI); + } + return; + } + + case MEM: + { + /* Reading memory. */ + + rtx pending, pending_mem; + + pending = pending_read_insns; + pending_mem = pending_read_mems; + while (pending) + { + /* If a dependency already exists, don't create a new one. */ + if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn))) + if (read_dependence (XEXP (pending_mem, 0), x)) + add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); + + pending = XEXP (pending, 1); + pending_mem = XEXP (pending_mem, 1); + } + + pending = pending_write_insns; + pending_mem = pending_write_mems; + while (pending) + { + /* If a dependency already exists, don't create a new one. */ + if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn))) + if (true_dependence (XEXP (pending_mem, 0), x)) + add_dependence (insn, XEXP (pending, 0), 0); + + pending = XEXP (pending, 1); + pending_mem = XEXP (pending_mem, 1); + } + if (last_pending_memory_flush) + add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI); + + /* Always add these dependencies to pending_reads, since + this insn may be followed by a write. */ + add_insn_mem_dependence (&pending_read_insns, &pending_read_mems, + insn, x); + + /* Take advantage of tail recursion here. */ + sched_analyze_2 (XEXP (x, 0), insn); + return; + } + + case ASM_OPERANDS: + case ASM_INPUT: + case UNSPEC_VOLATILE: + case TRAP_IF: + { + rtx u; + + /* Traditional and volatile asm instructions must be considered to use + and clobber all hard registers and all of memory. So must + TRAP_IF and UNSPEC_VOLATILE operations. */ + if (code != ASM_OPERANDS || MEM_VOLATILE_P (x)) + { + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) + add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); + reg_last_uses[i] = 0; + if (reg_last_sets[i]) + add_dependence (insn, reg_last_sets[i], 0); + reg_last_sets[i] = insn; + } + + flush_pending_lists (insn); + } + + /* For all ASM_OPERANDS, we must traverse the vector of input operands. + We can not just fall through here since then we would be confused + by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate + traditional asms unlike their normal usage. */ + + if (code == ASM_OPERANDS) + { + for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++) + sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn); + return; + } + break; + } + + case PRE_DEC: + case POST_DEC: + case PRE_INC: + case POST_INC: + /* These both read and modify the result. We must handle them as writes + to get proper dependencies for following instructions. We must handle + them as reads to get proper dependencies from this to previous + instructions. Thus we need to pass them to both sched_analyze_1 + and sched_analyze_2. We must call sched_analyze_2 first in order + to get the proper antecedent for the read. */ + sched_analyze_2 (XEXP (x, 0), insn); + sched_analyze_1 (x, insn); + return; + } + + /* Other cases: walk the insn. */ + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + sched_analyze_2 (XEXP (x, i), insn); + else if (fmt[i] == 'E') + for (j = 0; j < XVECLEN (x, i); j++) + sched_analyze_2 (XVECEXP (x, i, j), insn); + } +} + +/* Analyze an INSN with pattern X to find all dependencies. */ + +static void +sched_analyze_insn (x, insn) + rtx x, insn; +{ + register RTX_CODE code = GET_CODE (x); + rtx link; + + if (code == SET || code == CLOBBER) + sched_analyze_1 (x, insn); + else if (code == PARALLEL) + { + register int i; + for (i = XVECLEN (x, 0) - 1; i >= 0; i--) + { + code = GET_CODE (XVECEXP (x, 0, i)); + if (code == SET || code == CLOBBER) + sched_analyze_1 (XVECEXP (x, 0, i), insn); + else + sched_analyze_2 (XVECEXP (x, 0, i), insn); + } + } + else + sched_analyze_2 (x, insn); + + /* Handle function calls. */ + if (GET_CODE (insn) == CALL_INSN) + { + rtx dep_insn; + rtx prev_dep_insn; + + /* When scheduling instructions, we make sure calls don't lose their + accompanying USE insns by depending them one on another in order. */ + + prev_dep_insn = insn; + dep_insn = PREV_INSN (insn); + while (GET_CODE (dep_insn) == INSN + && GET_CODE (PATTERN (dep_insn)) == USE) + { + SCHED_GROUP_P (prev_dep_insn) = 1; + + /* Make a copy of all dependencies on dep_insn, and add to insn. + This is so that all of the dependencies will apply to the + group. */ + + for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1)) + add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); + + prev_dep_insn = dep_insn; + dep_insn = PREV_INSN (dep_insn); + } + } +} + +/* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS + for every dependency. */ + +static int +sched_analyze (head, tail) + rtx head, tail; +{ + register rtx insn; + register int n_insns = 0; + register rtx u; + register int luid = 0; + + for (insn = head; ; insn = NEXT_INSN (insn)) + { + INSN_LUID (insn) = luid++; + + if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) + { + sched_analyze_insn (PATTERN (insn), insn); + n_insns += 1; + } + else if (GET_CODE (insn) == CALL_INSN) + { + rtx dest = 0; + rtx x; + register int i; + + /* Any instruction using a hard register which may get clobbered + by a call needs to be marked as dependent on this call. + This prevents a use of a hard return reg from being moved + past a void call (i.e. it does not explicitly set the hard + return reg). */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (call_used_regs[i] || global_regs[i]) + { + for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) + add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); + reg_last_uses[i] = 0; + if (reg_last_sets[i]) + add_dependence (insn, reg_last_sets[i], REG_DEP_ANTI); + reg_last_sets[i] = insn; + /* Insn, being a CALL_INSN, magically depends on + `last_function_call' already. */ + } + + /* For each insn which shouldn't cross a call, add a dependence + between that insn and this call insn. */ + x = LOG_LINKS (sched_before_next_call); + while (x) + { + add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI); + x = XEXP (x, 1); + } + LOG_LINKS (sched_before_next_call) = 0; + + sched_analyze_insn (PATTERN (insn), insn); + + /* We don't need to flush memory for a function call which does + not involve memory. */ + if (! CONST_CALL_P (insn)) + { + /* In the absence of interprocedural alias analysis, + we must flush all pending reads and writes, and + start new dependencies starting from here. */ + flush_pending_lists (insn); + } + + /* Depend this function call (actually, the user of this + function call) on all hard register clobberage. */ + last_function_call = insn; + n_insns += 1; + } + + if (insn == tail) + return n_insns; + } +} + +/* Called when we see a set of a register. If death is true, then we are + scanning backwards. Mark that register as unborn. If nobody says + otherwise, that is how things will remain. If death is false, then we + are scanning forwards. Mark that register as being born. */ + +static void +sched_note_set (b, x, death) + int b; + rtx x; + int death; +{ + register int regno, j; + register rtx reg = SET_DEST (x); + int subreg_p = 0; + + if (reg == 0) + return; + + while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == STRICT_LOW_PART + || GET_CODE (reg) == SIGN_EXTRACT || GET_CODE (reg) == ZERO_EXTRACT) + { + /* Must treat modification of just one hardware register of a multi-reg + value or just a byte field of a register exactly the same way that + mark_set_1 in flow.c does, i.e. anything except a paradoxical subreg + does not kill the entire register. */ + if (GET_CODE (reg) != SUBREG + || REG_SIZE (SUBREG_REG (reg)) > REG_SIZE (reg)) + subreg_p = 1; + + reg = SUBREG_REG (reg); + } + + if (GET_CODE (reg) != REG) + return; + + /* Global registers are always live, so the code below does not apply + to them. */ + + regno = REGNO (reg); + if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno]) + { + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + + if (death) + { + /* If we only set part of the register, then this set does not + kill it. */ + if (subreg_p) + return; + + /* Try killing this register. */ + if (regno < FIRST_PSEUDO_REGISTER) + { + int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); + while (--j >= 0) + { + offset = (regno + j) / REGSET_ELT_BITS; + bit = (REGSET_ELT_TYPE) 1 << ((regno + j) % REGSET_ELT_BITS); + + bb_live_regs[offset] &= ~bit; + bb_dead_regs[offset] |= bit; + } + } + else + { + bb_live_regs[offset] &= ~bit; + bb_dead_regs[offset] |= bit; + } + } + else + { + /* Make the register live again. */ + if (regno < FIRST_PSEUDO_REGISTER) + { + int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); + while (--j >= 0) + { + offset = (regno + j) / REGSET_ELT_BITS; + bit = (REGSET_ELT_TYPE) 1 << ((regno + j) % REGSET_ELT_BITS); + + bb_live_regs[offset] |= bit; + bb_dead_regs[offset] &= ~bit; + } + } + else + { + bb_live_regs[offset] |= bit; + bb_dead_regs[offset] &= ~bit; + } + } + } +} + +/* Macros and functions for keeping the priority queue sorted, and + dealing with queueing and unqueueing of instructions. */ + +#define SCHED_SORT(READY, NEW_READY, OLD_READY) \ + do { if ((NEW_READY) - (OLD_READY) == 1) \ + swap_sort (READY, NEW_READY); \ + else if ((NEW_READY) - (OLD_READY) > 1) \ + qsort (READY, NEW_READY, sizeof (rtx), rank_for_schedule); } \ + while (0) + +/* Returns a positive value if y is preferred; returns a negative value if + x is preferred. Should never return 0, since that will make the sort + unstable. */ + +static int +rank_for_schedule (x, y) + rtx *x, *y; +{ + rtx tmp = *y; + rtx tmp2 = *x; + rtx link; + int tmp_class, tmp2_class; + int value; + + /* Choose the instruction with the highest priority, if different. */ + if (value = INSN_PRIORITY (tmp) - INSN_PRIORITY (tmp2)) + return value; + + if (last_scheduled_insn) + { + /* Classify the instructions into three classes: + 1) Data dependent on last schedule insn. + 2) Anti/Output dependent on last scheduled insn. + 3) Independent of last scheduled insn, or has latency of one. + Choose the insn from the highest numbered class if different. */ + link = find_insn_list (tmp, LOG_LINKS (last_scheduled_insn)); + if (link == 0 || insn_cost (tmp, link, last_scheduled_insn) == 1) + tmp_class = 3; + else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ + tmp_class = 1; + else + tmp_class = 2; + + link = find_insn_list (tmp2, LOG_LINKS (last_scheduled_insn)); + if (link == 0 || insn_cost (tmp2, link, last_scheduled_insn) == 1) + tmp2_class = 3; + else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ + tmp2_class = 1; + else + tmp2_class = 2; + + if (value = tmp_class - tmp2_class) + return value; + } + + /* If insns are equally good, sort by INSN_LUID (original insn order), + so that we make the sort stable. This minimizes instruction movement, + thus minimizing sched's effect on debugging and cross-jumping. */ + return INSN_LUID (tmp) - INSN_LUID (tmp2); +} + +/* Resort the array A in which only element at index N may be out of order. */ + +__inline static void +swap_sort (a, n) + rtx *a; + int n; +{ + rtx insn = a[n-1]; + int i = n-2; + + while (i >= 0 && rank_for_schedule (a+i, &insn) >= 0) + { + a[i+1] = a[i]; + i -= 1; + } + a[i+1] = insn; +} + +static int max_priority; + +/* Add INSN to the insn queue so that it fires at least N_CYCLES + before the currently executing insn. */ + +__inline static void +queue_insn (insn, n_cycles) + rtx insn; + int n_cycles; +{ + int next_q = NEXT_Q_AFTER (q_ptr, n_cycles); + NEXT_INSN (insn) = insn_queue[next_q]; + insn_queue[next_q] = insn; + q_size += 1; +} + +/* Return nonzero if PAT is the pattern of an insn which makes a + register live. */ + +__inline static int +birthing_insn_p (pat) + rtx pat; +{ + int j; + + if (reload_completed == 1) + return 0; + + if (GET_CODE (pat) == SET + && GET_CODE (SET_DEST (pat)) == REG) + { + rtx dest = SET_DEST (pat); + int i = REGNO (dest); + int offset = i / REGSET_ELT_BITS; + REGSET_ELT_TYPE bit = (REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS); + + /* It would be more accurate to use refers_to_regno_p or + reg_mentioned_p to determine when the dest is not live before this + insn. */ + + if (bb_live_regs[offset] & bit) + return (reg_n_sets[i] == 1); + + return 0; + } + if (GET_CODE (pat) == PARALLEL) + { + for (j = 0; j < XVECLEN (pat, 0); j++) + if (birthing_insn_p (XVECEXP (pat, 0, j))) + return 1; + } + return 0; +} + +/* PREV is an insn that is ready to execute. Adjust its priority if that + will help shorten register lifetimes. */ + +__inline static void +adjust_priority (prev) + rtx prev; +{ + /* Trying to shorten register lives after reload has completed + is useless and wrong. It gives inaccurate schedules. */ + if (reload_completed == 0) + { + rtx note; + int n_deaths = 0; + + /* ??? This code has no effect, because REG_DEAD notes are removed + before we ever get here. */ + for (note = REG_NOTES (prev); note; note = XEXP (note, 1)) + if (REG_NOTE_KIND (note) == REG_DEAD) + n_deaths += 1; + + /* Defer scheduling insns which kill registers, since that + shortens register lives. Prefer scheduling insns which + make registers live for the same reason. */ + switch (n_deaths) + { + default: + INSN_PRIORITY (prev) >>= 3; + break; + case 3: + INSN_PRIORITY (prev) >>= 2; + break; + case 2: + case 1: + INSN_PRIORITY (prev) >>= 1; + break; + case 0: + if (birthing_insn_p (PATTERN (prev))) + { + int max = max_priority; + + if (max > INSN_PRIORITY (prev)) + INSN_PRIORITY (prev) = max; + } + break; + } + } +} + +/* INSN is the "currently executing insn". Launch each insn which was + waiting on INSN (in the backwards dataflow sense). READY is a + vector of insns which are ready to fire. N_READY is the number of + elements in READY. CLOCK is the current virtual cycle. */ + +static int +schedule_insn (insn, ready, n_ready, clock) + rtx insn; + rtx *ready; + int n_ready; + int clock; +{ + rtx link; + int new_ready = n_ready; + + if (MAX_BLOCKAGE > 1) + schedule_unit (insn_unit (insn), insn, clock); + + if (LOG_LINKS (insn) == 0) + return n_ready; + + /* This is used by the function adjust_priority above. */ + if (n_ready > 0) + max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn)); + else + max_priority = INSN_PRIORITY (insn); + + for (link = LOG_LINKS (insn); link != 0; link = XEXP (link, 1)) + { + rtx prev = XEXP (link, 0); + int cost = insn_cost (prev, link, insn); + + if ((INSN_REF_COUNT (prev) -= 1) != 0) + { + /* We satisfied one requirement to fire PREV. Record the earliest + time when PREV can fire. No need to do this if the cost is 1, + because PREV can fire no sooner than the next cycle. */ + if (cost > 1) + INSN_TICK (prev) = MAX (INSN_TICK (prev), clock + cost); + } + else + { + /* We satisfied the last requirement to fire PREV. Ensure that all + timing requirements are satisfied. */ + if (INSN_TICK (prev) - clock > cost) + cost = INSN_TICK (prev) - clock; + + /* Adjust the priority of PREV and either put it on the ready + list or queue it. */ + adjust_priority (prev); + if (cost <= 1) + ready[new_ready++] = prev; + else + queue_insn (prev, cost); + } + } + + return new_ready; +} + +/* Given N_READY insns in the ready list READY at time CLOCK, queue + those that are blocked due to function unit hazards and rearrange + the remaining ones to minimize subsequent function unit hazards. */ + +static int +schedule_select (ready, n_ready, clock, file) + rtx *ready; + int n_ready, clock; + FILE *file; +{ + int pri = INSN_PRIORITY (ready[0]); + int i, j, k, q, cost, best_cost, best_insn = 0, new_ready = n_ready; + rtx insn; + + /* Work down the ready list in groups of instructions with the same + priority value. Queue insns in the group that are blocked and + select among those that remain for the one with the largest + potential hazard. */ + for (i = 0; i < n_ready; i = j) + { + int opri = pri; + for (j = i + 1; j < n_ready; j++) + if ((pri = INSN_PRIORITY (ready[j])) != opri) + break; + + /* Queue insns in the group that are blocked. */ + for (k = i, q = 0; k < j; k++) + { + insn = ready[k]; + if ((cost = actual_hazard (insn_unit (insn), insn, clock, 0)) != 0) + { + q++; + ready[k] = 0; + queue_insn (insn, cost); + if (file) + fprintf (file, "\n;; blocking insn %d for %d cycles", + INSN_UID (insn), cost); + } + } + new_ready -= q; + + /* Check the next group if all insns were queued. */ + if (j - i - q == 0) + continue; + + /* If more than one remains, select the first one with the largest + potential hazard. */ + else if (j - i - q > 1) + { + best_cost = -1; + for (k = i; k < j; k++) + { + if ((insn = ready[k]) == 0) + continue; + if ((cost = potential_hazard (insn_unit (insn), insn, 0)) + > best_cost) + { + best_cost = cost; + best_insn = k; + } + } + } + /* We have found a suitable insn to schedule. */ + break; + } + + /* Move the best insn to be front of the ready list. */ + if (best_insn != 0) + { + if (file) + { + fprintf (file, ", now"); + for (i = 0; i < n_ready; i++) + if (ready[i]) + fprintf (file, " %d", INSN_UID (ready[i])); + fprintf (file, "\n;; insn %d has a greater potential hazard", + INSN_UID (ready[best_insn])); + } + for (i = best_insn; i > 0; i--) + { + insn = ready[i-1]; + ready[i-1] = ready[i]; + ready[i] = insn; + } + } + + /* Compact the ready list. */ + if (new_ready < n_ready) + for (i = j = 0; i < n_ready; i++) + if (ready[i]) + ready[j++] = ready[i]; + + return new_ready; +} + +/* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the + dead_notes list. */ + +static void +create_reg_dead_note (reg, insn) + rtx reg, insn; +{ + rtx link, backlink; + + /* The number of registers killed after scheduling must be the same as the + number of registers killed before scheduling. The number of REG_DEAD + notes may not be conserved, i.e. two SImode hard register REG_DEAD notes + might become one DImode hard register REG_DEAD note, but the number of + registers killed will be conserved. + + We carefully remove REG_DEAD notes from the dead_notes list, so that + there will be none left at the end. If we run out early, then there + is a bug somewhere in flow, combine and/or sched. */ + + if (dead_notes == 0) + { +#if 1 + abort (); +#else + link = rtx_alloc (EXPR_LIST); + PUT_REG_NOTE_KIND (link, REG_DEAD); +#endif + } + else + { + /* Number of regs killed by REG. */ + int regs_killed = (REGNO (reg) >= FIRST_PSEUDO_REGISTER ? 1 + : HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg))); + /* Number of regs killed by REG_DEAD notes taken off the list. */ + int reg_note_regs; + + link = dead_notes; + reg_note_regs = (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1 + : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)), + GET_MODE (XEXP (link, 0)))); + while (reg_note_regs < regs_killed) + { + link = XEXP (link, 1); + reg_note_regs += (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1 + : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)), + GET_MODE (XEXP (link, 0)))); + } + dead_notes = XEXP (link, 1); + + /* If we took too many regs kills off, put the extra ones back. */ + while (reg_note_regs > regs_killed) + { + rtx temp_reg, temp_link; + + temp_reg = gen_rtx (REG, word_mode, 0); + temp_link = rtx_alloc (EXPR_LIST); + PUT_REG_NOTE_KIND (temp_link, REG_DEAD); + XEXP (temp_link, 0) = temp_reg; + XEXP (temp_link, 1) = dead_notes; + dead_notes = temp_link; + reg_note_regs--; + } + } + + XEXP (link, 0) = reg; + XEXP (link, 1) = REG_NOTES (insn); + REG_NOTES (insn) = link; +} + +/* Subroutine on attach_deaths_insn--handles the recursive search + through INSN. If SET_P is true, then x is being modified by the insn. */ + +static void +attach_deaths (x, insn, set_p) + rtx x; + rtx insn; + int set_p; +{ + register int i; + register int j; + register enum rtx_code code; + register char *fmt; + + if (x == 0) + return; + + code = GET_CODE (x); + + switch (code) + { + case CONST_INT: + case CONST_DOUBLE: + case LABEL_REF: + case SYMBOL_REF: + case CONST: + case CODE_LABEL: + case PC: + case CC0: + /* Get rid of the easy cases first. */ + return; + + case REG: + { + /* If the register dies in this insn, queue that note, and mark + this register as needing to die. */ + /* This code is very similar to mark_used_1 (if set_p is false) + and mark_set_1 (if set_p is true) in flow.c. */ + + register int regno = REGNO (x); + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + REGSET_ELT_TYPE all_needed = (old_live_regs[offset] & bit); + REGSET_ELT_TYPE some_needed = (old_live_regs[offset] & bit); + + if (set_p) + return; + + if (regno < FIRST_PSEUDO_REGISTER) + { + int n; + + n = HARD_REGNO_NREGS (regno, GET_MODE (x)); + while (--n > 0) + { + some_needed |= (old_live_regs[(regno + n) / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 + << ((regno + n) % REGSET_ELT_BITS))); + all_needed &= (old_live_regs[(regno + n) / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 + << ((regno + n) % REGSET_ELT_BITS))); + } + } + + /* If it wasn't live before we started, then add a REG_DEAD note. + We must check the previous lifetime info not the current info, + because we may have to execute this code several times, e.g. + once for a clobber (which doesn't add a note) and later + for a use (which does add a note). + + Always make the register live. We must do this even if it was + live before, because this may be an insn which sets and uses + the same register, in which case the register has already been + killed, so we must make it live again. + + Global registers are always live, and should never have a REG_DEAD + note added for them, so none of the code below applies to them. */ + + if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno]) + { + /* Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the + STACK_POINTER_REGNUM, since these are always considered to be + live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ + if (regno != FRAME_POINTER_REGNUM +#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM + && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) +#endif + && regno != STACK_POINTER_REGNUM) + { + if (! all_needed && ! dead_or_set_p (insn, x)) + { + /* If none of the words in X is needed, make a REG_DEAD + note. Otherwise, we must make partial REG_DEAD + notes. */ + if (! some_needed) + create_reg_dead_note (x, insn); + else + { + int i; + + /* Don't make a REG_DEAD note for a part of a + register that is set in the insn. */ + for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1; + i >= 0; i--) + if ((old_live_regs[(regno + i) / REGSET_ELT_BITS] + & ((REGSET_ELT_TYPE) 1 + << ((regno +i) % REGSET_ELT_BITS))) == 0 + && ! dead_or_set_regno_p (insn, regno + i)) + create_reg_dead_note (gen_rtx (REG, word_mode, + regno + i), + insn); + } + } + } + + if (regno < FIRST_PSEUDO_REGISTER) + { + int j = HARD_REGNO_NREGS (regno, GET_MODE (x)); + while (--j >= 0) + { + offset = (regno + j) / REGSET_ELT_BITS; + bit + = (REGSET_ELT_TYPE) 1 << ((regno + j) % REGSET_ELT_BITS); + + bb_dead_regs[offset] &= ~bit; + bb_live_regs[offset] |= bit; + } + } + else + { + bb_dead_regs[offset] &= ~bit; + bb_live_regs[offset] |= bit; + } + } + return; + } + + case MEM: + /* Handle tail-recursive case. */ + attach_deaths (XEXP (x, 0), insn, 0); + return; + + case SUBREG: + case STRICT_LOW_PART: + /* These two cases preserve the value of SET_P, so handle them + separately. */ + attach_deaths (XEXP (x, 0), insn, set_p); + return; + + case ZERO_EXTRACT: + case SIGN_EXTRACT: + /* This case preserves the value of SET_P for the first operand, but + clears it for the other two. */ + attach_deaths (XEXP (x, 0), insn, set_p); + attach_deaths (XEXP (x, 1), insn, 0); + attach_deaths (XEXP (x, 2), insn, 0); + return; + + default: + /* Other cases: walk the insn. */ + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + attach_deaths (XEXP (x, i), insn, 0); + else if (fmt[i] == 'E') + for (j = 0; j < XVECLEN (x, i); j++) + attach_deaths (XVECEXP (x, i, j), insn, 0); + } + } +} + +/* After INSN has executed, add register death notes for each register + that is dead after INSN. */ + +static void +attach_deaths_insn (insn) + rtx insn; +{ + rtx x = PATTERN (insn); + register RTX_CODE code = GET_CODE (x); + + if (code == SET) + { + attach_deaths (SET_SRC (x), insn, 0); + + /* A register might die here even if it is the destination, e.g. + it is the target of a volatile read and is otherwise unused. + Hence we must always call attach_deaths for the SET_DEST. */ + attach_deaths (SET_DEST (x), insn, 1); + } + else if (code == PARALLEL) + { + register int i; + for (i = XVECLEN (x, 0) - 1; i >= 0; i--) + { + code = GET_CODE (XVECEXP (x, 0, i)); + if (code == SET) + { + attach_deaths (SET_SRC (XVECEXP (x, 0, i)), insn, 0); + + attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1); + } + /* Flow does not add REG_DEAD notes to registers that die in + clobbers, so we can't either. */ + else if (code != CLOBBER) + attach_deaths (XVECEXP (x, 0, i), insn, 0); + } + } + /* Flow does not add REG_DEAD notes to registers that die in + clobbers, so we can't either. */ + else if (code != CLOBBER) + attach_deaths (x, insn, 0); +} + +/* Delete notes beginning with INSN and maybe put them in the chain + of notes ended by NOTE_LIST. + Returns the insn following the notes. */ + +static rtx +unlink_notes (insn, tail) + rtx insn, tail; +{ + rtx prev = PREV_INSN (insn); + + while (insn != tail && GET_CODE (insn) == NOTE) + { + rtx next = NEXT_INSN (insn); + /* Delete the note from its current position. */ + if (prev) + NEXT_INSN (prev) = next; + if (next) + PREV_INSN (next) = prev; + + if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0) + /* Record line-number notes so they can be reused. */ + LINE_NOTE (insn) = insn; + else + { + /* Insert the note at the end of the notes list. */ + PREV_INSN (insn) = note_list; + if (note_list) + NEXT_INSN (note_list) = insn; + note_list = insn; + } + + insn = next; + } + return insn; +} + +/* Data structure for keeping track of register information + during that register's life. */ + +struct sometimes +{ + short offset; short bit; + short live_length; short calls_crossed; +}; + +/* Constructor for `sometimes' data structure. */ + +static int +new_sometimes_live (regs_sometimes_live, offset, bit, sometimes_max) + struct sometimes *regs_sometimes_live; + int offset, bit; + int sometimes_max; +{ + register struct sometimes *p; + register int regno = offset * REGSET_ELT_BITS + bit; + int i; + + /* There should never be a register greater than max_regno here. If there + is, it means that a define_split has created a new pseudo reg. This + is not allowed, since there will not be flow info available for any + new register, so catch the error here. */ + if (regno >= max_regno) + abort (); + + p = ®s_sometimes_live[sometimes_max]; + p->offset = offset; + p->bit = bit; + p->live_length = 0; + p->calls_crossed = 0; + sometimes_max++; + return sometimes_max; +} + +/* Count lengths of all regs we are currently tracking, + and find new registers no longer live. */ + +static void +finish_sometimes_live (regs_sometimes_live, sometimes_max) + struct sometimes *regs_sometimes_live; + int sometimes_max; +{ + int i; + + for (i = 0; i < sometimes_max; i++) + { + register struct sometimes *p = ®s_sometimes_live[i]; + int regno; + + regno = p->offset * REGSET_ELT_BITS + p->bit; + + sched_reg_live_length[regno] += p->live_length; + sched_reg_n_calls_crossed[regno] += p->calls_crossed; + } +} + +/* Use modified list scheduling to rearrange insns in basic block + B. FILE, if nonzero, is where we dump interesting output about + this pass. */ + +static void +schedule_block (b, file) + int b; + FILE *file; +{ + rtx insn, last; + rtx last_note = 0; + rtx *ready, link; + int i, j, n_ready = 0, new_ready, n_insns = 0; + int sched_n_insns = 0; + int clock; +#define NEED_NOTHING 0 +#define NEED_HEAD 1 +#define NEED_TAIL 2 + int new_needs; + + /* HEAD and TAIL delimit the region being scheduled. */ + rtx head = basic_block_head[b]; + rtx tail = basic_block_end[b]; + /* PREV_HEAD and NEXT_TAIL are the boundaries of the insns + being scheduled. When the insns have been ordered, + these insns delimit where the new insns are to be + spliced back into the insn chain. */ + rtx next_tail; + rtx prev_head; + + /* Keep life information accurate. */ + register struct sometimes *regs_sometimes_live; + int sometimes_max; + + if (file) + fprintf (file, ";;\t -- basic block number %d from %d to %d --\n", + b, INSN_UID (basic_block_head[b]), INSN_UID (basic_block_end[b])); + + i = max_reg_num (); + reg_last_uses = (rtx *) alloca (i * sizeof (rtx)); + bzero (reg_last_uses, i * sizeof (rtx)); + reg_last_sets = (rtx *) alloca (i * sizeof (rtx)); + bzero (reg_last_sets, i * sizeof (rtx)); + clear_units (); + + /* Remove certain insns at the beginning from scheduling, + by advancing HEAD. */ + + /* At the start of a function, before reload has run, don't delay getting + parameters from hard registers into pseudo registers. */ + if (reload_completed == 0 && b == 0) + { + while (head != tail + && GET_CODE (head) == NOTE + && NOTE_LINE_NUMBER (head) != NOTE_INSN_FUNCTION_BEG) + head = NEXT_INSN (head); + while (head != tail + && GET_CODE (head) == INSN + && GET_CODE (PATTERN (head)) == SET) + { + rtx src = SET_SRC (PATTERN (head)); + while (GET_CODE (src) == SUBREG + || GET_CODE (src) == SIGN_EXTEND + || GET_CODE (src) == ZERO_EXTEND + || GET_CODE (src) == SIGN_EXTRACT + || GET_CODE (src) == ZERO_EXTRACT) + src = XEXP (src, 0); + if (GET_CODE (src) != REG + || REGNO (src) >= FIRST_PSEUDO_REGISTER) + break; + /* Keep this insn from ever being scheduled. */ + INSN_REF_COUNT (head) = 1; + head = NEXT_INSN (head); + } + } + + /* Don't include any notes or labels at the beginning of the + basic block, or notes at the ends of basic blocks. */ + while (head != tail) + { + if (GET_CODE (head) == NOTE) + head = NEXT_INSN (head); + else if (GET_CODE (tail) == NOTE) + tail = PREV_INSN (tail); + else if (GET_CODE (head) == CODE_LABEL) + head = NEXT_INSN (head); + else break; + } + /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need + to schedule this block. */ + if (head == tail + && (GET_CODE (head) == NOTE || GET_CODE (head) == CODE_LABEL)) + return; + +#if 0 + /* This short-cut doesn't work. It does not count call insns crossed by + registers in reg_sometimes_live. It does not mark these registers as + dead if they die in this block. It does not mark these registers live + (or create new reg_sometimes_live entries if necessary) if they are born + in this block. + + The easy solution is to just always schedule a block. This block only + has one insn, so this won't slow down this pass by much. */ + + if (head == tail) + return; +#endif + + /* Now HEAD through TAIL are the insns actually to be rearranged; + Let PREV_HEAD and NEXT_TAIL enclose them. */ + prev_head = PREV_INSN (head); + next_tail = NEXT_INSN (tail); + + /* Initialize basic block data structures. */ + dead_notes = 0; + pending_read_insns = 0; + pending_read_mems = 0; + pending_write_insns = 0; + pending_write_mems = 0; + pending_lists_length = 0; + last_pending_memory_flush = 0; + last_function_call = 0; + last_scheduled_insn = 0; + + LOG_LINKS (sched_before_next_call) = 0; + + n_insns += sched_analyze (head, tail); + if (n_insns == 0) + { + free_pending_lists (); + return; + } + + /* Allocate vector to hold insns to be rearranged (except those + insns which are controlled by an insn with SCHED_GROUP_P set). + All these insns are included between ORIG_HEAD and ORIG_TAIL, + as those variables ultimately are set up. */ + ready = (rtx *) alloca ((n_insns+1) * sizeof (rtx)); + + /* TAIL is now the last of the insns to be rearranged. + Put those insns into the READY vector. */ + insn = tail; + + /* For all branches, calls, uses, and cc0 setters, force them to remain + in order at the end of the block by adding dependencies and giving + the last a high priority. There may be notes present, and prev_head + may also be a note. + + Branches must obviously remain at the end. Calls should remain at the + end since moving them results in worse register allocation. Uses remain + at the end to ensure proper register allocation. cc0 setters remaim + at the end because they can't be moved away from their cc0 user. */ + last = 0; + while (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN + || (GET_CODE (insn) == INSN + && (GET_CODE (PATTERN (insn)) == USE +#ifdef HAVE_cc0 + || sets_cc0_p (PATTERN (insn)) +#endif + )) + || GET_CODE (insn) == NOTE) + { + if (GET_CODE (insn) != NOTE) + { + priority (insn); + if (last == 0) + { + ready[n_ready++] = insn; + INSN_PRIORITY (insn) = TAIL_PRIORITY - i; + INSN_REF_COUNT (insn) = 0; + } + else if (! find_insn_list (insn, LOG_LINKS (last))) + { + add_dependence (last, insn, REG_DEP_ANTI); + INSN_REF_COUNT (insn)++; + } + last = insn; + + /* Skip over insns that are part of a group. */ + while (SCHED_GROUP_P (insn)) + { + insn = prev_nonnote_insn (insn); + priority (insn); + } + } + + insn = PREV_INSN (insn); + /* Don't overrun the bounds of the basic block. */ + if (insn == prev_head) + break; + } + + /* Assign priorities to instructions. Also check whether they + are in priority order already. If so then I will be nonnegative. + We use this shortcut only before reloading. */ +#if 0 + i = reload_completed ? DONE_PRIORITY : MAX_PRIORITY; +#endif + + for (; insn != prev_head; insn = PREV_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + priority (insn); + if (INSN_REF_COUNT (insn) == 0) + { + if (last == 0) + ready[n_ready++] = insn; + else + { + /* Make this dependent on the last of the instructions + that must remain in order at the end of the block. */ + add_dependence (last, insn, REG_DEP_ANTI); + INSN_REF_COUNT (insn) = 1; + } + } + if (SCHED_GROUP_P (insn)) + { + while (SCHED_GROUP_P (insn)) + { + insn = PREV_INSN (insn); + while (GET_CODE (insn) == NOTE) + insn = PREV_INSN (insn); + priority (insn); + } + continue; + } +#if 0 + if (i < 0) + continue; + if (INSN_PRIORITY (insn) < i) + i = INSN_PRIORITY (insn); + else if (INSN_PRIORITY (insn) > i) + i = DONE_PRIORITY; +#endif + } + } + +#if 0 + /* This short-cut doesn't work. It does not count call insns crossed by + registers in reg_sometimes_live. It does not mark these registers as + dead if they die in this block. It does not mark these registers live + (or create new reg_sometimes_live entries if necessary) if they are born + in this block. + + The easy solution is to just always schedule a block. These blocks tend + to be very short, so this doesn't slow down this pass by much. */ + + /* If existing order is good, don't bother to reorder. */ + if (i != DONE_PRIORITY) + { + if (file) + fprintf (file, ";; already scheduled\n"); + + if (reload_completed == 0) + { + for (i = 0; i < sometimes_max; i++) + regs_sometimes_live[i].live_length += n_insns; + + finish_sometimes_live (regs_sometimes_live, sometimes_max); + } + free_pending_lists (); + return; + } +#endif + + /* Scan all the insns to be scheduled, removing NOTE insns + and register death notes. + Line number NOTE insns end up in NOTE_LIST. + Register death notes end up in DEAD_NOTES. + + Recreate the register life information for the end of this basic + block. */ + + if (reload_completed == 0) + { + bcopy (basic_block_live_at_start[b], bb_live_regs, regset_bytes); + bzero (bb_dead_regs, regset_bytes); + + if (b == 0) + { + /* This is the first block in the function. There may be insns + before head that we can't schedule. We still need to examine + them though for accurate register lifetime analysis. */ + + /* We don't want to remove any REG_DEAD notes as the code below + does. */ + + for (insn = basic_block_head[b]; insn != head; + insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + /* See if the register gets born here. */ + /* We must check for registers being born before we check for + registers dying. It is possible for a register to be born + and die in the same insn, e.g. reading from a volatile + memory location into an otherwise unused register. Such + a register must be marked as dead after this insn. */ + if (GET_CODE (PATTERN (insn)) == SET + || GET_CODE (PATTERN (insn)) == CLOBBER) + sched_note_set (b, PATTERN (insn), 0); + else if (GET_CODE (PATTERN (insn)) == PARALLEL) + { + int j; + for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) + if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET + || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) + sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0); + + /* ??? This code is obsolete and should be deleted. It + is harmless though, so we will leave it in for now. */ + for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) + if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE) + sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0); + } + + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + { + if ((REG_NOTE_KIND (link) == REG_DEAD + || REG_NOTE_KIND (link) == REG_UNUSED) + /* Verify that the REG_NOTE has a legal value. */ + && GET_CODE (XEXP (link, 0)) == REG) + { + register int regno = REGNO (XEXP (link, 0)); + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + + if (regno < FIRST_PSEUDO_REGISTER) + { + int j = HARD_REGNO_NREGS (regno, + GET_MODE (XEXP (link, 0))); + while (--j >= 0) + { + offset = (regno + j) / REGSET_ELT_BITS; + bit = ((REGSET_ELT_TYPE) 1 + << ((regno + j) % REGSET_ELT_BITS)); + + bb_live_regs[offset] &= ~bit; + bb_dead_regs[offset] |= bit; + } + } + else + { + bb_live_regs[offset] &= ~bit; + bb_dead_regs[offset] |= bit; + } + } + } + } + } + } + + /* If debugging information is being produced, keep track of the line + number notes for each insn. */ + if (write_symbols != NO_DEBUG) + { + /* We must use the true line number for the first insn in the block + that was computed and saved at the start of this pass. We can't + use the current line number, because scheduling of the previous + block may have changed the current line number. */ + rtx line = line_note_head[b]; + + for (insn = basic_block_head[b]; + insn != next_tail; + insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) + line = insn; + else + LINE_NOTE (insn) = line; + } + + for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) + { + rtx prev, next, link; + + /* Farm out notes. This is needed to keep the debugger from + getting completely deranged. */ + if (GET_CODE (insn) == NOTE) + { + prev = insn; + insn = unlink_notes (insn, next_tail); + if (prev == tail) + abort (); + if (prev == head) + abort (); + if (insn == next_tail) + abort (); + } + + if (reload_completed == 0 + && GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + /* See if the register gets born here. */ + /* We must check for registers being born before we check for + registers dying. It is possible for a register to be born and + die in the same insn, e.g. reading from a volatile memory + location into an otherwise unused register. Such a register + must be marked as dead after this insn. */ + if (GET_CODE (PATTERN (insn)) == SET + || GET_CODE (PATTERN (insn)) == CLOBBER) + sched_note_set (b, PATTERN (insn), 0); + else if (GET_CODE (PATTERN (insn)) == PARALLEL) + { + int j; + for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) + if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET + || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) + sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0); + + /* ??? This code is obsolete and should be deleted. It + is harmless though, so we will leave it in for now. */ + for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) + if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE) + sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0); + } + + /* Need to know what registers this insn kills. */ + for (prev = 0, link = REG_NOTES (insn); link; link = next) + { + int regno; + + next = XEXP (link, 1); + if ((REG_NOTE_KIND (link) == REG_DEAD + || REG_NOTE_KIND (link) == REG_UNUSED) + /* Verify that the REG_NOTE has a legal value. */ + && GET_CODE (XEXP (link, 0)) == REG) + { + register int regno = REGNO (XEXP (link, 0)); + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + + /* Only unlink REG_DEAD notes; leave REG_UNUSED notes + alone. */ + if (REG_NOTE_KIND (link) == REG_DEAD) + { + if (prev) + XEXP (prev, 1) = next; + else + REG_NOTES (insn) = next; + XEXP (link, 1) = dead_notes; + dead_notes = link; + } + else + prev = link; + + if (regno < FIRST_PSEUDO_REGISTER) + { + int j = HARD_REGNO_NREGS (regno, + GET_MODE (XEXP (link, 0))); + while (--j >= 0) + { + offset = (regno + j) / REGSET_ELT_BITS; + bit = ((REGSET_ELT_TYPE) 1 + << ((regno + j) % REGSET_ELT_BITS)); + + bb_live_regs[offset] &= ~bit; + bb_dead_regs[offset] |= bit; + } + } + else + { + bb_live_regs[offset] &= ~bit; + bb_dead_regs[offset] |= bit; + } + } + else + prev = link; + } + } + } + + if (reload_completed == 0) + { + /* Keep track of register lives. */ + old_live_regs = (regset) alloca (regset_bytes); + regs_sometimes_live + = (struct sometimes *) alloca (max_regno * sizeof (struct sometimes)); + sometimes_max = 0; + + /* Start with registers live at end. */ + for (j = 0; j < regset_size; j++) + { + REGSET_ELT_TYPE live = bb_live_regs[j]; + old_live_regs[j] = live; + if (live) + { + register REGSET_ELT_TYPE bit; + for (bit = 0; bit < REGSET_ELT_BITS; bit++) + if (live & ((REGSET_ELT_TYPE) 1 << bit)) + sometimes_max = new_sometimes_live (regs_sometimes_live, j, + bit, sometimes_max); + } + } + } + + SCHED_SORT (ready, n_ready, 1); + + if (file) + { + fprintf (file, ";; ready list initially:\n;; "); + for (i = 0; i < n_ready; i++) + fprintf (file, "%d ", INSN_UID (ready[i])); + fprintf (file, "\n\n"); + + for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) + if (INSN_PRIORITY (insn) > 0) + fprintf (file, ";; insn[%4d]: priority = %4d, ref_count = %4d\n", + INSN_UID (insn), INSN_PRIORITY (insn), + INSN_REF_COUNT (insn)); + } + + /* Now HEAD and TAIL are going to become disconnected + entirely from the insn chain. */ + tail = 0; + + /* Q_SIZE will always be zero here. */ + q_ptr = 0; clock = 0; + bzero (insn_queue, sizeof (insn_queue)); + + /* Now, perform list scheduling. */ + + /* Where we start inserting insns is after TAIL. */ + last = next_tail; + + new_needs = (NEXT_INSN (prev_head) == basic_block_head[b] + ? NEED_HEAD : NEED_NOTHING); + if (PREV_INSN (next_tail) == basic_block_end[b]) + new_needs |= NEED_TAIL; + + new_ready = n_ready; + while (sched_n_insns < n_insns) + { + q_ptr = NEXT_Q (q_ptr); clock++; + + /* Add all pending insns that can be scheduled without stalls to the + ready list. */ + for (insn = insn_queue[q_ptr]; insn; insn = NEXT_INSN (insn)) + { + if (file) + fprintf (file, ";; launching %d before %d with no stalls at T-%d\n", + INSN_UID (insn), INSN_UID (last), clock); + ready[new_ready++] = insn; + q_size -= 1; + } + insn_queue[q_ptr] = 0; + + /* If there are no ready insns, stall until one is ready and add all + of the pending insns at that point to the ready list. */ + if (new_ready == 0) + { + register int stalls; + + for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++) + if (insn = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]) + { + for (; insn; insn = NEXT_INSN (insn)) + { + if (file) + fprintf (file, ";; launching %d before %d with %d stalls at T-%d\n", + INSN_UID (insn), INSN_UID (last), stalls, clock); + ready[new_ready++] = insn; + q_size -= 1; + } + insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0; + break; + } + + q_ptr = NEXT_Q_AFTER (q_ptr, stalls); clock += stalls; + } + + /* There should be some instructions waiting to fire. */ + if (new_ready == 0) + abort (); + + if (file) + { + fprintf (file, ";; ready list at T-%d:", clock); + for (i = 0; i < new_ready; i++) + fprintf (file, " %d (%x)", + INSN_UID (ready[i]), INSN_PRIORITY (ready[i])); + } + + /* Sort the ready list and choose the best insn to schedule. Select + which insn should issue in this cycle and queue those that are + blocked by function unit hazards. + + N_READY holds the number of items that were scheduled the last time, + minus the one instruction scheduled on the last loop iteration; it + is not modified for any other reason in this loop. */ + + SCHED_SORT (ready, new_ready, n_ready); + if (MAX_BLOCKAGE > 1) + { + new_ready = schedule_select (ready, new_ready, clock, file); + if (new_ready == 0) + { + if (file) + fprintf (file, "\n"); + /* We must set n_ready here, to ensure that sorting always + occurs when we come back to the SCHED_SORT line above. */ + n_ready = 0; + continue; + } + } + n_ready = new_ready; + last_scheduled_insn = insn = ready[0]; + + /* The first insn scheduled becomes the new tail. */ + if (tail == 0) + tail = insn; + + if (file) + { + fprintf (file, ", now"); + for (i = 0; i < n_ready; i++) + fprintf (file, " %d", INSN_UID (ready[i])); + fprintf (file, "\n"); + } + + if (DONE_PRIORITY_P (insn)) + abort (); + + if (reload_completed == 0) + { + /* Process this insn, and each insn linked to this one which must + be immediately output after this insn. */ + do + { + /* First we kill registers set by this insn, and then we + make registers used by this insn live. This is the opposite + order used above because we are traversing the instructions + backwards. */ + + /* Strictly speaking, we should scan REG_UNUSED notes and make + every register mentioned there live, however, we will just + kill them again immediately below, so there doesn't seem to + be any reason why we bother to do this. */ + + /* See if this is the last notice we must take of a register. */ + if (GET_CODE (PATTERN (insn)) == SET + || GET_CODE (PATTERN (insn)) == CLOBBER) + sched_note_set (b, PATTERN (insn), 1); + else if (GET_CODE (PATTERN (insn)) == PARALLEL) + { + int j; + for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) + if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET + || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) + sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 1); + } + + /* This code keeps life analysis information up to date. */ + if (GET_CODE (insn) == CALL_INSN) + { + register struct sometimes *p; + + /* A call kills all call used and global registers, except + for those mentioned in the call pattern which will be + made live again later. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (call_used_regs[i] || global_regs[i]) + { + register int offset = i / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS); + + bb_live_regs[offset] &= ~bit; + bb_dead_regs[offset] |= bit; + } + + /* Regs live at the time of a call instruction must not + go in a register clobbered by calls. Record this for + all regs now live. Note that insns which are born or + die in a call do not cross a call, so this must be done + after the killings (above) and before the births + (below). */ + p = regs_sometimes_live; + for (i = 0; i < sometimes_max; i++, p++) + if (bb_live_regs[p->offset] + & ((REGSET_ELT_TYPE) 1 << p->bit)) + p->calls_crossed += 1; + } + + /* Make every register used live, and add REG_DEAD notes for + registers which were not live before we started. */ + attach_deaths_insn (insn); + + /* Find registers now made live by that instruction. */ + for (i = 0; i < regset_size; i++) + { + REGSET_ELT_TYPE diff = bb_live_regs[i] & ~old_live_regs[i]; + if (diff) + { + register int bit; + old_live_regs[i] |= diff; + for (bit = 0; bit < REGSET_ELT_BITS; bit++) + if (diff & ((REGSET_ELT_TYPE) 1 << bit)) + sometimes_max + = new_sometimes_live (regs_sometimes_live, i, bit, + sometimes_max); + } + } + + /* Count lengths of all regs we are worrying about now, + and handle registers no longer live. */ + + for (i = 0; i < sometimes_max; i++) + { + register struct sometimes *p = ®s_sometimes_live[i]; + int regno = p->offset*REGSET_ELT_BITS + p->bit; + + p->live_length += 1; + + if ((bb_live_regs[p->offset] + & ((REGSET_ELT_TYPE) 1 << p->bit)) == 0) + { + /* This is the end of one of this register's lifetime + segments. Save the lifetime info collected so far, + and clear its bit in the old_live_regs entry. */ + sched_reg_live_length[regno] += p->live_length; + sched_reg_n_calls_crossed[regno] += p->calls_crossed; + old_live_regs[p->offset] + &= ~((REGSET_ELT_TYPE) 1 << p->bit); + + /* Delete the reg_sometimes_live entry for this reg by + copying the last entry over top of it. */ + *p = regs_sometimes_live[--sometimes_max]; + /* ...and decrement i so that this newly copied entry + will be processed. */ + i--; + } + } + + link = insn; + insn = PREV_INSN (insn); + } + while (SCHED_GROUP_P (link)); + + /* Set INSN back to the insn we are scheduling now. */ + insn = ready[0]; + } + + /* Schedule INSN. Remove it from the ready list. */ + ready += 1; + n_ready -= 1; + + sched_n_insns += 1; + NEXT_INSN (insn) = last; + PREV_INSN (last) = insn; + last = insn; + + /* Everything that precedes INSN now either becomes "ready", if + it can execute immediately before INSN, or "pending", if + there must be a delay. Give INSN high enough priority that + at least one (maybe more) reg-killing insns can be launched + ahead of all others. Mark INSN as scheduled by changing its + priority to -1. */ + INSN_PRIORITY (insn) = LAUNCH_PRIORITY; + new_ready = schedule_insn (insn, ready, n_ready, clock); + INSN_PRIORITY (insn) = DONE_PRIORITY; + + /* Schedule all prior insns that must not be moved. */ + if (SCHED_GROUP_P (insn)) + { + /* Disable these insns from being launched. */ + link = insn; + while (SCHED_GROUP_P (link)) + { + /* Disable these insns from being launched by anybody. */ + link = PREV_INSN (link); + INSN_REF_COUNT (link) = 0; + } + + /* None of these insns can move forward into delay slots. */ + while (SCHED_GROUP_P (insn)) + { + insn = PREV_INSN (insn); + new_ready = schedule_insn (insn, ready, new_ready, clock); + INSN_PRIORITY (insn) = DONE_PRIORITY; + + sched_n_insns += 1; + NEXT_INSN (insn) = last; + PREV_INSN (last) = insn; + last = insn; + } + } + } + if (q_size != 0) + abort (); + + if (reload_completed == 0) + finish_sometimes_live (regs_sometimes_live, sometimes_max); + + /* HEAD is now the first insn in the chain of insns that + been scheduled by the loop above. + TAIL is the last of those insns. */ + head = insn; + + /* NOTE_LIST is the end of a chain of notes previously found + among the insns. Insert them at the beginning of the insns. */ + if (note_list != 0) + { + rtx note_head = note_list; + while (PREV_INSN (note_head)) + note_head = PREV_INSN (note_head); + + PREV_INSN (head) = note_list; + NEXT_INSN (note_list) = head; + head = note_head; + } + + /* There should be no REG_DEAD notes leftover at the end. + In practice, this can occur as the result of bugs in flow, combine.c, + and/or sched.c. The values of the REG_DEAD notes remaining are + meaningless, because dead_notes is just used as a free list. */ +#if 1 + if (dead_notes != 0) + abort (); +#endif + + if (new_needs & NEED_HEAD) + basic_block_head[b] = head; + PREV_INSN (head) = prev_head; + NEXT_INSN (prev_head) = head; + + if (new_needs & NEED_TAIL) + basic_block_end[b] = tail; + NEXT_INSN (tail) = next_tail; + PREV_INSN (next_tail) = tail; + + /* Restore the line-number notes of each insn. */ + if (write_symbols != NO_DEBUG) + { + rtx line, note, prev, new; + int notes = 0; + + head = basic_block_head[b]; + next_tail = NEXT_INSN (basic_block_end[b]); + + /* Determine the current line-number. We want to know the current + line number of the first insn of the block here, in case it is + different from the true line number that was saved earlier. If + different, then we need a line number note before the first insn + of this block. If it happens to be the same, then we don't want to + emit another line number note here. */ + for (line = head; line; line = PREV_INSN (line)) + if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) + break; + + /* Walk the insns keeping track of the current line-number and inserting + the line-number notes as needed. */ + for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) + line = insn; + else if (! (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) + && (note = LINE_NOTE (insn)) != 0 + && note != line + && (line == 0 + || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line) + || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line))) + { + line = note; + prev = PREV_INSN (insn); + if (LINE_NOTE (note)) + { + /* Re-use the original line-number note. */ + LINE_NOTE (note) = 0; + PREV_INSN (note) = prev; + NEXT_INSN (prev) = note; + PREV_INSN (insn) = note; + NEXT_INSN (note) = insn; + } + else + { + notes++; + new = emit_note_after (NOTE_LINE_NUMBER (note), prev); + NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note); + } + } + if (file && notes) + fprintf (file, ";; added %d line-number notes\n", notes); + } + + if (file) + { + fprintf (file, ";; total time = %d\n;; new basic block head = %d\n;; new basic block end = %d\n\n", + clock, INSN_UID (basic_block_head[b]), INSN_UID (basic_block_end[b])); + } + + /* Yow! We're done! */ + free_pending_lists (); + + return; +} + +/* Subroutine of split_hard_reg_notes. Searches X for any reference to + REGNO, returning the rtx of the reference found if any. Otherwise, + returns 0. */ + +rtx +regno_use_in (regno, x) + int regno; + rtx x; +{ + register char *fmt; + int i, j; + rtx tem; + + if (GET_CODE (x) == REG && REGNO (x) == regno) + return x; + + fmt = GET_RTX_FORMAT (GET_CODE (x)); + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + { + if (tem = regno_use_in (regno, XEXP (x, i))) + return tem; + } + else if (fmt[i] == 'E') + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + if (tem = regno_use_in (regno , XVECEXP (x, i, j))) + return tem; + } + + return 0; +} + +/* Subroutine of update_flow_info. Determines whether any new REG_NOTEs are + needed for the hard register mentioned in the note. This can happen + if the reference to the hard register in the original insn was split into + several smaller hard register references in the split insns. */ + +static void +split_hard_reg_notes (note, first, last, orig_insn) + rtx note, first, last, orig_insn; +{ + rtx reg, temp, link; + int n_regs, i, new_reg; + rtx insn; + + /* Assume that this is a REG_DEAD note. */ + if (REG_NOTE_KIND (note) != REG_DEAD) + abort (); + + reg = XEXP (note, 0); + + n_regs = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); + + for (i = 0; i < n_regs; i++) + { + new_reg = REGNO (reg) + i; + + /* Check for references to new_reg in the split insns. */ + for (insn = last; ; insn = PREV_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && (temp = regno_use_in (new_reg, PATTERN (insn)))) + { + /* Create a new reg dead note here. */ + link = rtx_alloc (EXPR_LIST); + PUT_REG_NOTE_KIND (link, REG_DEAD); + XEXP (link, 0) = temp; + XEXP (link, 1) = REG_NOTES (insn); + REG_NOTES (insn) = link; + + /* If killed multiple registers here, then add in the excess. */ + i += HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) - 1; + + break; + } + /* It isn't mentioned anywhere, so no new reg note is needed for + this register. */ + if (insn == first) + break; + } + } +} + +/* Subroutine of update_flow_info. Determines whether a SET or CLOBBER in an + insn created by splitting needs a REG_DEAD or REG_UNUSED note added. */ + +static void +new_insn_dead_notes (pat, insn, last, orig_insn) + rtx pat, insn, last, orig_insn; +{ + rtx dest, tem, set; + + /* PAT is either a CLOBBER or a SET here. */ + dest = XEXP (pat, 0); + + while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG + || GET_CODE (dest) == STRICT_LOW_PART + || GET_CODE (dest) == SIGN_EXTRACT) + dest = XEXP (dest, 0); + + if (GET_CODE (dest) == REG) + { + for (tem = last; tem != insn; tem = PREV_INSN (tem)) + { + if (GET_RTX_CLASS (GET_CODE (tem)) == 'i' + && reg_overlap_mentioned_p (dest, PATTERN (tem)) + && (set = single_set (tem))) + { + rtx tem_dest = SET_DEST (set); + + while (GET_CODE (tem_dest) == ZERO_EXTRACT + || GET_CODE (tem_dest) == SUBREG + || GET_CODE (tem_dest) == STRICT_LOW_PART + || GET_CODE (tem_dest) == SIGN_EXTRACT) + tem_dest = XEXP (tem_dest, 0); + + if (tem_dest != dest) + { + /* Use the same scheme as combine.c, don't put both REG_DEAD + and REG_UNUSED notes on the same insn. */ + if (! find_regno_note (tem, REG_UNUSED, REGNO (dest)) + && ! find_regno_note (tem, REG_DEAD, REGNO (dest))) + { + rtx note = rtx_alloc (EXPR_LIST); + PUT_REG_NOTE_KIND (note, REG_DEAD); + XEXP (note, 0) = dest; + XEXP (note, 1) = REG_NOTES (tem); + REG_NOTES (tem) = note; + } + /* The reg only dies in one insn, the last one that uses + it. */ + break; + } + else if (reg_overlap_mentioned_p (dest, SET_SRC (set))) + /* We found an instruction that both uses the register, + and sets it, so no new REG_NOTE is needed for this set. */ + break; + } + } + /* If this is a set, it must die somewhere, unless it is the dest of + the original insn, and hence is live after the original insn. Abort + if it isn't supposed to be live after the original insn. + + If this is a clobber, then just add a REG_UNUSED note. */ + if (tem == insn) + { + int live_after_orig_insn = 0; + rtx pattern = PATTERN (orig_insn); + int i; + + if (GET_CODE (pat) == CLOBBER) + { + rtx note = rtx_alloc (EXPR_LIST); + PUT_REG_NOTE_KIND (note, REG_UNUSED); + XEXP (note, 0) = dest; + XEXP (note, 1) = REG_NOTES (insn); + REG_NOTES (insn) = note; + return; + } + + /* The original insn could have multiple sets, so search the + insn for all sets. */ + if (GET_CODE (pattern) == SET) + { + if (reg_overlap_mentioned_p (dest, SET_DEST (pattern))) + live_after_orig_insn = 1; + } + else if (GET_CODE (pattern) == PARALLEL) + { + for (i = 0; i < XVECLEN (pattern, 0); i++) + if (GET_CODE (XVECEXP (pattern, 0, i)) == SET + && reg_overlap_mentioned_p (dest, + SET_DEST (XVECEXP (pattern, + 0, i)))) + live_after_orig_insn = 1; + } + + if (! live_after_orig_insn) + abort (); + } + } +} + +/* Subroutine of update_flow_info. Update the value of reg_n_sets for all + registers modified by X. INC is -1 if the containing insn is being deleted, + and is 1 if the containing insn is a newly generated insn. */ + +static void +update_n_sets (x, inc) + rtx x; + int inc; +{ + rtx dest = SET_DEST (x); + + while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG + || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) + dest = SUBREG_REG (dest); + + if (GET_CODE (dest) == REG) + { + int regno = REGNO (dest); + + if (regno < FIRST_PSEUDO_REGISTER) + { + register int i; + int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (dest)); + + for (i = regno; i < endregno; i++) + reg_n_sets[i] += inc; + } + else + reg_n_sets[regno] += inc; + } +} + +/* Updates all flow-analysis related quantities (including REG_NOTES) for + the insns from FIRST to LAST inclusive that were created by splitting + ORIG_INSN. NOTES are the original REG_NOTES. */ + +static void +update_flow_info (notes, first, last, orig_insn) + rtx notes; + rtx first, last; + rtx orig_insn; +{ + rtx insn, note; + rtx next; + rtx orig_dest, temp; + rtx set; + + /* Get and save the destination set by the original insn. */ + + orig_dest = single_set (orig_insn); + if (orig_dest) + orig_dest = SET_DEST (orig_dest); + + /* Move REG_NOTES from the original insn to where they now belong. */ + + for (note = notes; note; note = next) + { + next = XEXP (note, 1); + switch (REG_NOTE_KIND (note)) + { + case REG_DEAD: + case REG_UNUSED: + /* Move these notes from the original insn to the last new insn where + the register is now set. */ + + for (insn = last; ; insn = PREV_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_mentioned_p (XEXP (note, 0), PATTERN (insn))) + { + /* If this note refers to a multiple word hard register, it + may have been split into several smaller hard register + references, so handle it specially. */ + temp = XEXP (note, 0); + if (REG_NOTE_KIND (note) == REG_DEAD + && GET_CODE (temp) == REG + && REGNO (temp) < FIRST_PSEUDO_REGISTER + && HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) > 1) + split_hard_reg_notes (note, first, last, orig_insn); + else + { + XEXP (note, 1) = REG_NOTES (insn); + REG_NOTES (insn) = note; + } + + /* Sometimes need to convert REG_UNUSED notes to REG_DEAD + notes. */ + /* ??? This won't handle multiple word registers correctly, + but should be good enough for now. */ + if (REG_NOTE_KIND (note) == REG_UNUSED + && ! dead_or_set_p (insn, XEXP (note, 0))) + PUT_REG_NOTE_KIND (note, REG_DEAD); + + /* The reg only dies in one insn, the last one that uses + it. */ + break; + } + /* It must die somewhere, fail it we couldn't find where it died. + + If this is a REG_UNUSED note, then it must be a temporary + register that was not needed by this instantiation of the + pattern, so we can safely ignore it. */ + if (insn == first) + { + if (REG_NOTE_KIND (note) != REG_UNUSED) + abort (); + + break; + } + } + break; + + case REG_WAS_0: + /* This note applies to the dest of the original insn. Find the + first new insn that now has the same dest, and move the note + there. */ + + if (! orig_dest) + abort (); + + for (insn = first; ; insn = NEXT_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && (temp = single_set (insn)) + && rtx_equal_p (SET_DEST (temp), orig_dest)) + { + XEXP (note, 1) = REG_NOTES (insn); + REG_NOTES (insn) = note; + /* The reg is only zero before one insn, the first that + uses it. */ + break; + } + /* It must be set somewhere, fail if we couldn't find where it + was set. */ + if (insn == last) + abort (); + } + break; + + case REG_EQUAL: + case REG_EQUIV: + /* A REG_EQUIV or REG_EQUAL note on an insn with more than one + set is meaningless. Just drop the note. */ + if (! orig_dest) + break; + + case REG_NO_CONFLICT: + /* These notes apply to the dest of the original insn. Find the last + new insn that now has the same dest, and move the note there. */ + + if (! orig_dest) + abort (); + + for (insn = last; ; insn = PREV_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && (temp = single_set (insn)) + && rtx_equal_p (SET_DEST (temp), orig_dest)) + { + XEXP (note, 1) = REG_NOTES (insn); + REG_NOTES (insn) = note; + /* Only put this note on one of the new insns. */ + break; + } + + /* The original dest must still be set someplace. Abort if we + couldn't find it. */ + if (insn == first) + abort (); + } + break; + + case REG_LIBCALL: + /* Move a REG_LIBCALL note to the first insn created, and update + the corresponding REG_RETVAL note. */ + XEXP (note, 1) = REG_NOTES (first); + REG_NOTES (first) = note; + + insn = XEXP (note, 0); + note = find_reg_note (insn, REG_RETVAL, NULL_RTX); + if (note) + XEXP (note, 0) = first; + break; + + case REG_RETVAL: + /* Move a REG_RETVAL note to the last insn created, and update + the corresponding REG_LIBCALL note. */ + XEXP (note, 1) = REG_NOTES (last); + REG_NOTES (last) = note; + + insn = XEXP (note, 0); + note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); + if (note) + XEXP (note, 0) = last; + break; + + case REG_NONNEG: + /* This should be moved to whichever instruction is a JUMP_INSN. */ + + for (insn = last; ; insn = PREV_INSN (insn)) + { + if (GET_CODE (insn) == JUMP_INSN) + { + XEXP (note, 1) = REG_NOTES (insn); + REG_NOTES (insn) = note; + /* Only put this note on one of the new insns. */ + break; + } + /* Fail if we couldn't find a JUMP_INSN. */ + if (insn == first) + abort (); + } + break; + + case REG_INC: + /* This should be moved to whichever instruction now has the + increment operation. */ + abort (); + + case REG_LABEL: + /* Should be moved to the new insn(s) which use the label. */ + for (insn = first; insn != NEXT_INSN (last); insn = NEXT_INSN (insn)) + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_mentioned_p (XEXP (note, 0), PATTERN (insn))) + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL, + XEXP (note, 0), REG_NOTES (insn)); + break; + + case REG_CC_SETTER: + case REG_CC_USER: + /* These two notes will never appear until after reorg, so we don't + have to handle them here. */ + default: + abort (); + } + } + + /* Each new insn created, except the last, has a new set. If the destination + is a register, then this reg is now live across several insns, whereas + previously the dest reg was born and died within the same insn. To + reflect this, we now need a REG_DEAD note on the insn where this + dest reg dies. + + Similarly, the new insns may have clobbers that need REG_UNUSED notes. */ + + for (insn = first; insn != last; insn = NEXT_INSN (insn)) + { + rtx pat; + int i; + + pat = PATTERN (insn); + if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) + new_insn_dead_notes (pat, insn, last, orig_insn); + else if (GET_CODE (pat) == PARALLEL) + { + for (i = 0; i < XVECLEN (pat, 0); i++) + if (GET_CODE (XVECEXP (pat, 0, i)) == SET + || GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER) + new_insn_dead_notes (XVECEXP (pat, 0, i), insn, last, orig_insn); + } + } + + /* If any insn, except the last, uses the register set by the last insn, + then we need a new REG_DEAD note on that insn. In this case, there + would not have been a REG_DEAD note for this register in the original + insn because it was used and set within one insn. + + There is no new REG_DEAD note needed if the last insn uses the register + that it is setting. */ + + set = single_set (last); + if (set) + { + rtx dest = SET_DEST (set); + + while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG + || GET_CODE (dest) == STRICT_LOW_PART + || GET_CODE (dest) == SIGN_EXTRACT) + dest = XEXP (dest, 0); + + if (GET_CODE (dest) == REG + && ! reg_overlap_mentioned_p (dest, SET_SRC (set))) + { + for (insn = PREV_INSN (last); ; insn = PREV_INSN (insn)) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_mentioned_p (dest, PATTERN (insn)) + && (set = single_set (insn))) + { + rtx insn_dest = SET_DEST (set); + + while (GET_CODE (insn_dest) == ZERO_EXTRACT + || GET_CODE (insn_dest) == SUBREG + || GET_CODE (insn_dest) == STRICT_LOW_PART + || GET_CODE (insn_dest) == SIGN_EXTRACT) + insn_dest = XEXP (insn_dest, 0); + + if (insn_dest != dest) + { + note = rtx_alloc (EXPR_LIST); + PUT_REG_NOTE_KIND (note, REG_DEAD); + XEXP (note, 0) = dest; + XEXP (note, 1) = REG_NOTES (insn); + REG_NOTES (insn) = note; + /* The reg only dies in one insn, the last one + that uses it. */ + break; + } + } + if (insn == first) + break; + } + } + } + + /* If the original dest is modifying a multiple register target, and the + original instruction was split such that the original dest is now set + by two or more SUBREG sets, then the split insns no longer kill the + destination of the original insn. + + In this case, if there exists an instruction in the same basic block, + before the split insn, which uses the original dest, and this use is + killed by the original insn, then we must remove the REG_DEAD note on + this insn, because it is now superfluous. + + This does not apply when a hard register gets split, because the code + knows how to handle overlapping hard registers properly. */ + if (orig_dest && GET_CODE (orig_dest) == REG) + { + int found_orig_dest = 0; + int found_split_dest = 0; + + for (insn = first; ; insn = NEXT_INSN (insn)) + { + set = single_set (insn); + if (set) + { + if (GET_CODE (SET_DEST (set)) == REG + && REGNO (SET_DEST (set)) == REGNO (orig_dest)) + { + found_orig_dest = 1; + break; + } + else if (GET_CODE (SET_DEST (set)) == SUBREG + && SUBREG_REG (SET_DEST (set)) == orig_dest) + { + found_split_dest = 1; + break; + } + } + + if (insn == last) + break; + } + + if (found_split_dest) + { + /* Search backwards from FIRST, looking for the first insn that uses + the original dest. Stop if we pass a CODE_LABEL or a JUMP_INSN. + If we find an insn, and it has a REG_DEAD note, then delete the + note. */ + + for (insn = first; insn; insn = PREV_INSN (insn)) + { + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == JUMP_INSN) + break; + else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_mentioned_p (orig_dest, insn)) + { + note = find_regno_note (insn, REG_DEAD, REGNO (orig_dest)); + if (note) + remove_note (insn, note); + } + } + } + else if (! found_orig_dest) + { + /* This should never happen. */ + abort (); + } + } + + /* Update reg_n_sets. This is necessary to prevent local alloc from + converting REG_EQUAL notes to REG_EQUIV when splitting has modified + a reg from set once to set multiple times. */ + + { + rtx x = PATTERN (orig_insn); + RTX_CODE code = GET_CODE (x); + + if (code == SET || code == CLOBBER) + update_n_sets (x, -1); + else if (code == PARALLEL) + { + int i; + for (i = XVECLEN (x, 0) - 1; i >= 0; i--) + { + code = GET_CODE (XVECEXP (x, 0, i)); + if (code == SET || code == CLOBBER) + update_n_sets (XVECEXP (x, 0, i), -1); + } + } + + for (insn = first; ; insn = NEXT_INSN (insn)) + { + x = PATTERN (insn); + code = GET_CODE (x); + + if (code == SET || code == CLOBBER) + update_n_sets (x, 1); + else if (code == PARALLEL) + { + int i; + for (i = XVECLEN (x, 0) - 1; i >= 0; i--) + { + code = GET_CODE (XVECEXP (x, 0, i)); + if (code == SET || code == CLOBBER) + update_n_sets (XVECEXP (x, 0, i), 1); + } + } + + if (insn == last) + break; + } + } +} + +/* The one entry point in this file. DUMP_FILE is the dump file for + this pass. */ + +void +schedule_insns (dump_file) + FILE *dump_file; +{ + int max_uid = MAX_INSNS_PER_SPLIT * (get_max_uid () + 1); + int i, b; + rtx insn; + + /* Taking care of this degenerate case makes the rest of + this code simpler. */ + if (n_basic_blocks == 0) + return; + + /* Create an insn here so that we can hang dependencies off of it later. */ + sched_before_next_call + = gen_rtx (INSN, VOIDmode, 0, NULL_RTX, NULL_RTX, + NULL_RTX, 0, NULL_RTX, 0); + + /* Initialize the unused_*_lists. We can't use the ones left over from + the previous function, because gcc has freed that memory. We can use + the ones left over from the first sched pass in the second pass however, + so only clear them on the first sched pass. The first pass is before + reload if flag_schedule_insns is set, otherwise it is afterwards. */ + + if (reload_completed == 0 || ! flag_schedule_insns) + { + unused_insn_list = 0; + unused_expr_list = 0; + } + + /* We create no insns here, only reorder them, so we + remember how far we can cut back the stack on exit. */ + + /* Allocate data for this pass. See comments, above, + for what these vectors do. */ + insn_luid = (int *) alloca (max_uid * sizeof (int)); + insn_priority = (int *) alloca (max_uid * sizeof (int)); + insn_tick = (int *) alloca (max_uid * sizeof (int)); + insn_costs = (short *) alloca (max_uid * sizeof (short)); + insn_units = (short *) alloca (max_uid * sizeof (short)); + insn_blockage = (unsigned int *) alloca (max_uid * sizeof (unsigned int)); + insn_ref_count = (int *) alloca (max_uid * sizeof (int)); + + if (reload_completed == 0) + { + sched_reg_n_deaths = (short *) alloca (max_regno * sizeof (short)); + sched_reg_n_calls_crossed = (int *) alloca (max_regno * sizeof (int)); + sched_reg_live_length = (int *) alloca (max_regno * sizeof (int)); + bb_dead_regs = (regset) alloca (regset_bytes); + bb_live_regs = (regset) alloca (regset_bytes); + bzero (sched_reg_n_calls_crossed, max_regno * sizeof (int)); + bzero (sched_reg_live_length, max_regno * sizeof (int)); + bcopy (reg_n_deaths, sched_reg_n_deaths, max_regno * sizeof (short)); + init_alias_analysis (); + } + else + { + sched_reg_n_deaths = 0; + sched_reg_n_calls_crossed = 0; + sched_reg_live_length = 0; + bb_dead_regs = 0; + bb_live_regs = 0; + if (! flag_schedule_insns) + init_alias_analysis (); + } + + if (write_symbols != NO_DEBUG) + { + rtx line; + + line_note = (rtx *) alloca (max_uid * sizeof (rtx)); + bzero (line_note, max_uid * sizeof (rtx)); + line_note_head = (rtx *) alloca (n_basic_blocks * sizeof (rtx)); + bzero (line_note_head, n_basic_blocks * sizeof (rtx)); + + /* Determine the line-number at the start of each basic block. + This must be computed and saved now, because after a basic block's + predecessor has been scheduled, it is impossible to accurately + determine the correct line number for the first insn of the block. */ + + for (b = 0; b < n_basic_blocks; b++) + for (line = basic_block_head[b]; line; line = PREV_INSN (line)) + if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) + { + line_note_head[b] = line; + break; + } + } + + bzero (insn_luid, max_uid * sizeof (int)); + bzero (insn_priority, max_uid * sizeof (int)); + bzero (insn_tick, max_uid * sizeof (int)); + bzero (insn_costs, max_uid * sizeof (short)); + bzero (insn_units, max_uid * sizeof (short)); + bzero (insn_blockage, max_uid * sizeof (unsigned int)); + bzero (insn_ref_count, max_uid * sizeof (int)); + + /* Schedule each basic block, block by block. */ + + if (NEXT_INSN (basic_block_end[n_basic_blocks-1]) == 0 + || (GET_CODE (basic_block_end[n_basic_blocks-1]) != NOTE + && GET_CODE (basic_block_end[n_basic_blocks-1]) != CODE_LABEL)) + emit_note_after (NOTE_INSN_DELETED, basic_block_end[n_basic_blocks-1]); + + for (b = 0; b < n_basic_blocks; b++) + { + rtx insn, next; + rtx insns; + + note_list = 0; + + for (insn = basic_block_head[b]; ; insn = next) + { + rtx prev; + rtx set; + + /* Can't use `next_real_insn' because that + might go across CODE_LABELS and short-out basic blocks. */ + next = NEXT_INSN (insn); + if (GET_CODE (insn) != INSN) + { + if (insn == basic_block_end[b]) + break; + + continue; + } + + /* Don't split no-op move insns. These should silently disappear + later in final. Splitting such insns would break the code + that handles REG_NO_CONFLICT blocks. */ + set = single_set (insn); + if (set && rtx_equal_p (SET_SRC (set), SET_DEST (set))) + { + if (insn == basic_block_end[b]) + break; + + /* Nops get in the way while scheduling, so delete them now if + register allocation has already been done. It is too risky + to try to do this before register allocation, and there are + unlikely to be very many nops then anyways. */ + if (reload_completed) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + + continue; + } + + /* Split insns here to get max fine-grain parallelism. */ + prev = PREV_INSN (insn); + if (reload_completed == 0) + { + rtx last, first = PREV_INSN (insn); + rtx notes = REG_NOTES (insn); + + last = try_split (PATTERN (insn), insn, 1); + if (last != insn) + { + /* try_split returns the NOTE that INSN became. */ + first = NEXT_INSN (first); + update_flow_info (notes, first, last, insn); + + PUT_CODE (insn, NOTE); + NOTE_SOURCE_FILE (insn) = 0; + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + if (insn == basic_block_head[b]) + basic_block_head[b] = first; + if (insn == basic_block_end[b]) + { + basic_block_end[b] = last; + break; + } + } + } + + if (insn == basic_block_end[b]) + break; + } + + schedule_block (b, dump_file); + +#ifdef USE_C_ALLOCA + alloca (0); +#endif + } + + /* Reposition the prologue and epilogue notes in case we moved the + prologue/epilogue insns. */ + if (reload_completed) + reposition_prologue_and_epilogue_notes (get_insns ()); + + if (write_symbols != NO_DEBUG) + { + rtx line = 0; + rtx insn = get_insns (); + int active_insn = 0; + int notes = 0; + + /* Walk the insns deleting redundant line-number notes. Many of these + are already present. The remainder tend to occur at basic + block boundaries. */ + for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) + if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) + { + /* If there are no active insns following, INSN is redundant. */ + if (active_insn == 0) + { + notes++; + NOTE_SOURCE_FILE (insn) = 0; + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + } + /* If the line number is unchanged, LINE is redundant. */ + else if (line + && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn) + && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn)) + { + notes++; + NOTE_SOURCE_FILE (line) = 0; + NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED; + line = insn; + } + else + line = insn; + active_insn = 0; + } + else if (! ((GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) + || (GET_CODE (insn) == INSN + && (GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER)))) + active_insn++; + + if (dump_file && notes) + fprintf (dump_file, ";; deleted %d line-number notes\n", notes); + } + + if (reload_completed == 0) + { + int regno; + for (regno = 0; regno < max_regno; regno++) + if (sched_reg_live_length[regno]) + { + if (dump_file) + { + if (reg_live_length[regno] > sched_reg_live_length[regno]) + fprintf (dump_file, + ";; register %d life shortened from %d to %d\n", + regno, reg_live_length[regno], + sched_reg_live_length[regno]); + /* Negative values are special; don't overwrite the current + reg_live_length value if it is negative. */ + else if (reg_live_length[regno] < sched_reg_live_length[regno] + && reg_live_length[regno] >= 0) + fprintf (dump_file, + ";; register %d life extended from %d to %d\n", + regno, reg_live_length[regno], + sched_reg_live_length[regno]); + + if (reg_n_calls_crossed[regno] + && ! sched_reg_n_calls_crossed[regno]) + fprintf (dump_file, + ";; register %d no longer crosses calls\n", regno); + else if (! reg_n_calls_crossed[regno] + && sched_reg_n_calls_crossed[regno]) + fprintf (dump_file, + ";; register %d now crosses calls\n", regno); + } + /* Negative values are special; don't overwrite the current + reg_live_length value if it is negative. */ + if (reg_live_length[regno] >= 0) + reg_live_length[regno] = sched_reg_live_length[regno]; + reg_n_calls_crossed[regno] = sched_reg_n_calls_crossed[regno]; + } + } +} +#endif /* INSN_SCHEDULING */ diff --git a/gnu/usr.bin/cc/lib/sdbout.c b/gnu/usr.bin/cc/lib/sdbout.c new file mode 100644 index 000000000000..a08230dc94a2 --- /dev/null +++ b/gnu/usr.bin/cc/lib/sdbout.c @@ -0,0 +1,1484 @@ +/* Output sdb-format symbol table information from GNU compiler. + Copyright (C) 1988, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* mike@tredysvr.Tredydev.Unisys.COM says: +I modified the struct.c example and have a nm of a .o resulting from the +AT&T C compiler. From the example below I would conclude the following: + +1. All .defs from structures are emitted as scanned. The example below + clearly shows the symbol table entries for BoxRec2 are after the first + function. + +2. All functions and their locals (including statics) are emitted as scanned. + +3. All nested unnamed union and structure .defs must be emitted before + the structure in which they are nested. The AT&T assembler is a + one pass beast as far as symbolics are concerned. + +4. All structure .defs are emitted before the typedefs that refer to them. + +5. All top level static and external variable definitions are moved to the + end of file with all top level statics occurring first before externs. + +6. All undefined references are at the end of the file. +*/ + +#include "config.h" + +#ifdef SDB_DEBUGGING_INFO + +#include "tree.h" +#include "rtl.h" +#include +#include "regs.h" +#include "flags.h" +#include "insn-config.h" +#include "reload.h" + +/* Mips systems use the SDB functions to dump out symbols, but + do not supply usable syms.h include files. */ +#if defined(USG) && !defined(MIPS) && !defined (hpux) +#include +/* Use T_INT if we don't have T_VOID. */ +#ifndef T_VOID +#define T_VOID T_INT +#endif +#else /* not USG, or MIPS */ +#include "gsyms.h" +#endif /* not USG, or MIPS */ + +/* #include used to be this instead of syms.h. */ + +/* 1 if PARM is passed to this function in memory. */ + +#define PARM_PASSED_IN_MEMORY(PARM) \ + (GET_CODE (DECL_INCOMING_RTL (PARM)) == MEM) + +/* A C expression for the integer offset value of an automatic variable + (C_AUTO) having address X (an RTX). */ +#ifndef DEBUGGER_AUTO_OFFSET +#define DEBUGGER_AUTO_OFFSET(X) \ + (GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) +#endif + +/* A C expression for the integer offset value of an argument (C_ARG) + having address X (an RTX). The nominal offset is OFFSET. */ +#ifndef DEBUGGER_ARG_OFFSET +#define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET) +#endif + +/* Line number of beginning of current function, minus one. + Negative means not in a function or not using sdb. */ + +int sdb_begin_function_line = -1; + +/* Counter to generate unique "names" for nameless struct members. */ + +static int unnamed_struct_number = 0; + +extern FILE *asm_out_file; + +extern tree current_function_decl; + +void sdbout_init (); +void sdbout_symbol (); +void sdbout_types(); + +static void sdbout_typedefs (); +static void sdbout_syms (); +static void sdbout_one_type (); +static void sdbout_queue_anonymous_type (); +static void sdbout_dequeue_anonymous_types (); +static int plain_type_1 (); + +/* Define the default sizes for various types. */ + +#ifndef CHAR_TYPE_SIZE +#define CHAR_TYPE_SIZE BITS_PER_UNIT +#endif + +#ifndef SHORT_TYPE_SIZE +#define SHORT_TYPE_SIZE (BITS_PER_UNIT * MIN ((UNITS_PER_WORD + 1) / 2, 2)) +#endif + +#ifndef INT_TYPE_SIZE +#define INT_TYPE_SIZE BITS_PER_WORD +#endif + +#ifndef LONG_TYPE_SIZE +#define LONG_TYPE_SIZE BITS_PER_WORD +#endif + +#ifndef LONG_LONG_TYPE_SIZE +#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) +#endif + +#ifndef FLOAT_TYPE_SIZE +#define FLOAT_TYPE_SIZE BITS_PER_WORD +#endif + +#ifndef DOUBLE_TYPE_SIZE +#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) +#endif + +#ifndef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) +#endif + +/* Random macros describing parts of SDB data. */ + +/* Put something here if lines get too long */ +#define CONTIN + +/* Default value of delimiter is ";". */ +#ifndef SDB_DELIM +#define SDB_DELIM ";" +#endif + +/* Maximum number of dimensions the assembler will allow. */ +#ifndef SDB_MAX_DIM +#define SDB_MAX_DIM 4 +#endif + +#ifndef PUT_SDB_SCL +#define PUT_SDB_SCL(a) fprintf(asm_out_file, "\t.scl\t%d%s", (a), SDB_DELIM) +#endif + +#ifndef PUT_SDB_INT_VAL +#define PUT_SDB_INT_VAL(a) fprintf (asm_out_file, "\t.val\t%d%s", (a), SDB_DELIM) +#endif + +#ifndef PUT_SDB_VAL +#define PUT_SDB_VAL(a) \ +( fputs ("\t.val\t", asm_out_file), \ + output_addr_const (asm_out_file, (a)), \ + fprintf (asm_out_file, SDB_DELIM)) +#endif + +#ifndef PUT_SDB_DEF +#define PUT_SDB_DEF(a) \ +do { fprintf (asm_out_file, "\t.def\t"); \ + ASM_OUTPUT_LABELREF (asm_out_file, a); \ + fprintf (asm_out_file, SDB_DELIM); } while (0) +#endif + +#ifndef PUT_SDB_PLAIN_DEF +#define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\t.def\t.%s%s",a, SDB_DELIM) +#endif + +#ifndef PUT_SDB_ENDEF +#define PUT_SDB_ENDEF fputs("\t.endef\n", asm_out_file) +#endif + +#ifndef PUT_SDB_TYPE +#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0%o%s", a, SDB_DELIM) +#endif + +#ifndef PUT_SDB_SIZE +#define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\t.size\t%d%s", a, SDB_DELIM) +#endif + +#ifndef PUT_SDB_START_DIM +#define PUT_SDB_START_DIM fprintf(asm_out_file, "\t.dim\t") +#endif + +#ifndef PUT_SDB_NEXT_DIM +#define PUT_SDB_NEXT_DIM(a) fprintf(asm_out_file, "%d,", a) +#endif + +#ifndef PUT_SDB_LAST_DIM +#define PUT_SDB_LAST_DIM(a) fprintf(asm_out_file, "%d%s", a, SDB_DELIM) +#endif + +#ifndef PUT_SDB_TAG +#define PUT_SDB_TAG(a) \ +do { fprintf (asm_out_file, "\t.tag\t"); \ + ASM_OUTPUT_LABELREF (asm_out_file, a); \ + fprintf (asm_out_file, SDB_DELIM); } while (0) +#endif + +#ifndef PUT_SDB_BLOCK_START +#define PUT_SDB_BLOCK_START(LINE) \ + fprintf (asm_out_file, \ + "\t.def\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \ + SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) +#endif + +#ifndef PUT_SDB_BLOCK_END +#define PUT_SDB_BLOCK_END(LINE) \ + fprintf (asm_out_file, \ + "\t.def\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \ + SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) +#endif + +#ifndef PUT_SDB_FUNCTION_START +#define PUT_SDB_FUNCTION_START(LINE) \ + fprintf (asm_out_file, \ + "\t.def\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \ + SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) +#endif + +#ifndef PUT_SDB_FUNCTION_END +#define PUT_SDB_FUNCTION_END(LINE) \ + fprintf (asm_out_file, \ + "\t.def\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \ + SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) +#endif + +#ifndef PUT_SDB_EPILOGUE_END +#define PUT_SDB_EPILOGUE_END(NAME) \ +do { fprintf (asm_out_file, "\t.def\t"); \ + ASM_OUTPUT_LABELREF (asm_out_file, NAME); \ + fprintf (asm_out_file, \ + "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \ + SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0) +#endif + +#ifndef SDB_GENERATE_FAKE +#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ + sprintf ((BUFFER), ".%dfake", (NUMBER)); +#endif + +/* Return the sdb tag identifier string for TYPE + if TYPE has already been defined; otherwise return a null pointer. */ + +#define KNOWN_TYPE_TAG(type) (char *)(TYPE_SYMTAB_ADDRESS (type)) + +/* Set the sdb tag identifier string for TYPE to NAME. */ + +#define SET_KNOWN_TYPE_TAG(TYPE, NAME) \ + (TYPE_SYMTAB_ADDRESS (TYPE) = (int)(NAME)) + +/* Return the name (a string) of the struct, union or enum tag + described by the TREE_LIST node LINK. This is 0 for an anonymous one. */ + +#define TAG_NAME(link) \ + (((link) && TREE_PURPOSE ((link)) \ + && IDENTIFIER_POINTER (TREE_PURPOSE ((link)))) \ + ? IDENTIFIER_POINTER (TREE_PURPOSE ((link))) : (char *) 0) + +/* Ensure we don't output a negative line number. */ +#define MAKE_LINE_SAFE(line) \ + if (line <= sdb_begin_function_line) line = sdb_begin_function_line + 1 + +/* Set up for SDB output at the start of compilation. */ + +void +sdbout_init (asm_file, input_file_name, syms) + FILE *asm_file; + char *input_file_name; + tree syms; +{ +#if 0 /* Nothing need be output for the predefined types. */ + /* Get all permanent types that have typedef names, + and output them all, except for those already output. */ + + sdbout_typedefs (syms); +#endif +} + +#if 0 + +/* return the tag identifier for type + */ + +char * +tag_of_ru_type (type,link) + tree type,link; +{ + if (TYPE_SYMTAB_ADDRESS (type)) + return (char *)TYPE_SYMTAB_ADDRESS (type); + if (link && TREE_PURPOSE (link) + && IDENTIFIER_POINTER (TREE_PURPOSE (link))) + TYPE_SYMTAB_ADDRESS (type) + = (int)IDENTIFIER_POINTER (TREE_PURPOSE (link)); + else + return (char *) TYPE_SYMTAB_ADDRESS (type); +} +#endif + +/* Return a unique string to name an anonymous type. */ + +static char * +gen_fake_label () +{ + char label[10]; + char *labelstr; + SDB_GENERATE_FAKE (label, unnamed_struct_number); + unnamed_struct_number++; + labelstr = (char *) permalloc (strlen (label) + 1); + strcpy (labelstr, label); + return labelstr; +} + +/* Return the number which describes TYPE for SDB. + For pointers, etc., this function is recursive. + Each record, union or enumeral type must already have had a + tag number output. */ + +/* The number is given by d6d5d4d3d2d1bbbb + where bbbb is 4 bit basic type, and di indicate one of notype,ptr,fn,array. + Thus, char *foo () has bbbb=T_CHAR + d1=D_FCN + d2=D_PTR + N_BTMASK= 017 1111 basic type field. + N_TSHIFT= 2 derived type shift + N_BTSHFT= 4 Basic type shift */ + +/* Produce the number that describes a pointer, function or array type. + PREV is the number describing the target, value or element type. + DT_type describes how to transform that type. */ +#define PUSH_DERIVED_LEVEL(DT_type,PREV) \ + ((((PREV) & ~(int)N_BTMASK) << (int)N_TSHIFT) \ + | ((int)DT_type << (int)N_BTSHFT) \ + | ((PREV) & (int)N_BTMASK)) + +/* Number of elements used in sdb_dims. */ +static int sdb_n_dims = 0; + +/* Table of array dimensions of current type. */ +static int sdb_dims[SDB_MAX_DIM]; + +/* Size of outermost array currently being processed. */ +static int sdb_type_size = -1; + +static int +plain_type (type) + tree type; +{ + int val = plain_type_1 (type); + + /* If we have already saved up some array dimensions, print them now. */ + if (sdb_n_dims > 0) + { + int i; + PUT_SDB_START_DIM; + for (i = sdb_n_dims - 1; i > 0; i--) + PUT_SDB_NEXT_DIM (sdb_dims[i]); + PUT_SDB_LAST_DIM (sdb_dims[0]); + sdb_n_dims = 0; + + sdb_type_size = int_size_in_bytes (type); + /* Don't kill sdb if type is not laid out or has variable size. */ + if (sdb_type_size < 0) + sdb_type_size = 0; + } + /* If we have computed the size of an array containing this type, + print it now. */ + if (sdb_type_size >= 0) + { + PUT_SDB_SIZE (sdb_type_size); + sdb_type_size = -1; + } + return val; +} + +static int +template_name_p (name) + tree name; +{ + register char *ptr = IDENTIFIER_POINTER (name); + while (*ptr && *ptr != '<') + ptr++; + + return *ptr != '\0'; +} + +static void +sdbout_record_type_name (type) + tree type; +{ + char *name = 0; + int no_name; + + if (KNOWN_TYPE_TAG (type)) + return; + + if (TYPE_NAME (type) != 0) + { + tree t = 0; + /* Find the IDENTIFIER_NODE for the type name. */ + if (TREE_CODE (TYPE_NAME (type)) == IDENTIFIER_NODE) + { + t = TYPE_NAME (type); + } +#if 1 /* As a temporary hack, use typedef names for C++ only. */ + else if (TREE_CODE (TYPE_NAME (type)) == TYPE_DECL + && TYPE_LANG_SPECIFIC (type)) + { + t = DECL_NAME (TYPE_NAME (type)); + /* The DECL_NAME for templates includes "<>", which breaks + most assemblers. Use its assembler name instead, which + has been mangled into being safe. */ + if (t && template_name_p (t)) + t = DECL_ASSEMBLER_NAME (TYPE_NAME (type)); + } +#endif + + /* Now get the name as a string, or invent one. */ + if (t != NULL_TREE) + name = IDENTIFIER_POINTER (t); + } + + no_name = (name == 0 || *name == 0); + if (no_name) + name = gen_fake_label (); + + SET_KNOWN_TYPE_TAG (type, name); +#ifdef SDB_ALLOW_FORWARD_REFERENCES + if (no_name) + sdbout_queue_anonymous_type (type); +#endif +} + +static int +plain_type_1 (type) + tree type; +{ + if (type == 0) + type = void_type_node; + if (type == error_mark_node) + type = integer_type_node; + type = TYPE_MAIN_VARIANT (type); + + switch (TREE_CODE (type)) + { + case VOID_TYPE: + return T_VOID; + case INTEGER_TYPE: + { + int size = int_size_in_bytes (type) * BITS_PER_UNIT; + + /* Carefully distinguish all the standard types of C, + without messing up if the language is not C. + Note that we check only for the names that contain spaces; + other names might occur by coincidence in other languages. */ + if (TYPE_NAME (type) != 0 + && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL + && DECL_NAME (TYPE_NAME (type)) != 0 + && TREE_CODE (DECL_NAME (TYPE_NAME (type))) == IDENTIFIER_NODE) + { + char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))); + + if (!strcmp (name, "unsigned char")) + return T_UCHAR; + if (!strcmp (name, "signed char")) + return T_CHAR; + if (!strcmp (name, "unsigned int")) + return T_UINT; + if (!strcmp (name, "short int")) + return T_SHORT; + if (!strcmp (name, "short unsigned int")) + return T_USHORT; + if (!strcmp (name, "long int")) + return T_LONG; + if (!strcmp (name, "long unsigned int")) + return T_ULONG; + } + + if (size == CHAR_TYPE_SIZE) + return (TREE_UNSIGNED (type) ? T_UCHAR : T_CHAR); + if (size == SHORT_TYPE_SIZE) + return (TREE_UNSIGNED (type) ? T_USHORT : T_SHORT); + if (size == INT_TYPE_SIZE) + return (TREE_UNSIGNED (type) ? T_UINT : T_INT); + if (size == LONG_TYPE_SIZE) + return (TREE_UNSIGNED (type) ? T_ULONG : T_LONG); + return 0; + } + + case REAL_TYPE: + { + int size = int_size_in_bytes (type) * BITS_PER_UNIT; + if (size == FLOAT_TYPE_SIZE) + return T_FLOAT; + if (size == DOUBLE_TYPE_SIZE) + return T_DOUBLE; + return 0; + } + + case ARRAY_TYPE: + { + int m; + m = plain_type_1 (TREE_TYPE (type)); + if (sdb_n_dims < SDB_MAX_DIM) + sdb_dims[sdb_n_dims++] + = (TYPE_DOMAIN (type) + ? TREE_INT_CST_LOW (TYPE_MAX_VALUE (TYPE_DOMAIN (type))) + 1 + : 0); + return PUSH_DERIVED_LEVEL (DT_ARY, m); + } + + case RECORD_TYPE: + case UNION_TYPE: + case QUAL_UNION_TYPE: + case ENUMERAL_TYPE: + { + char *tag; +#ifdef SDB_ALLOW_FORWARD_REFERENCES + sdbout_record_type_name (type); +#endif +#ifndef SDB_ALLOW_UNKNOWN_REFERENCES + if ((TREE_ASM_WRITTEN (type) && KNOWN_TYPE_TAG (type) != 0) +#ifdef SDB_ALLOW_FORWARD_REFERENCES + || TYPE_MODE (type) != VOIDmode +#endif + ) +#endif + { + /* Output the referenced structure tag name + only if the .def has already been finished. + At least on 386, the Unix assembler + cannot handle forward references to tags. */ + /* But the 88100, it requires them, sigh... */ + /* And the MIPS requires unknown refs as well... */ + tag = KNOWN_TYPE_TAG (type); + PUT_SDB_TAG (tag); + /* These 3 lines used to follow the close brace. + However, a size of 0 without a tag implies a tag of 0, + so if we don't know a tag, we can't mention the size. */ + sdb_type_size = int_size_in_bytes (type); + if (sdb_type_size < 0) + sdb_type_size = 0; + } + return ((TREE_CODE (type) == RECORD_TYPE) ? T_STRUCT + : (TREE_CODE (type) == UNION_TYPE) ? T_UNION + : (TREE_CODE (type) == QUAL_UNION_TYPE) ? T_UNION + : T_ENUM); + } + case POINTER_TYPE: + case REFERENCE_TYPE: + { + int m = plain_type_1 (TREE_TYPE (type)); + return PUSH_DERIVED_LEVEL (DT_PTR, m); + } + case FUNCTION_TYPE: + case METHOD_TYPE: + { + int m = plain_type_1 (TREE_TYPE (type)); + return PUSH_DERIVED_LEVEL (DT_FCN, m); + } + default: + return 0; + } +} + +/* Output the symbols defined in block number DO_BLOCK. + Set NEXT_BLOCK_NUMBER to 0 before calling. + + This function works by walking the tree structure of blocks, + counting blocks until it finds the desired block. */ + +static int do_block = 0; + +static int next_block_number; + +static void +sdbout_block (block) + register tree block; +{ + while (block) + { + /* Ignore blocks never expanded or otherwise marked as real. */ + if (TREE_USED (block)) + { + /* When we reach the specified block, output its symbols. */ + if (next_block_number == do_block) + { + sdbout_syms (BLOCK_VARS (block)); + } + + /* If we are past the specified block, stop the scan. */ + if (next_block_number > do_block) + return; + + next_block_number++; + + /* Scan the blocks within this block. */ + sdbout_block (BLOCK_SUBBLOCKS (block)); + } + + block = BLOCK_CHAIN (block); + } +} + +/* Call sdbout_symbol on each decl in the chain SYMS. */ + +static void +sdbout_syms (syms) + tree syms; +{ + while (syms) + { + if (TREE_CODE (syms) != LABEL_DECL) + sdbout_symbol (syms, 1); + syms = TREE_CHAIN (syms); + } +} + +/* Output SDB information for a symbol described by DECL. + LOCAL is nonzero if the symbol is not file-scope. */ + +void +sdbout_symbol (decl, local) + tree decl; + int local; +{ + int letter = 0; + tree type = TREE_TYPE (decl); + tree context = NULL_TREE; + rtx value; + int regno = -1; + char *name; + + sdbout_one_type (type); + +#if 0 /* This loses when functions are marked to be ignored, + which happens in the C++ front end. */ + if (DECL_IGNORED_P (decl)) + return; +#endif + + switch (TREE_CODE (decl)) + { + case CONST_DECL: + /* Enum values are defined by defining the enum type. */ + return; + + case FUNCTION_DECL: + /* Don't mention a nested function under its parent. */ + context = decl_function_context (decl); + if (context == current_function_decl) + return; + if (DECL_EXTERNAL (decl)) + return; + if (GET_CODE (DECL_RTL (decl)) != MEM + || GET_CODE (XEXP (DECL_RTL (decl), 0)) != SYMBOL_REF) + return; + PUT_SDB_DEF (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); + PUT_SDB_VAL (XEXP (DECL_RTL (decl), 0)); + PUT_SDB_SCL (TREE_PUBLIC (decl) ? C_EXT : C_STAT); + break; + + case TYPE_DECL: + /* Done with tagged types. */ + if (DECL_NAME (decl) == 0) + return; + if (DECL_IGNORED_P (decl)) + return; + + /* Output typedef name. */ + if (template_name_p (DECL_NAME (decl))) + PUT_SDB_DEF (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); + else + PUT_SDB_DEF (IDENTIFIER_POINTER (DECL_NAME (decl))); + PUT_SDB_SCL (C_TPDEF); + break; + + case PARM_DECL: + /* Parm decls go in their own separate chains + and are output by sdbout_reg_parms and sdbout_parms. */ + abort (); + + case VAR_DECL: + /* Don't mention a variable that is external. + Let the file that defines it describe it. */ + if (DECL_EXTERNAL (decl)) + return; + + /* Ignore __FUNCTION__, etc. */ + if (DECL_IGNORED_P (decl)) + return; + + /* If there was an error in the declaration, don't dump core + if there is no RTL associated with the variable doesn't + exist. */ + if (DECL_RTL (decl) == 0) + return; + + DECL_RTL (decl) = eliminate_regs (DECL_RTL (decl), 0, NULL_RTX); +#ifdef LEAF_REG_REMAP + if (leaf_function) + leaf_renumber_regs_insn (DECL_RTL (decl)); +#endif + value = DECL_RTL (decl); + + /* Don't mention a variable at all + if it was completely optimized into nothingness. + + If DECL was from an inline function, then its rtl + is not identically the rtl that was used in this + particular compilation. */ + if (GET_CODE (value) == REG) + { + regno = REGNO (DECL_RTL (decl)); + if (regno >= FIRST_PSEUDO_REGISTER) + return; + } + else if (GET_CODE (value) == SUBREG) + { + int offset = 0; + while (GET_CODE (value) == SUBREG) + { + offset += SUBREG_WORD (value); + value = SUBREG_REG (value); + } + if (GET_CODE (value) == REG) + { + regno = REGNO (value); + if (regno >= FIRST_PSEUDO_REGISTER) + return; + regno += offset; + } + alter_subreg (DECL_RTL (decl)); + value = DECL_RTL (decl); + } + + /* Emit any structure, union, or enum type that has not been output. + This occurs for tag-less structs (et al) used to declare variables + within functions. */ + if (TREE_CODE (type) == ENUMERAL_TYPE + || TREE_CODE (type) == RECORD_TYPE + || TREE_CODE (type) == UNION_TYPE + || TREE_CODE (type) == QUAL_UNION_TYPE) + { + if (TYPE_SIZE (type) != 0 /* not a forward reference */ + && KNOWN_TYPE_TAG (type) == 0) /* not yet declared */ + sdbout_one_type (type); + } + + /* Defer SDB information for top-level initialized variables! */ + if (! local + && GET_CODE (value) == MEM + && DECL_INITIAL (decl)) + return; + + /* C++ in 2.3 makes nameless symbols. That will be fixed later. + For now, avoid crashing. */ + if (DECL_NAME (decl) == NULL_TREE) + return; + + /* Record the name for, starting a symtab entry. */ + name = IDENTIFIER_POINTER (DECL_NAME (decl)); + + if (GET_CODE (value) == MEM + && GET_CODE (XEXP (value, 0)) == SYMBOL_REF) + { + PUT_SDB_DEF (name); + if (TREE_PUBLIC (decl)) + { + PUT_SDB_VAL (XEXP (value, 0)); + PUT_SDB_SCL (C_EXT); + } + else + { + PUT_SDB_VAL (XEXP (value, 0)); + PUT_SDB_SCL (C_STAT); + } + } + else if (regno >= 0) + { + PUT_SDB_DEF (name); + PUT_SDB_INT_VAL (DBX_REGISTER_NUMBER (regno)); + PUT_SDB_SCL (C_REG); + } + else if (GET_CODE (value) == MEM + && (GET_CODE (XEXP (value, 0)) == MEM + || (GET_CODE (XEXP (value, 0)) == REG + && REGNO (XEXP (value, 0)) != FRAME_POINTER_REGNUM + && REGNO (XEXP (value, 0)) != STACK_POINTER_REGNUM))) + /* If the value is indirect by memory or by a register + that isn't the frame pointer + then it means the object is variable-sized and address through + that register or stack slot. COFF has no way to represent this + so all we can do is output the variable as a pointer. */ + { + PUT_SDB_DEF (name); + if (GET_CODE (XEXP (value, 0)) == REG) + { + PUT_SDB_INT_VAL (DBX_REGISTER_NUMBER (REGNO (XEXP (value, 0)))); + PUT_SDB_SCL (C_REG); + } + else + { + /* DECL_RTL looks like (MEM (MEM (PLUS (REG...) + (CONST_INT...)))). + We want the value of that CONST_INT. */ + /* Encore compiler hates a newline in a macro arg, it seems. */ + PUT_SDB_INT_VAL (DEBUGGER_AUTO_OFFSET + (XEXP (XEXP (value, 0), 0))); + PUT_SDB_SCL (C_AUTO); + } + + type = build_pointer_type (TREE_TYPE (decl)); + } + else if (GET_CODE (value) == MEM + && GET_CODE (XEXP (value, 0)) == PLUS + && GET_CODE (XEXP (XEXP (value, 0), 0)) == REG + && GET_CODE (XEXP (XEXP (value, 0), 1)) == CONST_INT) + { + /* DECL_RTL looks like (MEM (PLUS (REG...) (CONST_INT...))). + We want the value of that CONST_INT. */ + PUT_SDB_DEF (name); + PUT_SDB_INT_VAL (DEBUGGER_AUTO_OFFSET (XEXP (value, 0))); + PUT_SDB_SCL (C_AUTO); + } + else if (GET_CODE (value) == MEM && GET_CODE (XEXP (value, 0)) == CONST) + { + /* Handle an obscure case which can arise when optimizing and + when there are few available registers. (This is *always* + the case for i386/i486 targets). The DECL_RTL looks like + (MEM (CONST ...)) even though this variable is a local `auto' + or a local `register' variable. In effect, what has happened + is that the reload pass has seen that all assignments and + references for one such a local variable can be replaced by + equivalent assignments and references to some static storage + variable, thereby avoiding the need for a register. In such + cases we're forced to lie to debuggers and tell them that + this variable was itself `static'. */ + PUT_SDB_DEF (name); + PUT_SDB_VAL (XEXP (XEXP (value, 0), 0)); + PUT_SDB_SCL (C_STAT); + } + else + { + /* It is something we don't know how to represent for SDB. */ + return; + } + break; + } + PUT_SDB_TYPE (plain_type (type)); + PUT_SDB_ENDEF; +} + +/* Output SDB information for a top-level initialized variable + that has been delayed. */ + +void +sdbout_toplevel_data (decl) + tree decl; +{ + tree type = TREE_TYPE (decl); + + if (DECL_IGNORED_P (decl)) + return; + + if (! (TREE_CODE (decl) == VAR_DECL + && GET_CODE (DECL_RTL (decl)) == MEM + && DECL_INITIAL (decl))) + abort (); + + PUT_SDB_DEF (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); + PUT_SDB_VAL (XEXP (DECL_RTL (decl), 0)); + if (TREE_PUBLIC (decl)) + { + PUT_SDB_SCL (C_EXT); + } + else + { + PUT_SDB_SCL (C_STAT); + } + PUT_SDB_TYPE (plain_type (type)); + PUT_SDB_ENDEF; +} + +#ifdef SDB_ALLOW_FORWARD_REFERENCES + +/* Machinery to record and output anonymous types. */ + +static tree anonymous_types; + +static void +sdbout_queue_anonymous_type (type) + tree type; +{ + anonymous_types = saveable_tree_cons (NULL_TREE, type, anonymous_types); +} + +static void +sdbout_dequeue_anonymous_types () +{ + register tree types, link; + + while (anonymous_types) + { + types = nreverse (anonymous_types); + anonymous_types = NULL_TREE; + + for (link = types; link; link = TREE_CHAIN (link)) + { + register tree type = TREE_VALUE (link); + + if (type && ! TREE_ASM_WRITTEN (type)) + sdbout_one_type (type); + } + } +} + +#endif + +/* Given a chain of ..._TYPE nodes, all of which have names, + output definitions of those names, as typedefs. */ + +void +sdbout_types (types) + register tree types; +{ + register tree link; + + for (link = types; link; link = TREE_CHAIN (link)) + sdbout_one_type (link); + +#ifdef SDB_ALLOW_FORWARD_REFERENCES + sdbout_dequeue_anonymous_types (); +#endif +} + +static void +sdbout_type (type) + tree type; +{ + register tree tem; + if (type == error_mark_node) + type = integer_type_node; + PUT_SDB_TYPE (plain_type (type)); +} + +/* Output types of the fields of type TYPE, if they are structs. + + Formerly did not chase through pointer types, since that could be circular. + They must come before TYPE, since forward refs are not allowed. + Now james@bigtex.cactus.org says to try them. */ + +static void +sdbout_field_types (type) + tree type; +{ + tree tail; + for (tail = TYPE_FIELDS (type); tail; tail = TREE_CHAIN (tail)) + if (TREE_CODE (TREE_TYPE (tail)) == POINTER_TYPE) + sdbout_one_type (TREE_TYPE (TREE_TYPE (tail))); + else + sdbout_one_type (TREE_TYPE (tail)); +} + +/* Use this to put out the top level defined record and union types + for later reference. If this is a struct with a name, then put that + name out. Other unnamed structs will have .xxfake labels generated so + that they may be referred to later. + The label will be stored in the KNOWN_TYPE_TAG slot of a type. + It may NOT be called recursively. */ + +static void +sdbout_one_type (type) + tree type; +{ + text_section (); + + switch (TREE_CODE (type)) + { + case RECORD_TYPE: + case UNION_TYPE: + case QUAL_UNION_TYPE: + case ENUMERAL_TYPE: + type = TYPE_MAIN_VARIANT (type); + /* Don't output a type twice. */ + if (TREE_ASM_WRITTEN (type)) + /* James said test TREE_ASM_BEING_WRITTEN here. */ + return; + + /* Output nothing if type is not yet defined. */ + if (TYPE_SIZE (type) == 0) + return; + + TREE_ASM_WRITTEN (type) = 1; +#if 1 + /* This is reputed to cause trouble with the following case, + but perhaps checking TYPE_SIZE above will fix it. */ + + /* Here is a test case: + + struct foo { + struct badstr *bbb; + } forwardref; + + typedef struct intermediate { + int aaaa; + } intermediate_ref; + + typedef struct badstr { + int ccccc; + } badtype; */ + +#if 0 + TREE_ASM_BEING_WRITTEN (type) = 1; +#endif + /* This change, which ought to make better output, + used to make the COFF assembler unhappy. + Changes involving KNOWN_TYPE_TAG may fix the problem. */ + /* Before really doing anything, output types we want to refer to. */ + /* Note that in version 1 the following two lines + are not used if forward references are in use. */ + if (TREE_CODE (type) != ENUMERAL_TYPE) + sdbout_field_types (type); +#if 0 + TREE_ASM_WRITTEN (type) = 1; +#endif +#endif + + /* Output a structure type. */ + { + int size = int_size_in_bytes (type); + int member_scl; + tree tem; + int i, n_baseclasses = 0; + + /* Record the type tag, but not in its permanent place just yet. */ + sdbout_record_type_name (type); + + PUT_SDB_DEF (KNOWN_TYPE_TAG (type)); + + switch (TREE_CODE (type)) + { + case UNION_TYPE: + case QUAL_UNION_TYPE: + PUT_SDB_SCL (C_UNTAG); + PUT_SDB_TYPE (T_UNION); + member_scl = C_MOU; + break; + + case RECORD_TYPE: + PUT_SDB_SCL (C_STRTAG); + PUT_SDB_TYPE (T_STRUCT); + member_scl = C_MOS; + break; + + case ENUMERAL_TYPE: + PUT_SDB_SCL (C_ENTAG); + PUT_SDB_TYPE (T_ENUM); + member_scl = C_MOE; + break; + } + + PUT_SDB_SIZE (size); + PUT_SDB_ENDEF; + + /* Print out the base class information with fields + named after the types they hold. */ + if (TYPE_BINFO (type) + && TYPE_BINFO_BASETYPES (type)) + n_baseclasses = TREE_VEC_LENGTH (TYPE_BINFO_BASETYPES (type)); + for (i = 0; i < n_baseclasses; i++) + { + tree child = TREE_VEC_ELT (BINFO_BASETYPES (TYPE_BINFO (type)), i); + tree child_type = BINFO_TYPE (child); + tree child_type_name; + if (TYPE_NAME (child_type) == 0) + continue; + if (TREE_CODE (TYPE_NAME (child_type)) == IDENTIFIER_NODE) + child_type_name = TYPE_NAME (child_type); + else if (TREE_CODE (TYPE_NAME (child_type)) == TYPE_DECL) + child_type_name = DECL_NAME (TYPE_NAME (child_type)); + else + continue; + + CONTIN; + PUT_SDB_DEF (IDENTIFIER_POINTER (child_type_name)); + PUT_SDB_INT_VAL (TREE_INT_CST_LOW (BINFO_OFFSET (child))); + PUT_SDB_SCL (member_scl); + sdbout_type (BINFO_TYPE (child)); + PUT_SDB_ENDEF; + } + + /* output the individual fields */ + + if (TREE_CODE (type) == ENUMERAL_TYPE) + for (tem = TYPE_FIELDS (type); tem; tem = TREE_CHAIN (tem)) + { + PUT_SDB_DEF (IDENTIFIER_POINTER (TREE_PURPOSE (tem))); + PUT_SDB_INT_VAL (TREE_INT_CST_LOW (TREE_VALUE (tem))); + PUT_SDB_SCL (C_MOE); + PUT_SDB_TYPE (T_MOE); + PUT_SDB_ENDEF; + } + + else /* record or union type */ + for (tem = TYPE_FIELDS (type); tem; tem = TREE_CHAIN (tem)) + /* Output the name, type, position (in bits), size (in bits) + of each field. */ + + /* Omit here the nameless fields that are used to skip bits. + Also omit fields with variable size or position. + Also omit non FIELD_DECL nodes that GNU C++ may put here. */ + if (TREE_CODE (tem) == FIELD_DECL + && DECL_NAME (tem) != 0 + && TREE_CODE (DECL_SIZE (tem)) == INTEGER_CST + && TREE_CODE (DECL_FIELD_BITPOS (tem)) == INTEGER_CST) + { + CONTIN; + PUT_SDB_DEF (IDENTIFIER_POINTER (DECL_NAME (tem))); + if (DECL_BIT_FIELD_TYPE (tem)) + { + PUT_SDB_INT_VAL (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (tem))); + PUT_SDB_SCL (C_FIELD); + sdbout_type (DECL_BIT_FIELD_TYPE (tem)); + PUT_SDB_SIZE (TREE_INT_CST_LOW (DECL_SIZE (tem))); + } + else + { + PUT_SDB_INT_VAL (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (tem)) + / BITS_PER_UNIT); + PUT_SDB_SCL (member_scl); + sdbout_type (TREE_TYPE (tem)); + } + PUT_SDB_ENDEF; + } + /* output end of a structure,union, or enumeral definition */ + + PUT_SDB_PLAIN_DEF ("eos"); + PUT_SDB_INT_VAL (size); + PUT_SDB_SCL (C_EOS); + PUT_SDB_TAG (KNOWN_TYPE_TAG (type)); + PUT_SDB_SIZE (size); + PUT_SDB_ENDEF; + break; + } + } +} + +/* The following two functions output definitions of function parameters. + Each parameter gets a definition locating it in the parameter list. + Each parameter that is a register variable gets a second definition + locating it in the register. + + Printing or argument lists in gdb uses the definitions that + locate in the parameter list. But reference to the variable in + expressions uses preferentially the definition as a register. */ + +/* Output definitions, referring to storage in the parmlist, + of all the parms in PARMS, which is a chain of PARM_DECL nodes. */ + +static void +sdbout_parms (parms) + tree parms; +{ + for (; parms; parms = TREE_CHAIN (parms)) + if (DECL_NAME (parms)) + { + int current_sym_value = 0; + char *name = IDENTIFIER_POINTER (DECL_NAME (parms)); + + if (name == 0 || *name == 0) + name = gen_fake_label (); + + /* Perform any necessary register eliminations on the parameter's rtl, + so that the debugging output will be accurate. */ + DECL_INCOMING_RTL (parms) = + eliminate_regs (DECL_INCOMING_RTL (parms), 0, NULL_RTX); + DECL_RTL (parms) = eliminate_regs (DECL_RTL (parms), 0, NULL_RTX); + + if (PARM_PASSED_IN_MEMORY (parms)) + { + rtx addr = XEXP (DECL_INCOMING_RTL (parms), 0); + tree type; + + /* ??? Here we assume that the parm address is indexed + off the frame pointer or arg pointer. + If that is not true, we produce meaningless results, + but do not crash. */ + if (GET_CODE (addr) == PLUS + && GET_CODE (XEXP (addr, 1)) == CONST_INT) + current_sym_value = INTVAL (XEXP (addr, 1)); + else + current_sym_value = 0; + + if (GET_CODE (DECL_RTL (parms)) == REG + && REGNO (DECL_RTL (parms)) >= 0 + && REGNO (DECL_RTL (parms)) < FIRST_PSEUDO_REGISTER) + type = DECL_ARG_TYPE (parms); + else + { + int original_sym_value = current_sym_value; + + /* This is the case where the parm is passed as an int or + double and it is converted to a char, short or float + and stored back in the parmlist. In this case, describe + the parm with the variable's declared type, and adjust + the address if the least significant bytes (which we are + using) are not the first ones. */ +#if BYTES_BIG_ENDIAN + if (TREE_TYPE (parms) != DECL_ARG_TYPE (parms)) + current_sym_value += + (GET_MODE_SIZE (TYPE_MODE (DECL_ARG_TYPE (parms))) + - GET_MODE_SIZE (GET_MODE (DECL_RTL (parms)))); +#endif + if (GET_CODE (DECL_RTL (parms)) == MEM + && GET_CODE (XEXP (DECL_RTL (parms), 0)) == PLUS + && (GET_CODE (XEXP (XEXP (DECL_RTL (parms), 0), 1)) + == CONST_INT) + && (INTVAL (XEXP (XEXP (DECL_RTL (parms), 0), 1)) + == current_sym_value)) + type = TREE_TYPE (parms); + else + { + current_sym_value = original_sym_value; + type = DECL_ARG_TYPE (parms); + } + } + + PUT_SDB_DEF (name); + PUT_SDB_INT_VAL (DEBUGGER_ARG_OFFSET (current_sym_value, addr)); + PUT_SDB_SCL (C_ARG); + PUT_SDB_TYPE (plain_type (type)); + PUT_SDB_ENDEF; + } + else if (GET_CODE (DECL_RTL (parms)) == REG) + { + rtx best_rtl; + /* Parm passed in registers and lives in registers or nowhere. */ + + /* If parm lives in a register, use that register; + pretend the parm was passed there. It would be more consistent + to describe the register where the parm was passed, + but in practice that register usually holds something else. */ + if (REGNO (DECL_RTL (parms)) >= 0 + && REGNO (DECL_RTL (parms)) < FIRST_PSEUDO_REGISTER) + best_rtl = DECL_RTL (parms); + /* If the parm lives nowhere, + use the register where it was passed. */ + else + best_rtl = DECL_INCOMING_RTL (parms); + + PUT_SDB_DEF (name); + PUT_SDB_INT_VAL (DBX_REGISTER_NUMBER (REGNO (best_rtl))); + PUT_SDB_SCL (C_REGPARM); + PUT_SDB_TYPE (plain_type (TREE_TYPE (parms), 0)); + PUT_SDB_ENDEF; + } + else if (GET_CODE (DECL_RTL (parms)) == MEM + && XEXP (DECL_RTL (parms), 0) != const0_rtx) + { + /* Parm was passed in registers but lives on the stack. */ + + /* DECL_RTL looks like (MEM (PLUS (REG...) (CONST_INT...))), + in which case we want the value of that CONST_INT, + or (MEM (REG ...)) or (MEM (MEM ...)), + in which case we use a value of zero. */ + if (GET_CODE (XEXP (DECL_RTL (parms), 0)) == REG + || GET_CODE (XEXP (DECL_RTL (parms), 0)) == MEM) + current_sym_value = 0; + else + current_sym_value = INTVAL (XEXP (XEXP (DECL_RTL (parms), 0), 1)); + + /* Again, this assumes the offset is based on the arg pointer. */ + PUT_SDB_DEF (name); + PUT_SDB_INT_VAL (DEBUGGER_ARG_OFFSET (current_sym_value, + XEXP (DECL_RTL (parms), 0))); + PUT_SDB_SCL (C_ARG); + PUT_SDB_TYPE (plain_type (TREE_TYPE (parms), 0)); + PUT_SDB_ENDEF; + } + } +} + +/* Output definitions for the places where parms live during the function, + when different from where they were passed, when the parms were passed + in memory. + + It is not useful to do this for parms passed in registers + that live during the function in different registers, because it is + impossible to look in the passed register for the passed value, + so we use the within-the-function register to begin with. + + PARMS is a chain of PARM_DECL nodes. */ + +static void +sdbout_reg_parms (parms) + tree parms; +{ + for (; parms; parms = TREE_CHAIN (parms)) + if (DECL_NAME (parms)) + { + char *name = IDENTIFIER_POINTER (DECL_NAME (parms)); + + /* Report parms that live in registers during the function + but were passed in memory. */ + if (GET_CODE (DECL_RTL (parms)) == REG + && REGNO (DECL_RTL (parms)) >= 0 + && REGNO (DECL_RTL (parms)) < FIRST_PSEUDO_REGISTER + && PARM_PASSED_IN_MEMORY (parms)) + { + if (name == 0 || *name == 0) + name = gen_fake_label (); + PUT_SDB_DEF (name); + PUT_SDB_INT_VAL (DBX_REGISTER_NUMBER (REGNO (DECL_RTL (parms)))); + PUT_SDB_SCL (C_REG); + PUT_SDB_TYPE (plain_type (TREE_TYPE (parms), 0)); + PUT_SDB_ENDEF; + } + /* Report parms that live in memory but not where they were passed. */ + else if (GET_CODE (DECL_RTL (parms)) == MEM + && GET_CODE (XEXP (DECL_RTL (parms), 0)) == PLUS + && GET_CODE (XEXP (XEXP (DECL_RTL (parms), 0), 1)) == CONST_INT + && PARM_PASSED_IN_MEMORY (parms) + && ! rtx_equal_p (DECL_RTL (parms), DECL_INCOMING_RTL (parms))) + { +#if 0 /* ??? It is not clear yet what should replace this. */ + int offset = DECL_OFFSET (parms) / BITS_PER_UNIT; + /* A parm declared char is really passed as an int, + so it occupies the least significant bytes. + On a big-endian machine those are not the low-numbered ones. */ +#if BYTES_BIG_ENDIAN + if (offset != -1 && TREE_TYPE (parms) != DECL_ARG_TYPE (parms)) + offset += (GET_MODE_SIZE (TYPE_MODE (DECL_ARG_TYPE (parms))) + - GET_MODE_SIZE (GET_MODE (DECL_RTL (parms)))); +#endif + if (INTVAL (XEXP (XEXP (DECL_RTL (parms), 0), 1)) != offset) {...} +#endif + { + if (name == 0 || *name == 0) + name = gen_fake_label (); + PUT_SDB_DEF (name); + PUT_SDB_INT_VAL (DEBUGGER_AUTO_OFFSET + (XEXP (DECL_RTL (parms), 0))); + PUT_SDB_SCL (C_AUTO); + PUT_SDB_TYPE (plain_type (TREE_TYPE (parms))); + PUT_SDB_ENDEF; + } + } + } +} + +/* Describe the beginning of an internal block within a function. + Also output descriptions of variables defined in this block. + + N is the number of the block, by order of beginning, counting from 1, + and not counting the outermost (function top-level) block. + The blocks match the BLOCKs in DECL_INITIAL (current_function_decl), + if the count starts at 0 for the outermost one. */ + +void +sdbout_begin_block (file, line, n) + FILE *file; + int line; + int n; +{ + tree decl = current_function_decl; + MAKE_LINE_SAFE (line); + PUT_SDB_BLOCK_START (line - sdb_begin_function_line); + if (n == 1) + { + /* Include the outermost BLOCK's variables in block 1. */ + next_block_number = 0; + do_block = 0; + sdbout_block (DECL_INITIAL (decl)); + } + /* If -g1, suppress all the internal symbols of functions + except for arguments. */ + if (debug_info_level != DINFO_LEVEL_TERSE) + { + next_block_number = 0; + do_block = n; + sdbout_block (DECL_INITIAL (decl)); + } + +#ifdef SDB_ALLOW_FORWARD_REFERENCES + sdbout_dequeue_anonymous_types (); +#endif +} + +/* Describe the end line-number of an internal block within a function. */ + +void +sdbout_end_block (file, line) + FILE *file; + int line; +{ + MAKE_LINE_SAFE (line); + PUT_SDB_BLOCK_END (line - sdb_begin_function_line); +} + +/* Output sdb info for the current function name. + Called from assemble_start_function. */ + +void +sdbout_mark_begin_function () +{ + sdbout_symbol (current_function_decl, 0); +} + +/* Called at beginning of function body (after prologue). + Record the function's starting line number, so we can output + relative line numbers for the other lines. + Describe beginning of outermost block. + Also describe the parameter list. */ + +void +sdbout_begin_function (line) + int line; +{ + sdb_begin_function_line = line - 1; + PUT_SDB_FUNCTION_START (line); + sdbout_parms (DECL_ARGUMENTS (current_function_decl)); + sdbout_reg_parms (DECL_ARGUMENTS (current_function_decl)); +} + +/* Called at end of function (before epilogue). + Describe end of outermost block. */ + +void +sdbout_end_function (line) + int line; +{ +#ifdef SDB_ALLOW_FORWARD_REFERENCES + sdbout_dequeue_anonymous_types (); +#endif + + MAKE_LINE_SAFE (line); + PUT_SDB_FUNCTION_END (line - sdb_begin_function_line); + + /* Indicate we are between functions, for line-number output. */ + sdb_begin_function_line = -1; +} + +/* Output sdb info for the absolute end of a function. + Called after the epilogue is output. */ + +void +sdbout_end_epilogue () +{ + char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (current_function_decl)); + PUT_SDB_EPILOGUE_END (name); +} + +/* Output sdb info for the given label. Called only if LABEL_NAME (insn) + is present. */ + +void +sdbout_label (insn) + register rtx insn; +{ + PUT_SDB_DEF (LABEL_NAME (insn)); + PUT_SDB_VAL (insn); + PUT_SDB_SCL (C_LABEL); + PUT_SDB_TYPE (T_NULL); + PUT_SDB_ENDEF; +} + +#endif /* SDB_DEBUGGING_INFO */ diff --git a/gnu/usr.bin/cc/lib/stmt.c b/gnu/usr.bin/cc/lib/stmt.c new file mode 100644 index 000000000000..5647d26ce94a --- /dev/null +++ b/gnu/usr.bin/cc/lib/stmt.c @@ -0,0 +1,4749 @@ +/* Expands front end tree to back end RTL for GNU C-Compiler + Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This file handles the generation of rtl code from tree structure + above the level of expressions, using subroutines in exp*.c and emit-rtl.c. + It also creates the rtl expressions for parameters and auto variables + and has full responsibility for allocating stack slots. + + The functions whose names start with `expand_' are called by the + parser to generate RTL instructions for various kinds of constructs. + + Some control and binding constructs require calling several such + functions at different times. For example, a simple if-then + is expanded by calling `expand_start_cond' (with the condition-expression + as argument) before parsing the then-clause and calling `expand_end_cond' + after parsing the then-clause. */ + +#include "config.h" + +#include +#include + +#include "rtl.h" +#include "tree.h" +#include "flags.h" +#include "function.h" +#include "insn-flags.h" +#include "insn-config.h" +#include "insn-codes.h" +#include "expr.h" +#include "hard-reg-set.h" +#include "obstack.h" +#include "loop.h" +#include "recog.h" + +#define obstack_chunk_alloc xmalloc +#define obstack_chunk_free free +struct obstack stmt_obstack; + +/* Filename and line number of last line-number note, + whether we actually emitted it or not. */ +char *emit_filename; +int emit_lineno; + +/* Nonzero if within a ({...}) grouping, in which case we must + always compute a value for each expr-stmt in case it is the last one. */ + +int expr_stmts_for_value; + +/* Each time we expand an expression-statement, + record the expr's type and its RTL value here. */ + +static tree last_expr_type; +static rtx last_expr_value; + +/* Each time we expand the end of a binding contour (in `expand_end_bindings') + and we emit a new NOTE_INSN_BLOCK_END note, we save a pointer to it here. + This is used by the `remember_end_note' function to record the endpoint + of each generated block in its associated BLOCK node. */ + +static rtx last_block_end_note; + +/* Number of binding contours started so far in this function. */ + +int block_start_count; + +/* Nonzero if function being compiled needs to + return the address of where it has put a structure value. */ + +extern int current_function_returns_pcc_struct; + +/* Label that will go on parm cleanup code, if any. + Jumping to this label runs cleanup code for parameters, if + such code must be run. Following this code is the logical return label. */ + +extern rtx cleanup_label; + +/* Label that will go on function epilogue. + Jumping to this label serves as a "return" instruction + on machines which require execution of the epilogue on all returns. */ + +extern rtx return_label; + +/* List (chain of EXPR_LISTs) of pseudo-regs of SAVE_EXPRs. + So we can mark them all live at the end of the function, if nonopt. */ +extern rtx save_expr_regs; + +/* Offset to end of allocated area of stack frame. + If stack grows down, this is the address of the last stack slot allocated. + If stack grows up, this is the address for the next slot. */ +extern int frame_offset; + +/* Label to jump back to for tail recursion, or 0 if we have + not yet needed one for this function. */ +extern rtx tail_recursion_label; + +/* Place after which to insert the tail_recursion_label if we need one. */ +extern rtx tail_recursion_reentry; + +/* Location at which to save the argument pointer if it will need to be + referenced. There are two cases where this is done: if nonlocal gotos + exist, or if vars whose is an offset from the argument pointer will be + needed by inner routines. */ + +extern rtx arg_pointer_save_area; + +/* Chain of all RTL_EXPRs that have insns in them. */ +extern tree rtl_expr_chain; + +#if 0 /* Turned off because 0 seems to work just as well. */ +/* Cleanup lists are required for binding levels regardless of whether + that binding level has cleanups or not. This node serves as the + cleanup list whenever an empty list is required. */ +static tree empty_cleanup_list; +#endif + +/* Functions and data structures for expanding case statements. */ + +/* Case label structure, used to hold info on labels within case + statements. We handle "range" labels; for a single-value label + as in C, the high and low limits are the same. + + A chain of case nodes is initially maintained via the RIGHT fields + in the nodes. Nodes with higher case values are later in the list. + + Switch statements can be output in one of two forms. A branch table + is used if there are more than a few labels and the labels are dense + within the range between the smallest and largest case value. If a + branch table is used, no further manipulations are done with the case + node chain. + + The alternative to the use of a branch table is to generate a series + of compare and jump insns. When that is done, we use the LEFT, RIGHT, + and PARENT fields to hold a binary tree. Initially the tree is + totally unbalanced, with everything on the right. We balance the tree + with nodes on the left having lower case values than the parent + and nodes on the right having higher values. We then output the tree + in order. */ + +struct case_node +{ + struct case_node *left; /* Left son in binary tree */ + struct case_node *right; /* Right son in binary tree; also node chain */ + struct case_node *parent; /* Parent of node in binary tree */ + tree low; /* Lowest index value for this label */ + tree high; /* Highest index value for this label */ + tree code_label; /* Label to jump to when node matches */ +}; + +typedef struct case_node case_node; +typedef struct case_node *case_node_ptr; + +/* These are used by estimate_case_costs and balance_case_nodes. */ + +/* This must be a signed type, and non-ANSI compilers lack signed char. */ +static short *cost_table; +static int use_cost_table; + +static int estimate_case_costs (); +static void balance_case_nodes (); +static void emit_case_nodes (); +static void group_case_nodes (); +static void emit_jump_if_reachable (); + +static int warn_if_unused_value (); +static void expand_goto_internal (); +static int expand_fixup (); +void fixup_gotos (); +void free_temp_slots (); +static void expand_cleanups (); +static void expand_null_return_1 (); +static int tail_recursion_args (); +static void do_jump_if_equal (); + +/* Stack of control and binding constructs we are currently inside. + + These constructs begin when you call `expand_start_WHATEVER' + and end when you call `expand_end_WHATEVER'. This stack records + info about how the construct began that tells the end-function + what to do. It also may provide information about the construct + to alter the behavior of other constructs within the body. + For example, they may affect the behavior of C `break' and `continue'. + + Each construct gets one `struct nesting' object. + All of these objects are chained through the `all' field. + `nesting_stack' points to the first object (innermost construct). + The position of an entry on `nesting_stack' is in its `depth' field. + + Each type of construct has its own individual stack. + For example, loops have `loop_stack'. Each object points to the + next object of the same type through the `next' field. + + Some constructs are visible to `break' exit-statements and others + are not. Which constructs are visible depends on the language. + Therefore, the data structure allows each construct to be visible + or not, according to the args given when the construct is started. + The construct is visible if the `exit_label' field is non-null. + In that case, the value should be a CODE_LABEL rtx. */ + +struct nesting +{ + struct nesting *all; + struct nesting *next; + int depth; + rtx exit_label; + union + { + /* For conds (if-then and if-then-else statements). */ + struct + { + /* Label for the end of the if construct. + There is none if EXITFLAG was not set + and no `else' has been seen yet. */ + rtx endif_label; + /* Label for the end of this alternative. + This may be the end of the if or the next else/elseif. */ + rtx next_label; + } cond; + /* For loops. */ + struct + { + /* Label at the top of the loop; place to loop back to. */ + rtx start_label; + /* Label at the end of the whole construct. */ + rtx end_label; + /* Label for `continue' statement to jump to; + this is in front of the stepper of the loop. */ + rtx continue_label; + } loop; + /* For variable binding contours. */ + struct + { + /* Sequence number of this binding contour within the function, + in order of entry. */ + int block_start_count; + /* Nonzero => value to restore stack to on exit. */ + rtx stack_level; + /* The NOTE that starts this contour. + Used by expand_goto to check whether the destination + is within each contour or not. */ + rtx first_insn; + /* Innermost containing binding contour that has a stack level. */ + struct nesting *innermost_stack_block; + /* List of cleanups to be run on exit from this contour. + This is a list of expressions to be evaluated. + The TREE_PURPOSE of each link is the ..._DECL node + which the cleanup pertains to. */ + tree cleanups; + /* List of cleanup-lists of blocks containing this block, + as they were at the locus where this block appears. + There is an element for each containing block, + ordered innermost containing block first. + The tail of this list can be 0 (was empty_cleanup_list), + if all remaining elements would be empty lists. + The element's TREE_VALUE is the cleanup-list of that block, + which may be null. */ + tree outer_cleanups; + /* Chain of labels defined inside this binding contour. + For contours that have stack levels or cleanups. */ + struct label_chain *label_chain; + /* Number of function calls seen, as of start of this block. */ + int function_call_count; + } block; + /* For switch (C) or case (Pascal) statements, + and also for dummies (see `expand_start_case_dummy'). */ + struct + { + /* The insn after which the case dispatch should finally + be emitted. Zero for a dummy. */ + rtx start; + /* A list of case labels, kept in ascending order by value + as the list is built. + During expand_end_case, this list may be rearranged into a + nearly balanced binary tree. */ + struct case_node *case_list; + /* Label to jump to if no case matches. */ + tree default_label; + /* The expression to be dispatched on. */ + tree index_expr; + /* Type that INDEX_EXPR should be converted to. */ + tree nominal_type; + /* Number of range exprs in case statement. */ + int num_ranges; + /* Name of this kind of statement, for warnings. */ + char *printname; + /* Nonzero if a case label has been seen in this case stmt. */ + char seenlabel; + } case_stmt; + /* For exception contours. */ + struct + { + /* List of exceptions raised. This is a TREE_LIST + of whatever you want. */ + tree raised; + /* List of exceptions caught. This is also a TREE_LIST + of whatever you want. As a special case, it has the + value `void_type_node' if it handles default exceptions. */ + tree handled; + + /* First insn of TRY block, in case resumptive model is needed. */ + rtx first_insn; + /* Label for the catch clauses. */ + rtx except_label; + /* Label for unhandled exceptions. */ + rtx unhandled_label; + /* Label at the end of whole construct. */ + rtx after_label; + /* Label which "escapes" the exception construct. + Like EXIT_LABEL for BREAK construct, but for exceptions. */ + rtx escape_label; + } except_stmt; + } data; +}; + +/* Chain of all pending binding contours. */ +struct nesting *block_stack; + +/* If any new stacks are added here, add them to POPSTACKS too. */ + +/* Chain of all pending binding contours that restore stack levels + or have cleanups. */ +struct nesting *stack_block_stack; + +/* Chain of all pending conditional statements. */ +struct nesting *cond_stack; + +/* Chain of all pending loops. */ +struct nesting *loop_stack; + +/* Chain of all pending case or switch statements. */ +struct nesting *case_stack; + +/* Chain of all pending exception contours. */ +struct nesting *except_stack; + +/* Separate chain including all of the above, + chained through the `all' field. */ +struct nesting *nesting_stack; + +/* Number of entries on nesting_stack now. */ +int nesting_depth; + +/* Allocate and return a new `struct nesting'. */ + +#define ALLOC_NESTING() \ + (struct nesting *) obstack_alloc (&stmt_obstack, sizeof (struct nesting)) + +/* Pop the nesting stack element by element until we pop off + the element which is at the top of STACK. + Update all the other stacks, popping off elements from them + as we pop them from nesting_stack. */ + +#define POPSTACK(STACK) \ +do { struct nesting *target = STACK; \ + struct nesting *this; \ + do { this = nesting_stack; \ + if (loop_stack == this) \ + loop_stack = loop_stack->next; \ + if (cond_stack == this) \ + cond_stack = cond_stack->next; \ + if (block_stack == this) \ + block_stack = block_stack->next; \ + if (stack_block_stack == this) \ + stack_block_stack = stack_block_stack->next; \ + if (case_stack == this) \ + case_stack = case_stack->next; \ + if (except_stack == this) \ + except_stack = except_stack->next; \ + nesting_depth = nesting_stack->depth - 1; \ + nesting_stack = this->all; \ + obstack_free (&stmt_obstack, this); } \ + while (this != target); } while (0) + +/* In some cases it is impossible to generate code for a forward goto + until the label definition is seen. This happens when it may be necessary + for the goto to reset the stack pointer: we don't yet know how to do that. + So expand_goto puts an entry on this fixup list. + Each time a binding contour that resets the stack is exited, + we check each fixup. + If the target label has now been defined, we can insert the proper code. */ + +struct goto_fixup +{ + /* Points to following fixup. */ + struct goto_fixup *next; + /* Points to the insn before the jump insn. + If more code must be inserted, it goes after this insn. */ + rtx before_jump; + /* The LABEL_DECL that this jump is jumping to, or 0 + for break, continue or return. */ + tree target; + /* The BLOCK for the place where this goto was found. */ + tree context; + /* The CODE_LABEL rtx that this is jumping to. */ + rtx target_rtl; + /* Number of binding contours started in current function + before the label reference. */ + int block_start_count; + /* The outermost stack level that should be restored for this jump. + Each time a binding contour that resets the stack is exited, + if the target label is *not* yet defined, this slot is updated. */ + rtx stack_level; + /* List of lists of cleanup expressions to be run by this goto. + There is one element for each block that this goto is within. + The tail of this list can be 0 (was empty_cleanup_list), + if all remaining elements would be empty. + The TREE_VALUE contains the cleanup list of that block as of the + time this goto was seen. + The TREE_ADDRESSABLE flag is 1 for a block that has been exited. */ + tree cleanup_list_list; +}; + +static struct goto_fixup *goto_fixup_chain; + +/* Within any binding contour that must restore a stack level, + all labels are recorded with a chain of these structures. */ + +struct label_chain +{ + /* Points to following fixup. */ + struct label_chain *next; + tree label; +}; + +void +init_stmt () +{ + gcc_obstack_init (&stmt_obstack); +#if 0 + empty_cleanup_list = build_tree_list (NULL_TREE, NULL_TREE); +#endif +} + +void +init_stmt_for_function () +{ + /* We are not currently within any block, conditional, loop or case. */ + block_stack = 0; + loop_stack = 0; + case_stack = 0; + cond_stack = 0; + nesting_stack = 0; + nesting_depth = 0; + + block_start_count = 0; + + /* No gotos have been expanded yet. */ + goto_fixup_chain = 0; + + /* We are not processing a ({...}) grouping. */ + expr_stmts_for_value = 0; + last_expr_type = 0; +} + +void +save_stmt_status (p) + struct function *p; +{ + p->block_stack = block_stack; + p->stack_block_stack = stack_block_stack; + p->cond_stack = cond_stack; + p->loop_stack = loop_stack; + p->case_stack = case_stack; + p->nesting_stack = nesting_stack; + p->nesting_depth = nesting_depth; + p->block_start_count = block_start_count; + p->last_expr_type = last_expr_type; + p->last_expr_value = last_expr_value; + p->expr_stmts_for_value = expr_stmts_for_value; + p->emit_filename = emit_filename; + p->emit_lineno = emit_lineno; + p->goto_fixup_chain = goto_fixup_chain; +} + +void +restore_stmt_status (p) + struct function *p; +{ + block_stack = p->block_stack; + stack_block_stack = p->stack_block_stack; + cond_stack = p->cond_stack; + loop_stack = p->loop_stack; + case_stack = p->case_stack; + nesting_stack = p->nesting_stack; + nesting_depth = p->nesting_depth; + block_start_count = p->block_start_count; + last_expr_type = p->last_expr_type; + last_expr_value = p->last_expr_value; + expr_stmts_for_value = p->expr_stmts_for_value; + emit_filename = p->emit_filename; + emit_lineno = p->emit_lineno; + goto_fixup_chain = p->goto_fixup_chain; +} + +/* Emit a no-op instruction. */ + +void +emit_nop () +{ + rtx last_insn = get_last_insn (); + if (!optimize + && (GET_CODE (last_insn) == CODE_LABEL + || prev_real_insn (last_insn) == 0)) + emit_insn (gen_nop ()); +} + +/* Return the rtx-label that corresponds to a LABEL_DECL, + creating it if necessary. */ + +rtx +label_rtx (label) + tree label; +{ + if (TREE_CODE (label) != LABEL_DECL) + abort (); + + if (DECL_RTL (label)) + return DECL_RTL (label); + + return DECL_RTL (label) = gen_label_rtx (); +} + +/* Add an unconditional jump to LABEL as the next sequential instruction. */ + +void +emit_jump (label) + rtx label; +{ + do_pending_stack_adjust (); + emit_jump_insn (gen_jump (label)); + emit_barrier (); +} + +/* Emit code to jump to the address + specified by the pointer expression EXP. */ + +void +expand_computed_goto (exp) + tree exp; +{ + rtx x = expand_expr (exp, NULL_RTX, VOIDmode, 0); + emit_queue (); + emit_indirect_jump (x); +} + +/* Handle goto statements and the labels that they can go to. */ + +/* Specify the location in the RTL code of a label LABEL, + which is a LABEL_DECL tree node. + + This is used for the kind of label that the user can jump to with a + goto statement, and for alternatives of a switch or case statement. + RTL labels generated for loops and conditionals don't go through here; + they are generated directly at the RTL level, by other functions below. + + Note that this has nothing to do with defining label *names*. + Languages vary in how they do that and what that even means. */ + +void +expand_label (label) + tree label; +{ + struct label_chain *p; + + do_pending_stack_adjust (); + emit_label (label_rtx (label)); + if (DECL_NAME (label)) + LABEL_NAME (DECL_RTL (label)) = IDENTIFIER_POINTER (DECL_NAME (label)); + + if (stack_block_stack != 0) + { + p = (struct label_chain *) oballoc (sizeof (struct label_chain)); + p->next = stack_block_stack->data.block.label_chain; + stack_block_stack->data.block.label_chain = p; + p->label = label; + } +} + +/* Declare that LABEL (a LABEL_DECL) may be used for nonlocal gotos + from nested functions. */ + +void +declare_nonlocal_label (label) + tree label; +{ + nonlocal_labels = tree_cons (NULL_TREE, label, nonlocal_labels); + LABEL_PRESERVE_P (label_rtx (label)) = 1; + if (nonlocal_goto_handler_slot == 0) + { + nonlocal_goto_handler_slot + = assign_stack_local (Pmode, GET_MODE_SIZE (Pmode), 0); + emit_stack_save (SAVE_NONLOCAL, + &nonlocal_goto_stack_level, + PREV_INSN (tail_recursion_reentry)); + } +} + +/* Generate RTL code for a `goto' statement with target label LABEL. + LABEL should be a LABEL_DECL tree node that was or will later be + defined with `expand_label'. */ + +void +expand_goto (label) + tree label; +{ + /* Check for a nonlocal goto to a containing function. */ + tree context = decl_function_context (label); + if (context != 0 && context != current_function_decl) + { + struct function *p = find_function_data (context); + rtx label_ref = gen_rtx (LABEL_REF, Pmode, label_rtx (label)); + rtx temp; + + p->has_nonlocal_label = 1; + LABEL_REF_NONLOCAL_P (label_ref) = 1; + + /* Copy the rtl for the slots so that they won't be shared in + case the virtual stack vars register gets instantiated differently + in the parent than in the child. */ + +#if HAVE_nonlocal_goto + if (HAVE_nonlocal_goto) + emit_insn (gen_nonlocal_goto (lookup_static_chain (label), + copy_rtx (p->nonlocal_goto_handler_slot), + copy_rtx (p->nonlocal_goto_stack_level), + label_ref)); + else +#endif + { + rtx addr; + + /* Restore frame pointer for containing function. + This sets the actual hard register used for the frame pointer + to the location of the function's incoming static chain info. + The non-local goto handler will then adjust it to contain the + proper value and reload the argument pointer, if needed. */ + emit_move_insn (frame_pointer_rtx, lookup_static_chain (label)); + + /* We have now loaded the frame pointer hardware register with + the address of that corresponds to the start of the virtual + stack vars. So replace virtual_stack_vars_rtx in all + addresses we use with stack_pointer_rtx. */ + + /* Get addr of containing function's current nonlocal goto handler, + which will do any cleanups and then jump to the label. */ + addr = copy_rtx (p->nonlocal_goto_handler_slot); + temp = copy_to_reg (replace_rtx (addr, virtual_stack_vars_rtx, + frame_pointer_rtx)); + + /* Restore the stack pointer. Note this uses fp just restored. */ + addr = p->nonlocal_goto_stack_level; + if (addr) + addr = replace_rtx (copy_rtx (addr), + virtual_stack_vars_rtx, frame_pointer_rtx); + + emit_stack_restore (SAVE_NONLOCAL, addr, NULL_RTX); + + /* Put in the static chain register the nonlocal label address. */ + emit_move_insn (static_chain_rtx, label_ref); + /* USE of frame_pointer_rtx added for consistency; not clear if + really needed. */ + emit_insn (gen_rtx (USE, VOIDmode, frame_pointer_rtx)); + emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); + emit_insn (gen_rtx (USE, VOIDmode, static_chain_rtx)); + emit_indirect_jump (temp); + } + } + else + expand_goto_internal (label, label_rtx (label), NULL_RTX); +} + +/* Generate RTL code for a `goto' statement with target label BODY. + LABEL should be a LABEL_REF. + LAST_INSN, if non-0, is the rtx we should consider as the last + insn emitted (for the purposes of cleaning up a return). */ + +static void +expand_goto_internal (body, label, last_insn) + tree body; + rtx label; + rtx last_insn; +{ + struct nesting *block; + rtx stack_level = 0; + + if (GET_CODE (label) != CODE_LABEL) + abort (); + + /* If label has already been defined, we can tell now + whether and how we must alter the stack level. */ + + if (PREV_INSN (label) != 0) + { + /* Find the innermost pending block that contains the label. + (Check containment by comparing insn-uids.) + Then restore the outermost stack level within that block, + and do cleanups of all blocks contained in it. */ + for (block = block_stack; block; block = block->next) + { + if (INSN_UID (block->data.block.first_insn) < INSN_UID (label)) + break; + if (block->data.block.stack_level != 0) + stack_level = block->data.block.stack_level; + /* Execute the cleanups for blocks we are exiting. */ + if (block->data.block.cleanups != 0) + { + expand_cleanups (block->data.block.cleanups, NULL_TREE); + do_pending_stack_adjust (); + } + } + + if (stack_level) + { + /* Ensure stack adjust isn't done by emit_jump, as this would clobber + the stack pointer. This one should be deleted as dead by flow. */ + clear_pending_stack_adjust (); + do_pending_stack_adjust (); + emit_stack_restore (SAVE_BLOCK, stack_level, NULL_RTX); + } + + if (body != 0 && DECL_TOO_LATE (body)) + error ("jump to `%s' invalidly jumps into binding contour", + IDENTIFIER_POINTER (DECL_NAME (body))); + } + /* Label not yet defined: may need to put this goto + on the fixup list. */ + else if (! expand_fixup (body, label, last_insn)) + { + /* No fixup needed. Record that the label is the target + of at least one goto that has no fixup. */ + if (body != 0) + TREE_ADDRESSABLE (body) = 1; + } + + emit_jump (label); +} + +/* Generate if necessary a fixup for a goto + whose target label in tree structure (if any) is TREE_LABEL + and whose target in rtl is RTL_LABEL. + + If LAST_INSN is nonzero, we pretend that the jump appears + after insn LAST_INSN instead of at the current point in the insn stream. + + The fixup will be used later to insert insns just before the goto. + Those insns will restore the stack level as appropriate for the + target label, and will (in the case of C++) also invoke any object + destructors which have to be invoked when we exit the scopes which + are exited by the goto. + + Value is nonzero if a fixup is made. */ + +static int +expand_fixup (tree_label, rtl_label, last_insn) + tree tree_label; + rtx rtl_label; + rtx last_insn; +{ + struct nesting *block, *end_block; + + /* See if we can recognize which block the label will be output in. + This is possible in some very common cases. + If we succeed, set END_BLOCK to that block. + Otherwise, set it to 0. */ + + if (cond_stack + && (rtl_label == cond_stack->data.cond.endif_label + || rtl_label == cond_stack->data.cond.next_label)) + end_block = cond_stack; + /* If we are in a loop, recognize certain labels which + are likely targets. This reduces the number of fixups + we need to create. */ + else if (loop_stack + && (rtl_label == loop_stack->data.loop.start_label + || rtl_label == loop_stack->data.loop.end_label + || rtl_label == loop_stack->data.loop.continue_label)) + end_block = loop_stack; + else + end_block = 0; + + /* Now set END_BLOCK to the binding level to which we will return. */ + + if (end_block) + { + struct nesting *next_block = end_block->all; + block = block_stack; + + /* First see if the END_BLOCK is inside the innermost binding level. + If so, then no cleanups or stack levels are relevant. */ + while (next_block && next_block != block) + next_block = next_block->all; + + if (next_block) + return 0; + + /* Otherwise, set END_BLOCK to the innermost binding level + which is outside the relevant control-structure nesting. */ + next_block = block_stack->next; + for (block = block_stack; block != end_block; block = block->all) + if (block == next_block) + next_block = next_block->next; + end_block = next_block; + } + + /* Does any containing block have a stack level or cleanups? + If not, no fixup is needed, and that is the normal case + (the only case, for standard C). */ + for (block = block_stack; block != end_block; block = block->next) + if (block->data.block.stack_level != 0 + || block->data.block.cleanups != 0) + break; + + if (block != end_block) + { + /* Ok, a fixup is needed. Add a fixup to the list of such. */ + struct goto_fixup *fixup + = (struct goto_fixup *) oballoc (sizeof (struct goto_fixup)); + /* In case an old stack level is restored, make sure that comes + after any pending stack adjust. */ + /* ?? If the fixup isn't to come at the present position, + doing the stack adjust here isn't useful. Doing it with our + settings at that location isn't useful either. Let's hope + someone does it! */ + if (last_insn == 0) + do_pending_stack_adjust (); + fixup->target = tree_label; + fixup->target_rtl = rtl_label; + + /* Create a BLOCK node and a corresponding matched set of + NOTE_INSN_BEGIN_BLOCK and NOTE_INSN_END_BLOCK notes at + this point. The notes will encapsulate any and all fixup + code which we might later insert at this point in the insn + stream. Also, the BLOCK node will be the parent (i.e. the + `SUPERBLOCK') of any other BLOCK nodes which we might create + later on when we are expanding the fixup code. */ + + { + register rtx original_before_jump + = last_insn ? last_insn : get_last_insn (); + + start_sequence (); + pushlevel (0); + fixup->before_jump = emit_note (NULL_PTR, NOTE_INSN_BLOCK_BEG); + last_block_end_note = emit_note (NULL_PTR, NOTE_INSN_BLOCK_END); + fixup->context = poplevel (1, 0, 0); /* Create the BLOCK node now! */ + end_sequence (); + emit_insns_after (fixup->before_jump, original_before_jump); + } + + fixup->block_start_count = block_start_count; + fixup->stack_level = 0; + fixup->cleanup_list_list + = (((block->data.block.outer_cleanups +#if 0 + && block->data.block.outer_cleanups != empty_cleanup_list +#endif + ) + || block->data.block.cleanups) + ? tree_cons (NULL_TREE, block->data.block.cleanups, + block->data.block.outer_cleanups) + : 0); + fixup->next = goto_fixup_chain; + goto_fixup_chain = fixup; + } + + return block != 0; +} + +/* When exiting a binding contour, process all pending gotos requiring fixups. + THISBLOCK is the structure that describes the block being exited. + STACK_LEVEL is the rtx for the stack level to restore exiting this contour. + CLEANUP_LIST is a list of expressions to evaluate on exiting this contour. + FIRST_INSN is the insn that began this contour. + + Gotos that jump out of this contour must restore the + stack level and do the cleanups before actually jumping. + + DONT_JUMP_IN nonzero means report error there is a jump into this + contour from before the beginning of the contour. + This is also done if STACK_LEVEL is nonzero. */ + +void +fixup_gotos (thisblock, stack_level, cleanup_list, first_insn, dont_jump_in) + struct nesting *thisblock; + rtx stack_level; + tree cleanup_list; + rtx first_insn; + int dont_jump_in; +{ + register struct goto_fixup *f, *prev; + + /* F is the fixup we are considering; PREV is the previous one. */ + /* We run this loop in two passes so that cleanups of exited blocks + are run first, and blocks that are exited are marked so + afterwards. */ + + for (prev = 0, f = goto_fixup_chain; f; prev = f, f = f->next) + { + /* Test for a fixup that is inactive because it is already handled. */ + if (f->before_jump == 0) + { + /* Delete inactive fixup from the chain, if that is easy to do. */ + if (prev != 0) + prev->next = f->next; + } + /* Has this fixup's target label been defined? + If so, we can finalize it. */ + else if (PREV_INSN (f->target_rtl) != 0) + { + register rtx cleanup_insns; + + /* Get the first non-label after the label + this goto jumps to. If that's before this scope begins, + we don't have a jump into the scope. */ + rtx after_label = f->target_rtl; + while (after_label != 0 && GET_CODE (after_label) == CODE_LABEL) + after_label = NEXT_INSN (after_label); + + /* If this fixup jumped into this contour from before the beginning + of this contour, report an error. */ + /* ??? Bug: this does not detect jumping in through intermediate + blocks that have stack levels or cleanups. + It detects only a problem with the innermost block + around the label. */ + if (f->target != 0 + && (dont_jump_in || stack_level || cleanup_list) + /* If AFTER_LABEL is 0, it means the jump goes to the end + of the rtl, which means it jumps into this scope. */ + && (after_label == 0 + || INSN_UID (first_insn) < INSN_UID (after_label)) + && INSN_UID (first_insn) > INSN_UID (f->before_jump) + && ! DECL_REGISTER (f->target)) + { + error_with_decl (f->target, + "label `%s' used before containing binding contour"); + /* Prevent multiple errors for one label. */ + DECL_REGISTER (f->target) = 1; + } + + /* We will expand the cleanups into a sequence of their own and + then later on we will attach this new sequence to the insn + stream just ahead of the actual jump insn. */ + + start_sequence (); + + /* Temporarily restore the lexical context where we will + logically be inserting the fixup code. We do this for the + sake of getting the debugging information right. */ + + pushlevel (0); + set_block (f->context); + + /* Expand the cleanups for blocks this jump exits. */ + if (f->cleanup_list_list) + { + tree lists; + for (lists = f->cleanup_list_list; lists; lists = TREE_CHAIN (lists)) + /* Marked elements correspond to blocks that have been closed. + Do their cleanups. */ + if (TREE_ADDRESSABLE (lists) + && TREE_VALUE (lists) != 0) + { + expand_cleanups (TREE_VALUE (lists), 0); + /* Pop any pushes done in the cleanups, + in case function is about to return. */ + do_pending_stack_adjust (); + } + } + + /* Restore stack level for the biggest contour that this + jump jumps out of. */ + if (f->stack_level) + emit_stack_restore (SAVE_BLOCK, f->stack_level, f->before_jump); + + /* Finish up the sequence containing the insns which implement the + necessary cleanups, and then attach that whole sequence to the + insn stream just ahead of the actual jump insn. Attaching it + at that point insures that any cleanups which are in fact + implicit C++ object destructions (which must be executed upon + leaving the block) appear (to the debugger) to be taking place + in an area of the generated code where the object(s) being + destructed are still "in scope". */ + + cleanup_insns = get_insns (); + poplevel (1, 0, 0); + + end_sequence (); + emit_insns_after (cleanup_insns, f->before_jump); + + + f->before_jump = 0; + } + } + + /* Mark the cleanups of exited blocks so that they are executed + by the code above. */ + for (prev = 0, f = goto_fixup_chain; f; prev = f, f = f->next) + if (f->before_jump != 0 + && PREV_INSN (f->target_rtl) == 0 + /* Label has still not appeared. If we are exiting a block with + a stack level to restore, that started before the fixup, + mark this stack level as needing restoration + when the fixup is later finalized. + Also mark the cleanup_list_list element for F + that corresponds to this block, so that ultimately + this block's cleanups will be executed by the code above. */ + && thisblock != 0 + /* Note: if THISBLOCK == 0 and we have a label that hasn't appeared, + it means the label is undefined. That's erroneous, but possible. */ + && (thisblock->data.block.block_start_count + <= f->block_start_count)) + { + tree lists = f->cleanup_list_list; + for (; lists; lists = TREE_CHAIN (lists)) + /* If the following elt. corresponds to our containing block + then the elt. must be for this block. */ + if (TREE_CHAIN (lists) == thisblock->data.block.outer_cleanups) + TREE_ADDRESSABLE (lists) = 1; + + if (stack_level) + f->stack_level = stack_level; + } +} + +/* Generate RTL for an asm statement (explicit assembler code). + BODY is a STRING_CST node containing the assembler code text, + or an ADDR_EXPR containing a STRING_CST. */ + +void +expand_asm (body) + tree body; +{ + if (TREE_CODE (body) == ADDR_EXPR) + body = TREE_OPERAND (body, 0); + + emit_insn (gen_rtx (ASM_INPUT, VOIDmode, + TREE_STRING_POINTER (body))); + last_expr_type = 0; +} + +/* Generate RTL for an asm statement with arguments. + STRING is the instruction template. + OUTPUTS is a list of output arguments (lvalues); INPUTS a list of inputs. + Each output or input has an expression in the TREE_VALUE and + a constraint-string in the TREE_PURPOSE. + CLOBBERS is a list of STRING_CST nodes each naming a hard register + that is clobbered by this insn. + + Not all kinds of lvalue that may appear in OUTPUTS can be stored directly. + Some elements of OUTPUTS may be replaced with trees representing temporary + values. The caller should copy those temporary values to the originally + specified lvalues. + + VOL nonzero means the insn is volatile; don't optimize it. */ + +void +expand_asm_operands (string, outputs, inputs, clobbers, vol, filename, line) + tree string, outputs, inputs, clobbers; + int vol; + char *filename; + int line; +{ + rtvec argvec, constraints; + rtx body; + int ninputs = list_length (inputs); + int noutputs = list_length (outputs); + int nclobbers; + tree tail; + register int i; + /* Vector of RTX's of evaluated output operands. */ + rtx *output_rtx = (rtx *) alloca (noutputs * sizeof (rtx)); + /* The insn we have emitted. */ + rtx insn; + + /* Count the number of meaningful clobbered registers, ignoring what + we would ignore later. */ + nclobbers = 0; + for (tail = clobbers; tail; tail = TREE_CHAIN (tail)) + { + char *regname = TREE_STRING_POINTER (TREE_VALUE (tail)); + i = decode_reg_name (regname); + if (i >= 0 || i == -4) + ++nclobbers; + } + + last_expr_type = 0; + + for (i = 0, tail = outputs; tail; tail = TREE_CHAIN (tail), i++) + { + tree val = TREE_VALUE (tail); + tree val1; + int j; + int found_equal; + + /* If there's an erroneous arg, emit no insn. */ + if (TREE_TYPE (val) == error_mark_node) + return; + + /* Make sure constraint has `=' and does not have `+'. */ + + found_equal = 0; + for (j = 0; j < TREE_STRING_LENGTH (TREE_PURPOSE (tail)); j++) + { + if (TREE_STRING_POINTER (TREE_PURPOSE (tail))[j] == '+') + { + error ("output operand constraint contains `+'"); + return; + } + if (TREE_STRING_POINTER (TREE_PURPOSE (tail))[j] == '=') + found_equal = 1; + } + if (! found_equal) + { + error ("output operand constraint lacks `='"); + return; + } + + /* If an output operand is not a variable or indirect ref, + or a part of one, + create a SAVE_EXPR which is a pseudo-reg + to act as an intermediate temporary. + Make the asm insn write into that, then copy it to + the real output operand. */ + + while (TREE_CODE (val) == COMPONENT_REF + || TREE_CODE (val) == ARRAY_REF) + val = TREE_OPERAND (val, 0); + + if (TREE_CODE (val) != VAR_DECL + && TREE_CODE (val) != PARM_DECL + && TREE_CODE (val) != INDIRECT_REF) + { + TREE_VALUE (tail) = save_expr (TREE_VALUE (tail)); + /* If it's a constant, print error now so don't crash later. */ + if (TREE_CODE (TREE_VALUE (tail)) != SAVE_EXPR) + { + error ("invalid output in `asm'"); + return; + } + } + + output_rtx[i] = expand_expr (TREE_VALUE (tail), NULL_RTX, VOIDmode, 0); + } + + if (ninputs + noutputs > MAX_RECOG_OPERANDS) + { + error ("more than %d operands in `asm'", MAX_RECOG_OPERANDS); + return; + } + + /* Make vectors for the expression-rtx and constraint strings. */ + + argvec = rtvec_alloc (ninputs); + constraints = rtvec_alloc (ninputs); + + body = gen_rtx (ASM_OPERANDS, VOIDmode, + TREE_STRING_POINTER (string), "", 0, argvec, constraints, + filename, line); + MEM_VOLATILE_P (body) = vol; + + /* Eval the inputs and put them into ARGVEC. + Put their constraints into ASM_INPUTs and store in CONSTRAINTS. */ + + i = 0; + for (tail = inputs; tail; tail = TREE_CHAIN (tail)) + { + int j; + + /* If there's an erroneous arg, emit no insn, + because the ASM_INPUT would get VOIDmode + and that could cause a crash in reload. */ + if (TREE_TYPE (TREE_VALUE (tail)) == error_mark_node) + return; + if (TREE_PURPOSE (tail) == NULL_TREE) + { + error ("hard register `%s' listed as input operand to `asm'", + TREE_STRING_POINTER (TREE_VALUE (tail)) ); + return; + } + + /* Make sure constraint has neither `=' nor `+'. */ + + for (j = 0; j < TREE_STRING_LENGTH (TREE_PURPOSE (tail)); j++) + if (TREE_STRING_POINTER (TREE_PURPOSE (tail))[j] == '=' + || TREE_STRING_POINTER (TREE_PURPOSE (tail))[j] == '+') + { + error ("input operand constraint contains `%c'", + TREE_STRING_POINTER (TREE_PURPOSE (tail))[j]); + return; + } + + XVECEXP (body, 3, i) /* argvec */ + = expand_expr (TREE_VALUE (tail), NULL_RTX, VOIDmode, 0); + XVECEXP (body, 4, i) /* constraints */ + = gen_rtx (ASM_INPUT, TYPE_MODE (TREE_TYPE (TREE_VALUE (tail))), + TREE_STRING_POINTER (TREE_PURPOSE (tail))); + i++; + } + + /* Protect all the operands from the queue, + now that they have all been evaluated. */ + + for (i = 0; i < ninputs; i++) + XVECEXP (body, 3, i) = protect_from_queue (XVECEXP (body, 3, i), 0); + + for (i = 0; i < noutputs; i++) + output_rtx[i] = protect_from_queue (output_rtx[i], 1); + + /* Now, for each output, construct an rtx + (set OUTPUT (asm_operands INSN OUTPUTNUMBER OUTPUTCONSTRAINT + ARGVEC CONSTRAINTS)) + If there is more than one, put them inside a PARALLEL. */ + + if (noutputs == 1 && nclobbers == 0) + { + XSTR (body, 1) = TREE_STRING_POINTER (TREE_PURPOSE (outputs)); + insn = emit_insn (gen_rtx (SET, VOIDmode, output_rtx[0], body)); + } + else if (noutputs == 0 && nclobbers == 0) + { + /* No output operands: put in a raw ASM_OPERANDS rtx. */ + insn = emit_insn (body); + } + else + { + rtx obody = body; + int num = noutputs; + if (num == 0) num = 1; + body = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (num + nclobbers)); + + /* For each output operand, store a SET. */ + + for (i = 0, tail = outputs; tail; tail = TREE_CHAIN (tail), i++) + { + XVECEXP (body, 0, i) + = gen_rtx (SET, VOIDmode, + output_rtx[i], + gen_rtx (ASM_OPERANDS, VOIDmode, + TREE_STRING_POINTER (string), + TREE_STRING_POINTER (TREE_PURPOSE (tail)), + i, argvec, constraints, + filename, line)); + MEM_VOLATILE_P (SET_SRC (XVECEXP (body, 0, i))) = vol; + } + + /* If there are no outputs (but there are some clobbers) + store the bare ASM_OPERANDS into the PARALLEL. */ + + if (i == 0) + XVECEXP (body, 0, i++) = obody; + + /* Store (clobber REG) for each clobbered register specified. */ + + for (tail = clobbers; tail; tail = TREE_CHAIN (tail)) + { + char *regname = TREE_STRING_POINTER (TREE_VALUE (tail)); + int j = decode_reg_name (regname); + + if (j < 0) + { + if (j == -3) /* `cc', which is not a register */ + continue; + + if (j == -4) /* `memory', don't cache memory across asm */ + { + XVECEXP (body, 0, i++) + = gen_rtx (CLOBBER, VOIDmode, + gen_rtx (MEM, QImode, + gen_rtx (SCRATCH, VOIDmode, 0))); + continue; + } + + error ("unknown register name `%s' in `asm'", regname); + return; + } + + /* Use QImode since that's guaranteed to clobber just one reg. */ + XVECEXP (body, 0, i++) + = gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, QImode, j)); + } + + insn = emit_insn (body); + } + + free_temp_slots (); +} + +/* Generate RTL to evaluate the expression EXP + and remember it in case this is the VALUE in a ({... VALUE; }) constr. */ + +void +expand_expr_stmt (exp) + tree exp; +{ + /* If -W, warn about statements with no side effects, + except for an explicit cast to void (e.g. for assert()), and + except inside a ({...}) where they may be useful. */ + if (expr_stmts_for_value == 0 && exp != error_mark_node) + { + if (! TREE_SIDE_EFFECTS (exp) && (extra_warnings || warn_unused) + && !(TREE_CODE (exp) == CONVERT_EXPR + && TREE_TYPE (exp) == void_type_node)) + warning_with_file_and_line (emit_filename, emit_lineno, + "statement with no effect"); + else if (warn_unused) + warn_if_unused_value (exp); + } + last_expr_type = TREE_TYPE (exp); + if (! flag_syntax_only) + last_expr_value = expand_expr (exp, + (expr_stmts_for_value + ? NULL_RTX : const0_rtx), + VOIDmode, 0); + + /* If all we do is reference a volatile value in memory, + copy it to a register to be sure it is actually touched. */ + if (last_expr_value != 0 && GET_CODE (last_expr_value) == MEM + && TREE_THIS_VOLATILE (exp)) + { + if (TYPE_MODE (TREE_TYPE (exp)) == VOIDmode) + ; + else if (TYPE_MODE (TREE_TYPE (exp)) != BLKmode) + copy_to_reg (last_expr_value); + else + { + rtx lab = gen_label_rtx (); + + /* Compare the value with itself to reference it. */ + emit_cmp_insn (last_expr_value, last_expr_value, EQ, + expand_expr (TYPE_SIZE (last_expr_type), + NULL_RTX, VOIDmode, 0), + BLKmode, 0, + TYPE_ALIGN (last_expr_type) / BITS_PER_UNIT); + emit_jump_insn ((*bcc_gen_fctn[(int) EQ]) (lab)); + emit_label (lab); + } + } + + /* If this expression is part of a ({...}) and is in memory, we may have + to preserve temporaries. */ + preserve_temp_slots (last_expr_value); + + /* Free any temporaries used to evaluate this expression. Any temporary + used as a result of this expression will already have been preserved + above. */ + free_temp_slots (); + + emit_queue (); +} + +/* Warn if EXP contains any computations whose results are not used. + Return 1 if a warning is printed; 0 otherwise. */ + +static int +warn_if_unused_value (exp) + tree exp; +{ + if (TREE_USED (exp)) + return 0; + + switch (TREE_CODE (exp)) + { + case PREINCREMENT_EXPR: + case POSTINCREMENT_EXPR: + case PREDECREMENT_EXPR: + case POSTDECREMENT_EXPR: + case MODIFY_EXPR: + case INIT_EXPR: + case TARGET_EXPR: + case CALL_EXPR: + case METHOD_CALL_EXPR: + case RTL_EXPR: + case WITH_CLEANUP_EXPR: + case EXIT_EXPR: + /* We don't warn about COND_EXPR because it may be a useful + construct if either arm contains a side effect. */ + case COND_EXPR: + return 0; + + case BIND_EXPR: + /* For a binding, warn if no side effect within it. */ + return warn_if_unused_value (TREE_OPERAND (exp, 1)); + + case TRUTH_ORIF_EXPR: + case TRUTH_ANDIF_EXPR: + /* In && or ||, warn if 2nd operand has no side effect. */ + return warn_if_unused_value (TREE_OPERAND (exp, 1)); + + case COMPOUND_EXPR: + if (warn_if_unused_value (TREE_OPERAND (exp, 0))) + return 1; + /* Let people do `(foo (), 0)' without a warning. */ + if (TREE_CONSTANT (TREE_OPERAND (exp, 1))) + return 0; + return warn_if_unused_value (TREE_OPERAND (exp, 1)); + + case NOP_EXPR: + case CONVERT_EXPR: + case NON_LVALUE_EXPR: + /* Don't warn about values cast to void. */ + if (TREE_TYPE (exp) == void_type_node) + return 0; + /* Don't warn about conversions not explicit in the user's program. */ + if (TREE_NO_UNUSED_WARNING (exp)) + return 0; + /* Assignment to a cast usually results in a cast of a modify. + Don't complain about that. */ + if (TREE_CODE (TREE_OPERAND (exp, 0)) == MODIFY_EXPR) + return 0; + /* Sometimes it results in a cast of a cast of a modify. + Don't complain about that. */ + if ((TREE_CODE (TREE_OPERAND (exp, 0)) == CONVERT_EXPR + || TREE_CODE (TREE_OPERAND (exp, 0)) == NOP_EXPR) + && TREE_CODE (TREE_OPERAND (TREE_OPERAND (exp, 0), 0)) == MODIFY_EXPR) + return 0; + + default: + /* Referencing a volatile value is a side effect, so don't warn. */ + if ((TREE_CODE_CLASS (TREE_CODE (exp)) == 'd' + || TREE_CODE_CLASS (TREE_CODE (exp)) == 'r') + && TREE_THIS_VOLATILE (exp)) + return 0; + warning_with_file_and_line (emit_filename, emit_lineno, + "value computed is not used"); + return 1; + } +} + +/* Clear out the memory of the last expression evaluated. */ + +void +clear_last_expr () +{ + last_expr_type = 0; +} + +/* Begin a statement which will return a value. + Return the RTL_EXPR for this statement expr. + The caller must save that value and pass it to expand_end_stmt_expr. */ + +tree +expand_start_stmt_expr () +{ + /* Make the RTL_EXPR node temporary, not momentary, + so that rtl_expr_chain doesn't become garbage. */ + int momentary = suspend_momentary (); + tree t = make_node (RTL_EXPR); + resume_momentary (momentary); + start_sequence (); + NO_DEFER_POP; + expr_stmts_for_value++; + return t; +} + +/* Restore the previous state at the end of a statement that returns a value. + Returns a tree node representing the statement's value and the + insns to compute the value. + + The nodes of that expression have been freed by now, so we cannot use them. + But we don't want to do that anyway; the expression has already been + evaluated and now we just want to use the value. So generate a RTL_EXPR + with the proper type and RTL value. + + If the last substatement was not an expression, + return something with type `void'. */ + +tree +expand_end_stmt_expr (t) + tree t; +{ + OK_DEFER_POP; + + if (last_expr_type == 0) + { + last_expr_type = void_type_node; + last_expr_value = const0_rtx; + } + else if (last_expr_value == 0) + /* There are some cases where this can happen, such as when the + statement is void type. */ + last_expr_value = const0_rtx; + else if (GET_CODE (last_expr_value) != REG && ! CONSTANT_P (last_expr_value)) + /* Remove any possible QUEUED. */ + last_expr_value = protect_from_queue (last_expr_value, 0); + + emit_queue (); + + TREE_TYPE (t) = last_expr_type; + RTL_EXPR_RTL (t) = last_expr_value; + RTL_EXPR_SEQUENCE (t) = get_insns (); + + rtl_expr_chain = tree_cons (NULL_TREE, t, rtl_expr_chain); + + end_sequence (); + + /* Don't consider deleting this expr or containing exprs at tree level. */ + TREE_SIDE_EFFECTS (t) = 1; + /* Propagate volatility of the actual RTL expr. */ + TREE_THIS_VOLATILE (t) = volatile_refs_p (last_expr_value); + + last_expr_type = 0; + expr_stmts_for_value--; + + return t; +} + +/* The exception handling nesting looks like this: + + <-- Level N-1 + { <-- exception handler block + <-- Level N + <-- in an exception handler + { <-- try block + : <-- in a TRY block + : <-- in an exception handler + : + } + + { <-- except block + : <-- in an except block + : <-- in an exception handler + : + } + + } +*/ + +/* Return nonzero iff in a try block at level LEVEL. */ + +int +in_try_block (level) + int level; +{ + struct nesting *n = except_stack; + while (1) + { + while (n && n->data.except_stmt.after_label != 0) + n = n->next; + if (n == 0) + return 0; + if (level == 0) + return n != 0; + level--; + n = n->next; + } +} + +/* Return nonzero iff in an except block at level LEVEL. */ + +int +in_except_block (level) + int level; +{ + struct nesting *n = except_stack; + while (1) + { + while (n && n->data.except_stmt.after_label == 0) + n = n->next; + if (n == 0) + return 0; + if (level == 0) + return n != 0; + level--; + n = n->next; + } +} + +/* Return nonzero iff in an exception handler at level LEVEL. */ + +int +in_exception_handler (level) + int level; +{ + struct nesting *n = except_stack; + while (n && level--) + n = n->next; + return n != 0; +} + +/* Record the fact that the current exception nesting raises + exception EX. If not in an exception handler, return 0. */ +int +expand_raise (ex) + tree ex; +{ + tree *raises_ptr; + + if (except_stack == 0) + return 0; + raises_ptr = &except_stack->data.except_stmt.raised; + if (! value_member (ex, *raises_ptr)) + *raises_ptr = tree_cons (NULL_TREE, ex, *raises_ptr); + return 1; +} + +/* Generate RTL for the start of a try block. + + TRY_CLAUSE is the condition to test to enter the try block. */ + +void +expand_start_try (try_clause, exitflag, escapeflag) + tree try_clause; + int exitflag; + int escapeflag; +{ + struct nesting *thishandler = ALLOC_NESTING (); + + /* Make an entry on cond_stack for the cond we are entering. */ + + thishandler->next = except_stack; + thishandler->all = nesting_stack; + thishandler->depth = ++nesting_depth; + thishandler->data.except_stmt.raised = 0; + thishandler->data.except_stmt.handled = 0; + thishandler->data.except_stmt.first_insn = get_insns (); + thishandler->data.except_stmt.except_label = gen_label_rtx (); + thishandler->data.except_stmt.unhandled_label = 0; + thishandler->data.except_stmt.after_label = 0; + thishandler->data.except_stmt.escape_label + = escapeflag ? thishandler->data.except_stmt.except_label : 0; + thishandler->exit_label = exitflag ? gen_label_rtx () : 0; + except_stack = thishandler; + nesting_stack = thishandler; + + do_jump (try_clause, thishandler->data.except_stmt.except_label, NULL_RTX); +} + +/* End of a TRY block. Nothing to do for now. */ + +void +expand_end_try () +{ + except_stack->data.except_stmt.after_label = gen_label_rtx (); + expand_goto_internal (NULL_TREE, except_stack->data.except_stmt.after_label, + NULL_RTX); +} + +/* Start an `except' nesting contour. + EXITFLAG says whether this contour should be able to `exit' something. + ESCAPEFLAG says whether this contour should be escapable. */ + +void +expand_start_except (exitflag, escapeflag) + int exitflag; + int escapeflag; +{ + if (exitflag) + { + struct nesting *n; + /* An `exit' from catch clauses goes out to next exit level, + if there is one. Otherwise, it just goes to the end + of the construct. */ + for (n = except_stack->next; n; n = n->next) + if (n->exit_label != 0) + { + except_stack->exit_label = n->exit_label; + break; + } + if (n == 0) + except_stack->exit_label = except_stack->data.except_stmt.after_label; + } + if (escapeflag) + { + struct nesting *n; + /* An `escape' from catch clauses goes out to next escape level, + if there is one. Otherwise, it just goes to the end + of the construct. */ + for (n = except_stack->next; n; n = n->next) + if (n->data.except_stmt.escape_label != 0) + { + except_stack->data.except_stmt.escape_label + = n->data.except_stmt.escape_label; + break; + } + if (n == 0) + except_stack->data.except_stmt.escape_label + = except_stack->data.except_stmt.after_label; + } + do_pending_stack_adjust (); + emit_label (except_stack->data.except_stmt.except_label); +} + +/* Generate code to `escape' from an exception contour. This + is like `exiting', but does not conflict with constructs which + use `exit_label'. + + Return nonzero if this contour is escapable, otherwise + return zero, and language-specific code will emit the + appropriate error message. */ +int +expand_escape_except () +{ + struct nesting *n; + last_expr_type = 0; + for (n = except_stack; n; n = n->next) + if (n->data.except_stmt.escape_label != 0) + { + expand_goto_internal (NULL_TREE, + n->data.except_stmt.escape_label, NULL_RTX); + return 1; + } + + return 0; +} + +/* Finish processing and `except' contour. + Culls out all exceptions which might be raise but not + handled, and returns the list to the caller. + Language-specific code is responsible for dealing with these + exceptions. */ + +tree +expand_end_except () +{ + struct nesting *n; + tree raised = NULL_TREE; + + do_pending_stack_adjust (); + emit_label (except_stack->data.except_stmt.after_label); + + n = except_stack->next; + if (n) + { + /* Propagate exceptions raised but not handled to next + highest level. */ + tree handled = except_stack->data.except_stmt.raised; + if (handled != void_type_node) + { + tree prev = NULL_TREE; + raised = except_stack->data.except_stmt.raised; + while (handled) + { + tree this_raise; + for (this_raise = raised, prev = 0; this_raise; + this_raise = TREE_CHAIN (this_raise)) + { + if (value_member (TREE_VALUE (this_raise), handled)) + { + if (prev) + TREE_CHAIN (prev) = TREE_CHAIN (this_raise); + else + { + raised = TREE_CHAIN (raised); + if (raised == NULL_TREE) + goto nada; + } + } + else + prev = this_raise; + } + handled = TREE_CHAIN (handled); + } + if (prev == NULL_TREE) + prev = raised; + if (prev) + TREE_CHAIN (prev) = n->data.except_stmt.raised; + nada: + n->data.except_stmt.raised = raised; + } + } + + POPSTACK (except_stack); + last_expr_type = 0; + return raised; +} + +/* Record that exception EX is caught by this exception handler. + Return nonzero if in exception handling construct, otherwise return 0. */ +int +expand_catch (ex) + tree ex; +{ + tree *raises_ptr; + + if (except_stack == 0) + return 0; + raises_ptr = &except_stack->data.except_stmt.handled; + if (*raises_ptr != void_type_node + && ex != NULL_TREE + && ! value_member (ex, *raises_ptr)) + *raises_ptr = tree_cons (NULL_TREE, ex, *raises_ptr); + return 1; +} + +/* Record that this exception handler catches all exceptions. + Return nonzero if in exception handling construct, otherwise return 0. */ + +int +expand_catch_default () +{ + if (except_stack == 0) + return 0; + except_stack->data.except_stmt.handled = void_type_node; + return 1; +} + +int +expand_end_catch () +{ + if (except_stack == 0 || except_stack->data.except_stmt.after_label == 0) + return 0; + expand_goto_internal (NULL_TREE, except_stack->data.except_stmt.after_label, + NULL_RTX); + return 1; +} + +/* Generate RTL for the start of an if-then. COND is the expression + whose truth should be tested. + + If EXITFLAG is nonzero, this conditional is visible to + `exit_something'. */ + +void +expand_start_cond (cond, exitflag) + tree cond; + int exitflag; +{ + struct nesting *thiscond = ALLOC_NESTING (); + + /* Make an entry on cond_stack for the cond we are entering. */ + + thiscond->next = cond_stack; + thiscond->all = nesting_stack; + thiscond->depth = ++nesting_depth; + thiscond->data.cond.next_label = gen_label_rtx (); + /* Before we encounter an `else', we don't need a separate exit label + unless there are supposed to be exit statements + to exit this conditional. */ + thiscond->exit_label = exitflag ? gen_label_rtx () : 0; + thiscond->data.cond.endif_label = thiscond->exit_label; + cond_stack = thiscond; + nesting_stack = thiscond; + + do_jump (cond, thiscond->data.cond.next_label, NULL_RTX); +} + +/* Generate RTL between then-clause and the elseif-clause + of an if-then-elseif-.... */ + +void +expand_start_elseif (cond) + tree cond; +{ + if (cond_stack->data.cond.endif_label == 0) + cond_stack->data.cond.endif_label = gen_label_rtx (); + emit_jump (cond_stack->data.cond.endif_label); + emit_label (cond_stack->data.cond.next_label); + cond_stack->data.cond.next_label = gen_label_rtx (); + do_jump (cond, cond_stack->data.cond.next_label, NULL_RTX); +} + +/* Generate RTL between the then-clause and the else-clause + of an if-then-else. */ + +void +expand_start_else () +{ + if (cond_stack->data.cond.endif_label == 0) + cond_stack->data.cond.endif_label = gen_label_rtx (); + emit_jump (cond_stack->data.cond.endif_label); + emit_label (cond_stack->data.cond.next_label); + cond_stack->data.cond.next_label = 0; /* No more _else or _elseif calls. */ +} + +/* Generate RTL for the end of an if-then. + Pop the record for it off of cond_stack. */ + +void +expand_end_cond () +{ + struct nesting *thiscond = cond_stack; + + do_pending_stack_adjust (); + if (thiscond->data.cond.next_label) + emit_label (thiscond->data.cond.next_label); + if (thiscond->data.cond.endif_label) + emit_label (thiscond->data.cond.endif_label); + + POPSTACK (cond_stack); + last_expr_type = 0; +} + +/* Generate RTL for the start of a loop. EXIT_FLAG is nonzero if this + loop should be exited by `exit_something'. This is a loop for which + `expand_continue' will jump to the top of the loop. + + Make an entry on loop_stack to record the labels associated with + this loop. */ + +struct nesting * +expand_start_loop (exit_flag) + int exit_flag; +{ + register struct nesting *thisloop = ALLOC_NESTING (); + + /* Make an entry on loop_stack for the loop we are entering. */ + + thisloop->next = loop_stack; + thisloop->all = nesting_stack; + thisloop->depth = ++nesting_depth; + thisloop->data.loop.start_label = gen_label_rtx (); + thisloop->data.loop.end_label = gen_label_rtx (); + thisloop->data.loop.continue_label = thisloop->data.loop.start_label; + thisloop->exit_label = exit_flag ? thisloop->data.loop.end_label : 0; + loop_stack = thisloop; + nesting_stack = thisloop; + + do_pending_stack_adjust (); + emit_queue (); + emit_note (NULL_PTR, NOTE_INSN_LOOP_BEG); + emit_label (thisloop->data.loop.start_label); + + return thisloop; +} + +/* Like expand_start_loop but for a loop where the continuation point + (for expand_continue_loop) will be specified explicitly. */ + +struct nesting * +expand_start_loop_continue_elsewhere (exit_flag) + int exit_flag; +{ + struct nesting *thisloop = expand_start_loop (exit_flag); + loop_stack->data.loop.continue_label = gen_label_rtx (); + return thisloop; +} + +/* Specify the continuation point for a loop started with + expand_start_loop_continue_elsewhere. + Use this at the point in the code to which a continue statement + should jump. */ + +void +expand_loop_continue_here () +{ + do_pending_stack_adjust (); + emit_note (NULL_PTR, NOTE_INSN_LOOP_CONT); + emit_label (loop_stack->data.loop.continue_label); +} + +/* Finish a loop. Generate a jump back to the top and the loop-exit label. + Pop the block off of loop_stack. */ + +void +expand_end_loop () +{ + register rtx insn = get_last_insn (); + register rtx start_label = loop_stack->data.loop.start_label; + rtx last_test_insn = 0; + int num_insns = 0; + + /* Mark the continue-point at the top of the loop if none elsewhere. */ + if (start_label == loop_stack->data.loop.continue_label) + emit_note_before (NOTE_INSN_LOOP_CONT, start_label); + + do_pending_stack_adjust (); + + /* If optimizing, perhaps reorder the loop. If the loop + starts with a conditional exit, roll that to the end + where it will optimize together with the jump back. + + We look for the last conditional branch to the exit that we encounter + before hitting 30 insns or a CALL_INSN. If we see an unconditional + branch to the exit first, use it. + + We must also stop at NOTE_INSN_BLOCK_BEG and NOTE_INSN_BLOCK_END notes + because moving them is not valid. */ + + if (optimize + && + ! (GET_CODE (insn) == JUMP_INSN + && GET_CODE (PATTERN (insn)) == SET + && SET_DEST (PATTERN (insn)) == pc_rtx + && GET_CODE (SET_SRC (PATTERN (insn))) == IF_THEN_ELSE)) + { + /* Scan insns from the top of the loop looking for a qualified + conditional exit. */ + for (insn = NEXT_INSN (loop_stack->data.loop.start_label); insn; + insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == CODE_LABEL) + break; + + if (GET_CODE (insn) == NOTE + && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG + || NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END)) + break; + + if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == INSN) + num_insns++; + + if (last_test_insn && num_insns > 30) + break; + + if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) == SET + && SET_DEST (PATTERN (insn)) == pc_rtx + && GET_CODE (SET_SRC (PATTERN (insn))) == IF_THEN_ELSE + && ((GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == LABEL_REF + && (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0) + == loop_stack->data.loop.end_label)) + || (GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 2)) == LABEL_REF + && (XEXP (XEXP (SET_SRC (PATTERN (insn)), 2), 0) + == loop_stack->data.loop.end_label)))) + last_test_insn = insn; + + if (last_test_insn == 0 && GET_CODE (insn) == JUMP_INSN + && GET_CODE (PATTERN (insn)) == SET + && SET_DEST (PATTERN (insn)) == pc_rtx + && GET_CODE (SET_SRC (PATTERN (insn))) == LABEL_REF + && (XEXP (SET_SRC (PATTERN (insn)), 0) + == loop_stack->data.loop.end_label)) + /* Include BARRIER. */ + last_test_insn = NEXT_INSN (insn); + } + + if (last_test_insn != 0 && last_test_insn != get_last_insn ()) + { + /* We found one. Move everything from there up + to the end of the loop, and add a jump into the loop + to jump to there. */ + register rtx newstart_label = gen_label_rtx (); + register rtx start_move = start_label; + + /* If the start label is preceded by a NOTE_INSN_LOOP_CONT note, + then we want to move this note also. */ + if (GET_CODE (PREV_INSN (start_move)) == NOTE + && (NOTE_LINE_NUMBER (PREV_INSN (start_move)) + == NOTE_INSN_LOOP_CONT)) + start_move = PREV_INSN (start_move); + + emit_label_after (newstart_label, PREV_INSN (start_move)); + reorder_insns (start_move, last_test_insn, get_last_insn ()); + emit_jump_insn_after (gen_jump (start_label), + PREV_INSN (newstart_label)); + emit_barrier_after (PREV_INSN (newstart_label)); + start_label = newstart_label; + } + } + + emit_jump (start_label); + emit_note (NULL_PTR, NOTE_INSN_LOOP_END); + emit_label (loop_stack->data.loop.end_label); + + POPSTACK (loop_stack); + + last_expr_type = 0; +} + +/* Generate a jump to the current loop's continue-point. + This is usually the top of the loop, but may be specified + explicitly elsewhere. If not currently inside a loop, + return 0 and do nothing; caller will print an error message. */ + +int +expand_continue_loop (whichloop) + struct nesting *whichloop; +{ + last_expr_type = 0; + if (whichloop == 0) + whichloop = loop_stack; + if (whichloop == 0) + return 0; + expand_goto_internal (NULL_TREE, whichloop->data.loop.continue_label, + NULL_RTX); + return 1; +} + +/* Generate a jump to exit the current loop. If not currently inside a loop, + return 0 and do nothing; caller will print an error message. */ + +int +expand_exit_loop (whichloop) + struct nesting *whichloop; +{ + last_expr_type = 0; + if (whichloop == 0) + whichloop = loop_stack; + if (whichloop == 0) + return 0; + expand_goto_internal (NULL_TREE, whichloop->data.loop.end_label, NULL_RTX); + return 1; +} + +/* Generate a conditional jump to exit the current loop if COND + evaluates to zero. If not currently inside a loop, + return 0 and do nothing; caller will print an error message. */ + +int +expand_exit_loop_if_false (whichloop, cond) + struct nesting *whichloop; + tree cond; +{ + last_expr_type = 0; + if (whichloop == 0) + whichloop = loop_stack; + if (whichloop == 0) + return 0; + do_jump (cond, whichloop->data.loop.end_label, NULL_RTX); + return 1; +} + +/* Return non-zero if we should preserve sub-expressions as separate + pseudos. We never do so if we aren't optimizing. We always do so + if -fexpensive-optimizations. + + Otherwise, we only do so if we are in the "early" part of a loop. I.e., + the loop may still be a small one. */ + +int +preserve_subexpressions_p () +{ + rtx insn; + + if (flag_expensive_optimizations) + return 1; + + if (optimize == 0 || loop_stack == 0) + return 0; + + insn = get_last_insn_anywhere (); + + return (insn + && (INSN_UID (insn) - INSN_UID (loop_stack->data.loop.start_label) + < n_non_fixed_regs * 3)); + +} + +/* Generate a jump to exit the current loop, conditional, binding contour + or case statement. Not all such constructs are visible to this function, + only those started with EXIT_FLAG nonzero. Individual languages use + the EXIT_FLAG parameter to control which kinds of constructs you can + exit this way. + + If not currently inside anything that can be exited, + return 0 and do nothing; caller will print an error message. */ + +int +expand_exit_something () +{ + struct nesting *n; + last_expr_type = 0; + for (n = nesting_stack; n; n = n->all) + if (n->exit_label != 0) + { + expand_goto_internal (NULL_TREE, n->exit_label, NULL_RTX); + return 1; + } + + return 0; +} + +/* Generate RTL to return from the current function, with no value. + (That is, we do not do anything about returning any value.) */ + +void +expand_null_return () +{ + struct nesting *block = block_stack; + rtx last_insn = 0; + + /* Does any pending block have cleanups? */ + + while (block && block->data.block.cleanups == 0) + block = block->next; + + /* If yes, use a goto to return, since that runs cleanups. */ + + expand_null_return_1 (last_insn, block != 0); +} + +/* Generate RTL to return from the current function, with value VAL. */ + +void +expand_value_return (val) + rtx val; +{ + struct nesting *block = block_stack; + rtx last_insn = get_last_insn (); + rtx return_reg = DECL_RTL (DECL_RESULT (current_function_decl)); + + /* Copy the value to the return location + unless it's already there. */ + + if (return_reg != val) + { +#ifdef PROMOTE_FUNCTION_RETURN + enum machine_mode mode = DECL_MODE (DECL_RESULT (current_function_decl)); + tree type = TREE_TYPE (DECL_RESULT (current_function_decl)); + int unsignedp = TREE_UNSIGNED (type); + + if (TREE_CODE (type) == INTEGER_TYPE || TREE_CODE (type) == ENUMERAL_TYPE + || TREE_CODE (type) == BOOLEAN_TYPE || TREE_CODE (type) == CHAR_TYPE + || TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == POINTER_TYPE + || TREE_CODE (type) == OFFSET_TYPE) + { + PROMOTE_MODE (mode, unsignedp, type); + } + + if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) + convert_move (return_reg, val, unsignedp); + else +#endif + emit_move_insn (return_reg, val); + } + if (GET_CODE (return_reg) == REG + && REGNO (return_reg) < FIRST_PSEUDO_REGISTER) + emit_insn (gen_rtx (USE, VOIDmode, return_reg)); + + /* Does any pending block have cleanups? */ + + while (block && block->data.block.cleanups == 0) + block = block->next; + + /* If yes, use a goto to return, since that runs cleanups. + Use LAST_INSN to put cleanups *before* the move insn emitted above. */ + + expand_null_return_1 (last_insn, block != 0); +} + +/* Output a return with no value. If LAST_INSN is nonzero, + pretend that the return takes place after LAST_INSN. + If USE_GOTO is nonzero then don't use a return instruction; + go to the return label instead. This causes any cleanups + of pending blocks to be executed normally. */ + +static void +expand_null_return_1 (last_insn, use_goto) + rtx last_insn; + int use_goto; +{ + rtx end_label = cleanup_label ? cleanup_label : return_label; + + clear_pending_stack_adjust (); + do_pending_stack_adjust (); + last_expr_type = 0; + + /* PCC-struct return always uses an epilogue. */ + if (current_function_returns_pcc_struct || use_goto) + { + if (end_label == 0) + end_label = return_label = gen_label_rtx (); + expand_goto_internal (NULL_TREE, end_label, last_insn); + return; + } + + /* Otherwise output a simple return-insn if one is available, + unless it won't do the job. */ +#ifdef HAVE_return + if (HAVE_return && use_goto == 0 && cleanup_label == 0) + { + emit_jump_insn (gen_return ()); + emit_barrier (); + return; + } +#endif + + /* Otherwise jump to the epilogue. */ + expand_goto_internal (NULL_TREE, end_label, last_insn); +} + +/* Generate RTL to evaluate the expression RETVAL and return it + from the current function. */ + +void +expand_return (retval) + tree retval; +{ + /* If there are any cleanups to be performed, then they will + be inserted following LAST_INSN. It is desirable + that the last_insn, for such purposes, should be the + last insn before computing the return value. Otherwise, cleanups + which call functions can clobber the return value. */ + /* ??? rms: I think that is erroneous, because in C++ it would + run destructors on variables that might be used in the subsequent + computation of the return value. */ + rtx last_insn = 0; + register rtx val = 0; + register rtx op0; + tree retval_rhs; + int cleanups; + struct nesting *block; + + /* If function wants no value, give it none. */ + if (TREE_CODE (TREE_TYPE (TREE_TYPE (current_function_decl))) == VOID_TYPE) + { + expand_expr (retval, NULL_RTX, VOIDmode, 0); + emit_queue (); + expand_null_return (); + return; + } + + /* Are any cleanups needed? E.g. C++ destructors to be run? */ + cleanups = any_pending_cleanups (1); + + if (TREE_CODE (retval) == RESULT_DECL) + retval_rhs = retval; + else if ((TREE_CODE (retval) == MODIFY_EXPR || TREE_CODE (retval) == INIT_EXPR) + && TREE_CODE (TREE_OPERAND (retval, 0)) == RESULT_DECL) + retval_rhs = TREE_OPERAND (retval, 1); + else if (TREE_TYPE (retval) == void_type_node) + /* Recognize tail-recursive call to void function. */ + retval_rhs = retval; + else + retval_rhs = NULL_TREE; + + /* Only use `last_insn' if there are cleanups which must be run. */ + if (cleanups || cleanup_label != 0) + last_insn = get_last_insn (); + + /* Distribute return down conditional expr if either of the sides + may involve tail recursion (see test below). This enhances the number + of tail recursions we see. Don't do this always since it can produce + sub-optimal code in some cases and we distribute assignments into + conditional expressions when it would help. */ + + if (optimize && retval_rhs != 0 + && frame_offset == 0 + && TREE_CODE (retval_rhs) == COND_EXPR + && (TREE_CODE (TREE_OPERAND (retval_rhs, 1)) == CALL_EXPR + || TREE_CODE (TREE_OPERAND (retval_rhs, 2)) == CALL_EXPR)) + { + rtx label = gen_label_rtx (); + do_jump (TREE_OPERAND (retval_rhs, 0), label, NULL_RTX); + expand_return (build (MODIFY_EXPR, TREE_TYPE (current_function_decl), + DECL_RESULT (current_function_decl), + TREE_OPERAND (retval_rhs, 1))); + emit_label (label); + expand_return (build (MODIFY_EXPR, TREE_TYPE (current_function_decl), + DECL_RESULT (current_function_decl), + TREE_OPERAND (retval_rhs, 2))); + return; + } + + /* For tail-recursive call to current function, + just jump back to the beginning. + It's unsafe if any auto variable in this function + has its address taken; for simplicity, + require stack frame to be empty. */ + if (optimize && retval_rhs != 0 + && frame_offset == 0 + && TREE_CODE (retval_rhs) == CALL_EXPR + && TREE_CODE (TREE_OPERAND (retval_rhs, 0)) == ADDR_EXPR + && TREE_OPERAND (TREE_OPERAND (retval_rhs, 0), 0) == current_function_decl + /* Finish checking validity, and if valid emit code + to set the argument variables for the new call. */ + && tail_recursion_args (TREE_OPERAND (retval_rhs, 1), + DECL_ARGUMENTS (current_function_decl))) + { + if (tail_recursion_label == 0) + { + tail_recursion_label = gen_label_rtx (); + emit_label_after (tail_recursion_label, + tail_recursion_reentry); + } + emit_queue (); + expand_goto_internal (NULL_TREE, tail_recursion_label, last_insn); + emit_barrier (); + return; + } +#ifdef HAVE_return + /* This optimization is safe if there are local cleanups + because expand_null_return takes care of them. + ??? I think it should also be safe when there is a cleanup label, + because expand_null_return takes care of them, too. + Any reason why not? */ + if (HAVE_return && cleanup_label == 0 + && ! current_function_returns_pcc_struct) + { + /* If this is return x == y; then generate + if (x == y) return 1; else return 0; + if we can do it with explicit return insns. */ + if (retval_rhs) + switch (TREE_CODE (retval_rhs)) + { + case EQ_EXPR: + case NE_EXPR: + case GT_EXPR: + case GE_EXPR: + case LT_EXPR: + case LE_EXPR: + case TRUTH_ANDIF_EXPR: + case TRUTH_ORIF_EXPR: + case TRUTH_AND_EXPR: + case TRUTH_OR_EXPR: + case TRUTH_NOT_EXPR: + case TRUTH_XOR_EXPR: + op0 = gen_label_rtx (); + jumpifnot (retval_rhs, op0); + expand_value_return (const1_rtx); + emit_label (op0); + expand_value_return (const0_rtx); + return; + } + } +#endif /* HAVE_return */ + + if (cleanups + && retval_rhs != 0 + && TREE_TYPE (retval_rhs) != void_type_node + && GET_CODE (DECL_RTL (DECL_RESULT (current_function_decl))) == REG) + { + /* Calculate the return value into a pseudo reg. */ + val = expand_expr (retval_rhs, NULL_RTX, VOIDmode, 0); + emit_queue (); + /* All temporaries have now been used. */ + free_temp_slots (); + /* Return the calculated value, doing cleanups first. */ + expand_value_return (val); + } + else + { + /* No cleanups or no hard reg used; + calculate value into hard return reg. */ + expand_expr (retval, NULL_RTX, VOIDmode, 0); + emit_queue (); + free_temp_slots (); + expand_value_return (DECL_RTL (DECL_RESULT (current_function_decl))); + } +} + +/* Return 1 if the end of the generated RTX is not a barrier. + This means code already compiled can drop through. */ + +int +drop_through_at_end_p () +{ + rtx insn = get_last_insn (); + while (insn && GET_CODE (insn) == NOTE) + insn = PREV_INSN (insn); + return insn && GET_CODE (insn) != BARRIER; +} + +/* Emit code to alter this function's formal parms for a tail-recursive call. + ACTUALS is a list of actual parameter expressions (chain of TREE_LISTs). + FORMALS is the chain of decls of formals. + Return 1 if this can be done; + otherwise return 0 and do not emit any code. */ + +static int +tail_recursion_args (actuals, formals) + tree actuals, formals; +{ + register tree a = actuals, f = formals; + register int i; + register rtx *argvec; + + /* Check that number and types of actuals are compatible + with the formals. This is not always true in valid C code. + Also check that no formal needs to be addressable + and that all formals are scalars. */ + + /* Also count the args. */ + + for (a = actuals, f = formals, i = 0; a && f; a = TREE_CHAIN (a), f = TREE_CHAIN (f), i++) + { + if (TREE_TYPE (TREE_VALUE (a)) != TREE_TYPE (f)) + return 0; + if (GET_CODE (DECL_RTL (f)) != REG || DECL_MODE (f) == BLKmode) + return 0; + } + if (a != 0 || f != 0) + return 0; + + /* Compute all the actuals. */ + + argvec = (rtx *) alloca (i * sizeof (rtx)); + + for (a = actuals, i = 0; a; a = TREE_CHAIN (a), i++) + argvec[i] = expand_expr (TREE_VALUE (a), NULL_RTX, VOIDmode, 0); + + /* Find which actual values refer to current values of previous formals. + Copy each of them now, before any formal is changed. */ + + for (a = actuals, i = 0; a; a = TREE_CHAIN (a), i++) + { + int copy = 0; + register int j; + for (f = formals, j = 0; j < i; f = TREE_CHAIN (f), j++) + if (reg_mentioned_p (DECL_RTL (f), argvec[i])) + { copy = 1; break; } + if (copy) + argvec[i] = copy_to_reg (argvec[i]); + } + + /* Store the values of the actuals into the formals. */ + + for (f = formals, a = actuals, i = 0; f; + f = TREE_CHAIN (f), a = TREE_CHAIN (a), i++) + { + if (GET_MODE (DECL_RTL (f)) == GET_MODE (argvec[i])) + emit_move_insn (DECL_RTL (f), argvec[i]); + else + convert_move (DECL_RTL (f), argvec[i], + TREE_UNSIGNED (TREE_TYPE (TREE_VALUE (a)))); + } + + free_temp_slots (); + return 1; +} + +/* Generate the RTL code for entering a binding contour. + The variables are declared one by one, by calls to `expand_decl'. + + EXIT_FLAG is nonzero if this construct should be visible to + `exit_something'. */ + +void +expand_start_bindings (exit_flag) + int exit_flag; +{ + struct nesting *thisblock = ALLOC_NESTING (); + + rtx note = emit_note (NULL_PTR, NOTE_INSN_BLOCK_BEG); + + /* Make an entry on block_stack for the block we are entering. */ + + thisblock->next = block_stack; + thisblock->all = nesting_stack; + thisblock->depth = ++nesting_depth; + thisblock->data.block.stack_level = 0; + thisblock->data.block.cleanups = 0; + thisblock->data.block.function_call_count = 0; +#if 0 + if (block_stack) + { + if (block_stack->data.block.cleanups == NULL_TREE + && (block_stack->data.block.outer_cleanups == NULL_TREE + || block_stack->data.block.outer_cleanups == empty_cleanup_list)) + thisblock->data.block.outer_cleanups = empty_cleanup_list; + else + thisblock->data.block.outer_cleanups + = tree_cons (NULL_TREE, block_stack->data.block.cleanups, + block_stack->data.block.outer_cleanups); + } + else + thisblock->data.block.outer_cleanups = 0; +#endif +#if 1 + if (block_stack + && !(block_stack->data.block.cleanups == NULL_TREE + && block_stack->data.block.outer_cleanups == NULL_TREE)) + thisblock->data.block.outer_cleanups + = tree_cons (NULL_TREE, block_stack->data.block.cleanups, + block_stack->data.block.outer_cleanups); + else + thisblock->data.block.outer_cleanups = 0; +#endif + thisblock->data.block.label_chain = 0; + thisblock->data.block.innermost_stack_block = stack_block_stack; + thisblock->data.block.first_insn = note; + thisblock->data.block.block_start_count = ++block_start_count; + thisblock->exit_label = exit_flag ? gen_label_rtx () : 0; + block_stack = thisblock; + nesting_stack = thisblock; + + /* Make a new level for allocating stack slots. */ + push_temp_slots (); +} + +/* Given a pointer to a BLOCK node, save a pointer to the most recently + generated NOTE_INSN_BLOCK_END in the BLOCK_END_NOTE field of the given + BLOCK node. */ + +void +remember_end_note (block) + register tree block; +{ + BLOCK_END_NOTE (block) = last_block_end_note; + last_block_end_note = NULL_RTX; +} + +/* Generate RTL code to terminate a binding contour. + VARS is the chain of VAR_DECL nodes + for the variables bound in this contour. + MARK_ENDS is nonzero if we should put a note at the beginning + and end of this binding contour. + + DONT_JUMP_IN is nonzero if it is not valid to jump into this contour. + (That is true automatically if the contour has a saved stack level.) */ + +void +expand_end_bindings (vars, mark_ends, dont_jump_in) + tree vars; + int mark_ends; + int dont_jump_in; +{ + register struct nesting *thisblock = block_stack; + register tree decl; + + if (warn_unused) + for (decl = vars; decl; decl = TREE_CHAIN (decl)) + if (! TREE_USED (decl) && TREE_CODE (decl) == VAR_DECL + && ! DECL_IN_SYSTEM_HEADER (decl)) + warning_with_decl (decl, "unused variable `%s'"); + + if (thisblock->exit_label) + { + do_pending_stack_adjust (); + emit_label (thisblock->exit_label); + } + + /* If necessary, make a handler for nonlocal gotos taking + place in the function calls in this block. */ + if (function_call_count != thisblock->data.block.function_call_count + && nonlocal_labels + /* Make handler for outermost block + if there were any nonlocal gotos to this function. */ + && (thisblock->next == 0 ? current_function_has_nonlocal_label + /* Make handler for inner block if it has something + special to do when you jump out of it. */ + : (thisblock->data.block.cleanups != 0 + || thisblock->data.block.stack_level != 0))) + { + tree link; + rtx afterward = gen_label_rtx (); + rtx handler_label = gen_label_rtx (); + rtx save_receiver = gen_reg_rtx (Pmode); + + /* Don't let jump_optimize delete the handler. */ + LABEL_PRESERVE_P (handler_label) = 1; + + /* Record the handler address in the stack slot for that purpose, + during this block, saving and restoring the outer value. */ + if (thisblock->next != 0) + { + emit_move_insn (nonlocal_goto_handler_slot, save_receiver); + emit_insn_before (gen_move_insn (save_receiver, + nonlocal_goto_handler_slot), + thisblock->data.block.first_insn); + } + emit_insn_before (gen_move_insn (nonlocal_goto_handler_slot, + gen_rtx (LABEL_REF, Pmode, + handler_label)), + thisblock->data.block.first_insn); + + /* Jump around the handler; it runs only when specially invoked. */ + emit_jump (afterward); + emit_label (handler_label); + +#ifdef HAVE_nonlocal_goto + if (! HAVE_nonlocal_goto) +#endif + /* First adjust our frame pointer to its actual value. It was + previously set to the start of the virtual area corresponding to + the stacked variables when we branched here and now needs to be + adjusted to the actual hardware fp value. + + Assignments are to virtual registers are converted by + instantiate_virtual_regs into the corresponding assignment + to the underlying register (fp in this case) that makes + the original assignment true. + So the following insn will actually be + decrementing fp by STARTING_FRAME_OFFSET. */ + emit_move_insn (virtual_stack_vars_rtx, frame_pointer_rtx); + +#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM + if (fixed_regs[ARG_POINTER_REGNUM]) + { +#ifdef ELIMINABLE_REGS + /* If the argument pointer can be eliminated in favor of the + frame pointer, we don't need to restore it. We assume here + that if such an elimination is present, it can always be used. + This is the case on all known machines; if we don't make this + assumption, we do unnecessary saving on many machines. */ + static struct elims {int from, to;} elim_regs[] = ELIMINABLE_REGS; + int i; + + for (i = 0; i < sizeof elim_regs / sizeof elim_regs[0]; i++) + if (elim_regs[i].from == ARG_POINTER_REGNUM + && elim_regs[i].to == FRAME_POINTER_REGNUM) + break; + + if (i == sizeof elim_regs / sizeof elim_regs [0]) +#endif + { + /* Now restore our arg pointer from the address at which it + was saved in our stack frame. + If there hasn't be space allocated for it yet, make + some now. */ + if (arg_pointer_save_area == 0) + arg_pointer_save_area + = assign_stack_local (Pmode, GET_MODE_SIZE (Pmode), 0); + emit_move_insn (virtual_incoming_args_rtx, + /* We need a pseudo here, or else + instantiate_virtual_regs_1 complains. */ + copy_to_reg (arg_pointer_save_area)); + } + } +#endif + + /* The handler expects the desired label address in the static chain + register. It tests the address and does an appropriate jump + to whatever label is desired. */ + for (link = nonlocal_labels; link; link = TREE_CHAIN (link)) + /* Skip any labels we shouldn't be able to jump to from here. */ + if (! DECL_TOO_LATE (TREE_VALUE (link))) + { + rtx not_this = gen_label_rtx (); + rtx this = gen_label_rtx (); + do_jump_if_equal (static_chain_rtx, + gen_rtx (LABEL_REF, Pmode, DECL_RTL (TREE_VALUE (link))), + this, 0); + emit_jump (not_this); + emit_label (this); + expand_goto (TREE_VALUE (link)); + emit_label (not_this); + } + /* If label is not recognized, abort. */ + emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "abort"), 0, + VOIDmode, 0); + emit_label (afterward); + } + + /* Don't allow jumping into a block that has cleanups or a stack level. */ + if (dont_jump_in + || thisblock->data.block.stack_level != 0 + || thisblock->data.block.cleanups != 0) + { + struct label_chain *chain; + + /* Any labels in this block are no longer valid to go to. + Mark them to cause an error message. */ + for (chain = thisblock->data.block.label_chain; chain; chain = chain->next) + { + DECL_TOO_LATE (chain->label) = 1; + /* If any goto without a fixup came to this label, + that must be an error, because gotos without fixups + come from outside all saved stack-levels and all cleanups. */ + if (TREE_ADDRESSABLE (chain->label)) + error_with_decl (chain->label, + "label `%s' used before containing binding contour"); + } + } + + /* Restore stack level in effect before the block + (only if variable-size objects allocated). */ + /* Perform any cleanups associated with the block. */ + + if (thisblock->data.block.stack_level != 0 + || thisblock->data.block.cleanups != 0) + { + /* Don't let cleanups affect ({...}) constructs. */ + int old_expr_stmts_for_value = expr_stmts_for_value; + rtx old_last_expr_value = last_expr_value; + tree old_last_expr_type = last_expr_type; + expr_stmts_for_value = 0; + + /* Do the cleanups. */ + expand_cleanups (thisblock->data.block.cleanups, NULL_TREE); + do_pending_stack_adjust (); + + expr_stmts_for_value = old_expr_stmts_for_value; + last_expr_value = old_last_expr_value; + last_expr_type = old_last_expr_type; + + /* Restore the stack level. */ + + if (thisblock->data.block.stack_level != 0) + { + emit_stack_restore (thisblock->next ? SAVE_BLOCK : SAVE_FUNCTION, + thisblock->data.block.stack_level, NULL_RTX); + if (nonlocal_goto_handler_slot != 0) + emit_stack_save (SAVE_NONLOCAL, &nonlocal_goto_stack_level, + NULL_RTX); + } + + /* Any gotos out of this block must also do these things. + Also report any gotos with fixups that came to labels in this + level. */ + fixup_gotos (thisblock, + thisblock->data.block.stack_level, + thisblock->data.block.cleanups, + thisblock->data.block.first_insn, + dont_jump_in); + } + + /* Mark the beginning and end of the scope if requested. + We do this now, after running cleanups on the variables + just going out of scope, so they are in scope for their cleanups. */ + + if (mark_ends) + last_block_end_note = emit_note (NULL_PTR, NOTE_INSN_BLOCK_END); + else + /* Get rid of the beginning-mark if we don't make an end-mark. */ + NOTE_LINE_NUMBER (thisblock->data.block.first_insn) = NOTE_INSN_DELETED; + + /* If doing stupid register allocation, make sure lives of all + register variables declared here extend thru end of scope. */ + + if (obey_regdecls) + for (decl = vars; decl; decl = TREE_CHAIN (decl)) + { + rtx rtl = DECL_RTL (decl); + if (TREE_CODE (decl) == VAR_DECL && rtl != 0) + use_variable (rtl); + } + + /* Restore block_stack level for containing block. */ + + stack_block_stack = thisblock->data.block.innermost_stack_block; + POPSTACK (block_stack); + + /* Pop the stack slot nesting and free any slots at this level. */ + pop_temp_slots (); +} + +/* Generate RTL for the automatic variable declaration DECL. + (Other kinds of declarations are simply ignored if seen here.) + CLEANUP is an expression to be executed at exit from this binding contour; + for example, in C++, it might call the destructor for this variable. + + If CLEANUP contains any SAVE_EXPRs, then you must preevaluate them + either before or after calling `expand_decl' but before compiling + any subsequent expressions. This is because CLEANUP may be expanded + more than once, on different branches of execution. + For the same reason, CLEANUP may not contain a CALL_EXPR + except as its topmost node--else `preexpand_calls' would get confused. + + If CLEANUP is nonzero and DECL is zero, we record a cleanup + that is not associated with any particular variable. + + There is no special support here for C++ constructors. + They should be handled by the proper code in DECL_INITIAL. */ + +void +expand_decl (decl) + register tree decl; +{ + struct nesting *thisblock = block_stack; + tree type = TREE_TYPE (decl); + + /* Only automatic variables need any expansion done. + Static and external variables, and external functions, + will be handled by `assemble_variable' (called from finish_decl). + TYPE_DECL and CONST_DECL require nothing. + PARM_DECLs are handled in `assign_parms'. */ + + if (TREE_CODE (decl) != VAR_DECL) + return; + if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) + return; + + /* Create the RTL representation for the variable. */ + + if (type == error_mark_node) + DECL_RTL (decl) = gen_rtx (MEM, BLKmode, const0_rtx); + else if (DECL_SIZE (decl) == 0) + /* Variable with incomplete type. */ + { + if (DECL_INITIAL (decl) == 0) + /* Error message was already done; now avoid a crash. */ + DECL_RTL (decl) = assign_stack_temp (DECL_MODE (decl), 0, 1); + else + /* An initializer is going to decide the size of this array. + Until we know the size, represent its address with a reg. */ + DECL_RTL (decl) = gen_rtx (MEM, BLKmode, gen_reg_rtx (Pmode)); + } + else if (DECL_MODE (decl) != BLKmode + /* If -ffloat-store, don't put explicit float vars + into regs. */ + && !(flag_float_store + && TREE_CODE (type) == REAL_TYPE) + && ! TREE_THIS_VOLATILE (decl) + && ! TREE_ADDRESSABLE (decl) + && (DECL_REGISTER (decl) || ! obey_regdecls)) + { + /* Automatic variable that can go in a register. */ + enum machine_mode reg_mode = DECL_MODE (decl); + int unsignedp = TREE_UNSIGNED (type); + + if (TREE_CODE (type) == INTEGER_TYPE || TREE_CODE (type) == ENUMERAL_TYPE + || TREE_CODE (type) == BOOLEAN_TYPE || TREE_CODE (type) == CHAR_TYPE + || TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == POINTER_TYPE + || TREE_CODE (type) == OFFSET_TYPE) + { + PROMOTE_MODE (reg_mode, unsignedp, type); + } + + DECL_RTL (decl) = gen_reg_rtx (reg_mode); + if (TREE_CODE (type) == POINTER_TYPE) + mark_reg_pointer (DECL_RTL (decl)); + REG_USERVAR_P (DECL_RTL (decl)) = 1; + } + else if (TREE_CODE (DECL_SIZE (decl)) == INTEGER_CST) + { + /* Variable of fixed size that goes on the stack. */ + rtx oldaddr = 0; + rtx addr; + + /* If we previously made RTL for this decl, it must be an array + whose size was determined by the initializer. + The old address was a register; set that register now + to the proper address. */ + if (DECL_RTL (decl) != 0) + { + if (GET_CODE (DECL_RTL (decl)) != MEM + || GET_CODE (XEXP (DECL_RTL (decl), 0)) != REG) + abort (); + oldaddr = XEXP (DECL_RTL (decl), 0); + } + + DECL_RTL (decl) + = assign_stack_temp (DECL_MODE (decl), + ((TREE_INT_CST_LOW (DECL_SIZE (decl)) + + BITS_PER_UNIT - 1) + / BITS_PER_UNIT), + 1); + + /* Set alignment we actually gave this decl. */ + DECL_ALIGN (decl) = (DECL_MODE (decl) == BLKmode ? BIGGEST_ALIGNMENT + : GET_MODE_BITSIZE (DECL_MODE (decl))); + + if (oldaddr) + { + addr = force_operand (XEXP (DECL_RTL (decl), 0), oldaddr); + if (addr != oldaddr) + emit_move_insn (oldaddr, addr); + } + + /* If this is a memory ref that contains aggregate components, + mark it as such for cse and loop optimize. */ + MEM_IN_STRUCT_P (DECL_RTL (decl)) + = (TREE_CODE (TREE_TYPE (decl)) == ARRAY_TYPE + || TREE_CODE (TREE_TYPE (decl)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (decl)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (decl)) == QUAL_UNION_TYPE); +#if 0 + /* If this is in memory because of -ffloat-store, + set the volatile bit, to prevent optimizations from + undoing the effects. */ + if (flag_float_store && TREE_CODE (type) == REAL_TYPE) + MEM_VOLATILE_P (DECL_RTL (decl)) = 1; +#endif + } + else + /* Dynamic-size object: must push space on the stack. */ + { + rtx address, size; + + /* Record the stack pointer on entry to block, if have + not already done so. */ + if (thisblock->data.block.stack_level == 0) + { + do_pending_stack_adjust (); + emit_stack_save (thisblock->next ? SAVE_BLOCK : SAVE_FUNCTION, + &thisblock->data.block.stack_level, + thisblock->data.block.first_insn); + stack_block_stack = thisblock; + } + + /* Compute the variable's size, in bytes. */ + size = expand_expr (size_binop (CEIL_DIV_EXPR, + DECL_SIZE (decl), + size_int (BITS_PER_UNIT)), + NULL_RTX, VOIDmode, 0); + free_temp_slots (); + + /* This is equivalent to calling alloca. */ + current_function_calls_alloca = 1; + + /* Allocate space on the stack for the variable. */ + address = allocate_dynamic_stack_space (size, NULL_RTX, + DECL_ALIGN (decl)); + + if (nonlocal_goto_handler_slot != 0) + emit_stack_save (SAVE_NONLOCAL, &nonlocal_goto_stack_level, NULL_RTX); + + /* Reference the variable indirect through that rtx. */ + DECL_RTL (decl) = gen_rtx (MEM, DECL_MODE (decl), address); + + /* If this is a memory ref that contains aggregate components, + mark it as such for cse and loop optimize. */ + MEM_IN_STRUCT_P (DECL_RTL (decl)) + = (TREE_CODE (TREE_TYPE (decl)) == ARRAY_TYPE + || TREE_CODE (TREE_TYPE (decl)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (decl)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (decl)) == QUAL_UNION_TYPE); + + /* Indicate the alignment we actually gave this variable. */ +#ifdef STACK_BOUNDARY + DECL_ALIGN (decl) = STACK_BOUNDARY; +#else + DECL_ALIGN (decl) = BIGGEST_ALIGNMENT; +#endif + } + + if (TREE_THIS_VOLATILE (decl)) + MEM_VOLATILE_P (DECL_RTL (decl)) = 1; +#if 0 /* A variable is not necessarily unchanging + just because it is const. RTX_UNCHANGING_P + means no change in the function, + not merely no change in the variable's scope. + It is correct to set RTX_UNCHANGING_P if the variable's scope + is the whole function. There's no convenient way to test that. */ + if (TREE_READONLY (decl)) + RTX_UNCHANGING_P (DECL_RTL (decl)) = 1; +#endif + + /* If doing stupid register allocation, make sure life of any + register variable starts here, at the start of its scope. */ + + if (obey_regdecls) + use_variable (DECL_RTL (decl)); +} + +/* Emit code to perform the initialization of a declaration DECL. */ + +void +expand_decl_init (decl) + tree decl; +{ + int was_used = TREE_USED (decl); + + if (TREE_STATIC (decl)) + return; + + /* Compute and store the initial value now. */ + + if (DECL_INITIAL (decl) == error_mark_node) + { + enum tree_code code = TREE_CODE (TREE_TYPE (decl)); + if (code == INTEGER_TYPE || code == REAL_TYPE || code == ENUMERAL_TYPE + || code == POINTER_TYPE) + expand_assignment (decl, convert (TREE_TYPE (decl), integer_zero_node), + 0, 0); + emit_queue (); + } + else if (DECL_INITIAL (decl) && TREE_CODE (DECL_INITIAL (decl)) != TREE_LIST) + { + emit_line_note (DECL_SOURCE_FILE (decl), DECL_SOURCE_LINE (decl)); + expand_assignment (decl, DECL_INITIAL (decl), 0, 0); + emit_queue (); + } + + /* Don't let the initialization count as "using" the variable. */ + TREE_USED (decl) = was_used; + + /* Free any temporaries we made while initializing the decl. */ + free_temp_slots (); +} + +/* CLEANUP is an expression to be executed at exit from this binding contour; + for example, in C++, it might call the destructor for this variable. + + If CLEANUP contains any SAVE_EXPRs, then you must preevaluate them + either before or after calling `expand_decl' but before compiling + any subsequent expressions. This is because CLEANUP may be expanded + more than once, on different branches of execution. + For the same reason, CLEANUP may not contain a CALL_EXPR + except as its topmost node--else `preexpand_calls' would get confused. + + If CLEANUP is nonzero and DECL is zero, we record a cleanup + that is not associated with any particular variable. */ + +int +expand_decl_cleanup (decl, cleanup) + tree decl, cleanup; +{ + struct nesting *thisblock = block_stack; + + /* Error if we are not in any block. */ + if (thisblock == 0) + return 0; + + /* Record the cleanup if there is one. */ + + if (cleanup != 0) + { + thisblock->data.block.cleanups + = temp_tree_cons (decl, cleanup, thisblock->data.block.cleanups); + /* If this block has a cleanup, it belongs in stack_block_stack. */ + stack_block_stack = thisblock; + } + return 1; +} + +/* DECL is an anonymous union. CLEANUP is a cleanup for DECL. + DECL_ELTS is the list of elements that belong to DECL's type. + In each, the TREE_VALUE is a VAR_DECL, and the TREE_PURPOSE a cleanup. */ + +void +expand_anon_union_decl (decl, cleanup, decl_elts) + tree decl, cleanup, decl_elts; +{ + struct nesting *thisblock = block_stack; + rtx x; + + expand_decl (decl, cleanup); + x = DECL_RTL (decl); + + while (decl_elts) + { + tree decl_elt = TREE_VALUE (decl_elts); + tree cleanup_elt = TREE_PURPOSE (decl_elts); + enum machine_mode mode = TYPE_MODE (TREE_TYPE (decl_elt)); + + /* (SUBREG (MEM ...)) at RTL generation time is invalid, so we + instead create a new MEM rtx with the proper mode. */ + if (GET_CODE (x) == MEM) + { + if (mode == GET_MODE (x)) + DECL_RTL (decl_elt) = x; + else + { + DECL_RTL (decl_elt) = gen_rtx (MEM, mode, copy_rtx (XEXP (x, 0))); + MEM_IN_STRUCT_P (DECL_RTL (decl_elt)) = MEM_IN_STRUCT_P (x); + RTX_UNCHANGING_P (DECL_RTL (decl_elt)) = RTX_UNCHANGING_P (x); + } + } + else if (GET_CODE (x) == REG) + { + if (mode == GET_MODE (x)) + DECL_RTL (decl_elt) = x; + else + DECL_RTL (decl_elt) = gen_rtx (SUBREG, mode, x, 0); + } + else + abort (); + + /* Record the cleanup if there is one. */ + + if (cleanup != 0) + thisblock->data.block.cleanups + = temp_tree_cons (decl_elt, cleanup_elt, + thisblock->data.block.cleanups); + + decl_elts = TREE_CHAIN (decl_elts); + } +} + +/* Expand a list of cleanups LIST. + Elements may be expressions or may be nested lists. + + If DONT_DO is nonnull, then any list-element + whose TREE_PURPOSE matches DONT_DO is omitted. + This is sometimes used to avoid a cleanup associated with + a value that is being returned out of the scope. */ + +static void +expand_cleanups (list, dont_do) + tree list; + tree dont_do; +{ + tree tail; + for (tail = list; tail; tail = TREE_CHAIN (tail)) + if (dont_do == 0 || TREE_PURPOSE (tail) != dont_do) + { + if (TREE_CODE (TREE_VALUE (tail)) == TREE_LIST) + expand_cleanups (TREE_VALUE (tail), dont_do); + else + { + /* Cleanups may be run multiple times. For example, + when exiting a binding contour, we expand the + cleanups associated with that contour. When a goto + within that binding contour has a target outside that + contour, it will expand all cleanups from its scope to + the target. Though the cleanups are expanded multiple + times, the control paths are non-overlapping so the + cleanups will not be executed twice. */ + expand_expr (TREE_VALUE (tail), const0_rtx, VOIDmode, 0); + free_temp_slots (); + } + } +} + +/* Move all cleanups from the current block_stack + to the containing block_stack, where they are assumed to + have been created. If anything can cause a temporary to + be created, but not expanded for more than one level of + block_stacks, then this code will have to change. */ + +void +move_cleanups_up () +{ + struct nesting *block = block_stack; + struct nesting *outer = block->next; + + outer->data.block.cleanups + = chainon (block->data.block.cleanups, + outer->data.block.cleanups); + block->data.block.cleanups = 0; +} + +tree +last_cleanup_this_contour () +{ + if (block_stack == 0) + return 0; + + return block_stack->data.block.cleanups; +} + +/* Return 1 if there are any pending cleanups at this point. + If THIS_CONTOUR is nonzero, check the current contour as well. + Otherwise, look only at the contours that enclose this one. */ + +int +any_pending_cleanups (this_contour) + int this_contour; +{ + struct nesting *block; + + if (block_stack == 0) + return 0; + + if (this_contour && block_stack->data.block.cleanups != NULL) + return 1; + if (block_stack->data.block.cleanups == 0 + && (block_stack->data.block.outer_cleanups == 0 +#if 0 + || block_stack->data.block.outer_cleanups == empty_cleanup_list +#endif + )) + return 0; + + for (block = block_stack->next; block; block = block->next) + if (block->data.block.cleanups != 0) + return 1; + + return 0; +} + +/* Enter a case (Pascal) or switch (C) statement. + Push a block onto case_stack and nesting_stack + to accumulate the case-labels that are seen + and to record the labels generated for the statement. + + EXIT_FLAG is nonzero if `exit_something' should exit this case stmt. + Otherwise, this construct is transparent for `exit_something'. + + EXPR is the index-expression to be dispatched on. + TYPE is its nominal type. We could simply convert EXPR to this type, + but instead we take short cuts. */ + +void +expand_start_case (exit_flag, expr, type, printname) + int exit_flag; + tree expr; + tree type; + char *printname; +{ + register struct nesting *thiscase = ALLOC_NESTING (); + + /* Make an entry on case_stack for the case we are entering. */ + + thiscase->next = case_stack; + thiscase->all = nesting_stack; + thiscase->depth = ++nesting_depth; + thiscase->exit_label = exit_flag ? gen_label_rtx () : 0; + thiscase->data.case_stmt.case_list = 0; + thiscase->data.case_stmt.index_expr = expr; + thiscase->data.case_stmt.nominal_type = type; + thiscase->data.case_stmt.default_label = 0; + thiscase->data.case_stmt.num_ranges = 0; + thiscase->data.case_stmt.printname = printname; + thiscase->data.case_stmt.seenlabel = 0; + case_stack = thiscase; + nesting_stack = thiscase; + + do_pending_stack_adjust (); + + /* Make sure case_stmt.start points to something that won't + need any transformation before expand_end_case. */ + if (GET_CODE (get_last_insn ()) != NOTE) + emit_note (NULL_PTR, NOTE_INSN_DELETED); + + thiscase->data.case_stmt.start = get_last_insn (); +} + +/* Start a "dummy case statement" within which case labels are invalid + and are not connected to any larger real case statement. + This can be used if you don't want to let a case statement jump + into the middle of certain kinds of constructs. */ + +void +expand_start_case_dummy () +{ + register struct nesting *thiscase = ALLOC_NESTING (); + + /* Make an entry on case_stack for the dummy. */ + + thiscase->next = case_stack; + thiscase->all = nesting_stack; + thiscase->depth = ++nesting_depth; + thiscase->exit_label = 0; + thiscase->data.case_stmt.case_list = 0; + thiscase->data.case_stmt.start = 0; + thiscase->data.case_stmt.nominal_type = 0; + thiscase->data.case_stmt.default_label = 0; + thiscase->data.case_stmt.num_ranges = 0; + case_stack = thiscase; + nesting_stack = thiscase; +} + +/* End a dummy case statement. */ + +void +expand_end_case_dummy () +{ + POPSTACK (case_stack); +} + +/* Return the data type of the index-expression + of the innermost case statement, or null if none. */ + +tree +case_index_expr_type () +{ + if (case_stack) + return TREE_TYPE (case_stack->data.case_stmt.index_expr); + return 0; +} + +/* Accumulate one case or default label inside a case or switch statement. + VALUE is the value of the case (a null pointer, for a default label). + + If not currently inside a case or switch statement, return 1 and do + nothing. The caller will print a language-specific error message. + If VALUE is a duplicate or overlaps, return 2 and do nothing + except store the (first) duplicate node in *DUPLICATE. + If VALUE is out of range, return 3 and do nothing. + If we are jumping into the scope of a cleaup or var-sized array, return 5. + Return 0 on success. + + Extended to handle range statements. */ + +int +pushcase (value, label, duplicate) + register tree value; + register tree label; + tree *duplicate; +{ + register struct case_node **l; + register struct case_node *n; + tree index_type; + tree nominal_type; + + /* Fail if not inside a real case statement. */ + if (! (case_stack && case_stack->data.case_stmt.start)) + return 1; + + if (stack_block_stack + && stack_block_stack->depth > case_stack->depth) + return 5; + + index_type = TREE_TYPE (case_stack->data.case_stmt.index_expr); + nominal_type = case_stack->data.case_stmt.nominal_type; + + /* If the index is erroneous, avoid more problems: pretend to succeed. */ + if (index_type == error_mark_node) + return 0; + + /* Convert VALUE to the type in which the comparisons are nominally done. */ + if (value != 0) + value = convert (nominal_type, value); + + /* If this is the first label, warn if any insns have been emitted. */ + if (case_stack->data.case_stmt.seenlabel == 0) + { + rtx insn; + for (insn = case_stack->data.case_stmt.start; + insn; + insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == CODE_LABEL) + break; + if (GET_CODE (insn) != NOTE + && (GET_CODE (insn) != INSN || GET_CODE (PATTERN (insn)) != USE)) + { + warning ("unreachable code at beginning of %s", + case_stack->data.case_stmt.printname); + break; + } + } + } + case_stack->data.case_stmt.seenlabel = 1; + + /* Fail if this value is out of range for the actual type of the index + (which may be narrower than NOMINAL_TYPE). */ + if (value != 0 && ! int_fits_type_p (value, index_type)) + return 3; + + /* Fail if this is a duplicate or overlaps another entry. */ + if (value == 0) + { + if (case_stack->data.case_stmt.default_label != 0) + { + *duplicate = case_stack->data.case_stmt.default_label; + return 2; + } + case_stack->data.case_stmt.default_label = label; + } + else + { + /* Find the elt in the chain before which to insert the new value, + to keep the chain sorted in increasing order. + But report an error if this element is a duplicate. */ + for (l = &case_stack->data.case_stmt.case_list; + /* Keep going past elements distinctly less than VALUE. */ + *l != 0 && tree_int_cst_lt ((*l)->high, value); + l = &(*l)->right) + ; + if (*l) + { + /* Element we will insert before must be distinctly greater; + overlap means error. */ + if (! tree_int_cst_lt (value, (*l)->low)) + { + *duplicate = (*l)->code_label; + return 2; + } + } + + /* Add this label to the chain, and succeed. + Copy VALUE so it is on temporary rather than momentary + obstack and will thus survive till the end of the case statement. */ + n = (struct case_node *) oballoc (sizeof (struct case_node)); + n->left = 0; + n->right = *l; + n->high = n->low = copy_node (value); + n->code_label = label; + *l = n; + } + + expand_label (label); + return 0; +} + +/* Like pushcase but this case applies to all values + between VALUE1 and VALUE2 (inclusive). + The return value is the same as that of pushcase + but there is one additional error code: + 4 means the specified range was empty. */ + +int +pushcase_range (value1, value2, label, duplicate) + register tree value1, value2; + register tree label; + tree *duplicate; +{ + register struct case_node **l; + register struct case_node *n; + tree index_type; + tree nominal_type; + + /* Fail if not inside a real case statement. */ + if (! (case_stack && case_stack->data.case_stmt.start)) + return 1; + + if (stack_block_stack + && stack_block_stack->depth > case_stack->depth) + return 5; + + index_type = TREE_TYPE (case_stack->data.case_stmt.index_expr); + nominal_type = case_stack->data.case_stmt.nominal_type; + + /* If the index is erroneous, avoid more problems: pretend to succeed. */ + if (index_type == error_mark_node) + return 0; + + /* If this is the first label, warn if any insns have been emitted. */ + if (case_stack->data.case_stmt.seenlabel == 0) + { + rtx insn; + for (insn = case_stack->data.case_stmt.start; + insn; + insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == CODE_LABEL) + break; + if (GET_CODE (insn) != NOTE + && (GET_CODE (insn) != INSN || GET_CODE (PATTERN (insn)) != USE)) + { + warning ("unreachable code at beginning of %s", + case_stack->data.case_stmt.printname); + break; + } + } + } + case_stack->data.case_stmt.seenlabel = 1; + + /* Convert VALUEs to type in which the comparisons are nominally done. */ + if (value1 == 0) /* Negative infinity. */ + value1 = TYPE_MIN_VALUE(index_type); + value1 = convert (nominal_type, value1); + + if (value2 == 0) /* Positive infinity. */ + value2 = TYPE_MAX_VALUE(index_type); + value2 = convert (nominal_type, value2); + + /* Fail if these values are out of range. */ + if (! int_fits_type_p (value1, index_type)) + return 3; + + if (! int_fits_type_p (value2, index_type)) + return 3; + + /* Fail if the range is empty. */ + if (tree_int_cst_lt (value2, value1)) + return 4; + + /* If the bounds are equal, turn this into the one-value case. */ + if (tree_int_cst_equal (value1, value2)) + return pushcase (value1, label, duplicate); + + /* Find the elt in the chain before which to insert the new value, + to keep the chain sorted in increasing order. + But report an error if this element is a duplicate. */ + for (l = &case_stack->data.case_stmt.case_list; + /* Keep going past elements distinctly less than this range. */ + *l != 0 && tree_int_cst_lt ((*l)->high, value1); + l = &(*l)->right) + ; + if (*l) + { + /* Element we will insert before must be distinctly greater; + overlap means error. */ + if (! tree_int_cst_lt (value2, (*l)->low)) + { + *duplicate = (*l)->code_label; + return 2; + } + } + + /* Add this label to the chain, and succeed. + Copy VALUE1, VALUE2 so they are on temporary rather than momentary + obstack and will thus survive till the end of the case statement. */ + + n = (struct case_node *) oballoc (sizeof (struct case_node)); + n->left = 0; + n->right = *l; + n->low = copy_node (value1); + n->high = copy_node (value2); + n->code_label = label; + *l = n; + + expand_label (label); + + case_stack->data.case_stmt.num_ranges++; + + return 0; +} + +/* Called when the index of a switch statement is an enumerated type + and there is no default label. + + Checks that all enumeration literals are covered by the case + expressions of a switch. Also, warn if there are any extra + switch cases that are *not* elements of the enumerated type. + + If all enumeration literals were covered by the case expressions, + turn one of the expressions into the default expression since it should + not be possible to fall through such a switch. */ + +void +check_for_full_enumeration_handling (type) + tree type; +{ + register struct case_node *n; + register struct case_node **l; + register tree chain; + int all_values = 1; + + /* The time complexity of this loop is currently O(N * M), with + N being the number of members in the enumerated type, and + M being the number of case expressions in the switch. */ + + for (chain = TYPE_VALUES (type); + chain; + chain = TREE_CHAIN (chain)) + { + /* Find a match between enumeral and case expression, if possible. + Quit looking when we've gone too far (since case expressions + are kept sorted in ascending order). Warn about enumerators not + handled in the switch statement case expression list. */ + + for (n = case_stack->data.case_stmt.case_list; + n && tree_int_cst_lt (n->high, TREE_VALUE (chain)); + n = n->right) + ; + + if (!n || tree_int_cst_lt (TREE_VALUE (chain), n->low)) + { + if (warn_switch) + warning ("enumeration value `%s' not handled in switch", + IDENTIFIER_POINTER (TREE_PURPOSE (chain))); + all_values = 0; + } + } + + /* Now we go the other way around; we warn if there are case + expressions that don't correspond to enumerators. This can + occur since C and C++ don't enforce type-checking of + assignments to enumeration variables. */ + + if (warn_switch) + for (n = case_stack->data.case_stmt.case_list; n; n = n->right) + { + for (chain = TYPE_VALUES (type); + chain && !tree_int_cst_equal (n->low, TREE_VALUE (chain)); + chain = TREE_CHAIN (chain)) + ; + + if (!chain) + { + if (TYPE_NAME (type) == 0) + warning ("case value `%d' not in enumerated type", + TREE_INT_CST_LOW (n->low)); + else + warning ("case value `%d' not in enumerated type `%s'", + TREE_INT_CST_LOW (n->low), + IDENTIFIER_POINTER ((TREE_CODE (TYPE_NAME (type)) + == IDENTIFIER_NODE) + ? TYPE_NAME (type) + : DECL_NAME (TYPE_NAME (type)))); + } + if (!tree_int_cst_equal (n->low, n->high)) + { + for (chain = TYPE_VALUES (type); + chain && !tree_int_cst_equal (n->high, TREE_VALUE (chain)); + chain = TREE_CHAIN (chain)) + ; + + if (!chain) + { + if (TYPE_NAME (type) == 0) + warning ("case value `%d' not in enumerated type", + TREE_INT_CST_LOW (n->high)); + else + warning ("case value `%d' not in enumerated type `%s'", + TREE_INT_CST_LOW (n->high), + IDENTIFIER_POINTER ((TREE_CODE (TYPE_NAME (type)) + == IDENTIFIER_NODE) + ? TYPE_NAME (type) + : DECL_NAME (TYPE_NAME (type)))); + } + } + } + +#if 0 + /* ??? This optimization is disabled because it causes valid programs to + fail. ANSI C does not guarantee that an expression with enum type + will have a value that is the same as one of the enumation literals. */ + + /* If all values were found as case labels, make one of them the default + label. Thus, this switch will never fall through. We arbitrarily pick + the last one to make the default since this is likely the most + efficient choice. */ + + if (all_values) + { + for (l = &case_stack->data.case_stmt.case_list; + (*l)->right != 0; + l = &(*l)->right) + ; + + case_stack->data.case_stmt.default_label = (*l)->code_label; + *l = 0; + } +#endif /* 0 */ +} + +/* Terminate a case (Pascal) or switch (C) statement + in which ORIG_INDEX is the expression to be tested. + Generate the code to test it and jump to the right place. */ + +void +expand_end_case (orig_index) + tree orig_index; +{ + tree minval, maxval, range; + rtx default_label = 0; + register struct case_node *n; + int count; + rtx index; + rtx table_label = gen_label_rtx (); + int ncases; + rtx *labelvec; + register int i; + rtx before_case; + register struct nesting *thiscase = case_stack; + tree index_expr = thiscase->data.case_stmt.index_expr; + int unsignedp = TREE_UNSIGNED (TREE_TYPE (index_expr)); + + do_pending_stack_adjust (); + + /* An ERROR_MARK occurs for various reasons including invalid data type. */ + if (TREE_TYPE (index_expr) != error_mark_node) + { + /* If switch expression was an enumerated type, check that all + enumeration literals are covered by the cases. + No sense trying this if there's a default case, however. */ + + if (!thiscase->data.case_stmt.default_label + && TREE_CODE (TREE_TYPE (orig_index)) == ENUMERAL_TYPE + && TREE_CODE (index_expr) != INTEGER_CST) + check_for_full_enumeration_handling (TREE_TYPE (orig_index)); + + /* If this is the first label, warn if any insns have been emitted. */ + if (thiscase->data.case_stmt.seenlabel == 0) + { + rtx insn; + for (insn = get_last_insn (); + insn != case_stack->data.case_stmt.start; + insn = PREV_INSN (insn)) + if (GET_CODE (insn) != NOTE + && (GET_CODE (insn) != INSN || GET_CODE (PATTERN (insn))!= USE)) + { + warning ("unreachable code at beginning of %s", + case_stack->data.case_stmt.printname); + break; + } + } + + /* If we don't have a default-label, create one here, + after the body of the switch. */ + if (thiscase->data.case_stmt.default_label == 0) + { + thiscase->data.case_stmt.default_label + = build_decl (LABEL_DECL, NULL_TREE, NULL_TREE); + expand_label (thiscase->data.case_stmt.default_label); + } + default_label = label_rtx (thiscase->data.case_stmt.default_label); + + before_case = get_last_insn (); + + /* Simplify the case-list before we count it. */ + group_case_nodes (thiscase->data.case_stmt.case_list); + + /* Get upper and lower bounds of case values. + Also convert all the case values to the index expr's data type. */ + + count = 0; + for (n = thiscase->data.case_stmt.case_list; n; n = n->right) + { + /* Check low and high label values are integers. */ + if (TREE_CODE (n->low) != INTEGER_CST) + abort (); + if (TREE_CODE (n->high) != INTEGER_CST) + abort (); + + n->low = convert (TREE_TYPE (index_expr), n->low); + n->high = convert (TREE_TYPE (index_expr), n->high); + + /* Count the elements and track the largest and smallest + of them (treating them as signed even if they are not). */ + if (count++ == 0) + { + minval = n->low; + maxval = n->high; + } + else + { + if (INT_CST_LT (n->low, minval)) + minval = n->low; + if (INT_CST_LT (maxval, n->high)) + maxval = n->high; + } + /* A range counts double, since it requires two compares. */ + if (! tree_int_cst_equal (n->low, n->high)) + count++; + } + + /* Compute span of values. */ + if (count != 0) + range = fold (build (MINUS_EXPR, TREE_TYPE (index_expr), + maxval, minval)); + + if (count == 0 || TREE_CODE (TREE_TYPE (index_expr)) == ERROR_MARK) + { + expand_expr (index_expr, const0_rtx, VOIDmode, 0); + emit_queue (); + emit_jump (default_label); + } + /* If range of values is much bigger than number of values, + make a sequence of conditional branches instead of a dispatch. + If the switch-index is a constant, do it this way + because we can optimize it. */ + +#ifndef CASE_VALUES_THRESHOLD +#ifdef HAVE_casesi +#define CASE_VALUES_THRESHOLD (HAVE_casesi ? 4 : 5) +#else + /* If machine does not have a case insn that compares the + bounds, this means extra overhead for dispatch tables + which raises the threshold for using them. */ +#define CASE_VALUES_THRESHOLD 5 +#endif /* HAVE_casesi */ +#endif /* CASE_VALUES_THRESHOLD */ + + else if (TREE_INT_CST_HIGH (range) != 0 + || count < CASE_VALUES_THRESHOLD + || ((unsigned HOST_WIDE_INT) (TREE_INT_CST_LOW (range)) + > 10 * count) + || TREE_CODE (index_expr) == INTEGER_CST + /* These will reduce to a constant. */ + || (TREE_CODE (index_expr) == CALL_EXPR + && TREE_CODE (TREE_OPERAND (index_expr, 0)) == ADDR_EXPR + && TREE_CODE (TREE_OPERAND (TREE_OPERAND (index_expr, 0), 0)) == FUNCTION_DECL + && DECL_FUNCTION_CODE (TREE_OPERAND (TREE_OPERAND (index_expr, 0), 0)) == BUILT_IN_CLASSIFY_TYPE) + || (TREE_CODE (index_expr) == COMPOUND_EXPR + && TREE_CODE (TREE_OPERAND (index_expr, 1)) == INTEGER_CST)) + { + index = expand_expr (index_expr, NULL_RTX, VOIDmode, 0); + + /* If the index is a short or char that we do not have + an insn to handle comparisons directly, convert it to + a full integer now, rather than letting each comparison + generate the conversion. */ + + if (GET_MODE_CLASS (GET_MODE (index)) == MODE_INT + && (cmp_optab->handlers[(int) GET_MODE(index)].insn_code + == CODE_FOR_nothing)) + { + enum machine_mode wider_mode; + for (wider_mode = GET_MODE (index); wider_mode != VOIDmode; + wider_mode = GET_MODE_WIDER_MODE (wider_mode)) + if (cmp_optab->handlers[(int) wider_mode].insn_code + != CODE_FOR_nothing) + { + index = convert_to_mode (wider_mode, index, unsignedp); + break; + } + } + + emit_queue (); + do_pending_stack_adjust (); + + index = protect_from_queue (index, 0); + if (GET_CODE (index) == MEM) + index = copy_to_reg (index); + if (GET_CODE (index) == CONST_INT + || TREE_CODE (index_expr) == INTEGER_CST) + { + /* Make a tree node with the proper constant value + if we don't already have one. */ + if (TREE_CODE (index_expr) != INTEGER_CST) + { + index_expr + = build_int_2 (INTVAL (index), + !unsignedp && INTVAL (index) >= 0 ? 0 : -1); + index_expr = convert (TREE_TYPE (index_expr), index_expr); + } + + /* For constant index expressions we need only + issue a unconditional branch to the appropriate + target code. The job of removing any unreachable + code is left to the optimisation phase if the + "-O" option is specified. */ + for (n = thiscase->data.case_stmt.case_list; + n; + n = n->right) + { + if (! tree_int_cst_lt (index_expr, n->low) + && ! tree_int_cst_lt (n->high, index_expr)) + break; + } + if (n) + emit_jump (label_rtx (n->code_label)); + else + emit_jump (default_label); + } + else + { + /* If the index expression is not constant we generate + a binary decision tree to select the appropriate + target code. This is done as follows: + + The list of cases is rearranged into a binary tree, + nearly optimal assuming equal probability for each case. + + The tree is transformed into RTL, eliminating + redundant test conditions at the same time. + + If program flow could reach the end of the + decision tree an unconditional jump to the + default code is emitted. */ + + use_cost_table + = (TREE_CODE (TREE_TYPE (orig_index)) != ENUMERAL_TYPE + && estimate_case_costs (thiscase->data.case_stmt.case_list)); + balance_case_nodes (&thiscase->data.case_stmt.case_list, + NULL_PTR); + emit_case_nodes (index, thiscase->data.case_stmt.case_list, + default_label, TREE_TYPE (index_expr)); + emit_jump_if_reachable (default_label); + } + } + else + { + int win = 0; +#ifdef HAVE_casesi + if (HAVE_casesi) + { + enum machine_mode index_mode = SImode; + int index_bits = GET_MODE_BITSIZE (index_mode); + + /* Convert the index to SImode. */ + if (GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (index_expr))) + > GET_MODE_BITSIZE (index_mode)) + { + enum machine_mode omode = TYPE_MODE (TREE_TYPE (index_expr)); + rtx rangertx = expand_expr (range, NULL_RTX, VOIDmode, 0); + + /* We must handle the endpoints in the original mode. */ + index_expr = build (MINUS_EXPR, TREE_TYPE (index_expr), + index_expr, minval); + minval = integer_zero_node; + index = expand_expr (index_expr, NULL_RTX, VOIDmode, 0); + emit_cmp_insn (rangertx, index, LTU, NULL_RTX, omode, 0, 0); + emit_jump_insn (gen_bltu (default_label)); + /* Now we can safely truncate. */ + index = convert_to_mode (index_mode, index, 0); + } + else + { + if (TYPE_MODE (TREE_TYPE (index_expr)) != index_mode) + index_expr = convert (type_for_size (index_bits, 0), + index_expr); + index = expand_expr (index_expr, NULL_RTX, VOIDmode, 0); + } + emit_queue (); + index = protect_from_queue (index, 0); + do_pending_stack_adjust (); + + emit_jump_insn (gen_casesi (index, expand_expr (minval, NULL_RTX, + VOIDmode, 0), + expand_expr (range, NULL_RTX, + VOIDmode, 0), + table_label, default_label)); + win = 1; + } +#endif +#ifdef HAVE_tablejump + if (! win && HAVE_tablejump) + { + index_expr = convert (thiscase->data.case_stmt.nominal_type, + fold (build (MINUS_EXPR, + TREE_TYPE (index_expr), + index_expr, minval))); + index = expand_expr (index_expr, NULL_RTX, VOIDmode, 0); + emit_queue (); + index = protect_from_queue (index, 0); + do_pending_stack_adjust (); + + do_tablejump (index, TYPE_MODE (TREE_TYPE (index_expr)), + expand_expr (range, NULL_RTX, VOIDmode, 0), + table_label, default_label); + win = 1; + } +#endif + if (! win) + abort (); + + /* Get table of labels to jump to, in order of case index. */ + + ncases = TREE_INT_CST_LOW (range) + 1; + labelvec = (rtx *) alloca (ncases * sizeof (rtx)); + bzero (labelvec, ncases * sizeof (rtx)); + + for (n = thiscase->data.case_stmt.case_list; n; n = n->right) + { + register HOST_WIDE_INT i + = TREE_INT_CST_LOW (n->low) - TREE_INT_CST_LOW (minval); + + while (1) + { + labelvec[i] + = gen_rtx (LABEL_REF, Pmode, label_rtx (n->code_label)); + if (i + TREE_INT_CST_LOW (minval) + == TREE_INT_CST_LOW (n->high)) + break; + i++; + } + } + + /* Fill in the gaps with the default. */ + for (i = 0; i < ncases; i++) + if (labelvec[i] == 0) + labelvec[i] = gen_rtx (LABEL_REF, Pmode, default_label); + + /* Output the table */ + emit_label (table_label); + + /* This would be a lot nicer if CASE_VECTOR_PC_RELATIVE + were an expression, instead of an #ifdef/#ifndef. */ + if ( +#ifdef CASE_VECTOR_PC_RELATIVE + 1 || +#endif + flag_pic) + emit_jump_insn (gen_rtx (ADDR_DIFF_VEC, CASE_VECTOR_MODE, + gen_rtx (LABEL_REF, Pmode, table_label), + gen_rtvec_v (ncases, labelvec))); + else + emit_jump_insn (gen_rtx (ADDR_VEC, CASE_VECTOR_MODE, + gen_rtvec_v (ncases, labelvec))); + + /* If the case insn drops through the table, + after the table we must jump to the default-label. + Otherwise record no drop-through after the table. */ +#ifdef CASE_DROPS_THROUGH + emit_jump (default_label); +#else + emit_barrier (); +#endif + } + + before_case = squeeze_notes (NEXT_INSN (before_case), get_last_insn ()); + reorder_insns (before_case, get_last_insn (), + thiscase->data.case_stmt.start); + } + if (thiscase->exit_label) + emit_label (thiscase->exit_label); + + POPSTACK (case_stack); + + free_temp_slots (); +} + +/* Generate code to jump to LABEL if OP1 and OP2 are equal. */ + +static void +do_jump_if_equal (op1, op2, label, unsignedp) + rtx op1, op2, label; + int unsignedp; +{ + if (GET_CODE (op1) == CONST_INT + && GET_CODE (op2) == CONST_INT) + { + if (INTVAL (op1) == INTVAL (op2)) + emit_jump (label); + } + else + { + enum machine_mode mode = GET_MODE (op1); + if (mode == VOIDmode) + mode = GET_MODE (op2); + emit_cmp_insn (op1, op2, EQ, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn (gen_beq (label)); + } +} + +/* Not all case values are encountered equally. This function + uses a heuristic to weight case labels, in cases where that + looks like a reasonable thing to do. + + Right now, all we try to guess is text, and we establish the + following weights: + + chars above space: 16 + digits: 16 + default: 12 + space, punct: 8 + tab: 4 + newline: 2 + other "\" chars: 1 + remaining chars: 0 + + If we find any cases in the switch that are not either -1 or in the range + of valid ASCII characters, or are control characters other than those + commonly used with "\", don't treat this switch scanning text. + + Return 1 if these nodes are suitable for cost estimation, otherwise + return 0. */ + +static int +estimate_case_costs (node) + case_node_ptr node; +{ + tree min_ascii = build_int_2 (-1, -1); + tree max_ascii = convert (TREE_TYPE (node->high), build_int_2 (127, 0)); + case_node_ptr n; + int i; + + /* If we haven't already made the cost table, make it now. Note that the + lower bound of the table is -1, not zero. */ + + if (cost_table == NULL) + { + cost_table = ((short *) xmalloc (129 * sizeof (short))) + 1; + bzero (cost_table - 1, 129 * sizeof (short)); + + for (i = 0; i < 128; i++) + { + if (isalnum (i)) + cost_table[i] = 16; + else if (ispunct (i)) + cost_table[i] = 8; + else if (iscntrl (i)) + cost_table[i] = -1; + } + + cost_table[' '] = 8; + cost_table['\t'] = 4; + cost_table['\0'] = 4; + cost_table['\n'] = 2; + cost_table['\f'] = 1; + cost_table['\v'] = 1; + cost_table['\b'] = 1; + } + + /* See if all the case expressions look like text. It is text if the + constant is >= -1 and the highest constant is <= 127. Do all comparisons + as signed arithmetic since we don't want to ever access cost_table with a + value less than -1. Also check that none of the constants in a range + are strange control characters. */ + + for (n = node; n; n = n->right) + { + if ((INT_CST_LT (n->low, min_ascii)) || INT_CST_LT (max_ascii, n->high)) + return 0; + + for (i = TREE_INT_CST_LOW (n->low); i <= TREE_INT_CST_LOW (n->high); i++) + if (cost_table[i] < 0) + return 0; + } + + /* All interesting values are within the range of interesting + ASCII characters. */ + return 1; +} + +/* Scan an ordered list of case nodes + combining those with consecutive values or ranges. + + Eg. three separate entries 1: 2: 3: become one entry 1..3: */ + +static void +group_case_nodes (head) + case_node_ptr head; +{ + case_node_ptr node = head; + + while (node) + { + rtx lb = next_real_insn (label_rtx (node->code_label)); + case_node_ptr np = node; + + /* Try to group the successors of NODE with NODE. */ + while (((np = np->right) != 0) + /* Do they jump to the same place? */ + && next_real_insn (label_rtx (np->code_label)) == lb + /* Are their ranges consecutive? */ + && tree_int_cst_equal (np->low, + fold (build (PLUS_EXPR, + TREE_TYPE (node->high), + node->high, + integer_one_node))) + /* An overflow is not consecutive. */ + && tree_int_cst_lt (node->high, + fold (build (PLUS_EXPR, + TREE_TYPE (node->high), + node->high, + integer_one_node)))) + { + node->high = np->high; + } + /* NP is the first node after NODE which can't be grouped with it. + Delete the nodes in between, and move on to that node. */ + node->right = np; + node = np; + } +} + +/* Take an ordered list of case nodes + and transform them into a near optimal binary tree, + on the assumption that any target code selection value is as + likely as any other. + + The transformation is performed by splitting the ordered + list into two equal sections plus a pivot. The parts are + then attached to the pivot as left and right branches. Each + branch is is then transformed recursively. */ + +static void +balance_case_nodes (head, parent) + case_node_ptr *head; + case_node_ptr parent; +{ + register case_node_ptr np; + + np = *head; + if (np) + { + int cost = 0; + int i = 0; + int ranges = 0; + register case_node_ptr *npp; + case_node_ptr left; + + /* Count the number of entries on branch. Also count the ranges. */ + + while (np) + { + if (!tree_int_cst_equal (np->low, np->high)) + { + ranges++; + if (use_cost_table) + cost += cost_table[TREE_INT_CST_LOW (np->high)]; + } + + if (use_cost_table) + cost += cost_table[TREE_INT_CST_LOW (np->low)]; + + i++; + np = np->right; + } + + if (i > 2) + { + /* Split this list if it is long enough for that to help. */ + npp = head; + left = *npp; + if (use_cost_table) + { + /* Find the place in the list that bisects the list's total cost, + Here I gets half the total cost. */ + int n_moved = 0; + i = (cost + 1) / 2; + while (1) + { + /* Skip nodes while their cost does not reach that amount. */ + if (!tree_int_cst_equal ((*npp)->low, (*npp)->high)) + i -= cost_table[TREE_INT_CST_LOW ((*npp)->high)]; + i -= cost_table[TREE_INT_CST_LOW ((*npp)->low)]; + if (i <= 0) + break; + npp = &(*npp)->right; + n_moved += 1; + } + if (n_moved == 0) + { + /* Leave this branch lopsided, but optimize left-hand + side and fill in `parent' fields for right-hand side. */ + np = *head; + np->parent = parent; + balance_case_nodes (&np->left, np); + for (; np->right; np = np->right) + np->right->parent = np; + return; + } + } + /* If there are just three nodes, split at the middle one. */ + else if (i == 3) + npp = &(*npp)->right; + else + { + /* Find the place in the list that bisects the list's total cost, + where ranges count as 2. + Here I gets half the total cost. */ + i = (i + ranges + 1) / 2; + while (1) + { + /* Skip nodes while their cost does not reach that amount. */ + if (!tree_int_cst_equal ((*npp)->low, (*npp)->high)) + i--; + i--; + if (i <= 0) + break; + npp = &(*npp)->right; + } + } + *head = np = *npp; + *npp = 0; + np->parent = parent; + np->left = left; + + /* Optimize each of the two split parts. */ + balance_case_nodes (&np->left, np); + balance_case_nodes (&np->right, np); + } + else + { + /* Else leave this branch as one level, + but fill in `parent' fields. */ + np = *head; + np->parent = parent; + for (; np->right; np = np->right) + np->right->parent = np; + } + } +} + +/* Search the parent sections of the case node tree + to see if a test for the lower bound of NODE would be redundant. + INDEX_TYPE is the type of the index expression. + + The instructions to generate the case decision tree are + output in the same order as nodes are processed so it is + known that if a parent node checks the range of the current + node minus one that the current node is bounded at its lower + span. Thus the test would be redundant. */ + +static int +node_has_low_bound (node, index_type) + case_node_ptr node; + tree index_type; +{ + tree low_minus_one; + case_node_ptr pnode; + + /* If the lower bound of this node is the lowest value in the index type, + we need not test it. */ + + if (tree_int_cst_equal (node->low, TYPE_MIN_VALUE (index_type))) + return 1; + + /* If this node has a left branch, the value at the left must be less + than that at this node, so it cannot be bounded at the bottom and + we need not bother testing any further. */ + + if (node->left) + return 0; + + low_minus_one = fold (build (MINUS_EXPR, TREE_TYPE (node->low), + node->low, integer_one_node)); + + /* If the subtraction above overflowed, we can't verify anything. + Otherwise, look for a parent that tests our value - 1. */ + + if (! tree_int_cst_lt (low_minus_one, node->low)) + return 0; + + for (pnode = node->parent; pnode; pnode = pnode->parent) + if (tree_int_cst_equal (low_minus_one, pnode->high)) + return 1; + + return 0; +} + +/* Search the parent sections of the case node tree + to see if a test for the upper bound of NODE would be redundant. + INDEX_TYPE is the type of the index expression. + + The instructions to generate the case decision tree are + output in the same order as nodes are processed so it is + known that if a parent node checks the range of the current + node plus one that the current node is bounded at its upper + span. Thus the test would be redundant. */ + +static int +node_has_high_bound (node, index_type) + case_node_ptr node; + tree index_type; +{ + tree high_plus_one; + case_node_ptr pnode; + + /* If the upper bound of this node is the highest value in the type + of the index expression, we need not test against it. */ + + if (tree_int_cst_equal (node->high, TYPE_MAX_VALUE (index_type))) + return 1; + + /* If this node has a right branch, the value at the right must be greater + than that at this node, so it cannot be bounded at the top and + we need not bother testing any further. */ + + if (node->right) + return 0; + + high_plus_one = fold (build (PLUS_EXPR, TREE_TYPE (node->high), + node->high, integer_one_node)); + + /* If the addition above overflowed, we can't verify anything. + Otherwise, look for a parent that tests our value + 1. */ + + if (! tree_int_cst_lt (node->high, high_plus_one)) + return 0; + + for (pnode = node->parent; pnode; pnode = pnode->parent) + if (tree_int_cst_equal (high_plus_one, pnode->low)) + return 1; + + return 0; +} + +/* Search the parent sections of the + case node tree to see if both tests for the upper and lower + bounds of NODE would be redundant. */ + +static int +node_is_bounded (node, index_type) + case_node_ptr node; + tree index_type; +{ + return (node_has_low_bound (node, index_type) + && node_has_high_bound (node, index_type)); +} + +/* Emit an unconditional jump to LABEL unless it would be dead code. */ + +static void +emit_jump_if_reachable (label) + rtx label; +{ + if (GET_CODE (get_last_insn ()) != BARRIER) + emit_jump (label); +} + +/* Emit step-by-step code to select a case for the value of INDEX. + The thus generated decision tree follows the form of the + case-node binary tree NODE, whose nodes represent test conditions. + INDEX_TYPE is the type of the index of the switch. + + Care is taken to prune redundant tests from the decision tree + by detecting any boundary conditions already checked by + emitted rtx. (See node_has_high_bound, node_has_low_bound + and node_is_bounded, above.) + + Where the test conditions can be shown to be redundant we emit + an unconditional jump to the target code. As a further + optimization, the subordinates of a tree node are examined to + check for bounded nodes. In this case conditional and/or + unconditional jumps as a result of the boundary check for the + current node are arranged to target the subordinates associated + code for out of bound conditions on the current node node. + + We can assume that when control reaches the code generated here, + the index value has already been compared with the parents + of this node, and determined to be on the same side of each parent + as this node is. Thus, if this node tests for the value 51, + and a parent tested for 52, we don't need to consider + the possibility of a value greater than 51. If another parent + tests for the value 50, then this node need not test anything. */ + +static void +emit_case_nodes (index, node, default_label, index_type) + rtx index; + case_node_ptr node; + rtx default_label; + tree index_type; +{ + /* If INDEX has an unsigned type, we must make unsigned branches. */ + int unsignedp = TREE_UNSIGNED (index_type); + typedef rtx rtx_function (); + rtx_function *gen_bgt_pat = unsignedp ? gen_bgtu : gen_bgt; + rtx_function *gen_bge_pat = unsignedp ? gen_bgeu : gen_bge; + rtx_function *gen_blt_pat = unsignedp ? gen_bltu : gen_blt; + rtx_function *gen_ble_pat = unsignedp ? gen_bleu : gen_ble; + enum machine_mode mode = GET_MODE (index); + + /* See if our parents have already tested everything for us. + If they have, emit an unconditional jump for this node. */ + if (node_is_bounded (node, index_type)) + emit_jump (label_rtx (node->code_label)); + + else if (tree_int_cst_equal (node->low, node->high)) + { + /* Node is single valued. First see if the index expression matches + this node and then check our children, if any. */ + + do_jump_if_equal (index, expand_expr (node->low, NULL_RTX, VOIDmode, 0), + label_rtx (node->code_label), unsignedp); + + if (node->right != 0 && node->left != 0) + { + /* This node has children on both sides. + Dispatch to one side or the other + by comparing the index value with this node's value. + If one subtree is bounded, check that one first, + so we can avoid real branches in the tree. */ + + if (node_is_bounded (node->right, index_type)) + { + emit_cmp_insn (index, expand_expr (node->high, NULL_RTX, + VOIDmode, 0), + GT, NULL_RTX, mode, unsignedp, 0); + + emit_jump_insn ((*gen_bgt_pat) (label_rtx (node->right->code_label))); + emit_case_nodes (index, node->left, default_label, index_type); + } + + else if (node_is_bounded (node->left, index_type)) + { + emit_cmp_insn (index, expand_expr (node->high, NULL_RTX, + VOIDmode, 0), + LT, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_blt_pat) (label_rtx (node->left->code_label))); + emit_case_nodes (index, node->right, default_label, index_type); + } + + else + { + /* Neither node is bounded. First distinguish the two sides; + then emit the code for one side at a time. */ + + tree test_label + = build_decl (LABEL_DECL, NULL_TREE, NULL_TREE); + + /* See if the value is on the right. */ + emit_cmp_insn (index, expand_expr (node->high, NULL_RTX, + VOIDmode, 0), + GT, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_bgt_pat) (label_rtx (test_label))); + + /* Value must be on the left. + Handle the left-hand subtree. */ + emit_case_nodes (index, node->left, default_label, index_type); + /* If left-hand subtree does nothing, + go to default. */ + emit_jump_if_reachable (default_label); + + /* Code branches here for the right-hand subtree. */ + expand_label (test_label); + emit_case_nodes (index, node->right, default_label, index_type); + } + } + + else if (node->right != 0 && node->left == 0) + { + /* Here we have a right child but no left so we issue conditional + branch to default and process the right child. + + Omit the conditional branch to default if we it avoid only one + right child; it costs too much space to save so little time. */ + + if (node->right->right || node->right->left + || !tree_int_cst_equal (node->right->low, node->right->high)) + { + if (!node_has_low_bound (node, index_type)) + { + emit_cmp_insn (index, expand_expr (node->high, NULL_RTX, + VOIDmode, 0), + LT, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_blt_pat) (default_label)); + } + + emit_case_nodes (index, node->right, default_label, index_type); + } + else + /* We cannot process node->right normally + since we haven't ruled out the numbers less than + this node's value. So handle node->right explicitly. */ + do_jump_if_equal (index, + expand_expr (node->right->low, NULL_RTX, + VOIDmode, 0), + label_rtx (node->right->code_label), unsignedp); + } + + else if (node->right == 0 && node->left != 0) + { + /* Just one subtree, on the left. */ + +#if 0 /* The following code and comment were formerly part + of the condition here, but they didn't work + and I don't understand what the idea was. -- rms. */ + /* If our "most probable entry" is less probable + than the default label, emit a jump to + the default label using condition codes + already lying around. With no right branch, + a branch-greater-than will get us to the default + label correctly. */ + if (use_cost_table + && cost_table[TREE_INT_CST_LOW (node->high)] < 12) + ; +#endif /* 0 */ + if (node->left->left || node->left->right + || !tree_int_cst_equal (node->left->low, node->left->high)) + { + if (!node_has_high_bound (node, index_type)) + { + emit_cmp_insn (index, expand_expr (node->high, NULL_RTX, + VOIDmode, 0), + GT, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_bgt_pat) (default_label)); + } + + emit_case_nodes (index, node->left, default_label, index_type); + } + else + /* We cannot process node->left normally + since we haven't ruled out the numbers less than + this node's value. So handle node->left explicitly. */ + do_jump_if_equal (index, + expand_expr (node->left->low, NULL_RTX, + VOIDmode, 0), + label_rtx (node->left->code_label), unsignedp); + } + } + else + { + /* Node is a range. These cases are very similar to those for a single + value, except that we do not start by testing whether this node + is the one to branch to. */ + + if (node->right != 0 && node->left != 0) + { + /* Node has subtrees on both sides. + If the right-hand subtree is bounded, + test for it first, since we can go straight there. + Otherwise, we need to make a branch in the control structure, + then handle the two subtrees. */ + tree test_label = 0; + + emit_cmp_insn (index, expand_expr (node->high, NULL_RTX, + VOIDmode, 0), + GT, NULL_RTX, mode, unsignedp, 0); + + if (node_is_bounded (node->right, index_type)) + /* Right hand node is fully bounded so we can eliminate any + testing and branch directly to the target code. */ + emit_jump_insn ((*gen_bgt_pat) (label_rtx (node->right->code_label))); + else + { + /* Right hand node requires testing. + Branch to a label where we will handle it later. */ + + test_label = build_decl (LABEL_DECL, NULL_TREE, NULL_TREE); + emit_jump_insn ((*gen_bgt_pat) (label_rtx (test_label))); + } + + /* Value belongs to this node or to the left-hand subtree. */ + + emit_cmp_insn (index, expand_expr (node->low, NULL_RTX, VOIDmode, 0), + GE, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_bge_pat) (label_rtx (node->code_label))); + + /* Handle the left-hand subtree. */ + emit_case_nodes (index, node->left, default_label, index_type); + + /* If right node had to be handled later, do that now. */ + + if (test_label) + { + /* If the left-hand subtree fell through, + don't let it fall into the right-hand subtree. */ + emit_jump_if_reachable (default_label); + + expand_label (test_label); + emit_case_nodes (index, node->right, default_label, index_type); + } + } + + else if (node->right != 0 && node->left == 0) + { + /* Deal with values to the left of this node, + if they are possible. */ + if (!node_has_low_bound (node, index_type)) + { + emit_cmp_insn (index, expand_expr (node->low, NULL_RTX, + VOIDmode, 0), + LT, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_blt_pat) (default_label)); + } + + /* Value belongs to this node or to the right-hand subtree. */ + + emit_cmp_insn (index, expand_expr (node->high, NULL_RTX, + VOIDmode, 0), + LE, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_ble_pat) (label_rtx (node->code_label))); + + emit_case_nodes (index, node->right, default_label, index_type); + } + + else if (node->right == 0 && node->left != 0) + { + /* Deal with values to the right of this node, + if they are possible. */ + if (!node_has_high_bound (node, index_type)) + { + emit_cmp_insn (index, expand_expr (node->high, NULL_RTX, + VOIDmode, 0), + GT, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_bgt_pat) (default_label)); + } + + /* Value belongs to this node or to the left-hand subtree. */ + + emit_cmp_insn (index, expand_expr (node->low, NULL_RTX, VOIDmode, 0), + GE, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_bge_pat) (label_rtx (node->code_label))); + + emit_case_nodes (index, node->left, default_label, index_type); + } + + else + { + /* Node has no children so we check low and high bounds to remove + redundant tests. Only one of the bounds can exist, + since otherwise this node is bounded--a case tested already. */ + + if (!node_has_high_bound (node, index_type)) + { + emit_cmp_insn (index, expand_expr (node->high, NULL_RTX, + VOIDmode, 0), + GT, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_bgt_pat) (default_label)); + } + + if (!node_has_low_bound (node, index_type)) + { + emit_cmp_insn (index, expand_expr (node->low, NULL_RTX, + VOIDmode, 0), + LT, NULL_RTX, mode, unsignedp, 0); + emit_jump_insn ((*gen_blt_pat) (default_label)); + } + + emit_jump (label_rtx (node->code_label)); + } + } +} + +/* These routines are used by the loop unrolling code. They copy BLOCK trees + so that the debugging info will be correct for the unrolled loop. */ + +/* Indexed by block number, contains a pointer to the N'th block node. */ + +static tree *block_vector; + +void +find_loop_tree_blocks () +{ + tree block = DECL_INITIAL (current_function_decl); + + /* There first block is for the function body, and does not have + corresponding block notes. Don't include it in the block vector. */ + block = BLOCK_SUBBLOCKS (block); + + block_vector = identify_blocks (block, get_insns ()); +} + +void +unroll_block_trees () +{ + tree block = DECL_INITIAL (current_function_decl); + + reorder_blocks (block_vector, block, get_insns ()); +} + diff --git a/gnu/usr.bin/cc/lib/stor-layout.c b/gnu/usr.bin/cc/lib/stor-layout.c new file mode 100644 index 000000000000..c0efe3dab899 --- /dev/null +++ b/gnu/usr.bin/cc/lib/stor-layout.c @@ -0,0 +1,1170 @@ +/* C-compiler utilities for types and variables storage layout + Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include "config.h" +#include + +#include "tree.h" +#include "function.h" + +#define CEIL(x,y) (((x) + (y) - 1) / (y)) + +/* Data type for the expressions representing sizes of data types. + It is the first integer type laid out. + In C, this is int. */ + +tree sizetype; + +/* An integer constant with value 0 whose type is sizetype. */ + +tree size_zero_node; + +/* An integer constant with value 1 whose type is sizetype. */ + +tree size_one_node; + +/* If nonzero, this is an upper limit on alignment of structure fields. + The value is measured in bits. */ +int maximum_field_alignment; + +#define GET_MODE_ALIGNMENT(MODE) \ + MIN (BIGGEST_ALIGNMENT, \ + MAX (1, (GET_MODE_UNIT_SIZE (MODE) * BITS_PER_UNIT))) + +/* SAVE_EXPRs for sizes of types and decls, waiting to be expanded. */ + +static tree pending_sizes; + +/* Nonzero means cannot safely call expand_expr now, + so put variable sizes onto `pending_sizes' instead. */ + +int immediate_size_expand; + +tree +get_pending_sizes () +{ + tree chain = pending_sizes; + tree t; + + /* Put each SAVE_EXPR into the current function. */ + for (t = chain; t; t = TREE_CHAIN (t)) + SAVE_EXPR_CONTEXT (TREE_VALUE (t)) = current_function_decl; + pending_sizes = 0; + return chain; +} + +/* Given a size SIZE that isn't constant, return a SAVE_EXPR + to serve as the actual size-expression for a type or decl. */ + +tree +variable_size (size) + tree size; +{ + size = save_expr (size); + + if (global_bindings_p ()) + { + if (TREE_CONSTANT (size)) + error ("type size can't be explicitly evaluated"); + else + error ("variable-size type declared outside of any function"); + + return size_int (1); + } + + if (immediate_size_expand) + /* NULL_RTX is not defined; neither is the rtx type. + Also, we would like to pass const0_rtx here, but don't have it. */ + expand_expr (size, expand_expr (integer_zero_node, NULL_PTR, VOIDmode, 0), + VOIDmode, 0); + else + pending_sizes = tree_cons (NULL_TREE, size, pending_sizes); + + return size; +} + +#ifndef MAX_FIXED_MODE_SIZE +#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode) +#endif + +/* Return the machine mode to use for a nonscalar of SIZE bits. + The mode must be in class CLASS, and have exactly that many bits. + If LIMIT is nonzero, modes of wider than MAX_FIXED_MODE_SIZE will not + be used. */ + +enum machine_mode +mode_for_size (size, class, limit) + unsigned int size; + enum mode_class class; + int limit; +{ + register enum machine_mode mode; + + if (limit && size > MAX_FIXED_MODE_SIZE) + return BLKmode; + + /* Get the last mode which has this size, in the specified class. */ + for (mode = GET_CLASS_NARROWEST_MODE (class); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + if (GET_MODE_BITSIZE (mode) == size) + return mode; + + return BLKmode; +} + +/* Return the value of VALUE, rounded up to a multiple of DIVISOR. */ + +tree +round_up (value, divisor) + tree value; + int divisor; +{ + return size_binop (MULT_EXPR, + size_binop (CEIL_DIV_EXPR, value, size_int (divisor)), + size_int (divisor)); +} + +/* Set the size, mode and alignment of a ..._DECL node. + TYPE_DECL does need this for C++. + Note that LABEL_DECL and CONST_DECL nodes do not need this, + and FUNCTION_DECL nodes have them set up in a special (and simple) way. + Don't call layout_decl for them. + + KNOWN_ALIGN is the amount of alignment we can assume this + decl has with no special effort. It is relevant only for FIELD_DECLs + and depends on the previous fields. + All that matters about KNOWN_ALIGN is which powers of 2 divide it. + If KNOWN_ALIGN is 0, it means, "as much alignment as you like": + the record will be aligned to suit. */ + +void +layout_decl (decl, known_align) + tree decl; + unsigned known_align; +{ + register tree type = TREE_TYPE (decl); + register enum tree_code code = TREE_CODE (decl); + int spec_size = DECL_FIELD_SIZE (decl); + + if (code == CONST_DECL) + return; + + if (code != VAR_DECL && code != PARM_DECL && code != RESULT_DECL + && code != FIELD_DECL && code != TYPE_DECL) + abort (); + + if (type == error_mark_node) + { + type = void_type_node; + spec_size = 0; + } + + /* Usually the size and mode come from the data type without change. */ + + DECL_MODE (decl) = TYPE_MODE (type); + DECL_SIZE (decl) = TYPE_SIZE (type); + TREE_UNSIGNED (decl) = TREE_UNSIGNED (type); + + if (code == FIELD_DECL && DECL_BIT_FIELD (decl)) + { + /* This is a bit-field. We don't know how to handle + them except for integers and enums, and front end should + never generate them otherwise. */ + + if (! (TREE_CODE (type) == INTEGER_TYPE + || TREE_CODE (type) == ENUMERAL_TYPE)) + abort (); + + if (spec_size == 0 && DECL_NAME (decl) != 0) + abort (); + + /* Size is specified number of bits. */ + DECL_SIZE (decl) = size_int (spec_size); + } + /* Force alignment required for the data type. + But if the decl itself wants greater alignment, don't override that. + Likewise, if the decl is packed, don't override it. */ + else if (DECL_ALIGN (decl) == 0 + || (! DECL_PACKED (decl) && TYPE_ALIGN (type) > DECL_ALIGN (decl))) + DECL_ALIGN (decl) = TYPE_ALIGN (type); + + /* See if we can use an ordinary integer mode for a bit-field. */ + /* Conditions are: a fixed size that is correct for another mode + and occupying a complete byte or bytes on proper boundary. */ + if (code == FIELD_DECL) + { + DECL_BIT_FIELD_TYPE (decl) = DECL_BIT_FIELD (decl) ? type : 0; + if (maximum_field_alignment != 0) + DECL_ALIGN (decl) = MIN (DECL_ALIGN (decl), maximum_field_alignment); + } + + if (DECL_BIT_FIELD (decl) + && TYPE_SIZE (type) != 0 + && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) + { + register enum machine_mode xmode + = mode_for_size (TREE_INT_CST_LOW (DECL_SIZE (decl)), MODE_INT, 1); + + if (xmode != BLKmode + && known_align % GET_MODE_ALIGNMENT (xmode) == 0) + { + DECL_ALIGN (decl) = MAX (GET_MODE_ALIGNMENT (xmode), + DECL_ALIGN (decl)); + DECL_MODE (decl) = xmode; + DECL_SIZE (decl) = size_int (GET_MODE_BITSIZE (xmode)); + /* This no longer needs to be accessed as a bit field. */ + DECL_BIT_FIELD (decl) = 0; + } + } + + /* Evaluate nonconstant size only once, either now or as soon as safe. */ + if (DECL_SIZE (decl) != 0 && TREE_CODE (DECL_SIZE (decl)) != INTEGER_CST) + DECL_SIZE (decl) = variable_size (DECL_SIZE (decl)); +} + +/* Lay out a RECORD_TYPE type (a C struct). + This means laying out the fields, determining their positions, + and computing the overall size and required alignment of the record. + Note that if you set the TYPE_ALIGN before calling this + then the struct is aligned to at least that boundary. + + If the type has basetypes, you must call layout_basetypes + before calling this function. + + The return value is a list of static members of the record. + They still need to be laid out. */ + +static tree +layout_record (rec) + tree rec; +{ + register tree field; +#ifdef STRUCTURE_SIZE_BOUNDARY + unsigned record_align = MAX (STRUCTURE_SIZE_BOUNDARY, TYPE_ALIGN (rec)); +#else + unsigned record_align = MAX (BITS_PER_UNIT, TYPE_ALIGN (rec)); +#endif + /* These must be laid out *after* the record is. */ + tree pending_statics = NULL_TREE; + /* Record size so far is CONST_SIZE + VAR_SIZE bits, + where CONST_SIZE is an integer + and VAR_SIZE is a tree expression. + If VAR_SIZE is null, the size is just CONST_SIZE. + Naturally we try to avoid using VAR_SIZE. */ + register int const_size = 0; + register tree var_size = 0; + /* Once we start using VAR_SIZE, this is the maximum alignment + that we know VAR_SIZE has. */ + register int var_align = BITS_PER_UNIT; + + + for (field = TYPE_FIELDS (rec); field; field = TREE_CHAIN (field)) + { + register int desired_align; + + /* If FIELD is static, then treat it like a separate variable, + not really like a structure field. + If it is a FUNCTION_DECL, it's a method. + In both cases, all we do is lay out the decl, + and we do it *after* the record is laid out. */ + + if (TREE_STATIC (field)) + { + pending_statics = tree_cons (NULL_TREE, field, pending_statics); + continue; + } + /* Enumerators and enum types which are local to this class need not + be laid out. Likewise for initialized constant fields. */ + if (TREE_CODE (field) != FIELD_DECL) + continue; + + /* Lay out the field so we know what alignment it needs. + For KNOWN_ALIGN, pass the number of bits from start of record + or some divisor of it. */ + + /* For a packed field, use the alignment as specified, + disregarding what the type would want. */ + if (DECL_PACKED (field)) + desired_align = DECL_ALIGN (field); + layout_decl (field, var_size ? var_align : const_size); + if (! DECL_PACKED (field)) + desired_align = DECL_ALIGN (field); + /* Some targets (i.e. VMS) limit struct field alignment + to a lower boundary than alignment of variables. */ +#ifdef BIGGEST_FIELD_ALIGNMENT + desired_align = MIN (desired_align, BIGGEST_FIELD_ALIGNMENT); +#endif + + /* Record must have at least as much alignment as any field. + Otherwise, the alignment of the field within the record + is meaningless. */ + +#ifndef PCC_BITFIELD_TYPE_MATTERS + record_align = MAX (record_align, desired_align); +#else + if (PCC_BITFIELD_TYPE_MATTERS && TREE_TYPE (field) != error_mark_node + && DECL_BIT_FIELD_TYPE (field) + && ! integer_zerop (TYPE_SIZE (TREE_TYPE (field)))) + { + /* For these machines, a zero-length field does not + affect the alignment of the structure as a whole. + It does, however, affect the alignment of the next field + within the structure. */ + if (! integer_zerop (DECL_SIZE (field))) + record_align = MAX (record_align, desired_align); + else if (! DECL_PACKED (field)) + desired_align = TYPE_ALIGN (TREE_TYPE (field)); + /* A named bit field of declared type `int' + forces the entire structure to have `int' alignment. */ + if (DECL_NAME (field) != 0) + { + int type_align = TYPE_ALIGN (TREE_TYPE (field)); + if (maximum_field_alignment != 0) + type_align = MIN (type_align, maximum_field_alignment); + + record_align = MAX (record_align, type_align); + } + } + else + record_align = MAX (record_align, desired_align); +#endif + + /* Does this field automatically have alignment it needs + by virtue of the fields that precede it and the record's + own alignment? */ + + if (const_size % desired_align != 0 + || (var_align % desired_align != 0 + && var_size != 0)) + { + /* No, we need to skip space before this field. + Bump the cumulative size to multiple of field alignment. */ + + if (var_size == 0 + || var_align % desired_align == 0) + const_size + = CEIL (const_size, desired_align) * desired_align; + else + { + if (const_size > 0) + var_size = size_binop (PLUS_EXPR, var_size, + size_int (const_size)); + const_size = 0; + var_size = round_up (var_size, desired_align); + var_align = MIN (var_align, desired_align); + } + } + +#ifdef PCC_BITFIELD_TYPE_MATTERS + if (PCC_BITFIELD_TYPE_MATTERS + && TREE_CODE (field) == FIELD_DECL + && TREE_TYPE (field) != error_mark_node + && DECL_BIT_FIELD_TYPE (field) + && !DECL_PACKED (field) + && !integer_zerop (DECL_SIZE (field))) + { + int type_align = TYPE_ALIGN (TREE_TYPE (field)); + register tree dsize = DECL_SIZE (field); + int field_size = TREE_INT_CST_LOW (dsize); + + if (maximum_field_alignment != 0) + type_align = MIN (type_align, maximum_field_alignment); + + /* A bit field may not span the unit of alignment of its type. + Advance to next boundary if necessary. */ + /* ??? There is some uncertainty here as to what + should be done if type_align is less than the width of the type. + That can happen because the width exceeds BIGGEST_ALIGNMENT + or because it exceeds maximum_field_alignment. */ + if (const_size / type_align + != (const_size + field_size - 1) / type_align) + const_size = CEIL (const_size, type_align) * type_align; + } +#endif + +/* No existing machine description uses this parameter. + So I have made it in this aspect identical to PCC_BITFIELD_TYPE_MATTERS. */ +#ifdef BITFIELD_NBYTES_LIMITED + if (BITFIELD_NBYTES_LIMITED + && TREE_CODE (field) == FIELD_DECL + && TREE_TYPE (field) != error_mark_node + && DECL_BIT_FIELD_TYPE (field) + && !DECL_PACKED (field) + && !integer_zerop (DECL_SIZE (field))) + { + int type_align = TYPE_ALIGN (TREE_TYPE (field)); + register tree dsize = DECL_SIZE (field); + int field_size = TREE_INT_CST_LOW (dsize); + + if (maximum_field_alignment != 0) + type_align = MIN (type_align, maximum_field_alignment); + + /* A bit field may not span the unit of alignment of its type. + Advance to next boundary if necessary. */ + if (const_size / type_align + != (const_size + field_size - 1) / type_align) + const_size = CEIL (const_size, type_align) * type_align; + } +#endif + + /* Size so far becomes the position of this field. */ + + if (var_size && const_size) + DECL_FIELD_BITPOS (field) + = size_binop (PLUS_EXPR, var_size, size_int (const_size)); + else if (var_size) + DECL_FIELD_BITPOS (field) = var_size; + else + DECL_FIELD_BITPOS (field) = size_int (const_size); + + /* If this field is an anonymous union, + give each union-member the same position as the union has. + + ??? This is a real kludge because it makes the structure + of the types look strange. This feature is only used by + C++, which should have build_component_ref build two + COMPONENT_REF operations, one for the union and one for + the inner field. We set the offset of this field to zero + so that either the old or the correct method will work. + Setting DECL_FIELD_CONTEXT is wrong unless the inner fields are + moved into the type of this field, but nothing seems to break + by doing this. This kludge should be removed after 2.4. */ + + if (DECL_NAME (field) == 0 + && TREE_CODE (TREE_TYPE (field)) == UNION_TYPE) + { + tree uelt = TYPE_FIELDS (TREE_TYPE (field)); + for (; uelt; uelt = TREE_CHAIN (uelt)) + { + DECL_FIELD_CONTEXT (uelt) = DECL_FIELD_CONTEXT (field); + DECL_FIELD_BITPOS (uelt) = DECL_FIELD_BITPOS (field); + } + + DECL_FIELD_BITPOS (field) = integer_zero_node; + } + + /* Now add size of this field to the size of the record. */ + + { + register tree dsize = DECL_SIZE (field); + + /* This can happen when we have an invalid nested struct definition, + such as struct j { struct j { int i; } }. The error message is + printed in finish_struct. */ + if (dsize == 0) + /* Do nothing. */; + else if (TREE_CODE (dsize) == INTEGER_CST + && TREE_INT_CST_HIGH (dsize) == 0 + && TREE_INT_CST_LOW (dsize) + const_size > const_size) + /* Use const_size if there's no overflow. */ + const_size += TREE_INT_CST_LOW (dsize); + else + { + if (var_size == 0) + var_size = dsize; + else + var_size = size_binop (PLUS_EXPR, var_size, dsize); + } + } + } + + /* Work out the total size and alignment of the record + as one expression and store in the record type. + Round it up to a multiple of the record's alignment. */ + + if (var_size == 0) + { + TYPE_SIZE (rec) = size_int (const_size); + } + else + { + if (const_size) + var_size + = size_binop (PLUS_EXPR, var_size, size_int (const_size)); + TYPE_SIZE (rec) = var_size; + } + + /* Determine the desired alignment. */ +#ifdef ROUND_TYPE_ALIGN + TYPE_ALIGN (rec) = ROUND_TYPE_ALIGN (rec, TYPE_ALIGN (rec), record_align); +#else + TYPE_ALIGN (rec) = MAX (TYPE_ALIGN (rec), record_align); +#endif + +#ifdef ROUND_TYPE_SIZE + TYPE_SIZE (rec) = ROUND_TYPE_SIZE (rec, TYPE_SIZE (rec), TYPE_ALIGN (rec)); +#else + /* Round the size up to be a multiple of the required alignment */ + TYPE_SIZE (rec) = round_up (TYPE_SIZE (rec), TYPE_ALIGN (rec)); +#endif + + return pending_statics; +} + +/* Lay out a UNION_TYPE or QUAL_UNION_TYPE type. + Lay out all the fields, set their positions to zero, + and compute the size and alignment of the union (maximum of any field). + Note that if you set the TYPE_ALIGN before calling this + then the union align is aligned to at least that boundary. */ + +static void +layout_union (rec) + tree rec; +{ + register tree field; +#ifdef STRUCTURE_SIZE_BOUNDARY + unsigned union_align = STRUCTURE_SIZE_BOUNDARY; +#else + unsigned union_align = BITS_PER_UNIT; +#endif + + /* The size of the union, based on the fields scanned so far, + is max (CONST_SIZE, VAR_SIZE). + VAR_SIZE may be null; then CONST_SIZE by itself is the size. */ + register int const_size = 0; + register tree var_size = 0; + + /* If this is a QUAL_UNION_TYPE, we want to process the fields in + the reverse order in building the COND_EXPR that denotes its + size. We reverse them again later. */ + if (TREE_CODE (rec) == QUAL_UNION_TYPE) + TYPE_FIELDS (rec) = nreverse (TYPE_FIELDS (rec)); + + for (field = TYPE_FIELDS (rec); field; field = TREE_CHAIN (field)) + { + /* Enums which are local to this class need not be laid out. */ + if (TREE_CODE (field) == CONST_DECL || TREE_CODE (field) == TYPE_DECL) + continue; + + layout_decl (field, 0); + DECL_FIELD_BITPOS (field) = size_int (0); + + /* Union must be at least as aligned as any field requires. */ + + union_align = MAX (union_align, DECL_ALIGN (field)); + +#ifdef PCC_BITFIELD_TYPE_MATTERS + /* On the m88000, a bit field of declare type `int' + forces the entire union to have `int' alignment. */ + if (PCC_BITFIELD_TYPE_MATTERS && DECL_BIT_FIELD_TYPE (field)) + union_align = MAX (union_align, TYPE_ALIGN (TREE_TYPE (field))); +#endif + + if (TREE_CODE (rec) == UNION_TYPE) + { + /* Set union_size to max (decl_size, union_size). + There are more and less general ways to do this. + Use only CONST_SIZE unless forced to use VAR_SIZE. */ + + if (TREE_CODE (DECL_SIZE (field)) == INTEGER_CST) + const_size + = MAX (const_size, TREE_INT_CST_LOW (DECL_SIZE (field))); + else if (var_size == 0) + var_size = DECL_SIZE (field); + else + var_size = size_binop (MAX_EXPR, var_size, DECL_SIZE (field)); + } + else if (TREE_CODE (rec) == QUAL_UNION_TYPE) + var_size = fold (build (COND_EXPR, sizetype, DECL_QUALIFIER (field), + DECL_SIZE (field), + var_size ? var_size : integer_zero_node)); + } + + if (TREE_CODE (rec) == QUAL_UNION_TYPE) + TYPE_FIELDS (rec) = nreverse (TYPE_FIELDS (rec)); + + /* Determine the ultimate size of the union (in bytes). */ + if (NULL == var_size) + TYPE_SIZE (rec) = size_int (CEIL (const_size, BITS_PER_UNIT) + * BITS_PER_UNIT); + else if (const_size == 0) + TYPE_SIZE (rec) = var_size; + else + TYPE_SIZE (rec) = size_binop (MAX_EXPR, var_size, + round_up (size_int (const_size), + BITS_PER_UNIT)); + + /* Determine the desired alignment. */ +#ifdef ROUND_TYPE_ALIGN + TYPE_ALIGN (rec) = ROUND_TYPE_ALIGN (rec, TYPE_ALIGN (rec), union_align); +#else + TYPE_ALIGN (rec) = MAX (TYPE_ALIGN (rec), union_align); +#endif + +#ifdef ROUND_TYPE_SIZE + TYPE_SIZE (rec) = ROUND_TYPE_SIZE (rec, TYPE_SIZE (rec), TYPE_ALIGN (rec)); +#else + /* Round the size up to be a multiple of the required alignment */ + TYPE_SIZE (rec) = round_up (TYPE_SIZE (rec), TYPE_ALIGN (rec)); +#endif +} + +/* Calculate the mode, size, and alignment for TYPE. + For an array type, calculate the element separation as well. + Record TYPE on the chain of permanent or temporary types + so that dbxout will find out about it. + + TYPE_SIZE of a type is nonzero if the type has been laid out already. + layout_type does nothing on such a type. + + If the type is incomplete, its TYPE_SIZE remains zero. */ + +void +layout_type (type) + tree type; +{ + int old; + tree pending_statics; + + if (type == 0) + abort (); + + /* Do nothing if type has been laid out before. */ + if (TYPE_SIZE (type)) + return; + + /* Make sure all nodes we allocate are not momentary; + they must last past the current statement. */ + old = suspend_momentary (); + + /* If we are processing a permanent type, make nodes permanent. + If processing a temporary type, make it saveable, since the + type node itself is. This is important if the function is inline, + since its decls will get copied later. */ + push_obstacks_nochange (); + if (allocation_temporary_p ()) + { + if (TREE_PERMANENT (type)) + end_temporary_allocation (); + else + saveable_allocation (); + } + + switch (TREE_CODE (type)) + { + case LANG_TYPE: + /* This kind of type is the responsibility + of the languge-specific code. */ + abort (); + + case INTEGER_TYPE: + case ENUMERAL_TYPE: + if (TREE_INT_CST_HIGH (TYPE_MIN_VALUE (type)) >= 0) + TREE_UNSIGNED (type) = 1; + + /* We pass 0 for the last arg of mode_for_size because otherwise + on the Apollo using long long causes a crash. + It seems better to use integer modes than to try to support + integer types with BLKmode. */ + TYPE_MODE (type) = mode_for_size (TYPE_PRECISION (type), MODE_INT, 0); + TYPE_SIZE (type) = size_int (GET_MODE_BITSIZE (TYPE_MODE (type))); + break; + + case REAL_TYPE: + TYPE_MODE (type) = mode_for_size (TYPE_PRECISION (type), MODE_FLOAT, 0); + TYPE_SIZE (type) = size_int (GET_MODE_BITSIZE (TYPE_MODE (type))); + break; + + case COMPLEX_TYPE: + TREE_UNSIGNED (type) = TREE_UNSIGNED (TREE_TYPE (type)); + TYPE_MODE (type) + = mode_for_size (2 * TYPE_PRECISION (TREE_TYPE (type)), + (TREE_CODE (TREE_TYPE (type)) == INTEGER_TYPE + ? MODE_COMPLEX_INT : MODE_COMPLEX_FLOAT), + 0); + TYPE_SIZE (type) = size_int (GET_MODE_BITSIZE (TYPE_MODE (type))); + break; + + case VOID_TYPE: + TYPE_SIZE (type) = size_zero_node; + TYPE_ALIGN (type) = 1; + TYPE_MODE (type) = VOIDmode; + break; + + case OFFSET_TYPE: + TYPE_SIZE (type) = size_int (GET_MODE_BITSIZE (Pmode)); + TYPE_MODE (type) = Pmode; + break; + + case FUNCTION_TYPE: + case METHOD_TYPE: + TYPE_MODE (type) = mode_for_size (2 * GET_MODE_BITSIZE (Pmode), + MODE_INT, 0); + TYPE_SIZE (type) = size_int (GET_MODE_BITSIZE (TYPE_MODE (type))); + break; + + case POINTER_TYPE: + case REFERENCE_TYPE: + TYPE_MODE (type) = Pmode; + TYPE_SIZE (type) = size_int (GET_MODE_BITSIZE (TYPE_MODE (type))); + TREE_UNSIGNED (type) = 1; + TYPE_PRECISION (type) = GET_MODE_BITSIZE (TYPE_MODE (type)); + break; + + case ARRAY_TYPE: + { + register tree index = TYPE_DOMAIN (type); + register tree element = TREE_TYPE (type); + + build_pointer_type (element); + + /* We need to know both bounds in order to compute the size. */ + if (index && TYPE_MAX_VALUE (index) && TYPE_MIN_VALUE (index) + && TYPE_SIZE (element)) + { + tree length + = size_binop (PLUS_EXPR, size_one_node, + size_binop (MINUS_EXPR, TYPE_MAX_VALUE (index), + TYPE_MIN_VALUE (index))); + + TYPE_SIZE (type) = size_binop (MULT_EXPR, length, + TYPE_SIZE (element)); + } + + /* Now round the alignment and size, + using machine-dependent criteria if any. */ + +#ifdef ROUND_TYPE_ALIGN + TYPE_ALIGN (type) + = ROUND_TYPE_ALIGN (type, TYPE_ALIGN (element), BITS_PER_UNIT); +#else + TYPE_ALIGN (type) = MAX (TYPE_ALIGN (element), BITS_PER_UNIT); +#endif + +#ifdef ROUND_TYPE_SIZE + if (TYPE_SIZE (type) != 0) + TYPE_SIZE (type) + = ROUND_TYPE_SIZE (type, TYPE_SIZE (type), TYPE_ALIGN (type)); +#endif + + TYPE_MODE (type) = BLKmode; + if (TYPE_SIZE (type) != 0 + && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST + /* BLKmode elements force BLKmode aggregate; + else extract/store fields may lose. */ + && (TYPE_MODE (TREE_TYPE (type)) != BLKmode + || TYPE_NO_FORCE_BLK (TREE_TYPE (type)))) + { + TYPE_MODE (type) + = mode_for_size (TREE_INT_CST_LOW (TYPE_SIZE (type)), + MODE_INT, 1); + + if (STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT + && TYPE_ALIGN (type) < TREE_INT_CST_LOW (TYPE_SIZE (type)) + && TYPE_MODE (type) != BLKmode) + { + TYPE_NO_FORCE_BLK (type) = 1; + TYPE_MODE (type) = BLKmode; + } + } + break; + } + + case RECORD_TYPE: + pending_statics = layout_record (type); + TYPE_MODE (type) = BLKmode; + if (TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) + { + tree field; + /* A record which has any BLKmode members must itself be BLKmode; + it can't go in a register. + Unless the member is BLKmode only because it isn't aligned. */ + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) + { + int bitpos; + + if (TREE_CODE (field) != FIELD_DECL) + continue; + + if (TYPE_MODE (TREE_TYPE (field)) == BLKmode + && ! TYPE_NO_FORCE_BLK (TREE_TYPE (field))) + goto record_lose; + + if (TREE_CODE (DECL_FIELD_BITPOS (field)) != INTEGER_CST) + goto record_lose; + + bitpos = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); + + /* Must be BLKmode if any field crosses a word boundary, + since extract_bit_field can't handle that in registers. */ + if (bitpos / BITS_PER_WORD + != ((TREE_INT_CST_LOW (DECL_SIZE (field)) + bitpos - 1) + / BITS_PER_WORD) + /* But there is no problem if the field is entire words. */ + && TREE_INT_CST_LOW (DECL_SIZE (field)) % BITS_PER_WORD == 0) + goto record_lose; + } + + TYPE_MODE (type) + = mode_for_size (TREE_INT_CST_LOW (TYPE_SIZE (type)), + MODE_INT, 1); + + /* If structure's known alignment is less than + what the scalar mode would need, and it matters, + then stick with BLKmode. */ + if (STRICT_ALIGNMENT + && ! (TYPE_ALIGN (type) >= BIGGEST_ALIGNMENT + || (TYPE_ALIGN (type) + >= TREE_INT_CST_LOW (TYPE_SIZE (type))))) + { + if (TYPE_MODE (type) != BLKmode) + /* If this is the only reason this type is BLKmode, + then don't force containing types to be BLKmode. */ + TYPE_NO_FORCE_BLK (type) = 1; + TYPE_MODE (type) = BLKmode; + } + + record_lose: ; + } + + /* Lay out any static members. This is done now + because their type may use the record's type. */ + while (pending_statics) + { + layout_decl (TREE_VALUE (pending_statics), 0); + pending_statics = TREE_CHAIN (pending_statics); + } + break; + + case UNION_TYPE: + case QUAL_UNION_TYPE: + layout_union (type); + TYPE_MODE (type) = BLKmode; + if (TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST + /* If structure's known alignment is less than + what the scalar mode would need, and it matters, + then stick with BLKmode. */ + && (! STRICT_ALIGNMENT + || TYPE_ALIGN (type) >= BIGGEST_ALIGNMENT + || TYPE_ALIGN (type) >= TREE_INT_CST_LOW (TYPE_SIZE (type)))) + { + tree field; + /* A union which has any BLKmode members must itself be BLKmode; + it can't go in a register. + Unless the member is BLKmode only because it isn't aligned. */ + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) + { + if (TREE_CODE (field) != FIELD_DECL) + continue; + + if (TYPE_MODE (TREE_TYPE (field)) == BLKmode + && ! TYPE_NO_FORCE_BLK (TREE_TYPE (field))) + goto union_lose; + } + + TYPE_MODE (type) + = mode_for_size (TREE_INT_CST_LOW (TYPE_SIZE (type)), + MODE_INT, 1); + + union_lose: ; + } + break; + + /* Pascal types */ + case BOOLEAN_TYPE: /* store one byte/boolean for now. */ + TYPE_MODE (type) = QImode; + TYPE_SIZE (type) = size_int (GET_MODE_BITSIZE (TYPE_MODE (type))); + TYPE_PRECISION (type) = 1; + TYPE_ALIGN (type) = GET_MODE_ALIGNMENT (TYPE_MODE (type)); + break; + + case CHAR_TYPE: + TYPE_MODE (type) = QImode; + TYPE_SIZE (type) = size_int (GET_MODE_BITSIZE (TYPE_MODE (type))); + TYPE_PRECISION (type) = GET_MODE_BITSIZE (TYPE_MODE (type)); + TYPE_ALIGN (type) = GET_MODE_ALIGNMENT (TYPE_MODE (type)); + break; + + case FILE_TYPE: + /* The size may vary in different languages, so the language front end + should fill in the size. */ + TYPE_ALIGN (type) = BIGGEST_ALIGNMENT; + TYPE_MODE (type) = BLKmode; + break; + + default: + abort (); + } /* end switch */ + + /* Normally, use the alignment corresponding to the mode chosen. + However, where strict alignment is not required, avoid + over-aligning structures, since most compilers do not do this + alignment. */ + + if (TYPE_MODE (type) != BLKmode && TYPE_MODE (type) != VOIDmode + && (STRICT_ALIGNMENT + || (TREE_CODE (type) != RECORD_TYPE && TREE_CODE (type) != UNION_TYPE + && TREE_CODE (type) != QUAL_UNION_TYPE + && TREE_CODE (type) != ARRAY_TYPE))) + TYPE_ALIGN (type) = GET_MODE_ALIGNMENT (TYPE_MODE (type)); + + /* Evaluate nonconstant size only once, either now or as soon as safe. */ + if (TYPE_SIZE (type) != 0 && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) + TYPE_SIZE (type) = variable_size (TYPE_SIZE (type)); + + /* Also layout any other variants of the type. */ + if (TYPE_NEXT_VARIANT (type) + || type != TYPE_MAIN_VARIANT (type)) + { + tree variant; + /* Record layout info of this variant. */ + tree size = TYPE_SIZE (type); + int align = TYPE_ALIGN (type); + enum machine_mode mode = TYPE_MODE (type); + + /* Copy it into all variants. */ + for (variant = TYPE_MAIN_VARIANT (type); + variant; + variant = TYPE_NEXT_VARIANT (variant)) + { + TYPE_SIZE (variant) = size; + TYPE_ALIGN (variant) = align; + TYPE_MODE (variant) = mode; + } + } + + pop_obstacks (); + resume_momentary (old); +} + +/* Create and return a type for signed integers of PRECISION bits. */ + +tree +make_signed_type (precision) + int precision; +{ + register tree type = make_node (INTEGER_TYPE); + + TYPE_PRECISION (type) = precision; + + /* Create the extreme values based on the number of bits. */ + + TYPE_MIN_VALUE (type) + = build_int_2 ((precision - HOST_BITS_PER_WIDE_INT > 0 + ? 0 : (HOST_WIDE_INT) (-1) << (precision - 1)), + (((HOST_WIDE_INT) (-1) + << (precision - HOST_BITS_PER_WIDE_INT - 1 > 0 + ? precision - HOST_BITS_PER_WIDE_INT - 1 + : 0)))); + TYPE_MAX_VALUE (type) + = build_int_2 ((precision - HOST_BITS_PER_WIDE_INT > 0 + ? -1 : ((HOST_WIDE_INT) 1 << (precision - 1)) - 1), + (precision - HOST_BITS_PER_WIDE_INT - 1 > 0 + ? (((HOST_WIDE_INT) 1 + << (precision - HOST_BITS_PER_WIDE_INT - 1))) - 1 + : 0)); + + /* Give this type's extreme values this type as their type. */ + + TREE_TYPE (TYPE_MIN_VALUE (type)) = type; + TREE_TYPE (TYPE_MAX_VALUE (type)) = type; + + /* The first type made with this or `make_unsigned_type' + is the type for size values. */ + + if (sizetype == 0) + { + sizetype = type; + } + + /* Lay out the type: set its alignment, size, etc. */ + + layout_type (type); + + return type; +} + +/* Create and return a type for unsigned integers of PRECISION bits. */ + +tree +make_unsigned_type (precision) + int precision; +{ + register tree type = make_node (INTEGER_TYPE); + + TYPE_PRECISION (type) = precision; + + /* The first type made with this or `make_signed_type' + is the type for size values. */ + + if (sizetype == 0) + { + sizetype = type; + } + + fixup_unsigned_type (type); + return type; +} + +/* Set the extreme values of TYPE based on its precision in bits, + then lay it out. Used when make_signed_type won't do + because the tree code is not INTEGER_TYPE. + E.g. for Pascal, when the -fsigned-char option is given. */ + +void +fixup_signed_type (type) + tree type; +{ + register int precision = TYPE_PRECISION (type); + + TYPE_MIN_VALUE (type) + = build_int_2 ((precision - HOST_BITS_PER_WIDE_INT > 0 + ? 0 : (HOST_WIDE_INT) (-1) << (precision - 1)), + (((HOST_WIDE_INT) (-1) + << (precision - HOST_BITS_PER_WIDE_INT - 1 > 0 + ? precision - HOST_BITS_PER_WIDE_INT - 1 + : 0)))); + TYPE_MAX_VALUE (type) + = build_int_2 ((precision - HOST_BITS_PER_WIDE_INT > 0 + ? -1 : ((HOST_WIDE_INT) 1 << (precision - 1)) - 1), + (precision - HOST_BITS_PER_WIDE_INT - 1 > 0 + ? (((HOST_WIDE_INT) 1 + << (precision - HOST_BITS_PER_WIDE_INT - 1))) - 1 + : 0)); + + TREE_TYPE (TYPE_MIN_VALUE (type)) = type; + TREE_TYPE (TYPE_MAX_VALUE (type)) = type; + + /* Lay out the type: set its alignment, size, etc. */ + + layout_type (type); +} + +/* Set the extreme values of TYPE based on its precision in bits, + then lay it out. This is used both in `make_unsigned_type' + and for enumeral types. */ + +void +fixup_unsigned_type (type) + tree type; +{ + register int precision = TYPE_PRECISION (type); + + TYPE_MIN_VALUE (type) = build_int_2 (0, 0); + TYPE_MAX_VALUE (type) + = build_int_2 (precision - HOST_BITS_PER_WIDE_INT >= 0 + ? -1 : ((HOST_WIDE_INT) 1 << precision) - 1, + precision - HOST_BITS_PER_WIDE_INT > 0 + ? ((unsigned HOST_WIDE_INT) ~0 + >> (HOST_BITS_PER_WIDE_INT + - (precision - HOST_BITS_PER_WIDE_INT))) + : 0); + TREE_TYPE (TYPE_MIN_VALUE (type)) = type; + TREE_TYPE (TYPE_MAX_VALUE (type)) = type; + + /* Lay out the type: set its alignment, size, etc. */ + + layout_type (type); +} + +/* Find the best machine mode to use when referencing a bit field of length + BITSIZE bits starting at BITPOS. + + The underlying object is known to be aligned to a boundary of ALIGN bits. + If LARGEST_MODE is not VOIDmode, it means that we should not use a mode + larger than LARGEST_MODE (usually SImode). + + If no mode meets all these conditions, we return VOIDmode. Otherwise, if + VOLATILEP is true or SLOW_BYTE_ACCESS is false, we return the smallest + mode meeting these conditions. + + Otherwise (VOLATILEP is false and SLOW_BYTE_ACCESS is true), we return + the largest mode (but a mode no wider than UNITS_PER_WORD) that meets + all the conditions. */ + +enum machine_mode +get_best_mode (bitsize, bitpos, align, largest_mode, volatilep) + int bitsize, bitpos; + int align; + enum machine_mode largest_mode; + int volatilep; +{ + enum machine_mode mode; + int unit; + + /* Find the narrowest integer mode that contains the bit field. */ + for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; + mode = GET_MODE_WIDER_MODE (mode)) + { + unit = GET_MODE_BITSIZE (mode); + if (bitpos / unit == (bitpos + bitsize - 1) / unit) + break; + } + + if (mode == MAX_MACHINE_MODE + /* It is tempting to omit the following line + if STRICT_ALIGNMENT is true. + But that is incorrect, since if the bitfield uses part of 3 bytes + and we use a 4-byte mode, we could get a spurious segv + if the extra 4th byte is past the end of memory. + (Though at least one Unix compiler ignores this problem: + that on the Sequent 386 machine. */ + || MIN (unit, BIGGEST_ALIGNMENT) > align + || (largest_mode != VOIDmode && unit > GET_MODE_BITSIZE (largest_mode))) + return VOIDmode; + + if (SLOW_BYTE_ACCESS && ! volatilep) + { + enum machine_mode wide_mode = VOIDmode, tmode; + + for (tmode = GET_CLASS_NARROWEST_MODE (MODE_INT); tmode != VOIDmode; + tmode = GET_MODE_WIDER_MODE (tmode)) + { + unit = GET_MODE_BITSIZE (tmode); + if (bitpos / unit == (bitpos + bitsize - 1) / unit + && unit <= BITS_PER_WORD + && unit <= MIN (align, BIGGEST_ALIGNMENT) + && (largest_mode == VOIDmode + || unit <= GET_MODE_BITSIZE (largest_mode))) + wide_mode = tmode; + } + + if (wide_mode != VOIDmode) + return wide_mode; + } + + return mode; +} + +/* Save all variables describing the current status into the structure *P. + This is used before starting a nested function. */ + +void +save_storage_status (p) + struct function *p; +{ +#if 0 /* Need not save, since always 0 and non0 (resp.) within a function. */ + p->pending_sizes = pending_sizes; + p->immediate_size_expand = immediate_size_expand; +#endif /* 0 */ +} + +/* Restore all variables describing the current status from the structure *P. + This is used after a nested function. */ + +void +restore_storage_status (p) + struct function *p; +{ +#if 0 + pending_sizes = p->pending_sizes; + immediate_size_expand = p->immediate_size_expand; +#endif /* 0 */ +} diff --git a/gnu/usr.bin/cc/lib/stupid.c b/gnu/usr.bin/cc/lib/stupid.c new file mode 100644 index 000000000000..47d7740fb64f --- /dev/null +++ b/gnu/usr.bin/cc/lib/stupid.c @@ -0,0 +1,544 @@ +/* Dummy data flow analysis for GNU compiler in nonoptimizing mode. + Copyright (C) 1987, 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This file performs stupid register allocation, which is used + when cc1 gets the -noreg switch (which is when cc does not get -O). + + Stupid register allocation goes in place of the the flow_analysis, + local_alloc and global_alloc passes. combine_instructions cannot + be done with stupid allocation because the data flow info that it needs + is not computed here. + + In stupid allocation, the only user-defined variables that can + go in registers are those declared "register". They are assumed + to have a life span equal to their scope. Other user variables + are given stack slots in the rtl-generation pass and are not + represented as pseudo regs. A compiler-generated temporary + is assumed to live from its first mention to its last mention. + + Since each pseudo-reg's life span is just an interval, it can be + represented as a pair of numbers, each of which identifies an insn by + its position in the function (number of insns before it). The first + thing done for stupid allocation is to compute such a number for each + insn. It is called the suid. Then the life-interval of each + pseudo reg is computed. Then the pseudo regs are ordered by priority + and assigned hard regs in priority order. */ + +#include +#include "config.h" +#include "rtl.h" +#include "hard-reg-set.h" +#include "regs.h" +#include "flags.h" + +/* Vector mapping INSN_UIDs to suids. + The suids are like uids but increase monotonically always. + We use them to see whether a subroutine call came + between a variable's birth and its death. */ + +static int *uid_suid; + +/* Get the suid of an insn. */ + +#define INSN_SUID(INSN) (uid_suid[INSN_UID (INSN)]) + +/* Record the suid of the last CALL_INSN + so we can tell whether a pseudo reg crosses any calls. */ + +static int last_call_suid; + +/* Record the suid of the last JUMP_INSN + so we can tell whether a pseudo reg crosses any jumps. */ + +static int last_jump_suid; + +/* Record the suid of the last CODE_LABEL + so we can tell whether a pseudo reg crosses any labels. */ + +static int last_label_suid; + +/* Element N is suid of insn where life span of pseudo reg N ends. + Element is 0 if register N has not been seen yet on backward scan. */ + +static int *reg_where_dead; + +/* Element N is suid of insn where life span of pseudo reg N begins. */ + +static int *reg_where_born; + +/* Element N is 1 if pseudo reg N lives across labels or jumps. */ + +static char *reg_crosses_blocks; + +/* Numbers of pseudo-regs to be allocated, highest priority first. */ + +static int *reg_order; + +/* Indexed by reg number (hard or pseudo), nonzero if register is live + at the current point in the instruction stream. */ + +static char *regs_live; + +/* Indexed by insn's suid, the set of hard regs live after that insn. */ + +static HARD_REG_SET *after_insn_hard_regs; + +/* Record that hard reg REGNO is live after insn INSN. */ + +#define MARK_LIVE_AFTER(INSN,REGNO) \ + SET_HARD_REG_BIT (after_insn_hard_regs[INSN_SUID (INSN)], (REGNO)) + +static void stupid_mark_refs (); +static int stupid_reg_compare (); +static int stupid_find_reg (); + +/* Stupid life analysis is for the case where only variables declared + `register' go in registers. For this case, we mark all + pseudo-registers that belong to register variables as + dying in the last instruction of the function, and all other + pseudo registers as dying in the last place they are referenced. + Hard registers are marked as dying in the last reference before + the end or before each store into them. */ + +void +stupid_life_analysis (f, nregs, file) + rtx f; + int nregs; + FILE *file; +{ + register int i; + register rtx last, insn; + int max_uid; + + bzero (regs_ever_live, sizeof regs_ever_live); + + regs_live = (char *) alloca (nregs); + + /* First find the last real insn, and count the number of insns, + and assign insns their suids. */ + + for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) + if (INSN_UID (insn) > i) + i = INSN_UID (insn); + + max_uid = i + 1; + uid_suid = (int *) alloca ((i + 1) * sizeof (int)); + + /* Compute the mapping from uids to suids. + Suids are numbers assigned to insns, like uids, + except that suids increase monotonically through the code. */ + + last = 0; /* In case of empty function body */ + for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN + || GET_CODE (insn) == JUMP_INSN) + last = insn; + INSN_SUID (insn) = ++i; + } + + last_call_suid = i + 1; + last_jump_suid = i + 1; + last_label_suid = i + 1; + + max_regno = nregs; + + /* Allocate tables to record info about regs. */ + + reg_where_dead = (int *) alloca (nregs * sizeof (int)); + bzero (reg_where_dead, nregs * sizeof (int)); + + reg_where_born = (int *) alloca (nregs * sizeof (int)); + bzero (reg_where_born, nregs * sizeof (int)); + + reg_crosses_blocks = (char *) alloca (nregs); + bzero (reg_crosses_blocks, nregs); + + reg_order = (int *) alloca (nregs * sizeof (int)); + bzero (reg_order, nregs * sizeof (int)); + + reg_renumber = (short *) oballoc (nregs * sizeof (short)); + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + reg_renumber[i] = i; + + for (i = FIRST_VIRTUAL_REGISTER; i <= LAST_VIRTUAL_REGISTER; i++) + reg_renumber[i] = -1; + + after_insn_hard_regs = (HARD_REG_SET *) alloca (max_uid * sizeof (HARD_REG_SET)); + bzero (after_insn_hard_regs, max_uid * sizeof (HARD_REG_SET)); + + /* Allocate and zero out many data structures + that will record the data from lifetime analysis. */ + + allocate_for_life_analysis (); + + for (i = 0; i < max_regno; i++) + { + reg_n_deaths[i] = 1; + } + + bzero (regs_live, nregs); + + /* Find where each pseudo register is born and dies, + by scanning all insns from the end to the start + and noting all mentions of the registers. + + Also find where each hard register is live + and record that info in after_insn_hard_regs. + regs_live[I] is 1 if hard reg I is live + at the current point in the scan. */ + + for (insn = last; insn; insn = PREV_INSN (insn)) + { + register HARD_REG_SET *p = after_insn_hard_regs + INSN_SUID (insn); + + /* Copy the info in regs_live + into the element of after_insn_hard_regs + for the current position in the rtl code. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (regs_live[i]) + SET_HARD_REG_BIT (*p, i); + + /* Mark all call-clobbered regs as live after each call insn + so that a pseudo whose life span includes this insn + will not go in one of them. + Then mark those regs as all dead for the continuing scan + of the insns before the call. */ + + if (GET_CODE (insn) == CALL_INSN) + { + last_call_suid = INSN_SUID (insn); + IOR_HARD_REG_SET (after_insn_hard_regs[last_call_suid], + call_used_reg_set); + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (call_used_regs[i]) + regs_live[i] = 0; + } + + if (GET_CODE (insn) == JUMP_INSN) + last_jump_suid = INSN_SUID (insn); + + if (GET_CODE (insn) == CODE_LABEL) + last_label_suid = INSN_SUID (insn); + + /* Update which hard regs are currently live + and also the birth and death suids of pseudo regs + based on the pattern of this insn. */ + + if (GET_CODE (insn) == INSN + || GET_CODE (insn) == CALL_INSN + || GET_CODE (insn) == JUMP_INSN) + { + stupid_mark_refs (PATTERN (insn), insn); + } + } + + /* Now decide the order in which to allocate the pseudo registers. */ + + for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) + reg_order[i] = i; + + qsort (®_order[LAST_VIRTUAL_REGISTER + 1], + max_regno - LAST_VIRTUAL_REGISTER - 1, sizeof (int), + stupid_reg_compare); + + /* Now, in that order, try to find hard registers for those pseudo regs. */ + + for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) + { + register int r = reg_order[i]; + enum reg_class class; + + /* Some regnos disappear from the rtl. Ignore them to avoid crash. */ + if (regno_reg_rtx[r] == 0) + continue; + + /* Now find the best hard-register class for this pseudo register */ + if (N_REG_CLASSES > 1) + { + class = reg_preferred_class (r); + + reg_renumber[r] = stupid_find_reg (reg_n_calls_crossed[r], class, + PSEUDO_REGNO_MODE (r), + reg_where_born[r], + reg_where_dead[r], + reg_crosses_blocks[r]); + } + else + reg_renumber[r] = -1; + + /* If no reg available in that class, + try any reg. */ + if (reg_renumber[r] == -1) + reg_renumber[r] = stupid_find_reg (reg_n_calls_crossed[r], + GENERAL_REGS, + PSEUDO_REGNO_MODE (r), + reg_where_born[r], + reg_where_dead[r], + reg_crosses_blocks[r]); + } + + if (file) + dump_flow_info (file); +} + +/* Comparison function for qsort. + Returns -1 (1) if register *R1P is higher priority than *R2P. */ + +static int +stupid_reg_compare (r1p, r2p) + int *r1p, *r2p; +{ + register int r1 = *r1p, r2 = *r2p; + register int len1 = reg_where_dead[r1] - reg_where_born[r1]; + register int len2 = reg_where_dead[r2] - reg_where_born[r2]; + int tem; + + tem = len2 - len1; + if (tem != 0) return tem; + + tem = reg_n_refs[r1] - reg_n_refs[r2]; + if (tem != 0) return tem; + + /* If regs are equally good, sort by regno, + so that the results of qsort leave nothing to chance. */ + return r1 - r2; +} + +/* Find a block of SIZE words of hard registers in reg_class CLASS + that can hold a value of machine-mode MODE + (but actually we test only the first of the block for holding MODE) + currently free from after insn whose suid is BIRTH + through the insn whose suid is DEATH, + and return the number of the first of them. + Return -1 if such a block cannot be found. + + If CALL_PRESERVED is nonzero, insist on registers preserved + over subroutine calls, and return -1 if cannot find such. + If CROSSES_BLOCKS is nonzero, reject registers for which + PRESERVE_DEATH_INFO_REGNO_P is true. */ + +static int +stupid_find_reg (call_preserved, class, mode, + born_insn, dead_insn, crosses_blocks) + int call_preserved; + enum reg_class class; + enum machine_mode mode; + int born_insn, dead_insn; + int crosses_blocks; +{ + register int i, ins; +#ifdef HARD_REG_SET + register /* Declare them register if they are scalars. */ +#endif + HARD_REG_SET used, this_reg; +#ifdef ELIMINABLE_REGS + static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; +#endif + + COPY_HARD_REG_SET (used, + call_preserved ? call_used_reg_set : fixed_reg_set); + +#ifdef ELIMINABLE_REGS + for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++) + SET_HARD_REG_BIT (used, eliminables[i].from); +#else + SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); +#endif + + for (ins = born_insn; ins < dead_insn; ins++) + IOR_HARD_REG_SET (used, after_insn_hard_regs[ins]); + + IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { +#ifdef REG_ALLOC_ORDER + int regno = reg_alloc_order[i]; +#else + int regno = i; +#endif + + /* If we need reasonable death info on this hard reg, + don't use it for anything whose life spans a label or a jump. */ +#ifdef PRESERVE_DEATH_INFO_REGNO_P + if (PRESERVE_DEATH_INFO_REGNO_P (regno) + && crosses_blocks) + continue; +#endif + /* If a register has screwy overlap problems, + don't use it at all if not optimizing. + Actually this is only for the 387 stack register, + and it's because subsequent code won't work. */ +#ifdef OVERLAPPING_REGNO_P + if (OVERLAPPING_REGNO_P (regno)) + continue; +#endif + + if (! TEST_HARD_REG_BIT (used, regno) + && HARD_REGNO_MODE_OK (regno, mode)) + { + register int j; + register int size1 = HARD_REGNO_NREGS (regno, mode); + for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); + if (j == size1) + { + CLEAR_HARD_REG_SET (this_reg); + while (--j >= 0) + SET_HARD_REG_BIT (this_reg, regno + j); + for (ins = born_insn; ins < dead_insn; ins++) + { + IOR_HARD_REG_SET (after_insn_hard_regs[ins], this_reg); + } + return regno; + } +#ifndef REG_ALLOC_ORDER + i += j; /* Skip starting points we know will lose */ +#endif + } + } + return -1; +} + +/* Walk X, noting all assignments and references to registers + and recording what they imply about life spans. + INSN is the current insn, supplied so we can find its suid. */ + +static void +stupid_mark_refs (x, insn) + rtx x, insn; +{ + register RTX_CODE code = GET_CODE (x); + register char *fmt; + register int regno, i; + + if (code == SET || code == CLOBBER) + { + if (SET_DEST (x) != 0 && GET_CODE (SET_DEST (x)) == REG) + { + /* Register is being assigned. */ + regno = REGNO (SET_DEST (x)); + + /* For hard regs, update the where-live info. */ + if (regno < FIRST_PSEUDO_REGISTER) + { + register int j + = HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (x))); + while (--j >= 0) + { + regs_ever_live[regno+j] = 1; + regs_live[regno+j] = 0; + /* The following line is for unused outputs; + they do get stored even though never used again. */ + MARK_LIVE_AFTER (insn, regno); + /* When a hard reg is clobbered, mark it in use + just before this insn, so it is live all through. */ + if (code == CLOBBER && INSN_SUID (insn) > 0) + SET_HARD_REG_BIT (after_insn_hard_regs[INSN_SUID (insn) - 1], + regno); + } + } + /* For pseudo regs, record where born, where dead, number of + times used, and whether live across a call. */ + else + { + /* Update the life-interval bounds of this pseudo reg. */ + + /* When a pseudo-reg is CLOBBERed, it is born just before + the clobbering insn. When setting, just after. */ + int where_born = INSN_SUID (insn) - (code == CLOBBER); + + reg_where_born[regno] = where_born; + /* The reg must live at least one insn even + in it is never again used--because it has to go + in SOME hard reg. Mark it as dying after the current + insn so that it will conflict with any other outputs of + this insn. */ + if (reg_where_dead[regno] < where_born + 2) + reg_where_dead[regno] = where_born + 2; + + /* Count the refs of this reg. */ + reg_n_refs[regno]++; + + if (last_call_suid < reg_where_dead[regno]) + reg_n_calls_crossed[regno] += 1; + if (last_jump_suid < reg_where_dead[regno] + || last_label_suid < reg_where_dead[regno]) + reg_crosses_blocks[regno] = 1; + } + } + /* Record references from the value being set, + or from addresses in the place being set if that's not a reg. + If setting a SUBREG, we treat the entire reg as *used*. */ + if (code == SET) + { + stupid_mark_refs (SET_SRC (x), insn); + if (GET_CODE (SET_DEST (x)) != REG) + stupid_mark_refs (SET_DEST (x), insn); + } + return; + } + + /* Register value being used, not set. */ + + if (code == REG) + { + regno = REGNO (x); + if (regno < FIRST_PSEUDO_REGISTER) + { + /* Hard reg: mark it live for continuing scan of previous insns. */ + register int j = HARD_REGNO_NREGS (regno, GET_MODE (x)); + while (--j >= 0) + { + regs_ever_live[regno+j] = 1; + regs_live[regno+j] = 1; + } + } + else + { + /* Pseudo reg: record first use, last use and number of uses. */ + + reg_where_born[regno] = INSN_SUID (insn); + reg_n_refs[regno]++; + if (regs_live[regno] == 0) + { + regs_live[regno] = 1; + reg_where_dead[regno] = INSN_SUID (insn); + } + } + return; + } + + /* Recursive scan of all other rtx's. */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + stupid_mark_refs (XEXP (x, i), insn); + if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + stupid_mark_refs (XVECEXP (x, i, j), insn); + } + } +} diff --git a/gnu/usr.bin/cc/lib/tconfig.h b/gnu/usr.bin/cc/lib/tconfig.h new file mode 100644 index 000000000000..eb90681006fd --- /dev/null +++ b/gnu/usr.bin/cc/lib/tconfig.h @@ -0,0 +1,48 @@ +/* Configuration for GNU C-compiler for Intel 80386. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef i386 +#define i386 +#endif + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +/* If compiled with GNU C, use the built-in alloca */ +#ifdef __GNUC__ +#undef alloca +#define alloca __builtin_alloca +#endif + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ + +#include "tm.h" diff --git a/gnu/usr.bin/cc/lib/tm.h b/gnu/usr.bin/cc/lib/tm.h new file mode 100644 index 000000000000..22fb4b0a8e3f --- /dev/null +++ b/gnu/usr.bin/cc/lib/tm.h @@ -0,0 +1,172 @@ +/* Configuration for an i386 running 386BSD as the target machine. */ + +/* This is tested by i386gas.h. */ +#define YES_UNDERSCORES + +#include "i386/gstabs.h" + +/* Get perform_* macros to build libgcc.a. */ +#include "i386/perform.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -D__FreeBSD__ -D____386BSD____ -D__386BSD__ -DBSD_NET2" + +/* Like the default, except no -lg and no shared profiling libraries. */ +#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p -Bstatic}%{pg:-lc_p -Bstatic}" + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "short unsigned int" + +#define WCHAR_UNSIGNED 1 + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 16 + +/* 386BSD does have atexit. */ + +#define HAVE_ATEXIT + +/* Redefine this to use %eax instead of %edx. */ +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%eax\n", \ + LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%eax\n", LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall mcount\n"); \ + } \ +} + +/* There are conflicting reports about whether this system uses + a different assembler syntax. wilson@cygnus.com says # is right. */ +#undef COMMENT_BEGIN +#define COMMENT_BEGIN "#" + +#undef ASM_APP_ON +#define ASM_APP_ON "#APP\n" + +#undef ASM_APP_OFF +#define ASM_APP_OFF "#NO_APP\n" + +/* The following macros are stolen from i386v4.h */ +/* These have to be defined to get PIC code correct */ + +/* This is how to output an element of a case-vector that is relative. + This is only used for PIC code. See comments by the `casesi' insn in + i386.md for an explanation of the expression this outputs. */ + +#undef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) + +/* Indicate that jump tables go in the text section. This is + necessary when compiling PIC code. */ + +#define JUMP_TABLES_IN_TEXT_SECTION + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 + +/* + * Some imports from svr4.h in support of shared libraries. + * Currently, we need the DECLARE_OBJECT_SIZE stuff. + */ + +/* Define the strings used for the special svr4 .type and .size directives. + These strings generally do not vary from one system running svr4 to + another, but if a given system (e.g. m88k running svr) needs to use + different pseudo-op names for these, they may be overridden in the + file which includes this one. */ + +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" +#define WEAK_ASM_OP ".weak" + +/* The following macro defines the format used to output the second + operand of the .type assembler directive. Different svr4 assemblers + expect various different forms for this operand. The one given here + is just a default. You may need to override it in your machine- + specific tm.h file (depending upon the particulars of your assembler). */ + +#define TYPE_OPERAND_FMT "@%s" + +/* Write the extra assembler code needed to declare a function's result. + Most svr4 assemblers don't require any special declaration of the + result value, but there are exceptions. */ + +#ifndef ASM_DECLARE_RESULT +#define ASM_DECLARE_RESULT(FILE, RESULT) +#endif + +/* These macros generate the special .type and .size directives which + are used to set the corresponding fields of the linker symbol table + entries in an ELF object file under SVR4. These macros also output + the starting labels for the relevant functions/objects. */ + +/* Write the extra assembler code needed to declare a function properly. + Some svr4 assemblers need to also have something extra said about the + function's return value. We allow for that here. */ + +#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ + putc ('\n', FILE); \ + ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ + ASM_OUTPUT_LABEL(FILE, NAME); \ + } while (0) + +/* Write the extra assembler code needed to declare an object properly. */ + +#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ + putc ('\n', FILE); \ + if (!flag_inhibit_size_directive) \ + { \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (decl))); \ + } \ + ASM_OUTPUT_LABEL(FILE, NAME); \ + } while (0) + +/* This is how to declare the size of a function. */ + +#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ + do { \ + if (!flag_inhibit_size_directive) \ + { \ + char label[256]; \ + static int labelno; \ + labelno++; \ + ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \ + ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno); \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, (FNAME)); \ + fprintf (FILE, ","); \ + assemble_name (FILE, label); \ + fprintf (FILE, "-"); \ + assemble_name (FILE, (FNAME)); \ + putc ('\n', FILE); \ + } \ + } while (0) + diff --git a/gnu/usr.bin/cc/lib/toplev.c b/gnu/usr.bin/cc/lib/toplev.c new file mode 100644 index 000000000000..1e33806ee635 --- /dev/null +++ b/gnu/usr.bin/cc/lib/toplev.c @@ -0,0 +1,3509 @@ +/* Top level of GNU C compiler + Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This is the top level of cc1/c++. + It parses command args, opens files, invokes the various passes + in the proper order, and counts the time used by each. + Error messages and low-level interface to malloc also handled here. */ + +#include "config.h" +#include +#include +#include +#include + +#include + +#ifdef USG +#undef FLOAT +#include +/* This is for hpux. It is a real screw. They should change hpux. */ +#undef FLOAT +#include +#include /* Correct for hpux at least. Is it good on other USG? */ +#undef FFS /* Some systems define this in param.h. */ +#else +#ifndef VMS +#include +#include +#endif +#endif + +#include "input.h" +#include "tree.h" +/* #include "c-tree.h" */ +#include "rtl.h" +#include "flags.h" +#include "insn-attr.h" +#include "defaults.h" + +#ifdef XCOFF_DEBUGGING_INFO +#include "xcoffout.h" +#endif + +#ifdef VMS +/* The extra parameters substantially improve the I/O performance. */ +static FILE * +VMS_fopen (fname, type) + char * fname; + char * type; +{ + if (strcmp (type, "w") == 0) + return fopen (fname, type, "mbc=16", "deq=64", "fop=tef", "shr=nil"); + return fopen (fname, type, "mbc=16"); +} +#define fopen VMS_fopen +#endif + +#ifndef DEFAULT_GDB_EXTENSIONS +#define DEFAULT_GDB_EXTENSIONS 1 +#endif + +extern int rtx_equal_function_value_matters; + +#if ! (defined (VMS) || defined (OS2)) +extern char **environ; +#endif +extern char *version_string, *language_string; + +extern void init_lex (); +extern void init_decl_processing (); +extern void init_obstacks (); +extern void init_tree_codes (); +extern void init_rtl (); +extern void init_optabs (); +extern void init_stmt (); +extern void init_reg_sets (); +extern void dump_flow_info (); +extern void dump_sched_info (); +extern void dump_local_alloc (); + +void rest_of_decl_compilation (); +void error (); +void error_with_file_and_line (); +void fancy_abort (); +#ifndef abort +void abort (); +#endif +void set_target_switch (); +static void print_switch_values (); +static char *decl_name (); + +/* Name of program invoked, sans directories. */ + +char *progname; + +/* Copy of arguments to main. */ +int save_argc; +char **save_argv; + +/* Name of current original source file (what was input to cpp). + This comes from each #-command in the actual input. */ + +char *input_filename; + +/* Name of top-level original source file (what was input to cpp). + This comes from the #-command at the beginning of the actual input. + If there isn't any there, then this is the cc1 input file name. */ + +char *main_input_filename; + +/* Stream for reading from the input file. */ + +FILE *finput; + +/* Current line number in real source file. */ + +int lineno; + +/* Stack of currently pending input files. */ + +struct file_stack *input_file_stack; + +/* Incremented on each change to input_file_stack. */ +int input_file_stack_tick; + +/* FUNCTION_DECL for function now being parsed or compiled. */ + +extern tree current_function_decl; + +/* Name to use as base of names for dump output files. */ + +char *dump_base_name; + +/* Bit flags that specify the machine subtype we are compiling for. + Bits are tested using macros TARGET_... defined in the tm.h file + and set by `-m...' switches. Must be defined in rtlanal.c. */ + +extern int target_flags; + +/* Flags saying which kinds of debugging dump have been requested. */ + +int rtl_dump = 0; +int rtl_dump_and_exit = 0; +int jump_opt_dump = 0; +int cse_dump = 0; +int loop_dump = 0; +int cse2_dump = 0; +int flow_dump = 0; +int combine_dump = 0; +int sched_dump = 0; +int local_reg_dump = 0; +int global_reg_dump = 0; +int sched2_dump = 0; +int jump2_opt_dump = 0; +int dbr_sched_dump = 0; +int flag_print_asm_name = 0; +int stack_reg_dump = 0; + +/* Name for output file of assembly code, specified with -o. */ + +char *asm_file_name; + +/* Value of the -G xx switch, and whether it was passed or not. */ +int g_switch_value; +int g_switch_set; + +/* Type(s) of debugging information we are producing (if any). + See flags.h for the definitions of the different possible + types of debugging information. */ +enum debug_info_type write_symbols = NO_DEBUG; + +/* Level of debugging information we are producing. See flags.h + for the definitions of the different possible levels. */ +enum debug_info_level debug_info_level = DINFO_LEVEL_NONE; + +/* Nonzero means use GNU-only extensions in the generated symbolic + debugging information. */ +/* Currently, this only has an effect when write_symbols is set to + DBX_DEBUG, XCOFF_DEBUG, or DWARF_DEBUG. */ +int use_gnu_debug_info_extensions = 0; + +/* Nonzero means do optimizations. -O. + Particular numeric values stand for particular amounts of optimization; + thus, -O2 stores 2 here. However, the optimizations beyond the basic + ones are not controlled directly by this variable. Instead, they are + controlled by individual `flag_...' variables that are defaulted + based on this variable. */ + +int optimize = 0; + +/* Number of error messages and warning messages so far. */ + +int errorcount = 0; +int warningcount = 0; +int sorrycount = 0; + +/* Pointer to function to compute the name to use to print a declaration. */ + +char *(*decl_printable_name) (); + +/* Pointer to function to compute rtl for a language-specific tree code. */ + +struct rtx_def *(*lang_expand_expr) (); + +/* Pointer to function to finish handling an incomplete decl at the + end of compilation. */ + +void (*incomplete_decl_finalize_hook) () = 0; + +/* Nonzero if generating code to do profiling. */ + +int profile_flag = 0; + +/* Nonzero if generating code to do profiling on a line-by-line basis. */ + +int profile_block_flag; + +/* Nonzero for -pedantic switch: warn about anything + that standard spec forbids. */ + +int pedantic = 0; + +/* Temporarily suppress certain warnings. + This is set while reading code from a system header file. */ + +int in_system_header = 0; + +/* Nonzero means do stupid register allocation. + Currently, this is 1 if `optimize' is 0. */ + +int obey_regdecls = 0; + +/* Don't print functions as they are compiled and don't print + times taken by the various passes. -quiet. */ + +int quiet_flag = 0; + +/* -f flags. */ + +/* Nonzero means `char' should be signed. */ + +int flag_signed_char; + +/* Nonzero means give an enum type only as many bytes as it needs. */ + +int flag_short_enums; + +/* Nonzero for -fcaller-saves: allocate values in regs that need to + be saved across function calls, if that produces overall better code. + Optional now, so people can test it. */ + +#ifdef DEFAULT_CALLER_SAVES +int flag_caller_saves = 1; +#else +int flag_caller_saves = 0; +#endif + +/* Nonzero if structures and unions should be returned in memory. + + This should only be defined if compatibility with another compiler or + with an ABI is needed, because it results in slower code. */ + +#ifndef DEFAULT_PCC_STRUCT_RETURN +#define DEFAULT_PCC_STRUCT_RETURN 1 +#endif + +/* Nonzero for -fpcc-struct-return: return values the same way PCC does. */ + +int flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN; + +/* Nonzero for -fforce-mem: load memory value into a register + before arithmetic on it. This makes better cse but slower compilation. */ + +int flag_force_mem = 0; + +/* Nonzero for -fforce-addr: load memory address into a register before + reference to memory. This makes better cse but slower compilation. */ + +int flag_force_addr = 0; + +/* Nonzero for -fdefer-pop: don't pop args after each function call; + instead save them up to pop many calls' args with one insns. */ + +int flag_defer_pop = 0; + +/* Nonzero for -ffloat-store: don't allocate floats and doubles + in extended-precision registers. */ + +int flag_float_store = 0; + +/* Nonzero for -fcse-follow-jumps: + have cse follow jumps to do a more extensive job. */ + +int flag_cse_follow_jumps; + +/* Nonzero for -fcse-skip-blocks: + have cse follow a branch around a block. */ +int flag_cse_skip_blocks; + +/* Nonzero for -fexpensive-optimizations: + perform miscellaneous relatively-expensive optimizations. */ +int flag_expensive_optimizations; + +/* Nonzero for -fthread-jumps: + have jump optimize output of loop. */ + +int flag_thread_jumps; + +/* Nonzero enables strength-reduction in loop.c. */ + +int flag_strength_reduce = 0; + +/* Nonzero enables loop unrolling in unroll.c. Only loops for which the + number of iterations can be calculated at compile-time (UNROLL_COMPLETELY, + UNROLL_MODULO) or at run-time (preconditioned to be UNROLL_MODULO) are + unrolled. */ + +int flag_unroll_loops; + +/* Nonzero enables loop unrolling in unroll.c. All loops are unrolled. + This is generally not a win. */ + +int flag_unroll_all_loops; + +/* Nonzero for -fwritable-strings: + store string constants in data segment and don't uniquize them. */ + +int flag_writable_strings = 0; + +/* Nonzero means don't put addresses of constant functions in registers. + Used for compiling the Unix kernel, where strange substitutions are + done on the assembly output. */ + +int flag_no_function_cse = 0; + +/* Nonzero for -fomit-frame-pointer: + don't make a frame pointer in simple functions that don't require one. */ + +int flag_omit_frame_pointer = 0; + +/* Nonzero to inhibit use of define_optimization peephole opts. */ + +int flag_no_peephole = 0; + +/* Nonzero allows GCC to violate some IEEE or ANSI rules regarding math + operations in the interest of optimization. For example it allows + GCC to assume arguments to sqrt are nonnegative numbers, allowing + faster code for sqrt to be generated. */ + +int flag_fast_math = 0; + +/* Nonzero means all references through pointers are volatile. */ + +int flag_volatile; + +/* Nonzero means treat all global and extern variables as global. */ + +int flag_volatile_global; + +/* Nonzero means just do syntax checking; don't output anything. */ + +int flag_syntax_only = 0; + +/* Nonzero means to rerun cse after loop optimization. This increases + compilation time about 20% and picks up a few more common expressions. */ + +static int flag_rerun_cse_after_loop; + +/* Nonzero for -finline-functions: ok to inline functions that look like + good inline candidates. */ + +int flag_inline_functions; + +/* Nonzero for -fkeep-inline-functions: even if we make a function + go inline everywhere, keep its definition around for debugging + purposes. */ + +int flag_keep_inline_functions; + +/* Nonzero means that functions declared `inline' will be treated + as `static'. Prevents generation of zillions of copies of unused + static inline functions; instead, `inlines' are written out + only when actually used. Used in conjunction with -g. Also + does the right thing with #pragma interface. */ + +int flag_no_inline; + +/* Nonzero means we should be saving declaration info into a .X file. */ + +int flag_gen_aux_info = 0; + +/* Specified name of aux-info file. */ + +static char *aux_info_file_name; + +/* Nonzero means make the text shared if supported. */ + +int flag_shared_data; + +/* Nonzero means schedule into delayed branch slots if supported. */ + +int flag_delayed_branch; + +/* Nonzero if we are compiling pure (sharable) code. + Value is 1 if we are doing reasonable (i.e. simple + offset into offset table) pic. Value is 2 if we can + only perform register offsets. */ + +int flag_pic; + +/* Nonzero means place uninitialized global data in the bss section. */ + +int flag_no_common; + +/* Nonzero means pretend it is OK to examine bits of target floats, + even if that isn't true. The resulting code will have incorrect constants, + but the same series of instructions that the native compiler would make. */ + +int flag_pretend_float; + +/* Nonzero means change certain warnings into errors. + Usually these are warnings about failure to conform to some standard. */ + +int flag_pedantic_errors = 0; + +/* flag_schedule_insns means schedule insns within basic blocks (before + local_alloc). + flag_schedule_insns_after_reload means schedule insns after + global_alloc. */ + +int flag_schedule_insns = 0; +int flag_schedule_insns_after_reload = 0; + +/* -finhibit-size-directive inhibits output of .size for ELF. + This is used only for compiling crtstuff.c, + and it may be extended to other effects + needed for crtstuff.c on other systems. */ +int flag_inhibit_size_directive = 0; + +/* -fverbose-asm causes extra commentary information to be produced in + the generated assembly code (to make it more readable). This option + is generally only of use to those who actually need to read the + generated assembly code (perhaps while debugging the compiler itself). */ + +int flag_verbose_asm = 0; + +/* -fgnu-linker specifies use of the GNU linker for initializations. + (Or, more generally, a linker that handles initializations.) + -fno-gnu-linker says that collect2 will be used. */ +#ifdef USE_COLLECT2 +int flag_gnu_linker = 0; +#else +int flag_gnu_linker = 1; +#endif + +/* Table of language-independent -f options. + STRING is the option name. VARIABLE is the address of the variable. + ON_VALUE is the value to store in VARIABLE + if `-fSTRING' is seen as an option. + (If `-fno-STRING' is seen as an option, the opposite value is stored.) */ + +struct { char *string; int *variable; int on_value;} f_options[] = +{ + {"float-store", &flag_float_store, 1}, + {"volatile", &flag_volatile, 1}, + {"volatile-global", &flag_volatile_global, 1}, + {"defer-pop", &flag_defer_pop, 1}, + {"omit-frame-pointer", &flag_omit_frame_pointer, 1}, + {"cse-follow-jumps", &flag_cse_follow_jumps, 1}, + {"cse-skip-blocks", &flag_cse_skip_blocks, 1}, + {"expensive-optimizations", &flag_expensive_optimizations, 1}, + {"thread-jumps", &flag_thread_jumps, 1}, + {"strength-reduce", &flag_strength_reduce, 1}, + {"unroll-loops", &flag_unroll_loops, 1}, + {"unroll-all-loops", &flag_unroll_all_loops, 1}, + {"writable-strings", &flag_writable_strings, 1}, + {"peephole", &flag_no_peephole, 0}, + {"force-mem", &flag_force_mem, 1}, + {"force-addr", &flag_force_addr, 1}, + {"function-cse", &flag_no_function_cse, 0}, + {"inline-functions", &flag_inline_functions, 1}, + {"keep-inline-functions", &flag_keep_inline_functions, 1}, + {"inline", &flag_no_inline, 0}, + {"syntax-only", &flag_syntax_only, 1}, + {"shared-data", &flag_shared_data, 1}, + {"caller-saves", &flag_caller_saves, 1}, + {"pcc-struct-return", &flag_pcc_struct_return, 1}, + {"reg-struct-return", &flag_pcc_struct_return, 0}, + {"delayed-branch", &flag_delayed_branch, 1}, + {"rerun-cse-after-loop", &flag_rerun_cse_after_loop, 1}, + {"pretend-float", &flag_pretend_float, 1}, + {"schedule-insns", &flag_schedule_insns, 1}, + {"schedule-insns2", &flag_schedule_insns_after_reload, 1}, + {"pic", &flag_pic, 1}, + {"PIC", &flag_pic, 2}, + {"fast-math", &flag_fast_math, 1}, + {"common", &flag_no_common, 0}, + {"inhibit-size-directive", &flag_inhibit_size_directive, 1}, + {"verbose-asm", &flag_verbose_asm, 1}, + {"gnu-linker", &flag_gnu_linker, 1} +}; + +/* Table of language-specific options. */ + +char *lang_options[] = +{ + "-ftraditional", + "-traditional", + "-fnotraditional", + "-fno-traditional", + "-fsigned-char", + "-funsigned-char", + "-fno-signed-char", + "-fno-unsigned-char", + "-fsigned-bitfields", + "-funsigned-bitfields", + "-fno-signed-bitfields", + "-fno-unsigned-bitfields", + "-fshort-enums", + "-fno-short-enums", + "-fcond-mismatch", + "-fno-cond-mismatch", + "-fshort-double", + "-fno-short-double", + "-fasm", + "-fno-asm", + "-fbuiltin", + "-fno-builtin", + "-fno-ident", + "-fident", + "-ansi", + "-Wimplicit", + "-Wno-implicit", + "-Wwrite-strings", + "-Wno-write-strings", + "-Wcast-qual", + "-Wno-cast-qual", + "-Wpointer-arith", + "-Wno-pointer-arith", + "-Wstrict-prototypes", + "-Wno-strict-prototypes", + "-Wmissing-prototypes", + "-Wno-missing-prototypes", + "-Wredundant-decls", + "-Wno-redundant-decls", + "-Wnested-externs", + "-Wno-nested-externs", + "-Wtraditional", + "-Wno-traditional", + "-Wformat", + "-Wno-format", + "-Wchar-subscripts", + "-Wno-char-subscripts", + "-Wconversion", + "-Wno-conversion", + "-Wparentheses", + "-Wno-parentheses", + "-Wcomment", + "-Wno-comment", + "-Wcomments", + "-Wno-comments", + "-Wtrigraphs", + "-Wno-trigraphs", + "-Wimport", + "-Wno-import", + "-Wmissing-braces", + "-Wno-missing-braces", + "-Wall", + + /* These are for C++. */ + "-+e0", /* gcc.c tacks the `-' on the front. */ + "-+e1", + "-+e2", + "-fsave-memoized", + "-fno-save-memoized", + "-fcadillac", + "-fno-cadillac", + "-fgc", + "-fno-gc", + "-flabels-ok", + "-fno-labels-ok", + "-fstats", + "-fno-stats", + "-fthis-is-variable", + "-fno-this-is-variable", + "-fstrict-prototype", + "-fno-strict-prototype", + "-fall-virtual", + "-fno-all-virtual", + "-fmemoize-lookups", + "-fno-memoize-lookups", + "-felide-constructors", + "-fno-elide-constructors", + "-finline-debug", + "-fno-inline-debug", + "-fhandle-exceptions", + "-fno-handle-exceptions", + "-fansi-exceptions", + "-fno-ansi-exceptions", + "-fspring-exceptions", + "-fno-spring-exceptions", + "-fdefault-inline", + "-fno-default-inline", + "-fenum-int-equiv", + "-fno-enum-int-equiv", + "-fdossier", + "-fno-dossier", + "-fxref", + "-fno-xref", + "-fnonnull-objects", + "-fno-nonnull-objects", + "-fimplement-inlines", + "-fno-implement-inlines", + + "-Wreturn-type", + "-Wno-return-type", + "-Woverloaded-virtual", + "-Wno-overloaded-virtual", + "-Wenum-clash", + "-Wno-enum-clash", + "-Wtemplate-debugging", + "-Wno-template-debugging", + + /* these are for obj c */ + "-lang-objc", + "-gen-decls", + "-fgnu-runtime", + "-fno-gnu-runtime", + "-fnext-runtime", + "-fno-next-runtime", + "-Wselector", + "-Wno-selector", + "-Wprotocol", + "-Wno-protocol", + 0 +}; + +/* Options controlling warnings */ + +/* Don't print warning messages. -w. */ + +int inhibit_warnings = 0; + +/* Print various extra warnings. -W. */ + +int extra_warnings = 0; + +/* Treat warnings as errors. -Werror. */ + +int warnings_are_errors = 0; + +/* Nonzero to warn about unused local variables. */ + +int warn_unused; + +/* Nonzero to warn about variables used before they are initialized. */ + +int warn_uninitialized; + +/* Nonzero means warn about all declarations which shadow others. */ + +int warn_shadow; + +/* Warn if a switch on an enum fails to have a case for every enum value. */ + +int warn_switch; + +/* Nonzero means warn about function definitions that default the return type + or that use a null return and have a return-type other than void. */ + +int warn_return_type; + +/* Nonzero means warn about pointer casts that increase the required + alignment of the target type (and might therefore lead to a crash + due to a misaligned access). */ + +int warn_cast_align; + +/* Nonzero means warn about any identifiers that match in the first N + characters. The value N is in `id_clash_len'. */ + +int warn_id_clash; +int id_clash_len; + +/* Nonzero means warn if inline function is too large. */ + +int warn_inline; + +/* Warn if a function returns an aggregate, + since there are often incompatible calling conventions for doing this. */ + +int warn_aggregate_return; + +/* Likewise for -W. */ + +struct { char *string; int *variable; int on_value;} W_options[] = +{ + {"unused", &warn_unused, 1}, + {"error", &warnings_are_errors, 1}, + {"shadow", &warn_shadow, 1}, + {"switch", &warn_switch, 1}, + {"aggregate-return", &warn_aggregate_return, 1}, + {"cast-align", &warn_cast_align, 1}, + {"uninitialized", &warn_uninitialized, 1}, + {"inline", &warn_inline, 1} +}; + +/* Output files for assembler code (real compiler output) + and debugging dumps. */ + +FILE *asm_out_file; +FILE *aux_info_file; +FILE *rtl_dump_file; +FILE *jump_opt_dump_file; +FILE *cse_dump_file; +FILE *loop_dump_file; +FILE *cse2_dump_file; +FILE *flow_dump_file; +FILE *combine_dump_file; +FILE *sched_dump_file; +FILE *local_reg_dump_file; +FILE *global_reg_dump_file; +FILE *sched2_dump_file; +FILE *jump2_opt_dump_file; +FILE *dbr_sched_dump_file; +FILE *stack_reg_dump_file; + +/* Time accumulators, to count the total time spent in various passes. */ + +int parse_time; +int varconst_time; +int integration_time; +int jump_time; +int cse_time; +int loop_time; +int cse2_time; +int flow_time; +int combine_time; +int sched_time; +int local_alloc_time; +int global_alloc_time; +int sched2_time; +int dbr_sched_time; +int shorten_branch_time; +int stack_reg_time; +int final_time; +int symout_time; +int dump_time; + +/* Return time used so far, in microseconds. */ + +int +get_run_time () +{ +#ifdef USG + struct tms tms; +#else +#ifndef VMS + struct rusage rusage; +#else /* VMS */ + struct + { + int proc_user_time; + int proc_system_time; + int child_user_time; + int child_system_time; + } vms_times; +#endif +#endif + + if (quiet_flag) + return 0; + +#ifdef USG + times (&tms); + return (tms.tms_utime + tms.tms_stime) * (1000000 / HZ); +#else +#ifndef VMS + getrusage (0, &rusage); + return (rusage.ru_utime.tv_sec * 1000000 + rusage.ru_utime.tv_usec + + rusage.ru_stime.tv_sec * 1000000 + rusage.ru_stime.tv_usec); +#else /* VMS */ + times (&vms_times); + return (vms_times.proc_user_time + vms_times.proc_system_time) * 10000; +#endif +#endif +} + +#define TIMEVAR(VAR, BODY) \ +do { int otime = get_run_time (); BODY; VAR += get_run_time () - otime; } while (0) + +void +print_time (str, total) + char *str; + int total; +{ + fprintf (stderr, + "time in %s: %d.%06d\n", + str, total / 1000000, total % 1000000); +} + +/* Count an error or warning. Return 1 if the message should be printed. */ + +int +count_error (warningp) + int warningp; +{ + if (warningp && inhibit_warnings) + return 0; + + if (warningp && !warnings_are_errors) + warningcount++; + else + { + static int warning_message = 0; + + if (warningp && !warning_message) + { + fprintf (stderr, "%s: warnings being treated as errors\n", progname); + warning_message = 1; + } + errorcount++; + } + + return 1; +} + +/* Print a fatal error message. NAME is the text. + Also include a system error message based on `errno'. */ + +void +pfatal_with_name (name) + char *name; +{ + fprintf (stderr, "%s: ", progname); + perror (name); + exit (35); +} + +void +fatal_io_error (name) + char *name; +{ + fprintf (stderr, "%s: %s: I/O error\n", progname, name); + exit (35); +} + +void +fatal (s, v) + char *s; + int v; +{ + error (s, v); + exit (34); +} + +/* Called to give a better error message when we don't have an insn to match + what we are looking for or if the insn's constraints aren't satisfied, + rather than just calling abort(). */ + +void +fatal_insn_not_found (insn) + rtx insn; +{ + if (INSN_CODE (insn) < 0) + error ("internal error--unrecognizable insn:", 0); + else + error ("internal error--insn does not satisfy its constraints:", 0); + debug_rtx (insn); + if (asm_out_file) + fflush (asm_out_file); + if (aux_info_file) + fflush (aux_info_file); + if (rtl_dump_file) + fflush (rtl_dump_file); + if (jump_opt_dump_file) + fflush (jump_opt_dump_file); + if (cse_dump_file) + fflush (cse_dump_file); + if (loop_dump_file) + fflush (loop_dump_file); + if (cse2_dump_file) + fflush (cse2_dump_file); + if (flow_dump_file) + fflush (flow_dump_file); + if (combine_dump_file) + fflush (combine_dump_file); + if (sched_dump_file) + fflush (sched_dump_file); + if (local_reg_dump_file) + fflush (local_reg_dump_file); + if (global_reg_dump_file) + fflush (global_reg_dump_file); + if (sched2_dump_file) + fflush (sched2_dump_file); + if (jump2_opt_dump_file) + fflush (jump2_opt_dump_file); + if (dbr_sched_dump_file) + fflush (dbr_sched_dump_file); + if (stack_reg_dump_file) + fflush (stack_reg_dump_file); + abort (); +} + +/* This is the default decl_printable_name function. */ + +static char * +decl_name (decl, kind) + tree decl; + char **kind; +{ + return IDENTIFIER_POINTER (DECL_NAME (decl)); +} + +static int need_error_newline; + +/* Function of last error message; + more generally, function such that if next error message is in it + then we don't have to mention the function name. */ +static tree last_error_function = NULL; + +/* Used to detect when input_file_stack has changed since last described. */ +static int last_error_tick; + +/* Called when the start of a function definition is parsed, + this function prints on stderr the name of the function. */ + +void +announce_function (decl) + tree decl; +{ + if (! quiet_flag) + { + char *junk; + if (rtl_dump_and_exit) + fprintf (stderr, "%s ", IDENTIFIER_POINTER (DECL_NAME (decl))); + else + fprintf (stderr, " %s", (*decl_printable_name) (decl, &junk)); + fflush (stderr); + need_error_newline = 1; + last_error_function = current_function_decl; + } +} + +/* Prints out, if necessary, the name of the current function + which caused an error. Called from all error and warning functions. */ + +void +report_error_function (file) + char *file; +{ + struct file_stack *p; + + if (need_error_newline) + { + fprintf (stderr, "\n"); + need_error_newline = 0; + } + + if (last_error_function != current_function_decl) + { + char *kind = "function"; + if (current_function_decl != 0 + && TREE_CODE (TREE_TYPE (current_function_decl)) == METHOD_TYPE) + kind = "method"; + + if (file) + fprintf (stderr, "%s: ", file); + + if (current_function_decl == NULL) + fprintf (stderr, "At top level:\n"); + else + { + char *name = (*decl_printable_name) (current_function_decl, &kind); + fprintf (stderr, "In %s `%s':\n", kind, name); + } + + last_error_function = current_function_decl; + } + if (input_file_stack && input_file_stack->next != 0 + && input_file_stack_tick != last_error_tick) + { + fprintf (stderr, "In file included"); + for (p = input_file_stack->next; p; p = p->next) + { + fprintf (stderr, " from %s:%d", p->name, p->line); + if (p->next) + fprintf (stderr, ","); + } + fprintf (stderr, ":\n"); + last_error_tick = input_file_stack_tick; + } +} + +/* Report an error at the current line number. + S is a string and V and V2 are args for `printf'. We use HOST_WIDE_INT + as the type for these args assuming it is wide enough to hold a + pointer. This isn't terribly portable, but is the best we can do + without vprintf universally available. */ + +void +error (s, v, v2) + char *s; + HOST_WIDE_INT v; /* Also used as pointer */ + HOST_WIDE_INT v2; /* Also used as pointer */ +{ + error_with_file_and_line (input_filename, lineno, s, v, v2); +} + +/* Report an error at line LINE of file FILE. + S and V are a string and an arg for `printf'. */ + +void +error_with_file_and_line (file, line, s, v, v2) + char *file; + int line; + char *s; + HOST_WIDE_INT v; + HOST_WIDE_INT v2; +{ + count_error (0); + + report_error_function (file); + + if (file) + fprintf (stderr, "%s:%d: ", file, line); + else + fprintf (stderr, "%s: ", progname); + fprintf (stderr, s, v, v2); + fprintf (stderr, "\n"); +} + +/* Report an error at the declaration DECL. + S and V are a string and an arg which uses %s to substitute + the declaration name. */ + +void +error_with_decl (decl, s, v) + tree decl; + char *s; + HOST_WIDE_INT v; +{ + char *junk; + count_error (0); + + report_error_function (DECL_SOURCE_FILE (decl)); + + fprintf (stderr, "%s:%d: ", + DECL_SOURCE_FILE (decl), DECL_SOURCE_LINE (decl)); + + if (DECL_NAME (decl)) + fprintf (stderr, s, (*decl_printable_name) (decl, &junk), v); + else + fprintf (stderr, s, "((anonymous))", v); + fprintf (stderr, "\n"); +} + +/* Report an error at the line number of the insn INSN. + S and V are a string and an arg for `printf'. + This is used only when INSN is an `asm' with operands, + and each ASM_OPERANDS records its own source file and line. */ + +void +error_for_asm (insn, s, v, v2) + rtx insn; + char *s; + HOST_WIDE_INT v; /* Also used as pointer */ + HOST_WIDE_INT v2; /* Also used as pointer */ +{ + char *filename; + int line; + rtx body = PATTERN (insn); + rtx asmop; + + /* Find the (or one of the) ASM_OPERANDS in the insn. */ + if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) + asmop = SET_SRC (body); + else if (GET_CODE (body) == ASM_OPERANDS) + asmop = body; + else if (GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == SET) + asmop = SET_SRC (XVECEXP (body, 0, 0)); + else if (GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) + asmop = XVECEXP (body, 0, 0); + + filename = ASM_OPERANDS_SOURCE_FILE (asmop); + line = ASM_OPERANDS_SOURCE_LINE (asmop); + + error_with_file_and_line (filename, line, s, v, v2); +} + +/* Report a warning at line LINE. + S and V are a string and an arg for `printf'. */ + +void +warning_with_file_and_line (file, line, s, v, v2, v3) + char *file; + int line; + char *s; + HOST_WIDE_INT v, v2, v3; +{ + if (count_error (1) == 0) + return; + + report_error_function (file); + + if (file) + fprintf (stderr, "%s:%d: ", file, line); + else + fprintf (stderr, "%s: ", progname); + + fprintf (stderr, "warning: "); + fprintf (stderr, s, v, v2, v3); + fprintf (stderr, "\n"); +} + +/* Report a warning at the current line number. + S and V are a string and an arg for `printf'. */ + +void +warning (s, v, v2, v3) + char *s; + HOST_WIDE_INT v, v2, v3; /* Also used as pointer */ +{ + warning_with_file_and_line (input_filename, lineno, s, v, v2, v3); +} + +/* Report a warning at the declaration DECL. + S is string which uses %s to substitute the declaration name. + V is a second parameter that S can refer to. */ + +void +warning_with_decl (decl, s, v) + tree decl; + char *s; + HOST_WIDE_INT v; +{ + char *junk; + + if (count_error (1) == 0) + return; + + report_error_function (DECL_SOURCE_FILE (decl)); + + fprintf (stderr, "%s:%d: ", + DECL_SOURCE_FILE (decl), DECL_SOURCE_LINE (decl)); + + fprintf (stderr, "warning: "); + if (DECL_NAME (decl)) + fprintf (stderr, s, (*decl_printable_name) (decl, &junk), v); + else + fprintf (stderr, s, "((anonymous))", v); + fprintf (stderr, "\n"); +} + +/* Report a warning at the line number of the insn INSN. + S and V are a string and an arg for `printf'. + This is used only when INSN is an `asm' with operands, + and each ASM_OPERANDS records its own source file and line. */ + +void +warning_for_asm (insn, s, v, v2) + rtx insn; + char *s; + HOST_WIDE_INT v; /* Also used as pointer */ + HOST_WIDE_INT v2; /* Also used as pointer */ +{ + char *filename; + int line; + rtx body = PATTERN (insn); + rtx asmop; + + /* Find the (or one of the) ASM_OPERANDS in the insn. */ + if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) + asmop = SET_SRC (body); + else if (GET_CODE (body) == ASM_OPERANDS) + asmop = body; + else if (GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == SET) + asmop = SET_SRC (XVECEXP (body, 0, 0)); + else if (GET_CODE (body) == PARALLEL + && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) + asmop = XVECEXP (body, 0, 0); + + filename = ASM_OPERANDS_SOURCE_FILE (asmop); + line = ASM_OPERANDS_SOURCE_LINE (asmop); + + warning_with_file_and_line (filename, line, s, v, v2); +} + +/* These functions issue either warnings or errors depending on + -pedantic-errors. */ + +void +pedwarn (s, v, v2) + char *s; + HOST_WIDE_INT v; /* Also used as pointer */ + HOST_WIDE_INT v2; +{ + if (flag_pedantic_errors) + error (s, v, v2); + else + warning (s, v, v2); +} + +void +pedwarn_with_decl (decl, s, v) + tree decl; + char *s; + HOST_WIDE_INT v; +{ + if (flag_pedantic_errors) + error_with_decl (decl, s, v); + else + warning_with_decl (decl, s, v); +} + +void +pedwarn_with_file_and_line (file, line, s, v, v2) + char *file; + int line; + char *s; + HOST_WIDE_INT v; + HOST_WIDE_INT v2; +{ + if (flag_pedantic_errors) + error_with_file_and_line (file, line, s, v, v2); + else + warning_with_file_and_line (file, line, s, v, v2); +} + +/* Apologize for not implementing some feature. + S, V, and V2 are a string and args for `printf'. */ + +void +sorry (s, v, v2) + char *s; + HOST_WIDE_INT v, v2; +{ + sorrycount++; + if (input_filename) + fprintf (stderr, "%s:%d: ", input_filename, lineno); + else + fprintf (stderr, "%s: ", progname); + + fprintf (stderr, "sorry, not implemented: "); + fprintf (stderr, s, v, v2); + fprintf (stderr, "\n"); +} + +/* Apologize for not implementing some feature, then quit. + S, V, and V2 are a string and args for `printf'. */ + +void +really_sorry (s, v, v2) + char *s; + HOST_WIDE_INT v, v2; +{ + if (input_filename) + fprintf (stderr, "%s:%d: ", input_filename, lineno); + else + fprintf (stderr, "%s: ", progname); + + fprintf (stderr, "sorry, not implemented: "); + fprintf (stderr, s, v, v2); + fatal (" (fatal)\n"); +} + +/* More 'friendly' abort that prints the line and file. + config.h can #define abort fancy_abort if you like that sort of thing. + + I don't think this is actually a good idea. + Other sorts of crashes will look a certain way. + It is a good thing if crashes from calling abort look the same way. + -- RMS */ + +void +fancy_abort () +{ + fatal ("internal gcc abort"); +} + +/* This calls abort and is used to avoid problems when abort if a macro. + It is used when we need to pass the address of abort. */ + +void +do_abort () +{ + abort (); +} + +/* When `malloc.c' is compiled with `rcheck' defined, + it calls this function to report clobberage. */ + +void +botch (s) +{ + abort (); +} + +/* Same as `malloc' but report error if no memory available. */ + +char * +xmalloc (size) + unsigned size; +{ + register char *value = (char *) malloc (size); + if (value == 0) + fatal ("virtual memory exhausted"); + return value; +} + +/* Same as `realloc' but report error if no memory available. */ + +char * +xrealloc (ptr, size) + char *ptr; + int size; +{ + char *result = (char *) realloc (ptr, size); + if (!result) + fatal ("virtual memory exhausted"); + return result; +} + +/* Return the logarithm of X, base 2, considering X unsigned, + if X is a power of 2. Otherwise, returns -1. + + This should be used via the `exact_log2' macro. */ + +int +exact_log2_wide (x) + register unsigned HOST_WIDE_INT x; +{ + register int log = 0; + /* Test for 0 or a power of 2. */ + if (x == 0 || x != (x & -x)) + return -1; + while ((x >>= 1) != 0) + log++; + return log; +} + +/* Given X, an unsigned number, return the largest int Y such that 2**Y <= X. + If X is 0, return -1. + + This should be used via the floor_log2 macro. */ + +int +floor_log2_wide (x) + register unsigned HOST_WIDE_INT x; +{ + register int log = -1; + while (x != 0) + log++, + x >>= 1; + return log; +} + +int float_handled; +jmp_buf float_handler; + +/* Specify where to longjmp to when a floating arithmetic error happens. + If HANDLER is 0, it means don't handle the errors any more. */ + +void +set_float_handler (handler) + jmp_buf handler; +{ + float_handled = (handler != 0); + if (handler) + bcopy (handler, float_handler, sizeof (float_handler)); +} + +/* Specify, in HANDLER, where to longjmp to when a floating arithmetic + error happens, pushing the previous specification into OLD_HANDLER. + Return an indication of whether there was a previous handler in effect. */ + +int +push_float_handler (handler, old_handler) + jmp_buf handler, old_handler; +{ + int was_handled = float_handled; + + float_handled = 1; + if (was_handled) + bcopy (float_handler, old_handler, sizeof (float_handler)); + bcopy (handler, float_handler, sizeof (float_handler)); + return was_handled; +} + +/* Restore the previous specification of whether and where to longjmp to + when a floating arithmetic error happens. */ + +void +pop_float_handler (handled, handler) + int handled; + jmp_buf handler; +{ + float_handled = handled; + if (handled) + bcopy (handler, float_handler, sizeof (float_handler)); +} + +/* Signals actually come here. */ + +static void +float_signal (signo) + /* If this is missing, some compilers complain. */ + int signo; +{ + if (float_handled == 0) + abort (); +#if defined (USG) || defined (hpux) + signal (SIGFPE, float_signal); /* re-enable the signal catcher */ +#endif + float_handled = 0; + signal (SIGFPE, float_signal); + longjmp (float_handler, 1); +} + +/* Handler for SIGPIPE. */ + +static void +pipe_closed (signo) + /* If this is missing, some compilers complain. */ + int signo; +{ + fatal ("output pipe has been closed"); +} + +/* Strip off a legitimate source ending from the input string NAME of + length LEN. */ + +void +strip_off_ending (name, len) + char *name; + int len; +{ + if (len > 2 && ! strcmp (".c", name + len - 2)) + name[len - 2] = 0; + else if (len > 2 && ! strcmp (".m", name + len - 2)) + name[len - 2] = 0; + else if (len > 2 && ! strcmp (".i", name + len - 2)) + name[len - 2] = 0; + else if (len > 3 && ! strcmp (".ii", name + len - 3)) + name[len - 3] = 0; + else if (len > 3 && ! strcmp (".co", name + len - 3)) + name[len - 3] = 0; + else if (len > 3 && ! strcmp (".cc", name + len - 3)) + name[len - 3] = 0; + else if (len > 2 && ! strcmp (".C", name + len - 2)) + name[len - 2] = 0; + else if (len > 4 && ! strcmp (".cxx", name + len - 4)) + name[len - 4] = 0; + else if (len > 2 && ! strcmp (".f", name + len - 2)) + name[len - 2] = 0; + else if (len > 4 && ! strcmp (".ada", name + len - 4)) + name[len - 4] = 0; + else if (len > 4 && ! strcmp (".atr", name + len - 4)) + name[len - 4] = 0; +} + +/* Output a file name in the form wanted by System V. */ + +void +output_file_directive (asm_file, input_name) + FILE *asm_file; + char *input_name; +{ + int len = strlen (input_name); + char *na = input_name + len; + + /* NA gets INPUT_NAME sans directory names. */ + while (na > input_name) + { + if (na[-1] == '/') + break; + na--; + } + +#ifdef ASM_OUTPUT_MAIN_SOURCE_FILENAME + ASM_OUTPUT_MAIN_SOURCE_FILENAME (asm_file, na); +#else +#ifdef ASM_OUTPUT_SOURCE_FILENAME + ASM_OUTPUT_SOURCE_FILENAME (asm_file, na); +#else + fprintf (asm_file, "\t.file\t\"%s\"\n", na); +#endif +#endif +} + +/* Routine to build language identifier for object file. */ +static void +output_lang_identify (asm_out_file) + FILE *asm_out_file; +{ + int len = strlen (lang_identify ()) + sizeof ("__gnu_compiled_") + 1; + char *s = (char *) alloca (len); + sprintf (s, "__gnu_compiled_%s", lang_identify ()); + ASM_OUTPUT_LABEL (asm_out_file, s); +} + +/* Compile an entire file of output from cpp, named NAME. + Write a file of assembly output and various debugging dumps. */ + +static void +compile_file (name) + char *name; +{ + tree globals; + int start_time; + int dump_base_name_length; + + int name_specified = name != 0; + + if (dump_base_name == 0) + dump_base_name = name ? name : "gccdump"; + dump_base_name_length = strlen (dump_base_name); + + parse_time = 0; + varconst_time = 0; + integration_time = 0; + jump_time = 0; + cse_time = 0; + loop_time = 0; + cse2_time = 0; + flow_time = 0; + combine_time = 0; + sched_time = 0; + local_alloc_time = 0; + global_alloc_time = 0; + sched2_time = 0; + dbr_sched_time = 0; + shorten_branch_time = 0; + stack_reg_time = 0; + final_time = 0; + symout_time = 0; + dump_time = 0; + + /* Open input file. */ + + if (name == 0 || !strcmp (name, "-")) + { + finput = stdin; + name = "stdin"; + } + else + finput = fopen (name, "r"); + if (finput == 0) + pfatal_with_name (name); + +#ifdef IO_BUFFER_SIZE + setvbuf (finput, (char *) xmalloc (IO_BUFFER_SIZE), _IOFBF, IO_BUFFER_SIZE); +#endif + + /* Initialize data in various passes. */ + + init_obstacks (); + init_tree_codes (); + init_lex (); + init_rtl (); + init_emit_once (debug_info_level == DINFO_LEVEL_NORMAL + || debug_info_level == DINFO_LEVEL_VERBOSE); + init_decl_processing (); + init_optabs (); + init_stmt (); + init_expmed (); + init_expr_once (); + init_loop (); + init_reload (); + + if (flag_caller_saves) + init_caller_save (); + + /* If auxiliary info generation is desired, open the output file. + This goes in the same directory as the source file--unlike + all the other output files. */ + if (flag_gen_aux_info) + { + aux_info_file = fopen (aux_info_file_name, "w"); + if (aux_info_file == 0) + pfatal_with_name (aux_info_file_name); + } + + /* If rtl dump desired, open the output file. */ + if (rtl_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 6); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".rtl"); + rtl_dump_file = fopen (dumpname, "w"); + if (rtl_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If jump_opt dump desired, open the output file. */ + if (jump_opt_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 6); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".jump"); + jump_opt_dump_file = fopen (dumpname, "w"); + if (jump_opt_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If cse dump desired, open the output file. */ + if (cse_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 6); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".cse"); + cse_dump_file = fopen (dumpname, "w"); + if (cse_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If loop dump desired, open the output file. */ + if (loop_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 6); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".loop"); + loop_dump_file = fopen (dumpname, "w"); + if (loop_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If cse2 dump desired, open the output file. */ + if (cse2_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 6); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".cse2"); + cse2_dump_file = fopen (dumpname, "w"); + if (cse2_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If flow dump desired, open the output file. */ + if (flow_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 6); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".flow"); + flow_dump_file = fopen (dumpname, "w"); + if (flow_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If combine dump desired, open the output file. */ + if (combine_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 10); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".combine"); + combine_dump_file = fopen (dumpname, "w"); + if (combine_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If scheduling dump desired, open the output file. */ + if (sched_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 7); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".sched"); + sched_dump_file = fopen (dumpname, "w"); + if (sched_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If local_reg dump desired, open the output file. */ + if (local_reg_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 6); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".lreg"); + local_reg_dump_file = fopen (dumpname, "w"); + if (local_reg_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If global_reg dump desired, open the output file. */ + if (global_reg_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 6); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".greg"); + global_reg_dump_file = fopen (dumpname, "w"); + if (global_reg_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If 2nd scheduling dump desired, open the output file. */ + if (sched2_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 8); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".sched2"); + sched2_dump_file = fopen (dumpname, "w"); + if (sched2_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If jump2_opt dump desired, open the output file. */ + if (jump2_opt_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 7); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".jump2"); + jump2_opt_dump_file = fopen (dumpname, "w"); + if (jump2_opt_dump_file == 0) + pfatal_with_name (dumpname); + } + + /* If dbr_sched dump desired, open the output file. */ + if (dbr_sched_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 7); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".dbr"); + dbr_sched_dump_file = fopen (dumpname, "w"); + if (dbr_sched_dump_file == 0) + pfatal_with_name (dumpname); + } + +#ifdef STACK_REGS + + /* If stack_reg dump desired, open the output file. */ + if (stack_reg_dump) + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 10); + strcpy (dumpname, dump_base_name); + strcat (dumpname, ".stack"); + stack_reg_dump_file = fopen (dumpname, "w"); + if (stack_reg_dump_file == 0) + pfatal_with_name (dumpname); + } + +#endif + + /* Open assembler code output file. */ + + if (! name_specified && asm_file_name == 0) + asm_out_file = stdout; + else + { + register char *dumpname = (char *) xmalloc (dump_base_name_length + 6); + int len = strlen (dump_base_name); + strcpy (dumpname, dump_base_name); + strip_off_ending (dumpname, len); + strcat (dumpname, ".s"); + if (asm_file_name == 0) + { + asm_file_name = (char *) xmalloc (strlen (dumpname) + 1); + strcpy (asm_file_name, dumpname); + } + if (!strcmp (asm_file_name, "-")) + asm_out_file = stdout; + else + asm_out_file = fopen (asm_file_name, "w"); + if (asm_out_file == 0) + pfatal_with_name (asm_file_name); + } + +#ifdef IO_BUFFER_SIZE + setvbuf (asm_out_file, (char *) xmalloc (IO_BUFFER_SIZE), + _IOFBF, IO_BUFFER_SIZE); +#endif + + input_filename = name; + + /* Perform language-specific initialization. + This may set main_input_filename. */ + lang_init (); + + /* If the input doesn't start with a #line, use the input name + as the official input file name. */ + if (main_input_filename == 0) + main_input_filename = name; + + /* Put an entry on the input file stack for the main input file. */ + input_file_stack + = (struct file_stack *) xmalloc (sizeof (struct file_stack)); + input_file_stack->next = 0; + input_file_stack->name = input_filename; + + ASM_FILE_START (asm_out_file); + + /* Output something to inform GDB that this compilation was by GCC. */ +#ifndef ASM_IDENTIFY_GCC + fprintf (asm_out_file, "gcc2_compiled.:\n"); +#else + ASM_IDENTIFY_GCC (asm_out_file); +#endif + + /* Output something to identify which front-end produced this file. */ +#ifdef ASM_IDENTIFY_LANGUAGE + ASM_IDENTIFY_LANGUAGE (asm_out_file); +#endif + +/* ??? Note: There used to be a conditional here + to call assemble_zeros without fail if DBX_DEBUGGING_INFO is defined. + This was to guarantee separation between gcc_compiled. and + the first function, for the sake of dbx on Suns. + However, having the extra zero here confused the Emacs + code for unexec, and might confuse other programs too. + Therefore, I took out that change. + In future versions we should find another way to solve + that dbx problem. -- rms, 23 May 93. */ + + /* Don't let the first function fall at the same address + as gcc_compiled., if profiling. */ + if (profile_flag || profile_block_flag) + assemble_zeros (UNITS_PER_WORD); + + /* If dbx symbol table desired, initialize writing it + and output the predefined types. */ +#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) + if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) + TIMEVAR (symout_time, dbxout_init (asm_out_file, main_input_filename, + getdecls ())); +#endif +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG) + TIMEVAR (symout_time, sdbout_init (asm_out_file, main_input_filename, + getdecls ())); +#endif +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG) + TIMEVAR (symout_time, dwarfout_init (asm_out_file, main_input_filename)); +#endif + + /* Initialize yet another pass. */ + + init_final (main_input_filename); + + start_time = get_run_time (); + + /* Call the parser, which parses the entire file + (calling rest_of_compilation for each function). */ + + if (yyparse () != 0) + if (errorcount == 0) + fprintf (stderr, "Errors detected in input file (your bison.simple is out of date)"); + + /* Compilation is now finished except for writing + what's left of the symbol table output. */ + + parse_time += get_run_time () - start_time; + + parse_time -= integration_time; + parse_time -= varconst_time; + + globals = getdecls (); + + /* Really define vars that have had only a tentative definition. + Really output inline functions that must actually be callable + and have not been output so far. */ + + { + int len = list_length (globals); + tree *vec = (tree *) alloca (sizeof (tree) * len); + int i; + tree decl; + + /* Process the decls in reverse order--earliest first. + Put them into VEC from back to front, then take out from front. */ + + for (i = 0, decl = globals; i < len; i++, decl = TREE_CHAIN (decl)) + vec[len - i - 1] = decl; + + for (i = 0; i < len; i++) + { + decl = vec[i]; + if (TREE_CODE (decl) == VAR_DECL && DECL_SIZE (decl) == 0 + && incomplete_decl_finalize_hook != 0) + (*incomplete_decl_finalize_hook) (decl); + + if (TREE_CODE (decl) == VAR_DECL && TREE_STATIC (decl) + && ! TREE_ASM_WRITTEN (decl)) + { + /* Don't write out static consts, unless we used them. + (This used to write them out only if the address was + taken, but that was wrong; if the variable was simply + referred to, it still needs to exist or else it will + be undefined in the linker.) */ + if (! TREE_READONLY (decl) + || TREE_PUBLIC (decl) + || TREE_USED (decl) + || TREE_ADDRESSABLE (decl) + || TREE_ADDRESSABLE (DECL_ASSEMBLER_NAME (decl))) + rest_of_decl_compilation (decl, NULL_PTR, 1, 1); + else + /* Cancel the RTL for this decl so that, if debugging info + output for global variables is still to come, + this one will be omitted. */ + DECL_RTL (decl) = NULL; + } + + if (TREE_CODE (decl) == FUNCTION_DECL + && ! TREE_ASM_WRITTEN (decl) + && DECL_INITIAL (decl) != 0 + && (TREE_ADDRESSABLE (decl) + || TREE_ADDRESSABLE (DECL_ASSEMBLER_NAME (decl))) + && ! DECL_EXTERNAL (decl)) + output_inline_function (decl); + + /* Warn about any function + declared static but not defined. + We don't warn about variables, + because many programs have static variables + that exist only to get some text into the object file. */ + if ((warn_unused + || TREE_USED (decl) + || (DECL_NAME (decl) && TREE_USED (DECL_NAME (decl)))) + && TREE_CODE (decl) == FUNCTION_DECL + && DECL_INITIAL (decl) == 0 + && DECL_EXTERNAL (decl) + && ! TREE_PUBLIC (decl)) + { + /* This should be a pedwarn, except that there is + no easy way to prevent it from happening when the + name is used only inside a sizeof. + This at least avoids being incorrect. */ + warning_with_decl (decl, + "`%s' declared `static' but never defined"); + /* This symbol is effectively an "extern" declaration now. */ + TREE_PUBLIC (decl) = 1; + assemble_external (decl); + + } + /* Warn about static fns or vars defined but not used, + but not about inline functions + since unused inline statics is normal practice. */ + if (warn_unused + && (TREE_CODE (decl) == FUNCTION_DECL + || TREE_CODE (decl) == VAR_DECL) + && ! DECL_IN_SYSTEM_HEADER (decl) + && ! DECL_EXTERNAL (decl) + && ! TREE_PUBLIC (decl) + && ! TREE_USED (decl) + && ! DECL_INLINE (decl) + && ! DECL_REGISTER (decl) + /* The TREE_USED bit for file-scope decls + is kept in the identifier, to handle multiple + external decls in different scopes. */ + && ! TREE_USED (DECL_NAME (decl))) + warning_with_decl (decl, "`%s' defined but not used"); + +#ifdef SDB_DEBUGGING_INFO + /* The COFF linker can move initialized global vars to the end. + And that can screw up the symbol ordering. + By putting the symbols in that order to begin with, + we avoid a problem. mcsun!unido!fauern!tumuc!pes@uunet.uu.net. */ + if (write_symbols == SDB_DEBUG && TREE_CODE (decl) == VAR_DECL + && TREE_PUBLIC (decl) && DECL_INITIAL (decl) + && DECL_RTL (decl) != 0) + TIMEVAR (symout_time, sdbout_symbol (decl, 0)); + + /* Output COFF information for non-global + file-scope initialized variables. */ + if (write_symbols == SDB_DEBUG + && TREE_CODE (decl) == VAR_DECL + && DECL_INITIAL (decl) + && DECL_RTL (decl) != 0 + && GET_CODE (DECL_RTL (decl)) == MEM) + TIMEVAR (symout_time, sdbout_toplevel_data (decl)); +#endif /* SDB_DEBUGGING_INFO */ +#ifdef DWARF_DEBUGGING_INFO + /* Output DWARF information for file-scope tentative data object + declarations, file-scope (extern) function declarations (which + had no corresponding body) and file-scope tagged type declarations + and definitions which have not yet been forced out. */ + + if (write_symbols == DWARF_DEBUG + && (TREE_CODE (decl) != FUNCTION_DECL || !DECL_INITIAL (decl))) + TIMEVAR (symout_time, dwarfout_file_scope_decl (decl, 1)); +#endif + } + } + + /* Do dbx symbols */ +#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) + if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) + TIMEVAR (symout_time, + { + dbxout_finish (asm_out_file, main_input_filename); + }); +#endif + +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG) + TIMEVAR (symout_time, + { + dwarfout_finish (); + }); +#endif + + /* Output some stuff at end of file if nec. */ + + end_final (main_input_filename); + +#ifdef ASM_FILE_END + ASM_FILE_END (asm_out_file); +#endif + + after_finish_compilation: + + /* Language-specific end of compilation actions. */ + + lang_finish (); + + /* Close the dump files. */ + + if (flag_gen_aux_info) + { + fclose (aux_info_file); + if (errorcount) + unlink (aux_info_file_name); + } + + if (rtl_dump) + fclose (rtl_dump_file); + + if (jump_opt_dump) + fclose (jump_opt_dump_file); + + if (cse_dump) + fclose (cse_dump_file); + + if (loop_dump) + fclose (loop_dump_file); + + if (cse2_dump) + fclose (cse2_dump_file); + + if (flow_dump) + fclose (flow_dump_file); + + if (combine_dump) + { + dump_combine_total_stats (combine_dump_file); + fclose (combine_dump_file); + } + + if (sched_dump) + fclose (sched_dump_file); + + if (local_reg_dump) + fclose (local_reg_dump_file); + + if (global_reg_dump) + fclose (global_reg_dump_file); + + if (sched2_dump) + fclose (sched2_dump_file); + + if (jump2_opt_dump) + fclose (jump2_opt_dump_file); + + if (dbr_sched_dump) + fclose (dbr_sched_dump_file); + +#ifdef STACK_REGS + if (stack_reg_dump) + fclose (stack_reg_dump_file); +#endif + + /* Close non-debugging input and output files. Take special care to note + whether fclose returns an error, since the pages might still be on the + buffer chain while the file is open. */ + + fclose (finput); + if (ferror (asm_out_file) != 0 || fclose (asm_out_file) != 0) + fatal_io_error (asm_file_name); + + /* Print the times. */ + + if (! quiet_flag) + { + fprintf (stderr,"\n"); + print_time ("parse", parse_time); + print_time ("integration", integration_time); + print_time ("jump", jump_time); + print_time ("cse", cse_time); + print_time ("loop", loop_time); + print_time ("cse2", cse2_time); + print_time ("flow", flow_time); + print_time ("combine", combine_time); + print_time ("sched", sched_time); + print_time ("local-alloc", local_alloc_time); + print_time ("global-alloc", global_alloc_time); + print_time ("sched2", sched2_time); + print_time ("dbranch", dbr_sched_time); + print_time ("shorten-branch", shorten_branch_time); + print_time ("stack-reg", stack_reg_time); + print_time ("final", final_time); + print_time ("varconst", varconst_time); + print_time ("symout", symout_time); + print_time ("dump", dump_time); + } +} + +/* This is called from various places for FUNCTION_DECL, VAR_DECL, + and TYPE_DECL nodes. + + This does nothing for local (non-static) variables. + Otherwise, it sets up the RTL and outputs any assembler code + (label definition, storage allocation and initialization). + + DECL is the declaration. If ASMSPEC is nonzero, it specifies + the assembler symbol name to be used. TOP_LEVEL is nonzero + if this declaration is not within a function. */ + +void +rest_of_decl_compilation (decl, asmspec, top_level, at_end) + tree decl; + char *asmspec; + int top_level; + int at_end; +{ + /* Declarations of variables, and of functions defined elsewhere. */ + + /* Forward declarations for nested functions are not "external", + but we need to treat them as if they were. */ + if (TREE_STATIC (decl) || DECL_EXTERNAL (decl) + || TREE_CODE (decl) == FUNCTION_DECL) + TIMEVAR (varconst_time, + { + make_decl_rtl (decl, asmspec, top_level); + /* For a user-invisible decl that should be replaced + by its value when used, don't output anything. */ + if (! (TREE_CODE (decl) == VAR_DECL + && DECL_IGNORED_P (decl) && TREE_READONLY (decl) + && DECL_INITIAL (decl) != 0)) + /* Don't output anything + when a tentative file-scope definition is seen. + But at end of compilation, do output code for them. */ + if (! (! at_end && top_level + && (DECL_INITIAL (decl) == 0 + || DECL_INITIAL (decl) == error_mark_node + || DECL_IGNORED_P (decl)))) + assemble_variable (decl, top_level, at_end); + }); + else if (DECL_REGISTER (decl) && asmspec != 0) + { + if (decode_reg_name (asmspec) >= 0) + { + DECL_RTL (decl) = 0; + make_decl_rtl (decl, asmspec, top_level); + } + else + error ("invalid register name `%s' for register variable", asmspec); + } +#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) + else if ((write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) + && TREE_CODE (decl) == TYPE_DECL) + TIMEVAR (symout_time, dbxout_symbol (decl, 0)); +#endif +#ifdef SDB_DEBUGGING_INFO + else if (write_symbols == SDB_DEBUG && top_level + && TREE_CODE (decl) == TYPE_DECL) + TIMEVAR (symout_time, sdbout_symbol (decl, 0)); +#endif +} + +/* Called after finishing a record, union or enumeral type. */ + +void +rest_of_type_compilation (type, toplev) + tree type; + int toplev; +{ +#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) + if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) + TIMEVAR (symout_time, dbxout_symbol (TYPE_STUB_DECL (type), !toplev)); +#endif +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG) + TIMEVAR (symout_time, sdbout_symbol (TYPE_STUB_DECL (type), !toplev)); +#endif +} + +/* This is called from finish_function (within yyparse) + after each top-level definition is parsed. + It is supposed to compile that function or variable + and output the assembler code for it. + After we return, the tree storage is freed. */ + +void +rest_of_compilation (decl) + tree decl; +{ + register rtx insns; + int start_time = get_run_time (); + int tem; + /* Nonzero if we have saved the original DECL_INITIAL of the function, + to be restored after we finish compiling the function + (for use when compiling inline calls to this function). */ + tree saved_block_tree = 0; + /* Likewise, for DECL_ARGUMENTS. */ + tree saved_arguments = 0; + int failure = 0; + + /* If we are reconsidering an inline function + at the end of compilation, skip the stuff for making it inline. */ + + if (DECL_SAVED_INSNS (decl) == 0) + { + int specd = DECL_INLINE (decl); + char *lose; + + /* If requested, consider whether to make this function inline. */ + if (specd || flag_inline_functions) + TIMEVAR (integration_time, + { + lose = function_cannot_inline_p (decl); + if (lose) + { + if (warn_inline && specd) + warning_with_decl (decl, lose); + DECL_INLINE (decl) = 0; + } + else + DECL_INLINE (decl) = 1; + }); + + insns = get_insns (); + + /* Dump the rtl code if we are dumping rtl. */ + + if (rtl_dump) + TIMEVAR (dump_time, + { + fprintf (rtl_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + if (DECL_SAVED_INSNS (decl)) + fprintf (rtl_dump_file, ";; (integrable)\n\n"); + print_rtl (rtl_dump_file, insns); + fflush (rtl_dump_file); + }); + + /* If function is inline, and we don't yet know whether to + compile it by itself, defer decision till end of compilation. + finish_compilation will call rest_of_compilation again + for those functions that need to be output. */ + + if (DECL_INLINE (decl) + && ((! TREE_PUBLIC (decl) && ! TREE_ADDRESSABLE (decl) + && ! flag_keep_inline_functions) + || DECL_EXTERNAL (decl))) + { +#ifdef DWARF_DEBUGGING_INFO + /* Generate the DWARF info for the "abstract" instance + of a function which we may later generate inlined and/or + out-of-line instances of. */ + if (write_symbols == DWARF_DEBUG) + { + set_decl_abstract_flags (decl, 1); + TIMEVAR (symout_time, dwarfout_file_scope_decl (decl, 0)); + set_decl_abstract_flags (decl, 0); + } +#endif + TIMEVAR (integration_time, save_for_inline_nocopy (decl)); + goto exit_rest_of_compilation; + } + + /* If we have to compile the function now, save its rtl and subdecls + so that its compilation will not affect what others get. */ + if (DECL_INLINE (decl)) + { +#ifdef DWARF_DEBUGGING_INFO + /* Generate the DWARF info for the "abstract" instance of + a function which we will generate an out-of-line instance + of almost immediately (and which we may also later generate + various inlined instances of). */ + if (write_symbols == DWARF_DEBUG) + { + set_decl_abstract_flags (decl, 1); + TIMEVAR (symout_time, dwarfout_file_scope_decl (decl, 0)); + set_decl_abstract_flags (decl, 0); + } +#endif + saved_block_tree = DECL_INITIAL (decl); + saved_arguments = DECL_ARGUMENTS (decl); + TIMEVAR (integration_time, save_for_inline_copying (decl)); + } + } + + TREE_ASM_WRITTEN (decl) = 1; + + /* Now that integrate will no longer see our rtl, we need not distinguish + between the return value of this function and the return value of called + functions. */ + rtx_equal_function_value_matters = 0; + + /* Don't return yet if -Wreturn-type; we need to do jump_optimize. */ + if ((rtl_dump_and_exit || flag_syntax_only) && !warn_return_type) + { + goto exit_rest_of_compilation; + } + + /* From now on, allocate rtl in current_obstack, not in saveable_obstack. + Note that that may have been done above, in save_for_inline_copying. + The call to resume_temporary_allocation near the end of this function + goes back to the usual state of affairs. */ + + rtl_in_current_obstack (); + +#ifdef FINALIZE_PIC + /* If we are doing position-independent code generation, now + is the time to output special prologues and epilogues. + We do not want to do this earlier, because it just clutters + up inline functions with meaningless insns. */ + if (flag_pic) + FINALIZE_PIC; +#endif + + insns = get_insns (); + + /* Copy any shared structure that should not be shared. */ + + unshare_all_rtl (insns); + + /* Instantiate all virtual registers. */ + + instantiate_virtual_regs (current_function_decl, get_insns ()); + + /* See if we have allocated stack slots that are not directly addressable. + If so, scan all the insns and create explicit address computation + for all references to such slots. */ +/* fixup_stack_slots (); */ + + /* Do jump optimization the first time, if -opt. + Also do it if -W, but in that case it doesn't change the rtl code, + it only computes whether control can drop off the end of the function. */ + + if (optimize > 0 || extra_warnings || warn_return_type + /* If function is `volatile', we should warn if it tries to return. */ + || TREE_THIS_VOLATILE (decl)) + { + TIMEVAR (jump_time, reg_scan (insns, max_reg_num (), 0)); + TIMEVAR (jump_time, jump_optimize (insns, 0, 0, 1)); + } + + /* Now is when we stop if -fsyntax-only and -Wreturn-type. */ + if (rtl_dump_and_exit || flag_syntax_only) + goto exit_rest_of_compilation; + + /* Dump rtl code after jump, if we are doing that. */ + + if (jump_opt_dump) + TIMEVAR (dump_time, + { + fprintf (jump_opt_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + print_rtl (jump_opt_dump_file, insns); + fflush (jump_opt_dump_file); + }); + + /* Perform common subexpression elimination. + Nonzero value from `cse_main' means that jumps were simplified + and some code may now be unreachable, so do + jump optimization again. */ + + if (cse_dump) + TIMEVAR (dump_time, + { + fprintf (cse_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + }); + + if (optimize > 0) + { + TIMEVAR (cse_time, reg_scan (insns, max_reg_num (), 1)); + + if (flag_thread_jumps) + /* Hacks by tiemann & kenner. */ + TIMEVAR (jump_time, thread_jumps (insns, max_reg_num (), 0)); + + TIMEVAR (cse_time, tem = cse_main (insns, max_reg_num (), + 0, cse_dump_file)); + TIMEVAR (cse_time, delete_dead_from_cse (insns, max_reg_num ())); + + if (tem) + TIMEVAR (jump_time, jump_optimize (insns, 0, 0, 0)); + } + + /* Dump rtl code after cse, if we are doing that. */ + + if (cse_dump) + TIMEVAR (dump_time, + { + print_rtl (cse_dump_file, insns); + fflush (cse_dump_file); + }); + + if (loop_dump) + TIMEVAR (dump_time, + { + fprintf (loop_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + }); + + /* Move constant computations out of loops. */ + + if (optimize > 0) + { + TIMEVAR (loop_time, + { + loop_optimize (insns, loop_dump_file); + }); + } + + /* Dump rtl code after loop opt, if we are doing that. */ + + if (loop_dump) + TIMEVAR (dump_time, + { + print_rtl (loop_dump_file, insns); + fflush (loop_dump_file); + }); + + if (cse2_dump) + TIMEVAR (dump_time, + { + fprintf (cse2_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + }); + + if (optimize > 0 && flag_rerun_cse_after_loop) + { + TIMEVAR (cse2_time, reg_scan (insns, max_reg_num (), 0)); + + TIMEVAR (cse2_time, tem = cse_main (insns, max_reg_num (), + 1, cse2_dump_file)); + if (tem) + TIMEVAR (jump_time, jump_optimize (insns, 0, 0, 0)); + } + + if (optimize > 0 && flag_thread_jumps) + /* This pass of jump threading straightens out code + that was kinked by loop optimization. */ + TIMEVAR (jump_time, thread_jumps (insns, max_reg_num (), 0)); + + /* Dump rtl code after cse, if we are doing that. */ + + if (cse2_dump) + TIMEVAR (dump_time, + { + print_rtl (cse2_dump_file, insns); + fflush (cse2_dump_file); + }); + + /* We are no longer anticipating cse in this function, at least. */ + + cse_not_expected = 1; + + /* Now we choose between stupid (pcc-like) register allocation + (if we got the -noreg switch and not -opt) + and smart register allocation. */ + + if (optimize > 0) /* Stupid allocation probably won't work */ + obey_regdecls = 0; /* if optimizations being done. */ + + regclass_init (); + + /* Print function header into flow dump now + because doing the flow analysis makes some of the dump. */ + + if (flow_dump) + TIMEVAR (dump_time, + { + fprintf (flow_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + }); + + if (obey_regdecls) + { + TIMEVAR (flow_time, + { + regclass (insns, max_reg_num ()); + stupid_life_analysis (insns, max_reg_num (), + flow_dump_file); + }); + } + else + { + /* Do control and data flow analysis, + and write some of the results to dump file. */ + + TIMEVAR (flow_time, flow_analysis (insns, max_reg_num (), + flow_dump_file)); + if (warn_uninitialized) + { + uninitialized_vars_warning (DECL_INITIAL (decl)); + setjmp_args_warning (); + } + } + + /* Dump rtl after flow analysis. */ + + if (flow_dump) + TIMEVAR (dump_time, + { + print_rtl (flow_dump_file, insns); + fflush (flow_dump_file); + }); + + /* If -opt, try combining insns through substitution. */ + + if (optimize > 0) + TIMEVAR (combine_time, combine_instructions (insns, max_reg_num ())); + + /* Dump rtl code after insn combination. */ + + if (combine_dump) + TIMEVAR (dump_time, + { + fprintf (combine_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + dump_combine_stats (combine_dump_file); + print_rtl (combine_dump_file, insns); + fflush (combine_dump_file); + }); + + /* Print function header into sched dump now + because doing the sched analysis makes some of the dump. */ + + if (sched_dump) + TIMEVAR (dump_time, + { + fprintf (sched_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + }); + + if (optimize > 0 && flag_schedule_insns) + { + /* Do control and data sched analysis, + and write some of the results to dump file. */ + + TIMEVAR (sched_time, schedule_insns (sched_dump_file)); + } + + /* Dump rtl after instruction scheduling. */ + + if (sched_dump) + TIMEVAR (dump_time, + { + print_rtl (sched_dump_file, insns); + fflush (sched_dump_file); + }); + + /* Unless we did stupid register allocation, + allocate pseudo-regs that are used only within 1 basic block. */ + + if (!obey_regdecls) + TIMEVAR (local_alloc_time, + { + regclass (insns, max_reg_num ()); + local_alloc (); + }); + + /* Dump rtl code after allocating regs within basic blocks. */ + + if (local_reg_dump) + TIMEVAR (dump_time, + { + fprintf (local_reg_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + dump_flow_info (local_reg_dump_file); + dump_local_alloc (local_reg_dump_file); + print_rtl (local_reg_dump_file, insns); + fflush (local_reg_dump_file); + }); + + if (global_reg_dump) + TIMEVAR (dump_time, + fprintf (global_reg_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl)))); + + /* Unless we did stupid register allocation, + allocate remaining pseudo-regs, then do the reload pass + fixing up any insns that are invalid. */ + + TIMEVAR (global_alloc_time, + { + if (!obey_regdecls) + failure = global_alloc (global_reg_dump_file); + else + failure = reload (insns, 0, global_reg_dump_file); + }); + + if (global_reg_dump) + TIMEVAR (dump_time, + { + dump_global_regs (global_reg_dump_file); + print_rtl (global_reg_dump_file, insns); + fflush (global_reg_dump_file); + }); + + if (failure) + goto exit_rest_of_compilation; + + reload_completed = 1; + + /* On some machines, the prologue and epilogue code, or parts thereof, + can be represented as RTL. Doing so lets us schedule insns between + it and the rest of the code and also allows delayed branch + scheduling to operate in the epilogue. */ + + thread_prologue_and_epilogue_insns (insns); + + if (optimize > 0 && flag_schedule_insns_after_reload) + { + if (sched2_dump) + TIMEVAR (dump_time, + { + fprintf (sched2_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + }); + + /* Do control and data sched analysis again, + and write some more of the results to dump file. */ + + TIMEVAR (sched2_time, schedule_insns (sched2_dump_file)); + + /* Dump rtl after post-reorder instruction scheduling. */ + + if (sched2_dump) + TIMEVAR (dump_time, + { + print_rtl (sched2_dump_file, insns); + fflush (sched2_dump_file); + }); + } + +#ifdef LEAF_REGISTERS + leaf_function = 0; + if (optimize > 0 && only_leaf_regs_used () && leaf_function_p ()) + leaf_function = 1; +#endif + + /* One more attempt to remove jumps to .+1 + left by dead-store-elimination. + Also do cross-jumping this time + and delete no-op move insns. */ + + if (optimize > 0) + { + TIMEVAR (jump_time, jump_optimize (insns, 1, 1, 0)); + } + + /* Dump rtl code after jump, if we are doing that. */ + + if (jump2_opt_dump) + TIMEVAR (dump_time, + { + fprintf (jump2_opt_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + print_rtl (jump2_opt_dump_file, insns); + fflush (jump2_opt_dump_file); + }); + + /* If a scheduling pass for delayed branches is to be done, + call the scheduling code. */ + +#ifdef DELAY_SLOTS + if (optimize > 0 && flag_delayed_branch) + { + TIMEVAR (dbr_sched_time, dbr_schedule (insns, dbr_sched_dump_file)); + if (dbr_sched_dump) + { + TIMEVAR (dump_time, + { + fprintf (dbr_sched_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + print_rtl (dbr_sched_dump_file, insns); + fflush (dbr_sched_dump_file); + }); + } + } +#endif + + if (optimize > 0) + /* Shorten branches. */ + TIMEVAR (shorten_branch_time, + { + shorten_branches (get_insns ()); + }); + +#ifdef STACK_REGS + TIMEVAR (stack_reg_time, reg_to_stack (insns, stack_reg_dump_file)); + if (stack_reg_dump) + { + TIMEVAR (dump_time, + { + fprintf (stack_reg_dump_file, "\n;; Function %s\n\n", + IDENTIFIER_POINTER (DECL_NAME (decl))); + print_rtl (stack_reg_dump_file, insns); + fflush (stack_reg_dump_file); + }); + } +#endif + + /* Now turn the rtl into assembler code. */ + + TIMEVAR (final_time, + { + rtx x; + char *fnname; + + /* Get the function's name, as described by its RTL. + This may be different from the DECL_NAME name used + in the source file. */ + + x = DECL_RTL (decl); + if (GET_CODE (x) != MEM) + abort (); + x = XEXP (x, 0); + if (GET_CODE (x) != SYMBOL_REF) + abort (); + fnname = XSTR (x, 0); + + assemble_start_function (decl, fnname); + final_start_function (insns, asm_out_file, optimize); + final (insns, asm_out_file, optimize, 0); + final_end_function (insns, asm_out_file, optimize); + assemble_end_function (decl, fnname); + fflush (asm_out_file); + }); + + /* Write DBX symbols if requested */ + + /* Note that for those inline functions where we don't initially + know for certain that we will be generating an out-of-line copy, + the first invocation of this routine (rest_of_compilation) will + skip over this code by doing a `goto exit_rest_of_compilation;'. + Later on, finish_compilation will call rest_of_compilation again + for those inline functions that need to have out-of-line copies + generated. During that call, we *will* be routed past here. */ + +#ifdef DBX_DEBUGGING_INFO + if (write_symbols == DBX_DEBUG) + TIMEVAR (symout_time, dbxout_function (decl)); +#endif + +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols == DWARF_DEBUG) + TIMEVAR (symout_time, dwarfout_file_scope_decl (decl, 0)); +#endif + + exit_rest_of_compilation: + + /* In case the function was not output, + don't leave any temporary anonymous types + queued up for sdb output. */ +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG) + sdbout_types (NULL_TREE); +#endif + + /* Put back the tree of subblocks and list of arguments + from before we copied them. + Code generation and the output of debugging info may have modified + the copy, but the original is unchanged. */ + + if (saved_block_tree != 0) + DECL_INITIAL (decl) = saved_block_tree; + if (saved_arguments != 0) + DECL_ARGUMENTS (decl) = saved_arguments; + + reload_completed = 0; + + /* Clear out the real_constant_chain before some of the rtx's + it runs through become garbage. */ + + clear_const_double_mem (); + + /* Cancel the effect of rtl_in_current_obstack. */ + + resume_temporary_allocation (); + + /* The parsing time is all the time spent in yyparse + *except* what is spent in this function. */ + + parse_time -= get_run_time () - start_time; +} + +/* Entry point of cc1/c++. Decode command args, then call compile_file. + Exit code is 35 if can't open files, 34 if fatal error, + 33 if had nonfatal errors, else success. */ + +int +main (argc, argv, envp) + int argc; + char **argv; + char **envp; +{ + register int i; + char *filename = 0; + int flag_print_mem = 0; + int version_flag = 0; + char *p; + + /* save in case md file wants to emit args as a comment. */ + save_argc = argc; + save_argv = argv; + + p = argv[0] + strlen (argv[0]); + while (p != argv[0] && p[-1] != '/') --p; + progname = p; + +#ifdef RLIMIT_STACK + /* Get rid of any avoidable limit on stack size. */ + { + struct rlimit rlim; + + /* Set the stack limit huge so that alloca does not fail. */ + getrlimit (RLIMIT_STACK, &rlim); + rlim.rlim_cur = rlim.rlim_max; + setrlimit (RLIMIT_STACK, &rlim); + } +#endif /* RLIMIT_STACK */ + + signal (SIGFPE, float_signal); + +#ifdef SIGPIPE + signal (SIGPIPE, pipe_closed); +#endif + + decl_printable_name = decl_name; + lang_expand_expr = (struct rtx_def *(*)()) do_abort; + + /* Initialize whether `char' is signed. */ + flag_signed_char = DEFAULT_SIGNED_CHAR; +#ifdef DEFAULT_SHORT_ENUMS + /* Initialize how much space enums occupy, by default. */ + flag_short_enums = DEFAULT_SHORT_ENUMS; +#endif + + /* Scan to see what optimization level has been specified. That will + determine the default value of many flags. */ + for (i = 1; i < argc; i++) + { + if (!strcmp (argv[i], "-O")) + { + optimize = 1; + } + else if (argv[i][0] == '-' && argv[i][1] == 'O') + { + /* Handle -O2, -O3, -O69, ... */ + char *p = &argv[i][2]; + int c; + + while (c = *p++) + if (! (c >= '0' && c <= '9')) + break; + if (c == 0) + optimize = atoi (&argv[i][2]); + } + } + + obey_regdecls = (optimize == 0); + if (optimize == 0) + { + flag_no_inline = 1; + warn_inline = 0; + } + + if (optimize >= 1) + { + flag_defer_pop = 1; + flag_thread_jumps = 1; +#ifdef DELAY_SLOTS + flag_delayed_branch = 1; +#endif + } + + if (optimize >= 2) + { + flag_cse_follow_jumps = 1; + flag_cse_skip_blocks = 1; + flag_expensive_optimizations = 1; + flag_strength_reduce = 1; + flag_rerun_cse_after_loop = 1; + flag_caller_saves = 1; +#ifdef INSN_SCHEDULING + flag_schedule_insns = 1; + flag_schedule_insns_after_reload = 1; +#endif + } + +#ifdef OPTIMIZATION_OPTIONS + /* Allow default optimizations to be specified on a per-machine basis. */ + OPTIMIZATION_OPTIONS (optimize); +#endif + + /* Initialize register usage now so switches may override. */ + init_reg_sets (); + + target_flags = 0; + set_target_switch (""); + + for (i = 1; i < argc; i++) + { + int j; + /* If this is a language-specific option, + decode it in a language-specific way. */ + for (j = 0; lang_options[j] != 0; j++) + if (!strncmp (argv[i], lang_options[j], + strlen (lang_options[j]))) + break; + if (lang_options[j] != 0) + /* If the option is valid for *some* language, + treat it as valid even if this language doesn't understand it. */ + lang_decode_option (argv[i]); + else if (argv[i][0] == '-' && argv[i][1] != 0) + { + register char *str = argv[i] + 1; + if (str[0] == 'Y') + str++; + + if (str[0] == 'm') + set_target_switch (&str[1]); + else if (!strcmp (str, "dumpbase")) + { + dump_base_name = argv[++i]; + } + else if (str[0] == 'd') + { + register char *p = &str[1]; + while (*p) + switch (*p++) + { + case 'a': + combine_dump = 1; + dbr_sched_dump = 1; + flow_dump = 1; + global_reg_dump = 1; + jump_opt_dump = 1; + jump2_opt_dump = 1; + local_reg_dump = 1; + loop_dump = 1; + rtl_dump = 1; + cse_dump = 1, cse2_dump = 1; + sched_dump = 1; + sched2_dump = 1; + stack_reg_dump = 1; + break; + case 'k': + stack_reg_dump = 1; + break; + case 'c': + combine_dump = 1; + break; + case 'd': + dbr_sched_dump = 1; + break; + case 'f': + flow_dump = 1; + break; + case 'g': + global_reg_dump = 1; + break; + case 'j': + jump_opt_dump = 1; + break; + case 'J': + jump2_opt_dump = 1; + break; + case 'l': + local_reg_dump = 1; + break; + case 'L': + loop_dump = 1; + break; + case 'm': + flag_print_mem = 1; + break; + case 'p': + flag_print_asm_name = 1; + break; + case 'r': + rtl_dump = 1; + break; + case 's': + cse_dump = 1; + break; + case 't': + cse2_dump = 1; + break; + case 'S': + sched_dump = 1; + break; + case 'R': + sched2_dump = 1; + break; + case 'y': + set_yydebug (1); + break; + + case 'x': + rtl_dump_and_exit = 1; + break; + } + } + else if (str[0] == 'f') + { + register char *p = &str[1]; + int found = 0; + + /* Some kind of -f option. + P's value is the option sans `-f'. + Search for it in the table of options. */ + + for (j = 0; + !found && j < sizeof (f_options) / sizeof (f_options[0]); + j++) + { + if (!strcmp (p, f_options[j].string)) + { + *f_options[j].variable = f_options[j].on_value; + /* A goto here would be cleaner, + but breaks the vax pcc. */ + found = 1; + } + if (p[0] == 'n' && p[1] == 'o' && p[2] == '-' + && ! strcmp (p+3, f_options[j].string)) + { + *f_options[j].variable = ! f_options[j].on_value; + found = 1; + } + } + + if (found) + ; + else if (!strncmp (p, "fixed-", 6)) + fix_register (&p[6], 1, 1); + else if (!strncmp (p, "call-used-", 10)) + fix_register (&p[10], 0, 1); + else if (!strncmp (p, "call-saved-", 11)) + fix_register (&p[11], 0, 0); + else + error ("Invalid option `%s'", argv[i]); + } + else if (str[0] == 'O') + { + register char *p = str+1; + while (*p && *p >= '0' && *p <= '9') + p++; + if (*p == '\0') + ; + else + error ("Invalid option `%s'", argv[i]); + } + else if (!strcmp (str, "pedantic")) + pedantic = 1; + else if (!strcmp (str, "pedantic-errors")) + flag_pedantic_errors = pedantic = 1; + else if (!strcmp (str, "quiet")) + quiet_flag = 1; + else if (!strcmp (str, "version")) + version_flag = 1; + else if (!strcmp (str, "w")) + inhibit_warnings = 1; + else if (!strcmp (str, "W")) + { + extra_warnings = 1; + warn_uninitialized = 1; + } + else if (str[0] == 'W') + { + register char *p = &str[1]; + int found = 0; + + /* Some kind of -W option. + P's value is the option sans `-W'. + Search for it in the table of options. */ + + for (j = 0; + !found && j < sizeof (W_options) / sizeof (W_options[0]); + j++) + { + if (!strcmp (p, W_options[j].string)) + { + *W_options[j].variable = W_options[j].on_value; + /* A goto here would be cleaner, + but breaks the vax pcc. */ + found = 1; + } + if (p[0] == 'n' && p[1] == 'o' && p[2] == '-' + && ! strcmp (p+3, W_options[j].string)) + { + *W_options[j].variable = ! W_options[j].on_value; + found = 1; + } + } + + if (found) + ; + else if (!strncmp (p, "id-clash-", 9)) + { + char *endp = p + 9; + + while (*endp) + { + if (*endp >= '0' && *endp <= '9') + endp++; + else + { + error ("Invalid option `%s'", argv[i]); + goto id_clash_lose; + } + } + warn_id_clash = 1; + id_clash_len = atoi (str + 10); + id_clash_lose: ; + } + else + error ("Invalid option `%s'", argv[i]); + } + else if (!strcmp (str, "p")) + profile_flag = 1; + else if (!strcmp (str, "a")) + { +#if !defined (BLOCK_PROFILER) || !defined (FUNCTION_BLOCK_PROFILER) + warning ("`-a' option (basic block profile) not supported"); +#else + profile_block_flag = 1; +#endif + } + else if (str[0] == 'g') + { + char *p = str + 1; + char *q; + unsigned len; + unsigned level; + + while (*p && (*p < '0' || *p > '9')) + p++; + len = p - str; + q = p; + while (*q && (*q >= '0' && *q <= '9')) + q++; + if (*p) + level = atoi (p); + else + level = 2; /* default debugging info level */ + if (*q || level > 3) + { + warning ("invalid debug level specification in option: `-%s'", + str); + warning ("no debugging information will be generated"); + level = 0; + } + + /* If more than one debugging type is supported, + you must define PREFERRED_DEBUGGING_TYPE + to choose a format in a system-dependent way. */ + /* This is one long line cause VAXC can't handle a \-newline. */ +#if 1 < (defined (DBX_DEBUGGING_INFO) + defined (SDB_DEBUGGING_INFO) + defined (DWARF_DEBUGGING_INFO) + defined (XCOFF_DEBUGGING_INFO)) +#ifdef PREFERRED_DEBUGGING_TYPE + if (!strncmp (str, "ggdb", len)) + write_symbols = PREFERRED_DEBUGGING_TYPE; +#else /* no PREFERRED_DEBUGGING_TYPE */ +You Lose! You must define PREFERRED_DEBUGGING_TYPE! +#endif /* no PREFERRED_DEBUGGING_TYPE */ +#endif /* More than one debugger format enabled. */ +#ifdef DBX_DEBUGGING_INFO + if (write_symbols != NO_DEBUG) + ; + else if (!strncmp (str, "ggdb", len)) + write_symbols = DBX_DEBUG; + else if (!strncmp (str, "gstabs", len)) + write_symbols = DBX_DEBUG; + else if (!strncmp (str, "gstabs+", len)) + write_symbols = DBX_DEBUG; + + /* Always enable extensions for -ggdb or -gstabs+, + always disable for -gstabs. + For plain -g, use system-specific default. */ + if (write_symbols == DBX_DEBUG && !strncmp (str, "ggdb", len) + && len >= 2) + use_gnu_debug_info_extensions = 1; + else if (write_symbols == DBX_DEBUG && !strncmp (str, "gstabs+", len) + && len >= 7) + use_gnu_debug_info_extensions = 1; + else if (write_symbols == DBX_DEBUG + && !strncmp (str, "gstabs", len) && len >= 2) + use_gnu_debug_info_extensions = 0; + else + use_gnu_debug_info_extensions = DEFAULT_GDB_EXTENSIONS; +#endif /* DBX_DEBUGGING_INFO */ +#ifdef DWARF_DEBUGGING_INFO + if (write_symbols != NO_DEBUG) + ; + else if (!strncmp (str, "g", len)) + write_symbols = DWARF_DEBUG; + else if (!strncmp (str, "ggdb", len)) + write_symbols = DWARF_DEBUG; + else if (!strncmp (str, "gdwarf", len)) + write_symbols = DWARF_DEBUG; + + /* Always enable extensions for -ggdb or -gdwarf+, + always disable for -gdwarf. + For plain -g, use system-specific default. */ + if (write_symbols == DWARF_DEBUG && !strncmp (str, "ggdb", len) + && len >= 2) + use_gnu_debug_info_extensions = 1; + else if (write_symbols == DWARF_DEBUG && !strcmp (str, "gdwarf+")) + use_gnu_debug_info_extensions = 1; + else if (write_symbols == DWARF_DEBUG + && !strncmp (str, "gdwarf", len) && len >= 2) + use_gnu_debug_info_extensions = 0; + else + use_gnu_debug_info_extensions = DEFAULT_GDB_EXTENSIONS; +#endif +#ifdef SDB_DEBUGGING_INFO + if (write_symbols != NO_DEBUG) + ; + else if (!strncmp (str, "g", len)) + write_symbols = SDB_DEBUG; + else if (!strncmp (str, "gdb", len)) + write_symbols = SDB_DEBUG; + else if (!strncmp (str, "gcoff", len)) + write_symbols = SDB_DEBUG; +#endif /* SDB_DEBUGGING_INFO */ +#ifdef XCOFF_DEBUGGING_INFO + if (write_symbols != NO_DEBUG) + ; + else if (!strncmp (str, "g", len)) + write_symbols = XCOFF_DEBUG; + else if (!strncmp (str, "ggdb", len)) + write_symbols = XCOFF_DEBUG; + else if (!strncmp (str, "gxcoff", len)) + write_symbols = XCOFF_DEBUG; + + /* Always enable extensions for -ggdb or -gxcoff+, + always disable for -gxcoff. + For plain -g, use system-specific default. */ + if (write_symbols == XCOFF_DEBUG && !strncmp (str, "ggdb", len) + && len >= 2) + use_gnu_debug_info_extensions = 1; + else if (write_symbols == XCOFF_DEBUG && !strcmp (str, "gxcoff+")) + use_gnu_debug_info_extensions = 1; + else if (write_symbols == XCOFF_DEBUG + && !strncmp (str, "gxcoff", len) && len >= 2) + use_gnu_debug_info_extensions = 0; + else + use_gnu_debug_info_extensions = DEFAULT_GDB_EXTENSIONS; +#endif + if (write_symbols == NO_DEBUG) + warning ("`-%s' option not supported on this version of GCC", str); + else if (level == 0) + write_symbols = NO_DEBUG; + else + debug_info_level = (enum debug_info_level) level; + } + else if (!strcmp (str, "o")) + { + asm_file_name = argv[++i]; + } + else if (str[0] == 'G') + { + g_switch_set = TRUE; + g_switch_value = atoi ((str[1] != '\0') ? str+1 : argv[++i]); + } + else if (!strncmp (str, "aux-info", 8)) + { + flag_gen_aux_info = 1; + aux_info_file_name = (str[8] != '\0' ? str+8 : argv[++i]); + } + else + error ("Invalid option `%s'", argv[i]); + } + else if (argv[i][0] == '+') + error ("Invalid option `%s'", argv[i]); + else + filename = argv[i]; + } + + if (optimize == 0) + { + /* Inlining does not work if not optimizing, + so force it not to be done. */ + flag_no_inline = 1; + warn_inline = 0; + + /* The c_decode_option and lang_decode_option functions set + this to `2' if -Wall is used, so we can avoid giving out + lots of errors for people who don't realize what -Wall does. */ + if (warn_uninitialized == 1) + warning ("-Wuninitialized is not supported without -O"); + } + +#if defined(DWARF_DEBUGGING_INFO) + if (write_symbols == DWARF_DEBUG + && strcmp (language_string, "GNU C++") == 0) + { + warning ("-g option not supported for C++ on SVR4 systems"); + write_symbols = NO_DEBUG; + } +#endif /* defined(DWARF_DEBUGGING_INFO) */ + +#ifdef OVERRIDE_OPTIONS + /* Some machines may reject certain combinations of options. */ + OVERRIDE_OPTIONS; +#endif + + /* Unrolling all loops implies that standard loop unrolling must also + be done. */ + if (flag_unroll_all_loops) + flag_unroll_loops = 1; + /* Loop unrolling requires that strength_reduction be on also. Silently + turn on strength reduction here if it isn't already on. Also, the loop + unrolling code assumes that cse will be run after loop, so that must + be turned on also. */ + if (flag_unroll_loops) + { + flag_strength_reduce = 1; + flag_rerun_cse_after_loop = 1; + } + + /* Warn about options that are not supported on this machine. */ +#ifndef INSN_SCHEDULING + if (flag_schedule_insns || flag_schedule_insns_after_reload) + warning ("instruction scheduling not supported on this target machine"); +#endif +#ifndef DELAY_SLOTS + if (flag_delayed_branch) + warning ("this target machine does not have delayed branches"); +#endif + + /* If we are in verbose mode, write out the version and maybe all the + option flags in use. */ + if (version_flag) + { + fprintf (stderr, "%s version %s", language_string, version_string); +#ifdef TARGET_VERSION + TARGET_VERSION; +#endif +#ifdef __GNUC__ +#ifndef __VERSION__ +#define __VERSION__ "[unknown]" +#endif + fprintf (stderr, " compiled by GNU C version %s.\n", __VERSION__); +#else + fprintf (stderr, " compiled by CC.\n"); +#endif + if (! quiet_flag) + print_switch_values (); + } + + /* Now that register usage is specified, convert it to HARD_REG_SETs. */ + init_reg_sets_1 (); + + compile_file (filename); + +#ifndef OS2 +#ifndef VMS + if (flag_print_mem) + { + char *lim = (char *) sbrk (0); + + fprintf (stderr, "Data size %d.\n", + lim - (char *) &environ); + fflush (stderr); + +#ifdef USG + system ("ps -l 1>&2"); +#else /* not USG */ + system ("ps v"); +#endif /* not USG */ + } +#endif /* not VMS */ +#endif /* not OS2 */ + + if (errorcount) + exit (FATAL_EXIT_CODE); + if (sorrycount) + exit (FATAL_EXIT_CODE); + exit (SUCCESS_EXIT_CODE); + return 34; +} + +/* Decode -m switches. */ + +/* Here is a table, controlled by the tm.h file, listing each -m switch + and which bits in `target_switches' it should set or clear. + If VALUE is positive, it is bits to set. + If VALUE is negative, -VALUE is bits to clear. + (The sign bit is not used so there is no confusion.) */ + +struct {char *name; int value;} target_switches [] + = TARGET_SWITCHES; + +/* This table is similar, but allows the switch to have a value. */ + +#ifdef TARGET_OPTIONS +struct {char *prefix; char ** variable;} target_options [] + = TARGET_OPTIONS; +#endif + +/* Decode the switch -mNAME. */ + +void +set_target_switch (name) + char *name; +{ + register int j; + int valid = 0; + + for (j = 0; j < sizeof target_switches / sizeof target_switches[0]; j++) + if (!strcmp (target_switches[j].name, name)) + { + if (target_switches[j].value < 0) + target_flags &= ~-target_switches[j].value; + else + target_flags |= target_switches[j].value; + valid = 1; + } + +#ifdef TARGET_OPTIONS + if (!valid) + for (j = 0; j < sizeof target_options / sizeof target_options[0]; j++) + { + int len = strlen (target_options[j].prefix); + if (!strncmp (target_options[j].prefix, name, len)) + { + *target_options[j].variable = name + len; + valid = 1; + } + } +#endif + + if (!valid) + error ("Invalid option `%s'", name); +} + +/* Variable used for communication between the following two routines. */ + +static int line_position; + +/* Print an option value and adjust the position in the line. */ + +static void +print_single_switch (type, name) + char *type, *name; +{ + fprintf (stderr, " %s%s", type, name); + + line_position += strlen (type) + strlen (name) + 1; + + if (line_position > 65) + { + fprintf (stderr, "\n\t"); + line_position = 8; + } +} + +/* Print default target switches for -version. */ + +static void +print_switch_values () +{ + register int j; + + fprintf (stderr, "enabled:"); + line_position = 8; + + for (j = 0; j < sizeof f_options / sizeof f_options[0]; j++) + if (*f_options[j].variable == f_options[j].on_value) + print_single_switch ("-f", f_options[j].string); + + for (j = 0; j < sizeof W_options / sizeof W_options[0]; j++) + if (*W_options[j].variable == W_options[j].on_value) + print_single_switch ("-W", W_options[j].string); + + for (j = 0; j < sizeof target_switches / sizeof target_switches[0]; j++) + if (target_switches[j].name[0] != '\0' + && target_switches[j].value > 0 + && ((target_switches[j].value & target_flags) + == target_switches[j].value)) + print_single_switch ("-m", target_switches[j].name); + + fprintf (stderr, "\n"); +} diff --git a/gnu/usr.bin/cc/lib/tree.c b/gnu/usr.bin/cc/lib/tree.c new file mode 100644 index 000000000000..96a399f92d14 --- /dev/null +++ b/gnu/usr.bin/cc/lib/tree.c @@ -0,0 +1,3341 @@ +/* Language-independent node constructors for parse phase of GNU compiler. + Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This file contains the low level primitives for operating on tree nodes, + including allocation, list operations, interning of identifiers, + construction of data type nodes and statement nodes, + and construction of type conversion nodes. It also contains + tables index by tree code that describe how to take apart + nodes of that code. + + It is intended to be language-independent, but occasionally + calls language-dependent routines defined (for C) in typecheck.c. + + The low-level allocation routines oballoc and permalloc + are used also for allocating many other kinds of objects + by all passes of the compiler. */ + +#include "config.h" +#include "flags.h" +#include "tree.h" +#include "function.h" +#include "obstack.h" +#include "gvarargs.h" +#include + +#define obstack_chunk_alloc xmalloc +#define obstack_chunk_free free + +/* Tree nodes of permanent duration are allocated in this obstack. + They are the identifier nodes, and everything outside of + the bodies and parameters of function definitions. */ + +struct obstack permanent_obstack; + +/* The initial RTL, and all ..._TYPE nodes, in a function + are allocated in this obstack. Usually they are freed at the + end of the function, but if the function is inline they are saved. + For top-level functions, this is maybepermanent_obstack. + Separate obstacks are made for nested functions. */ + +struct obstack *function_maybepermanent_obstack; + +/* This is the function_maybepermanent_obstack for top-level functions. */ + +struct obstack maybepermanent_obstack; + +/* The contents of the current function definition are allocated + in this obstack, and all are freed at the end of the function. + For top-level functions, this is temporary_obstack. + Separate obstacks are made for nested functions. */ + +struct obstack *function_obstack; + +/* This is used for reading initializers of global variables. */ + +struct obstack temporary_obstack; + +/* The tree nodes of an expression are allocated + in this obstack, and all are freed at the end of the expression. */ + +struct obstack momentary_obstack; + +/* The tree nodes of a declarator are allocated + in this obstack, and all are freed when the declarator + has been parsed. */ + +static struct obstack temp_decl_obstack; + +/* This points at either permanent_obstack + or the current function_maybepermanent_obstack. */ + +struct obstack *saveable_obstack; + +/* This is same as saveable_obstack during parse and expansion phase; + it points to the current function's obstack during optimization. + This is the obstack to be used for creating rtl objects. */ + +struct obstack *rtl_obstack; + +/* This points at either permanent_obstack or the current function_obstack. */ + +struct obstack *current_obstack; + +/* This points at either permanent_obstack or the current function_obstack + or momentary_obstack. */ + +struct obstack *expression_obstack; + +/* Stack of obstack selections for push_obstacks and pop_obstacks. */ + +struct obstack_stack +{ + struct obstack_stack *next; + struct obstack *current; + struct obstack *saveable; + struct obstack *expression; + struct obstack *rtl; +}; + +struct obstack_stack *obstack_stack; + +/* Obstack for allocating struct obstack_stack entries. */ + +static struct obstack obstack_stack_obstack; + +/* Addresses of first objects in some obstacks. + This is for freeing their entire contents. */ +char *maybepermanent_firstobj; +char *temporary_firstobj; +char *momentary_firstobj; +char *temp_decl_firstobj; + +/* Nonzero means all ..._TYPE nodes should be allocated permanently. */ + +int all_types_permanent; + +/* Stack of places to restore the momentary obstack back to. */ + +struct momentary_level +{ + /* Pointer back to previous such level. */ + struct momentary_level *prev; + /* First object allocated within this level. */ + char *base; + /* Value of expression_obstack saved at entry to this level. */ + struct obstack *obstack; +}; + +struct momentary_level *momentary_stack; + +/* Table indexed by tree code giving a string containing a character + classifying the tree code. Possibilities are + t, d, s, c, r, <, 1, 2 and e. See tree.def for details. */ + +#define DEFTREECODE(SYM, NAME, TYPE, LENGTH) TYPE, + +char *standard_tree_code_type[] = { +#include "tree.def" +}; +#undef DEFTREECODE + +/* Table indexed by tree code giving number of expression + operands beyond the fixed part of the node structure. + Not used for types or decls. */ + +#define DEFTREECODE(SYM, NAME, TYPE, LENGTH) LENGTH, + +int standard_tree_code_length[] = { +#include "tree.def" +}; +#undef DEFTREECODE + +/* Names of tree components. + Used for printing out the tree and error messages. */ +#define DEFTREECODE(SYM, NAME, TYPE, LEN) NAME, + +char *standard_tree_code_name[] = { +#include "tree.def" +}; +#undef DEFTREECODE + +/* Table indexed by tree code giving a string containing a character + classifying the tree code. Possibilities are + t, d, s, c, r, e, <, 1 and 2. See tree.def for details. */ + +char **tree_code_type; + +/* Table indexed by tree code giving number of expression + operands beyond the fixed part of the node structure. + Not used for types or decls. */ + +int *tree_code_length; + +/* Table indexed by tree code giving name of tree code, as a string. */ + +char **tree_code_name; + +/* Statistics-gathering stuff. */ +typedef enum +{ + d_kind, + t_kind, + b_kind, + s_kind, + r_kind, + e_kind, + c_kind, + id_kind, + op_id_kind, + perm_list_kind, + temp_list_kind, + vec_kind, + x_kind, + lang_decl, + lang_type, + all_kinds +} tree_node_kind; + +int tree_node_counts[(int)all_kinds]; +int tree_node_sizes[(int)all_kinds]; +int id_string_size = 0; + +char *tree_node_kind_names[] = { + "decls", + "types", + "blocks", + "stmts", + "refs", + "exprs", + "constants", + "identifiers", + "op_identifiers", + "perm_tree_lists", + "temp_tree_lists", + "vecs", + "random kinds", + "lang_decl kinds", + "lang_type kinds" +}; + +/* Hash table for uniquizing IDENTIFIER_NODEs by name. */ + +#define MAX_HASH_TABLE 1009 +static tree hash_table[MAX_HASH_TABLE]; /* id hash buckets */ + +/* 0 while creating built-in identifiers. */ +static int do_identifier_warnings; + +/* Unique id for next decl created. */ +static int next_decl_uid; +/* Unique id for next type created. */ +static int next_type_uid = 1; + +extern char *mode_name[]; + +void gcc_obstack_init (); +static tree stabilize_reference_1 (); + +/* Init the principal obstacks. */ + +void +init_obstacks () +{ + gcc_obstack_init (&obstack_stack_obstack); + gcc_obstack_init (&permanent_obstack); + + gcc_obstack_init (&temporary_obstack); + temporary_firstobj = (char *) obstack_alloc (&temporary_obstack, 0); + gcc_obstack_init (&momentary_obstack); + momentary_firstobj = (char *) obstack_alloc (&momentary_obstack, 0); + gcc_obstack_init (&maybepermanent_obstack); + maybepermanent_firstobj + = (char *) obstack_alloc (&maybepermanent_obstack, 0); + gcc_obstack_init (&temp_decl_obstack); + temp_decl_firstobj = (char *) obstack_alloc (&temp_decl_obstack, 0); + + function_obstack = &temporary_obstack; + function_maybepermanent_obstack = &maybepermanent_obstack; + current_obstack = &permanent_obstack; + expression_obstack = &permanent_obstack; + rtl_obstack = saveable_obstack = &permanent_obstack; + + /* Init the hash table of identifiers. */ + bzero (hash_table, sizeof hash_table); +} + +void +gcc_obstack_init (obstack) + struct obstack *obstack; +{ + /* Let particular systems override the size of a chunk. */ +#ifndef OBSTACK_CHUNK_SIZE +#define OBSTACK_CHUNK_SIZE 0 +#endif + /* Let them override the alloc and free routines too. */ +#ifndef OBSTACK_CHUNK_ALLOC +#define OBSTACK_CHUNK_ALLOC xmalloc +#endif +#ifndef OBSTACK_CHUNK_FREE +#define OBSTACK_CHUNK_FREE free +#endif + _obstack_begin (obstack, OBSTACK_CHUNK_SIZE, 0, + (void *(*) ()) OBSTACK_CHUNK_ALLOC, + (void (*) ()) OBSTACK_CHUNK_FREE); +} + +/* Save all variables describing the current status into the structure *P. + This is used before starting a nested function. */ + +void +save_tree_status (p) + struct function *p; +{ + p->all_types_permanent = all_types_permanent; + p->momentary_stack = momentary_stack; + p->maybepermanent_firstobj = maybepermanent_firstobj; + p->momentary_firstobj = momentary_firstobj; + p->function_obstack = function_obstack; + p->function_maybepermanent_obstack = function_maybepermanent_obstack; + p->current_obstack = current_obstack; + p->expression_obstack = expression_obstack; + p->saveable_obstack = saveable_obstack; + p->rtl_obstack = rtl_obstack; + + function_obstack = (struct obstack *) xmalloc (sizeof (struct obstack)); + gcc_obstack_init (function_obstack); + + function_maybepermanent_obstack + = (struct obstack *) xmalloc (sizeof (struct obstack)); + gcc_obstack_init (function_maybepermanent_obstack); + + current_obstack = &permanent_obstack; + expression_obstack = &permanent_obstack; + rtl_obstack = saveable_obstack = &permanent_obstack; + + momentary_firstobj = (char *) obstack_finish (&momentary_obstack); + maybepermanent_firstobj + = (char *) obstack_finish (function_maybepermanent_obstack); +} + +/* Restore all variables describing the current status from the structure *P. + This is used after a nested function. */ + +void +restore_tree_status (p) + struct function *p; +{ + all_types_permanent = p->all_types_permanent; + momentary_stack = p->momentary_stack; + + obstack_free (&momentary_obstack, momentary_firstobj); + obstack_free (function_obstack, 0); + obstack_free (function_maybepermanent_obstack, 0); + free (function_obstack); + + momentary_firstobj = p->momentary_firstobj; + maybepermanent_firstobj = p->maybepermanent_firstobj; + function_obstack = p->function_obstack; + function_maybepermanent_obstack = p->function_maybepermanent_obstack; + current_obstack = p->current_obstack; + expression_obstack = p->expression_obstack; + saveable_obstack = p->saveable_obstack; + rtl_obstack = p->rtl_obstack; +} + +/* Start allocating on the temporary (per function) obstack. + This is done in start_function before parsing the function body, + and before each initialization at top level, and to go back + to temporary allocation after doing end_temporary_allocation. */ + +void +temporary_allocation () +{ + /* Note that function_obstack at top level points to temporary_obstack. + But within a nested function context, it is a separate obstack. */ + current_obstack = function_obstack; + expression_obstack = function_obstack; + rtl_obstack = saveable_obstack = function_maybepermanent_obstack; + momentary_stack = 0; +} + +/* Start allocating on the permanent obstack but don't + free the temporary data. After calling this, call + `permanent_allocation' to fully resume permanent allocation status. */ + +void +end_temporary_allocation () +{ + current_obstack = &permanent_obstack; + expression_obstack = &permanent_obstack; + rtl_obstack = saveable_obstack = &permanent_obstack; +} + +/* Resume allocating on the temporary obstack, undoing + effects of `end_temporary_allocation'. */ + +void +resume_temporary_allocation () +{ + current_obstack = function_obstack; + expression_obstack = function_obstack; + rtl_obstack = saveable_obstack = function_maybepermanent_obstack; +} + +/* While doing temporary allocation, switch to allocating in such a + way as to save all nodes if the function is inlined. Call + resume_temporary_allocation to go back to ordinary temporary + allocation. */ + +void +saveable_allocation () +{ + /* Note that function_obstack at top level points to temporary_obstack. + But within a nested function context, it is a separate obstack. */ + expression_obstack = current_obstack = saveable_obstack; +} + +/* Switch to current obstack CURRENT and maybepermanent obstack SAVEABLE, + recording the previously current obstacks on a stack. + This does not free any storage in any obstack. */ + +void +push_obstacks (current, saveable) + struct obstack *current, *saveable; +{ + struct obstack_stack *p + = (struct obstack_stack *) obstack_alloc (&obstack_stack_obstack, + (sizeof (struct obstack_stack))); + + p->current = current_obstack; + p->saveable = saveable_obstack; + p->expression = expression_obstack; + p->rtl = rtl_obstack; + p->next = obstack_stack; + obstack_stack = p; + + current_obstack = current; + expression_obstack = current; + rtl_obstack = saveable_obstack = saveable; +} + +/* Save the current set of obstacks, but don't change them. */ + +void +push_obstacks_nochange () +{ + struct obstack_stack *p + = (struct obstack_stack *) obstack_alloc (&obstack_stack_obstack, + (sizeof (struct obstack_stack))); + + p->current = current_obstack; + p->saveable = saveable_obstack; + p->expression = expression_obstack; + p->rtl = rtl_obstack; + p->next = obstack_stack; + obstack_stack = p; +} + +/* Pop the obstack selection stack. */ + +void +pop_obstacks () +{ + struct obstack_stack *p = obstack_stack; + obstack_stack = p->next; + + current_obstack = p->current; + saveable_obstack = p->saveable; + expression_obstack = p->expression; + rtl_obstack = p->rtl; + + obstack_free (&obstack_stack_obstack, p); +} + +/* Nonzero if temporary allocation is currently in effect. + Zero if currently doing permanent allocation. */ + +int +allocation_temporary_p () +{ + return current_obstack != &permanent_obstack; +} + +/* Go back to allocating on the permanent obstack + and free everything in the temporary obstack. + This is done in finish_function after fully compiling a function. */ + +void +permanent_allocation () +{ + /* Free up previous temporary obstack data */ + obstack_free (&temporary_obstack, temporary_firstobj); + obstack_free (&momentary_obstack, momentary_firstobj); + obstack_free (&maybepermanent_obstack, maybepermanent_firstobj); + obstack_free (&temp_decl_obstack, temp_decl_firstobj); + + current_obstack = &permanent_obstack; + expression_obstack = &permanent_obstack; + rtl_obstack = saveable_obstack = &permanent_obstack; +} + +/* Save permanently everything on the maybepermanent_obstack. */ + +void +preserve_data () +{ + maybepermanent_firstobj + = (char *) obstack_alloc (function_maybepermanent_obstack, 0); +} + +void +preserve_initializer () +{ + temporary_firstobj + = (char *) obstack_alloc (&temporary_obstack, 0); + momentary_firstobj + = (char *) obstack_alloc (&momentary_obstack, 0); + maybepermanent_firstobj + = (char *) obstack_alloc (function_maybepermanent_obstack, 0); +} + +/* Start allocating new rtl in current_obstack. + Use resume_temporary_allocation + to go back to allocating rtl in saveable_obstack. */ + +void +rtl_in_current_obstack () +{ + rtl_obstack = current_obstack; +} + +/* Start allocating rtl from saveable_obstack. Intended to be used after + a call to push_obstacks_nochange. */ + +void +rtl_in_saveable_obstack () +{ + rtl_obstack = saveable_obstack; +} + +/* Allocate SIZE bytes in the current obstack + and return a pointer to them. + In practice the current obstack is always the temporary one. */ + +char * +oballoc (size) + int size; +{ + return (char *) obstack_alloc (current_obstack, size); +} + +/* Free the object PTR in the current obstack + as well as everything allocated since PTR. + In practice the current obstack is always the temporary one. */ + +void +obfree (ptr) + char *ptr; +{ + obstack_free (current_obstack, ptr); +} + +/* Allocate SIZE bytes in the permanent obstack + and return a pointer to them. */ + +char * +permalloc (size) + int size; +{ + return (char *) obstack_alloc (&permanent_obstack, size); +} + +/* Allocate NELEM items of SIZE bytes in the permanent obstack + and return a pointer to them. The storage is cleared before + returning the value. */ + +char * +perm_calloc (nelem, size) + int nelem; + long size; +{ + char *rval = (char *) obstack_alloc (&permanent_obstack, nelem * size); + bzero (rval, nelem * size); + return rval; +} + +/* Allocate SIZE bytes in the saveable obstack + and return a pointer to them. */ + +char * +savealloc (size) + int size; +{ + return (char *) obstack_alloc (saveable_obstack, size); +} + +/* Print out which obstack an object is in. */ + +void +debug_obstack (object) + char *object; +{ + struct obstack *obstack = NULL; + char *obstack_name = NULL; + struct function *p; + + for (p = outer_function_chain; p; p = p->next) + { + if (_obstack_allocated_p (p->function_obstack, object)) + { + obstack = p->function_obstack; + obstack_name = "containing function obstack"; + } + if (_obstack_allocated_p (p->function_maybepermanent_obstack, object)) + { + obstack = p->function_maybepermanent_obstack; + obstack_name = "containing function maybepermanent obstack"; + } + } + + if (_obstack_allocated_p (&obstack_stack_obstack, object)) + { + obstack = &obstack_stack_obstack; + obstack_name = "obstack_stack_obstack"; + } + else if (_obstack_allocated_p (function_obstack, object)) + { + obstack = function_obstack; + obstack_name = "function obstack"; + } + else if (_obstack_allocated_p (&permanent_obstack, object)) + { + obstack = &permanent_obstack; + obstack_name = "permanent_obstack"; + } + else if (_obstack_allocated_p (&momentary_obstack, object)) + { + obstack = &momentary_obstack; + obstack_name = "momentary_obstack"; + } + else if (_obstack_allocated_p (function_maybepermanent_obstack, object)) + { + obstack = function_maybepermanent_obstack; + obstack_name = "function maybepermanent obstack"; + } + else if (_obstack_allocated_p (&temp_decl_obstack, object)) + { + obstack = &temp_decl_obstack; + obstack_name = "temp_decl_obstack"; + } + + /* Check to see if the object is in the free area of the obstack. */ + if (obstack != NULL) + { + if (object >= obstack->next_free + && object < obstack->chunk_limit) + fprintf (stderr, "object in free portion of obstack %s.\n", + obstack_name); + else + fprintf (stderr, "object allocated from %s.\n", obstack_name); + } + else + fprintf (stderr, "object not allocated from any obstack.\n"); +} + +/* Return 1 if OBJ is in the permanent obstack. + This is slow, and should be used only for debugging. + Use TREE_PERMANENT for other purposes. */ + +int +object_permanent_p (obj) + tree obj; +{ + return _obstack_allocated_p (&permanent_obstack, obj); +} + +/* Start a level of momentary allocation. + In C, each compound statement has its own level + and that level is freed at the end of each statement. + All expression nodes are allocated in the momentary allocation level. */ + +void +push_momentary () +{ + struct momentary_level *tem + = (struct momentary_level *) obstack_alloc (&momentary_obstack, + sizeof (struct momentary_level)); + tem->prev = momentary_stack; + tem->base = (char *) obstack_base (&momentary_obstack); + tem->obstack = expression_obstack; + momentary_stack = tem; + expression_obstack = &momentary_obstack; +} + +/* Free all the storage in the current momentary-allocation level. + In C, this happens at the end of each statement. */ + +void +clear_momentary () +{ + obstack_free (&momentary_obstack, momentary_stack->base); +} + +/* Discard a level of momentary allocation. + In C, this happens at the end of each compound statement. + Restore the status of expression node allocation + that was in effect before this level was created. */ + +void +pop_momentary () +{ + struct momentary_level *tem = momentary_stack; + momentary_stack = tem->prev; + expression_obstack = tem->obstack; + obstack_free (&momentary_obstack, tem); +} + +/* Call when starting to parse a declaration: + make expressions in the declaration last the length of the function. + Returns an argument that should be passed to resume_momentary later. */ + +int +suspend_momentary () +{ + register int tem = expression_obstack == &momentary_obstack; + expression_obstack = saveable_obstack; + return tem; +} + +/* Call when finished parsing a declaration: + restore the treatment of node-allocation that was + in effect before the suspension. + YES should be the value previously returned by suspend_momentary. */ + +void +resume_momentary (yes) + int yes; +{ + if (yes) + expression_obstack = &momentary_obstack; +} + +/* Init the tables indexed by tree code. + Note that languages can add to these tables to define their own codes. */ + +void +init_tree_codes () +{ + tree_code_type = (char **) xmalloc (sizeof (standard_tree_code_type)); + tree_code_length = (int *) xmalloc (sizeof (standard_tree_code_length)); + tree_code_name = (char **) xmalloc (sizeof (standard_tree_code_name)); + bcopy (standard_tree_code_type, tree_code_type, + sizeof (standard_tree_code_type)); + bcopy (standard_tree_code_length, tree_code_length, + sizeof (standard_tree_code_length)); + bcopy (standard_tree_code_name, tree_code_name, + sizeof (standard_tree_code_name)); +} + +/* Return a newly allocated node of code CODE. + Initialize the node's unique id and its TREE_PERMANENT flag. + For decl and type nodes, some other fields are initialized. + The rest of the node is initialized to zero. + + Achoo! I got a code in the node. */ + +tree +make_node (code) + enum tree_code code; +{ + register tree t; + register int type = TREE_CODE_CLASS (code); + register int length; + register struct obstack *obstack = current_obstack; + register int i; + register tree_node_kind kind; + + switch (type) + { + case 'd': /* A decl node */ +#ifdef GATHER_STATISTICS + kind = d_kind; +#endif + length = sizeof (struct tree_decl); + /* All decls in an inline function need to be saved. */ + if (obstack != &permanent_obstack) + obstack = saveable_obstack; + /* PARM_DECLs always go on saveable_obstack, not permanent, + even though we may make them before the function turns + on temporary allocation. */ + else if (code == PARM_DECL) + obstack = function_maybepermanent_obstack; + break; + + case 't': /* a type node */ +#ifdef GATHER_STATISTICS + kind = t_kind; +#endif + length = sizeof (struct tree_type); + /* All data types are put where we can preserve them if nec. */ + if (obstack != &permanent_obstack) + obstack = all_types_permanent ? &permanent_obstack : saveable_obstack; + break; + + case 'b': /* a lexical block */ +#ifdef GATHER_STATISTICS + kind = b_kind; +#endif + length = sizeof (struct tree_block); + /* All BLOCK nodes are put where we can preserve them if nec. */ + if (obstack != &permanent_obstack) + obstack = saveable_obstack; + break; + + case 's': /* an expression with side effects */ +#ifdef GATHER_STATISTICS + kind = s_kind; + goto usual_kind; +#endif + case 'r': /* a reference */ +#ifdef GATHER_STATISTICS + kind = r_kind; + goto usual_kind; +#endif + case 'e': /* an expression */ + case '<': /* a comparison expression */ + case '1': /* a unary arithmetic expression */ + case '2': /* a binary arithmetic expression */ +#ifdef GATHER_STATISTICS + kind = e_kind; + usual_kind: +#endif + obstack = expression_obstack; + /* All BIND_EXPR nodes are put where we can preserve them if nec. */ + if (code == BIND_EXPR && obstack != &permanent_obstack) + obstack = saveable_obstack; + length = sizeof (struct tree_exp) + + (tree_code_length[(int) code] - 1) * sizeof (char *); + break; + + case 'c': /* a constant */ +#ifdef GATHER_STATISTICS + kind = c_kind; +#endif + obstack = expression_obstack; + + /* We can't use tree_code_length for INTEGER_CST, since the number of + words is machine-dependent due to varying length of HOST_WIDE_INT, + which might be wider than a pointer (e.g., long long). Similarly + for REAL_CST, since the number of words is machine-dependent due + to varying size and alignment of `double'. */ + + if (code == INTEGER_CST) + length = sizeof (struct tree_int_cst); + else if (code == REAL_CST) + length = sizeof (struct tree_real_cst); + else + length = sizeof (struct tree_common) + + tree_code_length[(int) code] * sizeof (char *); + break; + + case 'x': /* something random, like an identifier. */ +#ifdef GATHER_STATISTICS + if (code == IDENTIFIER_NODE) + kind = id_kind; + else if (code == OP_IDENTIFIER) + kind = op_id_kind; + else if (code == TREE_VEC) + kind = vec_kind; + else + kind = x_kind; +#endif + length = sizeof (struct tree_common) + + tree_code_length[(int) code] * sizeof (char *); + /* Identifier nodes are always permanent since they are + unique in a compiler run. */ + if (code == IDENTIFIER_NODE) obstack = &permanent_obstack; + } + + t = (tree) obstack_alloc (obstack, length); + +#ifdef GATHER_STATISTICS + tree_node_counts[(int)kind]++; + tree_node_sizes[(int)kind] += length; +#endif + + /* Clear a word at a time. */ + for (i = (length / sizeof (int)) - 1; i >= 0; i--) + ((int *) t)[i] = 0; + /* Clear any extra bytes. */ + for (i = length / sizeof (int) * sizeof (int); i < length; i++) + ((char *) t)[i] = 0; + + TREE_SET_CODE (t, code); + if (obstack == &permanent_obstack) + TREE_PERMANENT (t) = 1; + + switch (type) + { + case 's': + TREE_SIDE_EFFECTS (t) = 1; + TREE_TYPE (t) = void_type_node; + break; + + case 'd': + if (code != FUNCTION_DECL) + DECL_ALIGN (t) = 1; + DECL_IN_SYSTEM_HEADER (t) + = in_system_header && (obstack == &permanent_obstack); + DECL_SOURCE_LINE (t) = lineno; + DECL_SOURCE_FILE (t) = (input_filename) ? input_filename : ""; + DECL_UID (t) = next_decl_uid++; + break; + + case 't': + TYPE_UID (t) = next_type_uid++; + TYPE_ALIGN (t) = 1; + TYPE_MAIN_VARIANT (t) = t; + break; + + case 'c': + TREE_CONSTANT (t) = 1; + break; + } + + return t; +} + +/* Return a new node with the same contents as NODE + except that its TREE_CHAIN is zero and it has a fresh uid. */ + +tree +copy_node (node) + tree node; +{ + register tree t; + register enum tree_code code = TREE_CODE (node); + register int length; + register int i; + + switch (TREE_CODE_CLASS (code)) + { + case 'd': /* A decl node */ + length = sizeof (struct tree_decl); + break; + + case 't': /* a type node */ + length = sizeof (struct tree_type); + break; + + case 'b': /* a lexical block node */ + length = sizeof (struct tree_block); + break; + + case 'r': /* a reference */ + case 'e': /* an expression */ + case 's': /* an expression with side effects */ + case '<': /* a comparison expression */ + case '1': /* a unary arithmetic expression */ + case '2': /* a binary arithmetic expression */ + length = sizeof (struct tree_exp) + + (tree_code_length[(int) code] - 1) * sizeof (char *); + break; + + case 'c': /* a constant */ + /* We can't use tree_code_length for this, since the number of words + is machine-dependent due to varying alignment of `double'. */ + if (code == REAL_CST) + { + length = sizeof (struct tree_real_cst); + break; + } + + case 'x': /* something random, like an identifier. */ + length = sizeof (struct tree_common) + + tree_code_length[(int) code] * sizeof (char *); + if (code == TREE_VEC) + length += (TREE_VEC_LENGTH (node) - 1) * sizeof (char *); + } + + t = (tree) obstack_alloc (current_obstack, length); + + for (i = (length / sizeof (int)) - 1; i >= 0; i--) + ((int *) t)[i] = ((int *) node)[i]; + /* Clear any extra bytes. */ + for (i = length / sizeof (int) * sizeof (int); i < length; i++) + ((char *) t)[i] = ((char *) node)[i]; + + TREE_CHAIN (t) = 0; + + if (TREE_CODE_CLASS (code) == 'd') + DECL_UID (t) = next_decl_uid++; + else if (TREE_CODE_CLASS (code) == 't') + TYPE_UID (t) = next_type_uid++; + + TREE_PERMANENT (t) = (current_obstack == &permanent_obstack); + + return t; +} + +/* Return a copy of a chain of nodes, chained through the TREE_CHAIN field. + For example, this can copy a list made of TREE_LIST nodes. */ + +tree +copy_list (list) + tree list; +{ + tree head; + register tree prev, next; + + if (list == 0) + return 0; + + head = prev = copy_node (list); + next = TREE_CHAIN (list); + while (next) + { + TREE_CHAIN (prev) = copy_node (next); + prev = TREE_CHAIN (prev); + next = TREE_CHAIN (next); + } + return head; +} + +#define HASHBITS 30 + +/* Return an IDENTIFIER_NODE whose name is TEXT (a null-terminated string). + If an identifier with that name has previously been referred to, + the same node is returned this time. */ + +tree +get_identifier (text) + register char *text; +{ + register int hi; + register int i; + register tree idp; + register int len, hash_len; + + /* Compute length of text in len. */ + for (len = 0; text[len]; len++); + + /* Decide how much of that length to hash on */ + hash_len = len; + if (warn_id_clash && len > id_clash_len) + hash_len = id_clash_len; + + /* Compute hash code */ + hi = hash_len * 613 + (unsigned)text[0]; + for (i = 1; i < hash_len; i += 2) + hi = ((hi * 613) + (unsigned)(text[i])); + + hi &= (1 << HASHBITS) - 1; + hi %= MAX_HASH_TABLE; + + /* Search table for identifier */ + for (idp = hash_table[hi]; idp; idp = TREE_CHAIN (idp)) + if (IDENTIFIER_LENGTH (idp) == len + && IDENTIFIER_POINTER (idp)[0] == text[0] + && !bcmp (IDENTIFIER_POINTER (idp), text, len)) + return idp; /* <-- return if found */ + + /* Not found; optionally warn about a similar identifier */ + if (warn_id_clash && do_identifier_warnings && len >= id_clash_len) + for (idp = hash_table[hi]; idp; idp = TREE_CHAIN (idp)) + if (!strncmp (IDENTIFIER_POINTER (idp), text, id_clash_len)) + { + warning ("`%s' and `%s' identical in first %d characters", + IDENTIFIER_POINTER (idp), text, id_clash_len); + break; + } + + if (tree_code_length[(int) IDENTIFIER_NODE] < 0) + abort (); /* set_identifier_size hasn't been called. */ + + /* Not found, create one, add to chain */ + idp = make_node (IDENTIFIER_NODE); + IDENTIFIER_LENGTH (idp) = len; +#ifdef GATHER_STATISTICS + id_string_size += len; +#endif + + IDENTIFIER_POINTER (idp) = obstack_copy0 (&permanent_obstack, text, len); + + TREE_CHAIN (idp) = hash_table[hi]; + hash_table[hi] = idp; + return idp; /* <-- return if created */ +} + +/* Enable warnings on similar identifiers (if requested). + Done after the built-in identifiers are created. */ + +void +start_identifier_warnings () +{ + do_identifier_warnings = 1; +} + +/* Record the size of an identifier node for the language in use. + SIZE is the total size in bytes. + This is called by the language-specific files. This must be + called before allocating any identifiers. */ + +void +set_identifier_size (size) + int size; +{ + tree_code_length[(int) IDENTIFIER_NODE] + = (size - sizeof (struct tree_common)) / sizeof (tree); +} + +/* Return a newly constructed INTEGER_CST node whose constant value + is specified by the two ints LOW and HI. + The TREE_TYPE is set to `int'. + + This function should be used via the `build_int_2' macro. */ + +tree +build_int_2_wide (low, hi) + HOST_WIDE_INT low, hi; +{ + register tree t = make_node (INTEGER_CST); + TREE_INT_CST_LOW (t) = low; + TREE_INT_CST_HIGH (t) = hi; + TREE_TYPE (t) = integer_type_node; + return t; +} + +/* Return a new REAL_CST node whose type is TYPE and value is D. */ + +tree +build_real (type, d) + tree type; + REAL_VALUE_TYPE d; +{ + tree v; + + /* Check for valid float value for this type on this target machine; + if not, can print error message and store a valid value in D. */ +#ifdef CHECK_FLOAT_VALUE + CHECK_FLOAT_VALUE (TYPE_MODE (type), d); +#endif + + v = make_node (REAL_CST); + TREE_TYPE (v) = type; + TREE_REAL_CST (v) = d; + return v; +} + +/* Return a new REAL_CST node whose type is TYPE + and whose value is the integer value of the INTEGER_CST node I. */ + +#if !defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + +REAL_VALUE_TYPE +real_value_from_int_cst (i) + tree i; +{ + REAL_VALUE_TYPE d; + REAL_VALUE_TYPE e; + /* Some 386 compilers mishandle unsigned int to float conversions, + so introduce a temporary variable E to avoid those bugs. */ + +#ifdef REAL_ARITHMETIC + if (! TREE_UNSIGNED (TREE_TYPE (i))) + REAL_VALUE_FROM_INT (d, TREE_INT_CST_LOW (i), TREE_INT_CST_HIGH (i)); + else + REAL_VALUE_FROM_UNSIGNED_INT (d, TREE_INT_CST_LOW (i), TREE_INT_CST_HIGH (i)); +#else /* not REAL_ARITHMETIC */ + if (TREE_INT_CST_HIGH (i) < 0 && ! TREE_UNSIGNED (TREE_TYPE (i))) + { + d = (double) (~ TREE_INT_CST_HIGH (i)); + e = ((double) ((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2)) + * (double) ((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2))); + d *= e; + e = (double) (unsigned HOST_WIDE_INT) (~ TREE_INT_CST_LOW (i)); + d += e; + d = (- d - 1.0); + } + else + { + d = (double) (unsigned HOST_WIDE_INT) TREE_INT_CST_HIGH (i); + e = ((double) ((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2)) + * (double) ((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT / 2))); + d *= e; + e = (double) (unsigned HOST_WIDE_INT) TREE_INT_CST_LOW (i); + d += e; + } +#endif /* not REAL_ARITHMETIC */ + return d; +} + +/* This function can't be implemented if we can't do arithmetic + on the float representation. */ + +tree +build_real_from_int_cst (type, i) + tree type; + tree i; +{ + tree v; + REAL_VALUE_TYPE d; + + v = make_node (REAL_CST); + TREE_TYPE (v) = type; + + d = REAL_VALUE_TRUNCATE (TYPE_MODE (type), real_value_from_int_cst (i)); + /* Check for valid float value for this type on this target machine; + if not, can print error message and store a valid value in D. */ +#ifdef CHECK_FLOAT_VALUE + CHECK_FLOAT_VALUE (TYPE_MODE (type), d); +#endif + + TREE_REAL_CST (v) = d; + return v; +} + +#endif /* not REAL_IS_NOT_DOUBLE, or REAL_ARITHMETIC */ + +/* Return a newly constructed STRING_CST node whose value is + the LEN characters at STR. + The TREE_TYPE is not initialized. */ + +tree +build_string (len, str) + int len; + char *str; +{ + register tree s = make_node (STRING_CST); + TREE_STRING_LENGTH (s) = len; + TREE_STRING_POINTER (s) = obstack_copy0 (saveable_obstack, str, len); + return s; +} + +/* Return a newly constructed COMPLEX_CST node whose value is + specified by the real and imaginary parts REAL and IMAG. + Both REAL and IMAG should be constant nodes. + The TREE_TYPE is not initialized. */ + +tree +build_complex (real, imag) + tree real, imag; +{ + register tree t = make_node (COMPLEX_CST); + TREE_REALPART (t) = real; + TREE_IMAGPART (t) = imag; + TREE_TYPE (t) = build_complex_type (TREE_TYPE (real)); + return t; +} + +/* Build a newly constructed TREE_VEC node of length LEN. */ +tree +make_tree_vec (len) + int len; +{ + register tree t; + register int length = (len-1) * sizeof (tree) + sizeof (struct tree_vec); + register struct obstack *obstack = current_obstack; + register int i; + +#ifdef GATHER_STATISTICS + tree_node_counts[(int)vec_kind]++; + tree_node_sizes[(int)vec_kind] += length; +#endif + + t = (tree) obstack_alloc (obstack, length); + + for (i = (length / sizeof (int)) - 1; i >= 0; i--) + ((int *) t)[i] = 0; + + TREE_SET_CODE (t, TREE_VEC); + TREE_VEC_LENGTH (t) = len; + if (obstack == &permanent_obstack) + TREE_PERMANENT (t) = 1; + + return t; +} + +/* Return 1 if EXPR is the integer constant zero. */ + +int +integer_zerop (expr) + tree expr; +{ + STRIP_NOPS (expr); + + return (TREE_CODE (expr) == INTEGER_CST + && TREE_INT_CST_LOW (expr) == 0 + && TREE_INT_CST_HIGH (expr) == 0); +} + +/* Return 1 if EXPR is the integer constant one. */ + +int +integer_onep (expr) + tree expr; +{ + STRIP_NOPS (expr); + + return (TREE_CODE (expr) == INTEGER_CST + && TREE_INT_CST_LOW (expr) == 1 + && TREE_INT_CST_HIGH (expr) == 0); +} + +/* Return 1 if EXPR is an integer containing all 1's + in as much precision as it contains. */ + +int +integer_all_onesp (expr) + tree expr; +{ + register int prec; + register int uns; + + STRIP_NOPS (expr); + + if (TREE_CODE (expr) != INTEGER_CST) + return 0; + + uns = TREE_UNSIGNED (TREE_TYPE (expr)); + if (!uns) + return TREE_INT_CST_LOW (expr) == -1 && TREE_INT_CST_HIGH (expr) == -1; + + prec = TYPE_PRECISION (TREE_TYPE (expr)); + if (prec >= HOST_BITS_PER_WIDE_INT) + { + int high_value, shift_amount; + + shift_amount = prec - HOST_BITS_PER_WIDE_INT; + + if (shift_amount > HOST_BITS_PER_WIDE_INT) + /* Can not handle precisions greater than twice the host int size. */ + abort (); + else if (shift_amount == HOST_BITS_PER_WIDE_INT) + /* Shifting by the host word size is undefined according to the ANSI + standard, so we must handle this as a special case. */ + high_value = -1; + else + high_value = ((HOST_WIDE_INT) 1 << shift_amount) - 1; + + return TREE_INT_CST_LOW (expr) == -1 + && TREE_INT_CST_HIGH (expr) == high_value; + } + else + return TREE_INT_CST_LOW (expr) == ((HOST_WIDE_INT) 1 << prec) - 1; +} + +/* Return 1 if EXPR is an integer constant that is a power of 2 (i.e., has only + one bit on). */ + +int +integer_pow2p (expr) + tree expr; +{ + HOST_WIDE_INT high, low; + + STRIP_NOPS (expr); + + if (TREE_CODE (expr) != INTEGER_CST) + return 0; + + high = TREE_INT_CST_HIGH (expr); + low = TREE_INT_CST_LOW (expr); + + if (high == 0 && low == 0) + return 0; + + return ((high == 0 && (low & (low - 1)) == 0) + || (low == 0 && (high & (high - 1)) == 0)); +} + +/* Return 1 if EXPR is the real constant zero. */ + +int +real_zerop (expr) + tree expr; +{ + STRIP_NOPS (expr); + + return (TREE_CODE (expr) == REAL_CST + && REAL_VALUES_EQUAL (TREE_REAL_CST (expr), dconst0)); +} + +/* Return 1 if EXPR is the real constant one. */ + +int +real_onep (expr) + tree expr; +{ + STRIP_NOPS (expr); + + return (TREE_CODE (expr) == REAL_CST + && REAL_VALUES_EQUAL (TREE_REAL_CST (expr), dconst1)); +} + +/* Return 1 if EXPR is the real constant two. */ + +int +real_twop (expr) + tree expr; +{ + STRIP_NOPS (expr); + + return (TREE_CODE (expr) == REAL_CST + && REAL_VALUES_EQUAL (TREE_REAL_CST (expr), dconst2)); +} + +/* Nonzero if EXP is a constant or a cast of a constant. */ + +int +really_constant_p (exp) + tree exp; +{ + /* This is not quite the same as STRIP_NOPS. It does more. */ + while (TREE_CODE (exp) == NOP_EXPR + || TREE_CODE (exp) == CONVERT_EXPR + || TREE_CODE (exp) == NON_LVALUE_EXPR) + exp = TREE_OPERAND (exp, 0); + return TREE_CONSTANT (exp); +} + +/* Return first list element whose TREE_VALUE is ELEM. + Return 0 if ELEM is not it LIST. */ + +tree +value_member (elem, list) + tree elem, list; +{ + while (list) + { + if (elem == TREE_VALUE (list)) + return list; + list = TREE_CHAIN (list); + } + return NULL_TREE; +} + +/* Return first list element whose TREE_PURPOSE is ELEM. + Return 0 if ELEM is not it LIST. */ + +tree +purpose_member (elem, list) + tree elem, list; +{ + while (list) + { + if (elem == TREE_PURPOSE (list)) + return list; + list = TREE_CHAIN (list); + } + return NULL_TREE; +} + +/* Return first list element whose BINFO_TYPE is ELEM. + Return 0 if ELEM is not it LIST. */ + +tree +binfo_member (elem, list) + tree elem, list; +{ + while (list) + { + if (elem == BINFO_TYPE (list)) + return list; + list = TREE_CHAIN (list); + } + return NULL_TREE; +} + +/* Return nonzero if ELEM is part of the chain CHAIN. */ + +int +chain_member (elem, chain) + tree elem, chain; +{ + while (chain) + { + if (elem == chain) + return 1; + chain = TREE_CHAIN (chain); + } + + return 0; +} + +/* Return the length of a chain of nodes chained through TREE_CHAIN. + We expect a null pointer to mark the end of the chain. + This is the Lisp primitive `length'. */ + +int +list_length (t) + tree t; +{ + register tree tail; + register int len = 0; + + for (tail = t; tail; tail = TREE_CHAIN (tail)) + len++; + + return len; +} + +/* Concatenate two chains of nodes (chained through TREE_CHAIN) + by modifying the last node in chain 1 to point to chain 2. + This is the Lisp primitive `nconc'. */ + +tree +chainon (op1, op2) + tree op1, op2; +{ + tree t; + + if (op1) + { + for (t = op1; TREE_CHAIN (t); t = TREE_CHAIN (t)) + if (t == op2) abort (); /* Circularity being created */ + if (t == op2) abort (); /* Circularity being created */ + TREE_CHAIN (t) = op2; + return op1; + } + else return op2; +} + +/* Return the last node in a chain of nodes (chained through TREE_CHAIN). */ + +tree +tree_last (chain) + register tree chain; +{ + register tree next; + if (chain) + while (next = TREE_CHAIN (chain)) + chain = next; + return chain; +} + +/* Reverse the order of elements in the chain T, + and return the new head of the chain (old last element). */ + +tree +nreverse (t) + tree t; +{ + register tree prev = 0, decl, next; + for (decl = t; decl; decl = next) + { + next = TREE_CHAIN (decl); + TREE_CHAIN (decl) = prev; + prev = decl; + } + return prev; +} + +/* Given a chain CHAIN of tree nodes, + construct and return a list of those nodes. */ + +tree +listify (chain) + tree chain; +{ + tree result = NULL_TREE; + tree in_tail = chain; + tree out_tail = NULL_TREE; + + while (in_tail) + { + tree next = tree_cons (NULL_TREE, in_tail, NULL_TREE); + if (out_tail) + TREE_CHAIN (out_tail) = next; + else + result = next; + out_tail = next; + in_tail = TREE_CHAIN (in_tail); + } + + return result; +} + +/* Return a newly created TREE_LIST node whose + purpose and value fields are PARM and VALUE. */ + +tree +build_tree_list (parm, value) + tree parm, value; +{ + register tree t = make_node (TREE_LIST); + TREE_PURPOSE (t) = parm; + TREE_VALUE (t) = value; + return t; +} + +/* Similar, but build on the temp_decl_obstack. */ + +tree +build_decl_list (parm, value) + tree parm, value; +{ + register tree node; + register struct obstack *ambient_obstack = current_obstack; + current_obstack = &temp_decl_obstack; + node = build_tree_list (parm, value); + current_obstack = ambient_obstack; + return node; +} + +/* Return a newly created TREE_LIST node whose + purpose and value fields are PARM and VALUE + and whose TREE_CHAIN is CHAIN. */ + +tree +tree_cons (purpose, value, chain) + tree purpose, value, chain; +{ +#if 0 + register tree node = make_node (TREE_LIST); +#else + register int i; + register tree node = (tree) obstack_alloc (current_obstack, sizeof (struct tree_list)); +#ifdef GATHER_STATISTICS + tree_node_counts[(int)x_kind]++; + tree_node_sizes[(int)x_kind] += sizeof (struct tree_list); +#endif + + for (i = (sizeof (struct tree_common) / sizeof (int)) - 1; i >= 0; i--) + ((int *) node)[i] = 0; + + TREE_SET_CODE (node, TREE_LIST); + if (current_obstack == &permanent_obstack) + TREE_PERMANENT (node) = 1; +#endif + + TREE_CHAIN (node) = chain; + TREE_PURPOSE (node) = purpose; + TREE_VALUE (node) = value; + return node; +} + +/* Similar, but build on the temp_decl_obstack. */ + +tree +decl_tree_cons (purpose, value, chain) + tree purpose, value, chain; +{ + register tree node; + register struct obstack *ambient_obstack = current_obstack; + current_obstack = &temp_decl_obstack; + node = tree_cons (purpose, value, chain); + current_obstack = ambient_obstack; + return node; +} + +/* Same as `tree_cons' but make a permanent object. */ + +tree +perm_tree_cons (purpose, value, chain) + tree purpose, value, chain; +{ + register tree node; + register struct obstack *ambient_obstack = current_obstack; + current_obstack = &permanent_obstack; + + node = tree_cons (purpose, value, chain); + current_obstack = ambient_obstack; + return node; +} + +/* Same as `tree_cons', but make this node temporary, regardless. */ + +tree +temp_tree_cons (purpose, value, chain) + tree purpose, value, chain; +{ + register tree node; + register struct obstack *ambient_obstack = current_obstack; + current_obstack = &temporary_obstack; + + node = tree_cons (purpose, value, chain); + current_obstack = ambient_obstack; + return node; +} + +/* Same as `tree_cons', but save this node if the function's RTL is saved. */ + +tree +saveable_tree_cons (purpose, value, chain) + tree purpose, value, chain; +{ + register tree node; + register struct obstack *ambient_obstack = current_obstack; + current_obstack = saveable_obstack; + + node = tree_cons (purpose, value, chain); + current_obstack = ambient_obstack; + return node; +} + +/* Return the size nominally occupied by an object of type TYPE + when it resides in memory. The value is measured in units of bytes, + and its data type is that normally used for type sizes + (which is the first type created by make_signed_type or + make_unsigned_type). */ + +tree +size_in_bytes (type) + tree type; +{ + tree t; + + if (type == error_mark_node) + return integer_zero_node; + type = TYPE_MAIN_VARIANT (type); + if (TYPE_SIZE (type) == 0) + { + incomplete_type_error (NULL_TREE, type); + return integer_zero_node; + } + t = size_binop (CEIL_DIV_EXPR, TYPE_SIZE (type), + size_int (BITS_PER_UNIT)); + if (TREE_CODE (t) == INTEGER_CST) + force_fit_type (t, 0); + return t; +} + +/* Return the size of TYPE (in bytes) as an integer, + or return -1 if the size can vary. */ + +int +int_size_in_bytes (type) + tree type; +{ + unsigned int size; + if (type == error_mark_node) + return 0; + type = TYPE_MAIN_VARIANT (type); + if (TYPE_SIZE (type) == 0) + return -1; + if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) + return -1; + if (TREE_INT_CST_HIGH (TYPE_SIZE (type)) != 0) + { + tree t = size_binop (CEIL_DIV_EXPR, TYPE_SIZE (type), + size_int (BITS_PER_UNIT)); + return TREE_INT_CST_LOW (t); + } + size = TREE_INT_CST_LOW (TYPE_SIZE (type)); + return (size + BITS_PER_UNIT - 1) / BITS_PER_UNIT; +} + +/* Return, as an INTEGER_CST node, the number of elements for + TYPE (which is an ARRAY_TYPE) minus one. + This counts only elements of the top array. */ + +tree +array_type_nelts (type) + tree type; +{ + tree index_type = TYPE_DOMAIN (type); + return (tree_int_cst_equal (TYPE_MIN_VALUE (index_type), integer_zero_node) + ? TYPE_MAX_VALUE (index_type) + : fold (build (MINUS_EXPR, integer_type_node, + TYPE_MAX_VALUE (index_type), + TYPE_MIN_VALUE (index_type)))); +} + +/* Return nonzero if arg is static -- a reference to an object in + static storage. This is not the same as the C meaning of `static'. */ + +int +staticp (arg) + tree arg; +{ + switch (TREE_CODE (arg)) + { + case VAR_DECL: + case FUNCTION_DECL: + case CONSTRUCTOR: + return TREE_STATIC (arg) || DECL_EXTERNAL (arg); + + case STRING_CST: + return 1; + + case COMPONENT_REF: + case BIT_FIELD_REF: + return staticp (TREE_OPERAND (arg, 0)); + + case INDIRECT_REF: + return TREE_CONSTANT (TREE_OPERAND (arg, 0)); + + case ARRAY_REF: + if (TREE_CODE (TYPE_SIZE (TREE_TYPE (arg))) == INTEGER_CST + && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST) + return staticp (TREE_OPERAND (arg, 0)); + } + + return 0; +} + +/* This should be applied to any node which may be used in more than one place, + but must be evaluated only once. Normally, the code generator would + reevaluate the node each time; this forces it to compute it once and save + the result. This is done by encapsulating the node in a SAVE_EXPR. */ + +tree +save_expr (expr) + tree expr; +{ + register tree t = fold (expr); + + /* We don't care about whether this can be used as an lvalue in this + context. */ + while (TREE_CODE (t) == NON_LVALUE_EXPR) + t = TREE_OPERAND (t, 0); + + /* If the tree evaluates to a constant, then we don't want to hide that + fact (i.e. this allows further folding, and direct checks for constants). + However, a read-only object that has side effects cannot be bypassed. + Since it is no problem to reevaluate literals, we just return the + literal node. */ + + if (TREE_CONSTANT (t) || (TREE_READONLY (t) && ! TREE_SIDE_EFFECTS (t)) + || TREE_CODE (t) == SAVE_EXPR) + return t; + + t = build (SAVE_EXPR, TREE_TYPE (expr), t, current_function_decl, NULL_TREE); + + /* This expression might be placed ahead of a jump to ensure that the + value was computed on both sides of the jump. So make sure it isn't + eliminated as dead. */ + TREE_SIDE_EFFECTS (t) = 1; + return t; +} + +/* Stabilize a reference so that we can use it any number of times + without causing its operands to be evaluated more than once. + Returns the stabilized reference. + + Also allows conversion expressions whose operands are references. + Any other kind of expression is returned unchanged. */ + +tree +stabilize_reference (ref) + tree ref; +{ + register tree result; + register enum tree_code code = TREE_CODE (ref); + + switch (code) + { + case VAR_DECL: + case PARM_DECL: + case RESULT_DECL: + /* No action is needed in this case. */ + return ref; + + case NOP_EXPR: + case CONVERT_EXPR: + case FLOAT_EXPR: + case FIX_TRUNC_EXPR: + case FIX_FLOOR_EXPR: + case FIX_ROUND_EXPR: + case FIX_CEIL_EXPR: + result = build_nt (code, stabilize_reference (TREE_OPERAND (ref, 0))); + break; + + case INDIRECT_REF: + result = build_nt (INDIRECT_REF, + stabilize_reference_1 (TREE_OPERAND (ref, 0))); + break; + + case COMPONENT_REF: + result = build_nt (COMPONENT_REF, + stabilize_reference (TREE_OPERAND (ref, 0)), + TREE_OPERAND (ref, 1)); + break; + + case BIT_FIELD_REF: + result = build_nt (BIT_FIELD_REF, + stabilize_reference (TREE_OPERAND (ref, 0)), + stabilize_reference_1 (TREE_OPERAND (ref, 1)), + stabilize_reference_1 (TREE_OPERAND (ref, 2))); + break; + + case ARRAY_REF: + result = build_nt (ARRAY_REF, + stabilize_reference (TREE_OPERAND (ref, 0)), + stabilize_reference_1 (TREE_OPERAND (ref, 1))); + break; + + /* If arg isn't a kind of lvalue we recognize, make no change. + Caller should recognize the error for an invalid lvalue. */ + default: + return ref; + + case ERROR_MARK: + return error_mark_node; + } + + TREE_TYPE (result) = TREE_TYPE (ref); + TREE_READONLY (result) = TREE_READONLY (ref); + TREE_SIDE_EFFECTS (result) = TREE_SIDE_EFFECTS (ref); + TREE_THIS_VOLATILE (result) = TREE_THIS_VOLATILE (ref); + TREE_RAISES (result) = TREE_RAISES (ref); + + return result; +} + +/* Subroutine of stabilize_reference; this is called for subtrees of + references. Any expression with side-effects must be put in a SAVE_EXPR + to ensure that it is only evaluated once. + + We don't put SAVE_EXPR nodes around everything, because assigning very + simple expressions to temporaries causes us to miss good opportunities + for optimizations. Among other things, the opportunity to fold in the + addition of a constant into an addressing mode often gets lost, e.g. + "y[i+1] += x;". In general, we take the approach that we should not make + an assignment unless we are forced into it - i.e., that any non-side effect + operator should be allowed, and that cse should take care of coalescing + multiple utterances of the same expression should that prove fruitful. */ + +static tree +stabilize_reference_1 (e) + tree e; +{ + register tree result; + register int length; + register enum tree_code code = TREE_CODE (e); + + /* We cannot ignore const expressions because it might be a reference + to a const array but whose index contains side-effects. But we can + ignore things that are actual constant or that already have been + handled by this function. */ + + if (TREE_CONSTANT (e) || code == SAVE_EXPR) + return e; + + switch (TREE_CODE_CLASS (code)) + { + case 'x': + case 't': + case 'd': + case 'b': + case '<': + case 's': + case 'e': + case 'r': + /* If the expression has side-effects, then encase it in a SAVE_EXPR + so that it will only be evaluated once. */ + /* The reference (r) and comparison (<) classes could be handled as + below, but it is generally faster to only evaluate them once. */ + if (TREE_SIDE_EFFECTS (e)) + return save_expr (e); + return e; + + case 'c': + /* Constants need no processing. In fact, we should never reach + here. */ + return e; + + case '2': + /* Division is slow and tends to be compiled with jumps, + especially the division by powers of 2 that is often + found inside of an array reference. So do it just once. */ + if (code == TRUNC_DIV_EXPR || code == TRUNC_MOD_EXPR + || code == FLOOR_DIV_EXPR || code == FLOOR_MOD_EXPR + || code == CEIL_DIV_EXPR || code == CEIL_MOD_EXPR + || code == ROUND_DIV_EXPR || code == ROUND_MOD_EXPR) + return save_expr (e); + /* Recursively stabilize each operand. */ + result = build_nt (code, stabilize_reference_1 (TREE_OPERAND (e, 0)), + stabilize_reference_1 (TREE_OPERAND (e, 1))); + break; + + case '1': + /* Recursively stabilize each operand. */ + result = build_nt (code, stabilize_reference_1 (TREE_OPERAND (e, 0))); + break; + } + + TREE_TYPE (result) = TREE_TYPE (e); + TREE_READONLY (result) = TREE_READONLY (e); + TREE_SIDE_EFFECTS (result) = TREE_SIDE_EFFECTS (e); + TREE_THIS_VOLATILE (result) = TREE_THIS_VOLATILE (e); + TREE_RAISES (result) = TREE_RAISES (e); + + return result; +} + +/* Low-level constructors for expressions. */ + +/* Build an expression of code CODE, data type TYPE, + and operands as specified by the arguments ARG1 and following arguments. + Expressions and reference nodes can be created this way. + Constants, decls, types and misc nodes cannot be. */ + +tree +build (va_alist) + va_dcl +{ + va_list p; + enum tree_code code; + register tree t; + register int length; + register int i; + + va_start (p); + + code = va_arg (p, enum tree_code); + t = make_node (code); + length = tree_code_length[(int) code]; + TREE_TYPE (t) = va_arg (p, tree); + + if (length == 2) + { + /* This is equivalent to the loop below, but faster. */ + register tree arg0 = va_arg (p, tree); + register tree arg1 = va_arg (p, tree); + TREE_OPERAND (t, 0) = arg0; + TREE_OPERAND (t, 1) = arg1; + if ((arg0 && TREE_SIDE_EFFECTS (arg0)) + || (arg1 && TREE_SIDE_EFFECTS (arg1))) + TREE_SIDE_EFFECTS (t) = 1; + TREE_RAISES (t) + = (arg0 && TREE_RAISES (arg0)) || (arg1 && TREE_RAISES (arg1)); + } + else if (length == 1) + { + register tree arg0 = va_arg (p, tree); + + /* Call build1 for this! */ + if (TREE_CODE_CLASS (code) != 's') + abort (); + TREE_OPERAND (t, 0) = arg0; + if (arg0 && TREE_SIDE_EFFECTS (arg0)) + TREE_SIDE_EFFECTS (t) = 1; + TREE_RAISES (t) = (arg0 && TREE_RAISES (arg0)); + } + else + { + for (i = 0; i < length; i++) + { + register tree operand = va_arg (p, tree); + TREE_OPERAND (t, i) = operand; + if (operand) + { + if (TREE_SIDE_EFFECTS (operand)) + TREE_SIDE_EFFECTS (t) = 1; + if (TREE_RAISES (operand)) + TREE_RAISES (t) = 1; + } + } + } + va_end (p); + return t; +} + +/* Same as above, but only builds for unary operators. + Saves lions share of calls to `build'; cuts down use + of varargs, which is expensive for RISC machines. */ +tree +build1 (code, type, node) + enum tree_code code; + tree type; + tree node; +{ + register struct obstack *obstack = current_obstack; + register int i, length; + register tree_node_kind kind; + register tree t; + +#ifdef GATHER_STATISTICS + if (TREE_CODE_CLASS (code) == 'r') + kind = r_kind; + else + kind = e_kind; +#endif + + obstack = expression_obstack; + length = sizeof (struct tree_exp); + + t = (tree) obstack_alloc (obstack, length); + +#ifdef GATHER_STATISTICS + tree_node_counts[(int)kind]++; + tree_node_sizes[(int)kind] += length; +#endif + + for (i = (length / sizeof (int)) - 1; i >= 0; i--) + ((int *) t)[i] = 0; + + TREE_TYPE (t) = type; + TREE_SET_CODE (t, code); + + if (obstack == &permanent_obstack) + TREE_PERMANENT (t) = 1; + + TREE_OPERAND (t, 0) = node; + if (node) + { + if (TREE_SIDE_EFFECTS (node)) + TREE_SIDE_EFFECTS (t) = 1; + if (TREE_RAISES (node)) + TREE_RAISES (t) = 1; + } + + return t; +} + +/* Similar except don't specify the TREE_TYPE + and leave the TREE_SIDE_EFFECTS as 0. + It is permissible for arguments to be null, + or even garbage if their values do not matter. */ + +tree +build_nt (va_alist) + va_dcl +{ + va_list p; + register enum tree_code code; + register tree t; + register int length; + register int i; + + va_start (p); + + code = va_arg (p, enum tree_code); + t = make_node (code); + length = tree_code_length[(int) code]; + + for (i = 0; i < length; i++) + TREE_OPERAND (t, i) = va_arg (p, tree); + + va_end (p); + return t; +} + +/* Similar to `build_nt', except we build + on the temp_decl_obstack, regardless. */ + +tree +build_parse_node (va_alist) + va_dcl +{ + register struct obstack *ambient_obstack = expression_obstack; + va_list p; + register enum tree_code code; + register tree t; + register int length; + register int i; + + expression_obstack = &temp_decl_obstack; + + va_start (p); + + code = va_arg (p, enum tree_code); + t = make_node (code); + length = tree_code_length[(int) code]; + + for (i = 0; i < length; i++) + TREE_OPERAND (t, i) = va_arg (p, tree); + + va_end (p); + expression_obstack = ambient_obstack; + return t; +} + +#if 0 +/* Commented out because this wants to be done very + differently. See cp-lex.c. */ +tree +build_op_identifier (op1, op2) + tree op1, op2; +{ + register tree t = make_node (OP_IDENTIFIER); + TREE_PURPOSE (t) = op1; + TREE_VALUE (t) = op2; + return t; +} +#endif + +/* Create a DECL_... node of code CODE, name NAME and data type TYPE. + We do NOT enter this node in any sort of symbol table. + + layout_decl is used to set up the decl's storage layout. + Other slots are initialized to 0 or null pointers. */ + +tree +build_decl (code, name, type) + enum tree_code code; + tree name, type; +{ + register tree t; + + t = make_node (code); + +/* if (type == error_mark_node) + type = integer_type_node; */ +/* That is not done, deliberately, so that having error_mark_node + as the type can suppress useless errors in the use of this variable. */ + + DECL_NAME (t) = name; + DECL_ASSEMBLER_NAME (t) = name; + TREE_TYPE (t) = type; + + if (code == VAR_DECL || code == PARM_DECL || code == RESULT_DECL) + layout_decl (t, 0); + else if (code == FUNCTION_DECL) + DECL_MODE (t) = FUNCTION_MODE; + + return t; +} + +/* BLOCK nodes are used to represent the structure of binding contours + and declarations, once those contours have been exited and their contents + compiled. This information is used for outputting debugging info. */ + +tree +build_block (vars, tags, subblocks, supercontext, chain) + tree vars, tags, subblocks, supercontext, chain; +{ + register tree block = make_node (BLOCK); + BLOCK_VARS (block) = vars; + BLOCK_TYPE_TAGS (block) = tags; + BLOCK_SUBBLOCKS (block) = subblocks; + BLOCK_SUPERCONTEXT (block) = supercontext; + BLOCK_CHAIN (block) = chain; + return block; +} + +/* Return a type like TYPE except that its TYPE_READONLY is CONSTP + and its TYPE_VOLATILE is VOLATILEP. + + Such variant types already made are recorded so that duplicates + are not made. + + A variant types should never be used as the type of an expression. + Always copy the variant information into the TREE_READONLY + and TREE_THIS_VOLATILE of the expression, and then give the expression + as its type the "main variant", the variant whose TYPE_READONLY + and TYPE_VOLATILE are zero. Use TYPE_MAIN_VARIANT to find the + main variant. */ + +tree +build_type_variant (type, constp, volatilep) + tree type; + int constp, volatilep; +{ + register tree t, m = TYPE_MAIN_VARIANT (type); + register struct obstack *ambient_obstack = current_obstack; + + /* Treat any nonzero argument as 1. */ + constp = !!constp; + volatilep = !!volatilep; + + /* If not generating auxiliary info, search the chain of variants to see + if there is already one there just like the one we need to have. If so, + use that existing one. + + We don't do this in the case where we are generating aux info because + in that case we want each typedef names to get it's own distinct type + node, even if the type of this new typedef is the same as some other + (existing) type. */ + + if (!flag_gen_aux_info) + for (t = m; t; t = TYPE_NEXT_VARIANT (t)) + if (constp == TYPE_READONLY (t) && volatilep == TYPE_VOLATILE (t)) + return t; + + /* We need a new one. */ + current_obstack + = TREE_PERMANENT (type) ? &permanent_obstack : saveable_obstack; + + t = copy_node (type); + TYPE_READONLY (t) = constp; + TYPE_VOLATILE (t) = volatilep; + TYPE_POINTER_TO (t) = 0; + TYPE_REFERENCE_TO (t) = 0; + + /* Add this type to the chain of variants of TYPE. */ + TYPE_NEXT_VARIANT (t) = TYPE_NEXT_VARIANT (m); + TYPE_NEXT_VARIANT (m) = t; + + current_obstack = ambient_obstack; + return t; +} + +/* Give TYPE a new main variant: NEW_MAIN. + This is the right thing to do only when something else + about TYPE is modified in place. */ + +tree +change_main_variant (type, new_main) + tree type, new_main; +{ + tree t; + tree omain = TYPE_MAIN_VARIANT (type); + + /* Remove TYPE from the TYPE_NEXT_VARIANT chain of its main variant. */ + if (TYPE_NEXT_VARIANT (omain) == type) + TYPE_NEXT_VARIANT (omain) = TYPE_NEXT_VARIANT (type); + else + for (t = TYPE_NEXT_VARIANT (omain); t && TYPE_NEXT_VARIANT (t); + t = TYPE_NEXT_VARIANT (t)) + if (TYPE_NEXT_VARIANT (t) == type) + { + TYPE_NEXT_VARIANT (t) = TYPE_NEXT_VARIANT (type); + break; + } + + TYPE_MAIN_VARIANT (type) = new_main; + TYPE_NEXT_VARIANT (type) = TYPE_NEXT_VARIANT (new_main); + TYPE_NEXT_VARIANT (new_main) = type; +} + +/* Create a new variant of TYPE, equivalent but distinct. + This is so the caller can modify it. */ + +tree +build_type_copy (type) + tree type; +{ + register tree t, m = TYPE_MAIN_VARIANT (type); + register struct obstack *ambient_obstack = current_obstack; + + current_obstack + = TREE_PERMANENT (type) ? &permanent_obstack : saveable_obstack; + + t = copy_node (type); + TYPE_POINTER_TO (t) = 0; + TYPE_REFERENCE_TO (t) = 0; + + /* Add this type to the chain of variants of TYPE. */ + TYPE_NEXT_VARIANT (t) = TYPE_NEXT_VARIANT (m); + TYPE_NEXT_VARIANT (m) = t; + + current_obstack = ambient_obstack; + return t; +} + +/* Hashing of types so that we don't make duplicates. + The entry point is `type_hash_canon'. */ + +/* Each hash table slot is a bucket containing a chain + of these structures. */ + +struct type_hash +{ + struct type_hash *next; /* Next structure in the bucket. */ + int hashcode; /* Hash code of this type. */ + tree type; /* The type recorded here. */ +}; + +/* Now here is the hash table. When recording a type, it is added + to the slot whose index is the hash code mod the table size. + Note that the hash table is used for several kinds of types + (function types, array types and array index range types, for now). + While all these live in the same table, they are completely independent, + and the hash code is computed differently for each of these. */ + +#define TYPE_HASH_SIZE 59 +struct type_hash *type_hash_table[TYPE_HASH_SIZE]; + +/* Here is how primitive or already-canonicalized types' hash + codes are made. */ +#define TYPE_HASH(TYPE) ((HOST_WIDE_INT) (TYPE) & 0777777) + +/* Compute a hash code for a list of types (chain of TREE_LIST nodes + with types in the TREE_VALUE slots), by adding the hash codes + of the individual types. */ + +int +type_hash_list (list) + tree list; +{ + register int hashcode; + register tree tail; + for (hashcode = 0, tail = list; tail; tail = TREE_CHAIN (tail)) + hashcode += TYPE_HASH (TREE_VALUE (tail)); + return hashcode; +} + +/* Look in the type hash table for a type isomorphic to TYPE. + If one is found, return it. Otherwise return 0. */ + +tree +type_hash_lookup (hashcode, type) + int hashcode; + tree type; +{ + register struct type_hash *h; + for (h = type_hash_table[hashcode % TYPE_HASH_SIZE]; h; h = h->next) + if (h->hashcode == hashcode + && TREE_CODE (h->type) == TREE_CODE (type) + && TREE_TYPE (h->type) == TREE_TYPE (type) + && (TYPE_MAX_VALUE (h->type) == TYPE_MAX_VALUE (type) + || tree_int_cst_equal (TYPE_MAX_VALUE (h->type), + TYPE_MAX_VALUE (type))) + && (TYPE_MIN_VALUE (h->type) == TYPE_MIN_VALUE (type) + || tree_int_cst_equal (TYPE_MIN_VALUE (h->type), + TYPE_MIN_VALUE (type))) + && (TYPE_DOMAIN (h->type) == TYPE_DOMAIN (type) + || (TYPE_DOMAIN (h->type) + && TREE_CODE (TYPE_DOMAIN (h->type)) == TREE_LIST + && TYPE_DOMAIN (type) + && TREE_CODE (TYPE_DOMAIN (type)) == TREE_LIST + && type_list_equal (TYPE_DOMAIN (h->type), TYPE_DOMAIN (type))))) + return h->type; + return 0; +} + +/* Add an entry to the type-hash-table + for a type TYPE whose hash code is HASHCODE. */ + +void +type_hash_add (hashcode, type) + int hashcode; + tree type; +{ + register struct type_hash *h; + + h = (struct type_hash *) oballoc (sizeof (struct type_hash)); + h->hashcode = hashcode; + h->type = type; + h->next = type_hash_table[hashcode % TYPE_HASH_SIZE]; + type_hash_table[hashcode % TYPE_HASH_SIZE] = h; +} + +/* Given TYPE, and HASHCODE its hash code, return the canonical + object for an identical type if one already exists. + Otherwise, return TYPE, and record it as the canonical object + if it is a permanent object. + + To use this function, first create a type of the sort you want. + Then compute its hash code from the fields of the type that + make it different from other similar types. + Then call this function and use the value. + This function frees the type you pass in if it is a duplicate. */ + +/* Set to 1 to debug without canonicalization. Never set by program. */ +int debug_no_type_hash = 0; + +tree +type_hash_canon (hashcode, type) + int hashcode; + tree type; +{ + tree t1; + + if (debug_no_type_hash) + return type; + + t1 = type_hash_lookup (hashcode, type); + if (t1 != 0) + { + struct obstack *o + = TREE_PERMANENT (type) ? &permanent_obstack : saveable_obstack; + obstack_free (o, type); +#ifdef GATHER_STATISTICS + tree_node_counts[(int)t_kind]--; + tree_node_sizes[(int)t_kind] -= sizeof (struct tree_type); +#endif + return t1; + } + + /* If this is a new type, record it for later reuse. */ + if (current_obstack == &permanent_obstack) + type_hash_add (hashcode, type); + + return type; +} + +/* Given two lists of types + (chains of TREE_LIST nodes with types in the TREE_VALUE slots) + return 1 if the lists contain the same types in the same order. + Also, the TREE_PURPOSEs must match. */ + +int +type_list_equal (l1, l2) + tree l1, l2; +{ + register tree t1, t2; + for (t1 = l1, t2 = l2; t1 && t2; t1 = TREE_CHAIN (t1), t2 = TREE_CHAIN (t2)) + { + if (TREE_VALUE (t1) != TREE_VALUE (t2)) + return 0; + if (TREE_PURPOSE (t1) != TREE_PURPOSE (t2)) + { + int cmp = simple_cst_equal (TREE_PURPOSE (t1), TREE_PURPOSE (t2)); + if (cmp < 0) + abort (); + if (cmp == 0) + return 0; + } + } + + return t1 == t2; +} + +/* Nonzero if integer constants T1 and T2 + represent the same constant value. */ + +int +tree_int_cst_equal (t1, t2) + tree t1, t2; +{ + if (t1 == t2) + return 1; + if (t1 == 0 || t2 == 0) + return 0; + if (TREE_CODE (t1) == INTEGER_CST + && TREE_CODE (t2) == INTEGER_CST + && TREE_INT_CST_LOW (t1) == TREE_INT_CST_LOW (t2) + && TREE_INT_CST_HIGH (t1) == TREE_INT_CST_HIGH (t2)) + return 1; + return 0; +} + +/* Nonzero if integer constants T1 and T2 represent values that satisfy <. + The precise way of comparison depends on their data type. */ + +int +tree_int_cst_lt (t1, t2) + tree t1, t2; +{ + if (t1 == t2) + return 0; + + if (!TREE_UNSIGNED (TREE_TYPE (t1))) + return INT_CST_LT (t1, t2); + return INT_CST_LT_UNSIGNED (t1, t2); +} + +/* Compare two constructor-element-type constants. */ +int +simple_cst_list_equal (l1, l2) + tree l1, l2; +{ + while (l1 != NULL_TREE && l2 != NULL_TREE) + { + int cmp = simple_cst_equal (TREE_VALUE (l1), TREE_VALUE (l2)); + if (cmp < 0) + abort (); + if (cmp == 0) + return 0; + l1 = TREE_CHAIN (l1); + l2 = TREE_CHAIN (l2); + } + return (l1 == l2); +} + +/* Return truthvalue of whether T1 is the same tree structure as T2. + Return 1 if they are the same. + Return 0 if they are understandably different. + Return -1 if either contains tree structure not understood by + this function. */ + +int +simple_cst_equal (t1, t2) + tree t1, t2; +{ + register enum tree_code code1, code2; + int cmp; + + if (t1 == t2) + return 1; + if (t1 == 0 || t2 == 0) + return 0; + + code1 = TREE_CODE (t1); + code2 = TREE_CODE (t2); + + if (code1 == NOP_EXPR || code1 == CONVERT_EXPR || code1 == NON_LVALUE_EXPR) + if (code2 == NOP_EXPR || code2 == CONVERT_EXPR || code2 == NON_LVALUE_EXPR) + return simple_cst_equal (TREE_OPERAND (t1, 0), TREE_OPERAND (t2, 0)); + else + return simple_cst_equal (TREE_OPERAND (t1, 0), t2); + else if (code2 == NOP_EXPR || code2 == CONVERT_EXPR + || code2 == NON_LVALUE_EXPR) + return simple_cst_equal (t1, TREE_OPERAND (t2, 0)); + + if (code1 != code2) + return 0; + + switch (code1) + { + case INTEGER_CST: + return TREE_INT_CST_LOW (t1) == TREE_INT_CST_LOW (t2) + && TREE_INT_CST_HIGH (t1) == TREE_INT_CST_HIGH (t2); + + case REAL_CST: + return REAL_VALUES_EQUAL (TREE_REAL_CST (t1), TREE_REAL_CST (t2)); + + case STRING_CST: + return TREE_STRING_LENGTH (t1) == TREE_STRING_LENGTH (t2) + && !bcmp (TREE_STRING_POINTER (t1), TREE_STRING_POINTER (t2), + TREE_STRING_LENGTH (t1)); + + case CONSTRUCTOR: + abort (); + + case SAVE_EXPR: + return simple_cst_equal (TREE_OPERAND (t1, 0), TREE_OPERAND (t2, 0)); + + case CALL_EXPR: + cmp = simple_cst_equal (TREE_OPERAND (t1, 0), TREE_OPERAND (t2, 0)); + if (cmp <= 0) + return cmp; + return simple_cst_list_equal (TREE_OPERAND (t1, 1), TREE_OPERAND (t2, 1)); + + case TARGET_EXPR: + /* Special case: if either target is an unallocated VAR_DECL, + it means that it's going to be unified with whatever the + TARGET_EXPR is really supposed to initialize, so treat it + as being equivalent to anything. */ + if ((TREE_CODE (TREE_OPERAND (t1, 0)) == VAR_DECL + && DECL_NAME (TREE_OPERAND (t1, 0)) == NULL_TREE + && DECL_RTL (TREE_OPERAND (t1, 0)) == 0) + || (TREE_CODE (TREE_OPERAND (t2, 0)) == VAR_DECL + && DECL_NAME (TREE_OPERAND (t2, 0)) == NULL_TREE + && DECL_RTL (TREE_OPERAND (t2, 0)) == 0)) + cmp = 1; + else + cmp = simple_cst_equal (TREE_OPERAND (t1, 0), TREE_OPERAND (t2, 0)); + if (cmp <= 0) + return cmp; + return simple_cst_equal (TREE_OPERAND (t1, 1), TREE_OPERAND (t2, 1)); + + case WITH_CLEANUP_EXPR: + cmp = simple_cst_equal (TREE_OPERAND (t1, 0), TREE_OPERAND (t2, 0)); + if (cmp <= 0) + return cmp; + return simple_cst_equal (TREE_OPERAND (t1, 2), TREE_OPERAND (t1, 2)); + + case COMPONENT_REF: + if (TREE_OPERAND (t1, 1) == TREE_OPERAND (t2, 1)) + return simple_cst_equal (TREE_OPERAND (t1, 0), TREE_OPERAND (t2, 0)); + return 0; + + case VAR_DECL: + case PARM_DECL: + case CONST_DECL: + case FUNCTION_DECL: + return 0; + } + + /* This general rule works for most tree codes. + All exceptions should be handled above. */ + + switch (TREE_CODE_CLASS (code1)) + { + int i; + case '1': + case '2': + case '<': + case 'e': + case 'r': + case 's': + cmp = 1; + for (i=0; i TYPE_PRECISION (type) + && TREE_UNSIGNED (type)); + register tree win = op; + + while (TREE_CODE (op) == NOP_EXPR) + { + register int bitschange + = TYPE_PRECISION (TREE_TYPE (op)) + - TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (op, 0))); + + /* Truncations are many-one so cannot be removed. + Unless we are later going to truncate down even farther. */ + if (bitschange < 0 + && final_prec > TYPE_PRECISION (TREE_TYPE (op))) + break; + + /* See what's inside this conversion. If we decide to strip it, + we will set WIN. */ + op = TREE_OPERAND (op, 0); + + /* If we have not stripped any zero-extensions (uns is 0), + we can strip any kind of extension. + If we have previously stripped a zero-extension, + only zero-extensions can safely be stripped. + Any extension can be stripped if the bits it would produce + are all going to be discarded later by truncating to FOR_TYPE. */ + + if (bitschange > 0) + { + if (! uns || final_prec <= TYPE_PRECISION (TREE_TYPE (op))) + win = op; + /* TREE_UNSIGNED says whether this is a zero-extension. + Let's avoid computing it if it does not affect WIN + and if UNS will not be needed again. */ + if ((uns || TREE_CODE (op) == NOP_EXPR) + && TREE_UNSIGNED (TREE_TYPE (op))) + { + uns = 1; + win = op; + } + } + } + + if (TREE_CODE (op) == COMPONENT_REF + /* Since type_for_size always gives an integer type. */ + && TREE_CODE (type) != REAL_TYPE) + { + unsigned innerprec = TREE_INT_CST_LOW (DECL_SIZE (TREE_OPERAND (op, 1))); + type = type_for_size (innerprec, TREE_UNSIGNED (TREE_OPERAND (op, 1))); + + /* We can get this structure field in the narrowest type it fits in. + If FOR_TYPE is 0, do this only for a field that matches the + narrower type exactly and is aligned for it + The resulting extension to its nominal type (a fullword type) + must fit the same conditions as for other extensions. */ + + if (innerprec < TYPE_PRECISION (TREE_TYPE (op)) + && (for_type || ! DECL_BIT_FIELD (TREE_OPERAND (op, 1))) + && (! uns || final_prec <= innerprec + || TREE_UNSIGNED (TREE_OPERAND (op, 1))) + && type != 0) + { + win = build (COMPONENT_REF, type, TREE_OPERAND (op, 0), + TREE_OPERAND (op, 1)); + TREE_SIDE_EFFECTS (win) = TREE_SIDE_EFFECTS (op); + TREE_THIS_VOLATILE (win) = TREE_THIS_VOLATILE (op); + TREE_RAISES (win) = TREE_RAISES (op); + } + } + return win; +} + +/* Return OP or a simpler expression for a narrower value + which can be sign-extended or zero-extended to give back OP. + Store in *UNSIGNEDP_PTR either 1 if the value should be zero-extended + or 0 if the value should be sign-extended. */ + +tree +get_narrower (op, unsignedp_ptr) + register tree op; + int *unsignedp_ptr; +{ + register int uns = 0; + int first = 1; + register tree win = op; + + while (TREE_CODE (op) == NOP_EXPR) + { + register int bitschange + = TYPE_PRECISION (TREE_TYPE (op)) + - TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (op, 0))); + + /* Truncations are many-one so cannot be removed. */ + if (bitschange < 0) + break; + + /* See what's inside this conversion. If we decide to strip it, + we will set WIN. */ + op = TREE_OPERAND (op, 0); + + if (bitschange > 0) + { + /* An extension: the outermost one can be stripped, + but remember whether it is zero or sign extension. */ + if (first) + uns = TREE_UNSIGNED (TREE_TYPE (op)); + /* Otherwise, if a sign extension has been stripped, + only sign extensions can now be stripped; + if a zero extension has been stripped, only zero-extensions. */ + else if (uns != TREE_UNSIGNED (TREE_TYPE (op))) + break; + first = 0; + } + /* A change in nominal type can always be stripped. */ + + win = op; + } + + if (TREE_CODE (op) == COMPONENT_REF + /* Since type_for_size always gives an integer type. */ + && TREE_CODE (TREE_TYPE (op)) != REAL_TYPE) + { + unsigned innerprec = TREE_INT_CST_LOW (DECL_SIZE (TREE_OPERAND (op, 1))); + tree type = type_for_size (innerprec, TREE_UNSIGNED (op)); + + /* We can get this structure field in a narrower type that fits it, + but the resulting extension to its nominal type (a fullword type) + must satisfy the same conditions as for other extensions. + + Do this only for fields that are aligned (not bit-fields), + because when bit-field insns will be used there is no + advantage in doing this. */ + + if (innerprec < TYPE_PRECISION (TREE_TYPE (op)) + && ! DECL_BIT_FIELD (TREE_OPERAND (op, 1)) + && (first || uns == TREE_UNSIGNED (TREE_OPERAND (op, 1))) + && type != 0) + { + if (first) + uns = TREE_UNSIGNED (TREE_OPERAND (op, 1)); + win = build (COMPONENT_REF, type, TREE_OPERAND (op, 0), + TREE_OPERAND (op, 1)); + TREE_SIDE_EFFECTS (win) = TREE_SIDE_EFFECTS (op); + TREE_THIS_VOLATILE (win) = TREE_THIS_VOLATILE (op); + TREE_RAISES (win) = TREE_RAISES (op); + } + } + *unsignedp_ptr = uns; + return win; +} + +/* Return the precision of a type, for arithmetic purposes. + Supports all types on which arithmetic is possible + (including pointer types). + It's not clear yet what will be right for complex types. */ + +int +type_precision (type) + register tree type; +{ + return ((TREE_CODE (type) == INTEGER_TYPE + || TREE_CODE (type) == ENUMERAL_TYPE + || TREE_CODE (type) == REAL_TYPE) + ? TYPE_PRECISION (type) : POINTER_SIZE); +} + +/* Nonzero if integer constant C has a value that is permissible + for type TYPE (an INTEGER_TYPE). */ + +int +int_fits_type_p (c, type) + tree c, type; +{ + if (TREE_UNSIGNED (type)) + return (!INT_CST_LT_UNSIGNED (TYPE_MAX_VALUE (type), c) + && !INT_CST_LT_UNSIGNED (c, TYPE_MIN_VALUE (type)) + && (TREE_INT_CST_HIGH (c) >= 0 || TREE_UNSIGNED (TREE_TYPE (c)))); + else + return (!INT_CST_LT (TYPE_MAX_VALUE (type), c) + && !INT_CST_LT (c, TYPE_MIN_VALUE (type)) + && (TREE_INT_CST_HIGH (c) >= 0 || !TREE_UNSIGNED (TREE_TYPE (c)))); +} + +/* Return the innermost context enclosing DECL that is + a FUNCTION_DECL, or zero if none. */ + +tree +decl_function_context (decl) + tree decl; +{ + tree context; + + if (TREE_CODE (decl) == ERROR_MARK) + return 0; + + if (TREE_CODE (decl) == SAVE_EXPR) + context = SAVE_EXPR_CONTEXT (decl); + else + context = DECL_CONTEXT (decl); + + while (context && TREE_CODE (context) != FUNCTION_DECL) + { + if (TREE_CODE (context) == RECORD_TYPE + || TREE_CODE (context) == UNION_TYPE) + context = TYPE_CONTEXT (context); + else if (TREE_CODE (context) == TYPE_DECL) + context = DECL_CONTEXT (context); + else if (TREE_CODE (context) == BLOCK) + context = BLOCK_SUPERCONTEXT (context); + else + /* Unhandled CONTEXT !? */ + abort (); + } + + return context; +} + +/* Return the innermost context enclosing DECL that is + a RECORD_TYPE or UNION_TYPE, or zero if none. + TYPE_DECLs and FUNCTION_DECLs are transparent to this function. */ + +tree +decl_type_context (decl) + tree decl; +{ + tree context = DECL_CONTEXT (decl); + + while (context) + { + if (TREE_CODE (context) == RECORD_TYPE + || TREE_CODE (context) == UNION_TYPE) + return context; + if (TREE_CODE (context) == TYPE_DECL + || TREE_CODE (context) == FUNCTION_DECL) + context = DECL_CONTEXT (context); + else if (TREE_CODE (context) == BLOCK) + context = BLOCK_SUPERCONTEXT (context); + else + /* Unhandled CONTEXT!? */ + abort (); + } + return NULL_TREE; +} + +void +print_obstack_statistics (str, o) + char *str; + struct obstack *o; +{ + struct _obstack_chunk *chunk = o->chunk; + int n_chunks = 0; + int n_alloc = 0; + + while (chunk) + { + n_chunks += 1; + n_alloc += chunk->limit - &chunk->contents[0]; + chunk = chunk->prev; + } + fprintf (stderr, "obstack %s: %d bytes, %d chunks\n", + str, n_alloc, n_chunks); +} +void +dump_tree_statistics () +{ + int i; + int total_nodes, total_bytes; + + fprintf (stderr, "\n??? tree nodes created\n\n"); +#ifdef GATHER_STATISTICS + fprintf (stderr, "Kind Nodes Bytes\n"); + fprintf (stderr, "-------------------------------------\n"); + total_nodes = total_bytes = 0; + for (i = 0; i < (int) all_kinds; i++) + { + fprintf (stderr, "%-20s %6d %9d\n", tree_node_kind_names[i], + tree_node_counts[i], tree_node_sizes[i]); + total_nodes += tree_node_counts[i]; + total_bytes += tree_node_sizes[i]; + } + fprintf (stderr, "%-20s %9d\n", "identifier names", id_string_size); + fprintf (stderr, "-------------------------------------\n"); + fprintf (stderr, "%-20s %6d %9d\n", "Total", total_nodes, total_bytes); + fprintf (stderr, "-------------------------------------\n"); +#else + fprintf (stderr, "(No per-node statistics)\n"); +#endif + print_lang_statistics (); +} diff --git a/gnu/usr.bin/cc/lib/tree.def b/gnu/usr.bin/cc/lib/tree.def new file mode 100644 index 000000000000..9bc81e7ad44c --- /dev/null +++ b/gnu/usr.bin/cc/lib/tree.def @@ -0,0 +1,645 @@ +/* This file contains the definitions and documentation for the + tree codes used in the GNU C compiler. + Copyright (C) 1987, 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* The third argument can be: + "x" for an exceptional code (fits no category). + "t" for a type object code. + "b" for a lexical block. + "c" for codes for constants. + "d" for codes for declarations (also serving as variable refs). + "r" for codes for references to storage. + "<" for codes for comparison expressions. + "1" for codes for unary arithmetic expressions. + "2" for codes for binary arithmetic expressions. + "s" for codes for expressions with inherent side effects. + "e" for codes for other kinds of expressions. */ + +/* For `r', `e', `<', `1', `2', `s' and `x' nodes, + the 4th element is the number of argument slots to allocate. + This determines the size of the tree node object. */ + +/* Any erroneous construct is parsed into a node of this type. + This type of node is accepted without complaint in all contexts + by later parsing activities, to avoid multiple error messages + for one error. + No fields in these nodes are used except the TREE_CODE. */ +DEFTREECODE (ERROR_MARK, "error_mark", "x", 0) + +/* Used to represent a name (such as, in the DECL_NAME of a decl node). + Internally it looks like a STRING_CST node. + There is only one IDENTIFIER_NODE ever made for any particular name. + Use `get_identifier' to get it (or create it, the first time). */ +DEFTREECODE (IDENTIFIER_NODE, "identifier_node", "x", -1) + +/* Used to hold information to identify an operator (or combination + of two operators) considered as a `noun' rather than a `verb'. + The first operand is encoded in the TREE_TYPE field. */ +DEFTREECODE (OP_IDENTIFIER, "op_identifier", "x", 2) + +/* Has the TREE_VALUE and TREE_PURPOSE fields. */ +/* These nodes are made into lists by chaining through the + TREE_CHAIN field. The elements of the list live in the + TREE_VALUE fields, while TREE_PURPOSE fields are occasionally + used as well to get the effect of Lisp association lists. */ +DEFTREECODE (TREE_LIST, "tree_list", "x", 2) + +/* These nodes contain an array of tree nodes. */ +DEFTREECODE (TREE_VEC, "tree_vec", "x", 2) + +/* A symbol binding block. These are arranged in a tree, + where the BLOCK_SUBBLOCKS field contains a chain of subblocks + chained through the BLOCK_CHAIN field. + BLOCK_SUPERCONTEXT points to the parent block. + For a block which represents the outermost scope of a function, it + points to the FUNCTION_DECL node. + BLOCK_VARS points to a chain of decl nodes. + BLOCK_TYPE_TAGS points to a chain of types which have their own names. + BLOCK_CHAIN points to the next BLOCK at the same level. + BLOCK_ABSTRACT_ORIGIN points to the original (abstract) tree node which + this block is an instance of, or else is NULL to indicate that this + block is not an instance of anything else. When non-NULL, the value + could either point to another BLOCK node or it could point to a + FUNCTION_DECL node (e.g. in the case of a block representing the + outermost scope of a particular inlining of a function). + BLOCK_ABSTRACT is non-zero if the block represents an abstract + instance of a block (i.e. one which is nested within an abstract + instance of a inline function. */ +DEFTREECODE (BLOCK, "block", "b", 0) + +/* Each data type is represented by a tree node whose code is one of + the following: */ +/* Each node that represents a data type has a component TYPE_SIZE + containing a tree that is an expression for the size in bits. + The TYPE_MODE contains the machine mode for values of this type. + The TYPE_POINTER_TO field contains a type for a pointer to this type, + or zero if no such has been created yet. + The TYPE_NEXT_VARIANT field is used to chain together types + that are variants made by type modifiers such as "const" and "volatile". + The TYPE_MAIN_VARIANT field, in any member of such a chain, + points to the start of the chain. + The TYPE_NONCOPIED_PARTS field is a list specifying which parts + of an object of this type should *not* be copied by assignment. + The TREE_PURPOSE of each element is the offset of the part + and the TREE_VALUE is the size in bits of the part. + The TYPE_NAME field contains info on the name used in the program + for this type (for GDB symbol table output). It is either a + TYPE_DECL node, for types that are typedefs, or an IDENTIFIER_NODE + in the case of structs, unions or enums that are known with a tag, + or zero for types that have no special name. + The TYPE_CONTEXT for any sort of type which could have a name or + which could have named members (e.g. tagged types in C/C++) will + point to the node which represents the scope of the given type, or + will be NULL_TREE if the type has "file scope". For most types, this + will point to a BLOCK node or a FUNCTION_DECL node, but it could also + point to a FUNCTION_TYPE node (for types whose scope is limited to the + formal parameter list of some function type specification) or it + could point to a RECORD_TYPE, UNION_TYPE or QUAL_UNION_TYPE node + (for C++ "member" types). + For non-tagged-types, TYPE_CONTEXT need not be set to anything in + particular, since any type which is of some type category (e.g. + an array type or a function type) which cannot either have a name + itself or have named members doesn't really have a "scope" per se. + The TREE_CHAIN field is used as a forward-references to names for + ENUMERAL_TYPE, RECORD_TYPE, UNION_TYPE, and QUAL_UNION_TYPE nodes; + see below. */ + +DEFTREECODE (VOID_TYPE, "void_type", "t", 0) /* The void type in C */ + +/* Integer types in all languages, including char in C. + Also used for sub-ranges of other discrete types. + Has components TYPE_MIN_VALUE, TYPE_MAX_VALUE (expressions, inclusive) + and TYPE_PRECISION (number of bits used by this type). + In the case of a subrange type in Pascal, the TREE_TYPE + of this will point at the supertype (another INTEGER_TYPE, + or an ENUMERAL_TYPE, CHAR_TYPE, or BOOLEAN_TYPE). + Otherwise, the TREE_TYPE is zero. */ +DEFTREECODE (INTEGER_TYPE, "integer_type", "t", 0) + +/* C's float and double. Different floating types are distinguished + by machine mode and by the TYPE_SIZE and the TYPE_PRECISION. */ +DEFTREECODE (REAL_TYPE, "real_type", "t", 0) + +/* Complex number types. The TREE_TYPE field is the data type + of the real and imaginary parts. */ +DEFTREECODE (COMPLEX_TYPE, "complex_type", "t", 0) + +/* C enums. The type node looks just like an INTEGER_TYPE node. + The symbols for the values of the enum type are defined by + CONST_DECL nodes, but the type does not point to them; + however, the TYPE_VALUES is a list in which each element's TREE_PURPOSE + is a name and the TREE_VALUE is the value (an INTEGER_CST node). */ +/* A forward reference `enum foo' when no enum named foo is defined yet + has zero (a null pointer) in its TYPE_SIZE. The tag name is in + the TYPE_NAME field. If the type is later defined, the normal + fields are filled in. + RECORD_TYPE, UNION_TYPE, and QUAL_UNION_TYPE forward refs are + treated similarly. */ +DEFTREECODE (ENUMERAL_TYPE, "enumeral_type", "t", 0) + +/* Pascal's boolean type (true or false are the only values); + no special fields needed. */ +DEFTREECODE (BOOLEAN_TYPE, "boolean_type", "t", 0) + +/* CHAR in Pascal; not used in C. + No special fields needed. */ +DEFTREECODE (CHAR_TYPE, "char_type", "t", 0) + +/* All pointer-to-x types have code POINTER_TYPE. + The TREE_TYPE points to the node for the type pointed to. */ +DEFTREECODE (POINTER_TYPE, "pointer_type", "t", 0) + +/* An offset is a pointer relative to an object. + The TREE_TYPE field is the type of the object at the offset. + The TYPE_OFFSET_BASETYPE points to the node for the type of object + that the offset is relative to. */ +DEFTREECODE (OFFSET_TYPE, "offset_type", "t", 0) + +/* A reference is like a pointer except that it is coerced + automatically to the value it points to. Used in C++. */ +DEFTREECODE (REFERENCE_TYPE, "reference_type", "t", 0) + +/* METHOD_TYPE is the type of a function which takes an extra first + argument for "self", which is not present in the declared argument list. + The TREE_TYPE is the return type of the method. The TYPE_METHOD_BASETYPE + is the type of "self". TYPE_ARG_TYPES is the real argument list, which + includes the hidden argument for "self". */ +DEFTREECODE (METHOD_TYPE, "method_type", "t", 0) + +/* Used for Pascal; details not determined right now. */ +DEFTREECODE (FILE_TYPE, "file_type", "t", 0) + +/* Types of arrays. Special fields: + TREE_TYPE Type of an array element. + TYPE_DOMAIN Type to index by. + Its range of values specifies the array length. + TYPE_SEP Expression for units from one elt to the next. + TYPE_SEP_UNIT Number of bits in a unit for previous. + The field TYPE_POINTER_TO (TREE_TYPE (array_type)) is always nonzero + and holds the type to coerce a value of that array type to in C. */ +/* Array types in C or Pascal */ +DEFTREECODE (ARRAY_TYPE, "array_type", "t", 0) + +/* Types of sets for Pascal. Special fields are the same as + in an array type. The target type is always a boolean type. */ +DEFTREECODE (SET_TYPE, "set_type", "t", 0) + +/* Not known whether Pascal really needs this + or what it should contain. */ +DEFTREECODE (STRING_TYPE, "string_type", "t", 0) + +/* Struct in C, or record in Pascal. */ +/* Special fields: + TYPE_FIELDS chain of FIELD_DECLs for the fields of the struct. + A few may need to be added for Pascal. */ +/* See the comment above, before ENUMERAL_TYPE, for how + forward references to struct tags are handled in C. */ +DEFTREECODE (RECORD_TYPE, "record_type", "t", 0) + +/* Union in C. Like a struct, except that the offsets of the fields + will all be zero. */ +/* See the comment above, before ENUMERAL_TYPE, for how + forward references to union tags are handled in C. */ +DEFTREECODE (UNION_TYPE, "union_type", "t", 0) /* C union type */ + +/* Similar to UNION_TYPE, except that the expressions in DECL_QUALIFIER + in each FIELD_DECL determine what the union contains. The first + field whose DECL_QUALIFIER expression is true is deemed to occupy + the union. */ +DEFTREECODE (QUAL_UNION_TYPE, "qual_union_type", "t", 0) + +/* Type of functions. Special fields: + TREE_TYPE type of value returned. + TYPE_ARG_TYPES list of types of arguments expected. + this list is made of TREE_LIST nodes. + Types of "Procedures" in languages where they are different from functions + have code FUNCTION_TYPE also, but then TREE_TYPE is zero or void type. */ +DEFTREECODE (FUNCTION_TYPE, "function_type", "t", 0) + +/* This is a language-specific kind of type. + Its meaning is defined by the language front end. + layout_type does not know how to lay this out, + so the front-end must do so manually. */ +DEFTREECODE (LANG_TYPE, "lang_type", "t", 0) + +/* Expressions */ + +/* First, the constants. */ + +/* Contents are in TREE_INT_CST_LOW and TREE_INT_CST_HIGH fields, + 32 bits each, giving us a 64 bit constant capability. + Note: constants of type char in Pascal are INTEGER_CST, + and so are pointer constants such as nil in Pascal or NULL in C. + `(int *) 1' in C also results in an INTEGER_CST. */ +DEFTREECODE (INTEGER_CST, "integer_cst", "c", 2) + +/* Contents are in TREE_REAL_CST field. Also there is TREE_CST_RTL. */ +DEFTREECODE (REAL_CST, "real_cst", "c", 3) + +/* Contents are in TREE_REALPART and TREE_IMAGPART fields, + whose contents are other constant nodes. + Also there is TREE_CST_RTL. */ +DEFTREECODE (COMPLEX_CST, "complex_cst", "c", 3) + +/* Contents are TREE_STRING_LENGTH and TREE_STRING_POINTER fields. + Also there is TREE_CST_RTL. */ +DEFTREECODE (STRING_CST, "string_cst", "c", 3) + +/* Declarations. All references to names are represented as ..._DECL nodes. + The decls in one binding context are chained through the TREE_CHAIN field. + Each DECL has a DECL_NAME field which contains an IDENTIFIER_NODE. + (Some decls, most often labels, may have zero as the DECL_NAME). + DECL_CONTEXT points to the node representing the context in which + this declaration has its scope. For FIELD_DECLs, this is the + RECORD_TYPE, UNION_TYPE, or QUAL_UNION_TYPE node that the field + is a member of. For VAR_DECL, PARM_DECL, FUNCTION_DECL, LABEL_DECL, + and CONST_DECL nodes, this points to the FUNCTION_DECL for the + containing function, or else yields NULL_TREE if the given decl + has "file scope". + DECL_ABSTRACT_ORIGIN, if non-NULL, points to the original (abstract) + ..._DECL node of which this decl is an (inlined or template expanded) + instance. + The TREE_TYPE field holds the data type of the object, when relevant. + LABEL_DECLs have no data type. For TYPE_DECL, the TREE_TYPE field + contents are the type whose name is being declared. + The DECL_ALIGN, DECL_SIZE, + and DECL_MODE fields exist in decl nodes just as in type nodes. + They are unused in LABEL_DECL, TYPE_DECL and CONST_DECL nodes. + + DECL_OFFSET holds an integer number of bits offset for the location. + DECL_VOFFSET holds an expression for a variable offset; it is + to be multiplied by DECL_VOFFSET_UNIT (an integer). + These fields are relevant only in FIELD_DECLs and PARM_DECLs. + + DECL_INITIAL holds the value to initialize a variable to, + or the value of a constant. For a function, it holds the body + (a node of type BLOCK representing the function's binding contour + and whose body contains the function's statements.) For a LABEL_DECL + in C, it is a flag, nonzero if the label's definition has been seen. + + PARM_DECLs use a special field: + DECL_ARG_TYPE is the type in which the argument is actually + passed, which may be different from its type within the function. + + FUNCTION_DECLs use four special fields: + DECL_ARGUMENTS holds a chain of PARM_DECL nodes for the arguments. + DECL_RESULT holds a RESULT_DECL node for the value of a function, + or it is 0 for a function that returns no value. + (C functions returning void have zero here.) + DECL_RESULT_TYPE holds the type in which the result is actually + returned. This is usually the same as the type of DECL_RESULT, + but (1) it may be a wider integer type and + (2) it remains valid, for the sake of inlining, even after the + function's compilation is done. + DECL_FUNCTION_CODE is a code number that is nonzero for + built-in functions. Its value is an enum built_in_function + that says which built-in function it is. + + DECL_SOURCE_FILE holds a filename string and DECL_SOURCE_LINE + holds a line number. In some cases these can be the location of + a reference, if no definition has been seen. + + DECL_ABSTRACT is non-zero if the decl represents an abstract instance + of a decl (i.e. one which is nested within an abstract instance of a + inline function. */ + +DEFTREECODE (FUNCTION_DECL, "function_decl", "d", 0) +DEFTREECODE (LABEL_DECL, "label_decl", "d", 0) +DEFTREECODE (CONST_DECL, "const_decl", "d", 0) +DEFTREECODE (TYPE_DECL, "type_decl", "d", 0) +DEFTREECODE (VAR_DECL, "var_decl", "d", 0) +DEFTREECODE (PARM_DECL, "parm_decl", "d", 0) +DEFTREECODE (RESULT_DECL, "result_decl", "d", 0) +DEFTREECODE (FIELD_DECL, "field_decl", "d", 0) + +/* References to storage. */ + +/* Value is structure or union component. + Operand 0 is the structure or union (an expression); + operand 1 is the field (a node of type FIELD_DECL). */ +DEFTREECODE (COMPONENT_REF, "component_ref", "r", 2) + +/* Reference to a group of bits within an object. Similar to COMPONENT_REF + except the position is given explicitly rather than via a FIELD_DECL. + Operand 0 is the structure or union expression; + operand 1 is a tree giving the number of bits being referenced; + operand 2 is a tree giving the position of the first referenced bit. + The field can be either a signed or unsigned field; + TREE_UNSIGNED says which. */ +DEFTREECODE (BIT_FIELD_REF, "bit_field_ref", "r", 3) + +/* C unary `*' or Pascal `^'. One operand, an expression for a pointer. */ +DEFTREECODE (INDIRECT_REF, "indirect_ref", "r", 1) + +/* Reference to the contents of an offset + (a value whose type is an OFFSET_TYPE). + Operand 0 is the object within which the offset is taken. + Operand 1 is the offset. */ +DEFTREECODE (OFFSET_REF, "offset_ref", "r", 2) + +/* Pascal `^` on a file. One operand, an expression for the file. */ +DEFTREECODE (BUFFER_REF, "buffer_ref", "r", 1) + +/* Array indexing in languages other than C. + Operand 0 is the array; operand 1 is a list of indices + stored as a chain of TREE_LIST nodes. */ +DEFTREECODE (ARRAY_REF, "array_ref", "r", 2) + +/* Constructor: return an aggregate value made from specified components. + In C, this is used only for structure and array initializers. + The first "operand" is really a pointer to the RTL, + for constant constructors only. + The second operand is a list of component values + made out of a chain of TREE_LIST nodes. */ +DEFTREECODE (CONSTRUCTOR, "constructor", "e", 2) + +/* The expression types are mostly straightforward, + with the fourth argument of DEFTREECODE saying + how many operands there are. + Unless otherwise specified, the operands are expressions. */ + +/* Contains two expressions to compute, one followed by the other. + the first value is ignored. The second one's value is used. */ +DEFTREECODE (COMPOUND_EXPR, "compound_expr", "e", 2) + +/* Assignment expression. Operand 0 is the what to set; 1, the new value. */ +DEFTREECODE (MODIFY_EXPR, "modify_expr", "e", 2) + +/* Initialization expression. Operand 0 is the variable to initialize; + Operand 1 is the initializer. */ +DEFTREECODE (INIT_EXPR, "init_expr", "e", 2) + +/* For TARGET_EXPR, operand 0 is the target of an initialization, + operand 1 is the initializer for the target, + and operand 2 is the cleanup for this node, if any. */ +DEFTREECODE (TARGET_EXPR, "target_expr", "e", 3) + +/* Conditional expression ( ... ? ... : ... in C). + Operand 0 is the condition. + Operand 1 is the then-value. + Operand 2 is the else-value. */ +DEFTREECODE (COND_EXPR, "cond_expr", "e", 3) + +/* Declare local variables, including making RTL and allocating space. + Operand 0 is a chain of VAR_DECL nodes for the variables. + Operand 1 is the body, the expression to be computed using + the variables. The value of operand 1 becomes that of the BIND_EXPR. + Operand 2 is the BLOCK that corresponds to these bindings + for debugging purposes. If this BIND_EXPR is actually expanded, + that sets the TREE_USED flag in the BLOCK. + + The BIND_EXPR is not responsible for informing parsers + about these variables. If the body is coming from the input file, + then the code that creates the BIND_EXPR is also responsible for + informing the parser of the variables. + + If the BIND_EXPR is ever expanded, its TREE_USED flag is set. + This tells the code for debugging symbol tables not to ignore the BIND_EXPR. + If the BIND_EXPR should be output for debugging but will not be expanded, + set the TREE_USED flag by hand. + + In order for the BIND_EXPR to be known at all, the code that creates it + must also install it as a subblock in the tree of BLOCK + nodes for the function. */ +DEFTREECODE (BIND_EXPR, "bind_expr", "e", 3) + +/* Function call. Operand 0 is the function. + Operand 1 is the argument list, a list of expressions + made out of a chain of TREE_LIST nodes. + There is no operand 2. That slot is used for the + CALL_EXPR_RTL macro (see preexpand_calls). */ +DEFTREECODE (CALL_EXPR, "call_expr", "e", 3) + +/* Call a method. Operand 0 is the method, whose type is a METHOD_TYPE. + Operand 1 is the expression for "self". + Operand 2 is the list of explicit arguments. */ +DEFTREECODE (METHOD_CALL_EXPR, "method_call_expr", "e", 4) + +/* Specify a value to compute along with its corresponding cleanup. + Operand 0 argument is an expression whose value needs a cleanup. + Operand 1 is an RTL_EXPR which will eventually represent that value. + Operand 2 is the cleanup expression for the object. + The RTL_EXPR is used in this expression, which is how the expression + manages to act on the proper value. + The cleanup is executed when the value is no longer needed, + which is not at precisely the same time that this value is computed. */ +DEFTREECODE (WITH_CLEANUP_EXPR, "with_cleanup_expr", "e", 3) + +/* Simple arithmetic. Operands must have the same machine mode + and the value shares that mode. */ +DEFTREECODE (PLUS_EXPR, "plus_expr", "2", 2) +DEFTREECODE (MINUS_EXPR, "minus_expr", "2", 2) +DEFTREECODE (MULT_EXPR, "mult_expr", "2", 2) + +/* Division for integer result that rounds the quotient toward zero. */ +/* Operands must have the same machine mode. + In principle they may be real, but that is not currently supported. + The result is always fixed point, and it has the same type as the + operands if they are fixed point. */ +DEFTREECODE (TRUNC_DIV_EXPR, "trunc_div_expr", "2", 2) + +/* Division for integer result that rounds the quotient toward infinity. */ +DEFTREECODE (CEIL_DIV_EXPR, "ceil_div_expr", "2", 2) + +/* Division for integer result that rounds toward minus infinity. */ +DEFTREECODE (FLOOR_DIV_EXPR, "floor_div_expr", "2", 2) + +/* Division for integer result that rounds toward nearest integer. */ +DEFTREECODE (ROUND_DIV_EXPR, "round_div_expr", "2", 2) + +/* Four kinds of remainder that go with the four kinds of division. */ +DEFTREECODE (TRUNC_MOD_EXPR, "trunc_mod_expr", "2", 2) +DEFTREECODE (CEIL_MOD_EXPR, "ceil_mod_expr", "2", 2) +DEFTREECODE (FLOOR_MOD_EXPR, "floor_mod_expr", "2", 2) +DEFTREECODE (ROUND_MOD_EXPR, "round_mod_expr", "2", 2) + +/* Division for real result. The two operands must have the same type. + In principle they could be integers, but currently only real + operands are supported. The result must have the same type + as the operands. */ +DEFTREECODE (RDIV_EXPR, "rdiv_expr", "2", 2) + +/* Division which is not supposed to need rounding. + Used for pointer subtraction in C. */ +DEFTREECODE (EXACT_DIV_EXPR, "exact_div_expr", "2", 2) + +/* Conversion of real to fixed point: four ways to round, + like the four ways to divide. + CONVERT_EXPR can also be used to convert a real to an integer, + and that is what is used in languages that do not have ways of + specifying which of these is wanted. Maybe these are not needed. */ +DEFTREECODE (FIX_TRUNC_EXPR, "fix_trunc_expr", "1", 1) +DEFTREECODE (FIX_CEIL_EXPR, "fix_ceil_expr", "1", 1) +DEFTREECODE (FIX_FLOOR_EXPR, "fix_floor_expr", "1", 1) +DEFTREECODE (FIX_ROUND_EXPR, "fix_round_expr", "1", 1) + +/* Conversion of an integer to a real. */ +DEFTREECODE (FLOAT_EXPR, "float_expr", "1", 1) + +/* Exponentiation. Operands may have any types; + constraints on value type are not known yet. */ +DEFTREECODE (EXPON_EXPR, "expon_expr", "2", 2) + +/* Unary negation. Value has same type as operand. */ +DEFTREECODE (NEGATE_EXPR, "negate_expr", "1", 1) + +DEFTREECODE (MIN_EXPR, "min_expr", "2", 2) +DEFTREECODE (MAX_EXPR, "max_expr", "2", 2) +DEFTREECODE (ABS_EXPR, "abs_expr", "1", 1) +DEFTREECODE (FFS_EXPR, "ffs_expr", "1", 1) + +/* Shift operations for shift and rotate. + Shift is supposed to mean logical shift if done on an + unsigned type, arithmetic shift on a signed type. + The second operand is the number of bits to + shift by, and must always have mode SImode. + The result has the same mode as the first operand. */ +DEFTREECODE (LSHIFT_EXPR, "alshift_expr", "2", 2) +DEFTREECODE (RSHIFT_EXPR, "arshift_expr", "2", 2) +DEFTREECODE (LROTATE_EXPR, "lrotate_expr", "2", 2) +DEFTREECODE (RROTATE_EXPR, "rrotate_expr", "2", 2) + +/* Bitwise operations. Operands have same mode as result. */ +DEFTREECODE (BIT_IOR_EXPR, "bit_ior_expr", "2", 2) +DEFTREECODE (BIT_XOR_EXPR, "bit_xor_expr", "2", 2) +DEFTREECODE (BIT_AND_EXPR, "bit_and_expr", "2", 2) +DEFTREECODE (BIT_ANDTC_EXPR, "bit_andtc_expr", "2", 2) +DEFTREECODE (BIT_NOT_EXPR, "bit_not_expr", "1", 1) + +/* Combination of boolean values or of integers considered only + as zero or nonzero. ANDIF and ORIF allow the second operand + not to be computed if the value of the expression is determined + from the first operand. AND, OR, and XOR always compute the second + operand whether its value is needed or not (for side effects). */ +DEFTREECODE (TRUTH_ANDIF_EXPR, "truth_andif_expr", "e", 2) +DEFTREECODE (TRUTH_ORIF_EXPR, "truth_orif_expr", "e", 2) +DEFTREECODE (TRUTH_AND_EXPR, "truth_and_expr", "2", 2) +DEFTREECODE (TRUTH_OR_EXPR, "truth_or_expr", "2", 2) +DEFTREECODE (TRUTH_XOR_EXPR, "truth_xor_expr", "2", 2) +DEFTREECODE (TRUTH_NOT_EXPR, "truth_not_expr", "e", 1) + +/* Relational operators. + `EQ_EXPR' and `NE_EXPR' are allowed for any types. + The others are allowed only for integer (or pointer or enumeral) + or real types. + In all cases the operands will have the same type, + and the value is always the type used by the language for booleans. */ +DEFTREECODE (LT_EXPR, "lt_expr", "<", 2) +DEFTREECODE (LE_EXPR, "le_expr", "<", 2) +DEFTREECODE (GT_EXPR, "gt_expr", "<", 2) +DEFTREECODE (GE_EXPR, "ge_expr", "<", 2) +DEFTREECODE (EQ_EXPR, "eq_expr", "<", 2) +DEFTREECODE (NE_EXPR, "ne_expr", "<", 2) + +/* Operations for Pascal sets. Not used now. */ +DEFTREECODE (IN_EXPR, "in_expr", "2", 2) +DEFTREECODE (SET_LE_EXPR, "set_le_expr", "<", 2) +DEFTREECODE (CARD_EXPR, "card_expr", "1", 1) +DEFTREECODE (RANGE_EXPR, "range_expr", "2", 2) + +/* Represents a conversion of type of a value. + All conversions, including implicit ones, must be + represented by CONVERT_EXPR nodes. */ +DEFTREECODE (CONVERT_EXPR, "convert_expr", "1", 1) + +/* Represents a conversion expected to require no code to be generated. */ +DEFTREECODE (NOP_EXPR, "nop_expr", "1", 1) + +/* Value is same as argument, but guaranteed not an lvalue. */ +DEFTREECODE (NON_LVALUE_EXPR, "non_lvalue_expr", "1", 1) + +/* Represents something we computed once and will use multiple times. + First operand is that expression. Second is the function decl + in which the SAVE_EXPR was created. The third operand is the RTL, + nonzero only after the expression has been computed. */ +DEFTREECODE (SAVE_EXPR, "save_expr", "e", 3) + +/* Represents something whose RTL has already been expanded + as a sequence which should be emitted when this expression is expanded. + The first operand is the RTL to emit. It is the first of a chain of insns. + The second is the RTL expression for the result. */ +DEFTREECODE (RTL_EXPR, "rtl_expr", "e", 2) + +/* & in C. Value is the address at which the operand's value resides. + Operand may have any mode. Result mode is Pmode. */ +DEFTREECODE (ADDR_EXPR, "addr_expr", "e", 1) + +/* Non-lvalue reference or pointer to an object. */ +DEFTREECODE (REFERENCE_EXPR, "reference_expr", "e", 1) + +/* Operand is a function constant; result is a function variable value + of typeEPmode. Used only for languages that need static chains. */ +DEFTREECODE (ENTRY_VALUE_EXPR, "entry_value_expr", "e", 1) + +/* Given two real or integer operands of the same type, + returns a complex value of the corresponding complex type. */ +DEFTREECODE (COMPLEX_EXPR, "complex_expr", "2", 2) + +/* Complex conjugate of operand. Used only on complex types. + The value has the same type as the operand. */ +DEFTREECODE (CONJ_EXPR, "conj_expr", "1", 1) + +/* Used only on an operand of complex type, these return + a value of the corresponding component type. */ +DEFTREECODE (REALPART_EXPR, "realpart_expr", "1", 1) +DEFTREECODE (IMAGPART_EXPR, "imagpart_expr", "1", 1) + +/* Nodes for ++ and -- in C. + The second arg is how much to increment or decrement by. + For a pointer, it would be the size of the object pointed to. */ +DEFTREECODE (PREDECREMENT_EXPR, "predecrement_expr", "e", 2) +DEFTREECODE (PREINCREMENT_EXPR, "preincrement_expr", "e", 2) +DEFTREECODE (POSTDECREMENT_EXPR, "postdecrement_expr", "e", 2) +DEFTREECODE (POSTINCREMENT_EXPR, "postincrement_expr", "e", 2) + +/* These types of expressions have no useful value, + and always have side effects. */ + +/* A label definition, encapsulated as a statement. + Operand 0 is the LABEL_DECL node for the label that appears here. + The type should be void and the value should be ignored. */ +DEFTREECODE (LABEL_EXPR, "label_expr", "s", 1) + +/* GOTO. Operand 0 is a LABEL_DECL node. + The type should be void and the value should be ignored. */ +DEFTREECODE (GOTO_EXPR, "goto_expr", "s", 1) + +/* RETURN. Evaluates operand 0, then returns from the current function. + Presumably that operand is an assignment that stores into the + RESULT_DECL that hold the value to be returned. + The operand may be null. + The type should be void and the value should be ignored. */ +DEFTREECODE (RETURN_EXPR, "return_expr", "s", 1) + +/* Exit the inner most loop conditionally. Operand 0 is the condition. + The type should be void and the value should be ignored. */ +DEFTREECODE (EXIT_EXPR, "exit_expr", "s", 1) + +/* A loop. Operand 0 is the body of the loop. + It must contain an EXIT_EXPR or is an infinite loop. + The type should be void and the value should be ignored. */ +DEFTREECODE (LOOP_EXPR, "loop_expr", "s", 1) + +/* +Local variables: +mode:c +version-control: t +End: +*/ diff --git a/gnu/usr.bin/cc/lib/tree.h b/gnu/usr.bin/cc/lib/tree.h new file mode 100644 index 000000000000..556dac0ecfb0 --- /dev/null +++ b/gnu/usr.bin/cc/lib/tree.h @@ -0,0 +1,1507 @@ +/* Front-end tree definitions for GNU compiler. + Copyright (C) 1989 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include "machmode.h" + +/* codes of tree nodes */ + +#define DEFTREECODE(SYM, STRING, TYPE, NARGS) SYM, + +enum tree_code { +#include "tree.def" + + LAST_AND_UNUSED_TREE_CODE /* A convenient way to get a value for + NUM_TREE_CODE. */ +}; + +#undef DEFTREECODE + +/* Number of tree codes. */ +#define NUM_TREE_CODES ((int)LAST_AND_UNUSED_TREE_CODE) + +/* Indexed by enum tree_code, contains a character which is + `<' for a comparison expression, `1', for a unary arithmetic + expression, `2' for a binary arithmetic expression, `e' for + other types of expressions, `r' for a reference, `c' for a + constant, `d' for a decl, `t' for a type, `s' for a statement, + and `x' for anything else (TREE_LIST, IDENTIFIER, etc). */ + +extern char **tree_code_type; +#define TREE_CODE_CLASS(CODE) (*tree_code_type[(int) (CODE)]) + +/* Number of argument-words in each kind of tree-node. */ + +extern int *tree_code_length; + +/* Names of tree components. */ + +extern char **tree_code_name; + +/* Codes that identify the various built in functions + so that expand_call can identify them quickly. */ + +enum built_in_function +{ + NOT_BUILT_IN, + BUILT_IN_ALLOCA, + BUILT_IN_ABS, + BUILT_IN_FABS, + BUILT_IN_LABS, + BUILT_IN_FFS, + BUILT_IN_DIV, + BUILT_IN_LDIV, + BUILT_IN_FFLOOR, + BUILT_IN_FCEIL, + BUILT_IN_FMOD, + BUILT_IN_FREM, + BUILT_IN_MEMCPY, + BUILT_IN_MEMCMP, + BUILT_IN_MEMSET, + BUILT_IN_STRCPY, + BUILT_IN_STRCMP, + BUILT_IN_STRLEN, + BUILT_IN_FSQRT, + BUILT_IN_SIN, + BUILT_IN_COS, + BUILT_IN_GETEXP, + BUILT_IN_GETMAN, + BUILT_IN_SAVEREGS, + BUILT_IN_CLASSIFY_TYPE, + BUILT_IN_NEXT_ARG, + BUILT_IN_ARGS_INFO, + BUILT_IN_CONSTANT_P, + BUILT_IN_FRAME_ADDRESS, + BUILT_IN_RETURN_ADDRESS, + BUILT_IN_CALLER_RETURN_ADDRESS, + BUILT_IN_APPLY_ARGS, + BUILT_IN_APPLY, + BUILT_IN_RETURN, + + /* C++ extensions */ + BUILT_IN_NEW, + BUILT_IN_VEC_NEW, + BUILT_IN_DELETE, + BUILT_IN_VEC_DELETE +}; + +/* The definition of tree nodes fills the next several pages. */ + +/* A tree node can represent a data type, a variable, an expression + or a statement. Each node has a TREE_CODE which says what kind of + thing it represents. Some common codes are: + INTEGER_TYPE -- represents a type of integers. + ARRAY_TYPE -- represents a type of pointer. + VAR_DECL -- represents a declared variable. + INTEGER_CST -- represents a constant integer value. + PLUS_EXPR -- represents a sum (an expression). + + As for the contents of a tree node: there are some fields + that all nodes share. Each TREE_CODE has various special-purpose + fields as well. The fields of a node are never accessed directly, + always through accessor macros. */ + +/* This type is used everywhere to refer to a tree node. */ + +typedef union tree_node *tree; + +/* Every kind of tree node starts with this structure, + so all nodes have these fields. + + See the accessor macros, defined below, for documentation of the fields. */ + +struct tree_common +{ + union tree_node *chain; + union tree_node *type; +#ifdef ONLY_INT_FIELDS + unsigned int code : 8; +#else + enum tree_code code : 8; +#endif + + unsigned side_effects_flag : 1; + unsigned constant_flag : 1; + unsigned permanent_flag : 1; + unsigned addressable_flag : 1; + unsigned volatile_flag : 1; + unsigned readonly_flag : 1; + unsigned unsigned_flag : 1; + unsigned asm_written_flag: 1; + + unsigned used_flag : 1; + unsigned raises_flag : 1; + unsigned static_flag : 1; + unsigned public_flag : 1; + unsigned private_flag : 1; + unsigned protected_flag : 1; + + unsigned lang_flag_0 : 1; + unsigned lang_flag_1 : 1; + unsigned lang_flag_2 : 1; + unsigned lang_flag_3 : 1; + unsigned lang_flag_4 : 1; + unsigned lang_flag_5 : 1; + unsigned lang_flag_6 : 1; + /* There is room for two more flags. */ +}; + +/* Define accessors for the fields that all tree nodes have + (though some fields are not used for all kinds of nodes). */ + +/* The tree-code says what kind of node it is. + Codes are defined in tree.def. */ +#define TREE_CODE(NODE) ((enum tree_code) (NODE)->common.code) +#define TREE_SET_CODE(NODE, VALUE) ((NODE)->common.code = (int) (VALUE)) + +/* In all nodes that are expressions, this is the data type of the expression. + In POINTER_TYPE nodes, this is the type that the pointer points to. + In ARRAY_TYPE nodes, this is the type of the elements. */ +#define TREE_TYPE(NODE) ((NODE)->common.type) + +/* Nodes are chained together for many purposes. + Types are chained together to record them for being output to the debugger + (see the function `chain_type'). + Decls in the same scope are chained together to record the contents + of the scope. + Statement nodes for successive statements used to be chained together. + Often lists of things are represented by TREE_LIST nodes that + are chained together. */ + +#define TREE_CHAIN(NODE) ((NODE)->common.chain) + +/* Given an expression as a tree, strip any NON_LVALUE_EXPRs and NOP_EXPRs + that don't change the machine mode. */ + +#define STRIP_NOPS(EXP) \ + while ((TREE_CODE (EXP) == NOP_EXPR \ + || TREE_CODE (EXP) == CONVERT_EXPR \ + || TREE_CODE (EXP) == NON_LVALUE_EXPR) \ + && (TYPE_MODE (TREE_TYPE (EXP)) \ + == TYPE_MODE (TREE_TYPE (TREE_OPERAND (EXP, 0))))) \ + (EXP) = TREE_OPERAND (EXP, 0); + +/* Like STRIP_NOPS, but don't alter the TREE_TYPE either. */ + +#define STRIP_TYPE_NOPS(EXP) \ + while ((TREE_CODE (EXP) == NOP_EXPR \ + || TREE_CODE (EXP) == CONVERT_EXPR \ + || TREE_CODE (EXP) == NON_LVALUE_EXPR) \ + && (TREE_TYPE (EXP) \ + == TREE_TYPE (TREE_OPERAND (EXP, 0)))) \ + (EXP) = TREE_OPERAND (EXP, 0); + +/* Nonzero if TYPE represents an integral type. Note that we do not + include COMPLEX types here. */ + +#define INTEGRAL_TYPE_P(TYPE) \ + (TREE_CODE (TYPE) == INTEGER_TYPE || TREE_CODE (TYPE) == ENUMERAL_TYPE \ + || TREE_CODE (TYPE) == BOOLEAN_TYPE || TREE_CODE (TYPE) == CHAR_TYPE) + +/* Nonzero if TYPE represents a floating-point type, including complex + floating-point types. */ + +#define FLOAT_TYPE_P(TYPE) \ + (TREE_CODE (TYPE) == REAL_TYPE \ + || (TREE_CODE (TYPE) == COMPLEX_TYPE \ + && TREE_CODE (TREE_TYPE (TYPE)) == REAL_TYPE)) + +/* Define many boolean fields that all tree nodes have. */ + +/* In VAR_DECL nodes, nonzero means address of this is needed. + So it cannot be in a register. + In a FUNCTION_DECL, nonzero means its address is needed. + So it must be compiled even if it is an inline function. + In CONSTRUCTOR nodes, it means object constructed must be in memory. + In LABEL_DECL nodes, it means a goto for this label has been seen + from a place outside all binding contours that restore stack levels. + In ..._TYPE nodes, it means that objects of this type must + be fully addressable. This means that pieces of this + object cannot go into register parameters, for example. + In IDENTIFIER_NODEs, this means that some extern decl for this name + had its address taken. That matters for inline functions. */ +#define TREE_ADDRESSABLE(NODE) ((NODE)->common.addressable_flag) + +/* In a VAR_DECL, nonzero means allocate static storage. + In a FUNCTION_DECL, nonzero if function has been defined. + In a CONSTRUCTOR, nonzero means allocate static storage. */ +#define TREE_STATIC(NODE) ((NODE)->common.static_flag) + +/* In a CONVERT_EXPR or NOP_EXPR, this means the node was made + implicitly and should not lead to an "unused value" warning. */ +#define TREE_NO_UNUSED_WARNING(NODE) ((NODE)->common.static_flag) + +/* In an INTEGER_CST, this means there was overflow in folding. */ +#define TREE_CONSTANT_OVERFLOW(NODE) ((NODE)->common.static_flag) + +/* Nonzero for a TREE_LIST or TREE_VEC node means that the derivation + chain is via a `virtual' declaration. */ +#define TREE_VIA_VIRTUAL(NODE) ((NODE)->common.static_flag) + +/* In a VAR_DECL or FUNCTION_DECL, + nonzero means name is to be accessible from outside this module. + In an identifier node, nonzero means an external declaration + accessible from outside this module was previously seen + for this name in an inner scope. */ +#define TREE_PUBLIC(NODE) ((NODE)->common.public_flag) + +/* Nonzero for TREE_LIST or TREE_VEC node means that the path to the + base class is via a `public' declaration, which preserves public + fields from the base class as public. */ +#define TREE_VIA_PUBLIC(NODE) ((NODE)->common.public_flag) + +/* Ditto, for `private' declarations. */ +#define TREE_VIA_PRIVATE(NODE) ((NODE)->common.private_flag) + +/* Nonzero for TREE_LIST node means that the path to the + base class is via a `protected' declaration, which preserves + protected fields from the base class as protected. + OVERLOADED. */ +#define TREE_VIA_PROTECTED(NODE) ((NODE)->common.protected_flag) + +/* In any expression, nonzero means it has side effects or reevaluation + of the whole expression could produce a different value. + This is set if any subexpression is a function call, a side effect + or a reference to a volatile variable. + In a ..._DECL, this is set only if the declaration said `volatile'. */ +#define TREE_SIDE_EFFECTS(NODE) ((NODE)->common.side_effects_flag) + +/* Nonzero means this expression is volatile in the C sense: + its address should be of type `volatile WHATEVER *'. + In other words, the declared item is volatile qualified. + This is used in _DECL nodes and _REF nodes. + + In a ..._TYPE node, means this type is volatile-qualified. + But use TYPE_VOLATILE instead of this macro when the node is a type, + because eventually we may make that a different bit. + + If this bit is set in an expression, so is TREE_SIDE_EFFECTS. */ +#define TREE_THIS_VOLATILE(NODE) ((NODE)->common.volatile_flag) + +/* In a VAR_DECL, PARM_DECL or FIELD_DECL, or any kind of ..._REF node, + nonzero means it may not be the lhs of an assignment. + In a ..._TYPE node, means this type is const-qualified + (but the macro TYPE_READONLY should be used instead of this macro + when the node is a type). */ +#define TREE_READONLY(NODE) ((NODE)->common.readonly_flag) + +/* Value of expression is constant. + Always appears in all ..._CST nodes. + May also appear in an arithmetic expression, an ADDR_EXPR or a CONSTRUCTOR + if the value is constant. */ +#define TREE_CONSTANT(NODE) ((NODE)->common.constant_flag) + +/* Nonzero means permanent node; + node will continue to exist for the entire compiler run. + Otherwise it will be recycled at the end of the function. */ +#define TREE_PERMANENT(NODE) ((NODE)->common.permanent_flag) + +/* In INTEGER_TYPE or ENUMERAL_TYPE nodes, means an unsigned type. + In FIELD_DECL nodes, means an unsigned bit field. + The same bit is used in functions as DECL_BUILT_IN_NONANSI. */ +#define TREE_UNSIGNED(NODE) ((NODE)->common.unsigned_flag) + +/* Nonzero in a VAR_DECL means assembler code has been written. + Nonzero in a FUNCTION_DECL means that the function has been compiled. + This is interesting in an inline function, since it might not need + to be compiled separately. + Nonzero in a RECORD_TYPE, UNION_TYPE, QUAL_UNION_TYPE or ENUMERAL_TYPE + if the sdb debugging info for the type has been written. + In a BLOCK node, nonzero if reorder_blocks has already seen this block. */ +#define TREE_ASM_WRITTEN(NODE) ((NODE)->common.asm_written_flag) + +/* Nonzero in a _DECL if the name is used in its scope. + Nonzero in an expr node means inhibit warning if value is unused. + In IDENTIFIER_NODEs, this means that some extern decl for this name + was used. */ +#define TREE_USED(NODE) ((NODE)->common.used_flag) + +/* Nonzero for a tree node whose evaluation could result + in the raising of an exception. Not implemented yet. */ +#define TREE_RAISES(NODE) ((NODE)->common.raises_flag) + +/* Used in classes in C++. */ +#define TREE_PRIVATE(NODE) ((NODE)->common.private_flag) +/* Used in classes in C++. + In a BLOCK node, this is BLOCK_HANDLER_BLOCK. */ +#define TREE_PROTECTED(NODE) ((NODE)->common.protected_flag) + +/* These flags are available for each language front end to use internally. */ +#define TREE_LANG_FLAG_0(NODE) ((NODE)->common.lang_flag_0) +#define TREE_LANG_FLAG_1(NODE) ((NODE)->common.lang_flag_1) +#define TREE_LANG_FLAG_2(NODE) ((NODE)->common.lang_flag_2) +#define TREE_LANG_FLAG_3(NODE) ((NODE)->common.lang_flag_3) +#define TREE_LANG_FLAG_4(NODE) ((NODE)->common.lang_flag_4) +#define TREE_LANG_FLAG_5(NODE) ((NODE)->common.lang_flag_5) +#define TREE_LANG_FLAG_6(NODE) ((NODE)->common.lang_flag_6) + +/* Define additional fields and accessors for nodes representing constants. */ + +/* In an INTEGER_CST node. These two together make a 2-word integer. + If the data type is signed, the value is sign-extended to 2 words + even though not all of them may really be in use. + In an unsigned constant shorter than 2 words, the extra bits are 0. */ +#define TREE_INT_CST_LOW(NODE) ((NODE)->int_cst.int_cst_low) +#define TREE_INT_CST_HIGH(NODE) ((NODE)->int_cst.int_cst_high) + +#define INT_CST_LT(A, B) \ +(TREE_INT_CST_HIGH (A) < TREE_INT_CST_HIGH (B) \ + || (TREE_INT_CST_HIGH (A) == TREE_INT_CST_HIGH (B) \ + && ((unsigned HOST_WIDE_INT) TREE_INT_CST_LOW (A) \ + < (unsigned HOST_WIDE_INT) TREE_INT_CST_LOW (B)))) + +#define INT_CST_LT_UNSIGNED(A, B) \ +(((unsigned HOST_WIDE_INT) TREE_INT_CST_HIGH (A) \ + < (unsigned HOST_WIDE_INT) TREE_INT_CST_HIGH (B)) \ + || (((unsigned HOST_WIDE_INT) TREE_INT_CST_HIGH (A) \ + == (unsigned HOST_WIDE_INT ) TREE_INT_CST_HIGH (B)) \ + && (((unsigned HOST_WIDE_INT) TREE_INT_CST_LOW (A) \ + < (unsigned HOST_WIDE_INT) TREE_INT_CST_LOW (B))))) + +struct tree_int_cst +{ + char common[sizeof (struct tree_common)]; + HOST_WIDE_INT int_cst_low; + HOST_WIDE_INT int_cst_high; +}; + +/* In REAL_CST, STRING_CST, COMPLEX_CST nodes, and CONSTRUCTOR nodes, + and generally in all kinds of constants that could + be given labels (rather than being immediate). */ + +#define TREE_CST_RTL(NODE) ((NODE)->real_cst.rtl) + +/* In a REAL_CST node. */ +/* We can represent a real value as either a `double' or a string. + Strings don't allow for any optimization, but they do allow + for cross-compilation. */ + +#define TREE_REAL_CST(NODE) ((NODE)->real_cst.real_cst) + +#include "real.h" + +struct tree_real_cst +{ + char common[sizeof (struct tree_common)]; + struct rtx_def *rtl; /* acts as link to register transfer language + (rtl) info */ + REAL_VALUE_TYPE real_cst; +}; + +/* In a STRING_CST */ +#define TREE_STRING_LENGTH(NODE) ((NODE)->string.length) +#define TREE_STRING_POINTER(NODE) ((NODE)->string.pointer) + +struct tree_string +{ + char common[sizeof (struct tree_common)]; + struct rtx_def *rtl; /* acts as link to register transfer language + (rtl) info */ + int length; + char *pointer; +}; + +/* In a COMPLEX_CST node. */ +#define TREE_REALPART(NODE) ((NODE)->complex.real) +#define TREE_IMAGPART(NODE) ((NODE)->complex.imag) + +struct tree_complex +{ + char common[sizeof (struct tree_common)]; + struct rtx_def *rtl; /* acts as link to register transfer language + (rtl) info */ + union tree_node *real; + union tree_node *imag; +}; + +/* Define fields and accessors for some special-purpose tree nodes. */ + +#define IDENTIFIER_LENGTH(NODE) ((NODE)->identifier.length) +#define IDENTIFIER_POINTER(NODE) ((NODE)->identifier.pointer) + +struct tree_identifier +{ + char common[sizeof (struct tree_common)]; + int length; + char *pointer; +}; + +/* In a TREE_LIST node. */ +#define TREE_PURPOSE(NODE) ((NODE)->list.purpose) +#define TREE_VALUE(NODE) ((NODE)->list.value) + +struct tree_list +{ + char common[sizeof (struct tree_common)]; + union tree_node *purpose; + union tree_node *value; +}; + +/* In a TREE_VEC node. */ +#define TREE_VEC_LENGTH(NODE) ((NODE)->vec.length) +#define TREE_VEC_ELT(NODE,I) ((NODE)->vec.a[I]) +#define TREE_VEC_END(NODE) (&((NODE)->vec.a[(NODE)->vec.length])) + +struct tree_vec +{ + char common[sizeof (struct tree_common)]; + int length; + union tree_node *a[1]; +}; + +/* Define fields and accessors for some nodes that represent expressions. */ + +/* In a SAVE_EXPR node. */ +#define SAVE_EXPR_CONTEXT(NODE) TREE_OPERAND(NODE, 1) +#define SAVE_EXPR_RTL(NODE) (*(struct rtx_def **) &(NODE)->exp.operands[2]) + +/* In a RTL_EXPR node. */ +#define RTL_EXPR_SEQUENCE(NODE) (*(struct rtx_def **) &(NODE)->exp.operands[0]) +#define RTL_EXPR_RTL(NODE) (*(struct rtx_def **) &(NODE)->exp.operands[1]) + +/* In a CALL_EXPR node. */ +#define CALL_EXPR_RTL(NODE) (*(struct rtx_def **) &(NODE)->exp.operands[2]) + +/* In a CONSTRUCTOR node. */ +#define CONSTRUCTOR_ELTS(NODE) TREE_OPERAND (NODE, 1) + +/* In ordinary expression nodes. */ +#define TREE_OPERAND(NODE, I) ((NODE)->exp.operands[I]) +#define TREE_COMPLEXITY(NODE) ((NODE)->exp.complexity) + +struct tree_exp +{ + char common[sizeof (struct tree_common)]; + int complexity; + union tree_node *operands[1]; +}; + +/* In a BLOCK node. */ +#define BLOCK_VARS(NODE) ((NODE)->block.vars) +#define BLOCK_TYPE_TAGS(NODE) ((NODE)->block.type_tags) +#define BLOCK_SUBBLOCKS(NODE) ((NODE)->block.subblocks) +#define BLOCK_SUPERCONTEXT(NODE) ((NODE)->block.supercontext) +/* Note: when changing this, make sure to find the places + that use chainon or nreverse. */ +#define BLOCK_CHAIN(NODE) TREE_CHAIN (NODE) +#define BLOCK_ABSTRACT_ORIGIN(NODE) ((NODE)->block.abstract_origin) +#define BLOCK_ABSTRACT(NODE) ((NODE)->block.abstract_flag) +#define BLOCK_END_NOTE(NODE) ((NODE)->block.end_note) + +/* Nonzero means that this block is prepared to handle exceptions + listed in the BLOCK_VARS slot. */ +#define BLOCK_HANDLER_BLOCK(NODE) ((NODE)->block.handler_block_flag) + +struct tree_block +{ + char common[sizeof (struct tree_common)]; + + unsigned handler_block_flag : 1; + unsigned abstract_flag : 1; + + union tree_node *vars; + union tree_node *type_tags; + union tree_node *subblocks; + union tree_node *supercontext; + union tree_node *abstract_origin; + struct rtx_def *end_note; +}; + +/* Define fields and accessors for nodes representing data types. */ + +/* See tree.def for documentation of the use of these fields. + Look at the documentation of the various ..._TYPE tree codes. */ + +#define TYPE_UID(NODE) ((NODE)->type.uid) +#define TYPE_SIZE(NODE) ((NODE)->type.size) +#define TYPE_MODE(NODE) ((NODE)->type.mode) +#define TYPE_VALUES(NODE) ((NODE)->type.values) +#define TYPE_DOMAIN(NODE) ((NODE)->type.values) +#define TYPE_FIELDS(NODE) ((NODE)->type.values) +#define TYPE_METHODS(NODE) ((NODE)->type.maxval) +#define TYPE_VFIELD(NODE) ((NODE)->type.minval) +#define TYPE_ARG_TYPES(NODE) ((NODE)->type.values) +#define TYPE_METHOD_BASETYPE(NODE) ((NODE)->type.maxval) +#define TYPE_OFFSET_BASETYPE(NODE) ((NODE)->type.maxval) +#define TYPE_POINTER_TO(NODE) ((NODE)->type.pointer_to) +#define TYPE_REFERENCE_TO(NODE) ((NODE)->type.reference_to) +#define TYPE_MIN_VALUE(NODE) ((NODE)->type.minval) +#define TYPE_MAX_VALUE(NODE) ((NODE)->type.maxval) +#define TYPE_PRECISION(NODE) ((NODE)->type.precision) +#define TYPE_PARSE_INFO(NODE) ((NODE)->type.parse_info) +#define TYPE_SYMTAB_ADDRESS(NODE) ((NODE)->type.symtab_address) +#define TYPE_NAME(NODE) ((NODE)->type.name) +#define TYPE_NEXT_VARIANT(NODE) ((NODE)->type.next_variant) +#define TYPE_MAIN_VARIANT(NODE) ((NODE)->type.main_variant) +#define TYPE_BINFO(NODE) ((NODE)->type.binfo) +#define TYPE_NONCOPIED_PARTS(NODE) ((NODE)->type.noncopied_parts) +#define TYPE_CONTEXT(NODE) ((NODE)->type.context) +#define TYPE_LANG_SPECIFIC(NODE) ((NODE)->type.lang_specific) + +/* The alignment necessary for objects of this type. + The value is an int, measured in bits. */ +#define TYPE_ALIGN(NODE) ((NODE)->type.align) + +#define TYPE_STUB_DECL(NODE) (TREE_CHAIN (NODE)) + +/* In a RECORD_TYPE, UNION_TYPE or QUAL_UNION_TYPE, it means the type + has BLKmode only because it lacks the alignment requirement for + its size. */ +#define TYPE_NO_FORCE_BLK(NODE) ((NODE)->type.no_force_blk_flag) + +/* Nonzero in a type considered volatile as a whole. */ +#define TYPE_VOLATILE(NODE) ((NODE)->common.volatile_flag) + +/* Means this type is const-qualified. */ +#define TYPE_READONLY(NODE) ((NODE)->common.readonly_flag) + +/* These flags are available for each language front end to use internally. */ +#define TYPE_LANG_FLAG_0(NODE) ((NODE)->type.lang_flag_0) +#define TYPE_LANG_FLAG_1(NODE) ((NODE)->type.lang_flag_1) +#define TYPE_LANG_FLAG_2(NODE) ((NODE)->type.lang_flag_2) +#define TYPE_LANG_FLAG_3(NODE) ((NODE)->type.lang_flag_3) +#define TYPE_LANG_FLAG_4(NODE) ((NODE)->type.lang_flag_4) +#define TYPE_LANG_FLAG_5(NODE) ((NODE)->type.lang_flag_5) +#define TYPE_LANG_FLAG_6(NODE) ((NODE)->type.lang_flag_6) + +struct tree_type +{ + char common[sizeof (struct tree_common)]; + union tree_node *values; + union tree_node *size; + unsigned uid; + +#ifdef ONLY_INT_FIELDS + int mode : 8; +#else + enum machine_mode mode : 8; +#endif + unsigned char precision; + + unsigned no_force_blk_flag : 1; + unsigned lang_flag_0 : 1; + unsigned lang_flag_1 : 1; + unsigned lang_flag_2 : 1; + unsigned lang_flag_3 : 1; + unsigned lang_flag_4 : 1; + unsigned lang_flag_5 : 1; + unsigned lang_flag_6 : 1; + + unsigned int align; + union tree_node *pointer_to; + union tree_node *reference_to; + int parse_info; + int symtab_address; + union tree_node *name; + union tree_node *minval; + union tree_node *maxval; + union tree_node *next_variant; + union tree_node *main_variant; + union tree_node *binfo; + union tree_node *noncopied_parts; + union tree_node *context; + /* Points to a structure whose details depend on the language in use. */ + struct lang_type *lang_specific; +}; + +/* Define accessor macros for information about type inheritance + and basetypes. + + A "basetype" means a particular usage of a data type for inheritance + in another type. Each such basetype usage has its own "binfo" + object to describe it. The binfo object is a TREE_VEC node. + + Inheritance is represented by the binfo nodes allocated for a + given type. For example, given types C and D, such that D is + inherited by C, 3 binfo nodes will be allocated: one for describing + the binfo properties of C, similarly one for D, and one for + describing the binfo properties of D as a base type for C. + Thus, given a pointer to class C, one can get a pointer to the binfo + of D acting as a basetype for C by looking at C's binfo's basetypes. */ + +/* The actual data type node being inherited in this basetype. */ +#define BINFO_TYPE(NODE) TREE_TYPE (NODE) + +/* The offset where this basetype appears in its containing type. + BINFO_OFFSET slot holds the offset (in bytes) + from the base of the complete object to the base of the part of the + object that is allocated on behalf of this `type'. + This is always 0 except when there is multiple inheritance. */ + +#define BINFO_OFFSET(NODE) TREE_VEC_ELT ((NODE), 1) +#define TYPE_BINFO_OFFSET(NODE) BINFO_OFFSET (TYPE_BINFO (NODE)) +#define BINFO_OFFSET_ZEROP(NODE) (BINFO_OFFSET (NODE) == integer_zero_node) + +/* The virtual function table belonging to this basetype. Virtual + function tables provide a mechanism for run-time method dispatching. + The entries of a virtual function table are language-dependent. */ + +#define BINFO_VTABLE(NODE) TREE_VEC_ELT ((NODE), 2) +#define TYPE_BINFO_VTABLE(NODE) BINFO_VTABLE (TYPE_BINFO (NODE)) + +/* The virtual functions in the virtual function table. This is + a TREE_LIST that is used as an initial approximation for building + a virtual function table for this basetype. */ +#define BINFO_VIRTUALS(NODE) TREE_VEC_ELT ((NODE), 3) +#define TYPE_BINFO_VIRTUALS(NODE) BINFO_VIRTUALS (TYPE_BINFO (NODE)) + +/* A vector of additional binfos for the types inherited by this basetype. + + If this basetype describes type D as inherited in C, + and if the basetypes of D are E anf F, + then this vector contains binfos for inheritance of E and F by C. + + ??? This could probably be done by just allocating the + base types at the end of this TREE_VEC (instead of using + another TREE_VEC). This would simplify the calculation + of how many basetypes a given type had. */ +#define BINFO_BASETYPES(NODE) TREE_VEC_ELT ((NODE), 4) +#define TYPE_BINFO_BASETYPES(NODE) TREE_VEC_ELT (TYPE_BINFO (NODE), 4) + +/* For a BINFO record describing an inheritance, this yields a pointer + to the artificial FIELD_DECL node which contains the "virtual base + class pointer" for the given inheritance. */ + +#define BINFO_VPTR_FIELD(NODE) TREE_VEC_ELT ((NODE), 5) + +/* Accessor macro to get to the Nth basetype of this basetype. */ +#define BINFO_BASETYPE(NODE,N) TREE_VEC_ELT (BINFO_BASETYPES (NODE), (N)) +#define TYPE_BINFO_BASETYPE(NODE,N) BINFO_TYPE (TREE_VEC_ELT (BINFO_BASETYPES (TYPE_BINFO (NODE)), (N))) + +/* Slot used to build a chain that represents a use of inheritance. + For example, if X is derived from Y, and Y is derived from Z, + then this field can be used to link the binfo node for X to + the binfo node for X's Y to represent the use of inheritance + from X to Y. Similarly, this slot of the binfo node for X's Y + can point to the Z from which Y is inherited (in X's inheritance + hierarchy). In this fashion, one can represent and traverse specific + uses of inheritance using the binfo nodes themselves (instead of + consing new space pointing to binfo nodes). + It is up to the language-dependent front-ends to maintain + this information as necessary. */ +#define BINFO_INHERITANCE_CHAIN(NODE) TREE_VEC_ELT ((NODE), 0) + +/* Define fields and accessors for nodes representing declared names. */ + +/* This is the name of the object as written by the user. + It is an IDENTIFIER_NODE. */ +#define DECL_NAME(NODE) ((NODE)->decl.name) +/* This macro is marked for death. */ +#define DECL_PRINT_NAME(NODE) ((NODE)->decl.print_name) +/* This is the name of the object as the assembler will see it + (but before any translations made by ASM_OUTPUT_LABELREF). + Often this is the same as DECL_NAME. + It is an IDENTIFIER_NODE. */ +#define DECL_ASSEMBLER_NAME(NODE) ((NODE)->decl.assembler_name) +/* For FIELD_DECLs, this is the + RECORD_TYPE, UNION_TYPE, or QUAL_UNION_TYPE node that the field is + a member of. For VAR_DECL, PARM_DECL, FUNCTION_DECL, LABEL_DECL, + and CONST_DECL nodes, this points to the FUNCTION_DECL for the + containing function, or else yields NULL_TREE if the given decl has "file scope". */ +#define DECL_CONTEXT(NODE) ((NODE)->decl.context) +#define DECL_FIELD_CONTEXT(NODE) ((NODE)->decl.context) +/* In a FIELD_DECL, this is the field position, counting in bits, + of the bit closest to the beginning of the structure. */ +#define DECL_FIELD_BITPOS(NODE) ((NODE)->decl.arguments) +/* In a FIELD_DECL, this indicates whether the field was a bit-field and + if so, the type that was originally specified for it. + TREE_TYPE may have been modified (in finish_struct). */ +#define DECL_BIT_FIELD_TYPE(NODE) ((NODE)->decl.result) +/* In FUNCTION_DECL, a chain of ..._DECL nodes. */ +/* VAR_DECL and PARM_DECL reserve the arguments slot + for language-specific uses. */ +#define DECL_ARGUMENTS(NODE) ((NODE)->decl.arguments) +/* In FUNCTION_DECL, holds the decl for the return value. */ +#define DECL_RESULT(NODE) ((NODE)->decl.result) +/* In PARM_DECL, holds the type as written (perhaps a function or array). */ +#define DECL_ARG_TYPE_AS_WRITTEN(NODE) ((NODE)->decl.result) +/* For a FUNCTION_DECL, holds the tree of BINDINGs. + For a VAR_DECL, holds the initial value. + For a PARM_DECL, not used--default + values for parameters are encoded in the type of the function, + not in the PARM_DECL slot. */ +#define DECL_INITIAL(NODE) ((NODE)->decl.initial) +/* For a PARM_DECL, records the data type used to pass the argument, + which may be different from the type seen in the program. */ +#define DECL_ARG_TYPE(NODE) ((NODE)->decl.initial) /* In PARM_DECL. */ +/* For a FIELD_DECL in a QUAL_UNION_TYPE, records the expression, which + if nonzero, indicates that the field occupies the type. */ +#define DECL_QUALIFIER(NODE) ((NODE)->decl.initial) +/* These two fields describe where in the source code the declaration was. */ +#define DECL_SOURCE_FILE(NODE) ((NODE)->decl.filename) +#define DECL_SOURCE_LINE(NODE) ((NODE)->decl.linenum) +/* Holds the size of the datum, as a tree expression. + Need not be constant. */ +#define DECL_SIZE(NODE) ((NODE)->decl.size) +/* Holds the alignment required for the datum. */ +#define DECL_ALIGN(NODE) ((NODE)->decl.frame_size) +/* Holds the machine mode corresponding to the declaration of a variable or + field. Always equal to TYPE_MODE (TREE_TYPE (decl)) except for a + FIELD_DECL. */ +#define DECL_MODE(NODE) ((NODE)->decl.mode) +/* Holds the RTL expression for the value of a variable or function. If + PROMOTED_MODE is defined, the mode of this expression may not be same + as DECL_MODE. In that case, DECL_MODE contains the mode corresponding + to the variable's data type, while the mode + of DECL_RTL is the mode actually used to contain the data. */ +#define DECL_RTL(NODE) ((NODE)->decl.rtl) +/* For PARM_DECL, holds an RTL for the stack slot or register + where the data was actually passed. */ +#define DECL_INCOMING_RTL(NODE) ((NODE)->decl.saved_insns.r) +/* For FUNCTION_DECL, if it is inline, holds the saved insn chain. */ +#define DECL_SAVED_INSNS(NODE) ((NODE)->decl.saved_insns.r) +/* For FUNCTION_DECL, if it is inline, + holds the size of the stack frame, as an integer. */ +#define DECL_FRAME_SIZE(NODE) ((NODE)->decl.frame_size) +/* For FUNCTION_DECL, if it is built-in, + this identifies which built-in operation it is. */ +#define DECL_FUNCTION_CODE(NODE) \ + ((enum built_in_function) (NODE)->decl.frame_size) +#define DECL_SET_FUNCTION_CODE(NODE,VAL) \ + ((NODE)->decl.frame_size = (int) (VAL)) +/* For a FIELD_DECL, holds the size of the member as an integer. */ +#define DECL_FIELD_SIZE(NODE) ((NODE)->decl.saved_insns.i) + +/* The DECL_VINDEX is used for FUNCTION_DECLS in two different ways. + Before the struct containing the FUNCTION_DECL is laid out, + DECL_VINDEX may point to a FUNCTION_DECL in a base class which + is the FUNCTION_DECL which this FUNCTION_DECL will replace as a virtual + function. When the class is laid out, this pointer is changed + to an INTEGER_CST node which is suitable for use as an index + into the virtual function table. */ +#define DECL_VINDEX(NODE) ((NODE)->decl.vindex) +/* For FIELD_DECLS, DECL_FCONTEXT is the *first* baseclass in + which this FIELD_DECL is defined. This information is needed when + writing debugging information about vfield and vbase decls for C++. */ +#define DECL_FCONTEXT(NODE) ((NODE)->decl.vindex) + +/* Every ..._DECL node gets a unique number. */ +#define DECL_UID(NODE) ((NODE)->decl.uid) + +/* For any sort of a ..._DECL node, this points to the original (abstract) + decl node which this decl is an instance of, or else it is NULL indicating + that this decl is not an instance of some other decl. */ +#define DECL_ABSTRACT_ORIGIN(NODE) ((NODE)->decl.abstract_origin) + +/* Nonzero for any sort of ..._DECL node means this decl node represents + an inline instance of some original (abstract) decl from an inline function; + suppress any warnings about shadowing some other variable. */ +#define DECL_FROM_INLINE(NODE) (DECL_ABSTRACT_ORIGIN (NODE) != (tree) 0) + +/* Nonzero if a _DECL means that the name of this decl should be ignored + for symbolic debug purposes. */ +#define DECL_IGNORED_P(NODE) ((NODE)->decl.ignored_flag) + +/* Nonzero for a given ..._DECL node means that this node represents an + "abstract instance" of the given declaration (e.g. in the original + declaration of an inline function). When generating symbolic debugging + information, we musn't try to generate any address information for nodes + marked as "abstract instances" because we don't actually generate + any code or allocate any data space for such instances. */ +#define DECL_ABSTRACT(NODE) ((NODE)->decl.abstract_flag) + +/* Nonzero if a _DECL means that no warnings should be generated just + because this decl is unused. */ +#define DECL_IN_SYSTEM_HEADER(NODE) ((NODE)->decl.in_system_header_flag) + +/* Language-specific decl information. */ +#define DECL_LANG_SPECIFIC(NODE) ((NODE)->decl.lang_specific) + +/* In a VAR_DECL or FUNCTION_DECL, + nonzero means external reference: + do not allocate storage, and refer to a definition elsewhere. */ +#define DECL_EXTERNAL(NODE) ((NODE)->decl.external_flag) + +/* In VAR_DECL and PARM_DECL nodes, nonzero means declared `register'. + In LABEL_DECL nodes, nonzero means that an error message about + jumping into such a binding contour has been printed for this label. */ +#define DECL_REGISTER(NODE) ((NODE)->decl.regdecl_flag) +/* In a FIELD_DECL, indicates this field should be bit-packed. */ +#define DECL_PACKED(NODE) ((NODE)->decl.regdecl_flag) + +/* Nonzero in a ..._DECL means this variable is ref'd from a nested function. + For VAR_DECL nodes, PARM_DECL nodes, and FUNCTION_DECL nodes. + + For LABEL_DECL nodes, nonzero if nonlocal gotos to the label are permitted. + + Also set in some languages for variables, etc., outside the normal + lexical scope, such as class instance variables. */ +#define DECL_NONLOCAL(NODE) ((NODE)->decl.nonlocal_flag) + +/* Nonzero in a FUNCTION_DECL means this function can be substituted + where it is called. */ +#define DECL_INLINE(NODE) ((NODE)->decl.inline_flag) + +/* Nonzero in a FUNCTION_DECL means this is a built-in function + that is not specified by ansi C and that users are supposed to be allowed + to redefine for any purpose whatever. */ +#define DECL_BUILT_IN_NONANSI(NODE) ((NODE)->common.unsigned_flag) + +/* Nonzero in a FIELD_DECL means it is a bit field, and must be accessed + specially. */ +#define DECL_BIT_FIELD(NODE) ((NODE)->decl.bit_field_flag) +/* In a LABEL_DECL, nonzero means label was defined inside a binding + contour that restored a stack level and which is now exited. */ +#define DECL_TOO_LATE(NODE) ((NODE)->decl.bit_field_flag) +/* In a FUNCTION_DECL, nonzero means a built in function. */ +#define DECL_BUILT_IN(NODE) ((NODE)->decl.bit_field_flag) + +/* Used in VAR_DECLs to indicate that the variable is a vtable. + It is also used in FIELD_DECLs for vtable pointers. */ +#define DECL_VIRTUAL_P(NODE) ((NODE)->decl.virtual_flag) + +/* Additional flags for language-specific uses. */ +#define DECL_LANG_FLAG_0(NODE) ((NODE)->decl.lang_flag_0) +#define DECL_LANG_FLAG_1(NODE) ((NODE)->decl.lang_flag_1) +#define DECL_LANG_FLAG_2(NODE) ((NODE)->decl.lang_flag_2) +#define DECL_LANG_FLAG_3(NODE) ((NODE)->decl.lang_flag_3) +#define DECL_LANG_FLAG_4(NODE) ((NODE)->decl.lang_flag_4) +#define DECL_LANG_FLAG_5(NODE) ((NODE)->decl.lang_flag_5) +#define DECL_LANG_FLAG_6(NODE) ((NODE)->decl.lang_flag_6) +#define DECL_LANG_FLAG_7(NODE) ((NODE)->decl.lang_flag_7) + +struct tree_decl +{ + char common[sizeof (struct tree_common)]; + char *filename; + int linenum; + union tree_node *size; + unsigned int uid; +#ifdef ONLY_INT_FIELDS + int mode : 8; +#else + enum machine_mode mode : 8; +#endif + + unsigned external_flag : 1; + unsigned nonlocal_flag : 1; + unsigned regdecl_flag : 1; + unsigned inline_flag : 1; + unsigned bit_field_flag : 1; + unsigned virtual_flag : 1; + unsigned ignored_flag : 1; + unsigned abstract_flag : 1; + + unsigned in_system_header_flag : 1; + /* room for seven more */ + + unsigned lang_flag_0 : 1; + unsigned lang_flag_1 : 1; + unsigned lang_flag_2 : 1; + unsigned lang_flag_3 : 1; + unsigned lang_flag_4 : 1; + unsigned lang_flag_5 : 1; + unsigned lang_flag_6 : 1; + unsigned lang_flag_7 : 1; + + union tree_node *name; + union tree_node *context; + union tree_node *arguments; + union tree_node *result; + union tree_node *initial; + union tree_node *abstract_origin; + /* The PRINT_NAME field is marked for death. */ + char *print_name; + union tree_node *assembler_name; + struct rtx_def *rtl; /* acts as link to register transfer language + (rtl) info */ + /* For a FUNCTION_DECL, if inline, this is the size of frame needed. + If built-in, this is the code for which built-in function. + For other kinds of decls, this is DECL_ALIGN. */ + int frame_size; + /* For FUNCTION_DECLs: points to insn that constitutes its definition + on the permanent obstack. For any other kind of decl, this is the + alignment. */ + union { + struct rtx_def *r; + int i; + } saved_insns; + union tree_node *vindex; + /* Points to a structure whose details depend on the language in use. */ + struct lang_decl *lang_specific; +}; + +/* Define the overall contents of a tree node. + It may be any of the structures declared above + for various types of node. */ + +union tree_node +{ + struct tree_common common; + struct tree_int_cst int_cst; + struct tree_real_cst real_cst; + struct tree_string string; + struct tree_complex complex; + struct tree_identifier identifier; + struct tree_decl decl; + struct tree_type type; + struct tree_list list; + struct tree_vec vec; + struct tree_exp exp; + struct tree_block block; + }; + +/* Add prototype support. */ +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif + + +#define NULL_TREE (tree) NULL + +/* Define a generic NULL if one hasn't already been defined. */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef GENERIC_PTR +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define GENERIC_PTR void * +#else +#define GENERIC_PTR char * +#endif +#endif + +#ifndef NULL_PTR +#define NULL_PTR ((GENERIC_PTR)0) +#endif + +/* Format for global names of constructor and destructor functions. */ +#ifndef CONSTRUCTOR_NAME_FORMAT /* Some machines need to override this. */ +#ifndef NO_DOLLAR_IN_LABEL +#define CONSTRUCTOR_NAME_FORMAT "_GLOBAL_$I$%s" +#else +#ifdef NO_DOT_IN_LABEL +#define CONSTRUCTOR_NAME_FORMAT "____GLOBAL__I_%s" +#else +#define CONSTRUCTOR_NAME_FORMAT "_GLOBAL_.I.%s" +#endif +#endif +#endif + +/* The following functions accept a wide integer argument. Rather than + having to cast on every function call, we use a macro instead, that is + defined here and in rtl.h. */ + +#ifndef exact_log2 +#define exact_log2(N) exact_log2_wide ((HOST_WIDE_INT) (N)) +#define floor_log2(N) floor_log2_wide ((HOST_WIDE_INT) (N)) +#endif + +#if 0 +/* At present, don't prototype xrealloc, since all of the callers don't + cast their pointers to char *, and all of the xrealloc's don't use + void * yet. */ +extern char *xmalloc PROTO((size_t)); +extern char *xrealloc PROTO((void *, size_t)); +#else +extern char *xmalloc (); +extern char *xrealloc (); +#endif + +extern char *oballoc PROTO((int)); +extern char *permalloc PROTO((int)); +extern char *savealloc PROTO((int)); +extern void free PROTO((void *)); + +/* Lowest level primitive for allocating a node. + The TREE_CODE is the only argument. Contents are initialized + to zero except for a few of the common fields. */ + +extern tree make_node PROTO((enum tree_code)); + +/* Make a copy of a node, with all the same contents except + for TREE_PERMANENT. (The copy is permanent + iff nodes being made now are permanent.) */ + +extern tree copy_node PROTO((tree)); + +/* Make a copy of a chain of TREE_LIST nodes. */ + +extern tree copy_list PROTO((tree)); + +/* Make a TREE_VEC. */ + +extern tree make_tree_vec PROTO((int)); + +/* Return the (unique) IDENTIFIER_NODE node for a given name. + The name is supplied as a char *. */ + +extern tree get_identifier PROTO((char *)); + +/* Construct various types of nodes. */ + +#define build_int_2(LO,HI) \ + build_int_2_wide ((HOST_WIDE_INT) (LO), (HOST_WIDE_INT) (HI)) + +#if 0 +/* We cannot define prototypes for the variable argument functions, + since they have not been ANSI-fied, and an ANSI compiler would + complain when compiling the definition of these functions. */ + +extern tree build PROTO((enum tree_code, tree, ...)); +extern tree build_nt PROTO((enum tree_code, ...)); +extern tree build_parse_node PROTO((enum tree_code, ...)); +#else +extern tree build (); +extern tree build_nt (); +extern tree build_parse_node (); +#endif + +extern tree build_int_2_wide PROTO((HOST_WIDE_INT, HOST_WIDE_INT)); +extern tree build_real PROTO((tree, REAL_VALUE_TYPE)); +extern tree build_real_from_int_cst PROTO((tree, tree)); +extern tree build_complex PROTO((tree, tree)); +extern tree build_string PROTO((int, char *)); +extern tree build1 PROTO((enum tree_code, tree, tree)); +extern tree build_tree_list PROTO((tree, tree)); +extern tree build_decl_list PROTO((tree, tree)); +extern tree build_decl PROTO((enum tree_code, tree, tree)); +extern tree build_block PROTO((tree, tree, tree, tree, tree)); + +/* Construct various nodes representing data types. */ + +extern tree make_signed_type PROTO((int)); +extern tree make_unsigned_type PROTO((int)); +extern tree signed_or_unsigned_type PROTO((int, tree)); +extern void fixup_unsigned_type PROTO((tree)); +extern tree build_pointer_type PROTO((tree)); +extern tree build_reference_type PROTO((tree)); +extern tree build_index_type PROTO((tree)); +extern tree build_index_2_type PROTO((tree, tree)); +extern tree build_array_type PROTO((tree, tree)); +extern tree build_function_type PROTO((tree, tree)); +extern tree build_method_type PROTO((tree, tree)); +extern tree build_offset_type PROTO((tree, tree)); +extern tree build_complex_type PROTO((tree)); +extern tree array_type_nelts PROTO((tree)); + +extern tree value_member PROTO((tree, tree)); +extern tree purpose_member PROTO((tree, tree)); +extern tree binfo_member PROTO((tree, tree)); +extern int tree_int_cst_equal PROTO((tree, tree)); +extern int tree_int_cst_lt PROTO((tree, tree)); +extern int index_type_equal PROTO((tree, tree)); + +/* From expmed.c. Since rtl.h is included after tree.h, we can't + put the prototype here. Rtl.h does declare the prototype if + tree.h had been included. */ + +extern tree make_tree (); + +/* Given a type node TYPE, and CONSTP and VOLATILEP, return a type + for the same kind of data as TYPE describes. + Variants point to the "main variant" (which has neither CONST nor VOLATILE) + via TYPE_MAIN_VARIANT, and it points to a chain of other variants + so that duplicate variants are never made. + Only main variants should ever appear as types of expressions. */ + +extern tree build_type_variant PROTO((tree, int, int)); + +/* Make a copy of a type node. */ + +extern tree build_type_copy PROTO((tree)); + +/* Given a ..._TYPE node, calculate the TYPE_SIZE, TYPE_SIZE_UNIT, + TYPE_ALIGN and TYPE_MODE fields. + If called more than once on one node, does nothing except + for the first time. */ + +extern void layout_type PROTO((tree)); + +/* Given a hashcode and a ..._TYPE node (for which the hashcode was made), + return a canonicalized ..._TYPE node, so that duplicates are not made. + How the hash code is computed is up to the caller, as long as any two + callers that could hash identical-looking type nodes agree. */ + +extern tree type_hash_canon PROTO((int, tree)); + +/* Given a VAR_DECL, PARM_DECL, RESULT_DECL or FIELD_DECL node, + calculates the DECL_SIZE, DECL_SIZE_UNIT, DECL_ALIGN and DECL_MODE + fields. Call this only once for any given decl node. + + Second argument is the boundary that this field can be assumed to + be starting at (in bits). Zero means it can be assumed aligned + on any boundary that may be needed. */ + +extern void layout_decl PROTO((tree, unsigned)); + +/* Fold constants as much as possible in an expression. + Returns the simplified expression. + Acts only on the top level of the expression; + if the argument itself cannot be simplified, its + subexpressions are not changed. */ + +extern tree fold PROTO((tree)); + +/* Return an expr equal to X but certainly not valid as an lvalue. */ + +extern tree non_lvalue PROTO((tree)); + +extern tree convert PROTO((tree, tree)); +extern tree size_in_bytes PROTO((tree)); +extern int int_size_in_bytes PROTO((tree)); +extern tree size_binop PROTO((enum tree_code, tree, tree)); +extern tree size_int PROTO((unsigned)); +extern tree round_up PROTO((tree, int)); +extern tree get_pending_sizes PROTO((void)); + +/* Type for sizes of data-type. */ + +extern tree sizetype; + +/* Concatenate two lists (chains of TREE_LIST nodes) X and Y + by making the last node in X point to Y. + Returns X, except if X is 0 returns Y. */ + +extern tree chainon PROTO((tree, tree)); + +/* Make a new TREE_LIST node from specified PURPOSE, VALUE and CHAIN. */ + +extern tree tree_cons PROTO((tree, tree, tree)); +extern tree perm_tree_cons PROTO((tree, tree, tree)); +extern tree temp_tree_cons PROTO((tree, tree, tree)); +extern tree saveable_tree_cons PROTO((tree, tree, tree)); +extern tree decl_tree_cons PROTO((tree, tree, tree)); + +/* Return the last tree node in a chain. */ + +extern tree tree_last PROTO((tree)); + +/* Reverse the order of elements in a chain, and return the new head. */ + +extern tree nreverse PROTO((tree)); + +/* Returns the length of a chain of nodes + (number of chain pointers to follow before reaching a null pointer). */ + +extern int list_length PROTO((tree)); + +/* integer_zerop (tree x) is nonzero if X is an integer constant of value 0 */ + +extern int integer_zerop PROTO((tree)); + +/* integer_onep (tree x) is nonzero if X is an integer constant of value 1 */ + +extern int integer_onep PROTO((tree)); + +/* integer_all_onesp (tree x) is nonzero if X is an integer constant + all of whose significant bits are 1. */ + +extern int integer_all_onesp PROTO((tree)); + +/* integer_pow2p (tree x) is nonzero is X is an integer constant with + exactly one bit 1. */ + +extern int integer_pow2p PROTO((tree)); + +/* staticp (tree x) is nonzero if X is a reference to data allocated + at a fixed address in memory. */ + +extern int staticp PROTO((tree)); + +/* Gets an error if argument X is not an lvalue. + Also returns 1 if X is an lvalue, 0 if not. */ + +extern int lvalue_or_else PROTO((tree, char *)); + +/* save_expr (EXP) returns an expression equivalent to EXP + but it can be used multiple times within context CTX + and only evaluate EXP once. */ + +extern tree save_expr PROTO((tree)); + +/* variable_size (EXP) is like save_expr (EXP) except that it + is for the special case of something that is part of a + variable size for a data type. It makes special arrangements + to compute the value at the right time when the data type + belongs to a function parameter. */ + +extern tree variable_size PROTO((tree)); + +/* stabilize_reference (EXP) returns an reference equivalent to EXP + but it can be used multiple times + and only evaluate the subexpressions once. */ + +extern tree stabilize_reference PROTO((tree)); + +/* Return EXP, stripped of any conversions to wider types + in such a way that the result of converting to type FOR_TYPE + is the same as if EXP were converted to FOR_TYPE. + If FOR_TYPE is 0, it signifies EXP's type. */ + +extern tree get_unwidened PROTO((tree, tree)); + +/* Return OP or a simpler expression for a narrower value + which can be sign-extended or zero-extended to give back OP. + Store in *UNSIGNEDP_PTR either 1 if the value should be zero-extended + or 0 if the value should be sign-extended. */ + +extern tree get_narrower PROTO((tree, int *)); + +/* Given MODE and UNSIGNEDP, return a suitable type-tree + with that mode. + The definition of this resides in language-specific code + as the repertoire of available types may vary. */ + +extern tree type_for_mode PROTO((enum machine_mode, int)); + +/* Given PRECISION and UNSIGNEDP, return a suitable type-tree + for an integer type with at least that precision. + The definition of this resides in language-specific code + as the repertoire of available types may vary. */ + +extern tree type_for_size PROTO((unsigned, int)); + +/* Given an integer type T, return a type like T but unsigned. + If T is unsigned, the value is T. + The definition of this resides in language-specific code + as the repertoire of available types may vary. */ + +extern tree unsigned_type PROTO((tree)); + +/* Given an integer type T, return a type like T but signed. + If T is signed, the value is T. + The definition of this resides in language-specific code + as the repertoire of available types may vary. */ + +extern tree signed_type PROTO((tree)); + +/* This function must be defined in the language-specific files. + expand_expr calls it to build the cleanup-expression for a TARGET_EXPR. + This is defined in a language-specific file. */ + +extern tree maybe_build_cleanup PROTO((tree)); + +/* Given an expression EXP that may be a COMPONENT_REF or an ARRAY_REF, + look for nested component-refs or array-refs at constant positions + and find the ultimate containing object, which is returned. */ + +extern tree get_inner_reference PROTO((tree, int *, int *, tree *, enum machine_mode *, int *, int *)); + +/* Return the FUNCTION_DECL which provides this _DECL with its context, + or zero if none. */ +extern tree decl_function_context PROTO((tree)); + +/* Return the RECORD_TYPE, UNION_TYPE, or QUAL_UNION_TYPE which provides + this _DECL with its context, or zero if none. */ +extern tree decl_type_context PROTO((tree)); + +/* Given the FUNCTION_DECL for the current function, + return zero if it is ok for this function to be inline. + Otherwise return a warning message with a single %s + for the function's name. */ + +extern char *function_cannot_inline_p PROTO((tree)); + +/* Return 1 if EXPR is the real constant zero. */ +extern int real_zerop PROTO((tree)); + +/* Declare commonly used variables for tree structure. */ + +/* An integer constant with value 0 */ +extern tree integer_zero_node; + +/* An integer constant with value 1 */ +extern tree integer_one_node; + +/* An integer constant with value 0 whose type is sizetype. */ +extern tree size_zero_node; + +/* An integer constant with value 1 whose type is sizetype. */ +extern tree size_one_node; + +/* A constant of type pointer-to-int and value 0 */ +extern tree null_pointer_node; + +/* A node of type ERROR_MARK. */ +extern tree error_mark_node; + +/* The type node for the void type. */ +extern tree void_type_node; + +/* The type node for the ordinary (signed) integer type. */ +extern tree integer_type_node; + +/* The type node for the unsigned integer type. */ +extern tree unsigned_type_node; + +/* The type node for the ordinary character type. */ +extern tree char_type_node; + +/* Points to the name of the input file from which the current input + being parsed originally came (before it went into cpp). */ +extern char *input_filename; + +/* Current line number in input file. */ +extern int lineno; + +/* Nonzero for -pedantic switch: warn about anything + that standard C forbids. */ +extern int pedantic; + +/* Nonzero means can safely call expand_expr now; + otherwise layout_type puts variable sizes onto `pending_sizes' instead. */ + +extern int immediate_size_expand; + +/* Points to the FUNCTION_DECL of the function whose body we are reading. */ + +extern tree current_function_decl; + +/* Nonzero if function being compiled can call setjmp. */ + +extern int current_function_calls_setjmp; + +/* Nonzero if function being compiled can call longjmp. */ + +extern int current_function_calls_longjmp; + +/* Nonzero means all ..._TYPE nodes should be allocated permanently. */ + +extern int all_types_permanent; + +/* Pointer to function to compute the name to use to print a declaration. */ + +extern char *(*decl_printable_name) (); + +/* Pointer to function to finish handling an incomplete decl at the + end of compilation. */ + +extern void (*incomplete_decl_finalize_hook) (); + +/* In tree.c */ +extern char *perm_calloc PROTO((int, long)); + +/* In stmt.c */ + +extern tree expand_start_stmt_expr PROTO((void)); +extern tree expand_end_stmt_expr PROTO((tree)); +extern void expand_expr_stmt PROTO((tree)); +extern void expand_decl_init PROTO((tree)); +extern void clear_last_expr PROTO((void)); +extern void expand_label PROTO((tree)); +extern void expand_goto PROTO((tree)); +extern void expand_asm PROTO((tree)); +extern void expand_start_cond PROTO((tree, int)); +extern void expand_end_cond PROTO((void)); +extern void expand_start_else PROTO((void)); +extern void expand_start_elseif PROTO((tree)); +extern struct nesting *expand_start_loop PROTO((int)); +extern struct nesting *expand_start_loop_continue_elsewhere PROTO((int)); +extern void expand_loop_continue_here PROTO((void)); +extern void expand_end_loop PROTO((void)); +extern int expand_continue_loop PROTO((struct nesting *)); +extern int expand_exit_loop PROTO((struct nesting *)); +extern int expand_exit_loop_if_false PROTO((struct nesting *, tree)); +extern int expand_exit_something PROTO((void)); + +extern void expand_null_return PROTO((void)); +extern void expand_return PROTO((tree)); +extern void expand_start_bindings PROTO((int)); +extern void expand_end_bindings PROTO((tree, int, int)); +extern tree last_cleanup_this_contour PROTO((void)); +extern void expand_start_case PROTO((int, tree, tree, char *)); +extern void expand_end_case PROTO((tree)); +extern int pushcase PROTO((tree, tree, tree *)); +extern int pushcase_range PROTO((tree, tree, tree, tree *)); + +/* In fold-const.c */ + +extern tree invert_truthvalue PROTO((tree)); + +/* The language front-end must define these functions. */ + +/* Function of no arguments for initializing lexical scanning. */ +extern void init_lex PROTO((void)); +/* Function of no arguments for initializing the symbol table. */ +extern void init_decl_processing PROTO((void)); + +/* Functions called with no arguments at the beginning and end or processing + the input source file. */ +extern void lang_init PROTO((void)); +extern void lang_finish PROTO((void)); + +/* Funtion to identify which front-end produced the output file. */ +extern char *lang_identify PROTO((void)); + +/* Function called with no arguments to parse and compile the input. */ +extern int yyparse PROTO((void)); +/* Function called with option as argument + to decode options starting with -f or -W or +. + It should return nonzero if it handles the option. */ +extern int lang_decode_option PROTO((char *)); + +/* Functions for processing symbol declarations. */ +/* Function to enter a new lexical scope. + Takes one argument: always zero when called from outside the front end. */ +extern void pushlevel PROTO((int)); +/* Function to exit a lexical scope. It returns a BINDING for that scope. + Takes three arguments: + KEEP -- nonzero if there were declarations in this scope. + REVERSE -- reverse the order of decls before returning them. + FUNCTIONBODY -- nonzero if this level is the body of a function. */ +extern tree poplevel PROTO((int, int, int)); +/* Set the BLOCK node for the current scope level. */ +extern void set_block PROTO((tree)); +/* Function to add a decl to the current scope level. + Takes one argument, a decl to add. + Returns that decl, or, if the same symbol is already declared, may + return a different decl for that name. */ +extern tree pushdecl PROTO((tree)); +/* Function to return the chain of decls so far in the current scope level. */ +extern tree getdecls PROTO((void)); +/* Function to return the chain of structure tags in the current scope level. */ +extern tree gettags PROTO((void)); + +extern tree build_range_type PROTO((tree, tree, tree)); + +/* Call when starting to parse a declaration: + make expressions in the declaration last the length of the function. + Returns an argument that should be passed to resume_momentary later. */ +extern int suspend_momentary PROTO((void)); + +extern int allocation_temporary_p PROTO((void)); + +/* Call when finished parsing a declaration: + restore the treatment of node-allocation that was + in effect before the suspension. + YES should be the value previously returned by suspend_momentary. */ +extern void resume_momentary PROTO((int)); + +/* Called after finishing a record, union or enumeral type. */ +extern void rest_of_type_compilation PROTO((tree, int)); + +/* Save the current set of obstacks, but don't change them. */ +extern void push_obstacks_nochange PROTO((void)); + +extern void push_momentary PROTO((void)); + +extern void clear_momentary PROTO((void)); + +extern void pop_momentary PROTO((void)); + +extern void end_temporary_allocation PROTO((void)); + +/* Pop the obstack selection stack. */ +extern void pop_obstacks PROTO((void)); diff --git a/gnu/usr.bin/cc/lib/typeclass.h b/gnu/usr.bin/cc/lib/typeclass.h new file mode 100644 index 000000000000..b16604253617 --- /dev/null +++ b/gnu/usr.bin/cc/lib/typeclass.h @@ -0,0 +1,14 @@ +/* Values returned by __builtin_classify_type. */ + +enum type_class +{ + no_type_class = -1, + void_type_class, integer_type_class, char_type_class, + enumeral_type_class, boolean_type_class, + pointer_type_class, reference_type_class, offset_type_class, + real_type_class, complex_type_class, + function_type_class, method_type_class, + record_type_class, union_type_class, + array_type_class, string_type_class, set_type_class, file_type_class, + lang_type_class +}; diff --git a/gnu/usr.bin/cc/lib/unroll.c b/gnu/usr.bin/cc/lib/unroll.c new file mode 100644 index 000000000000..fc8a3f69f19b --- /dev/null +++ b/gnu/usr.bin/cc/lib/unroll.c @@ -0,0 +1,3251 @@ +/* Try to unroll loops, and split induction variables. + Copyright (C) 1992, 1993 Free Software Foundation, Inc. + Contributed by James E. Wilson, Cygnus Support/UC Berkeley. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Try to unroll a loop, and split induction variables. + + Loops for which the number of iterations can be calculated exactly are + handled specially. If the number of iterations times the insn_count is + less than MAX_UNROLLED_INSNS, then the loop is unrolled completely. + Otherwise, we try to unroll the loop a number of times modulo the number + of iterations, so that only one exit test will be needed. It is unrolled + a number of times approximately equal to MAX_UNROLLED_INSNS divided by + the insn count. + + Otherwise, if the number of iterations can be calculated exactly at + run time, and the loop is always entered at the top, then we try to + precondition the loop. That is, at run time, calculate how many times + the loop will execute, and then execute the loop body a few times so + that the remaining iterations will be some multiple of 4 (or 2 if the + loop is large). Then fall through to a loop unrolled 4 (or 2) times, + with only one exit test needed at the end of the loop. + + Otherwise, if the number of iterations can not be calculated exactly, + not even at run time, then we still unroll the loop a number of times + approximately equal to MAX_UNROLLED_INSNS divided by the insn count, + but there must be an exit test after each copy of the loop body. + + For each induction variable, which is dead outside the loop (replaceable) + or for which we can easily calculate the final value, if we can easily + calculate its value at each place where it is set as a function of the + current loop unroll count and the variable's value at loop entry, then + the induction variable is split into `N' different variables, one for + each copy of the loop body. One variable is live across the backward + branch, and the others are all calculated as a function of this variable. + This helps eliminate data dependencies, and leads to further opportunities + for cse. */ + +/* Possible improvements follow: */ + +/* ??? Add an extra pass somewhere to determine whether unrolling will + give any benefit. E.g. after generating all unrolled insns, compute the + cost of all insns and compare against cost of insns in rolled loop. + + - On traditional architectures, unrolling a non-constant bound loop + is a win if there is a giv whose only use is in memory addresses, the + memory addresses can be split, and hence giv increments can be + eliminated. + - It is also a win if the loop is executed many times, and preconditioning + can be performed for the loop. + Add code to check for these and similar cases. */ + +/* ??? Improve control of which loops get unrolled. Could use profiling + info to only unroll the most commonly executed loops. Perhaps have + a user specifyable option to control the amount of code expansion, + or the percent of loops to consider for unrolling. Etc. */ + +/* ??? Look at the register copies inside the loop to see if they form a + simple permutation. If so, iterate the permutation until it gets back to + the start state. This is how many times we should unroll the loop, for + best results, because then all register copies can be eliminated. + For example, the lisp nreverse function should be unrolled 3 times + while (this) + { + next = this->cdr; + this->cdr = prev; + prev = this; + this = next; + } + + ??? The number of times to unroll the loop may also be based on data + references in the loop. For example, if we have a loop that references + x[i-1], x[i], and x[i+1], we should unroll it a multiple of 3 times. */ + +/* ??? Add some simple linear equation solving capability so that we can + determine the number of loop iterations for more complex loops. + For example, consider this loop from gdb + #define SWAP_TARGET_AND_HOST(buffer,len) + { + char tmp; + char *p = (char *) buffer; + char *q = ((char *) buffer) + len - 1; + int iterations = (len + 1) >> 1; + int i; + for (p; p < q; p++, q--;) + { + tmp = *q; + *q = *p; + *p = tmp; + } + } + Note that: + start value = p = &buffer + current_iteration + end value = q = &buffer + len - 1 - current_iteration + Given the loop exit test of "p < q", then there must be "q - p" iterations, + set equal to zero and solve for number of iterations: + q - p = len - 1 - 2*current_iteration = 0 + current_iteration = (len - 1) / 2 + Hence, there are (len - 1) / 2 (rounded up to the nearest integer) + iterations of this loop. */ + +/* ??? Currently, no labels are marked as loop invariant when doing loop + unrolling. This is because an insn inside the loop, that loads the address + of a label inside the loop into a register, could be moved outside the loop + by the invariant code motion pass if labels were invariant. If the loop + is subsequently unrolled, the code will be wrong because each unrolled + body of the loop will use the same address, whereas each actually needs a + different address. A case where this happens is when a loop containing + a switch statement is unrolled. + + It would be better to let labels be considered invariant. When we + unroll loops here, check to see if any insns using a label local to the + loop were moved before the loop. If so, then correct the problem, by + moving the insn back into the loop, or perhaps replicate the insn before + the loop, one copy for each time the loop is unrolled. */ + +/* The prime factors looked for when trying to unroll a loop by some + number which is modulo the total number of iterations. Just checking + for these 4 prime factors will find at least one factor for 75% of + all numbers theoretically. Practically speaking, this will succeed + almost all of the time since loops are generally a multiple of 2 + and/or 5. */ + +#define NUM_FACTORS 4 + +struct _factor { int factor, count; } factors[NUM_FACTORS] + = { {2, 0}, {3, 0}, {5, 0}, {7, 0}}; + +/* Describes the different types of loop unrolling performed. */ + +enum unroll_types { UNROLL_COMPLETELY, UNROLL_MODULO, UNROLL_NAIVE }; + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "integrate.h" +#include "regs.h" +#include "flags.h" +#include "expr.h" +#include +#include "loop.h" + +/* This controls which loops are unrolled, and by how much we unroll + them. */ + +#ifndef MAX_UNROLLED_INSNS +#define MAX_UNROLLED_INSNS 100 +#endif + +/* Indexed by register number, if non-zero, then it contains a pointer + to a struct induction for a DEST_REG giv which has been combined with + one of more address givs. This is needed because whenever such a DEST_REG + giv is modified, we must modify the value of all split address givs + that were combined with this DEST_REG giv. */ + +static struct induction **addr_combined_regs; + +/* Indexed by register number, if this is a splittable induction variable, + then this will hold the current value of the register, which depends on the + iteration number. */ + +static rtx *splittable_regs; + +/* Indexed by register number, if this is a splittable induction variable, + then this will hold the number of instructions in the loop that modify + the induction variable. Used to ensure that only the last insn modifying + a split iv will update the original iv of the dest. */ + +static int *splittable_regs_updates; + +/* Values describing the current loop's iteration variable. These are set up + by loop_iterations, and used by precondition_loop_p. */ + +static rtx loop_iteration_var; +static rtx loop_initial_value; +static rtx loop_increment; +static rtx loop_final_value; + +/* Forward declarations. */ + +static void init_reg_map (); +static int precondition_loop_p (); +static void copy_loop_body (); +static void iteration_info (); +static rtx approx_final_value (); +static int find_splittable_regs (); +static int find_splittable_givs (); +static rtx fold_rtx_mult_add (); + +/* Try to unroll one loop and split induction variables in the loop. + + The loop is described by the arguments LOOP_END, INSN_COUNT, and + LOOP_START. END_INSERT_BEFORE indicates where insns should be added + which need to be executed when the loop falls through. STRENGTH_REDUCTION_P + indicates whether information generated in the strength reduction pass + is available. + + This function is intended to be called from within `strength_reduce' + in loop.c. */ + +void +unroll_loop (loop_end, insn_count, loop_start, end_insert_before, + strength_reduce_p) + rtx loop_end; + int insn_count; + rtx loop_start; + rtx end_insert_before; + int strength_reduce_p; +{ + int i, j, temp; + int unroll_number = 1; + rtx copy_start, copy_end; + rtx insn, copy, sequence, pattern, tem; + int max_labelno, max_insnno; + rtx insert_before; + struct inline_remap *map; + char *local_label; + int maxregnum; + int new_maxregnum; + rtx exit_label = 0; + rtx start_label; + struct iv_class *bl; + struct induction *v; + int splitting_not_safe = 0; + enum unroll_types unroll_type; + int loop_preconditioned = 0; + rtx safety_label; + /* This points to the last real insn in the loop, which should be either + a JUMP_INSN (for conditional jumps) or a BARRIER (for unconditional + jumps). */ + rtx last_loop_insn; + + /* Don't bother unrolling huge loops. Since the minimum factor is + two, loops greater than one half of MAX_UNROLLED_INSNS will never + be unrolled. */ + if (insn_count > MAX_UNROLLED_INSNS / 2) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, "Unrolling failure: Loop too big.\n"); + return; + } + + /* When emitting debugger info, we can't unroll loops with unequal numbers + of block_beg and block_end notes, because that would unbalance the block + structure of the function. This can happen as a result of the + "if (foo) bar; else break;" optimization in jump.c. */ + + if (write_symbols != NO_DEBUG) + { + int block_begins = 0; + int block_ends = 0; + + for (insn = loop_start; insn != loop_end; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == NOTE) + { + if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG) + block_begins++; + else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) + block_ends++; + } + } + + if (block_begins != block_ends) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Unrolling failure: Unbalanced block notes.\n"); + return; + } + } + + /* Determine type of unroll to perform. Depends on the number of iterations + and the size of the loop. */ + + /* If there is no strength reduce info, then set loop_n_iterations to zero. + This can happen if strength_reduce can't find any bivs in the loop. + A value of zero indicates that the number of iterations could not be + calculated. */ + + if (! strength_reduce_p) + loop_n_iterations = 0; + + if (loop_dump_stream && loop_n_iterations > 0) + fprintf (loop_dump_stream, + "Loop unrolling: %d iterations.\n", loop_n_iterations); + + /* Find and save a pointer to the last nonnote insn in the loop. */ + + last_loop_insn = prev_nonnote_insn (loop_end); + + /* Calculate how many times to unroll the loop. Indicate whether or + not the loop is being completely unrolled. */ + + if (loop_n_iterations == 1) + { + /* If number of iterations is exactly 1, then eliminate the compare and + branch at the end of the loop since they will never be taken. + Then return, since no other action is needed here. */ + + /* If the last instruction is not a BARRIER or a JUMP_INSN, then + don't do anything. */ + + if (GET_CODE (last_loop_insn) == BARRIER) + { + /* Delete the jump insn. This will delete the barrier also. */ + delete_insn (PREV_INSN (last_loop_insn)); + } + else if (GET_CODE (last_loop_insn) == JUMP_INSN) + { +#ifdef HAVE_cc0 + /* The immediately preceding insn is a compare which must be + deleted. */ + delete_insn (last_loop_insn); + delete_insn (PREV_INSN (last_loop_insn)); +#else + /* The immediately preceding insn may not be the compare, so don't + delete it. */ + delete_insn (last_loop_insn); +#endif + } + return; + } + else if (loop_n_iterations > 0 + && loop_n_iterations * insn_count < MAX_UNROLLED_INSNS) + { + unroll_number = loop_n_iterations; + unroll_type = UNROLL_COMPLETELY; + } + else if (loop_n_iterations > 0) + { + /* Try to factor the number of iterations. Don't bother with the + general case, only using 2, 3, 5, and 7 will get 75% of all + numbers theoretically, and almost all in practice. */ + + for (i = 0; i < NUM_FACTORS; i++) + factors[i].count = 0; + + temp = loop_n_iterations; + for (i = NUM_FACTORS - 1; i >= 0; i--) + while (temp % factors[i].factor == 0) + { + factors[i].count++; + temp = temp / factors[i].factor; + } + + /* Start with the larger factors first so that we generally + get lots of unrolling. */ + + unroll_number = 1; + temp = insn_count; + for (i = 3; i >= 0; i--) + while (factors[i].count--) + { + if (temp * factors[i].factor < MAX_UNROLLED_INSNS) + { + unroll_number *= factors[i].factor; + temp *= factors[i].factor; + } + else + break; + } + + /* If we couldn't find any factors, then unroll as in the normal + case. */ + if (unroll_number == 1) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: No factors found.\n"); + } + else + unroll_type = UNROLL_MODULO; + } + + + /* Default case, calculate number of times to unroll loop based on its + size. */ + if (unroll_number == 1) + { + if (8 * insn_count < MAX_UNROLLED_INSNS) + unroll_number = 8; + else if (4 * insn_count < MAX_UNROLLED_INSNS) + unroll_number = 4; + else + unroll_number = 2; + + unroll_type = UNROLL_NAIVE; + } + + /* Now we know how many times to unroll the loop. */ + + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Unrolling loop %d times.\n", unroll_number); + + + if (unroll_type == UNROLL_COMPLETELY || unroll_type == UNROLL_MODULO) + { + /* Loops of these types should never start with a jump down to + the exit condition test. For now, check for this case just to + be sure. UNROLL_NAIVE loops can be of this form, this case is + handled below. */ + insn = loop_start; + while (GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != JUMP_INSN) + insn = NEXT_INSN (insn); + if (GET_CODE (insn) == JUMP_INSN) + abort (); + } + + if (unroll_type == UNROLL_COMPLETELY) + { + /* Completely unrolling the loop: Delete the compare and branch at + the end (the last two instructions). This delete must done at the + very end of loop unrolling, to avoid problems with calls to + back_branch_in_range_p, which is called by find_splittable_regs. + All increments of splittable bivs/givs are changed to load constant + instructions. */ + + copy_start = loop_start; + + /* Set insert_before to the instruction immediately after the JUMP_INSN + (or BARRIER), so that any NOTEs between the JUMP_INSN and the end of + the loop will be correctly handled by copy_loop_body. */ + insert_before = NEXT_INSN (last_loop_insn); + + /* Set copy_end to the insn before the jump at the end of the loop. */ + if (GET_CODE (last_loop_insn) == BARRIER) + copy_end = PREV_INSN (PREV_INSN (last_loop_insn)); + else if (GET_CODE (last_loop_insn) == JUMP_INSN) + { +#ifdef HAVE_cc0 + /* The instruction immediately before the JUMP_INSN is a compare + instruction which we do not want to copy. */ + copy_end = PREV_INSN (PREV_INSN (last_loop_insn)); +#else + /* The instruction immediately before the JUMP_INSN may not be the + compare, so we must copy it. */ + copy_end = PREV_INSN (last_loop_insn); +#endif + } + else + { + /* We currently can't unroll a loop if it doesn't end with a + JUMP_INSN. There would need to be a mechanism that recognizes + this case, and then inserts a jump after each loop body, which + jumps to after the last loop body. */ + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Unrolling failure: loop does not end with a JUMP_INSN.\n"); + return; + } + } + else if (unroll_type == UNROLL_MODULO) + { + /* Partially unrolling the loop: The compare and branch at the end + (the last two instructions) must remain. Don't copy the compare + and branch instructions at the end of the loop. Insert the unrolled + code immediately before the compare/branch at the end so that the + code will fall through to them as before. */ + + copy_start = loop_start; + + /* Set insert_before to the jump insn at the end of the loop. + Set copy_end to before the jump insn at the end of the loop. */ + if (GET_CODE (last_loop_insn) == BARRIER) + { + insert_before = PREV_INSN (last_loop_insn); + copy_end = PREV_INSN (insert_before); + } + else if (GET_CODE (last_loop_insn) == JUMP_INSN) + { +#ifdef HAVE_cc0 + /* The instruction immediately before the JUMP_INSN is a compare + instruction which we do not want to copy or delete. */ + insert_before = PREV_INSN (last_loop_insn); + copy_end = PREV_INSN (insert_before); +#else + /* The instruction immediately before the JUMP_INSN may not be the + compare, so we must copy it. */ + insert_before = last_loop_insn; + copy_end = PREV_INSN (last_loop_insn); +#endif + } + else + { + /* We currently can't unroll a loop if it doesn't end with a + JUMP_INSN. There would need to be a mechanism that recognizes + this case, and then inserts a jump after each loop body, which + jumps to after the last loop body. */ + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Unrolling failure: loop does not end with a JUMP_INSN.\n"); + return; + } + } + else + { + /* Normal case: Must copy the compare and branch instructions at the + end of the loop. */ + + if (GET_CODE (last_loop_insn) == BARRIER) + { + /* Loop ends with an unconditional jump and a barrier. + Handle this like above, don't copy jump and barrier. + This is not strictly necessary, but doing so prevents generating + unconditional jumps to an immediately following label. + + This will be corrected below if the target of this jump is + not the start_label. */ + + insert_before = PREV_INSN (last_loop_insn); + copy_end = PREV_INSN (insert_before); + } + else if (GET_CODE (last_loop_insn) == JUMP_INSN) + { + /* Set insert_before to immediately after the JUMP_INSN, so that + NOTEs at the end of the loop will be correctly handled by + copy_loop_body. */ + insert_before = NEXT_INSN (last_loop_insn); + copy_end = last_loop_insn; + } + else + { + /* We currently can't unroll a loop if it doesn't end with a + JUMP_INSN. There would need to be a mechanism that recognizes + this case, and then inserts a jump after each loop body, which + jumps to after the last loop body. */ + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Unrolling failure: loop does not end with a JUMP_INSN.\n"); + return; + } + + /* If copying exit test branches because they can not be eliminated, + then must convert the fall through case of the branch to a jump past + the end of the loop. Create a label to emit after the loop and save + it for later use. Do not use the label after the loop, if any, since + it might be used by insns outside the loop, or there might be insns + added before it later by final_[bg]iv_value which must be after + the real exit label. */ + exit_label = gen_label_rtx (); + + insn = loop_start; + while (GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != JUMP_INSN) + insn = NEXT_INSN (insn); + + if (GET_CODE (insn) == JUMP_INSN) + { + /* The loop starts with a jump down to the exit condition test. + Start copying the loop after the barrier following this + jump insn. */ + copy_start = NEXT_INSN (insn); + + /* Splitting induction variables doesn't work when the loop is + entered via a jump to the bottom, because then we end up doing + a comparison against a new register for a split variable, but + we did not execute the set insn for the new register because + it was skipped over. */ + splitting_not_safe = 1; + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Splitting not safe, because loop not entered at top.\n"); + } + else + copy_start = loop_start; + } + + /* This should always be the first label in the loop. */ + start_label = NEXT_INSN (copy_start); + /* There may be a line number note and/or a loop continue note here. */ + while (GET_CODE (start_label) == NOTE) + start_label = NEXT_INSN (start_label); + if (GET_CODE (start_label) != CODE_LABEL) + { + /* This can happen as a result of jump threading. If the first insns in + the loop test the same condition as the loop's backward jump, or the + opposite condition, then the backward jump will be modified to point + to elsewhere, and the loop's start label is deleted. + + This case currently can not be handled by the loop unrolling code. */ + + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Unrolling failure: unknown insns between BEG note and loop label.\n"); + return; + } + + if (unroll_type == UNROLL_NAIVE + && GET_CODE (last_loop_insn) == BARRIER + && start_label != JUMP_LABEL (PREV_INSN (last_loop_insn))) + { + /* In this case, we must copy the jump and barrier, because they will + not be converted to jumps to an immediately following label. */ + + insert_before = NEXT_INSN (last_loop_insn); + copy_end = last_loop_insn; + } + + /* Allocate a translation table for the labels and insn numbers. + They will be filled in as we copy the insns in the loop. */ + + max_labelno = max_label_num (); + max_insnno = get_max_uid (); + + map = (struct inline_remap *) alloca (sizeof (struct inline_remap)); + + map->integrating = 0; + + /* Allocate the label map. */ + + if (max_labelno > 0) + { + map->label_map = (rtx *) alloca (max_labelno * sizeof (rtx)); + + local_label = (char *) alloca (max_labelno); + bzero (local_label, max_labelno); + } + else + map->label_map = 0; + + /* Search the loop and mark all local labels, i.e. the ones which have to + be distinct labels when copied. For all labels which might be + non-local, set their label_map entries to point to themselves. + If they happen to be local their label_map entries will be overwritten + before the loop body is copied. The label_map entries for local labels + will be set to a different value each time the loop body is copied. */ + + for (insn = copy_start; insn != loop_end; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == CODE_LABEL) + local_label[CODE_LABEL_NUMBER (insn)] = 1; + else if (GET_CODE (insn) == JUMP_INSN) + { + if (JUMP_LABEL (insn)) + map->label_map[CODE_LABEL_NUMBER (JUMP_LABEL (insn))] + = JUMP_LABEL (insn); + else if (GET_CODE (PATTERN (insn)) == ADDR_VEC + || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) + { + rtx pat = PATTERN (insn); + int diff_vec_p = GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC; + int len = XVECLEN (pat, diff_vec_p); + rtx label; + + for (i = 0; i < len; i++) + { + label = XEXP (XVECEXP (pat, diff_vec_p, i), 0); + map->label_map[CODE_LABEL_NUMBER (label)] = label; + } + } + } + } + + /* Allocate space for the insn map. */ + + map->insn_map = (rtx *) alloca (max_insnno * sizeof (rtx)); + + /* Set this to zero, to indicate that we are doing loop unrolling, + not function inlining. */ + map->inline_target = 0; + + /* The register and constant maps depend on the number of registers + present, so the final maps can't be created until after + find_splittable_regs is called. However, they are needed for + preconditioning, so we create temporary maps when preconditioning + is performed. */ + + /* The preconditioning code may allocate two new pseudo registers. */ + maxregnum = max_reg_num (); + + /* Allocate and zero out the splittable_regs and addr_combined_regs + arrays. These must be zeroed here because they will be used if + loop preconditioning is performed, and must be zero for that case. + + It is safe to do this here, since the extra registers created by the + preconditioning code and find_splittable_regs will never be used + to access the splittable_regs[] and addr_combined_regs[] arrays. */ + + splittable_regs = (rtx *) alloca (maxregnum * sizeof (rtx)); + bzero (splittable_regs, maxregnum * sizeof (rtx)); + splittable_regs_updates = (int *) alloca (maxregnum * sizeof (int)); + bzero (splittable_regs_updates, maxregnum * sizeof (int)); + addr_combined_regs + = (struct induction **) alloca (maxregnum * sizeof (struct induction *)); + bzero (addr_combined_regs, maxregnum * sizeof (struct induction *)); + + /* If this loop requires exit tests when unrolled, check to see if we + can precondition the loop so as to make the exit tests unnecessary. + Just like variable splitting, this is not safe if the loop is entered + via a jump to the bottom. Also, can not do this if no strength + reduce info, because precondition_loop_p uses this info. */ + + /* Must copy the loop body for preconditioning before the following + find_splittable_regs call since that will emit insns which need to + be after the preconditioned loop copies, but immediately before the + unrolled loop copies. */ + + /* Also, it is not safe to split induction variables for the preconditioned + copies of the loop body. If we split induction variables, then the code + assumes that each induction variable can be represented as a function + of its initial value and the loop iteration number. This is not true + in this case, because the last preconditioned copy of the loop body + could be any iteration from the first up to the `unroll_number-1'th, + depending on the initial value of the iteration variable. Therefore + we can not split induction variables here, because we can not calculate + their value. Hence, this code must occur before find_splittable_regs + is called. */ + + if (unroll_type == UNROLL_NAIVE && ! splitting_not_safe && strength_reduce_p) + { + rtx initial_value, final_value, increment; + + if (precondition_loop_p (&initial_value, &final_value, &increment, + loop_start, loop_end)) + { + register rtx diff, temp; + enum machine_mode mode; + rtx *labels; + int abs_inc, neg_inc; + + map->reg_map = (rtx *) alloca (maxregnum * sizeof (rtx)); + + map->const_equiv_map = (rtx *) alloca (maxregnum * sizeof (rtx)); + map->const_age_map = (unsigned *) alloca (maxregnum + * sizeof (unsigned)); + map->const_equiv_map_size = maxregnum; + global_const_equiv_map = map->const_equiv_map; + + init_reg_map (map, maxregnum); + + /* Limit loop unrolling to 4, since this will make 7 copies of + the loop body. */ + if (unroll_number > 4) + unroll_number = 4; + + /* Save the absolute value of the increment, and also whether or + not it is negative. */ + neg_inc = 0; + abs_inc = INTVAL (increment); + if (abs_inc < 0) + { + abs_inc = - abs_inc; + neg_inc = 1; + } + + start_sequence (); + + /* Decide what mode to do these calculations in. Choose the larger + of final_value's mode and initial_value's mode, or a full-word if + both are constants. */ + mode = GET_MODE (final_value); + if (mode == VOIDmode) + { + mode = GET_MODE (initial_value); + if (mode == VOIDmode) + mode = word_mode; + } + else if (mode != GET_MODE (initial_value) + && (GET_MODE_SIZE (mode) + < GET_MODE_SIZE (GET_MODE (initial_value)))) + mode = GET_MODE (initial_value); + + /* Calculate the difference between the final and initial values. + Final value may be a (plus (reg x) (const_int 1)) rtx. + Let the following cse pass simplify this if initial value is + a constant. + + We must copy the final and initial values here to avoid + improperly shared rtl. */ + + diff = expand_binop (mode, sub_optab, copy_rtx (final_value), + copy_rtx (initial_value), NULL_RTX, 0, + OPTAB_LIB_WIDEN); + + /* Now calculate (diff % (unroll * abs (increment))) by using an + and instruction. */ + diff = expand_binop (GET_MODE (diff), and_optab, diff, + GEN_INT (unroll_number * abs_inc - 1), + NULL_RTX, 0, OPTAB_LIB_WIDEN); + + /* Now emit a sequence of branches to jump to the proper precond + loop entry point. */ + + labels = (rtx *) alloca (sizeof (rtx) * unroll_number); + for (i = 0; i < unroll_number; i++) + labels[i] = gen_label_rtx (); + + /* Assuming the unroll_number is 4, and the increment is 2, then + for a negative increment: for a positive increment: + diff = 0,1 precond 0 diff = 0,7 precond 0 + diff = 2,3 precond 3 diff = 1,2 precond 1 + diff = 4,5 precond 2 diff = 3,4 precond 2 + diff = 6,7 precond 1 diff = 5,6 precond 3 */ + + /* We only need to emit (unroll_number - 1) branches here, the + last case just falls through to the following code. */ + + /* ??? This would give better code if we emitted a tree of branches + instead of the current linear list of branches. */ + + for (i = 0; i < unroll_number - 1; i++) + { + int cmp_const; + + /* For negative increments, must invert the constant compared + against, except when comparing against zero. */ + if (i == 0) + cmp_const = 0; + else if (neg_inc) + cmp_const = unroll_number - i; + else + cmp_const = i; + + emit_cmp_insn (diff, GEN_INT (abs_inc * cmp_const), + EQ, NULL_RTX, mode, 0, 0); + + if (i == 0) + emit_jump_insn (gen_beq (labels[i])); + else if (neg_inc) + emit_jump_insn (gen_bge (labels[i])); + else + emit_jump_insn (gen_ble (labels[i])); + JUMP_LABEL (get_last_insn ()) = labels[i]; + LABEL_NUSES (labels[i])++; + } + + /* If the increment is greater than one, then we need another branch, + to handle other cases equivalent to 0. */ + + /* ??? This should be merged into the code above somehow to help + simplify the code here, and reduce the number of branches emitted. + For the negative increment case, the branch here could easily + be merged with the `0' case branch above. For the positive + increment case, it is not clear how this can be simplified. */ + + if (abs_inc != 1) + { + int cmp_const; + + if (neg_inc) + cmp_const = abs_inc - 1; + else + cmp_const = abs_inc * (unroll_number - 1) + 1; + + emit_cmp_insn (diff, GEN_INT (cmp_const), EQ, NULL_RTX, + mode, 0, 0); + + if (neg_inc) + emit_jump_insn (gen_ble (labels[0])); + else + emit_jump_insn (gen_bge (labels[0])); + JUMP_LABEL (get_last_insn ()) = labels[0]; + LABEL_NUSES (labels[0])++; + } + + sequence = gen_sequence (); + end_sequence (); + emit_insn_before (sequence, loop_start); + + /* Only the last copy of the loop body here needs the exit + test, so set copy_end to exclude the compare/branch here, + and then reset it inside the loop when get to the last + copy. */ + + if (GET_CODE (last_loop_insn) == BARRIER) + copy_end = PREV_INSN (PREV_INSN (last_loop_insn)); + else if (GET_CODE (last_loop_insn) == JUMP_INSN) + { +#ifdef HAVE_cc0 + /* The immediately preceding insn is a compare which we do not + want to copy. */ + copy_end = PREV_INSN (PREV_INSN (last_loop_insn)); +#else + /* The immediately preceding insn may not be a compare, so we + must copy it. */ + copy_end = PREV_INSN (last_loop_insn); +#endif + } + else + abort (); + + for (i = 1; i < unroll_number; i++) + { + emit_label_after (labels[unroll_number - i], + PREV_INSN (loop_start)); + + bzero (map->insn_map, max_insnno * sizeof (rtx)); + bzero (map->const_equiv_map, maxregnum * sizeof (rtx)); + bzero (map->const_age_map, maxregnum * sizeof (unsigned)); + map->const_age = 0; + + for (j = 0; j < max_labelno; j++) + if (local_label[j]) + map->label_map[j] = gen_label_rtx (); + + /* The last copy needs the compare/branch insns at the end, + so reset copy_end here if the loop ends with a conditional + branch. */ + + if (i == unroll_number - 1) + { + if (GET_CODE (last_loop_insn) == BARRIER) + copy_end = PREV_INSN (PREV_INSN (last_loop_insn)); + else + copy_end = last_loop_insn; + } + + /* None of the copies are the `last_iteration', so just + pass zero for that parameter. */ + copy_loop_body (copy_start, copy_end, map, exit_label, 0, + unroll_type, start_label, loop_end, + loop_start, copy_end); + } + emit_label_after (labels[0], PREV_INSN (loop_start)); + + if (GET_CODE (last_loop_insn) == BARRIER) + { + insert_before = PREV_INSN (last_loop_insn); + copy_end = PREV_INSN (insert_before); + } + else + { +#ifdef HAVE_cc0 + /* The immediately preceding insn is a compare which we do not + want to copy. */ + insert_before = PREV_INSN (last_loop_insn); + copy_end = PREV_INSN (insert_before); +#else + /* The immediately preceding insn may not be a compare, so we + must copy it. */ + insert_before = last_loop_insn; + copy_end = PREV_INSN (last_loop_insn); +#endif + } + + /* Set unroll type to MODULO now. */ + unroll_type = UNROLL_MODULO; + loop_preconditioned = 1; + } + } + + /* If reach here, and the loop type is UNROLL_NAIVE, then don't unroll + the loop unless all loops are being unrolled. */ + if (unroll_type == UNROLL_NAIVE && ! flag_unroll_all_loops) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, "Unrolling failure: Naive unrolling not being done.\n"); + return; + } + + /* At this point, we are guaranteed to unroll the loop. */ + + /* For each biv and giv, determine whether it can be safely split into + a different variable for each unrolled copy of the loop body. + We precalculate and save this info here, since computing it is + expensive. + + Do this before deleting any instructions from the loop, so that + back_branch_in_range_p will work correctly. */ + + if (splitting_not_safe) + temp = 0; + else + temp = find_splittable_regs (unroll_type, loop_start, loop_end, + end_insert_before, unroll_number); + + /* find_splittable_regs may have created some new registers, so must + reallocate the reg_map with the new larger size, and must realloc + the constant maps also. */ + + maxregnum = max_reg_num (); + map->reg_map = (rtx *) alloca (maxregnum * sizeof (rtx)); + + init_reg_map (map, maxregnum); + + /* Space is needed in some of the map for new registers, so new_maxregnum + is an (over)estimate of how many registers will exist at the end. */ + new_maxregnum = maxregnum + (temp * unroll_number * 2); + + /* Must realloc space for the constant maps, because the number of registers + may have changed. */ + + map->const_equiv_map = (rtx *) alloca (new_maxregnum * sizeof (rtx)); + map->const_age_map = (unsigned *) alloca (new_maxregnum * sizeof (unsigned)); + + global_const_equiv_map = map->const_equiv_map; + + /* Search the list of bivs and givs to find ones which need to be remapped + when split, and set their reg_map entry appropriately. */ + + for (bl = loop_iv_list; bl; bl = bl->next) + { + if (REGNO (bl->biv->src_reg) != bl->regno) + map->reg_map[bl->regno] = bl->biv->src_reg; +#if 0 + /* Currently, non-reduced/final-value givs are never split. */ + for (v = bl->giv; v; v = v->next_iv) + if (REGNO (v->src_reg) != bl->regno) + map->reg_map[REGNO (v->dest_reg)] = v->src_reg; +#endif + } + + /* If the loop is being partially unrolled, and the iteration variables + are being split, and are being renamed for the split, then must fix up + the compare instruction at the end of the loop to refer to the new + registers. This compare isn't copied, so the registers used in it + will never be replaced if it isn't done here. */ + + if (unroll_type == UNROLL_MODULO) + { + insn = NEXT_INSN (copy_end); + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET) + { +#if 0 + /* If non-reduced/final-value givs were split, then this would also + have to remap those givs. */ +#endif + + tem = SET_SRC (PATTERN (insn)); + /* The set source is a register. */ + if (GET_CODE (tem) == REG) + { + if (REGNO (tem) < max_reg_before_loop + && reg_iv_type[REGNO (tem)] == BASIC_INDUCT) + SET_SRC (PATTERN (insn)) + = reg_biv_class[REGNO (tem)]->biv->src_reg; + } + else + { + /* The set source is a compare of some sort. */ + tem = XEXP (SET_SRC (PATTERN (insn)), 0); + if (GET_CODE (tem) == REG + && REGNO (tem) < max_reg_before_loop + && reg_iv_type[REGNO (tem)] == BASIC_INDUCT) + XEXP (SET_SRC (PATTERN (insn)), 0) + = reg_biv_class[REGNO (tem)]->biv->src_reg; + + tem = XEXP (SET_SRC (PATTERN (insn)), 1); + if (GET_CODE (tem) == REG + && REGNO (tem) < max_reg_before_loop + && reg_iv_type[REGNO (tem)] == BASIC_INDUCT) + XEXP (SET_SRC (PATTERN (insn)), 1) + = reg_biv_class[REGNO (tem)]->biv->src_reg; + } + } + } + + /* For unroll_number - 1 times, make a copy of each instruction + between copy_start and copy_end, and insert these new instructions + before the end of the loop. */ + + for (i = 0; i < unroll_number; i++) + { + bzero (map->insn_map, max_insnno * sizeof (rtx)); + bzero (map->const_equiv_map, new_maxregnum * sizeof (rtx)); + bzero (map->const_age_map, new_maxregnum * sizeof (unsigned)); + map->const_age = 0; + + for (j = 0; j < max_labelno; j++) + if (local_label[j]) + map->label_map[j] = gen_label_rtx (); + + /* If loop starts with a branch to the test, then fix it so that + it points to the test of the first unrolled copy of the loop. */ + if (i == 0 && loop_start != copy_start) + { + insn = PREV_INSN (copy_start); + pattern = PATTERN (insn); + + tem = map->label_map[CODE_LABEL_NUMBER + (XEXP (SET_SRC (pattern), 0))]; + SET_SRC (pattern) = gen_rtx (LABEL_REF, VOIDmode, tem); + + /* Set the jump label so that it can be used by later loop unrolling + passes. */ + JUMP_LABEL (insn) = tem; + LABEL_NUSES (tem)++; + } + + copy_loop_body (copy_start, copy_end, map, exit_label, + i == unroll_number - 1, unroll_type, start_label, + loop_end, insert_before, insert_before); + } + + /* Before deleting any insns, emit a CODE_LABEL immediately after the last + insn to be deleted. This prevents any runaway delete_insn call from + more insns that it should, as it always stops at a CODE_LABEL. */ + + /* Delete the compare and branch at the end of the loop if completely + unrolling the loop. Deleting the backward branch at the end also + deletes the code label at the start of the loop. This is done at + the very end to avoid problems with back_branch_in_range_p. */ + + if (unroll_type == UNROLL_COMPLETELY) + safety_label = emit_label_after (gen_label_rtx (), last_loop_insn); + else + safety_label = emit_label_after (gen_label_rtx (), copy_end); + + /* Delete all of the original loop instructions. Don't delete the + LOOP_BEG note, or the first code label in the loop. */ + + insn = NEXT_INSN (copy_start); + while (insn != safety_label) + { + if (insn != start_label) + insn = delete_insn (insn); + else + insn = NEXT_INSN (insn); + } + + /* Can now delete the 'safety' label emitted to protect us from runaway + delete_insn calls. */ + if (INSN_DELETED_P (safety_label)) + abort (); + delete_insn (safety_label); + + /* If exit_label exists, emit it after the loop. Doing the emit here + forces it to have a higher INSN_UID than any insn in the unrolled loop. + This is needed so that mostly_true_jump in reorg.c will treat jumps + to this loop end label correctly, i.e. predict that they are usually + not taken. */ + if (exit_label) + emit_label_after (exit_label, loop_end); +} + +/* Return true if the loop can be safely, and profitably, preconditioned + so that the unrolled copies of the loop body don't need exit tests. + + This only works if final_value, initial_value and increment can be + determined, and if increment is a constant power of 2. + If increment is not a power of 2, then the preconditioning modulo + operation would require a real modulo instead of a boolean AND, and this + is not considered `profitable'. */ + +/* ??? If the loop is known to be executed very many times, or the machine + has a very cheap divide instruction, then preconditioning is a win even + when the increment is not a power of 2. Use RTX_COST to compute + whether divide is cheap. */ + +static int +precondition_loop_p (initial_value, final_value, increment, loop_start, + loop_end) + rtx *initial_value, *final_value, *increment; + rtx loop_start, loop_end; +{ + int unsigned_compare, compare_dir; + + if (loop_n_iterations > 0) + { + *initial_value = const0_rtx; + *increment = const1_rtx; + *final_value = GEN_INT (loop_n_iterations); + + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Preconditioning: Success, number of iterations known, %d.\n", + loop_n_iterations); + return 1; + } + + if (loop_initial_value == 0) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Preconditioning: Could not find initial value.\n"); + return 0; + } + else if (loop_increment == 0) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Preconditioning: Could not find increment value.\n"); + return 0; + } + else if (GET_CODE (loop_increment) != CONST_INT) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Preconditioning: Increment not a constant.\n"); + return 0; + } + else if ((exact_log2 (INTVAL (loop_increment)) < 0) + && (exact_log2 (- INTVAL (loop_increment)) < 0)) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Preconditioning: Increment not a constant power of 2.\n"); + return 0; + } + + /* Unsigned_compare and compare_dir can be ignored here, since they do + not matter for preconditioning. */ + + if (loop_final_value == 0) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Preconditioning: EQ comparison loop.\n"); + return 0; + } + + /* Must ensure that final_value is invariant, so call invariant_p to + check. Before doing so, must check regno against max_reg_before_loop + to make sure that the register is in the range covered by invariant_p. + If it isn't, then it is most likely a biv/giv which by definition are + not invariant. */ + if ((GET_CODE (loop_final_value) == REG + && REGNO (loop_final_value) >= max_reg_before_loop) + || (GET_CODE (loop_final_value) == PLUS + && REGNO (XEXP (loop_final_value, 0)) >= max_reg_before_loop) + || ! invariant_p (loop_final_value)) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Preconditioning: Final value not invariant.\n"); + return 0; + } + + /* Fail for floating point values, since the caller of this function + does not have code to deal with them. */ + if (GET_MODE_CLASS (GET_MODE (loop_final_value)) == MODE_FLOAT + || GET_MODE_CLASS (GET_MODE (loop_initial_value)) == MODE_FLOAT) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Preconditioning: Floating point final or initial value.\n"); + return 0; + } + + /* Now set initial_value to be the iteration_var, since that may be a + simpler expression, and is guaranteed to be correct if all of the + above tests succeed. + + We can not use the initial_value as calculated, because it will be + one too small for loops of the form "while (i-- > 0)". We can not + emit code before the loop_skip_over insns to fix this problem as this + will then give a number one too large for loops of the form + "while (--i > 0)". + + Note that all loops that reach here are entered at the top, because + this function is not called if the loop starts with a jump. */ + + /* Fail if loop_iteration_var is not live before loop_start, since we need + to test its value in the preconditioning code. */ + + if (uid_luid[regno_first_uid[REGNO (loop_iteration_var)]] + > INSN_LUID (loop_start)) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Preconditioning: Iteration var not live before loop start.\n"); + return 0; + } + + *initial_value = loop_iteration_var; + *increment = loop_increment; + *final_value = loop_final_value; + + /* Success! */ + if (loop_dump_stream) + fprintf (loop_dump_stream, "Preconditioning: Successful.\n"); + return 1; +} + + +/* All pseudo-registers must be mapped to themselves. Two hard registers + must be mapped, VIRTUAL_STACK_VARS_REGNUM and VIRTUAL_INCOMING_ARGS_ + REGNUM, to avoid function-inlining specific conversions of these + registers. All other hard regs can not be mapped because they may be + used with different + modes. */ + +static void +init_reg_map (map, maxregnum) + struct inline_remap *map; + int maxregnum; +{ + int i; + + for (i = maxregnum - 1; i > LAST_VIRTUAL_REGISTER; i--) + map->reg_map[i] = regno_reg_rtx[i]; + /* Just clear the rest of the entries. */ + for (i = LAST_VIRTUAL_REGISTER; i >= 0; i--) + map->reg_map[i] = 0; + + map->reg_map[VIRTUAL_STACK_VARS_REGNUM] + = regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM]; + map->reg_map[VIRTUAL_INCOMING_ARGS_REGNUM] + = regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM]; +} + +/* Strength-reduction will often emit code for optimized biv/givs which + calculates their value in a temporary register, and then copies the result + to the iv. This procedure reconstructs the pattern computing the iv; + verifying that all operands are of the proper form. + + The return value is the amount that the giv is incremented by. */ + +static rtx +calculate_giv_inc (pattern, src_insn, regno) + rtx pattern, src_insn; + int regno; +{ + rtx increment; + rtx increment_total = 0; + int tries = 0; + + retry: + /* Verify that we have an increment insn here. First check for a plus + as the set source. */ + if (GET_CODE (SET_SRC (pattern)) != PLUS) + { + /* SR sometimes computes the new giv value in a temp, then copies it + to the new_reg. */ + src_insn = PREV_INSN (src_insn); + pattern = PATTERN (src_insn); + if (GET_CODE (SET_SRC (pattern)) != PLUS) + abort (); + + /* The last insn emitted is not needed, so delete it to avoid confusing + the second cse pass. This insn sets the giv unnecessarily. */ + delete_insn (get_last_insn ()); + } + + /* Verify that we have a constant as the second operand of the plus. */ + increment = XEXP (SET_SRC (pattern), 1); + if (GET_CODE (increment) != CONST_INT) + { + /* SR sometimes puts the constant in a register, especially if it is + too big to be an add immed operand. */ + src_insn = PREV_INSN (src_insn); + increment = SET_SRC (PATTERN (src_insn)); + + /* SR may have used LO_SUM to compute the constant if it is too large + for a load immed operand. In this case, the constant is in operand + one of the LO_SUM rtx. */ + if (GET_CODE (increment) == LO_SUM) + increment = XEXP (increment, 1); + + if (GET_CODE (increment) != CONST_INT) + abort (); + + /* The insn loading the constant into a register is not longer needed, + so delete it. */ + delete_insn (get_last_insn ()); + } + + if (increment_total) + increment_total = GEN_INT (INTVAL (increment_total) + INTVAL (increment)); + else + increment_total = increment; + + /* Check that the source register is the same as the register we expected + to see as the source. If not, something is seriously wrong. */ + if (GET_CODE (XEXP (SET_SRC (pattern), 0)) != REG + || REGNO (XEXP (SET_SRC (pattern), 0)) != regno) + { + /* Some machines (e.g. the romp), may emit two add instructions for + certain constants, so lets try looking for another add immediately + before this one if we have only seen one add insn so far. */ + + if (tries == 0) + { + tries++; + + src_insn = PREV_INSN (src_insn); + pattern = PATTERN (src_insn); + + delete_insn (get_last_insn ()); + + goto retry; + } + + abort (); + } + + return increment_total; +} + +/* Copy REG_NOTES, except for insn references, because not all insn_map + entries are valid yet. We do need to copy registers now though, because + the reg_map entries can change during copying. */ + +static rtx +initial_reg_note_copy (notes, map) + rtx notes; + struct inline_remap *map; +{ + rtx copy; + + if (notes == 0) + return 0; + + copy = rtx_alloc (GET_CODE (notes)); + PUT_MODE (copy, GET_MODE (notes)); + + if (GET_CODE (notes) == EXPR_LIST) + XEXP (copy, 0) = copy_rtx_and_substitute (XEXP (notes, 0), map); + else if (GET_CODE (notes) == INSN_LIST) + /* Don't substitute for these yet. */ + XEXP (copy, 0) = XEXP (notes, 0); + else + abort (); + + XEXP (copy, 1) = initial_reg_note_copy (XEXP (notes, 1), map); + + return copy; +} + +/* Fixup insn references in copied REG_NOTES. */ + +static void +final_reg_note_copy (notes, map) + rtx notes; + struct inline_remap *map; +{ + rtx note; + + for (note = notes; note; note = XEXP (note, 1)) + if (GET_CODE (note) == INSN_LIST) + XEXP (note, 0) = map->insn_map[INSN_UID (XEXP (note, 0))]; +} + +/* Copy each instruction in the loop, substituting from map as appropriate. + This is very similar to a loop in expand_inline_function. */ + +static void +copy_loop_body (copy_start, copy_end, map, exit_label, last_iteration, + unroll_type, start_label, loop_end, insert_before, + copy_notes_from) + rtx copy_start, copy_end; + struct inline_remap *map; + rtx exit_label; + int last_iteration; + enum unroll_types unroll_type; + rtx start_label, loop_end, insert_before, copy_notes_from; +{ + rtx insn, pattern; + rtx tem, copy; + int dest_reg_was_split, i; + rtx cc0_insn = 0; + rtx final_label = 0; + rtx giv_inc, giv_dest_reg, giv_src_reg; + + /* If this isn't the last iteration, then map any references to the + start_label to final_label. Final label will then be emitted immediately + after the end of this loop body if it was ever used. + + If this is the last iteration, then map references to the start_label + to itself. */ + if (! last_iteration) + { + final_label = gen_label_rtx (); + map->label_map[CODE_LABEL_NUMBER (start_label)] = final_label; + } + else + map->label_map[CODE_LABEL_NUMBER (start_label)] = start_label; + + start_sequence (); + + insn = copy_start; + do + { + insn = NEXT_INSN (insn); + + map->orig_asm_operands_vector = 0; + + switch (GET_CODE (insn)) + { + case INSN: + pattern = PATTERN (insn); + copy = 0; + giv_inc = 0; + + /* Check to see if this is a giv that has been combined with + some split address givs. (Combined in the sense that + `combine_givs' in loop.c has put two givs in the same register.) + In this case, we must search all givs based on the same biv to + find the address givs. Then split the address givs. + Do this before splitting the giv, since that may map the + SET_DEST to a new register. */ + + if (GET_CODE (pattern) == SET + && GET_CODE (SET_DEST (pattern)) == REG + && addr_combined_regs[REGNO (SET_DEST (pattern))]) + { + struct iv_class *bl; + struct induction *v, *tv; + int regno = REGNO (SET_DEST (pattern)); + + v = addr_combined_regs[REGNO (SET_DEST (pattern))]; + bl = reg_biv_class[REGNO (v->src_reg)]; + + /* Although the giv_inc amount is not needed here, we must call + calculate_giv_inc here since it might try to delete the + last insn emitted. If we wait until later to call it, + we might accidentally delete insns generated immediately + below by emit_unrolled_add. */ + + giv_inc = calculate_giv_inc (pattern, insn, regno); + + /* Now find all address giv's that were combined with this + giv 'v'. */ + for (tv = bl->giv; tv; tv = tv->next_iv) + if (tv->giv_type == DEST_ADDR && tv->same == v) + { + int this_giv_inc = INTVAL (giv_inc); + + /* Scale this_giv_inc if the multiplicative factors of + the two givs are different. */ + if (tv->mult_val != v->mult_val) + this_giv_inc = (this_giv_inc / INTVAL (v->mult_val) + * INTVAL (tv->mult_val)); + + tv->dest_reg = plus_constant (tv->dest_reg, this_giv_inc); + *tv->location = tv->dest_reg; + + if (last_iteration && unroll_type != UNROLL_COMPLETELY) + { + /* Must emit an insn to increment the split address + giv. Add in the const_adjust field in case there + was a constant eliminated from the address. */ + rtx value, dest_reg; + + /* tv->dest_reg will be either a bare register, + or else a register plus a constant. */ + if (GET_CODE (tv->dest_reg) == REG) + dest_reg = tv->dest_reg; + else + dest_reg = XEXP (tv->dest_reg, 0); + + /* tv->dest_reg may actually be a (PLUS (REG) (CONST)) + here, so we must call plus_constant to add + the const_adjust amount before calling + emit_unrolled_add below. */ + value = plus_constant (tv->dest_reg, tv->const_adjust); + + /* The constant could be too large for an add + immediate, so can't directly emit an insn here. */ + emit_unrolled_add (dest_reg, XEXP (value, 0), + XEXP (value, 1)); + + /* Reset the giv to be just the register again, in case + it is used after the set we have just emitted. + We must subtract the const_adjust factor added in + above. */ + tv->dest_reg = plus_constant (dest_reg, + - tv->const_adjust); + *tv->location = tv->dest_reg; + } + } + } + + /* If this is a setting of a splittable variable, then determine + how to split the variable, create a new set based on this split, + and set up the reg_map so that later uses of the variable will + use the new split variable. */ + + dest_reg_was_split = 0; + + if (GET_CODE (pattern) == SET + && GET_CODE (SET_DEST (pattern)) == REG + && splittable_regs[REGNO (SET_DEST (pattern))]) + { + int regno = REGNO (SET_DEST (pattern)); + + dest_reg_was_split = 1; + + /* Compute the increment value for the giv, if it wasn't + already computed above. */ + + if (giv_inc == 0) + giv_inc = calculate_giv_inc (pattern, insn, regno); + giv_dest_reg = SET_DEST (pattern); + giv_src_reg = SET_DEST (pattern); + + if (unroll_type == UNROLL_COMPLETELY) + { + /* Completely unrolling the loop. Set the induction + variable to a known constant value. */ + + /* The value in splittable_regs may be an invariant + value, so we must use plus_constant here. */ + splittable_regs[regno] + = plus_constant (splittable_regs[regno], INTVAL (giv_inc)); + + if (GET_CODE (splittable_regs[regno]) == PLUS) + { + giv_src_reg = XEXP (splittable_regs[regno], 0); + giv_inc = XEXP (splittable_regs[regno], 1); + } + else + { + /* The splittable_regs value must be a REG or a + CONST_INT, so put the entire value in the giv_src_reg + variable. */ + giv_src_reg = splittable_regs[regno]; + giv_inc = const0_rtx; + } + } + else + { + /* Partially unrolling loop. Create a new pseudo + register for the iteration variable, and set it to + be a constant plus the original register. Except + on the last iteration, when the result has to + go back into the original iteration var register. */ + + /* Handle bivs which must be mapped to a new register + when split. This happens for bivs which need their + final value set before loop entry. The new register + for the biv was stored in the biv's first struct + induction entry by find_splittable_regs. */ + + if (regno < max_reg_before_loop + && reg_iv_type[regno] == BASIC_INDUCT) + { + giv_src_reg = reg_biv_class[regno]->biv->src_reg; + giv_dest_reg = giv_src_reg; + } + +#if 0 + /* If non-reduced/final-value givs were split, then + this would have to remap those givs also. See + find_splittable_regs. */ +#endif + + splittable_regs[regno] + = GEN_INT (INTVAL (giv_inc) + + INTVAL (splittable_regs[regno])); + giv_inc = splittable_regs[regno]; + + /* Now split the induction variable by changing the dest + of this insn to a new register, and setting its + reg_map entry to point to this new register. + + If this is the last iteration, and this is the last insn + that will update the iv, then reuse the original dest, + to ensure that the iv will have the proper value when + the loop exits or repeats. + + Using splittable_regs_updates here like this is safe, + because it can only be greater than one if all + instructions modifying the iv are always executed in + order. */ + + if (! last_iteration + || (splittable_regs_updates[regno]-- != 1)) + { + tem = gen_reg_rtx (GET_MODE (giv_src_reg)); + giv_dest_reg = tem; + map->reg_map[regno] = tem; + } + else + map->reg_map[regno] = giv_src_reg; + } + + /* The constant being added could be too large for an add + immediate, so can't directly emit an insn here. */ + emit_unrolled_add (giv_dest_reg, giv_src_reg, giv_inc); + copy = get_last_insn (); + pattern = PATTERN (copy); + } + else + { + pattern = copy_rtx_and_substitute (pattern, map); + copy = emit_insn (pattern); + } + REG_NOTES (copy) = initial_reg_note_copy (REG_NOTES (insn), map); + +#ifdef HAVE_cc0 + /* If this insn is setting CC0, it may need to look at + the insn that uses CC0 to see what type of insn it is. + In that case, the call to recog via validate_change will + fail. So don't substitute constants here. Instead, + do it when we emit the following insn. + + For example, see the pyr.md file. That machine has signed and + unsigned compares. The compare patterns must check the + following branch insn to see which what kind of compare to + emit. + + If the previous insn set CC0, substitute constants on it as + well. */ + if (sets_cc0_p (copy) != 0) + cc0_insn = copy; + else + { + if (cc0_insn) + try_constants (cc0_insn, map); + cc0_insn = 0; + try_constants (copy, map); + } +#else + try_constants (copy, map); +#endif + + /* Make split induction variable constants `permanent' since we + know there are no backward branches across iteration variable + settings which would invalidate this. */ + if (dest_reg_was_split) + { + int regno = REGNO (SET_DEST (pattern)); + + if (map->const_age_map[regno] == map->const_age) + map->const_age_map[regno] = -1; + } + break; + + case JUMP_INSN: + pattern = copy_rtx_and_substitute (PATTERN (insn), map); + copy = emit_jump_insn (pattern); + REG_NOTES (copy) = initial_reg_note_copy (REG_NOTES (insn), map); + + if (JUMP_LABEL (insn) == start_label && insn == copy_end + && ! last_iteration) + { + /* This is a branch to the beginning of the loop; this is the + last insn being copied; and this is not the last iteration. + In this case, we want to change the original fall through + case to be a branch past the end of the loop, and the + original jump label case to fall_through. */ + + if (! invert_exp (pattern, copy) + || ! redirect_exp (&pattern, + map->label_map[CODE_LABEL_NUMBER + (JUMP_LABEL (insn))], + exit_label, copy)) + abort (); + } + +#ifdef HAVE_cc0 + if (cc0_insn) + try_constants (cc0_insn, map); + cc0_insn = 0; +#endif + try_constants (copy, map); + + /* Set the jump label of COPY correctly to avoid problems with + later passes of unroll_loop, if INSN had jump label set. */ + if (JUMP_LABEL (insn)) + { + rtx label = 0; + + /* Can't use the label_map for every insn, since this may be + the backward branch, and hence the label was not mapped. */ + if (GET_CODE (pattern) == SET) + { + tem = SET_SRC (pattern); + if (GET_CODE (tem) == LABEL_REF) + label = XEXP (tem, 0); + else if (GET_CODE (tem) == IF_THEN_ELSE) + { + if (XEXP (tem, 1) != pc_rtx) + label = XEXP (XEXP (tem, 1), 0); + else + label = XEXP (XEXP (tem, 2), 0); + } + } + + if (label && GET_CODE (label) == CODE_LABEL) + JUMP_LABEL (copy) = label; + else + { + /* An unrecognizable jump insn, probably the entry jump + for a switch statement. This label must have been mapped, + so just use the label_map to get the new jump label. */ + JUMP_LABEL (copy) = map->label_map[CODE_LABEL_NUMBER + (JUMP_LABEL (insn))]; + } + + /* If this is a non-local jump, then must increase the label + use count so that the label will not be deleted when the + original jump is deleted. */ + LABEL_NUSES (JUMP_LABEL (copy))++; + } + else if (GET_CODE (PATTERN (copy)) == ADDR_VEC + || GET_CODE (PATTERN (copy)) == ADDR_DIFF_VEC) + { + rtx pat = PATTERN (copy); + int diff_vec_p = GET_CODE (pat) == ADDR_DIFF_VEC; + int len = XVECLEN (pat, diff_vec_p); + int i; + + for (i = 0; i < len; i++) + LABEL_NUSES (XEXP (XVECEXP (pat, diff_vec_p, i), 0))++; + } + + /* If this used to be a conditional jump insn but whose branch + direction is now known, we must do something special. */ + if (condjump_p (insn) && !simplejump_p (insn) && map->last_pc_value) + { +#ifdef HAVE_cc0 + /* The previous insn set cc0 for us. So delete it. */ + delete_insn (PREV_INSN (copy)); +#endif + + /* If this is now a no-op, delete it. */ + if (map->last_pc_value == pc_rtx) + { + delete_insn (copy); + copy = 0; + } + else + /* Otherwise, this is unconditional jump so we must put a + BARRIER after it. We could do some dead code elimination + here, but jump.c will do it just as well. */ + emit_barrier (); + } + break; + + case CALL_INSN: + pattern = copy_rtx_and_substitute (PATTERN (insn), map); + copy = emit_call_insn (pattern); + REG_NOTES (copy) = initial_reg_note_copy (REG_NOTES (insn), map); + +#ifdef HAVE_cc0 + if (cc0_insn) + try_constants (cc0_insn, map); + cc0_insn = 0; +#endif + try_constants (copy, map); + + /* Be lazy and assume CALL_INSNs clobber all hard registers. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + map->const_equiv_map[i] = 0; + break; + + case CODE_LABEL: + /* If this is the loop start label, then we don't need to emit a + copy of this label since no one will use it. */ + + if (insn != start_label) + { + copy = emit_label (map->label_map[CODE_LABEL_NUMBER (insn)]); + map->const_age++; + } + break; + + case BARRIER: + copy = emit_barrier (); + break; + + case NOTE: + /* VTOP notes are valid only before the loop exit test. If placed + anywhere else, loop may generate bad code. */ + + if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED + && (NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_VTOP + || (last_iteration && unroll_type != UNROLL_COMPLETELY))) + copy = emit_note (NOTE_SOURCE_FILE (insn), + NOTE_LINE_NUMBER (insn)); + else + copy = 0; + break; + + default: + abort (); + break; + } + + map->insn_map[INSN_UID (insn)] = copy; + } + while (insn != copy_end); + + /* Now finish coping the REG_NOTES. */ + insn = copy_start; + do + { + insn = NEXT_INSN (insn); + if ((GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN + || GET_CODE (insn) == CALL_INSN) + && map->insn_map[INSN_UID (insn)]) + final_reg_note_copy (REG_NOTES (map->insn_map[INSN_UID (insn)]), map); + } + while (insn != copy_end); + + /* There may be notes between copy_notes_from and loop_end. Emit a copy of + each of these notes here, since there may be some important ones, such as + NOTE_INSN_BLOCK_END notes, in this group. We don't do this on the last + iteration, because the original notes won't be deleted. + + We can't use insert_before here, because when from preconditioning, + insert_before points before the loop. We can't use copy_end, because + there may be insns already inserted after it (which we don't want to + copy) when not from preconditioning code. */ + + if (! last_iteration) + { + for (insn = copy_notes_from; insn != loop_end; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == NOTE + && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED) + emit_note (NOTE_SOURCE_FILE (insn), NOTE_LINE_NUMBER (insn)); + } + } + + if (final_label && LABEL_NUSES (final_label) > 0) + emit_label (final_label); + + tem = gen_sequence (); + end_sequence (); + emit_insn_before (tem, insert_before); +} + +/* Emit an insn, using the expand_binop to ensure that a valid insn is + emitted. This will correctly handle the case where the increment value + won't fit in the immediate field of a PLUS insns. */ + +void +emit_unrolled_add (dest_reg, src_reg, increment) + rtx dest_reg, src_reg, increment; +{ + rtx result; + + result = expand_binop (GET_MODE (dest_reg), add_optab, src_reg, increment, + dest_reg, 0, OPTAB_LIB_WIDEN); + + if (dest_reg != result) + emit_move_insn (dest_reg, result); +} + +/* Searches the insns between INSN and LOOP_END. Returns 1 if there + is a backward branch in that range that branches to somewhere between + LOOP_START and INSN. Returns 0 otherwise. */ + +/* ??? This is quadratic algorithm. Could be rewritten to be linear. + In practice, this is not a problem, because this function is seldom called, + and uses a negligible amount of CPU time on average. */ + +static int +back_branch_in_range_p (insn, loop_start, loop_end) + rtx insn; + rtx loop_start, loop_end; +{ + rtx p, q, target_insn; + + /* Stop before we get to the backward branch at the end of the loop. */ + loop_end = prev_nonnote_insn (loop_end); + if (GET_CODE (loop_end) == BARRIER) + loop_end = PREV_INSN (loop_end); + + /* Check in case insn has been deleted, search forward for first non + deleted insn following it. */ + while (INSN_DELETED_P (insn)) + insn = NEXT_INSN (insn); + + /* Check for the case where insn is the last insn in the loop. */ + if (insn == loop_end) + return 0; + + for (p = NEXT_INSN (insn); p != loop_end; p = NEXT_INSN (p)) + { + if (GET_CODE (p) == JUMP_INSN) + { + target_insn = JUMP_LABEL (p); + + /* Search from loop_start to insn, to see if one of them is + the target_insn. We can't use INSN_LUID comparisons here, + since insn may not have an LUID entry. */ + for (q = loop_start; q != insn; q = NEXT_INSN (q)) + if (q == target_insn) + return 1; + } + } + + return 0; +} + +/* Try to generate the simplest rtx for the expression + (PLUS (MULT mult1 mult2) add1). This is used to calculate the initial + value of giv's. */ + +static rtx +fold_rtx_mult_add (mult1, mult2, add1, mode) + rtx mult1, mult2, add1; + enum machine_mode mode; +{ + rtx temp, mult_res; + rtx result; + + /* The modes must all be the same. This should always be true. For now, + check to make sure. */ + if ((GET_MODE (mult1) != mode && GET_MODE (mult1) != VOIDmode) + || (GET_MODE (mult2) != mode && GET_MODE (mult2) != VOIDmode) + || (GET_MODE (add1) != mode && GET_MODE (add1) != VOIDmode)) + abort (); + + /* Ensure that if at least one of mult1/mult2 are constant, then mult2 + will be a constant. */ + if (GET_CODE (mult1) == CONST_INT) + { + temp = mult2; + mult2 = mult1; + mult1 = temp; + } + + mult_res = simplify_binary_operation (MULT, mode, mult1, mult2); + if (! mult_res) + mult_res = gen_rtx (MULT, mode, mult1, mult2); + + /* Again, put the constant second. */ + if (GET_CODE (add1) == CONST_INT) + { + temp = add1; + add1 = mult_res; + mult_res = temp; + } + + result = simplify_binary_operation (PLUS, mode, add1, mult_res); + if (! result) + result = gen_rtx (PLUS, mode, add1, mult_res); + + return result; +} + +/* Searches the list of induction struct's for the biv BL, to try to calculate + the total increment value for one iteration of the loop as a constant. + + Returns the increment value as an rtx, simplified as much as possible, + if it can be calculated. Otherwise, returns 0. */ + +rtx +biv_total_increment (bl, loop_start, loop_end) + struct iv_class *bl; + rtx loop_start, loop_end; +{ + struct induction *v; + rtx result; + + /* For increment, must check every instruction that sets it. Each + instruction must be executed only once each time through the loop. + To verify this, we check that the the insn is always executed, and that + there are no backward branches after the insn that branch to before it. + Also, the insn must have a mult_val of one (to make sure it really is + an increment). */ + + result = const0_rtx; + for (v = bl->biv; v; v = v->next_iv) + { + if (v->always_computable && v->mult_val == const1_rtx + && ! back_branch_in_range_p (v->insn, loop_start, loop_end)) + result = fold_rtx_mult_add (result, const1_rtx, v->add_val, v->mode); + else + return 0; + } + + return result; +} + +/* Determine the initial value of the iteration variable, and the amount + that it is incremented each loop. Use the tables constructed by + the strength reduction pass to calculate these values. + + Initial_value and/or increment are set to zero if their values could not + be calculated. */ + +static void +iteration_info (iteration_var, initial_value, increment, loop_start, loop_end) + rtx iteration_var, *initial_value, *increment; + rtx loop_start, loop_end; +{ + struct iv_class *bl; + struct induction *v, *b; + + /* Clear the result values, in case no answer can be found. */ + *initial_value = 0; + *increment = 0; + + /* The iteration variable can be either a giv or a biv. Check to see + which it is, and compute the variable's initial value, and increment + value if possible. */ + + /* If this is a new register, can't handle it since we don't have any + reg_iv_type entry for it. */ + if (REGNO (iteration_var) >= max_reg_before_loop) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: No reg_iv_type entry for iteration var.\n"); + return; + } + /* Reject iteration variables larger than the host long size, since they + could result in a number of iterations greater than the range of our + `unsigned long' variable loop_n_iterations. */ + else if (GET_MODE_BITSIZE (GET_MODE (iteration_var)) > HOST_BITS_PER_LONG) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: Iteration var rejected because mode larger than host long.\n"); + return; + } + else if (GET_MODE_CLASS (GET_MODE (iteration_var)) != MODE_INT) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: Iteration var not an integer.\n"); + return; + } + else if (reg_iv_type[REGNO (iteration_var)] == BASIC_INDUCT) + { + /* Grab initial value, only useful if it is a constant. */ + bl = reg_biv_class[REGNO (iteration_var)]; + *initial_value = bl->initial_value; + + *increment = biv_total_increment (bl, loop_start, loop_end); + } + else if (reg_iv_type[REGNO (iteration_var)] == GENERAL_INDUCT) + { +#if 1 + /* ??? The code below does not work because the incorrect number of + iterations is calculated when the biv is incremented after the giv + is set (which is the usual case). This can probably be accounted + for by biasing the initial_value by subtracting the amount of the + increment that occurs between the giv set and the giv test. However, + a giv as an iterator is very rare, so it does not seem worthwhile + to handle this. */ + /* ??? An example failure is: i = 6; do {;} while (i++ < 9). */ + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: Giv iterators are not handled.\n"); + return; +#else + /* Initial value is mult_val times the biv's initial value plus + add_val. Only useful if it is a constant. */ + v = reg_iv_info[REGNO (iteration_var)]; + bl = reg_biv_class[REGNO (v->src_reg)]; + *initial_value = fold_rtx_mult_add (v->mult_val, bl->initial_value, + v->add_val, v->mode); + + /* Increment value is mult_val times the increment value of the biv. */ + + *increment = biv_total_increment (bl, loop_start, loop_end); + if (*increment) + *increment = fold_rtx_mult_add (v->mult_val, *increment, const0_rtx, + v->mode); +#endif + } + else + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: Not basic or general induction var.\n"); + return; + } +} + +/* Calculate the approximate final value of the iteration variable + which has an loop exit test with code COMPARISON_CODE and comparison value + of COMPARISON_VALUE. Also returns an indication of whether the comparison + was signed or unsigned, and the direction of the comparison. This info is + needed to calculate the number of loop iterations. */ + +static rtx +approx_final_value (comparison_code, comparison_value, unsigned_p, compare_dir) + enum rtx_code comparison_code; + rtx comparison_value; + int *unsigned_p; + int *compare_dir; +{ + /* Calculate the final value of the induction variable. + The exact final value depends on the branch operator, and increment sign. + This is only an approximate value. It will be wrong if the iteration + variable is not incremented by one each time through the loop, and + approx final value - start value % increment != 0. */ + + *unsigned_p = 0; + switch (comparison_code) + { + case LEU: + *unsigned_p = 1; + case LE: + *compare_dir = 1; + return plus_constant (comparison_value, 1); + case GEU: + *unsigned_p = 1; + case GE: + *compare_dir = -1; + return plus_constant (comparison_value, -1); + case EQ: + /* Can not calculate a final value for this case. */ + *compare_dir = 0; + return 0; + case LTU: + *unsigned_p = 1; + case LT: + *compare_dir = 1; + return comparison_value; + break; + case GTU: + *unsigned_p = 1; + case GT: + *compare_dir = -1; + return comparison_value; + case NE: + *compare_dir = 0; + return comparison_value; + default: + abort (); + } +} + +/* For each biv and giv, determine whether it can be safely split into + a different variable for each unrolled copy of the loop body. If it + is safe to split, then indicate that by saving some useful info + in the splittable_regs array. + + If the loop is being completely unrolled, then splittable_regs will hold + the current value of the induction variable while the loop is unrolled. + It must be set to the initial value of the induction variable here. + Otherwise, splittable_regs will hold the difference between the current + value of the induction variable and the value the induction variable had + at the top of the loop. It must be set to the value 0 here. */ + +/* ?? If the loop is only unrolled twice, then most of the restrictions to + constant values are unnecessary, since we can easily calculate increment + values in this case even if nothing is constant. The increment value + should not involve a multiply however. */ + +/* ?? Even if the biv/giv increment values aren't constant, it may still + be beneficial to split the variable if the loop is only unrolled a few + times, since multiplies by small integers (1,2,3,4) are very cheap. */ + +static int +find_splittable_regs (unroll_type, loop_start, loop_end, end_insert_before, + unroll_number) + enum unroll_types unroll_type; + rtx loop_start, loop_end; + rtx end_insert_before; + int unroll_number; +{ + struct iv_class *bl; + struct induction *v; + rtx increment, tem; + rtx biv_final_value; + int biv_splittable; + int result = 0; + + for (bl = loop_iv_list; bl; bl = bl->next) + { + /* Biv_total_increment must return a constant value, + otherwise we can not calculate the split values. */ + + increment = biv_total_increment (bl, loop_start, loop_end); + if (! increment || GET_CODE (increment) != CONST_INT) + continue; + + /* The loop must be unrolled completely, or else have a known number + of iterations and only one exit, or else the biv must be dead + outside the loop, or else the final value must be known. Otherwise, + it is unsafe to split the biv since it may not have the proper + value on loop exit. */ + + /* loop_number_exit_labels is non-zero if the loop has an exit other than + a fall through at the end. */ + + biv_splittable = 1; + biv_final_value = 0; + if (unroll_type != UNROLL_COMPLETELY + && (loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]] + || unroll_type == UNROLL_NAIVE) + && (uid_luid[regno_last_uid[bl->regno]] >= INSN_LUID (loop_end) + || ! bl->init_insn + || INSN_UID (bl->init_insn) >= max_uid_for_loop + || (uid_luid[regno_first_uid[bl->regno]] + < INSN_LUID (bl->init_insn)) + || reg_mentioned_p (bl->biv->dest_reg, SET_SRC (bl->init_set))) + && ! (biv_final_value = final_biv_value (bl, loop_start, loop_end))) + biv_splittable = 0; + + /* If any of the insns setting the BIV don't do so with a simple + PLUS, we don't know how to split it. */ + for (v = bl->biv; biv_splittable && v; v = v->next_iv) + if ((tem = single_set (v->insn)) == 0 + || GET_CODE (SET_DEST (tem)) != REG + || REGNO (SET_DEST (tem)) != bl->regno + || GET_CODE (SET_SRC (tem)) != PLUS) + biv_splittable = 0; + + /* If final value is non-zero, then must emit an instruction which sets + the value of the biv to the proper value. This is done after + handling all of the givs, since some of them may need to use the + biv's value in their initialization code. */ + + /* This biv is splittable. If completely unrolling the loop, save + the biv's initial value. Otherwise, save the constant zero. */ + + if (biv_splittable == 1) + { + if (unroll_type == UNROLL_COMPLETELY) + { + /* If the initial value of the biv is itself (i.e. it is too + complicated for strength_reduce to compute), or is a hard + register, then we must create a new pseudo reg to hold the + initial value of the biv. */ + + if (GET_CODE (bl->initial_value) == REG + && (REGNO (bl->initial_value) == bl->regno + || REGNO (bl->initial_value) < FIRST_PSEUDO_REGISTER)) + { + rtx tem = gen_reg_rtx (bl->biv->mode); + + emit_insn_before (gen_move_insn (tem, bl->biv->src_reg), + loop_start); + + if (loop_dump_stream) + fprintf (loop_dump_stream, "Biv %d initial value remapped to %d.\n", + bl->regno, REGNO (tem)); + + splittable_regs[bl->regno] = tem; + } + else + splittable_regs[bl->regno] = bl->initial_value; + } + else + splittable_regs[bl->regno] = const0_rtx; + + /* Save the number of instructions that modify the biv, so that + we can treat the last one specially. */ + + splittable_regs_updates[bl->regno] = bl->biv_count; + + result++; + + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Biv %d safe to split.\n", bl->regno); + } + + /* Check every giv that depends on this biv to see whether it is + splittable also. Even if the biv isn't splittable, givs which + depend on it may be splittable if the biv is live outside the + loop, and the givs aren't. */ + + result = find_splittable_givs (bl, unroll_type, loop_start, loop_end, + increment, unroll_number, result); + + /* If final value is non-zero, then must emit an instruction which sets + the value of the biv to the proper value. This is done after + handling all of the givs, since some of them may need to use the + biv's value in their initialization code. */ + if (biv_final_value) + { + /* If the loop has multiple exits, emit the insns before the + loop to ensure that it will always be executed no matter + how the loop exits. Otherwise emit the insn after the loop, + since this is slightly more efficient. */ + if (! loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]]) + emit_insn_before (gen_move_insn (bl->biv->src_reg, + biv_final_value), + end_insert_before); + else + { + /* Create a new register to hold the value of the biv, and then + set the biv to its final value before the loop start. The biv + is set to its final value before loop start to ensure that + this insn will always be executed, no matter how the loop + exits. */ + rtx tem = gen_reg_rtx (bl->biv->mode); + emit_insn_before (gen_move_insn (tem, bl->biv->src_reg), + loop_start); + emit_insn_before (gen_move_insn (bl->biv->src_reg, + biv_final_value), + loop_start); + + if (loop_dump_stream) + fprintf (loop_dump_stream, "Biv %d mapped to %d for split.\n", + REGNO (bl->biv->src_reg), REGNO (tem)); + + /* Set up the mapping from the original biv register to the new + register. */ + bl->biv->src_reg = tem; + } + } + } + return result; +} + +/* For every giv based on the biv BL, check to determine whether it is + splittable. This is a subroutine to find_splittable_regs (). */ + +static int +find_splittable_givs (bl, unroll_type, loop_start, loop_end, increment, + unroll_number, result) + struct iv_class *bl; + enum unroll_types unroll_type; + rtx loop_start, loop_end; + rtx increment; + int unroll_number, result; +{ + struct induction *v; + rtx final_value; + rtx tem; + + for (v = bl->giv; v; v = v->next_iv) + { + rtx giv_inc, value; + + /* Only split the giv if it has already been reduced, or if the loop is + being completely unrolled. */ + if (unroll_type != UNROLL_COMPLETELY && v->ignore) + continue; + + /* The giv can be split if the insn that sets the giv is executed once + and only once on every iteration of the loop. */ + /* An address giv can always be split. v->insn is just a use not a set, + and hence it does not matter whether it is always executed. All that + matters is that all the biv increments are always executed, and we + won't reach here if they aren't. */ + if (v->giv_type != DEST_ADDR + && (! v->always_computable + || back_branch_in_range_p (v->insn, loop_start, loop_end))) + continue; + + /* The giv increment value must be a constant. */ + giv_inc = fold_rtx_mult_add (v->mult_val, increment, const0_rtx, + v->mode); + if (! giv_inc || GET_CODE (giv_inc) != CONST_INT) + continue; + + /* The loop must be unrolled completely, or else have a known number of + iterations and only one exit, or else the giv must be dead outside + the loop, or else the final value of the giv must be known. + Otherwise, it is not safe to split the giv since it may not have the + proper value on loop exit. */ + + /* The used outside loop test will fail for DEST_ADDR givs. They are + never used outside the loop anyways, so it is always safe to split a + DEST_ADDR giv. */ + + final_value = 0; + if (unroll_type != UNROLL_COMPLETELY + && (loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]] + || unroll_type == UNROLL_NAIVE) + && v->giv_type != DEST_ADDR + && ((regno_first_uid[REGNO (v->dest_reg)] != INSN_UID (v->insn) + /* Check for the case where the pseudo is set by a shift/add + sequence, in which case the first insn setting the pseudo + is the first insn of the shift/add sequence. */ + && (! (tem = find_reg_note (v->insn, REG_RETVAL, NULL_RTX)) + || (regno_first_uid[REGNO (v->dest_reg)] + != INSN_UID (XEXP (tem, 0))))) + /* Line above always fails if INSN was moved by loop opt. */ + || (uid_luid[regno_last_uid[REGNO (v->dest_reg)]] + >= INSN_LUID (loop_end))) + && ! (final_value = v->final_value)) + continue; + +#if 0 + /* Currently, non-reduced/final-value givs are never split. */ + /* Should emit insns after the loop if possible, as the biv final value + code below does. */ + + /* If the final value is non-zero, and the giv has not been reduced, + then must emit an instruction to set the final value. */ + if (final_value && !v->new_reg) + { + /* Create a new register to hold the value of the giv, and then set + the giv to its final value before the loop start. The giv is set + to its final value before loop start to ensure that this insn + will always be executed, no matter how we exit. */ + tem = gen_reg_rtx (v->mode); + emit_insn_before (gen_move_insn (tem, v->dest_reg), loop_start); + emit_insn_before (gen_move_insn (v->dest_reg, final_value), + loop_start); + + if (loop_dump_stream) + fprintf (loop_dump_stream, "Giv %d mapped to %d for split.\n", + REGNO (v->dest_reg), REGNO (tem)); + + v->src_reg = tem; + } +#endif + + /* This giv is splittable. If completely unrolling the loop, save the + giv's initial value. Otherwise, save the constant zero for it. */ + + if (unroll_type == UNROLL_COMPLETELY) + { + /* It is not safe to use bl->initial_value here, because it may not + be invariant. It is safe to use the initial value stored in + the splittable_regs array if it is set. In rare cases, it won't + be set, so then we do exactly the same thing as + find_splittable_regs does to get a safe value. */ + rtx biv_initial_value; + + if (splittable_regs[bl->regno]) + biv_initial_value = splittable_regs[bl->regno]; + else if (GET_CODE (bl->initial_value) != REG + || (REGNO (bl->initial_value) != bl->regno + && REGNO (bl->initial_value) >= FIRST_PSEUDO_REGISTER)) + biv_initial_value = bl->initial_value; + else + { + rtx tem = gen_reg_rtx (bl->biv->mode); + + emit_insn_before (gen_move_insn (tem, bl->biv->src_reg), + loop_start); + biv_initial_value = tem; + } + value = fold_rtx_mult_add (v->mult_val, biv_initial_value, + v->add_val, v->mode); + } + else + value = const0_rtx; + + if (v->new_reg) + { + /* If a giv was combined with another giv, then we can only split + this giv if the giv it was combined with was reduced. This + is because the value of v->new_reg is meaningless in this + case. */ + if (v->same && ! v->same->new_reg) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "giv combined with unreduced giv not split.\n"); + continue; + } + /* If the giv is an address destination, it could be something other + than a simple register, these have to be treated differently. */ + else if (v->giv_type == DEST_REG) + { + /* If value is not a constant, register, or register plus + constant, then compute its value into a register before + loop start. This prevents illegal rtx sharing, and should + generate better code. We can use bl->initial_value here + instead of splittable_regs[bl->regno] because this code + is going before the loop start. */ + if (unroll_type == UNROLL_COMPLETELY + && GET_CODE (value) != CONST_INT + && GET_CODE (value) != REG + && (GET_CODE (value) != PLUS + || GET_CODE (XEXP (value, 0)) != REG + || GET_CODE (XEXP (value, 1)) != CONST_INT)) + { + rtx tem = gen_reg_rtx (v->mode); + emit_iv_add_mult (bl->initial_value, v->mult_val, + v->add_val, tem, loop_start); + value = tem; + } + + splittable_regs[REGNO (v->new_reg)] = value; + } + else + { + /* Splitting address givs is useful since it will often allow us + to eliminate some increment insns for the base giv as + unnecessary. */ + + /* If the addr giv is combined with a dest_reg giv, then all + references to that dest reg will be remapped, which is NOT + what we want for split addr regs. We always create a new + register for the split addr giv, just to be safe. */ + + /* ??? If there are multiple address givs which have been + combined with the same dest_reg giv, then we may only need + one new register for them. Pulling out constants below will + catch some of the common cases of this. Currently, I leave + the work of simplifying multiple address givs to the + following cse pass. */ + + v->const_adjust = 0; + if (unroll_type != UNROLL_COMPLETELY) + { + /* If not completely unrolling the loop, then create a new + register to hold the split value of the DEST_ADDR giv. + Emit insn to initialize its value before loop start. */ + tem = gen_reg_rtx (v->mode); + + /* If the address giv has a constant in its new_reg value, + then this constant can be pulled out and put in value, + instead of being part of the initialization code. */ + + if (GET_CODE (v->new_reg) == PLUS + && GET_CODE (XEXP (v->new_reg, 1)) == CONST_INT) + { + v->dest_reg + = plus_constant (tem, INTVAL (XEXP (v->new_reg,1))); + + /* Only succeed if this will give valid addresses. + Try to validate both the first and the last + address resulting from loop unrolling, if + one fails, then can't do const elim here. */ + if (memory_address_p (v->mem_mode, v->dest_reg) + && memory_address_p (v->mem_mode, + plus_constant (v->dest_reg, + INTVAL (giv_inc) + * (unroll_number - 1)))) + { + /* Save the negative of the eliminated const, so + that we can calculate the dest_reg's increment + value later. */ + v->const_adjust = - INTVAL (XEXP (v->new_reg, 1)); + + v->new_reg = XEXP (v->new_reg, 0); + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Eliminating constant from giv %d\n", + REGNO (tem)); + } + else + v->dest_reg = tem; + } + else + v->dest_reg = tem; + + /* If the address hasn't been checked for validity yet, do so + now, and fail completely if either the first or the last + unrolled copy of the address is not a valid address. */ + if (v->dest_reg == tem + && (! memory_address_p (v->mem_mode, v->dest_reg) + || ! memory_address_p (v->mem_mode, + plus_constant (v->dest_reg, + INTVAL (giv_inc) + * (unroll_number -1))))) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Illegal address for giv at insn %d\n", + INSN_UID (v->insn)); + continue; + } + + /* To initialize the new register, just move the value of + new_reg into it. This is not guaranteed to give a valid + instruction on machines with complex addressing modes. + If we can't recognize it, then delete it and emit insns + to calculate the value from scratch. */ + emit_insn_before (gen_rtx (SET, VOIDmode, tem, + copy_rtx (v->new_reg)), + loop_start); + if (recog_memoized (PREV_INSN (loop_start)) < 0) + { + delete_insn (PREV_INSN (loop_start)); + emit_iv_add_mult (bl->initial_value, v->mult_val, + v->add_val, tem, loop_start); + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Illegal init insn, rewritten.\n"); + } + } + else + { + v->dest_reg = value; + + /* Check the resulting address for validity, and fail + if the resulting address would be illegal. */ + if (! memory_address_p (v->mem_mode, v->dest_reg) + || ! memory_address_p (v->mem_mode, + plus_constant (v->dest_reg, + INTVAL (giv_inc) * + (unroll_number -1)))) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Illegal address for giv at insn %d\n", + INSN_UID (v->insn)); + continue; + } + } + + /* Store the value of dest_reg into the insn. This sharing + will not be a problem as this insn will always be copied + later. */ + + *v->location = v->dest_reg; + + /* If this address giv is combined with a dest reg giv, then + save the base giv's induction pointer so that we will be + able to handle this address giv properly. The base giv + itself does not have to be splittable. */ + + if (v->same && v->same->giv_type == DEST_REG) + addr_combined_regs[REGNO (v->same->new_reg)] = v->same; + + if (GET_CODE (v->new_reg) == REG) + { + /* This giv maybe hasn't been combined with any others. + Make sure that it's giv is marked as splittable here. */ + + splittable_regs[REGNO (v->new_reg)] = value; + + /* Make it appear to depend upon itself, so that the + giv will be properly split in the main loop above. */ + if (! v->same) + { + v->same = v; + addr_combined_regs[REGNO (v->new_reg)] = v; + } + } + + if (loop_dump_stream) + fprintf (loop_dump_stream, "DEST_ADDR giv being split.\n"); + } + } + else + { +#if 0 + /* Currently, unreduced giv's can't be split. This is not too much + of a problem since unreduced giv's are not live across loop + iterations anyways. When unrolling a loop completely though, + it makes sense to reduce&split givs when possible, as this will + result in simpler instructions, and will not require that a reg + be live across loop iterations. */ + + splittable_regs[REGNO (v->dest_reg)] = value; + fprintf (stderr, "Giv %d at insn %d not reduced\n", + REGNO (v->dest_reg), INSN_UID (v->insn)); +#else + continue; +#endif + } + + /* Givs are only updated once by definition. Mark it so if this is + a splittable register. Don't need to do anything for address givs + where this may not be a register. */ + + if (GET_CODE (v->new_reg) == REG) + splittable_regs_updates[REGNO (v->new_reg)] = 1; + + result++; + + if (loop_dump_stream) + { + int regnum; + + if (GET_CODE (v->dest_reg) == CONST_INT) + regnum = -1; + else if (GET_CODE (v->dest_reg) != REG) + regnum = REGNO (XEXP (v->dest_reg, 0)); + else + regnum = REGNO (v->dest_reg); + fprintf (loop_dump_stream, "Giv %d at insn %d safe to split.\n", + regnum, INSN_UID (v->insn)); + } + } + + return result; +} + +/* Try to prove that the register is dead after the loop exits. Trace every + loop exit looking for an insn that will always be executed, which sets + the register to some value, and appears before the first use of the register + is found. If successful, then return 1, otherwise return 0. */ + +/* ?? Could be made more intelligent in the handling of jumps, so that + it can search past if statements and other similar structures. */ + +static int +reg_dead_after_loop (reg, loop_start, loop_end) + rtx reg, loop_start, loop_end; +{ + rtx insn, label; + enum rtx_code code; + int jump_count = 0; + + /* HACK: Must also search the loop fall through exit, create a label_ref + here which points to the loop_end, and append the loop_number_exit_labels + list to it. */ + label = gen_rtx (LABEL_REF, VOIDmode, loop_end); + LABEL_NEXTREF (label) + = loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]]; + + for ( ; label; label = LABEL_NEXTREF (label)) + { + /* Succeed if find an insn which sets the biv or if reach end of + function. Fail if find an insn that uses the biv, or if come to + a conditional jump. */ + + insn = NEXT_INSN (XEXP (label, 0)); + while (insn) + { + code = GET_CODE (insn); + if (GET_RTX_CLASS (code) == 'i') + { + rtx set; + + if (reg_referenced_p (reg, PATTERN (insn))) + return 0; + + set = single_set (insn); + if (set && rtx_equal_p (SET_DEST (set), reg)) + break; + } + + if (code == JUMP_INSN) + { + if (GET_CODE (PATTERN (insn)) == RETURN) + break; + else if (! simplejump_p (insn) + /* Prevent infinite loop following infinite loops. */ + || jump_count++ > 20) + return 0; + else + insn = JUMP_LABEL (insn); + } + + insn = NEXT_INSN (insn); + } + } + + /* Success, the register is dead on all loop exits. */ + return 1; +} + +/* Try to calculate the final value of the biv, the value it will have at + the end of the loop. If we can do it, return that value. */ + +rtx +final_biv_value (bl, loop_start, loop_end) + struct iv_class *bl; + rtx loop_start, loop_end; +{ + rtx increment, tem; + + /* ??? This only works for MODE_INT biv's. Reject all others for now. */ + + if (GET_MODE_CLASS (bl->biv->mode) != MODE_INT) + return 0; + + /* The final value for reversed bivs must be calculated differently than + for ordinary bivs. In this case, there is already an insn after the + loop which sets this biv's final value (if necessary), and there are + no other loop exits, so we can return any value. */ + if (bl->reversed) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Final biv value for %d, reversed biv.\n", bl->regno); + + return const0_rtx; + } + + /* Try to calculate the final value as initial value + (number of iterations + * increment). For this to work, increment must be invariant, the only + exit from the loop must be the fall through at the bottom (otherwise + it may not have its final value when the loop exits), and the initial + value of the biv must be invariant. */ + + if (loop_n_iterations != 0 + && ! loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]] + && invariant_p (bl->initial_value)) + { + increment = biv_total_increment (bl, loop_start, loop_end); + + if (increment && invariant_p (increment)) + { + /* Can calculate the loop exit value, emit insns after loop + end to calculate this value into a temporary register in + case it is needed later. */ + + tem = gen_reg_rtx (bl->biv->mode); + /* Make sure loop_end is not the last insn. */ + if (NEXT_INSN (loop_end) == 0) + emit_note_after (NOTE_INSN_DELETED, loop_end); + emit_iv_add_mult (increment, GEN_INT (loop_n_iterations), + bl->initial_value, tem, NEXT_INSN (loop_end)); + + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Final biv value for %d, calculated.\n", bl->regno); + + return tem; + } + } + + /* Check to see if the biv is dead at all loop exits. */ + if (reg_dead_after_loop (bl->biv->src_reg, loop_start, loop_end)) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Final biv value for %d, biv dead after loop exit.\n", + bl->regno); + + return const0_rtx; + } + + return 0; +} + +/* Try to calculate the final value of the giv, the value it will have at + the end of the loop. If we can do it, return that value. */ + +rtx +final_giv_value (v, loop_start, loop_end) + struct induction *v; + rtx loop_start, loop_end; +{ + struct iv_class *bl; + rtx insn; + rtx increment, tem; + enum rtx_code code; + rtx insert_before, seq; + + bl = reg_biv_class[REGNO (v->src_reg)]; + + /* The final value for givs which depend on reversed bivs must be calculated + differently than for ordinary givs. In this case, there is already an + insn after the loop which sets this giv's final value (if necessary), + and there are no other loop exits, so we can return any value. */ + if (bl->reversed) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Final giv value for %d, depends on reversed biv\n", + REGNO (v->dest_reg)); + return const0_rtx; + } + + /* Try to calculate the final value as a function of the biv it depends + upon. The only exit from the loop must be the fall through at the bottom + (otherwise it may not have its final value when the loop exits). */ + + /* ??? Can calculate the final giv value by subtracting off the + extra biv increments times the giv's mult_val. The loop must have + only one exit for this to work, but the loop iterations does not need + to be known. */ + + if (loop_n_iterations != 0 + && ! loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]]) + { + /* ?? It is tempting to use the biv's value here since these insns will + be put after the loop, and hence the biv will have its final value + then. However, this fails if the biv is subsequently eliminated. + Perhaps determine whether biv's are eliminable before trying to + determine whether giv's are replaceable so that we can use the + biv value here if it is not eliminable. */ + + increment = biv_total_increment (bl, loop_start, loop_end); + + if (increment && invariant_p (increment)) + { + /* Can calculate the loop exit value of its biv as + (loop_n_iterations * increment) + initial_value */ + + /* The loop exit value of the giv is then + (final_biv_value - extra increments) * mult_val + add_val. + The extra increments are any increments to the biv which + occur in the loop after the giv's value is calculated. + We must search from the insn that sets the giv to the end + of the loop to calculate this value. */ + + insert_before = NEXT_INSN (loop_end); + + /* Put the final biv value in tem. */ + tem = gen_reg_rtx (bl->biv->mode); + emit_iv_add_mult (increment, GEN_INT (loop_n_iterations), + bl->initial_value, tem, insert_before); + + /* Subtract off extra increments as we find them. */ + for (insn = NEXT_INSN (v->insn); insn != loop_end; + insn = NEXT_INSN (insn)) + { + struct induction *biv; + + for (biv = bl->biv; biv; biv = biv->next_iv) + if (biv->insn == insn) + { + start_sequence (); + tem = expand_binop (GET_MODE (tem), sub_optab, tem, + biv->add_val, NULL_RTX, 0, + OPTAB_LIB_WIDEN); + seq = gen_sequence (); + end_sequence (); + emit_insn_before (seq, insert_before); + } + } + + /* Now calculate the giv's final value. */ + emit_iv_add_mult (tem, v->mult_val, v->add_val, tem, + insert_before); + + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Final giv value for %d, calc from biv's value.\n", + REGNO (v->dest_reg)); + + return tem; + } + } + + /* Replaceable giv's should never reach here. */ + if (v->replaceable) + abort (); + + /* Check to see if the biv is dead at all loop exits. */ + if (reg_dead_after_loop (v->dest_reg, loop_start, loop_end)) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Final giv value for %d, giv dead after loop exit.\n", + REGNO (v->dest_reg)); + + return const0_rtx; + } + + return 0; +} + + +/* Calculate the number of loop iterations. Returns the exact number of loop + iterations if it can be calculated, otherwise returns zero. */ + +unsigned HOST_WIDE_INT +loop_iterations (loop_start, loop_end) + rtx loop_start, loop_end; +{ + rtx comparison, comparison_value; + rtx iteration_var, initial_value, increment, final_value; + enum rtx_code comparison_code; + HOST_WIDE_INT i; + int increment_dir; + int unsigned_compare, compare_dir, final_larger; + unsigned long tempu; + rtx last_loop_insn; + + /* First find the iteration variable. If the last insn is a conditional + branch, and the insn before tests a register value, make that the + iteration variable. */ + + loop_initial_value = 0; + loop_increment = 0; + loop_final_value = 0; + loop_iteration_var = 0; + + last_loop_insn = prev_nonnote_insn (loop_end); + + comparison = get_condition_for_loop (last_loop_insn); + if (comparison == 0) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: No final conditional branch found.\n"); + return 0; + } + + /* ??? Get_condition may switch position of induction variable and + invariant register when it canonicalizes the comparison. */ + + comparison_code = GET_CODE (comparison); + iteration_var = XEXP (comparison, 0); + comparison_value = XEXP (comparison, 1); + + if (GET_CODE (iteration_var) != REG) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: Comparison not against register.\n"); + return 0; + } + + /* Loop iterations is always called before any new registers are created + now, so this should never occur. */ + + if (REGNO (iteration_var) >= max_reg_before_loop) + abort (); + + iteration_info (iteration_var, &initial_value, &increment, + loop_start, loop_end); + if (initial_value == 0) + /* iteration_info already printed a message. */ + return 0; + + if (increment == 0) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: Increment value can't be calculated.\n"); + return 0; + } + if (GET_CODE (increment) != CONST_INT) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: Increment value not constant.\n"); + return 0; + } + if (GET_CODE (initial_value) != CONST_INT) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: Initial value not constant.\n"); + return 0; + } + + /* If the comparison value is an invariant register, then try to find + its value from the insns before the start of the loop. */ + + if (GET_CODE (comparison_value) == REG && invariant_p (comparison_value)) + { + rtx insn, set; + + for (insn = PREV_INSN (loop_start); insn ; insn = PREV_INSN (insn)) + { + if (GET_CODE (insn) == CODE_LABEL) + break; + + else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' + && reg_set_p (comparison_value, insn)) + { + /* We found the last insn before the loop that sets the register. + If it sets the entire register, and has a REG_EQUAL note, + then use the value of the REG_EQUAL note. */ + if ((set = single_set (insn)) + && (SET_DEST (set) == comparison_value)) + { + rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); + + if (note && GET_CODE (XEXP (note, 0)) != EXPR_LIST) + comparison_value = XEXP (note, 0); + } + break; + } + } + } + + final_value = approx_final_value (comparison_code, comparison_value, + &unsigned_compare, &compare_dir); + + /* Save the calculated values describing this loop's bounds, in case + precondition_loop_p will need them later. These values can not be + recalculated inside precondition_loop_p because strength reduction + optimizations may obscure the loop's structure. */ + + loop_iteration_var = iteration_var; + loop_initial_value = initial_value; + loop_increment = increment; + loop_final_value = final_value; + + if (final_value == 0) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: EQ comparison loop.\n"); + return 0; + } + else if (GET_CODE (final_value) != CONST_INT) + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: Final value not constant.\n"); + return 0; + } + + /* ?? Final value and initial value do not have to be constants. + Only their difference has to be constant. When the iteration variable + is an array address, the final value and initial value might both + be addresses with the same base but different constant offsets. + Final value must be invariant for this to work. + + To do this, need some way to find the values of registers which are + invariant. */ + + /* Final_larger is 1 if final larger, 0 if they are equal, otherwise -1. */ + if (unsigned_compare) + final_larger + = ((unsigned HOST_WIDE_INT) INTVAL (final_value) + > (unsigned HOST_WIDE_INT) INTVAL (initial_value)) + - ((unsigned HOST_WIDE_INT) INTVAL (final_value) + < (unsigned HOST_WIDE_INT) INTVAL (initial_value)); + else + final_larger = (INTVAL (final_value) > INTVAL (initial_value)) + - (INTVAL (final_value) < INTVAL (initial_value)); + + if (INTVAL (increment) > 0) + increment_dir = 1; + else if (INTVAL (increment) == 0) + increment_dir = 0; + else + increment_dir = -1; + + /* There are 27 different cases: compare_dir = -1, 0, 1; + final_larger = -1, 0, 1; increment_dir = -1, 0, 1. + There are 4 normal cases, 4 reverse cases (where the iteration variable + will overflow before the loop exits), 4 infinite loop cases, and 15 + immediate exit (0 or 1 iteration depending on loop type) cases. + Only try to optimize the normal cases. */ + + /* (compare_dir/final_larger/increment_dir) + Normal cases: (0/-1/-1), (0/1/1), (-1/-1/-1), (1/1/1) + Reverse cases: (0/-1/1), (0/1/-1), (-1/-1/1), (1/1/-1) + Infinite loops: (0/-1/0), (0/1/0), (-1/-1/0), (1/1/0) + Immediate exit: (0/0/X), (-1/0/X), (-1/1/X), (1/0/X), (1/-1/X) */ + + /* ?? If the meaning of reverse loops (where the iteration variable + will overflow before the loop exits) is undefined, then could + eliminate all of these special checks, and just always assume + the loops are normal/immediate/infinite. Note that this means + the sign of increment_dir does not have to be known. Also, + since it does not really hurt if immediate exit loops or infinite loops + are optimized, then that case could be ignored also, and hence all + loops can be optimized. + + According to ANSI Spec, the reverse loop case result is undefined, + because the action on overflow is undefined. + + See also the special test for NE loops below. */ + + if (final_larger == increment_dir && final_larger != 0 + && (final_larger == compare_dir || compare_dir == 0)) + /* Normal case. */ + ; + else + { + if (loop_dump_stream) + fprintf (loop_dump_stream, + "Loop unrolling: Not normal loop.\n"); + return 0; + } + + /* Calculate the number of iterations, final_value is only an approximation, + so correct for that. Note that tempu and loop_n_iterations are + unsigned, because they can be as large as 2^n - 1. */ + + i = INTVAL (increment); + if (i > 0) + tempu = INTVAL (final_value) - INTVAL (initial_value); + else if (i < 0) + { + tempu = INTVAL (initial_value) - INTVAL (final_value); + i = -i; + } + else + abort (); + + /* For NE tests, make sure that the iteration variable won't miss the + final value. If tempu mod i is not zero, then the iteration variable + will overflow before the loop exits, and we can not calculate the + number of iterations. */ + if (compare_dir == 0 && (tempu % i) != 0) + return 0; + + return tempu / i + ((tempu % i) != 0); +} diff --git a/gnu/usr.bin/cc/lib/varasm.c b/gnu/usr.bin/cc/lib/varasm.c new file mode 100644 index 000000000000..67954442233e --- /dev/null +++ b/gnu/usr.bin/cc/lib/varasm.c @@ -0,0 +1,3033 @@ +/* Output variables, constants and external declarations, for GNU compiler. + Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This file handles generation of all the assembler code + *except* the instructions of a function. + This includes declarations of variables and their initial values. + + We also output the assembler code for constants stored in memory + and are responsible for combining constants with the same value. */ + +#include +#include +/* #include */ +#include "config.h" +#include "rtl.h" +#include "tree.h" +#include "flags.h" +#include "function.h" +#include "expr.h" +#include "hard-reg-set.h" +#include "regs.h" +#include "defaults.h" +#include "real.h" + +#include "obstack.h" + +#ifdef XCOFF_DEBUGGING_INFO +#include "xcoffout.h" +#endif + +#ifndef ASM_STABS_OP +#define ASM_STABS_OP ".stabs" +#endif + +/* This macro gets just the user-specified name + out of the string in a SYMBOL_REF. On most machines, + we discard the * if any and that's all. */ +#ifndef STRIP_NAME_ENCODING +#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \ + (VAR) = ((SYMBOL_NAME) + ((SYMBOL_NAME)[0] == '*')) +#endif + +/* File in which assembler code is being written. */ + +extern FILE *asm_out_file; + +/* The (assembler) name of the first globally-visible object output. */ +char *first_global_object_name; + +extern struct obstack *current_obstack; +extern struct obstack *saveable_obstack; +extern struct obstack permanent_obstack; +#define obstack_chunk_alloc xmalloc + +/* Number for making the label on the next + constant that is stored in memory. */ + +int const_labelno; + +/* Number for making the label on the next + static variable internal to a function. */ + +int var_labelno; + +/* Nonzero if at least one function definition has been seen. */ +static int function_defined; + +extern FILE *asm_out_file; + +static char *compare_constant_1 (); +static void record_constant_1 (); +void output_constant_pool (); +void assemble_name (); +int output_addressed_constants (); +void output_constant (); +void output_constructor (); +void text_section (); +void readonly_data_section (); +void data_section (); + +#ifdef EXTRA_SECTIONS +static enum in_section {no_section, in_text, in_data, EXTRA_SECTIONS} in_section + = no_section; +#else +static enum in_section {no_section, in_text, in_data} in_section + = no_section; +#endif + +/* Define functions like text_section for any extra sections. */ +#ifdef EXTRA_SECTION_FUNCTIONS +EXTRA_SECTION_FUNCTIONS +#endif + +/* Tell assembler to switch to text section. */ + +void +text_section () +{ + if (in_section != in_text) + { + fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP); + in_section = in_text; + } +} + +/* Tell assembler to switch to data section. */ + +void +data_section () +{ + if (in_section != in_data) + { + if (flag_shared_data) + { +#ifdef SHARED_SECTION_ASM_OP + fprintf (asm_out_file, "%s\n", SHARED_SECTION_ASM_OP); +#else + fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP); +#endif + } + else + fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP); + + in_section = in_data; + } +} + +/* Tell assembler to switch to read-only data section. This is normally + the text section. */ + +void +readonly_data_section () +{ +#ifdef READONLY_DATA_SECTION + READONLY_DATA_SECTION (); /* Note this can call data_section. */ +#else + text_section (); +#endif +} + +/* Determine if we're in the text section. */ + +int +in_text_section () +{ + return in_section == in_text; +} + +/* Create the rtl to represent a function, for a function definition. + DECL is a FUNCTION_DECL node which describes which function. + The rtl is stored into DECL. */ + +void +make_function_rtl (decl) + tree decl; +{ + char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); + + /* Rename a nested function to avoid conflicts. */ + if (decl_function_context (decl) != 0 + && DECL_INITIAL (decl) != 0 + && DECL_RTL (decl) == 0) + { + char *label; + + name = IDENTIFIER_POINTER (DECL_NAME (decl)); + ASM_FORMAT_PRIVATE_NAME (label, name, var_labelno); + name = obstack_copy0 (saveable_obstack, label, strlen (label)); + var_labelno++; + } + + if (DECL_RTL (decl) == 0) + { + DECL_RTL (decl) + = gen_rtx (MEM, DECL_MODE (decl), + gen_rtx (SYMBOL_REF, Pmode, name)); + + /* Optionally set flags or add text to the name to record information + such as that it is a function name. If the name is changed, the macro + ASM_OUTPUT_LABELREF will have to know how to strip this information. + And if it finds a * at the beginning after doing so, it must handle + that too. */ +#ifdef ENCODE_SECTION_INFO + ENCODE_SECTION_INFO (decl); +#endif + } + + /* Record at least one function has been defined. */ + function_defined = 1; +} + +/* Given NAME, a putative register name, discard any customary prefixes. */ + +static char * +strip_reg_name (name) + char *name; +{ +#ifdef REGISTER_PREFIX + if (!strncmp (name, REGISTER_PREFIX, strlen (REGISTER_PREFIX))) + name += strlen (REGISTER_PREFIX); +#endif + if (name[0] == '%' || name[0] == '#') + name++; + return name; +} + +/* Decode an `asm' spec for a declaration as a register name. + Return the register number, or -1 if nothing specified, + or -2 if the ASMSPEC is not `cc' or `memory' and is not recognized, + or -3 if ASMSPEC is `cc' and is not recognized, + or -4 if ASMSPEC is `memory' and is not recognized. + Accept an exact spelling or a decimal number. + Prefixes such as % are optional. */ + +int +decode_reg_name (asmspec) + char *asmspec; +{ + if (asmspec != 0) + { + int i; + + /* Get rid of confusing prefixes. */ + asmspec = strip_reg_name (asmspec); + + /* Allow a decimal number as a "register name". */ + for (i = strlen (asmspec) - 1; i >= 0; i--) + if (! (asmspec[i] >= '0' && asmspec[i] <= '9')) + break; + if (asmspec[0] != 0 && i < 0) + { + i = atoi (asmspec); + if (i < FIRST_PSEUDO_REGISTER && i >= 0) + return i; + else + return -2; + } + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (reg_names[i][0] + && ! strcmp (asmspec, strip_reg_name (reg_names[i]))) + return i; + +#ifdef ADDITIONAL_REGISTER_NAMES + { + static struct { char *name; int number; } table[] + = ADDITIONAL_REGISTER_NAMES; + + for (i = 0; i < sizeof (table) / sizeof (table[0]); i++) + if (! strcmp (asmspec, table[i].name)) + return table[i].number; + } +#endif /* ADDITIONAL_REGISTER_NAMES */ + + if (!strcmp (asmspec, "memory")) + return -4; + + if (!strcmp (asmspec, "cc")) + return -3; + + return -2; + } + + return -1; +} + +/* Create the DECL_RTL for a declaration for a static or external variable + or static or external function. + ASMSPEC, if not 0, is the string which the user specified + as the assembler symbol name. + TOP_LEVEL is nonzero if this is a file-scope variable. + + This is never called for PARM_DECL nodes. */ + +void +make_decl_rtl (decl, asmspec, top_level) + tree decl; + char *asmspec; + int top_level; +{ + register char *name; + int reg_number = decode_reg_name (asmspec); + + if (DECL_ASSEMBLER_NAME (decl) != NULL_TREE) + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); + + if (reg_number == -2) + { + /* ASMSPEC is given, and not the name of a register. */ + name = (char *) obstack_alloc (saveable_obstack, + strlen (asmspec) + 2); + name[0] = '*'; + strcpy (&name[1], asmspec); + } + + /* For a duplicate declaration, we can be called twice on the + same DECL node. Don't alter the RTL already made + unless the old mode is wrong (which can happen when + the previous rtl was made when the type was incomplete). */ + if (DECL_RTL (decl) == 0 + || GET_MODE (DECL_RTL (decl)) != DECL_MODE (decl)) + { + DECL_RTL (decl) = 0; + + /* First detect errors in declaring global registers. */ + if (DECL_REGISTER (decl) && reg_number == -1) + error_with_decl (decl, + "register name not specified for `%s'"); + else if (DECL_REGISTER (decl) && reg_number < 0) + error_with_decl (decl, + "invalid register name for `%s'"); + else if ((reg_number >= 0 || reg_number == -3) && ! DECL_REGISTER (decl)) + error_with_decl (decl, + "register name given for non-register variable `%s'"); + else if (DECL_REGISTER (decl) && TREE_CODE (decl) == FUNCTION_DECL) + error ("function declared `register'"); + else if (DECL_REGISTER (decl) && TYPE_MODE (TREE_TYPE (decl)) == BLKmode) + error_with_decl (decl, "data type of `%s' isn't suitable for a register"); + else if (DECL_REGISTER (decl) + && ! HARD_REGNO_MODE_OK (reg_number, TYPE_MODE (TREE_TYPE (decl)))) + error_with_decl (decl, "register number for `%s' isn't suitable for the data type"); + /* Now handle properly declared static register variables. */ + else if (DECL_REGISTER (decl)) + { + int nregs; +#if 0 /* yylex should print the warning for this */ + if (pedantic) + pedwarn ("ANSI C forbids global register variables"); +#endif + if (DECL_INITIAL (decl) != 0 && top_level) + { + DECL_INITIAL (decl) = 0; + error ("global register variable has initial value"); + } + if (fixed_regs[reg_number] == 0 + && function_defined && top_level) + error ("global register variable follows a function definition"); + if (TREE_THIS_VOLATILE (decl)) + warning ("volatile register variables don't work as you might wish"); + + /* If the user specified one of the eliminables registers here, + e.g., FRAME_POINTER_REGNUM, we don't want to get this variable + confused with that register and be eliminated. Although this + usage is somewhat suspect, we nevertheless use the following + kludge to avoid setting DECL_RTL to frame_pointer_rtx. */ + + DECL_RTL (decl) + = gen_rtx (REG, DECL_MODE (decl), FIRST_PSEUDO_REGISTER); + REGNO (DECL_RTL (decl)) = reg_number; + REG_USERVAR_P (DECL_RTL (decl)) = 1; + + if (top_level) + { + /* Make this register fixed, so not usable for anything else. */ + nregs = HARD_REGNO_NREGS (reg_number, DECL_MODE (decl)); + while (nregs > 0) + global_regs[reg_number + --nregs] = 1; + init_reg_sets_1 (); + } + } + + /* Now handle ordinary static variables and functions (in memory). + Also handle vars declared register invalidly. */ + if (DECL_RTL (decl) == 0) + { + /* Can't use just the variable's own name for a variable + whose scope is less than the whole file. + Concatenate a distinguishing number. */ + if (!top_level && !DECL_EXTERNAL (decl) && asmspec == 0) + { + char *label; + + ASM_FORMAT_PRIVATE_NAME (label, name, var_labelno); + name = obstack_copy0 (saveable_obstack, label, strlen (label)); + var_labelno++; + } + + DECL_RTL (decl) = gen_rtx (MEM, DECL_MODE (decl), + gen_rtx (SYMBOL_REF, Pmode, name)); + if (TREE_THIS_VOLATILE (decl) + || (flag_volatile_global && TREE_CODE (decl) == VAR_DECL + && TREE_PUBLIC (decl))) + MEM_VOLATILE_P (DECL_RTL (decl)) = 1; + if (TREE_READONLY (decl)) + RTX_UNCHANGING_P (DECL_RTL (decl)) = 1; + MEM_IN_STRUCT_P (DECL_RTL (decl)) + = (TREE_CODE (TREE_TYPE (decl)) == ARRAY_TYPE + || TREE_CODE (TREE_TYPE (decl)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (decl)) == UNION_TYPE + || TREE_CODE (TREE_TYPE (decl)) == QUAL_UNION_TYPE); + + /* Optionally set flags or add text to the name to record information + such as that it is a function name. + If the name is changed, the macro ASM_OUTPUT_LABELREF + will have to know how to strip this information. + And if it finds a * at the beginning after doing so, + it must handle that too. */ +#ifdef ENCODE_SECTION_INFO + ENCODE_SECTION_INFO (decl); +#endif + } + } +} + +/* Make the rtl for variable VAR be volatile. + Use this only for static variables. */ + +void +make_var_volatile (var) + tree var; +{ + if (GET_CODE (DECL_RTL (var)) != MEM) + abort (); + + MEM_VOLATILE_P (DECL_RTL (var)) = 1; +} + +/* Output alignment directive to align for constant expression EXP. */ + +void +assemble_constant_align (exp) + tree exp; +{ + int align; + + /* Align the location counter as required by EXP's data type. */ + align = TYPE_ALIGN (TREE_TYPE (exp)); +#ifdef CONSTANT_ALIGNMENT + align = CONSTANT_ALIGNMENT (exp, align); +#endif + + if (align > BITS_PER_UNIT) + ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); +} + +/* Output a string of literal assembler code + for an `asm' keyword used between functions. */ + +void +assemble_asm (string) + tree string; +{ + app_enable (); + + if (TREE_CODE (string) == ADDR_EXPR) + string = TREE_OPERAND (string, 0); + + fprintf (asm_out_file, "\t%s\n", TREE_STRING_POINTER (string)); +} + +#if 0 /* This should no longer be needed, because + flag_gnu_linker should be 0 on these systems, + which should prevent any output + if ASM_OUTPUT_CONSTRUCTOR and ASM_OUTPUT_DESTRUCTOR are absent. */ +#if !(defined(DBX_DEBUGGING_INFO) && !defined(FASCIST_ASSEMBLER)) +#ifndef ASM_OUTPUT_CONSTRUCTOR +#define ASM_OUTPUT_CONSTRUCTOR(file, name) +#endif +#ifndef ASM_OUTPUT_DESTRUCTOR +#define ASM_OUTPUT_DESTRUCTOR(file, name) +#endif +#endif +#endif /* 0 */ + +/* Record an element in the table of global destructors. + How this is done depends on what sort of assembler and linker + are in use. + + NAME should be the name of a global function to be called + at exit time. This name is output using assemble_name. */ + +void +assemble_destructor (name) + char *name; +{ +#ifdef ASM_OUTPUT_DESTRUCTOR + ASM_OUTPUT_DESTRUCTOR (asm_out_file, name); +#else + if (flag_gnu_linker) + { + /* Now tell GNU LD that this is part of the static destructor set. */ + /* This code works for any machine provided you use GNU as/ld. */ + fprintf (asm_out_file, "%s \"___DTOR_LIST__\",22,0,0,", ASM_STABS_OP); + assemble_name (asm_out_file, name); + fputc ('\n', asm_out_file); + } +#endif +} + +/* Likewise for global constructors. */ + +void +assemble_constructor (name) + char *name; +{ +#ifdef ASM_OUTPUT_CONSTRUCTOR + ASM_OUTPUT_CONSTRUCTOR (asm_out_file, name); +#else + if (flag_gnu_linker) + { + /* Now tell GNU LD that this is part of the static constructor set. */ + /* This code works for any machine provided you use GNU as/ld. */ + fprintf (asm_out_file, "%s \"___CTOR_LIST__\",22,0,0,", ASM_STABS_OP); + assemble_name (asm_out_file, name); + fputc ('\n', asm_out_file); + } +#endif +} + +/* Likewise for entries we want to record for garbage collection. + Garbage collection is still under development. */ + +void +assemble_gc_entry (name) + char *name; +{ +#ifdef ASM_OUTPUT_GC_ENTRY + ASM_OUTPUT_GC_ENTRY (asm_out_file, name); +#else + if (flag_gnu_linker) + { + /* Now tell GNU LD that this is part of the static constructor set. */ + fprintf (asm_out_file, "%s \"___PTR_LIST__\",22,0,0,", ASM_STABS_OP); + assemble_name (asm_out_file, name); + fputc ('\n', asm_out_file); + } +#endif +} + +/* Output assembler code for the constant pool of a function and associated + with defining the name of the function. DECL describes the function. + NAME is the function's name. For the constant pool, we use the current + constant pool data. */ + +void +assemble_start_function (decl, fnname) + tree decl; + char *fnname; +{ + int align; + + /* The following code does not need preprocessing in the assembler. */ + + app_disable (); + + output_constant_pool (fnname, decl); + + text_section (); + + + /* Tell assembler to move to target machine's alignment for functions. */ + align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); + if (align > 0) + ASM_OUTPUT_ALIGN (asm_out_file, align); + +#ifdef ASM_OUTPUT_FUNCTION_PREFIX + ASM_OUTPUT_FUNCTION_PREFIX (asm_out_file, fnname); +#endif + +#ifdef SDB_DEBUGGING_INFO + /* Output SDB definition of the function. */ + if (write_symbols == SDB_DEBUG) + sdbout_mark_begin_function (); +#endif + +#ifdef DBX_DEBUGGING_INFO + /* Output DBX definition of the function. */ + if (write_symbols == DBX_DEBUG) + dbxout_begin_function (decl); +#endif + + /* Make function name accessible from other files, if appropriate. */ + + if (TREE_PUBLIC (decl)) + { + if (!first_global_object_name) + STRIP_NAME_ENCODING (first_global_object_name, fnname); + ASM_GLOBALIZE_LABEL (asm_out_file, fnname); + } + + /* Do any machine/system dependent processing of the function name */ +#ifdef ASM_DECLARE_FUNCTION_NAME + ASM_DECLARE_FUNCTION_NAME (asm_out_file, fnname, current_function_decl); +#else + /* Standard thing is just output label for the function. */ + ASM_OUTPUT_LABEL (asm_out_file, fnname); +#endif /* ASM_DECLARE_FUNCTION_NAME */ +} + +/* Output assembler code associated with defining the size of the + function. DECL describes the function. NAME is the function's name. */ + +void +assemble_end_function (decl, fnname) + tree decl; + char *fnname; +{ +#ifdef ASM_DECLARE_FUNCTION_SIZE + ASM_DECLARE_FUNCTION_SIZE (asm_out_file, fnname, decl); +#endif +} + +/* Assemble code to leave SIZE bytes of zeros. */ + +void +assemble_zeros (size) + int size; +{ +#ifdef ASM_NO_SKIP_IN_TEXT + /* The `space' pseudo in the text section outputs nop insns rather than 0s, + so we must output 0s explicitly in the text section. */ + if (ASM_NO_SKIP_IN_TEXT && in_text_section ()) + { + int i; + + for (i = 0; i < size - 20; i += 20) + { +#ifdef ASM_BYTE_OP + fprintf (asm_out_file, + "%s 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n", ASM_BYTE_OP); +#else + fprintf (asm_out_file, + "\tbyte 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n"); +#endif + } + if (i < size) + { +#ifdef ASM_BYTE_OP + fprintf (asm_out_file, "%s 0", ASM_BYTE_OP); +#else + fprintf (asm_out_file, "\tbyte 0"); +#endif + i++; + for (; i < size; i++) + fprintf (asm_out_file, ",0"); + fprintf (asm_out_file, "\n"); + } + } + else +#endif + if (size > 0) + ASM_OUTPUT_SKIP (asm_out_file, size); +} + +/* Assemble a string constant with the specified C string as contents. */ + +void +assemble_string (p, size) + char *p; + int size; +{ + register int i; + int pos = 0; + int maximum = 2000; + + /* If the string is very long, split it up. */ + + while (pos < size) + { + int thissize = size - pos; + if (thissize > maximum) + thissize = maximum; + + ASM_OUTPUT_ASCII (asm_out_file, p, thissize); + + pos += thissize; + p += thissize; + } +} + +/* Assemble everything that is needed for a variable or function declaration. + Not used for automatic variables, and not used for function definitions. + Should not be called for variables of incomplete structure type. + + TOP_LEVEL is nonzero if this variable has file scope. + AT_END is nonzero if this is the special handling, at end of compilation, + to define things that have had only tentative definitions. */ + +void +assemble_variable (decl, top_level, at_end) + tree decl; + int top_level; + int at_end; +{ + register char *name; + int align; + tree size_tree; + int reloc = 0; + + if (GET_CODE (DECL_RTL (decl)) == REG) + { + /* Do output symbol info for global register variables, but do nothing + else for them. */ + + if (TREE_ASM_WRITTEN (decl)) + return; + TREE_ASM_WRITTEN (decl) = 1; + +#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) + /* File-scope global variables are output here. */ + if ((write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) + && top_level) + dbxout_symbol (decl, 0); +#endif +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG && top_level + /* Leave initialized global vars for end of compilation; + see comment in compile_file. */ + && (TREE_PUBLIC (decl) == 0 || DECL_INITIAL (decl) == 0)) + sdbout_symbol (decl, 0); +#endif + + /* Don't output any DWARF debugging information for variables here. + In the case of local variables, the information for them is output + when we do our recursive traversal of the tree representation for + the entire containing function. In the case of file-scope variables, + we output information for all of them at the very end of compilation + while we are doing our final traversal of the chain of file-scope + declarations. */ + + return; + } + + /* Normally no need to say anything here for external references, + since assemble_external is called by the langauge-specific code + when a declaration is first seen. */ + + if (DECL_EXTERNAL (decl)) + return; + + /* Output no assembler code for a function declaration. + Only definitions of functions output anything. */ + + if (TREE_CODE (decl) == FUNCTION_DECL) + return; + + /* If type was incomplete when the variable was declared, + see if it is complete now. */ + + if (DECL_SIZE (decl) == 0) + layout_decl (decl, 0); + + /* Still incomplete => don't allocate it; treat the tentative defn + (which is what it must have been) as an `extern' reference. */ + + if (DECL_SIZE (decl) == 0) + { + error_with_file_and_line (DECL_SOURCE_FILE (decl), + DECL_SOURCE_LINE (decl), + "storage size of `%s' isn't known", + IDENTIFIER_POINTER (DECL_NAME (decl))); + return; + } + + /* The first declaration of a variable that comes through this function + decides whether it is global (in C, has external linkage) + or local (in C, has internal linkage). So do nothing more + if this function has already run. */ + + if (TREE_ASM_WRITTEN (decl)) + return; + + TREE_ASM_WRITTEN (decl) = 1; + +#ifdef DBX_DEBUGGING_INFO + /* File-scope global variables are output here. */ + if (write_symbols == DBX_DEBUG && top_level) + dbxout_symbol (decl, 0); +#endif +#ifdef SDB_DEBUGGING_INFO + if (write_symbols == SDB_DEBUG && top_level + /* Leave initialized global vars for end of compilation; + see comment in compile_file. */ + && (TREE_PUBLIC (decl) == 0 || DECL_INITIAL (decl) == 0)) + sdbout_symbol (decl, 0); +#endif + + /* Don't output any DWARF debugging information for variables here. + In the case of local variables, the information for them is output + when we do our recursive traversal of the tree representation for + the entire containing function. In the case of file-scope variables, + we output information for all of them at the very end of compilation + while we are doing our final traversal of the chain of file-scope + declarations. */ + + /* If storage size is erroneously variable, just continue. + Error message was already made. */ + + if (TREE_CODE (DECL_SIZE (decl)) != INTEGER_CST) + goto finish; + + app_disable (); + + /* This is better than explicit arithmetic, since it avoids overflow. */ + size_tree = size_binop (CEIL_DIV_EXPR, + DECL_SIZE (decl), size_int (BITS_PER_UNIT)); + + if (TREE_INT_CST_HIGH (size_tree) != 0) + { + error_with_decl (decl, "size of variable `%s' is too large"); + goto finish; + } + + name = XSTR (XEXP (DECL_RTL (decl), 0), 0); + + /* Handle uninitialized definitions. */ + + /* ANSI specifies that a tentative definition which is not merged with + a non-tentative definition behaves exactly like a definition with an + initializer equal to zero. (Section 3.7.2) + -fno-common gives strict ANSI behavior. Usually you don't want it. */ + if (! flag_no_common + && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node)) + { + int size = TREE_INT_CST_LOW (size_tree); + int rounded = size; + + if (TREE_INT_CST_HIGH (size_tree) != 0) + error_with_decl (decl, "size of variable `%s' is too large"); + /* Don't allocate zero bytes of common, + since that means "undefined external" in the linker. */ + if (size == 0) rounded = 1; + /* Round size up to multiple of BIGGEST_ALIGNMENT bits + so that each uninitialized object starts on such a boundary. */ + rounded += (BIGGEST_ALIGNMENT / BITS_PER_UNIT) - 1; + rounded = (rounded / (BIGGEST_ALIGNMENT / BITS_PER_UNIT) + * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); +#if 0 + if (flag_shared_data) + data_section (); +#endif + if (TREE_PUBLIC (decl)) + { +#ifdef ASM_OUTPUT_SHARED_COMMON + if (flag_shared_data) + ASM_OUTPUT_SHARED_COMMON (asm_out_file, name, size, rounded); + else +#endif +#ifdef ASM_OUTPUT_ALIGNED_COMMON + ASM_OUTPUT_ALIGNED_COMMON (asm_out_file, name, size, + DECL_ALIGN (decl)); +#else + ASM_OUTPUT_COMMON (asm_out_file, name, size, rounded); +#endif + } + else + { +#ifdef ASM_OUTPUT_SHARED_LOCAL + if (flag_shared_data) + ASM_OUTPUT_SHARED_LOCAL (asm_out_file, name, size, rounded); + else +#endif +#ifdef ASM_OUTPUT_ALIGNED_LOCAL + ASM_OUTPUT_ALIGNED_LOCAL (asm_out_file, name, size, + DECL_ALIGN (decl)); +#else + ASM_OUTPUT_LOCAL (asm_out_file, name, size, rounded); +#endif + } + goto finish; + } + + /* Handle initialized definitions. */ + + /* First make the assembler name(s) global if appropriate. */ + if (TREE_PUBLIC (decl) && DECL_NAME (decl)) + { + if (!first_global_object_name) + STRIP_NAME_ENCODING(first_global_object_name, name); + ASM_GLOBALIZE_LABEL (asm_out_file, name); + } +#if 0 + for (d = equivalents; d; d = TREE_CHAIN (d)) + { + tree e = TREE_VALUE (d); + if (TREE_PUBLIC (e) && DECL_NAME (e)) + ASM_GLOBALIZE_LABEL (asm_out_file, + XSTR (XEXP (DECL_RTL (e), 0), 0)); + } +#endif + + /* Output any data that we will need to use the address of. */ + if (DECL_INITIAL (decl)) + reloc = output_addressed_constants (DECL_INITIAL (decl)); + + /* Switch to the proper section for this data. */ +#ifdef SELECT_SECTION + SELECT_SECTION (decl, reloc); +#else + if (TREE_READONLY (decl) + && ! TREE_THIS_VOLATILE (decl) + && ! (flag_pic && reloc)) + readonly_data_section (); + else + data_section (); +#endif + + /* Compute and output the alignment of this data. */ + + align = DECL_ALIGN (decl); + /* Some object file formats have a maximum alignment which they support. + In particular, a.out format supports a maximum alignment of 4. */ +#ifndef MAX_OFILE_ALIGNMENT +#define MAX_OFILE_ALIGNMENT BIGGEST_ALIGNMENT +#endif + if (align > MAX_OFILE_ALIGNMENT) + { + warning_with_decl (decl, + "alignment of `%s' is greater than maximum object file alignment"); + align = MAX_OFILE_ALIGNMENT; + } +#ifdef DATA_ALIGNMENT + /* On some machines, it is good to increase alignment sometimes. */ + align = DATA_ALIGNMENT (TREE_TYPE (decl), align); +#endif +#ifdef CONSTANT_ALIGNMENT + if (DECL_INITIAL (decl)) + align = CONSTANT_ALIGNMENT (DECL_INITIAL (decl), align); +#endif + + /* Reset the alignment in case we have made it tighter, so we can benefit + from it in get_pointer_alignment. */ + DECL_ALIGN (decl) = align; + + if (align > BITS_PER_UNIT) + ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); + + /* Do any machine/system dependent processing of the object. */ +#ifdef ASM_DECLARE_OBJECT_NAME + ASM_DECLARE_OBJECT_NAME (asm_out_file, name, decl); +#else + /* Standard thing is just output label for the object. */ + ASM_OUTPUT_LABEL (asm_out_file, name); +#endif /* ASM_DECLARE_OBJECT_NAME */ + +#if 0 + for (d = equivalents; d; d = TREE_CHAIN (d)) + { + tree e = TREE_VALUE (d); + ASM_OUTPUT_LABEL (asm_out_file, XSTR (XEXP (DECL_RTL (e), 0), 0)); + } +#endif + + if (DECL_INITIAL (decl)) + /* Output the actual data. */ + output_constant (DECL_INITIAL (decl), + int_size_in_bytes (TREE_TYPE (decl))); + else + /* Leave space for it. */ + assemble_zeros (int_size_in_bytes (TREE_TYPE (decl))); + + finish: +#ifdef XCOFF_DEBUGGING_INFO + /* Unfortunately, the IBM assembler cannot handle stabx before the actual + declaration. When something like ".stabx "aa:S-2",aa,133,0" is emitted + and `aa' hasn't been output yet, the assembler generates a stab entry with + a value of zero, in addition to creating an unnecessary external entry + for `aa'. Hence, we must postpone dbxout_symbol to here at the end. */ + + /* File-scope global variables are output here. */ + if (write_symbols == XCOFF_DEBUG && top_level) + dbxout_symbol (decl, 0); +#else + /* There must be a statement after a label. */ + ; +#endif +} + +/* Output something to declare an external symbol to the assembler. + (Most assemblers don't need this, so we normally output nothing.) + Do nothing if DECL is not external. */ + +void +assemble_external (decl) + tree decl; +{ +#ifdef ASM_OUTPUT_EXTERNAL + if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd' + && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)) + { + rtx rtl = DECL_RTL (decl); + + if (GET_CODE (rtl) == MEM && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF + && ! SYMBOL_REF_USED (XEXP (rtl, 0))) + { + /* Some systems do require some output. */ + SYMBOL_REF_USED (XEXP (rtl, 0)) = 1; + ASM_OUTPUT_EXTERNAL (asm_out_file, decl, XSTR (XEXP (rtl, 0), 0)); + } + } +#endif +} + +/* Similar, for calling a library function FUN. */ + +void +assemble_external_libcall (fun) + rtx fun; +{ +#ifdef ASM_OUTPUT_EXTERNAL_LIBCALL + /* Declare library function name external when first used, if nec. */ + if (! SYMBOL_REF_USED (fun)) + { + SYMBOL_REF_USED (fun) = 1; + ASM_OUTPUT_EXTERNAL_LIBCALL (asm_out_file, fun); + } +#endif +} + +/* Declare the label NAME global. */ + +void +assemble_global (name) + char *name; +{ + ASM_GLOBALIZE_LABEL (asm_out_file, name); +} + +/* Assemble a label named NAME. */ + +void +assemble_label (name) + char *name; +{ + ASM_OUTPUT_LABEL (asm_out_file, name); +} + +/* Output to FILE a reference to the assembler name of a C-level name NAME. + If NAME starts with a *, the rest of NAME is output verbatim. + Otherwise NAME is transformed in an implementation-defined way + (usually by the addition of an underscore). + Many macros in the tm file are defined to call this function. */ + +void +assemble_name (file, name) + FILE *file; + char *name; +{ + if (name[0] == '*') + fputs (&name[1], file); + else + ASM_OUTPUT_LABELREF (file, name); +} + +/* Allocate SIZE bytes writable static space with a gensym name + and return an RTX to refer to its address. */ + +rtx +assemble_static_space (size) + int size; +{ + char name[12]; + char *namestring; + rtx x; + /* Round size up to multiple of BIGGEST_ALIGNMENT bits + so that each uninitialized object starts on such a boundary. */ + int rounded = ((size + (BIGGEST_ALIGNMENT / BITS_PER_UNIT) - 1) + / (BIGGEST_ALIGNMENT / BITS_PER_UNIT) + * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); + +#if 0 + if (flag_shared_data) + data_section (); +#endif + + ASM_GENERATE_INTERNAL_LABEL (name, "LF", const_labelno); + ++const_labelno; + + namestring = (char *) obstack_alloc (saveable_obstack, + strlen (name) + 2); + strcpy (namestring, name); + + x = gen_rtx (SYMBOL_REF, Pmode, namestring); +#ifdef ASM_OUTPUT_ALIGNED_LOCAL + ASM_OUTPUT_ALIGNED_LOCAL (asm_out_file, name, size, BIGGEST_ALIGNMENT); +#else + ASM_OUTPUT_LOCAL (asm_out_file, name, size, rounded); +#endif + return x; +} + +/* Assemble the static constant template for function entry trampolines. + This is done at most once per compilation. + Returns an RTX for the address of the template. */ + +rtx +assemble_trampoline_template () +{ + char label[256]; + char *name; + int align; + + /* By default, put trampoline templates in read-only data section. */ + +#ifdef TRAMPOLINE_SECTION + TRAMPOLINE_SECTION (); +#else + readonly_data_section (); +#endif + + /* Write the assembler code to define one. */ + align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); + if (align > 0) + ASM_OUTPUT_ALIGN (asm_out_file, align); + + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LTRAMP", 0); + TRAMPOLINE_TEMPLATE (asm_out_file); + + /* Record the rtl to refer to it. */ + ASM_GENERATE_INTERNAL_LABEL (label, "LTRAMP", 0); + name + = (char *) obstack_copy0 (&permanent_obstack, label, strlen (label)); + return gen_rtx (SYMBOL_REF, Pmode, name); +} + +/* Assemble the integer constant X into an object of SIZE bytes. + X must be either a CONST_INT or CONST_DOUBLE. + + Return 1 if we were able to output the constant, otherwise 0. If FORCE is + non-zero, abort if we can't output the constant. */ + +int +assemble_integer (x, size, force) + rtx x; + int size; + int force; +{ + /* First try to use the standard 1, 2, 4, 8, and 16 byte + ASM_OUTPUT... macros. */ + + switch (size) + { +#ifdef ASM_OUTPUT_CHAR + case 1: + ASM_OUTPUT_CHAR (asm_out_file, x); + return 1; +#endif + +#ifdef ASM_OUTPUT_SHORT + case 2: + ASM_OUTPUT_SHORT (asm_out_file, x); + return 1; +#endif + +#ifdef ASM_OUTPUT_INT + case 4: + ASM_OUTPUT_INT (asm_out_file, x); + return 1; +#endif + +#ifdef ASM_OUTPUT_DOUBLE_INT + case 8: + ASM_OUTPUT_DOUBLE_INT (asm_out_file, x); + return 1; +#endif + +#ifdef ASM_OUTPUT_QUADRUPLE_INT + case 16: + ASM_OUTPUT_QUADRUPLE_INT (asm_out_file, x); + return 1; +#endif + } + + /* If we couldn't do it that way, there are two other possibilities: First, + if the machine can output an explicit byte and this is a 1 byte constant, + we can use ASM_OUTPUT_BYTE. */ + +#ifdef ASM_OUTPUT_BYTE + if (size == 1 && GET_CODE (x) == CONST_INT) + { + ASM_OUTPUT_BYTE (asm_out_file, INTVAL (x)); + return 1; + } +#endif + + /* Finally, if SIZE is larger than a single word, try to output the constant + one word at a time. */ + + if (size > UNITS_PER_WORD) + { + int i; + enum machine_mode mode + = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); + rtx word; + + for (i = 0; i < size / UNITS_PER_WORD; i++) + { + word = operand_subword (x, i, 0, mode); + + if (word == 0) + break; + + if (! assemble_integer (word, UNITS_PER_WORD, 0)) + break; + } + + if (i == size / UNITS_PER_WORD) + return 1; + /* If we output at least one word and then could not finish, + there is no valid way to continue. */ + if (i > 0) + abort (); + } + + if (force) + abort (); + + return 0; +} + +/* Assemble the floating-point constant D into an object of size MODE. */ + +void +assemble_real (d, mode) + REAL_VALUE_TYPE d; + enum machine_mode mode; +{ + jmp_buf output_constant_handler; + + if (setjmp (output_constant_handler)) + { + error ("floating point trap outputting a constant"); +#ifdef REAL_IS_NOT_DOUBLE + bzero (&d, sizeof d); + d = dconst0; +#else + d = 0; +#endif + } + + set_float_handler (output_constant_handler); + + switch (mode) + { +#ifdef ASM_OUTPUT_BYTE_FLOAT + case QFmode: + ASM_OUTPUT_BYTE_FLOAT (asm_out_file, d); + break; +#endif +#ifdef ASM_OUTPUT_SHORT_FLOAT + case HFmode: + ASM_OUTPUT_SHORT_FLOAT (asm_out_file, d); + break; +#endif +#ifdef ASM_OUTPUT_FLOAT + case SFmode: + ASM_OUTPUT_FLOAT (asm_out_file, d); + break; +#endif + +#ifdef ASM_OUTPUT_DOUBLE + case DFmode: + ASM_OUTPUT_DOUBLE (asm_out_file, d); + break; +#endif + +#ifdef ASM_OUTPUT_LONG_DOUBLE + case XFmode: + case TFmode: + ASM_OUTPUT_LONG_DOUBLE (asm_out_file, d); + break; +#endif + + default: + abort (); + } + + set_float_handler (NULL_PTR); +} + +/* Here we combine duplicate floating constants to make + CONST_DOUBLE rtx's, and force those out to memory when necessary. */ + +/* Chain of all CONST_DOUBLE rtx's constructed for the current function. + They are chained through the CONST_DOUBLE_CHAIN. + A CONST_DOUBLE rtx has CONST_DOUBLE_MEM != cc0_rtx iff it is on this chain. + In that case, CONST_DOUBLE_MEM is either a MEM, + or const0_rtx if no MEM has been made for this CONST_DOUBLE yet. + + (CONST_DOUBLE_MEM is used only for top-level functions. + See force_const_mem for explanation.) */ + +static rtx const_double_chain; + +/* Return a CONST_DOUBLE for a value specified as a pair of ints. + For an integer, I0 is the low-order word and I1 is the high-order word. + For a real number, I0 is the word with the low address + and I1 is the word with the high address. */ + +rtx +immed_double_const (i0, i1, mode) + HOST_WIDE_INT i0, i1; + enum machine_mode mode; +{ + register rtx r; + int in_current_obstack; + + if (GET_MODE_CLASS (mode) == MODE_INT + || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) + { + /* We clear out all bits that don't belong in MODE, unless they and our + sign bit are all one. So we get either a reasonable negative value + or a reasonable unsigned value for this mode. */ + int width = GET_MODE_BITSIZE (mode); + if (width < HOST_BITS_PER_WIDE_INT + && ((i0 & ((HOST_WIDE_INT) (-1) << (width - 1))) + != ((HOST_WIDE_INT) (-1) << (width - 1)))) + i0 &= ((HOST_WIDE_INT) 1 << width) - 1, i1 = 0; + else if (width == HOST_BITS_PER_WIDE_INT + && ! (i1 == ~0 && i0 < 0)) + i1 = 0; + else if (width > 2 * HOST_BITS_PER_WIDE_INT) + /* We cannot represent this value as a constant. */ + abort (); + + /* If MODE fits within HOST_BITS_PER_WIDE_INT, always use a CONST_INT. + + ??? Strictly speaking, this is wrong if we create a CONST_INT + for a large unsigned constant with the size of MODE being + HOST_BITS_PER_WIDE_INT and later try to interpret that constant in a + wider mode. In that case we will mis-interpret it as a negative + number. + + Unfortunately, the only alternative is to make a CONST_DOUBLE + for any constant in any mode if it is an unsigned constant larger + than the maximum signed integer in an int on the host. However, + doing this will break everyone that always expects to see a CONST_INT + for SImode and smaller. + + We have always been making CONST_INTs in this case, so nothing new + is being broken. */ + + if (width <= HOST_BITS_PER_WIDE_INT) + i1 = (i0 < 0) ? ~0 : 0; + + /* If this integer fits in one word, return a CONST_INT. */ + if ((i1 == 0 && i0 >= 0) + || (i1 == ~0 && i0 < 0)) + return GEN_INT (i0); + + /* We use VOIDmode for integers. */ + mode = VOIDmode; + } + + /* Search the chain for an existing CONST_DOUBLE with the right value. + If one is found, return it. */ + + for (r = const_double_chain; r; r = CONST_DOUBLE_CHAIN (r)) + if (CONST_DOUBLE_LOW (r) == i0 && CONST_DOUBLE_HIGH (r) == i1 + && GET_MODE (r) == mode) + return r; + + /* No; make a new one and add it to the chain. + + We may be called by an optimizer which may be discarding any memory + allocated during its processing (such as combine and loop). However, + we will be leaving this constant on the chain, so we cannot tolerate + freed memory. So switch to saveable_obstack for this allocation + and then switch back if we were in current_obstack. */ + + push_obstacks_nochange (); + rtl_in_saveable_obstack (); + r = gen_rtx (CONST_DOUBLE, mode, 0, i0, i1); + pop_obstacks (); + + /* Don't touch const_double_chain in nested function; + see force_const_mem. */ + if (outer_function_chain == 0) + { + CONST_DOUBLE_CHAIN (r) = const_double_chain; + const_double_chain = r; + } + + /* Store const0_rtx in mem-slot since this CONST_DOUBLE is on the chain. + Actual use of mem-slot is only through force_const_mem. */ + + CONST_DOUBLE_MEM (r) = const0_rtx; + + return r; +} + +/* Return a CONST_DOUBLE for a specified `double' value + and machine mode. */ + +rtx +immed_real_const_1 (d, mode) + REAL_VALUE_TYPE d; + enum machine_mode mode; +{ + union real_extract u; + register rtx r; + int in_current_obstack; + + /* Get the desired `double' value as a sequence of ints + since that is how they are stored in a CONST_DOUBLE. */ + + u.d = d; + + /* Detect special cases. */ + + /* Avoid REAL_VALUES_EQUAL here in order to distinguish minus zero. */ + if (!bcmp (&dconst0, &d, sizeof d)) + return CONST0_RTX (mode); + /* Check for NaN first, because some ports (specifically the i386) do not + emit correct ieee-fp code by default, and thus will generate a core + dump here if we pass a NaN to REAL_VALUES_EQUAL and if REAL_VALUES_EQUAL + does a floating point comparison. */ + else if (! REAL_VALUE_ISNAN (d) && REAL_VALUES_EQUAL (dconst1, d)) + return CONST1_RTX (mode); + + if (sizeof u == 2 * sizeof (HOST_WIDE_INT)) + return immed_double_const (u.i[0], u.i[1], mode); + + /* The rest of this function handles the case where + a float value requires more than 2 ints of space. + It will be deleted as dead code on machines that don't need it. */ + + /* Search the chain for an existing CONST_DOUBLE with the right value. + If one is found, return it. */ + + for (r = const_double_chain; r; r = CONST_DOUBLE_CHAIN (r)) + if (! bcmp (&CONST_DOUBLE_LOW (r), &u, sizeof u) + && GET_MODE (r) == mode) + return r; + + /* No; make a new one and add it to the chain. + + We may be called by an optimizer which may be discarding any memory + allocated during its processing (such as combine and loop). However, + we will be leaving this constant on the chain, so we cannot tolerate + freed memory. So switch to saveable_obstack for this allocation + and then switch back if we were in current_obstack. */ + + push_obstacks_nochange (); + rtl_in_saveable_obstack (); + r = rtx_alloc (CONST_DOUBLE); + PUT_MODE (r, mode); + bcopy (&u, &CONST_DOUBLE_LOW (r), sizeof u); + pop_obstacks (); + + /* Don't touch const_double_chain in nested function; + see force_const_mem. */ + if (outer_function_chain == 0) + { + CONST_DOUBLE_CHAIN (r) = const_double_chain; + const_double_chain = r; + } + + /* Store const0_rtx in CONST_DOUBLE_MEM since this CONST_DOUBLE is on the + chain, but has not been allocated memory. Actual use of CONST_DOUBLE_MEM + is only through force_const_mem. */ + + CONST_DOUBLE_MEM (r) = const0_rtx; + + return r; +} + +/* Return a CONST_DOUBLE rtx for a value specified by EXP, + which must be a REAL_CST tree node. */ + +rtx +immed_real_const (exp) + tree exp; +{ + return immed_real_const_1 (TREE_REAL_CST (exp), TYPE_MODE (TREE_TYPE (exp))); +} + +/* At the end of a function, forget the memory-constants + previously made for CONST_DOUBLEs. Mark them as not on real_constant_chain. + Also clear out real_constant_chain and clear out all the chain-pointers. */ + +void +clear_const_double_mem () +{ + register rtx r, next; + + /* Don't touch CONST_DOUBLE_MEM for nested functions. + See force_const_mem for explanation. */ + if (outer_function_chain != 0) + return; + + for (r = const_double_chain; r; r = next) + { + next = CONST_DOUBLE_CHAIN (r); + CONST_DOUBLE_CHAIN (r) = 0; + CONST_DOUBLE_MEM (r) = cc0_rtx; + } + const_double_chain = 0; +} + +/* Given an expression EXP with a constant value, + reduce it to the sum of an assembler symbol and an integer. + Store them both in the structure *VALUE. + Abort if EXP does not reduce. */ + +struct addr_const +{ + rtx base; + HOST_WIDE_INT offset; +}; + +static void +decode_addr_const (exp, value) + tree exp; + struct addr_const *value; +{ + register tree target = TREE_OPERAND (exp, 0); + register int offset = 0; + register rtx x; + + while (1) + { + if (TREE_CODE (target) == COMPONENT_REF + && (TREE_CODE (DECL_FIELD_BITPOS (TREE_OPERAND (target, 1))) + == INTEGER_CST)) + { + offset += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (TREE_OPERAND (target, 1))) / BITS_PER_UNIT; + target = TREE_OPERAND (target, 0); + } + else if (TREE_CODE (target) == ARRAY_REF) + { + if (TREE_CODE (TREE_OPERAND (target, 1)) != INTEGER_CST + || TREE_CODE (TYPE_SIZE (TREE_TYPE (target))) != INTEGER_CST) + abort (); + offset += ((TREE_INT_CST_LOW (TYPE_SIZE (TREE_TYPE (target))) + * TREE_INT_CST_LOW (TREE_OPERAND (target, 1))) + / BITS_PER_UNIT); + target = TREE_OPERAND (target, 0); + } + else + break; + } + + switch (TREE_CODE (target)) + { + case VAR_DECL: + case FUNCTION_DECL: + x = DECL_RTL (target); + break; + + case LABEL_DECL: + x = gen_rtx (MEM, FUNCTION_MODE, + gen_rtx (LABEL_REF, VOIDmode, + label_rtx (TREE_OPERAND (exp, 0)))); + break; + + case REAL_CST: + case STRING_CST: + case COMPLEX_CST: + case CONSTRUCTOR: + x = TREE_CST_RTL (target); + break; + + default: + abort (); + } + + if (GET_CODE (x) != MEM) + abort (); + x = XEXP (x, 0); + + value->base = x; + value->offset = offset; +} + +/* Uniquize all constants that appear in memory. + Each constant in memory thus far output is recorded + in `const_hash_table' with a `struct constant_descriptor' + that contains a polish representation of the value of + the constant. + + We cannot store the trees in the hash table + because the trees may be temporary. */ + +struct constant_descriptor +{ + struct constant_descriptor *next; + char *label; + char contents[1]; +}; + +#define HASHBITS 30 +#define MAX_HASH_TABLE 1009 +static struct constant_descriptor *const_hash_table[MAX_HASH_TABLE]; + +/* Compute a hash code for a constant expression. */ + +int +const_hash (exp) + tree exp; +{ + register char *p; + register int len, hi, i; + register enum tree_code code = TREE_CODE (exp); + + if (code == INTEGER_CST) + { + p = (char *) &TREE_INT_CST_LOW (exp); + len = 2 * sizeof TREE_INT_CST_LOW (exp); + } + else if (code == REAL_CST) + { + p = (char *) &TREE_REAL_CST (exp); + len = sizeof TREE_REAL_CST (exp); + } + else if (code == STRING_CST) + p = TREE_STRING_POINTER (exp), len = TREE_STRING_LENGTH (exp); + else if (code == COMPLEX_CST) + return const_hash (TREE_REALPART (exp)) * 5 + + const_hash (TREE_IMAGPART (exp)); + else if (code == CONSTRUCTOR) + { + register tree link; + + /* For record type, include the type in the hashing. + We do not do so for array types + because (1) the sizes of the elements are sufficient + and (2) distinct array types can have the same constructor. + Instead, we include the array size because the constructor could + be shorter. */ + if (TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE) + hi = ((HOST_WIDE_INT) TREE_TYPE (exp) & ((1 << HASHBITS) - 1)) + % MAX_HASH_TABLE; + else + hi = ((5 + int_size_in_bytes (TREE_TYPE (exp))) + & ((1 << HASHBITS) - 1)) % MAX_HASH_TABLE; + + for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link)) + if (TREE_VALUE (link)) + hi = (hi * 603 + const_hash (TREE_VALUE (link))) % MAX_HASH_TABLE; + + return hi; + } + else if (code == ADDR_EXPR) + { + struct addr_const value; + decode_addr_const (exp, &value); + if (GET_CODE (value.base) == SYMBOL_REF) + { + /* Don't hash the address of the SYMBOL_REF; + only use the offset and the symbol name. */ + hi = value.offset; + p = XSTR (value.base, 0); + for (i = 0; p[i] != 0; i++) + hi = ((hi * 613) + (unsigned)(p[i])); + } + else if (GET_CODE (value.base) == LABEL_REF) + hi = value.offset + CODE_LABEL_NUMBER (XEXP (value.base, 0)) * 13; + + hi &= (1 << HASHBITS) - 1; + hi %= MAX_HASH_TABLE; + return hi; + } + else if (code == PLUS_EXPR || code == MINUS_EXPR) + return const_hash (TREE_OPERAND (exp, 0)) * 9 + + const_hash (TREE_OPERAND (exp, 1)); + else if (code == NOP_EXPR || code == CONVERT_EXPR) + return const_hash (TREE_OPERAND (exp, 0)) * 7 + 2; + + /* Compute hashing function */ + hi = len; + for (i = 0; i < len; i++) + hi = ((hi * 613) + (unsigned)(p[i])); + + hi &= (1 << HASHBITS) - 1; + hi %= MAX_HASH_TABLE; + return hi; +} + +/* Compare a constant expression EXP with a constant-descriptor DESC. + Return 1 if DESC describes a constant with the same value as EXP. */ + +static int +compare_constant (exp, desc) + tree exp; + struct constant_descriptor *desc; +{ + return 0 != compare_constant_1 (exp, desc->contents); +} + +/* Compare constant expression EXP with a substring P of a constant descriptor. + If they match, return a pointer to the end of the substring matched. + If they do not match, return 0. + + Since descriptors are written in polish prefix notation, + this function can be used recursively to test one operand of EXP + against a subdescriptor, and if it succeeds it returns the + address of the subdescriptor for the next operand. */ + +static char * +compare_constant_1 (exp, p) + tree exp; + char *p; +{ + register char *strp; + register int len; + register enum tree_code code = TREE_CODE (exp); + + if (code != (enum tree_code) *p++) + return 0; + + if (code == INTEGER_CST) + { + /* Integer constants are the same only if the same width of type. */ + if (*p++ != TYPE_PRECISION (TREE_TYPE (exp))) + return 0; + strp = (char *) &TREE_INT_CST_LOW (exp); + len = 2 * sizeof TREE_INT_CST_LOW (exp); + } + else if (code == REAL_CST) + { + /* Real constants are the same only if the same width of type. */ + if (*p++ != TYPE_PRECISION (TREE_TYPE (exp))) + return 0; + strp = (char *) &TREE_REAL_CST (exp); + len = sizeof TREE_REAL_CST (exp); + } + else if (code == STRING_CST) + { + if (flag_writable_strings) + return 0; + strp = TREE_STRING_POINTER (exp); + len = TREE_STRING_LENGTH (exp); + if (bcmp (&TREE_STRING_LENGTH (exp), p, + sizeof TREE_STRING_LENGTH (exp))) + return 0; + p += sizeof TREE_STRING_LENGTH (exp); + } + else if (code == COMPLEX_CST) + { + p = compare_constant_1 (TREE_REALPART (exp), p); + if (p == 0) return 0; + p = compare_constant_1 (TREE_IMAGPART (exp), p); + return p; + } + else if (code == CONSTRUCTOR) + { + register tree link; + int length = list_length (CONSTRUCTOR_ELTS (exp)); + tree type; + + if (bcmp (&length, p, sizeof length)) + return 0; + p += sizeof length; + + /* For record constructors, insist that the types match. + For arrays, just verify both constructors are for arrays. */ + if (TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE) + type = TREE_TYPE (exp); + else + type = 0; + if (bcmp (&type, p, sizeof type)) + return 0; + p += sizeof type; + + /* For arrays, insist that the size in bytes match. */ + if (TREE_CODE (TREE_TYPE (exp)) == ARRAY_TYPE) + { + int size = int_size_in_bytes (TREE_TYPE (exp)); + if (bcmp (&size, p, sizeof size)) + return 0; + p += sizeof size; + } + + for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link)) + { + if (TREE_VALUE (link)) + { + if ((p = compare_constant_1 (TREE_VALUE (link), p)) == 0) + return 0; + } + else + { + tree zero = 0; + + if (bcmp (&zero, p, sizeof zero)) + return 0; + p += sizeof zero; + } + } + + return p; + } + else if (code == ADDR_EXPR) + { + struct addr_const value; + decode_addr_const (exp, &value); + strp = (char *) &value.offset; + len = sizeof value.offset; + /* Compare the offset. */ + while (--len >= 0) + if (*p++ != *strp++) + return 0; + /* Compare symbol name. */ + strp = XSTR (value.base, 0); + len = strlen (strp) + 1; + } + else if (code == PLUS_EXPR || code == MINUS_EXPR) + { + p = compare_constant_1 (TREE_OPERAND (exp, 0), p); + if (p == 0) return 0; + p = compare_constant_1 (TREE_OPERAND (exp, 1), p); + return p; + } + else if (code == NOP_EXPR || code == CONVERT_EXPR) + { + p = compare_constant_1 (TREE_OPERAND (exp, 0), p); + return p; + } + + /* Compare constant contents. */ + while (--len >= 0) + if (*p++ != *strp++) + return 0; + + return p; +} + +/* Construct a constant descriptor for the expression EXP. + It is up to the caller to enter the descriptor in the hash table. */ + +static struct constant_descriptor * +record_constant (exp) + tree exp; +{ + struct constant_descriptor *next = 0; + char *label = 0; + + /* Make a struct constant_descriptor. The first two pointers will + be filled in later. Here we just leave space for them. */ + + obstack_grow (&permanent_obstack, (char *) &next, sizeof next); + obstack_grow (&permanent_obstack, (char *) &label, sizeof label); + record_constant_1 (exp); + return (struct constant_descriptor *) obstack_finish (&permanent_obstack); +} + +/* Add a description of constant expression EXP + to the object growing in `permanent_obstack'. + No need to return its address; the caller will get that + from the obstack when the object is complete. */ + +static void +record_constant_1 (exp) + tree exp; +{ + register char *strp; + register int len; + register enum tree_code code = TREE_CODE (exp); + + obstack_1grow (&permanent_obstack, (unsigned int) code); + + if (code == INTEGER_CST) + { + obstack_1grow (&permanent_obstack, TYPE_PRECISION (TREE_TYPE (exp))); + strp = (char *) &TREE_INT_CST_LOW (exp); + len = 2 * sizeof TREE_INT_CST_LOW (exp); + } + else if (code == REAL_CST) + { + obstack_1grow (&permanent_obstack, TYPE_PRECISION (TREE_TYPE (exp))); + strp = (char *) &TREE_REAL_CST (exp); + len = sizeof TREE_REAL_CST (exp); + } + else if (code == STRING_CST) + { + if (flag_writable_strings) + return; + strp = TREE_STRING_POINTER (exp); + len = TREE_STRING_LENGTH (exp); + obstack_grow (&permanent_obstack, (char *) &TREE_STRING_LENGTH (exp), + sizeof TREE_STRING_LENGTH (exp)); + } + else if (code == COMPLEX_CST) + { + record_constant_1 (TREE_REALPART (exp)); + record_constant_1 (TREE_IMAGPART (exp)); + return; + } + else if (code == CONSTRUCTOR) + { + register tree link; + int length = list_length (CONSTRUCTOR_ELTS (exp)); + tree type; + + obstack_grow (&permanent_obstack, (char *) &length, sizeof length); + + /* For record constructors, insist that the types match. + For arrays, just verify both constructors are for arrays. */ + if (TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE) + type = TREE_TYPE (exp); + else + type = 0; + obstack_grow (&permanent_obstack, (char *) &type, sizeof type); + + /* For arrays, insist that the size in bytes match. */ + if (TREE_CODE (TREE_TYPE (exp)) == ARRAY_TYPE) + { + int size = int_size_in_bytes (TREE_TYPE (exp)); + obstack_grow (&permanent_obstack, (char *) &size, sizeof size); + } + + for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link)) + { + if (TREE_VALUE (link)) + record_constant_1 (TREE_VALUE (link)); + else + { + tree zero = 0; + + obstack_grow (&permanent_obstack, (char *) &zero, sizeof zero); + } + } + + return; + } + else if (code == ADDR_EXPR) + { + struct addr_const value; + decode_addr_const (exp, &value); + /* Record the offset. */ + obstack_grow (&permanent_obstack, + (char *) &value.offset, sizeof value.offset); + /* Record the symbol name. */ + obstack_grow (&permanent_obstack, XSTR (value.base, 0), + strlen (XSTR (value.base, 0)) + 1); + return; + } + else if (code == PLUS_EXPR || code == MINUS_EXPR) + { + record_constant_1 (TREE_OPERAND (exp, 0)); + record_constant_1 (TREE_OPERAND (exp, 1)); + return; + } + else if (code == NOP_EXPR || code == CONVERT_EXPR) + { + record_constant_1 (TREE_OPERAND (exp, 0)); + return; + } + + /* Record constant contents. */ + obstack_grow (&permanent_obstack, strp, len); +} + +/* Return an rtx representing a reference to constant data in memory + for the constant expression EXP. + If assembler code for such a constant has already been output, + return an rtx to refer to it. + Otherwise, output such a constant in memory and generate + an rtx for it. The TREE_CST_RTL of EXP is set up to point to that rtx. + The const_hash_table records which constants already have label strings. */ + +rtx +output_constant_def (exp) + tree exp; +{ + register int hash, align; + register struct constant_descriptor *desc; + char label[256]; + char *found = 0; + int reloc; + register rtx def; + + if (TREE_CODE (exp) == INTEGER_CST) + abort (); /* No TREE_CST_RTL slot in these. */ + + if (TREE_CST_RTL (exp)) + return TREE_CST_RTL (exp); + + /* Make sure any other constants whose addresses appear in EXP + are assigned label numbers. */ + + reloc = output_addressed_constants (exp); + + /* Compute hash code of EXP. Search the descriptors for that hash code + to see if any of them describes EXP. If yes, the descriptor records + the label number already assigned. */ + + hash = const_hash (exp) % MAX_HASH_TABLE; + + for (desc = const_hash_table[hash]; desc; desc = desc->next) + if (compare_constant (exp, desc)) + { + found = desc->label; + break; + } + + if (found == 0) + { + /* No constant equal to EXP is known to have been output. + Make a constant descriptor to enter EXP in the hash table. + Assign the label number and record it in the descriptor for + future calls to this function to find. */ + + /* Create a string containing the label name, in LABEL. */ + ASM_GENERATE_INTERNAL_LABEL (label, "LC", const_labelno); + + desc = record_constant (exp); + desc->next = const_hash_table[hash]; + desc->label + = (char *) obstack_copy0 (&permanent_obstack, label, strlen (label)); + const_hash_table[hash] = desc; + } + + /* We have a symbol name; construct the SYMBOL_REF and the MEM. */ + + push_obstacks_nochange (); + if (TREE_PERMANENT (exp)) + end_temporary_allocation (); + + def = gen_rtx (SYMBOL_REF, Pmode, desc->label); + + TREE_CST_RTL (exp) + = gen_rtx (MEM, TYPE_MODE (TREE_TYPE (exp)), def); + RTX_UNCHANGING_P (TREE_CST_RTL (exp)) = 1; + if (TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE + || TREE_CODE (TREE_TYPE (exp)) == ARRAY_TYPE) + MEM_IN_STRUCT_P (TREE_CST_RTL (exp)) = 1; + + pop_obstacks (); + + /* Optionally set flags or add text to the name to record information + such as that it is a function name. If the name is changed, the macro + ASM_OUTPUT_LABELREF will have to know how to strip this information. + And if it finds a * at the beginning after doing so, it must handle + that too. */ +#ifdef ENCODE_SECTION_INFO + ENCODE_SECTION_INFO (exp); +#endif + + if (found == 0) + { + /* Now output assembler code to define that label + and follow it with the data of EXP. */ + + /* First switch to text section, except for writable strings. */ +#ifdef SELECT_SECTION + SELECT_SECTION (exp, reloc); +#else + if (((TREE_CODE (exp) == STRING_CST) && flag_writable_strings) + || (flag_pic && reloc)) + data_section (); + else + readonly_data_section (); +#endif + + /* Align the location counter as required by EXP's data type. */ + align = TYPE_ALIGN (TREE_TYPE (exp)); +#ifdef CONSTANT_ALIGNMENT + align = CONSTANT_ALIGNMENT (exp, align); +#endif + + if (align > BITS_PER_UNIT) + ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); + + /* Output the label itself. */ + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LC", const_labelno); + + /* Output the value of EXP. */ + output_constant (exp, + (TREE_CODE (exp) == STRING_CST + ? TREE_STRING_LENGTH (exp) + : int_size_in_bytes (TREE_TYPE (exp)))); + + ++const_labelno; + } + + return TREE_CST_RTL (exp); +} + +/* Similar hash facility for making memory-constants + from constant rtl-expressions. It is used on RISC machines + where immediate integer arguments and constant addresses are restricted + so that such constants must be stored in memory. + + This pool of constants is reinitialized for each function + so each function gets its own constants-pool that comes right before it. + + All structures allocated here are discarded when functions are saved for + inlining, so they do not need to be allocated permanently. */ + +#define MAX_RTX_HASH_TABLE 61 +static struct constant_descriptor **const_rtx_hash_table; + +/* Structure to represent sufficient information about a constant so that + it can be output when the constant pool is output, so that function + integration can be done, and to simplify handling on machines that reference + constant pool as base+displacement. */ + +struct pool_constant +{ + struct constant_descriptor *desc; + struct pool_constant *next; + enum machine_mode mode; + rtx constant; + int labelno; + int align; + int offset; +}; + +/* Pointers to first and last constant in pool. */ + +static struct pool_constant *first_pool, *last_pool; + +/* Current offset in constant pool (does not include any machine-specific + header. */ + +static int pool_offset; + +/* Structure used to maintain hash table mapping symbols used to their + corresponding constants. */ + +struct pool_sym +{ + char *label; + struct pool_constant *pool; + struct pool_sym *next; +}; + +static struct pool_sym **const_rtx_sym_hash_table; + +/* Hash code for a SYMBOL_REF with CONSTANT_POOL_ADDRESS_P true. + The argument is XSTR (... , 0) */ + +#define SYMHASH(LABEL) \ + ((((HOST_WIDE_INT) (LABEL)) & ((1 << HASHBITS) - 1)) % MAX_RTX_HASH_TABLE) + +/* Initialize constant pool hashing for next function. */ + +void +init_const_rtx_hash_table () +{ + const_rtx_hash_table + = ((struct constant_descriptor **) + oballoc (MAX_RTX_HASH_TABLE * sizeof (struct constant_descriptor *))); + const_rtx_sym_hash_table + = ((struct pool_sym **) + oballoc (MAX_RTX_HASH_TABLE * sizeof (struct pool_sym *))); + bzero (const_rtx_hash_table, + MAX_RTX_HASH_TABLE * sizeof (struct constant_descriptor *)); + bzero (const_rtx_sym_hash_table, + MAX_RTX_HASH_TABLE * sizeof (struct pool_sym *)); + + first_pool = last_pool = 0; + pool_offset = 0; +} + +/* Save and restore it for a nested function. */ + +void +save_varasm_status (p) + struct function *p; +{ + p->const_rtx_hash_table = const_rtx_hash_table; + p->const_rtx_sym_hash_table = const_rtx_sym_hash_table; + p->first_pool = first_pool; + p->last_pool = last_pool; + p->pool_offset = pool_offset; +} + +void +restore_varasm_status (p) + struct function *p; +{ + const_rtx_hash_table = p->const_rtx_hash_table; + const_rtx_sym_hash_table = p->const_rtx_sym_hash_table; + first_pool = p->first_pool; + last_pool = p->last_pool; + pool_offset = p->pool_offset; +} + +enum kind { RTX_DOUBLE, RTX_INT }; + +struct rtx_const +{ +#ifdef ONLY_INT_FIELDS + unsigned int kind : 16; + unsigned int mode : 16; +#else + enum kind kind : 16; + enum machine_mode mode : 16; +#endif + union { + union real_extract du; + struct addr_const addr; + } un; +}; + +/* Express an rtx for a constant integer (perhaps symbolic) + as the sum of a symbol or label plus an explicit integer. + They are stored into VALUE. */ + +static void +decode_rtx_const (mode, x, value) + enum machine_mode mode; + rtx x; + struct rtx_const *value; +{ + /* Clear the whole structure, including any gaps. */ + + { + int *p = (int *) value; + int *end = (int *) (value + 1); + while (p < end) + *p++ = 0; + } + + value->kind = RTX_INT; /* Most usual kind. */ + value->mode = mode; + + switch (GET_CODE (x)) + { + case CONST_DOUBLE: + value->kind = RTX_DOUBLE; + value->mode = GET_MODE (x); + bcopy (&CONST_DOUBLE_LOW (x), &value->un.du, sizeof value->un.du); + break; + + case CONST_INT: + value->un.addr.offset = INTVAL (x); + break; + + case SYMBOL_REF: + case LABEL_REF: + case PC: + value->un.addr.base = x; + break; + + case CONST: + x = XEXP (x, 0); + if (GET_CODE (x) == PLUS) + { + value->un.addr.base = XEXP (x, 0); + if (GET_CODE (XEXP (x, 1)) != CONST_INT) + abort (); + value->un.addr.offset = INTVAL (XEXP (x, 1)); + } + else if (GET_CODE (x) == MINUS) + { + value->un.addr.base = XEXP (x, 0); + if (GET_CODE (XEXP (x, 1)) != CONST_INT) + abort (); + value->un.addr.offset = - INTVAL (XEXP (x, 1)); + } + else + abort (); + break; + + default: + abort (); + } + + if (value->kind == RTX_INT && value->un.addr.base != 0) + switch (GET_CODE (value->un.addr.base)) + { + case SYMBOL_REF: + case LABEL_REF: + /* Use the string's address, not the SYMBOL_REF's address, + for the sake of addresses of library routines. + For a LABEL_REF, compare labels. */ + value->un.addr.base = XEXP (value->un.addr.base, 0); + } +} + +/* Given a MINUS expression, simplify it if both sides + include the same symbol. */ + +rtx +simplify_subtraction (x) + rtx x; +{ + struct rtx_const val0, val1; + + decode_rtx_const (GET_MODE (x), XEXP (x, 0), &val0); + decode_rtx_const (GET_MODE (x), XEXP (x, 1), &val1); + + if (val0.un.addr.base == val1.un.addr.base) + return GEN_INT (val0.un.addr.offset - val1.un.addr.offset); + return x; +} + +/* Compute a hash code for a constant RTL expression. */ + +int +const_hash_rtx (mode, x) + enum machine_mode mode; + rtx x; +{ + register int hi, i; + + struct rtx_const value; + decode_rtx_const (mode, x, &value); + + /* Compute hashing function */ + hi = 0; + for (i = 0; i < sizeof value / sizeof (int); i++) + hi += ((int *) &value)[i]; + + hi &= (1 << HASHBITS) - 1; + hi %= MAX_RTX_HASH_TABLE; + return hi; +} + +/* Compare a constant rtl object X with a constant-descriptor DESC. + Return 1 if DESC describes a constant with the same value as X. */ + +static int +compare_constant_rtx (mode, x, desc) + enum machine_mode mode; + rtx x; + struct constant_descriptor *desc; +{ + register int *p = (int *) desc->contents; + register int *strp; + register int len; + struct rtx_const value; + + decode_rtx_const (mode, x, &value); + strp = (int *) &value; + len = sizeof value / sizeof (int); + + /* Compare constant contents. */ + while (--len >= 0) + if (*p++ != *strp++) + return 0; + + return 1; +} + +/* Construct a constant descriptor for the rtl-expression X. + It is up to the caller to enter the descriptor in the hash table. */ + +static struct constant_descriptor * +record_constant_rtx (mode, x) + enum machine_mode mode; + rtx x; +{ + struct constant_descriptor *ptr; + char *label; + struct rtx_const value; + + decode_rtx_const (mode, x, &value); + + obstack_grow (current_obstack, &ptr, sizeof ptr); + obstack_grow (current_obstack, &label, sizeof label); + + /* Record constant contents. */ + obstack_grow (current_obstack, &value, sizeof value); + + return (struct constant_descriptor *) obstack_finish (current_obstack); +} + +/* Given a constant rtx X, make (or find) a memory constant for its value + and return a MEM rtx to refer to it in memory. */ + +rtx +force_const_mem (mode, x) + enum machine_mode mode; + rtx x; +{ + register int hash; + register struct constant_descriptor *desc; + char label[256]; + char *found = 0; + rtx def; + + /* If we want this CONST_DOUBLE in the same mode as it is in memory + (this will always be true for floating CONST_DOUBLEs that have been + placed in memory, but not for VOIDmode (integer) CONST_DOUBLEs), + use the previous copy. Otherwise, make a new one. Note that in + the unlikely event that this same CONST_DOUBLE is used in two different + modes in an alternating fashion, we will allocate a lot of different + memory locations, but this should be extremely rare. */ + + /* Don't use CONST_DOUBLE_MEM in a nested function. + Nested functions have their own constant pools, + so they can't share the same values in CONST_DOUBLE_MEM + with the containing function. */ + if (outer_function_chain == 0) + if (GET_CODE (x) == CONST_DOUBLE + && GET_CODE (CONST_DOUBLE_MEM (x)) == MEM + && GET_MODE (CONST_DOUBLE_MEM (x)) == mode) + return CONST_DOUBLE_MEM (x); + + /* Compute hash code of X. Search the descriptors for that hash code + to see if any of them describes X. If yes, the descriptor records + the label number already assigned. */ + + hash = const_hash_rtx (mode, x); + + for (desc = const_rtx_hash_table[hash]; desc; desc = desc->next) + if (compare_constant_rtx (mode, x, desc)) + { + found = desc->label; + break; + } + + if (found == 0) + { + register struct pool_constant *pool; + register struct pool_sym *sym; + int align; + + /* No constant equal to X is known to have been output. + Make a constant descriptor to enter X in the hash table. + Assign the label number and record it in the descriptor for + future calls to this function to find. */ + + desc = record_constant_rtx (mode, x); + desc->next = const_rtx_hash_table[hash]; + const_rtx_hash_table[hash] = desc; + + /* Align the location counter as required by EXP's data type. */ + align = (mode == VOIDmode) ? UNITS_PER_WORD : GET_MODE_SIZE (mode); + if (align > BIGGEST_ALIGNMENT / BITS_PER_UNIT) + align = BIGGEST_ALIGNMENT / BITS_PER_UNIT; + + pool_offset += align - 1; + pool_offset &= ~ (align - 1); + + /* Allocate a pool constant descriptor, fill it in, and chain it in. */ + + pool = (struct pool_constant *) oballoc (sizeof (struct pool_constant)); + pool->desc = desc; + pool->constant = x; + pool->mode = mode; + pool->labelno = const_labelno; + pool->align = align; + pool->offset = pool_offset; + pool->next = 0; + + if (last_pool == 0) + first_pool = pool; + else + last_pool->next = pool; + + last_pool = pool; + pool_offset += GET_MODE_SIZE (mode); + + /* Create a string containing the label name, in LABEL. */ + ASM_GENERATE_INTERNAL_LABEL (label, "LC", const_labelno); + + ++const_labelno; + + desc->label = found + = (char *) obstack_copy0 (saveable_obstack, label, strlen (label)); + + /* Add label to symbol hash table. */ + hash = SYMHASH (found); + sym = (struct pool_sym *) oballoc (sizeof (struct pool_sym)); + sym->label = found; + sym->pool = pool; + sym->next = const_rtx_sym_hash_table[hash]; + const_rtx_sym_hash_table[hash] = sym; + } + + /* We have a symbol name; construct the SYMBOL_REF and the MEM. */ + + def = gen_rtx (MEM, mode, gen_rtx (SYMBOL_REF, Pmode, found)); + + RTX_UNCHANGING_P (def) = 1; + /* Mark the symbol_ref as belonging to this constants pool. */ + CONSTANT_POOL_ADDRESS_P (XEXP (def, 0)) = 1; + current_function_uses_const_pool = 1; + + if (outer_function_chain == 0) + if (GET_CODE (x) == CONST_DOUBLE) + { + if (CONST_DOUBLE_MEM (x) == cc0_rtx) + { + CONST_DOUBLE_CHAIN (x) = const_double_chain; + const_double_chain = x; + } + CONST_DOUBLE_MEM (x) = def; + } + + return def; +} + +/* Given a SYMBOL_REF with CONSTANT_POOL_ADDRESS_P true, return a pointer to + the corresponding pool_constant structure. */ + +static struct pool_constant * +find_pool_constant (addr) + rtx addr; +{ + struct pool_sym *sym; + char *label = XSTR (addr, 0); + + for (sym = const_rtx_sym_hash_table[SYMHASH (label)]; sym; sym = sym->next) + if (sym->label == label) + return sym->pool; + + abort (); +} + +/* Given a constant pool SYMBOL_REF, return the corresponding constant. */ + +rtx +get_pool_constant (addr) + rtx addr; +{ + return (find_pool_constant (addr))->constant; +} + +/* Similar, return the mode. */ + +enum machine_mode +get_pool_mode (addr) + rtx addr; +{ + return (find_pool_constant (addr))->mode; +} + +/* Similar, return the offset in the constant pool. */ + +int +get_pool_offset (addr) + rtx addr; +{ + return (find_pool_constant (addr))->offset; +} + +/* Return the size of the constant pool. */ + +int +get_pool_size () +{ + return pool_offset; +} + +/* Write all the constants in the constant pool. */ + +void +output_constant_pool (fnname, fndecl) + char *fnname; + tree fndecl; +{ + struct pool_constant *pool; + rtx x; + union real_extract u; + +#ifdef ASM_OUTPUT_POOL_PROLOGUE + ASM_OUTPUT_POOL_PROLOGUE (asm_out_file, fnname, fndecl, pool_offset); +#endif + + for (pool = first_pool; pool; pool = pool->next) + { + x = pool->constant; + + /* See if X is a LABEL_REF (or a CONST referring to a LABEL_REF) + whose CODE_LABEL has been deleted. This can occur if a jump table + is eliminated by optimization. If so, write a constant of zero + instead. Note that this can also happen by turning the + CODE_LABEL into a NOTE. */ + if (((GET_CODE (x) == LABEL_REF + && (INSN_DELETED_P (XEXP (x, 0)) + || GET_CODE (XEXP (x, 0)) == NOTE))) + || (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF + && (INSN_DELETED_P (XEXP (XEXP (XEXP (x, 0), 0), 0)) + || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == NOTE))) + x = const0_rtx; + + /* First switch to correct section. */ +#ifdef SELECT_RTX_SECTION + SELECT_RTX_SECTION (pool->mode, x); +#else + readonly_data_section (); +#endif + +#ifdef ASM_OUTPUT_SPECIAL_POOL_ENTRY + ASM_OUTPUT_SPECIAL_POOL_ENTRY (asm_out_file, x, pool->mode, + pool->align, pool->labelno, done); +#endif + + if (pool->align > 1) + ASM_OUTPUT_ALIGN (asm_out_file, exact_log2 (pool->align)); + + /* Output the label. */ + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LC", pool->labelno); + + /* Output the value of the constant itself. */ + switch (GET_MODE_CLASS (pool->mode)) + { + case MODE_FLOAT: + if (GET_CODE (x) != CONST_DOUBLE) + abort (); + + bcopy (&CONST_DOUBLE_LOW (x), &u, sizeof u); + assemble_real (u.d, pool->mode); + break; + + case MODE_INT: + case MODE_PARTIAL_INT: + assemble_integer (x, GET_MODE_SIZE (pool->mode), 1); + break; + + default: + abort (); + } + + done: ; + } + + /* Done with this pool. */ + first_pool = last_pool = 0; +} + +/* Find all the constants whose addresses are referenced inside of EXP, + and make sure assembler code with a label has been output for each one. + Indicate whether an ADDR_EXPR has been encountered. */ + +int +output_addressed_constants (exp) + tree exp; +{ + int reloc = 0; + + switch (TREE_CODE (exp)) + { + case ADDR_EXPR: + { + register tree constant = TREE_OPERAND (exp, 0); + + while (TREE_CODE (constant) == COMPONENT_REF) + { + constant = TREE_OPERAND (constant, 0); + } + + if (TREE_CODE_CLASS (TREE_CODE (constant)) == 'c' + || TREE_CODE (constant) == CONSTRUCTOR) + /* No need to do anything here + for addresses of variables or functions. */ + output_constant_def (constant); + } + reloc = 1; + break; + + case PLUS_EXPR: + case MINUS_EXPR: + reloc = output_addressed_constants (TREE_OPERAND (exp, 0)); + reloc |= output_addressed_constants (TREE_OPERAND (exp, 1)); + break; + + case NOP_EXPR: + case CONVERT_EXPR: + case NON_LVALUE_EXPR: + reloc = output_addressed_constants (TREE_OPERAND (exp, 0)); + break; + + case CONSTRUCTOR: + { + register tree link; + for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link)) + if (TREE_VALUE (link) != 0) + reloc |= output_addressed_constants (TREE_VALUE (link)); + } + break; + + case ERROR_MARK: + break; + } + return reloc; +} + +/* Output assembler code for constant EXP to FILE, with no label. + This includes the pseudo-op such as ".int" or ".byte", and a newline. + Assumes output_addressed_constants has been done on EXP already. + + Generate exactly SIZE bytes of assembler data, padding at the end + with zeros if necessary. SIZE must always be specified. + + SIZE is important for structure constructors, + since trailing members may have been omitted from the constructor. + It is also important for initialization of arrays from string constants + since the full length of the string constant might not be wanted. + It is also needed for initialization of unions, where the initializer's + type is just one member, and that may not be as long as the union. + + There a case in which we would fail to output exactly SIZE bytes: + for a structure constructor that wants to produce more than SIZE bytes. + But such constructors will never be generated for any possible input. */ + +void +output_constant (exp, size) + register tree exp; + register int size; +{ + register enum tree_code code = TREE_CODE (TREE_TYPE (exp)); + rtx x; + + if (size == 0) + return; + + /* Allow a constructor with no elements for any data type. + This means to fill the space with zeros. */ + if (TREE_CODE (exp) == CONSTRUCTOR && CONSTRUCTOR_ELTS (exp) == 0) + { + assemble_zeros (size); + return; + } + + /* Eliminate the NOP_EXPR that makes a cast not be an lvalue. + That way we get the constant (we hope) inside it. */ + if (TREE_CODE (exp) == NOP_EXPR + && TREE_TYPE (exp) == TREE_TYPE (TREE_OPERAND (exp, 0))) + exp = TREE_OPERAND (exp, 0); + + switch (code) + { + case CHAR_TYPE: + case BOOLEAN_TYPE: + case INTEGER_TYPE: + case ENUMERAL_TYPE: + case POINTER_TYPE: + case REFERENCE_TYPE: + /* ??? What about (int)((float)(int)&foo + 4) */ + while (TREE_CODE (exp) == NOP_EXPR || TREE_CODE (exp) == CONVERT_EXPR + || TREE_CODE (exp) == NON_LVALUE_EXPR) + exp = TREE_OPERAND (exp, 0); + + if (! assemble_integer (expand_expr (exp, NULL_RTX, VOIDmode, + EXPAND_INITIALIZER), + size, 0)) + error ("initializer for integer value is too complicated"); + size = 0; + break; + + case REAL_TYPE: + if (TREE_CODE (exp) != REAL_CST) + error ("initializer for floating value is not a floating constant"); + + assemble_real (TREE_REAL_CST (exp), + mode_for_size (size * BITS_PER_UNIT, MODE_FLOAT, 0)); + size = 0; + break; + + case COMPLEX_TYPE: + output_constant (TREE_REALPART (exp), size / 2); + output_constant (TREE_IMAGPART (exp), size / 2); + size -= (size / 2) * 2; + break; + + case ARRAY_TYPE: + if (TREE_CODE (exp) == CONSTRUCTOR) + { + output_constructor (exp, size); + return; + } + else if (TREE_CODE (exp) == STRING_CST) + { + int excess = 0; + + if (size > TREE_STRING_LENGTH (exp)) + { + excess = size - TREE_STRING_LENGTH (exp); + size = TREE_STRING_LENGTH (exp); + } + + assemble_string (TREE_STRING_POINTER (exp), size); + size = excess; + } + else + abort (); + break; + + case RECORD_TYPE: + case UNION_TYPE: + if (TREE_CODE (exp) == CONSTRUCTOR) + output_constructor (exp, size); + else + abort (); + return; + } + + if (size > 0) + assemble_zeros (size); +} + +/* Subroutine of output_constant, used for CONSTRUCTORs + (aggregate constants). + Generate at least SIZE bytes, padding if necessary. */ + +void +output_constructor (exp, size) + tree exp; + int size; +{ + register tree link, field = 0; + /* Number of bytes output or skipped so far. + In other words, current position within the constructor. */ + int total_bytes = 0; + /* Non-zero means BYTE contains part of a byte, to be output. */ + int byte_buffer_in_use = 0; + register int byte; + + if (HOST_BITS_PER_WIDE_INT < BITS_PER_UNIT) + abort (); + + if (TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE) + field = TYPE_FIELDS (TREE_TYPE (exp)); + + /* As LINK goes through the elements of the constant, + FIELD goes through the structure fields, if the constant is a structure. + if the constant is a union, then we override this, + by getting the field from the TREE_LIST element. + But the constant could also be an array. Then FIELD is zero. */ + for (link = CONSTRUCTOR_ELTS (exp); + link; + link = TREE_CHAIN (link), + field = field ? TREE_CHAIN (field) : 0) + { + tree val = TREE_VALUE (link); + /* the element in a union constructor specifies the proper field. */ + if (TREE_PURPOSE (link) != 0) + field = TREE_PURPOSE (link); + + /* Eliminate the marker that makes a cast not be an lvalue. */ + if (val != 0) + STRIP_NOPS (val); + + if (field == 0 || !DECL_BIT_FIELD (field)) + { + register int fieldsize; + /* Since this structure is static, + we know the positions are constant. */ + int bitpos = (field ? (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) + / BITS_PER_UNIT) + : 0); + + /* An element that is not a bit-field. + Output any buffered-up bit-fields preceding it. */ + if (byte_buffer_in_use) + { + ASM_OUTPUT_BYTE (asm_out_file, byte); + total_bytes++; + byte_buffer_in_use = 0; + } + + /* Advance to offset of this element. + Note no alignment needed in an array, since that is guaranteed + if each element has the proper size. */ + if (field != 0 && bitpos != total_bytes) + { + assemble_zeros (bitpos - total_bytes); + total_bytes = bitpos; + } + + /* Determine size this element should occupy. */ + if (field) + { + if (TREE_CODE (DECL_SIZE (field)) != INTEGER_CST) + abort (); + if (TREE_INT_CST_LOW (DECL_SIZE (field)) > 100000) + { + /* This avoids overflow trouble. */ + tree size_tree = size_binop (CEIL_DIV_EXPR, + DECL_SIZE (field), + size_int (BITS_PER_UNIT)); + fieldsize = TREE_INT_CST_LOW (size_tree); + } + else + { + fieldsize = TREE_INT_CST_LOW (DECL_SIZE (field)); + fieldsize = (fieldsize + BITS_PER_UNIT - 1) / BITS_PER_UNIT; + } + } + else + fieldsize = int_size_in_bytes (TREE_TYPE (TREE_TYPE (exp))); + + /* Output the element's initial value. */ + if (val == 0) + assemble_zeros (fieldsize); + else + output_constant (val, fieldsize); + + /* Count its size. */ + total_bytes += fieldsize; + } + else if (val != 0 && TREE_CODE (val) != INTEGER_CST) + error ("invalid initial value for member `%s'", + IDENTIFIER_POINTER (DECL_NAME (field))); + else + { + /* Element that is a bit-field. */ + + int next_offset = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); + int end_offset + = (next_offset + TREE_INT_CST_LOW (DECL_SIZE (field))); + + if (val == 0) + val = integer_zero_node; + + /* If this field does not start in this (or, next) byte, + skip some bytes. */ + if (next_offset / BITS_PER_UNIT != total_bytes) + { + /* Output remnant of any bit field in previous bytes. */ + if (byte_buffer_in_use) + { + ASM_OUTPUT_BYTE (asm_out_file, byte); + total_bytes++; + byte_buffer_in_use = 0; + } + + /* If still not at proper byte, advance to there. */ + if (next_offset / BITS_PER_UNIT != total_bytes) + { + assemble_zeros (next_offset / BITS_PER_UNIT - total_bytes); + total_bytes = next_offset / BITS_PER_UNIT; + } + } + + if (! byte_buffer_in_use) + byte = 0; + + /* We must split the element into pieces that fall within + separate bytes, and combine each byte with previous or + following bit-fields. */ + + /* next_offset is the offset n fbits from the beginning of + the structure to the next bit of this element to be processed. + end_offset is the offset of the first bit past the end of + this element. */ + while (next_offset < end_offset) + { + int this_time; + int shift, value; + int next_byte = next_offset / BITS_PER_UNIT; + int next_bit = next_offset % BITS_PER_UNIT; + + /* Advance from byte to byte + within this element when necessary. */ + while (next_byte != total_bytes) + { + ASM_OUTPUT_BYTE (asm_out_file, byte); + total_bytes++; + byte = 0; + } + + /* Number of bits we can process at once + (all part of the same byte). */ + this_time = MIN (end_offset - next_offset, + BITS_PER_UNIT - next_bit); +#if BYTES_BIG_ENDIAN + /* On big-endian machine, take the most significant bits + first (of the bits that are significant) + and put them into bytes from the most significant end. */ + shift = end_offset - next_offset - this_time; + /* Don't try to take a bunch of bits that cross + the word boundary in the INTEGER_CST. */ + if (shift < HOST_BITS_PER_WIDE_INT + && shift + this_time > HOST_BITS_PER_WIDE_INT) + { + this_time -= (HOST_BITS_PER_WIDE_INT - shift); + shift = HOST_BITS_PER_WIDE_INT; + } + + /* Now get the bits from the appropriate constant word. */ + if (shift < HOST_BITS_PER_WIDE_INT) + { + value = TREE_INT_CST_LOW (val); + } + else if (shift < 2 * HOST_BITS_PER_WIDE_INT) + { + value = TREE_INT_CST_HIGH (val); + shift -= HOST_BITS_PER_WIDE_INT; + } + else + abort (); + byte |= (((value >> shift) + & (((HOST_WIDE_INT) 1 << this_time) - 1)) + << (BITS_PER_UNIT - this_time - next_bit)); +#else + /* On little-endian machines, + take first the least significant bits of the value + and pack them starting at the least significant + bits of the bytes. */ + shift = (next_offset + - TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))); + /* Don't try to take a bunch of bits that cross + the word boundary in the INTEGER_CST. */ + if (shift < HOST_BITS_PER_WIDE_INT + && shift + this_time > HOST_BITS_PER_WIDE_INT) + { + this_time -= (HOST_BITS_PER_WIDE_INT - shift); + shift = HOST_BITS_PER_WIDE_INT; + } + + /* Now get the bits from the appropriate constant word. */ + if (shift < HOST_BITS_PER_INT) + value = TREE_INT_CST_LOW (val); + else if (shift < 2 * HOST_BITS_PER_WIDE_INT) + { + value = TREE_INT_CST_HIGH (val); + shift -= HOST_BITS_PER_WIDE_INT; + } + else + abort (); + byte |= ((value >> shift) + & (((HOST_WIDE_INT) 1 << this_time) - 1)) << next_bit; +#endif + next_offset += this_time; + byte_buffer_in_use = 1; + } + } + } + if (byte_buffer_in_use) + { + ASM_OUTPUT_BYTE (asm_out_file, byte); + total_bytes++; + } + if (total_bytes < size) + assemble_zeros (size - total_bytes); +} diff --git a/gnu/usr.bin/cc/lib/version.c b/gnu/usr.bin/cc/lib/version.c new file mode 100644 index 000000000000..47bd2c078760 --- /dev/null +++ b/gnu/usr.bin/cc/lib/version.c @@ -0,0 +1 @@ +char *version_string = "2.4.5"; diff --git a/gnu/usr.bin/cc/lib/xcoffout.c b/gnu/usr.bin/cc/lib/xcoffout.c new file mode 100644 index 000000000000..568d443a9e82 --- /dev/null +++ b/gnu/usr.bin/cc/lib/xcoffout.c @@ -0,0 +1,484 @@ +/* Output xcoff-format symbol table information from GNU compiler. + Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* Output xcoff-format symbol table data. The main functionality is contained + in dbxout.c. This file implements the sdbout-like parts of the xcoff + interface. Many functions are very similar to their counterparts in + sdbout.c. */ + +/* Include this first, because it may define MIN and MAX. */ +#include + +#include "config.h" +#include "tree.h" +#include "rtl.h" +#include "flags.h" + +#ifdef XCOFF_DEBUGGING_INFO + +/* This defines the C_* storage classes. */ +#include + +#include "xcoffout.h" + +#if defined (USG) || defined (NO_STAB_H) +#include "gstab.h" +#else +#include + +/* This is a GNU extension we need to reference in this file. */ +#ifndef N_CATCH +#define N_CATCH 0x54 +#endif +#endif + +/* Line number of beginning of current function, minus one. + Negative means not in a function or not using xcoff. */ + +int xcoff_begin_function_line = -1; + +/* Name of the current include file. */ + +char *xcoff_current_include_file; + +/* Name of the current function file. This is the file the `.bf' is + emitted from. In case a line is emitted from a different file, + (by including that file of course), then the line number will be + absolute. */ + +char *xcoff_current_function_file; + +/* Names of bss and data sections. These should be unique names for each + compilation unit. */ + +char *xcoff_bss_section_name; +char *xcoff_private_data_section_name; +char *xcoff_read_only_section_name; + +/* Macro definitions used below. */ +/* Ensure we don't output a negative line number. */ +#define MAKE_LINE_SAFE(LINE) \ + if (LINE <= xcoff_begin_function_line) \ + LINE = xcoff_begin_function_line + 1 \ + +#define ASM_OUTPUT_LFB(FILE,LINENUM) \ +{ \ + if (xcoff_begin_function_line == -1) \ + { \ + xcoff_begin_function_line = (LINENUM) - 1;\ + fprintf (FILE, "\t.bf\t%d\n", (LINENUM)); \ + } \ + xcoff_current_function_file \ + = (xcoff_current_include_file \ + ? xcoff_current_include_file : main_input_filename); \ +} + +#define ASM_OUTPUT_LFE(FILE,LINENUM) \ + do { \ + int linenum = LINENUM; \ + MAKE_LINE_SAFE (linenum); \ + fprintf (FILE, "\t.ef\t%d\n", ABS_OR_RELATIVE_LINENO (linenum)); \ + xcoff_begin_function_line = -1; \ + } while (0) + +#define ASM_OUTPUT_LBB(FILE,LINENUM,BLOCKNUM) \ + do { \ + int linenum = LINENUM; \ + MAKE_LINE_SAFE (linenum); \ + fprintf (FILE, "\t.bb\t%d\n", ABS_OR_RELATIVE_LINENO (linenum)); \ + } while (0) + +#define ASM_OUTPUT_LBE(FILE,LINENUM,BLOCKNUM) \ + do { \ + int linenum = LINENUM; \ + MAKE_LINE_SAFE (linenum); \ + fprintf (FILE, "\t.eb\t%d\n", ABS_OR_RELATIVE_LINENO (linenum)); \ + } while (0) + +/* Support routines for XCOFF debugging info. */ + +/* Assign NUMBER as the stabx type number for the type described by NAME. + Search all decls in the list SYMS to find the type NAME. */ + +static void +assign_type_number (syms, name, number) + tree syms; + char *name; + int number; +{ + tree decl; + + for (decl = syms; decl; decl = TREE_CHAIN (decl)) + if (DECL_NAME (decl) + && strcmp (IDENTIFIER_POINTER (DECL_NAME (decl)), name) == 0) + { + TREE_ASM_WRITTEN (decl) = 1; + TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = number; + } +} + +/* Setup gcc primitive types to use the XCOFF built-in type numbers where + possible. */ + +void +xcoff_output_standard_types (syms) + tree syms; +{ + /* Handle built-in C types here. */ + + assign_type_number (syms, "int", -1); + assign_type_number (syms, "char", -2); + assign_type_number (syms, "short int", -3); + assign_type_number (syms, "long int", -4); + assign_type_number (syms, "unsigned char", -5); + assign_type_number (syms, "signed char", -6); + assign_type_number (syms, "short unsigned int", -7); + assign_type_number (syms, "unsigned int", -8); + /* No such type "unsigned". */ + assign_type_number (syms, "long unsigned int", -10); + assign_type_number (syms, "void", -11); + assign_type_number (syms, "float", -12); + assign_type_number (syms, "double", -13); + assign_type_number (syms, "long double", -14); + /* Pascal and Fortran types run from -15 to -29. */ + /* No such type "wchar". */ + + /* "long long int", and "long long unsigned int", are not handled here, + because there are no predefined types that match them. */ + + /* ??? Should also handle built-in C++ and Obj-C types. There perhaps + aren't any that C doesn't already have. */ +} + +/* Print an error message for unrecognized stab codes. */ + +#define UNKNOWN_STAB(STR) \ + do { \ + fprintf(stderr, "Error, unknown stab %s: : 0x%x\n", STR, stab); \ + fflush (stderr); \ + } while (0) + +/* Conversion routine from BSD stabs to AIX storage classes. */ + +int +stab_to_sclass (stab) + int stab; +{ + switch (stab) + { + case N_GSYM: + return C_GSYM; + + case N_FNAME: + UNKNOWN_STAB ("N_FNAME"); + abort(); + + case N_FUN: + return C_FUN; + + case N_STSYM: + case N_LCSYM: + return C_STSYM; + +#ifdef N_MAIN + case N_MAIN: + UNKNOWN_STAB ("N_MAIN"); + abort (); +#endif + + case N_RSYM: + return C_RSYM; + + case N_SSYM: + UNKNOWN_STAB ("N_SSYM"); + abort (); + + case N_RPSYM: + return C_RPSYM; + + case N_PSYM: + return C_PSYM; + case N_LSYM: + return C_LSYM; + case N_DECL: + return C_DECL; + case N_ENTRY: + return C_ENTRY; + + case N_SO: + UNKNOWN_STAB ("N_SO"); + abort (); + + case N_SOL: + UNKNOWN_STAB ("N_SOL"); + abort (); + + case N_SLINE: + UNKNOWN_STAB ("N_SLINE"); + abort (); + +#ifdef N_DSLINE + case N_DSLINE: + UNKNOWN_STAB ("N_DSLINE"); + abort (); +#endif + +#ifdef N_BSLINE + case N_BSLINE: + UNKNOWN_STAB ("N_BSLINE"); + abort (); +#endif +#if 0 + /* This has the same value as N_BSLINE. */ + case N_BROWS: + UNKNOWN_STAB ("N_BROWS"); + abort (); +#endif + +#ifdef N_BINCL + case N_BINCL: + UNKNOWN_STAB ("N_BINCL"); + abort (); +#endif + +#ifdef N_EINCL + case N_EINCL: + UNKNOWN_STAB ("N_EINCL"); + abort (); +#endif + +#ifdef N_EXCL + case N_EXCL: + UNKNOWN_STAB ("N_EXCL"); + abort (); +#endif + + case N_LBRAC: + UNKNOWN_STAB ("N_LBRAC"); + abort (); + + case N_RBRAC: + UNKNOWN_STAB ("N_RBRAC"); + abort (); + + case N_BCOMM: + return C_BCOMM; + case N_ECOMM: + return C_ECOMM; + case N_ECOML: + return C_ECOML; + + case N_LENG: + UNKNOWN_STAB ("N_LENG"); + abort (); + + case N_PC: + UNKNOWN_STAB ("N_PC"); + abort (); + +#ifdef N_M2C + case N_M2C: + UNKNOWN_STAB ("N_M2C"); + abort (); +#endif + +#ifdef N_SCOPE + case N_SCOPE: + UNKNOWN_STAB ("N_SCOPE"); + abort (); +#endif + + case N_CATCH: + UNKNOWN_STAB ("N_CATCH"); + abort (); + + default: + UNKNOWN_STAB ("default"); + abort (); + } +} + +/* In XCOFF, we have to have this .bf before the function prologue. + Rely on the value of `dbx_begin_function_line' not to duplicate .bf. */ + +void +xcoffout_output_first_source_line (file, last_linenum) + FILE *file; + int last_linenum; +{ + ASM_OUTPUT_LFB (file, last_linenum); + dbxout_parms (DECL_ARGUMENTS (current_function_decl)); + ASM_OUTPUT_SOURCE_LINE (file, last_linenum); +} + +/* Output the symbols defined in block number DO_BLOCK. + Set NEXT_BLOCK_NUMBER to 0 before calling. + + This function works by walking the tree structure of blocks, + counting blocks until it finds the desired block. */ + +static int do_block = 0; + +static int next_block_number; + +static void +xcoffout_block (block, depth, args) + register tree block; + int depth; + tree args; +{ + while (block) + { + /* Ignore blocks never expanded or otherwise marked as real. */ + if (TREE_USED (block)) + { + /* When we reach the specified block, output its symbols. */ + if (next_block_number == do_block) + { + /* Output the syms of the block. */ + if (debug_info_level != DINFO_LEVEL_TERSE || depth == 0) + dbxout_syms (BLOCK_VARS (block)); + if (args) + dbxout_reg_parms (args); + + /* We are now done with the block. Don't go to inner blocks. */ + return; + } + /* If we are past the specified block, stop the scan. */ + else if (next_block_number >= do_block) + return; + + next_block_number++; + + /* Output the subblocks. */ + xcoffout_block (BLOCK_SUBBLOCKS (block), depth + 1, NULL_TREE); + } + block = BLOCK_CHAIN (block); + } +} + +/* Describe the beginning of an internal block within a function. + Also output descriptions of variables defined in this block. + + N is the number of the block, by order of beginning, counting from 1, + and not counting the outermost (function top-level) block. + The blocks match the BLOCKs in DECL_INITIAL (current_function_decl), + if the count starts at 0 for the outermost one. */ + +void +xcoffout_begin_block (file, line, n) + FILE *file; + int line; + int n; +{ + tree decl = current_function_decl; + + ASM_OUTPUT_LBB (file, line, n); + + do_block = n; + next_block_number = 0; + xcoffout_block (DECL_INITIAL (decl), 0, DECL_ARGUMENTS (decl)); +} + +/* Describe the end line-number of an internal block within a function. */ + +void +xcoffout_end_block (file, line, n) + FILE *file; + int line; + int n; +{ + ASM_OUTPUT_LBE (file, line, n); +} + +/* Called at beginning of function (before prologue). + Declare function as needed for debugging. */ + +void +xcoffout_declare_function (file, decl, name) + FILE *file; + tree decl; + char *name; +{ + char *n = name; + int i; + + for (i = 0; name[i]; ++i) + { + if (name[i] == '[') + { + n = (char *) alloca (i + 1); + strncpy (n, name, i); + n[i] = '\0'; + break; + } + } + + /* Any pending .bi or .ei must occur before the .function psuedo op. + Otherwise debuggers will think that the function is in the previous + file and/or at the wrong line number. */ + dbxout_source_file (file, DECL_SOURCE_FILE (decl)); + dbxout_symbol (decl, 0); + fprintf (file, "\t.function .%s,.%s,16,044,FE..%s-.%s\n", n, n, n, n); +} + +/* Called at beginning of function body (after prologue). + Record the function's starting line number, so we can output + relative line numbers for the other lines. + Record the file name that this function is contained in. */ + +void +xcoffout_begin_function (file, last_linenum) + FILE *file; + int last_linenum; +{ + ASM_OUTPUT_LFB (file, last_linenum); +} + +/* Called at end of function (before epilogue). + Describe end of outermost block. */ + +void +xcoffout_end_function (file, last_linenum) + FILE *file; + int last_linenum; +{ + ASM_OUTPUT_LFE (file, last_linenum); +} + +/* Output xcoff info for the absolute end of a function. + Called after the epilogue is output. */ + +void +xcoffout_end_epilogue (file) + FILE *file; +{ + /* We need to pass the correct function size to .function, otherwise, + the xas assembler can't figure out the correct size for the function + aux entry. So, we emit a label after the last instruction which can + be used by the .function pseudo op to calculate the function size. */ + + char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + if (*fname == '*') + ++fname; + fprintf (file, "FE.."); + ASM_OUTPUT_LABEL (file, fname); +} +#endif /* XCOFF_DEBUGGING_INFO */ -- cgit v1.3