From 49011b52fcba02a6051957b84705159f52fae4e4 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Thu, 7 Oct 2010 16:32:35 +0000 Subject: Vendor import of llvm 2.8 release: http://llvm.org/svn/llvm-project/llvm/tags/RELEASE_28@115866 Approved by: rpaulo (mentor) --- lib/Target/ARM/ARMBaseInstrInfo.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'lib/Target/ARM') diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 3a8bebe0dd24..e4f10f93fb74 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1389,7 +1389,8 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const { // Check that CPSR isn't set between the comparison instruction and the one we // want to change. - MachineBasicBlock::const_iterator I = CmpInstr, E = MI; + MachineBasicBlock::const_iterator I = CmpInstr, E = MI, + B = MI->getParent()->begin(); --I; for (; I != E; --I) { const MachineInstr &Instr = *I; @@ -1403,6 +1404,10 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const { if (MO.getReg() == ARM::CPSR) return false; } + + if (I == B) + // The 'and' is below the comparison instruction. + return false; } // Set the "zero" bit in CPSR. -- cgit v1.2.3