From 71d5a2540a98c81f5bcaeb48805e0e2881f530ef Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Sun, 16 Apr 2017 16:01:22 +0000 Subject: Vendor import of llvm trunk r300422: https://llvm.org/svn/llvm-project/llvm/trunk@300422 --- lib/Target/RISCV/RISCVTargetMachine.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'lib/Target/RISCV/RISCVTargetMachine.cpp') diff --git a/lib/Target/RISCV/RISCVTargetMachine.cpp b/lib/Target/RISCV/RISCVTargetMachine.cpp index afbbe004186e..a20331cd0a3e 100644 --- a/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -32,7 +32,7 @@ static std::string computeDataLayout(const Triple &TT) { return "e-m:e-i64:64-n32:64-S128"; } else { assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); - return "e-m:e-i64:64-n32-S128"; + return "e-m:e-p:32:32-i64:64-n32-S128"; } } @@ -51,7 +51,9 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, CodeGenOpt::Level OL) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), CM, OL), - TLOF(make_unique()) {} + TLOF(make_unique()) { + initAsmInfo(); +} TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { return new TargetPassConfig(this, PM); -- cgit v1.2.3