From 2ffb582a455628a8d21a4c8630d894149aa19bf6 Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Thu, 2 Feb 2017 17:29:15 +0000 Subject: Require Data Layer Active reporting for native PCI-e HotPlug. Some PCI-e bridges report that they support HotPlug in the slot capabilities but do not report support for Data Layer Active events in the link capabilities register. These bridges do not work correctly when HotPlug is used. Further, while the description of HotPlug in the spec does not mention that DL active events are required, the description of the link capabilities register says that DL active is required for HotPlug. Thanks to Dave Baukus for finding that language in the spec. PR: 211699 Submitted by: Dave Baukus Reviewed by: vangyzen MFC after: 3 days --- sys/dev/pci/pci_pci.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'sys/dev/pci/pci_pci.c') diff --git a/sys/dev/pci/pci_pci.c b/sys/dev/pci/pci_pci.c index dedc55a13929..36f6834c4c2a 100644 --- a/sys/dev/pci/pci_pci.c +++ b/sys/dev/pci/pci_pci.c @@ -935,6 +935,8 @@ pcib_probe_hotplug(struct pcib_softc *sc) if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0) return; + if ((sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0) + return; /* * Some devices report that they have an MRL when they actually -- cgit v1.2.3 From 3729014801eafeadaee0291fdad74244ee998a10 Mon Sep 17 00:00:00 2001 From: Eric van Gyzen Date: Sat, 4 Feb 2017 00:34:00 +0000 Subject: PCIe HotPlug: remove tests for DL active link capability As of r313097, the HotPlug code requires the link to support reporting of the data-link status. Remove tests for this capability from code that can now assume its presence. Suggested by: jhb Reviewed by: jhb MFC after: 3 days Sponsored by: Dell EMC Differential Revision: https://reviews.freebsd.org/D9431 --- sys/dev/pci/pci_pci.c | 44 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 25 deletions(-) (limited to 'sys/dev/pci/pci_pci.c') diff --git a/sys/dev/pci/pci_pci.c b/sys/dev/pci/pci_pci.c index 36f6834c4c2a..553b9cb8a28a 100644 --- a/sys/dev/pci/pci_pci.c +++ b/sys/dev/pci/pci_pci.c @@ -918,6 +918,7 @@ static void pcib_probe_hotplug(struct pcib_softc *sc) { device_t dev; + uint32_t link_cap; uint16_t link_sta, slot_sta; if (!pci_enable_pcie_hp) @@ -930,12 +931,12 @@ pcib_probe_hotplug(struct pcib_softc *sc) if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT)) return; - sc->pcie_link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4); if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0) return; - if ((sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0) + link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); + if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0) return; /* @@ -947,8 +948,7 @@ pcib_probe_hotplug(struct pcib_softc *sc) * If there is an open MRL but the Data Link Layer is active, * the MRL is not real. */ - if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0 && - (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) != 0) { + if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) { link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 && @@ -1061,10 +1061,8 @@ pcib_hotplug_present(struct pcib_softc *sc) return (0); /* Require the Data Link Layer to be active. */ - if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) { - if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) - return (0); - } + if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) + return (0); return (-1); } @@ -1121,20 +1119,18 @@ pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, * changed on this interrupt. Stop any scheduled timer if * the Data Link Layer is active. */ - if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) { - if (card_inserted && - !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && - sc->pcie_slot_sta & - (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) { - if (cold) - device_printf(sc->dev, - "Data Link Layer inactive\n"); - else - callout_reset(&sc->pcie_dll_timer, hz, - pcib_pcie_dll_timeout, sc); - } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) - callout_stop(&sc->pcie_dll_timer); - } + if (card_inserted && + !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && + sc->pcie_slot_sta & + (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) { + if (cold) + device_printf(sc->dev, + "Data Link Layer inactive\n"); + else + callout_reset(&sc->pcie_dll_timer, hz, + pcib_pcie_dll_timeout, sc); + } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) + callout_stop(&sc->pcie_dll_timer); pcib_pcie_hotplug_command(sc, val, mask); @@ -1384,7 +1380,7 @@ pcib_setup_hotplug(struct pcib_softc *sc) mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; - val = PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_HPIE; + val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE; if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB) val |= PCIEM_SLOT_CTL_ABPE; if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) @@ -1393,8 +1389,6 @@ pcib_setup_hotplug(struct pcib_softc *sc) val |= PCIEM_SLOT_CTL_MRLSCE; if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) val |= PCIEM_SLOT_CTL_CCIE; - if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) - val |= PCIEM_SLOT_CTL_DLLSCE; /* Turn the attention indicator off. */ if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { -- cgit v1.2.3