From 5a5ac124e1efaf208671f01c46edb15f29ed2a0b Mon Sep 17 00:00:00 2001
From: Dimitry Andric <dim@FreeBSD.org>
Date: Wed, 27 May 2015 18:44:32 +0000
Subject: Vendor import of llvm trunk r238337:
 https://llvm.org/svn/llvm-project/llvm/trunk@238337

---
 test/CodeGen/PowerPC/vec_shuffle_le.ll | 54 +++++++++++++++++-----------------
 1 file changed, 27 insertions(+), 27 deletions(-)

(limited to 'test/CodeGen/PowerPC/vec_shuffle_le.ll')

diff --git a/test/CodeGen/PowerPC/vec_shuffle_le.ll b/test/CodeGen/PowerPC/vec_shuffle_le.ll
index c7fc1c60c5ea..46d451ff1573 100644
--- a/test/CodeGen/PowerPC/vec_shuffle_le.ll
+++ b/test/CodeGen/PowerPC/vec_shuffle_le.ll
@@ -3,8 +3,8 @@
 define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VPKUHUM_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -16,7 +16,7 @@ entry:
 define void @VPKUHUM_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VPKUHUM_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
 ; CHECK: vpkuhum
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -26,8 +26,8 @@ entry:
 define void @VPKUWUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VPKUWUM_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -39,7 +39,7 @@ entry:
 define void @VPKUWUM_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VPKUWUM_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>
 ; CHECK: vpkuwum
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -49,8 +49,8 @@ entry:
 define void @VMRGLB_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGLB_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -62,7 +62,7 @@ entry:
 define void @VMRGLB_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGLB_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
 ; CHECK: vmrglb
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -72,8 +72,8 @@ entry:
 define void @VMRGHB_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGHB_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -85,7 +85,7 @@ entry:
 define void @VMRGHB_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGHB_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
 ; CHECK: vmrghb
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -95,8 +95,8 @@ entry:
 define void @VMRGLH_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGLH_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -108,7 +108,7 @@ entry:
 define void @VMRGLH_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGLH_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7>
 ; CHECK: vmrglh
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -118,8 +118,8 @@ entry:
 define void @VMRGHH_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGHH_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -131,7 +131,7 @@ entry:
 define void @VMRGHH_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGHH_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15>
 ; CHECK: vmrghh
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -141,8 +141,8 @@ entry:
 define void @VMRGLW_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGLW_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -154,7 +154,7 @@ entry:
 define void @VMRGLW_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGLW_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
 ; CHECK: vmrglw
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -164,8 +164,8 @@ entry:
 define void @VMRGHW_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGHW_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -177,7 +177,7 @@ entry:
 define void @VMRGHW_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGHW_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
 ; CHECK: vmrghw
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -187,8 +187,8 @@ entry:
 define void @VSLDOI_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VSLDOI_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -200,7 +200,7 @@ entry:
 define void @VSLDOI_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VSLDOI_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
 ; CHECK: vsldoi
         store <16 x i8> %tmp2, <16 x i8>* %A
-- 
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