From ea5b2dd11c0526581803e7eb58224a2eabf191e6 Mon Sep 17 00:00:00 2001 From: Roman Divacky Date: Wed, 10 Mar 2010 17:45:15 +0000 Subject: Update LLVM to r98164. --- test/CodeGen/XCore/addsub64.ll | 38 +++++++++++++++++-- test/CodeGen/XCore/ladd_lsub_combine.ll | 67 +++++++++++++++++++++++++++++++++ test/CodeGen/XCore/mul64.ll | 39 +++++++++++++++++++ 3 files changed, 141 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/XCore/ladd_lsub_combine.ll create mode 100644 test/CodeGen/XCore/mul64.ll (limited to 'test/CodeGen/XCore') diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll index a1494adfcc46..0432e5e712e6 100644 --- a/test/CodeGen/XCore/addsub64.ll +++ b/test/CodeGen/XCore/addsub64.ll @@ -1,12 +1,44 @@ -; RUN: llc < %s -march=xcore -mcpu=xs1b-generic > %t1.s -; RUN: grep ladd %t1.s | count 2 -; RUN: grep lsub %t1.s | count 2 +; RUN: llc < %s -march=xcore | FileCheck %s define i64 @add64(i64 %a, i64 %b) { %result = add i64 %a, %b ret i64 %result } +; CHECK: add64 +; CHECK: ldc r11, 0 +; CHECK-NEXT: ladd r2, r0, r0, r2, r11 +; CHECK-NEXT: ladd r2, r1, r1, r3, r2 +; CHECK-NEXT: retsp 0 define i64 @sub64(i64 %a, i64 %b) { %result = sub i64 %a, %b ret i64 %result } +; CHECK: sub64 +; CHECK: ldc r11, 0 +; CHECK-NEXT: lsub r2, r0, r0, r2, r11 +; CHECK-NEXT: lsub r2, r1, r1, r3, r2 +; CHECK-NEXT: retsp 0 + +define i64 @maccu(i64 %a, i32 %b, i32 %c) { +entry: + %0 = zext i32 %b to i64 + %1 = zext i32 %c to i64 + %2 = mul i64 %1, %0 + %3 = add i64 %2, %a + ret i64 %3 +} +; CHECK: maccu: +; CHECK: maccu r1, r0, r3, r2 +; CHECK-NEXT: retsp 0 + +define i64 @maccs(i64 %a, i32 %b, i32 %c) { +entry: + %0 = sext i32 %b to i64 + %1 = sext i32 %c to i64 + %2 = mul i64 %1, %0 + %3 = add i64 %2, %a + ret i64 %3 +} +; CHECK: maccs: +; CHECK: maccs r1, r0, r3, r2 +; CHECK-NEXT: retsp 0 diff --git a/test/CodeGen/XCore/ladd_lsub_combine.ll b/test/CodeGen/XCore/ladd_lsub_combine.ll new file mode 100644 index 000000000000..a693ee22291a --- /dev/null +++ b/test/CodeGen/XCore/ladd_lsub_combine.ll @@ -0,0 +1,67 @@ +; RUN: llvm-as < %s | llc -march=xcore | FileCheck %s + +; Only needs one ladd +define i64 @f1(i32 %x, i32 %y) nounwind { +entry: + %0 = zext i32 %x to i64 ; [#uses=1] + %1 = zext i32 %y to i64 ; [#uses=1] + %2 = add i64 %1, %0 ; [#uses=1] + ret i64 %2 +} +; CHECK: f1: +; CHECK: ldc r2, 0 +; CHECK-NEXT: ladd r1, r0, r1, r0, r2 +; CHECK-NEXT: retsp 0 + +; Only needs one lsub and one neg +define i64 @f2(i32 %x, i32 %y) nounwind { +entry: + %0 = zext i32 %x to i64 ; [#uses=1] + %1 = zext i32 %y to i64 ; [#uses=1] + %2 = sub i64 %1, %0 ; [#uses=1] + ret i64 %2 +} +; CHECK: f2: +; CHECK: ldc r2, 0 +; CHECK-NEXT: lsub r1, r0, r1, r0, r2 +; CHECK-NEXT: neg r1, r1 +; CHECK-NEXT: retsp 0 + +; Should compile to one ladd and one add +define i64 @f3(i64 %x, i32 %y) nounwind { +entry: + %0 = zext i32 %y to i64 ; [#uses=1] + %1 = add i64 %x, %0 ; [#uses=1] + ret i64 %1 +} +; CHECK: f3: +; CHECK: ldc r3, 0 +; CHECK-NEXT: ladd r2, r0, r0, r2, r3 +; CHECK-NEXT: add r1, r1, r2 +; CHECK-NEXT: retsp 0 + +; Should compile to one ladd and one add +define i64 @f4(i32 %x, i64 %y) nounwind { +entry: + %0 = zext i32 %x to i64 ; [#uses=1] + %1 = add i64 %0, %y ; [#uses=1] + ret i64 %1 +} +; CHECK: f4: +; CHECK: ldc r3, 0 +; CHECK-NEXT: ladd r1, r0, r0, r1, r3 +; CHECK-NEXT: add r1, r2, r1 +; CHECK-NEXT: retsp 0 + +; Should compile to one lsub and one sub +define i64 @f5(i64 %x, i32 %y) nounwind { +entry: + %0 = zext i32 %y to i64 ; [#uses=1] + %1 = sub i64 %x, %0 ; [#uses=1] + ret i64 %1 +} +; CHECK: f5: +; CHECK: ldc r3, 0 +; CHECK-NEXT: lsub r2, r0, r0, r2, r3 +; CHECK-NEXT: sub r1, r1, r2 +; CHECK-NEXT: retsp 0 diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll new file mode 100644 index 000000000000..329e214d1d23 --- /dev/null +++ b/test/CodeGen/XCore/mul64.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +define i64 @umul_lohi(i32 %a, i32 %b) { +entry: + %0 = zext i32 %a to i64 + %1 = zext i32 %b to i64 + %2 = mul i64 %1, %0 + ret i64 %2 +} +; CHECK: umul_lohi: +; CHECK: ldc r2, 0 +; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2 +; CHECK-NEXT: retsp 0 + +define i64 @smul_lohi(i32 %a, i32 %b) { +entry: + %0 = sext i32 %a to i64 + %1 = sext i32 %b to i64 + %2 = mul i64 %1, %0 + ret i64 %2 +} +; CHECK: smul_lohi: +; CHECK: ldc r2, 0 +; CHECK-NEXT: mov r3, r2 +; CHECK-NEXT: maccs r2, r3, r1, r0 +; CHECK-NEXT: mov r0, r3 +; CHECK-NEXT: mov r1, r2 +; CHECK-NEXT: retsp 0 + +define i64 @mul64(i64 %a, i64 %b) { +entry: + %0 = mul i64 %a, %b + ret i64 %0 +} +; CHECK: mul64: +; CHECK: ldc r11, 0 +; CHECK-NEXT: lmul r11, r4, r0, r2, r11, r11 +; CHECK-NEXT: mul r0, r0, r3 +; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0 +; CHECK-NEXT: mov r0, r4 -- cgit v1.3