From 571945e6affd20b19264ec22495da418d0fbdbb4 Mon Sep 17 00:00:00 2001 From: Roman Divacky Date: Tue, 15 Dec 2009 18:09:07 +0000 Subject: Update LLVM to 91430. --- test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll | 414 --------------------- test/CodeGen/ARM/2009-12-02-vtrn-undef.ll | 19 + test/CodeGen/ARM/inlineasm3.ll | 13 + test/CodeGen/CellSPU/and_ops.ll | 8 +- test/CodeGen/CellSPU/call_indirect.ll | 6 +- test/CodeGen/MSP430/bit.ll | 166 +++++++++ test/CodeGen/MSP430/setcc.ll | 116 ++++++ test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll | 128 +++++++ test/CodeGen/Thumb2/large-stack.ll | 2 +- test/CodeGen/Thumb2/thumb2-spill-q.ll | 2 +- test/CodeGen/X86/2007-01-08-InstrSched.ll | 2 +- test/CodeGen/X86/2009-09-10-SpillComments.ll | 13 +- .../X86/2009-09-19-SchedCustomLoweringBug.ll | 2 +- test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll | 38 ++ test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll | 63 ++++ test/CodeGen/X86/2009-12-12-CoalescerBug.ll | 40 ++ test/CodeGen/X86/3addr-16bit.ll | 95 +++++ test/CodeGen/X86/fastcc3struct.ll | 15 + test/CodeGen/X86/select-aggregate.ll | 15 + test/CodeGen/X86/setcc.ll | 37 ++ test/CodeGen/X86/sink-hoist.ll | 2 +- test/CodeGen/X86/splat-scalar-load.ll | 43 +++ test/CodeGen/X86/sse2.ll | 2 +- test/CodeGen/X86/sse3.ll | 2 +- test/CodeGen/X86/tail-opts.ll | 2 +- test/CodeGen/X86/tailcallstack64.ll | 2 +- test/CodeGen/X86/unaligned-load.ll | 1 - test/CodeGen/X86/vec-trunc-store.ll | 13 + test/CodeGen/X86/vec_compare-2.ll | 29 ++ test/CodeGen/X86/vec_ext_inreg.ll | 37 ++ test/CodeGen/X86/widen_arith-3.ll | 2 +- test/CodeGen/X86/zext-shl.ll | 25 ++ 32 files changed, 916 insertions(+), 438 deletions(-) delete mode 100644 test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll create mode 100644 test/CodeGen/ARM/2009-12-02-vtrn-undef.ll create mode 100644 test/CodeGen/ARM/inlineasm3.ll create mode 100644 test/CodeGen/MSP430/bit.ll create mode 100644 test/CodeGen/MSP430/setcc.ll create mode 100644 test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll create mode 100644 test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll create mode 100644 test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll create mode 100644 test/CodeGen/X86/2009-12-12-CoalescerBug.ll create mode 100644 test/CodeGen/X86/3addr-16bit.ll create mode 100644 test/CodeGen/X86/fastcc3struct.ll create mode 100644 test/CodeGen/X86/select-aggregate.ll create mode 100644 test/CodeGen/X86/setcc.ll create mode 100644 test/CodeGen/X86/splat-scalar-load.ll create mode 100644 test/CodeGen/X86/vec-trunc-store.ll create mode 100644 test/CodeGen/X86/vec_compare-2.ll create mode 100644 test/CodeGen/X86/vec_ext_inreg.ll create mode 100644 test/CodeGen/X86/zext-shl.ll (limited to 'test/CodeGen') diff --git a/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll b/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll deleted file mode 100644 index 35ca7b4c9af2..000000000000 --- a/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll +++ /dev/null @@ -1,414 +0,0 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 154 - - %"struct.Adv5::Ekin<3>" = type <{ i8 }> - %"struct.Adv5::X::Energyflux<3>" = type { double } - %"struct.BinaryNode >, double, MultiPatchView, 3> >,Field >, double, MultiPatchView, 3> > >" = type { %"struct.Field >,double,MultiPatchView, 3> >", %"struct.Field >,double,MultiPatchView, 3> >" } - %"struct.BinaryNode >, double, Remote >,Field >, double, Remote > >" = type { %"struct.Field >,double,Remote >", %"struct.Field >,double,Remote >" } - %"struct.BinaryNode,BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > >" = type { %"struct.Adv5::X::Energyflux<3>", %"struct.BinaryNode >, double, MultiPatchView, 3> >,Field >, double, MultiPatchView, 3> > >" } - %"struct.BinaryNode,BinaryNode >, double, Remote >, Field >, double, Remote > > >" = type { %"struct.Adv5::X::Energyflux<3>", %"struct.BinaryNode >, double, Remote >,Field >, double, Remote > >" } - %"struct.Centering<3>" = type { i32, i32, %"struct.std::vector,std::allocator > >", %"struct.std::vector,std::allocator > >" } - %"struct.ContextMapper<1>" = type { i32 (...)** } - %"struct.DataBlockController" = type { %"struct.RefBlockController", %"struct.Adv5::Ekin<3>"*, i8, %"struct.SingleObservable", i32 } - %"struct.DataBlockPtr" = type { %"struct.RefCountedBlockPtr >" } - %"struct.Domain<1,DomainTraits > >" = type { %"struct.DomainBase > >" } - %"struct.Domain<1,DomainTraits > >" = type { %"struct.DomainBase > >" } - %"struct.Domain<1,DomainTraits > >" = type { %"struct.DomainBase > >" } - %"struct.Domain<3,DomainTraits > >" = type { %"struct.DomainBase > >" } - %"struct.Domain<3,DomainTraits > >" = type { %"struct.DomainBase > >" } - %"struct.Domain<3,DomainTraits > >" = type { %"struct.DomainBase > >" } - %"struct.DomainBase > >" = type { [2 x i32] } - %"struct.DomainBase > >" = type { [3 x %"struct.WrapNoInit >"] } - %"struct.DomainBase > >" = type { i32 } - %"struct.DomainBase > >" = type { [3 x %"struct.WrapNoInit >"] } - %"struct.DomainBase > >" = type { [3 x i32] } - %"struct.DomainBase > >" = type { [3 x %"struct.WrapNoInit >"] } - %"struct.DomainLayout<3>" = type { %"struct.Node,Interval<3> >" } - %"struct.DomainMap,int>" = type { i32, %"struct.DomainMapNode,int>"*, %"struct.DomainMapIterator,int>" } - %"struct.DomainMapIterator,int>" = type { %"struct.DomainMapNode,int>"*, %"struct.std::_List_const_iterator >" } - %"struct.DomainMapNode,int>" = type { %"struct.Interval<1>", %"struct.DomainMapNode,int>"*, %"struct.DomainMapNode,int>"*, %"struct.DomainMapNode,int>"*, %"struct.std::list,std::allocator > >" } - %"struct.Engine<3,Zero,ConstantFunction>" = type { %"struct.Adv5::Ekin<3>", %"struct.Interval<3>", [3 x i32] } - %"struct.Engine<3,double,Brick>" = type { %"struct.Pooma::BrickBase<3>", %"struct.DataBlockPtr", double* } - %"struct.Engine<3,double,BrickView>" = type { %"struct.Pooma::BrickViewBase<3>", %"struct.DataBlockPtr", double* } - %"struct.Engine<3,double,ConstantFunction>" = type { double, %"struct.Interval<3>", [3 x i32] } - %"struct.Engine<3,double,ExpressionTag, BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > > > >" = type { %"struct.BinaryNode,BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > >", %"struct.Interval<3>" } - %"struct.Engine<3,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >" = type { %"struct.BinaryNode,BinaryNode >, double, Remote >, Field >, double, Remote > > >", %"struct.Interval<3>" } - %"struct.Engine<3,double,MultiPatch > >" = type { %"struct.ContextMapper<1>", %"struct.GridLayout<3>", %"struct.RefCountedBlockPtr >,false,RefBlockController > > >", i32* } - %"struct.Engine<3,double,MultiPatchView, 3> >" = type { %"struct.GridLayoutView<3,3>", %"struct.Engine<3,double,MultiPatch > >" } - %"struct.Engine<3,double,Remote >" = type { %"struct.Interval<3>", i32, %"struct.RefCountedPtr > >" } - %"struct.Engine<3,double,Remote >" = type { %"struct.Interval<3>", i32, %"struct.RefCountedPtr > >" } - %"struct.Field >,Zero,ConstantFunction>" = type { %"struct.FieldEngine >,Zero,ConstantFunction>" } - %"struct.Field >,double,ConstantFunction>" = type { %"struct.FieldEngine >,double,ConstantFunction>" } - %"struct.Field >,double,ExpressionTag, BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > > > >" = type { %"struct.FieldEngine >,double,ExpressionTag, BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > > > >" } - %"struct.Field >,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >" = type { %"struct.FieldEngine >,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >" } - %"struct.Field >,double,MultiPatch > >" = type { %"struct.FieldEngine >,double,MultiPatch > >" } - %"struct.Field >,double,MultiPatchView, 3> >" = type { %"struct.FieldEngine >,double,MultiPatchView, 3> >" } - %"struct.Field >,double,Remote >" = type { %"struct.FieldEngine >,double,Remote >" } - %"struct.FieldEngine >,Zero,ConstantFunction>" = type { i32, %"struct.Centering<3>", i32, %"struct.RefCountedBlockPtr, ConstantFunction>,false,RefBlockController, ConstantFunction> > >", %"struct.Interval<3>", %"struct.GuardLayers<3>", %"struct.UniformRectilinearMesh >" } - %"struct.FieldEngine >,double,ConstantFunction>" = type { i32, %"struct.Centering<3>", i32, %"struct.RefCountedBlockPtr,false,RefBlockController > >", %"struct.Interval<3>", %"struct.GuardLayers<3>", %"struct.UniformRectilinearMesh >" } - %"struct.FieldEngine >,double,ExpressionTag, BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > > > >" = type { %"struct.Engine<3,double,ExpressionTag, BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > > > >", %"struct.Field >,double,MultiPatchView, 3> >"* } - %"struct.FieldEngine >,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >" = type { %"struct.Engine<3,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >", %"struct.Field >,double,Remote >"* } - %"struct.FieldEngine >,double,MultiPatch > >" = type { i32, %"struct.Centering<3>", i32, %"struct.RefCountedBlockPtr > >,false,RefBlockController > > > >", %"struct.Interval<3>", %"struct.GuardLayers<3>", %"struct.UniformRectilinearMesh >" } - %"struct.FieldEngine >,double,MultiPatchView, 3> >" = type { i32, %"struct.Centering<3>", i32, %"struct.RefCountedBlockPtr, 3> >,false,RefBlockController, 3> > > >", %"struct.Interval<3>", %"struct.GuardLayers<3>", %"struct.UniformRectilinearMesh >" } - %"struct.FieldEngine >,double,Remote >" = type { i32, %"struct.Centering<3>", i32, %"struct.RefCountedBlockPtr >,false,RefBlockController > > >", %"struct.Interval<3>", %"struct.GuardLayers<3>", %"struct.UniformRectilinearMesh >" } - %"struct.FieldEngineBaseData<3,Zero,ConstantFunction>" = type { %"struct.Engine<3,Zero,ConstantFunction>", %struct.RelationList } - %"struct.FieldEngineBaseData<3,double,ConstantFunction>" = type { %"struct.Engine<3,double,ConstantFunction>", %struct.RelationList } - %"struct.FieldEngineBaseData<3,double,MultiPatch > >" = type { %"struct.Engine<3,double,MultiPatch > >", %struct.RelationList } - %"struct.FieldEngineBaseData<3,double,MultiPatchView, 3> >" = type { %"struct.Engine<3,double,MultiPatchView, 3> >", %struct.RelationList } - %"struct.FieldEngineBaseData<3,double,Remote >" = type { %"struct.Engine<3,double,Remote >", %struct.RelationList } - %struct.GlobalIDDataBase = type { %"struct.std::vector >", %"struct.std::map,std::allocator > >" } - %"struct.GlobalIDDataBase::Pack" = type { i32, i32, i32, i32 } - %"struct.GridLayout<3>" = type { %"struct.ContextMapper<1>", %"struct.LayoutBase<3,GridLayoutData<3> >", %"struct.Observable >" } - %"struct.GridLayoutData<3>" = type { %"struct.LayoutBaseData<3>", %struct.RefCounted, [21 x i8], i8, [3 x i32], [3 x %"struct.DomainMap,int>"], [3 x %"struct.DomainMap,int>"] } - %"struct.GridLayoutView<3,3>" = type { %"struct.LayoutBaseView<3,3,GridLayoutViewData<3, 3> >" } - %"struct.GridLayoutViewData<3,3>" = type { %"struct.LayoutBaseViewData<3,3,GridLayout<3> >", %struct.RefCounted } - %"struct.GuardLayers<3>" = type { [3 x i32], [3 x i32] } - %"struct.INode<3>" = type { %"struct.Interval<3>", %struct.GlobalIDDataBase*, i32 } - %"struct.Interval<1>" = type { %"struct.Domain<1,DomainTraits > >" } - %"struct.Interval<3>" = type { %"struct.Domain<3,DomainTraits > >" } - %"struct.LayoutBase<3,GridLayoutData<3> >" = type { %"struct.RefCountedPtr >" } - %"struct.LayoutBaseData<3>" = type { i32, %"struct.Interval<3>", %"struct.Interval<3>", %"struct.std::vector, Interval<3> >*,std::allocator, Interval<3> >*> >", %"struct.std::vector, Interval<3> >*,std::allocator, Interval<3> >*> >", %"struct.std::vector, Interval<3> >*,std::allocator, Interval<3> >*> >", i8, i8, %"struct.GuardLayers<3>", %"struct.GuardLayers<3>", %"struct.std::vector::GCFillInfo,std::allocator::GCFillInfo> >", [3 x i32], [3 x i32], %"struct.Loc<3>" } - %"struct.LayoutBaseData<3>::GCFillInfo" = type { %"struct.Interval<3>", i32, i32, i32 } - %"struct.LayoutBaseView<3,3,GridLayoutViewData<3, 3> >" = type { %"struct.RefCountedPtr >" } - %"struct.LayoutBaseViewData<3,3,GridLayout<3> >" = type { i32, %"struct.GridLayout<3>", %"struct.GuardLayers<3>", %"struct.GuardLayers<3>", %"struct.ViewIndexer<3,3>", %"struct.std::vector, Interval<3> >*,std::allocator, Interval<3> >*> >", %"struct.std::vector, Interval<3> >*,std::allocator, Interval<3> >*> >", %"struct.std::vector, Interval<3> >*,std::allocator, Interval<3> >*> >", i8 } - %"struct.Loc<1>" = type { %"struct.Domain<1,DomainTraits > >" } - %"struct.Loc<3>" = type { %"struct.Domain<3,DomainTraits > >" } - %"struct.MultiArg6 >, double, MultiPatch > >,Field >, double, MultiPatch > >,Field >, double, MultiPatch > >,Field >, double, MultiPatch > >,Field >, double, ConstantFunction>,Field >, Zero, ConstantFunction> >" = type { %"struct.Field >,double,MultiPatch > >", %"struct.Field >,double,MultiPatch > >", %"struct.Field >,double,MultiPatch > >", %"struct.Field >,double,MultiPatch > >", %"struct.Field >,double,ConstantFunction>", %"struct.Field >,Zero,ConstantFunction>" } - %"struct.NoMeshData<3>" = type { %struct.RefCounted, %"struct.Interval<3>", %"struct.Interval<3>", %"struct.Interval<3>", %"struct.Interval<3>" } - %"struct.Node,Interval<3> >" = type { %"struct.Interval<3>", %"struct.Interval<3>", i32, i32, i32, i32 } - %"struct.Observable >" = type { %"struct.GridLayout<3>"*, %"struct.std::vector >*,std::allocator >*> >", i32, %"struct.Adv5::Ekin<3>" } - %"struct.Pooma::BrickBase<3>" = type { %"struct.DomainLayout<3>", [3 x i32], [3 x i32], i32, i8 } - %"struct.Pooma::BrickViewBase<3>" = type { %"struct.Interval<3>", [3 x i32], [3 x i32], i32, i8 } - %"struct.Range<1>" = type { %"struct.Domain<1,DomainTraits > >" } - %"struct.Range<3>" = type { %"struct.Domain<3,DomainTraits > >" } - %"struct.RefBlockController > >" = type { %struct.RefCounted, %"struct.Engine<3,double,Remote >"*, %"struct.Engine<3,double,Remote >"*, %"struct.Engine<3,double,Remote >"*, i8 } - %"struct.RefBlockController, ConstantFunction> >" = type { %struct.RefCounted, %"struct.FieldEngineBaseData<3,Zero,ConstantFunction>"*, %"struct.FieldEngineBaseData<3,Zero,ConstantFunction>"*, %"struct.FieldEngineBaseData<3,Zero,ConstantFunction>"*, i8 } - %"struct.RefBlockController >" = type { %struct.RefCounted, %"struct.FieldEngineBaseData<3,double,ConstantFunction>"*, %"struct.FieldEngineBaseData<3,double,ConstantFunction>"*, %"struct.FieldEngineBaseData<3,double,ConstantFunction>"*, i8 } - %"struct.RefBlockController > > >" = type { %struct.RefCounted, %"struct.FieldEngineBaseData<3,double,MultiPatch > >"*, %"struct.FieldEngineBaseData<3,double,MultiPatch > >"*, %"struct.FieldEngineBaseData<3,double,MultiPatch > >"*, i8 } - %"struct.RefBlockController, 3> > >" = type { %struct.RefCounted, %"struct.FieldEngineBaseData<3,double,MultiPatchView, 3> >"*, %"struct.FieldEngineBaseData<3,double,MultiPatchView, 3> >"*, %"struct.FieldEngineBaseData<3,double,MultiPatchView, 3> >"*, i8 } - %"struct.RefBlockController > >" = type { %struct.RefCounted, %"struct.FieldEngineBaseData<3,double,Remote >"*, %"struct.FieldEngineBaseData<3,double,Remote >"*, %"struct.FieldEngineBaseData<3,double,Remote >"*, i8 } - %"struct.RefBlockController" = type { %struct.RefCounted, double*, double*, double*, i8 } - %struct.RefCounted = type { i32, %"struct.Adv5::Ekin<3>" } - %"struct.RefCountedBlockPtr >,false,RefBlockController > > >" = type { i32, %"struct.RefCountedPtr > > >" } - %"struct.RefCountedBlockPtr, ConstantFunction>,false,RefBlockController, ConstantFunction> > >" = type { i32, %"struct.RefCountedPtr, ConstantFunction> > >" } - %"struct.RefCountedBlockPtr,false,RefBlockController > >" = type { i32, %"struct.RefCountedPtr > >" } - %"struct.RefCountedBlockPtr > >,false,RefBlockController > > > >" = type { i32, %"struct.RefCountedPtr > > > >" } - %"struct.RefCountedBlockPtr, 3> >,false,RefBlockController, 3> > > >" = type { i32, %"struct.RefCountedPtr, 3> > > >" } - %"struct.RefCountedBlockPtr >,false,RefBlockController > > >" = type { i32, %"struct.RefCountedPtr > > >" } - %"struct.RefCountedBlockPtr >" = type { i32, %"struct.RefCountedPtr >" } - %"struct.RefCountedPtr >" = type { %"struct.DataBlockController"* } - %"struct.RefCountedPtr >" = type { %"struct.GridLayoutData<3>"* } - %"struct.RefCountedPtr >" = type { %"struct.GridLayoutViewData<3,3>"* } - %"struct.RefCountedPtr > > >" = type { %"struct.RefBlockController > >"* } - %"struct.RefCountedPtr, ConstantFunction> > >" = type { %"struct.RefBlockController, ConstantFunction> >"* } - %"struct.RefCountedPtr > >" = type { %"struct.RefBlockController >"* } - %"struct.RefCountedPtr > > > >" = type { %"struct.RefBlockController > > >"* } - %"struct.RefCountedPtr, 3> > > >" = type { %"struct.RefBlockController, 3> > >"* } - %"struct.RefCountedPtr > > >" = type { %"struct.RefBlockController > >"* } - %"struct.RefCountedPtr" = type { %struct.RelationListData* } - %"struct.RefCountedPtr > >" = type { %"struct.Shared >"* } - %"struct.RefCountedPtr > >" = type { %"struct.Shared >"* } - %"struct.RefCountedPtr > >" = type { %"struct.UniformRectilinearMeshData >"* } - %struct.RelationList = type { %"struct.RefCountedPtr" } - %struct.RelationListData = type { %struct.RefCounted, %"struct.std::vector >" } - %struct.RelationListItem = type { i32 (...)**, i32, i32, i8 } - %"struct.Shared >" = type { %struct.RefCounted, %"struct.Engine<3,double,Brick>" } - %"struct.Shared >" = type { %struct.RefCounted, %"struct.Engine<3,double,BrickView>" } - %"struct.SingleObservable" = type { %"struct.ContextMapper<1>"* } - %"struct.UniformRectilinearMesh >" = type { %"struct.RefCountedPtr > >" } - %"struct.UniformRectilinearMeshData >" = type { %"struct.NoMeshData<3>", %"struct.Vector<3,double,Full>", %"struct.Vector<3,double,Full>" } - %"struct.Vector<3,double,Full>" = type { %"struct.VectorEngine<3,double,Full>" } - %"struct.VectorEngine<3,double,Full>" = type { [3 x double] } - %"struct.ViewIndexer<3,3>" = type { %"struct.Interval<3>", %"struct.Range<3>", [3 x i32], [3 x i32], %"struct.Loc<3>" } - %"struct.WrapNoInit >" = type { %"struct.Interval<1>" } - %"struct.WrapNoInit >" = type { %"struct.Loc<1>" } - %"struct.WrapNoInit >" = type { %"struct.Range<1>" } - %"struct.std::_List_base,std::allocator > >" = type { %"struct.std::_List_base,std::allocator > >::_List_impl" } - %"struct.std::_List_base,std::allocator > >::_List_impl" = type { %"struct.std::_List_node_base" } - %"struct.std::_List_const_iterator >" = type { %"struct.std::_List_node_base"* } - %"struct.std::_List_node_base" = type { %"struct.std::_List_node_base"*, %"struct.std::_List_node_base"* } - %"struct.std::_Rb_tree,std::_Select1st >,std::less,std::allocator > >" = type { %"struct.std::_Rb_tree,std::_Select1st >,std::less,std::allocator > >::_Rb_tree_impl,false>" } - %"struct.std::_Rb_tree,std::_Select1st >,std::less,std::allocator > >::_Rb_tree_impl,false>" = type { %"struct.Adv5::Ekin<3>", %"struct.std::_Rb_tree_node_base", i32 } - %"struct.std::_Rb_tree_node_base" = type { i32, %"struct.std::_Rb_tree_node_base"*, %"struct.std::_Rb_tree_node_base"*, %"struct.std::_Rb_tree_node_base"* } - %"struct.std::_Vector_base >" = type { %"struct.std::_Vector_base >::_Vector_impl" } - %"struct.std::_Vector_base >::_Vector_impl" = type { %"struct.GlobalIDDataBase::Pack"*, %"struct.GlobalIDDataBase::Pack"*, %"struct.GlobalIDDataBase::Pack"* } - %"struct.std::_Vector_base::GCFillInfo,std::allocator::GCFillInfo> >" = type { %"struct.std::_Vector_base::GCFillInfo,std::allocator::GCFillInfo> >::_Vector_impl" } - %"struct.std::_Vector_base::GCFillInfo,std::allocator::GCFillInfo> >::_Vector_impl" = type { %"struct.LayoutBaseData<3>::GCFillInfo"*, %"struct.LayoutBaseData<3>::GCFillInfo"*, %"struct.LayoutBaseData<3>::GCFillInfo"* } - %"struct.std::_Vector_base,std::allocator > >" = type { %"struct.std::_Vector_base,std::allocator > >::_Vector_impl" } - %"struct.std::_Vector_base,std::allocator > >::_Vector_impl" = type { %"struct.Loc<3>"*, %"struct.Loc<3>"*, %"struct.Loc<3>"* } - %"struct.std::_Vector_base, Interval<3> >*,std::allocator, Interval<3> >*> >" = type { %"struct.std::_Vector_base, Interval<3> >*,std::allocator, Interval<3> >*> >::_Vector_impl" } - %"struct.std::_Vector_base, Interval<3> >*,std::allocator, Interval<3> >*> >::_Vector_impl" = type { %"struct.Node,Interval<3> >"**, %"struct.Node,Interval<3> >"**, %"struct.Node,Interval<3> >"** } - %"struct.std::_Vector_base >*,std::allocator >*> >" = type { %"struct.std::_Vector_base >*,std::allocator >*> >::_Vector_impl" } - %"struct.std::_Vector_base >*,std::allocator >*> >::_Vector_impl" = type { %"struct.ContextMapper<1>"**, %"struct.ContextMapper<1>"**, %"struct.ContextMapper<1>"** } - %"struct.std::_Vector_base >" = type { %"struct.std::_Vector_base >::_Vector_impl" } - %"struct.std::_Vector_base >::_Vector_impl" = type { %struct.RelationListItem**, %struct.RelationListItem**, %struct.RelationListItem** } - %"struct.std::_Vector_base,std::allocator > >" = type { %"struct.std::_Vector_base,std::allocator > >::_Vector_impl" } - %"struct.std::_Vector_base,std::allocator > >::_Vector_impl" = type { %"struct.Vector<3,double,Full>"*, %"struct.Vector<3,double,Full>"*, %"struct.Vector<3,double,Full>"* } - %"struct.std::list,std::allocator > >" = type { %"struct.std::_List_base,std::allocator > >" } - %"struct.std::map,std::allocator > >" = type { %"struct.std::_Rb_tree,std::_Select1st >,std::less,std::allocator > >" } - %"struct.std::vector >" = type { %"struct.std::_Vector_base >" } - %"struct.std::vector::GCFillInfo,std::allocator::GCFillInfo> >" = type { %"struct.std::_Vector_base::GCFillInfo,std::allocator::GCFillInfo> >" } - %"struct.std::vector,std::allocator > >" = type { %"struct.std::_Vector_base,std::allocator > >" } - %"struct.std::vector, Interval<3> >*,std::allocator, Interval<3> >*> >" = type { %"struct.std::_Vector_base, Interval<3> >*,std::allocator, Interval<3> >*> >" } - %"struct.std::vector >*,std::allocator >*> >" = type { %"struct.std::_Vector_base >*,std::allocator >*> >" } - %"struct.std::vector >" = type { %"struct.std::_Vector_base >" } - %"struct.std::vector,std::allocator > >" = type { %"struct.std::_Vector_base,std::allocator > >" } - -declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind - -declare fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEEC1ERKSC_(%"struct.FieldEngine >,double,MultiPatch > >"*, %"struct.FieldEngine >,double,MultiPatch > >"*) nounwind - -declare fastcc void @_ZN9CenteringILi3EEC1ERKS0_i(%"struct.Centering<3>"*, %"struct.Centering<3>"*, i32) nounwind - -declare fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEED1Ev(%"struct.FieldEngine >,double,Remote >"*) nounwind - -declare fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEEC1Id14MultiPatchViewI7GridTagS6_I5BrickELi3EEEERKS_IS5_T_T0_ERK5INodeILi3EE(%"struct.FieldEngine >,double,Remote >"*, %"struct.FieldEngine >,double,MultiPatchView, 3> >"*, %"struct.INode<3>"*) nounwind - -declare fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EEED1Ev(%"struct.FieldEngine >,double,MultiPatchView, 3> >"*) nounwind - -declare fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EEEC1Id10MultiPatchIS7_SA_EEERKS_IS5_T_T0_ERK8IntervalILi3EE(%"struct.FieldEngine >,double,MultiPatchView, 3> >"*, %"struct.FieldEngine >,double,MultiPatch > >"*, %"struct.Interval<3>"*) nounwind - -define fastcc void @t(double %dt, %"struct.Field >,double,MultiPatch > >"* %rh, %"struct.Field >,double,MultiPatch > >"* %T, %"struct.Field >,double,MultiPatch > >"* %v, %"struct.Field >,double,MultiPatch > >"* %pg, %"struct.Field >,double,MultiPatch > >"* %ph, %"struct.Field >,double,MultiPatch > >"* %cs, %"struct.Field >,double,ConstantFunction>"* %cv, %"struct.Field >,Zero,ConstantFunction>"* %dlmdlt, %"struct.Field >,double,ConstantFunction>"* %xmue, %"struct.Field >,double,MultiPatch > >"* %vint, %"struct.Field >,double,MultiPatch > >"* %cent, %"struct.Field >,double,MultiPatch > >"* %fvis, double %c_nr, double %c_av, i8 zeroext %cartvis_f) nounwind { -entry: - %0 = alloca %"struct.Field >,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >" ; <%"struct.Field >,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >"*> [#uses=4] - %s.i.i.i.i.i = alloca %"struct.Interval<3>" ; <%"struct.Interval<3>"*> [#uses=0] - %1 = alloca %"struct.BinaryNode,BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > >" ; <%"struct.BinaryNode,BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > >"*> [#uses=2] - %multiArg.i = alloca %"struct.MultiArg6 >, double, MultiPatch > >,Field >, double, MultiPatch > >,Field >, double, MultiPatch > >,Field >, double, MultiPatch > >,Field >, double, ConstantFunction>,Field >, Zero, ConstantFunction> >" ; <%"struct.MultiArg6 >, double, MultiPatch > >,Field >, double, MultiPatch > >,Field >, double, MultiPatch > >,Field >, double, MultiPatch > >,Field >, double, ConstantFunction>,Field >, Zero, ConstantFunction> >"*> [#uses=0] - %2 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=6] - %3 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=2] - %4 = alloca %"struct.Field >,double,MultiPatchView, 3> >" ; <%"struct.Field >,double,MultiPatchView, 3> >"*> [#uses=0] - %5 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=2] - %6 = alloca %"struct.Field >,double,MultiPatchView, 3> >" ; <%"struct.Field >,double,MultiPatchView, 3> >"*> [#uses=0] - %7 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %8 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %9 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %10 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %11 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %12 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %13 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %14 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %15 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %16 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %17 = alloca %"struct.Interval<3>" ; <%"struct.Interval<3>"*> [#uses=0] - %18 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %19 = alloca double ; [#uses=0] - %20 = alloca %"struct.Field >,double,MultiPatchView, 3> >" ; <%"struct.Field >,double,MultiPatchView, 3> >"*> [#uses=0] - %21 = alloca %"struct.Interval<3>" ; <%"struct.Interval<3>"*> [#uses=0] - %22 = alloca %"struct.Field >,double,MultiPatchView, 3> >" ; <%"struct.Field >,double,MultiPatchView, 3> >"*> [#uses=0] - %23 = alloca %"struct.Field >,double,MultiPatchView, 3> >" ; <%"struct.Field >,double,MultiPatchView, 3> >"*> [#uses=0] - %24 = alloca %"struct.Interval<3>" ; <%"struct.Interval<3>"*> [#uses=0] - %25 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %26 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %27 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %28 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %29 = alloca %"struct.Interval<3>" ; <%"struct.Interval<3>"*> [#uses=0] - %30 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %31 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %32 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %33 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %34 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %35 = alloca %"struct.Interval<3>" ; <%"struct.Interval<3>"*> [#uses=0] - %36 = alloca %"struct.Field >,double,MultiPatch > >" ; <%"struct.Field >,double,MultiPatch > >"*> [#uses=0] - %37 = getelementptr %"struct.Field >,double,MultiPatch > >"* %v, i32 0, i32 0, i32 5 ; <%"struct.GuardLayers<3>"*> [#uses=1] - %38 = bitcast %"struct.GuardLayers<3>"* %37 to i8* ; [#uses=1] - br label %bb.i.i.i.i.i - -bb.i.i.i.i.i: ; preds = %bb.i.i.i.i.i, %entry - %39 = icmp eq i32* null, null ; [#uses=1] - br i1 %39, label %_ZN14ScalarCodeInfoILi3ELi4EEC1Ev.exit.i, label %bb.i.i.i.i.i - -_ZN14ScalarCodeInfoILi3ELi4EEC1Ev.exit.i: ; preds = %bb.i.i.i.i.i - br label %bb.i.i.i35.i.i34 - -bb.i.i.i35.i.i34: ; preds = %bb.i.i.i35.i.i34, %_ZN14ScalarCodeInfoILi3ELi4EEC1Ev.exit.i - %40 = icmp eq i32* null, null ; [#uses=1] - br i1 %40, label %_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit36.i.i37, label %bb.i.i.i35.i.i34 - -_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit36.i.i37: ; preds = %bb.i.i.i35.i.i34 - br label %bb.i.i.i19.i.i47 - -bb.i.i.i19.i.i47: ; preds = %bb.i.i.i19.i.i47, %_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit36.i.i37 - %41 = icmp eq i32* null, null ; [#uses=1] - br i1 %41, label %_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit20.i.i50, label %bb.i.i.i19.i.i47 - -_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit20.i.i50: ; preds = %bb.i.i.i19.i.i47 - %42 = getelementptr %"struct.Field >,double,MultiPatch > >"* %rh, i32 0, i32 0 ; <%"struct.FieldEngine >,double,MultiPatch > >"*> [#uses=1] - br label %bb.i.i.i19.i.i.i - -bb.i.i.i19.i.i.i: ; preds = %bb.i.i.i19.i.i.i, %_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit20.i.i50 - %43 = icmp eq i32* null, null ; [#uses=1] - br i1 %43, label %_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit20.i.i.i, label %bb.i.i.i19.i.i.i - -_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit20.i.i.i: ; preds = %bb.i.i.i19.i.i.i - br label %bb.i.i.i35.i.i433 - -bb.i.i.i35.i.i433: ; preds = %bb.i.i.i35.i.i433, %_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit20.i.i.i - %44 = icmp eq i32* null, null ; [#uses=1] - br i1 %44, label %_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit36.i.i436, label %bb.i.i.i35.i.i433 - -_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit36.i.i436: ; preds = %bb.i.i.i35.i.i433 - br label %bb.i.i.i19.i.i446 - -bb.i.i.i19.i.i446: ; preds = %bb.i.i.i19.i.i446, %_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit36.i.i436 - %45 = icmp eq i32* null, null ; [#uses=1] - br i1 %45, label %_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit20.i.i449, label %bb.i.i.i19.i.i446 - -_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit20.i.i449: ; preds = %bb.i.i.i19.i.i446 - br label %bb.i.i.i.i.i459 - -bb.i.i.i.i.i459: ; preds = %bb.i.i.i.i.i459, %_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_.exit20.i.i449 - %46 = icmp eq i32* null, null ; [#uses=1] - br i1 %46, label %_ZN14ScalarCodeInfoILi3ELi6EEC1Ev.exit.i460, label %bb.i.i.i.i.i459 - -_ZN14ScalarCodeInfoILi3ELi6EEC1Ev.exit.i460: ; preds = %bb.i.i.i.i.i459 - %47 = getelementptr %"struct.Field >,double,MultiPatch > >"* %5, i32 0, i32 0, i32 1 ; <%"struct.Centering<3>"*> [#uses=1] - %48 = getelementptr %"struct.Field >,double,MultiPatch > >"* %vint, i32 0, i32 0, i32 1 ; <%"struct.Centering<3>"*> [#uses=2] - %49 = getelementptr %"struct.Field >,double,MultiPatch > >"* %5, i32 0, i32 0, i32 5 ; <%"struct.GuardLayers<3>"*> [#uses=1] - %50 = bitcast %"struct.GuardLayers<3>"* %49 to i8* ; [#uses=1] - %51 = bitcast %"struct.GuardLayers<3>"* null to i8* ; [#uses=2] - %52 = getelementptr %"struct.Field >,double,MultiPatch > >"* %3, i32 0, i32 0, i32 1 ; <%"struct.Centering<3>"*> [#uses=1] - %53 = getelementptr %"struct.Field >,double,MultiPatch > >"* %3, i32 0, i32 0, i32 5 ; <%"struct.GuardLayers<3>"*> [#uses=1] - %54 = bitcast %"struct.GuardLayers<3>"* %53 to i8* ; [#uses=1] - %55 = getelementptr %"struct.Field >,double,MultiPatch > >"* %2, i32 0, i32 0, i32 1 ; <%"struct.Centering<3>"*> [#uses=1] - %56 = getelementptr %"struct.Field >,double,MultiPatch > >"* %2, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1 ; [#uses=1] - %57 = getelementptr %"struct.Field >,double,MultiPatch > >"* %2, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1 ; [#uses=1] - %58 = getelementptr %"struct.Field >,double,MultiPatch > >"* %2, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0, i32 0 ; [#uses=1] - %59 = getelementptr %"struct.Field >,double,MultiPatch > >"* %2, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0, i32 1 ; [#uses=1] - %60 = getelementptr %"struct.Field >,double,MultiPatch > >"* %2, i32 0, i32 0, i32 5 ; <%"struct.GuardLayers<3>"*> [#uses=1] - %61 = bitcast %"struct.GuardLayers<3>"* %60 to i8* ; [#uses=1] - %62 = getelementptr %"struct.BinaryNode,BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > >"* %1, i32 0, i32 1, i32 0, i32 0 ; <%"struct.FieldEngine >,double,MultiPatchView, 3> >"*> [#uses=1] - %63 = getelementptr %"struct.BinaryNode,BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > >"* %1, i32 0, i32 1, i32 1, i32 0 ; <%"struct.FieldEngine >,double,MultiPatchView, 3> >"*> [#uses=1] - %64 = getelementptr %"struct.Field >,double,ExpressionTag, BinaryNode >, double, MultiPatchView, 3> >, Field >, double, MultiPatchView, 3> > > > > >"* null, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 ; [#uses=1] - %65 = getelementptr %"struct.Field >,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >"* %0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0 ; <%"struct.FieldEngine >,double,Remote >"*> [#uses=2] - %66 = getelementptr %"struct.Field >,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >"* %0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0 ; [#uses=1] - %67 = getelementptr %"struct.Field >,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >"* %0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1 ; [#uses=1] - %68 = getelementptr %"struct.Field >,double,ExpressionTag, BinaryNode >, double, Remote >, Field >, double, Remote > > > > >"* %0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0, i32 1 ; [#uses=1] - br label %bb15 - -bb15: ; preds = %_Z6assignI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EES5_d13ExpressionTagI10BinaryNodeI10OpMultiply6ScalarIdESD_I5OpAdd9ReferenceI5FieldIS5_dSB_EESL_EEE8OpAssignERKSJ_IT_T0_T1_ESV_RKSJ_IT2_T3_T4_ERKT5_.exit, %_ZN14ScalarCodeInfoILi3ELi6EEC1Ev.exit.i460 - %i.0.reg2mem.0 = phi i32 [ 0, %_ZN14ScalarCodeInfoILi3ELi6EEC1Ev.exit.i460 ], [ %indvar.next, %_Z6assignI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EES5_d13ExpressionTagI10BinaryNodeI10OpMultiply6ScalarIdESD_I5OpAdd9ReferenceI5FieldIS5_dSB_EESL_EEE8OpAssignERKSJ_IT_T0_T1_ESV_RKSJ_IT2_T3_T4_ERKT5_.exit ] ; [#uses=4] - call fastcc void @_ZN9CenteringILi3EEC1ERKS0_i(%"struct.Centering<3>"* %47, %"struct.Centering<3>"* %48, i32 %i.0.reg2mem.0) nounwind - call void @llvm.memcpy.i32(i8* %50, i8* %51, i32 24, i32 4) nounwind - call fastcc void @_ZN9CenteringILi3EEC1ERKS0_i(%"struct.Centering<3>"* %52, %"struct.Centering<3>"* %48, i32 %i.0.reg2mem.0) nounwind - call void @llvm.memcpy.i32(i8* %54, i8* %51, i32 24, i32 4) nounwind - br i1 false, label %bb.i940, label %bb4.i943 - -bb.i940: ; preds = %bb15 - br label %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEE11totalDomainEv.exit944 - -bb4.i943: ; preds = %bb15 - br label %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEE11totalDomainEv.exit944 - -_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEE11totalDomainEv.exit944: ; preds = %bb4.i943, %bb.i940 - call fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EEEC1Id10MultiPatchIS7_SA_EEERKS_IS5_T_T0_ERK8IntervalILi3EE(%"struct.FieldEngine >,double,MultiPatchView, 3> >"* null, %"struct.FieldEngine >,double,MultiPatch > >"* null, %"struct.Interval<3>"* null) nounwind - call fastcc void @_ZN9CenteringILi3EEC1ERKS0_i(%"struct.Centering<3>"* %55, %"struct.Centering<3>"* null, i32 %i.0.reg2mem.0) nounwind - call void @llvm.memcpy.i32(i8* %61, i8* %38, i32 24, i32 4) nounwind - %69 = load %"struct.Loc<3>"** null, align 4 ; <%"struct.Loc<3>"*> [#uses=1] - %70 = ptrtoint %"struct.Loc<3>"* %69 to i32 ; [#uses=1] - %.off.i911 = sub i32 0, %70 ; [#uses=1] - %71 = icmp ult i32 %.off.i911, 12 ; [#uses=1] - %72 = sub i32 0, 0 ; [#uses=2] - %73 = load i32* %56, align 4 ; [#uses=1] - %74 = add i32 %73, 0 ; [#uses=1] - %75 = sub i32 %74, %72 ; [#uses=1] - %76 = add i32 %75, 0 ; [#uses=1] - %77 = load i32* null, align 8 ; [#uses=2] - %78 = load i32* null, align 4 ; [#uses=1] - %79 = sub i32 %77, %78 ; [#uses=1] - %80 = load i32* %57, align 4 ; [#uses=1] - %81 = load i32* null, align 4 ; [#uses=1] - br i1 %71, label %bb.i912, label %bb4.i915 - -bb.i912: ; preds = %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEE11totalDomainEv.exit944 - br label %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEE11totalDomainEv.exit916 - -bb4.i915: ; preds = %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEE11totalDomainEv.exit944 - %82 = sub i32 %77, %79 ; [#uses=1] - %83 = add i32 %82, %80 ; [#uses=1] - %84 = add i32 %83, %81 ; [#uses=1] - %85 = load i32* %58, align 8 ; [#uses=2] - %86 = load i32* null, align 8 ; [#uses=1] - %87 = sub i32 %85, %86 ; [#uses=2] - %88 = load i32* %59, align 4 ; [#uses=1] - %89 = load i32* null, align 4 ; [#uses=1] - %90 = sub i32 %85, %87 ; [#uses=1] - %91 = add i32 %90, %88 ; [#uses=1] - %92 = add i32 %91, %89 ; [#uses=1] - br label %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEE11totalDomainEv.exit916 - -_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEE11totalDomainEv.exit916: ; preds = %bb4.i915, %bb.i912 - %.0978.0.0.1.0.0.0.0.1.0 = phi i32 [ %84, %bb4.i915 ], [ 0, %bb.i912 ] ; [#uses=0] - %.0978.0.0.2.0.0.0.0.0.0 = phi i32 [ %87, %bb4.i915 ], [ 0, %bb.i912 ] ; [#uses=1] - %.0978.0.0.2.0.0.0.0.1.0 = phi i32 [ %92, %bb4.i915 ], [ 0, %bb.i912 ] ; [#uses=0] - store i32 %72, i32* null, align 8 - store i32 %76, i32* null, align 4 - store i32 %.0978.0.0.2.0.0.0.0.0.0, i32* null, align 8 - call fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EEEC1Id10MultiPatchIS7_SA_EEERKS_IS5_T_T0_ERK8IntervalILi3EE(%"struct.FieldEngine >,double,MultiPatchView, 3> >"* null, %"struct.FieldEngine >,double,MultiPatch > >"* null, %"struct.Interval<3>"* null) nounwind - %93 = load i32* null, align 8 ; [#uses=1] - %94 = icmp sgt i32 %93, 0 ; [#uses=1] - br i1 %94, label %bb1.i, label %_Z6assignI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EES5_d13ExpressionTagI10BinaryNodeI10OpMultiply6ScalarIdESD_I5OpAdd9ReferenceI5FieldIS5_dSB_EESL_EEE8OpAssignERKSJ_IT_T0_T1_ESV_RKSJ_IT2_T3_T4_ERKT5_.exit - -bb1.i: ; preds = %bb3.i23.i.i, %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEE11totalDomainEv.exit916 - call fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EEED1Ev(%"struct.FieldEngine >,double,MultiPatchView, 3> >"* %63) nounwind - call fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EEED1Ev(%"struct.FieldEngine >,double,MultiPatchView, 3> >"* %62) nounwind - br label %bb.i17.i14.i - -bb.i17.i14.i: ; preds = %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEE14physicalDomainEv.exit26.i.i.i.i, %bb1.i - %i.0.02.rec.i.i.i = phi i32 [ %.rec.i.i.i641, %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEE14physicalDomainEv.exit26.i.i.i.i ], [ 0, %bb1.i ] ; [#uses=1] - %95 = load double* %64, align 8 ; [#uses=1] - store double %95, double* null, align 8 - call fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEEC1Id14MultiPatchViewI7GridTagS6_I5BrickELi3EEEERKS_IS5_T_T0_ERK5INodeILi3EE(%"struct.FieldEngine >,double,Remote >"* %65, %"struct.FieldEngine >,double,MultiPatchView, 3> >"* null, %"struct.INode<3>"* null) nounwind - %96 = load %"struct.Loc<3>"** null, align 4 ; <%"struct.Loc<3>"*> [#uses=1] - %97 = ptrtoint %"struct.Loc<3>"* %96 to i32 ; [#uses=1] - %.off.i21.i.i.i.i = sub i32 0, %97 ; [#uses=1] - %98 = icmp ult i32 %.off.i21.i.i.i.i, 12 ; [#uses=1] - br i1 %98, label %bb.i22.i.i.i.i, label %bb3.i25.i.i.i.i - -bb.i22.i.i.i.i: ; preds = %bb.i17.i14.i - %99 = load i32* null, align 4 ; [#uses=1] - %100 = icmp eq i32 %99, 1 ; [#uses=1] - %101 = load i32* null, align 4 ; [#uses=1] - br i1 %100, label %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEE14physicalDomainEv.exit26.i.i.i.i, label %bb6.i.i24.i.i.i.i - -bb6.i.i24.i.i.i.i: ; preds = %bb.i22.i.i.i.i - br label %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEE14physicalDomainEv.exit26.i.i.i.i - -bb3.i25.i.i.i.i: ; preds = %bb.i17.i14.i - %102 = load i32* %66, align 8 ; [#uses=2] - %103 = load i32* %67, align 4 ; [#uses=1] - %104 = load i32* %68, align 4 ; [#uses=1] - br label %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEE14physicalDomainEv.exit26.i.i.i.i - -_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEE14physicalDomainEv.exit26.i.i.i.i: ; preds = %bb3.i25.i.i.i.i, %bb6.i.i24.i.i.i.i, %bb.i22.i.i.i.i - %.rle1279 = phi i32 [ 0, %bb3.i25.i.i.i.i ], [ 0, %bb6.i.i24.i.i.i.i ], [ 0, %bb.i22.i.i.i.i ] ; [#uses=1] - %.rle1277 = phi i32 [ %102, %bb3.i25.i.i.i.i ], [ 0, %bb6.i.i24.i.i.i.i ], [ 0, %bb.i22.i.i.i.i ] ; [#uses=1] - %.rle1275 = phi i32 [ 0, %bb3.i25.i.i.i.i ], [ 0, %bb6.i.i24.i.i.i.i ], [ 0, %bb.i22.i.i.i.i ] ; [#uses=1] - %.01034.0.0.2.0.0.0.0.1.0 = phi i32 [ %104, %bb3.i25.i.i.i.i ], [ 0, %bb6.i.i24.i.i.i.i ], [ 0, %bb.i22.i.i.i.i ] ; [#uses=1] - %.01034.0.0.2.0.0.0.0.0.0 = phi i32 [ 0, %bb3.i25.i.i.i.i ], [ 0, %bb6.i.i24.i.i.i.i ], [ 0, %bb.i22.i.i.i.i ] ; [#uses=1] - %.01034.0.0.1.0.0.0.0.1.0 = phi i32 [ %103, %bb3.i25.i.i.i.i ], [ 0, %bb6.i.i24.i.i.i.i ], [ 0, %bb.i22.i.i.i.i ] ; [#uses=1] - %.01034.0.0.1.0.0.0.0.0.0 = phi i32 [ %102, %bb3.i25.i.i.i.i ], [ 0, %bb6.i.i24.i.i.i.i ], [ 0, %bb.i22.i.i.i.i ] ; [#uses=1] - %.01034.0.0.0.0.0.0.0.1.0 = phi i32 [ 0, %bb3.i25.i.i.i.i ], [ 0, %bb6.i.i24.i.i.i.i ], [ %101, %bb.i22.i.i.i.i ] ; [#uses=1] - %.01034.0.0.0.0.0.0.0.0.0 = phi i32 [ 0, %bb3.i25.i.i.i.i ], [ 0, %bb6.i.i24.i.i.i.i ], [ 0, %bb.i22.i.i.i.i ] ; [#uses=1] - %105 = sub i32 %.01034.0.0.0.0.0.0.0.0.0, %.rle1275 ; [#uses=0] - %106 = sub i32 %.01034.0.0.1.0.0.0.0.0.0, %.rle1277 ; [#uses=0] - %107 = sub i32 %.01034.0.0.2.0.0.0.0.0.0, %.rle1279 ; [#uses=0] - store i32 %.01034.0.0.0.0.0.0.0.1.0, i32* null, align 4 - store i32 %.01034.0.0.1.0.0.0.0.1.0, i32* null, align 4 - store i32 %.01034.0.0.2.0.0.0.0.1.0, i32* null, align 4 - call fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEED1Ev(%"struct.FieldEngine >,double,Remote >"* %65) nounwind - %.rec.i.i.i641 = add i32 %i.0.02.rec.i.i.i, 1 ; [#uses=1] - %108 = load %"struct.INode<3>"** null, align 4 ; <%"struct.INode<3>"*> [#uses=1] - %109 = icmp eq %"struct.INode<3>"* null, %108 ; [#uses=1] - br i1 %109, label %bb3.i23.i.i, label %bb.i17.i14.i - -bb3.i23.i.i: ; preds = %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd6RemoteI9BrickViewEE14physicalDomainEv.exit26.i.i.i.i - br label %bb1.i - -_Z6assignI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EES5_d13ExpressionTagI10BinaryNodeI10OpMultiply6ScalarIdESD_I5OpAdd9ReferenceI5FieldIS5_dSB_EESL_EEE8OpAssignERKSJ_IT_T0_T1_ESV_RKSJ_IT2_T3_T4_ERKT5_.exit: ; preds = %_ZNK11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEE11totalDomainEv.exit916 - %indvar.next = add i32 %i.0.reg2mem.0, 1 ; [#uses=2] - %exitcond = icmp eq i32 %indvar.next, 3 ; [#uses=1] - br i1 %exitcond, label %bb18, label %bb15 - -bb18: ; preds = %_Z6assignI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd14MultiPatchViewI7GridTag6RemoteI5BrickELi3EES5_d13ExpressionTagI10BinaryNodeI10OpMultiply6ScalarIdESD_I5OpAdd9ReferenceI5FieldIS5_dSB_EESL_EEE8OpAssignERKSJ_IT_T0_T1_ESV_RKSJ_IT2_T3_T4_ERKT5_.exit - call fastcc void @_ZN11FieldEngineI22UniformRectilinearMeshI10MeshTraitsILi3Ed21UniformRectilinearTag12CartesianTagLi3EEEd10MultiPatchI7GridTag6RemoteI5BrickEEEC1ERKSC_(%"struct.FieldEngine >,double,MultiPatch > >"* null, %"struct.FieldEngine >,double,MultiPatch > >"* %42) nounwind - unreachable -} diff --git a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll new file mode 100644 index 000000000000..a737591bd9fc --- /dev/null +++ b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll @@ -0,0 +1,19 @@ +; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "armv7-apple-darwin10" + +%struct.int16x8_t = type { <8 x i16> } +%struct.int16x8x2_t = type { [2 x %struct.int16x8_t] } + +define arm_apcscc void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { +entry: +;CHECK: vtrn.16 + %0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> + %1 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> + %agg.result1218.0 = getelementptr %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 0, i32 0 ; <<8 x i16>*> + store <8 x i16> %0, <8 x i16>* %agg.result1218.0, align 16 + %agg.result12.1.0 = getelementptr %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 1, i32 0 ; <<8 x i16>*> + store <8 x i16> %1, <8 x i16>* %agg.result12.1.0, align 16 + ret void +} diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll new file mode 100644 index 000000000000..5ebf2fb94ccd --- /dev/null +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +%struct.int32x4_t = type { <4 x i32> } + +define arm_apcscc void @t() nounwind { +entry: +; CHECK: vmov.I64 q15, #0 +; CHECK: vmov.32 d30[0], r0 +; CHECK: vmov q0, q15 + %tmp = alloca %struct.int32x4_t, align 16 + call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind + ret void +} diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll index 139e97b967a7..716de2ee83ca 100644 --- a/test/CodeGen/CellSPU/and_ops.ll +++ b/test/CodeGen/CellSPU/and_ops.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep and %t1.s | count 234 +; RUN: grep and %t1.s | count 230 ; RUN: grep andc %t1.s | count 85 -; RUN: grep andi %t1.s | count 37 -; RUN: grep andhi %t1.s | count 30 -; RUN: grep andbi %t1.s | count 4 +; RUN: grep andi %t1.s | count 39 +; RUN: grep andhi %t1.s | count 28 +; RUN: grep andbi %t1.s | count 2 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/call_indirect.ll b/test/CodeGen/CellSPU/call_indirect.ll index 639c794424f3..f25d6b5810f5 100644 --- a/test/CodeGen/CellSPU/call_indirect.ll +++ b/test/CodeGen/CellSPU/call_indirect.ll @@ -2,17 +2,17 @@ ; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s ; RUN: grep bisl %t1.s | count 7 ; RUN: grep ila %t1.s | count 1 -; RUN: grep rotqby %t1.s | count 6 +; RUN: grep rotqby %t1.s | count 5 ; RUN: grep lqa %t1.s | count 1 ; RUN: grep lqd %t1.s | count 12 ; RUN: grep dispatch_tab %t1.s | count 5 ; RUN: grep bisl %t2.s | count 7 ; RUN: grep ilhu %t2.s | count 2 ; RUN: grep iohl %t2.s | count 2 -; RUN: grep rotqby %t2.s | count 6 +; RUN: grep rotqby %t2.s | count 5 ; RUN: grep lqd %t2.s | count 13 ; RUN: grep ilhu %t2.s | count 2 -; RUN: grep ai %t2.s | count 9 +; RUN: grep ai %t2.s | count 8 ; RUN: grep dispatch_tab %t2.s | count 6 ; ModuleID = 'call_indirect.bc' diff --git a/test/CodeGen/MSP430/bit.ll b/test/CodeGen/MSP430/bit.ll new file mode 100644 index 000000000000..2c7836661ff6 --- /dev/null +++ b/test/CodeGen/MSP430/bit.ll @@ -0,0 +1,166 @@ +; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s +target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32" +target triple = "msp430-generic-generic" + +@foo8 = external global i8; +@bar8 = external global i8; + +define i8 @bitbrr(i8 %a, i8 %b) nounwind { + %t1 = and i8 %a, %b + %t2 = icmp ne i8 %t1, 0 + %t3 = zext i1 %t2 to i8 + ret i8 %t3 +} +; CHECK: bitbrr: +; CHECK: bit.b r14, r15 + +define i8 @bitbri(i8 %a) nounwind { + %t1 = and i8 %a, 15 + %t2 = icmp ne i8 %t1, 0 + %t3 = zext i1 %t2 to i8 + ret i8 %t3 +} +; CHECK: bitbri: +; CHECK: bit.b #15, r15 + +define i8 @bitbir(i8 %a) nounwind { + %t1 = and i8 15, %a + %t2 = icmp ne i8 %t1, 0 + %t3 = zext i1 %t2 to i8 + ret i8 %t3 +} +; CHECK: bitbir: +; CHECK: bit.b #15, r15 + +define i8 @bitbmi() nounwind { + %t1 = load i8* @foo8 + %t2 = and i8 %t1, 15 + %t3 = icmp ne i8 %t2, 0 + %t4 = zext i1 %t3 to i8 + ret i8 %t4 +} +; CHECK: bitbmi: +; CHECK: bit.b #15, &foo8 + +define i8 @bitbim() nounwind { + %t1 = load i8* @foo8 + %t2 = and i8 15, %t1 + %t3 = icmp ne i8 %t2, 0 + %t4 = zext i1 %t3 to i8 + ret i8 %t4 +} +; CHECK: bitbim: +; CHECK: bit.b #15, &foo8 + +define i8 @bitbrm(i8 %a) nounwind { + %t1 = load i8* @foo8 + %t2 = and i8 %a, %t1 + %t3 = icmp ne i8 %t2, 0 + %t4 = zext i1 %t3 to i8 + ret i8 %t4 +} +; CHECK: bitbrm: +; CHECK: bit.b &foo8, r15 + +define i8 @bitbmr(i8 %a) nounwind { + %t1 = load i8* @foo8 + %t2 = and i8 %t1, %a + %t3 = icmp ne i8 %t2, 0 + %t4 = zext i1 %t3 to i8 + ret i8 %t4 +} +; CHECK: bitbmr: +; CHECK: bit.b r15, &foo8 + +define i8 @bitbmm() nounwind { + %t1 = load i8* @foo8 + %t2 = load i8* @bar8 + %t3 = and i8 %t1, %t2 + %t4 = icmp ne i8 %t3, 0 + %t5 = zext i1 %t4 to i8 + ret i8 %t5 +} +; CHECK: bitbmm: +; CHECK: bit.b &bar8, &foo8 + +@foo16 = external global i16; +@bar16 = external global i16; + +define i16 @bitwrr(i16 %a, i16 %b) nounwind { + %t1 = and i16 %a, %b + %t2 = icmp ne i16 %t1, 0 + %t3 = zext i1 %t2 to i16 + ret i16 %t3 +} +; CHECK: bitwrr: +; CHECK: bit.w r14, r15 + +define i16 @bitwri(i16 %a) nounwind { + %t1 = and i16 %a, 4080 + %t2 = icmp ne i16 %t1, 0 + %t3 = zext i1 %t2 to i16 + ret i16 %t3 +} +; CHECK: bitwri: +; CHECK: bit.w #4080, r15 + +define i16 @bitwir(i16 %a) nounwind { + %t1 = and i16 4080, %a + %t2 = icmp ne i16 %t1, 0 + %t3 = zext i1 %t2 to i16 + ret i16 %t3 +} +; CHECK: bitwir: +; CHECK: bit.w #4080, r15 + +define i16 @bitwmi() nounwind { + %t1 = load i16* @foo16 + %t2 = and i16 %t1, 4080 + %t3 = icmp ne i16 %t2, 0 + %t4 = zext i1 %t3 to i16 + ret i16 %t4 +} +; CHECK: bitwmi: +; CHECK: bit.w #4080, &foo16 + +define i16 @bitwim() nounwind { + %t1 = load i16* @foo16 + %t2 = and i16 4080, %t1 + %t3 = icmp ne i16 %t2, 0 + %t4 = zext i1 %t3 to i16 + ret i16 %t4 +} +; CHECK: bitwim: +; CHECK: bit.w #4080, &foo16 + +define i16 @bitwrm(i16 %a) nounwind { + %t1 = load i16* @foo16 + %t2 = and i16 %a, %t1 + %t3 = icmp ne i16 %t2, 0 + %t4 = zext i1 %t3 to i16 + ret i16 %t4 +} +; CHECK: bitwrm: +; CHECK: bit.w &foo16, r15 + +define i16 @bitwmr(i16 %a) nounwind { + %t1 = load i16* @foo16 + %t2 = and i16 %t1, %a + %t3 = icmp ne i16 %t2, 0 + %t4 = zext i1 %t3 to i16 + ret i16 %t4 +} +; CHECK: bitwmr: +; CHECK: bit.w r15, &foo16 + +define i16 @bitwmm() nounwind { + %t1 = load i16* @foo16 + %t2 = load i16* @bar16 + %t3 = and i16 %t1, %t2 + %t4 = icmp ne i16 %t3, 0 + %t5 = zext i1 %t4 to i16 + ret i16 %t5 +} +; CHECK: bitwmm: +; CHECK: bit.w &bar16, &foo16 + diff --git a/test/CodeGen/MSP430/setcc.ll b/test/CodeGen/MSP430/setcc.ll new file mode 100644 index 000000000000..971d1b5be8cf --- /dev/null +++ b/test/CodeGen/MSP430/setcc.ll @@ -0,0 +1,116 @@ +; RUN: llc -march=msp430 < %s | FileCheck %s +target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32" +target triple = "msp430-generic-generic" + +define i16 @sccweqand(i16 %a, i16 %b) nounwind { + %t1 = and i16 %a, %b + %t2 = icmp eq i16 %t1, 0 + %t3 = zext i1 %t2 to i16 + ret i16 %t3 +} +; CHECK: sccweqand: +; CHECK: bit.w r14, r15 +; CHECK-NEXT: mov.w r2, r15 +; CHECK-NEXT: and.w #1, r15 +; CHECK-NEXT: xor.w #1, r15 + +define i16 @sccwneand(i16 %a, i16 %b) nounwind { + %t1 = and i16 %a, %b + %t2 = icmp ne i16 %t1, 0 + %t3 = zext i1 %t2 to i16 + ret i16 %t3 +} +; CHECK: sccwneand: +; CHECK: bit.w r14, r15 +; CHECK-NEXT: mov.w r2, r15 +; CHECK-NEXT: and.w #1, r15 + +define i16 @sccwne(i16 %a, i16 %b) nounwind { + %t1 = icmp ne i16 %a, %b + %t2 = zext i1 %t1 to i16 + ret i16 %t2 +} +; CHECK:sccwne: +; CHECK: cmp.w r15, r14 +; CHECK-NEXT: mov.w r2, r15 +; CHECK-NEXT: rra.w r15 +; CHECK-NEXT: and.w #1, r15 + +define i16 @sccweq(i16 %a, i16 %b) nounwind { + %t1 = icmp eq i16 %a, %b + %t2 = zext i1 %t1 to i16 + ret i16 %t2 +} +; CHECK:sccweq: +; CHECK: cmp.w r15, r14 +; CHECK-NEXT: mov.w r2, r15 +; CHECK-NEXT: rra.w r15 +; CHECK-NEXT: and.w #1, r15 +; CHECK-NEXT: xor.w #1, r15 + +define i16 @sccwugt(i16 %a, i16 %b) nounwind { + %t1 = icmp ugt i16 %a, %b + %t2 = zext i1 %t1 to i16 + ret i16 %t2 +} +; CHECK:sccwugt: +; CHECK: cmp.w r14, r15 +; CHECK-NEXT: mov.w r2, r15 +; CHECK-NEXT: and.w #1, r15 +; CHECK-NEXT: xor.w #1, r15 + +define i16 @sccwuge(i16 %a, i16 %b) nounwind { + %t1 = icmp uge i16 %a, %b + %t2 = zext i1 %t1 to i16 + ret i16 %t2 +} +; CHECK:sccwuge: +; CHECK: cmp.w r15, r14 +; CHECK-NEXT: mov.w r2, r15 +; CHECK-NEXT: and.w #1, r15 + +define i16 @sccwult(i16 %a, i16 %b) nounwind { + %t1 = icmp ult i16 %a, %b + %t2 = zext i1 %t1 to i16 + ret i16 %t2 +} +; CHECK:sccwult: +; CHECK: cmp.w r15, r14 +; CHECK-NEXT: mov.w r2, r15 +; CHECK-NEXT: and.w #1, r15 +; CHECK-NEXT: xor.w #1, r15 + +define i16 @sccwule(i16 %a, i16 %b) nounwind { + %t1 = icmp ule i16 %a, %b + %t2 = zext i1 %t1 to i16 + ret i16 %t2 +} +; CHECK:sccwule: +; CHECK: cmp.w r14, r15 +; CHECK-NEXT: mov.w r2, r15 +; CHECK-NEXT: and.w #1, r15 + +define i16 @sccwsgt(i16 %a, i16 %b) nounwind { + %t1 = icmp sgt i16 %a, %b + %t2 = zext i1 %t1 to i16 + ret i16 %t2 +} + +define i16 @sccwsge(i16 %a, i16 %b) nounwind { + %t1 = icmp sge i16 %a, %b + %t2 = zext i1 %t1 to i16 + ret i16 %t2 +} + +define i16 @sccwslt(i16 %a, i16 %b) nounwind { + %t1 = icmp slt i16 %a, %b + %t2 = zext i1 %t1 to i16 + ret i16 %t2 +} + +define i16 @sccwsle(i16 %a, i16 %b) nounwind { + %t1 = icmp sle i16 %a, %b + %t2 = zext i1 %t1 to i16 + ret i16 %t2 +} + diff --git a/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll new file mode 100644 index 000000000000..79ad0a912650 --- /dev/null +++ b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll @@ -0,0 +1,128 @@ +; RUN: opt < %s -std-compile-opts | \ +; RUN: llc -mtriple=thumbv7-apple-darwin10 -mattr=+neon | FileCheck %s + +define arm_apcscc void @fred(i32 %three_by_three, i8* %in, double %dt1, i32 %x_size, i32 %y_size, i8* %bp) nounwind { +entry: +; -- The loop following the load should only use a single add-literation +; instruction. +; CHECK: ldr.64 +; CHECK: adds r{{[0-9]+}}, #1 +; CHECK-NOT: adds r{{[0-9]+}}, #1 +; CHECK: subsections_via_symbols + + + %three_by_three_addr = alloca i32 ; [#uses=2] + %in_addr = alloca i8* ; [#uses=2] + %dt_addr = alloca float ; [#uses=4] + %x_size_addr = alloca i32 ; [#uses=2] + %y_size_addr = alloca i32 ; [#uses=1] + %bp_addr = alloca i8* ; [#uses=1] + %tmp_image = alloca i8* ; [#uses=0] + %out = alloca i8* ; [#uses=1] + %cp = alloca i8* ; [#uses=0] + %dpt = alloca i8* ; [#uses=4] + %dp = alloca i8* ; [#uses=2] + %ip = alloca i8* ; [#uses=0] + %centre = alloca i32 ; [#uses=0] + %tmp = alloca i32 ; [#uses=0] + %brightness = alloca i32 ; [#uses=0] + %area = alloca i32 ; [#uses=0] + %y = alloca i32 ; [#uses=0] + %x = alloca i32 ; [#uses=2] + %j = alloca i32 ; [#uses=6] + %i = alloca i32 ; [#uses=1] + %mask_size = alloca i32 ; [#uses=5] + %increment = alloca i32 ; [#uses=1] + %n_max = alloca i32 ; [#uses=4] + %temp = alloca float ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 %three_by_three, i32* %three_by_three_addr + store i8* %in, i8** %in_addr + %dt = fptrunc double %dt1 to float ; [#uses=1] + store float %dt, float* %dt_addr + store i32 %x_size, i32* %x_size_addr + store i32 %y_size, i32* %y_size_addr + store i8* %bp, i8** %bp_addr + %0 = load i8** %in_addr, align 4 ; [#uses=1] + store i8* %0, i8** %out, align 4 + %1 = call arm_apcscc i32 (...)* @foo() nounwind ; [#uses=1] + store i32 %1, i32* %i, align 4 + %2 = load i32* %three_by_three_addr, align 4 ; [#uses=1] + %3 = icmp eq i32 %2, 0 ; [#uses=1] + br i1 %3, label %bb, label %bb2 + +bb: ; preds = %entry + %4 = load float* %dt_addr, align 4 ; [#uses=1] + %5 = fpext float %4 to double ; [#uses=1] + %6 = fmul double %5, 1.500000e+00 ; [#uses=1] + %7 = fptosi double %6 to i32 ; [#uses=1] + %8 = add nsw i32 %7, 1 ; [#uses=1] + store i32 %8, i32* %mask_size, align 4 + br label %bb3 + +bb2: ; preds = %entry + store i32 1, i32* %mask_size, align 4 + br label %bb3 + +bb3: ; preds = %bb2, %bb + %9 = load i32* %mask_size, align 4 ; [#uses=1] + %10 = mul i32 %9, 2 ; [#uses=1] + %11 = add nsw i32 %10, 1 ; [#uses=1] + store i32 %11, i32* %n_max, align 4 + %12 = load i32* %x_size_addr, align 4 ; [#uses=1] + %13 = load i32* %n_max, align 4 ; [#uses=1] + %14 = sub i32 %12, %13 ; [#uses=1] + store i32 %14, i32* %increment, align 4 + %15 = load i32* %n_max, align 4 ; [#uses=1] + %16 = load i32* %n_max, align 4 ; [#uses=1] + %17 = mul i32 %15, %16 ; [#uses=1] + %18 = call arm_apcscc noalias i8* @malloc(i32 %17) nounwind ; [#uses=1] + store i8* %18, i8** %dp, align 4 + %19 = load i8** %dp, align 4 ; [#uses=1] + store i8* %19, i8** %dpt, align 4 + %20 = load float* %dt_addr, align 4 ; [#uses=1] + %21 = load float* %dt_addr, align 4 ; [#uses=1] + %22 = fmul float %20, %21 ; [#uses=1] + %23 = fsub float -0.000000e+00, %22 ; [#uses=1] + store float %23, float* %temp, align 4 + %24 = load i32* %mask_size, align 4 ; [#uses=1] + %25 = sub i32 0, %24 ; [#uses=1] + store i32 %25, i32* %j, align 4 + br label %bb5 + +bb4: ; preds = %bb5 + %26 = load i32* %j, align 4 ; [#uses=1] + %27 = load i32* %j, align 4 ; [#uses=1] + %28 = mul i32 %26, %27 ; [#uses=1] + %29 = sitofp i32 %28 to double ; [#uses=1] + %30 = fmul double %29, 1.234000e+00 ; [#uses=1] + %31 = fptosi double %30 to i32 ; [#uses=1] + store i32 %31, i32* %x, align 4 + %32 = load i32* %x, align 4 ; [#uses=1] + %33 = trunc i32 %32 to i8 ; [#uses=1] + %34 = load i8** %dpt, align 4 ; [#uses=1] + store i8 %33, i8* %34, align 1 + %35 = load i8** %dpt, align 4 ; [#uses=1] + %36 = getelementptr inbounds i8* %35, i64 1 ; [#uses=1] + store i8* %36, i8** %dpt, align 4 + %37 = load i32* %j, align 4 ; [#uses=1] + %38 = add nsw i32 %37, 1 ; [#uses=1] + store i32 %38, i32* %j, align 4 + br label %bb5 + +bb5: ; preds = %bb4, %bb3 + %39 = load i32* %j, align 4 ; [#uses=1] + %40 = load i32* %mask_size, align 4 ; [#uses=1] + %41 = icmp sle i32 %39, %40 ; [#uses=1] + br i1 %41, label %bb4, label %bb6 + +bb6: ; preds = %bb5 + br label %return + +return: ; preds = %bb6 + ret void +} + +declare arm_apcscc i32 @foo(...) + +declare arm_apcscc noalias i8* @malloc(i32) nounwind diff --git a/test/CodeGen/Thumb2/large-stack.ll b/test/CodeGen/Thumb2/large-stack.ll index 6f5996174ac3..da44cdea0fb6 100644 --- a/test/CodeGen/Thumb2/large-stack.ll +++ b/test/CodeGen/Thumb2/large-stack.ll @@ -18,7 +18,7 @@ define void @test2() { define i32 @test3() { ; CHECK: test3: ; CHECK: sub.w sp, sp, #805306368 -; CHECK: sub sp, #24 +; CHECK: sub sp, #20 %retval = alloca i32, align 4 %tmp = alloca i32, align 4 %a = alloca [805306369 x i8], align 16 diff --git a/test/CodeGen/Thumb2/thumb2-spill-q.ll b/test/CodeGen/Thumb2/thumb2-spill-q.ll index aef167b07f7f..2b087893fd6a 100644 --- a/test/CodeGen/Thumb2/thumb2-spill-q.ll +++ b/test/CodeGen/Thumb2/thumb2-spill-q.ll @@ -11,7 +11,7 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly define arm_apcscc void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: -; CHECK: bic sp, sp, #15 +; CHECK: bic r4, r4, #15 ; CHECK: vst1.64 {{.*}}sp, :128 ; CHECK: vld1.64 {{.*}}sp, :128 entry: diff --git a/test/CodeGen/X86/2007-01-08-InstrSched.ll b/test/CodeGen/X86/2007-01-08-InstrSched.ll index 81f0a1d7244d..317ed0a4f7d3 100644 --- a/test/CodeGen/X86/2007-01-08-InstrSched.ll +++ b/test/CodeGen/X86/2007-01-08-InstrSched.ll @@ -1,5 +1,5 @@ ; PR1075 -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -O3 | FileCheck %s define float @foo(float %x) nounwind { %tmp1 = fmul float %x, 3.000000e+00 diff --git a/test/CodeGen/X86/2009-09-10-SpillComments.ll b/test/CodeGen/X86/2009-09-10-SpillComments.ll index 8c62f4dbe0be..1dd9990e71a5 100644 --- a/test/CodeGen/X86/2009-09-10-SpillComments.ll +++ b/test/CodeGen/X86/2009-09-10-SpillComments.ll @@ -1,6 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Spill" -; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Folded Spill" -; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Reload" +; RUN: llc < %s -mtriple=x86_64-unknown-linux | FileCheck %s %struct..0anon = type { i32 } %struct.rtvec_def = type { i32, [1 x %struct..0anon] } @@ -12,6 +10,9 @@ declare %struct.rtx_def* @fixup_memory_subreg(%struct.rtx_def*, %struct.rtx_def* define %struct.rtx_def* @walk_fixup_memory_subreg(%struct.rtx_def* %x, %struct.rtx_def* %insn) { entry: +; CHECK: Spill +; CHECK: Folded Spill +; CHECK: Reload %tmp2 = icmp eq %struct.rtx_def* %x, null ; [#uses=1] br i1 %tmp2, label %UnifiedReturnBlock, label %cond_next @@ -32,7 +33,7 @@ cond_true13: ; preds = %cond_next br i1 %tmp22, label %cond_true25, label %cond_next32 cond_true25: ; preds = %cond_true13 - %tmp29 = tail call %struct.rtx_def* @fixup_memory_subreg( %struct.rtx_def* %x, %struct.rtx_def* %insn, i32 1 ) ; <%struct.rtx_def*> [#uses=1] + %tmp29 = tail call %struct.rtx_def* @fixup_memory_subreg( %struct.rtx_def* %x, %struct.rtx_def* %insn, i32 1 ) nounwind ; <%struct.rtx_def*> [#uses=1] ret %struct.rtx_def* %tmp29 cond_next32: ; preds = %cond_true13, %cond_next @@ -58,7 +59,7 @@ cond_true47: ; preds = %bb %tmp52 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0 ; <%struct..0anon*> [#uses=1] %tmp5354 = bitcast %struct..0anon* %tmp52 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=1] %tmp55 = load %struct.rtx_def** %tmp5354 ; <%struct.rtx_def*> [#uses=1] - %tmp58 = tail call %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp55, %struct.rtx_def* %insn ) ; <%struct.rtx_def*> [#uses=1] + %tmp58 = tail call %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp55, %struct.rtx_def* %insn ) nounwind ; <%struct.rtx_def*> [#uses=1] %tmp62 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0, i32 0 ; [#uses=1] %tmp58.c = ptrtoint %struct.rtx_def* %tmp58 to i32 ; [#uses=1] store i32 %tmp58.c, i32* %tmp62 @@ -81,7 +82,7 @@ bb73: ; preds = %bb73, %bb105.preheader %tmp92 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019 ; <%struct..0anon*> [#uses=1] %tmp9394 = bitcast %struct..0anon* %tmp92 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=1] %tmp95 = load %struct.rtx_def** %tmp9394 ; <%struct.rtx_def*> [#uses=1] - %tmp98 = tail call %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp95, %struct.rtx_def* %insn ) ; <%struct.rtx_def*> [#uses=1] + %tmp98 = tail call %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp95, %struct.rtx_def* %insn ) nounwind ; <%struct.rtx_def*> [#uses=1] %tmp101 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019, i32 0 ; [#uses=1] %tmp98.c = ptrtoint %struct.rtx_def* %tmp98 to i32 ; [#uses=1] store i32 %tmp98.c, i32* %tmp101 diff --git a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll index d372da336769..8cb538b07359 100644 --- a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll +++ b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10 -post-RA-scheduler=true | FileCheck %s ; PR4958 diff --git a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll new file mode 100644 index 000000000000..1e7a418d1d67 --- /dev/null +++ b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; pr5391 + +define void @t() nounwind ssp { +entry: +; CHECK: t: +; CHECK: movl %ecx, %eax +; CHECK: %eax = foo (%eax, %ecx) + %b = alloca i32 ; [#uses=2] + %a = alloca i32 ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = load i32* %b, align 4 ; [#uses=1] + %1 = load i32* %b, align 4 ; [#uses=1] + %asmtmp = call i32 asm "$0 = foo ($1, $2)", "=&{ax},%0,r,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1) nounwind ; [#uses=1] + store i32 %asmtmp, i32* %a + br label %return + +return: ; preds = %entry + ret void +} + +define void @t2() nounwind ssp { +entry: +; CHECK: t2: +; CHECK: movl %eax, %ecx +; CHECK: %ecx = foo (%ecx, %eax) + %b = alloca i32 ; [#uses=2] + %a = alloca i32 ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = load i32* %b, align 4 ; [#uses=1] + %1 = load i32* %b, align 4 ; [#uses=1] + %asmtmp = call i32 asm "$0 = foo ($1, $2)", "=&r,%0,r,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1) nounwind ; [#uses=1] + store i32 %asmtmp, i32* %a + br label %return + +return: ; preds = %entry + ret void +} diff --git a/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll b/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll new file mode 100644 index 000000000000..f7ba661c4f75 --- /dev/null +++ b/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll @@ -0,0 +1,63 @@ +; RUN: llc -relocation-model=pic < %s | FileCheck %s +; PR5723 +target datalayout = "e-p:64:64" +target triple = "x86_64-unknown-linux-gnu" + +%0 = type { [1 x i64] } +%link = type { %0* } +%test = type { i32, %link } + +@data = global [2 x i64] zeroinitializer, align 64 ; <[2 x i64]*> [#uses=1] +@ptr = linkonce thread_local global [1 x i64] [i64 ptrtoint ([2 x i64]* @data to i64)], align 64 ; <[1 x i64]*> [#uses=1] +@link_ptr = linkonce thread_local global [1 x i64] zeroinitializer, align 64 ; <[1 x i64]*> [#uses=1] +@_dm_my_pe = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0] +@_dm_pes_in_prog = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0] +@_dm_npes_div_mult = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0] +@_dm_npes_div_shift = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0] +@_dm_pe_addr_loc = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0] +@_dm_offset_addr_mask = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0] + +define void @leaf() nounwind { +; CHECK: leaf: +; CHECK-NOT: -8(%rsp) +; CHECK: leaq link_ptr@TLSGD +; CHECK: call __tls_get_addr@PLT +"file foo2.c, line 14, bb1": + %p = alloca %test*, align 8 ; <%test**> [#uses=4] + br label %"file foo2.c, line 14, bb2" + +"file foo2.c, line 14, bb2": ; preds = %"file foo2.c, line 14, bb1" + br label %"@CFE_debug_label_0" + +"@CFE_debug_label_0": ; preds = %"file foo2.c, line 14, bb2" + %r = load %test** bitcast ([1 x i64]* @ptr to %test**), align 8 ; <%test*> [#uses=1] + store %test* %r, %test** %p, align 8 + br label %"@CFE_debug_label_2" + +"@CFE_debug_label_2": ; preds = %"@CFE_debug_label_0" + %r1 = load %link** bitcast ([1 x i64]* @link_ptr to %link**), align 8 ; <%link*> [#uses=1] + %r2 = load %test** %p, align 8 ; <%test*> [#uses=1] + %r3 = ptrtoint %test* %r2 to i64 ; [#uses=1] + %r4 = inttoptr i64 %r3 to %link** ; <%link**> [#uses=1] + %r5 = getelementptr %link** %r4, i64 1 ; <%link**> [#uses=1] + store %link* %r1, %link** %r5, align 8 + br label %"@CFE_debug_label_3" + +"@CFE_debug_label_3": ; preds = %"@CFE_debug_label_2" + %r6 = load %test** %p, align 8 ; <%test*> [#uses=1] + %r7 = ptrtoint %test* %r6 to i64 ; [#uses=1] + %r8 = inttoptr i64 %r7 to %link* ; <%link*> [#uses=1] + %r9 = getelementptr %link* %r8, i64 1 ; <%link*> [#uses=1] + store %link* %r9, %link** bitcast ([1 x i64]* @link_ptr to %link**), align 8 + br label %"@CFE_debug_label_4" + +"@CFE_debug_label_4": ; preds = %"@CFE_debug_label_3" + %r10 = load %test** %p, align 8 ; <%test*> [#uses=1] + %r11 = ptrtoint %test* %r10 to i64 ; [#uses=1] + %r12 = inttoptr i64 %r11 to i32* ; [#uses=1] + store i32 1, i32* %r12, align 4 + br label %"@CFE_debug_label_5" + +"@CFE_debug_label_5": ; preds = %"@CFE_debug_label_4" + ret void +} diff --git a/test/CodeGen/X86/2009-12-12-CoalescerBug.ll b/test/CodeGen/X86/2009-12-12-CoalescerBug.ll new file mode 100644 index 000000000000..4e8f5fdc530d --- /dev/null +++ b/test/CodeGen/X86/2009-12-12-CoalescerBug.ll @@ -0,0 +1,40 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s + +define i32 @do_loop(i32* nocapture %sdp, i32* nocapture %ddp, i8* %mdp, i8* nocapture %cdp, i32 %w) nounwind readonly optsize ssp { +entry: + br label %bb + +bb: ; preds = %bb5, %entry + %mask.1.in = load i8* undef, align 1 ; [#uses=3] + %0 = icmp eq i8 %mask.1.in, 0 ; [#uses=1] + br i1 %0, label %bb5, label %bb1 + +bb1: ; preds = %bb + br i1 undef, label %bb2, label %bb3 + +bb2: ; preds = %bb1 +; CHECK: %bb2 +; CHECK: movb %ch, %al + %1 = zext i8 %mask.1.in to i32 ; [#uses=1] + %2 = zext i8 undef to i32 ; [#uses=1] + %3 = mul i32 %2, %1 ; [#uses=1] + %4 = add i32 %3, 1 ; [#uses=1] + %5 = add i32 %4, 0 ; [#uses=1] + %6 = lshr i32 %5, 8 ; [#uses=1] + %retval12.i = trunc i32 %6 to i8 ; [#uses=1] + br label %bb3 + +bb3: ; preds = %bb2, %bb1 + %mask.0.in = phi i8 [ %retval12.i, %bb2 ], [ %mask.1.in, %bb1 ] ; [#uses=1] + %7 = icmp eq i8 %mask.0.in, 0 ; [#uses=1] + br i1 %7, label %bb5, label %bb4 + +bb4: ; preds = %bb3 + br label %bb5 + +bb5: ; preds = %bb4, %bb3, %bb + br i1 undef, label %bb6, label %bb + +bb6: ; preds = %bb5 + ret i32 undef +} diff --git a/test/CodeGen/X86/3addr-16bit.ll b/test/CodeGen/X86/3addr-16bit.ll new file mode 100644 index 000000000000..c51247ab925a --- /dev/null +++ b/test/CodeGen/X86/3addr-16bit.ll @@ -0,0 +1,95 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -asm-verbose=false | FileCheck %s -check-prefix=64BIT +; rdar://7329206 + +; In 32-bit the partial register stall would degrade performance. + +define zeroext i16 @t1(i16 zeroext %c, i16 zeroext %k) nounwind ssp { +entry: +; 32BIT: t1: +; 32BIT: movw 20(%esp), %ax +; 32BIT-NOT: movw %ax, %cx +; 32BIT: leal 1(%eax), %ecx + +; 64BIT: t1: +; 64BIT-NOT: movw %si, %ax +; 64BIT: leal 1(%rsi), %eax + %0 = icmp eq i16 %k, %c ; [#uses=1] + %1 = add i16 %k, 1 ; [#uses=3] + br i1 %0, label %bb, label %bb1 + +bb: ; preds = %entry + tail call void @foo(i16 zeroext %1) nounwind + ret i16 %1 + +bb1: ; preds = %entry + ret i16 %1 +} + +define zeroext i16 @t2(i16 zeroext %c, i16 zeroext %k) nounwind ssp { +entry: +; 32BIT: t2: +; 32BIT: movw 20(%esp), %ax +; 32BIT-NOT: movw %ax, %cx +; 32BIT: leal -1(%eax), %ecx + +; 64BIT: t2: +; 64BIT-NOT: movw %si, %ax +; 64BIT: leal -1(%rsi), %eax + %0 = icmp eq i16 %k, %c ; [#uses=1] + %1 = add i16 %k, -1 ; [#uses=3] + br i1 %0, label %bb, label %bb1 + +bb: ; preds = %entry + tail call void @foo(i16 zeroext %1) nounwind + ret i16 %1 + +bb1: ; preds = %entry + ret i16 %1 +} + +declare void @foo(i16 zeroext) + +define zeroext i16 @t3(i16 zeroext %c, i16 zeroext %k) nounwind ssp { +entry: +; 32BIT: t3: +; 32BIT: movw 20(%esp), %ax +; 32BIT-NOT: movw %ax, %cx +; 32BIT: leal 2(%eax), %ecx + +; 64BIT: t3: +; 64BIT-NOT: movw %si, %ax +; 64BIT: leal 2(%rsi), %eax + %0 = add i16 %k, 2 ; [#uses=3] + %1 = icmp eq i16 %k, %c ; [#uses=1] + br i1 %1, label %bb, label %bb1 + +bb: ; preds = %entry + tail call void @foo(i16 zeroext %0) nounwind + ret i16 %0 + +bb1: ; preds = %entry + ret i16 %0 +} + +define zeroext i16 @t4(i16 zeroext %c, i16 zeroext %k) nounwind ssp { +entry: +; 32BIT: t4: +; 32BIT: movw 16(%esp), %ax +; 32BIT: movw 20(%esp), %cx +; 32BIT-NOT: movw %cx, %dx +; 32BIT: leal (%ecx,%eax), %edx + +; 64BIT: t4: +; 64BIT-NOT: movw %si, %ax +; 64BIT: leal (%rsi,%rdi), %eax + %0 = add i16 %k, %c ; [#uses=3] + %1 = icmp eq i16 %k, %c ; [#uses=1] + br i1 %1, label %bb, label %bb1 + +bb: ; preds = %entry + tail call void @foo(i16 zeroext %0) nounwind + ret i16 %0 + +bb1: ; preds = %entry + ret i16 %0 +} diff --git a/test/CodeGen/X86/fastcc3struct.ll b/test/CodeGen/X86/fastcc3struct.ll new file mode 100644 index 000000000000..84f8ef6cf360 --- /dev/null +++ b/test/CodeGen/X86/fastcc3struct.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=x86 -o %t +; RUN: grep "movl .48, %ecx" %t +; RUN: grep "movl .24, %edx" %t +; RUN: grep "movl .12, %eax" %t + +%0 = type { i32, i32, i32 } + +define internal fastcc %0 @ReturnBigStruct() nounwind readnone { +entry: + %0 = insertvalue %0 zeroinitializer, i32 12, 0 + %1 = insertvalue %0 %0, i32 24, 1 + %2 = insertvalue %0 %1, i32 48, 2 + ret %0 %2 +} + diff --git a/test/CodeGen/X86/select-aggregate.ll b/test/CodeGen/X86/select-aggregate.ll new file mode 100644 index 000000000000..822e5946d342 --- /dev/null +++ b/test/CodeGen/X86/select-aggregate.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; PR5757 + +; CHECK: cmovne %rdi, %rsi +; CHECK: movl (%rsi), %eax + +%0 = type { i64, i32 } + +define i32 @foo(%0* %p, %0* %q, i1 %r) nounwind { + %t0 = load %0* %p + %t1 = load %0* %q + %t4 = select i1 %r, %0 %t0, %0 %t1 + %t5 = extractvalue %0 %t4, 1 + ret i32 %t5 +} diff --git a/test/CodeGen/X86/setcc.ll b/test/CodeGen/X86/setcc.ll new file mode 100644 index 000000000000..42ce4c1c1d57 --- /dev/null +++ b/test/CodeGen/X86/setcc.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; XFAIL: * +; rdar://7329206 + +; Use sbb x, x to materialize carry bit in a GPR. The value is either +; all 1's or all 0's. + +define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp { +entry: +; CHECK: t1: +; CHECK: seta %al +; CHECK: movzbl %al, %eax +; CHECK: shll $5, %eax + %0 = icmp ugt i16 %x, 26 ; [#uses=1] + %iftmp.1.0 = select i1 %0, i16 32, i16 0 ; [#uses=1] + ret i16 %iftmp.1.0 +} + +define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp { +entry: +; CHECK: t2: +; CHECK: sbbl %eax, %eax +; CHECK: andl $32, %eax + %0 = icmp ult i16 %x, 26 ; [#uses=1] + %iftmp.0.0 = select i1 %0, i16 32, i16 0 ; [#uses=1] + ret i16 %iftmp.0.0 +} + +define i64 @t3(i64 %x) nounwind readnone ssp { +entry: +; CHECK: t3: +; CHECK: sbbq %rax, %rax +; CHECK: andq $64, %rax + %0 = icmp ult i64 %x, 18 ; [#uses=1] + %iftmp.2.0 = select i1 %0, i64 64, i64 0 ; [#uses=1] + ret i64 %iftmp.2.0 +} diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index f8d542e525c6..01d73736d6c2 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu | FileCheck %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true | FileCheck %s ; Currently, floating-point selects are lowered to CFG triangles. ; This means that one side of the select is always unconditionally diff --git a/test/CodeGen/X86/splat-scalar-load.ll b/test/CodeGen/X86/splat-scalar-load.ll new file mode 100644 index 000000000000..32d3ab661d18 --- /dev/null +++ b/test/CodeGen/X86/splat-scalar-load.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 | FileCheck %s +; rdar://7434544 + +define <2 x i64> @t1() nounwind ssp { +entry: +; CHECK: t1: +; CHECK: pshufd $0, (%esp), %xmm0 + %array = alloca [8 x float], align 16 + %arrayidx = getelementptr inbounds [8 x float]* %array, i32 0, i32 0 + %tmp2 = load float* %arrayidx + %vecinit = insertelement <4 x float> undef, float %tmp2, i32 0 + %vecinit5 = insertelement <4 x float> %vecinit, float %tmp2, i32 1 + %vecinit7 = insertelement <4 x float> %vecinit5, float %tmp2, i32 2 + %vecinit9 = insertelement <4 x float> %vecinit7, float %tmp2, i32 3 + %0 = bitcast <4 x float> %vecinit9 to <2 x i64> + ret <2 x i64> %0 +} + +define <2 x i64> @t2() nounwind ssp { +entry: +; CHECK: t2: +; CHECK: pshufd $85, (%esp), %xmm0 + %array = alloca [8 x float], align 4 + %arrayidx = getelementptr inbounds [8 x float]* %array, i32 0, i32 1 + %tmp2 = load float* %arrayidx + %vecinit = insertelement <4 x float> undef, float %tmp2, i32 0 + %vecinit5 = insertelement <4 x float> %vecinit, float %tmp2, i32 1 + %vecinit7 = insertelement <4 x float> %vecinit5, float %tmp2, i32 2 + %vecinit9 = insertelement <4 x float> %vecinit7, float %tmp2, i32 3 + %0 = bitcast <4 x float> %vecinit9 to <2 x i64> + ret <2 x i64> %0 +} + +define <4 x float> @t3(float %tmp1, float %tmp2, float %tmp3) nounwind readnone ssp { +entry: +; CHECK: t3: +; CHECK: pshufd $-86, (%esp), %xmm0 + %0 = insertelement <4 x float> undef, float %tmp3, i32 0 + %1 = insertelement <4 x float> %0, float %tmp3, i32 1 + %2 = insertelement <4 x float> %1, float %tmp3, i32 2 + %3 = insertelement <4 x float> %2, float %tmp3, i32 3 + ret <4 x float> %3 +} diff --git a/test/CodeGen/X86/sse2.ll b/test/CodeGen/X86/sse2.ll index 58fe28b09fe9..f2b8010d4138 100644 --- a/test/CodeGen/X86/sse2.ll +++ b/test/CodeGen/X86/sse2.ll @@ -1,5 +1,5 @@ ; Tests for SSE2 and below, without SSE3+. -; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 -O3 | FileCheck %s define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { %tmp3 = load <2 x double>* %A, align 16 diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 21c1a3c81223..5550d263389a 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -1,6 +1,6 @@ ; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+. -; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9\ +; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9 -O3 \ ; RUN: | FileCheck %s --check-prefix=X64 ; Test for v8xi16 lowering where we extract the first element of the vector and diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll index 0d86e561325c..c70c9fadd2c5 100644 --- a/test/CodeGen/X86/tail-opts.ll +++ b/test/CodeGen/X86/tail-opts.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false | FileCheck %s +; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false -post-RA-scheduler=true | FileCheck %s declare void @bar(i32) declare void @car(i32) diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll index 69018aa13dd2..d05dff8928ba 100644 --- a/test/CodeGen/X86/tailcallstack64.ll +++ b/test/CodeGen/X86/tailcallstack64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -tailcallopt -march=x86-64 | FileCheck %s +; RUN: llc < %s -tailcallopt -march=x86-64 -post-RA-scheduler=true | FileCheck %s ; Check that lowered arguments on the stack do not overwrite each other. ; Add %in1 %p1 to a different temporary register (%eax). diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll index 7dddcda8dde8..7778983e2855 100644 --- a/test/CodeGen/X86/unaligned-load.ll +++ b/test/CodeGen/X86/unaligned-load.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic | not grep {movaps\t_.str3} ; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic | FileCheck %s @.str1 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 8 diff --git a/test/CodeGen/X86/vec-trunc-store.ll b/test/CodeGen/X86/vec-trunc-store.ll new file mode 100644 index 000000000000..ea1a151a5916 --- /dev/null +++ b/test/CodeGen/X86/vec-trunc-store.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=x86-64 -disable-mmx | grep punpcklwd | count 2 + +define void @foo() nounwind { + %cti69 = trunc <8 x i32> undef to <8 x i16> ; <<8 x i16>> [#uses=1] + store <8 x i16> %cti69, <8 x i16>* undef + ret void +} + +define void @bar() nounwind { + %cti44 = trunc <4 x i32> undef to <4 x i16> ; <<4 x i16>> [#uses=1] + store <4 x i16> %cti44, <4 x i16>* undef + ret void +} diff --git a/test/CodeGen/X86/vec_compare-2.ll b/test/CodeGen/X86/vec_compare-2.ll new file mode 100644 index 000000000000..091641b3bc3b --- /dev/null +++ b/test/CodeGen/X86/vec_compare-2.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx | FileCheck %s + +declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone + +declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readnone + +declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone + +define void @blackDespeckle_wrapper(i8** %args_list, i64* %gtid, i64 %xend) { +entry: +; CHECK-NOT: set +; CHECK: pcmpgt +; CHECK: blendvps + %shr.i = ashr <4 x i32> zeroinitializer, ; <<4 x i32>> [#uses=1] + %cmp318.i = sext <4 x i1> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=1] + %sub322.i = sub <4 x i32> %shr.i, zeroinitializer ; <<4 x i32>> [#uses=1] + %cmp323.x = icmp slt <4 x i32> zeroinitializer, %sub322.i ; <<4 x i1>> [#uses=1] + %cmp323.i = sext <4 x i1> %cmp323.x to <4 x i32> ; <<4 x i32>> [#uses=1] + %or.i = or <4 x i32> %cmp318.i, %cmp323.i ; <<4 x i32>> [#uses=1] + %tmp10.i83.i = bitcast <4 x i32> %or.i to <4 x float> ; <<4 x float>> [#uses=1] + %0 = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> undef, <4 x float> undef, <4 x float> %tmp10.i83.i) nounwind ; <<4 x float>> [#uses=1] + %conv.i.i15.i = bitcast <4 x float> %0 to <4 x i32> ; <<4 x i32>> [#uses=1] + %swz.i.i28.i = shufflevector <4 x i32> %conv.i.i15.i, <4 x i32> undef, <2 x i32> ; <<2 x i32>> [#uses=1] + %tmp6.i29.i = bitcast <2 x i32> %swz.i.i28.i to <4 x i16> ; <<4 x i16>> [#uses=1] + %swz.i30.i = shufflevector <4 x i16> %tmp6.i29.i, <4 x i16> undef, <2 x i32> ; <<2 x i16>> [#uses=1] + store <2 x i16> %swz.i30.i, <2 x i16>* undef + unreachable + ret void +} diff --git a/test/CodeGen/X86/vec_ext_inreg.ll b/test/CodeGen/X86/vec_ext_inreg.ll new file mode 100644 index 000000000000..02b16a79f4a0 --- /dev/null +++ b/test/CodeGen/X86/vec_ext_inreg.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=x86-64 + +define <8 x i32> @a(<8 x i32> %a) nounwind { + %b = trunc <8 x i32> %a to <8 x i16> + %c = sext <8 x i16> %b to <8 x i32> + ret <8 x i32> %c +} + +define <3 x i32> @b(<3 x i32> %a) nounwind { + %b = trunc <3 x i32> %a to <3 x i16> + %c = sext <3 x i16> %b to <3 x i32> + ret <3 x i32> %c +} + +define <1 x i32> @c(<1 x i32> %a) nounwind { + %b = trunc <1 x i32> %a to <1 x i16> + %c = sext <1 x i16> %b to <1 x i32> + ret <1 x i32> %c +} + +define <8 x i32> @d(<8 x i32> %a) nounwind { + %b = trunc <8 x i32> %a to <8 x i16> + %c = zext <8 x i16> %b to <8 x i32> + ret <8 x i32> %c +} + +define <3 x i32> @e(<3 x i32> %a) nounwind { + %b = trunc <3 x i32> %a to <3 x i16> + %c = zext <3 x i16> %b to <3 x i32> + ret <3 x i32> %c +} + +define <1 x i32> @f(<1 x i32> %a) nounwind { + %b = trunc <1 x i32> %a to <1 x i16> + %c = zext <1 x i16> %b to <1 x i32> + ret <1 x i32> %c +} diff --git a/test/CodeGen/X86/widen_arith-3.ll b/test/CodeGen/X86/widen_arith-3.ll index a2b8b8291ead..1f2c25068ca4 100644 --- a/test/CodeGen/X86/widen_arith-3.ll +++ b/test/CodeGen/X86/widen_arith-3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -post-RA-scheduler=true | FileCheck %s ; CHECK: paddw ; CHECK: pextrw ; CHECK: movd diff --git a/test/CodeGen/X86/zext-shl.ll b/test/CodeGen/X86/zext-shl.ll new file mode 100644 index 000000000000..928848e3f7a2 --- /dev/null +++ b/test/CodeGen/X86/zext-shl.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=x86 | FileCheck %s + +define i32 @t1(i8 zeroext %x) nounwind readnone ssp { +entry: +; CHECK: t1: +; CHECK: shll +; CHECK-NOT: movzwl +; CHECK: ret + %0 = zext i8 %x to i16 + %1 = shl i16 %0, 5 + %2 = zext i16 %1 to i32 + ret i32 %2 +} + +define i32 @t2(i8 zeroext %x) nounwind readnone ssp { +entry: +; CHECK: t2: +; CHECK: shrl +; CHECK-NOT: movzwl +; CHECK: ret + %0 = zext i8 %x to i16 + %1 = lshr i16 %0, 3 + %2 = zext i16 %1 to i32 + ret i32 %2 +} -- cgit v1.3