From 67c32a98315f785a9ec9d531c1f571a0196c7463 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Sun, 18 Jan 2015 16:17:27 +0000 Subject: Vendor import of llvm RELEASE_360/rc1 tag r226102 (effectively, 3.6.0 RC1): https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_360/rc1@226102 --- test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll') diff --git a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll index f4edf092641f..26b294042d42 100644 --- a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll +++ b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll @@ -201,7 +201,7 @@ for.end: ; preds = %for.body ; ; Currently we have three extra add.w's that keep the store address ; live past the next increment because ISEL is unfortunately undoing -; the store chain. ISEL also fails to convert the stores to +; the store chain. ISEL also fails to convert all but one of the stores to ; post-increment addressing. However, the loads should use ; post-increment addressing, no add's or add.w's beyond the three ; mentioned. Most importantly, there should be no spills or reloads! @@ -210,7 +210,7 @@ for.end: ; preds = %for.body ; A9: %.lr.ph ; A9-NOT: lsl.w ; A9-NOT: {{ldr|str|adds|add r}} -; A9: add.w r +; A9: vst1.8 {{.*}} [r{{[0-9]+}}]! ; A9-NOT: {{ldr|str|adds|add r}} ; A9: add.w r ; A9-NOT: {{ldr|str|adds|add r}} -- cgit v1.2.3