From 4a16efa3e43e35f0cc9efe3a67f620f0017c3d36 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Mon, 8 Apr 2013 18:41:23 +0000 Subject: Vendor import of llvm trunk r178860: http://llvm.org/svn/llvm-project/llvm/trunk@178860 --- test/Analysis/BasicAA/intrinsics.ll | 7 +- test/Analysis/BasicAA/invariant_load.ll | 29 + test/Analysis/BasicAA/phi-spec-order.ll | 71 + test/Analysis/BasicAA/phi-speculation.ll | 65 +- test/Analysis/BasicAA/pure-const-dce.ll | 9 +- test/Analysis/CostModel/ARM/cast.ll | 547 + test/Analysis/CostModel/ARM/gep.ll | 43 + test/Analysis/CostModel/ARM/insertelement.ll | 46 + test/Analysis/CostModel/ARM/lit.local.cfg | 6 + test/Analysis/CostModel/ARM/select.ll | 67 + test/Analysis/CostModel/ARM/shuffle.ll | 40 + test/Analysis/CostModel/PowerPC/insert_extract.ll | 16 + test/Analysis/CostModel/PowerPC/lit.local.cfg | 6 + test/Analysis/CostModel/PowerPC/load_store.ll | 34 + test/Analysis/CostModel/X86/arith.ll | 90 +- test/Analysis/CostModel/X86/cast.ll | 89 +- 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| 94 + test/CodeGen/AArch64/tls-dynamic-together.ll | 18 + test/CodeGen/AArch64/tls-dynamics.ll | 121 + test/CodeGen/AArch64/tls-execs.ll | 63 + test/CodeGen/AArch64/tst-br.ll | 48 + test/CodeGen/AArch64/variadic.ll | 144 + test/CodeGen/AArch64/zero-reg.ll | 31 + test/CodeGen/ARM/2007-03-13-InstrSched.ll | 1 + .../CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll | 28 - test/CodeGen/ARM/2010-08-04-StackVariable.ll | 67 +- test/CodeGen/ARM/2010-11-30-reloc-movt.ll | 4 +- test/CodeGen/ARM/2010-12-15-elf-lcomm.ll | 3 +- test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll | 74 +- test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll | 75 +- test/CodeGen/ARM/2011-10-26-memset-with-neon.ll | 8 - test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll | 4 +- test/CodeGen/ARM/2011-12-14-machine-sink.ll | 1 + test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll | 2 + test/CodeGen/ARM/2012-08-09-neon-extload.ll | 12 +- test/CodeGen/ARM/2012-08-23-legalize-vmull.ll | 150 + test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll | 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test/Transforms/SimplifyLibCalls/exp2.ll delete mode 100644 test/Transforms/SimplifyLibCalls/floor.ll delete mode 100644 test/Transforms/SimplifyLibCalls/fwrite.ll delete mode 100644 test/Transforms/SimplifyLibCalls/iprintf.ll delete mode 100644 test/Transforms/SimplifyLibCalls/osx-names.ll delete mode 100644 test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll delete mode 100644 test/Transforms/SimplifyLibCalls/pow2.ll create mode 100644 test/Verifier/module-flags-1.ll create mode 100644 test/tools/llvm-lit/chain.c create mode 100644 test/tools/llvm-lit/lit.local.cfg create mode 100644 test/tools/llvm-objdump/disassembly-show-raw.s create mode 100644 test/tools/llvm-objdump/lit.local.cfg create mode 100644 test/tools/llvm-objdump/win64-unwind-data.s create mode 100644 test/tools/llvm-readobj/Inputs/trivial.ll create mode 100644 test/tools/llvm-readobj/Inputs/trivial.obj.coff-i386 create mode 100644 test/tools/llvm-readobj/Inputs/trivial.obj.coff-x86-64 create mode 100644 test/tools/llvm-readobj/Inputs/trivial.obj.elf-i386 create mode 100644 test/tools/llvm-readobj/Inputs/trivial.obj.elf-x86-64 create mode 100644 test/tools/llvm-readobj/Inputs/trivial.obj.macho-i386 create mode 100644 test/tools/llvm-readobj/Inputs/trivial.obj.macho-x86-64 create mode 100644 test/tools/llvm-readobj/file-headers.test create mode 100644 test/tools/llvm-readobj/lit.local.cfg create mode 100644 test/tools/llvm-readobj/relocations.test create mode 100644 test/tools/llvm-readobj/sections-ext.test create mode 100644 test/tools/llvm-readobj/sections.test create mode 100644 test/tools/llvm-readobj/symbols.test (limited to 'test') diff --git a/test/Analysis/BasicAA/intrinsics.ll b/test/Analysis/BasicAA/intrinsics.ll index 59725cfded05..c1cf587204cf 100644 --- a/test/Analysis/BasicAA/intrinsics.ll +++ b/test/Analysis/BasicAA/intrinsics.ll @@ -7,7 +7,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- ; CHECK: define <8 x i16> @test0(i8* noalias %p, i8* noalias %q, <8 x i16> %y) { ; CHECK-NEXT: entry: -; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind +; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) [[ATTR:#[0-9]+]] ; CHECK-NEXT: call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16) ; CHECK-NEXT: %c = add <8 x i16> %a, %a define <8 x i16> @test0(i8* noalias %p, i8* noalias %q, <8 x i16> %y) { @@ -22,7 +22,7 @@ entry: ; CHECK: define <8 x i16> @test1(i8* %p, <8 x i16> %y) { ; CHECK-NEXT: entry: ; CHECK-NEXT: %q = getelementptr i8* %p, i64 16 -; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind +; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) [[ATTR]] ; CHECK-NEXT: call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16) ; CHECK-NEXT: %c = add <8 x i16> %a, %a define <8 x i16> @test1(i8* %p, <8 x i16> %y) { @@ -37,3 +37,6 @@ entry: declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind + +; CHECK: attributes #0 = { nounwind readonly } +; CHECK: attributes [[ATTR]] = { nounwind } diff --git a/test/Analysis/BasicAA/invariant_load.ll b/test/Analysis/BasicAA/invariant_load.ll new file mode 100644 index 000000000000..cd6ddb92d210 --- /dev/null +++ b/test/Analysis/BasicAA/invariant_load.ll @@ -0,0 +1,29 @@ +; RUN: opt < %s -basicaa -gvn -S | FileCheck %s + +; The input *.ll is obtained by manually annotating "invariant.load" to the +; two loads. With "invariant.load" metadata, the second load is redundant. +; +; int foo(int *p, char *q) { +; *q = (char)*p; +; return *p + 1; +; } + +define i32 @foo(i32* nocapture %p, i8* nocapture %q) { +entry: + %0 = load i32* %p, align 4, !tbaa !0, !invariant.load !3 + %conv = trunc i32 %0 to i8 + store i8 %conv, i8* %q, align 1, !tbaa !1 + %1 = load i32* %p, align 4, !tbaa !0, !invariant.load !3 + %add = add nsw i32 %1, 1 + ret i32 %add + +; CHECK: foo +; CHECK: %0 = load i32* %p +; CHECK: store i8 %conv, i8* %q, +; CHECK: %add = add nsw i32 %0, 1 +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!3 = metadata !{} diff --git a/test/Analysis/BasicAA/phi-spec-order.ll b/test/Analysis/BasicAA/phi-spec-order.ll new file mode 100644 index 000000000000..27d47bcd5bf3 --- /dev/null +++ b/test/Analysis/BasicAA/phi-spec-order.ll @@ -0,0 +1,71 @@ +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output 2>&1 | FileCheck %s + +@X = external global [16000 x double], align 32 +@Y = external global [16000 x double], align 32 + +define signext i32 @s000() nounwind { +entry: + br label %for.cond2.preheader + +for.cond2.preheader: ; preds = %for.end, %entry + %nl.018 = phi i32 [ 0, %entry ], [ %inc9, %for.end ] + br label %for.body4 + +for.body4: ; preds = %for.body4, %for.cond2.preheader + %lsr.iv4 = phi [16000 x double]* [ %i11, %for.body4 ], [ bitcast (double* getelementptr inbounds ([16000 x double]* @Y, i64 0, i64 8) + to [16000 x double]*), %for.cond2.preheader ] + %lsr.iv1 = phi [16000 x double]* [ %i10, %for.body4 ], [ @X, %for.cond2.preheader ] + +; CHECK: NoAlias:{{[ \t]+}}[16000 x double]* %lsr.iv1, [16000 x double]* %lsr.iv4 + + %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ] + %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>* + %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>* + %scevgep11 = getelementptr <4 x double>* %lsr.iv46, i64 -2 + %i6 = load <4 x double>* %scevgep11, align 32, !tbaa !0 + %add = fadd <4 x double> %i6, + store <4 x double> %add, <4 x double>* %lsr.iv12, align 32, !tbaa !0 + %scevgep10 = getelementptr <4 x double>* %lsr.iv46, i64 -1 + %i7 = load <4 x double>* %scevgep10, align 32, !tbaa !0 + %add.4 = fadd <4 x double> %i7, + %scevgep9 = getelementptr <4 x double>* %lsr.iv12, i64 1 + store <4 x double> %add.4, <4 x double>* %scevgep9, align 32, !tbaa !0 + %i8 = load <4 x double>* %lsr.iv46, align 32, !tbaa !0 + %add.8 = fadd <4 x double> %i8, + %scevgep8 = getelementptr <4 x double>* %lsr.iv12, i64 2 + store <4 x double> %add.8, <4 x double>* %scevgep8, align 32, !tbaa !0 + %scevgep7 = getelementptr <4 x double>* %lsr.iv46, i64 1 + %i9 = load <4 x double>* %scevgep7, align 32, !tbaa !0 + %add.12 = fadd <4 x double> %i9, + %scevgep3 = getelementptr <4 x double>* %lsr.iv12, i64 3 + store <4 x double> %add.12, <4 x double>* %scevgep3, align 32, !tbaa !0 + +; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep11, <4 x double>* %scevgep7 +; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep10, <4 x double>* %scevgep7 +; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep7, <4 x double>* %scevgep9 +; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep11, <4 x double>* %scevgep3 +; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep10, <4 x double>* %scevgep3 +; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep3, <4 x double>* %scevgep9 + + %lsr.iv.next = add i32 %lsr.iv, -16 + %scevgep = getelementptr [16000 x double]* %lsr.iv1, i64 0, i64 16 + %i10 = bitcast double* %scevgep to [16000 x double]* + %scevgep5 = getelementptr [16000 x double]* %lsr.iv4, i64 0, i64 16 + %i11 = bitcast double* %scevgep5 to [16000 x double]* + %exitcond.15 = icmp eq i32 %lsr.iv.next, 0 + br i1 %exitcond.15, label %for.end, label %for.body4 + +for.end: ; preds = %for.body4 + %inc9 = add nsw i32 %nl.018, 1 + %exitcond = icmp eq i32 %inc9, 400000 + br i1 %exitcond, label %for.end10, label %for.cond2.preheader + +for.end10: ; preds = %for.end + ret i32 0 +} + +!0 = metadata !{metadata !"double", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Analysis/BasicAA/phi-speculation.ll b/test/Analysis/BasicAA/phi-speculation.ll index 21c65929862f..5e1e118d9855 100644 --- a/test/Analysis/BasicAA/phi-speculation.ll +++ b/test/Analysis/BasicAA/phi-speculation.ll @@ -4,9 +4,9 @@ target datalayout = ; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output 2>&1 | FileCheck %s ; ptr_phi and ptr2_phi do not alias. +; CHECK: test_noalias_1 ; CHECK: NoAlias: i32* %ptr2_phi, i32* %ptr_phi - -define i32 @test_noalias(i32* %ptr2, i32 %count, i32* %coeff) { +define i32 @test_noalias_1(i32* %ptr2, i32 %count, i32* %coeff) { entry: %ptr = getelementptr inbounds i32* %ptr2, i64 1 br label %while.body @@ -31,3 +31,64 @@ while.body: the_exit: ret i32 %add } + +; CHECK: test_noalias_2 +; CHECK: NoAlias: i32* %ptr_outer_phi, i32* %ptr_outer_phi2 +; CHECK: NoAlias: i32* %ptr2_phi, i32* %ptr_phi +define i32 @test_noalias_2(i32* %ptr2, i32 %count, i32* %coeff) { +entry: + %ptr = getelementptr inbounds i32* %ptr2, i64 1 + br label %outer.while.header + +outer.while.header: + %ptr_outer_phi = phi i32* [%ptr_inc_outer, %outer.while.backedge], [ %ptr, %entry] + %ptr_outer_phi2 = phi i32* [%ptr2_inc_outer, %outer.while.backedge], [ %ptr2, %entry] + %num.outer = phi i32 [ %count, %entry ], [ %dec.outer, %outer.while.backedge ] + br label %while.body + +while.body: + %num = phi i32 [ %count, %outer.while.header ], [ %dec, %while.body ] + %ptr_phi = phi i32* [ %ptr_outer_phi, %outer.while.header ], [ %ptr_inc, %while.body ] + %ptr2_phi = phi i32* [ %ptr_outer_phi2, %outer.while.header ], [ %ptr2_inc, %while.body ] + %result.09 = phi i32 [ 0 , %outer.while.header ], [ %add, %while.body ] + %dec = add nsw i32 %num, -1 + %0 = load i32* %ptr_phi, align 4 + store i32 %0, i32* %ptr2_phi, align 4 + %1 = load i32* %coeff, align 4 + %2 = load i32* %ptr_phi, align 4 + %mul = mul nsw i32 %1, %2 + %add = add nsw i32 %mul, %result.09 + %tobool = icmp eq i32 %dec, 0 + %ptr_inc = getelementptr inbounds i32* %ptr_phi, i64 1 + %ptr2_inc = getelementptr inbounds i32* %ptr2_phi, i64 1 + br i1 %tobool, label %outer.while.backedge, label %while.body + +outer.while.backedge: + %ptr_inc_outer = getelementptr inbounds i32* %ptr_phi, i64 1 + %ptr2_inc_outer = getelementptr inbounds i32* %ptr2_phi, i64 1 + %dec.outer = add nsw i32 %num.outer, -1 + %br.cond = icmp eq i32 %dec.outer, 0 + br i1 %br.cond, label %the_exit, label %outer.while.header + +the_exit: + ret i32 %add +} + +; CHECK: test_noalias_3 +; CHECK: MayAlias: i8* %ptr2_phi, i8* %ptr_phi +define i32 @test_noalias_3(i8* noalias %x, i8* noalias %y, i8* noalias %z, + i32 %count) { +entry: + br label %while.body + +while.body: + %num = phi i32 [ %count, %entry ], [ %dec, %while.body ] + %ptr_phi = phi i8* [ %x, %entry ], [ %z, %while.body ] + %ptr2_phi = phi i8* [ %y, %entry ], [ %ptr_phi, %while.body ] + %dec = add nsw i32 %num, -1 + %tobool = icmp eq i32 %dec, 0 + br i1 %tobool, label %the_exit, label %while.body + +the_exit: + ret i32 1 +} diff --git a/test/Analysis/BasicAA/pure-const-dce.ll b/test/Analysis/BasicAA/pure-const-dce.ll index 266e607b21a4..e48992860a60 100644 --- a/test/Analysis/BasicAA/pure-const-dce.ll +++ b/test/Analysis/BasicAA/pure-const-dce.ll @@ -4,11 +4,11 @@ ; CHECK: @test ; CHECK: entry -; CHECK: %tmp0 = call i32 @TestConst(i32 5) readnone -; CHECK-NEXT: %tmp1 = call i32 @TestPure(i32 6) readonly +; CHECK: %tmp0 = call i32 @TestConst(i32 5) [[READNONE:#[0-9]+]] +; CHECK-NEXT: %tmp1 = call i32 @TestPure(i32 6) [[READONLY:#[0-9]+]] ; CHECK-NEXT: %tmp2 = call i32 @TestNone(i32 7) ; CHECK-NEXT: store i32 1, i32* @g -; CHECK-NEXT: %tmp5 = call i32 @TestPure(i32 6) readonly +; CHECK-NEXT: %tmp5 = call i32 @TestPure(i32 6) [[READONLY]] ; CHECK-NEXT: %tmp7 = call i32 @TestNone(i32 7) ; CHECK-NEXT: %tmp8 = call i32 @TestNone(i32 7) ; CHECK-NEXT: %sum0 = add i32 %tmp0, %tmp1 @@ -49,3 +49,6 @@ declare i32 @TestConst(i32) readnone declare i32 @TestPure(i32) readonly declare i32 @TestNone(i32) + +; CHECK: attributes [[READNONE]] = { readnone } +; CHECK: attributes [[READONLY]] = { readonly } diff --git a/test/Analysis/CostModel/ARM/cast.ll b/test/Analysis/CostModel/ARM/cast.ll new file mode 100644 index 000000000000..ba9d84cf3e23 --- /dev/null +++ b/test/Analysis/CostModel/ARM/cast.ll @@ -0,0 +1,547 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a8 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios6.0.0" + +define i32 @casts() { + + ; -- scalars -- + ; CHECK: cost of 1 {{.*}} sext + %r0 = sext i1 undef to i8 + ; CHECK: cost of 1 {{.*}} zext + %r1 = zext i1 undef to i8 + ; CHECK: cost of 1 {{.*}} sext + %r2 = sext i1 undef to i16 + ; CHECK: cost of 1 {{.*}} zext + %r3 = zext i1 undef to i16 + ; CHECK: cost of 1 {{.*}} sext + %r4 = sext i1 undef to i32 + ; CHECK: cost of 1 {{.*}} zext + %r5 = zext i1 undef to i32 + ; CHECK: cost of 1 {{.*}} sext + %r6 = sext i1 undef to i64 + ; CHECK: cost of 1 {{.*}} zext + %r7 = zext i1 undef to i64 + ; CHECK: cost of 0 {{.*}} trunc + %r8 = trunc i8 undef to i1 + ; CHECK: cost of 1 {{.*}} sext + %r9 = sext i8 undef to i16 + ; CHECK: cost of 1 {{.*}} zext + %r10 = zext i8 undef to i16 + ; CHECK: cost of 1 {{.*}} sext + %r11 = sext i8 undef to i32 + ; CHECK: cost of 1 {{.*}} zext + %r12 = zext i8 undef to i32 + ; CHECK: cost of 1 {{.*}} sext + %r13 = sext i8 undef to i64 + ; CHECK: cost of 1 {{.*}} zext + %r14 = zext i8 undef to i64 + ; CHECK: cost of 0 {{.*}} trunc + %r15 = trunc i16 undef to i1 + ; CHECK: cost of 0 {{.*}} trunc + %r16 = trunc i16 undef to i8 + ; CHECK: cost of 1 {{.*}} sext + %r17 = sext i16 undef to i32 + ; CHECK: cost of 1 {{.*}} zext + %r18 = zext i16 undef to i32 + ; CHECK: cost of 2 {{.*}} sext + %r19 = sext i16 undef to i64 + ; CHECK: cost of 1 {{.*}} zext + %r20 = zext i16 undef to i64 + ; CHECK: cost of 0 {{.*}} trunc + %r21 = trunc i32 undef to i1 + ; CHECK: cost of 0 {{.*}} trunc + %r22 = trunc i32 undef to i8 + ; CHECK: cost of 0 {{.*}} trunc + %r23 = trunc i32 undef to i16 + ; CHECK: cost of 1 {{.*}} sext + %r24 = sext i32 undef to i64 + ; CHECK: cost of 1 {{.*}} zext + %r25 = zext i32 undef to i64 + ; CHECK: cost of 0 {{.*}} trunc + %r26 = trunc i64 undef to i1 + ; CHECK: cost of 0 {{.*}} trunc + %r27 = trunc i64 undef to i8 + ; CHECK: cost of 0 {{.*}} trunc + %r28 = trunc i64 undef to i16 + ; CHECK: cost of 0 {{.*}} trunc + %r29 = trunc i64 undef to i32 + + ; -- floating point conversions -- + ; Moves between scalar and NEON registers. + ; CHECK: cost of 2 {{.*}} fptoui + %r30 = fptoui float undef to i1 + ; CHECK: cost of 2 {{.*}} fptosi + %r31 = fptosi float undef to i1 + ; CHECK: cost of 2 {{.*}} fptoui + %r32 = fptoui float undef to i8 + ; CHECK: cost of 2 {{.*}} fptosi + %r33 = fptosi float undef to i8 + ; CHECK: cost of 2 {{.*}} fptoui + %r34 = fptoui float undef to i16 + ; CHECK: cost of 2 {{.*}} fptosi + %r35 = fptosi float undef to i16 + ; CHECK: cost of 2 {{.*}} fptoui + %r36 = fptoui float undef to i32 + ; CHECK: cost of 2 {{.*}} fptosi + %r37 = fptosi float undef to i32 + ; CHECK: cost of 10 {{.*}} fptoui + %r38 = fptoui float undef to i64 + ; CHECK: cost of 10 {{.*}} fptosi + %r39 = fptosi float undef to i64 + ; CHECK: cost of 2 {{.*}} fptoui + %r40 = fptoui double undef to i1 + ; CHECK: cost of 2 {{.*}} fptosi + %r41 = fptosi double undef to i1 + ; CHECK: cost of 2 {{.*}} fptoui + %r42 = fptoui double undef to i8 + ; CHECK: cost of 2 {{.*}} fptosi + %r43 = fptosi double undef to i8 + ; CHECK: cost of 2 {{.*}} fptoui + %r44 = fptoui double undef to i16 + ; CHECK: cost of 2 {{.*}} fptosi + %r45 = fptosi double undef to i16 + ; CHECK: cost of 2 {{.*}} fptoui + %r46 = fptoui double undef to i32 + ; CHECK: cost of 2 {{.*}} fptosi + %r47 = fptosi double undef to i32 + ; Function call + ; CHECK: cost of 10 {{.*}} fptoui + %r48 = fptoui double undef to i64 + ; CHECK: cost of 10 {{.*}} fptosi + %r49 = fptosi double undef to i64 + + ; CHECK: cost of 2 {{.*}} sitofp + %r50 = sitofp i1 undef to float + ; CHECK: cost of 2 {{.*}} uitofp + %r51 = uitofp i1 undef to float + ; CHECK: cost of 2 {{.*}} sitofp + %r52 = sitofp i1 undef to double + ; CHECK: cost of 2 {{.*}} uitofp + %r53 = uitofp i1 undef to double + ; CHECK: cost of 2 {{.*}} sitofp + %r54 = sitofp i8 undef to float + ; CHECK: cost of 2 {{.*}} uitofp + %r55 = uitofp i8 undef to float + ; CHECK: cost of 2 {{.*}} sitofp + %r56 = sitofp i8 undef to double + ; CHECK: cost of 2 {{.*}} uitofp + %r57 = uitofp i8 undef to double + ; CHECK: cost of 2 {{.*}} sitofp + %r58 = sitofp i16 undef to float + ; CHECK: cost of 2 {{.*}} uitofp + %r59 = uitofp i16 undef to float + ; CHECK: cost of 2 {{.*}} sitofp + %r60 = sitofp i16 undef to double + ; CHECK: cost of 2 {{.*}} uitofp + %r61 = uitofp i16 undef to double + ; CHECK: cost of 2 {{.*}} sitofp + %r62 = sitofp i32 undef to float + ; CHECK: cost of 2 {{.*}} uitofp + %r63 = uitofp i32 undef to float + ; CHECK: cost of 2 {{.*}} sitofp + %r64 = sitofp i32 undef to double + ; CHECK: cost of 2 {{.*}} uitofp + %r65 = uitofp i32 undef to double + ; Function call + ; CHECK: cost of 10 {{.*}} sitofp + %r66 = sitofp i64 undef to float + ; CHECK: cost of 10 {{.*}} uitofp + %r67 = uitofp i64 undef to float + ; CHECK: cost of 10 {{.*}} sitofp + %r68 = sitofp i64 undef to double + ; CHECK: cost of 10 {{.*}} uitofp + %r69 = uitofp i64 undef to double + + ; CHECK: cost of 3 {{.*}} sext + %r70 = sext <8 x i8> undef to <8 x i32> + ; CHECK: cost of 6 {{.*}} sext + %r71 = sext <16 x i8> undef to <16 x i32> + ; CHECK: cost of 3 {{.*}} zext + %r72 = zext <8 x i8> undef to <8 x i32> + ; CHECK: cost of 6 {{.*}} zext + %r73 = zext <16 x i8> undef to <16 x i32> + + ; CHECK: cost of 7 {{.*}} sext + %rext_0 = sext <8 x i8> undef to <8 x i64> + ; CHECK: cost of 7 {{.*}} zext + %rext_1 = zext <8 x i8> undef to <8 x i64> + ; CHECK: cost of 6 {{.*}} sext + %rext_2 = sext <8 x i16> undef to <8 x i64> + ; CHECK: cost of 6 {{.*}} zext + %rext_3 = zext <8 x i16> undef to <8 x i64> + ; CHECK: cost of 3 {{.*}} sext + %rext_4 = sext <4 x i16> undef to <4 x i64> + ; CHECK: cost of 3 {{.*}} zext + %rext_5 = zext <4 x i16> undef to <4 x i64> + + ; Vector cast cost of instructions lowering the cast to the stack. + ; CHECK: cost of 19 {{.*}} trunc + %r74 = trunc <8 x i32> undef to <8 x i8> + ; CHECK: cost of 38 {{.*}} trunc + %r75 = trunc <16 x i32> undef to <16 x i8> + + ; Floating point truncation costs. + ; CHECK: cost of 1 {{.*}} fptrunc double + %r80 = fptrunc double undef to float + ; CHECK: cost of 2 {{.*}} fptrunc <2 x double + %r81 = fptrunc <2 x double> undef to <2 x float> + ; CHECK: cost of 4 {{.*}} fptrunc <4 x double + %r82 = fptrunc <4 x double> undef to <4 x float> + ; CHECK: cost of 8 {{.*}} fptrunc <8 x double + %r83 = fptrunc <8 x double> undef to <8 x float> + ; CHECK: cost of 16 {{.*}} fptrunc <16 x double + %r84 = fptrunc <16 x double> undef to <16 x float> + + ; Floating point extension costs. + ; CHECK: cost of 1 {{.*}} fpext float + %r85 = fpext float undef to double + ; CHECK: cost of 2 {{.*}} fpext <2 x float + %r86 = fpext <2 x float> undef to <2 x double> + ; CHECK: cost of 4 {{.*}} fpext <4 x float + %r87 = fpext <4 x float> undef to <4 x double> + ; CHECK: cost of 8 {{.*}} fpext <8 x float + %r88 = fpext <8 x float> undef to <8 x double> + ; CHECK: cost of 16 {{.*}} fpext <16 x float + %r89 = fpext <16 x float> undef to <16 x double> + + ;; Floating point to integer vector casts. + ; CHECK: cost of 1 {{.*}} fptoui + %r90 = fptoui <2 x float> undef to <2 x i1> + ; CHECK: cost of 1 {{.*}} fptosi + %r91 = fptosi <2 x float> undef to <2 x i1> + ; CHECK: cost of 1 {{.*}} fptoui + %r92 = fptoui <2 x float> undef to <2 x i8> + ; CHECK: cost of 1 {{.*}} fptosi + %r93 = fptosi <2 x float> undef to <2 x i8> + ; CHECK: cost of 1 {{.*}} fptoui + %r94 = fptoui <2 x float> undef to <2 x i16> + ; CHECK: cost of 1 {{.*}} fptosi + %r95 = fptosi <2 x float> undef to <2 x i16> + ; CHECK: cost of 1 {{.*}} fptoui + %r96 = fptoui <2 x float> undef to <2 x i32> + ; CHECK: cost of 1 {{.*}} fptosi + %r97 = fptosi <2 x float> undef to <2 x i32> + ; CHECK: cost of 24 {{.*}} fptoui + %r98 = fptoui <2 x float> undef to <2 x i64> + ; CHECK: cost of 24 {{.*}} fptosi + %r99 = fptosi <2 x float> undef to <2 x i64> + + ; CHECK: cost of 8 {{.*}} fptoui + %r100 = fptoui <2 x double> undef to <2 x i1> + ; CHECK: cost of 8 {{.*}} fptosi + %r101 = fptosi <2 x double> undef to <2 x i1> + ; CHECK: cost of 8 {{.*}} fptoui + %r102 = fptoui <2 x double> undef to <2 x i8> + ; CHECK: cost of 8 {{.*}} fptosi + %r103 = fptosi <2 x double> undef to <2 x i8> + ; CHECK: cost of 8 {{.*}} fptoui + %r104 = fptoui <2 x double> undef to <2 x i16> + ; CHECK: cost of 8 {{.*}} fptosi + %r105 = fptosi <2 x double> undef to <2 x i16> + ; CHECK: cost of 2 {{.*}} fptoui + %r106 = fptoui <2 x double> undef to <2 x i32> + ; CHECK: cost of 2 {{.*}} fptosi + %r107 = fptosi <2 x double> undef to <2 x i32> + ; CHECK: cost of 24 {{.*}} fptoui + %r108 = fptoui <2 x double> undef to <2 x i64> + ; CHECK: cost of 24 {{.*}} fptosi + %r109 = fptosi <2 x double> undef to <2 x i64> + + ; CHECK: cost of 16 {{.*}} fptoui + %r110 = fptoui <4 x float> undef to <4 x i1> + ; CHECK: cost of 16 {{.*}} fptosi + %r111 = fptosi <4 x float> undef to <4 x i1> + ; CHECK: cost of 3 {{.*}} fptoui + %r112 = fptoui <4 x float> undef to <4 x i8> + ; CHECK: cost of 3 {{.*}} fptosi + %r113 = fptosi <4 x float> undef to <4 x i8> + ; CHECK: cost of 2 {{.*}} fptoui + %r114 = fptoui <4 x float> undef to <4 x i16> + ; CHECK: cost of 2 {{.*}} fptosi + %r115 = fptosi <4 x float> undef to <4 x i16> + ; CHECK: cost of 1 {{.*}} fptoui + %r116 = fptoui <4 x float> undef to <4 x i32> + ; CHECK: cost of 1 {{.*}} fptosi + %r117 = fptosi <4 x float> undef to <4 x i32> + ; CHECK: cost of 48 {{.*}} fptoui + %r118 = fptoui <4 x float> undef to <4 x i64> + ; CHECK: cost of 48 {{.*}} fptosi + %r119 = fptosi <4 x float> undef to <4 x i64> + + ; CHECK: cost of 16 {{.*}} fptoui + %r120 = fptoui <4 x double> undef to <4 x i1> + ; CHECK: cost of 16 {{.*}} fptosi + %r121 = fptosi <4 x double> undef to <4 x i1> + ; CHECK: cost of 16 {{.*}} fptoui + %r122 = fptoui <4 x double> undef to <4 x i8> + ; CHECK: cost of 16 {{.*}} fptosi + %r123 = fptosi <4 x double> undef to <4 x i8> + ; CHECK: cost of 16 {{.*}} fptoui + %r124 = fptoui <4 x double> undef to <4 x i16> + ; CHECK: cost of 16 {{.*}} fptosi + %r125 = fptosi <4 x double> undef to <4 x i16> + ; CHECK: cost of 16 {{.*}} fptoui + %r126 = fptoui <4 x double> undef to <4 x i32> + ; CHECK: cost of 16 {{.*}} fptosi + %r127 = fptosi <4 x double> undef to <4 x i32> + ; CHECK: cost of 48 {{.*}} fptoui + %r128 = fptoui <4 x double> undef to <4 x i64> + ; CHECK: cost of 48 {{.*}} fptosi + %r129 = fptosi <4 x double> undef to <4 x i64> + + ; CHECK: cost of 32 {{.*}} fptoui + %r130 = fptoui <8 x float> undef to <8 x i1> + ; CHECK: cost of 32 {{.*}} fptosi + %r131 = fptosi <8 x float> undef to <8 x i1> + ; CHECK: cost of 32 {{.*}} fptoui + %r132 = fptoui <8 x float> undef to <8 x i8> + ; CHECK: cost of 32 {{.*}} fptosi + %r133 = fptosi <8 x float> undef to <8 x i8> + ; CHECK: cost of 4 {{.*}} fptoui + %r134 = fptoui <8 x float> undef to <8 x i16> + ; CHECK: cost of 4 {{.*}} fptosi + %r135 = fptosi <8 x float> undef to <8 x i16> + ; CHECK: cost of 2 {{.*}} fptoui + %r136 = fptoui <8 x float> undef to <8 x i32> + ; CHECK: cost of 2 {{.*}} fptosi + %r137 = fptosi <8 x float> undef to <8 x i32> + ; CHECK: cost of 96 {{.*}} fptoui + %r138 = fptoui <8 x float> undef to <8 x i64> + ; CHECK: cost of 96 {{.*}} fptosi + %r139 = fptosi <8 x float> undef to <8 x i64> + + ; CHECK: cost of 32 {{.*}} fptoui + %r140 = fptoui <8 x double> undef to <8 x i1> + ; CHECK: cost of 32 {{.*}} fptosi + %r141 = fptosi <8 x double> undef to <8 x i1> + ; CHECK: cost of 32 {{.*}} fptoui + %r142 = fptoui <8 x double> undef to <8 x i8> + ; CHECK: cost of 32 {{.*}} fptosi + %r143 = fptosi <8 x double> undef to <8 x i8> + ; CHECK: cost of 32 {{.*}} fptoui + %r144 = fptoui <8 x double> undef to <8 x i16> + ; CHECK: cost of 32 {{.*}} fptosi + %r145 = fptosi <8 x double> undef to <8 x i16> + ; CHECK: cost of 32 {{.*}} fptoui + %r146 = fptoui <8 x double> undef to <8 x i32> + ; CHECK: cost of 32 {{.*}} fptosi + %r147 = fptosi <8 x double> undef to <8 x i32> + ; CHECK: cost of 96 {{.*}} fptoui + %r148 = fptoui <8 x double> undef to <8 x i64> + ; CHECK: cost of 96 {{.*}} fptosi + %r149 = fptosi <8 x double> undef to <8 x i64> + + ; CHECK: cost of 64 {{.*}} fptoui + %r150 = fptoui <16 x float> undef to <16 x i1> + ; CHECK: cost of 64 {{.*}} fptosi + %r151 = fptosi <16 x float> undef to <16 x i1> + ; CHECK: cost of 64 {{.*}} fptoui + %r152 = fptoui <16 x float> undef to <16 x i8> + ; CHECK: cost of 64 {{.*}} fptosi + %r153 = fptosi <16 x float> undef to <16 x i8> + ; CHECK: cost of 8 {{.*}} fptoui + %r154 = fptoui <16 x float> undef to <16 x i16> + ; CHECK: cost of 8 {{.*}} fptosi + %r155 = fptosi <16 x float> undef to <16 x i16> + ; CHECK: cost of 4 {{.*}} fptoui + %r156 = fptoui <16 x float> undef to <16 x i32> + ; CHECK: cost of 4 {{.*}} fptosi + %r157 = fptosi <16 x float> undef to <16 x i32> + ; CHECK: cost of 192 {{.*}} fptoui + %r158 = fptoui <16 x float> undef to <16 x i64> + ; CHECK: cost of 192 {{.*}} fptosi + %r159 = fptosi <16 x float> undef to <16 x i64> + + ; CHECK: cost of 64 {{.*}} fptoui + %r160 = fptoui <16 x double> undef to <16 x i1> + ; CHECK: cost of 64 {{.*}} fptosi + %r161 = fptosi <16 x double> undef to <16 x i1> + ; CHECK: cost of 64 {{.*}} fptoui + %r162 = fptoui <16 x double> undef to <16 x i8> + ; CHECK: cost of 64 {{.*}} fptosi + %r163 = fptosi <16 x double> undef to <16 x i8> + ; CHECK: cost of 64 {{.*}} fptoui + %r164 = fptoui <16 x double> undef to <16 x i16> + ; CHECK: cost of 64 {{.*}} fptosi + %r165 = fptosi <16 x double> undef to <16 x i16> + ; CHECK: cost of 64 {{.*}} fptoui + %r166 = fptoui <16 x double> undef to <16 x i32> + ; CHECK: cost of 64 {{.*}} fptosi + %r167 = fptosi <16 x double> undef to <16 x i32> + ; CHECK: cost of 192 {{.*}} fptoui + %r168 = fptoui <16 x double> undef to <16 x i64> + ; CHECK: cost of 192 {{.*}} fptosi + %r169 = fptosi <16 x double> undef to <16 x i64> + + ; CHECK: cost of 8 {{.*}} uitofp + %r170 = uitofp <2 x i1> undef to <2 x float> + ; CHECK: cost of 8 {{.*}} sitofp + %r171 = sitofp <2 x i1> undef to <2 x float> + ; CHECK: cost of 3 {{.*}} uitofp + %r172 = uitofp <2 x i8> undef to <2 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %r173 = sitofp <2 x i8> undef to <2 x float> + ; CHECK: cost of 2 {{.*}} uitofp + %r174 = uitofp <2 x i16> undef to <2 x float> + ; CHECK: cost of 2 {{.*}} sitofp + %r175 = sitofp <2 x i16> undef to <2 x float> + ; CHECK: cost of 1 {{.*}} uitofp + %r176 = uitofp <2 x i32> undef to <2 x float> + ; CHECK: cost of 1 {{.*}} sitofp + %r177 = sitofp <2 x i32> undef to <2 x float> + ; CHECK: cost of 24 {{.*}} uitofp + %r178 = uitofp <2 x i64> undef to <2 x float> + ; CHECK: cost of 24 {{.*}} sitofp + %r179 = sitofp <2 x i64> undef to <2 x float> + + ; CHECK: cost of 8 {{.*}} uitofp + %r180 = uitofp <2 x i1> undef to <2 x double> + ; CHECK: cost of 8 {{.*}} sitofp + %r181 = sitofp <2 x i1> undef to <2 x double> + ; CHECK: cost of 4 {{.*}} uitofp + %r182 = uitofp <2 x i8> undef to <2 x double> + ; CHECK: cost of 4 {{.*}} sitofp + %r183 = sitofp <2 x i8> undef to <2 x double> + ; CHECK: cost of 3 {{.*}} uitofp + %r184 = uitofp <2 x i16> undef to <2 x double> + ; CHECK: cost of 3 {{.*}} sitofp + %r185 = sitofp <2 x i16> undef to <2 x double> + ; CHECK: cost of 2 {{.*}} uitofp + %r186 = uitofp <2 x i32> undef to <2 x double> + ; CHECK: cost of 2 {{.*}} sitofp + %r187 = sitofp <2 x i32> undef to <2 x double> + ; CHECK: cost of 24 {{.*}} uitofp + %r188 = uitofp <2 x i64> undef to <2 x double> + ; CHECK: cost of 24 {{.*}} sitofp + %r189 = sitofp <2 x i64> undef to <2 x double> + + ; CHECK: cost of 3 {{.*}} uitofp + %r190 = uitofp <4 x i1> undef to <4 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %r191 = sitofp <4 x i1> undef to <4 x float> + ; CHECK: cost of 3 {{.*}} uitofp + %r192 = uitofp <4 x i8> undef to <4 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %r193 = sitofp <4 x i8> undef to <4 x float> + ; CHECK: cost of 2 {{.*}} uitofp + %r194 = uitofp <4 x i16> undef to <4 x float> + ; CHECK: cost of 2 {{.*}} sitofp + %r195 = sitofp <4 x i16> undef to <4 x float> + ; CHECK: cost of 1 {{.*}} uitofp + %r196 = uitofp <4 x i32> undef to <4 x float> + ; CHECK: cost of 1 {{.*}} sitofp + %r197 = sitofp <4 x i32> undef to <4 x float> + ; CHECK: cost of 48 {{.*}} uitofp + %r198 = uitofp <4 x i64> undef to <4 x float> + ; CHECK: cost of 48 {{.*}} sitofp + %r199 = sitofp <4 x i64> undef to <4 x float> + + ; CHECK: cost of 16 {{.*}} uitofp + %r200 = uitofp <4 x i1> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} sitofp + %r201 = sitofp <4 x i1> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} uitofp + %r202 = uitofp <4 x i8> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} sitofp + %r203 = sitofp <4 x i8> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} uitofp + %r204 = uitofp <4 x i16> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} sitofp + %r205 = sitofp <4 x i16> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} uitofp + %r206 = uitofp <4 x i32> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} sitofp + %r207 = sitofp <4 x i32> undef to <4 x double> + ; CHECK: cost of 48 {{.*}} uitofp + %r208 = uitofp <4 x i64> undef to <4 x double> + ; CHECK: cost of 48 {{.*}} sitofp + %r209 = sitofp <4 x i64> undef to <4 x double> + + ; CHECK: cost of 32 {{.*}} uitofp + %r210 = uitofp <8 x i1> undef to <8 x float> + ; CHECK: cost of 32 {{.*}} sitofp + %r211 = sitofp <8 x i1> undef to <8 x float> + ; CHECK: cost of 32 {{.*}} uitofp + %r212 = uitofp <8 x i8> undef to <8 x float> + ; CHECK: cost of 32 {{.*}} sitofp + %r213 = sitofp <8 x i8> undef to <8 x float> + ; CHECK: cost of 4 {{.*}} uitofp + %r214 = uitofp <8 x i16> undef to <8 x float> + ; CHECK: cost of 4 {{.*}} sitofp + %r215 = sitofp <8 x i16> undef to <8 x float> + ; CHECK: cost of 2 {{.*}} uitofp + %r216 = uitofp <8 x i32> undef to <8 x float> + ; CHECK: cost of 2 {{.*}} sitofp + %r217 = sitofp <8 x i32> undef to <8 x float> + ; CHECK: cost of 96 {{.*}} uitofp + %r218 = uitofp <8 x i64> undef to <8 x float> + ; CHECK: cost of 96 {{.*}} sitofp + %r219 = sitofp <8 x i64> undef to <8 x float> + + ; CHECK: cost of 32 {{.*}} uitofp + %r220 = uitofp <8 x i1> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} sitofp + %r221 = sitofp <8 x i1> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} uitofp + %r222 = uitofp <8 x i8> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} sitofp + %r223 = sitofp <8 x i8> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} uitofp + %r224 = uitofp <8 x i16> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} sitofp + %r225 = sitofp <8 x i16> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} uitofp + %r226 = uitofp <8 x i16> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} sitofp + %r227 = sitofp <8 x i16> undef to <8 x double> + ; CHECK: cost of 96 {{.*}} uitofp + %r228 = uitofp <8 x i64> undef to <8 x double> + ; CHECK: cost of 96 {{.*}} sitofp + %r229 = sitofp <8 x i64> undef to <8 x double> + + ; CHECK: cost of 64 {{.*}} uitofp + %r230 = uitofp <16 x i1> undef to <16 x float> + ; CHECK: cost of 64 {{.*}} sitofp + %r231 = sitofp <16 x i1> undef to <16 x float> + ; CHECK: cost of 64 {{.*}} uitofp + %r232 = uitofp <16 x i8> undef to <16 x float> + ; CHECK: cost of 64 {{.*}} sitofp + %r233 = sitofp <16 x i8> undef to <16 x float> + ; CHECK: cost of 8 {{.*}} uitofp + %r234 = uitofp <16 x i16> undef to <16 x float> + ; CHECK: cost of 8 {{.*}} sitofp + %r235 = sitofp <16 x i16> undef to <16 x float> + ; CHECK: cost of 4 {{.*}} uitofp + %r236 = uitofp <16 x i32> undef to <16 x float> + ; CHECK: cost of 4 {{.*}} sitofp + %r237 = sitofp <16 x i32> undef to <16 x float> + ; CHECK: cost of 192 {{.*}} uitofp + %r238 = uitofp <16 x i64> undef to <16 x float> + ; CHECK: cost of 192 {{.*}} sitofp + %r239 = sitofp <16 x i64> undef to <16 x float> + + ; CHECK: cost of 64 {{.*}} uitofp + %r240 = uitofp <16 x i1> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} sitofp + %r241 = sitofp <16 x i1> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} uitofp + %r242 = uitofp <16 x i8> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} sitofp + %r243 = sitofp <16 x i8> undef to <16 x double> + ; C4ECK: cost of 64 {{.*}} uitofp + %r244 = uitofp <16 x i16> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} sitofp + %r245 = sitofp <16 x i16> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} uitofp + %r246 = uitofp <16 x i16> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} sitofp + %r247 = sitofp <16 x i16> undef to <16 x double> + ; CHECK: cost of 192 {{.*}} uitofp + %r248 = uitofp <16 x i64> undef to <16 x double> + ; CHECK: cost of 192 {{.*}} sitofp + %r249 = sitofp <16 x i64> undef to <16 x double> + + ;CHECK: cost of 0 {{.*}} ret + ret i32 undef +} + diff --git a/test/Analysis/CostModel/ARM/gep.ll b/test/Analysis/CostModel/ARM/gep.ll new file mode 100644 index 000000000000..a63b87d2ad11 --- /dev/null +++ b/test/Analysis/CostModel/ARM/gep.ll @@ -0,0 +1,43 @@ +; RUN: opt -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios6.0.0" + +define void @test_geps() { + ; Cost of scalar integer geps should be one. We can't always expect it to be + ; folded into the instruction addressing mode. +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i8* + %a0 = getelementptr inbounds i8* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i16* + %a1 = getelementptr inbounds i16* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i32* + %a2 = getelementptr inbounds i32* undef, i32 0 + +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i64* + %a3 = getelementptr inbounds i64* undef, i32 0 + + ; Cost of scalar floating point geps should be one. We cannot fold the address + ; computation. +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds float* + %a4 = getelementptr inbounds float* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds double* + %a5 = getelementptr inbounds double* undef, i32 0 + + + ; Cost of vector geps should be one. We cannot fold the address computation. +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i8>* + %a7 = getelementptr inbounds <4 x i8>* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i16>* + %a8 = getelementptr inbounds <4 x i16>* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i32>* + %a9 = getelementptr inbounds <4 x i32>* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i64>* + %a10 = getelementptr inbounds <4 x i64>* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x float>* + %a11 = getelementptr inbounds <4 x float>* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x double>* + %a12 = getelementptr inbounds <4 x double>* undef, i32 0 + + + ret void +} diff --git a/test/Analysis/CostModel/ARM/insertelement.ll b/test/Analysis/CostModel/ARM/insertelement.ll new file mode 100644 index 000000000000..f951b08f9baa --- /dev/null +++ b/test/Analysis/CostModel/ARM/insertelement.ll @@ -0,0 +1,46 @@ +; RUN: opt -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios6.0.0" + +; Multiple insert elements from loads into d subregisters are expensive on swift +; due to renaming constraints. +%T_i8v = type <8 x i8> +%T_i8 = type i8 +; CHECK: insertelement_i8 +define void @insertelement_i8(%T_i8* %saddr, + %T_i8v* %vaddr) { + %v0 = load %T_i8v* %vaddr + %v1 = load %T_i8* %saddr +;CHECK: estimated cost of 3 for {{.*}} insertelement <8 x i8> + %v2 = insertelement %T_i8v %v0, %T_i8 %v1, i32 1 + store %T_i8v %v2, %T_i8v* %vaddr + ret void +} + + +%T_i16v = type <4 x i16> +%T_i16 = type i16 +; CHECK: insertelement_i16 +define void @insertelement_i16(%T_i16* %saddr, + %T_i16v* %vaddr) { + %v0 = load %T_i16v* %vaddr + %v1 = load %T_i16* %saddr +;CHECK: estimated cost of 3 for {{.*}} insertelement <4 x i16> + %v2 = insertelement %T_i16v %v0, %T_i16 %v1, i32 1 + store %T_i16v %v2, %T_i16v* %vaddr + ret void +} + +%T_i32v = type <2 x i32> +%T_i32 = type i32 +; CHECK: insertelement_i32 +define void @insertelement_i32(%T_i32* %saddr, + %T_i32v* %vaddr) { + %v0 = load %T_i32v* %vaddr + %v1 = load %T_i32* %saddr +;CHECK: estimated cost of 3 for {{.*}} insertelement <2 x i32> + %v2 = insertelement %T_i32v %v0, %T_i32 %v1, i32 1 + store %T_i32v %v2, %T_i32v* %vaddr + ret void +} diff --git a/test/Analysis/CostModel/ARM/lit.local.cfg b/test/Analysis/CostModel/ARM/lit.local.cfg new file mode 100644 index 000000000000..cb77b09ef4ad --- /dev/null +++ b/test/Analysis/CostModel/ARM/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +targets = set(config.root.targets_to_build.split()) +if not 'ARM' in targets: + config.unsupported = True + diff --git a/test/Analysis/CostModel/ARM/select.ll b/test/Analysis/CostModel/ARM/select.ll new file mode 100644 index 000000000000..34ed1eefdaf4 --- /dev/null +++ b/test/Analysis/CostModel/ARM/select.ll @@ -0,0 +1,67 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios6.0.0" + +; CHECK: casts +define void @casts() { + ; Scalar values + ; CHECK: cost of 1 {{.*}} select + %v1 = select i1 undef, i8 undef, i8 undef + ; CHECK: cost of 1 {{.*}} select + %v2 = select i1 undef, i16 undef, i16 undef + ; CHECK: cost of 1 {{.*}} select + %v3 = select i1 undef, i32 undef, i32 undef + ; CHECK: cost of 2 {{.*}} select + %v4 = select i1 undef, i64 undef, i64 undef + ; CHECK: cost of 1 {{.*}} select + %v5 = select i1 undef, float undef, float undef + ; CHECK: cost of 1 {{.*}} select + %v6 = select i1 undef, double undef, double undef + + ; Vector values + ; CHECK: cost of 1 {{.*}} select + %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef + ; CHECK: cost of 1 {{.*}} select + %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef + ; CHECK: cost of 1 {{.*}} select + %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef + ; CHECK: cost of 1 {{.*}} select + %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef + + ; CHECK: cost of 1 {{.*}} select + %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef + ; CHECK: cost of 1 {{.*}} select + %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef + ; CHECK: cost of 1 {{.*}} select + %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef + ; CHECK: cost of 40 {{.*}} select + %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef + + ; CHECK: cost of 1 {{.*}} select + %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef + ; CHECK: cost of 1 {{.*}} select + %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef + ; CHECK: cost of 41 {{.*}} select + %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef + ; CHECK: cost of 82 {{.*}} select + %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef + + ; CHECK: cost of 1 {{.*}} select + %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef + ; CHECK: cost of 19 {{.*}} select + %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef + ; CHECK: cost of 50 {{.*}} select + %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef + ; CHECK: cost of 100 {{.*}} select + %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef + + ; CHECK: cost of 1 {{.*}} select + %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef + ; CHECK: cost of 1 {{.*}} select + %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef + + ; CHECK: cost of 1 {{.*}} select + %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef + + ret void +} diff --git a/test/Analysis/CostModel/ARM/shuffle.ll b/test/Analysis/CostModel/ARM/shuffle.ll new file mode 100644 index 000000000000..c92d66880464 --- /dev/null +++ b/test/Analysis/CostModel/ARM/shuffle.ll @@ -0,0 +1,40 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios6.0.0" + +; CHECK: shuffle +define void @shuffle() { + + + ;; Reverse shuffles should be lowered to vrev and possibly a vext (for + ;; quadwords) + + ; Vector values + ; CHECK: cost of 1 {{.*}} shuffle + %v7 = shufflevector <2 x i8> undef, <2 x i8>undef, <2 x i32> + ; CHECK: cost of 1 {{.*}} shuffle + %v8 = shufflevector <4 x i8> undef, <4 x i8>undef, <4 x i32> + ; CHECK: cost of 1 {{.*}} shuffle + %v9 = shufflevector <8 x i8> undef, <8 x i8>undef, <8 x i32> + ; CHECK: cost of 2 {{.*}} shuffle + %v10 = shufflevector <16 x i8> undef, <16 x i8>undef, <16 x i32> + + ; CHECK: cost of 1 {{.*}} shuffle + %v11 = shufflevector <2 x i16> undef, <2 x i16>undef, <2 x i32> + ; CHECK: cost of 1 {{.*}} shuffle + %v12 = shufflevector <4 x i16> undef, <4 x i16>undef, <4 x i32> + ; CHECK: cost of 2 {{.*}} shuffle + %v13 = shufflevector <8 x i16> undef, <8 x i16>undef, <8 x i32> + + ; CHECK: cost of 1 {{.*}} shuffle + %v14 = shufflevector <2 x i32> undef, <2 x i32>undef, <2 x i32> + ; CHECK: cost of 2 {{.*}} shuffle + %v15 = shufflevector <4 x i32> undef, <4 x i32>undef, <4 x i32> + + ; CHECK: cost of 1 {{.*}} shuffle + %v16 = shufflevector <2 x float> undef, <2 x float>undef, <2 x i32> + ; CHECK: cost of 2 {{.*}} shuffle + %v17 = shufflevector <4 x float> undef, <4 x float>undef, <4 x i32> + + ret void +} diff --git a/test/Analysis/CostModel/PowerPC/insert_extract.ll b/test/Analysis/CostModel/PowerPC/insert_extract.ll new file mode 100644 index 000000000000..f51963d56fde --- /dev/null +++ b/test/Analysis/CostModel/PowerPC/insert_extract.ll @@ -0,0 +1,16 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i32 @insert(i32 %arg) { + ; CHECK: cost of 13 {{.*}} insertelement + %x = insertelement <4 x i32> undef, i32 %arg, i32 0 + ret i32 undef +} + +define i32 @extract(<4 x i32> %arg) { + ; CHECK: cost of 13 {{.*}} extractelement + %x = extractelement <4 x i32> %arg, i32 0 + ret i32 %x +} + diff --git a/test/Analysis/CostModel/PowerPC/lit.local.cfg b/test/Analysis/CostModel/PowerPC/lit.local.cfg new file mode 100644 index 000000000000..4019eca0bb88 --- /dev/null +++ b/test/Analysis/CostModel/PowerPC/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +targets = set(config.root.targets_to_build.split()) +if not 'PowerPC' in targets: + config.unsupported = True + diff --git a/test/Analysis/CostModel/PowerPC/load_store.ll b/test/Analysis/CostModel/PowerPC/load_store.ll new file mode 100644 index 000000000000..c77cce955abf --- /dev/null +++ b/test/Analysis/CostModel/PowerPC/load_store.ll @@ -0,0 +1,34 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i32 @stores(i32 %arg) { + + ; CHECK: cost of 1 {{.*}} store + store i8 undef, i8* undef, align 4 + ; CHECK: cost of 1 {{.*}} store + store i16 undef, i16* undef, align 4 + ; CHECK: cost of 1 {{.*}} store + store i32 undef, i32* undef, align 4 + ; CHECK: cost of 2 {{.*}} store + store i64 undef, i64* undef, align 4 + ; CHECK: cost of 4 {{.*}} store + store i128 undef, i128* undef, align 4 + + ret i32 undef +} +define i32 @loads(i32 %arg) { + ; CHECK: cost of 1 {{.*}} load + load i8* undef, align 4 + ; CHECK: cost of 1 {{.*}} load + load i16* undef, align 4 + ; CHECK: cost of 1 {{.*}} load + load i32* undef, align 4 + ; CHECK: cost of 2 {{.*}} load + load i64* undef, align 4 + ; CHECK: cost of 4 {{.*}} load + load i128* undef, align 4 + + ret i32 undef +} + diff --git a/test/Analysis/CostModel/X86/arith.ll b/test/Analysis/CostModel/X86/arith.ll index 37cca8d54067..85b442533f41 100644 --- a/test/Analysis/CostModel/X86/arith.ll +++ b/test/Analysis/CostModel/X86/arith.ll @@ -1,4 +1,6 @@ ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core2 | FileCheck %s --check-prefix=SSE3 +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core-avx2 | FileCheck %s --check-prefix=AVX2 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" @@ -14,7 +16,7 @@ define i32 @add(i32 %arg) { %D = add <4 x i64> undef, undef ;CHECK: cost of 8 {{.*}} add %E = add <8 x i64> undef, undef - ;CHECK: cost of 1 {{.*}} ret + ;CHECK: cost of 0 {{.*}} ret ret i32 undef } @@ -28,11 +30,41 @@ define i32 @xor(i32 %arg) { %C = xor <2 x i64> undef, undef ;CHECK: cost of 1 {{.*}} xor %D = xor <4 x i64> undef, undef - ;CHECK: cost of 1 {{.*}} ret + ;CHECK: cost of 0 {{.*}} ret ret i32 undef } +; CHECK: mul +define void @mul() { + ; A <2 x i32> gets expanded to a <2 x i64> vector. + ; A <2 x i64> vector multiply is implemented using + ; 3 PMULUDQ and 2 PADDS and 4 shifts. + ;CHECK: cost of 9 {{.*}} mul + %A0 = mul <2 x i32> undef, undef + ;CHECK: cost of 9 {{.*}} mul + %A1 = mul <2 x i64> undef, undef + ;CHECK: cost of 18 {{.*}} mul + %A2 = mul <4 x i64> undef, undef + ret void +} + +; SSE3: sse3mull +define void @sse3mull() { + ; SSE3: cost of 6 {{.*}} mul + %A0 = mul <4 x i32> undef, undef + ret void + ; SSE3: avx2mull +} + +; AVX2: avx2mull +define void @avx2mull() { + ; AVX2: cost of 9 {{.*}} mul + %A0 = mul <4 x i64> undef, undef + ret void + ; AVX2: fmul +} +; CHECK: fmul define i32 @fmul(i32 %arg) { ;CHECK: cost of 1 {{.*}} fmul %A = fmul <4 x float> undef, undef @@ -40,3 +72,57 @@ define i32 @fmul(i32 %arg) { %B = fmul <8 x float> undef, undef ret i32 undef } + +; AVX: shift +; AVX2: shift +define void @shift() { + ; AVX: cost of 2 {{.*}} shl + ; AVX2: cost of 1 {{.*}} shl + %A0 = shl <4 x i32> undef, undef + ; AVX: cost of 2 {{.*}} shl + ; AVX2: cost of 1 {{.*}} shl + %A1 = shl <2 x i64> undef, undef + + ; AVX: cost of 2 {{.*}} lshr + ; AVX2: cost of 1 {{.*}} lshr + %B0 = lshr <4 x i32> undef, undef + ; AVX: cost of 2 {{.*}} lshr + ; AVX2: cost of 1 {{.*}} lshr + %B1 = lshr <2 x i64> undef, undef + + ; AVX: cost of 2 {{.*}} ashr + ; AVX2: cost of 1 {{.*}} ashr + %C0 = ashr <4 x i32> undef, undef + ; AVX: cost of 6 {{.*}} ashr + ; AVX2: cost of 20 {{.*}} ashr + %C1 = ashr <2 x i64> undef, undef + + ret void +} + +; AVX: avx2shift +; AVX2: avx2shift +define void @avx2shift() { + ; AVX: cost of 2 {{.*}} shl + ; AVX2: cost of 1 {{.*}} shl + %A0 = shl <8 x i32> undef, undef + ; AVX: cost of 2 {{.*}} shl + ; AVX2: cost of 1 {{.*}} shl + %A1 = shl <4 x i64> undef, undef + + ; AVX: cost of 2 {{.*}} lshr + ; AVX2: cost of 1 {{.*}} lshr + %B0 = lshr <8 x i32> undef, undef + ; AVX: cost of 2 {{.*}} lshr + ; AVX2: cost of 1 {{.*}} lshr + %B1 = lshr <4 x i64> undef, undef + + ; AVX: cost of 2 {{.*}} ashr + ; AVX2: cost of 1 {{.*}} ashr + %C0 = ashr <8 x i32> undef, undef + ; AVX: cost of 12 {{.*}} ashr + ; AVX2: cost of 40 {{.*}} ashr + %C1 = ashr <4 x i64> undef, undef + + ret void +} diff --git a/test/Analysis/CostModel/X86/cast.ll b/test/Analysis/CostModel/X86/cast.ll index 75c97a781e7f..b69b3bf6304c 100644 --- a/test/Analysis/CostModel/X86/cast.ll +++ b/test/Analysis/CostModel/X86/cast.ll @@ -28,7 +28,7 @@ define i32 @add(i32 %arg) { ;CHECK: cost of 0 {{.*}} trunc %H = trunc i32 undef to i1 - ;CHECK: cost of 1 {{.*}} ret + ;CHECK: cost of 0 {{.*}} ret ret i32 undef } @@ -44,6 +44,10 @@ define i32 @zext_sext(<8 x i1> %in) { %B = zext <8 x i16> undef to <8 x i32> ;CHECK: cost of 1 {{.*}} sext %C = sext <4 x i32> undef to <4 x i64> + ;CHECK: cost of 6 {{.*}} sext + %C1 = sext <4 x i8> undef to <4 x i64> + ;CHECK: cost of 6 {{.*}} sext + %C2 = sext <4 x i16> undef to <4 x i64> ;CHECK: cost of 1 {{.*}} zext %D = zext <4 x i32> undef to <4 x i64> @@ -59,7 +63,7 @@ define i32 @zext_sext(<8 x i1> %in) { ret i32 undef } -define i32 @masks(<8 x i1> %in) { +define i32 @masks8(<8 x i1> %in) { ;CHECK: cost of 6 {{.*}} zext %Z = zext <8 x i1> %in to <8 x i32> ;CHECK: cost of 9 {{.*}} sext @@ -67,3 +71,84 @@ define i32 @masks(<8 x i1> %in) { ret i32 undef } +define i32 @masks4(<4 x i1> %in) { + ;CHECK: cost of 8 {{.*}} sext + %S = sext <4 x i1> %in to <4 x i64> + ret i32 undef +} + +define void @sitofp4(<4 x i1> %a, <4 x i8> %b, <4 x i16> %c, <4 x i32> %d) { + ; CHECK: cost of 3 {{.*}} sitofp + %A1 = sitofp <4 x i1> %a to <4 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %A2 = sitofp <4 x i1> %a to <4 x double> + + ; CHECK: cost of 3 {{.*}} sitofp + %B1 = sitofp <4 x i8> %b to <4 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %B2 = sitofp <4 x i8> %b to <4 x double> + + ; CHECK: cost of 3 {{.*}} sitofp + %C1 = sitofp <4 x i16> %c to <4 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %C2 = sitofp <4 x i16> %c to <4 x double> + + ; CHECK: cost of 1 {{.*}} sitofp + %D1 = sitofp <4 x i32> %d to <4 x float> + ; CHECK: cost of 1 {{.*}} sitofp + %D2 = sitofp <4 x i32> %d to <4 x double> + ret void +} + +define void @sitofp8(<8 x i1> %a, <8 x i8> %b, <8 x i16> %c, <8 x i32> %d) { + ; CHECK: cost of 8 {{.*}} sitofp + %A1 = sitofp <8 x i1> %a to <8 x float> + + ; CHECK: cost of 8 {{.*}} sitofp + %B1 = sitofp <8 x i8> %b to <8 x float> + + ; CHECK: cost of 5 {{.*}} sitofp + %C1 = sitofp <8 x i16> %c to <8 x float> + + ; CHECK: cost of 1 {{.*}} sitofp + %D1 = sitofp <8 x i32> %d to <8 x float> + ret void +} + +define void @uitofp4(<4 x i1> %a, <4 x i8> %b, <4 x i16> %c, <4 x i32> %d) { + ; CHECK: cost of 7 {{.*}} uitofp + %A1 = uitofp <4 x i1> %a to <4 x float> + ; CHECK: cost of 7 {{.*}} uitofp + %A2 = uitofp <4 x i1> %a to <4 x double> + + ; CHECK: cost of 2 {{.*}} uitofp + %B1 = uitofp <4 x i8> %b to <4 x float> + ; CHECK: cost of 2 {{.*}} uitofp + %B2 = uitofp <4 x i8> %b to <4 x double> + + ; CHECK: cost of 2 {{.*}} uitofp + %C1 = uitofp <4 x i16> %c to <4 x float> + ; CHECK: cost of 2 {{.*}} uitofp + %C2 = uitofp <4 x i16> %c to <4 x double> + + ; CHECK: cost of 6 {{.*}} uitofp + %D1 = uitofp <4 x i32> %d to <4 x float> + ; CHECK: cost of 6 {{.*}} uitofp + %D2 = uitofp <4 x i32> %d to <4 x double> + ret void +} + +define void @uitofp8(<8 x i1> %a, <8 x i8> %b, <8 x i16> %c, <8 x i32> %d) { + ; CHECK: cost of 6 {{.*}} uitofp + %A1 = uitofp <8 x i1> %a to <8 x float> + + ; CHECK: cost of 5 {{.*}} uitofp + %B1 = uitofp <8 x i8> %b to <8 x float> + + ; CHECK: cost of 5 {{.*}} uitofp + %C1 = uitofp <8 x i16> %c to <8 x float> + + ; CHECK: cost of 9 {{.*}} uitofp + %D1 = uitofp <8 x i32> %d to <8 x float> + ret void +} diff --git a/test/Analysis/CostModel/X86/cmp.ll b/test/Analysis/CostModel/X86/cmp.ll index f868bd18b54f..713b3742e920 100644 --- a/test/Analysis/CostModel/X86/cmp.ll +++ b/test/Analysis/CostModel/X86/cmp.ll @@ -1,41 +1,55 @@ -; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck --check-prefix=AVX1 %s +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core-avx2 | FileCheck --check-prefix=AVX2 %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" define i32 @cmp(i32 %arg) { ; -- floats -- - ;CHECK: cost of 1 {{.*}} fcmp + ;AVX1: cost of 1 {{.*}} fcmp + ;AVX2: cost of 1 {{.*}} fcmp %A = fcmp olt <2 x float> undef, undef - ;CHECK: cost of 1 {{.*}} fcmp + ;AVX1: cost of 1 {{.*}} fcmp + ;AVX2: cost of 1 {{.*}} fcmp %B = fcmp olt <4 x float> undef, undef - ;CHECK: cost of 1 {{.*}} fcmp + ;AVX1: cost of 1 {{.*}} fcmp + ;AVX2: cost of 1 {{.*}} fcmp %C = fcmp olt <8 x float> undef, undef - ;CHECK: cost of 1 {{.*}} fcmp + ;AVX1: cost of 1 {{.*}} fcmp + ;AVX2: cost of 1 {{.*}} fcmp %D = fcmp olt <2 x double> undef, undef - ;CHECK: cost of 1 {{.*}} fcmp + ;AVX1: cost of 1 {{.*}} fcmp + ;AVX2: cost of 1 {{.*}} fcmp %E = fcmp olt <4 x double> undef, undef ; -- integers -- - ;CHECK: cost of 1 {{.*}} icmp + ;AVX1: cost of 1 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %F = icmp eq <16 x i8> undef, undef - ;CHECK: cost of 1 {{.*}} icmp + ;AVX1: cost of 1 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %G = icmp eq <8 x i16> undef, undef - ;CHECK: cost of 1 {{.*}} icmp + ;AVX1: cost of 1 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %H = icmp eq <4 x i32> undef, undef - ;CHECK: cost of 1 {{.*}} icmp + ;AVX1: cost of 1 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %I = icmp eq <2 x i64> undef, undef - ;CHECK: cost of 4 {{.*}} icmp + ;AVX1: cost of 4 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %J = icmp eq <4 x i64> undef, undef - ;CHECK: cost of 4 {{.*}} icmp + ;AVX1: cost of 4 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %K = icmp eq <8 x i32> undef, undef - ;CHECK: cost of 4 {{.*}} icmp + ;AVX1: cost of 4 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %L = icmp eq <16 x i16> undef, undef - ;CHECK: cost of 4 {{.*}} icmp + ;AVX1: cost of 4 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %M = icmp eq <32 x i8> undef, undef - ;CHECK: cost of 1 {{.*}} ret + ;CHECK: cost of 0 {{.*}} ret ret i32 undef } diff --git a/test/Analysis/CostModel/X86/gep.ll b/test/Analysis/CostModel/X86/gep.ll new file mode 100644 index 000000000000..877184a3eaa8 --- /dev/null +++ b/test/Analysis/CostModel/X86/gep.ll @@ -0,0 +1,40 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + + +define void @test_geps() { + ; Cost of should be zero. We expect it to be folded into + ; the instruction addressing mode. +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i8* + %a0 = getelementptr inbounds i8* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i16* + %a1 = getelementptr inbounds i16* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i32* + %a2 = getelementptr inbounds i32* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i64* + %a3 = getelementptr inbounds i64* undef, i32 0 + +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds float* + %a4 = getelementptr inbounds float* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds double* + %a5 = getelementptr inbounds double* undef, i32 0 + + ; Vector geps should also have zero cost. +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i8>* + %a7 = getelementptr inbounds <4 x i8>* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i16>* + %a8 = getelementptr inbounds <4 x i16>* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i32>* + %a9 = getelementptr inbounds <4 x i32>* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i64>* + %a10 = getelementptr inbounds <4 x i64>* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x float>* + %a11 = getelementptr inbounds <4 x float>* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x double>* + %a12 = getelementptr inbounds <4 x double>* undef, i32 0 + + + ret void +} diff --git a/test/Analysis/CostModel/X86/i32.ll b/test/Analysis/CostModel/X86/i32.ll index 4015e0b1eef4..c2dce762a091 100644 --- a/test/Analysis/CostModel/X86/i32.ll +++ b/test/Analysis/CostModel/X86/i32.ll @@ -1,8 +1,6 @@ ; RUN: opt < %s -cost-model -analyze -mtriple=i386 -mcpu=corei7-avx | FileCheck %s - -;CHECK: cost of 2 {{.*}} add -;CHECK: cost of 1 {{.*}} ret +;CHECK: cost of 0 {{.*}} ret define i32 @no_info(i32 %arg) { %e = add i64 undef, undef ret i32 undef diff --git a/test/Analysis/CostModel/X86/intrinsic-cost.ll b/test/Analysis/CostModel/X86/intrinsic-cost.ll new file mode 100644 index 000000000000..e235a36222a7 --- /dev/null +++ b/test/Analysis/CostModel/X86/intrinsic-cost.ll @@ -0,0 +1,32 @@ +; RUN: opt -S -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck %s -check-prefix=CORE2 +; RUN: opt -S -mtriple=x86_64-apple-darwin -mcpu=corei7 -cost-model -analyze < %s | FileCheck %s -check-prefix=COREI7 + +; If SSE4.1 roundps instruction is available it is cheap to lower, otherwise +; it'll be scalarized into calls which are expensive. +define void @test1(float* nocapture %f) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds float* %f, i64 %index + %1 = bitcast float* %0 to <4 x float>* + %wide.load = load <4 x float>* %1, align 4 + %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load) + store <4 x float> %2, <4 x float>* %1, align 4 + %index.next = add i64 %index, 4 + %3 = icmp eq i64 %index.next, 1024 + br i1 %3, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; CORE2: Printing analysis 'Cost Model Analysis' for function 'test1': +; CORE2: Cost Model: Found an estimated cost of 400 for instruction: %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load) + +; COREI7: Printing analysis 'Cost Model Analysis' for function 'test1': +; COREI7: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load) + +} + +declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone diff --git a/test/Analysis/CostModel/X86/load_store.ll b/test/Analysis/CostModel/X86/load_store.ll new file mode 100644 index 000000000000..4195b1d879a1 --- /dev/null +++ b/test/Analysis/CostModel/X86/load_store.ll @@ -0,0 +1,64 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +define i32 @stores(i32 %arg) { + + ;CHECK: cost of 1 {{.*}} store + store i8 undef, i8* undef, align 4 + ;CHECK: cost of 1 {{.*}} store + store i16 undef, i16* undef, align 4 + ;CHECK: cost of 1 {{.*}} store + store i32 undef, i32* undef, align 4 + ;CHECK: cost of 1 {{.*}} store + store i64 undef, i64* undef, align 4 + ;CHECK: cost of 2 {{.*}} store + store i128 undef, i128* undef, align 4 + + ;CHECK: cost of 1 {{.*}} store + store <4 x i16> undef, <4 x i16>* undef, align 4 + ;CHECK: cost of 1 {{.*}} store + store <4 x i32> undef, <4 x i32>* undef, align 4 + ;CHECK: cost of 2 {{.*}} store + store <4 x i64> undef, <4 x i64>* undef, align 4 + + ;CHECK: cost of 1 {{.*}} store + store <8 x i16> undef, <8 x i16>* undef, align 4 + ;CHECK: cost of 2 {{.*}} store + store <8 x i32> undef, <8 x i32>* undef, align 4 + ;CHECK: cost of 4 {{.*}} store + store <8 x i64> undef, <8 x i64>* undef, align 4 + + ret i32 undef +} +define i32 @loads(i32 %arg) { + ;CHECK: cost of 1 {{.*}} load + load i8* undef, align 4 + ;CHECK: cost of 1 {{.*}} load + load i16* undef, align 4 + ;CHECK: cost of 1 {{.*}} load + load i32* undef, align 4 + ;CHECK: cost of 1 {{.*}} load + load i64* undef, align 4 + ;CHECK: cost of 2 {{.*}} load + load i128* undef, align 4 + + ;CHECK: cost of 1 {{.*}} load + load <2 x i32>* undef, align 4 + ;CHECK: cost of 1 {{.*}} load + load <4 x i32>* undef, align 4 + ;CHECK: cost of 2 {{.*}} load + load <8 x i32>* undef, align 4 + + + ;CHECK: cost of 1 {{.*}} load + load <2 x i64>* undef, align 4 + ;CHECK: cost of 2 {{.*}} load + load <4 x i64>* undef, align 4 + ;CHECK: cost of 4 {{.*}} load + load <8 x i64>* undef, align 4 + + ret i32 undef +} + diff --git a/test/Analysis/CostModel/X86/testshiftashr.ll b/test/Analysis/CostModel/X86/testshiftashr.ll new file mode 100644 index 000000000000..f35eea87164c --- /dev/null +++ b/test/Analysis/CostModel/X86/testshiftashr.ll @@ -0,0 +1,531 @@ +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core2 < %s | FileCheck --check-prefix=SSE2-CODEGEN %s +; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s + +%shifttype = type <2 x i16> +define %shifttype @shift2i16(%shifttype %a, %shifttype %b) { +entry: + ; SSE2: shift2i16 + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i16 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype %a , %b + ret %shifttype %0 +} + +%shifttype4i16 = type <4 x i16> +define %shifttype4i16 @shift4i16(%shifttype4i16 %a, %shifttype4i16 %b) { +entry: + ; SSE2: shift4i16 + ; SSE2: cost of 40 {{.*}} ashr + ; SSE2-CODEGEN: shift4i16 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype4i16 %a , %b + ret %shifttype4i16 %0 +} + +%shifttype8i16 = type <8 x i16> +define %shifttype8i16 @shift8i16(%shifttype8i16 %a, %shifttype8i16 %b) { +entry: + ; SSE2: shift8i16 + ; SSE2: cost of 80 {{.*}} ashr + ; SSE2-CODEGEN: shift8i16 + ; SSE2-CODEGEN: sarw %cl + + %0 = ashr %shifttype8i16 %a , %b + ret %shifttype8i16 %0 +} + +%shifttype16i16 = type <16 x i16> +define %shifttype16i16 @shift16i16(%shifttype16i16 %a, %shifttype16i16 %b) { +entry: + ; SSE2: shift16i16 + ; SSE2: cost of 160 {{.*}} ashr + ; SSE2-CODEGEN: shift16i16 + ; SSE2-CODEGEN: sarw %cl + + %0 = ashr %shifttype16i16 %a , %b + ret %shifttype16i16 %0 +} + +%shifttype32i16 = type <32 x i16> +define %shifttype32i16 @shift32i16(%shifttype32i16 %a, %shifttype32i16 %b) { +entry: + ; SSE2: shift32i16 + ; SSE2: cost of 320 {{.*}} ashr + ; SSE2-CODEGEN: shift32i16 + ; SSE2-CODEGEN: sarw %cl + + %0 = ashr %shifttype32i16 %a , %b + ret %shifttype32i16 %0 +} + +%shifttype2i32 = type <2 x i32> +define %shifttype2i32 @shift2i32(%shifttype2i32 %a, %shifttype2i32 %b) { +entry: + ; SSE2: shift2i32 + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i32 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype2i32 %a , %b + ret %shifttype2i32 %0 +} + +%shifttype4i32 = type <4 x i32> +define %shifttype4i32 @shift4i32(%shifttype4i32 %a, %shifttype4i32 %b) { +entry: + ; SSE2: shift4i32 + ; SSE2: cost of 40 {{.*}} ashr + ; SSE2-CODEGEN: shift4i32 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype4i32 %a , %b + ret %shifttype4i32 %0 +} + +%shifttype8i32 = type <8 x i32> +define %shifttype8i32 @shift8i32(%shifttype8i32 %a, %shifttype8i32 %b) { +entry: + ; SSE2: shift8i32 + ; SSE2: cost of 80 {{.*}} ashr + ; SSE2-CODEGEN: shift8i32 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype8i32 %a , %b + ret %shifttype8i32 %0 +} + +%shifttype16i32 = type <16 x i32> +define %shifttype16i32 @shift16i32(%shifttype16i32 %a, %shifttype16i32 %b) { +entry: + ; SSE2: shift16i32 + ; SSE2: cost of 160 {{.*}} ashr + ; SSE2-CODEGEN: shift16i32 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype16i32 %a , %b + ret %shifttype16i32 %0 +} + +%shifttype32i32 = type <32 x i32> +define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { +entry: + ; SSE2: shift32i32 + ; SSE2: cost of 256 {{.*}} ashr + ; SSE2-CODEGEN: shift32i32 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype32i32 %a , %b + ret %shifttype32i32 %0 +} + +%shifttype2i64 = type <2 x i64> +define %shifttype2i64 @shift2i64(%shifttype2i64 %a, %shifttype2i64 %b) { +entry: + ; SSE2: shift2i64 + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i64 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype2i64 %a , %b + ret %shifttype2i64 %0 +} + +%shifttype4i64 = type <4 x i64> +define %shifttype4i64 @shift4i64(%shifttype4i64 %a, %shifttype4i64 %b) { +entry: + ; SSE2: shift4i64 + ; SSE2: cost of 40 {{.*}} ashr + ; SSE2-CODEGEN: shift4i64 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype4i64 %a , %b + ret %shifttype4i64 %0 +} + +%shifttype8i64 = type <8 x i64> +define %shifttype8i64 @shift8i64(%shifttype8i64 %a, %shifttype8i64 %b) { +entry: + ; SSE2: shift8i64 + ; SSE2: cost of 80 {{.*}} ashr + ; SSE2-CODEGEN: shift8i64 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype8i64 %a , %b + ret %shifttype8i64 %0 +} + +%shifttype16i64 = type <16 x i64> +define %shifttype16i64 @shift16i64(%shifttype16i64 %a, %shifttype16i64 %b) { +entry: + ; SSE2: shift16i64 + ; SSE2: cost of 160 {{.*}} ashr + ; SSE2-CODEGEN: shift16i64 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype16i64 %a , %b + ret %shifttype16i64 %0 +} + +%shifttype32i64 = type <32 x i64> +define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { +entry: + ; SSE2: shift32i64 + ; SSE2: cost of 256 {{.*}} ashr + ; SSE2-CODEGEN: shift32i64 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype32i64 %a , %b + ret %shifttype32i64 %0 +} + +%shifttype2i8 = type <2 x i8> +define %shifttype2i8 @shift2i8(%shifttype2i8 %a, %shifttype2i8 %b) { +entry: + ; SSE2: shift2i8 + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i8 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype2i8 %a , %b + ret %shifttype2i8 %0 +} + +%shifttype4i8 = type <4 x i8> +define %shifttype4i8 @shift4i8(%shifttype4i8 %a, %shifttype4i8 %b) { +entry: + ; SSE2: shift4i8 + ; SSE2: cost of 40 {{.*}} ashr + ; SSE2-CODEGEN: shift4i8 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype4i8 %a , %b + ret %shifttype4i8 %0 +} + +%shifttype8i8 = type <8 x i8> +define %shifttype8i8 @shift8i8(%shifttype8i8 %a, %shifttype8i8 %b) { +entry: + ; SSE2: shift8i8 + ; SSE2: cost of 80 {{.*}} ashr + ; SSE2-CODEGEN: shift8i8 + ; SSE2-CODEGEN: sarw %cl + + %0 = ashr %shifttype8i8 %a , %b + ret %shifttype8i8 %0 +} + +%shifttype16i8 = type <16 x i8> +define %shifttype16i8 @shift16i8(%shifttype16i8 %a, %shifttype16i8 %b) { +entry: + ; SSE2: shift16i8 + ; SSE2: cost of 160 {{.*}} ashr + ; SSE2-CODEGEN: shift16i8 + ; SSE2-CODEGEN: sarb %cl + + %0 = ashr %shifttype16i8 %a , %b + ret %shifttype16i8 %0 +} + +%shifttype32i8 = type <32 x i8> +define %shifttype32i8 @shift32i8(%shifttype32i8 %a, %shifttype32i8 %b) { +entry: + ; SSE2: shift32i8 + ; SSE2: cost of 320 {{.*}} ashr + ; SSE2-CODEGEN: shift32i8 + ; SSE2-CODEGEN: sarb %cl + + %0 = ashr %shifttype32i8 %a , %b + ret %shifttype32i8 %0 +} + +; Test shift by a constant a value. + +%shifttypec = type <2 x i16> +define %shifttypec @shift2i16const(%shifttypec %a, %shifttypec %b) { +entry: + ; SSE2: shift2i16const + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i16const + ; SSE2-CODEGEN: sarq $ + + %0 = ashr %shifttypec %a , + ret %shifttypec %0 +} + +%shifttypec4i16 = type <4 x i16> +define %shifttypec4i16 @shift4i16const(%shifttypec4i16 %a, %shifttypec4i16 %b) { +entry: + ; SSE2: shift4i16const + ; SSE2: cost of 1 {{.*}} ashr + ; SSE2-CODEGEN: shift4i16const + ; SSE2-CODEGEN: psrad $3 + + %0 = ashr %shifttypec4i16 %a , + ret %shifttypec4i16 %0 +} + +%shifttypec8i16 = type <8 x i16> +define %shifttypec8i16 @shift8i16const(%shifttypec8i16 %a, %shifttypec8i16 %b) { +entry: + ; SSE2: shift8i16const + ; SSE2: cost of 1 {{.*}} ashr + ; SSE2-CODEGEN: shift8i16const + ; SSE2-CODEGEN: psraw $3 + + %0 = ashr %shifttypec8i16 %a , + ret %shifttypec8i16 %0 +} + +%shifttypec16i16 = type <16 x i16> +define %shifttypec16i16 @shift16i16const(%shifttypec16i16 %a, + %shifttypec16i16 %b) { +entry: + ; SSE2: shift16i16const + ; SSE2: cost of 2 {{.*}} ashr + ; SSE2-CODEGEN: shift16i16const + ; SSE2-CODEGEN: psraw $3 + + %0 = ashr %shifttypec16i16 %a , + ret %shifttypec16i16 %0 +} + +%shifttypec32i16 = type <32 x i16> +define %shifttypec32i16 @shift32i16const(%shifttypec32i16 %a, + %shifttypec32i16 %b) { +entry: + ; SSE2: shift32i16const + ; SSE2: cost of 4 {{.*}} ashr + ; SSE2-CODEGEN: shift32i16const + ; SSE2-CODEGEN: psraw $3 + + %0 = ashr %shifttypec32i16 %a , + ret %shifttypec32i16 %0 +} + +%shifttypec2i32 = type <2 x i32> +define %shifttypec2i32 @shift2i32c(%shifttypec2i32 %a, %shifttypec2i32 %b) { +entry: + ; SSE2: shift2i32c + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i32c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec2i32 %a , + ret %shifttypec2i32 %0 +} + +%shifttypec4i32 = type <4 x i32> +define %shifttypec4i32 @shift4i32c(%shifttypec4i32 %a, %shifttypec4i32 %b) { +entry: + ; SSE2: shift4i32c + ; SSE2: cost of 1 {{.*}} ashr + ; SSE2-CODEGEN: shift4i32c + ; SSE2-CODEGEN: psrad $3 + + %0 = ashr %shifttypec4i32 %a , + ret %shifttypec4i32 %0 +} + +%shifttypec8i32 = type <8 x i32> +define %shifttypec8i32 @shift8i32c(%shifttypec8i32 %a, %shifttypec8i32 %b) { +entry: + ; SSE2: shift8i32c + ; SSE2: cost of 2 {{.*}} ashr + ; SSE2-CODEGEN: shift8i32c + ; SSE2-CODEGEN: psrad $3 + + %0 = ashr %shifttypec8i32 %a , + ret %shifttypec8i32 %0 +} + +%shifttypec16i32 = type <16 x i32> +define %shifttypec16i32 @shift16i32c(%shifttypec16i32 %a, %shifttypec16i32 %b) { +entry: + ; SSE2: shift16i32c + ; SSE2: cost of 4 {{.*}} ashr + ; SSE2-CODEGEN: shift16i32c + ; SSE2-CODEGEN: psrad $3 + + %0 = ashr %shifttypec16i32 %a , + ret %shifttypec16i32 %0 +} + +%shifttypec32i32 = type <32 x i32> +define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { +entry: + ; SSE2: shift32i32c + ; getTypeConversion fails here and promotes this to a i64. + ; SSE2: cost of 256 {{.*}} ashr + ; SSE2-CODEGEN: shift32i32c + ; SSE2-CODEGEN: psrad $3 + %0 = ashr %shifttypec32i32 %a , + ret %shifttypec32i32 %0 +} + +%shifttypec2i64 = type <2 x i64> +define %shifttypec2i64 @shift2i64c(%shifttypec2i64 %a, %shifttypec2i64 %b) { +entry: + ; SSE2: shift2i64c + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i64c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec2i64 %a , + ret %shifttypec2i64 %0 +} + +%shifttypec4i64 = type <4 x i64> +define %shifttypec4i64 @shift4i64c(%shifttypec4i64 %a, %shifttypec4i64 %b) { +entry: + ; SSE2: shift4i64c + ; SSE2: cost of 40 {{.*}} ashr + ; SSE2-CODEGEN: shift4i64c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec4i64 %a , + ret %shifttypec4i64 %0 +} + +%shifttypec8i64 = type <8 x i64> +define %shifttypec8i64 @shift8i64c(%shifttypec8i64 %a, %shifttypec8i64 %b) { +entry: + ; SSE2: shift8i64c + ; SSE2: cost of 80 {{.*}} ashr + ; SSE2-CODEGEN: shift8i64c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec8i64 %a , + ret %shifttypec8i64 %0 +} + +%shifttypec16i64 = type <16 x i64> +define %shifttypec16i64 @shift16i64c(%shifttypec16i64 %a, %shifttypec16i64 %b) { +entry: + ; SSE2: shift16i64c + ; SSE2: cost of 160 {{.*}} ashr + ; SSE2-CODEGEN: shift16i64c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec16i64 %a , + ret %shifttypec16i64 %0 +} + +%shifttypec32i64 = type <32 x i64> +define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { +entry: + ; SSE2: shift32i64c + ; SSE2: cost of 256 {{.*}} ashr + ; SSE2-CODEGEN: shift32i64c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec32i64 %a , + ret %shifttypec32i64 %0 +} + +%shifttypec2i8 = type <2 x i8> +define %shifttypec2i8 @shift2i8c(%shifttypec2i8 %a, %shifttypec2i8 %b) { +entry: + ; SSE2: shift2i8c + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i8c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec2i8 %a , + ret %shifttypec2i8 %0 +} + +%shifttypec4i8 = type <4 x i8> +define %shifttypec4i8 @shift4i8c(%shifttypec4i8 %a, %shifttypec4i8 %b) { +entry: + ; SSE2: shift4i8c + ; SSE2: cost of 1 {{.*}} ashr + ; SSE2-CODEGEN: shift4i8c + ; SSE2-CODEGEN: psrad $3 + + %0 = ashr %shifttypec4i8 %a , + ret %shifttypec4i8 %0 +} + +%shifttypec8i8 = type <8 x i8> +define %shifttypec8i8 @shift8i8c(%shifttypec8i8 %a, %shifttypec8i8 %b) { +entry: + ; SSE2: shift8i8c + ; SSE2: cost of 1 {{.*}} ashr + ; SSE2-CODEGEN: shift8i8c + ; SSE2-CODEGEN: psraw $3 + + %0 = ashr %shifttypec8i8 %a , + ret %shifttypec8i8 %0 +} + +%shifttypec16i8 = type <16 x i8> +define %shifttypec16i8 @shift16i8c(%shifttypec16i8 %a, %shifttypec16i8 %b) { +entry: + ; SSE2: shift16i8c + ; SSE2: cost of 4 {{.*}} ashr + ; SSE2-CODEGEN: shift16i8c + ; SSE2-CODEGEN: psrlw $3 + + %0 = ashr %shifttypec16i8 %a , + ret %shifttypec16i8 %0 +} + +%shifttypec32i8 = type <32 x i8> +define %shifttypec32i8 @shift32i8c(%shifttypec32i8 %a, %shifttypec32i8 %b) { +entry: + ; SSE2: shift32i8c + ; SSE2: cost of 8 {{.*}} ashr + ; SSE2-CODEGEN: shift32i8c + ; SSE2-CODEGEN: psrlw $3 + + %0 = ashr %shifttypec32i8 %a , + ret %shifttypec32i8 %0 +} + diff --git a/test/Analysis/CostModel/X86/testshiftlshr.ll b/test/Analysis/CostModel/X86/testshiftlshr.ll new file mode 100644 index 000000000000..8d6ef3874208 --- /dev/null +++ b/test/Analysis/CostModel/X86/testshiftlshr.ll @@ -0,0 +1,530 @@ +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core2 < %s | FileCheck --check-prefix=SSE2-CODEGEN %s +; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s + +%shifttype = type <2 x i16> +define %shifttype @shift2i16(%shifttype %a, %shifttype %b) { +entry: + ; SSE2: shift2i16 + ; SSE2: cost of 20 {{.*}} lshr + ; SSE2-CODEGEN: shift2i16 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype %a , %b + ret %shifttype %0 +} + +%shifttype4i16 = type <4 x i16> +define %shifttype4i16 @shift4i16(%shifttype4i16 %a, %shifttype4i16 %b) { +entry: + ; SSE2: shift4i16 + ; SSE2: cost of 40 {{.*}} lshr + ; SSE2-CODEGEN: shift4i16 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype4i16 %a , %b + ret %shifttype4i16 %0 +} + +%shifttype8i16 = type <8 x i16> +define %shifttype8i16 @shift8i16(%shifttype8i16 %a, %shifttype8i16 %b) { +entry: + ; SSE2: shift8i16 + ; SSE2: cost of 80 {{.*}} lshr + ; SSE2-CODEGEN: shift8i16 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype8i16 %a , %b + ret %shifttype8i16 %0 +} + +%shifttype16i16 = type <16 x i16> +define %shifttype16i16 @shift16i16(%shifttype16i16 %a, %shifttype16i16 %b) { +entry: + ; SSE2: shift16i16 + ; SSE2: cost of 160 {{.*}} lshr + ; SSE2-CODEGEN: shift16i16 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype16i16 %a , %b + ret %shifttype16i16 %0 +} + +%shifttype32i16 = type <32 x i16> +define %shifttype32i16 @shift32i16(%shifttype32i16 %a, %shifttype32i16 %b) { +entry: + ; SSE2: shift32i16 + ; SSE2: cost of 320 {{.*}} lshr + ; SSE2-CODEGEN: shift32i16 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype32i16 %a , %b + ret %shifttype32i16 %0 +} + +%shifttype2i32 = type <2 x i32> +define %shifttype2i32 @shift2i32(%shifttype2i32 %a, %shifttype2i32 %b) { +entry: + ; SSE2: shift2i32 + ; SSE2: cost of 20 {{.*}} lshr + ; SSE2-CODEGEN: shift2i32 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype2i32 %a , %b + ret %shifttype2i32 %0 +} + +%shifttype4i32 = type <4 x i32> +define %shifttype4i32 @shift4i32(%shifttype4i32 %a, %shifttype4i32 %b) { +entry: + ; SSE2: shift4i32 + ; SSE2: cost of 40 {{.*}} lshr + ; SSE2-CODEGEN: shift4i32 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype4i32 %a , %b + ret %shifttype4i32 %0 +} + +%shifttype8i32 = type <8 x i32> +define %shifttype8i32 @shift8i32(%shifttype8i32 %a, %shifttype8i32 %b) { +entry: + ; SSE2: shift8i32 + ; SSE2: cost of 80 {{.*}} lshr + ; SSE2-CODEGEN: shift8i32 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype8i32 %a , %b + ret %shifttype8i32 %0 +} + +%shifttype16i32 = type <16 x i32> +define %shifttype16i32 @shift16i32(%shifttype16i32 %a, %shifttype16i32 %b) { +entry: + ; SSE2: shift16i32 + ; SSE2: cost of 160 {{.*}} lshr + ; SSE2-CODEGEN: shift16i32 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype16i32 %a , %b + ret %shifttype16i32 %0 +} + +%shifttype32i32 = type <32 x i32> +define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { +entry: + ; SSE2: shift32i32 + ; SSE2: cost of 256 {{.*}} lshr + ; SSE2-CODEGEN: shift32i32 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype32i32 %a , %b + ret %shifttype32i32 %0 +} + +%shifttype2i64 = type <2 x i64> +define %shifttype2i64 @shift2i64(%shifttype2i64 %a, %shifttype2i64 %b) { +entry: + ; SSE2: shift2i64 + ; SSE2: cost of 20 {{.*}} lshr + ; SSE2-CODEGEN: shift2i64 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype2i64 %a , %b + ret %shifttype2i64 %0 +} + +%shifttype4i64 = type <4 x i64> +define %shifttype4i64 @shift4i64(%shifttype4i64 %a, %shifttype4i64 %b) { +entry: + ; SSE2: shift4i64 + ; SSE2: cost of 40 {{.*}} lshr + ; SSE2-CODEGEN: shift4i64 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype4i64 %a , %b + ret %shifttype4i64 %0 +} + +%shifttype8i64 = type <8 x i64> +define %shifttype8i64 @shift8i64(%shifttype8i64 %a, %shifttype8i64 %b) { +entry: + ; SSE2: shift8i64 + ; SSE2: cost of 80 {{.*}} lshr + ; SSE2-CODEGEN: shift8i64 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype8i64 %a , %b + ret %shifttype8i64 %0 +} + +%shifttype16i64 = type <16 x i64> +define %shifttype16i64 @shift16i64(%shifttype16i64 %a, %shifttype16i64 %b) { +entry: + ; SSE2: shift16i64 + ; SSE2: cost of 160 {{.*}} lshr + ; SSE2-CODEGEN: shift16i64 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype16i64 %a , %b + ret %shifttype16i64 %0 +} + +%shifttype32i64 = type <32 x i64> +define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { +entry: + ; SSE2: shift32i64 + ; SSE2: cost of 256 {{.*}} lshr + ; SSE2-CODEGEN: shift32i64 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype32i64 %a , %b + ret %shifttype32i64 %0 +} + +%shifttype2i8 = type <2 x i8> +define %shifttype2i8 @shift2i8(%shifttype2i8 %a, %shifttype2i8 %b) { +entry: + ; SSE2: shift2i8 + ; SSE2: cost of 20 {{.*}} lshr + ; SSE2-CODEGEN: shift2i8 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype2i8 %a , %b + ret %shifttype2i8 %0 +} + +%shifttype4i8 = type <4 x i8> +define %shifttype4i8 @shift4i8(%shifttype4i8 %a, %shifttype4i8 %b) { +entry: + ; SSE2: shift4i8 + ; SSE2: cost of 40 {{.*}} lshr + ; SSE2-CODEGEN: shift4i8 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype4i8 %a , %b + ret %shifttype4i8 %0 +} + +%shifttype8i8 = type <8 x i8> +define %shifttype8i8 @shift8i8(%shifttype8i8 %a, %shifttype8i8 %b) { +entry: + ; SSE2: shift8i8 + ; SSE2: cost of 80 {{.*}} lshr + ; SSE2-CODEGEN: shift8i8 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype8i8 %a , %b + ret %shifttype8i8 %0 +} + +%shifttype16i8 = type <16 x i8> +define %shifttype16i8 @shift16i8(%shifttype16i8 %a, %shifttype16i8 %b) { +entry: + ; SSE2: shift16i8 + ; SSE2: cost of 160 {{.*}} lshr + ; SSE2-CODEGEN: shift16i8 + ; SSE2-CODEGEN: shrb %cl + + %0 = lshr %shifttype16i8 %a , %b + ret %shifttype16i8 %0 +} + +%shifttype32i8 = type <32 x i8> +define %shifttype32i8 @shift32i8(%shifttype32i8 %a, %shifttype32i8 %b) { +entry: + ; SSE2: shift32i8 + ; SSE2: cost of 320 {{.*}} lshr + ; SSE2-CODEGEN: shift32i8 + ; SSE2-CODEGEN: shrb %cl + + %0 = lshr %shifttype32i8 %a , %b + ret %shifttype32i8 %0 +} + +; Test shift by a constant vector. + +%shifttypec = type <2 x i16> +define %shifttypec @shift2i16const(%shifttypec %a, %shifttypec %b) { +entry: + ; SSE2: shift2i16const + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift2i16const + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec %a , + ret %shifttypec %0 +} + +%shifttypec4i16 = type <4 x i16> +define %shifttypec4i16 @shift4i16const(%shifttypec4i16 %a, %shifttypec4i16 %b) { +entry: + ; SSE2: shift4i16const + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift4i16const + ; SSE2-CODEGEN: psrld $3 + + %0 = lshr %shifttypec4i16 %a , + ret %shifttypec4i16 %0 +} + +%shifttypec8i16 = type <8 x i16> +define %shifttypec8i16 @shift8i16const(%shifttypec8i16 %a, %shifttypec8i16 %b) { +entry: + ; SSE2: shift8i16const + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift8i16const + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec8i16 %a , + ret %shifttypec8i16 %0 +} + +%shifttypec16i16 = type <16 x i16> +define %shifttypec16i16 @shift16i16const(%shifttypec16i16 %a, + %shifttypec16i16 %b) { +entry: + ; SSE2: shift16i16const + ; SSE2: cost of 2 {{.*}} lshr + ; SSE2-CODEGEN: shift16i16const + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec16i16 %a , + ret %shifttypec16i16 %0 +} + +%shifttypec32i16 = type <32 x i16> +define %shifttypec32i16 @shift32i16const(%shifttypec32i16 %a, + %shifttypec32i16 %b) { +entry: + ; SSE2: shift32i16const + ; SSE2: cost of 4 {{.*}} lshr + ; SSE2-CODEGEN: shift32i16const + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec32i16 %a , + ret %shifttypec32i16 %0 +} + +%shifttypec2i32 = type <2 x i32> +define %shifttypec2i32 @shift2i32c(%shifttypec2i32 %a, %shifttypec2i32 %b) { +entry: + ; SSE2: shift2i32c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift2i32c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec2i32 %a , + ret %shifttypec2i32 %0 +} + +%shifttypec4i32 = type <4 x i32> +define %shifttypec4i32 @shift4i32c(%shifttypec4i32 %a, %shifttypec4i32 %b) { +entry: + ; SSE2: shift4i32c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift4i32c + ; SSE2-CODEGEN: psrld $3 + + %0 = lshr %shifttypec4i32 %a , + ret %shifttypec4i32 %0 +} + +%shifttypec8i32 = type <8 x i32> +define %shifttypec8i32 @shift8i32c(%shifttypec8i32 %a, %shifttypec8i32 %b) { +entry: + ; SSE2: shift8i32c + ; SSE2: cost of 2 {{.*}} lshr + ; SSE2-CODEGEN: shift8i32c + ; SSE2-CODEGEN: psrld $3 + + %0 = lshr %shifttypec8i32 %a , + ret %shifttypec8i32 %0 +} + +%shifttypec16i32 = type <16 x i32> +define %shifttypec16i32 @shift16i32c(%shifttypec16i32 %a, %shifttypec16i32 %b) { +entry: + ; SSE2: shift16i32c + ; SSE2: cost of 4 {{.*}} lshr + ; SSE2-CODEGEN: shift16i32c + ; SSE2-CODEGEN: psrld $3 + + %0 = lshr %shifttypec16i32 %a , + ret %shifttypec16i32 %0 +} + +%shifttypec32i32 = type <32 x i32> +define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { +entry: + ; SSE2: shift32i32c + ; getTypeConversion fails here and promotes this to a i64. + ; SSE2: cost of 256 {{.*}} lshr + ; SSE2-CODEGEN: shift32i32c + ; SSE2-CODEGEN: psrld $3 + %0 = lshr %shifttypec32i32 %a , + ret %shifttypec32i32 %0 +} + +%shifttypec2i64 = type <2 x i64> +define %shifttypec2i64 @shift2i64c(%shifttypec2i64 %a, %shifttypec2i64 %b) { +entry: + ; SSE2: shift2i64c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift2i64c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec2i64 %a , + ret %shifttypec2i64 %0 +} + +%shifttypec4i64 = type <4 x i64> +define %shifttypec4i64 @shift4i64c(%shifttypec4i64 %a, %shifttypec4i64 %b) { +entry: + ; SSE2: shift4i64c + ; SSE2: cost of 2 {{.*}} lshr + ; SSE2-CODEGEN: shift4i64c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec4i64 %a , + ret %shifttypec4i64 %0 +} + +%shifttypec8i64 = type <8 x i64> +define %shifttypec8i64 @shift8i64c(%shifttypec8i64 %a, %shifttypec8i64 %b) { +entry: + ; SSE2: shift8i64c + ; SSE2: cost of 4 {{.*}} lshr + ; SSE2-CODEGEN: shift8i64c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec8i64 %a , + ret %shifttypec8i64 %0 +} + +%shifttypec16i64 = type <16 x i64> +define %shifttypec16i64 @shift16i64c(%shifttypec16i64 %a, %shifttypec16i64 %b) { +entry: + ; SSE2: shift16i64c + ; SSE2: cost of 8 {{.*}} lshr + ; SSE2-CODEGEN: shift16i64c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec16i64 %a , + ret %shifttypec16i64 %0 +} + +%shifttypec32i64 = type <32 x i64> +define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { +entry: + ; SSE2: shift32i64c + ; SSE2: cost of 256 {{.*}} lshr + ; SSE2-CODEGEN: shift32i64c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec32i64 %a , + ret %shifttypec32i64 %0 +} + +%shifttypec2i8 = type <2 x i8> +define %shifttypec2i8 @shift2i8c(%shifttypec2i8 %a, %shifttypec2i8 %b) { +entry: + ; SSE2: shift2i8c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift2i8c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec2i8 %a , + ret %shifttypec2i8 %0 +} + +%shifttypec4i8 = type <4 x i8> +define %shifttypec4i8 @shift4i8c(%shifttypec4i8 %a, %shifttypec4i8 %b) { +entry: + ; SSE2: shift4i8c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift4i8c + ; SSE2-CODEGEN: psrld $3 + + %0 = lshr %shifttypec4i8 %a , + ret %shifttypec4i8 %0 +} + +%shifttypec8i8 = type <8 x i8> +define %shifttypec8i8 @shift8i8c(%shifttypec8i8 %a, %shifttypec8i8 %b) { +entry: + ; SSE2: shift8i8c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift8i8c + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec8i8 %a , + ret %shifttypec8i8 %0 +} + +%shifttypec16i8 = type <16 x i8> +define %shifttypec16i8 @shift16i8c(%shifttypec16i8 %a, %shifttypec16i8 %b) { +entry: + ; SSE2: shift16i8c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift16i8c + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec16i8 %a , + ret %shifttypec16i8 %0 +} + +%shifttypec32i8 = type <32 x i8> +define %shifttypec32i8 @shift32i8c(%shifttypec32i8 %a, %shifttypec32i8 %b) { +entry: + ; SSE2: shift32i8c + ; SSE2: cost of 2 {{.*}} lshr + ; SSE2-CODEGEN: shift32i8c + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec32i8 %a , + ret %shifttypec32i8 %0 +} diff --git a/test/Analysis/CostModel/X86/testshiftshl.ll b/test/Analysis/CostModel/X86/testshiftshl.ll new file mode 100644 index 000000000000..f45a69879210 --- /dev/null +++ b/test/Analysis/CostModel/X86/testshiftshl.ll @@ -0,0 +1,530 @@ +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core2 < %s | FileCheck --check-prefix=SSE2-CODEGEN %s +; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s + +%shifttype = type <2 x i16> +define %shifttype @shift2i16(%shifttype %a, %shifttype %b) { +entry: + ; SSE2: shift2i16 + ; SSE2: cost of 20 {{.*}} shl + ; SSE2-CODEGEN: shift2i16 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype %a , %b + ret %shifttype %0 +} + +%shifttype4i16 = type <4 x i16> +define %shifttype4i16 @shift4i16(%shifttype4i16 %a, %shifttype4i16 %b) { +entry: + ; SSE2: shift4i16 + ; SSE2: cost of 10 {{.*}} shl + ; SSE2-CODEGEN: shift4i16 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype4i16 %a , %b + ret %shifttype4i16 %0 +} + +%shifttype8i16 = type <8 x i16> +define %shifttype8i16 @shift8i16(%shifttype8i16 %a, %shifttype8i16 %b) { +entry: + ; SSE2: shift8i16 + ; SSE2: cost of 80 {{.*}} shl + ; SSE2-CODEGEN: shift8i16 + ; SSE2-CODEGEN: shll %cl + + %0 = shl %shifttype8i16 %a , %b + ret %shifttype8i16 %0 +} + +%shifttype16i16 = type <16 x i16> +define %shifttype16i16 @shift16i16(%shifttype16i16 %a, %shifttype16i16 %b) { +entry: + ; SSE2: shift16i16 + ; SSE2: cost of 160 {{.*}} shl + ; SSE2-CODEGEN: shift16i16 + ; SSE2-CODEGEN: shll %cl + + %0 = shl %shifttype16i16 %a , %b + ret %shifttype16i16 %0 +} + +%shifttype32i16 = type <32 x i16> +define %shifttype32i16 @shift32i16(%shifttype32i16 %a, %shifttype32i16 %b) { +entry: + ; SSE2: shift32i16 + ; SSE2: cost of 320 {{.*}} shl + ; SSE2-CODEGEN: shift32i16 + ; SSE2-CODEGEN: shll %cl + + %0 = shl %shifttype32i16 %a , %b + ret %shifttype32i16 %0 +} + +%shifttype2i32 = type <2 x i32> +define %shifttype2i32 @shift2i32(%shifttype2i32 %a, %shifttype2i32 %b) { +entry: + ; SSE2: shift2i32 + ; SSE2: cost of 20 {{.*}} shl + ; SSE2-CODEGEN: shift2i32 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype2i32 %a , %b + ret %shifttype2i32 %0 +} + +%shifttype4i32 = type <4 x i32> +define %shifttype4i32 @shift4i32(%shifttype4i32 %a, %shifttype4i32 %b) { +entry: + ; SSE2: shift4i32 + ; SSE2: cost of 10 {{.*}} shl + ; SSE2-CODEGEN: shift4i32 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype4i32 %a , %b + ret %shifttype4i32 %0 +} + +%shifttype8i32 = type <8 x i32> +define %shifttype8i32 @shift8i32(%shifttype8i32 %a, %shifttype8i32 %b) { +entry: + ; SSE2: shift8i32 + ; SSE2: cost of 20 {{.*}} shl + ; SSE2-CODEGEN: shift8i32 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype8i32 %a , %b + ret %shifttype8i32 %0 +} + +%shifttype16i32 = type <16 x i32> +define %shifttype16i32 @shift16i32(%shifttype16i32 %a, %shifttype16i32 %b) { +entry: + ; SSE2: shift16i32 + ; SSE2: cost of 40 {{.*}} shl + ; SSE2-CODEGEN: shift16i32 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype16i32 %a , %b + ret %shifttype16i32 %0 +} + +%shifttype32i32 = type <32 x i32> +define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { +entry: + ; SSE2: shift32i32 + ; SSE2: cost of 256 {{.*}} shl + ; SSE2-CODEGEN: shift32i32 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype32i32 %a , %b + ret %shifttype32i32 %0 +} + +%shifttype2i64 = type <2 x i64> +define %shifttype2i64 @shift2i64(%shifttype2i64 %a, %shifttype2i64 %b) { +entry: + ; SSE2: shift2i64 + ; SSE2: cost of 20 {{.*}} shl + ; SSE2-CODEGEN: shift2i64 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype2i64 %a , %b + ret %shifttype2i64 %0 +} + +%shifttype4i64 = type <4 x i64> +define %shifttype4i64 @shift4i64(%shifttype4i64 %a, %shifttype4i64 %b) { +entry: + ; SSE2: shift4i64 + ; SSE2: cost of 40 {{.*}} shl + ; SSE2-CODEGEN: shift4i64 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype4i64 %a , %b + ret %shifttype4i64 %0 +} + +%shifttype8i64 = type <8 x i64> +define %shifttype8i64 @shift8i64(%shifttype8i64 %a, %shifttype8i64 %b) { +entry: + ; SSE2: shift8i64 + ; SSE2: cost of 80 {{.*}} shl + ; SSE2-CODEGEN: shift8i64 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype8i64 %a , %b + ret %shifttype8i64 %0 +} + +%shifttype16i64 = type <16 x i64> +define %shifttype16i64 @shift16i64(%shifttype16i64 %a, %shifttype16i64 %b) { +entry: + ; SSE2: shift16i64 + ; SSE2: cost of 160 {{.*}} shl + ; SSE2-CODEGEN: shift16i64 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype16i64 %a , %b + ret %shifttype16i64 %0 +} + +%shifttype32i64 = type <32 x i64> +define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { +entry: + ; SSE2: shift32i64 + ; SSE2: cost of 256 {{.*}} shl + ; SSE2-CODEGEN: shift32i64 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype32i64 %a , %b + ret %shifttype32i64 %0 +} + +%shifttype2i8 = type <2 x i8> +define %shifttype2i8 @shift2i8(%shifttype2i8 %a, %shifttype2i8 %b) { +entry: + ; SSE2: shift2i8 + ; SSE2: cost of 20 {{.*}} shl + ; SSE2-CODEGEN: shift2i8 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype2i8 %a , %b + ret %shifttype2i8 %0 +} + +%shifttype4i8 = type <4 x i8> +define %shifttype4i8 @shift4i8(%shifttype4i8 %a, %shifttype4i8 %b) { +entry: + ; SSE2: shift4i8 + ; SSE2: cost of 10 {{.*}} shl + ; SSE2-CODEGEN: shift4i8 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype4i8 %a , %b + ret %shifttype4i8 %0 +} + +%shifttype8i8 = type <8 x i8> +define %shifttype8i8 @shift8i8(%shifttype8i8 %a, %shifttype8i8 %b) { +entry: + ; SSE2: shift8i8 + ; SSE2: cost of 80 {{.*}} shl + ; SSE2-CODEGEN: shift8i8 + ; SSE2-CODEGEN: shll + + %0 = shl %shifttype8i8 %a , %b + ret %shifttype8i8 %0 +} + +%shifttype16i8 = type <16 x i8> +define %shifttype16i8 @shift16i8(%shifttype16i8 %a, %shifttype16i8 %b) { +entry: + ; SSE2: shift16i8 + ; SSE2: cost of 30 {{.*}} shl + ; SSE2-CODEGEN: shift16i8 + ; SSE2-CODEGEN: cmpeqb + + %0 = shl %shifttype16i8 %a , %b + ret %shifttype16i8 %0 +} + +%shifttype32i8 = type <32 x i8> +define %shifttype32i8 @shift32i8(%shifttype32i8 %a, %shifttype32i8 %b) { +entry: + ; SSE2: shift32i8 + ; SSE2: cost of 60 {{.*}} shl + ; SSE2-CODEGEN: shift32i8 + ; SSE2-CODEGEN: cmpeqb + + %0 = shl %shifttype32i8 %a , %b + ret %shifttype32i8 %0 +} + +; Test shift by a constant vector. + +%shifttypec = type <2 x i16> +define %shifttypec @shift2i16const(%shifttypec %a, %shifttypec %b) { +entry: + ; SSE2: shift2i16const + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift2i16const + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec %a , + ret %shifttypec %0 +} + +%shifttypec4i16 = type <4 x i16> +define %shifttypec4i16 @shift4i16const(%shifttypec4i16 %a, %shifttypec4i16 %b) { +entry: + ; SSE2: shift4i16const + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift4i16const + ; SSE2-CODEGEN: pslld $3 + + %0 = shl %shifttypec4i16 %a , + ret %shifttypec4i16 %0 +} + +%shifttypec8i16 = type <8 x i16> +define %shifttypec8i16 @shift8i16const(%shifttypec8i16 %a, %shifttypec8i16 %b) { +entry: + ; SSE2: shift8i16const + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift8i16const + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec8i16 %a , + ret %shifttypec8i16 %0 +} + +%shifttypec16i16 = type <16 x i16> +define %shifttypec16i16 @shift16i16const(%shifttypec16i16 %a, + %shifttypec16i16 %b) { +entry: + ; SSE2: shift16i16const + ; SSE2: cost of 2 {{.*}} shl + ; SSE2-CODEGEN: shift16i16const + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec16i16 %a , + ret %shifttypec16i16 %0 +} + +%shifttypec32i16 = type <32 x i16> +define %shifttypec32i16 @shift32i16const(%shifttypec32i16 %a, + %shifttypec32i16 %b) { +entry: + ; SSE2: shift32i16const + ; SSE2: cost of 4 {{.*}} shl + ; SSE2-CODEGEN: shift32i16const + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec32i16 %a , + ret %shifttypec32i16 %0 +} + +%shifttypec2i32 = type <2 x i32> +define %shifttypec2i32 @shift2i32c(%shifttypec2i32 %a, %shifttypec2i32 %b) { +entry: + ; SSE2: shift2i32c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift2i32c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec2i32 %a , + ret %shifttypec2i32 %0 +} + +%shifttypec4i32 = type <4 x i32> +define %shifttypec4i32 @shift4i32c(%shifttypec4i32 %a, %shifttypec4i32 %b) { +entry: + ; SSE2: shift4i32c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift4i32c + ; SSE2-CODEGEN: pslld $3 + + %0 = shl %shifttypec4i32 %a , + ret %shifttypec4i32 %0 +} + +%shifttypec8i32 = type <8 x i32> +define %shifttypec8i32 @shift8i32c(%shifttypec8i32 %a, %shifttypec8i32 %b) { +entry: + ; SSE2: shift8i32c + ; SSE2: cost of 2 {{.*}} shl + ; SSE2-CODEGEN: shift8i32c + ; SSE2-CODEGEN: pslld $3 + + %0 = shl %shifttypec8i32 %a , + ret %shifttypec8i32 %0 +} + +%shifttypec16i32 = type <16 x i32> +define %shifttypec16i32 @shift16i32c(%shifttypec16i32 %a, %shifttypec16i32 %b) { +entry: + ; SSE2: shift16i32c + ; SSE2: cost of 4 {{.*}} shl + ; SSE2-CODEGEN: shift16i32c + ; SSE2-CODEGEN: pslld $3 + + %0 = shl %shifttypec16i32 %a , + ret %shifttypec16i32 %0 +} + +%shifttypec32i32 = type <32 x i32> +define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { +entry: + ; SSE2: shift32i32c + ; getTypeConversion fails here and promotes this to a i64. + ; SSE2: cost of 256 {{.*}} shl + ; SSE2-CODEGEN: shift32i32c + ; SSE2-CODEGEN: pslld $3 + %0 = shl %shifttypec32i32 %a , + ret %shifttypec32i32 %0 +} + +%shifttypec2i64 = type <2 x i64> +define %shifttypec2i64 @shift2i64c(%shifttypec2i64 %a, %shifttypec2i64 %b) { +entry: + ; SSE2: shift2i64c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift2i64c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec2i64 %a , + ret %shifttypec2i64 %0 +} + +%shifttypec4i64 = type <4 x i64> +define %shifttypec4i64 @shift4i64c(%shifttypec4i64 %a, %shifttypec4i64 %b) { +entry: + ; SSE2: shift4i64c + ; SSE2: cost of 2 {{.*}} shl + ; SSE2-CODEGEN: shift4i64c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec4i64 %a , + ret %shifttypec4i64 %0 +} + +%shifttypec8i64 = type <8 x i64> +define %shifttypec8i64 @shift8i64c(%shifttypec8i64 %a, %shifttypec8i64 %b) { +entry: + ; SSE2: shift8i64c + ; SSE2: cost of 4 {{.*}} shl + ; SSE2-CODEGEN: shift8i64c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec8i64 %a , + ret %shifttypec8i64 %0 +} + +%shifttypec16i64 = type <16 x i64> +define %shifttypec16i64 @shift16i64c(%shifttypec16i64 %a, %shifttypec16i64 %b) { +entry: + ; SSE2: shift16i64c + ; SSE2: cost of 8 {{.*}} shl + ; SSE2-CODEGEN: shift16i64c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec16i64 %a , + ret %shifttypec16i64 %0 +} + +%shifttypec32i64 = type <32 x i64> +define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { +entry: + ; SSE2: shift32i64c + ; SSE2: cost of 256 {{.*}} shl + ; SSE2-CODEGEN: shift32i64c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec32i64 %a , + ret %shifttypec32i64 %0 +} + +%shifttypec2i8 = type <2 x i8> +define %shifttypec2i8 @shift2i8c(%shifttypec2i8 %a, %shifttypec2i8 %b) { +entry: + ; SSE2: shift2i8c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift2i8c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec2i8 %a , + ret %shifttypec2i8 %0 +} + +%shifttypec4i8 = type <4 x i8> +define %shifttypec4i8 @shift4i8c(%shifttypec4i8 %a, %shifttypec4i8 %b) { +entry: + ; SSE2: shift4i8c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift4i8c + ; SSE2-CODEGEN: pslld $3 + + %0 = shl %shifttypec4i8 %a , + ret %shifttypec4i8 %0 +} + +%shifttypec8i8 = type <8 x i8> +define %shifttypec8i8 @shift8i8c(%shifttypec8i8 %a, %shifttypec8i8 %b) { +entry: + ; SSE2: shift8i8c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift8i8c + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec8i8 %a , + ret %shifttypec8i8 %0 +} + +%shifttypec16i8 = type <16 x i8> +define %shifttypec16i8 @shift16i8c(%shifttypec16i8 %a, %shifttypec16i8 %b) { +entry: + ; SSE2: shift16i8c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift16i8c + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec16i8 %a , + ret %shifttypec16i8 %0 +} + +%shifttypec32i8 = type <32 x i8> +define %shifttypec32i8 @shift32i8c(%shifttypec32i8 %a, %shifttypec32i8 %b) { +entry: + ; SSE2: shift32i8c + ; SSE2: cost of 2 {{.*}} shl + ; SSE2-CODEGEN: shift32i8c + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec32i8 %a , + ret %shifttypec32i8 %0 +} diff --git a/test/Analysis/CostModel/X86/tiny.ll b/test/Analysis/CostModel/X86/tiny.ll index cc7b443a7dfc..0dafdadb5b15 100644 --- a/test/Analysis/CostModel/X86/tiny.ll +++ b/test/Analysis/CostModel/X86/tiny.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-macosx10.8.0" ;CHECK: cost of 1 {{.*}} add -;CHECK: cost of 1 {{.*}} ret +;CHECK: cost of 0 {{.*}} ret define i32 @no_info(i32 %arg) { %e = add i32 %arg, %arg ret i32 %e diff --git a/test/Analysis/CostModel/X86/vectorized-loop.ll b/test/Analysis/CostModel/X86/vectorized-loop.ll index 7919a9ca9a64..25b11145c661 100644 --- a/test/Analysis/CostModel/X86/vectorized-loop.ll +++ b/test/Analysis/CostModel/X86/vectorized-loop.ll @@ -28,20 +28,21 @@ vector.body: ; preds = %for.body.lr.ph, %ve %4 = getelementptr inbounds i32* %B, i64 %3 ;CHECK: cost of 0 {{.*}} bitcast %5 = bitcast i32* %4 to <8 x i32>* - ;CHECK: cost of 1 {{.*}} load + ;CHECK: cost of 2 {{.*}} load %6 = load <8 x i32>* %5, align 4 ;CHECK: cost of 4 {{.*}} mul %7 = mul nsw <8 x i32> %6, %8 = getelementptr inbounds i32* %A, i64 %index %9 = bitcast i32* %8 to <8 x i32>* + ;CHECK: cost of 2 {{.*}} load %10 = load <8 x i32>* %9, align 4 ;CHECK: cost of 4 {{.*}} add %11 = add nsw <8 x i32> %10, %7 - ;CHECK: cost of 1 {{.*}} store + ;CHECK: cost of 2 {{.*}} store store <8 x i32> %11, <8 x i32>* %9, align 4 %index.next = add i64 %index, 8 %12 = icmp eq i64 %index.next, %end.idx.rnd.down - ;CHECK: cost of 1 {{.*}} br + ;CHECK: cost of 0 {{.*}} br br i1 %12, label %middle.block, label %vector.body middle.block: ; preds = %vector.body, %for.body.lr.ph @@ -65,11 +66,11 @@ for.body: ; preds = %middle.block, %for. ;CHECK: cost of 0 {{.*}} trunc %16 = trunc i64 %indvars.iv.next to i32 %cmp = icmp slt i32 %16, %end - ;CHECK: cost of 1 {{.*}} br + ;CHECK: cost of 0 {{.*}} br br i1 %cmp, label %for.body, label %for.end for.end: ; preds = %middle.block, %for.body, %entry - ;CHECK: cost of 1 {{.*}} ret + ;CHECK: cost of 0 {{.*}} ret ret i32 undef } diff --git a/test/Analysis/CostModel/no_info.ll b/test/Analysis/CostModel/no_info.ll index d20d56b79a7f..f3f165b1b52a 100644 --- a/test/Analysis/CostModel/no_info.ll +++ b/test/Analysis/CostModel/no_info.ll @@ -1,11 +1,8 @@ ; RUN: opt < %s -cost-model -analyze | FileCheck %s ; The cost model does not have any target information so it can't make a decision. -; Notice that OPT does not read the triple information from the module itself, only through the command line. -; This info ignored: -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -target triple = "x86_64-apple-macosx10.8.0" +; -- No triple in this module -- ;CHECK: Unknown cost {{.*}} add ;CHECK: Unknown cost {{.*}} ret diff --git a/test/Analysis/DependenceAnalysis/Banerjee.ll b/test/Analysis/DependenceAnalysis/Banerjee.ll index 8865ee94016f..003ee03ab0be 100644 --- a/test/Analysis/DependenceAnalysis/Banerjee.ll +++ b/test/Analysis/DependenceAnalysis/Banerjee.ll @@ -7,13 +7,20 @@ target triple = "x86_64-apple-macosx10.6.0" ;; for (long int i = 1; i <= 10; i++) ;; for (long int j = 1; j <= 10; j++) { -;; A[10*i + j] = ... -;; ... = A[10*i + j - 1]; +;; A[10*i + j] = 0; +;; *B++ = A[10*i + j - 1]; define void @banerjee0(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - flow [<= <>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc7 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc7 ] %i.03 = phi i64 [ 1, %entry ], [ %inc8, %for.inc7 ] @@ -31,7 +38,6 @@ for.body3: ; preds = %for.cond1.preheader %sub = add nsw i64 %add5, -1 %arrayidx6 = getelementptr inbounds i64* %A, i64 %sub %0 = load i64* %arrayidx6, align 8 -; CHECK: da analyze - flow [<= <>]! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %0, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -51,14 +57,21 @@ for.end9: ; preds = %for.inc7 ;; for (long int i = 1; i <= n; i++) ;; for (long int j = 1; j <= m; j++) { -;; A[10*i + j] = ... -;; ... = A[10*i + j - 1]; +;; A[10*i + j] = 0; +;; *B++ = A[10*i + j - 1]; define void @banerjee1(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: %cmp4 = icmp sgt i64 %n, 0 br i1 %cmp4, label %for.cond1.preheader.preheader, label %for.end9 +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - flow [* <>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - output [* *]! + for.cond1.preheader.preheader: ; preds = %entry %0 = add i64 %n, 1 br label %for.cond1.preheader @@ -85,7 +98,6 @@ for.body3: ; preds = %for.body3.preheader %sub = add nsw i64 %add5, -1 %arrayidx6 = getelementptr inbounds i64* %A, i64 %sub %2 = load i64* %arrayidx6, align 8 -; CHECK: da analyze - flow [* <>]! %incdec.ptr = getelementptr inbounds i64* %B.addr.12, i64 1 store i64 %2, i64* %B.addr.12, align 8 %inc = add nsw i64 %j.03, 1 @@ -119,6 +131,13 @@ define void @banerjee2(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc8 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc8 ] %i.03 = phi i64 [ 0, %entry ], [ %inc9, %for.inc8 ] @@ -136,7 +155,6 @@ for.body3: ; preds = %for.cond1.preheader %add6 = add nsw i64 %add5, 100 %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6 %0 = load i64* %arrayidx7, align 8 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %0, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -156,13 +174,20 @@ for.end10: ; preds = %for.inc8 ;; for (long int i = 0; i < 10; i++) ;; for (long int j = 0; j < 10; j++) { -;; A[10*i + j] = ... -;; ... = A[10*i + j + 99]; +;; A[10*i + j] = 0; +;; *B++ = A[10*i + j + 99]; define void @banerjee3(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - flow [> >]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc8 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc8 ] %i.03 = phi i64 [ 0, %entry ], [ %inc9, %for.inc8 ] @@ -180,7 +205,6 @@ for.body3: ; preds = %for.cond1.preheader %add6 = add nsw i64 %add5, 99 %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6 %0 = load i64* %arrayidx7, align 8 -; CHECK: da analyze - flow [> >]! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %0, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -200,13 +224,20 @@ for.end10: ; preds = %for.inc8 ;; for (long int i = 0; i < 10; i++) ;; for (long int j = 0; j < 10; j++) { -;; A[10*i + j] = ... -;; ... = A[10*i + j - 100]; +;; A[10*i + j] = 0; +;; *B++ = A[10*i + j - 100]; define void @banerjee4(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc7 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc7 ] %i.03 = phi i64 [ 0, %entry ], [ %inc8, %for.inc7 ] @@ -224,7 +255,6 @@ for.body3: ; preds = %for.cond1.preheader %sub = add nsw i64 %add5, -100 %arrayidx6 = getelementptr inbounds i64* %A, i64 %sub %0 = load i64* %arrayidx6, align 8 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %0, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -244,13 +274,20 @@ for.end9: ; preds = %for.inc7 ;; for (long int i = 0; i < 10; i++) ;; for (long int j = 0; j < 10; j++) { -;; A[10*i + j] = ... -;; ... = A[10*i + j - 99]; +;; A[10*i + j] = 0; +;; *B++ = A[10*i + j - 99]; define void @banerjee5(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - flow [< <]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc7 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc7 ] %i.03 = phi i64 [ 0, %entry ], [ %inc8, %for.inc7 ] @@ -268,7 +305,6 @@ for.body3: ; preds = %for.cond1.preheader %sub = add nsw i64 %add5, -99 %arrayidx6 = getelementptr inbounds i64* %A, i64 %sub %0 = load i64* %arrayidx6, align 8 -; CHECK: da analyze - flow [< <]! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %0, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -288,13 +324,20 @@ for.end9: ; preds = %for.inc7 ;; for (long int i = 0; i < 10; i++) ;; for (long int j = 0; j < 10; j++) { -;; A[10*i + j] = ... -;; ... = A[10*i + j + 9]; +;; A[10*i + j] = 0; +;; *B++ = A[10*i + j + 9]; define void @banerjee6(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - flow [=> <>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc8 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc8 ] %i.03 = phi i64 [ 0, %entry ], [ %inc9, %for.inc8 ] @@ -312,7 +355,6 @@ for.body3: ; preds = %for.cond1.preheader %add6 = add nsw i64 %add5, 9 %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6 %0 = load i64* %arrayidx7, align 8 -; CHECK: da analyze - flow [=> <>]! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %0, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -332,13 +374,20 @@ for.end10: ; preds = %for.inc8 ;; for (long int i = 0; i < 10; i++) ;; for (long int j = 0; j < 10; j++) { -;; A[10*i + j] = ... -;; ... = A[10*i + j + 10]; +;; A[10*i + j] = 0; +;; *B++ = A[10*i + j + 10]; define void @banerjee7(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - flow [> <=]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc8 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc8 ] %i.03 = phi i64 [ 0, %entry ], [ %inc9, %for.inc8 ] @@ -356,7 +405,6 @@ for.body3: ; preds = %for.cond1.preheader %add6 = add nsw i64 %add5, 10 %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6 %0 = load i64* %arrayidx7, align 8 -; CHECK: da analyze - flow [> <=]! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %0, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -376,13 +424,20 @@ for.end10: ; preds = %for.inc8 ;; for (long int i = 0; i < 10; i++) ;; for (long int j = 0; j < 10; j++) { -;; A[10*i + j] = ... -;; ... = A[10*i + j + 11]; +;; A[10*i + j] = 0; +;; *B++ = A[10*i + j + 11]; define void @banerjee8(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - flow [> <>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc8 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc8 ] %i.03 = phi i64 [ 0, %entry ], [ %inc9, %for.inc8 ] @@ -400,7 +455,6 @@ for.body3: ; preds = %for.cond1.preheader %add6 = add nsw i64 %add5, 11 %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6 %0 = load i64* %arrayidx7, align 8 -; CHECK: da analyze - flow [> <>]! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %0, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -420,13 +474,20 @@ for.end10: ; preds = %for.inc8 ;; for (long int i = 0; i < 20; i++) ;; for (long int j = 0; j < 20; j++) { -;; A[30*i + 500*j] = ... -;; ... = A[i - 500*j + 11]; +;; A[30*i + 500*j] = 0; +;; *B++ = A[i - 500*j + 11]; define void @banerjee9(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - flow [<= =|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc8 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc8 ] %i.03 = phi i64 [ 0, %entry ], [ %inc9, %for.inc8 ] @@ -445,7 +506,6 @@ for.body3: ; preds = %for.cond1.preheader %add6 = add nsw i64 %sub, 11 %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6 %1 = load i64* %arrayidx7, align 8 -; CHECK: da analyze - flow [<= =|<]! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %1, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -465,13 +525,20 @@ for.end10: ; preds = %for.inc8 ;; for (long int i = 0; i < 20; i++) ;; for (long int j = 0; j < 20; j++) { -;; A[i + 500*j] = ... -;; ... = A[i - 500*j + 11]; +;; A[i + 500*j] = 0; +;; *B++ = A[i - 500*j + 11]; define void @banerjee10(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - flow [<> =]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc7 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc7 ] %i.03 = phi i64 [ 0, %entry ], [ %inc8, %for.inc7 ] @@ -489,7 +556,6 @@ for.body3: ; preds = %for.cond1.preheader %add5 = add nsw i64 %sub, 11 %arrayidx6 = getelementptr inbounds i64* %A, i64 %add5 %1 = load i64* %arrayidx6, align 8 -; CHECK: da analyze - flow [<> =]! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %1, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -509,13 +575,20 @@ for.end9: ; preds = %for.inc7 ;; for (long int i = 0; i < 20; i++) ;; for (long int j = 0; j < 20; j++) { -;; A[300*i + j] = ... -;; ... = A[250*i - j + 11]; +;; A[300*i + j] = 0; +;; *B++ = A[250*i - j + 11]; define void @banerjee11(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - flow [<= <>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc7 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc7 ] %i.03 = phi i64 [ 0, %entry ], [ %inc8, %for.inc7 ] @@ -533,7 +606,6 @@ for.body3: ; preds = %for.cond1.preheader %add5 = add nsw i64 %sub, 11 %arrayidx6 = getelementptr inbounds i64* %A, i64 %add5 %0 = load i64* %arrayidx6, align 8 -; CHECK: da analyze - flow [<= <>]! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %0, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 @@ -553,13 +625,20 @@ for.end9: ; preds = %for.inc7 ;; for (long int i = 0; i < 20; i++) ;; for (long int j = 0; j < 20; j++) { -;; A[100*i + j] = ... -;; ... = A[100*i - j + 11]; +;; A[100*i + j] = 0; +;; *B++ = A[100*i - j + 11]; define void @banerjee12(i64* %A, i64* %B, i64 %m, i64 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - flow [= <>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc7 %B.addr.04 = phi i64* [ %B, %entry ], [ %scevgep, %for.inc7 ] %i.03 = phi i64 [ 0, %entry ], [ %inc8, %for.inc7 ] @@ -577,7 +656,6 @@ for.body3: ; preds = %for.cond1.preheader %add5 = add nsw i64 %sub, 11 %arrayidx6 = getelementptr inbounds i64* %A, i64 %add5 %0 = load i64* %arrayidx6, align 8 -; CHECK: da analyze - flow [= <>]! %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1 store i64 %0, i64* %B.addr.11, align 8 %inc = add nsw i64 %j.02, 1 diff --git a/test/Analysis/DependenceAnalysis/Coupled.ll b/test/Analysis/DependenceAnalysis/Coupled.ll index 60163fe7c2d0..8c77849ae847 100644 --- a/test/Analysis/DependenceAnalysis/Coupled.ll +++ b/test/Analysis/DependenceAnalysis/Coupled.ll @@ -5,15 +5,22 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-macosx10.6.0" -;; for (long int i = 0; i < 50; i++) -;; A[i][i] = ... -;; ... = A[i + 10][i + 9] +;; for (long int i = 0; i < 50; i++) { +;; A[i][i] = i; +;; *B++ = A[i + 10][i + 9]; define void @couple0([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -23,27 +30,33 @@ for.body: ; preds = %for.body, %entry %add2 = add nsw i64 %i.02, 10 %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %add2, i64 %add %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 50 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i < 50; i++) -;; A[i][i] = ... -;; ... = A[i + 9][i + 9] +;; for (long int i = 0; i < 50; i++) { +;; A[i][i] = i; +;; *B++ = A[i + 9][i + 9]; define void @couple1([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [-9]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -53,27 +66,33 @@ for.body: ; preds = %for.body, %entry %add2 = add nsw i64 %i.02, 9 %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %add2, i64 %add %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - consistent flow [-9]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 50 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i < 50; i++) -;; A[3*i - 6][3*i - 6] = ... -;; ... = A[i][i] +;; for (long int i = 0; i < 50; i++) { +;; A[3*i - 6][3*i - 6] = i; +;; *B++ = A[i][i]; define void @couple2([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [*|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -85,27 +104,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx3, align 4 %arrayidx5 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - flow [*|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 50 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i < 50; i++) -;; A[3*i - 6][3*i - 5] = ... -;; ... = A[i][i] +;; for (long int i = 0; i < 50; i++) { +;; A[3*i - 6][3*i - 5] = i; +;; *B++ = A[i][i]; define void @couple3([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -117,27 +142,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx3, align 4 %arrayidx5 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 50 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i < 50; i++) -;; A[3*i - 6][3*i - n] = ... -;; ... = A[i][i] +;; for (long int i = 0; i < 50; i++) { +;; A[3*i - 6][3*i - n] = i; +;; *B++ = A[i][i]; define void @couple4([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [*|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -150,27 +181,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx4, align 4 %arrayidx6 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx6, align 4 -; CHECK: da analyze - flow [*|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 50 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i < 50; i++) -;; A[3*i - n + 1][3*i - n] = ... -;; ... = A[i][i] +;; for (long int i = 0; i < 50; i++) { +;; A[3*i - n + 1][3*i - n] = i; +;; *B++ = A[i][i]; define void @couple5([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -185,27 +222,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx5, align 4 %arrayidx7 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx7, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 50 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i < 50; i++) -;; A[i][3*i - 6] = ... -;; ... = A[i][i] +;; for (long int i = 0; i < 50; i++) { +;; A[i][3*i - 6] = i; +;; *B++ = A[i][i]; define void @couple6([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [=|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -215,27 +258,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx1, align 4 %arrayidx3 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx3, align 4 -; CHECK: da analyze - flow [=|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 50 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i < 50; i++) -;; A[i][3*i - 5] = ... -;; ... = A[i][i] +;; for (long int i = 0; i < 50; i++) { +;; A[i][3*i - 5] = i; +;; *B++ = A[i][i]; define void @couple7([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -245,27 +294,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx1, align 4 %arrayidx3 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx3, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 50 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i <= 15; i++) -;; A[3*i - 18][3 - i] = ... -;; ... = A[i][i] +;; for (long int i = 0; i <= 15; i++) { +;; A[3*i - 18][3 - i] = i; +;; *B++ = A[i][i]; define void @couple8([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -276,27 +331,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx2, align 4 %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 16 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 16 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i <= 15; i++) -;; A[3*i - 18][2 - i] = ... -;; ... = A[i][i] +;; for (long int i = 0; i <= 15; i++) { +;; A[3*i - 18][2 - i] = i; +;; *B++ = A[i][i]; define void @couple9([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -307,27 +368,34 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx2, align 4 %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 16 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 16 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i <= 15; i++) -;; A[3*i - 18][6 - i] = ... -;; ... = A[i][i] +;; for (long int i = 0; i <= 15; i++) { +;; A[3*i - 18][6 - i] = i; +;; *B++ = A[i][i]; define void @couple10([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [>] splitable! +; CHECK: da analyze - split level = 1, iteration = 3! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -338,28 +406,34 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx2, align 4 %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - flow [>] splitable! -; CHECK: da analyze - split level = 1, iteration = 3! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 16 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 16 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i <= 15; i++) -;; A[3*i - 18][18 - i] = ... -;; ... = A[i][i] +;; for (long int i = 0; i <= 15; i++) { +;; A[3*i - 18][18 - i] = i; +;; *B++ = A[i][i]; define void @couple11([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [=|<] splitable! +; CHECK: da analyze - split level = 1, iteration = 9! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -370,28 +444,34 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx2, align 4 %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - flow [=|<] splitable! -; CHECK: da analyze - split level = 1, iteration = 9! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 16 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 16 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i <= 12; i++) -;; A[3*i - 18][22 - i] = ... -;; ... = A[i][i] +;; for (long int i = 0; i <= 12; i++) { +;; A[3*i - 18][22 - i] = i; +;; *B++ = A[i][i]; define void @couple12([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [<] splitable! +; CHECK: da analyze - split level = 1, iteration = 11! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -402,28 +482,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx2, align 4 %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - flow [<] splitable! -; CHECK: da analyze - split level = 1, iteration = 11! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 13 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 13 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i < 12; i++) -;; A[3*i - 18][22 - i] = ... -;; ... = A[i][i] +;; for (long int i = 0; i < 12; i++) { +;; A[3*i - 18][22 - i] = i; +;; *B++ = A[i][i]; define void @couple13([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -434,27 +519,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx2, align 4 %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 12 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 12 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } - -;; for (long int i = 0; i < 100; i++) -;; A[3*i - 18][18 - i][i] = ... -;; ... = A[i][i][i] +;; for (long int i = 0; i < 100; i++) { +;; A[3*i - 18][18 - i][i] = i; +;; *B++ = A[i][i][i]; define void @couple14([100 x [100 x i32]]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [=|<] splitable! +; CHECK: da analyze - split level = 1, iteration = 9! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -465,28 +556,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx3, align 4 %arrayidx6 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %i.02, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx6, align 4 -; CHECK: da analyze - flow [=|<] splitable! -; CHECK: da analyze - split level = 1, iteration = 9! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 100 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long int i = 0; i < 100; i++) -;; A[3*i - 18][22 - i][i] = ... -;; ... = A[i][i][i] +;; for (long int i = 0; i < 100; i++) { +;; A[3*i - 18][22 - i][i] = i; +;; *B++ = A[i][i][i]; define void @couple15([100 x [100 x i32]]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -497,12 +593,11 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx3, align 4 %arrayidx6 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %i.02, i64 %i.02, i64 %i.02 %0 = load i32* %arrayidx6, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add nsw i64 %i.02, 1 - %cmp = icmp slt i64 %inc, 100 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void diff --git a/test/Analysis/DependenceAnalysis/ExactRDIV.ll b/test/Analysis/DependenceAnalysis/ExactRDIV.ll index aa5d254a0ce2..81f55161c0df 100644 --- a/test/Analysis/DependenceAnalysis/ExactRDIV.ll +++ b/test/Analysis/DependenceAnalysis/ExactRDIV.ll @@ -6,15 +6,22 @@ target triple = "x86_64-apple-macosx10.6.0" ;; for (long int i = 0; i < 10; i++) -;; A[4*i + 10] = ... +;; A[4*i + 10] = i; ;; for (long int j = 0; j < 10; j++) -;; ... = A[2*j + 1]; +;; *B++ = A[2*j + 1]; define void @rdiv0(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.03 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %conv = trunc i64 %i.03 to i32 %mul = shl nsw i64 %i.03, 2 @@ -22,22 +29,24 @@ for.body: ; preds = %for.body, %entry %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc, 10 - br i1 %cmp, label %for.body, label %for.body4 + %exitcond5 = icmp ne i64 %inc, 10 + br i1 %exitcond5, label %for.body, label %for.body4.preheader + +for.body4.preheader: ; preds = %for.body + br label %for.body4 -for.body4: ; preds = %for.body4, %for.body - %j.02 = phi i64 [ %inc9, %for.body4 ], [ 0, %for.body ] - %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.02 = phi i64 [ %inc9, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %mul5 = shl nsw i64 %j.02, 1 %add64 = or i64 %mul5, 1 %arrayidx7 = getelementptr inbounds i32* %A, i64 %add64 %0 = load i32* %arrayidx7, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc9 = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc9, 10 - br i1 %cmp2, label %for.body4, label %for.end10 + %exitcond = icmp ne i64 %inc9, 10 + br i1 %exitcond, label %for.body4, label %for.end10 for.end10: ; preds = %for.body4 ret void @@ -45,15 +54,22 @@ for.end10: ; preds = %for.body4 ;; for (long int i = 0; i < 5; i++) -;; A[11*i - 45] = ... +;; A[11*i - 45] = i; ;; for (long int j = 0; j < 10; j++) -;; ... = A[j]; +;; *B++ = A[j]; define void @rdiv1(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.03 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, 11 @@ -61,20 +77,22 @@ for.body: ; preds = %for.body, %entry %arrayidx = getelementptr inbounds i32* %A, i64 %sub store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc, 5 - br i1 %cmp, label %for.body, label %for.body4 + %exitcond4 = icmp ne i64 %inc, 5 + br i1 %exitcond4, label %for.body, label %for.body4.preheader + +for.body4.preheader: ; preds = %for.body + br label %for.body4 -for.body4: ; preds = %for.body4, %for.body - %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body ] - %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %arrayidx5 = getelementptr inbounds i32* %A, i64 %j.02 %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc7 = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc7, 10 - br i1 %cmp2, label %for.body4, label %for.end8 + %exitcond = icmp ne i64 %inc7, 10 + br i1 %exitcond, label %for.body4, label %for.end8 for.end8: ; preds = %for.body4 ret void @@ -82,15 +100,22 @@ for.end8: ; preds = %for.body4 ;; for (long int i = 0; i <= 5; i++) -;; A[11*i - 45] = ... +;; A[11*i - 45] = i; ;; for (long int j = 0; j < 10; j++) -;; ... = A[j]; +;; *B++ = A[j]; define void @rdiv2(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.03 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, 11 @@ -98,20 +123,22 @@ for.body: ; preds = %for.body, %entry %arrayidx = getelementptr inbounds i32* %A, i64 %sub store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc, 6 - br i1 %cmp, label %for.body, label %for.body4 + %exitcond4 = icmp ne i64 %inc, 6 + br i1 %exitcond4, label %for.body, label %for.body4.preheader + +for.body4.preheader: ; preds = %for.body + br label %for.body4 -for.body4: ; preds = %for.body4, %for.body - %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body ] - %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %arrayidx5 = getelementptr inbounds i32* %A, i64 %j.02 %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc7 = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc7, 10 - br i1 %cmp2, label %for.body4, label %for.end8 + %exitcond = icmp ne i64 %inc7, 10 + br i1 %exitcond, label %for.body4, label %for.end8 for.end8: ; preds = %for.body4 ret void @@ -119,15 +146,22 @@ for.end8: ; preds = %for.body4 ;; for (long int i = 0; i < 5; i++) -;; A[11*i - 45] = ... +;; A[11*i - 45] = i; ;; for (long int j = 0; j <= 10; j++) -;; ... = A[j]; +;; *B++ = A[j]; define void @rdiv3(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.03 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, 11 @@ -135,20 +169,22 @@ for.body: ; preds = %for.body, %entry %arrayidx = getelementptr inbounds i32* %A, i64 %sub store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc, 5 - br i1 %cmp, label %for.body, label %for.body4 + %exitcond4 = icmp ne i64 %inc, 5 + br i1 %exitcond4, label %for.body, label %for.body4.preheader + +for.body4.preheader: ; preds = %for.body + br label %for.body4 -for.body4: ; preds = %for.body4, %for.body - %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body ] - %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %arrayidx5 = getelementptr inbounds i32* %A, i64 %j.02 %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc7 = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc7, 11 - br i1 %cmp2, label %for.body4, label %for.end8 + %exitcond = icmp ne i64 %inc7, 11 + br i1 %exitcond, label %for.body4, label %for.end8 for.end8: ; preds = %for.body4 ret void @@ -156,15 +192,22 @@ for.end8: ; preds = %for.body4 ;; for (long int i = 0; i <= 5; i++) -;; A[11*i - 45] = ... +;; A[11*i - 45] = i; ;; for (long int j = 0; j <= 10; j++) -;; ... = A[j]; +;; *B++ = A[j]; define void @rdiv4(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.03 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, 11 @@ -172,20 +215,22 @@ for.body: ; preds = %for.body, %entry %arrayidx = getelementptr inbounds i32* %A, i64 %sub store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc, 6 - br i1 %cmp, label %for.body, label %for.body4 + %exitcond4 = icmp ne i64 %inc, 6 + br i1 %exitcond4, label %for.body, label %for.body4.preheader + +for.body4.preheader: ; preds = %for.body + br label %for.body4 -for.body4: ; preds = %for.body4, %for.body - %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body ] - %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %arrayidx5 = getelementptr inbounds i32* %A, i64 %j.02 %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - flow! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc7 = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc7, 11 - br i1 %cmp2, label %for.body4, label %for.end8 + %exitcond = icmp ne i64 %inc7, 11 + br i1 %exitcond, label %for.body4, label %for.end8 for.end8: ; preds = %for.body4 ret void @@ -193,15 +238,22 @@ for.end8: ; preds = %for.body4 ;; for (long int i = 0; i < 5; i++) -;; A[-11*i + 45] = ... +;; A[-11*i + 45] = i; ;; for (long int j = 0; j < 10; j++) -;; ... = A[-j]; +;; *B++ = A[-j]; define void @rdiv5(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.03 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, -11 @@ -209,21 +261,23 @@ for.body: ; preds = %for.body, %entry %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc, 5 - br i1 %cmp, label %for.body, label %for.body4 + %exitcond4 = icmp ne i64 %inc, 5 + br i1 %exitcond4, label %for.body, label %for.body4.preheader -for.body4: ; preds = %for.body4, %for.body - %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body ] - %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body ] +for.body4.preheader: ; preds = %for.body + br label %for.body4 + +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %sub = sub nsw i64 0, %j.02 %arrayidx5 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc7 = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc7, 10 - br i1 %cmp2, label %for.body4, label %for.end8 + %exitcond = icmp ne i64 %inc7, 10 + br i1 %exitcond, label %for.body4, label %for.end8 for.end8: ; preds = %for.body4 ret void @@ -231,15 +285,22 @@ for.end8: ; preds = %for.body4 ;; for (long int i = 0; i <= 5; i++) -;; A[-11*i + 45] = ... +;; A[-11*i + 45] = i; ;; for (long int j = 0; j < 10; j++) -;; ... = A[-j]; +;; *B++ = A[-j]; define void @rdiv6(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.03 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, -11 @@ -247,21 +308,23 @@ for.body: ; preds = %for.body, %entry %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc, 6 - br i1 %cmp, label %for.body, label %for.body4 + %exitcond4 = icmp ne i64 %inc, 6 + br i1 %exitcond4, label %for.body, label %for.body4.preheader + +for.body4.preheader: ; preds = %for.body + br label %for.body4 -for.body4: ; preds = %for.body4, %for.body - %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body ] - %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %sub = sub nsw i64 0, %j.02 %arrayidx5 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc7 = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc7, 10 - br i1 %cmp2, label %for.body4, label %for.end8 + %exitcond = icmp ne i64 %inc7, 10 + br i1 %exitcond, label %for.body4, label %for.end8 for.end8: ; preds = %for.body4 ret void @@ -269,15 +332,22 @@ for.end8: ; preds = %for.body4 ;; for (long int i = 0; i < 5; i++) -;; A[-11*i + 45] = ... +;; A[-11*i + 45] = i; ;; for (long int j = 0; j <= 10; j++) -;; ... = A[-j]; +;; *B++ = A[-j]; define void @rdiv7(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.03 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, -11 @@ -285,21 +355,23 @@ for.body: ; preds = %for.body, %entry %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc, 5 - br i1 %cmp, label %for.body, label %for.body4 + %exitcond4 = icmp ne i64 %inc, 5 + br i1 %exitcond4, label %for.body, label %for.body4.preheader -for.body4: ; preds = %for.body4, %for.body - %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body ] - %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body ] +for.body4.preheader: ; preds = %for.body + br label %for.body4 + +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %sub = sub nsw i64 0, %j.02 %arrayidx5 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc7 = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc7, 11 - br i1 %cmp2, label %for.body4, label %for.end8 + %exitcond = icmp ne i64 %inc7, 11 + br i1 %exitcond, label %for.body4, label %for.end8 for.end8: ; preds = %for.body4 ret void @@ -307,15 +379,22 @@ for.end8: ; preds = %for.body4 ;; for (long int i = 0; i <= 5; i++) -;; A[-11*i + 45] = ... +;; A[-11*i + 45] = i; ;; for (long int j = 0; j <= 10; j++) -;; ... = A[-j]; +;; *B++ = A[-j]; define void @rdiv8(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.03 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, -11 @@ -323,21 +402,23 @@ for.body: ; preds = %for.body, %entry %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc, 6 - br i1 %cmp, label %for.body, label %for.body4 + %exitcond4 = icmp ne i64 %inc, 6 + br i1 %exitcond4, label %for.body, label %for.body4.preheader + +for.body4.preheader: ; preds = %for.body + br label %for.body4 -for.body4: ; preds = %for.body4, %for.body - %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body ] - %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %sub = sub nsw i64 0, %j.02 %arrayidx5 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - flow! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc7 = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc7, 11 - br i1 %cmp2, label %for.body4, label %for.end8 + %exitcond = icmp ne i64 %inc7, 11 + br i1 %exitcond, label %for.body4, label %for.end8 for.end8: ; preds = %for.body4 ret void @@ -345,20 +426,27 @@ for.end8: ; preds = %for.body4 ;; for (long int i = 0; i < 5; i++) -;; for (long int j = 0; j < 10; j++) -;; A[11*i - j] = ... -;; ... = A[45]; +;; for (long int j = 0; j < 10; j++) { +;; A[11*i - j] = i; +;; *B++ = A[45]; define void @rdiv9(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc5, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc5 ] +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc5 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc5 ] %i.03 = phi i64 [ 0, %entry ], [ %inc6, %for.inc5 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -368,38 +456,46 @@ for.body3: ; preds = %for.body3, %for.con store i32 %conv, i32* %arrayidx, align 4 %arrayidx4 = getelementptr inbounds i32* %A, i64 45 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 10 - br i1 %cmp2, label %for.body3, label %for.inc5 + %exitcond = icmp ne i64 %inc, 10 + br i1 %exitcond, label %for.body3, label %for.inc5 for.inc5: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 10 %inc6 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc6, 5 - br i1 %cmp, label %for.cond1.preheader, label %for.end7 + %exitcond5 = icmp ne i64 %inc6, 5 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end7 for.end7: ; preds = %for.inc5 ret void } -;; for (long int i = 0; i < 5; i++) -;; for (long int j = 0; j <= 10; j++) -;; A[11*i - j] = ... -;; ... = A[45]; + +;; for (long int i = 0; i <= 5; i++) +;; for (long int j = 0; j < 10; j++) { +;; A[11*i - j] = i; +;; *B++ = A[45]; define void @rdiv10(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc5, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc5 ] +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc5 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc5 ] %i.03 = phi i64 [ 0, %entry ], [ %inc6, %for.inc5 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -409,38 +505,45 @@ for.body3: ; preds = %for.body3, %for.con store i32 %conv, i32* %arrayidx, align 4 %arrayidx4 = getelementptr inbounds i32* %A, i64 45 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 10 - br i1 %cmp2, label %for.body3, label %for.inc5 + %exitcond = icmp ne i64 %inc, 10 + br i1 %exitcond, label %for.body3, label %for.inc5 for.inc5: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 10 %inc6 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc6, 6 - br i1 %cmp, label %for.cond1.preheader, label %for.end7 + %exitcond5 = icmp ne i64 %inc6, 6 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end7 for.end7: ; preds = %for.inc5 ret void } -;; for (long int i = 0; i <= 5; i++) -;; for (long int j = 0; j <= 10; j++) -;; A[11*i - j] = ... -;; ... = A[45]; +;; for (long int i = 0; i < 5; i++) +;; for (long int j = 0; j <= 10; j++) { +;; A[11*i - j] = i; +;; *B++ = A[45]; define void @rdiv11(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc5, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc5 ] +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc5 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc5 ] %i.03 = phi i64 [ 0, %entry ], [ %inc6, %for.inc5 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -450,38 +553,45 @@ for.body3: ; preds = %for.body3, %for.con store i32 %conv, i32* %arrayidx, align 4 %arrayidx4 = getelementptr inbounds i32* %A, i64 45 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 11 - br i1 %cmp2, label %for.body3, label %for.inc5 + %exitcond = icmp ne i64 %inc, 11 + br i1 %exitcond, label %for.body3, label %for.inc5 for.inc5: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 11 %inc6 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc6, 5 - br i1 %cmp, label %for.cond1.preheader, label %for.end7 + %exitcond5 = icmp ne i64 %inc6, 5 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end7 for.end7: ; preds = %for.inc5 ret void } -;; for (long int i = 0; i < 5; i++) -;; for (long int j = 0; j < 10; j++) -;; A[11*i - j] = ... -;; ... = A[45]; +;; for (long int i = 0; i <= 5; i++) +;; for (long int j = 0; j <= 10; j++) { +;; A[11*i - j] = i; +;; *B++ = A[45]; define void @rdiv12(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc5, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc5 ] +; CHECK: da analyze - none! +; CHECK: da analyze - flow [* *|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc5 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc5 ] %i.03 = phi i64 [ 0, %entry ], [ %inc6, %for.inc5 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -491,17 +601,17 @@ for.body3: ; preds = %for.body3, %for.con store i32 %conv, i32* %arrayidx, align 4 %arrayidx4 = getelementptr inbounds i32* %A, i64 45 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - flow [* *|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 11 - br i1 %cmp2, label %for.body3, label %for.inc5 + %exitcond = icmp ne i64 %inc, 11 + br i1 %exitcond, label %for.body3, label %for.inc5 for.inc5: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 11 %inc6 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc6, 6 - br i1 %cmp, label %for.cond1.preheader, label %for.end7 + %exitcond5 = icmp ne i64 %inc6, 6 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end7 for.end7: ; preds = %for.inc5 ret void diff --git a/test/Analysis/DependenceAnalysis/ExactSIV.ll b/test/Analysis/DependenceAnalysis/ExactSIV.ll index 71e050246291..586bbe5096d6 100644 --- a/test/Analysis/DependenceAnalysis/ExactSIV.ll +++ b/test/Analysis/DependenceAnalysis/ExactSIV.ll @@ -6,14 +6,21 @@ target triple = "x86_64-apple-macosx10.6.0" ;; for (long unsigned i = 0; i < 10; i++) { -;; A[i + 10] = ... -;; ... = A[2*i + 1]; +;; A[i + 10] = i; +;; *B++ = A[2*i + 1]; define void @exact0(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [<=|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -24,12 +31,11 @@ for.body: ; preds = %for.body, %entry %add13 = or i64 %mul, 1 %arrayidx2 = getelementptr inbounds i32* %A, i64 %add13 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - flow [<=|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 10 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 10 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -37,14 +43,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i < 10; i++) { -;; A[4*i + 10] = ... -;; ... = A[2*i + 1]; +;; A[4*i + 10] = i; +;; *B++ = A[2*i + 1]; define void @exact1(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -56,12 +69,11 @@ for.body: ; preds = %for.body, %entry %add23 = or i64 %mul1, 1 %arrayidx3 = getelementptr inbounds i32* %A, i64 %add23 %0 = load i32* %arrayidx3, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 10 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 10 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -69,14 +81,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i < 10; i++) { -;; A[6*i] = ... -;; ... = A[i + 60]; +;; A[6*i] = i; +;; *B++ = A[i + 60]; define void @exact2(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -86,12 +105,11 @@ for.body: ; preds = %for.body, %entry %add = add i64 %i.02, 60 %arrayidx1 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 10 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 10 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -99,14 +117,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i <= 10; i++) { -;; A[6*i] = ... -;; ... = A[i + 60]; +;; A[6*i] = i; +;; *B++ = A[i + 60]; define void @exact3(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -116,12 +141,11 @@ for.body: ; preds = %for.body, %entry %add = add i64 %i.02, 60 %arrayidx1 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [>]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 11 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 11 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -129,14 +153,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i < 12; i++) { -;; A[6*i] = ... -;; ... = A[i + 60]; +;; A[6*i] = i; +;; *B++ = A[i + 60]; define void @exact4(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -146,12 +177,11 @@ for.body: ; preds = %for.body, %entry %add = add i64 %i.02, 60 %arrayidx1 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [>]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 12 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 12 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -159,14 +189,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i <= 12; i++) { -;; A[6*i] = ... -;; ... = A[i + 60]; +;; A[6*i] = i; +;; *B++ = A[i + 60]; define void @exact5(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [=>|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -176,12 +213,11 @@ for.body: ; preds = %for.body, %entry %add = add i64 %i.02, 60 %arrayidx1 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [=>|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 13 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 13 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -189,14 +225,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i < 18; i++) { -;; A[6*i] = ... -;; ... = A[i + 60]; +;; A[6*i] = i; +;; *B++ = A[i + 60]; define void @exact6(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [=>|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -206,12 +249,11 @@ for.body: ; preds = %for.body, %entry %add = add i64 %i.02, 60 %arrayidx1 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [=>|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 18 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 18 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -219,14 +261,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i <= 18; i++) { -;; A[6*i] = ... -;; ... = A[i + 60]; +;; A[6*i] = i; +;; *B++ = A[i + 60]; define void @exact7(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [*|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -236,12 +285,11 @@ for.body: ; preds = %for.body, %entry %add = add i64 %i.02, 60 %arrayidx1 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [*|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 19 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 19 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -249,14 +297,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i < 10; i++) { -;; A[-6*i] = ... -;; ... = A[-i - 60]; +;; A[-6*i] = i; +;; *B++ = A[-i - 60]; define void @exact8(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -266,12 +321,11 @@ for.body: ; preds = %for.body, %entry %sub1 = sub i64 -60, %i.02 %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 10 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 10 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -279,14 +333,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i <= 10; i++) { -;; A[-6*i] = ... -;; ... = A[-i - 60]; +;; A[-6*i] = i; +;; *B++ = A[-i - 60]; define void @exact9(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -296,12 +357,11 @@ for.body: ; preds = %for.body, %entry %sub1 = sub i64 -60, %i.02 %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - flow [>]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 11 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 11 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -309,14 +369,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i < 12; i++) { -;; A[-6*i] = ... -;; ... = A[-i - 60]; +;; A[-6*i] = i; +;; *B++ = A[-i - 60]; define void @exact10(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -326,12 +393,11 @@ for.body: ; preds = %for.body, %entry %sub1 = sub i64 -60, %i.02 %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - flow [>]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 12 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 12 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -339,14 +405,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i <= 12; i++) { -;; A[-6*i] = ... -;; ... = A[-i - 60]; +;; A[-6*i] = i; +;; *B++ = A[-i - 60]; define void @exact11(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [=>|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -356,12 +429,11 @@ for.body: ; preds = %for.body, %entry %sub1 = sub i64 -60, %i.02 %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - flow [=>|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 13 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 13 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -369,14 +441,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i < 18; i++) { -;; A[-6*i] = ... -;; ... = A[-i - 60]; +;; A[-6*i] = i; +;; *B++ = A[-i - 60]; define void @exact12(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [=>|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -386,12 +465,11 @@ for.body: ; preds = %for.body, %entry %sub1 = sub i64 -60, %i.02 %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - flow [=>|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 18 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 18 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void @@ -399,14 +477,21 @@ for.end: ; preds = %for.body ;; for (long unsigned i = 0; i <= 18; i++) { -;; A[-6*i] = ... -;; ... = A[-i - 60]; +;; A[-6*i] = i; +;; *B++ = A[-i - 60]; define void @exact13(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [*|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -416,12 +501,11 @@ for.body: ; preds = %for.body, %entry %sub1 = sub i64 -60, %i.02 %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - flow [*|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 19 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 19 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void diff --git a/test/Analysis/DependenceAnalysis/GCD.ll b/test/Analysis/DependenceAnalysis/GCD.ll index 94c93a8a0dd4..a42212464f86 100644 --- a/test/Analysis/DependenceAnalysis/GCD.ll +++ b/test/Analysis/DependenceAnalysis/GCD.ll @@ -6,14 +6,21 @@ target triple = "x86_64-apple-macosx10.6.0" ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[2*i - 4*j] = ... -;; ... = A[6*i + 8*j]; +;; for (long int j = 0; j < 100; j++) { +;; A[2*i - 4*j] = i; +;; *B++ = A[6*i + 8*j]; define void @gcd0(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - flow [=> *|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc8 %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc8 ] %i.03 = phi i64 [ 0, %entry ], [ %inc9, %for.inc8 ] @@ -33,7 +40,6 @@ for.body3: ; preds = %for.cond1.preheader %add = add nsw i64 %mul5, %mul6 %arrayidx7 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx7, align 4 -; CHECK: da analyze - flow [=> *|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 @@ -52,14 +58,21 @@ for.end10: ; preds = %for.inc8 ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[2*i - 4*j] = ... -;; ... = A[6*i + 8*j + 1]; +;; for (long int j = 0; j < 100; j++) { +;; A[2*i - 4*j] = i; +;; *B++ = A[6*i + 8*j + 1]; define void @gcd1(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc9 %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc9 ] %i.03 = phi i64 [ 0, %entry ], [ %inc10, %for.inc9 ] @@ -80,7 +93,6 @@ for.body3: ; preds = %for.cond1.preheader %add7 = or i64 %add, 1 %arrayidx8 = getelementptr inbounds i32* %A, i64 %add7 %0 = load i32* %arrayidx8, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 @@ -99,14 +111,21 @@ for.end11: ; preds = %for.inc9 ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[2*i - 4*j + 1] = ... -;; ... = A[6*i + 8*j]; +;; for (long int j = 0; j < 100; j++) { +;; A[2*i - 4*j + 1] = i; +;; *B++ = A[6*i + 8*j]; define void @gcd2(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc9 %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc9 ] %i.03 = phi i64 [ 0, %entry ], [ %inc10, %for.inc9 ] @@ -127,7 +146,6 @@ for.body3: ; preds = %for.cond1.preheader %add7 = add nsw i64 %mul5, %mul6 %arrayidx8 = getelementptr inbounds i32* %A, i64 %add7 %0 = load i32* %arrayidx8, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 @@ -146,14 +164,21 @@ for.end11: ; preds = %for.inc9 ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[i + 2*j] = ... -;; ... = A[i + 2*j - 1]; +;; for (long int j = 0; j < 100; j++) { +;; A[i + 2*j] = i; +;; *B++ = A[i + 2*j - 1]; define void @gcd3(i32* %A, i32* %B) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - flow [<> *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc7 %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc7 ] %i.03 = phi i64 [ 0, %entry ], [ %inc8, %for.inc7 ] @@ -172,7 +197,6 @@ for.body3: ; preds = %for.cond1.preheader %sub = add nsw i64 %add5, -1 %arrayidx6 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx6, align 4 -; CHECK: da analyze - flow [<> *]! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 @@ -190,16 +214,22 @@ for.end9: ; preds = %for.inc7 } -;; void gcd4(int *A, int *B, long int M, long int N) { -;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) { -;; A[5*i + 10*j*M + 9*M*N] = i; -;; *B++ = A[15*i + 20*j*M - 21*N*M + 4]; +;; for (long int i = 0; i < 100; i++) +;; for (long int j = 0; j < 100; j++) { +;; A[5*i + 10*j*M + 9*M*N] = i; +;; *B++ = A[15*i + 20*j*M - 21*N*M + 4]; define void @gcd4(i32* %A, i32* %B, i64 %M, i64 %N) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc17 %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc17 ] %i.03 = phi i64 [ 0, %entry ], [ %inc18, %for.inc17 ] @@ -228,7 +258,6 @@ for.body3: ; preds = %for.cond1.preheader %add15 = add nsw i64 %sub, 4 %arrayidx16 = getelementptr inbounds i32* %A, i64 %add15 %0 = load i32* %arrayidx16, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 @@ -246,16 +275,22 @@ for.end19: ; preds = %for.inc17 } -;; void gcd5(int *A, int *B, long int M, long int N) { -;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) { -;; A[5*i + 10*j*M + 9*M*N] = i; -;; *B++ = A[15*i + 20*j*M - 21*N*M + 5]; +;; for (long int i = 0; i < 100; i++) +;; for (long int j = 0; j < 100; j++) { +;; A[5*i + 10*j*M + 9*M*N] = i; +;; *B++ = A[15*i + 20*j*M - 21*N*M + 5]; define void @gcd5(i32* %A, i32* %B, i64 %M, i64 %N) nounwind uwtable ssp { entry: br label %for.cond1.preheader +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - flow [<> *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.cond1.preheader: ; preds = %entry, %for.inc17 %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc17 ] %i.03 = phi i64 [ 0, %entry ], [ %inc18, %for.inc17 ] @@ -284,7 +319,6 @@ for.body3: ; preds = %for.cond1.preheader %add15 = add nsw i64 %sub, 5 %arrayidx16 = getelementptr inbounds i32* %A, i64 %add15 %0 = load i32* %arrayidx16, align 4 -; CHECK: da analyze - flow [<> *]! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 @@ -302,17 +336,23 @@ for.end19: ; preds = %for.inc17 } -;; void gcd6(long int n, int A[][n], int *B) { -;; for (long int i = 0; i < n; i++) -;; for (long int j = 0; j < n; j++) { -;; A[2*i][4*j] = i; -;; *B++ = A[8*i][6*j + 1]; +;; for (long int i = 0; i < n; i++) +;; for (long int j = 0; j < n; j++) { +;; A[2*i][4*j] = i; +;; *B++ = A[8*i][6*j + 1]; define void @gcd6(i64 %n, i32* %A, i32* %B) nounwind uwtable ssp { entry: %cmp4 = icmp sgt i64 %n, 0 br i1 %cmp4, label %for.cond1.preheader.preheader, label %for.end12 +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - output [* *]! + for.cond1.preheader.preheader: ; preds = %entry br label %for.cond1.preheader @@ -342,7 +382,6 @@ for.body3: ; preds = %for.body3.preheader %arrayidx8.sum = add i64 %1, %add7 %arrayidx9 = getelementptr inbounds i32* %A, i64 %arrayidx8.sum %2 = load i32* %arrayidx9, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.12, i64 1 store i32 %2, i32* %B.addr.12, align 4 %inc = add nsw i64 %j.03, 1 @@ -367,11 +406,10 @@ for.end12: ; preds = %for.end12.loopexit, } -;; void gcd7(int n, int A[][n], int *B) { -;; for (int i = 0; i < n; i++) -;; for (int j = 0; j < n; j++) { -;; A[2*i][4*j] = i; -;; *B++ = A[8*i][6*j + 1]; +;; for (int i = 0; i < n; i++) +;; for (int j = 0; j < n; j++) { +;; A[2*i][4*j] = i; +;; *B++ = A[8*i][6*j + 1]; define void @gcd7(i32 %n, i32* %A, i32* %B) nounwind uwtable ssp { entry: @@ -379,6 +417,13 @@ entry: %cmp4 = icmp sgt i32 %n, 0 br i1 %cmp4, label %for.cond1.preheader.preheader, label %for.end15 +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - flow [* *|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - output [* *]! + for.cond1.preheader.preheader: ; preds = %entry br label %for.cond1.preheader @@ -419,7 +464,6 @@ for.body3: ; preds = %for.body3.preheader %arrayidx11.sum = add i64 %10, %idxprom8 %arrayidx12 = getelementptr inbounds i32* %A, i64 %arrayidx11.sum %11 = load i32* %arrayidx12, align 4 -; CHECK: da analyze - flow [* *|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.12, i64 1 store i32 %11, i32* %B.addr.12, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 @@ -446,17 +490,23 @@ for.end15: ; preds = %for.end15.loopexit, } -;; void gcd8(int n, int *A, int *B) { -;; for (int i = 0; i < n; i++) -;; for (int j = 0; j < n; j++) { -;; A[n*2*i + 4*j] = i; -;; *B++ = A[n*8*i + 6*j + 1]; +;; for (int i = 0; i < n; i++) +;; for (int j = 0; j < n; j++) { +;; A[n*2*i + 4*j] = i; +;; *B++ = A[n*8*i + 6*j + 1]; define void @gcd8(i32 %n, i32* %A, i32* %B) nounwind uwtable ssp { entry: %cmp4 = icmp sgt i32 %n, 0 br i1 %cmp4, label %for.cond1.preheader.preheader, label %for.end15 +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - output [* *]! + for.cond1.preheader.preheader: ; preds = %entry br label %for.cond1.preheader @@ -492,7 +542,6 @@ for.body3: ; preds = %for.body3.preheader %idxprom11 = sext i32 %add10 to i64 %arrayidx12 = getelementptr inbounds i32* %A, i64 %idxprom11 %5 = load i32* %arrayidx12, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.12, i64 1 store i32 %5, i32* %B.addr.12, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 @@ -518,11 +567,10 @@ for.end15: ; preds = %for.end15.loopexit, } -;; void gcd9(unsigned n, int A[][n], int *B) { -;; for (unsigned i = 0; i < n; i++) -;; for (unsigned j = 0; j < n; j++) { -;; A[2*i][4*j] = i; -;; *B++ = A[8*i][6*j + 1]; +;; for (unsigned i = 0; i < n; i++) +;; for (unsigned j = 0; j < n; j++) { +;; A[2*i][4*j] = i; +;; *B++ = A[8*i][6*j + 1]; define void @gcd9(i32 %n, i32* %A, i32* %B) nounwind uwtable ssp { entry: @@ -530,6 +578,13 @@ entry: %cmp4 = icmp eq i32 %n, 0 br i1 %cmp4, label %for.end15, label %for.cond1.preheader.preheader +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - flow [* *|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [* *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - output [* *]! + for.cond1.preheader.preheader: ; preds = %entry br label %for.cond1.preheader @@ -570,7 +625,6 @@ for.body3: ; preds = %for.body3.preheader %arrayidx11.sum = add i64 %10, %idxprom8 %arrayidx12 = getelementptr inbounds i32* %A, i64 %arrayidx11.sum %11 = load i32* %arrayidx12, align 4 -; CHECK: da analyze - flow [* *|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.12, i64 1 store i32 %11, i32* %B.addr.12, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 diff --git a/test/Analysis/DependenceAnalysis/Preliminary.ll b/test/Analysis/DependenceAnalysis/Preliminary.ll index 3ef63fd5592f..f36b85a5951e 100644 --- a/test/Analysis/DependenceAnalysis/Preliminary.ll +++ b/test/Analysis/DependenceAnalysis/Preliminary.ll @@ -1,111 +1,147 @@ -; RUN: opt < %s -analyze -basicaa -indvars -da | FileCheck %s - -; This series of tests is more interesting when debugging is enabled. +; RUN: opt < %s -analyze -basicaa -da | FileCheck %s ; ModuleID = 'Preliminary.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.6.0" -;; may alias -;; int p0(int n, int *A, int *B) { +;;int p0(int n, int *A, int *B) { ;; A[0] = n; ;; return B[1]; define i32 @p0(i32 %n, i32* %A, i32* %B) nounwind uwtable ssp { entry: store i32 %n, i32* %A, align 4 + +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + %arrayidx1 = getelementptr inbounds i32* %B, i64 1 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - confused! ret i32 %0 } -;; no alias -;; int p1(int n, int *restrict A, int *restrict B) { +;;int p1(int n, int *restrict A, int *restrict B) { ;; A[0] = n; ;; return B[1]; define i32 @p1(i32 %n, i32* noalias %A, i32* noalias %B) nounwind uwtable ssp { entry: store i32 %n, i32* %A, align 4 + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - none! + %arrayidx1 = getelementptr inbounds i32* %B, i64 1 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! ret i32 %0 } -;; check loop nesting levels -;; for (long int i = 0; i < n; i++) -;; for (long int j = 0; j < n; j++) -;; for (long int k = 0; k < n; k++) -;; A[i][j][k] = ... -;; for (long int k = 0; k < n; k++) -;; ... = A[i + 3][j + 2][k + 1]; + +;; for (long int i = 0; i < n; i++) { +;; for (long int j = 0; j < n; j++) { +;; for (long int k = 0; k < n; k++) { +;; A[i][j][k] = i; +;; } +;; for (long int k = 0; k < n; k++) { +;; *B++ = A[i + 3][j + 2][k + 1]; define void @p2(i64 %n, [100 x [100 x i64]]* %A, i64* %B) nounwind uwtable ssp { entry: %cmp10 = icmp sgt i64 %n, 0 - br i1 %cmp10, label %for.cond1.preheader, label %for.end26 + br i1 %cmp10, label %for.cond1.preheader.preheader, label %for.end26 + +; CHECK: da analyze - none! +; CHECK: da analyze - flow [-3 -2]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - output [* * *]! -for.cond1.preheader: ; preds = %for.inc24, %entry - %B.addr.012 = phi i64* [ %B.addr.1.lcssa, %for.inc24 ], [ %B, %entry ] - %i.011 = phi i64 [ %inc25, %for.inc24 ], [ 0, %entry ] +for.cond1.preheader.preheader: ; preds = %entry + br label %for.cond1.preheader + +for.cond1.preheader: ; preds = %for.cond1.preheader.preheader, %for.inc24 + %B.addr.012 = phi i64* [ %B.addr.1.lcssa, %for.inc24 ], [ %B, %for.cond1.preheader.preheader ] + %i.011 = phi i64 [ %inc25, %for.inc24 ], [ 0, %for.cond1.preheader.preheader ] %cmp26 = icmp sgt i64 %n, 0 - br i1 %cmp26, label %for.cond4.preheader, label %for.inc24 + br i1 %cmp26, label %for.cond4.preheader.preheader, label %for.inc24 + +for.cond4.preheader.preheader: ; preds = %for.cond1.preheader + br label %for.cond4.preheader -for.cond4.preheader: ; preds = %for.inc21, %for.cond1.preheader - %B.addr.18 = phi i64* [ %B.addr.2.lcssa, %for.inc21 ], [ %B.addr.012, %for.cond1.preheader ] - %j.07 = phi i64 [ %inc22, %for.inc21 ], [ 0, %for.cond1.preheader ] +for.cond4.preheader: ; preds = %for.cond4.preheader.preheader, %for.inc21 + %B.addr.18 = phi i64* [ %B.addr.2.lcssa, %for.inc21 ], [ %B.addr.012, %for.cond4.preheader.preheader ] + %j.07 = phi i64 [ %inc22, %for.inc21 ], [ 0, %for.cond4.preheader.preheader ] %cmp51 = icmp sgt i64 %n, 0 - br i1 %cmp51, label %for.body6, label %for.cond10.loopexit + br i1 %cmp51, label %for.body6.preheader, label %for.cond10.loopexit -for.body6: ; preds = %for.body6, %for.cond4.preheader - %k.02 = phi i64 [ %inc, %for.body6 ], [ 0, %for.cond4.preheader ] +for.body6.preheader: ; preds = %for.cond4.preheader + br label %for.body6 + +for.body6: ; preds = %for.body6.preheader, %for.body6 + %k.02 = phi i64 [ %inc, %for.body6 ], [ 0, %for.body6.preheader ] %arrayidx8 = getelementptr inbounds [100 x [100 x i64]]* %A, i64 %i.011, i64 %j.07, i64 %k.02 store i64 %i.011, i64* %arrayidx8, align 8 %inc = add nsw i64 %k.02, 1 - %cmp5 = icmp slt i64 %inc, %n - br i1 %cmp5, label %for.body6, label %for.cond10.loopexit + %exitcond13 = icmp ne i64 %inc, %n + br i1 %exitcond13, label %for.body6, label %for.cond10.loopexit.loopexit + +for.cond10.loopexit.loopexit: ; preds = %for.body6 + br label %for.cond10.loopexit -for.cond10.loopexit: ; preds = %for.body6, %for.cond4.preheader +for.cond10.loopexit: ; preds = %for.cond10.loopexit.loopexit, %for.cond4.preheader %cmp113 = icmp sgt i64 %n, 0 - br i1 %cmp113, label %for.body12, label %for.inc21 + br i1 %cmp113, label %for.body12.preheader, label %for.inc21 -for.body12: ; preds = %for.body12, %for.cond10.loopexit - %k9.05 = phi i64 [ %inc19, %for.body12 ], [ 0, %for.cond10.loopexit ] - %B.addr.24 = phi i64* [ %incdec.ptr, %for.body12 ], [ %B.addr.18, %for.cond10.loopexit ] +for.body12.preheader: ; preds = %for.cond10.loopexit + br label %for.body12 + +for.body12: ; preds = %for.body12.preheader, %for.body12 + %k9.05 = phi i64 [ %inc19, %for.body12 ], [ 0, %for.body12.preheader ] + %B.addr.24 = phi i64* [ %incdec.ptr, %for.body12 ], [ %B.addr.18, %for.body12.preheader ] %add = add nsw i64 %k9.05, 1 %add13 = add nsw i64 %j.07, 2 %add14 = add nsw i64 %i.011, 3 %arrayidx17 = getelementptr inbounds [100 x [100 x i64]]* %A, i64 %add14, i64 %add13, i64 %add %0 = load i64* %arrayidx17, align 8 -; CHECK: da analyze - flow [-3 -2]! %incdec.ptr = getelementptr inbounds i64* %B.addr.24, i64 1 store i64 %0, i64* %B.addr.24, align 8 %inc19 = add nsw i64 %k9.05, 1 - %cmp11 = icmp slt i64 %inc19, %n - br i1 %cmp11, label %for.body12, label %for.inc21 + %exitcond = icmp ne i64 %inc19, %n + br i1 %exitcond, label %for.body12, label %for.inc21.loopexit -for.inc21: ; preds = %for.body12, %for.cond10.loopexit - %B.addr.2.lcssa = phi i64* [ %B.addr.18, %for.cond10.loopexit ], [ %incdec.ptr, %for.body12 ] +for.inc21.loopexit: ; preds = %for.body12 + %scevgep = getelementptr i64* %B.addr.18, i64 %n + br label %for.inc21 + +for.inc21: ; preds = %for.inc21.loopexit, %for.cond10.loopexit + %B.addr.2.lcssa = phi i64* [ %B.addr.18, %for.cond10.loopexit ], [ %scevgep, %for.inc21.loopexit ] %inc22 = add nsw i64 %j.07, 1 - %cmp2 = icmp slt i64 %inc22, %n - br i1 %cmp2, label %for.cond4.preheader, label %for.inc24 + %exitcond14 = icmp ne i64 %inc22, %n + br i1 %exitcond14, label %for.cond4.preheader, label %for.inc24.loopexit + +for.inc24.loopexit: ; preds = %for.inc21 + %B.addr.2.lcssa.lcssa = phi i64* [ %B.addr.2.lcssa, %for.inc21 ] + br label %for.inc24 -for.inc24: ; preds = %for.inc21, %for.cond1.preheader - %B.addr.1.lcssa = phi i64* [ %B.addr.012, %for.cond1.preheader ], [ %B.addr.2.lcssa, %for.inc21 ] +for.inc24: ; preds = %for.inc24.loopexit, %for.cond1.preheader + %B.addr.1.lcssa = phi i64* [ %B.addr.012, %for.cond1.preheader ], [ %B.addr.2.lcssa.lcssa, %for.inc24.loopexit ] %inc25 = add nsw i64 %i.011, 1 - %cmp = icmp slt i64 %inc25, %n - br i1 %cmp, label %for.cond1.preheader, label %for.end26 + %exitcond15 = icmp ne i64 %inc25, %n + br i1 %exitcond15, label %for.cond1.preheader, label %for.end26.loopexit + +for.end26.loopexit: ; preds = %for.inc24 + br label %for.end26 -for.end26: ; preds = %for.inc24, %entry +for.end26: ; preds = %for.end26.loopexit, %entry ret void } -;; classify subscripts ;; for (long int i = 0; i < n; i++) ;; for (long int j = 0; j < n; j++) ;; for (long int k = 0; k < n; k++) @@ -118,83 +154,127 @@ for.end26: ; preds = %for.inc24, %entry ;; for (long int s = 0; s < n; s++) ;; for (long int u = 0; u < n; u++) ;; for (long int t = 0; t < n; t++) { -;; A[i - 3] [j] [2] [k-1] [2*l + 1] [m] [p + q] [r + s] = ... -;; ... = A[i + 3] [2] [u] [1-k] [3*l - 1] [o] [1 + n] [t + 2]; +;; A[i - 3] [j] [2] [k-1] [2*l + 1] [m] [p + q] [r + s] = i; +;; *B++ = A[i + 3] [2] [u] [1-k] [3*l - 1] [o] [1 + n] [t + 2]; define void @p3(i64 %n, [100 x [100 x [100 x [100 x [100 x [100 x [100 x i64]]]]]]]* %A, i64* %B) nounwind uwtable ssp { entry: %cmp44 = icmp sgt i64 %n, 0 - br i1 %cmp44, label %for.cond1.preheader, label %for.end90 + br i1 %cmp44, label %for.cond1.preheader.preheader, label %for.end90 + +; CHECK: da analyze - output [0 0 0 0 0 S * * * * S S]! +; CHECK: da analyze - flow [-6 * * => * * * * * * * *] splitable! +; CHECK: da analyze - split level = 3, iteration = 1! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [0 S 0 0 S 0 S S S S 0 0]! +; CHECK: da analyze - confused! +; CHECK: da analyze - output [* * * * * * * * * * * *]! + +for.cond1.preheader.preheader: ; preds = %entry + br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc88, %entry - %B.addr.046 = phi i64* [ %B.addr.1.lcssa, %for.inc88 ], [ %B, %entry ] - %i.045 = phi i64 [ %inc89, %for.inc88 ], [ 0, %entry ] +for.cond1.preheader: ; preds = %for.cond1.preheader.preheader, %for.inc88 + %B.addr.046 = phi i64* [ %B.addr.1.lcssa, %for.inc88 ], [ %B, %for.cond1.preheader.preheader ] + %i.045 = phi i64 [ %inc89, %for.inc88 ], [ 0, %for.cond1.preheader.preheader ] %cmp240 = icmp sgt i64 %n, 0 - br i1 %cmp240, label %for.cond4.preheader, label %for.inc88 + br i1 %cmp240, label %for.cond4.preheader.preheader, label %for.inc88 -for.cond4.preheader: ; preds = %for.inc85, %for.cond1.preheader - %B.addr.142 = phi i64* [ %B.addr.2.lcssa, %for.inc85 ], [ %B.addr.046, %for.cond1.preheader ] - %j.041 = phi i64 [ %inc86, %for.inc85 ], [ 0, %for.cond1.preheader ] +for.cond4.preheader.preheader: ; preds = %for.cond1.preheader + br label %for.cond4.preheader + +for.cond4.preheader: ; preds = %for.cond4.preheader.preheader, %for.inc85 + %B.addr.142 = phi i64* [ %B.addr.2.lcssa, %for.inc85 ], [ %B.addr.046, %for.cond4.preheader.preheader ] + %j.041 = phi i64 [ %inc86, %for.inc85 ], [ 0, %for.cond4.preheader.preheader ] %cmp536 = icmp sgt i64 %n, 0 - br i1 %cmp536, label %for.cond7.preheader, label %for.inc85 + br i1 %cmp536, label %for.cond7.preheader.preheader, label %for.inc85 + +for.cond7.preheader.preheader: ; preds = %for.cond4.preheader + br label %for.cond7.preheader -for.cond7.preheader: ; preds = %for.inc82, %for.cond4.preheader - %B.addr.238 = phi i64* [ %B.addr.3.lcssa, %for.inc82 ], [ %B.addr.142, %for.cond4.preheader ] - %k.037 = phi i64 [ %inc83, %for.inc82 ], [ 0, %for.cond4.preheader ] +for.cond7.preheader: ; preds = %for.cond7.preheader.preheader, %for.inc82 + %B.addr.238 = phi i64* [ %B.addr.3.lcssa, %for.inc82 ], [ %B.addr.142, %for.cond7.preheader.preheader ] + %k.037 = phi i64 [ %inc83, %for.inc82 ], [ 0, %for.cond7.preheader.preheader ] %cmp832 = icmp sgt i64 %n, 0 - br i1 %cmp832, label %for.cond10.preheader, label %for.inc82 + br i1 %cmp832, label %for.cond10.preheader.preheader, label %for.inc82 + +for.cond10.preheader.preheader: ; preds = %for.cond7.preheader + br label %for.cond10.preheader -for.cond10.preheader: ; preds = %for.inc79, %for.cond7.preheader - %B.addr.334 = phi i64* [ %B.addr.4.lcssa, %for.inc79 ], [ %B.addr.238, %for.cond7.preheader ] - %l.033 = phi i64 [ %inc80, %for.inc79 ], [ 0, %for.cond7.preheader ] +for.cond10.preheader: ; preds = %for.cond10.preheader.preheader, %for.inc79 + %B.addr.334 = phi i64* [ %B.addr.4.lcssa, %for.inc79 ], [ %B.addr.238, %for.cond10.preheader.preheader ] + %l.033 = phi i64 [ %inc80, %for.inc79 ], [ 0, %for.cond10.preheader.preheader ] %cmp1128 = icmp sgt i64 %n, 0 - br i1 %cmp1128, label %for.cond13.preheader, label %for.inc79 + br i1 %cmp1128, label %for.cond13.preheader.preheader, label %for.inc79 -for.cond13.preheader: ; preds = %for.inc76, %for.cond10.preheader - %B.addr.430 = phi i64* [ %B.addr.5.lcssa, %for.inc76 ], [ %B.addr.334, %for.cond10.preheader ] - %m.029 = phi i64 [ %inc77, %for.inc76 ], [ 0, %for.cond10.preheader ] +for.cond13.preheader.preheader: ; preds = %for.cond10.preheader + br label %for.cond13.preheader + +for.cond13.preheader: ; preds = %for.cond13.preheader.preheader, %for.inc76 + %B.addr.430 = phi i64* [ %B.addr.5.lcssa, %for.inc76 ], [ %B.addr.334, %for.cond13.preheader.preheader ] + %m.029 = phi i64 [ %inc77, %for.inc76 ], [ 0, %for.cond13.preheader.preheader ] %cmp1424 = icmp sgt i64 %n, 0 - br i1 %cmp1424, label %for.cond16.preheader, label %for.inc76 + br i1 %cmp1424, label %for.cond16.preheader.preheader, label %for.inc76 + +for.cond16.preheader.preheader: ; preds = %for.cond13.preheader + br label %for.cond16.preheader -for.cond16.preheader: ; preds = %for.inc73, %for.cond13.preheader - %B.addr.526 = phi i64* [ %B.addr.6.lcssa, %for.inc73 ], [ %B.addr.430, %for.cond13.preheader ] - %o.025 = phi i64 [ %inc74, %for.inc73 ], [ 0, %for.cond13.preheader ] +for.cond16.preheader: ; preds = %for.cond16.preheader.preheader, %for.inc73 + %B.addr.526 = phi i64* [ %B.addr.6.lcssa, %for.inc73 ], [ %B.addr.430, %for.cond16.preheader.preheader ] + %o.025 = phi i64 [ %inc74, %for.inc73 ], [ 0, %for.cond16.preheader.preheader ] %cmp1720 = icmp sgt i64 %n, 0 - br i1 %cmp1720, label %for.cond19.preheader, label %for.inc73 + br i1 %cmp1720, label %for.cond19.preheader.preheader, label %for.inc73 -for.cond19.preheader: ; preds = %for.inc70, %for.cond16.preheader - %B.addr.622 = phi i64* [ %B.addr.7.lcssa, %for.inc70 ], [ %B.addr.526, %for.cond16.preheader ] - %p.021 = phi i64 [ %inc71, %for.inc70 ], [ 0, %for.cond16.preheader ] +for.cond19.preheader.preheader: ; preds = %for.cond16.preheader + br label %for.cond19.preheader + +for.cond19.preheader: ; preds = %for.cond19.preheader.preheader, %for.inc70 + %B.addr.622 = phi i64* [ %B.addr.7.lcssa, %for.inc70 ], [ %B.addr.526, %for.cond19.preheader.preheader ] + %p.021 = phi i64 [ %inc71, %for.inc70 ], [ 0, %for.cond19.preheader.preheader ] %cmp2016 = icmp sgt i64 %n, 0 - br i1 %cmp2016, label %for.cond22.preheader, label %for.inc70 + br i1 %cmp2016, label %for.cond22.preheader.preheader, label %for.inc70 + +for.cond22.preheader.preheader: ; preds = %for.cond19.preheader + br label %for.cond22.preheader -for.cond22.preheader: ; preds = %for.inc67, %for.cond19.preheader - %B.addr.718 = phi i64* [ %B.addr.8.lcssa, %for.inc67 ], [ %B.addr.622, %for.cond19.preheader ] - %q.017 = phi i64 [ %inc68, %for.inc67 ], [ 0, %for.cond19.preheader ] +for.cond22.preheader: ; preds = %for.cond22.preheader.preheader, %for.inc67 + %B.addr.718 = phi i64* [ %B.addr.8.lcssa, %for.inc67 ], [ %B.addr.622, %for.cond22.preheader.preheader ] + %q.017 = phi i64 [ %inc68, %for.inc67 ], [ 0, %for.cond22.preheader.preheader ] %cmp2312 = icmp sgt i64 %n, 0 - br i1 %cmp2312, label %for.cond25.preheader, label %for.inc67 + br i1 %cmp2312, label %for.cond25.preheader.preheader, label %for.inc67 -for.cond25.preheader: ; preds = %for.inc64, %for.cond22.preheader - %B.addr.814 = phi i64* [ %B.addr.9.lcssa, %for.inc64 ], [ %B.addr.718, %for.cond22.preheader ] - %r.013 = phi i64 [ %inc65, %for.inc64 ], [ 0, %for.cond22.preheader ] +for.cond25.preheader.preheader: ; preds = %for.cond22.preheader + br label %for.cond25.preheader + +for.cond25.preheader: ; preds = %for.cond25.preheader.preheader, %for.inc64 + %B.addr.814 = phi i64* [ %B.addr.9.lcssa, %for.inc64 ], [ %B.addr.718, %for.cond25.preheader.preheader ] + %r.013 = phi i64 [ %inc65, %for.inc64 ], [ 0, %for.cond25.preheader.preheader ] %cmp268 = icmp sgt i64 %n, 0 - br i1 %cmp268, label %for.cond28.preheader, label %for.inc64 + br i1 %cmp268, label %for.cond28.preheader.preheader, label %for.inc64 + +for.cond28.preheader.preheader: ; preds = %for.cond25.preheader + br label %for.cond28.preheader -for.cond28.preheader: ; preds = %for.inc61, %for.cond25.preheader - %B.addr.910 = phi i64* [ %B.addr.10.lcssa, %for.inc61 ], [ %B.addr.814, %for.cond25.preheader ] - %s.09 = phi i64 [ %inc62, %for.inc61 ], [ 0, %for.cond25.preheader ] +for.cond28.preheader: ; preds = %for.cond28.preheader.preheader, %for.inc61 + %B.addr.910 = phi i64* [ %B.addr.10.lcssa, %for.inc61 ], [ %B.addr.814, %for.cond28.preheader.preheader ] + %s.09 = phi i64 [ %inc62, %for.inc61 ], [ 0, %for.cond28.preheader.preheader ] %cmp294 = icmp sgt i64 %n, 0 - br i1 %cmp294, label %for.cond31.preheader, label %for.inc61 + br i1 %cmp294, label %for.cond31.preheader.preheader, label %for.inc61 -for.cond31.preheader: ; preds = %for.inc58, %for.cond28.preheader - %u.06 = phi i64 [ %inc59, %for.inc58 ], [ 0, %for.cond28.preheader ] - %B.addr.105 = phi i64* [ %B.addr.11.lcssa, %for.inc58 ], [ %B.addr.910, %for.cond28.preheader ] +for.cond31.preheader.preheader: ; preds = %for.cond28.preheader + br label %for.cond31.preheader + +for.cond31.preheader: ; preds = %for.cond31.preheader.preheader, %for.inc58 + %u.06 = phi i64 [ %inc59, %for.inc58 ], [ 0, %for.cond31.preheader.preheader ] + %B.addr.105 = phi i64* [ %B.addr.11.lcssa, %for.inc58 ], [ %B.addr.910, %for.cond31.preheader.preheader ] %cmp321 = icmp sgt i64 %n, 0 - br i1 %cmp321, label %for.body33, label %for.inc58 + br i1 %cmp321, label %for.body33.preheader, label %for.inc58 + +for.body33.preheader: ; preds = %for.cond31.preheader + br label %for.body33 -for.body33: ; preds = %for.body33, %for.cond31.preheader - %t.03 = phi i64 [ %inc, %for.body33 ], [ 0, %for.cond31.preheader ] - %B.addr.112 = phi i64* [ %incdec.ptr, %for.body33 ], [ %B.addr.105, %for.cond31.preheader ] +for.body33: ; preds = %for.body33.preheader, %for.body33 + %t.03 = phi i64 [ %inc, %for.body33 ], [ 0, %for.body33.preheader ] + %B.addr.112 = phi i64* [ %incdec.ptr, %for.body33 ], [ %B.addr.105, %for.body33.preheader ] %add = add nsw i64 %r.013, %s.09 %add34 = add nsw i64 %p.021, %q.017 %mul = shl nsw i64 %l.033, 1 @@ -211,99 +291,153 @@ for.body33: ; preds = %for.body33, %for.co %add49 = add nsw i64 %i.045, 3 %arrayidx57 = getelementptr inbounds [100 x [100 x [100 x [100 x [100 x [100 x [100 x i64]]]]]]]* %A, i64 %add49, i64 2, i64 %u.06, i64 %sub48, i64 %sub47, i64 %o.025, i64 %add45, i64 %add44 %0 = load i64* %arrayidx57, align 8 -; CHECK: da analyze - flow [-6 * * => * * * * * * * *] splitable! -; CHECK: da analyze - split level = 3, iteration = 1! %incdec.ptr = getelementptr inbounds i64* %B.addr.112, i64 1 store i64 %0, i64* %B.addr.112, align 8 %inc = add nsw i64 %t.03, 1 - %cmp32 = icmp slt i64 %inc, %n - br i1 %cmp32, label %for.body33, label %for.inc58 + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body33, label %for.inc58.loopexit + +for.inc58.loopexit: ; preds = %for.body33 + %scevgep = getelementptr i64* %B.addr.105, i64 %n + br label %for.inc58 -for.inc58: ; preds = %for.body33, %for.cond31.preheader - %B.addr.11.lcssa = phi i64* [ %B.addr.105, %for.cond31.preheader ], [ %incdec.ptr, %for.body33 ] +for.inc58: ; preds = %for.inc58.loopexit, %for.cond31.preheader + %B.addr.11.lcssa = phi i64* [ %B.addr.105, %for.cond31.preheader ], [ %scevgep, %for.inc58.loopexit ] %inc59 = add nsw i64 %u.06, 1 - %cmp29 = icmp slt i64 %inc59, %n - br i1 %cmp29, label %for.cond31.preheader, label %for.inc61 + %exitcond48 = icmp ne i64 %inc59, %n + br i1 %exitcond48, label %for.cond31.preheader, label %for.inc61.loopexit -for.inc61: ; preds = %for.inc58, %for.cond28.preheader - %B.addr.10.lcssa = phi i64* [ %B.addr.910, %for.cond28.preheader ], [ %B.addr.11.lcssa, %for.inc58 ] +for.inc61.loopexit: ; preds = %for.inc58 + %B.addr.11.lcssa.lcssa = phi i64* [ %B.addr.11.lcssa, %for.inc58 ] + br label %for.inc61 + +for.inc61: ; preds = %for.inc61.loopexit, %for.cond28.preheader + %B.addr.10.lcssa = phi i64* [ %B.addr.910, %for.cond28.preheader ], [ %B.addr.11.lcssa.lcssa, %for.inc61.loopexit ] %inc62 = add nsw i64 %s.09, 1 - %cmp26 = icmp slt i64 %inc62, %n - br i1 %cmp26, label %for.cond28.preheader, label %for.inc64 + %exitcond49 = icmp ne i64 %inc62, %n + br i1 %exitcond49, label %for.cond28.preheader, label %for.inc64.loopexit + +for.inc64.loopexit: ; preds = %for.inc61 + %B.addr.10.lcssa.lcssa = phi i64* [ %B.addr.10.lcssa, %for.inc61 ] + br label %for.inc64 -for.inc64: ; preds = %for.inc61, %for.cond25.preheader - %B.addr.9.lcssa = phi i64* [ %B.addr.814, %for.cond25.preheader ], [ %B.addr.10.lcssa, %for.inc61 ] +for.inc64: ; preds = %for.inc64.loopexit, %for.cond25.preheader + %B.addr.9.lcssa = phi i64* [ %B.addr.814, %for.cond25.preheader ], [ %B.addr.10.lcssa.lcssa, %for.inc64.loopexit ] %inc65 = add nsw i64 %r.013, 1 - %cmp23 = icmp slt i64 %inc65, %n - br i1 %cmp23, label %for.cond25.preheader, label %for.inc67 + %exitcond50 = icmp ne i64 %inc65, %n + br i1 %exitcond50, label %for.cond25.preheader, label %for.inc67.loopexit -for.inc67: ; preds = %for.inc64, %for.cond22.preheader - %B.addr.8.lcssa = phi i64* [ %B.addr.718, %for.cond22.preheader ], [ %B.addr.9.lcssa, %for.inc64 ] +for.inc67.loopexit: ; preds = %for.inc64 + %B.addr.9.lcssa.lcssa = phi i64* [ %B.addr.9.lcssa, %for.inc64 ] + br label %for.inc67 + +for.inc67: ; preds = %for.inc67.loopexit, %for.cond22.preheader + %B.addr.8.lcssa = phi i64* [ %B.addr.718, %for.cond22.preheader ], [ %B.addr.9.lcssa.lcssa, %for.inc67.loopexit ] %inc68 = add nsw i64 %q.017, 1 - %cmp20 = icmp slt i64 %inc68, %n - br i1 %cmp20, label %for.cond22.preheader, label %for.inc70 + %exitcond51 = icmp ne i64 %inc68, %n + br i1 %exitcond51, label %for.cond22.preheader, label %for.inc70.loopexit + +for.inc70.loopexit: ; preds = %for.inc67 + %B.addr.8.lcssa.lcssa = phi i64* [ %B.addr.8.lcssa, %for.inc67 ] + br label %for.inc70 -for.inc70: ; preds = %for.inc67, %for.cond19.preheader - %B.addr.7.lcssa = phi i64* [ %B.addr.622, %for.cond19.preheader ], [ %B.addr.8.lcssa, %for.inc67 ] +for.inc70: ; preds = %for.inc70.loopexit, %for.cond19.preheader + %B.addr.7.lcssa = phi i64* [ %B.addr.622, %for.cond19.preheader ], [ %B.addr.8.lcssa.lcssa, %for.inc70.loopexit ] %inc71 = add nsw i64 %p.021, 1 - %cmp17 = icmp slt i64 %inc71, %n - br i1 %cmp17, label %for.cond19.preheader, label %for.inc73 + %exitcond52 = icmp ne i64 %inc71, %n + br i1 %exitcond52, label %for.cond19.preheader, label %for.inc73.loopexit -for.inc73: ; preds = %for.inc70, %for.cond16.preheader - %B.addr.6.lcssa = phi i64* [ %B.addr.526, %for.cond16.preheader ], [ %B.addr.7.lcssa, %for.inc70 ] +for.inc73.loopexit: ; preds = %for.inc70 + %B.addr.7.lcssa.lcssa = phi i64* [ %B.addr.7.lcssa, %for.inc70 ] + br label %for.inc73 + +for.inc73: ; preds = %for.inc73.loopexit, %for.cond16.preheader + %B.addr.6.lcssa = phi i64* [ %B.addr.526, %for.cond16.preheader ], [ %B.addr.7.lcssa.lcssa, %for.inc73.loopexit ] %inc74 = add nsw i64 %o.025, 1 - %cmp14 = icmp slt i64 %inc74, %n - br i1 %cmp14, label %for.cond16.preheader, label %for.inc76 + %exitcond53 = icmp ne i64 %inc74, %n + br i1 %exitcond53, label %for.cond16.preheader, label %for.inc76.loopexit + +for.inc76.loopexit: ; preds = %for.inc73 + %B.addr.6.lcssa.lcssa = phi i64* [ %B.addr.6.lcssa, %for.inc73 ] + br label %for.inc76 -for.inc76: ; preds = %for.inc73, %for.cond13.preheader - %B.addr.5.lcssa = phi i64* [ %B.addr.430, %for.cond13.preheader ], [ %B.addr.6.lcssa, %for.inc73 ] +for.inc76: ; preds = %for.inc76.loopexit, %for.cond13.preheader + %B.addr.5.lcssa = phi i64* [ %B.addr.430, %for.cond13.preheader ], [ %B.addr.6.lcssa.lcssa, %for.inc76.loopexit ] %inc77 = add nsw i64 %m.029, 1 - %cmp11 = icmp slt i64 %inc77, %n - br i1 %cmp11, label %for.cond13.preheader, label %for.inc79 + %exitcond54 = icmp ne i64 %inc77, %n + br i1 %exitcond54, label %for.cond13.preheader, label %for.inc79.loopexit + +for.inc79.loopexit: ; preds = %for.inc76 + %B.addr.5.lcssa.lcssa = phi i64* [ %B.addr.5.lcssa, %for.inc76 ] + br label %for.inc79 -for.inc79: ; preds = %for.inc76, %for.cond10.preheader - %B.addr.4.lcssa = phi i64* [ %B.addr.334, %for.cond10.preheader ], [ %B.addr.5.lcssa, %for.inc76 ] +for.inc79: ; preds = %for.inc79.loopexit, %for.cond10.preheader + %B.addr.4.lcssa = phi i64* [ %B.addr.334, %for.cond10.preheader ], [ %B.addr.5.lcssa.lcssa, %for.inc79.loopexit ] %inc80 = add nsw i64 %l.033, 1 - %cmp8 = icmp slt i64 %inc80, %n - br i1 %cmp8, label %for.cond10.preheader, label %for.inc82 + %exitcond55 = icmp ne i64 %inc80, %n + br i1 %exitcond55, label %for.cond10.preheader, label %for.inc82.loopexit -for.inc82: ; preds = %for.inc79, %for.cond7.preheader - %B.addr.3.lcssa = phi i64* [ %B.addr.238, %for.cond7.preheader ], [ %B.addr.4.lcssa, %for.inc79 ] +for.inc82.loopexit: ; preds = %for.inc79 + %B.addr.4.lcssa.lcssa = phi i64* [ %B.addr.4.lcssa, %for.inc79 ] + br label %for.inc82 + +for.inc82: ; preds = %for.inc82.loopexit, %for.cond7.preheader + %B.addr.3.lcssa = phi i64* [ %B.addr.238, %for.cond7.preheader ], [ %B.addr.4.lcssa.lcssa, %for.inc82.loopexit ] %inc83 = add nsw i64 %k.037, 1 - %cmp5 = icmp slt i64 %inc83, %n - br i1 %cmp5, label %for.cond7.preheader, label %for.inc85 + %exitcond56 = icmp ne i64 %inc83, %n + br i1 %exitcond56, label %for.cond7.preheader, label %for.inc85.loopexit + +for.inc85.loopexit: ; preds = %for.inc82 + %B.addr.3.lcssa.lcssa = phi i64* [ %B.addr.3.lcssa, %for.inc82 ] + br label %for.inc85 -for.inc85: ; preds = %for.inc82, %for.cond4.preheader - %B.addr.2.lcssa = phi i64* [ %B.addr.142, %for.cond4.preheader ], [ %B.addr.3.lcssa, %for.inc82 ] +for.inc85: ; preds = %for.inc85.loopexit, %for.cond4.preheader + %B.addr.2.lcssa = phi i64* [ %B.addr.142, %for.cond4.preheader ], [ %B.addr.3.lcssa.lcssa, %for.inc85.loopexit ] %inc86 = add nsw i64 %j.041, 1 - %cmp2 = icmp slt i64 %inc86, %n - br i1 %cmp2, label %for.cond4.preheader, label %for.inc88 + %exitcond57 = icmp ne i64 %inc86, %n + br i1 %exitcond57, label %for.cond4.preheader, label %for.inc88.loopexit -for.inc88: ; preds = %for.inc85, %for.cond1.preheader - %B.addr.1.lcssa = phi i64* [ %B.addr.046, %for.cond1.preheader ], [ %B.addr.2.lcssa, %for.inc85 ] +for.inc88.loopexit: ; preds = %for.inc85 + %B.addr.2.lcssa.lcssa = phi i64* [ %B.addr.2.lcssa, %for.inc85 ] + br label %for.inc88 + +for.inc88: ; preds = %for.inc88.loopexit, %for.cond1.preheader + %B.addr.1.lcssa = phi i64* [ %B.addr.046, %for.cond1.preheader ], [ %B.addr.2.lcssa.lcssa, %for.inc88.loopexit ] %inc89 = add nsw i64 %i.045, 1 - %cmp = icmp slt i64 %inc89, %n - br i1 %cmp, label %for.cond1.preheader, label %for.end90 + %exitcond58 = icmp ne i64 %inc89, %n + br i1 %exitcond58, label %for.cond1.preheader, label %for.end90.loopexit + +for.end90.loopexit: ; preds = %for.inc88 + br label %for.end90 -for.end90: ; preds = %for.inc88, %entry +for.end90: ; preds = %for.end90.loopexit, %entry ret void } -;; cleanup around chars, shorts, ints -;;void p4(int *A, int *B, long int n) -;; for (char i = 0; i < n; i++) -;; A[i + 2] = ... -;; ... = A[i]; +;;void p4(int *A, int *B, long int n) { +;; for (char i = 0; i < n; i++) { +;; A[i + 2] = i; +;; *B++ = A[i]; define void @p4(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp sgt i64 %n, 0 - br i1 %cmp1, label %for.body, label %for.end + br i1 %cmp1, label %for.body.preheader, label %for.end -for.body: ; preds = %for.body, %entry - %i.03 = phi i8 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +; CHECK: da analyze - output [*]! +; CHECK: da analyze - flow [*|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i8 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv2 = sext i8 %i.03 to i32 %conv3 = sext i8 %i.03 to i64 %add = add i64 %conv3, 2 @@ -312,32 +446,44 @@ for.body: ; preds = %for.body, %entry %idxprom4 = sext i8 %i.03 to i64 %arrayidx5 = getelementptr inbounds i32* %A, i64 %idxprom4 %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - flow [*|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i8 %i.03, 1 %conv = sext i8 %inc to i64 %cmp = icmp slt i64 %conv, %n - br i1 %cmp, label %for.body, label %for.end + br i1 %cmp, label %for.body, label %for.end.loopexit -for.end: ; preds = %for.body, %entry +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry ret void } -;;void p5(int *A, int *B, long int n) -;; for (short i = 0; i < n; i++) -;; A[i + 2] = ... -;; ... = A[i]; +;;void p5(int *A, int *B, long int n) { +;; for (short i = 0; i < n; i++) { +;; A[i + 2] = i; +;; *B++ = A[i]; define void @p5(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp sgt i64 %n, 0 - br i1 %cmp1, label %for.body, label %for.end + br i1 %cmp1, label %for.body.preheader, label %for.end -for.body: ; preds = %for.body, %entry - %i.03 = phi i16 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +; CHECK: da analyze - output [*]! +; CHECK: da analyze - flow [*|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i16 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv2 = sext i16 %i.03 to i32 %conv3 = sext i16 %i.03 to i64 %add = add i64 %conv3, 2 @@ -346,124 +492,208 @@ for.body: ; preds = %for.body, %entry %idxprom4 = sext i16 %i.03 to i64 %arrayidx5 = getelementptr inbounds i32* %A, i64 %idxprom4 %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - flow [*|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i16 %i.03, 1 %conv = sext i16 %inc to i64 %cmp = icmp slt i64 %conv, %n - br i1 %cmp, label %for.body, label %for.end + br i1 %cmp, label %for.body, label %for.end.loopexit -for.end: ; preds = %for.body, %entry +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry ret void } -;;void p6(int *A, int *B, long int n) -;; for (int i = 0; i < n; i++) -;; A[i + 2] = ... -;; ... = A[i]; +;;void p6(int *A, int *B, long int n) { +;; for (int i = 0; i < n; i++) { +;; A[i + 2] = i; +;; *B++ = A[i]; define void @p6(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp sgt i64 %n, 0 - br i1 %cmp1, label %for.body, label %for.end + br i1 %cmp1, label %for.body.preheader, label %for.end -for.body: ; preds = %for.body, %entry - %i.03 = phi i32 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] - %add = add nsw i32 %i.03, 2 - %idxprom = sext i32 %add to i64 - %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom - store i32 %i.03, i32* %arrayidx, align 4 - %idxprom2 = sext i32 %i.03 to i64 - %arrayidx3 = getelementptr inbounds i32* %A, i64 %idxprom2 - %0 = load i32* %arrayidx3, align 4 +; CHECK: da analyze - none! ; CHECK: da analyze - consistent flow [2]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] + %0 = add nsw i64 %indvars.iv, 2 + %arrayidx = getelementptr inbounds i32* %A, i64 %0 + %1 = trunc i64 %indvars.iv to i32 + store i32 %1, i32* %arrayidx, align 4 + %arrayidx3 = getelementptr inbounds i32* %A, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 - store i32 %0, i32* %B.addr.02, align 4 - %inc = add nsw i32 %i.03, 1 - %conv = sext i32 %inc to i64 - %cmp = icmp slt i64 %conv, %n - br i1 %cmp, label %for.body, label %for.end + store i32 %2, i32* %B.addr.02, align 4 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp ne i64 %indvars.iv.next, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } -;;void p7(unsigned *A, unsigned *B, char n) -;; A[n] = ... -;; ... = A[n + 1]; +;;void p7(unsigned *A, unsigned *B, char n) { +;; A[n] = 0; +;; *B = A[n + 1]; define void @p7(i32* %A, i32* %B, i8 signext %n) nounwind uwtable ssp { entry: %idxprom = sext i8 %n to i64 %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + store i32 0, i32* %arrayidx, align 4 %conv = sext i8 %n to i64 %add = add i64 %conv, 1 %arrayidx2 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - none! store i32 %0, i32* %B, align 4 ret void } - -;;void p8(unsigned *A, unsigned *B, short n) -;; A[n] = ... -;; ... = A[n + 1]; +;;void p8(unsigned *A, unsigned *B, short n) { +;; A[n] = 0; +;; *B = A[n + 1]; define void @p8(i32* %A, i32* %B, i16 signext %n) nounwind uwtable ssp { entry: %idxprom = sext i16 %n to i64 %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom store i32 0, i32* %arrayidx, align 4 + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + %conv = sext i16 %n to i64 %add = add i64 %conv, 1 %arrayidx2 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - none! store i32 %0, i32* %B, align 4 ret void } -;;void p9(unsigned *A, unsigned *B, int n) -;; A[n] = ... -;; ... = A[n + 1]; +;;void p9(unsigned *A, unsigned *B, int n) { +;; A[n] = 0; +;; *B = A[n + 1]; define void @p9(i32* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: %idxprom = sext i32 %n to i64 %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom store i32 0, i32* %arrayidx, align 4 + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + %add = add nsw i32 %n, 1 %idxprom1 = sext i32 %add to i64 %arrayidx2 = getelementptr inbounds i32* %A, i64 %idxprom1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - none! store i32 %0, i32* %B, align 4 ret void } -;;void p10(unsigned *A, unsigned *B, unsigned n) -;; A[n] = ... -;; ... = A[n + 1]; +;;void p10(unsigned *A, unsigned *B, unsigned n) { +;; A[n] = 0; +;; *B = A[n + 1]; define void @p10(i32* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: %idxprom = zext i32 %n to i64 %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom store i32 0, i32* %arrayidx, align 4 + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + %add = add i32 %n, 1 %idxprom1 = zext i32 %add to i64 %arrayidx2 = getelementptr inbounds i32* %A, i64 %idxprom1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - none! store i32 %0, i32* %B, align 4 ret void } + + +;;typedef struct { int v; } S; +;; +;;void f(S *s, unsigned size) { +;; S *i = s, *e = s + size - 1; +;; while (i != e) { +;; *i = *(i + 1); +;; ++i; + +%struct.S = type { i32 } + +define void @f(%struct.S* %s, i32 %size) nounwind uwtable ssp { +entry: + %idx.ext = zext i32 %size to i64 + %add.ptr.sum = add i64 %idx.ext, -1 + %add.ptr1 = getelementptr inbounds %struct.S* %s, i64 %add.ptr.sum + %cmp1 = icmp eq i64 %add.ptr.sum, 0 + br i1 %cmp1, label %while.end, label %while.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - consistent anti [1]! +; CHECK: da analyze - none! + +while.body.preheader: ; preds = %entry + br label %while.body + +while.body: ; preds = %while.body.preheader, %while.body + %i.02 = phi %struct.S* [ %incdec.ptr, %while.body ], [ %s, %while.body.preheader ] + %0 = getelementptr inbounds %struct.S* %i.02, i64 1, i32 0 + %1 = load i32* %0, align 4 + %2 = getelementptr inbounds %struct.S* %i.02, i64 0, i32 0 + store i32 %1, i32* %2, align 4 + %incdec.ptr = getelementptr inbounds %struct.S* %i.02, i64 1 + %cmp = icmp eq %struct.S* %incdec.ptr, %add.ptr1 + br i1 %cmp, label %while.end.loopexit, label %while.body + +while.end.loopexit: ; preds = %while.body + br label %while.end + +while.end: ; preds = %while.end.loopexit, %entry + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind diff --git a/test/Analysis/DependenceAnalysis/Propagating.ll b/test/Analysis/DependenceAnalysis/Propagating.ll index 076348c68dc8..f9034ede9d0b 100644 --- a/test/Analysis/DependenceAnalysis/Propagating.ll +++ b/test/Analysis/DependenceAnalysis/Propagating.ll @@ -6,7 +6,7 @@ target triple = "x86_64-apple-macosx10.6.0" ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) +;; for (long int j = 0; j < 100; j++) { ;; A[i + 1][i + j] = i; ;; *B++ = A[i][i + j]; @@ -14,12 +14,19 @@ define void @prop0([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc9, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc9 ] +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [1 -1]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc9 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc9 ] %i.03 = phi i64 [ 0, %entry ], [ %inc10, %for.inc9 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -30,17 +37,17 @@ for.body3: ; preds = %for.body3, %for.con %add6 = add nsw i64 %i.03, %j.02 %arrayidx8 = getelementptr inbounds [100 x i32]* %A, i64 %i.03, i64 %add6 %0 = load i32* %arrayidx8, align 4 -; CHECK: da analyze - consistent flow [1 -1]! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 100 - br i1 %cmp2, label %for.body3, label %for.inc9 + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body3, label %for.inc9 for.inc9: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 100 %inc10 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc10, 100 - br i1 %cmp, label %for.cond1.preheader, label %for.end11 + %exitcond5 = icmp ne i64 %inc10, 100 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end11 for.end11: ; preds = %for.inc9 ret void @@ -49,25 +56,32 @@ for.end11: ; preds = %for.inc9 ;; for (long int i = 0; i < 100; i++) ;; for (long int j = 0; j < 100; j++) -;; for (long int k = 0; k < 100; k++) -;; A[j - i][i + 1][j + k] = ... -;; ... = A[j - i][i][j + k]; +;; for (long int k = 0; k < 100; k++) { +;; A[j - i][i + 1][j + k] = i; +;; *B++ = A[j - i][i][j + k]; define void @prop1([100 x [100 x i32]]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc18, %entry - %B.addr.06 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc18 ] +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [1 1 -1]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc18 + %B.addr.06 = phi i32* [ %B, %entry ], [ %scevgep7, %for.inc18 ] %i.05 = phi i64 [ 0, %entry ], [ %inc19, %for.inc18 ] br label %for.cond4.preheader -for.cond4.preheader: ; preds = %for.inc15, %for.cond1.preheader - %B.addr.14 = phi i32* [ %B.addr.06, %for.cond1.preheader ], [ %incdec.ptr, %for.inc15 ] +for.cond4.preheader: ; preds = %for.cond1.preheader, %for.inc15 + %B.addr.14 = phi i32* [ %B.addr.06, %for.cond1.preheader ], [ %scevgep, %for.inc15 ] %j.03 = phi i64 [ 0, %for.cond1.preheader ], [ %inc16, %for.inc15 ] br label %for.body6 -for.body6: ; preds = %for.body6, %for.cond4.preheader +for.body6: ; preds = %for.cond4.preheader, %for.body6 %k.02 = phi i64 [ 0, %for.cond4.preheader ], [ %inc, %for.body6 ] %B.addr.21 = phi i32* [ %B.addr.14, %for.cond4.preheader ], [ %incdec.ptr, %for.body6 ] %conv = trunc i64 %i.05 to i32 @@ -80,22 +94,23 @@ for.body6: ; preds = %for.body6, %for.con %sub11 = sub nsw i64 %j.03, %i.05 %arrayidx14 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %sub11, i64 %i.05, i64 %add10 %0 = load i32* %arrayidx14, align 4 -; CHECK: da analyze - consistent flow [1 1 -1]! %incdec.ptr = getelementptr inbounds i32* %B.addr.21, i64 1 store i32 %0, i32* %B.addr.21, align 4 %inc = add nsw i64 %k.02, 1 - %cmp5 = icmp slt i64 %inc, 100 - br i1 %cmp5, label %for.body6, label %for.inc15 + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body6, label %for.inc15 for.inc15: ; preds = %for.body6 + %scevgep = getelementptr i32* %B.addr.14, i64 100 %inc16 = add nsw i64 %j.03, 1 - %cmp2 = icmp slt i64 %inc16, 100 - br i1 %cmp2, label %for.cond4.preheader, label %for.inc18 + %exitcond8 = icmp ne i64 %inc16, 100 + br i1 %exitcond8, label %for.cond4.preheader, label %for.inc18 for.inc18: ; preds = %for.inc15 + %scevgep7 = getelementptr i32* %B.addr.06, i64 10000 %inc19 = add nsw i64 %i.05, 1 - %cmp = icmp slt i64 %inc19, 100 - br i1 %cmp, label %for.cond1.preheader, label %for.end20 + %exitcond9 = icmp ne i64 %inc19, 100 + br i1 %exitcond9, label %for.cond1.preheader, label %for.end20 for.end20: ; preds = %for.inc18 ret void @@ -103,20 +118,27 @@ for.end20: ; preds = %for.inc18 ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[i - 1][2*i] = ... -;; ... = A[i][i + j + 110]; +;; for (long int j = 0; j < 100; j++) { +;; A[i - 1][2*i] = i; +;; *B++ = A[i][i + j + 110]; define void @prop2([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc8, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc8 ] +; CHECK: da analyze - consistent output [0 S]! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc8 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc8 ] %i.03 = phi i64 [ 0, %entry ], [ %inc9, %for.inc8 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -128,17 +150,17 @@ for.body3: ; preds = %for.body3, %for.con %add5 = add nsw i64 %add, 110 %arrayidx7 = getelementptr inbounds [100 x i32]* %A, i64 %i.03, i64 %add5 %0 = load i32* %arrayidx7, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 100 - br i1 %cmp2, label %for.body3, label %for.inc8 + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body3, label %for.inc8 for.inc8: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 100 %inc9 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc9, 100 - br i1 %cmp, label %for.cond1.preheader, label %for.end10 + %exitcond5 = icmp ne i64 %inc9, 100 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end10 for.end10: ; preds = %for.inc8 ret void @@ -146,20 +168,27 @@ for.end10: ; preds = %for.inc8 ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[i][2*j + i] = ... -;; ... = A[i][2*j - i + 5]; +;; for (long int j = 0; j < 100; j++) { +;; A[i][2*j + i] = i; +;; *B++ = A[i][2*j - i + 5]; define void @prop3([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc9, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc9 ] +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc9 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc9 ] %i.03 = phi i64 [ 0, %entry ], [ %inc10, %for.inc9 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -172,39 +201,45 @@ for.body3: ; preds = %for.body3, %for.con %add6 = add nsw i64 %sub, 5 %arrayidx8 = getelementptr inbounds [100 x i32]* %A, i64 %i.03, i64 %add6 %0 = load i32* %arrayidx8, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 100 - br i1 %cmp2, label %for.body3, label %for.inc9 + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body3, label %for.inc9 for.inc9: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 100 %inc10 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc10, 100 - br i1 %cmp, label %for.cond1.preheader, label %for.end11 + %exitcond5 = icmp ne i64 %inc10, 100 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end11 for.end11: ; preds = %for.inc9 ret void } -;; propagate Distance ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[i + 2][2*i + j + 1] = ... -;; ... = A[i][2*i + j]; +;; for (long int j = 0; j < 100; j++) { +;; A[i + 2][2*i + j + 1] = i; +;; *B++ = A[i][2*i + j]; define void @prop4([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc11, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc11 ] +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [2 -3]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc11 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc11 ] %i.03 = phi i64 [ 0, %entry ], [ %inc12, %for.inc11 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -218,39 +253,46 @@ for.body3: ; preds = %for.body3, %for.con %add8 = add nsw i64 %mul7, %j.02 %arrayidx10 = getelementptr inbounds [100 x i32]* %A, i64 %i.03, i64 %add8 %0 = load i32* %arrayidx10, align 4 -; CHECK: da analyze - consistent flow [2 -3]! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 100 - br i1 %cmp2, label %for.body3, label %for.inc11 + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body3, label %for.inc11 for.inc11: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 100 %inc12 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc12, 100 - br i1 %cmp, label %for.cond1.preheader, label %for.end13 + %exitcond5 = icmp ne i64 %inc12, 100 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end13 for.end13: ; preds = %for.inc11 ret void } -;; propagate Point ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[3*i - 18][22 - i][2*i + j] = ... -;; ... = A[i][i][3*i + j]; +;; for (long int j = 0; j < 100; j++) { +;; A[3*i - 18][22 - i][2*i + j] = i; +;; *B++ = A[i][i][3*i + j]; define void @prop5([100 x [100 x i32]]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc13, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc13 ] +; CHECK: da analyze - none! +; CHECK: da analyze - flow [< -16] splitable! +; CHECK: da analyze - split level = 1, iteration = 11! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc13 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc13 ] %i.03 = phi i64 [ 0, %entry ], [ %inc14, %for.inc13 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -265,40 +307,45 @@ for.body3: ; preds = %for.body3, %for.con %add9 = add nsw i64 %mul8, %j.02 %arrayidx12 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %i.03, i64 %i.03, i64 %add9 %0 = load i32* %arrayidx12, align 4 -; CHECK: da analyze - flow [< -16] splitable! -; CHECK: da analyze - split level = 1, iteration = 11! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 100 - br i1 %cmp2, label %for.body3, label %for.inc13 + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body3, label %for.inc13 for.inc13: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 100 %inc14 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc14, 100 - br i1 %cmp, label %for.cond1.preheader, label %for.end15 + %exitcond5 = icmp ne i64 %inc14, 100 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end15 for.end15: ; preds = %for.inc13 ret void } -;; propagate Line ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[i + 1][4*i + j + 2] = ... -;; ... = A[2*i][8*i + j]; +;; for (long int j = 0; j < 100; j++) { +;; A[i + 1][4*i + j + 2] = i; +;; *B++ = A[2*i][8*i + j]; define void @prop6([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc12, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc12 ] +; CHECK: da analyze - none! +; CHECK: da analyze - flow [=> -2]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc12 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc12 ] %i.03 = phi i64 [ 0, %entry ], [ %inc13, %for.inc12 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -313,17 +360,17 @@ for.body3: ; preds = %for.body3, %for.con %mul9 = shl nsw i64 %i.03, 1 %arrayidx11 = getelementptr inbounds [100 x i32]* %A, i64 %mul9, i64 %add8 %0 = load i32* %arrayidx11, align 4 -; CHECK: da analyze - flow [=> -2]! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 100 - br i1 %cmp2, label %for.body3, label %for.inc12 + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body3, label %for.inc12 for.inc12: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 100 %inc13 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc13, 100 - br i1 %cmp, label %for.cond1.preheader, label %for.end14 + %exitcond5 = icmp ne i64 %inc13, 100 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end14 for.end14: ; preds = %for.inc12 ret void @@ -331,20 +378,28 @@ for.end14: ; preds = %for.inc12 ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[2*i + 4][-5*i + j + 2] = ... -;; ... = A[-2*i + 20][5*i + j]; +;; for (long int j = 0; j < 100; j++) { +;; A[2*i + 4][-5*i + j + 2] = i; +;; *B++ = A[-2*i + 20][5*i + j]; define void @prop7([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc14, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc14 ] +; CHECK: da analyze - none! +; CHECK: da analyze - flow [* -38] splitable! +; CHECK: da analyze - split level = 1, iteration = 4! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc14 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc14 ] %i.03 = phi i64 [ 0, %entry ], [ %inc15, %for.inc14 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -361,18 +416,17 @@ for.body3: ; preds = %for.body3, %for.con %add11 = add nsw i64 %mul10, 20 %arrayidx13 = getelementptr inbounds [100 x i32]* %A, i64 %add11, i64 %add9 %0 = load i32* %arrayidx13, align 4 -; CHECK: da analyze - flow [* -38] splitable! -; CHECK: da analyze - split level = 1, iteration = 4! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 100 - br i1 %cmp2, label %for.body3, label %for.inc14 + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body3, label %for.inc14 for.inc14: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 100 %inc15 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc15, 100 - br i1 %cmp, label %for.cond1.preheader, label %for.end16 + %exitcond5 = icmp ne i64 %inc15, 100 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end16 for.end16: ; preds = %for.inc14 ret void @@ -380,20 +434,27 @@ for.end16: ; preds = %for.inc14 ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[4][j + 2] = ... -;; ... = A[-2*i + 4][5*i + j]; +;; for (long int j = 0; j < 100; j++) { +;; A[4][j + 2] = i; +;; *B++ = A[-2*i + 4][5*i + j]; define void @prop8([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc10, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc10 ] +; CHECK: da analyze - consistent output [S 0]! +; CHECK: da analyze - flow [p<= 2]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc10 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc10 ] %i.03 = phi i64 [ 0, %entry ], [ %inc11, %for.inc10 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -406,17 +467,17 @@ for.body3: ; preds = %for.body3, %for.con %add7 = add nsw i64 %mul6, 4 %arrayidx9 = getelementptr inbounds [100 x i32]* %A, i64 %add7, i64 %add5 %0 = load i32* %arrayidx9, align 4 -; CHECK: da analyze - flow [p<= 2]! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 100 - br i1 %cmp2, label %for.body3, label %for.inc10 + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body3, label %for.inc10 for.inc10: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 100 %inc11 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc11, 100 - br i1 %cmp, label %for.cond1.preheader, label %for.end12 + %exitcond5 = icmp ne i64 %inc11, 100 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end12 for.end12: ; preds = %for.inc10 ret void @@ -424,20 +485,27 @@ for.end12: ; preds = %for.inc10 ;; for (long int i = 0; i < 100; i++) -;; for (long int j = 0; j < 100; j++) -;; A[2*i + 4][5*i + j + 2] = ... -;; ... = A[4][j]; +;; for (long int j = 0; j < 100; j++) { +;; A[2*i + 4][5*i + j + 2] = i; +;; *B++ = A[4][j]; define void @prop9([100 x i32]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc10, %entry - %B.addr.04 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc10 ] +; CHECK: da analyze - none! +; CHECK: da analyze - flow [p<= 2]! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S 0]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc10 + %B.addr.04 = phi i32* [ %B, %entry ], [ %scevgep, %for.inc10 ] %i.03 = phi i64 [ 0, %entry ], [ %inc11, %for.inc10 ] br label %for.body3 -for.body3: ; preds = %for.body3, %for.cond1.preheader +for.body3: ; preds = %for.cond1.preheader, %for.body3 %j.02 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.body3 ] %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] %conv = trunc i64 %i.03 to i32 @@ -450,17 +518,17 @@ for.body3: ; preds = %for.body3, %for.con store i32 %conv, i32* %arrayidx7, align 4 %arrayidx9 = getelementptr inbounds [100 x i32]* %A, i64 4, i64 %j.02 %0 = load i32* %arrayidx9, align 4 -; CHECK: da analyze - flow [p<= 2]! %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1 store i32 %0, i32* %B.addr.11, align 4 %inc = add nsw i64 %j.02, 1 - %cmp2 = icmp slt i64 %inc, 100 - br i1 %cmp2, label %for.body3, label %for.inc10 + %exitcond = icmp ne i64 %inc, 100 + br i1 %exitcond, label %for.body3, label %for.inc10 for.inc10: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.04, i64 100 %inc11 = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc11, 100 - br i1 %cmp, label %for.cond1.preheader, label %for.end12 + %exitcond5 = icmp ne i64 %inc11, 100 + br i1 %exitcond5, label %for.cond1.preheader, label %for.end12 for.end12: ; preds = %for.inc10 ret void diff --git a/test/Analysis/DependenceAnalysis/Separability.ll b/test/Analysis/DependenceAnalysis/Separability.ll index d42d3cdb39e5..3dcaaec2ae85 100644 --- a/test/Analysis/DependenceAnalysis/Separability.ll +++ b/test/Analysis/DependenceAnalysis/Separability.ll @@ -8,30 +8,37 @@ target triple = "x86_64-apple-macosx10.6.0" ;; for (long int i = 0; i < 50; i++) ;; for (long int j = 0; j < 50; j++) ;; for (long int k = 0; k < 50; k++) -;; for (long int l = 0; l < 50; l++) -;; A[n][i][j + k] = ... -;; ... = A[10][i + 10][2*j - l]; +;; for (long int l = 0; l < 50; l++) { +;; A[n][i][j + k] = i; +;; *B++ = A[10][i + 10][2*j - l]; define void @sep0([100 x [100 x i32]]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc22, %entry - %B.addr.08 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc22 ] +; CHECK: da analyze - output [0 * * S]! +; CHECK: da analyze - flow [-10 * * *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [0 * S *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc22 + %B.addr.08 = phi i32* [ %B, %entry ], [ %scevgep11, %for.inc22 ] %i.07 = phi i64 [ 0, %entry ], [ %inc23, %for.inc22 ] br label %for.cond4.preheader -for.cond4.preheader: ; preds = %for.inc19, %for.cond1.preheader - %B.addr.16 = phi i32* [ %B.addr.08, %for.cond1.preheader ], [ %incdec.ptr, %for.inc19 ] +for.cond4.preheader: ; preds = %for.cond1.preheader, %for.inc19 + %B.addr.16 = phi i32* [ %B.addr.08, %for.cond1.preheader ], [ %scevgep9, %for.inc19 ] %j.05 = phi i64 [ 0, %for.cond1.preheader ], [ %inc20, %for.inc19 ] br label %for.cond7.preheader -for.cond7.preheader: ; preds = %for.inc16, %for.cond4.preheader - %B.addr.24 = phi i32* [ %B.addr.16, %for.cond4.preheader ], [ %incdec.ptr, %for.inc16 ] +for.cond7.preheader: ; preds = %for.cond4.preheader, %for.inc16 + %B.addr.24 = phi i32* [ %B.addr.16, %for.cond4.preheader ], [ %scevgep, %for.inc16 ] %k.03 = phi i64 [ 0, %for.cond4.preheader ], [ %inc17, %for.inc16 ] br label %for.body9 -for.body9: ; preds = %for.body9, %for.cond7.preheader +for.body9: ; preds = %for.cond7.preheader, %for.body9 %l.02 = phi i64 [ 0, %for.cond7.preheader ], [ %inc, %for.body9 ] %B.addr.31 = phi i32* [ %B.addr.24, %for.cond7.preheader ], [ %incdec.ptr, %for.body9 ] %conv = trunc i64 %i.07 to i32 @@ -44,27 +51,29 @@ for.body9: ; preds = %for.body9, %for.con %add12 = add nsw i64 %i.07, 10 %arrayidx15 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 10, i64 %add12, i64 %sub %0 = load i32* %arrayidx15, align 4 -; CHECK: da analyze - flow [-10 * * *]! %incdec.ptr = getelementptr inbounds i32* %B.addr.31, i64 1 store i32 %0, i32* %B.addr.31, align 4 %inc = add nsw i64 %l.02, 1 - %cmp8 = icmp slt i64 %inc, 50 - br i1 %cmp8, label %for.body9, label %for.inc16 + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body9, label %for.inc16 for.inc16: ; preds = %for.body9 + %scevgep = getelementptr i32* %B.addr.24, i64 50 %inc17 = add nsw i64 %k.03, 1 - %cmp5 = icmp slt i64 %inc17, 50 - br i1 %cmp5, label %for.cond7.preheader, label %for.inc19 + %exitcond10 = icmp ne i64 %inc17, 50 + br i1 %exitcond10, label %for.cond7.preheader, label %for.inc19 for.inc19: ; preds = %for.inc16 + %scevgep9 = getelementptr i32* %B.addr.16, i64 2500 %inc20 = add nsw i64 %j.05, 1 - %cmp2 = icmp slt i64 %inc20, 50 - br i1 %cmp2, label %for.cond4.preheader, label %for.inc22 + %exitcond12 = icmp ne i64 %inc20, 50 + br i1 %exitcond12, label %for.cond4.preheader, label %for.inc22 for.inc22: ; preds = %for.inc19 + %scevgep11 = getelementptr i32* %B.addr.08, i64 125000 %inc23 = add nsw i64 %i.07, 1 - %cmp = icmp slt i64 %inc23, 50 - br i1 %cmp, label %for.cond1.preheader, label %for.end24 + %exitcond13 = icmp ne i64 %inc23, 50 + br i1 %exitcond13, label %for.cond1.preheader, label %for.end24 for.end24: ; preds = %for.inc22 ret void @@ -74,30 +83,37 @@ for.end24: ; preds = %for.inc22 ;; for (long int i = 0; i < 50; i++) ;; for (long int j = 0; j < 50; j++) ;; for (long int k = 0; k < 50; k++) -;; for (long int l = 0; l < 50; l++) -;; A[i][i][j + k] = ... -;; ... = A[10][i + 10][2*j - l]; +;; for (long int l = 0; l < 50; l++) { +;; A[i][i][j + k] = i; +;; *B++ = A[10][i + 10][2*j - l]; define void @sep1([100 x [100 x i32]]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc22, %entry - %B.addr.08 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc22 ] +; CHECK: da analyze - output [0 * * S]! +; CHECK: da analyze - flow [> * * *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [0 * S *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc22 + %B.addr.08 = phi i32* [ %B, %entry ], [ %scevgep11, %for.inc22 ] %i.07 = phi i64 [ 0, %entry ], [ %inc23, %for.inc22 ] br label %for.cond4.preheader -for.cond4.preheader: ; preds = %for.inc19, %for.cond1.preheader - %B.addr.16 = phi i32* [ %B.addr.08, %for.cond1.preheader ], [ %incdec.ptr, %for.inc19 ] +for.cond4.preheader: ; preds = %for.cond1.preheader, %for.inc19 + %B.addr.16 = phi i32* [ %B.addr.08, %for.cond1.preheader ], [ %scevgep9, %for.inc19 ] %j.05 = phi i64 [ 0, %for.cond1.preheader ], [ %inc20, %for.inc19 ] br label %for.cond7.preheader -for.cond7.preheader: ; preds = %for.inc16, %for.cond4.preheader - %B.addr.24 = phi i32* [ %B.addr.16, %for.cond4.preheader ], [ %incdec.ptr, %for.inc16 ] +for.cond7.preheader: ; preds = %for.cond4.preheader, %for.inc16 + %B.addr.24 = phi i32* [ %B.addr.16, %for.cond4.preheader ], [ %scevgep, %for.inc16 ] %k.03 = phi i64 [ 0, %for.cond4.preheader ], [ %inc17, %for.inc16 ] br label %for.body9 -for.body9: ; preds = %for.body9, %for.cond7.preheader +for.body9: ; preds = %for.cond7.preheader, %for.body9 %l.02 = phi i64 [ 0, %for.cond7.preheader ], [ %inc, %for.body9 ] %B.addr.31 = phi i32* [ %B.addr.24, %for.cond7.preheader ], [ %incdec.ptr, %for.body9 ] %conv = trunc i64 %i.07 to i32 @@ -109,27 +125,29 @@ for.body9: ; preds = %for.body9, %for.con %add12 = add nsw i64 %i.07, 10 %arrayidx15 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 10, i64 %add12, i64 %sub %0 = load i32* %arrayidx15, align 4 -; CHECK: da analyze - flow [> * * *]! %incdec.ptr = getelementptr inbounds i32* %B.addr.31, i64 1 store i32 %0, i32* %B.addr.31, align 4 %inc = add nsw i64 %l.02, 1 - %cmp8 = icmp slt i64 %inc, 50 - br i1 %cmp8, label %for.body9, label %for.inc16 + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body9, label %for.inc16 for.inc16: ; preds = %for.body9 + %scevgep = getelementptr i32* %B.addr.24, i64 50 %inc17 = add nsw i64 %k.03, 1 - %cmp5 = icmp slt i64 %inc17, 50 - br i1 %cmp5, label %for.cond7.preheader, label %for.inc19 + %exitcond10 = icmp ne i64 %inc17, 50 + br i1 %exitcond10, label %for.cond7.preheader, label %for.inc19 for.inc19: ; preds = %for.inc16 + %scevgep9 = getelementptr i32* %B.addr.16, i64 2500 %inc20 = add nsw i64 %j.05, 1 - %cmp2 = icmp slt i64 %inc20, 50 - br i1 %cmp2, label %for.cond4.preheader, label %for.inc22 + %exitcond12 = icmp ne i64 %inc20, 50 + br i1 %exitcond12, label %for.cond4.preheader, label %for.inc22 for.inc22: ; preds = %for.inc19 + %scevgep11 = getelementptr i32* %B.addr.08, i64 125000 %inc23 = add nsw i64 %i.07, 1 - %cmp = icmp slt i64 %inc23, 50 - br i1 %cmp, label %for.cond1.preheader, label %for.end24 + %exitcond13 = icmp ne i64 %inc23, 50 + br i1 %exitcond13, label %for.cond1.preheader, label %for.end24 for.end24: ; preds = %for.inc22 ret void @@ -139,30 +157,37 @@ for.end24: ; preds = %for.inc22 ;; for (long int i = 0; i < 50; i++) ;; for (long int j = 0; j < 50; j++) ;; for (long int k = 0; k < 50; k++) -;; for (long int l = 0; l < 50; l++) -;; A[i][i][i + k][l] = ... -;; ... = A[10][i + 10][j + k][l + 10]; +;; for (long int l = 0; l < 50; l++) { +;; A[i][i][i + k][l] = i; +;; *B++ = A[10][i + 10][j + k][l + 10]; define void @sep2([100 x [100 x [100 x i32]]]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc26, %entry - %B.addr.08 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc26 ] +; CHECK: da analyze - consistent output [0 S 0 0]! +; CHECK: da analyze - flow [> * * -10]! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [0 * * 0]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc26 + %B.addr.08 = phi i32* [ %B, %entry ], [ %scevgep11, %for.inc26 ] %i.07 = phi i64 [ 0, %entry ], [ %inc27, %for.inc26 ] br label %for.cond4.preheader -for.cond4.preheader: ; preds = %for.inc23, %for.cond1.preheader - %B.addr.16 = phi i32* [ %B.addr.08, %for.cond1.preheader ], [ %incdec.ptr, %for.inc23 ] +for.cond4.preheader: ; preds = %for.cond1.preheader, %for.inc23 + %B.addr.16 = phi i32* [ %B.addr.08, %for.cond1.preheader ], [ %scevgep9, %for.inc23 ] %j.05 = phi i64 [ 0, %for.cond1.preheader ], [ %inc24, %for.inc23 ] br label %for.cond7.preheader -for.cond7.preheader: ; preds = %for.inc20, %for.cond4.preheader - %B.addr.24 = phi i32* [ %B.addr.16, %for.cond4.preheader ], [ %incdec.ptr, %for.inc20 ] +for.cond7.preheader: ; preds = %for.cond4.preheader, %for.inc20 + %B.addr.24 = phi i32* [ %B.addr.16, %for.cond4.preheader ], [ %scevgep, %for.inc20 ] %k.03 = phi i64 [ 0, %for.cond4.preheader ], [ %inc21, %for.inc20 ] br label %for.body9 -for.body9: ; preds = %for.body9, %for.cond7.preheader +for.body9: ; preds = %for.cond7.preheader, %for.body9 %l.02 = phi i64 [ 0, %for.cond7.preheader ], [ %inc, %for.body9 ] %B.addr.31 = phi i32* [ %B.addr.24, %for.cond7.preheader ], [ %incdec.ptr, %for.body9 ] %conv = trunc i64 %i.07 to i32 @@ -174,27 +199,29 @@ for.body9: ; preds = %for.body9, %for.con %add15 = add nsw i64 %i.07, 10 %arrayidx19 = getelementptr inbounds [100 x [100 x [100 x i32]]]* %A, i64 10, i64 %add15, i64 %add14, i64 %add13 %0 = load i32* %arrayidx19, align 4 -; CHECK: da analyze - flow [> * * -10]! %incdec.ptr = getelementptr inbounds i32* %B.addr.31, i64 1 store i32 %0, i32* %B.addr.31, align 4 %inc = add nsw i64 %l.02, 1 - %cmp8 = icmp slt i64 %inc, 50 - br i1 %cmp8, label %for.body9, label %for.inc20 + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body9, label %for.inc20 for.inc20: ; preds = %for.body9 + %scevgep = getelementptr i32* %B.addr.24, i64 50 %inc21 = add nsw i64 %k.03, 1 - %cmp5 = icmp slt i64 %inc21, 50 - br i1 %cmp5, label %for.cond7.preheader, label %for.inc23 + %exitcond10 = icmp ne i64 %inc21, 50 + br i1 %exitcond10, label %for.cond7.preheader, label %for.inc23 for.inc23: ; preds = %for.inc20 + %scevgep9 = getelementptr i32* %B.addr.16, i64 2500 %inc24 = add nsw i64 %j.05, 1 - %cmp2 = icmp slt i64 %inc24, 50 - br i1 %cmp2, label %for.cond4.preheader, label %for.inc26 + %exitcond12 = icmp ne i64 %inc24, 50 + br i1 %exitcond12, label %for.cond4.preheader, label %for.inc26 for.inc26: ; preds = %for.inc23 + %scevgep11 = getelementptr i32* %B.addr.08, i64 125000 %inc27 = add nsw i64 %i.07, 1 - %cmp = icmp slt i64 %inc27, 50 - br i1 %cmp, label %for.cond1.preheader, label %for.end28 + %exitcond13 = icmp ne i64 %inc27, 50 + br i1 %exitcond13, label %for.cond1.preheader, label %for.end28 for.end28: ; preds = %for.inc26 ret void @@ -204,30 +231,37 @@ for.end28: ; preds = %for.inc26 ;; for (long int i = 0; i < 50; i++) ;; for (long int j = 0; j < 50; j++) ;; for (long int k = 0; k < 50; k++) -;; for (long int l = 0; l < 50; l++) -;; A[i][i][i + k][l + k] = ... -;; ... = A[10][i + 10][j + k][l + 10]; +;; for (long int l = 0; l < 50; l++) { +;; A[i][i][i + k][l + k] = i; +;; *B++ = A[10][i + 10][j + k][l + 10]; define void @sep3([100 x [100 x [100 x i32]]]* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc27, %entry - %B.addr.08 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.inc27 ] +; CHECK: da analyze - consistent output [0 S 0 0]! +; CHECK: da analyze - flow [> * * *]! +; CHECK: da analyze - confused! +; CHECK: da analyze - input [0 * * 0]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.cond1.preheader: ; preds = %entry, %for.inc27 + %B.addr.08 = phi i32* [ %B, %entry ], [ %scevgep11, %for.inc27 ] %i.07 = phi i64 [ 0, %entry ], [ %inc28, %for.inc27 ] br label %for.cond4.preheader -for.cond4.preheader: ; preds = %for.inc24, %for.cond1.preheader - %B.addr.16 = phi i32* [ %B.addr.08, %for.cond1.preheader ], [ %incdec.ptr, %for.inc24 ] +for.cond4.preheader: ; preds = %for.cond1.preheader, %for.inc24 + %B.addr.16 = phi i32* [ %B.addr.08, %for.cond1.preheader ], [ %scevgep9, %for.inc24 ] %j.05 = phi i64 [ 0, %for.cond1.preheader ], [ %inc25, %for.inc24 ] br label %for.cond7.preheader -for.cond7.preheader: ; preds = %for.inc21, %for.cond4.preheader - %B.addr.24 = phi i32* [ %B.addr.16, %for.cond4.preheader ], [ %incdec.ptr, %for.inc21 ] +for.cond7.preheader: ; preds = %for.cond4.preheader, %for.inc21 + %B.addr.24 = phi i32* [ %B.addr.16, %for.cond4.preheader ], [ %scevgep, %for.inc21 ] %k.03 = phi i64 [ 0, %for.cond4.preheader ], [ %inc22, %for.inc21 ] br label %for.body9 -for.body9: ; preds = %for.body9, %for.cond7.preheader +for.body9: ; preds = %for.cond7.preheader, %for.body9 %l.02 = phi i64 [ 0, %for.cond7.preheader ], [ %inc, %for.body9 ] %B.addr.31 = phi i32* [ %B.addr.24, %for.cond7.preheader ], [ %incdec.ptr, %for.body9 ] %conv = trunc i64 %i.07 to i32 @@ -240,27 +274,29 @@ for.body9: ; preds = %for.body9, %for.con %add16 = add nsw i64 %i.07, 10 %arrayidx20 = getelementptr inbounds [100 x [100 x [100 x i32]]]* %A, i64 10, i64 %add16, i64 %add15, i64 %add14 %0 = load i32* %arrayidx20, align 4 -; CHECK: da analyze - flow [> * * *]! %incdec.ptr = getelementptr inbounds i32* %B.addr.31, i64 1 store i32 %0, i32* %B.addr.31, align 4 %inc = add nsw i64 %l.02, 1 - %cmp8 = icmp slt i64 %inc, 50 - br i1 %cmp8, label %for.body9, label %for.inc21 + %exitcond = icmp ne i64 %inc, 50 + br i1 %exitcond, label %for.body9, label %for.inc21 for.inc21: ; preds = %for.body9 + %scevgep = getelementptr i32* %B.addr.24, i64 50 %inc22 = add nsw i64 %k.03, 1 - %cmp5 = icmp slt i64 %inc22, 50 - br i1 %cmp5, label %for.cond7.preheader, label %for.inc24 + %exitcond10 = icmp ne i64 %inc22, 50 + br i1 %exitcond10, label %for.cond7.preheader, label %for.inc24 for.inc24: ; preds = %for.inc21 + %scevgep9 = getelementptr i32* %B.addr.16, i64 2500 %inc25 = add nsw i64 %j.05, 1 - %cmp2 = icmp slt i64 %inc25, 50 - br i1 %cmp2, label %for.cond4.preheader, label %for.inc27 + %exitcond12 = icmp ne i64 %inc25, 50 + br i1 %exitcond12, label %for.cond4.preheader, label %for.inc27 for.inc27: ; preds = %for.inc24 + %scevgep11 = getelementptr i32* %B.addr.08, i64 125000 %inc28 = add nsw i64 %i.07, 1 - %cmp = icmp slt i64 %inc28, 50 - br i1 %cmp, label %for.cond1.preheader, label %for.end29 + %exitcond13 = icmp ne i64 %inc28, 50 + br i1 %exitcond13, label %for.cond1.preheader, label %for.end29 for.end29: ; preds = %for.inc27 ret void diff --git a/test/Analysis/DependenceAnalysis/StrongSIV.ll b/test/Analysis/DependenceAnalysis/StrongSIV.ll index be336c3580ce..f499e84d4844 100644 --- a/test/Analysis/DependenceAnalysis/StrongSIV.ll +++ b/test/Analysis/DependenceAnalysis/StrongSIV.ll @@ -1,143 +1,196 @@ -; RUN: opt < %s -analyze -basicaa -indvars -da | FileCheck %s +; RUN: opt < %s -analyze -basicaa -da | FileCheck %s ; ModuleID = 'StrongSIV.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.6.0" -;; for (int i = 0; i < n; i++) -;; A[i + 2] = ... -;; ... = A[i]; +;; for (int i = 0; i < n; i++) { +;; A[i + 2] = i; +;; *B++ = A[i]; define void @strong0(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp sgt i64 %n, 0 - br i1 %cmp1, label %for.body, label %for.end - -for.body: ; preds = %for.body, %entry - %i.03 = phi i32 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] - %add = add nsw i32 %i.03, 2 - %idxprom = sext i32 %add to i64 - %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom - store i32 %i.03, i32* %arrayidx, align 4 - %idxprom2 = sext i32 %i.03 to i64 - %arrayidx3 = getelementptr inbounds i32* %A, i64 %idxprom2 - %0 = load i32* %arrayidx3, align 4 + br i1 %cmp1, label %for.body.preheader, label %for.end + +; CHECK: da analyze - none! ; CHECK: da analyze - consistent flow [2]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] + %0 = add nsw i64 %indvars.iv, 2 + %arrayidx = getelementptr inbounds i32* %A, i64 %0 + %1 = trunc i64 %indvars.iv to i32 + store i32 %1, i32* %arrayidx, align 4 + %arrayidx3 = getelementptr inbounds i32* %A, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 - store i32 %0, i32* %B.addr.02, align 4 - %inc = add nsw i32 %i.03, 1 - %conv = sext i32 %inc to i64 - %cmp = icmp slt i64 %conv, %n - br i1 %cmp, label %for.body, label %for.end + store i32 %2, i32* %B.addr.02, align 4 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp ne i64 %indvars.iv.next, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit -for.end: ; preds = %for.body, %entry +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long int i = 0; i < n; i++) -;; A[i + 2] = ... -;; ... = A[i]; +;; for (long int i = 0; i < n; i++) { +;; A[i + 2] = i; +;; *B++ = A[i]; define void @strong1(i32* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: - %conv = sext i32 %n to i64 %cmp1 = icmp sgt i32 %n, 0 - br i1 %cmp1, label %for.body, label %for.end + br i1 %cmp1, label %for.body.preheader, label %for.end + +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [2]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + %0 = sext i32 %n to i64 + br label %for.body -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv2 = trunc i64 %i.03 to i32 %add = add nsw i64 %i.03, 2 %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv2, i32* %arrayidx, align 4 %arrayidx3 = getelementptr inbounds i32* %A, i64 %i.03 - %0 = load i32* %arrayidx3, align 4 -; CHECK: da analyze - consistent flow [2]! + %1 = load i32* %arrayidx3, align 4 %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 - store i32 %0, i32* %B.addr.02, align 4 + store i32 %1, i32* %B.addr.02, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp slt i64 %inc, %conv - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %0 + br i1 %exitcond, label %for.body, label %for.end.loopexit -for.end: ; preds = %for.body, %entry +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long unsigned i = 0; i < n; i++) -;; A[i + 2] = ... -;; ... = A[i]; +;; for (long unsigned i = 0; i < n; i++) { +;; A[i + 2] = i; +;; *B++ = A[i]; define void @strong2(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [2]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %add = add i64 %i.03, 2 %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 %i.03 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - consistent flow [2]! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (int i = 0; i < n; i++) -;; A[i + 2] = ... -;; ... = A[i]; +;; for (int i = 0; i < n; i++) { +;; A[i + 2] = i; +;; *B++ = A[i]; define void @strong3(i32* %A, i32* %B, i32 %n) nounwind uwtable ssp { entry: %cmp1 = icmp sgt i32 %n, 0 - br i1 %cmp1, label %for.body, label %for.end - -for.body: ; preds = %for.body, %entry - %i.03 = phi i32 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] - %add = add nsw i32 %i.03, 2 - %idxprom = sext i32 %add to i64 - %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom - store i32 %i.03, i32* %arrayidx, align 4 - %idxprom1 = sext i32 %i.03 to i64 - %arrayidx2 = getelementptr inbounds i32* %A, i64 %idxprom1 - %0 = load i32* %arrayidx2, align 4 + br i1 %cmp1, label %for.body.preheader, label %for.end + +; CHECK: da analyze - none! ; CHECK: da analyze - consistent flow [2]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] + %0 = add nsw i64 %indvars.iv, 2 + %arrayidx = getelementptr inbounds i32* %A, i64 %0 + %1 = trunc i64 %indvars.iv to i32 + store i32 %1, i32* %arrayidx, align 4 + %arrayidx2 = getelementptr inbounds i32* %A, i64 %indvars.iv + %2 = load i32* %arrayidx2, align 4 %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 - store i32 %0, i32* %B.addr.02, align 4 - %inc = add nsw i32 %i.03, 1 - %cmp = icmp slt i32 %inc, %n - br i1 %cmp, label %for.body, label %for.end + store i32 %2, i32* %B.addr.02, align 4 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp ne i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long unsigned i = 0; i < 19; i++) -;; A[i + 19] = ... -;; ... = A[i]; +;; for (long unsigned i = 0; i < 19; i++) { +;; A[i + 19] = i; +;; *B++ = A[i]; define void @strong4(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -146,27 +199,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 %i.02 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 19 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 19 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 20; i++) -;; A[i + 19] = ... -;; ... = A[i]; +;; for (long unsigned i = 0; i < 20; i++) { +;; A[i + 19] = i; +;; *B++ = A[i]; define void @strong5(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [19]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -175,27 +234,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 %i.02 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - consistent flow [19]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 20 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 20 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 20; i++) -;; A[2*i + 6] = ... -;; ... = A[2*i]; +;; for (long unsigned i = 0; i < 20; i++) { +;; A[2*i + 6] = i; +;; *B++ = A[2*i]; define void @strong6(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [3]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -206,27 +271,33 @@ for.body: ; preds = %for.body, %entry %mul1 = shl i64 %i.02, 1 %arrayidx2 = getelementptr inbounds i32* %A, i64 %mul1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - consistent flow [3]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 20 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 20 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 20; i++) -;; A[2*i + 7] = ... -;; ... = A[2*i]; +;; for (long unsigned i = 0; i < 20; i++) { +;; A[2*i + 7] = i; +;; *B++ = A[2*i]; define void @strong7(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -237,27 +308,33 @@ for.body: ; preds = %for.body, %entry %mul1 = shl i64 %i.02, 1 %arrayidx2 = getelementptr inbounds i32* %A, i64 %mul1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 20 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 20 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 20; i++) -;; A[i + n] = ... -;; ... = A[i]; +;; for (long unsigned i = 0; i < 20; i++) { +;; A[i + n] = i; +;; *B++ = A[i]; define void @strong8(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [%n|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -266,30 +343,39 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 %i.02 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - consistent flow [%n|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 20 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 20 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < n; i++) -;; A[i + n] = ... -;; ... = A[i + 2*n]; +;; for (long unsigned i = 0; i < n; i++) { +;; A[i + n] = i; +;; *B++ = A[i + 2*n]; define void @strong9(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %add = add i64 %i.03, %n %arrayidx = getelementptr inbounds i32* %A, i64 %add @@ -298,27 +384,36 @@ for.body: ; preds = %for.body, %entry %add1 = add i64 %i.03, %mul %arrayidx2 = getelementptr inbounds i32* %A, i64 %add1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit -for.end: ; preds = %for.body, %entry +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long unsigned i = 0; i < 1000; i++) -;; A[n*i + 5] = ... -;; ... = A[n*i + 5]; +;; for (long unsigned i = 0; i < 1000; i++) { +;; A[n*i + 5] = i; +;; *B++ = A[n*i + 5]; define void @strong10(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [0|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -330,12 +425,11 @@ for.body: ; preds = %for.body, %entry %add2 = add i64 %mul1, 5 %arrayidx3 = getelementptr inbounds i32* %A, i64 %add2 %0 = load i32* %arrayidx3, align 4 -; CHECK: da analyze - consistent flow [0|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 1000 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 1000 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void diff --git a/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll b/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll index 2a1b4e7e971d..81e61892d8e8 100644 --- a/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll +++ b/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll @@ -6,65 +6,99 @@ target triple = "x86_64-apple-macosx10.6.0" ;; for (long int i = 0; i < n1; i++) -;; A[2*i + n1] = ... +;; A[2*i + n1] = i; ;; for (long int j = 0; j < n2; j++) -;; ... = A[3*j + 3*n1]; +;; *B++ = A[3*j + 3*n1]; define void @symbolicrdiv0(i32* %A, i32* %B, i64 %n1, i64 %n2) nounwind uwtable ssp { entry: %cmp4 = icmp eq i64 %n1, 0 - br i1 %cmp4, label %for.cond1.preheader, label %for.body + br i1 %cmp4, label %for.cond1.preheader, label %for.body.preheader -for.cond1.preheader: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond1.preheader.loopexit: ; preds = %for.body + br label %for.cond1.preheader + +for.cond1.preheader: ; preds = %for.cond1.preheader.loopexit, %entry %cmp21 = icmp eq i64 %n2, 0 - br i1 %cmp21, label %for.end11, label %for.body4 + br i1 %cmp21, label %for.end11, label %for.body4.preheader -for.body: ; preds = %for.body, %entry - %i.05 = phi i64 [ %inc, %for.body ], [ 0, %entry ] +for.body4.preheader: ; preds = %for.cond1.preheader + br label %for.body4 + +for.body: ; preds = %for.body.preheader, %for.body + %i.05 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] %conv = trunc i64 %i.05 to i32 %mul = shl nsw i64 %i.05, 1 %add = add i64 %mul, %n1 %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.05, 1 - %cmp = icmp ult i64 %inc, %n1 - br i1 %cmp, label %for.body, label %for.cond1.preheader + %exitcond = icmp ne i64 %inc, %n1 + br i1 %exitcond, label %for.body, label %for.cond1.preheader.loopexit -for.body4: ; preds = %for.body4, %for.cond1.preheader - %j.03 = phi i64 [ %inc10, %for.body4 ], [ 0, %for.cond1.preheader ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.cond1.preheader ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.03 = phi i64 [ %inc10, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %mul56 = add i64 %j.03, %n1 %add7 = mul i64 %mul56, 3 %arrayidx8 = getelementptr inbounds i32* %A, i64 %add7 %0 = load i32* %arrayidx8, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc10 = add nsw i64 %j.03, 1 - %cmp2 = icmp ult i64 %inc10, %n2 - br i1 %cmp2, label %for.body4, label %for.end11 + %exitcond7 = icmp ne i64 %inc10, %n2 + br i1 %exitcond7, label %for.body4, label %for.end11.loopexit -for.end11: ; preds = %for.body4, %for.cond1.preheader +for.end11.loopexit: ; preds = %for.body4 + br label %for.end11 + +for.end11: ; preds = %for.end11.loopexit, %for.cond1.preheader ret void } ;; for (long int i = 0; i < n1; i++) -;; A[2*i + 5*n2] = ... +;; A[2*i + 5*n2] = i; ;; for (long int j = 0; j < n2; j++) -;; ... = A[3*j + 2*n2]; +;; *B++ = A[3*j + 2*n2]; define void @symbolicrdiv1(i32* %A, i32* %B, i64 %n1, i64 %n2) nounwind uwtable ssp { entry: %cmp4 = icmp eq i64 %n1, 0 - br i1 %cmp4, label %for.cond2.preheader, label %for.body + br i1 %cmp4, label %for.cond2.preheader, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond2.preheader.loopexit: ; preds = %for.body + br label %for.cond2.preheader -for.cond2.preheader: ; preds = %for.body, %entry +for.cond2.preheader: ; preds = %for.cond2.preheader.loopexit, %entry %cmp31 = icmp eq i64 %n2, 0 - br i1 %cmp31, label %for.end12, label %for.body5 + br i1 %cmp31, label %for.end12, label %for.body5.preheader -for.body: ; preds = %for.body, %entry - %i.05 = phi i64 [ %inc, %for.body ], [ 0, %entry ] +for.body5.preheader: ; preds = %for.cond2.preheader + br label %for.body5 + +for.body: ; preds = %for.body.preheader, %for.body + %i.05 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] %conv = trunc i64 %i.05 to i32 %mul = shl nsw i64 %i.05, 1 %mul1 = mul i64 %n2, 5 @@ -72,220 +106,307 @@ for.body: ; preds = %for.body, %entry %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.05, 1 - %cmp = icmp ult i64 %inc, %n1 - br i1 %cmp, label %for.body, label %for.cond2.preheader + %exitcond = icmp ne i64 %inc, %n1 + br i1 %exitcond, label %for.body, label %for.cond2.preheader.loopexit -for.body5: ; preds = %for.body5, %for.cond2.preheader - %j.03 = phi i64 [ %inc11, %for.body5 ], [ 0, %for.cond2.preheader ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body5 ], [ %B, %for.cond2.preheader ] +for.body5: ; preds = %for.body5.preheader, %for.body5 + %j.03 = phi i64 [ %inc11, %for.body5 ], [ 0, %for.body5.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body5 ], [ %B, %for.body5.preheader ] %mul6 = mul nsw i64 %j.03, 3 %mul7 = shl i64 %n2, 1 %add8 = add i64 %mul6, %mul7 %arrayidx9 = getelementptr inbounds i32* %A, i64 %add8 %0 = load i32* %arrayidx9, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc11 = add nsw i64 %j.03, 1 - %cmp3 = icmp ult i64 %inc11, %n2 - br i1 %cmp3, label %for.body5, label %for.end12 + %exitcond6 = icmp ne i64 %inc11, %n2 + br i1 %exitcond6, label %for.body5, label %for.end12.loopexit + +for.end12.loopexit: ; preds = %for.body5 + br label %for.end12 -for.end12: ; preds = %for.body5, %for.cond2.preheader +for.end12: ; preds = %for.end12.loopexit, %for.cond2.preheader ret void } ;; for (long int i = 0; i < n1; i++) -;; A[2*i - n2] = ... +;; A[2*i - n2] = i; ;; for (long int j = 0; j < n2; j++) -;; ... = A[-j + 2*n1]; +;; *B++ = A[-j + 2*n1]; define void @symbolicrdiv2(i32* %A, i32* %B, i64 %n1, i64 %n2) nounwind uwtable ssp { entry: %cmp4 = icmp eq i64 %n1, 0 - br i1 %cmp4, label %for.cond1.preheader, label %for.body + br i1 %cmp4, label %for.cond1.preheader, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body -for.cond1.preheader: ; preds = %for.body, %entry +for.cond1.preheader.loopexit: ; preds = %for.body + br label %for.cond1.preheader + +for.cond1.preheader: ; preds = %for.cond1.preheader.loopexit, %entry %cmp21 = icmp eq i64 %n2, 0 - br i1 %cmp21, label %for.end10, label %for.body4 + br i1 %cmp21, label %for.end10, label %for.body4.preheader + +for.body4.preheader: ; preds = %for.cond1.preheader + br label %for.body4 -for.body: ; preds = %for.body, %entry - %i.05 = phi i64 [ %inc, %for.body ], [ 0, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.05 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] %conv = trunc i64 %i.05 to i32 %mul = shl nsw i64 %i.05, 1 %sub = sub i64 %mul, %n2 %arrayidx = getelementptr inbounds i32* %A, i64 %sub store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.05, 1 - %cmp = icmp ult i64 %inc, %n1 - br i1 %cmp, label %for.body, label %for.cond1.preheader + %exitcond = icmp ne i64 %inc, %n1 + br i1 %exitcond, label %for.body, label %for.cond1.preheader.loopexit -for.body4: ; preds = %for.body4, %for.cond1.preheader - %j.03 = phi i64 [ %inc9, %for.body4 ], [ 0, %for.cond1.preheader ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.cond1.preheader ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.03 = phi i64 [ %inc9, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %mul6 = shl i64 %n1, 1 %add = sub i64 %mul6, %j.03 %arrayidx7 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx7, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc9 = add nsw i64 %j.03, 1 - %cmp2 = icmp ult i64 %inc9, %n2 - br i1 %cmp2, label %for.body4, label %for.end10 + %exitcond6 = icmp ne i64 %inc9, %n2 + br i1 %exitcond6, label %for.body4, label %for.end10.loopexit + +for.end10.loopexit: ; preds = %for.body4 + br label %for.end10 -for.end10: ; preds = %for.body4, %for.cond1.preheader +for.end10: ; preds = %for.end10.loopexit, %for.cond1.preheader ret void } ;; for (long int i = 0; i < n1; i++) -;; A[-i + n2] = ... +;; A[-i + n2] = i; ;; for (long int j = 0; j < n2; j++) -;; ... = A[j - n1]; +;; *B++ = A[j - n1]; define void @symbolicrdiv3(i32* %A, i32* %B, i64 %n1, i64 %n2) nounwind uwtable ssp { entry: %cmp4 = icmp eq i64 %n1, 0 - br i1 %cmp4, label %for.cond1.preheader, label %for.body + br i1 %cmp4, label %for.cond1.preheader, label %for.body.preheader -for.cond1.preheader: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond1.preheader.loopexit: ; preds = %for.body + br label %for.cond1.preheader + +for.cond1.preheader: ; preds = %for.cond1.preheader.loopexit, %entry %cmp21 = icmp eq i64 %n2, 0 - br i1 %cmp21, label %for.end9, label %for.body4 + br i1 %cmp21, label %for.end9, label %for.body4.preheader -for.body: ; preds = %for.body, %entry - %i.05 = phi i64 [ %inc, %for.body ], [ 0, %entry ] +for.body4.preheader: ; preds = %for.cond1.preheader + br label %for.body4 + +for.body: ; preds = %for.body.preheader, %for.body + %i.05 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] %conv = trunc i64 %i.05 to i32 %add = sub i64 %n2, %i.05 %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.05, 1 - %cmp = icmp ult i64 %inc, %n1 - br i1 %cmp, label %for.body, label %for.cond1.preheader + %exitcond = icmp ne i64 %inc, %n1 + br i1 %exitcond, label %for.body, label %for.cond1.preheader.loopexit -for.body4: ; preds = %for.body4, %for.cond1.preheader - %j.03 = phi i64 [ %inc8, %for.body4 ], [ 0, %for.cond1.preheader ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.cond1.preheader ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.03 = phi i64 [ %inc8, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %sub5 = sub i64 %j.03, %n1 %arrayidx6 = getelementptr inbounds i32* %A, i64 %sub5 %0 = load i32* %arrayidx6, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc8 = add nsw i64 %j.03, 1 - %cmp2 = icmp ult i64 %inc8, %n2 - br i1 %cmp2, label %for.body4, label %for.end9 + %exitcond6 = icmp ne i64 %inc8, %n2 + br i1 %exitcond6, label %for.body4, label %for.end9.loopexit -for.end9: ; preds = %for.body4, %for.cond1.preheader +for.end9.loopexit: ; preds = %for.body4 + br label %for.end9 + +for.end9: ; preds = %for.end9.loopexit, %for.cond1.preheader ret void } ;; for (long int i = 0; i < n1; i++) -;; A[-i + 2*n1] = ... +;; A[-i + 2*n1] = i; ;; for (long int j = 0; j < n2; j++) -;; ... = A[-j + n1]; +;; *B++ = A[-j + n1]; define void @symbolicrdiv4(i32* %A, i32* %B, i64 %n1, i64 %n2) nounwind uwtable ssp { entry: %cmp4 = icmp eq i64 %n1, 0 - br i1 %cmp4, label %for.cond1.preheader, label %for.body + br i1 %cmp4, label %for.cond1.preheader, label %for.body.preheader -for.cond1.preheader: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond1.preheader.loopexit: ; preds = %for.body + br label %for.cond1.preheader + +for.cond1.preheader: ; preds = %for.cond1.preheader.loopexit, %entry %cmp21 = icmp eq i64 %n2, 0 - br i1 %cmp21, label %for.end10, label %for.body4 + br i1 %cmp21, label %for.end10, label %for.body4.preheader -for.body: ; preds = %for.body, %entry - %i.05 = phi i64 [ %inc, %for.body ], [ 0, %entry ] +for.body4.preheader: ; preds = %for.cond1.preheader + br label %for.body4 + +for.body: ; preds = %for.body.preheader, %for.body + %i.05 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] %conv = trunc i64 %i.05 to i32 %mul = shl i64 %n1, 1 %add = sub i64 %mul, %i.05 %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.05, 1 - %cmp = icmp ult i64 %inc, %n1 - br i1 %cmp, label %for.body, label %for.cond1.preheader + %exitcond = icmp ne i64 %inc, %n1 + br i1 %exitcond, label %for.body, label %for.cond1.preheader.loopexit -for.body4: ; preds = %for.body4, %for.cond1.preheader - %j.03 = phi i64 [ %inc9, %for.body4 ], [ 0, %for.cond1.preheader ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.cond1.preheader ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.03 = phi i64 [ %inc9, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %add6 = sub i64 %n1, %j.03 %arrayidx7 = getelementptr inbounds i32* %A, i64 %add6 %0 = load i32* %arrayidx7, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc9 = add nsw i64 %j.03, 1 - %cmp2 = icmp ult i64 %inc9, %n2 - br i1 %cmp2, label %for.body4, label %for.end10 + %exitcond6 = icmp ne i64 %inc9, %n2 + br i1 %exitcond6, label %for.body4, label %for.end10.loopexit -for.end10: ; preds = %for.body4, %for.cond1.preheader +for.end10.loopexit: ; preds = %for.body4 + br label %for.end10 + +for.end10: ; preds = %for.end10.loopexit, %for.cond1.preheader ret void } ;; for (long int i = 0; i < n1; i++) -;; A[-i + n2] = ... +;; A[-i + n2] = i; ;; for (long int j = 0; j < n2; j++) -;; ... = A[-j + 2*n2]; +;; *B++ = A[-j + 2*n2]; define void @symbolicrdiv5(i32* %A, i32* %B, i64 %n1, i64 %n2) nounwind uwtable ssp { entry: %cmp4 = icmp eq i64 %n1, 0 - br i1 %cmp4, label %for.cond1.preheader, label %for.body + br i1 %cmp4, label %for.cond1.preheader, label %for.body.preheader -for.cond1.preheader: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond1.preheader.loopexit: ; preds = %for.body + br label %for.cond1.preheader + +for.cond1.preheader: ; preds = %for.cond1.preheader.loopexit, %entry %cmp21 = icmp eq i64 %n2, 0 - br i1 %cmp21, label %for.end10, label %for.body4 + br i1 %cmp21, label %for.end10, label %for.body4.preheader -for.body: ; preds = %for.body, %entry - %i.05 = phi i64 [ %inc, %for.body ], [ 0, %entry ] +for.body4.preheader: ; preds = %for.cond1.preheader + br label %for.body4 + +for.body: ; preds = %for.body.preheader, %for.body + %i.05 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] %conv = trunc i64 %i.05 to i32 %add = sub i64 %n2, %i.05 %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 %conv, i32* %arrayidx, align 4 %inc = add nsw i64 %i.05, 1 - %cmp = icmp ult i64 %inc, %n1 - br i1 %cmp, label %for.body, label %for.cond1.preheader + %exitcond = icmp ne i64 %inc, %n1 + br i1 %exitcond, label %for.body, label %for.cond1.preheader.loopexit -for.body4: ; preds = %for.body4, %for.cond1.preheader - %j.03 = phi i64 [ %inc9, %for.body4 ], [ 0, %for.cond1.preheader ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.cond1.preheader ] +for.body4: ; preds = %for.body4.preheader, %for.body4 + %j.03 = phi i64 [ %inc9, %for.body4 ], [ 0, %for.body4.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %mul = shl i64 %n2, 1 %add6 = sub i64 %mul, %j.03 %arrayidx7 = getelementptr inbounds i32* %A, i64 %add6 %0 = load i32* %arrayidx7, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc9 = add nsw i64 %j.03, 1 - %cmp2 = icmp ult i64 %inc9, %n2 - br i1 %cmp2, label %for.body4, label %for.end10 + %exitcond6 = icmp ne i64 %inc9, %n2 + br i1 %exitcond6, label %for.body4, label %for.end10.loopexit -for.end10: ; preds = %for.body4, %for.cond1.preheader +for.end10.loopexit: ; preds = %for.body4 + br label %for.end10 + +for.end10: ; preds = %for.end10.loopexit, %for.cond1.preheader ret void } ;; for (long int i = 0; i < n1; i++) -;; for (long int j = 0; j < n2; j++) -;; A[j -i + n2] = ... -;; ... = A[2*n2]; +;; for (long int j = 0; j < n2; j++) { +;; A[j -i + n2] = i; +;; *B++ = A[2*n2]; define void @symbolicrdiv6(i32* %A, i32* %B, i64 %n1, i64 %n2) nounwind uwtable ssp { entry: %cmp4 = icmp eq i64 %n1, 0 - br i1 %cmp4, label %for.end7, label %for.cond1.preheader + br i1 %cmp4, label %for.end7, label %for.cond1.preheader.preheader + +; CHECK: da analyze - output [* *]! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - output [* *]! + +for.cond1.preheader.preheader: ; preds = %entry + br label %for.cond1.preheader -for.cond1.preheader: ; preds = %for.inc5, %entry - %B.addr.06 = phi i32* [ %B.addr.1.lcssa, %for.inc5 ], [ %B, %entry ] - %i.05 = phi i64 [ %inc6, %for.inc5 ], [ 0, %entry ] +for.cond1.preheader: ; preds = %for.cond1.preheader.preheader, %for.inc5 + %B.addr.06 = phi i32* [ %B.addr.1.lcssa, %for.inc5 ], [ %B, %for.cond1.preheader.preheader ] + %i.05 = phi i64 [ %inc6, %for.inc5 ], [ 0, %for.cond1.preheader.preheader ] %cmp21 = icmp eq i64 %n2, 0 - br i1 %cmp21, label %for.inc5, label %for.body3 + br i1 %cmp21, label %for.inc5, label %for.body3.preheader -for.body3: ; preds = %for.body3, %for.cond1.preheader - %j.03 = phi i64 [ %inc, %for.body3 ], [ 0, %for.cond1.preheader ] - %B.addr.12 = phi i32* [ %incdec.ptr, %for.body3 ], [ %B.addr.06, %for.cond1.preheader ] +for.body3.preheader: ; preds = %for.cond1.preheader + br label %for.body3 + +for.body3: ; preds = %for.body3.preheader, %for.body3 + %j.03 = phi i64 [ %inc, %for.body3 ], [ 0, %for.body3.preheader ] + %B.addr.12 = phi i32* [ %incdec.ptr, %for.body3 ], [ %B.addr.06, %for.body3.preheader ] %conv = trunc i64 %i.05 to i32 %sub = sub nsw i64 %j.03, %i.05 %add = add i64 %sub, %n2 @@ -294,19 +415,25 @@ for.body3: ; preds = %for.body3, %for.con %mul = shl i64 %n2, 1 %arrayidx4 = getelementptr inbounds i32* %A, i64 %mul %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.12, i64 1 store i32 %0, i32* %B.addr.12, align 4 %inc = add nsw i64 %j.03, 1 - %cmp2 = icmp ult i64 %inc, %n2 - br i1 %cmp2, label %for.body3, label %for.inc5 + %exitcond = icmp ne i64 %inc, %n2 + br i1 %exitcond, label %for.body3, label %for.inc5.loopexit -for.inc5: ; preds = %for.body3, %for.cond1.preheader - %B.addr.1.lcssa = phi i32* [ %B.addr.06, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ] +for.inc5.loopexit: ; preds = %for.body3 + %scevgep = getelementptr i32* %B.addr.06, i64 %n2 + br label %for.inc5 + +for.inc5: ; preds = %for.inc5.loopexit, %for.cond1.preheader + %B.addr.1.lcssa = phi i32* [ %B.addr.06, %for.cond1.preheader ], [ %scevgep, %for.inc5.loopexit ] %inc6 = add nsw i64 %i.05, 1 - %cmp = icmp ult i64 %inc6, %n1 - br i1 %cmp, label %for.cond1.preheader, label %for.end7 + %exitcond7 = icmp ne i64 %inc6, %n1 + br i1 %exitcond7, label %for.cond1.preheader, label %for.end7.loopexit + +for.end7.loopexit: ; preds = %for.inc5 + br label %for.end7 -for.end7: ; preds = %for.inc5, %entry +for.end7: ; preds = %for.end7.loopexit, %entry ret void } diff --git a/test/Analysis/DependenceAnalysis/SymbolicSIV.ll b/test/Analysis/DependenceAnalysis/SymbolicSIV.ll index ee2343fa51e9..297096ce135d 100644 --- a/test/Analysis/DependenceAnalysis/SymbolicSIV.ll +++ b/test/Analysis/DependenceAnalysis/SymbolicSIV.ll @@ -5,18 +5,28 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-macosx10.6.0" -;; for (long int i = 0; i < n; i++) -;; A[2*i + n] = ... -;; ... = A[3*i + 3*n]; +;; for (long int i = 0; i < n; i++) { +;; A[2*i + n] = i; +;; *B++ = A[3*i + 3*n]; define void @symbolicsiv0(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %mul = shl nsw i64 %i.03, 1 %add = add i64 %mul, %n @@ -26,30 +36,42 @@ for.body: ; preds = %for.body, %entry %add3 = mul i64 %mul14, 3 %arrayidx4 = getelementptr inbounds i32* %A, i64 %add3 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit -for.end: ; preds = %for.body, %entry +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long int i = 0; i < n; i++) -;; A[2*i + 5*n] = ... -;; ... = A[3*i + 2*n]; +;; for (long int i = 0; i < n; i++) { +;; A[2*i + 5*n] = i; +;; *B++ = A[3*i + 2*n]; define void @symbolicsiv1(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %mul = shl nsw i64 %i.03, 1 %mul1 = mul i64 %n, 5 @@ -61,30 +83,42 @@ for.body: ; preds = %for.body, %entry %add4 = add i64 %mul2, %mul3 %arrayidx5 = getelementptr inbounds i32* %A, i64 %add4 %0 = load i32* %arrayidx5, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long int i = 0; i < n; i++) -;; A[2*i - n] = ... -;; ... = A[-i + 2*n]; +;; for (long int i = 0; i < n; i++) { +;; A[2*i - n] = i; +;; *B++ = A[-i + 2*n]; define void @symbolicsiv2(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %mul = shl nsw i64 %i.03, 1 %sub = sub i64 %mul, %n @@ -94,30 +128,42 @@ for.body: ; preds = %for.body, %entry %add = sub i64 %mul2, %i.03 %arrayidx3 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx3, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long int i = 0; i < n; i++) -;; A[-2*i + n + 1] = ... -;; ... = A[i - 2*n]; +;; for (long int i = 0; i < n; i++) { +;; A[-2*i + n + 1] = i; +;; *B++ = A[i - 2*n]; define void @symbolicsiv3(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, -2 %add = add i64 %mul, %n @@ -128,30 +174,42 @@ for.body: ; preds = %for.body, %entry %sub = sub i64 %i.03, %mul2 %arrayidx3 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx3, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit -for.end: ; preds = %for.body, %entry +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long int i = 0; i < n; i++) -;; A[-2*i + 3*n] = ... -;; ... = A[-i + n]; +;; for (long int i = 0; i < n; i++) { +;; A[-2*i + 3*n] = i; +;; *B++ = A[-i + n]; define void @symbolicsiv4(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, -2 %mul1 = mul i64 %n, 3 @@ -161,30 +219,42 @@ for.body: ; preds = %for.body, %entry %add2 = sub i64 %n, %i.03 %arrayidx3 = getelementptr inbounds i32* %A, i64 %add2 %0 = load i32* %arrayidx3, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit -for.end: ; preds = %for.body, %entry +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long int i = 0; i < n; i++) -;; A[-2*i - 2*n] = ... -;; ... = A[-i - n]; +;; for (long int i = 0; i < n; i++) { +;; A[-2*i - 2*n] = i; +;; *B++ = A[-i - n]; define void @symbolicsiv5(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %mul = mul nsw i64 %i.03, -2 %mul1 = shl i64 %n, 1 @@ -195,32 +265,44 @@ for.body: ; preds = %for.body, %entry %sub3 = sub i64 %sub2, %n %arrayidx4 = getelementptr inbounds i32* %A, i64 %sub3 %0 = load i32* %arrayidx4, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add nsw i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit -for.end: ; preds = %for.body, %entry +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry ret void } ;; why doesn't SCEV package understand that n >= 0? -;;void weaktest(int *A, int *B, long unsigned n) -;; for (long unsigned i = 0; i < n; i++) -;; A[i + n + 1] = ... -;; ... = A[-i]; +;; for (long unsigned i = 0; i < n; i++) { +;; A[i + n + 1] = i; +;; *B++ = A[-i]; define void @weaktest(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - flow [*|<] splitable! +; CHECK: da analyze - split level = 1, iteration = ((0 smax (-1 + (-1 * %n))) /u 2)! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %add = add i64 %i.03, %n %add1 = add i64 %add, 1 @@ -229,29 +311,36 @@ for.body: ; preds = %for.body, %entry %sub = sub i64 0, %i.03 %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - flow [*|<] splitable! -; CHECK: da analyze - split level = 1, iteration = ((0 smax (-1 + (-1 * %n))) /u 2)! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; void symbolicsiv6(int *A, int *B, long unsigned n, long unsigned N, long unsigned M) { -;; for (long int i = 0; i < n; i++) { -;; A[4*N*i + M] = i; -;; *B++ = A[4*N*i + 3*M + 1]; +;; for (long int i = 0; i < n; i++) { +;; A[4*N*i + M] = i; +;; *B++ = A[4*N*i + 3*M + 1]; define void @symbolicsiv6(i32* %A, i32* %B, i64 %n, i64 %N, i64 %M) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 br i1 %cmp1, label %for.end, label %for.body.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.body.preheader: ; preds = %entry br label %for.body @@ -272,7 +361,6 @@ for.body: ; preds = %for.body.preheader, %arrayidx7 = getelementptr inbounds i32* %A, i64 %add6 %0 = load i32* %arrayidx7, align 4 %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 -; CHECK: da analyze - none! store i32 %0, i32* %B.addr.02, align 4 %inc = add nsw i64 %i.03, 1 %exitcond = icmp ne i64 %inc, %n @@ -286,16 +374,22 @@ for.end: ; preds = %for.end.loopexit, % } -;; void symbolicsiv7(int *A, int *B, long unsigned n, long unsigned N, long unsigned M) { -;; for (long int i = 0; i < n; i++) { -;; A[2*N*i + M] = i; -;; *B++ = A[2*N*i - 3*M + 2]; +;; for (long int i = 0; i < n; i++) { +;; A[2*N*i + M] = i; +;; *B++ = A[2*N*i - 3*M + 2]; define void @symbolicsiv7(i32* %A, i32* %B, i64 %n, i64 %N, i64 %M) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 br i1 %cmp1, label %for.end, label %for.body.preheader +; CHECK: da analyze - none! +; CHECK: da analyze - flow [<>]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + for.body.preheader: ; preds = %entry br label %for.body @@ -316,7 +410,6 @@ for.body: ; preds = %for.body.preheader, %arrayidx6 = getelementptr inbounds i32* %A, i64 %add5 %1 = load i32* %arrayidx6, align 4 %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 -; CHECK: da analyze - flow [<>]! store i32 %1, i32* %B.addr.02, align 4 %inc = add nsw i64 %i.03, 1 %exitcond = icmp ne i64 %inc, %n diff --git a/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll b/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll index 343e8f49bf9e..8b2e43f3d868 100644 --- a/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll +++ b/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll @@ -5,18 +5,28 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-macosx10.6.0" -;; for (long unsigned i = 0; i < n; i++) -;; A[1 + n*i] = ... -;; ... = A[1 - n*i]; +;; for (long unsigned i = 0; i < n; i++) { +;; A[1 + n*i] = i; +;; *B++ = A[1 - n*i]; define void @weakcrossing0(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body.preheader: ; preds = %entry + br label %for.body + +; CHECK: da analyze - none! +; CHECK: da analyze - flow [0|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %mul = mul i64 %i.03, %n %add = add i64 %mul, 1 @@ -26,30 +36,43 @@ for.body: ; preds = %for.body, %entry %sub = sub i64 1, %mul1 %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - flow [0|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long unsigned i = 0; i < n; i++) -;; A[n + i] = ... -;; ... = A[1 + n - i]; +;; for (long unsigned i = 0; i < n; i++) { +;; A[n + i] = i; +;; *B++ = A[1 + n - i]; define void @weakcrossing1(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - flow [<>] splitable! +; CHECK: da analyze - split level = 1, iteration = 0! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %add = add i64 %i.03, %n %arrayidx = getelementptr inbounds i32* %A, i64 %add @@ -58,28 +81,36 @@ for.body: ; preds = %for.body, %entry %sub = sub i64 %add1, %i.03 %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - flow [<>] splitable! -; CHECK: da analyze - split level = 1, iteration = 0! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long unsigned i = 0; i < 3; i++) -;; A[i] = ... -;; ... = A[6 - i]; +;; for (long unsigned i = 0; i < 3; i++) { +;; A[i] = i; +;; *B++ = A[6 - i]; define void @weakcrossing2(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -88,27 +119,33 @@ for.body: ; preds = %for.body, %entry %sub = sub i64 6, %i.02 %arrayidx1 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 3 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 3 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 4; i++) -;; A[i] = ... -;; ... = A[6 - i]; +;; for (long unsigned i = 0; i < 4; i++) { +;; A[i] = i; +;; *B++ = A[6 - i]; define void @weakcrossing3(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [0|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -117,27 +154,33 @@ for.body: ; preds = %for.body, %entry %sub = sub i64 6, %i.02 %arrayidx1 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [0|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 4 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 4 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 10; i++) -;; A[i] = ... -;; ... = A[-6 - i]; +;; for (long unsigned i = 0; i < 10; i++) { +;; A[i] = i; +;; *B++ = A[-6 - i]; define void @weakcrossing4(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -146,30 +189,39 @@ for.body: ; preds = %for.body, %entry %sub = sub i64 -6, %i.02 %arrayidx1 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 10 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 10 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < n; i++) -;; A[3*i] = ... -;; ... = A[5 - 3*i]; +;; for (long unsigned i = 0; i < n; i++) { +;; A[3*i] = i; +;; *B++ = A[5 - 3*i]; define void @weakcrossing5(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %mul = mul i64 %i.03, 3 %arrayidx = getelementptr inbounds i32* %A, i64 %mul @@ -178,27 +230,37 @@ for.body: ; preds = %for.body, %entry %sub = add i64 %0, 5 %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub %1 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %1, i32* %B.addr.02, align 4 %inc = add i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit -for.end: ; preds = %for.body, %entry +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long unsigned i = 0; i < 4; i++) -;; A[i] = ... -;; ... = A[5 - i]; +;; for (long unsigned i = 0; i < 4; i++) { +;; A[i] = i; +;; *B++ = A[5 - i]; define void @weakcrossing6(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [<>] splitable! +; CHECK: da analyze - split level = 1, iteration = 2! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -207,13 +269,11 @@ for.body: ; preds = %for.body, %entry %sub = sub i64 5, %i.02 %arrayidx1 = getelementptr inbounds i32* %A, i64 %sub %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [<>] splitable! -; CHECK: da analyze - split level = 1, iteration = 2! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 4 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 4 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void diff --git a/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll b/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll index a59871602b6c..bc85e6c8b690 100644 --- a/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll +++ b/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll @@ -5,15 +5,22 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-macosx10.6.0" -;; for (long unsigned i = 0; i < 30; i++) -;; A[2*i + 10] = ... -;; ... = A[10]; +;; for (long unsigned i = 0; i < 30; i++) { +;; A[2*i + 10] = i; +;; *B++ = A[10]; define void @weakzerodst0(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [p<=|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -23,30 +30,39 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 10 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [p<=|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 30 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 30 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < n; i++) -;; A[n*i + 10] = ... -;; ... = A[10]; +;; for (long unsigned i = 0; i < n; i++) { +;; A[n*i + 10] = i; +;; *B++ = A[10]; define void @weakzerodst1(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - flow [p<=|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %mul = mul i64 %i.03, %n %add = add i64 %mul, 10 @@ -54,27 +70,36 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 10 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [p<=|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long unsigned i = 0; i < 5; i++) -;; A[2*i] = ... -;; ... = A[10]; +;; for (long unsigned i = 0; i < 5; i++) { +;; A[2*i] = i; +;; *B++ = A[10]; define void @weakzerodst2(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -83,27 +108,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 10 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 5 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 5 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 6; i++) -;; A[2*i] = ... -;; ... = A[10]; +;; for (long unsigned i = 0; i < 6; i++) { +;; A[2*i] = i; +;; *B++ = A[10]; define void @weakzerodst3(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [=>p|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -112,27 +143,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 10 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [=>p|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 6 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 6 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 7; i++) -;; A[2*i] = ... -;; ... = A[10]; +;; for (long unsigned i = 0; i < 7; i++) { +;; A[2*i] = i; +;; *B++ = A[10]; define void @weakzerodst4(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - flow [*|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -141,27 +178,33 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 10 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [*|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 7 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 7 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 7; i++) -;; A[2*i] = ... -;; ... = A[-10]; +;; for (long unsigned i = 0; i < 7; i++) { +;; A[2*i] = i; +;; *B++ = A[-10]; define void @weakzerodst5(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -170,43 +213,54 @@ for.body: ; preds = %for.body, %entry store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 -10 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 7 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 7 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < n; i++) -;; A[3*i] = ... -;; ... = A[10]; +;; for (long unsigned i = 0; i < n; i++) { +;; A[3*i] = i; +;; *B++ = A[10]; define void @weakzerodst6(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - consistent input [S]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %mul = mul i64 %i.03, 3 %arrayidx = getelementptr inbounds i32* %A, i64 %mul store i32 %conv, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32* %A, i64 10 %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } diff --git a/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll b/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll index fd4f46269546..2b3b2d00ecac 100644 --- a/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll +++ b/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll @@ -5,15 +5,22 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-macosx10.6.0" -;; for (long unsigned i = 0; i < 30; i++) -;; A[10] = ... -;; ... = A[2*i + 10]; +;; for (long unsigned i = 0; i < 30; i++) { +;; A[10] = i; +;; *B++ = A[2*i + 10]; define void @weakzerosrc0(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - consistent output [S]! +; CHECK: da analyze - flow [p<=|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -23,30 +30,39 @@ for.body: ; preds = %for.body, %entry %add = add i64 %mul, 10 %arrayidx1 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [p<=|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 30 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 30 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < n; i++) -;; A[10] = ... -;; ... = A[n*i + 10]; +;; for (long unsigned i = 0; i < n; i++) { +;; A[10] = i; +;; *B++ = A[n*i + 10]; define void @weakzerosrc1(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - consistent output [S]! +; CHECK: da analyze - flow [p<=|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %arrayidx = getelementptr inbounds i32* %A, i64 10 store i32 %conv, i32* %arrayidx, align 4 @@ -54,27 +70,36 @@ for.body: ; preds = %for.body, %entry %add = add i64 %mul, 10 %arrayidx1 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [p<=|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } -;; for (long unsigned i = 0; i < 5; i++) -;; A[10] = ... -;; ... = A[2*i]; +;; for (long unsigned i = 0; i < 5; i++) { +;; A[10] = i; +;; *B++ = A[2*i]; define void @weakzerosrc2(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - consistent output [S]! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -83,27 +108,33 @@ for.body: ; preds = %for.body, %entry %mul = shl i64 %i.02, 1 %arrayidx1 = getelementptr inbounds i32* %A, i64 %mul %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 5 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 5 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 6; i++) -;; A[10] = ... -;; ... = A[2*i]; +;; for (long unsigned i = 0; i < 6; i++) { +;; A[10] = i; +;; *B++ = A[2*i]; define void @weakzerosrc3(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - consistent output [S]! +; CHECK: da analyze - flow [=>p|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -112,27 +143,33 @@ for.body: ; preds = %for.body, %entry %mul = shl i64 %i.02, 1 %arrayidx1 = getelementptr inbounds i32* %A, i64 %mul %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [=>p|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 6 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 6 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 7; i++) -;; A[10] = ... -;; ... = A[2*i]; +;; for (long unsigned i = 0; i < 7; i++) { +;; A[10] = i; +;; *B++ = A[2*i]; define void @weakzerosrc4(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - consistent output [S]! +; CHECK: da analyze - flow [*|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -141,27 +178,33 @@ for.body: ; preds = %for.body, %entry %mul = shl i64 %i.02, 1 %arrayidx1 = getelementptr inbounds i32* %A, i64 %mul %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow [*|<]! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 7 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 7 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < 7; i++) -;; A[-10] = ... -;; ... = A[2*i]; +;; for (long unsigned i = 0; i < 7; i++) { +;; A[-10] = i; +;; *B++ = A[2*i]; define void @weakzerosrc5(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: br label %for.body -for.body: ; preds = %for.body, %entry +; CHECK: da analyze - consistent output [S]! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body: ; preds = %entry, %for.body %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ] %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ] %conv = trunc i64 %i.02 to i32 @@ -170,43 +213,54 @@ for.body: ; preds = %for.body, %entry %mul = shl i64 %i.02, 1 %arrayidx1 = getelementptr inbounds i32* %A, i64 %mul %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1 store i32 %0, i32* %B.addr.01, align 4 %inc = add i64 %i.02, 1 - %cmp = icmp ult i64 %inc, 7 - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, 7 + br i1 %exitcond, label %for.body, label %for.end for.end: ; preds = %for.body ret void } -;; for (long unsigned i = 0; i < n; i++) -;; A[10] = ... -;; ... = A[3*i]; +;; for (long unsigned i = 0; i < n; i++) { +;; A[10] = i; +;; *B++ = A[3*i]; define void @weakzerosrc6(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %cmp1 = icmp eq i64 %n, 0 - br i1 %cmp1, label %for.end, label %for.body + br i1 %cmp1, label %for.end, label %for.body.preheader + +; CHECK: da analyze - consistent output [S]! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + +for.body.preheader: ; preds = %entry + br label %for.body -for.body: ; preds = %for.body, %entry - %i.03 = phi i64 [ %inc, %for.body ], [ 0, %entry ] - %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %entry ] +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ] %conv = trunc i64 %i.03 to i32 %arrayidx = getelementptr inbounds i32* %A, i64 10 store i32 %conv, i32* %arrayidx, align 4 %mul = mul i64 %i.03, 3 %arrayidx1 = getelementptr inbounds i32* %A, i64 %mul %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1 store i32 %0, i32* %B.addr.02, align 4 %inc = add i64 %i.03, 1 - %cmp = icmp ult i64 %inc, %n - br i1 %cmp, label %for.body, label %for.end + %exitcond = icmp ne i64 %inc, %n + br i1 %exitcond, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end -for.end: ; preds = %for.body, %entry +for.end: ; preds = %for.end.loopexit, %entry ret void } diff --git a/test/Analysis/DependenceAnalysis/ZIV.ll b/test/Analysis/DependenceAnalysis/ZIV.ll index 42b2389df268..5463c63ba3fb 100644 --- a/test/Analysis/DependenceAnalysis/ZIV.ll +++ b/test/Analysis/DependenceAnalysis/ZIV.ll @@ -5,49 +5,70 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-macosx10.6.0" -;; A[n + 1] = ... -;; ... = A[1 + n]; +;; A[n + 1] = 0; +;; *B = A[1 + n]; define void @z0(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %add = add i64 %n, 1 %arrayidx = getelementptr inbounds i32* %A, i64 %add store i32 0, i32* %arrayidx, align 4 + +; CHECK: da analyze - none! +; CHECK: da analyze - consistent flow [|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + %add1 = add i64 %n, 1 %arrayidx2 = getelementptr inbounds i32* %A, i64 %add1 %0 = load i32* %arrayidx2, align 4 -; CHECK: da analyze - consistent flow! store i32 %0, i32* %B, align 4 ret void } -;; A[n] = ... -;; ... = A[n + 1]; +;; A[n] = 0; +;; *B = A[n + 1]; define void @z1(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp { entry: %arrayidx = getelementptr inbounds i32* %A, i64 %n store i32 0, i32* %arrayidx, align 4 + +; CHECK: da analyze - none! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + %add = add i64 %n, 1 %arrayidx1 = getelementptr inbounds i32* %A, i64 %add %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - none! store i32 %0, i32* %B, align 4 ret void } -;; A[n] = ... -;; ... = A[m]; +;; A[n] = 0; +;; *B = A[m]; define void @z2(i32* %A, i32* %B, i64 %n, i64 %m) nounwind uwtable ssp { entry: %arrayidx = getelementptr inbounds i32* %A, i64 %n store i32 0, i32* %arrayidx, align 4 + +; CHECK: da analyze - none! +; CHECK: da analyze - flow [|<]! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! +; CHECK: da analyze - confused! +; CHECK: da analyze - none! + %arrayidx1 = getelementptr inbounds i32* %A, i64 %m %0 = load i32* %arrayidx1, align 4 -; CHECK: da analyze - flow! store i32 %0, i32* %B, align 4 ret void } diff --git a/test/Analysis/Dominators/invoke.ll b/test/Analysis/Dominators/invoke.ll index f935750c987e..da0b2461656c 100644 --- a/test/Analysis/Dominators/invoke.ll +++ b/test/Analysis/Dominators/invoke.ll @@ -1,4 +1,4 @@ -; RUN: opt -verify -disable-output %s +; RUN: opt -verify -disable-output < %s ; This tests that we handle unreachable blocks correctly define void @f() { diff --git a/test/Analysis/Profiling/lit.local.cfg b/test/Analysis/Profiling/lit.local.cfg index 19eebc0ac7ac..444b7dc27410 100644 --- a/test/Analysis/Profiling/lit.local.cfg +++ b/test/Analysis/Profiling/lit.local.cfg @@ -1 +1,16 @@ config.suffixes = ['.ll', '.c', '.cpp'] + +def getRoot(config): + if not config.parent: + return config + return getRoot(config.parent) + +root = getRoot(config) + +# Most profiling tests rely on a JIT being present to gather their data; AArch64 +# doesn't have any JIT at present so they will fail when run there. +if root.host_arch in ['AArch64']: + config.unsupported = True + +if 'hexagon' in root.target_triple: + config.unsupported = True diff --git a/test/Analysis/RegionInfo/20100809_bb_not_in_domtree.ll b/test/Analysis/RegionInfo/20100809_bb_not_in_domtree.ll index 218b4375f70c..0dfa0bf9cd8d 100644 --- a/test/Analysis/RegionInfo/20100809_bb_not_in_domtree.ll +++ b/test/Analysis/RegionInfo/20100809_bb_not_in_domtree.ll @@ -1,4 +1,4 @@ -; RUN: opt -regions %s +; RUN: opt -regions < %s define i32 @main() nounwind { entry: br label %for.cond diff --git a/test/Analysis/RegionInfo/block_sort.ll b/test/Analysis/RegionInfo/block_sort.ll index ac77ab36e6f5..d7ef79cf6b55 100644 --- a/test/Analysis/RegionInfo/block_sort.ll +++ b/test/Analysis/RegionInfo/block_sort.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats -analyze < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/cond_loop.ll b/test/Analysis/RegionInfo/cond_loop.ll index 1145ffdba039..0da4e5dca3d3 100644 --- a/test/Analysis/RegionInfo/cond_loop.ll +++ b/test/Analysis/RegionInfo/cond_loop.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/condition_complicated.ll b/test/Analysis/RegionInfo/condition_complicated.ll index 6b398800db9c..53f13c10eaf3 100644 --- a/test/Analysis/RegionInfo/condition_complicated.ll +++ b/test/Analysis/RegionInfo/condition_complicated.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/condition_complicated_2.ll b/test/Analysis/RegionInfo/condition_complicated_2.ll index f551108d6083..fd04afc20dca 100644 --- a/test/Analysis/RegionInfo/condition_complicated_2.ll +++ b/test/Analysis/RegionInfo/condition_complicated_2.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/condition_forward_edge.ll b/test/Analysis/RegionInfo/condition_forward_edge.ll index 5e4d9d2f8b23..88c45c2e6efd 100644 --- a/test/Analysis/RegionInfo/condition_forward_edge.ll +++ b/test/Analysis/RegionInfo/condition_forward_edge.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/condition_same_exit.ll b/test/Analysis/RegionInfo/condition_same_exit.ll index e48413a4c2dd..bfb0df84b44d 100644 --- a/test/Analysis/RegionInfo/condition_same_exit.ll +++ b/test/Analysis/RegionInfo/condition_same_exit.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/condition_simple.ll b/test/Analysis/RegionInfo/condition_simple.ll index 00d9ed24e17d..3f93a6ecd358 100644 --- a/test/Analysis/RegionInfo/condition_simple.ll +++ b/test/Analysis/RegionInfo/condition_simple.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/exit_in_condition.ll b/test/Analysis/RegionInfo/exit_in_condition.ll index b84abecc1649..ac409ec1bb25 100644 --- a/test/Analysis/RegionInfo/exit_in_condition.ll +++ b/test/Analysis/RegionInfo/exit_in_condition.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/infinite_loop.ll b/test/Analysis/RegionInfo/infinite_loop.ll index 8e588286a58a..61abef8ff7a9 100644 --- a/test/Analysis/RegionInfo/infinite_loop.ll +++ b/test/Analysis/RegionInfo/infinite_loop.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s diff --git a/test/Analysis/RegionInfo/infinite_loop_2.ll b/test/Analysis/RegionInfo/infinite_loop_2.ll index a8227e340c5e..56e83cfdebb9 100644 --- a/test/Analysis/RegionInfo/infinite_loop_2.ll +++ b/test/Analysis/RegionInfo/infinite_loop_2.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/infinite_loop_3.ll b/test/Analysis/RegionInfo/infinite_loop_3.ll index b09c9c1e5919..4538f0f78587 100644 --- a/test/Analysis/RegionInfo/infinite_loop_3.ll +++ b/test/Analysis/RegionInfo/infinite_loop_3.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s diff --git a/test/Analysis/RegionInfo/infinite_loop_4.ll b/test/Analysis/RegionInfo/infinite_loop_4.ll index 681c305ce971..4ac9068f0dd8 100644 --- a/test/Analysis/RegionInfo/infinite_loop_4.ll +++ b/test/Analysis/RegionInfo/infinite_loop_4.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/loop_with_condition.ll b/test/Analysis/RegionInfo/loop_with_condition.ll index 08d2ba8e35a9..4c1c8654ca4f 100644 --- a/test/Analysis/RegionInfo/loop_with_condition.ll +++ b/test/Analysis/RegionInfo/loop_with_condition.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s diff --git a/test/Analysis/RegionInfo/loops_1.ll b/test/Analysis/RegionInfo/loops_1.ll index 6449949df843..9efe619ad9d7 100644 --- a/test/Analysis/RegionInfo/loops_1.ll +++ b/test/Analysis/RegionInfo/loops_1.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/loops_2.ll b/test/Analysis/RegionInfo/loops_2.ll index dc4a1adffbac..ca7eca75affd 100644 --- a/test/Analysis/RegionInfo/loops_2.ll +++ b/test/Analysis/RegionInfo/loops_2.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/mix_1.ll b/test/Analysis/RegionInfo/mix_1.ll index 1474e033e574..55001c7f435c 100644 --- a/test/Analysis/RegionInfo/mix_1.ll +++ b/test/Analysis/RegionInfo/mix_1.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s diff --git a/test/Analysis/RegionInfo/nested_loops.ll b/test/Analysis/RegionInfo/nested_loops.ll index a3707a19872f..3e73b3a328f6 100644 --- a/test/Analysis/RegionInfo/nested_loops.ll +++ b/test/Analysis/RegionInfo/nested_loops.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s diff --git a/test/Analysis/RegionInfo/next.ll b/test/Analysis/RegionInfo/next.ll index 890b4f23001e..b22bbcc2b6d5 100644 --- a/test/Analysis/RegionInfo/next.ll +++ b/test/Analysis/RegionInfo/next.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/paper.ll b/test/Analysis/RegionInfo/paper.ll index 96c87e0559b4..0398d2baa225 100644 --- a/test/Analysis/RegionInfo/paper.ll +++ b/test/Analysis/RegionInfo/paper.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/RegionInfo/two_loops_same_header.ll b/test/Analysis/RegionInfo/two_loops_same_header.ll index e75661e8905b..25713420a3b7 100644 --- a/test/Analysis/RegionInfo/two_loops_same_header.ll +++ b/test/Analysis/RegionInfo/two_loops_same_header.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: opt -regions -analyze < %s | FileCheck %s ; RUN: opt -regions -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s ; RUN: opt -regions -print-region-style=bb -analyze < %s 2>&1 | FileCheck -check-prefix=BBIT %s diff --git a/test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll b/test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll index aba0ce74678f..5a0239810418 100644 --- a/test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll +++ b/test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll @@ -1,8 +1,10 @@ -; RUN: opt -indvars -scalar-evolution -analyze %s +; RUN: opt -indvars -scalar-evolution -analyze < %s | FileCheck %s ; This test checks if the SCEV analysis is printed out at all. ; It failed once as the RequiredTransitive option was not implemented ; correctly. +; CHECK: Classifying expressions for: @main + define i32 @main() nounwind { entry: br label %for.cond diff --git a/test/Analysis/ScalarEvolution/2011-03-09-ExactNoMaxBECount.ll b/test/Analysis/ScalarEvolution/2011-03-09-ExactNoMaxBECount.ll index 9f17e27577c2..49e944dcd266 100644 --- a/test/Analysis/ScalarEvolution/2011-03-09-ExactNoMaxBECount.ll +++ b/test/Analysis/ScalarEvolution/2011-03-09-ExactNoMaxBECount.ll @@ -1,4 +1,4 @@ -; RUN: opt -indvars %s +; RUN: opt -indvars < %s ; PR9424: Attempt to use a SCEVCouldNotCompute object! ; The inner loop computes the Step and Start of the outer loop. ; Call that Vexit. The outer End value is max(2,Vexit), because diff --git a/test/Analysis/ScalarEvolution/fold.ll b/test/Analysis/ScalarEvolution/fold.ll index 4e2adf187e8b..57006dd9bb42 100644 --- a/test/Analysis/ScalarEvolution/fold.ll +++ b/test/Analysis/ScalarEvolution/fold.ll @@ -1,4 +1,4 @@ -; RUN: opt -analyze -scalar-evolution %s -S | FileCheck %s +; RUN: opt -analyze -scalar-evolution -S < %s | FileCheck %s define i16 @test1(i8 %x) { %A = zext i8 %x to i12 diff --git a/test/Analysis/ScalarEvolution/scev-invalid.ll b/test/Analysis/ScalarEvolution/scev-invalid.ll new file mode 100644 index 000000000000..aac0d319ae84 --- /dev/null +++ b/test/Analysis/ScalarEvolution/scev-invalid.ll @@ -0,0 +1,34 @@ +; RUN: opt < %s -S -indvars -loop-unroll | FileCheck %s +; +; PR15570: SEGV: SCEV back-edge info invalid after dead code removal. +; +; Indvars creates a SCEV expression for the loop's back edge taken +; count, then determines that the comparison is always true and +; removes it. +; +; When loop-unroll asks for the expression, it contains a NULL +; SCEVUnknkown (as a CallbackVH). +; +; forgetMemoizedResults should invalidate the backedge taken count expression. + +; CHECK: @test +; CHECK-NOT: phi +; CHECK-NOT: icmp +; CHECK: ret void +define void @test() { +entry: + %xor1 = xor i32 0, 1 + br label %b17 + +b17: + br i1 undef, label %b22, label %b18 + +b18: + %phi1 = phi i32 [ %add1, %b18 ], [ %xor1, %b17 ] + %add1 = add nsw i32 %phi1, -1 + %cmp1 = icmp sgt i32 %add1, 0 + br i1 %cmp1, label %b18, label %b22 + +b22: + ret void +} diff --git a/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll b/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll index 1ac59278e7ea..c6cc26a24106 100644 --- a/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll +++ b/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll @@ -9,13 +9,13 @@ ; invalid, as it's possible that this only happens after optimization on a ; code path which isn't ever executed. -; CHECK: define void @test0_yes(i32* nocapture %p) nounwind readnone { +; CHECK: define void @test0_yes(i32* nocapture %p) #0 { define void @test0_yes(i32* %p) nounwind { store i32 0, i32* %p, !tbaa !1 ret void } -; CHECK: define void @test0_no(i32* nocapture %p) nounwind { +; CHECK: define void @test0_no(i32* nocapture %p) #1 { define void @test0_no(i32* %p) nounwind { store i32 0, i32* %p, !tbaa !2 ret void @@ -24,13 +24,13 @@ define void @test0_no(i32* %p) nounwind { ; Add the readonly attribute, since there's just a call to a function which ; TBAA says doesn't modify any memory. -; CHECK: define void @test1_yes(i32* nocapture %p) nounwind readonly { +; CHECK: define void @test1_yes(i32* nocapture %p) #2 { define void @test1_yes(i32* %p) nounwind { call void @callee(i32* %p), !tbaa !1 ret void } -; CHECK: define void @test1_no(i32* %p) nounwind { +; CHECK: define void @test1_no(i32* %p) #1 { define void @test1_no(i32* %p) nounwind { call void @callee(i32* %p), !tbaa !2 ret void @@ -43,13 +43,13 @@ define void @test1_no(i32* %p) nounwind { ; This is unusual, since the function is memcpy, but as above, this ; isn't necessarily invalid. -; CHECK: define void @test2_yes(i8* nocapture %p, i8* nocapture %q, i64 %n) nounwind readnone { +; CHECK: define void @test2_yes(i8* nocapture %p, i8* nocapture %q, i64 %n) #0 { define void @test2_yes(i8* %p, i8* %q, i64 %n) nounwind { call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i32 1, i1 false), !tbaa !1 ret void } -; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture %q, i64 %n) nounwind { +; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture %q, i64 %n) #1 { define void @test2_no(i8* %p, i8* %q, i64 %n) nounwind { call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i32 1, i1 false), !tbaa !2 ret void @@ -57,13 +57,13 @@ define void @test2_no(i8* %p, i8* %q, i64 %n) nounwind { ; Similar to the others, va_arg only accesses memory through its operand. -; CHECK: define i32 @test3_yes(i8* nocapture %p) nounwind readnone { +; CHECK: define i32 @test3_yes(i8* nocapture %p) #0 { define i32 @test3_yes(i8* %p) nounwind { %t = va_arg i8* %p, i32, !tbaa !1 ret i32 %t } -; CHECK: define i32 @test3_no(i8* nocapture %p) nounwind { +; CHECK: define i32 @test3_no(i8* nocapture %p) #1 { define i32 @test3_no(i8* %p) nounwind { %t = va_arg i8* %p, i32, !tbaa !2 ret i32 %t @@ -72,6 +72,10 @@ define i32 @test3_no(i8* %p) nounwind { declare void @callee(i32* %p) nounwind declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1) nounwind +; CHECK: attributes #0 = { nounwind readnone } +; CHECK: attributes #1 = { nounwind } +; CHECK: attributes #2 = { nounwind readonly } + ; Root note. !0 = metadata !{ } diff --git a/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll b/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll index 8f080e2108bd..6f1c22da3ac5 100644 --- a/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll +++ b/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll @@ -7,7 +7,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- ; CHECK: define <8 x i16> @test0(i8* %p, i8* %q, <8 x i16> %y) { ; CHECK-NEXT: entry: -; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind +; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) [[NUW:#[0-9]+]] ; CHECK-NEXT: call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16) ; CHECK-NEXT: %c = add <8 x i16> %a, %a define <8 x i16> @test0(i8* %p, i8* %q, <8 x i16> %y) { @@ -22,6 +22,9 @@ entry: declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind +; CHECK: attributes #0 = { nounwind readonly } +; CHECK: attributes [[NUW]] = { nounwind } + !0 = metadata !{metadata !"tbaa root", null} !1 = metadata !{metadata !"A", metadata !0} !2 = metadata !{metadata !"B", metadata !0} diff --git a/test/Analysis/TypeBasedAliasAnalysis/placement-tbaa.ll b/test/Analysis/TypeBasedAliasAnalysis/placement-tbaa.ll new file mode 100644 index 000000000000..f1edb4482cf1 --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/placement-tbaa.ll @@ -0,0 +1,104 @@ +; RUN: opt < %s -tbaa -basicaa -aa-eval -evaluate-tbaa -print-no-aliases -print-may-aliases -disable-output 2>&1 | FileCheck %s + +; Generated with "clang -cc1 -disable-llvm-optzns -O1 -emit-llvm" +; #include +; struct Foo { long i; }; +; struct Bar { void *p; }; +; long foo(int n) { +; Foo *f = new Foo; +; f->i = 1; +; for (int i=0; ip = 0; +; f = new (f) Foo; +; f->i = i; +; } +; return f->i; +; } + +; Basic AA says MayAlias, TBAA says NoAlias +; CHECK: MayAlias: i64* %i5, i8** %p +; CHECK: NoAlias: store i64 %conv, i64* %i5, align 8, !tbaa !4 <-> store i8* null, i8** %p, align 8, !tbaa !3 + +%struct.Foo = type { i64 } +%struct.Bar = type { i8* } + +define i64 @_Z3fooi(i32 %n) #0 { +entry: + %n.addr = alloca i32, align 4 + %f = alloca %struct.Foo*, align 8 + %i1 = alloca i32, align 4 + %b = alloca %struct.Bar*, align 8 + store i32 %n, i32* %n.addr, align 4, !tbaa !0 + %call = call noalias i8* @_Znwm(i64 8) + %0 = bitcast i8* %call to %struct.Foo* + store %struct.Foo* %0, %struct.Foo** %f, align 8, !tbaa !3 + %1 = load %struct.Foo** %f, align 8, !tbaa !3 + %i = getelementptr inbounds %struct.Foo* %1, i32 0, i32 0 + store i64 1, i64* %i, align 8, !tbaa !4 + store i32 0, i32* %i1, align 4, !tbaa !0 + br label %for.cond + +for.cond: + %2 = load i32* %i1, align 4, !tbaa !0 + %3 = load i32* %n.addr, align 4, !tbaa !0 + %cmp = icmp slt i32 %2, %3 + br i1 %cmp, label %for.body, label %for.end + +for.body: + %4 = load %struct.Foo** %f, align 8, !tbaa !3 + %5 = bitcast %struct.Foo* %4 to i8* + %new.isnull = icmp eq i8* %5, null + br i1 %new.isnull, label %new.cont, label %new.notnull + +new.notnull: + %6 = bitcast i8* %5 to %struct.Bar* + br label %new.cont + +new.cont: + %7 = phi %struct.Bar* [ %6, %new.notnull ], [ null, %for.body ] + store %struct.Bar* %7, %struct.Bar** %b, align 8, !tbaa !3 + %8 = load %struct.Bar** %b, align 8, !tbaa !3 + %p = getelementptr inbounds %struct.Bar* %8, i32 0, i32 0 + store i8* null, i8** %p, align 8, !tbaa !3 + %9 = load %struct.Foo** %f, align 8, !tbaa !3 + %10 = bitcast %struct.Foo* %9 to i8* + %new.isnull2 = icmp eq i8* %10, null + br i1 %new.isnull2, label %new.cont4, label %new.notnull3 + +new.notnull3: + %11 = bitcast i8* %10 to %struct.Foo* + br label %new.cont4 + +new.cont4: + %12 = phi %struct.Foo* [ %11, %new.notnull3 ], [ null, %new.cont ] + store %struct.Foo* %12, %struct.Foo** %f, align 8, !tbaa !3 + %13 = load i32* %i1, align 4, !tbaa !0 + %conv = sext i32 %13 to i64 + %14 = load %struct.Foo** %f, align 8, !tbaa !3 + %i5 = getelementptr inbounds %struct.Foo* %14, i32 0, i32 0 + store i64 %conv, i64* %i5, align 8, !tbaa !4 + br label %for.inc + +for.inc: + %15 = load i32* %i1, align 4, !tbaa !0 + %inc = add nsw i32 %15, 1 + store i32 %inc, i32* %i1, align 4, !tbaa !0 + br label %for.cond + +for.end: + %16 = load %struct.Foo** %f, align 8, !tbaa !3 + %i6 = getelementptr inbounds %struct.Foo* %16, i32 0, i32 0 + %17 = load i64* %i6, align 8, !tbaa !4 + ret i64 %17 +} + +declare noalias i8* @_Znwm(i64) + +attributes #0 = { nounwind } + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!3 = metadata !{metadata !"any pointer", metadata !1} +!4 = metadata !{metadata !"long", metadata !1} diff --git a/test/Assembler/2008-09-02-FunctionNotes.ll b/test/Assembler/2008-09-02-FunctionNotes.ll index 761c91e864c4..11a0411ef79f 100644 --- a/test/Assembler/2008-09-02-FunctionNotes.ll +++ b/test/Assembler/2008-09-02-FunctionNotes.ll @@ -1,14 +1,21 @@ ; Test function attributes -; RUN: llvm-as < %s | llvm-dis | grep inline | count 2 +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; CHECK: define void @fn1() #0 define void @fn1() alwaysinline { ret void } +; CHECK: define void @fn2() #1 define void @fn2() noinline { ret void } +; CHECK: define void @fn3() +; CHECK-NOT: define void @fn3() #{{.*}} define void @fn3() { ret void } + +; CHECK: attributes #0 = { alwaysinline } +; CHECK: attributes #1 = { noinline } diff --git a/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll b/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll index b2256b10a8da..df70149a33f6 100644 --- a/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll +++ b/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll @@ -22,4 +22,11 @@ define i32 @main() nounwind readonly { declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone -!0 = metadata !{i32 459008, metadata !0, metadata !0, metadata !0, i32 38, metadata !0} ; [ DW_TAG_auto_variable ] +!7 = metadata !{metadata !1} +!6 = metadata !{i32 786449, i32 0, i32 12, metadata !"/d/j/debug-test.c", metadata !"/Volumes/Data/b", metadata !"clang version 3.0 (trunk 131941)", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !7, null, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786688, metadata !1, metadata !"c", metadata !2, i32 2, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 ()* @main, null, null, null, i32 1} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !"/d/j/debug-test.c", metadata !"/Volumes/Data/b", metadata !0} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 786468, metadata !6, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/Assembler/ConstantExprNoFold.ll b/test/Assembler/ConstantExprNoFold.ll new file mode 100644 index 000000000000..83e8909b5ebd --- /dev/null +++ b/test/Assembler/ConstantExprNoFold.ll @@ -0,0 +1,23 @@ +; This test checks to make sure that constant exprs don't fold in some simple +; situations + +; RUN: llvm-as < %s | llvm-dis | FileCheck %s + +; Even give it a datalayout, to tempt folding as much as possible. +target datalayout = "p:32:32" + +@A = global i64 0 +@B = global i64 0 + +; Don't fold this. @A might really be allocated next to @B, in which case the +; icmp should return true. It's not valid to *dereference* in @B from a pointer +; based on @A, but icmp isn't a dereference. + +; CHECK: @C = global i1 icmp eq (i64* getelementptr inbounds (i64* @A, i64 1), i64* @B) +@C = global i1 icmp eq (i64* getelementptr inbounds (i64* @A, i64 1), i64* @B) + +; Don't fold this completely away either. In theory this could be simplified +; to only use a gep on one side of the icmp though. + +; CHECK: @D = global i1 icmp eq (i64* getelementptr inbounds (i64* @A, i64 1), i64* getelementptr inbounds (i64* @B, i64 2)) +@D = global i1 icmp eq (i64* getelementptr inbounds (i64* @A, i64 1), i64* getelementptr inbounds (i64* @B, i64 2)) diff --git a/test/Assembler/externally-initialized.ll b/test/Assembler/externally-initialized.ll new file mode 100644 index 000000000000..4be6e629a1d0 --- /dev/null +++ b/test/Assembler/externally-initialized.ll @@ -0,0 +1,5 @@ +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s + +; CHECK: @G = externally_initialized global i32 0 + +@G = externally_initialized global i32 0 diff --git a/test/Assembler/fast-math-flags.ll b/test/Assembler/fast-math-flags.ll new file mode 100644 index 000000000000..3a116c507f48 --- /dev/null +++ b/test/Assembler/fast-math-flags.ll @@ -0,0 +1,142 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: opt -S < %s | FileCheck %s + +@addr = external global i64 +@select = external global i1 +@vec = external global <3 x float> +@arr = external global [3 x float] + +define float @none(float %x, float %y) { +entry: +; CHECK: %vec = load <3 x float>* @vec + %vec = load <3 x float>* @vec +; CHECK: %select = load i1* @select + %select = load i1* @select +; CHECK: %arr = load [3 x float]* @arr + %arr = load [3 x float]* @arr + +; CHECK: %a = fadd float %x, %y + %a = fadd float %x, %y +; CHECK: %a_vec = fadd <3 x float> %vec, %vec + %a_vec = fadd <3 x float> %vec, %vec +; CHECK: %b = fsub float %x, %y + %b = fsub float %x, %y +; CHECK: %b_vec = fsub <3 x float> %vec, %vec + %b_vec = fsub <3 x float> %vec, %vec +; CHECK: %c = fmul float %x, %y + %c = fmul float %x, %y +; CHECK: %c_vec = fmul <3 x float> %vec, %vec + %c_vec = fmul <3 x float> %vec, %vec +; CHECK: %d = fdiv float %x, %y + %d = fdiv float %x, %y +; CHECK: %d_vec = fdiv <3 x float> %vec, %vec + %d_vec = fdiv <3 x float> %vec, %vec +; CHECK: %e = frem float %x, %y + %e = frem float %x, %y +; CHECK: %e_vec = frem <3 x float> %vec, %vec + %e_vec = frem <3 x float> %vec, %vec +; CHECK: ret float %e + ret float %e +} + +; CHECK: no_nan +define float @no_nan(float %x, float %y) { +entry: +; CHECK: %vec = load <3 x float>* @vec + %vec = load <3 x float>* @vec +; CHECK: %select = load i1* @select + %select = load i1* @select +; CHECK: %arr = load [3 x float]* @arr + %arr = load [3 x float]* @arr + +; CHECK: %a = fadd nnan float %x, %y + %a = fadd nnan float %x, %y +; CHECK: %a_vec = fadd nnan <3 x float> %vec, %vec + %a_vec = fadd nnan <3 x float> %vec, %vec +; CHECK: %b = fsub nnan float %x, %y + %b = fsub nnan float %x, %y +; CHECK: %b_vec = fsub nnan <3 x float> %vec, %vec + %b_vec = fsub nnan <3 x float> %vec, %vec +; CHECK: %c = fmul nnan float %x, %y + %c = fmul nnan float %x, %y +; CHECK: %c_vec = fmul nnan <3 x float> %vec, %vec + %c_vec = fmul nnan <3 x float> %vec, %vec +; CHECK: %d = fdiv nnan float %x, %y + %d = fdiv nnan float %x, %y +; CHECK: %d_vec = fdiv nnan <3 x float> %vec, %vec + %d_vec = fdiv nnan <3 x float> %vec, %vec +; CHECK: %e = frem nnan float %x, %y + %e = frem nnan float %x, %y +; CHECK: %e_vec = frem nnan <3 x float> %vec, %vec + %e_vec = frem nnan <3 x float> %vec, %vec +; CHECK: ret float %e + ret float %e +} + +; CHECK: no_nan_inf +define float @no_nan_inf(float %x, float %y) { +entry: +; CHECK: %vec = load <3 x float>* @vec + %vec = load <3 x float>* @vec +; CHECK: %select = load i1* @select + %select = load i1* @select +; CHECK: %arr = load [3 x float]* @arr + %arr = load [3 x float]* @arr + +; CHECK: %a = fadd nnan ninf float %x, %y + %a = fadd ninf nnan float %x, %y +; CHECK: %a_vec = fadd nnan <3 x float> %vec, %vec + %a_vec = fadd nnan <3 x float> %vec, %vec +; CHECK: %b = fsub nnan float %x, %y + %b = fsub nnan float %x, %y +; CHECK: %b_vec = fsub nnan ninf <3 x float> %vec, %vec + %b_vec = fsub ninf nnan <3 x float> %vec, %vec +; CHECK: %c = fmul nnan float %x, %y + %c = fmul nnan float %x, %y +; CHECK: %c_vec = fmul nnan <3 x float> %vec, %vec + %c_vec = fmul nnan <3 x float> %vec, %vec +; CHECK: %d = fdiv nnan ninf float %x, %y + %d = fdiv ninf nnan float %x, %y +; CHECK: %d_vec = fdiv nnan <3 x float> %vec, %vec + %d_vec = fdiv nnan <3 x float> %vec, %vec +; CHECK: %e = frem nnan float %x, %y + %e = frem nnan float %x, %y +; CHECK: %e_vec = frem nnan ninf <3 x float> %vec, %vec + %e_vec = frem ninf nnan <3 x float> %vec, %vec +; CHECK: ret float %e + ret float %e +} + +; CHECK: mixed_flags +define float @mixed_flags(float %x, float %y) { +entry: +; CHECK: %vec = load <3 x float>* @vec + %vec = load <3 x float>* @vec +; CHECK: %select = load i1* @select + %select = load i1* @select +; CHECK: %arr = load [3 x float]* @arr + %arr = load [3 x float]* @arr + +; CHECK: %a = fadd nnan ninf float %x, %y + %a = fadd ninf nnan float %x, %y +; CHECK: %a_vec = fadd nnan <3 x float> %vec, %vec + %a_vec = fadd nnan <3 x float> %vec, %vec +; CHECK: %b = fsub fast float %x, %y + %b = fsub nnan nsz fast float %x, %y +; CHECK: %b_vec = fsub nnan <3 x float> %vec, %vec + %b_vec = fsub nnan <3 x float> %vec, %vec +; CHECK: %c = fmul fast float %x, %y + %c = fmul nsz fast arcp float %x, %y +; CHECK: %c_vec = fmul nsz <3 x float> %vec, %vec + %c_vec = fmul nsz <3 x float> %vec, %vec +; CHECK: %d = fdiv nnan ninf arcp float %x, %y + %d = fdiv arcp ninf nnan float %x, %y +; CHECK: %d_vec = fdiv fast <3 x float> %vec, %vec + %d_vec = fdiv fast nnan arcp <3 x float> %vec, %vec +; CHECK: %e = frem nnan nsz float %x, %y + %e = frem nnan nsz float %x, %y +; CHECK: %e_vec = frem nnan <3 x float> %vec, %vec + %e_vec = frem nnan <3 x float> %vec, %vec +; CHECK: ret float %e + ret float %e +} diff --git a/test/Assembler/getelementptr.ll b/test/Assembler/getelementptr.ll index ce6866d54417..af03fca6d2c1 100644 --- a/test/Assembler/getelementptr.ll +++ b/test/Assembler/getelementptr.ll @@ -7,12 +7,12 @@ @C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 3, i64 2, i64 0, i64 0, i64 7523) ; CHECK: @C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 39, i64 1, i64 1, i64 4, i64 5) -;; Verify that i16 indices work. +; Verify that i16 indices work. @x = external global {i32, i32} @y = global i32* getelementptr ({ i32, i32 }* @x, i16 42, i32 0) ; CHECK: @y = global i32* getelementptr ({ i32, i32 }* @x, i16 42, i32 0) -; see if i92 indices work too. +; See if i92 indices work too. define i32 *@test({i32, i32}* %t, i92 %n) { ; CHECK: @test ; CHECK: %B = getelementptr { i32, i32 }* %t, i92 %n, i32 0 @@ -20,3 +20,18 @@ define i32 *@test({i32, i32}* %t, i92 %n) { ret i32* %B } +; Verify that constant expression vector GEPs work. + +@z = global <2 x i32*> getelementptr (<2 x [3 x {i32, i32}]*> zeroinitializer, <2 x i32> , <2 x i32> , <2 x i32> ) + +; Verify that struct GEP works with a vector of pointers. +define <2 x i32*> @test7(<2 x {i32, i32}*> %a) { + %w = getelementptr <2 x {i32, i32}*> %a, <2 x i32> , <2 x i32> zeroinitializer + ret <2 x i32*> %w +} + +; Verify that array GEP works with a vector of pointers. +define <2 x i8*> @test8(<2 x [2 x i8]*> %a) { + %w = getelementptr <2 x [2 x i8]*> %a, <2 x i32> , <2 x i8> + ret <2 x i8*> %w +} diff --git a/test/Assembler/getelementptr_vec_idx1.ll b/test/Assembler/getelementptr_vec_idx1.ll new file mode 100644 index 000000000000..d2479f44048a --- /dev/null +++ b/test/Assembler/getelementptr_vec_idx1.ll @@ -0,0 +1,10 @@ +; RUN: not llvm-as < %s >/dev/null 2> %t +; RUN: FileCheck %s < %t +; Test that a vector index is only used with a vector pointer. + +; CHECK: getelementptr index type missmatch + +define i32 @test(i32* %a) { + %w = getelementptr i32* %a, <2 x i32> + ret i32 %w +} diff --git a/test/Assembler/getelementptr_vec_idx2.ll b/test/Assembler/getelementptr_vec_idx2.ll new file mode 100644 index 000000000000..8b71ce3095b1 --- /dev/null +++ b/test/Assembler/getelementptr_vec_idx2.ll @@ -0,0 +1,10 @@ +; RUN: not llvm-as < %s >/dev/null 2> %t +; RUN: FileCheck %s < %t +; Test that a vector pointer is only used with a vector index. + +; CHECK: getelementptr index type missmatch + +define <2 x i32> @test(<2 x i32*> %a) { + %w = getelementptr <2 x i32*> %a, i32 2 + ret <2 x i32> %w +} diff --git a/test/Assembler/getelementptr_vec_idx3.ll b/test/Assembler/getelementptr_vec_idx3.ll new file mode 100644 index 000000000000..1f6c29b3ccc2 --- /dev/null +++ b/test/Assembler/getelementptr_vec_idx3.ll @@ -0,0 +1,10 @@ +; RUN: not llvm-as < %s >/dev/null 2> %t +; RUN: FileCheck %s < %t +; Test that vector indices have the same number of elements as the pointer. + +; CHECK: getelementptr index type missmatch + +define <4 x i32> @test(<4 x i32>* %a) { + %w = getelementptr <4 x i32>* %a, <2 x i32> + ret i32 %w +} diff --git a/test/Assembler/getelementptr_vec_struct.ll b/test/Assembler/getelementptr_vec_struct.ll new file mode 100644 index 000000000000..ec66836bac19 --- /dev/null +++ b/test/Assembler/getelementptr_vec_struct.ll @@ -0,0 +1,10 @@ +; RUN: not llvm-as < %s >/dev/null 2> %t +; RUN: FileCheck %s < %t +; Test that a vector struct index with non-equal elements is rejected. + +; CHECK: invalid getelementptr indices + +define <2 x i32*> @test7(<2 x {i32, i32}*> %a) { + %w = getelementptr <2 x {i32, i32}*> %a, <2 x i32> , <2 x i32> + ret <2 x i32*> %w +} diff --git a/test/Assembler/unnamed-addr.ll b/test/Assembler/unnamed-addr.ll index 3c94ca213081..35b3b39ce48f 100644 --- a/test/Assembler/unnamed-addr.ll +++ b/test/Assembler/unnamed-addr.ll @@ -15,4 +15,6 @@ declare i32 @zed(%struct.foobar*, %struct.foobar*) ; CHECK: @bar.d = internal unnamed_addr constant %struct.foobar zeroinitializer, align 4 ; CHECK: @foo.d = internal constant %struct.foobar zeroinitializer, align 4 -; CHECK: define i32 @main() unnamed_addr nounwind ssp { +; CHECK: define i32 @main() unnamed_addr #0 { + +; CHECK: attributes #0 = { nounwind ssp } diff --git a/test/Bindings/Ocaml/vmcore.ml b/test/Bindings/Ocaml/vmcore.ml index 61be4b770358..b49bab9ab17b 100644 --- a/test/Bindings/Ocaml/vmcore.ml +++ b/test/Bindings/Ocaml/vmcore.ml @@ -860,7 +860,8 @@ let test_builder () = group "function attribute"; begin ignore (add_function_attr fn Attribute.UWTable); - (* RUN: grep "X7.*uwtable" < %t.ll + (* RUN: grep "X7.*#0" < %t.ll + * RUN: grep "attributes #0 = .*uwtable.*" < %t.ll *) insist ([Attribute.UWTable] = function_attr fn); end; diff --git a/test/Bitcode/attributes.ll b/test/Bitcode/attributes.ll index 502e96728230..6c46e94012a5 100644 --- a/test/Bitcode/attributes.ll +++ b/test/Bitcode/attributes.ll @@ -14,7 +14,7 @@ define void @f2(i8 signext) } define void @f3() noreturn -; CHECK: define void @f3() noreturn +; CHECK: define void @f3() #0 { ret void; } @@ -32,7 +32,7 @@ define void @f5(i8* sret) } define void @f6() nounwind -; CHECK: define void @f6() nounwind +; CHECK: define void @f6() #1 { ret void; } @@ -56,43 +56,43 @@ define void @f9(i8* nest) } define void @f10() readnone -; CHECK: define void @f10() readnone +; CHECK: define void @f10() #2 { ret void; } define void @f11() readonly -; CHECK: define void @f11() readonly +; CHECK: define void @f11() #3 { ret void; } define void @f12() noinline -; CHECK: define void @f12() noinline +; CHECK: define void @f12() #4 { ret void; } define void @f13() alwaysinline -; CHECK: define void @f13() alwaysinline +; CHECK: define void @f13() #5 { ret void; } define void @f14() optsize -; CHECK: define void @f14() optsize +; CHECK: define void @f14() #6 { ret void; } define void @f15() ssp -; CHECK: define void @f15() ssp +; CHECK: define void @f15() #7 { ret void; } define void @f16() sspreq -; CHECK: define void @f16() sspreq +; CHECK: define void @f16() #8 { ret void; } @@ -110,55 +110,93 @@ define void @f18(i8* nocapture) } define void @f19() noredzone -; CHECK: define void @f19() noredzone +; CHECK: define void @f19() #9 { ret void; } define void @f20() noimplicitfloat -; CHECK: define void @f20() noimplicitfloat +; CHECK: define void @f20() #10 { ret void; } define void @f21() naked -; CHECK: define void @f21() naked +; CHECK: define void @f21() #11 { ret void; } define void @f22() inlinehint -; CHECK: define void @f22() inlinehint +; CHECK: define void @f22() #12 { ret void; } define void @f23() alignstack(4) -; CHECK: define void @f23() alignstack(4) +; CHECK: define void @f23() #13 { ret void; } define void @f24() returns_twice -; CHECK: define void @f24() returns_twice +; CHECK: define void @f24() #14 { ret void; } define void @f25() uwtable -; CHECK: define void @f25() uwtable +; CHECK: define void @f25() #15 { ret void; } define void @f26() nonlazybind -; CHECK: define void @f26() nonlazybind +; CHECK: define void @f26() #16 { ret void; } -define void @f27() address_safety -; CHECK: define void @f27() address_safety +define void @f27() sanitize_address +; CHECK: define void @f27() #17 { ret void; } +define void @f28() sanitize_thread +; CHECK: define void @f28() #18 +{ + ret void; +} +define void @f29() sanitize_memory +; CHECK: define void @f29() #19 +{ + ret void; +} + +define void @f30() "cpu"="cortex-a8" +; CHECK: define void @f30() #20 +{ + ret void; +} + +; CHECK: attributes #0 = { noreturn } +; CHECK: attributes #1 = { nounwind } +; CHECK: attributes #2 = { readnone } +; CHECK: attributes #3 = { readonly } +; CHECK: attributes #4 = { noinline } +; CHECK: attributes #5 = { alwaysinline } +; CHECK: attributes #6 = { optsize } +; CHECK: attributes #7 = { ssp } +; CHECK: attributes #8 = { sspreq } +; CHECK: attributes #9 = { noredzone } +; CHECK: attributes #10 = { noimplicitfloat } +; CHECK: attributes #11 = { naked } +; CHECK: attributes #12 = { inlinehint } +; CHECK: attributes #13 = { alignstack=4 } +; CHECK: attributes #14 = { returns_twice } +; CHECK: attributes #15 = { uwtable } +; CHECK: attributes #16 = { nonlazybind } +; CHECK: attributes #17 = { sanitize_address } +; CHECK: attributes #18 = { sanitize_thread } +; CHECK: attributes #19 = { sanitize_memory } +; CHECK: attributes #20 = { "cpu"="cortex-a8" } diff --git a/test/Bitcode/ptest-new.ll b/test/Bitcode/ptest-new.ll index 276fb7ab6a13..735cc9c1cc44 100644 --- a/test/Bitcode/ptest-new.ll +++ b/test/Bitcode/ptest-new.ll @@ -13,10 +13,13 @@ entry: ret i32 %add2 } -; CHECK: declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone -; CHECK: declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone -; CHECK: declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone +; CHECK: declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) #1 +; CHECK: declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) #1 +; CHECK: declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) #1 declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone + +; CHECK: attributes #0 = { nounwind } +; CHECK: attributes #1 = { nounwind readnone } diff --git a/test/Bitcode/ptest-old.ll b/test/Bitcode/ptest-old.ll index fc6ed8ef7b67..fbe962fae51a 100644 --- a/test/Bitcode/ptest-old.ll +++ b/test/Bitcode/ptest-old.ll @@ -13,10 +13,13 @@ entry: ret i32 %add2 } -; CHECK: declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone -; CHECK: declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone -; CHECK: declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone +; CHECK: declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) #1 +; CHECK: declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) #1 +; CHECK: declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) #1 declare i32 @llvm.x86.sse41.ptestc(<4 x float>, <4 x float>) nounwind readnone declare i32 @llvm.x86.sse41.ptestz(<4 x float>, <4 x float>) nounwind readnone declare i32 @llvm.x86.sse41.ptestnzc(<4 x float>, <4 x float>) nounwind readnone + +; CHECK: attributes #0 = { nounwind } +; CHECK: attributes #1 = { nounwind readnone } diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index e10a532341e6..728213f6130a 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -12,11 +12,8 @@ if(NOT LLVM_BUILD_TOOLS) set(EXCLUDE_FROM_ALL ON) endif() -add_lit_testsuite(check-llvm "Running the LLVM regression tests" - ${CMAKE_CURRENT_BINARY_DIR} - PARAMS llvm_site_config=${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg - llvm_unit_site_config=${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg - DEPENDS UnitTests +# Set the depends list as a variable so that it can grow conditionally. +set(LLVM_TEST_DEPENDS UnitTests BugpointPasses LLVMHello llc lli llvm-ar llvm-as llvm-bcanalyzer llvm-diff @@ -27,10 +24,23 @@ add_lit_testsuite(check-llvm "Running the LLVM regression tests" llvm-nm llvm-objdump llvm-readobj + llvm-rtdyld + llvm-symbolizer macho-dump opt profile_rt-shared FileCheck count not - yaml2obj + yaml2obj obj2yaml) + +# If Intel JIT events are supported, depend on a tool that tests the listener. +if( LLVM_USE_INTEL_JITEVENTS ) + set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} llvm-jitlistener) +endif( LLVM_USE_INTEL_JITEVENTS ) + +add_lit_testsuite(check-llvm "Running the LLVM regression tests" + ${CMAKE_CURRENT_BINARY_DIR} + PARAMS llvm_site_config=${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg + llvm_unit_site_config=${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg + DEPENDS ${LLVM_TEST_DEPENDS} ) set_target_properties(check-llvm PROPERTIES FOLDER "Tests") diff --git a/test/CodeGen/AArch64/adc.ll b/test/CodeGen/AArch64/adc.ll new file mode 100644 index 000000000000..7cb373232a2c --- /dev/null +++ b/test/CodeGen/AArch64/adc.ll @@ -0,0 +1,54 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +define i128 @test_simple(i128 %a, i128 %b, i128 %c) { +; CHECK: test_simple: + + %valadd = add i128 %a, %b +; CHECK: adds [[ADDLO:x[0-9]+]], x0, x2 +; CHECK-NEXT: adcs [[ADDHI:x[0-9]+]], x1, x3 + + %valsub = sub i128 %valadd, %c +; CHECK: subs x0, [[ADDLO]], x4 +; CHECK: sbcs x1, [[ADDHI]], x5 + + ret i128 %valsub +; CHECK: ret +} + +define i128 @test_imm(i128 %a) { +; CHECK: test_imm: + + %val = add i128 %a, 12 +; CHECK: adds x0, x0, #12 +; CHECK: adcs x1, x1, {{x[0-9]|xzr}} + + ret i128 %val +; CHECK: ret +} + +define i128 @test_shifted(i128 %a, i128 %b) { +; CHECK: test_shifted: + + %rhs = shl i128 %b, 45 + + %val = add i128 %a, %rhs +; CHECK: adds x0, x0, x2, lsl #45 +; CHECK: adcs x1, x1, {{x[0-9]}} + + ret i128 %val +; CHECK: ret +} + +define i128 @test_extended(i128 %a, i16 %b) { +; CHECK: test_extended: + + %ext = sext i16 %b to i128 + %rhs = shl i128 %ext, 3 + + %val = add i128 %a, %rhs +; CHECK: adds x0, x0, w2, sxth #3 +; CHECK: adcs x1, x1, {{x[0-9]}} + + ret i128 %val +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/addsub-shifted.ll b/test/CodeGen/AArch64/addsub-shifted.ll new file mode 100644 index 000000000000..f2c74f6952b0 --- /dev/null +++ b/test/CodeGen/AArch64/addsub-shifted.ll @@ -0,0 +1,295 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var32 = global i32 0 +@var64 = global i64 0 + +define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { +; CHECK: test_lsl_arith: + + %rhs1 = load volatile i32* @var32 + %shift1 = shl i32 %rhs1, 18 + %val1 = add i32 %lhs32, %shift1 + store volatile i32 %val1, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #18 + + %rhs2 = load volatile i32* @var32 + %shift2 = shl i32 %rhs2, 31 + %val2 = add i32 %shift2, %lhs32 + store volatile i32 %val2, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31 + + %rhs3 = load volatile i32* @var32 + %shift3 = shl i32 %rhs3, 5 + %val3 = sub i32 %lhs32, %shift3 + store volatile i32 %val3, i32* @var32 +; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #5 + +; Subtraction is not commutative! + %rhs4 = load volatile i32* @var32 + %shift4 = shl i32 %rhs4, 19 + %val4 = sub i32 %shift4, %lhs32 + store volatile i32 %val4, i32* @var32 +; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #19 + + %lhs4a = load volatile i32* @var32 + %shift4a = shl i32 %lhs4a, 15 + %val4a = sub i32 0, %shift4a + store volatile i32 %val4a, i32* @var32 +; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsl #15 + + %rhs5 = load volatile i64* @var64 + %shift5 = shl i64 %rhs5, 18 + %val5 = add i64 %lhs64, %shift5 + store volatile i64 %val5, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #18 + + %rhs6 = load volatile i64* @var64 + %shift6 = shl i64 %rhs6, 31 + %val6 = add i64 %shift6, %lhs64 + store volatile i64 %val6, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #31 + + %rhs7 = load volatile i64* @var64 + %shift7 = shl i64 %rhs7, 5 + %val7 = sub i64 %lhs64, %shift7 + store volatile i64 %val7, i64* @var64 +; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #5 + +; Subtraction is not commutative! + %rhs8 = load volatile i64* @var64 + %shift8 = shl i64 %rhs8, 19 + %val8 = sub i64 %shift8, %lhs64 + store volatile i64 %val8, i64* @var64 +; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #19 + + %lhs8a = load volatile i64* @var64 + %shift8a = shl i64 %lhs8a, 60 + %val8a = sub i64 0, %shift8a + store volatile i64 %val8a, i64* @var64 +; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsl #60 + + ret void +; CHECK: ret +} + +define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { +; CHECK: test_lsr_arith: + + %shift1 = lshr i32 %rhs32, 18 + %val1 = add i32 %lhs32, %shift1 + store volatile i32 %val1, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #18 + + %shift2 = lshr i32 %rhs32, 31 + %val2 = add i32 %shift2, %lhs32 + store volatile i32 %val2, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #31 + + %shift3 = lshr i32 %rhs32, 5 + %val3 = sub i32 %lhs32, %shift3 + store volatile i32 %val3, i32* @var32 +; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #5 + +; Subtraction is not commutative! + %shift4 = lshr i32 %rhs32, 19 + %val4 = sub i32 %shift4, %lhs32 + store volatile i32 %val4, i32* @var32 +; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #19 + + %shift4a = lshr i32 %lhs32, 15 + %val4a = sub i32 0, %shift4a + store volatile i32 %val4a, i32* @var32 +; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsr #15 + + %shift5 = lshr i64 %rhs64, 18 + %val5 = add i64 %lhs64, %shift5 + store volatile i64 %val5, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #18 + + %shift6 = lshr i64 %rhs64, 31 + %val6 = add i64 %shift6, %lhs64 + store volatile i64 %val6, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #31 + + %shift7 = lshr i64 %rhs64, 5 + %val7 = sub i64 %lhs64, %shift7 + store volatile i64 %val7, i64* @var64 +; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #5 + +; Subtraction is not commutative! + %shift8 = lshr i64 %rhs64, 19 + %val8 = sub i64 %shift8, %lhs64 + store volatile i64 %val8, i64* @var64 +; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #19 + + %shift8a = lshr i64 %lhs64, 45 + %val8a = sub i64 0, %shift8a + store volatile i64 %val8a, i64* @var64 +; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsr #45 + + ret void +; CHECK: ret +} + +define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { +; CHECK: test_asr_arith: + + %shift1 = ashr i32 %rhs32, 18 + %val1 = add i32 %lhs32, %shift1 + store volatile i32 %val1, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #18 + + %shift2 = ashr i32 %rhs32, 31 + %val2 = add i32 %shift2, %lhs32 + store volatile i32 %val2, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #31 + + %shift3 = ashr i32 %rhs32, 5 + %val3 = sub i32 %lhs32, %shift3 + store volatile i32 %val3, i32* @var32 +; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #5 + +; Subtraction is not commutative! + %shift4 = ashr i32 %rhs32, 19 + %val4 = sub i32 %shift4, %lhs32 + store volatile i32 %val4, i32* @var32 +; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #19 + + %shift4a = ashr i32 %lhs32, 15 + %val4a = sub i32 0, %shift4a + store volatile i32 %val4a, i32* @var32 +; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, asr #15 + + %shift5 = ashr i64 %rhs64, 18 + %val5 = add i64 %lhs64, %shift5 + store volatile i64 %val5, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #18 + + %shift6 = ashr i64 %rhs64, 31 + %val6 = add i64 %shift6, %lhs64 + store volatile i64 %val6, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #31 + + %shift7 = ashr i64 %rhs64, 5 + %val7 = sub i64 %lhs64, %shift7 + store volatile i64 %val7, i64* @var64 +; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #5 + +; Subtraction is not commutative! + %shift8 = ashr i64 %rhs64, 19 + %val8 = sub i64 %shift8, %lhs64 + store volatile i64 %val8, i64* @var64 +; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #19 + + %shift8a = ashr i64 %lhs64, 45 + %val8a = sub i64 0, %shift8a + store volatile i64 %val8a, i64* @var64 +; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, asr #45 + + ret void +; CHECK: ret +} + +define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { +; CHECK: test_cmp: + + %shift1 = shl i32 %rhs32, 13 + %tst1 = icmp uge i32 %lhs32, %shift1 + br i1 %tst1, label %t2, label %end +; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, lsl #13 + +t2: + %shift2 = lshr i32 %rhs32, 20 + %tst2 = icmp ne i32 %lhs32, %shift2 + br i1 %tst2, label %t3, label %end +; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, lsr #20 + +t3: + %shift3 = ashr i32 %rhs32, 9 + %tst3 = icmp ne i32 %lhs32, %shift3 + br i1 %tst3, label %t4, label %end +; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, asr #9 + +t4: + %shift4 = shl i64 %rhs64, 43 + %tst4 = icmp uge i64 %lhs64, %shift4 + br i1 %tst4, label %t5, label %end +; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, lsl #43 + +t5: + %shift5 = lshr i64 %rhs64, 20 + %tst5 = icmp ne i64 %lhs64, %shift5 + br i1 %tst5, label %t6, label %end +; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, lsr #20 + +t6: + %shift6 = ashr i64 %rhs64, 59 + %tst6 = icmp ne i64 %lhs64, %shift6 + br i1 %tst6, label %t7, label %end +; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, asr #59 + +t7: + ret i32 1 +end: + + ret i32 0 +; CHECK: ret +} + +define i32 @test_cmn(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { +; CHECK: test_cmn: + + %shift1 = shl i32 %rhs32, 13 + %val1 = sub i32 0, %shift1 + %tst1 = icmp uge i32 %lhs32, %val1 + br i1 %tst1, label %t2, label %end + ; Important that this isn't lowered to a cmn instruction because if %rhs32 == + ; 0 then the results will differ. +; CHECK: sub [[RHS:w[0-9]+]], wzr, {{w[0-9]+}}, lsl #13 +; CHECK: cmp {{w[0-9]+}}, [[RHS]] + +t2: + %shift2 = lshr i32 %rhs32, 20 + %val2 = sub i32 0, %shift2 + %tst2 = icmp ne i32 %lhs32, %val2 + br i1 %tst2, label %t3, label %end +; CHECK: cmn {{w[0-9]+}}, {{w[0-9]+}}, lsr #20 + +t3: + %shift3 = ashr i32 %rhs32, 9 + %val3 = sub i32 0, %shift3 + %tst3 = icmp eq i32 %lhs32, %val3 + br i1 %tst3, label %t4, label %end +; CHECK: cmn {{w[0-9]+}}, {{w[0-9]+}}, asr #9 + +t4: + %shift4 = shl i64 %rhs64, 43 + %val4 = sub i64 0, %shift4 + %tst4 = icmp slt i64 %lhs64, %val4 + br i1 %tst4, label %t5, label %end + ; Again, it's important that cmn isn't used here in case %rhs64 == 0. +; CHECK: sub [[RHS:x[0-9]+]], xzr, {{x[0-9]+}}, lsl #43 +; CHECK: cmp {{x[0-9]+}}, [[RHS]] + +t5: + %shift5 = lshr i64 %rhs64, 20 + %val5 = sub i64 0, %shift5 + %tst5 = icmp ne i64 %lhs64, %val5 + br i1 %tst5, label %t6, label %end +; CHECK: cmn {{x[0-9]+}}, {{x[0-9]+}}, lsr #20 + +t6: + %shift6 = ashr i64 %rhs64, 59 + %val6 = sub i64 0, %shift6 + %tst6 = icmp ne i64 %lhs64, %val6 + br i1 %tst6, label %t7, label %end +; CHECK: cmn {{x[0-9]+}}, {{x[0-9]+}}, asr #59 + +t7: + ret i32 1 +end: + + ret i32 0 +; CHECK: ret +} + diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll new file mode 100644 index 000000000000..5148807163c9 --- /dev/null +++ b/test/CodeGen/AArch64/addsub.ll @@ -0,0 +1,127 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +; Note that this should be refactored (for efficiency if nothing else) +; when the PCS is implemented so we don't have to worry about the +; loads and stores. + +@var_i32 = global i32 42 +@var_i64 = global i64 0 + +; Add pure 12-bit immediates: +define void @add_small() { +; CHECK: add_small: + +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095 + %val32 = load i32* @var_i32 + %newval32 = add i32 %val32, 4095 + store i32 %newval32, i32* @var_i32 + +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #52 + %val64 = load i64* @var_i64 + %newval64 = add i64 %val64, 52 + store i64 %newval64, i64* @var_i64 + + ret void +} + +; Add 12-bit immediates, shifted left by 12 bits +define void @add_med() { +; CHECK: add_med: + +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12 + %val32 = load i32* @var_i32 + %newval32 = add i32 %val32, 14610432 ; =0xdef000 + store i32 %newval32, i32* @var_i32 + +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #4095, lsl #12 + %val64 = load i64* @var_i64 + %newval64 = add i64 %val64, 16773120 ; =0xfff000 + store i64 %newval64, i64* @var_i64 + + ret void +} + +; Subtract 12-bit immediates +define void @sub_small() { +; CHECK: sub_small: + +; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095 + %val32 = load i32* @var_i32 + %newval32 = sub i32 %val32, 4095 + store i32 %newval32, i32* @var_i32 + +; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #52 + %val64 = load i64* @var_i64 + %newval64 = sub i64 %val64, 52 + store i64 %newval64, i64* @var_i64 + + ret void +} + +; Subtract 12-bit immediates, shifted left by 12 bits +define void @sub_med() { +; CHECK: sub_med: + +; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12 + %val32 = load i32* @var_i32 + %newval32 = sub i32 %val32, 14610432 ; =0xdef000 + store i32 %newval32, i32* @var_i32 + +; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #4095, lsl #12 + %val64 = load i64* @var_i64 + %newval64 = sub i64 %val64, 16773120 ; =0xfff000 + store i64 %newval64, i64* @var_i64 + + ret void +} + +define void @testing() { +; CHECK: testing: + %val = load i32* @var_i32 + +; CHECK: cmp {{w[0-9]+}}, #4095 +; CHECK: b.ne .LBB4_6 + %cmp_pos_small = icmp ne i32 %val, 4095 + br i1 %cmp_pos_small, label %ret, label %test2 + +test2: +; CHECK: cmp {{w[0-9]+}}, #3567, lsl #12 +; CHECK: b.lo .LBB4_6 + %newval2 = add i32 %val, 1 + store i32 %newval2, i32* @var_i32 + %cmp_pos_big = icmp ult i32 %val, 14610432 + br i1 %cmp_pos_big, label %ret, label %test3 + +test3: +; CHECK: cmp {{w[0-9]+}}, #123 +; CHECK: b.lt .LBB4_6 + %newval3 = add i32 %val, 2 + store i32 %newval3, i32* @var_i32 + %cmp_pos_slt = icmp slt i32 %val, 123 + br i1 %cmp_pos_slt, label %ret, label %test4 + +test4: +; CHECK: cmp {{w[0-9]+}}, #321 +; CHECK: b.gt .LBB4_6 + %newval4 = add i32 %val, 3 + store i32 %newval4, i32* @var_i32 + %cmp_pos_sgt = icmp sgt i32 %val, 321 + br i1 %cmp_pos_sgt, label %ret, label %test5 + +test5: +; CHECK: cmn {{w[0-9]+}}, #444 +; CHECK: b.gt .LBB4_6 + %newval5 = add i32 %val, 4 + store i32 %newval5, i32* @var_i32 + %cmp_neg_uge = icmp sgt i32 %val, -444 + br i1 %cmp_neg_uge, label %ret, label %test6 + +test6: + %newval6 = add i32 %val, 5 + store i32 %newval6, i32* @var_i32 + ret void + +ret: + ret void +} +; TODO: adds/subs diff --git a/test/CodeGen/AArch64/addsub_ext.ll b/test/CodeGen/AArch64/addsub_ext.ll new file mode 100644 index 000000000000..2dd16626ea9f --- /dev/null +++ b/test/CodeGen/AArch64/addsub_ext.ll @@ -0,0 +1,189 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var8 = global i8 0 +@var16 = global i16 0 +@var32 = global i32 0 +@var64 = global i64 0 + +define void @addsub_i8rhs() { +; CHECK: addsub_i8rhs: + %val8_tmp = load i8* @var8 + %lhs32 = load i32* @var32 + %lhs64 = load i64* @var64 + + ; Need this to prevent extension upon load and give a vanilla i8 operand. + %val8 = add i8 %val8_tmp, 123 + + +; Zero-extending to 32-bits + %rhs32_zext = zext i8 %val8 to i32 + %res32_zext = add i32 %lhs32, %rhs32_zext + store volatile i32 %res32_zext, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb + + %rhs32_zext_shift = shl i32 %rhs32_zext, 3 + %res32_zext_shift = add i32 %lhs32, %rhs32_zext_shift + store volatile i32 %res32_zext_shift, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3 + + +; Zero-extending to 64-bits + %rhs64_zext = zext i8 %val8 to i64 + %res64_zext = add i64 %lhs64, %rhs64_zext + store volatile i64 %res64_zext, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb + + %rhs64_zext_shift = shl i64 %rhs64_zext, 1 + %res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift + store volatile i64 %res64_zext_shift, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1 + +; Sign-extending to 32-bits + %rhs32_sext = sext i8 %val8 to i32 + %res32_sext = add i32 %lhs32, %rhs32_sext + store volatile i32 %res32_sext, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb + + %rhs32_sext_shift = shl i32 %rhs32_sext, 1 + %res32_sext_shift = add i32 %lhs32, %rhs32_sext_shift + store volatile i32 %res32_sext_shift, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1 + +; Sign-extending to 64-bits + %rhs64_sext = sext i8 %val8 to i64 + %res64_sext = add i64 %lhs64, %rhs64_sext + store volatile i64 %res64_sext, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb + + %rhs64_sext_shift = shl i64 %rhs64_sext, 4 + %res64_sext_shift = add i64 %lhs64, %rhs64_sext_shift + store volatile i64 %res64_sext_shift, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4 + + +; CMP variants + %tst = icmp slt i32 %lhs32, %rhs32_zext + br i1 %tst, label %end, label %test2 +; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxtb + +test2: + %cmp_sext = sext i8 %val8 to i64 + %tst2 = icmp eq i64 %lhs64, %cmp_sext + br i1 %tst2, label %other, label %end +; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxtb + +other: + store volatile i32 %lhs32, i32* @var32 + ret void + +end: + ret void +} + +define void @addsub_i16rhs() { +; CHECK: addsub_i16rhs: + %val16_tmp = load i16* @var16 + %lhs32 = load i32* @var32 + %lhs64 = load i64* @var64 + + ; Need this to prevent extension upon load and give a vanilla i16 operand. + %val16 = add i16 %val16_tmp, 123 + + +; Zero-extending to 32-bits + %rhs32_zext = zext i16 %val16 to i32 + %res32_zext = add i32 %lhs32, %rhs32_zext + store volatile i32 %res32_zext, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth + + %rhs32_zext_shift = shl i32 %rhs32_zext, 3 + %res32_zext_shift = add i32 %lhs32, %rhs32_zext_shift + store volatile i32 %res32_zext_shift, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3 + + +; Zero-extending to 64-bits + %rhs64_zext = zext i16 %val16 to i64 + %res64_zext = add i64 %lhs64, %rhs64_zext + store volatile i64 %res64_zext, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth + + %rhs64_zext_shift = shl i64 %rhs64_zext, 1 + %res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift + store volatile i64 %res64_zext_shift, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1 + +; Sign-extending to 32-bits + %rhs32_sext = sext i16 %val16 to i32 + %res32_sext = add i32 %lhs32, %rhs32_sext + store volatile i32 %res32_sext, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth + + %rhs32_sext_shift = shl i32 %rhs32_sext, 1 + %res32_sext_shift = add i32 %lhs32, %rhs32_sext_shift + store volatile i32 %res32_sext_shift, i32* @var32 +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth #1 + +; Sign-extending to 64-bits + %rhs64_sext = sext i16 %val16 to i64 + %res64_sext = add i64 %lhs64, %rhs64_sext + store volatile i64 %res64_sext, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth + + %rhs64_sext_shift = shl i64 %rhs64_sext, 4 + %res64_sext_shift = add i64 %lhs64, %rhs64_sext_shift + store volatile i64 %res64_sext_shift, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth #4 + + +; CMP variants + %tst = icmp slt i32 %lhs32, %rhs32_zext + br i1 %tst, label %end, label %test2 +; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxth + +test2: + %cmp_sext = sext i16 %val16 to i64 + %tst2 = icmp eq i64 %lhs64, %cmp_sext + br i1 %tst2, label %other, label %end +; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxth + +other: + store volatile i32 %lhs32, i32* @var32 + ret void + +end: + ret void +} + +; N.b. we could probably check more here ("add w2, w3, w1, uxtw" for +; example), but the remaining instructions are probably not idiomatic +; in the face of "add/sub (shifted register)" so I don't intend to. +define void @addsub_i32rhs() { +; CHECK: addsub_i32rhs: + %val32_tmp = load i32* @var32 + %lhs64 = load i64* @var64 + + %val32 = add i32 %val32_tmp, 123 + + %rhs64_zext = zext i32 %val32 to i64 + %res64_zext = add i64 %lhs64, %rhs64_zext + store volatile i64 %res64_zext, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw + + %rhs64_zext_shift = shl i64 %rhs64_zext, 2 + %res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift + store volatile i64 %res64_zext_shift, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2 + + %rhs64_sext = sext i32 %val32 to i64 + %res64_sext = add i64 %lhs64, %rhs64_sext + store volatile i64 %res64_sext, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw + + %rhs64_sext_shift = shl i64 %rhs64_sext, 2 + %res64_sext_shift = add i64 %lhs64, %rhs64_sext_shift + store volatile i64 %res64_sext_shift, i64* @var64 +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2 + + ret void +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/adrp-relocation.ll b/test/CodeGen/AArch64/adrp-relocation.ll new file mode 100644 index 000000000000..c33b442624a5 --- /dev/null +++ b/test/CodeGen/AArch64/adrp-relocation.ll @@ -0,0 +1,35 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -filetype=obj < %s | elf-dump | FileCheck %s + +define i64 @testfn() nounwind { +entry: + ret i64 0 +} + +define i64 @foo() nounwind { +entry: + %bar = alloca i64 ()*, align 8 + store i64 ()* @testfn, i64 ()** %bar, align 8 + %call = call i64 @testfn() + ret i64 %call +} + +; The above should produce an ADRP/ADD pair to calculate the address of +; testfn. The important point is that LLVM shouldn't think it can deal with the +; relocation on the ADRP itself (even though it knows everything about the +; relative offsets of testfn and foo) because its value depends on where this +; object file's .text section gets relocated in memory. + +; CHECK: .rela.text + +; CHECK: # Relocation 0 +; CHECK-NEXT: (('r_offset', 0x0000000000000010) +; CHECK-NEXT: ('r_sym', 0x00000007) +; CHECK-NEXT: ('r_type', 0x00000113) +; CHECK-NEXT: ('r_addend', 0x0000000000000000) +; CHECK-NEXT: ), +; CHECK-NEXT: Relocation 1 +; CHECK-NEXT: (('r_offset', 0x0000000000000014) +; CHECK-NEXT: ('r_sym', 0x00000007) +; CHECK-NEXT: ('r_type', 0x00000115) +; CHECK-NEXT: ('r_addend', 0x0000000000000000) +; CHECK-NEXT: ), diff --git a/test/CodeGen/AArch64/alloca.ll b/test/CodeGen/AArch64/alloca.ll new file mode 100644 index 000000000000..c62edf6503c6 --- /dev/null +++ b/test/CodeGen/AArch64/alloca.ll @@ -0,0 +1,134 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +declare void @use_addr(i8*) + +define void @test_simple_alloca(i64 %n) { +; CHECK: test_simple_alloca: + + %buf = alloca i8, i64 %n + ; Make sure we align the stack change to 16 bytes: +; CHECK: add [[SPDELTA:x[0-9]+]], x0, #15 +; CHECK: and x0, [[SPDELTA]], #0xfffffffffffffff0 + + ; Make sure we change SP. It would be surprising if anything but x0 were used + ; for the final sp, but it could be if it was then moved into x0. +; CHECK: mov [[TMP:x[0-9]+]], sp +; CHECK: sub x0, [[TMP]], [[SPDELTA]] +; CHECK: mov sp, x0 + + call void @use_addr(i8* %buf) +; CHECK: bl use_addr + + ret void + ; Make sure epilogue restores sp from fp +; CHECK: sub sp, x29, #16 +; CHECK: ldp x29, x30, [sp, #16] +; CHECK: add sp, sp, #32 +; CHECK: ret +} + +declare void @use_addr_loc(i8*, i64*) + +define i64 @test_alloca_with_local(i64 %n) { +; CHECK: test_alloca_with_local: +; CHECK: sub sp, sp, #32 +; CHECK: stp x29, x30, [sp, #16] + + %loc = alloca i64 + %buf = alloca i8, i64 %n + ; Make sure we align the stack change to 16 bytes: +; CHECK: add [[SPDELTA:x[0-9]+]], x0, #15 +; CHECK: and x0, [[SPDELTA]], #0xfffffffffffffff0 + + ; Make sure we change SP. It would be surprising if anything but x0 were used + ; for the final sp, but it could be if it was then moved into x0. +; CHECK: mov [[TMP:x[0-9]+]], sp +; CHECK: sub x0, [[TMP]], [[SPDELTA]] +; CHECK: mov sp, x0 + + ; Obviously suboptimal code here, but it to get &local in x1 +; CHECK: sub [[TMP:x[0-9]+]], x29, [[LOC_FROM_FP:#[0-9]+]] +; CHECK: add x1, [[TMP]], #0 + + call void @use_addr_loc(i8* %buf, i64* %loc) +; CHECK: bl use_addr + + %val = load i64* %loc +; CHECK: sub x[[TMP:[0-9]+]], x29, [[LOC_FROM_FP]] +; CHECK: ldr x0, [x[[TMP]]] + + ret i64 %val + ; Make sure epilogue restores sp from fp +; CHECK: sub sp, x29, #16 +; CHECK: ldp x29, x30, [sp, #16] +; CHECK: add sp, sp, #32 +; CHECK: ret +} + +define void @test_variadic_alloca(i64 %n, ...) { +; CHECK: test_variadic_alloca: + +; CHECK: sub sp, sp, #208 +; CHECK: stp x29, x30, [sp, #192] +; CHECK: add x29, sp, #192 +; CHECK: sub [[TMP:x[0-9]+]], x29, #192 +; CHECK: add x8, [[TMP]], #0 +; CHECK: str q7, [x8, #112] +; [...] +; CHECK: str q1, [x8, #16] + + %addr = alloca i8, i64 %n + + call void @use_addr(i8* %addr) +; CHECK: bl use_addr + + ret void +; CHECK: sub sp, x29, #192 +; CHECK: ldp x29, x30, [sp, #192] +; CHECK: add sp, sp, #208 +} + +define void @test_alloca_large_frame(i64 %n) { +; CHECK: test_alloca_large_frame: + +; CHECK: sub sp, sp, #496 +; CHECK: stp x29, x30, [sp, #480] +; CHECK: add x29, sp, #480 +; CHECK: sub sp, sp, #48 +; CHECK: sub sp, sp, #1953, lsl #12 + + %addr1 = alloca i8, i64 %n + %addr2 = alloca i64, i64 1000000 + + call void @use_addr_loc(i8* %addr1, i64* %addr2) + + ret void +; CHECK: sub sp, x29, #480 +; CHECK: ldp x29, x30, [sp, #480] +; CHECK: add sp, sp, #496 +} + +declare i8* @llvm.stacksave() +declare void @llvm.stackrestore(i8*) + +define void @test_scoped_alloca(i64 %n) { +; CHECK: test_scoped_alloca +; CHECK: sub sp, sp, #32 + + %sp = call i8* @llvm.stacksave() +; CHECK: mov [[SAVED_SP:x[0-9]+]], sp + + %addr = alloca i8, i64 %n +; CHECK: and [[SPDELTA:x[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0 +; CHECK: mov [[OLDSP:x[0-9]+]], sp +; CHECK: sub [[NEWSP:x[0-9]+]], [[OLDSP]], [[SPDELTA]] +; CHECK: mov sp, [[NEWSP]] + + call void @use_addr(i8* %addr) +; CHECK: bl use_addr + + call void @llvm.stackrestore(i8* %sp) +; CHECK: mov sp, [[SAVED_SP]] + + ret void +} diff --git a/test/CodeGen/AArch64/analyze-branch.ll b/test/CodeGen/AArch64/analyze-branch.ll new file mode 100644 index 000000000000..e10bbb0f8691 --- /dev/null +++ b/test/CodeGen/AArch64/analyze-branch.ll @@ -0,0 +1,231 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +; This test checks that LLVM can do basic stripping and reapplying of branches +; to basic blocks. + +declare void @test_true() +declare void @test_false() + +; !0 corresponds to a branch being taken, !1 to not being takne. +!0 = metadata !{metadata !"branch_weights", i32 64, i32 4} +!1 = metadata !{metadata !"branch_weights", i32 4, i32 64} + +define void @test_Bcc_fallthrough_taken(i32 %in) nounwind { +; CHECK: test_Bcc_fallthrough_taken: + %tst = icmp eq i32 %in, 42 + br i1 %tst, label %true, label %false, !prof !0 + +; CHECK: cmp {{w[0-9]+}}, #42 + +; CHECK: b.ne [[FALSE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: // BB# +; CHECK-NEXT: bl test_true + +; CHECK: [[FALSE]]: +; CHECK: bl test_false + +true: + call void @test_true() + ret void + +false: + call void @test_false() + ret void +} + +define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind { +; CHECK: test_Bcc_fallthrough_nottaken: + %tst = icmp eq i32 %in, 42 + br i1 %tst, label %true, label %false, !prof !1 + +; CHECK: cmp {{w[0-9]+}}, #42 + +; CHECK: b.eq [[TRUE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: // BB# +; CHECK-NEXT: bl test_false + +; CHECK: [[TRUE]]: +; CHECK: bl test_true + +true: + call void @test_true() + ret void + +false: + call void @test_false() + ret void +} + +define void @test_CBZ_fallthrough_taken(i32 %in) nounwind { +; CHECK: test_CBZ_fallthrough_taken: + %tst = icmp eq i32 %in, 0 + br i1 %tst, label %true, label %false, !prof !0 + +; CHECK: cbnz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: // BB# +; CHECK-NEXT: bl test_true + +; CHECK: [[FALSE]]: +; CHECK: bl test_false + +true: + call void @test_true() + ret void + +false: + call void @test_false() + ret void +} + +define void @test_CBZ_fallthrough_nottaken(i64 %in) nounwind { +; CHECK: test_CBZ_fallthrough_nottaken: + %tst = icmp eq i64 %in, 0 + br i1 %tst, label %true, label %false, !prof !1 + +; CHECK: cbz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: // BB# +; CHECK-NEXT: bl test_false + +; CHECK: [[TRUE]]: +; CHECK: bl test_true + +true: + call void @test_true() + ret void + +false: + call void @test_false() + ret void +} + +define void @test_CBNZ_fallthrough_taken(i32 %in) nounwind { +; CHECK: test_CBNZ_fallthrough_taken: + %tst = icmp ne i32 %in, 0 + br i1 %tst, label %true, label %false, !prof !0 + +; CHECK: cbz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: // BB# +; CHECK-NEXT: bl test_true + +; CHECK: [[FALSE]]: +; CHECK: bl test_false + +true: + call void @test_true() + ret void + +false: + call void @test_false() + ret void +} + +define void @test_CBNZ_fallthrough_nottaken(i64 %in) nounwind { +; CHECK: test_CBNZ_fallthrough_nottaken: + %tst = icmp ne i64 %in, 0 + br i1 %tst, label %true, label %false, !prof !1 + +; CHECK: cbnz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: // BB# +; CHECK-NEXT: bl test_false + +; CHECK: [[TRUE]]: +; CHECK: bl test_true + +true: + call void @test_true() + ret void + +false: + call void @test_false() + ret void +} + +define void @test_TBZ_fallthrough_taken(i32 %in) nounwind { +; CHECK: test_TBZ_fallthrough_taken: + %bit = and i32 %in, 32768 + %tst = icmp eq i32 %bit, 0 + br i1 %tst, label %true, label %false, !prof !0 + +; CHECK: tbnz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: // BB# +; CHECK-NEXT: bl test_true + +; CHECK: [[FALSE]]: +; CHECK: bl test_false + +true: + call void @test_true() + ret void + +false: + call void @test_false() + ret void +} + +define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind { +; CHECK: test_TBZ_fallthrough_nottaken: + %bit = and i64 %in, 32768 + %tst = icmp eq i64 %bit, 0 + br i1 %tst, label %true, label %false, !prof !1 + +; CHECK: tbz {{x[0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: // BB# +; CHECK-NEXT: bl test_false + +; CHECK: [[TRUE]]: +; CHECK: bl test_true + +true: + call void @test_true() + ret void + +false: + call void @test_false() + ret void +} + + +define void @test_TBNZ_fallthrough_taken(i32 %in) nounwind { +; CHECK: test_TBNZ_fallthrough_taken: + %bit = and i32 %in, 32768 + %tst = icmp ne i32 %bit, 0 + br i1 %tst, label %true, label %false, !prof !0 + +; CHECK: tbz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: // BB# +; CHECK-NEXT: bl test_true + +; CHECK: [[FALSE]]: +; CHECK: bl test_false + +true: + call void @test_true() + ret void + +false: + call void @test_false() + ret void +} + +define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind { +; CHECK: test_TBNZ_fallthrough_nottaken: + %bit = and i64 %in, 32768 + %tst = icmp ne i64 %bit, 0 + br i1 %tst, label %true, label %false, !prof !1 + +; CHECK: tbnz {{x[0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: // BB# +; CHECK-NEXT: bl test_false + +; CHECK: [[TRUE]]: +; CHECK: bl test_true + +true: + call void @test_true() + ret void + +false: + call void @test_false() + ret void +} + diff --git a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll new file mode 100644 index 000000000000..3c03e47147b0 --- /dev/null +++ b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll @@ -0,0 +1,24 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +define i32 @foo(i32* %var, i1 %cond) { +; CHECK: foo: + br i1 %cond, label %atomic_ver, label %simple_ver +simple_ver: + %oldval = load i32* %var + %newval = add nsw i32 %oldval, -1 + store i32 %newval, i32* %var + br label %somewhere +atomic_ver: + %val = atomicrmw add i32* %var, i32 -1 seq_cst + br label %somewhere +; CHECK: dmb +; CHECK: ldxr +; CHECK: dmb + ; The key point here is that the second dmb isn't immediately followed by the + ; simple_ver basic block, which LLVM attempted to do when DMB had been marked + ; with isBarrier. For now, look for something that looks like "somewhere". +; CHECK-NEXT: mov +somewhere: + %combined = phi i32 [ %val, %atomic_ver ], [ %newval, %simple_ver] + ret i32 %combined +} diff --git a/test/CodeGen/AArch64/atomic-ops.ll b/test/CodeGen/AArch64/atomic-ops.ll new file mode 100644 index 000000000000..f3c16171cc83 --- /dev/null +++ b/test/CodeGen/AArch64/atomic-ops.ll @@ -0,0 +1,1055 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +@var8 = global i8 0 +@var16 = global i16 0 +@var32 = global i32 0 +@var64 = global i64 0 + +define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { +; CHECK: test_atomic_load_add_i8: + %old = atomicrmw add i8* @var8, i8 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { +; CHECK: test_atomic_load_add_i16: + %old = atomicrmw add i16* @var16, i16 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { +; CHECK: test_atomic_load_add_i32: + %old = atomicrmw add i32* @var32, i32 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { +; CHECK: test_atomic_load_add_i64: + %old = atomicrmw add i64* @var64, i64 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; x0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: add [[NEW:x[0-9]+]], x[[OLD]], x0 +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + +define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { +; CHECK: test_atomic_load_sub_i8: + %old = atomicrmw sub i8* @var8, i8 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { +; CHECK: test_atomic_load_sub_i16: + %old = atomicrmw sub i16* @var16, i16 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { +; CHECK: test_atomic_load_sub_i32: + %old = atomicrmw sub i32* @var32, i32 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { +; CHECK: test_atomic_load_sub_i64: + %old = atomicrmw sub i64* @var64, i64 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; x0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: sub [[NEW:x[0-9]+]], x[[OLD]], x0 +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + +define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { +; CHECK: test_atomic_load_and_i8: + %old = atomicrmw and i8* @var8, i8 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { +; CHECK: test_atomic_load_and_i16: + %old = atomicrmw and i16* @var16, i16 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { +; CHECK: test_atomic_load_and_i32: + %old = atomicrmw and i32* @var32, i32 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { +; CHECK: test_atomic_load_and_i64: + %old = atomicrmw and i64* @var64, i64 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; x0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: and [[NEW:x[0-9]+]], x[[OLD]], x0 +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + +define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { +; CHECK: test_atomic_load_or_i8: + %old = atomicrmw or i8* @var8, i8 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { +; CHECK: test_atomic_load_or_i16: + %old = atomicrmw or i16* @var16, i16 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { +; CHECK: test_atomic_load_or_i32: + %old = atomicrmw or i32* @var32, i32 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { +; CHECK: test_atomic_load_or_i64: + %old = atomicrmw or i64* @var64, i64 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; x0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: orr [[NEW:x[0-9]+]], x[[OLD]], x0 +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + +define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { +; CHECK: test_atomic_load_xor_i8: + %old = atomicrmw xor i8* @var8, i8 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { +; CHECK: test_atomic_load_xor_i16: + %old = atomicrmw xor i16* @var16, i16 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { +; CHECK: test_atomic_load_xor_i32: + %old = atomicrmw xor i32* @var32, i32 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { +; CHECK: test_atomic_load_xor_i64: + %old = atomicrmw xor i64* @var64, i64 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; x0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: eor [[NEW:x[0-9]+]], x[[OLD]], x0 +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + +define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { +; CHECK: test_atomic_load_xchg_i8: + %old = atomicrmw xchg i8* @var8, i8 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { +; CHECK: test_atomic_load_xchg_i16: + %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { +; CHECK: test_atomic_load_xchg_i32: + %old = atomicrmw xchg i32* @var32, i32 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { +; CHECK: test_atomic_load_xchg_i64: + %old = atomicrmw xchg i64* @var64, i64 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; x0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + + +define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { +; CHECK: test_atomic_load_min_i8: + %old = atomicrmw min i8* @var8, i8 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]], sxtb +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt +; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { +; CHECK: test_atomic_load_min_i16: + %old = atomicrmw min i16* @var16, i16 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]], sxth +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt +; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { +; CHECK: test_atomic_load_min_i32: + %old = atomicrmw min i32* @var32, i32 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]] +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { +; CHECK: test_atomic_load_min_i64: + %old = atomicrmw min i64* @var64, i64 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; x0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp x0, x[[OLD]] +; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + +define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { +; CHECK: test_atomic_load_max_i8: + %old = atomicrmw max i8* @var8, i8 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]], sxtb +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt +; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { +; CHECK: test_atomic_load_max_i16: + %old = atomicrmw max i16* @var16, i16 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]], sxth +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt +; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { +; CHECK: test_atomic_load_max_i32: + %old = atomicrmw max i32* @var32, i32 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]] +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { +; CHECK: test_atomic_load_max_i64: + %old = atomicrmw max i64* @var64, i64 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; x0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp x0, x[[OLD]] +; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lt +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + +define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { +; CHECK: test_atomic_load_umin_i8: + %old = atomicrmw umin i8* @var8, i8 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]], uxtb +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi +; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { +; CHECK: test_atomic_load_umin_i16: + %old = atomicrmw umin i16* @var16, i16 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]], uxth +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi +; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { +; CHECK: test_atomic_load_umin_i32: + %old = atomicrmw umin i32* @var32, i32 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]] +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { +; CHECK: test_atomic_load_umin_i64: + %old = atomicrmw umin i64* @var64, i64 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; x0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp x0, x[[OLD]] +; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + +define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { +; CHECK: test_atomic_load_umax_i8: + %old = atomicrmw umax i8* @var8, i8 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]], uxtb +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo +; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { +; CHECK: test_atomic_load_umax_i16: + %old = atomicrmw umax i16* @var16, i16 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]], uxth +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo +; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { +; CHECK: test_atomic_load_umax_i32: + %old = atomicrmw umax i32* @var32, i32 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w0, w[[OLD]] +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { +; CHECK: test_atomic_load_umax_i64: + %old = atomicrmw umax i64* @var64, i64 %offset seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; x0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp x0, x[[OLD]] +; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lo +; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + +define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { +; CHECK: test_atomic_cmpxchg_i8: + %old = cmpxchg i8* @var8, i8 %wanted, i8 %new seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: +; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w[[OLD]], w0 +; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] + ; As above, w1 is a reasonable guess. +; CHECK: stxrb [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { +; CHECK: test_atomic_cmpxchg_i16: + %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 + +; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: +; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w[[OLD]], w0 +; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] + ; As above, w1 is a reasonable guess. +; CHECK: stxrh [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { +; CHECK: test_atomic_cmpxchg_i32: + %old = cmpxchg i32* @var32, i32 %wanted, i32 %new seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 + +; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: +; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp w[[OLD]], w0 +; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] + ; As above, w1 is a reasonable guess. +; CHECK: stxr [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { +; CHECK: test_atomic_cmpxchg_i64: + %old = cmpxchg i64* @var64, i64 %wanted, i64 %new seq_cst +; CHECK: dmb ish +; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 + +; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: +; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] + ; w0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp x[[OLD]], x0 +; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] + ; As above, w1 is a reasonable guess. +; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]] +; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] +; CHECK: dmb ish + +; CHECK: mov x0, x[[OLD]] + ret i64 %old +} + +define i8 @test_atomic_load_monotonic_i8() nounwind { +; CHECK: test_atomic_load_monotonic_i8: + %val = load atomic i8* @var8 monotonic, align 1 +; CHECK-NOT: dmb +; CHECK: adrp x[[HIADDR:[0-9]+]], var8 +; CHECK: ldrb w0, [x[[HIADDR]], #:lo12:var8] +; CHECK-NOT: dmb + + ret i8 %val +} + +define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { +; CHECK: test_atomic_load_monotonic_regoff_i8: + %addr_int = add i64 %base, %off + %addr = inttoptr i64 %addr_int to i8* + + %val = load atomic i8* %addr monotonic, align 1 +; CHECK-NOT: dmb +; CHECK: ldrb w0, [x0, x1] +; CHECK-NOT: dmb + + ret i8 %val +} + +define i8 @test_atomic_load_acquire_i8() nounwind { +; CHECK: test_atomic_load_acquire_i8: + %val = load atomic i8* @var8 acquire, align 1 +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 + +; CHECK: ldarb w0, [x[[ADDR]]] + ret i8 %val +} + +define i8 @test_atomic_load_seq_cst_i8() nounwind { +; CHECK: test_atomic_load_seq_cst_i8: + %val = load atomic i8* @var8 seq_cst, align 1 +; CHECK: adrp x[[HIADDR:[0-9]+]], var8 +; CHECK: ldrb w0, [x[[HIADDR]], #:lo12:var8] +; CHECK: dmb ish + ret i8 %val +} + +define i16 @test_atomic_load_monotonic_i16() nounwind { +; CHECK: test_atomic_load_monotonic_i16: + %val = load atomic i16* @var16 monotonic, align 2 +; CHECK-NOT: dmb +; CHECK: adrp x[[HIADDR:[0-9]+]], var16 +; CHECK: ldrh w0, [x[[HIADDR]], #:lo12:var16] +; CHECK-NOT: dmb + + ret i16 %val +} + +define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind { +; CHECK: test_atomic_load_monotonic_regoff_i32: + %addr_int = add i64 %base, %off + %addr = inttoptr i64 %addr_int to i32* + + %val = load atomic i32* %addr monotonic, align 4 +; CHECK-NOT: dmb +; CHECK: ldr w0, [x0, x1] +; CHECK-NOT: dmb + + ret i32 %val +} + +define i64 @test_atomic_load_seq_cst_i64() nounwind { +; CHECK: test_atomic_load_seq_cst_i64: + %val = load atomic i64* @var64 seq_cst, align 8 +; CHECK: adrp x[[HIADDR:[0-9]+]], var64 +; CHECK: ldr x0, [x[[HIADDR]], #:lo12:var64] +; CHECK: dmb ish + ret i64 %val +} + +define void @test_atomic_store_monotonic_i8(i8 %val) nounwind { +; CHECK: test_atomic_store_monotonic_i8: + store atomic i8 %val, i8* @var8 monotonic, align 1 +; CHECK: adrp x[[HIADDR:[0-9]+]], var8 +; CHECK: strb w0, [x[[HIADDR]], #:lo12:var8] + + ret void +} + +define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind { +; CHECK: test_atomic_store_monotonic_regoff_i8: + + %addr_int = add i64 %base, %off + %addr = inttoptr i64 %addr_int to i8* + + store atomic i8 %val, i8* %addr monotonic, align 1 +; CHECK: strb w2, [x0, x1] + + ret void +} +define void @test_atomic_store_release_i8(i8 %val) nounwind { +; CHECK: test_atomic_store_release_i8: + store atomic i8 %val, i8* @var8 release, align 1 +; CHECK: adrp [[HIADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK: stlrb w0, [x[[ADDR]]] + + ret void +} + +define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { +; CHECK: test_atomic_store_seq_cst_i8: + store atomic i8 %val, i8* @var8 seq_cst, align 1 +; CHECK: adrp [[HIADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK: stlrb w0, [x[[ADDR]]] +; CHECK: dmb ish + + ret void +} + +define void @test_atomic_store_monotonic_i16(i16 %val) nounwind { +; CHECK: test_atomic_store_monotonic_i16: + store atomic i16 %val, i16* @var16 monotonic, align 2 +; CHECK: adrp x[[HIADDR:[0-9]+]], var16 +; CHECK: strh w0, [x[[HIADDR]], #:lo12:var16] + + ret void +} + +define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind { +; CHECK: test_atomic_store_monotonic_regoff_i32: + + %addr_int = add i64 %base, %off + %addr = inttoptr i64 %addr_int to i32* + + store atomic i32 %val, i32* %addr monotonic, align 4 +; CHECK: str w2, [x0, x1] + + ret void +} + +define void @test_atomic_store_release_i64(i64 %val) nounwind { +; CHECK: test_atomic_store_release_i64: + store atomic i64 %val, i64* @var64 release, align 8 +; CHECK: adrp [[HIADDR:x[0-9]+]], var64 +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var64 +; CHECK: stlr x0, [x[[ADDR]]] + + ret void +} diff --git a/test/CodeGen/AArch64/basic-pic.ll b/test/CodeGen/AArch64/basic-pic.ll new file mode 100644 index 000000000000..da94041c95ff --- /dev/null +++ b/test/CodeGen/AArch64/basic-pic.ll @@ -0,0 +1,70 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -relocation-model=pic %s -o - | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -relocation-model=pic -filetype=obj %s -o -| llvm-objdump -r - | FileCheck --check-prefix=CHECK-ELF %s + +@var = global i32 0 + +; CHECK-ELF: RELOCATION RECORDS FOR [.text] + +define i32 @get_globalvar() { +; CHECK: get_globalvar: + + %val = load i32* @var +; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var +; CHECK: ldr x[[GOTLOC:[0-9]+]], [x[[GOTHI]], #:got_lo12:var] +; CHECK: ldr w0, [x[[GOTLOC]]] + +; CHECK-ELF: R_AARCH64_ADR_GOT_PAGE var +; CHECK-ELF: R_AARCH64_LD64_GOT_LO12_NC var + ret i32 %val +} + +define i32* @get_globalvaraddr() { +; CHECK: get_globalvaraddr: + + %val = load i32* @var +; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var +; CHECK: ldr x0, [x[[GOTHI]], #:got_lo12:var] + +; CHECK-ELF: R_AARCH64_ADR_GOT_PAGE var +; CHECK-ELF: R_AARCH64_LD64_GOT_LO12_NC var + ret i32* @var +} + +@hiddenvar = hidden global i32 0 + +define i32 @get_hiddenvar() { +; CHECK: get_hiddenvar: + + %val = load i32* @hiddenvar +; CHECK: adrp x[[HI:[0-9]+]], hiddenvar +; CHECK: ldr w0, [x[[HI]], #:lo12:hiddenvar] + +; CHECK-ELF: R_AARCH64_ADR_PREL_PG_HI21 hiddenvar +; CHECK-ELF: R_AARCH64_LDST32_ABS_LO12_NC hiddenvar + ret i32 %val +} + +define i32* @get_hiddenvaraddr() { +; CHECK: get_hiddenvaraddr: + + %val = load i32* @hiddenvar +; CHECK: adrp [[HI:x[0-9]+]], hiddenvar +; CHECK: add x0, [[HI]], #:lo12:hiddenvar + +; CHECK-ELF: R_AARCH64_ADR_PREL_PG_HI21 hiddenvar +; CHECK-ELF: R_AARCH64_ADD_ABS_LO12_NC hiddenvar + ret i32* @hiddenvar +} + +define void()* @get_func() { +; CHECK: get_func: + + ret void()* bitcast(void()*()* @get_func to void()*) +; CHECK: adrp x[[GOTHI:[0-9]+]], :got:get_func +; CHECK: ldr x0, [x[[GOTHI]], #:got_lo12:get_func] + + ; Particularly important that the ADRP gets a relocation, LLVM tends to think + ; it can relax it because it knows where get_func is. It can't! +; CHECK-ELF: R_AARCH64_ADR_GOT_PAGE get_func +; CHECK-ELF: R_AARCH64_LD64_GOT_LO12_NC get_func +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/bitfield-insert-0.ll b/test/CodeGen/AArch64/bitfield-insert-0.ll new file mode 100644 index 000000000000..d1191f6aaa8a --- /dev/null +++ b/test/CodeGen/AArch64/bitfield-insert-0.ll @@ -0,0 +1,19 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -filetype=obj < %s | llvm-objdump -disassemble - | FileCheck %s + +; The encoding of lsb -> immr in the CGed bitfield instructions was wrong at one +; point, in the edge case where lsb = 0. Just make sure. + +define void @test_bfi0(i32* %existing, i32* %new) { +; CHECK: bfxil {{w[0-9]+}}, {{w[0-9]+}}, #0, #18 + + %oldval = load volatile i32* %existing + %oldval_keep = and i32 %oldval, 4294705152 ; 0xfffc_0000 + + %newval = load volatile i32* %new + %newval_masked = and i32 %newval, 262143 ; = 0x0003_ffff + + %combined = or i32 %newval_masked, %oldval_keep + store volatile i32 %combined, i32* %existing + + ret void +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/bitfield-insert.ll b/test/CodeGen/AArch64/bitfield-insert.ll new file mode 100644 index 000000000000..3e871b9a6d27 --- /dev/null +++ b/test/CodeGen/AArch64/bitfield-insert.ll @@ -0,0 +1,193 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +; First, a simple example from Clang. The registers could plausibly be +; different, but probably won't be. + +%struct.foo = type { i8, [2 x i8], i8 } + +define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone { +; CHECK: from_clang: +; CHECK: bfi w0, w1, #3, #4 +; CHECK-NEXT: ret + +entry: + %f.coerce.fca.0.extract = extractvalue [1 x i64] %f.coerce, 0 + %tmp.sroa.0.0.extract.trunc = trunc i64 %f.coerce.fca.0.extract to i32 + %bf.value = shl i32 %n, 3 + %0 = and i32 %bf.value, 120 + %f.sroa.0.0.insert.ext.masked = and i32 %tmp.sroa.0.0.extract.trunc, 135 + %1 = or i32 %f.sroa.0.0.insert.ext.masked, %0 + %f.sroa.0.0.extract.trunc = zext i32 %1 to i64 + %tmp1.sroa.1.1.insert.insert = and i64 %f.coerce.fca.0.extract, 4294967040 + %tmp1.sroa.0.0.insert.insert = or i64 %f.sroa.0.0.extract.trunc, %tmp1.sroa.1.1.insert.insert + %.fca.0.insert = insertvalue [1 x i64] undef, i64 %tmp1.sroa.0.0.insert.insert, 0 + ret [1 x i64] %.fca.0.insert +} + +define void @test_whole32(i32* %existing, i32* %new) { +; CHECK: test_whole32: +; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5 + + %oldval = load volatile i32* %existing + %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff + + %newval = load volatile i32* %new + %newval_shifted = shl i32 %newval, 26 + %newval_masked = and i32 %newval_shifted, 2080374784 ; = 0x7c000000 + + %combined = or i32 %oldval_keep, %newval_masked + store volatile i32 %combined, i32* %existing + + ret void +} + +define void @test_whole64(i64* %existing, i64* %new) { +; CHECK: test_whole64: +; CHECK: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14 +; CHECK-NOT: and +; CHECK: ret + + %oldval = load volatile i64* %existing + %oldval_keep = and i64 %oldval, 18446742974265032703 ; = 0xffffff0003ffffffL + + %newval = load volatile i64* %new + %newval_shifted = shl i64 %newval, 26 + %newval_masked = and i64 %newval_shifted, 1099444518912 ; = 0xfffc000000 + + %combined = or i64 %oldval_keep, %newval_masked + store volatile i64 %combined, i64* %existing + + ret void +} + +define void @test_whole32_from64(i64* %existing, i64* %new) { +; CHECK: test_whole32_from64: +; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #{{0|16}}, #16 +; CHECK-NOT: and +; CHECK: ret + + %oldval = load volatile i64* %existing + %oldval_keep = and i64 %oldval, 4294901760 ; = 0xffff0000 + + %newval = load volatile i64* %new + %newval_masked = and i64 %newval, 65535 ; = 0xffff + + %combined = or i64 %oldval_keep, %newval_masked + store volatile i64 %combined, i64* %existing + + ret void +} + +define void @test_32bit_masked(i32 *%existing, i32 *%new) { +; CHECK: test_32bit_masked: +; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4 +; CHECK: and {{w[0-9]+}}, [[INSERT]], #0xff + + %oldval = load volatile i32* %existing + %oldval_keep = and i32 %oldval, 135 ; = 0x87 + + %newval = load volatile i32* %new + %newval_shifted = shl i32 %newval, 3 + %newval_masked = and i32 %newval_shifted, 120 ; = 0x78 + + %combined = or i32 %oldval_keep, %newval_masked + store volatile i32 %combined, i32* %existing + + ret void +} + +define void @test_64bit_masked(i64 *%existing, i64 *%new) { +; CHECK: test_64bit_masked: +; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8 +; CHECK: and {{x[0-9]+}}, [[INSERT]], #0xffff00000000 + + %oldval = load volatile i64* %existing + %oldval_keep = and i64 %oldval, 1095216660480 ; = 0xff_0000_0000 + + %newval = load volatile i64* %new + %newval_shifted = shl i64 %newval, 40 + %newval_masked = and i64 %newval_shifted, 280375465082880 ; = 0xff00_0000_0000 + + %combined = or i64 %newval_masked, %oldval_keep + store volatile i64 %combined, i64* %existing + + ret void +} + +; Mask is too complicated for literal ANDwwi, make sure other avenues are tried. +define void @test_32bit_complexmask(i32 *%existing, i32 *%new) { +; CHECK: test_32bit_complexmask: +; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4 +; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + + %oldval = load volatile i32* %existing + %oldval_keep = and i32 %oldval, 647 ; = 0x287 + + %newval = load volatile i32* %new + %newval_shifted = shl i32 %newval, 3 + %newval_masked = and i32 %newval_shifted, 120 ; = 0x278 + + %combined = or i32 %oldval_keep, %newval_masked + store volatile i32 %combined, i32* %existing + + ret void +} + +; Neither mask is is a contiguous set of 1s. BFI can't be used +define void @test_32bit_badmask(i32 *%existing, i32 *%new) { +; CHECK: test_32bit_badmask: +; CHECK-NOT: bfi +; CHECK: ret + + %oldval = load volatile i32* %existing + %oldval_keep = and i32 %oldval, 135 ; = 0x87 + + %newval = load volatile i32* %new + %newval_shifted = shl i32 %newval, 3 + %newval_masked = and i32 %newval_shifted, 632 ; = 0x278 + + %combined = or i32 %oldval_keep, %newval_masked + store volatile i32 %combined, i32* %existing + + ret void +} + +; Ditto +define void @test_64bit_badmask(i64 *%existing, i64 *%new) { +; CHECK: test_64bit_badmask: +; CHECK-NOT: bfi +; CHECK: ret + + %oldval = load volatile i64* %existing + %oldval_keep = and i64 %oldval, 135 ; = 0x87 + + %newval = load volatile i64* %new + %newval_shifted = shl i64 %newval, 3 + %newval_masked = and i64 %newval_shifted, 664 ; = 0x278 + + %combined = or i64 %oldval_keep, %newval_masked + store volatile i64 %combined, i64* %existing + + ret void +} + +; Bitfield insert where there's a left-over shr needed at the beginning +; (e.g. result of str.bf1 = str.bf2) +define void @test_32bit_with_shr(i32* %existing, i32* %new) { +; CHECK: test_32bit_with_shr: + + %oldval = load volatile i32* %existing + %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff + + %newval = load i32* %new + %newval_shifted = shl i32 %newval, 12 + %newval_masked = and i32 %newval_shifted, 2080374784 ; = 0x7c000000 + + %combined = or i32 %oldval_keep, %newval_masked + store volatile i32 %combined, i32* %existing +; CHECK: lsr [[BIT:w[0-9]+]], {{w[0-9]+}}, #14 +; CHECK: bfi {{w[0-9]}}, [[BIT]], #26, #5 + + ret void +} + diff --git a/test/CodeGen/AArch64/bitfield.ll b/test/CodeGen/AArch64/bitfield.ll new file mode 100644 index 000000000000..36d337ef05ef --- /dev/null +++ b/test/CodeGen/AArch64/bitfield.ll @@ -0,0 +1,218 @@ + +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var32 = global i32 0 +@var64 = global i64 0 + +define void @test_extendb(i8 %var) { +; CHECK: test_extendb: + + %sxt32 = sext i8 %var to i32 + store volatile i32 %sxt32, i32* @var32 +; CHECK: sxtb {{w[0-9]+}}, {{w[0-9]+}} + + %sxt64 = sext i8 %var to i64 + store volatile i64 %sxt64, i64* @var64 +; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}} + +; N.b. this doesn't actually produce a bitfield instruction at the +; moment, but it's still a good test to have and the semantics are +; correct. + %uxt32 = zext i8 %var to i32 + store volatile i32 %uxt32, i32* @var32 +; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xff + + %uxt64 = zext i8 %var to i64 + store volatile i64 %uxt64, i64* @var64 +; CHECK: uxtb {{x[0-9]+}}, {{w[0-9]+}} + ret void +} + +define void @test_extendh(i16 %var) { +; CHECK: test_extendh: + + %sxt32 = sext i16 %var to i32 + store volatile i32 %sxt32, i32* @var32 +; CHECK: sxth {{w[0-9]+}}, {{w[0-9]+}} + + %sxt64 = sext i16 %var to i64 + store volatile i64 %sxt64, i64* @var64 +; CHECK: sxth {{x[0-9]+}}, {{w[0-9]+}} + +; N.b. this doesn't actually produce a bitfield instruction at the +; moment, but it's still a good test to have and the semantics are +; correct. + %uxt32 = zext i16 %var to i32 + store volatile i32 %uxt32, i32* @var32 +; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff + + %uxt64 = zext i16 %var to i64 + store volatile i64 %uxt64, i64* @var64 +; CHECK: uxth {{x[0-9]+}}, {{w[0-9]+}} + ret void +} + +define void @test_extendw(i32 %var) { +; CHECK: test_extendw: + + %sxt64 = sext i32 %var to i64 + store volatile i64 %sxt64, i64* @var64 +; CHECK: sxtw {{x[0-9]+}}, {{w[0-9]+}} + + %uxt64 = zext i32 %var to i64 + store volatile i64 %uxt64, i64* @var64 +; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #0, #32 + ret void +} + +define void @test_shifts(i32 %val32, i64 %val64) { +; CHECK: test_shifts: + + %shift1 = ashr i32 %val32, 31 + store volatile i32 %shift1, i32* @var32 +; CHECK: asr {{w[0-9]+}}, {{w[0-9]+}}, #31 + + %shift2 = lshr i32 %val32, 8 + store volatile i32 %shift2, i32* @var32 +; CHECK: lsr {{w[0-9]+}}, {{w[0-9]+}}, #8 + + %shift3 = shl i32 %val32, 1 + store volatile i32 %shift3, i32* @var32 +; CHECK: lsl {{w[0-9]+}}, {{w[0-9]+}}, #1 + + %shift4 = ashr i64 %val64, 31 + store volatile i64 %shift4, i64* @var64 +; CHECK: asr {{x[0-9]+}}, {{x[0-9]+}}, #31 + + %shift5 = lshr i64 %val64, 8 + store volatile i64 %shift5, i64* @var64 +; CHECK: lsr {{x[0-9]+}}, {{x[0-9]+}}, #8 + + %shift6 = shl i64 %val64, 63 + store volatile i64 %shift6, i64* @var64 +; CHECK: lsl {{x[0-9]+}}, {{x[0-9]+}}, #63 + + %shift7 = ashr i64 %val64, 63 + store volatile i64 %shift7, i64* @var64 +; CHECK: asr {{x[0-9]+}}, {{x[0-9]+}}, #63 + + %shift8 = lshr i64 %val64, 63 + store volatile i64 %shift8, i64* @var64 +; CHECK: lsr {{x[0-9]+}}, {{x[0-9]+}}, #63 + + %shift9 = lshr i32 %val32, 31 + store volatile i32 %shift9, i32* @var32 +; CHECK: lsr {{w[0-9]+}}, {{w[0-9]+}}, #31 + + %shift10 = shl i32 %val32, 31 + store volatile i32 %shift10, i32* @var32 +; CHECK: lsl {{w[0-9]+}}, {{w[0-9]+}}, #31 + + ret void +} + +; LLVM can produce in-register extensions taking place entirely with +; 64-bit registers too. +define void @test_sext_inreg_64(i64 %in) { +; CHECK: test_sext_inreg_64: + +; i1 doesn't have an official alias, but crops up and is handled by +; the bitfield ops. + %trunc_i1 = trunc i64 %in to i1 + %sext_i1 = sext i1 %trunc_i1 to i64 + store volatile i64 %sext_i1, i64* @var64 +; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1 + + %trunc_i8 = trunc i64 %in to i8 + %sext_i8 = sext i8 %trunc_i8 to i64 + store volatile i64 %sext_i8, i64* @var64 +; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}} + + %trunc_i16 = trunc i64 %in to i16 + %sext_i16 = sext i16 %trunc_i16 to i64 + store volatile i64 %sext_i16, i64* @var64 +; CHECK: sxth {{x[0-9]+}}, {{w[0-9]+}} + + %trunc_i32 = trunc i64 %in to i32 + %sext_i32 = sext i32 %trunc_i32 to i64 + store volatile i64 %sext_i32, i64* @var64 +; CHECK: sxtw {{x[0-9]+}}, {{w[0-9]+}} + ret void +} + +; These instructions don't actually select to official bitfield +; operations, but it's important that we select them somehow: +define void @test_zext_inreg_64(i64 %in) { +; CHECK: test_zext_inreg_64: + + %trunc_i8 = trunc i64 %in to i8 + %zext_i8 = zext i8 %trunc_i8 to i64 + store volatile i64 %zext_i8, i64* @var64 +; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xff + + %trunc_i16 = trunc i64 %in to i16 + %zext_i16 = zext i16 %trunc_i16 to i64 + store volatile i64 %zext_i16, i64* @var64 +; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffff + + %trunc_i32 = trunc i64 %in to i32 + %zext_i32 = zext i32 %trunc_i32 to i64 + store volatile i64 %zext_i32, i64* @var64 +; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffffffff + + ret void +} + +define i64 @test_sext_inreg_from_32(i32 %in) { +; CHECK: test_sext_inreg_from_32: + + %small = trunc i32 %in to i1 + %ext = sext i1 %small to i64 + + ; Different registers are of course, possible, though suboptimal. This is + ; making sure that a 64-bit "(sext_inreg (anyext GPR32), i1)" uses the 64-bit + ; sbfx rather than just 32-bits. +; CHECK: sbfx x0, x0, #0, #1 + ret i64 %ext +} + + +define i32 @test_ubfx32(i32* %addr) { +; CHECK: test_ubfx32: +; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3 + + %fields = load i32* %addr + %shifted = lshr i32 %fields, 23 + %masked = and i32 %shifted, 7 + ret i32 %masked +} + +define i64 @test_ubfx64(i64* %addr) { +; CHECK: test_ubfx64: +; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10 + + %fields = load i64* %addr + %shifted = lshr i64 %fields, 25 + %masked = and i64 %shifted, 1023 + ret i64 %masked +} + +define i32 @test_sbfx32(i32* %addr) { +; CHECK: test_sbfx32: +; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3 + + %fields = load i32* %addr + %shifted = shl i32 %fields, 23 + %extended = ashr i32 %shifted, 29 + ret i32 %extended +} + +define i64 @test_sbfx64(i64* %addr) { +; CHECK: test_sbfx64: +; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63 + + %fields = load i64* %addr + %shifted = shl i64 %fields, 1 + %extended = ashr i64 %shifted, 1 + ret i64 %extended +} diff --git a/test/CodeGen/AArch64/blockaddress.ll b/test/CodeGen/AArch64/blockaddress.ll new file mode 100644 index 000000000000..3d0a5cf96bcd --- /dev/null +++ b/test/CodeGen/AArch64/blockaddress.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +@addr = global i8* null + +define void @test_blockaddress() { +; CHECK: test_blockaddress: + store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr + %val = load volatile i8** @addr + indirectbr i8* %val, [label %block] +; CHECK: adrp [[DEST_HI:x[0-9]+]], [[DEST_LBL:.Ltmp[0-9]+]] +; CHECK: add [[DEST:x[0-9]+]], [[DEST_HI]], #:lo12:[[DEST_LBL]] +; CHECK: str [[DEST]], +; CHECK: ldr [[NEWDEST:x[0-9]+]] +; CHECK: br [[NEWDEST]] + +block: + ret void +} diff --git a/test/CodeGen/AArch64/bool-loads.ll b/test/CodeGen/AArch64/bool-loads.ll new file mode 100644 index 000000000000..5c7640bc4218 --- /dev/null +++ b/test/CodeGen/AArch64/bool-loads.ll @@ -0,0 +1,55 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +@var = global i1 0 + +define i32 @test_sextloadi32() { +; CHECK: test_sextloadi32 + + %val = load i1* @var + %ret = sext i1 %val to i32 +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var] +; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1 + + ret i32 %ret +; CHECK: ret +} + +define i64 @test_sextloadi64() { +; CHECK: test_sextloadi64 + + %val = load i1* @var + %ret = sext i1 %val to i64 +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var] +; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1 + + ret i64 %ret +; CHECK: ret +} + +define i32 @test_zextloadi32() { +; CHECK: test_zextloadi32 + +; It's not actually necessary that "ret" is next, but as far as LLVM +; is concerned only 0 or 1 should be loadable so no extension is +; necessary. + %val = load i1* @var + %ret = zext i1 %val to i32 +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var] + + ret i32 %ret +; CHECK-NEXT: ret +} + +define i64 @test_zextloadi64() { +; CHECK: test_zextloadi64 + +; It's not actually necessary that "ret" is next, but as far as LLVM +; is concerned only 0 or 1 should be loadable so no extension is +; necessary. + %val = load i1* @var + %ret = zext i1 %val to i64 +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var] + + ret i64 %ret +; CHECK-NEXT: ret +} diff --git a/test/CodeGen/AArch64/breg.ll b/test/CodeGen/AArch64/breg.ll new file mode 100644 index 000000000000..38ed4734e1b4 --- /dev/null +++ b/test/CodeGen/AArch64/breg.ll @@ -0,0 +1,17 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@stored_label = global i8* null + +define void @foo() { +; CHECK: foo: + %lab = load i8** @stored_label + indirectbr i8* %lab, [label %otherlab, label %retlab] +; CHECK: adrp {{x[0-9]+}}, stored_label +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:stored_label] +; CHECK: br {{x[0-9]+}} + +otherlab: + ret void +retlab: + ret void +} diff --git a/test/CodeGen/AArch64/callee-save.ll b/test/CodeGen/AArch64/callee-save.ll new file mode 100644 index 000000000000..c66aa5bfc510 --- /dev/null +++ b/test/CodeGen/AArch64/callee-save.ll @@ -0,0 +1,86 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var = global float 0.0 + +define void @foo() { +; CHECK: foo: + +; CHECK: stp d14, d15, [sp +; CHECK: stp d12, d13, [sp +; CHECK: stp d10, d11, [sp +; CHECK: stp d8, d9, [sp + + ; Create lots of live variables to exhaust the supply of + ; caller-saved registers + %val1 = load volatile float* @var + %val2 = load volatile float* @var + %val3 = load volatile float* @var + %val4 = load volatile float* @var + %val5 = load volatile float* @var + %val6 = load volatile float* @var + %val7 = load volatile float* @var + %val8 = load volatile float* @var + %val9 = load volatile float* @var + %val10 = load volatile float* @var + %val11 = load volatile float* @var + %val12 = load volatile float* @var + %val13 = load volatile float* @var + %val14 = load volatile float* @var + %val15 = load volatile float* @var + %val16 = load volatile float* @var + %val17 = load volatile float* @var + %val18 = load volatile float* @var + %val19 = load volatile float* @var + %val20 = load volatile float* @var + %val21 = load volatile float* @var + %val22 = load volatile float* @var + %val23 = load volatile float* @var + %val24 = load volatile float* @var + %val25 = load volatile float* @var + %val26 = load volatile float* @var + %val27 = load volatile float* @var + %val28 = load volatile float* @var + %val29 = load volatile float* @var + %val30 = load volatile float* @var + %val31 = load volatile float* @var + %val32 = load volatile float* @var + + store volatile float %val1, float* @var + store volatile float %val2, float* @var + store volatile float %val3, float* @var + store volatile float %val4, float* @var + store volatile float %val5, float* @var + store volatile float %val6, float* @var + store volatile float %val7, float* @var + store volatile float %val8, float* @var + store volatile float %val9, float* @var + store volatile float %val10, float* @var + store volatile float %val11, float* @var + store volatile float %val12, float* @var + store volatile float %val13, float* @var + store volatile float %val14, float* @var + store volatile float %val15, float* @var + store volatile float %val16, float* @var + store volatile float %val17, float* @var + store volatile float %val18, float* @var + store volatile float %val19, float* @var + store volatile float %val20, float* @var + store volatile float %val21, float* @var + store volatile float %val22, float* @var + store volatile float %val23, float* @var + store volatile float %val24, float* @var + store volatile float %val25, float* @var + store volatile float %val26, float* @var + store volatile float %val27, float* @var + store volatile float %val28, float* @var + store volatile float %val29, float* @var + store volatile float %val30, float* @var + store volatile float %val31, float* @var + store volatile float %val32, float* @var + +; CHECK: ldp d8, d9, [sp +; CHECK: ldp d10, d11, [sp +; CHECK: ldp d12, d13, [sp +; CHECK: ldp d14, d15, [sp + ret void +} diff --git a/test/CodeGen/AArch64/compare-branch.ll b/test/CodeGen/AArch64/compare-branch.ll new file mode 100644 index 000000000000..4213110497d3 --- /dev/null +++ b/test/CodeGen/AArch64/compare-branch.ll @@ -0,0 +1,38 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var32 = global i32 0 +@var64 = global i64 0 + +define void @foo() { +; CHECK: foo: + + %val1 = load volatile i32* @var32 + %tst1 = icmp eq i32 %val1, 0 + br i1 %tst1, label %end, label %test2 +; CHECK: cbz {{w[0-9]+}}, .LBB + +test2: + %val2 = load volatile i32* @var32 + %tst2 = icmp ne i32 %val2, 0 + br i1 %tst2, label %end, label %test3 +; CHECK: cbnz {{w[0-9]+}}, .LBB + +test3: + %val3 = load volatile i64* @var64 + %tst3 = icmp eq i64 %val3, 0 + br i1 %tst3, label %end, label %test4 +; CHECK: cbz {{x[0-9]+}}, .LBB + +test4: + %val4 = load volatile i64* @var64 + %tst4 = icmp ne i64 %val4, 0 + br i1 %tst4, label %end, label %test5 +; CHECK: cbnz {{x[0-9]+}}, .LBB + +test5: + store volatile i64 %val4, i64* @var64 + ret void + +end: + ret void +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/cond-sel.ll b/test/CodeGen/AArch64/cond-sel.ll new file mode 100644 index 000000000000..3051cf53fdf8 --- /dev/null +++ b/test/CodeGen/AArch64/cond-sel.ll @@ -0,0 +1,213 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var32 = global i32 0 +@var64 = global i64 0 + +define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) { +; CHECK: test_csel: + + %tst1 = icmp ugt i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, i32 42, i32 52 + store i32 %val1, i32* @var32 +; CHECK: movz [[W52:w[0-9]+]], #52 +; CHECK: movz [[W42:w[0-9]+]], #42 +; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi + + %rhs64 = sext i32 %rhs32 to i64 + %tst2 = icmp sle i64 %lhs64, %rhs64 + %val2 = select i1 %tst2, i64 %lhs64, i64 %rhs64 + store i64 %val2, i64* @var64 +; CHECK: cmp [[LHS:x[0-9]+]], [[RHS:w[0-9]+]], sxtw +; CHECK: sxtw [[EXT_RHS:x[0-9]+]], [[RHS]] +; CHECK: csel {{x[0-9]+}}, [[LHS]], [[EXT_RHS]], le + + ret void +; CHECK: ret +} + +define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %rhs64) { +; CHECK: test_floatcsel: + + %tst1 = fcmp one float %lhs32, %rhs32 +; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}} + %val1 = select i1 %tst1, i32 42, i32 52 + store i32 %val1, i32* @var32 +; CHECK: movz [[W52:w[0-9]+]], #52 +; CHECK: movz [[W42:w[0-9]+]], #42 +; CHECK: csel [[MAYBETRUE:w[0-9]+]], [[W42]], [[W52]], mi +; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt + + + %tst2 = fcmp ueq double %lhs64, %rhs64 +; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}} + %val2 = select i1 %tst2, i64 9, i64 15 + store i64 %val2, i64* @var64 +; CHECK: movz [[CONST15:x[0-9]+]], #15 +; CHECK: movz [[CONST9:x[0-9]+]], #9 +; CHECK: csel [[MAYBETRUE:x[0-9]+]], [[CONST9]], [[CONST15]], eq +; CHECK: csel {{x[0-9]+}}, [[CONST9]], [[MAYBETRUE]], vs + + ret void +; CHECK: ret +} + + +define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) { +; CHECK: test_csinc: + +; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). + %tst1 = icmp ugt i32 %lhs32, %rhs32 + %inc1 = add i32 %rhs32, 1 + %val1 = select i1 %tst1, i32 %inc1, i32 %lhs32 + store volatile i32 %val1, i32* @var32 +; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]] +; CHECK: csinc {{w[0-9]+}}, [[LHS]], [[RHS]], ls + + %rhs2 = add i32 %rhs32, 42 + %tst2 = icmp sle i32 %lhs32, %rhs2 + %inc2 = add i32 %rhs32, 1 + %val2 = select i1 %tst2, i32 %lhs32, i32 %inc2 + store volatile i32 %val2, i32* @var32 +; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}} +; CHECK: csinc {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le + +; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). + %rhs3 = sext i32 %rhs32 to i64 + %tst3 = icmp ugt i64 %lhs64, %rhs3 + %inc3 = add i64 %rhs3, 1 + %val3 = select i1 %tst3, i64 %inc3, i64 %lhs64 + store volatile i64 %val3, i64* @var64 +; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}} +; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls + + %rhs4 = zext i32 %rhs32 to i64 + %tst4 = icmp sle i64 %lhs64, %rhs4 + %inc4 = add i64 %rhs4, 1 + %val4 = select i1 %tst4, i64 %lhs64, i64 %inc4 + store volatile i64 %val4, i64* @var64 +; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}} +; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le + + ret void +; CHECK: ret +} + +define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) { +; CHECK: test_csinv: + +; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). + %tst1 = icmp ugt i32 %lhs32, %rhs32 + %inc1 = xor i32 -1, %rhs32 + %val1 = select i1 %tst1, i32 %inc1, i32 %lhs32 + store volatile i32 %val1, i32* @var32 +; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]] +; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls + + %rhs2 = add i32 %rhs32, 42 + %tst2 = icmp sle i32 %lhs32, %rhs2 + %inc2 = xor i32 -1, %rhs32 + %val2 = select i1 %tst2, i32 %lhs32, i32 %inc2 + store volatile i32 %val2, i32* @var32 +; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}} +; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le + +; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). + %rhs3 = sext i32 %rhs32 to i64 + %tst3 = icmp ugt i64 %lhs64, %rhs3 + %inc3 = xor i64 -1, %rhs3 + %val3 = select i1 %tst3, i64 %inc3, i64 %lhs64 + store volatile i64 %val3, i64* @var64 +; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}} +; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls + + %rhs4 = zext i32 %rhs32 to i64 + %tst4 = icmp sle i64 %lhs64, %rhs4 + %inc4 = xor i64 -1, %rhs4 + %val4 = select i1 %tst4, i64 %lhs64, i64 %inc4 + store volatile i64 %val4, i64* @var64 +; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}} +; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le + + ret void +; CHECK: ret +} + +define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) { +; CHECK: test_csneg: + +; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). + %tst1 = icmp ugt i32 %lhs32, %rhs32 + %inc1 = sub i32 0, %rhs32 + %val1 = select i1 %tst1, i32 %inc1, i32 %lhs32 + store volatile i32 %val1, i32* @var32 +; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]] +; CHECK: csneg {{w[0-9]+}}, [[LHS]], [[RHS]], ls + + %rhs2 = add i32 %rhs32, 42 + %tst2 = icmp sle i32 %lhs32, %rhs2 + %inc2 = sub i32 0, %rhs32 + %val2 = select i1 %tst2, i32 %lhs32, i32 %inc2 + store volatile i32 %val2, i32* @var32 +; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}} +; CHECK: csneg {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le + +; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). + %rhs3 = sext i32 %rhs32 to i64 + %tst3 = icmp ugt i64 %lhs64, %rhs3 + %inc3 = sub i64 0, %rhs3 + %val3 = select i1 %tst3, i64 %inc3, i64 %lhs64 + store volatile i64 %val3, i64* @var64 +; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}} +; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls + + %rhs4 = zext i32 %rhs32 to i64 + %tst4 = icmp sle i64 %lhs64, %rhs4 + %inc4 = sub i64 0, %rhs4 + %val4 = select i1 %tst4, i64 %lhs64, i64 %inc4 + store volatile i64 %val4, i64* @var64 +; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}} +; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le + + ret void +; CHECK: ret +} + +define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) { +; CHECK: test_cset: + +; N.b. code is not optimal here (32-bit csinc would be better) but +; incoming DAG is too complex + %tst1 = icmp eq i32 %lhs, %rhs + %val1 = zext i1 %tst1 to i32 + store i32 %val1, i32* @var32 +; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}} +; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ne + + %rhs64 = sext i32 %rhs to i64 + %tst2 = icmp ule i64 %lhs64, %rhs64 + %val2 = zext i1 %tst2 to i64 + store i64 %val2, i64* @var64 +; CHECK: csinc {{w[0-9]+}}, wzr, wzr, hi + + ret void +; CHECK: ret +} + +define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) { +; CHECK: test_csetm: + + %tst1 = icmp eq i32 %lhs, %rhs + %val1 = sext i1 %tst1 to i32 + store i32 %val1, i32* @var32 +; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}} +; CHECK: csinv {{w[0-9]+}}, wzr, wzr, ne + + %rhs64 = sext i32 %rhs to i64 + %tst2 = icmp ule i64 %lhs64, %rhs64 + %val2 = sext i1 %tst2 to i64 + store i64 %val2, i64* @var64 +; CHECK: csinv {{x[0-9]+}}, xzr, xzr, hi + + ret void +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/directcond.ll b/test/CodeGen/AArch64/directcond.ll new file mode 100644 index 000000000000..f5d57593bfad --- /dev/null +++ b/test/CodeGen/AArch64/directcond.ll @@ -0,0 +1,84 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) { +; CHECK: test_select_i32: + %val = select i1 %bit, i32 %a, i32 %b +; CHECK: movz [[ONE:w[0-9]+]], #1 +; CHECK: tst w0, [[ONE]] +; CHECK-NEXT: csel w0, w1, w2, ne + + ret i32 %val +} + +define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) { +; CHECK: test_select_i64: + %val = select i1 %bit, i64 %a, i64 %b +; CHECK: movz [[ONE:w[0-9]+]], #1 +; CHECK: tst w0, [[ONE]] +; CHECK-NEXT: csel x0, x1, x2, ne + + ret i64 %val +} + +define float @test_select_float(i1 %bit, float %a, float %b) { +; CHECK: test_select_float: + %val = select i1 %bit, float %a, float %b +; CHECK: movz [[ONE:w[0-9]+]], #1 +; CHECK: tst w0, [[ONE]] +; CHECK-NEXT: fcsel s0, s0, s1, ne + + ret float %val +} + +define double @test_select_double(i1 %bit, double %a, double %b) { +; CHECK: test_select_double: + %val = select i1 %bit, double %a, double %b +; CHECK: movz [[ONE:w[0-9]+]], #1 +; CHECK: tst w0, [[ONE]] +; CHECK-NEXT: fcsel d0, d0, d1, ne + + ret double %val +} + +define i32 @test_brcond(i1 %bit) { +; CHECK: test_brcond: + br i1 %bit, label %true, label %false +; CHECK: tbz {{w[0-9]+}}, #0, .LBB + +true: + ret i32 0 +false: + ret i32 42 +} + +define i1 @test_setcc_float(float %lhs, float %rhs) { +; CHECK: test_setcc_float + %val = fcmp oeq float %lhs, %rhs +; CHECK: fcmp s0, s1 +; CHECK: csinc w0, wzr, wzr, ne + ret i1 %val +} + +define i1 @test_setcc_double(double %lhs, double %rhs) { +; CHECK: test_setcc_double + %val = fcmp oeq double %lhs, %rhs +; CHECK: fcmp d0, d1 +; CHECK: csinc w0, wzr, wzr, ne + ret i1 %val +} + +define i1 @test_setcc_i32(i32 %lhs, i32 %rhs) { +; CHECK: test_setcc_i32 + %val = icmp ugt i32 %lhs, %rhs +; CHECK: cmp w0, w1 +; CHECK: csinc w0, wzr, wzr, ls + ret i1 %val +} + +define i1 @test_setcc_i64(i64 %lhs, i64 %rhs) { +; CHECK: test_setcc_i64 + %val = icmp ne i64 %lhs, %rhs +; CHECK: cmp x0, x1 +; CHECK: csinc w0, wzr, wzr, eq + ret i1 %val +} diff --git a/test/CodeGen/AArch64/dp-3source.ll b/test/CodeGen/AArch64/dp-3source.ll new file mode 100644 index 000000000000..c40d3933b44b --- /dev/null +++ b/test/CodeGen/AArch64/dp-3source.ll @@ -0,0 +1,163 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) { +; CHECK: test_madd32: + %mid = mul i32 %val1, %val2 + %res = add i32 %val0, %mid +; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + ret i32 %res +} + +define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) { +; CHECK: test_madd64: + %mid = mul i64 %val1, %val2 + %res = add i64 %val0, %mid +; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + ret i64 %res +} + +define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) { +; CHECK: test_msub32: + %mid = mul i32 %val1, %val2 + %res = sub i32 %val0, %mid +; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + ret i32 %res +} + +define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) { +; CHECK: test_msub64: + %mid = mul i64 %val1, %val2 + %res = sub i64 %val0, %mid +; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + ret i64 %res +} + +define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) { +; CHECK: test_smaddl: + %ext1 = sext i32 %val1 to i64 + %ext2 = sext i32 %val2 to i64 + %prod = mul i64 %ext1, %ext2 + %res = add i64 %acc, %prod +; CHECK: smaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}} + ret i64 %res +} + +define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) { +; CHECK: test_smsubl: + %ext1 = sext i32 %val1 to i64 + %ext2 = sext i32 %val2 to i64 + %prod = mul i64 %ext1, %ext2 + %res = sub i64 %acc, %prod +; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}} + ret i64 %res +} + +define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) { +; CHECK: test_umaddl: + %ext1 = zext i32 %val1 to i64 + %ext2 = zext i32 %val2 to i64 + %prod = mul i64 %ext1, %ext2 + %res = add i64 %acc, %prod +; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}} + ret i64 %res +} + +define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) { +; CHECK: test_umsubl: + %ext1 = zext i32 %val1 to i64 + %ext2 = zext i32 %val2 to i64 + %prod = mul i64 %ext1, %ext2 + %res = sub i64 %acc, %prod +; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}} + ret i64 %res +} + +define i64 @test_smulh(i64 %lhs, i64 %rhs) { +; CHECK: test_smulh: + %ext1 = sext i64 %lhs to i128 + %ext2 = sext i64 %rhs to i128 + %res = mul i128 %ext1, %ext2 + %high = lshr i128 %res, 64 + %val = trunc i128 %high to i64 +; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + ret i64 %val +} + +define i64 @test_umulh(i64 %lhs, i64 %rhs) { +; CHECK: test_umulh: + %ext1 = zext i64 %lhs to i128 + %ext2 = zext i64 %rhs to i128 + %res = mul i128 %ext1, %ext2 + %high = lshr i128 %res, 64 + %val = trunc i128 %high to i64 +; CHECK: umulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + ret i64 %val +} + +define i32 @test_mul32(i32 %lhs, i32 %rhs) { +; CHECK: test_mul32: + %res = mul i32 %lhs, %rhs +; CHECK: mul {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + ret i32 %res +} + +define i64 @test_mul64(i64 %lhs, i64 %rhs) { +; CHECK: test_mul64: + %res = mul i64 %lhs, %rhs +; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + ret i64 %res +} + +define i32 @test_mneg32(i32 %lhs, i32 %rhs) { +; CHECK: test_mneg32: + %prod = mul i32 %lhs, %rhs + %res = sub i32 0, %prod +; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + ret i32 %res +} + +define i64 @test_mneg64(i64 %lhs, i64 %rhs) { +; CHECK: test_mneg64: + %prod = mul i64 %lhs, %rhs + %res = sub i64 0, %prod +; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + ret i64 %res +} + +define i64 @test_smull(i32 %lhs, i32 %rhs) { +; CHECK: test_smull: + %ext1 = sext i32 %lhs to i64 + %ext2 = sext i32 %rhs to i64 + %res = mul i64 %ext1, %ext2 +; CHECK: smull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + ret i64 %res +} + +define i64 @test_umull(i32 %lhs, i32 %rhs) { +; CHECK: test_umull: + %ext1 = zext i32 %lhs to i64 + %ext2 = zext i32 %rhs to i64 + %res = mul i64 %ext1, %ext2 +; CHECK: umull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + ret i64 %res +} + +define i64 @test_smnegl(i32 %lhs, i32 %rhs) { +; CHECK: test_smnegl: + %ext1 = sext i32 %lhs to i64 + %ext2 = sext i32 %rhs to i64 + %prod = mul i64 %ext1, %ext2 + %res = sub i64 0, %prod +; CHECK: smnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + ret i64 %res +} + +define i64 @test_umnegl(i32 %lhs, i32 %rhs) { +; CHECK: test_umnegl: + %ext1 = zext i32 %lhs to i64 + %ext2 = zext i32 %rhs to i64 + %prod = mul i64 %ext1, %ext2 + %res = sub i64 0, %prod +; CHECK: umnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + ret i64 %res +} diff --git a/test/CodeGen/AArch64/dp1.ll b/test/CodeGen/AArch64/dp1.ll new file mode 100644 index 000000000000..83aa8b4f6631 --- /dev/null +++ b/test/CodeGen/AArch64/dp1.ll @@ -0,0 +1,152 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var32 = global i32 0 +@var64 = global i64 0 + +define void @rev_i32() { +; CHECK: rev_i32: + %val0_tmp = load i32* @var32 + %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp) +; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %val1_tmp, i32* @var32 + ret void +} + +define void @rev_i64() { +; CHECK: rev_i64: + %val0_tmp = load i64* @var64 + %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp) +; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %val1_tmp, i64* @var64 + ret void +} + +define void @rev32_i64() { +; CHECK: rev32_i64: + %val0_tmp = load i64* @var64 + %val1_tmp = shl i64 %val0_tmp, 32 + %val5_tmp = sub i64 64, 32 + %val2_tmp = lshr i64 %val0_tmp, %val5_tmp + %val3_tmp = or i64 %val1_tmp, %val2_tmp + %val4_tmp = call i64 @llvm.bswap.i64(i64 %val3_tmp) +; CHECK: rev32 {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %val4_tmp, i64* @var64 + ret void +} + +define void @rev16_i32() { +; CHECK: rev16_i32: + %val0_tmp = load i32* @var32 + %val1_tmp = shl i32 %val0_tmp, 16 + %val2_tmp = lshr i32 %val0_tmp, 16 + %val3_tmp = or i32 %val1_tmp, %val2_tmp + %val4_tmp = call i32 @llvm.bswap.i32(i32 %val3_tmp) +; CHECK: rev16 {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %val4_tmp, i32* @var32 + ret void +} + +define void @clz_zerodef_i32() { +; CHECK: clz_zerodef_i32: + %val0_tmp = load i32* @var32 + %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0) +; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %val4_tmp, i32* @var32 + ret void +} + +define void @clz_zerodef_i64() { +; CHECK: clz_zerodef_i64: + %val0_tmp = load i64* @var64 + %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0) +; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %val4_tmp, i64* @var64 + ret void +} + +define void @clz_zeroundef_i32() { +; CHECK: clz_zeroundef_i32: + %val0_tmp = load i32* @var32 + %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1) +; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %val4_tmp, i32* @var32 + ret void +} + +define void @clz_zeroundef_i64() { +; CHECK: clz_zeroundef_i64: + %val0_tmp = load i64* @var64 + %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1) +; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %val4_tmp, i64* @var64 + ret void +} + +define void @cttz_zerodef_i32() { +; CHECK: cttz_zerodef_i32: + %val0_tmp = load i32* @var32 + %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0) +; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}} +; CHECK: clz {{w[0-9]+}}, [[REVERSED]] + store volatile i32 %val4_tmp, i32* @var32 + ret void +} + +define void @cttz_zerodef_i64() { +; CHECK: cttz_zerodef_i64: + %val0_tmp = load i64* @var64 + %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0) +; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}} +; CHECK: clz {{x[0-9]+}}, [[REVERSED]] + store volatile i64 %val4_tmp, i64* @var64 + ret void +} + +define void @cttz_zeroundef_i32() { +; CHECK: cttz_zeroundef_i32: + %val0_tmp = load i32* @var32 + %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1) +; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}} +; CHECK: clz {{w[0-9]+}}, [[REVERSED]] + store volatile i32 %val4_tmp, i32* @var32 + ret void +} + +define void @cttz_zeroundef_i64() { +; CHECK: cttz_zeroundef_i64: + %val0_tmp = load i64* @var64 + %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1) +; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}} +; CHECK: clz {{x[0-9]+}}, [[REVERSED]] + store volatile i64 %val4_tmp, i64* @var64 + ret void +} + +; These two are just compilation tests really: the operation's set to Expand in +; ISelLowering. +define void @ctpop_i32() { +; CHECK: ctpop_i32: + %val0_tmp = load i32* @var32 + %val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp) + store volatile i32 %val4_tmp, i32* @var32 + ret void +} + +define void @ctpop_i64() { +; CHECK: ctpop_i64: + %val0_tmp = load i64* @var64 + %val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp) + store volatile i64 %val4_tmp, i64* @var64 + ret void +} + + +declare i32 @llvm.bswap.i32(i32) +declare i64 @llvm.bswap.i64(i64) +declare i32 @llvm.ctlz.i32 (i32, i1) +declare i64 @llvm.ctlz.i64 (i64, i1) +declare i32 @llvm.cttz.i32 (i32, i1) +declare i64 @llvm.cttz.i64 (i64, i1) +declare i32 @llvm.ctpop.i32 (i32) +declare i64 @llvm.ctpop.i64 (i64) + diff --git a/test/CodeGen/AArch64/dp2.ll b/test/CodeGen/AArch64/dp2.ll new file mode 100644 index 000000000000..4c740f6b8623 --- /dev/null +++ b/test/CodeGen/AArch64/dp2.ll @@ -0,0 +1,169 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var32_0 = global i32 0 +@var32_1 = global i32 0 +@var64_0 = global i64 0 +@var64_1 = global i64 0 + +define void @rorv_i64() { +; CHECK: rorv_i64: + %val0_tmp = load i64* @var64_0 + %val1_tmp = load i64* @var64_1 + %val2_tmp = sub i64 64, %val1_tmp + %val3_tmp = shl i64 %val0_tmp, %val2_tmp + %val4_tmp = lshr i64 %val0_tmp, %val1_tmp + %val5_tmp = or i64 %val3_tmp, %val4_tmp +; CHECK: ror {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %val5_tmp, i64* @var64_0 + ret void +} + +define void @asrv_i64() { +; CHECK: asrv_i64: + %val0_tmp = load i64* @var64_0 + %val1_tmp = load i64* @var64_1 + %val4_tmp = ashr i64 %val0_tmp, %val1_tmp +; CHECK: asr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %val4_tmp, i64* @var64_1 + ret void +} + +define void @lsrv_i64() { +; CHECK: lsrv_i64: + %val0_tmp = load i64* @var64_0 + %val1_tmp = load i64* @var64_1 + %val4_tmp = lshr i64 %val0_tmp, %val1_tmp +; CHECK: lsr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %val4_tmp, i64* @var64_0 + ret void +} + +define void @lslv_i64() { +; CHECK: lslv_i64: + %val0_tmp = load i64* @var64_0 + %val1_tmp = load i64* @var64_1 + %val4_tmp = shl i64 %val0_tmp, %val1_tmp +; CHECK: lsl {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %val4_tmp, i64* @var64_1 + ret void +} + +define void @udiv_i64() { +; CHECK: udiv_i64: + %val0_tmp = load i64* @var64_0 + %val1_tmp = load i64* @var64_1 + %val4_tmp = udiv i64 %val0_tmp, %val1_tmp +; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %val4_tmp, i64* @var64_0 + ret void +} + +define void @sdiv_i64() { +; CHECK: sdiv_i64: + %val0_tmp = load i64* @var64_0 + %val1_tmp = load i64* @var64_1 + %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp +; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %val4_tmp, i64* @var64_1 + ret void +} + + +define void @lsrv_i32() { +; CHECK: lsrv_i32: + %val0_tmp = load i32* @var32_0 + %val1_tmp = load i32* @var32_1 + %val2_tmp = add i32 1, %val1_tmp + %val4_tmp = lshr i32 %val0_tmp, %val2_tmp +; CHECK: lsr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %val4_tmp, i32* @var32_0 + ret void +} + +define void @lslv_i32() { +; CHECK: lslv_i32: + %val0_tmp = load i32* @var32_0 + %val1_tmp = load i32* @var32_1 + %val2_tmp = add i32 1, %val1_tmp + %val4_tmp = shl i32 %val0_tmp, %val2_tmp +; CHECK: lsl {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %val4_tmp, i32* @var32_1 + ret void +} + +define void @rorv_i32() { +; CHECK: rorv_i32: + %val0_tmp = load i32* @var32_0 + %val6_tmp = load i32* @var32_1 + %val1_tmp = add i32 1, %val6_tmp + %val2_tmp = sub i32 32, %val1_tmp + %val3_tmp = shl i32 %val0_tmp, %val2_tmp + %val4_tmp = lshr i32 %val0_tmp, %val1_tmp + %val5_tmp = or i32 %val3_tmp, %val4_tmp +; CHECK: ror {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %val5_tmp, i32* @var32_0 + ret void +} + +define void @asrv_i32() { +; CHECK: asrv_i32: + %val0_tmp = load i32* @var32_0 + %val1_tmp = load i32* @var32_1 + %val2_tmp = add i32 1, %val1_tmp + %val4_tmp = ashr i32 %val0_tmp, %val2_tmp +; CHECK: asr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %val4_tmp, i32* @var32_1 + ret void +} + +define void @sdiv_i32() { +; CHECK: sdiv_i32: + %val0_tmp = load i32* @var32_0 + %val1_tmp = load i32* @var32_1 + %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp +; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %val4_tmp, i32* @var32_1 + ret void +} + +define void @udiv_i32() { +; CHECK: udiv_i32: + %val0_tmp = load i32* @var32_0 + %val1_tmp = load i32* @var32_1 + %val4_tmp = udiv i32 %val0_tmp, %val1_tmp +; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %val4_tmp, i32* @var32_0 + ret void +} + +; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2)) +; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions. +define i32 @test_lsl32() { +; CHECK: test_lsl32: + + %val = load i32* @var32_0 + %ret = shl i32 1, %val +; CHECK: lsl {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + + ret i32 %ret +} + +define i32 @test_lsr32() { +; CHECK: test_lsr32: + + %val = load i32* @var32_0 + %ret = lshr i32 1, %val +; CHECK: lsr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + + ret i32 %ret +} + +define i32 @test_asr32(i32 %in) { +; CHECK: test_asr32: + + %val = load i32* @var32_0 + %ret = ashr i32 %in, %val +; CHECK: asr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + + ret i32 %ret +} diff --git a/test/CodeGen/AArch64/elf-extern.ll b/test/CodeGen/AArch64/elf-extern.ll new file mode 100644 index 000000000000..ee89d8d94ba4 --- /dev/null +++ b/test/CodeGen/AArch64/elf-extern.ll @@ -0,0 +1,21 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -filetype=obj | elf-dump | FileCheck %s + +; External symbols are a different concept to global variables but should still +; get relocations and so on when used. + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) + +define i32 @check_extern() { + call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0) + ret i32 0 +} + +; CHECK: .rela.text +; CHECK: ('r_sym', 0x00000009) +; CHECK-NEXT: ('r_type', 0x0000011b) + +; CHECK: .symtab +; CHECK: Symbol 9 +; CHECK-NEXT: memcpy + + diff --git a/test/CodeGen/AArch64/extern-weak.ll b/test/CodeGen/AArch64/extern-weak.ll new file mode 100644 index 000000000000..3d3d8676818a --- /dev/null +++ b/test/CodeGen/AArch64/extern-weak.ll @@ -0,0 +1,35 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -o - < %s | FileCheck %s + +declare extern_weak i32 @var() + +define i32()* @foo() { +; The usual ADRP/ADD pair can't be used for a weak reference because it must +; evaluate to 0 if the symbol is undefined. We use a litpool entry. + ret i32()* @var +; CHECK: .LCPI0_0: +; CHECK-NEXT: .xword var + +; CHECK: ldr x0, [{{x[0-9]+}}, #:lo12:.LCPI0_0] + +} + + +@arr_var = extern_weak global [10 x i32] + +define i32* @bar() { + %addr = getelementptr [10 x i32]* @arr_var, i32 0, i32 5 +; CHECK: .LCPI1_0: +; CHECK-NEXT: .xword arr_var + +; CHECK: ldr [[BASE:x[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI1_0] +; CHECK: add x0, [[BASE]], #20 + ret i32* %addr +} + +@defined_weak_var = internal unnamed_addr global i32 0 + +define i32* @wibble() { + ret i32* @defined_weak_var +; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var +; CHECK: add x0, [[BASE]], #:lo12:defined_weak_var +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/extract.ll b/test/CodeGen/AArch64/extract.ll new file mode 100644 index 000000000000..06267816a4e1 --- /dev/null +++ b/test/CodeGen/AArch64/extract.ll @@ -0,0 +1,57 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +define i64 @ror_i64(i64 %in) { +; CHECK: ror_i64: + %left = shl i64 %in, 19 + %right = lshr i64 %in, 45 + %val5 = or i64 %left, %right +; CHECK: extr {{x[0-9]+}}, x0, x0, #45 + ret i64 %val5 +} + +define i32 @ror_i32(i32 %in) { +; CHECK: ror_i32: + %left = shl i32 %in, 9 + %right = lshr i32 %in, 23 + %val5 = or i32 %left, %right +; CHECK: extr {{w[0-9]+}}, w0, w0, #23 + ret i32 %val5 +} + +define i32 @extr_i32(i32 %lhs, i32 %rhs) { +; CHECK: extr_i32: + %left = shl i32 %lhs, 6 + %right = lshr i32 %rhs, 26 + %val = or i32 %left, %right + ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use + ; something other than w0 and w1. +; CHECK: extr {{w[0-9]+}}, w0, w1, #26 + + ret i32 %val +} + +define i64 @extr_i64(i64 %lhs, i64 %rhs) { +; CHECK: extr_i64: + %right = lshr i64 %rhs, 40 + %left = shl i64 %lhs, 24 + %val = or i64 %right, %left + ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use + ; something other than w0 and w1. +; CHECK: extr {{x[0-9]+}}, x0, x1, #40 + + ret i64 %val +} + +; Regression test: a bad experimental pattern crept into git which optimised +; this pattern to a single EXTR. +define i32 @extr_regress(i32 %a, i32 %b) { +; CHECK: extr_regress: + + %sh1 = shl i32 %a, 14 + %sh2 = lshr i32 %b, 14 + %val = or i32 %sh2, %sh1 +; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}} + + ret i32 %val +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/fastcc-reserved.ll b/test/CodeGen/AArch64/fastcc-reserved.ll new file mode 100644 index 000000000000..e40aa3033bde --- /dev/null +++ b/test/CodeGen/AArch64/fastcc-reserved.ll @@ -0,0 +1,58 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -tailcallopt | FileCheck %s + +; This test is designed to be run in the situation where the +; call-frame is not reserved (hence disable-fp-elim), but where +; callee-pop can occur (hence tailcallopt). + +declare fastcc void @will_pop([8 x i32], i32 %val) + +define fastcc void @foo(i32 %in) { +; CHECK: foo: + + %addr = alloca i8, i32 %in + +; Normal frame setup stuff: +; CHECK: sub sp, sp, +; CHECK: stp x29, x30 + +; Reserve space for call-frame: +; CHECK: sub sp, sp, #16 + + call fastcc void @will_pop([8 x i32] undef, i32 42) +; CHECK: bl will_pop + +; Since @will_pop is fastcc with tailcallopt, it will put the stack +; back where it needs to be, we shouldn't duplicate that +; CHECK-NOT: sub sp, sp, #16 +; CHECK-NOT: add sp, sp, + +; CHECK: ldp x29, x30 +; CHECK: add sp, sp, + ret void +} + +declare void @wont_pop([8 x i32], i32 %val) + +define void @foo1(i32 %in) { +; CHECK: foo1: + + %addr = alloca i8, i32 %in +; Normal frame setup again +; CHECK: sub sp, sp, +; CHECK: stp x29, x30 + +; Reserve space for call-frame +; CHECK: sub sp, sp, #16 + + call void @wont_pop([8 x i32] undef, i32 42) +; CHECK: bl wont_pop + +; This time we *do* need to unreserve the call-frame +; CHECK: add sp, sp, #16 + +; Check for epilogue (primarily to make sure sp spotted above wasn't +; part of it). +; CHECK: ldp x29, x30 +; CHECK: add sp, sp, + ret void +} diff --git a/test/CodeGen/AArch64/fastcc.ll b/test/CodeGen/AArch64/fastcc.ll new file mode 100644 index 000000000000..41cde94edc1c --- /dev/null +++ b/test/CodeGen/AArch64/fastcc.ll @@ -0,0 +1,123 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -tailcallopt | FileCheck %s -check-prefix CHECK-TAIL +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +; Without tailcallopt fastcc still means the caller cleans up the +; stack, so try to make sure this is respected. + +define fastcc void @func_stack0() { +; CHECK: func_stack0: +; CHECK: sub sp, sp, #48 + +; CHECK-TAIL: func_stack0: +; CHECK-TAIL: sub sp, sp, #48 + + + call fastcc void @func_stack8([8 x i32] undef, i32 42) +; CHECK: bl func_stack8 +; CHECK-NOT: sub sp, sp, + +; CHECK-TAIL: bl func_stack8 +; CHECK-TAIL: sub sp, sp, #16 + + + call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9) +; CHECK: bl func_stack32 +; CHECK-NOT: sub sp, sp, + +; CHECK-TAIL: bl func_stack32 +; CHECK-TAIL: sub sp, sp, #32 + + + call fastcc void @func_stack0() +; CHECK: bl func_stack0 +; CHECK-NOT: sub sp, sp + +; CHECK-TAIL: bl func_stack0 +; CHECK-TAIL-NOT: sub sp, sp + + ret void +; CHECK: add sp, sp, #48 +; CHECK-NEXT: ret + +; CHECK-TAIL: add sp, sp, #48 +; CHECK-TAIL-NEXT: ret + +} + +define fastcc void @func_stack8([8 x i32], i32 %stacked) { +; CHECK: func_stack8: +; CHECK: sub sp, sp, #48 + +; CHECK-TAIL: func_stack8: +; CHECK-TAIL: sub sp, sp, #48 + + + call fastcc void @func_stack8([8 x i32] undef, i32 42) +; CHECK: bl func_stack8 +; CHECK-NOT: sub sp, sp, + +; CHECK-TAIL: bl func_stack8 +; CHECK-TAIL: sub sp, sp, #16 + + + call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9) +; CHECK: bl func_stack32 +; CHECK-NOT: sub sp, sp, + +; CHECK-TAIL: bl func_stack32 +; CHECK-TAIL: sub sp, sp, #32 + + + call fastcc void @func_stack0() +; CHECK: bl func_stack0 +; CHECK-NOT: sub sp, sp + +; CHECK-TAIL: bl func_stack0 +; CHECK-TAIL-NOT: sub sp, sp + + ret void +; CHECK: add sp, sp, #48 +; CHECK-NEXT: ret + +; CHECK-TAIL: add sp, sp, #64 +; CHECK-TAIL-NEXT: ret +} + +define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) { +; CHECK: func_stack32: +; CHECK: sub sp, sp, #48 + +; CHECK-TAIL: func_stack32: +; CHECK-TAIL: sub sp, sp, #48 + + + call fastcc void @func_stack8([8 x i32] undef, i32 42) +; CHECK: bl func_stack8 +; CHECK-NOT: sub sp, sp, + +; CHECK-TAIL: bl func_stack8 +; CHECK-TAIL: sub sp, sp, #16 + + + call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9) +; CHECK: bl func_stack32 +; CHECK-NOT: sub sp, sp, + +; CHECK-TAIL: bl func_stack32 +; CHECK-TAIL: sub sp, sp, #32 + + + call fastcc void @func_stack0() +; CHECK: bl func_stack0 +; CHECK-NOT: sub sp, sp + +; CHECK-TAIL: bl func_stack0 +; CHECK-TAIL-NOT: sub sp, sp + + ret void +; CHECK: add sp, sp, #48 +; CHECK-NEXT: ret + +; CHECK-TAIL: add sp, sp, #80 +; CHECK-TAIL-NEXT: ret +} diff --git a/test/CodeGen/AArch64/fcmp.ll b/test/CodeGen/AArch64/fcmp.ll new file mode 100644 index 000000000000..ad4a903c9b25 --- /dev/null +++ b/test/CodeGen/AArch64/fcmp.ll @@ -0,0 +1,81 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +declare void @bar(i32) + +define void @test_float(float %a, float %b) { +; CHECK: test_float: + + %tst1 = fcmp oeq float %a, %b + br i1 %tst1, label %end, label %t2 +; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}} +; CHECK: b.eq .L + +t2: + %tst2 = fcmp une float %b, 0.0 + br i1 %tst2, label %t3, label %end +; CHECK: fcmp {{s[0-9]+}}, #0.0 +; CHECK: b.eq .L + + +t3: +; This test can't be implemented with just one A64 conditional +; branch. LLVM converts "ordered and not equal" to "unordered or +; equal" before instruction selection, which is what we currently +; test. Obviously, other sequences are valid. + %tst3 = fcmp one float %a, %b + br i1 %tst3, label %t4, label %end +; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}} +; CHECK-NEXT: b.eq .[[T4:LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: b.vs .[[T4]] +t4: + %tst4 = fcmp uge float %a, -0.0 + br i1 %tst4, label %t5, label %end +; CHECK-NOT: fcmp {{s[0-9]+}}, #0.0 +; CHECK: b.mi .LBB + +t5: + call void @bar(i32 0) + ret void +end: + ret void + +} + +define void @test_double(double %a, double %b) { +; CHECK: test_double: + + %tst1 = fcmp oeq double %a, %b + br i1 %tst1, label %end, label %t2 +; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}} +; CHECK: b.eq .L + +t2: + %tst2 = fcmp une double %b, 0.0 + br i1 %tst2, label %t3, label %end +; CHECK: fcmp {{d[0-9]+}}, #0.0 +; CHECK: b.eq .L + + +t3: +; This test can't be implemented with just one A64 conditional +; branch. LLVM converts "ordered and not equal" to "unordered or +; equal" before instruction selection, which is what we currently +; test. Obviously, other sequences are valid. + %tst3 = fcmp one double %a, %b + br i1 %tst3, label %t4, label %end +; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}} +; CHECK-NEXT: b.eq .[[T4:LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: b.vs .[[T4]] +t4: + %tst4 = fcmp uge double %a, -0.0 + br i1 %tst4, label %t5, label %end +; CHECK-NOT: fcmp {{d[0-9]+}}, #0.0 +; CHECK: b.mi .LBB + +t5: + call void @bar(i32 0) + ret void +end: + ret void + +} diff --git a/test/CodeGen/AArch64/fcvt-fixed.ll b/test/CodeGen/AArch64/fcvt-fixed.ll new file mode 100644 index 000000000000..0f7b95b2a48f --- /dev/null +++ b/test/CodeGen/AArch64/fcvt-fixed.ll @@ -0,0 +1,191 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -O0 | FileCheck %s + +@var32 = global i32 0 +@var64 = global i64 0 + +define void @test_fcvtzs(float %flt, double %dbl) { +; CHECK: test_fcvtzs: + + %fix1 = fmul float %flt, 128.0 + %cvt1 = fptosi float %fix1 to i32 +; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #7 + store volatile i32 %cvt1, i32* @var32 + + %fix2 = fmul float %flt, 4294967296.0 + %cvt2 = fptosi float %fix2 to i32 +; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #32 + store volatile i32 %cvt2, i32* @var32 + + %fix3 = fmul float %flt, 128.0 + %cvt3 = fptosi float %fix3 to i64 +; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #7 + store volatile i64 %cvt3, i64* @var64 + + %fix4 = fmul float %flt, 18446744073709551616.0 + %cvt4 = fptosi float %fix4 to i64 +; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #64 + store volatile i64 %cvt4, i64* @var64 + + %fix5 = fmul double %dbl, 128.0 + %cvt5 = fptosi double %fix5 to i32 +; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #7 + store volatile i32 %cvt5, i32* @var32 + + %fix6 = fmul double %dbl, 4294967296.0 + %cvt6 = fptosi double %fix6 to i32 +; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #32 + store volatile i32 %cvt6, i32* @var32 + + %fix7 = fmul double %dbl, 128.0 + %cvt7 = fptosi double %fix7 to i64 +; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #7 + store volatile i64 %cvt7, i64* @var64 + + %fix8 = fmul double %dbl, 18446744073709551616.0 + %cvt8 = fptosi double %fix8 to i64 +; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #64 + store volatile i64 %cvt8, i64* @var64 + + ret void +} + +define void @test_fcvtzu(float %flt, double %dbl) { +; CHECK: test_fcvtzu: + + %fix1 = fmul float %flt, 128.0 + %cvt1 = fptoui float %fix1 to i32 +; CHECK: fcvtzu {{w[0-9]+}}, {{s[0-9]+}}, #7 + store volatile i32 %cvt1, i32* @var32 + + %fix2 = fmul float %flt, 4294967296.0 + %cvt2 = fptoui float %fix2 to i32 +; CHECK: fcvtzu {{w[0-9]+}}, {{s[0-9]+}}, #32 + store volatile i32 %cvt2, i32* @var32 + + %fix3 = fmul float %flt, 128.0 + %cvt3 = fptoui float %fix3 to i64 +; CHECK: fcvtzu {{x[0-9]+}}, {{s[0-9]+}}, #7 + store volatile i64 %cvt3, i64* @var64 + + %fix4 = fmul float %flt, 18446744073709551616.0 + %cvt4 = fptoui float %fix4 to i64 +; CHECK: fcvtzu {{x[0-9]+}}, {{s[0-9]+}}, #64 + store volatile i64 %cvt4, i64* @var64 + + %fix5 = fmul double %dbl, 128.0 + %cvt5 = fptoui double %fix5 to i32 +; CHECK: fcvtzu {{w[0-9]+}}, {{d[0-9]+}}, #7 + store volatile i32 %cvt5, i32* @var32 + + %fix6 = fmul double %dbl, 4294967296.0 + %cvt6 = fptoui double %fix6 to i32 +; CHECK: fcvtzu {{w[0-9]+}}, {{d[0-9]+}}, #32 + store volatile i32 %cvt6, i32* @var32 + + %fix7 = fmul double %dbl, 128.0 + %cvt7 = fptoui double %fix7 to i64 +; CHECK: fcvtzu {{x[0-9]+}}, {{d[0-9]+}}, #7 + store volatile i64 %cvt7, i64* @var64 + + %fix8 = fmul double %dbl, 18446744073709551616.0 + %cvt8 = fptoui double %fix8 to i64 +; CHECK: fcvtzu {{x[0-9]+}}, {{d[0-9]+}}, #64 + store volatile i64 %cvt8, i64* @var64 + + ret void +} + +@varfloat = global float 0.0 +@vardouble = global double 0.0 + +define void @test_scvtf(i32 %int, i64 %long) { +; CHECK: test_scvtf: + + %cvt1 = sitofp i32 %int to float + %fix1 = fdiv float %cvt1, 128.0 +; CHECK: scvtf {{s[0-9]+}}, {{w[0-9]+}}, #7 + store volatile float %fix1, float* @varfloat + + %cvt2 = sitofp i32 %int to float + %fix2 = fdiv float %cvt2, 4294967296.0 +; CHECK: scvtf {{s[0-9]+}}, {{w[0-9]+}}, #32 + store volatile float %fix2, float* @varfloat + + %cvt3 = sitofp i64 %long to float + %fix3 = fdiv float %cvt3, 128.0 +; CHECK: scvtf {{s[0-9]+}}, {{x[0-9]+}}, #7 + store volatile float %fix3, float* @varfloat + + %cvt4 = sitofp i64 %long to float + %fix4 = fdiv float %cvt4, 18446744073709551616.0 +; CHECK: scvtf {{s[0-9]+}}, {{x[0-9]+}}, #64 + store volatile float %fix4, float* @varfloat + + %cvt5 = sitofp i32 %int to double + %fix5 = fdiv double %cvt5, 128.0 +; CHECK: scvtf {{d[0-9]+}}, {{w[0-9]+}}, #7 + store volatile double %fix5, double* @vardouble + + %cvt6 = sitofp i32 %int to double + %fix6 = fdiv double %cvt6, 4294967296.0 +; CHECK: scvtf {{d[0-9]+}}, {{w[0-9]+}}, #32 + store volatile double %fix6, double* @vardouble + + %cvt7 = sitofp i64 %long to double + %fix7 = fdiv double %cvt7, 128.0 +; CHECK: scvtf {{d[0-9]+}}, {{x[0-9]+}}, #7 + store volatile double %fix7, double* @vardouble + + %cvt8 = sitofp i64 %long to double + %fix8 = fdiv double %cvt8, 18446744073709551616.0 +; CHECK: scvtf {{d[0-9]+}}, {{x[0-9]+}}, #64 + store volatile double %fix8, double* @vardouble + + ret void +} + +define void @test_ucvtf(i32 %int, i64 %long) { +; CHECK: test_ucvtf: + + %cvt1 = uitofp i32 %int to float + %fix1 = fdiv float %cvt1, 128.0 +; CHECK: ucvtf {{s[0-9]+}}, {{w[0-9]+}}, #7 + store volatile float %fix1, float* @varfloat + + %cvt2 = uitofp i32 %int to float + %fix2 = fdiv float %cvt2, 4294967296.0 +; CHECK: ucvtf {{s[0-9]+}}, {{w[0-9]+}}, #32 + store volatile float %fix2, float* @varfloat + + %cvt3 = uitofp i64 %long to float + %fix3 = fdiv float %cvt3, 128.0 +; CHECK: ucvtf {{s[0-9]+}}, {{x[0-9]+}}, #7 + store volatile float %fix3, float* @varfloat + + %cvt4 = uitofp i64 %long to float + %fix4 = fdiv float %cvt4, 18446744073709551616.0 +; CHECK: ucvtf {{s[0-9]+}}, {{x[0-9]+}}, #64 + store volatile float %fix4, float* @varfloat + + %cvt5 = uitofp i32 %int to double + %fix5 = fdiv double %cvt5, 128.0 +; CHECK: ucvtf {{d[0-9]+}}, {{w[0-9]+}}, #7 + store volatile double %fix5, double* @vardouble + + %cvt6 = uitofp i32 %int to double + %fix6 = fdiv double %cvt6, 4294967296.0 +; CHECK: ucvtf {{d[0-9]+}}, {{w[0-9]+}}, #32 + store volatile double %fix6, double* @vardouble + + %cvt7 = uitofp i64 %long to double + %fix7 = fdiv double %cvt7, 128.0 +; CHECK: ucvtf {{d[0-9]+}}, {{x[0-9]+}}, #7 + store volatile double %fix7, double* @vardouble + + %cvt8 = uitofp i64 %long to double + %fix8 = fdiv double %cvt8, 18446744073709551616.0 +; CHECK: ucvtf {{d[0-9]+}}, {{x[0-9]+}}, #64 + store volatile double %fix8, double* @vardouble + + ret void +} diff --git a/test/CodeGen/AArch64/fcvt-int.ll b/test/CodeGen/AArch64/fcvt-int.ll new file mode 100644 index 000000000000..c771d683a99c --- /dev/null +++ b/test/CodeGen/AArch64/fcvt-int.ll @@ -0,0 +1,151 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +define i32 @test_floattoi32(float %in) { +; CHECK: test_floattoi32: + + %signed = fptosi float %in to i32 + %unsigned = fptoui float %in to i32 +; CHECK: fcvtzu [[UNSIG:w[0-9]+]], {{s[0-9]+}} +; CHECK: fcvtzs [[SIG:w[0-9]+]], {{s[0-9]+}} + + %res = sub i32 %signed, %unsigned +; CHECK: sub {{w[0-9]+}}, [[SIG]], [[UNSIG]] + + ret i32 %res +; CHECK: ret +} + +define i32 @test_doubletoi32(double %in) { +; CHECK: test_doubletoi32: + + %signed = fptosi double %in to i32 + %unsigned = fptoui double %in to i32 +; CHECK: fcvtzu [[UNSIG:w[0-9]+]], {{d[0-9]+}} +; CHECK: fcvtzs [[SIG:w[0-9]+]], {{d[0-9]+}} + + %res = sub i32 %signed, %unsigned +; CHECK: sub {{w[0-9]+}}, [[SIG]], [[UNSIG]] + + ret i32 %res +; CHECK: ret +} + +define i64 @test_floattoi64(float %in) { +; CHECK: test_floattoi64: + + %signed = fptosi float %in to i64 + %unsigned = fptoui float %in to i64 +; CHECK: fcvtzu [[UNSIG:x[0-9]+]], {{s[0-9]+}} +; CHECK: fcvtzs [[SIG:x[0-9]+]], {{s[0-9]+}} + + %res = sub i64 %signed, %unsigned +; CHECK: sub {{x[0-9]+}}, [[SIG]], [[UNSIG]] + + ret i64 %res +; CHECK: ret +} + +define i64 @test_doubletoi64(double %in) { +; CHECK: test_doubletoi64: + + %signed = fptosi double %in to i64 + %unsigned = fptoui double %in to i64 +; CHECK: fcvtzu [[UNSIG:x[0-9]+]], {{d[0-9]+}} +; CHECK: fcvtzs [[SIG:x[0-9]+]], {{d[0-9]+}} + + %res = sub i64 %signed, %unsigned +; CHECK: sub {{x[0-9]+}}, [[SIG]], [[UNSIG]] + + ret i64 %res +; CHECK: ret +} + +define float @test_i32tofloat(i32 %in) { +; CHECK: test_i32tofloat: + + %signed = sitofp i32 %in to float + %unsigned = uitofp i32 %in to float +; CHECK: ucvtf [[UNSIG:s[0-9]+]], {{w[0-9]+}} +; CHECK: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}} + + %res = fsub float %signed, %unsigned +; CHECL: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]] + ret float %res +; CHECK: ret +} + +define double @test_i32todouble(i32 %in) { +; CHECK: test_i32todouble: + + %signed = sitofp i32 %in to double + %unsigned = uitofp i32 %in to double +; CHECK: ucvtf [[UNSIG:d[0-9]+]], {{w[0-9]+}} +; CHECK: scvtf [[SIG:d[0-9]+]], {{w[0-9]+}} + + %res = fsub double %signed, %unsigned +; CHECK: fsub {{d[0-9]+}}, [[SIG]], [[UNSIG]] + ret double %res +; CHECK: ret +} + +define float @test_i64tofloat(i64 %in) { +; CHECK: test_i64tofloat: + + %signed = sitofp i64 %in to float + %unsigned = uitofp i64 %in to float +; CHECK: ucvtf [[UNSIG:s[0-9]+]], {{x[0-9]+}} +; CHECK: scvtf [[SIG:s[0-9]+]], {{x[0-9]+}} + + %res = fsub float %signed, %unsigned +; CHECK: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]] + ret float %res +; CHECK: ret +} + +define double @test_i64todouble(i64 %in) { +; CHECK: test_i64todouble: + + %signed = sitofp i64 %in to double + %unsigned = uitofp i64 %in to double +; CHECK: ucvtf [[UNSIG:d[0-9]+]], {{x[0-9]+}} +; CHECK: scvtf [[SIG:d[0-9]+]], {{x[0-9]+}} + + %res = fsub double %signed, %unsigned +; CHECK: sub {{d[0-9]+}}, [[SIG]], [[UNSIG]] + ret double %res +; CHECK: ret +} + +define i32 @test_bitcastfloattoi32(float %in) { +; CHECK: test_bitcastfloattoi32: + + %res = bitcast float %in to i32 +; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}} + ret i32 %res +} + +define i64 @test_bitcastdoubletoi64(double %in) { +; CHECK: test_bitcastdoubletoi64: + + %res = bitcast double %in to i64 +; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}} + ret i64 %res +} + +define float @test_bitcasti32tofloat(i32 %in) { +; CHECK: test_bitcasti32tofloat: + + %res = bitcast i32 %in to float +; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}} + ret float %res + +} + +define double @test_bitcasti64todouble(i64 %in) { +; CHECK: test_bitcasti64todouble: + + %res = bitcast i64 %in to double +; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}} + ret double %res + +} diff --git a/test/CodeGen/AArch64/flags-multiuse.ll b/test/CodeGen/AArch64/flags-multiuse.ll new file mode 100644 index 000000000000..940c146f0a9f --- /dev/null +++ b/test/CodeGen/AArch64/flags-multiuse.ll @@ -0,0 +1,35 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +; LLVM should be able to cope with multiple uses of the same flag-setting +; instruction at different points of a routine. Either by rematerializing the +; compare or by saving and restoring the flag register. + +declare void @bar() + +@var = global i32 0 + +define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) { +; CHECK: test_multiflag: + + %test = icmp ne i32 %n, %m +; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]] + + %val = zext i1 %test to i32 +; CHECK: csinc {{[xw][0-9]+}}, {{xzr|wzr}}, {{xzr|wzr}}, eq + + store i32 %val, i32* @var + + call void @bar() +; CHECK: bl bar + + ; Currently, the comparison is emitted again. An MSR/MRS pair would also be + ; acceptable, but assuming the call preserves NZCV is not. + br i1 %test, label %iftrue, label %iffalse +; CHECK: cmp [[LHS]], [[RHS]] +; CHECK: b.eq + +iftrue: + ret i32 42 +iffalse: + ret i32 0 +} diff --git a/test/CodeGen/AArch64/floatdp_1source.ll b/test/CodeGen/AArch64/floatdp_1source.ll new file mode 100644 index 000000000000..c94ba9b57b5a --- /dev/null +++ b/test/CodeGen/AArch64/floatdp_1source.ll @@ -0,0 +1,138 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@varhalf = global half 0.0 +@varfloat = global float 0.0 +@vardouble = global double 0.0 + +declare float @fabsf(float) readonly +declare double @fabs(double) readonly + +declare float @llvm.sqrt.f32(float %Val) +declare double @llvm.sqrt.f64(double %Val) + +declare float @ceilf(float) readonly +declare double @ceil(double) readonly + +declare float @floorf(float) readonly +declare double @floor(double) readonly + +declare float @truncf(float) readonly +declare double @trunc(double) readonly + +declare float @rintf(float) readonly +declare double @rint(double) readonly + +declare float @nearbyintf(float) readonly +declare double @nearbyint(double) readonly + +define void @simple_float() { +; CHECK: simple_float: + %val1 = load volatile float* @varfloat + + %valabs = call float @fabsf(float %val1) + store volatile float %valabs, float* @varfloat +; CHECK: fabs {{s[0-9]+}}, {{s[0-9]+}} + + %valneg = fsub float -0.0, %val1 + store volatile float %valneg, float* @varfloat +; CHECK: fneg {{s[0-9]+}}, {{s[0-9]+}} + + %valsqrt = call float @llvm.sqrt.f32(float %val1) + store volatile float %valsqrt, float* @varfloat +; CHECK: fsqrt {{s[0-9]+}}, {{s[0-9]+}} + + %valceil = call float @ceilf(float %val1) + store volatile float %valceil, float* @varfloat +; CHECK: frintp {{s[0-9]+}}, {{s[0-9]+}} + + %valfloor = call float @floorf(float %val1) + store volatile float %valfloor, float* @varfloat +; CHECK: frintm {{s[0-9]+}}, {{s[0-9]+}} + + %valtrunc = call float @truncf(float %val1) + store volatile float %valtrunc, float* @varfloat +; CHECK: frintz {{s[0-9]+}}, {{s[0-9]+}} + + %valrint = call float @rintf(float %val1) + store volatile float %valrint, float* @varfloat +; CHECK: frintx {{s[0-9]+}}, {{s[0-9]+}} + + %valnearbyint = call float @nearbyintf(float %val1) + store volatile float %valnearbyint, float* @varfloat +; CHECK: frinti {{s[0-9]+}}, {{s[0-9]+}} + + ret void +} + +define void @simple_double() { +; CHECK: simple_double: + %val1 = load volatile double* @vardouble + + %valabs = call double @fabs(double %val1) + store volatile double %valabs, double* @vardouble +; CHECK: fabs {{d[0-9]+}}, {{d[0-9]+}} + + %valneg = fsub double -0.0, %val1 + store volatile double %valneg, double* @vardouble +; CHECK: fneg {{d[0-9]+}}, {{d[0-9]+}} + + %valsqrt = call double @llvm.sqrt.f64(double %val1) + store volatile double %valsqrt, double* @vardouble +; CHECK: fsqrt {{d[0-9]+}}, {{d[0-9]+}} + + %valceil = call double @ceil(double %val1) + store volatile double %valceil, double* @vardouble +; CHECK: frintp {{d[0-9]+}}, {{d[0-9]+}} + + %valfloor = call double @floor(double %val1) + store volatile double %valfloor, double* @vardouble +; CHECK: frintm {{d[0-9]+}}, {{d[0-9]+}} + + %valtrunc = call double @trunc(double %val1) + store volatile double %valtrunc, double* @vardouble +; CHECK: frintz {{d[0-9]+}}, {{d[0-9]+}} + + %valrint = call double @rint(double %val1) + store volatile double %valrint, double* @vardouble +; CHECK: frintx {{d[0-9]+}}, {{d[0-9]+}} + + %valnearbyint = call double @nearbyint(double %val1) + store volatile double %valnearbyint, double* @vardouble +; CHECK: frinti {{d[0-9]+}}, {{d[0-9]+}} + + ret void +} + +define void @converts() { +; CHECK: converts: + + %val16 = load volatile half* @varhalf + %val32 = load volatile float* @varfloat + %val64 = load volatile double* @vardouble + + %val16to32 = fpext half %val16 to float + store volatile float %val16to32, float* @varfloat +; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}} + + %val16to64 = fpext half %val16 to double + store volatile double %val16to64, double* @vardouble +; CHECK: fcvt {{d[0-9]+}}, {{h[0-9]+}} + + %val32to16 = fptrunc float %val32 to half + store volatile half %val32to16, half* @varhalf +; CHECK: fcvt {{h[0-9]+}}, {{s[0-9]+}} + + %val32to64 = fpext float %val32 to double + store volatile double %val32to64, double* @vardouble +; CHECK: fcvt {{d[0-9]+}}, {{s[0-9]+}} + + %val64to16 = fptrunc double %val64 to half + store volatile half %val64to16, half* @varhalf +; CHECK: fcvt {{h[0-9]+}}, {{d[0-9]+}} + + %val64to32 = fptrunc double %val64 to float + store volatile float %val64to32, float* @varfloat +; CHECK: fcvt {{s[0-9]+}}, {{d[0-9]+}} + + ret void +} diff --git a/test/CodeGen/AArch64/floatdp_2source.ll b/test/CodeGen/AArch64/floatdp_2source.ll new file mode 100644 index 000000000000..b2256b342acf --- /dev/null +++ b/test/CodeGen/AArch64/floatdp_2source.ll @@ -0,0 +1,60 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@varfloat = global float 0.0 +@vardouble = global double 0.0 + +define void @testfloat() { +; CHECK: testfloat: + %val1 = load float* @varfloat + + %val2 = fadd float %val1, %val1 +; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + + %val3 = fmul float %val2, %val1 +; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + + %val4 = fdiv float %val3, %val1 +; CHECK: fdiv {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + + %val5 = fsub float %val4, %val2 +; CHECK: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + + store volatile float %val5, float* @varfloat + +; These will be enabled with the implementation of floating-point litpool entries. + %val6 = fmul float %val1, %val2 + %val7 = fsub float -0.0, %val6 +; CHECK: fnmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + + store volatile float %val7, float* @varfloat + + ret void +} + +define void @testdouble() { +; CHECK: testdouble: + %val1 = load double* @vardouble + + %val2 = fadd double %val1, %val1 +; CHECK: fadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + + %val3 = fmul double %val2, %val1 +; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + + %val4 = fdiv double %val3, %val1 +; CHECK: fdiv {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + + %val5 = fsub double %val4, %val2 +; CHECK: fsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + + store volatile double %val5, double* @vardouble + +; These will be enabled with the implementation of doubleing-point litpool entries. + %val6 = fmul double %val1, %val2 + %val7 = fsub double -0.0, %val6 +; CHECK: fnmul {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + + store volatile double %val7, double* @vardouble + + ret void +} diff --git a/test/CodeGen/AArch64/fp-cond-sel.ll b/test/CodeGen/AArch64/fp-cond-sel.ll new file mode 100644 index 000000000000..56e8f16f9b36 --- /dev/null +++ b/test/CodeGen/AArch64/fp-cond-sel.ll @@ -0,0 +1,26 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@varfloat = global float 0.0 +@vardouble = global double 0.0 + +define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) { +; CHECK: test_csel: + + %tst1 = icmp ugt i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, float 0.0, float 1.0 + store float %val1, float* @varfloat +; CHECK: ldr [[FLT0:s[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI +; CHECK: fmov [[FLT1:s[0-9]+]], #1.0 +; CHECK: fcsel {{s[0-9]+}}, [[FLT0]], [[FLT1]], hi + + %rhs64 = sext i32 %rhs32 to i64 + %tst2 = icmp sle i64 %lhs64, %rhs64 + %val2 = select i1 %tst2, double 1.0, double 0.0 + store double %val2, double* @vardouble +; CHECK: ldr [[FLT0:d[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI +; CHECK: fmov [[FLT1:d[0-9]+]], #1.0 +; CHECK: fcsel {{d[0-9]+}}, [[FLT1]], [[FLT0]], le + + ret void +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/fp-dp3.ll b/test/CodeGen/AArch64/fp-dp3.ll new file mode 100644 index 000000000000..39db9be15771 --- /dev/null +++ b/test/CodeGen/AArch64/fp-dp3.ll @@ -0,0 +1,102 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -fp-contract=fast | FileCheck %s + +declare float @llvm.fma.f32(float, float, float) +declare double @llvm.fma.f64(double, double, double) + +define float @test_fmadd(float %a, float %b, float %c) { +; CHECK: test_fmadd: + %val = call float @llvm.fma.f32(float %a, float %b, float %c) +; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + ret float %val +} + +define float @test_fmsub(float %a, float %b, float %c) { +; CHECK: test_fmsub: + %nega = fsub float -0.0, %a + %val = call float @llvm.fma.f32(float %nega, float %b, float %c) +; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + ret float %val +} + +define float @test_fnmadd(float %a, float %b, float %c) { +; CHECK: test_fnmadd: + %negc = fsub float -0.0, %c + %val = call float @llvm.fma.f32(float %a, float %b, float %negc) +; CHECK: fnmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + ret float %val +} + +define float @test_fnmsub(float %a, float %b, float %c) { +; CHECK: test_fnmsub: + %nega = fsub float -0.0, %a + %negc = fsub float -0.0, %c + %val = call float @llvm.fma.f32(float %nega, float %b, float %negc) +; CHECK: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + ret float %val +} + +define double @testd_fmadd(double %a, double %b, double %c) { +; CHECK: testd_fmadd: + %val = call double @llvm.fma.f64(double %a, double %b, double %c) +; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + ret double %val +} + +define double @testd_fmsub(double %a, double %b, double %c) { +; CHECK: testd_fmsub: + %nega = fsub double -0.0, %a + %val = call double @llvm.fma.f64(double %nega, double %b, double %c) +; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + ret double %val +} + +define double @testd_fnmadd(double %a, double %b, double %c) { +; CHECK: testd_fnmadd: + %negc = fsub double -0.0, %c + %val = call double @llvm.fma.f64(double %a, double %b, double %negc) +; CHECK: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + ret double %val +} + +define double @testd_fnmsub(double %a, double %b, double %c) { +; CHECK: testd_fnmsub: + %nega = fsub double -0.0, %a + %negc = fsub double -0.0, %c + %val = call double @llvm.fma.f64(double %nega, double %b, double %negc) +; CHECK: fnmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + ret double %val +} + +define float @test_fmadd_unfused(float %a, float %b, float %c) { +; CHECK: test_fmadd_unfused: + %prod = fmul float %b, %c + %sum = fadd float %a, %prod +; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + ret float %sum +} + +define float @test_fmsub_unfused(float %a, float %b, float %c) { +; CHECK: test_fmsub_unfused: + %prod = fmul float %b, %c + %diff = fsub float %a, %prod +; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + ret float %diff +} + +define float @test_fnmadd_unfused(float %a, float %b, float %c) { +; CHECK: test_fnmadd_unfused: + %nega = fsub float -0.0, %a + %prod = fmul float %b, %c + %sum = fadd float %nega, %prod +; CHECK: fnmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + ret float %sum +} + +define float @test_fnmsub_unfused(float %a, float %b, float %c) { +; CHECK: test_fnmsub_unfused: + %nega = fsub float -0.0, %a + %prod = fmul float %b, %c + %diff = fsub float %nega, %prod +; CHECK: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + ret float %diff +} diff --git a/test/CodeGen/AArch64/fp128-folding.ll b/test/CodeGen/AArch64/fp128-folding.ll new file mode 100644 index 000000000000..b5bdcf4f37b4 --- /dev/null +++ b/test/CodeGen/AArch64/fp128-folding.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s +declare void @bar(i8*, i8*, i32*) + +; SelectionDAG used to try to fold some fp128 operations using the ppc128 type, +; which is not supported. + +define fp128 @test_folding() { +; CHECK: test_folding: + %l = alloca i32 + store i32 42, i32* %l + %val = load i32* %l + %fpval = sitofp i32 %val to fp128 + ; If the value is loaded from a constant pool into an fp128, it's been folded + ; successfully. +; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI + ret fp128 %fpval +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/fp128.ll b/test/CodeGen/AArch64/fp128.ll new file mode 100644 index 000000000000..258d34b8f81f --- /dev/null +++ b/test/CodeGen/AArch64/fp128.ll @@ -0,0 +1,280 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +@lhs = global fp128 zeroinitializer +@rhs = global fp128 zeroinitializer + +define fp128 @test_add() { +; CHECK: test_add: + + %lhs = load fp128* @lhs + %rhs = load fp128* @rhs +; CHECK: ldr q0, [{{x[0-9]+}}, #:lo12:lhs] +; CHECK: ldr q1, [{{x[0-9]+}}, #:lo12:rhs] + + %val = fadd fp128 %lhs, %rhs +; CHECK: bl __addtf3 + ret fp128 %val +} + +define fp128 @test_sub() { +; CHECK: test_sub: + + %lhs = load fp128* @lhs + %rhs = load fp128* @rhs +; CHECK: ldr q0, [{{x[0-9]+}}, #:lo12:lhs] +; CHECK: ldr q1, [{{x[0-9]+}}, #:lo12:rhs] + + %val = fsub fp128 %lhs, %rhs +; CHECK: bl __subtf3 + ret fp128 %val +} + +define fp128 @test_mul() { +; CHECK: test_mul: + + %lhs = load fp128* @lhs + %rhs = load fp128* @rhs +; CHECK: ldr q0, [{{x[0-9]+}}, #:lo12:lhs] +; CHECK: ldr q1, [{{x[0-9]+}}, #:lo12:rhs] + + %val = fmul fp128 %lhs, %rhs +; CHECK: bl __multf3 + ret fp128 %val +} + +define fp128 @test_div() { +; CHECK: test_div: + + %lhs = load fp128* @lhs + %rhs = load fp128* @rhs +; CHECK: ldr q0, [{{x[0-9]+}}, #:lo12:lhs] +; CHECK: ldr q1, [{{x[0-9]+}}, #:lo12:rhs] + + %val = fdiv fp128 %lhs, %rhs +; CHECK: bl __divtf3 + ret fp128 %val +} + +@var32 = global i32 0 +@var64 = global i64 0 + +define void @test_fptosi() { +; CHECK: test_fptosi: + %val = load fp128* @lhs + + %val32 = fptosi fp128 %val to i32 + store i32 %val32, i32* @var32 +; CHECK: bl __fixtfsi + + %val64 = fptosi fp128 %val to i64 + store i64 %val64, i64* @var64 +; CHECK: bl __fixtfdi + + ret void +} + +define void @test_fptoui() { +; CHECK: test_fptoui: + %val = load fp128* @lhs + + %val32 = fptoui fp128 %val to i32 + store i32 %val32, i32* @var32 +; CHECK: bl __fixunstfsi + + %val64 = fptoui fp128 %val to i64 + store i64 %val64, i64* @var64 +; CHECK: bl __fixunstfdi + + ret void +} + +define void @test_sitofp() { +; CHECK: test_sitofp: + + %src32 = load i32* @var32 + %val32 = sitofp i32 %src32 to fp128 + store volatile fp128 %val32, fp128* @lhs +; CHECK: bl __floatsitf + + %src64 = load i64* @var64 + %val64 = sitofp i64 %src64 to fp128 + store volatile fp128 %val64, fp128* @lhs +; CHECK: bl __floatditf + + ret void +} + +define void @test_uitofp() { +; CHECK: test_uitofp: + + %src32 = load i32* @var32 + %val32 = uitofp i32 %src32 to fp128 + store volatile fp128 %val32, fp128* @lhs +; CHECK: bl __floatunsitf + + %src64 = load i64* @var64 + %val64 = uitofp i64 %src64 to fp128 + store volatile fp128 %val64, fp128* @lhs +; CHECK: bl __floatunditf + + ret void +} + +define i1 @test_setcc1() { +; CHECK: test_setcc1: + + %lhs = load fp128* @lhs + %rhs = load fp128* @rhs +; CHECK: ldr q0, [{{x[0-9]+}}, #:lo12:lhs] +; CHECK: ldr q1, [{{x[0-9]+}}, #:lo12:rhs] + +; Technically, everything after the call to __letf2 is redundant, but we'll let +; LLVM have its fun for now. + %val = fcmp ole fp128 %lhs, %rhs +; CHECK: bl __letf2 +; CHECK: cmp w0, #0 +; CHECK: csinc w0, wzr, wzr, gt + + ret i1 %val +; CHECK: ret +} + +define i1 @test_setcc2() { +; CHECK: test_setcc2: + + %lhs = load fp128* @lhs + %rhs = load fp128* @rhs +; CHECK: ldr q0, [{{x[0-9]+}}, #:lo12:lhs] +; CHECK: ldr q1, [{{x[0-9]+}}, #:lo12:rhs] + +; Technically, everything after the call to __letf2 is redundant, but we'll let +; LLVM have its fun for now. + %val = fcmp ugt fp128 %lhs, %rhs +; CHECK: bl __unordtf2 +; CHECK: mov x[[UNORDERED:[0-9]+]], x0 + +; CHECK: bl __gttf2 +; CHECK: cmp w0, #0 +; CHECK: csinc [[GT:w[0-9]+]], wzr, wzr, le +; CHECK: cmp w[[UNORDERED]], #0 +; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq +; CHECK: orr w0, [[UNORDERED]], [[GT]] + + ret i1 %val +; CHECK: ret +} + +define i32 @test_br_cc() { +; CHECK: test_br_cc: + + %lhs = load fp128* @lhs + %rhs = load fp128* @rhs +; CHECK: ldr q0, [{{x[0-9]+}}, #:lo12:lhs] +; CHECK: ldr q1, [{{x[0-9]+}}, #:lo12:rhs] + + ; olt == !uge, which LLVM unfortunately "optimizes" this to. + %cond = fcmp olt fp128 %lhs, %rhs +; CHECK: bl __unordtf2 +; CHECK: mov x[[UNORDERED:[0-9]+]], x0 + +; CHECK: bl __getf2 +; CHECK: cmp w0, #0 + +; CHECK: csinc [[OGE:w[0-9]+]], wzr, wzr, lt +; CHECK: cmp w[[UNORDERED]], #0 +; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq +; CHECK: orr [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]] +; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]] + br i1 %cond, label %iftrue, label %iffalse + +iftrue: + ret i32 42 +; CHECK-NEXT: BB# +; CHECK-NEXT: movz x0, #42 +; CHECK-NEXT: b [[REALRET:.LBB[0-9]+_[0-9]+]] + +iffalse: + ret i32 29 +; CHECK: [[RET29]]: +; CHECK-NEXT: movz x0, #29 +; CHECK-NEXT: [[REALRET]]: +; CHECK: ret +} + +define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) { +; CHECK: test_select: + + %val = select i1 %cond, fp128 %lhs, fp128 %rhs + store fp128 %val, fp128* @lhs +; CHECK: cmp w0, #0 +; CHECK: str q1, [sp] +; CHECK-NEXT: b.eq [[IFFALSE:.LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: BB# +; CHECK-NEXT: str q0, [sp] +; CHECK-NEXT: [[IFFALSE]]: +; CHECK-NEXT: ldr q0, [sp] +; CHECK: str q0, [{{x[0-9]+}}, #:lo12:lhs] + ret void +; CHECK: ret +} + +@varfloat = global float 0.0 +@vardouble = global double 0.0 + +define void @test_round() { +; CHECK: test_round: + + %val = load fp128* @lhs + + %float = fptrunc fp128 %val to float + store float %float, float* @varfloat +; CHECK: bl __trunctfsf2 +; CHECK: str s0, [{{x[0-9]+}}, #:lo12:varfloat] + + %double = fptrunc fp128 %val to double + store double %double, double* @vardouble +; CHECK: bl __trunctfdf2 +; CHECK: str d0, [{{x[0-9]+}}, #:lo12:vardouble] + + ret void +} + +define void @test_extend() { +; CHECK: test_extend: + + %val = load fp128* @lhs + + %float = load float* @varfloat + %fromfloat = fpext float %float to fp128 + store volatile fp128 %fromfloat, fp128* @lhs +; CHECK: bl __extendsftf2 +; CHECK: str q0, [{{x[0-9]+}}, #:lo12:lhs] + + %double = load double* @vardouble + %fromdouble = fpext double %double to fp128 + store volatile fp128 %fromdouble, fp128* @lhs +; CHECK: bl __extenddftf2 +; CHECK: str q0, [{{x[0-9]+}}, #:lo12:lhs] + + ret void +; CHECK: ret +} + +define fp128 @test_neg(fp128 %in) { +; CHECK: [[MINUS0:.LCPI[0-9]+_0]]: +; Make sure the weird hex constant below *is* -0.0 +; CHECK-NEXT: fp128 -0 + +; CHECK: test_neg: + + ; Could in principle be optimized to fneg which we can't select, this makes + ; sure that doesn't happen. + %ret = fsub fp128 0xL00000000000000008000000000000000, %in +; CHECK: str q0, [sp, #-16] +; CHECK-NEXT: ldr q1, [sp], #16 +; CHECK: ldr q0, [{{x[0-9]+}}, #:lo12:[[MINUS0]]] +; CHECK: bl __subtf3 + + ret fp128 %ret +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/fpimm.ll b/test/CodeGen/AArch64/fpimm.ll new file mode 100644 index 000000000000..fd28aeef9291 --- /dev/null +++ b/test/CodeGen/AArch64/fpimm.ll @@ -0,0 +1,34 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@varf32 = global float 0.0 +@varf64 = global double 0.0 + +define void @check_float() { +; CHECK: check_float: + + %val = load float* @varf32 + %newval1 = fadd float %val, 8.5 + store volatile float %newval1, float* @varf32 +; CHECK: fmov {{s[0-9]+}}, #8.5 + + %newval2 = fadd float %val, 128.0 + store volatile float %newval2, float* @varf32 +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI0_0 + + ret void +} + +define void @check_double() { +; CHECK: check_double: + + %val = load double* @varf64 + %newval1 = fadd double %val, 8.5 + store volatile double %newval1, double* @varf64 +; CHECK: fmov {{d[0-9]+}}, #8.5 + + %newval2 = fadd double %val, 128.0 + store volatile double %newval2, double* @varf64 +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI1_0 + + ret void +} diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll new file mode 100644 index 000000000000..78fde6a3c33a --- /dev/null +++ b/test/CodeGen/AArch64/func-argpassing.ll @@ -0,0 +1,193 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +%myStruct = type { i64 , i8, i32 } + +@var8 = global i8 0 +@var32 = global i32 0 +@var64 = global i64 0 +@var128 = global i128 0 +@varfloat = global float 0.0 +@vardouble = global double 0.0 +@varstruct = global %myStruct zeroinitializer + +define void @take_i8s(i8 %val1, i8 %val2) { +; CHECK: take_i8s: + store i8 %val2, i8* @var8 + ; Not using w1 may be technically allowed, but it would indicate a + ; problem in itself. +; CHECK: strb w1, [{{x[0-9]+}}, #:lo12:var8] + ret void +} + +define void @add_floats(float %val1, float %val2) { +; CHECK: add_floats: + %newval = fadd float %val1, %val2 +; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1 + store float %newval, float* @varfloat +; CHECK: str [[ADDRES]], [{{x[0-9]+}}, #:lo12:varfloat] + ret void +} + +; byval pointers should be allocated to the stack and copied as if +; with memcpy. +define void @take_struct(%myStruct* byval %structval) { +; CHECK: take_struct: + %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 + %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 + + %val0 = load i32* %addr0 + ; Some weird move means x0 is used for one access +; CHECK: ldr [[REG32:w[0-9]+]], [{{x[0-9]+|sp}}, #12] + store i32 %val0, i32* @var32 +; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32] + + %val1 = load i64* %addr1 +; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}] + store i64 %val1, i64* @var64 +; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64] + + ret void +} + +; %structval should be at sp + 16 +define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) { +; CHECK: check_byval_align: + + %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 + %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 + + %val0 = load i32* %addr0 + ; Some weird move means x0 is used for one access +; CHECK: add x[[STRUCTVAL_ADDR:[0-9]+]], sp, #16 +; CHECK: ldr [[REG32:w[0-9]+]], [x[[STRUCTVAL_ADDR]], #12] + store i32 %val0, i32* @var32 +; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32] + + %val1 = load i64* %addr1 +; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16] + store i64 %val1, i64* @var64 +; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64] + + ret void +} + +define i32 @return_int() { +; CHECK: return_int: + %val = load i32* @var32 + ret i32 %val +; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32] + ; Make sure epilogue follows +; CHECK-NEXT: ret +} + +define double @return_double() { +; CHECK: return_double: + ret double 3.14 +; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI +} + +; This is the kind of IR clang will produce for returning a struct +; small enough to go into registers. Not all that pretty, but it +; works. +define [2 x i64] @return_struct() { +; CHECK: return_struct: + %addr = bitcast %myStruct* @varstruct to [2 x i64]* + %val = load [2 x i64]* %addr + ret [2 x i64] %val +; CHECK: ldr x0, [{{x[0-9]+}}, #:lo12:varstruct] + ; Odd register regex below disallows x0 which we want to be live now. +; CHECK: add {{x[1-9][0-9]*}}, {{x[1-9][0-9]*}}, #:lo12:varstruct +; CHECK-NEXT: ldr x1, [{{x[1-9][0-9]*}}, #8] + ; Make sure epilogue immediately follows +; CHECK-NEXT: ret +} + +; Large structs are passed by reference (storage allocated by caller +; to preserve value semantics) in x8. Strictly this only applies to +; structs larger than 16 bytes, but C semantics can still be provided +; if LLVM does it to %myStruct too. So this is the simplest check +define void @return_large_struct(%myStruct* sret %retval) { +; CHECK: return_large_struct: + %addr0 = getelementptr %myStruct* %retval, i64 0, i32 0 + %addr1 = getelementptr %myStruct* %retval, i64 0, i32 1 + %addr2 = getelementptr %myStruct* %retval, i64 0, i32 2 + + store i64 42, i64* %addr0 + store i8 2, i8* %addr1 + store i32 9, i32* %addr2 +; CHECK: str {{x[0-9]+}}, [x8] +; CHECK: strb {{w[0-9]+}}, [x8, #8] +; CHECK: str {{w[0-9]+}}, [x8, #12] + + ret void +} + +; This struct is just too far along to go into registers: (only x7 is +; available, but it needs two). Also make sure that %stacked doesn't +; sneak into x7 behind. +define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45, + i32* %var6, %myStruct* byval %struct, i32* byval %stacked, + double %notstacked) { +; CHECK: struct_on_stack: + %addr = getelementptr %myStruct* %struct, i64 0, i32 0 + %val64 = load i64* %addr + store i64 %val64, i64* @var64 + ; Currently nothing on local stack, so struct should be at sp +; CHECK: ldr [[VAL64:x[0-9]+]], [sp] +; CHECK: str [[VAL64]], [{{x[0-9]+}}, #:lo12:var64] + + store double %notstacked, double* @vardouble +; CHECK-NOT: ldr d0 +; CHECK: str d0, [{{x[0-9]+}}, #:lo12:vardouble + + %retval = load i32* %stacked + ret i32 %retval +; CHECK: ldr w0, [sp, #16] +} + +define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, + float %var4, float %var5, float %var6, float %var7, + float %var8) { +; CHECK: stacked_fpu: + store float %var8, float* @varfloat + ; Beware as above: the offset would be different on big-endian + ; machines if the first ldr were changed to use s-registers. +; CHECK: ldr d[[VALFLOAT:[0-9]+]], [sp] +; CHECK: str s[[VALFLOAT]], [{{x[0-9]+}}, #:lo12:varfloat] + + ret void +} + +; 128-bit integer types should be passed in xEVEN, xODD rather than +; the reverse. In this case x2 and x3. Nothing should use x1. +define i32 @check_i128_regalign(i32 %val0, i128 %val1, i32 %val2) { +; CHECK: check_i128_regalign + store i128 %val1, i128* @var128 +; CHECK: str x2, [{{x[0-9]+}}, #:lo12:var128] +; CHECK: str x3, [{{x[0-9]+}}, #8] + + ret i32 %val2 +; CHECK: mov x0, x4 +} + +define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3, + i32 %val4, i32 %val5, i32 %val6, i32 %val7, + i32 %stack1, i128 %stack2) { +; CHECK: check_i128_stackalign + store i128 %stack2, i128* @var128 + ; Nothing local on stack in current codegen, so first stack is 16 away +; CHECK: ldr {{x[0-9]+}}, [sp, #16] + ; Important point is that we address sp+24 for second dword +; CHECK: add [[REG:x[0-9]+]], sp, #16 +; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8] + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) + +define i32 @test_extern() { +; CHECK: test_extern: + call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0) +; CHECK: bl memcpy + ret i32 0 +} diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll new file mode 100644 index 000000000000..13b689c40886 --- /dev/null +++ b/test/CodeGen/AArch64/func-calls.ll @@ -0,0 +1,140 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +%myStruct = type { i64 , i8, i32 } + +@var8 = global i8 0 +@var8_2 = global i8 0 +@var32 = global i32 0 +@var64 = global i64 0 +@var128 = global i128 0 +@varfloat = global float 0.0 +@varfloat_2 = global float 0.0 +@vardouble = global double 0.0 +@varstruct = global %myStruct zeroinitializer +@varsmallstruct = global [2 x i64] zeroinitializer + +declare void @take_i8s(i8 %val1, i8 %val2) +declare void @take_floats(float %val1, float %val2) + +define void @simple_args() { +; CHECK: simple_args: + %char1 = load i8* @var8 + %char2 = load i8* @var8_2 + call void @take_i8s(i8 %char1, i8 %char2) +; CHECK: ldrb w0, [{{x[0-9]+}}, #:lo12:var8] +; CHECK: ldrb w1, [{{x[0-9]+}}, #:lo12:var8_2] +; CHECK: bl take_i8s + + %float1 = load float* @varfloat + %float2 = load float* @varfloat_2 + call void @take_floats(float %float1, float %float2) +; CHECK: ldr s1, [{{x[0-9]+}}, #:lo12:varfloat_2] +; CHECK: ldr s0, [{{x[0-9]+}}, #:lo12:varfloat] +; CHECK: bl take_floats + + ret void +} + +declare i32 @return_int() +declare double @return_double() +declare [2 x i64] @return_smallstruct() +declare void @return_large_struct(%myStruct* sret %retval) + +define void @simple_rets() { +; CHECK: simple_rets: + + %int = call i32 @return_int() + store i32 %int, i32* @var32 +; CHECK: bl return_int +; CHECK: str w0, [{{x[0-9]+}}, #:lo12:var32] + + %dbl = call double @return_double() + store double %dbl, double* @vardouble +; CHECK: bl return_double +; CHECK: str d0, [{{x[0-9]+}}, #:lo12:vardouble] + + %arr = call [2 x i64] @return_smallstruct() + store [2 x i64] %arr, [2 x i64]* @varsmallstruct +; CHECK: bl return_smallstruct +; CHECK: str x1, [{{x[0-9]+}}, #8] +; CHECK: str x0, [{{x[0-9]+}}, #:lo12:varsmallstruct] + + call void @return_large_struct(%myStruct* sret @varstruct) +; CHECK: add x8, {{x[0-9]+}}, #:lo12:varstruct +; CHECK: bl return_large_struct + + ret void +} + + +declare i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45, + i32* %var6, %myStruct* byval %struct, i32 %stacked, + double %notstacked) +declare void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, + float %var4, float %var5, float %var6, float %var7, + float %var8) + +define void @check_stack_args() { + call i32 @struct_on_stack(i8 0, i16 12, i32 42, i64 99, i128 1, + i32* @var32, %myStruct* byval @varstruct, + i32 999, double 1.0) + ; Want to check that the final double is passed in registers and + ; that varstruct is passed on the stack. Rather dependent on how a + ; memcpy gets created, but the following works for now. +; CHECK: mov x0, sp +; CHECK: str {{w[0-9]+}}, [x0] +; CHECK: str {{w[0-9]+}}, [x0, #12] +; CHECK: fmov d0, +; CHECK: bl struct_on_stack + + call void @stacked_fpu(float -1.0, double 1.0, float 4.0, float 2.0, + float -2.0, float -8.0, float 16.0, float 1.0, + float 64.0) +; CHECK: ldr s[[STACKEDREG:[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI +; CHECK: mov x0, sp +; CHECK: str d[[STACKEDREG]], [x0] +; CHECK: bl stacked_fpu + ret void +} + + +declare void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3, + i32 %val4, i32 %val5, i32 %val6, i32 %val7, + i32 %stack1, i128 %stack2) + +declare void @check_i128_regalign(i32 %val0, i128 %val1) + + +define void @check_i128_align() { +; CHECK: check_i128_align: + %val = load i128* @var128 + call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3, + i32 4, i32 5, i32 6, i32 7, + i32 42, i128 %val) +; CHECK: ldr [[I128LO:x[0-9]+]], [{{x[0-9]+}}, #:lo12:var128] +; CHECK: ldr [[I128HI:x[0-9]+]], [{{x[0-9]+}}, #8] +; CHECK: mov x[[SPREG:[0-9]+]], sp +; CHECK: str [[I128HI]], [x[[SPREG]], #24] +; CHECK: str [[I128LO]], [x[[SPREG]], #16] +; CHECK: bl check_i128_stackalign + + call void @check_i128_regalign(i32 0, i128 42) +; CHECK-NOT: mov x1 +; CHECK: movz x2, #42 +; CHECK: mov x3, xzr +; CHECK: bl check_i128_regalign + + ret void +} + +@fptr = global void()* null + +define void @check_indirect_call() { +; CHECK: check_indirect_call: + %func = load void()** @fptr + call void %func() +; CHECK: ldr [[FPTR:x[0-9]+]], [{{x[0-9]+}}, #:lo12:fptr] +; CHECK: blr [[FPTR]] + + ret void +} diff --git a/test/CodeGen/AArch64/global-alignment.ll b/test/CodeGen/AArch64/global-alignment.ll new file mode 100644 index 000000000000..8ed6e551cdeb --- /dev/null +++ b/test/CodeGen/AArch64/global-alignment.ll @@ -0,0 +1,69 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +@var32 = global [3 x i32] zeroinitializer +@var64 = global [3 x i64] zeroinitializer +@var32_align64 = global [3 x i32] zeroinitializer, align 8 + +define i64 @test_align32() { +; CHECK: test_align32: + %addr = bitcast [3 x i32]* @var32 to i64* + + ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to + ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load. + %val = load i64* %addr +; CHECK: adrp [[HIBITS:x[0-9]+]], var32 +; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], #:lo12:var32 +; CHECK: ldr x0, [x[[ADDR]]] + + ret i64 %val +} + +define i64 @test_align64() { +; CHECK: test_align64: + %addr = bitcast [3 x i64]* @var64 to i64* + + ; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be + ; inefficient. + %val = load i64* %addr +; CHECK: adrp x[[HIBITS:[0-9]+]], var64 +; CHECK-NOT: add x[[HIBITS]] +; CHECK: ldr x0, [x[[HIBITS]], #:lo12:var64] + + ret i64 %val +} + +define i64 @test_var32_align64() { +; CHECK: test_var32_align64: + %addr = bitcast [3 x i32]* @var32_align64 to i64* + + ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to + ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load. + %val = load i64* %addr +; CHECK: adrp x[[HIBITS:[0-9]+]], var32_align64 +; CHECK-NOT: add x[[HIBITS]] +; CHECK: ldr x0, [x[[HIBITS]], #:lo12:var32_align64] + + ret i64 %val +} + +@yet_another_var = external global {i32, i32} + +define i64 @test_yet_another_var() { +; CHECK: test_yet_another_var: + + ; @yet_another_var has a preferred alignment of 8, but that's not enough if + ; we're going to be linking against other things. Its ABI alignment is only 4 + ; so we can't fold the load. + %val = load i64* bitcast({i32, i32}* @yet_another_var to i64*) +; CHECK: adrp [[HIBITS:x[0-9]+]], yet_another_var +; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], #:lo12:yet_another_var +; CHECK: ldr x0, [x[[ADDR]]] + ret i64 %val +} + +define i64()* @test_functions() { +; CHECK: test_functions: + ret i64()* @test_yet_another_var +; CHECK: adrp [[HIBITS:x[0-9]+]], test_yet_another_var +; CHECK: add x0, [[HIBITS]], #:lo12:test_yet_another_var +} diff --git a/test/CodeGen/AArch64/got-abuse.ll b/test/CodeGen/AArch64/got-abuse.ll new file mode 100644 index 000000000000..c474e5845a64 --- /dev/null +++ b/test/CodeGen/AArch64/got-abuse.ll @@ -0,0 +1,23 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -filetype=obj < %s + +; LLVM gives well-defined semantics to this horrible construct (though C says +; it's undefined). Regardless, we shouldn't crash. The important feature here is +; that in general the only way to access a GOT symbol is via a 64-bit +; load. Neither of these alternatives has the ELF relocations required to +; support it: +; + ldr wD, [xN, #:got_lo12:func] +; + add xD, xN, #:got_lo12:func + +declare void @consume(i32) +declare void @func() + +define void @foo() nounwind { +; CHECK: foo: +entry: + call void @consume(i32 ptrtoint (void ()* @func to i32)) +; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:func +; CHECK: ldr {{x[0-9]+}}, [x[[ADDRHI]], #:got_lo12:func] + ret void +} + diff --git a/test/CodeGen/AArch64/i128-align.ll b/test/CodeGen/AArch64/i128-align.ll new file mode 100644 index 000000000000..f019ea0a6706 --- /dev/null +++ b/test/CodeGen/AArch64/i128-align.ll @@ -0,0 +1,29 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +%struct = type { i32, i128, i8 } + +@var = global %struct zeroinitializer + +define i64 @check_size() { +; CHECK: check_size: + %starti = ptrtoint %struct* @var to i64 + + %endp = getelementptr %struct* @var, i64 1 + %endi = ptrtoint %struct* %endp to i64 + + %diff = sub i64 %endi, %starti + ret i64 %diff +; CHECK: movz x0, #48 +} + +define i64 @check_field() { +; CHECK: check_field: + %starti = ptrtoint %struct* @var to i64 + + %endp = getelementptr %struct* @var, i64 0, i32 1 + %endi = ptrtoint i128* %endp to i64 + + %diff = sub i64 %endi, %starti + ret i64 %diff +; CHECK: movz x0, #16 +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/illegal-float-ops.ll b/test/CodeGen/AArch64/illegal-float-ops.ll new file mode 100644 index 000000000000..446151b8ffac --- /dev/null +++ b/test/CodeGen/AArch64/illegal-float-ops.ll @@ -0,0 +1,221 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +@varfloat = global float 0.0 +@vardouble = global double 0.0 +@varfp128 = global fp128 zeroinitializer + +declare float @llvm.cos.f32(float) +declare double @llvm.cos.f64(double) +declare fp128 @llvm.cos.f128(fp128) + +define void @test_cos(float %float, double %double, fp128 %fp128) { +; CHECK: test_cos: + + %cosfloat = call float @llvm.cos.f32(float %float) + store float %cosfloat, float* @varfloat +; CHECK: bl cosf + + %cosdouble = call double @llvm.cos.f64(double %double) + store double %cosdouble, double* @vardouble +; CHECK: bl cos + + %cosfp128 = call fp128 @llvm.cos.f128(fp128 %fp128) + store fp128 %cosfp128, fp128* @varfp128 +; CHECK: bl cosl + + ret void +} + +declare float @llvm.exp.f32(float) +declare double @llvm.exp.f64(double) +declare fp128 @llvm.exp.f128(fp128) + +define void @test_exp(float %float, double %double, fp128 %fp128) { +; CHECK: test_exp: + + %expfloat = call float @llvm.exp.f32(float %float) + store float %expfloat, float* @varfloat +; CHECK: bl expf + + %expdouble = call double @llvm.exp.f64(double %double) + store double %expdouble, double* @vardouble +; CHECK: bl exp + + %expfp128 = call fp128 @llvm.exp.f128(fp128 %fp128) + store fp128 %expfp128, fp128* @varfp128 +; CHECK: bl expl + + ret void +} + +declare float @llvm.exp2.f32(float) +declare double @llvm.exp2.f64(double) +declare fp128 @llvm.exp2.f128(fp128) + +define void @test_exp2(float %float, double %double, fp128 %fp128) { +; CHECK: test_exp2: + + %exp2float = call float @llvm.exp2.f32(float %float) + store float %exp2float, float* @varfloat +; CHECK: bl exp2f + + %exp2double = call double @llvm.exp2.f64(double %double) + store double %exp2double, double* @vardouble +; CHECK: bl exp2 + + %exp2fp128 = call fp128 @llvm.exp2.f128(fp128 %fp128) + store fp128 %exp2fp128, fp128* @varfp128 +; CHECK: bl exp2l + ret void + +} + +declare float @llvm.log.f32(float) +declare double @llvm.log.f64(double) +declare fp128 @llvm.log.f128(fp128) + +define void @test_log(float %float, double %double, fp128 %fp128) { +; CHECK: test_log: + + %logfloat = call float @llvm.log.f32(float %float) + store float %logfloat, float* @varfloat +; CHECK: bl logf + + %logdouble = call double @llvm.log.f64(double %double) + store double %logdouble, double* @vardouble +; CHECK: bl log + + %logfp128 = call fp128 @llvm.log.f128(fp128 %fp128) + store fp128 %logfp128, fp128* @varfp128 +; CHECK: bl logl + + ret void +} + +declare float @llvm.log2.f32(float) +declare double @llvm.log2.f64(double) +declare fp128 @llvm.log2.f128(fp128) + +define void @test_log2(float %float, double %double, fp128 %fp128) { +; CHECK: test_log2: + + %log2float = call float @llvm.log2.f32(float %float) + store float %log2float, float* @varfloat +; CHECK: bl log2f + + %log2double = call double @llvm.log2.f64(double %double) + store double %log2double, double* @vardouble +; CHECK: bl log2 + + %log2fp128 = call fp128 @llvm.log2.f128(fp128 %fp128) + store fp128 %log2fp128, fp128* @varfp128 +; CHECK: bl log2l + ret void + +} + +declare float @llvm.log10.f32(float) +declare double @llvm.log10.f64(double) +declare fp128 @llvm.log10.f128(fp128) + +define void @test_log10(float %float, double %double, fp128 %fp128) { +; CHECK: test_log10: + + %log10float = call float @llvm.log10.f32(float %float) + store float %log10float, float* @varfloat +; CHECK: bl log10f + + %log10double = call double @llvm.log10.f64(double %double) + store double %log10double, double* @vardouble +; CHECK: bl log10 + + %log10fp128 = call fp128 @llvm.log10.f128(fp128 %fp128) + store fp128 %log10fp128, fp128* @varfp128 +; CHECK: bl log10l + + ret void +} + +declare float @llvm.sin.f32(float) +declare double @llvm.sin.f64(double) +declare fp128 @llvm.sin.f128(fp128) + +define void @test_sin(float %float, double %double, fp128 %fp128) { +; CHECK: test_sin: + + %sinfloat = call float @llvm.sin.f32(float %float) + store float %sinfloat, float* @varfloat +; CHECK: bl sinf + + %sindouble = call double @llvm.sin.f64(double %double) + store double %sindouble, double* @vardouble +; CHECK: bl sin + + %sinfp128 = call fp128 @llvm.sin.f128(fp128 %fp128) + store fp128 %sinfp128, fp128* @varfp128 +; CHECK: bl sinl + ret void + +} + +declare float @llvm.pow.f32(float, float) +declare double @llvm.pow.f64(double, double) +declare fp128 @llvm.pow.f128(fp128, fp128) + +define void @test_pow(float %float, double %double, fp128 %fp128) { +; CHECK: test_pow: + + %powfloat = call float @llvm.pow.f32(float %float, float %float) + store float %powfloat, float* @varfloat +; CHECK: bl powf + + %powdouble = call double @llvm.pow.f64(double %double, double %double) + store double %powdouble, double* @vardouble +; CHECK: bl pow + + %powfp128 = call fp128 @llvm.pow.f128(fp128 %fp128, fp128 %fp128) + store fp128 %powfp128, fp128* @varfp128 +; CHECK: bl powl + + ret void +} + +declare float @llvm.powi.f32(float, i32) +declare double @llvm.powi.f64(double, i32) +declare fp128 @llvm.powi.f128(fp128, i32) + +define void @test_powi(float %float, double %double, i32 %exponent, fp128 %fp128) { +; CHECK: test_powi: + + %powifloat = call float @llvm.powi.f32(float %float, i32 %exponent) + store float %powifloat, float* @varfloat +; CHECK: bl __powisf2 + + %powidouble = call double @llvm.powi.f64(double %double, i32 %exponent) + store double %powidouble, double* @vardouble +; CHECK: bl __powidf2 + + %powifp128 = call fp128 @llvm.powi.f128(fp128 %fp128, i32 %exponent) + store fp128 %powifp128, fp128* @varfp128 +; CHECK: bl __powitf2 + ret void + +} + +define void @test_frem(float %float, double %double, fp128 %fp128) { +; CHECK: test_frem: + + %fremfloat = frem float %float, %float + store float %fremfloat, float* @varfloat +; CHECK: bl fmodf + + %fremdouble = frem double %double, %double + store double %fremdouble, double* @vardouble +; CHECK: bl fmod + + %fremfp128 = frem fp128 %fp128, %fp128 + store fp128 %fremfp128, fp128* @varfp128 +; CHECK: bl fmodl + + ret void +} diff --git a/test/CodeGen/AArch64/init-array.ll b/test/CodeGen/AArch64/init-array.ll new file mode 100644 index 000000000000..d80be8f3a639 --- /dev/null +++ b/test/CodeGen/AArch64/init-array.ll @@ -0,0 +1,9 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -use-init-array < %s | FileCheck %s + +define internal void @_GLOBAL__I_a() section ".text.startup" { + ret void +} + +@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }] + +; CHECK: .section .init_array \ No newline at end of file diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badI.ll b/test/CodeGen/AArch64/inline-asm-constraints-badI.ll new file mode 100644 index 000000000000..c39c57f05822 --- /dev/null +++ b/test/CodeGen/AArch64/inline-asm-constraints-badI.ll @@ -0,0 +1,7 @@ +; RUN: not llc -mtriple=aarch64-none-linux-gnu < %s + +define void @foo() { + ; Out of range immediate for I. + call void asm sideeffect "add x0, x0, $0", "I"(i32 4096) + ret void +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badK.ll b/test/CodeGen/AArch64/inline-asm-constraints-badK.ll new file mode 100644 index 000000000000..47c5f98bf009 --- /dev/null +++ b/test/CodeGen/AArch64/inline-asm-constraints-badK.ll @@ -0,0 +1,7 @@ +; RUN: not llc -mtriple=aarch64-none-linux-gnu < %s + +define void @foo() { + ; 32-bit bitpattern ending in 1101 can't be produced. + call void asm sideeffect "and w0, w0, $0", "K"(i32 13) + ret void +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll b/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll new file mode 100644 index 000000000000..7a5b99e23b3d --- /dev/null +++ b/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll @@ -0,0 +1,7 @@ +; RUN: not llc -mtriple=aarch64-none-linux-gnu < %s + +define void @foo() { + ; 32-bit bitpattern ending in 1101 can't be produced. + call void asm sideeffect "and w0, w0, $0", "K"(i64 4294967296) + ret void +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badL.ll b/test/CodeGen/AArch64/inline-asm-constraints-badL.ll new file mode 100644 index 000000000000..4f0039865a35 --- /dev/null +++ b/test/CodeGen/AArch64/inline-asm-constraints-badL.ll @@ -0,0 +1,7 @@ +; RUN: not llc -mtriple=aarch64-none-linux-gnu < %s + +define void @foo() { + ; 32-bit bitpattern ending in 1101 can't be produced. + call void asm sideeffect "and x0, x0, $0", "L"(i32 13) + ret void +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/inline-asm-constraints.ll b/test/CodeGen/AArch64/inline-asm-constraints.ll new file mode 100644 index 000000000000..c232f3208cfa --- /dev/null +++ b/test/CodeGen/AArch64/inline-asm-constraints.ll @@ -0,0 +1,117 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +define i64 @test_inline_constraint_r(i64 %base, i32 %offset) { +; CHECK: test_inline_constraint_r: + %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset) +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw + ret i64 %val +} + +define i16 @test_small_reg(i16 %lhs, i16 %rhs) { +; CHECK: test_small_reg: + %val = call i16 asm sideeffect "add $0, $1, $2, sxth", "=r,r,r"(i16 %lhs, i16 %rhs) +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth + ret i16 %val +} + +define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) { +; CHECK: test_inline_constraint_r_imm: + %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 4, i32 12) +; CHECK: movz [[FOUR:x[0-9]+]], #4 +; CHECK: movz [[TWELVE:w[0-9]+]], #12 +; CHECK: add {{x[0-9]+}}, [[FOUR]], [[TWELVE]], sxtw + ret i64 %val +} + +; m is permitted to have a base/offset form. We don't do that +; currently though. +define i32 @test_inline_constraint_m(i32 *%ptr) { +; CHECK: test_inline_constraint_m: + %val = call i32 asm "ldr $0, $1", "=r,m"(i32 *%ptr) +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}] + ret i32 %val +} + +@arr = global [8 x i32] zeroinitializer + +; Q should *never* have base/offset form even if given the chance. +define i32 @test_inline_constraint_Q(i32 *%ptr) { +; CHECK: test_inline_constraint_Q: + %val = call i32 asm "ldr $0, $1", "=r,Q"(i32* getelementptr([8 x i32]* @arr, i32 0, i32 1)) +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}] + ret i32 %val +} + +@dump = global fp128 zeroinitializer + +define void @test_inline_constraint_I() { +; CHECK: test_inline_constraint_I: + call void asm sideeffect "add x0, x0, $0", "I"(i32 0) + call void asm sideeffect "add x0, x0, $0", "I"(i64 4095) +; CHECK: add x0, x0, #0 +; CHECK: add x0, x0, #4095 + + ret void +} + +; Skip J because it's useless + +define void @test_inline_constraint_K() { +; CHECK: test_inline_constraint_K: + call void asm sideeffect "and w0, w0, $0", "K"(i32 2863311530) ; = 0xaaaaaaaa + call void asm sideeffect "and w0, w0, $0", "K"(i32 65535) +; CHECK: and w0, w0, #-1431655766 +; CHECK: and w0, w0, #65535 + + ret void +} + +define void @test_inline_constraint_L() { +; CHECK: test_inline_constraint_L: + call void asm sideeffect "and x0, x0, $0", "L"(i64 4294967296) ; = 0xaaaaaaaa + call void asm sideeffect "and x0, x0, $0", "L"(i64 65535) +; CHECK: and x0, x0, #4294967296 +; CHECK: and x0, x0, #65535 + + ret void +} + +; Skip M and N because we don't support MOV pseudo-instructions yet. + +@var = global i32 0 + +define void @test_inline_constraint_S() { +; CHECK: test_inline_constraint_S: + call void asm sideeffect "adrp x0, $0", "S"(i32* @var) + call void asm sideeffect "adrp x0, ${0:A}", "S"(i32* @var) + call void asm sideeffect "add x0, x0, ${0:L}", "S"(i32* @var) +; CHECK: adrp x0, var +; CHECK: adrp x0, var +; CHECK: add x0, x0, #:lo12:var + ret void +} + +define i32 @test_inline_constraint_S_label(i1 %in) { +; CHECK: test_inline_constraint_S_label: + call void asm sideeffect "adr x0, $0", "S"(i8* blockaddress(@test_inline_constraint_S_label, %loc)) +; CHECK: adr x0, .Ltmp{{[0-9]+}} + br i1 %in, label %loc, label %loc2 +loc: + ret i32 0 +loc2: + ret i32 42 +} + +define void @test_inline_constraint_Y() { +; CHECK: test_inline_constraint_Y: + call void asm sideeffect "fcmp s0, $0", "Y"(float 0.0) +; CHECK: fcmp s0, #0.0 + ret void +} + +define void @test_inline_constraint_Z() { +; CHECK: test_inline_constraint_Z: + call void asm sideeffect "cmp w0, $0", "Z"(i32 0) +; CHECK: cmp w0, #0 + ret void +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/inline-asm-modifiers.ll b/test/CodeGen/AArch64/inline-asm-modifiers.ll new file mode 100644 index 000000000000..3b55945561eb --- /dev/null +++ b/test/CodeGen/AArch64/inline-asm-modifiers.ll @@ -0,0 +1,125 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-ELF %s + +@var_simple = hidden global i32 0 +@var_got = global i32 0 +@var_tlsgd = thread_local global i32 0 +@var_tlsld = thread_local(localdynamic) global i32 0 +@var_tlsie = thread_local(initialexec) global i32 0 +@var_tlsle = thread_local(localexec) global i32 0 + +define void @test_inline_modifier_L() nounwind { +; CHECK: test_inline_modifier_L: + call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_simple) + call void asm sideeffect "ldr x0, [x0, ${0:L}]", "S,~{x0}"(i32* @var_got) + call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_tlsgd) + call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_tlsld) + call void asm sideeffect "ldr x0, [x0, ${0:L}]", "S,~{x0}"(i32* @var_tlsie) + call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_tlsle) +; CHECK: add x0, x0, #:lo12:var_simple +; CHECK: ldr x0, [x0, #:got_lo12:var_got] +; CHECK: add x0, x0, #:tlsdesc_lo12:var_tlsgd +; CHECK: add x0, x0, #:dtprel_lo12:var_tlsld +; CHECK: ldr x0, [x0, #:gottprel_lo12:var_tlsie] +; CHECK: add x0, x0, #:tprel_lo12:var_tlsle + +; CHECK-ELF: R_AARCH64_ADD_ABS_LO12_NC var_simple +; CHECK-ELF: R_AARCH64_LD64_GOT_LO12_NC var_got +; CHECK-ELF: R_AARCH64_TLSDESC_ADD_LO12_NC var_tlsgd +; CHECK-ELF: R_AARCH64_TLSLD_ADD_DTPREL_LO12 var_tlsld +; CHECK-ELF: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC var_tlsie +; CHECK-ELF: R_AARCH64_TLSLE_ADD_TPREL_LO12 var_tlsle + + ret void +} + +define void @test_inline_modifier_G() nounwind { +; CHECK: test_inline_modifier_G: + call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsld) + call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsle) +; CHECK: add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12 +; CHECK: add x0, x0, #:tprel_hi12:var_tlsle, lsl #12 + +; CHECK-ELF: R_AARCH64_TLSLD_ADD_DTPREL_HI12 var_tlsld +; CHECK-ELF: R_AARCH64_TLSLE_ADD_TPREL_HI12 var_tlsle + + ret void +} + +define void @test_inline_modifier_A() nounwind { +; CHECK: test_inline_modifier_A: + call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_simple) + call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_got) + call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_tlsgd) + call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_tlsie) + ; N.b. All tprel and dtprel relocs are modified: lo12 or granules. +; CHECK: adrp x0, var_simple +; CHECK: adrp x0, :got:var_got +; CHECK: adrp x0, :tlsdesc:var_tlsgd +; CHECK: adrp x0, :gottprel:var_tlsie + +; CHECK-ELF: R_AARCH64_ADR_PREL_PG_HI21 var_simple +; CHECK-ELF: R_AARCH64_ADR_GOT_PAGE var_got +; CHECK-ELF: R_AARCH64_TLSDESC_ADR_PAGE var_tlsgd +; CHECK-ELF: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 var_tlsie + + ret void +} + +define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind { +; CHECK: test_inline_modifier_wx: + call i32 asm sideeffect "add $0, $0, $0", "=r,0"(i32 %small) + call i32 asm sideeffect "add ${0:w}, ${0:w}, ${0:w}", "=r,0"(i32 %small) + call i32 asm sideeffect "add ${0:x}, ${0:x}, ${0:x}", "=r,0"(i32 %small) +; CHECK: //APP +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + + call i64 asm sideeffect "add $0, $0, $0", "=r,0"(i64 %big) + call i64 asm sideeffect "add ${0:w}, ${0:w}, ${0:w}", "=r,0"(i64 %big) + call i64 asm sideeffect "add ${0:x}, ${0:x}, ${0:x}", "=r,0"(i64 %big) +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} +; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + + call i32 asm sideeffect "add ${0:w}, ${1:w}, ${1:w}", "=r,r"(i32 0) + call i32 asm sideeffect "add ${0:x}, ${1:x}, ${1:x}", "=r,r"(i32 0) +; CHECK: add {{w[0-9]+}}, wzr, wzr +; CHECK: add {{x[0-9]+}}, xzr, xzr + ret void +} + +define void @test_inline_modifier_bhsdq() nounwind { +; CHECK: test_inline_modifier_bhsdq: + call float asm sideeffect "ldr ${0:b}, [sp]", "=w"() + call float asm sideeffect "ldr ${0:h}, [sp]", "=w"() + call float asm sideeffect "ldr ${0:s}, [sp]", "=w"() + call float asm sideeffect "ldr ${0:d}, [sp]", "=w"() + call float asm sideeffect "ldr ${0:q}, [sp]", "=w"() +; CHECK: ldr b0, [sp] +; CHECK: ldr h0, [sp] +; CHECK: ldr s0, [sp] +; CHECK: ldr d0, [sp] +; CHECK: ldr q0, [sp] + + call double asm sideeffect "ldr ${0:b}, [sp]", "=w"() + call double asm sideeffect "ldr ${0:h}, [sp]", "=w"() + call double asm sideeffect "ldr ${0:s}, [sp]", "=w"() + call double asm sideeffect "ldr ${0:d}, [sp]", "=w"() + call double asm sideeffect "ldr ${0:q}, [sp]", "=w"() +; CHECK: ldr b0, [sp] +; CHECK: ldr h0, [sp] +; CHECK: ldr s0, [sp] +; CHECK: ldr d0, [sp] +; CHECK: ldr q0, [sp] + ret void +} + +define void @test_inline_modifier_c() nounwind { +; CHECK: test_inline_modifier_c: + call void asm sideeffect "adr x0, ${0:c}", "i"(i32 3) +; CHECK: adr x0, 3 + + ret void +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/jump-table.ll b/test/CodeGen/AArch64/jump-table.ll new file mode 100644 index 000000000000..dcf9f4ed455c --- /dev/null +++ b/test/CodeGen/AArch64/jump-table.ll @@ -0,0 +1,56 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -filetype=obj | elf-dump | FileCheck %s -check-prefix=CHECK-ELF + +define i32 @test_jumptable(i32 %in) { +; CHECK: test_jumptable + + switch i32 %in, label %def [ + i32 0, label %lbl1 + i32 1, label %lbl2 + i32 2, label %lbl3 + i32 4, label %lbl4 + ] +; CHECK: adrp [[JTPAGE:x[0-9]+]], .LJTI0_0 +; CHECK: add x[[JT:[0-9]+]], [[JTPAGE]], #:lo12:.LJTI0_0 +; CHECK: ldr [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #3] +; CHECK: br [[DEST]] + +def: + ret i32 0 + +lbl1: + ret i32 1 + +lbl2: + ret i32 2 + +lbl3: + ret i32 4 + +lbl4: + ret i32 8 + +} + +; CHECK: .rodata + +; CHECK: .LJTI0_0: +; CHECK-NEXT: .xword +; CHECK-NEXT: .xword +; CHECK-NEXT: .xword +; CHECK-NEXT: .xword +; CHECK-NEXT: .xword + +; ELF tests: + +; First make sure we get a page/lo12 pair in .text to pick up the jump-table +; CHECK-ELF: .rela.text +; CHECK-ELF: ('r_sym', 0x00000008) +; CHECK-ELF-NEXT: ('r_type', 0x00000113) +; CHECK-ELF: ('r_sym', 0x00000008) +; CHECK-ELF-NEXT: ('r_type', 0x00000115) + +; Also check the targets in .rodata are relocated +; CHECK-ELF: .rela.rodata +; CHECK-ELF: ('r_sym', 0x00000005) +; CHECK-ELF-NEXT: ('r_type', 0x00000101) \ No newline at end of file diff --git a/test/CodeGen/AArch64/large-frame.ll b/test/CodeGen/AArch64/large-frame.ll new file mode 100644 index 000000000000..2b2e1295c4f6 --- /dev/null +++ b/test/CodeGen/AArch64/large-frame.ll @@ -0,0 +1,114 @@ +; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s +declare void @use_addr(i8*) + +@addr = global i8* null + +define void @test_bigframe() { +; CHECK: test_bigframe: + + %var1 = alloca i8, i32 20000000 + %var2 = alloca i8, i32 16 + %var3 = alloca i8, i32 20000000 +; CHECK: sub sp, sp, #496 +; CHECK: str x30, [sp, #488] + ; Total adjust is 39999536 +; CHECK: movz [[SUBCONST:x[0-9]+]], #22576 +; CHECK: movk [[SUBCONST]], #610, lsl #16 +; CHECK: sub sp, sp, [[SUBCONST]] + + ; Total offset is 20000024 +; CHECK: movz [[VAR1OFFSET:x[0-9]+]], #11544 +; CHECK: movk [[VAR1OFFSET]], #305, lsl #16 +; CHECK: add {{x[0-9]+}}, sp, [[VAR1OFFSET]] + store volatile i8* %var1, i8** @addr + + %var1plus2 = getelementptr i8* %var1, i32 2 + store volatile i8* %var1plus2, i8** @addr + +; CHECK: movz [[VAR2OFFSET:x[0-9]+]], #11528 +; CHECK: movk [[VAR2OFFSET]], #305, lsl #16 +; CHECK: add {{x[0-9]+}}, sp, [[VAR2OFFSET]] + store volatile i8* %var2, i8** @addr + + %var2plus2 = getelementptr i8* %var2, i32 2 + store volatile i8* %var2plus2, i8** @addr + + store volatile i8* %var3, i8** @addr + + %var3plus2 = getelementptr i8* %var3, i32 2 + store volatile i8* %var3plus2, i8** @addr + +; CHECK: movz [[ADDCONST:x[0-9]+]], #22576 +; CHECK: movk [[ADDCONST]], #610, lsl #16 +; CHECK: add sp, sp, [[ADDCONST]] + ret void +} + +define void @test_mediumframe() { +; CHECK: test_mediumframe: + %var1 = alloca i8, i32 1000000 + %var2 = alloca i8, i32 16 + %var3 = alloca i8, i32 1000000 +; CHECK: sub sp, sp, #496 +; CHECK: str x30, [sp, #488] +; CHECK: sub sp, sp, #688 +; CHECK-NEXT: sub sp, sp, #488, lsl #12 + + store volatile i8* %var1, i8** @addr +; CHECK: add [[VAR1ADDR:x[0-9]+]], sp, #600 +; CHECK: add [[VAR1ADDR]], [[VAR1ADDR]], #244, lsl #12 + + %var1plus2 = getelementptr i8* %var1, i32 2 + store volatile i8* %var1plus2, i8** @addr +; CHECK: add [[VAR1PLUS2:x[0-9]+]], {{x[0-9]+}}, #2 + + store volatile i8* %var2, i8** @addr +; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #584 +; CHECK: add [[VAR2ADDR]], [[VAR2ADDR]], #244, lsl #12 + + %var2plus2 = getelementptr i8* %var2, i32 2 + store volatile i8* %var2plus2, i8** @addr +; CHECK: add [[VAR2PLUS2:x[0-9]+]], {{x[0-9]+}}, #2 + + store volatile i8* %var3, i8** @addr + + %var3plus2 = getelementptr i8* %var3, i32 2 + store volatile i8* %var3plus2, i8** @addr + +; CHECK: add sp, sp, #688 +; CHECK: add sp, sp, #488, lsl #12 +; CHECK: ldr x30, [sp, #488] +; CHECK: add sp, sp, #496 + ret void +} + + +@bigspace = global [8 x i64] zeroinitializer + +; If temporary registers are allocated for adjustment, they should *not* clobber +; argument registers. +define void @test_tempallocation([8 x i64] %val) nounwind { +; CHECK: test_tempallocation: + %var = alloca i8, i32 1000000 +; CHECK: sub sp, sp, + +; Make sure the prologue is reasonably efficient +; CHECK-NEXT: stp x29, x30, [sp, +; CHECK-NEXT: stp x25, x26, [sp, +; CHECK-NEXT: stp x23, x24, [sp, +; CHECK-NEXT: stp x21, x22, [sp, +; CHECK-NEXT: stp x19, x20, [sp, + +; Make sure we don't trash an argument register +; CHECK-NOT: movz {{x[0-7],}} +; CHECK: sub sp, sp, + +; CHECK-NOT: movz {{x[0-7],}} + +; CHECK: bl use_addr + call void @use_addr(i8* %var) + + store [8 x i64] %val, [8 x i64]* @bigspace + ret void +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/ldst-regoffset.ll b/test/CodeGen/AArch64/ldst-regoffset.ll new file mode 100644 index 000000000000..45935129fd7e --- /dev/null +++ b/test/CodeGen/AArch64/ldst-regoffset.ll @@ -0,0 +1,333 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var_8bit = global i8 0 +@var_16bit = global i16 0 +@var_32bit = global i32 0 +@var_64bit = global i64 0 + +@var_float = global float 0.0 +@var_double = global double 0.0 + +define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) { +; CHECK: ldst_8bit: + + %addr8_sxtw = getelementptr i8* %base, i32 %off32 + %val8_sxtw = load volatile i8* %addr8_sxtw + %val32_signed = sext i8 %val8_sxtw to i32 + store volatile i32 %val32_signed, i32* @var_32bit +; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] + + %addr_lsl = getelementptr i8* %base, i64 %off64 + %val8_lsl = load volatile i8* %addr_lsl + %val32_unsigned = zext i8 %val8_lsl to i32 + store volatile i32 %val32_unsigned, i32* @var_32bit +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] + + %addrint_uxtw = ptrtoint i8* %base to i64 + %offset_uxtw = zext i32 %off32 to i64 + %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw + %addr_uxtw = inttoptr i64 %addrint1_uxtw to i8* + %val8_uxtw = load volatile i8* %addr_uxtw + %newval8 = add i8 %val8_uxtw, 1 + store volatile i8 %newval8, i8* @var_8bit +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] + + ret void +} + + +define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) { +; CHECK: ldst_16bit: + + %addr8_sxtwN = getelementptr i16* %base, i32 %off32 + %val8_sxtwN = load volatile i16* %addr8_sxtwN + %val32_signed = sext i16 %val8_sxtwN to i32 + store volatile i32 %val32_signed, i32* @var_32bit +; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #1] + + %addr_lslN = getelementptr i16* %base, i64 %off64 + %val8_lslN = load volatile i16* %addr_lslN + %val32_unsigned = zext i16 %val8_lslN to i32 + store volatile i32 %val32_unsigned, i32* @var_32bit +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #1] + + %addrint_uxtw = ptrtoint i16* %base to i64 + %offset_uxtw = zext i32 %off32 to i64 + %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw + %addr_uxtw = inttoptr i64 %addrint1_uxtw to i16* + %val8_uxtw = load volatile i16* %addr_uxtw + %newval8 = add i16 %val8_uxtw, 1 + store volatile i16 %newval8, i16* @var_16bit +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] + + %base_sxtw = ptrtoint i16* %base to i64 + %offset_sxtw = sext i32 %off32 to i64 + %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw + %addr_sxtw = inttoptr i64 %addrint_sxtw to i16* + %val16_sxtw = load volatile i16* %addr_sxtw + %val64_signed = sext i16 %val16_sxtw to i64 + store volatile i64 %val64_signed, i64* @var_64bit +; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] + + + %base_lsl = ptrtoint i16* %base to i64 + %addrint_lsl = add i64 %base_lsl, %off64 + %addr_lsl = inttoptr i64 %addrint_lsl to i16* + %val16_lsl = load volatile i16* %addr_lsl + %val64_unsigned = zext i16 %val16_lsl to i64 + store volatile i64 %val64_unsigned, i64* @var_64bit +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] + + %base_uxtwN = ptrtoint i16* %base to i64 + %offset_uxtwN = zext i32 %off32 to i64 + %offset2_uxtwN = shl i64 %offset_uxtwN, 1 + %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN + %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i16* + %val32 = load volatile i32* @var_32bit + %val16_trunc32 = trunc i32 %val32 to i16 + store volatile i16 %val16_trunc32, i16* %addr_uxtwN +; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #1] + ret void +} + +define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) { +; CHECK: ldst_32bit: + + %addr_sxtwN = getelementptr i32* %base, i32 %off32 + %val_sxtwN = load volatile i32* %addr_sxtwN + store volatile i32 %val_sxtwN, i32* @var_32bit +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #2] + + %addr_lslN = getelementptr i32* %base, i64 %off64 + %val_lslN = load volatile i32* %addr_lslN + store volatile i32 %val_lslN, i32* @var_32bit +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #2] + + %addrint_uxtw = ptrtoint i32* %base to i64 + %offset_uxtw = zext i32 %off32 to i64 + %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw + %addr_uxtw = inttoptr i64 %addrint1_uxtw to i32* + %val_uxtw = load volatile i32* %addr_uxtw + %newval8 = add i32 %val_uxtw, 1 + store volatile i32 %newval8, i32* @var_32bit +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] + + + %base_sxtw = ptrtoint i32* %base to i64 + %offset_sxtw = sext i32 %off32 to i64 + %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw + %addr_sxtw = inttoptr i64 %addrint_sxtw to i32* + %val16_sxtw = load volatile i32* %addr_sxtw + %val64_signed = sext i32 %val16_sxtw to i64 + store volatile i64 %val64_signed, i64* @var_64bit +; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] + + + %base_lsl = ptrtoint i32* %base to i64 + %addrint_lsl = add i64 %base_lsl, %off64 + %addr_lsl = inttoptr i64 %addrint_lsl to i32* + %val16_lsl = load volatile i32* %addr_lsl + %val64_unsigned = zext i32 %val16_lsl to i64 + store volatile i64 %val64_unsigned, i64* @var_64bit +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] + + %base_uxtwN = ptrtoint i32* %base to i64 + %offset_uxtwN = zext i32 %off32 to i64 + %offset2_uxtwN = shl i64 %offset_uxtwN, 2 + %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN + %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i32* + %val32 = load volatile i32* @var_32bit + store volatile i32 %val32, i32* %addr_uxtwN +; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2] + ret void +} + +define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) { +; CHECK: ldst_64bit: + + %addr_sxtwN = getelementptr i64* %base, i32 %off32 + %val_sxtwN = load volatile i64* %addr_sxtwN + store volatile i64 %val_sxtwN, i64* @var_64bit +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #3] + + %addr_lslN = getelementptr i64* %base, i64 %off64 + %val_lslN = load volatile i64* %addr_lslN + store volatile i64 %val_lslN, i64* @var_64bit +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #3] + + %addrint_uxtw = ptrtoint i64* %base to i64 + %offset_uxtw = zext i32 %off32 to i64 + %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw + %addr_uxtw = inttoptr i64 %addrint1_uxtw to i64* + %val8_uxtw = load volatile i64* %addr_uxtw + %newval8 = add i64 %val8_uxtw, 1 + store volatile i64 %newval8, i64* @var_64bit +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] + + %base_sxtw = ptrtoint i64* %base to i64 + %offset_sxtw = sext i32 %off32 to i64 + %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw + %addr_sxtw = inttoptr i64 %addrint_sxtw to i64* + %val64_sxtw = load volatile i64* %addr_sxtw + store volatile i64 %val64_sxtw, i64* @var_64bit +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] + + %base_lsl = ptrtoint i64* %base to i64 + %addrint_lsl = add i64 %base_lsl, %off64 + %addr_lsl = inttoptr i64 %addrint_lsl to i64* + %val64_lsl = load volatile i64* %addr_lsl + store volatile i64 %val64_lsl, i64* @var_64bit +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] + + %base_uxtwN = ptrtoint i64* %base to i64 + %offset_uxtwN = zext i32 %off32 to i64 + %offset2_uxtwN = shl i64 %offset_uxtwN, 3 + %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN + %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i64* + %val64 = load volatile i64* @var_64bit + store volatile i64 %val64, i64* %addr_uxtwN +; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3] + ret void +} + +define void @ldst_float(float* %base, i32 %off32, i64 %off64) { +; CHECK: ldst_float: + + %addr_sxtwN = getelementptr float* %base, i32 %off32 + %val_sxtwN = load volatile float* %addr_sxtwN + store volatile float %val_sxtwN, float* @var_float +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #2] + + %addr_lslN = getelementptr float* %base, i64 %off64 + %val_lslN = load volatile float* %addr_lslN + store volatile float %val_lslN, float* @var_float +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #2] + + %addrint_uxtw = ptrtoint float* %base to i64 + %offset_uxtw = zext i32 %off32 to i64 + %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw + %addr_uxtw = inttoptr i64 %addrint1_uxtw to float* + %val_uxtw = load volatile float* %addr_uxtw + store volatile float %val_uxtw, float* @var_float +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] + + %base_sxtw = ptrtoint float* %base to i64 + %offset_sxtw = sext i32 %off32 to i64 + %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw + %addr_sxtw = inttoptr i64 %addrint_sxtw to float* + %val64_sxtw = load volatile float* %addr_sxtw + store volatile float %val64_sxtw, float* @var_float +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] + + %base_lsl = ptrtoint float* %base to i64 + %addrint_lsl = add i64 %base_lsl, %off64 + %addr_lsl = inttoptr i64 %addrint_lsl to float* + %val64_lsl = load volatile float* %addr_lsl + store volatile float %val64_lsl, float* @var_float +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] + + %base_uxtwN = ptrtoint float* %base to i64 + %offset_uxtwN = zext i32 %off32 to i64 + %offset2_uxtwN = shl i64 %offset_uxtwN, 2 + %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN + %addr_uxtwN = inttoptr i64 %addrint_uxtwN to float* + %val64 = load volatile float* @var_float + store volatile float %val64, float* %addr_uxtwN +; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2] + ret void +} + +define void @ldst_double(double* %base, i32 %off32, i64 %off64) { +; CHECK: ldst_double: + + %addr_sxtwN = getelementptr double* %base, i32 %off32 + %val_sxtwN = load volatile double* %addr_sxtwN + store volatile double %val_sxtwN, double* @var_double +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #3] + + %addr_lslN = getelementptr double* %base, i64 %off64 + %val_lslN = load volatile double* %addr_lslN + store volatile double %val_lslN, double* @var_double +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #3] + + %addrint_uxtw = ptrtoint double* %base to i64 + %offset_uxtw = zext i32 %off32 to i64 + %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw + %addr_uxtw = inttoptr i64 %addrint1_uxtw to double* + %val_uxtw = load volatile double* %addr_uxtw + store volatile double %val_uxtw, double* @var_double +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] + + %base_sxtw = ptrtoint double* %base to i64 + %offset_sxtw = sext i32 %off32 to i64 + %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw + %addr_sxtw = inttoptr i64 %addrint_sxtw to double* + %val64_sxtw = load volatile double* %addr_sxtw + store volatile double %val64_sxtw, double* @var_double +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] + + %base_lsl = ptrtoint double* %base to i64 + %addrint_lsl = add i64 %base_lsl, %off64 + %addr_lsl = inttoptr i64 %addrint_lsl to double* + %val64_lsl = load volatile double* %addr_lsl + store volatile double %val64_lsl, double* @var_double +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] + + %base_uxtwN = ptrtoint double* %base to i64 + %offset_uxtwN = zext i32 %off32 to i64 + %offset2_uxtwN = shl i64 %offset_uxtwN, 3 + %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN + %addr_uxtwN = inttoptr i64 %addrint_uxtwN to double* + %val64 = load volatile double* @var_double + store volatile double %val64, double* %addr_uxtwN +; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3] + ret void +} + + +define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) { +; CHECK: ldst_128bit: + + %addr_sxtwN = getelementptr fp128* %base, i32 %off32 + %val_sxtwN = load volatile fp128* %addr_sxtwN + store volatile fp128 %val_sxtwN, fp128* %base +; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #4] + + %addr_lslN = getelementptr fp128* %base, i64 %off64 + %val_lslN = load volatile fp128* %addr_lslN + store volatile fp128 %val_lslN, fp128* %base +; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #4] + + %addrint_uxtw = ptrtoint fp128* %base to i64 + %offset_uxtw = zext i32 %off32 to i64 + %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw + %addr_uxtw = inttoptr i64 %addrint1_uxtw to fp128* + %val_uxtw = load volatile fp128* %addr_uxtw + store volatile fp128 %val_uxtw, fp128* %base +; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] + + %base_sxtw = ptrtoint fp128* %base to i64 + %offset_sxtw = sext i32 %off32 to i64 + %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw + %addr_sxtw = inttoptr i64 %addrint_sxtw to fp128* + %val64_sxtw = load volatile fp128* %addr_sxtw + store volatile fp128 %val64_sxtw, fp128* %base +; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] + + %base_lsl = ptrtoint fp128* %base to i64 + %addrint_lsl = add i64 %base_lsl, %off64 + %addr_lsl = inttoptr i64 %addrint_lsl to fp128* + %val64_lsl = load volatile fp128* %addr_lsl + store volatile fp128 %val64_lsl, fp128* %base +; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] + + %base_uxtwN = ptrtoint fp128* %base to i64 + %offset_uxtwN = zext i32 %off32 to i64 + %offset2_uxtwN = shl i64 %offset_uxtwN, 4 + %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN + %addr_uxtwN = inttoptr i64 %addrint_uxtwN to fp128* + %val64 = load volatile fp128* %base + store volatile fp128 %val64, fp128* %addr_uxtwN +; CHECK: str {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #4] + ret void +} diff --git a/test/CodeGen/AArch64/ldst-unscaledimm.ll b/test/CodeGen/AArch64/ldst-unscaledimm.ll new file mode 100644 index 000000000000..78a3c83c3dd8 --- /dev/null +++ b/test/CodeGen/AArch64/ldst-unscaledimm.ll @@ -0,0 +1,218 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var_8bit = global i8 0 +@var_16bit = global i16 0 +@var_32bit = global i32 0 +@var_64bit = global i64 0 + +@var_float = global float 0.0 +@var_double = global double 0.0 + +@varptr = global i8* null + +define void @ldst_8bit() { +; CHECK: ldst_8bit: + +; No architectural support for loads to 16-bit or 8-bit since we +; promote i8 during lowering. + %addr_8bit = load i8** @varptr + +; match a sign-extending load 8-bit -> 32-bit + %addr_sext32 = getelementptr i8* %addr_8bit, i64 -256 + %val8_sext32 = load volatile i8* %addr_sext32 + %val32_signed = sext i8 %val8_sext32 to i32 + store volatile i32 %val32_signed, i32* @var_32bit +; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256] + +; match a zero-extending load volatile 8-bit -> 32-bit + %addr_zext32 = getelementptr i8* %addr_8bit, i64 -12 + %val8_zext32 = load volatile i8* %addr_zext32 + %val32_unsigned = zext i8 %val8_zext32 to i32 + store volatile i32 %val32_unsigned, i32* @var_32bit +; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-12] + +; match an any-extending load volatile 8-bit -> 32-bit + %addr_anyext = getelementptr i8* %addr_8bit, i64 -1 + %val8_anyext = load volatile i8* %addr_anyext + %newval8 = add i8 %val8_anyext, 1 + store volatile i8 %newval8, i8* @var_8bit +; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-1] + +; match a sign-extending load volatile 8-bit -> 64-bit + %addr_sext64 = getelementptr i8* %addr_8bit, i64 -5 + %val8_sext64 = load volatile i8* %addr_sext64 + %val64_signed = sext i8 %val8_sext64 to i64 + store volatile i64 %val64_signed, i64* @var_64bit +; CHECK: ldursb {{x[0-9]+}}, [{{x[0-9]+}}, #-5] + +; match a zero-extending load volatile 8-bit -> 64-bit. +; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits +; of x0 so it's identical to load volatileing to 32-bits. + %addr_zext64 = getelementptr i8* %addr_8bit, i64 -9 + %val8_zext64 = load volatile i8* %addr_zext64 + %val64_unsigned = zext i8 %val8_zext64 to i64 + store volatile i64 %val64_unsigned, i64* @var_64bit +; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-9] + +; truncating store volatile 32-bits to 8-bits + %addr_trunc32 = getelementptr i8* %addr_8bit, i64 -256 + %val32 = load volatile i32* @var_32bit + %val8_trunc32 = trunc i32 %val32 to i8 + store volatile i8 %val8_trunc32, i8* %addr_trunc32 +; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-256] + +; truncating store volatile 64-bits to 8-bits + %addr_trunc64 = getelementptr i8* %addr_8bit, i64 -1 + %val64 = load volatile i64* @var_64bit + %val8_trunc64 = trunc i64 %val64 to i8 + store volatile i8 %val8_trunc64, i8* %addr_trunc64 +; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-1] + + ret void +} + +define void @ldst_16bit() { +; CHECK: ldst_16bit: + +; No architectural support for loads to 16-bit or 16-bit since we +; promote i16 during lowering. + %addr_8bit = load i8** @varptr + +; match a sign-extending load 16-bit -> 32-bit + %addr8_sext32 = getelementptr i8* %addr_8bit, i64 -256 + %addr_sext32 = bitcast i8* %addr8_sext32 to i16* + %val16_sext32 = load volatile i16* %addr_sext32 + %val32_signed = sext i16 %val16_sext32 to i32 + store volatile i32 %val32_signed, i32* @var_32bit +; CHECK: ldursh {{w[0-9]+}}, [{{x[0-9]+}}, #-256] + +; match a zero-extending load volatile 16-bit -> 32-bit. With offset that would be unaligned. + %addr8_zext32 = getelementptr i8* %addr_8bit, i64 15 + %addr_zext32 = bitcast i8* %addr8_zext32 to i16* + %val16_zext32 = load volatile i16* %addr_zext32 + %val32_unsigned = zext i16 %val16_zext32 to i32 + store volatile i32 %val32_unsigned, i32* @var_32bit +; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #15] + +; match an any-extending load volatile 16-bit -> 32-bit + %addr8_anyext = getelementptr i8* %addr_8bit, i64 -1 + %addr_anyext = bitcast i8* %addr8_anyext to i16* + %val16_anyext = load volatile i16* %addr_anyext + %newval16 = add i16 %val16_anyext, 1 + store volatile i16 %newval16, i16* @var_16bit +; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-1] + +; match a sign-extending load volatile 16-bit -> 64-bit + %addr8_sext64 = getelementptr i8* %addr_8bit, i64 -5 + %addr_sext64 = bitcast i8* %addr8_sext64 to i16* + %val16_sext64 = load volatile i16* %addr_sext64 + %val64_signed = sext i16 %val16_sext64 to i64 + store volatile i64 %val64_signed, i64* @var_64bit +; CHECK: ldursh {{x[0-9]+}}, [{{x[0-9]+}}, #-5] + +; match a zero-extending load volatile 16-bit -> 64-bit. +; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits +; of x0 so it's identical to load volatileing to 32-bits. + %addr8_zext64 = getelementptr i8* %addr_8bit, i64 9 + %addr_zext64 = bitcast i8* %addr8_zext64 to i16* + %val16_zext64 = load volatile i16* %addr_zext64 + %val64_unsigned = zext i16 %val16_zext64 to i64 + store volatile i64 %val64_unsigned, i64* @var_64bit +; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #9] + +; truncating store volatile 32-bits to 16-bits + %addr8_trunc32 = getelementptr i8* %addr_8bit, i64 -256 + %addr_trunc32 = bitcast i8* %addr8_trunc32 to i16* + %val32 = load volatile i32* @var_32bit + %val16_trunc32 = trunc i32 %val32 to i16 + store volatile i16 %val16_trunc32, i16* %addr_trunc32 +; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-256] + +; truncating store volatile 64-bits to 16-bits + %addr8_trunc64 = getelementptr i8* %addr_8bit, i64 -1 + %addr_trunc64 = bitcast i8* %addr8_trunc64 to i16* + %val64 = load volatile i64* @var_64bit + %val16_trunc64 = trunc i64 %val64 to i16 + store volatile i16 %val16_trunc64, i16* %addr_trunc64 +; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-1] + + ret void +} + +define void @ldst_32bit() { +; CHECK: ldst_32bit: + + %addr_8bit = load i8** @varptr + +; Straight 32-bit load/store + %addr32_8_noext = getelementptr i8* %addr_8bit, i64 1 + %addr32_noext = bitcast i8* %addr32_8_noext to i32* + %val32_noext = load volatile i32* %addr32_noext + store volatile i32 %val32_noext, i32* %addr32_noext +; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #1] +; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #1] + +; Zero-extension to 64-bits + %addr32_8_zext = getelementptr i8* %addr_8bit, i64 -256 + %addr32_zext = bitcast i8* %addr32_8_zext to i32* + %val32_zext = load volatile i32* %addr32_zext + %val64_unsigned = zext i32 %val32_zext to i64 + store volatile i64 %val64_unsigned, i64* @var_64bit +; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #-256] +; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_64bit] + +; Sign-extension to 64-bits + %addr32_8_sext = getelementptr i8* %addr_8bit, i64 -12 + %addr32_sext = bitcast i8* %addr32_8_sext to i32* + %val32_sext = load volatile i32* %addr32_sext + %val64_signed = sext i32 %val32_sext to i64 + store volatile i64 %val64_signed, i64* @var_64bit +; CHECK: ldursw {{x[0-9]+}}, [{{x[0-9]+}}, #-12] +; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_64bit] + +; Truncation from 64-bits + %addr64_8_trunc = getelementptr i8* %addr_8bit, i64 255 + %addr64_trunc = bitcast i8* %addr64_8_trunc to i64* + %addr32_8_trunc = getelementptr i8* %addr_8bit, i64 -20 + %addr32_trunc = bitcast i8* %addr32_8_trunc to i32* + + %val64_trunc = load volatile i64* %addr64_trunc + %val32_trunc = trunc i64 %val64_trunc to i32 + store volatile i32 %val32_trunc, i32* %addr32_trunc +; CHECK: ldur {{x[0-9]+}}, [{{x[0-9]+}}, #255] +; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #-20] + + ret void +} + +define void @ldst_float() { +; CHECK: ldst_float: + + %addr_8bit = load i8** @varptr + %addrfp_8 = getelementptr i8* %addr_8bit, i64 -5 + %addrfp = bitcast i8* %addrfp_8 to float* + + %valfp = load volatile float* %addrfp +; CHECK: ldur {{s[0-9]+}}, [{{x[0-9]+}}, #-5] + + store volatile float %valfp, float* %addrfp +; CHECK: stur {{s[0-9]+}}, [{{x[0-9]+}}, #-5] + + ret void +} + +define void @ldst_double() { +; CHECK: ldst_double: + + %addr_8bit = load i8** @varptr + %addrfp_8 = getelementptr i8* %addr_8bit, i64 4 + %addrfp = bitcast i8* %addrfp_8 to double* + + %valfp = load volatile double* %addrfp +; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #4] + + store volatile double %valfp, double* %addrfp +; CHECK: stur {{d[0-9]+}}, [{{x[0-9]+}}, #4] + + ret void +} diff --git a/test/CodeGen/AArch64/ldst-unsignedimm.ll b/test/CodeGen/AArch64/ldst-unsignedimm.ll new file mode 100644 index 000000000000..1e7540d9be0a --- /dev/null +++ b/test/CodeGen/AArch64/ldst-unsignedimm.ll @@ -0,0 +1,251 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var_8bit = global i8 0 +@var_16bit = global i16 0 +@var_32bit = global i32 0 +@var_64bit = global i64 0 + +@var_float = global float 0.0 +@var_double = global double 0.0 + +define void @ldst_8bit() { +; CHECK: ldst_8bit: + +; No architectural support for loads to 16-bit or 8-bit since we +; promote i8 during lowering. + +; match a sign-extending load 8-bit -> 32-bit + %val8_sext32 = load volatile i8* @var_8bit + %val32_signed = sext i8 %val8_sext32 to i32 + store volatile i32 %val32_signed, i32* @var_32bit +; CHECK: adrp {{x[0-9]+}}, var_8bit +; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] + +; match a zero-extending load volatile 8-bit -> 32-bit + %val8_zext32 = load volatile i8* @var_8bit + %val32_unsigned = zext i8 %val8_zext32 to i32 + store volatile i32 %val32_unsigned, i32* @var_32bit +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] + +; match an any-extending load volatile 8-bit -> 32-bit + %val8_anyext = load volatile i8* @var_8bit + %newval8 = add i8 %val8_anyext, 1 + store volatile i8 %newval8, i8* @var_8bit +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] + +; match a sign-extending load volatile 8-bit -> 64-bit + %val8_sext64 = load volatile i8* @var_8bit + %val64_signed = sext i8 %val8_sext64 to i64 + store volatile i64 %val64_signed, i64* @var_64bit +; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] + +; match a zero-extending load volatile 8-bit -> 64-bit. +; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits +; of x0 so it's identical to load volatileing to 32-bits. + %val8_zext64 = load volatile i8* @var_8bit + %val64_unsigned = zext i8 %val8_zext64 to i64 + store volatile i64 %val64_unsigned, i64* @var_64bit +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] + +; truncating store volatile 32-bits to 8-bits + %val32 = load volatile i32* @var_32bit + %val8_trunc32 = trunc i32 %val32 to i8 + store volatile i8 %val8_trunc32, i8* @var_8bit +; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] + +; truncating store volatile 64-bits to 8-bits + %val64 = load volatile i64* @var_64bit + %val8_trunc64 = trunc i64 %val64 to i8 + store volatile i8 %val8_trunc64, i8* @var_8bit +; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] + + ret void +} + +define void @ldst_16bit() { +; CHECK: ldst_16bit: + +; No architectural support for load volatiles to 16-bit promote i16 during +; lowering. + +; match a sign-extending load volatile 16-bit -> 32-bit + %val16_sext32 = load volatile i16* @var_16bit + %val32_signed = sext i16 %val16_sext32 to i32 + store volatile i32 %val32_signed, i32* @var_32bit +; CHECK: adrp {{x[0-9]+}}, var_16bit +; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] + +; match a zero-extending load volatile 16-bit -> 32-bit + %val16_zext32 = load volatile i16* @var_16bit + %val32_unsigned = zext i16 %val16_zext32 to i32 + store volatile i32 %val32_unsigned, i32* @var_32bit +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] + +; match an any-extending load volatile 16-bit -> 32-bit + %val16_anyext = load volatile i16* @var_16bit + %newval16 = add i16 %val16_anyext, 1 + store volatile i16 %newval16, i16* @var_16bit +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] + +; match a sign-extending load volatile 16-bit -> 64-bit + %val16_sext64 = load volatile i16* @var_16bit + %val64_signed = sext i16 %val16_sext64 to i64 + store volatile i64 %val64_signed, i64* @var_64bit +; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] + +; match a zero-extending load volatile 16-bit -> 64-bit. +; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits +; of x0 so it's identical to load volatileing to 32-bits. + %val16_zext64 = load volatile i16* @var_16bit + %val64_unsigned = zext i16 %val16_zext64 to i64 + store volatile i64 %val64_unsigned, i64* @var_64bit +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] + +; truncating store volatile 32-bits to 16-bits + %val32 = load volatile i32* @var_32bit + %val16_trunc32 = trunc i32 %val32 to i16 + store volatile i16 %val16_trunc32, i16* @var_16bit +; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] + +; truncating store volatile 64-bits to 16-bits + %val64 = load volatile i64* @var_64bit + %val16_trunc64 = trunc i64 %val64 to i16 + store volatile i16 %val16_trunc64, i16* @var_16bit +; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] + + ret void +} + +define void @ldst_32bit() { +; CHECK: ldst_32bit: + +; Straight 32-bit load/store + %val32_noext = load volatile i32* @var_32bit + store volatile i32 %val32_noext, i32* @var_32bit +; CHECK: adrp {{x[0-9]+}}, var_32bit +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_32bit] +; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_32bit] + +; Zero-extension to 64-bits + %val32_zext = load volatile i32* @var_32bit + %val64_unsigned = zext i32 %val32_zext to i64 + store volatile i64 %val64_unsigned, i64* @var_64bit +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_32bit] +; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_64bit] + +; Sign-extension to 64-bits + %val32_sext = load volatile i32* @var_32bit + %val64_signed = sext i32 %val32_sext to i64 + store volatile i64 %val64_signed, i64* @var_64bit +; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_32bit] +; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_64bit] + +; Truncation from 64-bits + %val64_trunc = load volatile i64* @var_64bit + %val32_trunc = trunc i64 %val64_trunc to i32 + store volatile i32 %val32_trunc, i32* @var_32bit +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_64bit] +; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_32bit] + + ret void +} + +@arr8 = global i8* null +@arr16 = global i16* null +@arr32 = global i32* null +@arr64 = global i64* null + +; Now check that our selection copes with accesses more complex than a +; single symbol. Permitted offsets should be folded into the loads and +; stores. Since all forms use the same Operand it's only necessary to +; check the various access-sizes involved. + +define void @ldst_complex_offsets() { +; CHECK: ldst_complex_offsets + %arr8_addr = load volatile i8** @arr8 +; CHECK: adrp {{x[0-9]+}}, arr8 +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:arr8] + + %arr8_sub1_addr = getelementptr i8* %arr8_addr, i64 1 + %arr8_sub1 = load volatile i8* %arr8_sub1_addr + store volatile i8 %arr8_sub1, i8* @var_8bit +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #1] + + %arr8_sub4095_addr = getelementptr i8* %arr8_addr, i64 4095 + %arr8_sub4095 = load volatile i8* %arr8_sub4095_addr + store volatile i8 %arr8_sub4095, i8* @var_8bit +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #4095] + + + %arr16_addr = load volatile i16** @arr16 +; CHECK: adrp {{x[0-9]+}}, arr16 +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:arr16] + + %arr16_sub1_addr = getelementptr i16* %arr16_addr, i64 1 + %arr16_sub1 = load volatile i16* %arr16_sub1_addr + store volatile i16 %arr16_sub1, i16* @var_16bit +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #2] + + %arr16_sub4095_addr = getelementptr i16* %arr16_addr, i64 4095 + %arr16_sub4095 = load volatile i16* %arr16_sub4095_addr + store volatile i16 %arr16_sub4095, i16* @var_16bit +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #8190] + + + %arr32_addr = load volatile i32** @arr32 +; CHECK: adrp {{x[0-9]+}}, arr32 +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:arr32] + + %arr32_sub1_addr = getelementptr i32* %arr32_addr, i64 1 + %arr32_sub1 = load volatile i32* %arr32_sub1_addr + store volatile i32 %arr32_sub1, i32* @var_32bit +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #4] + + %arr32_sub4095_addr = getelementptr i32* %arr32_addr, i64 4095 + %arr32_sub4095 = load volatile i32* %arr32_sub4095_addr + store volatile i32 %arr32_sub4095, i32* @var_32bit +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #16380] + + + %arr64_addr = load volatile i64** @arr64 +; CHECK: adrp {{x[0-9]+}}, arr64 +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:arr64] + + %arr64_sub1_addr = getelementptr i64* %arr64_addr, i64 1 + %arr64_sub1 = load volatile i64* %arr64_sub1_addr + store volatile i64 %arr64_sub1, i64* @var_64bit +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8] + + %arr64_sub4095_addr = getelementptr i64* %arr64_addr, i64 4095 + %arr64_sub4095 = load volatile i64* %arr64_sub4095_addr + store volatile i64 %arr64_sub4095, i64* @var_64bit +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #32760] + + ret void +} + +define void @ldst_float() { +; CHECK: ldst_float: + + %valfp = load volatile float* @var_float +; CHECK: adrp {{x[0-9]+}}, var_float +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_float] + + store volatile float %valfp, float* @var_float +; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_float] + + ret void +} + +define void @ldst_double() { +; CHECK: ldst_double: + + %valfp = load volatile double* @var_double +; CHECK: adrp {{x[0-9]+}}, var_double +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_double] + + store volatile double %valfp, double* @var_double +; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_double] + + ret void +} diff --git a/test/CodeGen/AArch64/lit.local.cfg b/test/CodeGen/AArch64/lit.local.cfg new file mode 100644 index 000000000000..c5ce2411ed48 --- /dev/null +++ b/test/CodeGen/AArch64/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +targets = set(config.root.targets_to_build.split()) +if not 'AArch64' in targets: + config.unsupported = True + diff --git a/test/CodeGen/AArch64/literal_pools.ll b/test/CodeGen/AArch64/literal_pools.ll new file mode 100644 index 000000000000..e09084148fdf --- /dev/null +++ b/test/CodeGen/AArch64/literal_pools.ll @@ -0,0 +1,55 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var32 = global i32 0 +@var64 = global i64 0 + +define void @foo() { +; CHECK: foo: + %val32 = load i32* @var32 + %val64 = load i64* @var64 + + %val32_lit32 = and i32 %val32, 123456785 + store volatile i32 %val32_lit32, i32* @var32 +; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] +; CHECK: ldr {{w[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] + + %val64_lit32 = and i64 %val64, 305402420 + store volatile i64 %val64_lit32, i64* @var64 +; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] +; CHECK: ldr {{w[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] + + %val64_lit32signed = and i64 %val64, -12345678 + store volatile i64 %val64_lit32signed, i64* @var64 +; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] +; CHECK: ldrsw {{x[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] + + %val64_lit64 = and i64 %val64, 1234567898765432 + store volatile i64 %val64_lit64, i64* @var64 +; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] +; CHECK: ldr {{x[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] + + ret void +} + +@varfloat = global float 0.0 +@vardouble = global double 0.0 + +define void @floating_lits() { +; CHECK: floating_lits: + + %floatval = load float* @varfloat + %newfloat = fadd float %floatval, 128.0 +; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]] +; CHECK: ldr {{s[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK: fadd + store float %newfloat, float* @varfloat + + %doubleval = load double* @vardouble + %newdouble = fadd double %doubleval, 129.0 +; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]] +; CHECK: ldr {{d[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK: fadd + store double %newdouble, double* @vardouble + + ret void +} diff --git a/test/CodeGen/AArch64/local_vars.ll b/test/CodeGen/AArch64/local_vars.ll new file mode 100644 index 000000000000..5cbf5a37ec54 --- /dev/null +++ b/test/CodeGen/AArch64/local_vars.ll @@ -0,0 +1,57 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -O0 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -O0 -disable-fp-elim | FileCheck -check-prefix CHECK-WITHFP %s + +; Make sure a reasonably sane prologue and epilogue are +; generated. This test is not robust in the face of an frame-handling +; evolving, but still has value for unrelated changes, I +; believe. +; +; In particular, it will fail when ldp/stp are used for frame setup, +; when FP-elim is implemented, and when addressing from FP is +; implemented. + +@var = global i64 0 +@local_addr = global i64* null + +declare void @foo() + +define void @trivial_func() nounwind { +; CHECK: trivial_func: // @trivial_func +; CHECK-NEXT: // BB#0 +; CHECK-NEXT: ret + + ret void +} + +define void @trivial_fp_func() { +; CHECK-WITHFP: trivial_fp_func: + +; CHECK-WITHFP: sub sp, sp, #16 +; CHECK-WITHFP: stp x29, x30, [sp] +; CHECK-WITHFP-NEXT: mov x29, sp + +; Dont't really care, but it would be a Bad Thing if this came after the epilogue. +; CHECK: bl foo + call void @foo() + ret void + +; CHECK-WITHFP: ldp x29, x30, [sp] +; CHECK-WITHFP: add sp, sp, #16 + +; CHECK-WITHFP: ret +} + +define void @stack_local() { + %local_var = alloca i64 +; CHECK: stack_local: +; CHECK: sub sp, sp, #16 + + %val = load i64* @var + store i64 %val, i64* %local_var +; CHECK: str {{x[0-9]+}}, [sp, #{{[0-9]+}}] + + store i64* %local_var, i64** @local_addr +; CHECK: add {{x[0-9]+}}, sp, #{{[0-9]+}} + + ret void +} diff --git a/test/CodeGen/AArch64/logical-imm.ll b/test/CodeGen/AArch64/logical-imm.ll new file mode 100644 index 000000000000..5f3f4da0cdad --- /dev/null +++ b/test/CodeGen/AArch64/logical-imm.ll @@ -0,0 +1,84 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var32 = global i32 0 +@var64 = global i64 0 + +define void @test_and(i32 %in32, i64 %in64) { +; CHECK: test_and: + + %val0 = and i32 %in32, 2863311530 + store volatile i32 %val0, i32* @var32 +; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xaaaaaaaa + + %val1 = and i32 %in32, 4293984240 + store volatile i32 %val1, i32* @var32 +; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xfff0fff0 + + %val2 = and i64 %in64, 9331882296111890817 + store volatile i64 %val2, i64* @var64 +; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0x8181818181818181 + + %val3 = and i64 %in64, 18429855317404942275 + store volatile i64 %val3, i64* @var64 +; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffc3ffc3ffc3ffc3 + + ret void +} + +define void @test_orr(i32 %in32, i64 %in64) { +; CHECK: test_orr: + + %val0 = or i32 %in32, 2863311530 + store volatile i32 %val0, i32* @var32 +; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, #0xaaaaaaaa + + %val1 = or i32 %in32, 4293984240 + store volatile i32 %val1, i32* @var32 +; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, #0xfff0fff0 + + %val2 = or i64 %in64, 9331882296111890817 + store volatile i64 %val2, i64* @var64 +; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, #0x8181818181818181 + + %val3 = or i64 %in64, 18429855317404942275 + store volatile i64 %val3, i64* @var64 +; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, #0xffc3ffc3ffc3ffc3 + + ret void +} + +define void @test_eor(i32 %in32, i64 %in64) { +; CHECK: test_eor: + + %val0 = xor i32 %in32, 2863311530 + store volatile i32 %val0, i32* @var32 +; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, #0xaaaaaaaa + + %val1 = xor i32 %in32, 4293984240 + store volatile i32 %val1, i32* @var32 +; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, #0xfff0fff0 + + %val2 = xor i64 %in64, 9331882296111890817 + store volatile i64 %val2, i64* @var64 +; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, #0x8181818181818181 + + %val3 = xor i64 %in64, 18429855317404942275 + store volatile i64 %val3, i64* @var64 +; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, #0xffc3ffc3ffc3ffc3 + + ret void +} + +define void @test_mov(i32 %in32, i64 %in64) { +; CHECK: test_mov: + %val0 = add i32 %in32, 2863311530 + store i32 %val0, i32* @var32 +; CHECK: orr {{w[0-9]+}}, wzr, #0xaaaaaaaa + + %val1 = add i64 %in64, 11068046444225730969 + store i64 %val1, i64* @var64 +; CHECK: orr {{x[0-9]+}}, xzr, #0x9999999999999999 + + ret void +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/logical_shifted_reg.ll b/test/CodeGen/AArch64/logical_shifted_reg.ll new file mode 100644 index 000000000000..bbbfcc1b9118 --- /dev/null +++ b/test/CodeGen/AArch64/logical_shifted_reg.ll @@ -0,0 +1,224 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -O0 | FileCheck %s + +@var1_32 = global i32 0 +@var2_32 = global i32 0 + +@var1_64 = global i64 0 +@var2_64 = global i64 0 + +define void @logical_32bit() { +; CHECK: logical_32bit: + %val1 = load i32* @var1_32 + %val2 = load i32* @var2_32 + + ; First check basic and/bic/or/orn/eor/eon patterns with no shift + %neg_val2 = xor i32 -1, %val2 + + %and_noshift = and i32 %val1, %val2 +; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %and_noshift, i32* @var1_32 + %bic_noshift = and i32 %neg_val2, %val1 +; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %bic_noshift, i32* @var1_32 + + %or_noshift = or i32 %val1, %val2 +; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %or_noshift, i32* @var1_32 + %orn_noshift = or i32 %neg_val2, %val1 +; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %orn_noshift, i32* @var1_32 + + %xor_noshift = xor i32 %val1, %val2 +; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %xor_noshift, i32* @var1_32 + %xorn_noshift = xor i32 %neg_val2, %val1 +; CHECK: eon {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + store volatile i32 %xorn_noshift, i32* @var1_32 + + ; Check the maximum shift on each + %operand_lsl31 = shl i32 %val2, 31 + %neg_operand_lsl31 = xor i32 -1, %operand_lsl31 + + %and_lsl31 = and i32 %val1, %operand_lsl31 +; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31 + store volatile i32 %and_lsl31, i32* @var1_32 + %bic_lsl31 = and i32 %val1, %neg_operand_lsl31 +; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31 + store volatile i32 %bic_lsl31, i32* @var1_32 + + %or_lsl31 = or i32 %val1, %operand_lsl31 +; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31 + store volatile i32 %or_lsl31, i32* @var1_32 + %orn_lsl31 = or i32 %val1, %neg_operand_lsl31 +; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31 + store volatile i32 %orn_lsl31, i32* @var1_32 + + %xor_lsl31 = xor i32 %val1, %operand_lsl31 +; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31 + store volatile i32 %xor_lsl31, i32* @var1_32 + %xorn_lsl31 = xor i32 %val1, %neg_operand_lsl31 +; CHECK: eon {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31 + store volatile i32 %xorn_lsl31, i32* @var1_32 + + ; Check other shifts on a subset + %operand_asr10 = ashr i32 %val2, 10 + %neg_operand_asr10 = xor i32 -1, %operand_asr10 + + %bic_asr10 = and i32 %val1, %neg_operand_asr10 +; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #10 + store volatile i32 %bic_asr10, i32* @var1_32 + %xor_asr10 = xor i32 %val1, %operand_asr10 +; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #10 + store volatile i32 %xor_asr10, i32* @var1_32 + + %operand_lsr1 = lshr i32 %val2, 1 + %neg_operand_lsr1 = xor i32 -1, %operand_lsr1 + + %orn_lsr1 = or i32 %val1, %neg_operand_lsr1 +; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1 + store volatile i32 %orn_lsr1, i32* @var1_32 + %xor_lsr1 = xor i32 %val1, %operand_lsr1 +; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1 + store volatile i32 %xor_lsr1, i32* @var1_32 + + %operand_ror20_big = shl i32 %val2, 12 + %operand_ror20_small = lshr i32 %val2, 20 + %operand_ror20 = or i32 %operand_ror20_big, %operand_ror20_small + %neg_operand_ror20 = xor i32 -1, %operand_ror20 + + %xorn_ror20 = xor i32 %val1, %neg_operand_ror20 +; CHECK: eon {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, ror #20 + store volatile i32 %xorn_ror20, i32* @var1_32 + %and_ror20 = and i32 %val1, %operand_ror20 +; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, ror #20 + store volatile i32 %and_ror20, i32* @var1_32 + + ret void +} + +define void @logical_64bit() { +; CHECK: logical_64bit: + %val1 = load i64* @var1_64 + %val2 = load i64* @var2_64 + + ; First check basic and/bic/or/orn/eor/eon patterns with no shift + %neg_val2 = xor i64 -1, %val2 + + %and_noshift = and i64 %val1, %val2 +; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %and_noshift, i64* @var1_64 + %bic_noshift = and i64 %neg_val2, %val1 +; CHECK: bic {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %bic_noshift, i64* @var1_64 + + %or_noshift = or i64 %val1, %val2 +; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %or_noshift, i64* @var1_64 + %orn_noshift = or i64 %neg_val2, %val1 +; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %orn_noshift, i64* @var1_64 + + %xor_noshift = xor i64 %val1, %val2 +; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %xor_noshift, i64* @var1_64 + %xorn_noshift = xor i64 %neg_val2, %val1 +; CHECK: eon {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + store volatile i64 %xorn_noshift, i64* @var1_64 + + ; Check the maximum shift on each + %operand_lsl63 = shl i64 %val2, 63 + %neg_operand_lsl63 = xor i64 -1, %operand_lsl63 + + %and_lsl63 = and i64 %val1, %operand_lsl63 +; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63 + store volatile i64 %and_lsl63, i64* @var1_64 + %bic_lsl63 = and i64 %val1, %neg_operand_lsl63 +; CHECK: bic {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63 + store volatile i64 %bic_lsl63, i64* @var1_64 + + %or_lsl63 = or i64 %val1, %operand_lsl63 +; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63 + store volatile i64 %or_lsl63, i64* @var1_64 + %orn_lsl63 = or i64 %val1, %neg_operand_lsl63 +; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63 + store volatile i64 %orn_lsl63, i64* @var1_64 + + %xor_lsl63 = xor i64 %val1, %operand_lsl63 +; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63 + store volatile i64 %xor_lsl63, i64* @var1_64 + %xorn_lsl63 = xor i64 %val1, %neg_operand_lsl63 +; CHECK: eon {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63 + store volatile i64 %xorn_lsl63, i64* @var1_64 + + ; Check other shifts on a subset + %operand_asr10 = ashr i64 %val2, 10 + %neg_operand_asr10 = xor i64 -1, %operand_asr10 + + %bic_asr10 = and i64 %val1, %neg_operand_asr10 +; CHECK: bic {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #10 + store volatile i64 %bic_asr10, i64* @var1_64 + %xor_asr10 = xor i64 %val1, %operand_asr10 +; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #10 + store volatile i64 %xor_asr10, i64* @var1_64 + + %operand_lsr1 = lshr i64 %val2, 1 + %neg_operand_lsr1 = xor i64 -1, %operand_lsr1 + + %orn_lsr1 = or i64 %val1, %neg_operand_lsr1 +; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #1 + store volatile i64 %orn_lsr1, i64* @var1_64 + %xor_lsr1 = xor i64 %val1, %operand_lsr1 +; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #1 + store volatile i64 %xor_lsr1, i64* @var1_64 + + ; Construct a rotate-right from a bunch of other logical + ; operations. DAGCombiner should ensure we the ROTR during + ; selection + %operand_ror20_big = shl i64 %val2, 44 + %operand_ror20_small = lshr i64 %val2, 20 + %operand_ror20 = or i64 %operand_ror20_big, %operand_ror20_small + %neg_operand_ror20 = xor i64 -1, %operand_ror20 + + %xorn_ror20 = xor i64 %val1, %neg_operand_ror20 +; CHECK: eon {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, ror #20 + store volatile i64 %xorn_ror20, i64* @var1_64 + %and_ror20 = and i64 %val1, %operand_ror20 +; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, ror #20 + store volatile i64 %and_ror20, i64* @var1_64 + + ret void +} + +define void @flag_setting() { +; CHECK: flag_setting: + %val1 = load i64* @var1_64 + %val2 = load i64* @var2_64 + +; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}} +; CHECK: b.gt .L + %simple_and = and i64 %val1, %val2 + %tst1 = icmp sgt i64 %simple_and, 0 + br i1 %tst1, label %ret, label %test2 + +test2: +; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}, lsl #63 +; CHECK: b.lt .L + %shifted_op = shl i64 %val2, 63 + %shifted_and = and i64 %val1, %shifted_op + %tst2 = icmp slt i64 %shifted_and, 0 + br i1 %tst2, label %ret, label %test3 + +test3: +; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}, asr #12 +; CHECK: b.gt .L + %asr_op = ashr i64 %val2, 12 + %asr_and = and i64 %asr_op, %val1 + %tst3 = icmp sgt i64 %asr_and, 0 + br i1 %tst3, label %ret, label %other_exit + +other_exit: + store volatile i64 %val1, i64* @var1_64 + ret void +ret: + ret void +} diff --git a/test/CodeGen/AArch64/logical_shifted_reg.s b/test/CodeGen/AArch64/logical_shifted_reg.s new file mode 100644 index 000000000000..89aea580119b --- /dev/null +++ b/test/CodeGen/AArch64/logical_shifted_reg.s @@ -0,0 +1,208 @@ + .file "/home/timnor01/a64-trunk/llvm/test/CodeGen/AArch64/logical_shifted_reg.ll" + .text + .globl logical_32bit + .type logical_32bit,@function +logical_32bit: // @logical_32bit + .cfi_startproc +// BB#0: + adrp x0, var1_32 + ldr w1, [x0, #:lo12:var1_32] + adrp x0, var2_32 + ldr w2, [x0, #:lo12:var2_32] + and w3, w1, w2 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + bic w3, w1, w2 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + orr w3, w1, w2 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + orn w3, w1, w2 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + eor w3, w1, w2 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + eon w3, w2, w1 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + and w3, w1, w2, lsl #31 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + bic w3, w1, w2, lsl #31 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + orr w3, w1, w2, lsl #31 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + orn w3, w1, w2, lsl #31 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + eor w3, w1, w2, lsl #31 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + eon w3, w1, w2, lsl #31 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + bic w3, w1, w2, asr #10 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + eor w3, w1, w2, asr #10 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + orn w3, w1, w2, lsr #1 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + eor w3, w1, w2, lsr #1 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + eon w3, w1, w2, ror #20 + adrp x0, var1_32 + str w3, [x0, #:lo12:var1_32] + and w1, w1, w2, ror #20 + adrp x0, var1_32 + str w1, [x0, #:lo12:var1_32] + ret +.Ltmp0: + .size logical_32bit, .Ltmp0-logical_32bit + .cfi_endproc + + .globl logical_64bit + .type logical_64bit,@function +logical_64bit: // @logical_64bit + .cfi_startproc +// BB#0: + adrp x0, var1_64 + ldr x0, [x0, #:lo12:var1_64] + adrp x1, var2_64 + ldr x1, [x1, #:lo12:var2_64] + and x2, x0, x1 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + bic x2, x0, x1 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + orr x2, x0, x1 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + orn x2, x0, x1 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + eor x2, x0, x1 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + eon x2, x1, x0 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + and x2, x0, x1, lsl #63 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + bic x2, x0, x1, lsl #63 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + orr x2, x0, x1, lsl #63 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + orn x2, x0, x1, lsl #63 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + eor x2, x0, x1, lsl #63 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + eon x2, x0, x1, lsl #63 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + bic x2, x0, x1, asr #10 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + eor x2, x0, x1, asr #10 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + orn x2, x0, x1, lsr #1 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + eor x2, x0, x1, lsr #1 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + eon x2, x0, x1, ror #20 + adrp x3, var1_64 + str x2, [x3, #:lo12:var1_64] + and x0, x0, x1, ror #20 + adrp x1, var1_64 + str x0, [x1, #:lo12:var1_64] + ret +.Ltmp1: + .size logical_64bit, .Ltmp1-logical_64bit + .cfi_endproc + + .globl flag_setting + .type flag_setting,@function +flag_setting: // @flag_setting + .cfi_startproc +// BB#0: + sub sp, sp, #16 + adrp x0, var1_64 + ldr x0, [x0, #:lo12:var1_64] + adrp x1, var2_64 + ldr x1, [x1, #:lo12:var2_64] + tst x0, x1 + str x0, [sp, #8] // 8-byte Folded Spill + str x1, [sp] // 8-byte Folded Spill + b.gt .LBB2_4 + b .LBB2_1 +.LBB2_1: // %test2 + ldr x0, [sp, #8] // 8-byte Folded Reload + ldr x1, [sp] // 8-byte Folded Reload + tst x0, x1, lsl #63 + b.lt .LBB2_4 + b .LBB2_2 +.LBB2_2: // %test3 + ldr x0, [sp, #8] // 8-byte Folded Reload + ldr x1, [sp] // 8-byte Folded Reload + tst x0, x1, asr #12 + b.gt .LBB2_4 + b .LBB2_3 +.LBB2_3: // %other_exit + adrp x0, var1_64 + ldr x1, [sp, #8] // 8-byte Folded Reload + str x1, [x0, #:lo12:var1_64] + add sp, sp, #16 + ret +.LBB2_4: // %ret + add sp, sp, #16 + ret +.Ltmp2: + .size flag_setting, .Ltmp2-flag_setting + .cfi_endproc + + .type var1_32,@object // @var1_32 + .bss + .globl var1_32 + .align 2 +var1_32: + .word 0 // 0x0 + .size var1_32, 4 + + .type var2_32,@object // @var2_32 + .globl var2_32 + .align 2 +var2_32: + .word 0 // 0x0 + .size var2_32, 4 + + .type var1_64,@object // @var1_64 + .globl var1_64 + .align 3 +var1_64: + .xword 0 // 0x0 + .size var1_64, 8 + + .type var2_64,@object // @var2_64 + .globl var2_64 + .align 3 +var2_64: + .xword 0 // 0x0 + .size var2_64, 8 + + diff --git a/test/CodeGen/AArch64/movw-consts.ll b/test/CodeGen/AArch64/movw-consts.ll new file mode 100644 index 000000000000..b8a5fb932202 --- /dev/null +++ b/test/CodeGen/AArch64/movw-consts.ll @@ -0,0 +1,124 @@ +; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +define i64 @test0() { +; CHECK: test0: +; Not produced by move wide instructions, but good to make sure we can return 0 anyway: +; CHECK: mov x0, xzr + ret i64 0 +} + +define i64 @test1() { +; CHECK: test1: +; CHECK: movz x0, #1 + ret i64 1 +} + +define i64 @test2() { +; CHECK: test2: +; CHECK: movz x0, #65535 + ret i64 65535 +} + +define i64 @test3() { +; CHECK: test3: +; CHECK: movz x0, #1, lsl #16 + ret i64 65536 +} + +define i64 @test4() { +; CHECK: test4: +; CHECK: movz x0, #65535, lsl #16 + ret i64 4294901760 +} + +define i64 @test5() { +; CHECK: test5: +; CHECK: movz x0, #1, lsl #32 + ret i64 4294967296 +} + +define i64 @test6() { +; CHECK: test6: +; CHECK: movz x0, #65535, lsl #32 + ret i64 281470681743360 +} + +define i64 @test7() { +; CHECK: test7: +; CHECK: movz x0, #1, lsl #48 + ret i64 281474976710656 +} + +; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one +; couldn't. Useful even for i64 +define i64 @test8() { +; CHECK: test8: +; CHECK: movn w0, #60875 + ret i64 4294906420 +} + +define i64 @test9() { +; CHECK: test9: +; CHECK: movn x0, #0 + ret i64 -1 +} + +define i64 @test10() { +; CHECK: test10: +; CHECK: movn x0, #60875, lsl #16 + ret i64 18446744069720047615 +} + +; For reasonably legitimate reasons returning an i32 results in the +; selection of an i64 constant, so we need a different idiom to test that selection +@var32 = global i32 0 + +define void @test11() { +; CHECK: test11: +; CHECK: mov {{w[0-9]+}}, wzr + store i32 0, i32* @var32 + ret void +} + +define void @test12() { +; CHECK: test12: +; CHECK: movz {{w[0-9]+}}, #1 + store i32 1, i32* @var32 + ret void +} + +define void @test13() { +; CHECK: test13: +; CHECK: movz {{w[0-9]+}}, #65535 + store i32 65535, i32* @var32 + ret void +} + +define void @test14() { +; CHECK: test14: +; CHECK: movz {{w[0-9]+}}, #1, lsl #16 + store i32 65536, i32* @var32 + ret void +} + +define void @test15() { +; CHECK: test15: +; CHECK: movz {{w[0-9]+}}, #65535, lsl #16 + store i32 4294901760, i32* @var32 + ret void +} + +define void @test16() { +; CHECK: test16: +; CHECK: movn {{w[0-9]+}}, #0 + store i32 -1, i32* @var32 + ret void +} + +define i64 @test17() { +; CHECK: test17: + + ; Mustn't MOVN w0 here. +; CHECK: movn x0, #2 + ret i64 -3 +} diff --git a/test/CodeGen/AArch64/pic-eh-stubs.ll b/test/CodeGen/AArch64/pic-eh-stubs.ll new file mode 100644 index 000000000000..77bf691cbcbd --- /dev/null +++ b/test/CodeGen/AArch64/pic-eh-stubs.ll @@ -0,0 +1,60 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s + +; Make sure exception-handling PIC code can be linked correctly. An alternative +; to the sequence described below would have .gcc_except_table itself writable +; and not use the indirection, but this isn't what LLVM does right now. + + ; There should be a read-only .gcc_except_table section... +; CHECK: .section .gcc_except_table,"a" + + ; ... referring indirectly to stubs for its typeinfo ... +; CHECK: // @TType Encoding = indirect pcrel sdata8 + ; ... one of which is "int"'s typeinfo +; CHECK: .Ltmp9: +; CHECK-NEXT: .xword .L_ZTIi.DW.stub-.Ltmp9 + + ; .. and which is properly defined (in a writable section for the dynamic loader) later. +; CHECK: .section .data.rel,"aw" +; CHECK: .L_ZTIi.DW.stub: +; CHECK-NEXT: .xword _ZTIi + +@_ZTIi = external constant i8* + +define i32 @_Z3barv() { +entry: + invoke void @_Z3foov() + to label %return unwind label %lpad + +lpad: ; preds = %entry + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* bitcast (i8** @_ZTIi to i8*) + %1 = extractvalue { i8*, i32 } %0, 1 + %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) nounwind + %matches = icmp eq i32 %1, %2 + br i1 %matches, label %catch, label %eh.resume + +catch: ; preds = %lpad + %3 = extractvalue { i8*, i32 } %0, 0 + %4 = tail call i8* @__cxa_begin_catch(i8* %3) nounwind + %5 = bitcast i8* %4 to i32* + %exn.scalar = load i32* %5, align 4 + tail call void @__cxa_end_catch() nounwind + br label %return + +return: ; preds = %entry, %catch + %retval.0 = phi i32 [ %exn.scalar, %catch ], [ 42, %entry ] + ret i32 %retval.0 + +eh.resume: ; preds = %lpad + resume { i8*, i32 } %0 +} + +declare void @_Z3foov() + +declare i32 @__gxx_personality_v0(...) + +declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone + +declare i8* @__cxa_begin_catch(i8*) + +declare void @__cxa_end_catch() \ No newline at end of file diff --git a/test/CodeGen/AArch64/regress-bitcast-formals.ll b/test/CodeGen/AArch64/regress-bitcast-formals.ll new file mode 100644 index 000000000000..28dc9a7e2515 --- /dev/null +++ b/test/CodeGen/AArch64/regress-bitcast-formals.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +; CallingConv.td requires a bitcast for vector arguments. Make sure we're +; actually capable of that (the test was omitted from LowerFormalArguments). + +define void @test_bitcast_lower(<2 x i32> %a) { +; CHECK: test_bitcast_lower: + + ret void +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/regress-f128csel-flags.ll b/test/CodeGen/AArch64/regress-f128csel-flags.ll new file mode 100644 index 000000000000..b35185ccd6f3 --- /dev/null +++ b/test/CodeGen/AArch64/regress-f128csel-flags.ll @@ -0,0 +1,27 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +; We used to not mark NZCV as being used in the continuation basic-block +; when lowering a 128-bit "select" to branches. This meant a subsequent use +; of the same flags gave an internal fault here. + +declare void @foo(fp128) + +define double @test_f128csel_flags(i32 %lhs, fp128 %a, fp128 %b) nounwind { +; CHECK: test_f128csel_flags + + %tst = icmp ne i32 %lhs, 42 + %val = select i1 %tst, fp128 %a, fp128 %b +; CHECK: cmp w0, #42 +; CHECK: b.eq .LBB0 + + call void @foo(fp128 %val) + %retval = select i1 %tst, double 4.0, double 5.0 + + ; It's also reasonably important that the actual fcsel comes before the + ; function call since bl may corrupt NZCV. We were doing the right thing anyway, + ; but just as well test it while we're here. +; CHECK: fcsel {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, ne +; CHECK: bl foo + + ret double %retval +} diff --git a/test/CodeGen/AArch64/regress-tail-livereg.ll b/test/CodeGen/AArch64/regress-tail-livereg.ll new file mode 100644 index 000000000000..8d5485cae4c8 --- /dev/null +++ b/test/CodeGen/AArch64/regress-tail-livereg.ll @@ -0,0 +1,19 @@ +; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s +@var = global void()* zeroinitializer + +declare void @bar() + +define void @foo() { +; CHECK: foo: + %func = load void()** @var + + ; Calling a function encourages @foo to use a callee-saved register, + ; which makes it a natural choice for the tail call itself. But we don't + ; want that: the final "br xN" has to use a temporary or argument + ; register. + call void @bar() + + tail call void %func() +; CHECK: br {{x([0-79]|1[0-8])}} + ret void +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/regress-tblgen-chains.ll b/test/CodeGen/AArch64/regress-tblgen-chains.ll new file mode 100644 index 000000000000..e54552fd8edf --- /dev/null +++ b/test/CodeGen/AArch64/regress-tblgen-chains.ll @@ -0,0 +1,36 @@ +; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +; When generating DAG selection tables, TableGen used to only flag an +; instruction as needing a chain on its own account if it had a built-in pattern +; which used the chain. This meant that the AArch64 load/stores weren't +; recognised and so both loads from %locvar below were coalesced into a single +; LS8_LDR instruction (same operands other than the non-existent chain) and the +; increment was lost at return. + +; This was obviously a Bad Thing. + +declare void @bar(i8*) + +define i64 @test_chains() { +; CHECK: test_chains: + + %locvar = alloca i8 + + call void @bar(i8* %locvar) +; CHECK: bl bar + + %inc.1 = load i8* %locvar + %inc.2 = zext i8 %inc.1 to i64 + %inc.3 = add i64 %inc.2, 1 + %inc.4 = trunc i64 %inc.3 to i8 + store i8 %inc.4, i8* %locvar +; CHECK: ldrb {{w[0-9]+}}, [sp, [[LOCADDR:#[0-9]+]]] +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #1 +; CHECK: strb {{w[0-9]+}}, [sp, [[LOCADDR]]] +; CHECK: ldrb {{w[0-9]+}}, [sp, [[LOCADDR]]] + + %ret.1 = load i8* %locvar + %ret.2 = zext i8 %ret.1 to i64 + ret i64 %ret.2 +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll new file mode 100644 index 000000000000..980e2ffef901 --- /dev/null +++ b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll @@ -0,0 +1,37 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-fp-elim < %s | FileCheck %s +@var = global i32 0 + +declare void @bar() + +define void @test_w29_reserved() { +; CHECK: test_w29_reserved: +; CHECK: add x29, sp, #{{[0-9]+}} + + %val1 = load volatile i32* @var + %val2 = load volatile i32* @var + %val3 = load volatile i32* @var + %val4 = load volatile i32* @var + %val5 = load volatile i32* @var + %val6 = load volatile i32* @var + %val7 = load volatile i32* @var + %val8 = load volatile i32* @var + %val9 = load volatile i32* @var + +; CHECK-NOT: ldr w29, + + ; Call to prevent fp-elim that occurs regardless in leaf functions. + call void @bar() + + store volatile i32 %val1, i32* @var + store volatile i32 %val2, i32* @var + store volatile i32 %val3, i32* @var + store volatile i32 %val4, i32* @var + store volatile i32 %val5, i32* @var + store volatile i32 %val6, i32* @var + store volatile i32 %val7, i32* @var + store volatile i32 %val8, i32* @var + store volatile i32 %val9, i32* @var + + ret void +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/regress-wzr-allocatable.ll b/test/CodeGen/AArch64/regress-wzr-allocatable.ll new file mode 100644 index 000000000000..764d2bc44f0d --- /dev/null +++ b/test/CodeGen/AArch64/regress-wzr-allocatable.ll @@ -0,0 +1,41 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -O0 + +; When WZR wasn't marked as reserved, this function tried to allocate +; it at O0 and then generated an internal fault (mostly incidentally) +; when it discovered that it was already in use for a multiplication. + +; I'm not really convinced this is a good test since it could easily +; stop testing what it does now with no-one any the wiser. However, I +; can't think of a better way to force the allocator to use WZR +; specifically. + +define void @test() nounwind { +entry: + br label %for.cond + +for.cond: ; preds = %for.body, %entry + br i1 undef, label %for.body, label %for.end + +for.body: ; preds = %for.cond + br label %for.cond + +for.end: ; preds = %for.cond + br label %for.cond6 + +for.cond6: ; preds = %for.body9, %for.end + br i1 undef, label %for.body9, label %while.cond30 + +for.body9: ; preds = %for.cond6 + store i16 0, i16* undef, align 2 + %0 = load i32* undef, align 4 + %1 = load i32* undef, align 4 + %mul15 = mul i32 %0, %1 + %add16 = add i32 %mul15, 32768 + %div = udiv i32 %add16, 65535 + %add17 = add i32 %div, 1 + store i32 %add17, i32* undef, align 4 + br label %for.cond6 + +while.cond30: ; preds = %for.cond6 + ret void +} diff --git a/test/CodeGen/AArch64/setcc-takes-i32.ll b/test/CodeGen/AArch64/setcc-takes-i32.ll new file mode 100644 index 000000000000..d2eb77ab1b54 --- /dev/null +++ b/test/CodeGen/AArch64/setcc-takes-i32.ll @@ -0,0 +1,22 @@ +; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +; Most important point here is that the promotion of the i1 works +; correctly. Previously LLVM thought that i64 was the appropriate SetCC output, +; which meant it proceded in two steps and produced an i64 -> i64 any_ext which +; couldn't be selected and faulted. + +; It was expecting the smallest legal promotion of i1 to be the preferred SetCC +; type, so we'll satisfy it (this actually arguably gives better code anyway, +; with flag-manipulation operations allowed to use W-registers). + +declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) + +define i64 @test_select(i64 %lhs, i64 %rhs) { +; CHECK: test_select: + + %res = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %lhs, i64 %rhs) + %flag = extractvalue {i64, i1} %res, 1 + %retval = select i1 %flag, i64 %lhs, i64 %rhs + ret i64 %retval +; CHECK: ret +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/sibling-call.ll b/test/CodeGen/AArch64/sibling-call.ll new file mode 100644 index 000000000000..a1ec618b03ba --- /dev/null +++ b/test/CodeGen/AArch64/sibling-call.ll @@ -0,0 +1,97 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +declare void @callee_stack0() +declare void @callee_stack8([8 x i32], i64) +declare void @callee_stack16([8 x i32], i64, i64) + +define void @caller_to0_from0() nounwind { +; CHECK: caller_to0_from0: +; CHECK-NEXT: // BB + tail call void @callee_stack0() + ret void +; CHECK-NEXT: b callee_stack0 +} + +define void @caller_to0_from8([8 x i32], i64) nounwind{ +; CHECK: caller_to0_from8: +; CHECK-NEXT: // BB + + tail call void @callee_stack0() + ret void +; CHECK-NEXT: b callee_stack0 +} + +define void @caller_to8_from0() { +; CHECK: caller_to8_from0: + +; Caller isn't going to clean up any extra stack we allocate, so it +; can't be a tail call. + tail call void @callee_stack8([8 x i32] undef, i64 42) + ret void +; CHECK: bl callee_stack8 +} + +define void @caller_to8_from8([8 x i32], i64 %a) { +; CHECK: caller_to8_from8: +; CHECK-NOT: sub sp, sp, + +; This should reuse our stack area for the 42 + tail call void @callee_stack8([8 x i32] undef, i64 42) + ret void +; CHECK: str {{x[0-9]+}}, [sp] +; CHECK-NEXT: b callee_stack8 +} + +define void @caller_to16_from8([8 x i32], i64 %a) { +; CHECK: caller_to16_from8: + +; Shouldn't be a tail call: we can't use SP+8 because our caller might +; have something there. This may sound obvious but implementation does +; some funky aligning. + tail call void @callee_stack16([8 x i32] undef, i64 undef, i64 undef) +; CHECK: bl callee_stack16 + ret void +} + +define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) { +; CHECK: caller_to8_from24: +; CHECK-NOT: sub sp, sp + +; Reuse our area, putting "42" at incoming sp + tail call void @callee_stack8([8 x i32] undef, i64 42) + ret void +; CHECK: str {{x[0-9]+}}, [sp] +; CHECK-NEXT: b callee_stack8 +} + +define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) { +; CHECK: caller_to16_from16: +; CHECK-NOT: sub sp, sp, + +; Here we want to make sure that both loads happen before the stores: +; otherwise either %a or %b will be wrongly clobbered. + tail call void @callee_stack16([8 x i32] undef, i64 %b, i64 %a) + ret void + +; CHECK: ldr x0, +; CHECK: ldr x1, +; CHECK: str x1, +; CHECK: str x0, + +; CHECK-NOT: add sp, sp, +; CHECK: b callee_stack16 +} + +@func = global void(i32)* null + +define void @indirect_tail() { +; CHECK: indirect_tail: +; CHECK-NOT: sub sp, sp + + %fptr = load void(i32)** @func + tail call void %fptr(i32 42) + ret void +; CHECK: movz w0, #42 +; CHECK: ldr [[FPTR:x[1-9]+]], [{{x[0-9]+}}, #:lo12:func] +; CHECK: br [[FPTR]] +} \ No newline at end of file diff --git a/test/CodeGen/AArch64/sincos-expansion.ll b/test/CodeGen/AArch64/sincos-expansion.ll new file mode 100644 index 000000000000..c7a392b78c24 --- /dev/null +++ b/test/CodeGen/AArch64/sincos-expansion.ll @@ -0,0 +1,35 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +define float @test_sincos_f32(float %f) { + %sin = call float @sinf(float %f) readnone + %cos = call float @cosf(float %f) readnone +; CHECK: bl cosf +; CHECK: bl sinf + %val = fadd float %sin, %cos + ret float %val +} + +define double @test_sincos_f64(double %f) { + %sin = call double @sin(double %f) readnone + %cos = call double @cos(double %f) readnone + %val = fadd double %sin, %cos +; CHECK: bl cos +; CHECK: bl sin + ret double %val +} + +define fp128 @test_sincos_f128(fp128 %f) { + %sin = call fp128 @sinl(fp128 %f) readnone + %cos = call fp128 @cosl(fp128 %f) readnone + %val = fadd fp128 %sin, %cos +; CHECK: bl cosl +; CHECK: bl sinl + ret fp128 %val +} + +declare float @sinf(float) readonly +declare double @sin(double) readonly +declare fp128 @sinl(fp128) readonly +declare float @cosf(float) readonly +declare double @cos(double) readonly +declare fp128 @cosl(fp128) readonly \ No newline at end of file diff --git a/test/CodeGen/AArch64/tail-call.ll b/test/CodeGen/AArch64/tail-call.ll new file mode 100644 index 000000000000..f323b151ad1e --- /dev/null +++ b/test/CodeGen/AArch64/tail-call.ll @@ -0,0 +1,94 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -tailcallopt | FileCheck %s + +declare fastcc void @callee_stack0() +declare fastcc void @callee_stack8([8 x i32], i64) +declare fastcc void @callee_stack16([8 x i32], i64, i64) + +define fastcc void @caller_to0_from0() nounwind { +; CHECK: caller_to0_from0: +; CHECK-NEXT: // BB + tail call fastcc void @callee_stack0() + ret void +; CHECK-NEXT: b callee_stack0 +} + +define fastcc void @caller_to0_from8([8 x i32], i64) { +; CHECK: caller_to0_from8: + + tail call fastcc void @callee_stack0() + ret void +; CHECK: add sp, sp, #16 +; CHECK-NEXT: b callee_stack0 +} + +define fastcc void @caller_to8_from0() { +; CHECK: caller_to8_from0: +; CHECK: sub sp, sp, #32 + +; Key point is that the "42" should go #16 below incoming stack +; pointer (we didn't have arg space to reuse). + tail call fastcc void @callee_stack8([8 x i32] undef, i64 42) + ret void +; CHECK: str {{x[0-9]+}}, [sp, #16] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: b callee_stack8 +} + +define fastcc void @caller_to8_from8([8 x i32], i64 %a) { +; CHECK: caller_to8_from8: +; CHECK: sub sp, sp, #16 + +; Key point is that the "%a" should go where at SP on entry. + tail call fastcc void @callee_stack8([8 x i32] undef, i64 42) + ret void +; CHECK: str {{x[0-9]+}}, [sp, #16] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: b callee_stack8 +} + +define fastcc void @caller_to16_from8([8 x i32], i64 %a) { +; CHECK: caller_to16_from8: +; CHECK: sub sp, sp, #16 + +; Important point is that the call reuses the "dead" argument space +; above %a on the stack. If it tries to go below incoming-SP then the +; callee will not deallocate the space, even in fastcc. + tail call fastcc void @callee_stack16([8 x i32] undef, i64 42, i64 2) +; CHECK: str {{x[0-9]+}}, [sp, #24] +; CHECK: str {{x[0-9]+}}, [sp, #16] +; CHECK: add sp, sp, #16 +; CHECK: b callee_stack16 + ret void +} + + +define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) { +; CHECK: caller_to8_from24: +; CHECK: sub sp, sp, #16 + +; Key point is that the "%a" should go where at #16 above SP on entry. + tail call fastcc void @callee_stack8([8 x i32] undef, i64 42) + ret void +; CHECK: str {{x[0-9]+}}, [sp, #32] +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: b callee_stack8 +} + + +define fastcc void @caller_to16_from16([8 x i32], i64 %a, i64 %b) { +; CHECK: caller_to16_from16: +; CHECK: sub sp, sp, #16 + +; Here we want to make sure that both loads happen before the stores: +; otherwise either %a or %b will be wrongly clobbered. + tail call fastcc void @callee_stack16([8 x i32] undef, i64 %b, i64 %a) + ret void + +; CHECK: ldr x0, +; CHECK: ldr x1, +; CHECK: str x1, +; CHECK: str x0, + +; CHECK: add sp, sp, #16 +; CHECK: b callee_stack16 +} diff --git a/test/CodeGen/AArch64/tls-dynamic-together.ll b/test/CodeGen/AArch64/tls-dynamic-together.ll new file mode 100644 index 000000000000..bad2298c8a65 --- /dev/null +++ b/test/CodeGen/AArch64/tls-dynamic-together.ll @@ -0,0 +1,18 @@ +; RUN: llc -O0 -mtriple=aarch64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s + +; If the .tlsdesccall and blr parts are emitted completely separately (even with +; glue) then LLVM will separate them quite happily (with a spill at O0, hence +; the option). This is definitely wrong, so we make sure they are emitted +; together. + +@general_dynamic_var = external thread_local global i32 + +define i32 @test_generaldynamic() { +; CHECK: test_generaldynamic: + + %val = load i32* @general_dynamic_var + ret i32 %val + +; CHECK: .tlsdesccall general_dynamic_var +; CHECK-NEXT: blr {{x[0-9]+}} +} diff --git a/test/CodeGen/AArch64/tls-dynamics.ll b/test/CodeGen/AArch64/tls-dynamics.ll new file mode 100644 index 000000000000..cdfd11783c23 --- /dev/null +++ b/test/CodeGen/AArch64/tls-dynamics.ll @@ -0,0 +1,121 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s + +@general_dynamic_var = external thread_local global i32 + +define i32 @test_generaldynamic() { +; CHECK: test_generaldynamic: + + %val = load i32* @general_dynamic_var + ret i32 %val + +; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var +; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var +; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var] +; CHECK: .tlsdesccall general_dynamic_var +; CHECK-NEXT: blr [[CALLEE]] + +; CHECK: mrs x[[TP:[0-9]+]], tpidr_el0 +; CHECK: ldr w0, [x[[TP]], x0] + +; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_CALL + +} + +define i32* @test_generaldynamic_addr() { +; CHECK: test_generaldynamic_addr: + + ret i32* @general_dynamic_var + +; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var +; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var +; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var] +; CHECK: .tlsdesccall general_dynamic_var +; CHECK-NEXT: blr [[CALLEE]] + +; CHECK: mrs [[TP:x[0-9]+]], tpidr_el0 +; CHECK: add x0, [[TP]], x0 + +; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_CALL + +} + +@local_dynamic_var = external thread_local(localdynamic) global i32 + +define i32 @test_localdynamic() { +; CHECK: test_localdynamic: + + %val = load i32* @local_dynamic_var + ret i32 %val + +; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ +; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK: .tlsdesccall _TLS_MODULE_BASE_ +; CHECK-NEXT: blr [[CALLEE]] + +; CHECK: movz [[DTP_OFFSET:x[0-9]+]], #:dtprel_g1:local_dynamic_var +; CHECK: movk [[DTP_OFFSET]], #:dtprel_g0_nc:local_dynamic_var + +; CHECK: ldr w0, [x0, [[DTP_OFFSET]]] + +; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_CALL + +} + +define i32* @test_localdynamic_addr() { +; CHECK: test_localdynamic_addr: + + ret i32* @local_dynamic_var + +; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ +; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK: .tlsdesccall _TLS_MODULE_BASE_ +; CHECK-NEXT: blr [[CALLEE]] + +; CHECK: movz [[DTP_OFFSET:x[0-9]+]], #:dtprel_g1:local_dynamic_var +; CHECK: movk [[DTP_OFFSET]], #:dtprel_g0_nc:local_dynamic_var + +; CHECK: add x0, x0, [[DTP_OFFSET]] + +; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_CALL + +} + +; The entire point of the local-dynamic access model is to have a single call to +; the expensive resolver. Make sure we achieve that goal. + +@local_dynamic_var2 = external thread_local(localdynamic) global i32 + +define i32 @test_localdynamic_deduplicate() { +; CHECK: test_localdynamic_deduplicate: + + %val = load i32* @local_dynamic_var + %val2 = load i32* @local_dynamic_var2 + + %sum = add i32 %val, %val2 + ret i32 %sum + +; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ +; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK: .tlsdesccall _TLS_MODULE_BASE_ +; CHECK-NEXT: blr [[CALLEE]] + +; CHECK-NOT: _TLS_MODULE_BASE_ + +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/tls-execs.ll b/test/CodeGen/AArch64/tls-execs.ll new file mode 100644 index 000000000000..a66588422793 --- /dev/null +++ b/test/CodeGen/AArch64/tls-execs.ll @@ -0,0 +1,63 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s + +@initial_exec_var = external thread_local(initialexec) global i32 + +define i32 @test_initial_exec() { +; CHECK: test_initial_exec: + %val = load i32* @initial_exec_var + +; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var +; CHECK: ldr x[[TP_OFFSET:[0-9]+]], [x[[GOTADDR]], #:gottprel_lo12:initial_exec_var] +; CHECK: mrs x[[TP:[0-9]+]], tpidr_el0 +; CHECK: ldr w0, [x[[TP]], x[[TP_OFFSET]]] + +; CHECK-RELOC: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 +; CHECK-RELOC: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC + + ret i32 %val +} + +define i32* @test_initial_exec_addr() { +; CHECK: test_initial_exec_addr: + ret i32* @initial_exec_var + +; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var +; CHECK: ldr [[TP_OFFSET:x[0-9]+]], [x[[GOTADDR]], #:gottprel_lo12:initial_exec_var] +; CHECK: mrs [[TP:x[0-9]+]], tpidr_el0 +; CHECK: add x0, [[TP]], [[TP_OFFSET]] + +; CHECK-RELOC: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 +; CHECK-RELOC: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC + +} + +@local_exec_var = thread_local(initialexec) global i32 0 + +define i32 @test_local_exec() { +; CHECK: test_local_exec: + %val = load i32* @local_exec_var + +; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var +; CHECK: movk [[TP_OFFSET]], #:tprel_g0_nc:local_exec_var +; CHECK: mrs x[[TP:[0-9]+]], tpidr_el0 +; CHECK: ldr w0, [x[[TP]], [[TP_OFFSET]]] + +; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G1 +; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC + + ret i32 %val +} + +define i32* @test_local_exec_addr() { +; CHECK: test_local_exec_addr: + ret i32* @local_exec_var + +; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var +; CHECK: movk [[TP_OFFSET]], #:tprel_g0_nc:local_exec_var +; CHECK: mrs [[TP:x[0-9]+]], tpidr_el0 +; CHECK: add x0, [[TP]], [[TP_OFFSET]] + +; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G1 +; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC +} diff --git a/test/CodeGen/AArch64/tst-br.ll b/test/CodeGen/AArch64/tst-br.ll new file mode 100644 index 000000000000..65c1fda49e2d --- /dev/null +++ b/test/CodeGen/AArch64/tst-br.ll @@ -0,0 +1,48 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +; We've got the usual issues with LLVM reordering blocks here. The +; tests are correct for the current order, but who knows when that +; will change. Beware! +@var32 = global i32 0 +@var64 = global i64 0 + +define i32 @test_tbz() { +; CHECK: test_tbz: + + %val = load i32* @var32 + %val64 = load i64* @var64 + + %tbit0 = and i32 %val, 32768 + %tst0 = icmp ne i32 %tbit0, 0 + br i1 %tst0, label %test1, label %end1 +; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.LBB0_[0-9]+]] + +test1: + %tbit1 = and i32 %val, 4096 + %tst1 = icmp ne i32 %tbit1, 0 + br i1 %tst1, label %test2, label %end1 +; CHECK: tbz {{w[0-9]+}}, #12, [[LBL_end1]] + +test2: + %tbit2 = and i64 %val64, 32768 + %tst2 = icmp ne i64 %tbit2, 0 + br i1 %tst2, label %test3, label %end1 +; CHECK: tbz {{x[0-9]+}}, #15, [[LBL_end1]] + +test3: + %tbit3 = and i64 %val64, 4096 + %tst3 = icmp ne i64 %tbit3, 0 + br i1 %tst3, label %end2, label %end1 +; CHECK: tbz {{x[0-9]+}}, #12, [[LBL_end1]] + +end2: +; CHECK: movz x0, #1 +; CHECK-NEXT: ret + ret i32 1 + +end1: +; CHECK: [[LBL_end1]]: +; CHECK-NEXT: mov x0, xzr +; CHECK-NEXT: ret + ret i32 0 +} diff --git a/test/CodeGen/AArch64/variadic.ll b/test/CodeGen/AArch64/variadic.ll new file mode 100644 index 000000000000..c5d319eb112b --- /dev/null +++ b/test/CodeGen/AArch64/variadic.ll @@ -0,0 +1,144 @@ +; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +%va_list = type {i8*, i8*, i8*, i32, i32} + +@var = global %va_list zeroinitializer + +declare void @llvm.va_start(i8*) + +define void @test_simple(i32 %n, ...) { +; CHECK: test_simple: +; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] +; CHECK: mov x[[FPRBASE:[0-9]+]], sp +; CHECK: str q7, [x[[FPRBASE]], #112] +; CHECK: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]] +; CHECK: str x7, [x[[GPRBASE]], #48] + +; Omit the middle ones + +; CHECK: str q0, [sp] +; CHECK: str x1, [sp, #[[GPRFROMSP]]] + + %addr = bitcast %va_list* @var to i8* + call void @llvm.va_start(i8* %addr) +; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var +; CHECK: movn [[VR_OFFS:w[0-9]+]], #127 +; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] +; CHECK: movn [[GR_OFFS:w[0-9]+]], #55 +; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] +; CHECK: add [[VR_TOP:x[0-9]+]], x[[FPRBASE]], #128 +; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] +; CHECK: add [[GR_TOP:x[0-9]+]], x[[GPRBASE]], #56 +; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8] +; CHECK: add [[STACK:x[0-9]+]], sp, #[[STACKSIZE]] +; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var] + + ret void +} + +define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { +; CHECK: test_fewargs: +; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] +; CHECK: mov x[[FPRBASE:[0-9]+]], sp +; CHECK: str q7, [x[[FPRBASE]], #96] +; CHECK: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]] +; CHECK: str x7, [x[[GPRBASE]], #32] + +; Omit the middle ones + +; CHECK: str q1, [sp] +; CHECK: str x3, [sp, #[[GPRFROMSP]]] + + %addr = bitcast %va_list* @var to i8* + call void @llvm.va_start(i8* %addr) +; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var +; CHECK: movn [[VR_OFFS:w[0-9]+]], #111 +; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] +; CHECK: movn [[GR_OFFS:w[0-9]+]], #39 +; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] +; CHECK: add [[VR_TOP:x[0-9]+]], x[[FPRBASE]], #112 +; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] +; CHECK: add [[GR_TOP:x[0-9]+]], x[[GPRBASE]], #40 +; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8] +; CHECK: add [[STACK:x[0-9]+]], sp, #[[STACKSIZE]] +; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var] + + ret void +} + +define void @test_nospare([8 x i64], [8 x float], ...) { +; CHECK: test_nospare: + + %addr = bitcast %va_list* @var to i8* + call void @llvm.va_start(i8* %addr) +; CHECK-NOT: sub sp, sp +; CHECK: mov [[STACK:x[0-9]+]], sp +; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var] + + ret void +} + +; If there are non-variadic arguments on the stack (here two i64s) then the +; __stack field should point just past them. +define void @test_offsetstack([10 x i64], [3 x float], ...) { +; CHECK: test_offsetstack: +; CHECK: sub sp, sp, #80 +; CHECK: mov x[[FPRBASE:[0-9]+]], sp +; CHECK: str q7, [x[[FPRBASE]], #64] + +; CHECK-NOT: str x{{[0-9]+}}, +; Omit the middle ones + +; CHECK: str q3, [sp] + + %addr = bitcast %va_list* @var to i8* + call void @llvm.va_start(i8* %addr) +; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var +; CHECK: movn [[VR_OFFS:w[0-9]+]], #79 +; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] +; CHECK: str wzr, [x[[VA_LIST]], #24] +; CHECK: add [[VR_TOP:x[0-9]+]], x[[FPRBASE]], #80 +; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] +; CHECK: add [[STACK:x[0-9]+]], sp, #96 +; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var] + + ret void +} + +declare void @llvm.va_end(i8*) + +define void @test_va_end() nounwind { +; CHECK: test_va_end: +; CHECK-NEXT: BB#0 + + %addr = bitcast %va_list* @var to i8* + call void @llvm.va_end(i8* %addr) + + ret void +; CHECK-NEXT: ret +} + +declare void @llvm.va_copy(i8* %dest, i8* %src) + +@second_list = global %va_list zeroinitializer + +define void @test_va_copy() { +; CHECK: test_va_copy: + %srcaddr = bitcast %va_list* @var to i8* + %dstaddr = bitcast %va_list* @second_list to i8* + call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr) + +; Check beginning and end again: + +; CHECK: ldr [[BLOCK:x[0-9]+]], [{{x[0-9]+}}, #:lo12:var] +; CHECK: str [[BLOCK]], [{{x[0-9]+}}, #:lo12:second_list] + +; CHECK: add x[[DEST_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:second_list +; CHECK: add x[[SRC_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var + +; CHECK: ldr [[BLOCK:x[0-9]+]], [x[[SRC_LIST]], #24] +; CHECK: str [[BLOCK]], [x[[DEST_LIST]], #24] + + ret void +; CHECK: ret +} diff --git a/test/CodeGen/AArch64/zero-reg.ll b/test/CodeGen/AArch64/zero-reg.ll new file mode 100644 index 000000000000..fef0437ae7f3 --- /dev/null +++ b/test/CodeGen/AArch64/zero-reg.ll @@ -0,0 +1,31 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +@var32 = global i32 0 +@var64 = global i64 0 + +define void @test_zr() { +; CHECK: test_zr: + + store i32 0, i32* @var32 +; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32] + store i64 0, i64* @var64 +; CHECK: str xzr, [{{x[0-9]+}}, #:lo12:var64] + + ret void +; CHECK: ret +} + +define void @test_sp(i32 %val) { +; CHECK: test_sp: + +; Important correctness point here is that LLVM doesn't try to use xzr +; as an addressing register: "str w0, [xzr]" is not a valid A64 +; instruction (0b11111 in the Rn field would mean "sp"). + %addr = getelementptr i32* null, i64 0 + store i32 %val, i32* %addr +; CHECK: mov x[[NULL:[0-9]+]], xzr +; CHECK: str {{w[0-9]+}}, [x[[NULL]]] + + ret void +; CHECK: ret +} \ No newline at end of file diff --git a/test/CodeGen/ARM/2007-03-13-InstrSched.ll b/test/CodeGen/ARM/2007-03-13-InstrSched.ll index a63cdd46e2d8..4783f3707690 100644 --- a/test/CodeGen/ARM/2007-03-13-InstrSched.ll +++ b/test/CodeGen/ARM/2007-03-13-InstrSched.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \ ; RUN: -mattr=+v6 | grep r9 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \ diff --git a/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll deleted file mode 100644 index 642268992062..000000000000 --- a/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: llc -O0 -march=arm -asm-verbose < %s | FileCheck %s -; Check that DEBUG_VALUE comments come through on a variety of targets. - -define i32 @main() nounwind ssp { -entry: -; CHECK: DEBUG_VALUE - call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 - ret i32 0, !dbg !10 -} - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone - -!llvm.dbg.sp = !{!0} - -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 0} -!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!9 = metadata !{i32 3, i32 11, metadata !8, null} -!10 = metadata !{i32 4, i32 2, metadata !8, null} - diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index 6aeaa26cebd1..91a9903f3852 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -74,51 +74,54 @@ return: ; preds = %entry declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -!llvm.dbg.sp = !{!0, !9, !16, !17, !20} +!llvm.dbg.cu = !{!3} -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524307, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] -!2 = metadata !{i32 524329, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 524305, i32 0, i32 4, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786451, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] +!2 = metadata !{i32 786473, metadata !48} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !47, metadata !47, metadata !46, metadata !47, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} -!5 = metadata !{i32 524301, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] -!6 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] -!7 = metadata !{i32 524301, metadata !1, metadata !"Kind", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] -!8 = metadata !{i32 524324, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 786445, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!6 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 786445, metadata !1, metadata !"Kind", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] +!8 = metadata !{i32 786468, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 786478, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] !11 = metadata !{null, metadata !12, metadata !13} -!12 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] -!13 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] +!13 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ] !15 = metadata !{null, metadata !12} -!16 = metadata !{i32 524334, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev} ; [ DW_TAG_subprogram ] -!17 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal} ; [ DW_TAG_subprogram ] -!18 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ] +!16 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev} ; [ DW_TAG_subprogram ] +!17 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal} ; [ DW_TAG_subprogram ] +!18 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ] !19 = metadata !{metadata !13, metadata !13, metadata !1} -!20 = metadata !{i32 524334, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!21 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ] +!20 = metadata !{i32 786478, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!21 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ] !22 = metadata !{metadata !13} -!23 = metadata !{i32 524545, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13} ; [ DW_TAG_arg_variable ] +!23 = metadata !{i32 786689, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13, i32 0, i32 0} ; [ DW_TAG_arg_variable ] !24 = metadata !{i32 16, i32 0, metadata !17, null} -!25 = metadata !{i32 524545, metadata !17, metadata !"location", metadata !2, i32 16, metadata !26} ; [ DW_TAG_arg_variable ] -!26 = metadata !{i32 524304, metadata !2, metadata !"SVal", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] +!25 = metadata !{i32 786689, metadata !17, metadata !"location", metadata !2, i32 16, metadata !26, i32 0, i32 0} ; [ DW_TAG_arg_variable ] +!26 = metadata !{i32 786448, metadata !2, metadata !"SVal", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] !27 = metadata !{i32 17, i32 0, metadata !28, null} -!28 = metadata !{i32 524299, metadata !17, i32 16, i32 0, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 786443, metadata !2, metadata !17, i32 16, i32 0, i32 2} ; [ DW_TAG_lexical_block ] !29 = metadata !{i32 18, i32 0, metadata !28, null} !30 = metadata !{i32 20, i32 0, metadata !28, null} -!31 = metadata !{i32 524545, metadata !16, metadata !"this", metadata !2, i32 11, metadata !32} ; [ DW_TAG_arg_variable ] -!32 = metadata !{i32 524326, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !33} ; [ DW_TAG_const_type ] -!33 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ] +!31 = metadata !{i32 786689, metadata !16, metadata !"this", metadata !2, i32 11, metadata !32, i32 0, i32 0} ; [ DW_TAG_arg_variable ] +!32 = metadata !{i32 786470, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !33} ; [ DW_TAG_const_type ] +!33 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ] !34 = metadata !{i32 11, i32 0, metadata !16, null} !35 = metadata !{i32 11, i32 0, metadata !36, null} -!36 = metadata !{i32 524299, metadata !37, i32 11, i32 0, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] -!37 = metadata !{i32 524299, metadata !16, i32 11, i32 0, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] -!38 = metadata !{i32 524544, metadata !39, metadata !"v", metadata !2, i32 24, metadata !1} ; [ DW_TAG_auto_variable ] -!39 = metadata !{i32 524299, metadata !40, i32 23, i32 0, metadata !2, i32 4} ; [ DW_TAG_lexical_block ] -!40 = metadata !{i32 524299, metadata !20, i32 23, i32 0, metadata !2, i32 3} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 786443, metadata !2, metadata !37, i32 11, i32 0, i32 1} ; [ DW_TAG_lexical_block ] +!37 = metadata !{i32 786443, metadata !2, metadata !16, i32 11, i32 0, i32 0} ; [ DW_TAG_lexical_block ] +!38 = metadata !{i32 786688, metadata !39, metadata !"v", metadata !2, i32 24, metadata !1, i32 0, i32 0} ; [ DW_TAG_auto_variable ] +!39 = metadata !{i32 786443, metadata !2, metadata !40, i32 23, i32 0, i32 4} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 786443, metadata !2, metadata !20, i32 23, i32 0, i32 3} ; [ DW_TAG_lexical_block ] !41 = metadata !{i32 24, i32 0, metadata !39, null} !42 = metadata !{i32 25, i32 0, metadata !39, null} !43 = metadata !{i32 26, i32 0, metadata !39, null} -!44 = metadata !{i32 524544, metadata !39, metadata !"k", metadata !2, i32 26, metadata !13} ; [ DW_TAG_auto_variable ] +!44 = metadata !{i32 786688, metadata !39, metadata !"k", metadata !2, i32 26, metadata !13, i32 0, i32 0} ; [ DW_TAG_auto_variable ] !45 = metadata !{i32 27, i32 0, metadata !39, null} +!46 = metadata !{metadata !0, metadata !9, metadata !16, metadata !17, metadata !20} +!47 = metadata !{i32 0} +!48 = metadata !{metadata !"small.cc", metadata !"/Users/manav/R8248330"} diff --git a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll index 8b164c5d91f8..94a05412f5d4 100644 --- a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll +++ b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll @@ -23,7 +23,7 @@ entry: ; OBJ: Relocation 0 ; OBJ-NEXT: 'r_offset', 0x00000004 -; OBJ-NEXT: 'r_sym', 0x000007 +; OBJ-NEXT: 'r_sym', 0x000009 ; OBJ-NEXT: 'r_type', 0x2b ; OBJ: Relocation 1 @@ -33,7 +33,7 @@ entry: ; OBJ: # Relocation 2 ; OBJ-NEXT: 'r_offset', 0x0000000c -; OBJ-NEXT: 'r_sym', 0x000008 +; OBJ-NEXT: 'r_sym', 0x00000a ; OBJ-NEXT: 'r_type', 0x1c } diff --git a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll index 5cfbb4f944f7..1272a257931d 100644 --- a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll +++ b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -10,7 +10,8 @@ @STRIDE = internal global i32 8 ; ASM: .type array00,%object @ @array00 -; ASM-NEXT: .lcomm array00,80 +; ASM-NEXT: .local array00 +; ASM-NEXT: .comm array00,80,1 ; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index ca88eedcea60..1d1b89a34f9a 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -75,44 +75,38 @@ entry: ret i8 %0, !dbg !39 } -!llvm.dbg.sp = !{!0, !6, !7, !8, !9} -!llvm.dbg.lv.get1 = !{!10, !11} -!llvm.dbg.gv = !{!13, !14, !15, !16, !17} -!llvm.dbg.lv.get2 = !{!18, !19} -!llvm.dbg.lv.get3 = !{!21, !22} -!llvm.dbg.lv.get4 = !{!24, !25} -!llvm.dbg.lv.get5 = !{!27, !28} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"get1", metadata !"get1", metadata !"get1", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"foo.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"foo.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"get1", metadata !"get1", metadata !"get1", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get1, null, null, metadata !42, i32 4} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !47, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5, metadata !5} -!5 = metadata !{i32 589860, metadata !1, metadata !"_Bool", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"get2", metadata !"get2", metadata !"get2", metadata !1, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get2} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 589870, i32 0, metadata !1, metadata !"get3", metadata !"get3", metadata !"get3", metadata !1, i32 10, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get3} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 589870, i32 0, metadata !1, metadata !"get4", metadata !"get4", metadata !"get4", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get4} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 589870, i32 0, metadata !1, metadata !"get5", metadata !"get5", metadata !"get5", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get5} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 590081, metadata !0, metadata !"a", metadata !1, i32 4, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!11 = metadata !{i32 590080, metadata !12, metadata !"b", metadata !1, i32 4, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!12 = metadata !{i32 589835, metadata !0, i32 4, i32 0, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!13 = metadata !{i32 589876, i32 0, metadata !1, metadata !"x1", metadata !"x1", metadata !"", metadata !1, i32 3, metadata !5, i1 true, i1 true, i8* @x1} ; [ DW_TAG_variable ] -!14 = metadata !{i32 589876, i32 0, metadata !1, metadata !"x2", metadata !"x2", metadata !"", metadata !1, i32 6, metadata !5, i1 true, i1 true, i8* @x2} ; [ DW_TAG_variable ] -!15 = metadata !{i32 589876, i32 0, metadata !1, metadata !"x3", metadata !"x3", metadata !"", metadata !1, i32 9, metadata !5, i1 true, i1 true, i8* @x3} ; [ DW_TAG_variable ] -!16 = metadata !{i32 589876, i32 0, metadata !1, metadata !"x4", metadata !"x4", metadata !"", metadata !1, i32 12, metadata !5, i1 true, i1 true, i8* @x4} ; [ DW_TAG_variable ] -!17 = metadata !{i32 589876, i32 0, metadata !1, metadata !"x5", metadata !"x5", metadata !"", metadata !1, i32 15, metadata !5, i1 false, i1 true, i8* @x5} ; [ DW_TAG_variable ] -!18 = metadata !{i32 590081, metadata !6, metadata !"a", metadata !1, i32 7, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!19 = metadata !{i32 590080, metadata !20, metadata !"b", metadata !1, i32 7, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!20 = metadata !{i32 589835, metadata !6, i32 7, i32 0, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] -!21 = metadata !{i32 590081, metadata !7, metadata !"a", metadata !1, i32 10, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!22 = metadata !{i32 590080, metadata !23, metadata !"b", metadata !1, i32 10, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!23 = metadata !{i32 589835, metadata !7, i32 10, i32 0, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] -!24 = metadata !{i32 590081, metadata !8, metadata !"a", metadata !1, i32 13, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!25 = metadata !{i32 590080, metadata !26, metadata !"b", metadata !1, i32 13, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!26 = metadata !{i32 589835, metadata !8, i32 13, i32 0, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] -!27 = metadata !{i32 590081, metadata !9, metadata !"a", metadata !1, i32 16, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!28 = metadata !{i32 590080, metadata !29, metadata !"b", metadata !1, i32 16, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!29 = metadata !{i32 589835, metadata !9, i32 16, i32 0, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] +!5 = metadata !{i32 786468, metadata !1, metadata !1, metadata !"_Bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, metadata !1, metadata !"get2", metadata !"get2", metadata !"get2", metadata !1, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get2, null, null, metadata !43, i32 7} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786478, metadata !1, metadata !"get3", metadata !"get3", metadata !"get3", metadata !1, i32 10, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get3, null, null, metadata !44, i32 10} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 786478, metadata !1, metadata !"get4", metadata !"get4", metadata !"get4", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get4, null, null, metadata !45, i32 13} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 786478, metadata !1, metadata !"get5", metadata !"get5", metadata !"get5", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get5, null, null, metadata !46, i32 16} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 786689, metadata !0, metadata !"a", metadata !1, i32 4, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!11 = metadata !{i32 786688, metadata !12, metadata !"b", metadata !1, i32 4, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!12 = metadata !{i32 786443, metadata !0, i32 4, i32 0, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!13 = metadata !{i32 786484, i32 0, metadata !1, metadata !"x1", metadata !"x1", metadata !"", metadata !1, i32 3, metadata !5, i1 true, i1 true, i8* @x1, null} ; [ DW_TAG_variable ] +!14 = metadata !{i32 786484, i32 0, metadata !1, metadata !"x2", metadata !"x2", metadata !"", metadata !1, i32 6, metadata !5, i1 true, i1 true, i8* @x2, null} ; [ DW_TAG_variable ] +!15 = metadata !{i32 786484, i32 0, metadata !1, metadata !"x3", metadata !"x3", metadata !"", metadata !1, i32 9, metadata !5, i1 true, i1 true, i8* @x3, null} ; [ DW_TAG_variable ] +!16 = metadata !{i32 786484, i32 0, metadata !1, metadata !"x4", metadata !"x4", metadata !"", metadata !1, i32 12, metadata !5, i1 true, i1 true, i8* @x4, null} ; [ DW_TAG_variable ] +!17 = metadata !{i32 786484, i32 0, metadata !1, metadata !"x5", metadata !"x5", metadata !"", metadata !1, i32 15, metadata !5, i1 false, i1 true, i8* @x5, null} ; [ DW_TAG_variable ] +!18 = metadata !{i32 786689, metadata !6, metadata !"a", metadata !1, i32 7, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 786688, metadata !20, metadata !"b", metadata !1, i32 7, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!20 = metadata !{i32 786443, metadata !6, i32 7, i32 0, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!21 = metadata !{i32 786689, metadata !7, metadata !"a", metadata !1, i32 10, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!22 = metadata !{i32 786688, metadata !23, metadata !"b", metadata !1, i32 10, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!23 = metadata !{i32 786443, metadata !7, i32 10, i32 0, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 786689, metadata !8, metadata !"a", metadata !1, i32 13, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 786688, metadata !26, metadata !"b", metadata !1, i32 13, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!26 = metadata !{i32 786443, metadata !8, i32 13, i32 0, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] +!27 = metadata !{i32 786689, metadata !9, metadata !"a", metadata !1, i32 16, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!28 = metadata !{i32 786688, metadata !29, metadata !"b", metadata !1, i32 16, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 786443, metadata !9, i32 16, i32 0, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] !30 = metadata !{i32 4, i32 0, metadata !0, null} !31 = metadata !{i32 4, i32 0, metadata !12, null} !32 = metadata !{i32 7, i32 0, metadata !6, null} @@ -123,3 +117,11 @@ entry: !37 = metadata !{i32 13, i32 0, metadata !26, null} !38 = metadata !{i32 16, i32 0, metadata !9, null} !39 = metadata !{i32 16, i32 0, metadata !29, null} +!40 = metadata !{metadata !0, metadata !6, metadata !7, metadata !8, metadata !9} +!41 = metadata !{metadata !13, metadata !14, metadata !15, metadata !16, metadata !17} +!42 = metadata !{metadata !10, metadata !11} +!43 = metadata !{metadata !18, metadata !19} +!44 = metadata !{metadata !21, metadata !22} +!45 = metadata !{metadata !24, metadata !25} +!46 = metadata !{metadata !27, metadata !28} +!47 = metadata !{metadata !"foo.c", metadata !"/tmp/"} diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index f2b0c5d7d090..266609b8ce69 100644 --- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -8,7 +8,7 @@ ; DW_OP_constu ; offset -;CHECK: .long Lset33 +;CHECK: .long Lset8 ;CHECK-NEXT: @ DW_AT_type ;CHECK-NEXT: @ DW_AT_decl_file ;CHECK-NEXT: @ DW_AT_decl_line @@ -73,44 +73,37 @@ define i32 @get5(i32 %a) nounwind optsize ssp { declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!llvm.dbg.sp = !{!1, !6, !7, !8, !9} -!llvm.dbg.lv.get1 = !{!10, !11} -!llvm.dbg.lv.get2 = !{!13, !14} -!llvm.dbg.lv.get3 = !{!16, !17} -!llvm.dbg.lv.get4 = !{!19, !20} -!llvm.dbg.gv = !{!22, !23, !24, !25, !26} -!llvm.dbg.lv.get5 = !{!27, !28} -!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"ss3.c", metadata !"/private/tmp", metadata !"clang", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"get1", metadata !"get1", metadata !"", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get1, null, null} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 589865, metadata !"ss3.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786449, metadata !47, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"get1", metadata !"get1", metadata !"", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get1, null, null, metadata !42, i32 5} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786453, metadata !2, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 589870, i32 0, metadata !2, metadata !"get2", metadata !"get2", metadata !"", metadata !2, i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get2, null, null} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 589870, i32 0, metadata !2, metadata !"get3", metadata !"get3", metadata !"", metadata !2, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get3, null, null} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 589870, i32 0, metadata !2, metadata !"get4", metadata !"get4", metadata !"", metadata !2, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get4, null, null} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 589870, i32 0, metadata !2, metadata !"get5", metadata !"get5", metadata !"", metadata !2, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get5, null, null} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 590081, metadata !1, metadata !"a", metadata !2, i32 16777221, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!11 = metadata !{i32 590080, metadata !12, metadata !"b", metadata !2, i32 5, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!12 = metadata !{i32 589835, metadata !1, i32 5, i32 19, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] -!13 = metadata !{i32 590081, metadata !6, metadata !"a", metadata !2, i32 16777224, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!14 = metadata !{i32 590080, metadata !15, metadata !"b", metadata !2, i32 8, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!15 = metadata !{i32 589835, metadata !6, i32 8, i32 17, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] -!16 = metadata !{i32 590081, metadata !7, metadata !"a", metadata !2, i32 16777227, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!17 = metadata !{i32 590080, metadata !18, metadata !"b", metadata !2, i32 11, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!18 = metadata !{i32 589835, metadata !7, i32 11, i32 19, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] -!19 = metadata !{i32 590081, metadata !8, metadata !"a", metadata !2, i32 16777230, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!20 = metadata !{i32 590080, metadata !21, metadata !"b", metadata !2, i32 14, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!21 = metadata !{i32 589835, metadata !8, i32 14, i32 19, metadata !2, i32 3} ; [ DW_TAG_lexical_block ] -!22 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x5", metadata !"x5", metadata !"", metadata !2, i32 16, metadata !5, i32 0, i32 1, i32* @x5} ; [ DW_TAG_variable ] -!23 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x4", metadata !"x4", metadata !"", metadata !2, i32 13, metadata !5, i32 1, i32 1, i32* @x4} ; [ DW_TAG_variable ] -!24 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x3", metadata !"x3", metadata !"", metadata !2, i32 10, metadata !5, i32 1, i32 1, i32* @x3} ; [ DW_TAG_variable ] -!25 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x2", metadata !"x2", metadata !"", metadata !2, i32 7, metadata !5, i32 1, i32 1, i32* @x2} ; [ DW_TAG_variable ] -!26 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x1", metadata !"x1", metadata !"", metadata !2, i32 4, metadata !5, i32 1, i32 1, i32* @x1} ; [ DW_TAG_variable ] -!27 = metadata !{i32 590081, metadata !9, metadata !"a", metadata !2, i32 16777233, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!28 = metadata !{i32 590080, metadata !29, metadata !"b", metadata !2, i32 17, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!29 = metadata !{i32 589835, metadata !9, i32 17, i32 19, metadata !2, i32 4} ; [ DW_TAG_lexical_block ] +!5 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, metadata !2, metadata !"get2", metadata !"get2", metadata !"", metadata !2, i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get2, null, null, metadata !43, i32 8} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786478, metadata !2, metadata !"get3", metadata !"get3", metadata !"", metadata !2, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get3, null, null, metadata !44, i32 11} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 786478, metadata !2, metadata !"get4", metadata !"get4", metadata !"", metadata !2, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get4, null, null, metadata !45, i32 14} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 786478, metadata !2, metadata !"get5", metadata !"get5", metadata !"", metadata !2, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get5, null, null, metadata !46, i32 17} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 786689, metadata !1, metadata !"a", metadata !2, i32 16777221, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!11 = metadata !{i32 786688, metadata !12, metadata !"b", metadata !2, i32 5, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!12 = metadata !{i32 786443, metadata !1, i32 5, i32 19, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!13 = metadata !{i32 786689, metadata !6, metadata !"a", metadata !2, i32 16777224, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!14 = metadata !{i32 786688, metadata !15, metadata !"b", metadata !2, i32 8, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!15 = metadata !{i32 786443, metadata !6, i32 8, i32 17, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!16 = metadata !{i32 786689, metadata !7, metadata !"a", metadata !2, i32 16777227, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 786688, metadata !18, metadata !"b", metadata !2, i32 11, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!18 = metadata !{i32 786443, metadata !7, i32 11, i32 19, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] +!19 = metadata !{i32 786689, metadata !8, metadata !"a", metadata !2, i32 16777230, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!20 = metadata !{i32 786688, metadata !21, metadata !"b", metadata !2, i32 14, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!21 = metadata !{i32 786443, metadata !8, i32 14, i32 19, metadata !2, i32 3} ; [ DW_TAG_lexical_block ] +!22 = metadata !{i32 786484, i32 0, metadata !0, metadata !"x5", metadata !"x5", metadata !"", metadata !2, i32 16, metadata !5, i32 0, i32 1, i32* @x5, null} ; [ DW_TAG_variable ] +!23 = metadata !{i32 786484, i32 0, metadata !0, metadata !"x4", metadata !"x4", metadata !"", metadata !2, i32 13, metadata !5, i32 1, i32 1, i32* @x4, null} ; [ DW_TAG_variable ] +!24 = metadata !{i32 786484, i32 0, metadata !0, metadata !"x3", metadata !"x3", metadata !"", metadata !2, i32 10, metadata !5, i32 1, i32 1, i32* @x3, null} ; [ DW_TAG_variable ] +!25 = metadata !{i32 786484, i32 0, metadata !0, metadata !"x2", metadata !"x2", metadata !"", metadata !2, i32 7, metadata !5, i32 1, i32 1, i32* @x2, null} ; [ DW_TAG_variable ] +!26 = metadata !{i32 786484, i32 0, metadata !0, metadata !"x1", metadata !"x1", metadata !"", metadata !2, i32 4, metadata !5, i32 1, i32 1, i32* @x1, null} ; [ DW_TAG_variable ] +!27 = metadata !{i32 786689, metadata !9, metadata !"a", metadata !2, i32 16777233, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!28 = metadata !{i32 786688, metadata !29, metadata !"b", metadata !2, i32 17, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 786443, metadata !9, i32 17, i32 19, metadata !2, i32 4} ; [ DW_TAG_lexical_block ] !30 = metadata !{i32 5, i32 16, metadata !1, null} !31 = metadata !{i32 5, i32 32, metadata !12, null} !32 = metadata !{i32 8, i32 14, metadata !6, null} @@ -121,3 +114,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !37 = metadata !{i32 14, i32 32, metadata !21, null} !38 = metadata !{i32 17, i32 16, metadata !9, null} !39 = metadata !{i32 17, i32 32, metadata !29, null} +!40 = metadata !{metadata !1, metadata !6, metadata !7, metadata !8, metadata !9} +!41 = metadata !{metadata !22, metadata !23, metadata !24, metadata !25, metadata !26} +!42 = metadata !{metadata !10, metadata !11} +!43 = metadata !{metadata !13, metadata !14} +!44 = metadata !{metadata !16, metadata !17} +!45 = metadata !{metadata !19, metadata !20} +!46 = metadata !{metadata !27, metadata !28} +!47 = metadata !{metadata !"ss3.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll b/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll index 6e0ef9619657..f563eeef0180 100644 --- a/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll +++ b/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll @@ -1,13 +1,5 @@ ; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s -; Should trigger a NEON store. -; CHECK: vstr -define void @f_0_12(i8* nocapture %c) nounwind optsize { -entry: - call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false) - ret void -} - ; Trigger multiple NEON stores. ; CHECK: vst1.64 ; CHECK-NEXT: vst1.64 diff --git a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll index f9ede7401a3c..0d0d03b23e86 100644 --- a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll +++ b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll @@ -8,7 +8,7 @@ define void @test_sqrt(<4 x float>* %X) nounwind { ; CHECK: movw r1, :lower16:{{.*}} ; CHECK: movt r1, :upper16:{{.*}} -; CHECK: vld1.64 {{.*}}, [r1, :128] +; CHECK: vld1.64 {{.*}}, [r1:128] ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} @@ -252,7 +252,7 @@ define void @test_powi(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vld1.64 {{.*}}, :128 +; CHECK: vld1.64 {{.*}}:128 ; CHECK: vmul.f32 {{.*}} ; CHECK: vst1.64 diff --git a/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/test/CodeGen/ARM/2011-12-14-machine-sink.ll index b21bb006e327..1b21f7571d8e 100644 --- a/test/CodeGen/ARM/2011-12-14-machine-sink.ll +++ b/test/CodeGen/ARM/2011-12-14-machine-sink.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS ; Radar 10266272 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" diff --git a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll index b05ec6367ee4..ca0964a05933 100644 --- a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll +++ b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -13,6 +13,7 @@ ; CHECK-NOT: ch SU ; CHECK: ch SU(2): Latency=1 ; CHECK-NOT: ch SU +; CHECK: Successors: ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}} ; CHECK-NOT: ch SU @@ -22,6 +23,7 @@ ; CHECK-NOT: ch SU ; CHECK: ch SU(2): Latency=1 ; CHECK-NOT: ch SU +; CHECK: Successors: define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: store volatile i32 65540, i32* %p1, align 4, !tbaa !0 diff --git a/test/CodeGen/ARM/2012-08-09-neon-extload.ll b/test/CodeGen/ARM/2012-08-09-neon-extload.ll index b55f1cae7fe6..764c58f2e159 100644 --- a/test/CodeGen/ARM/2012-08-09-neon-extload.ll +++ b/test/CodeGen/ARM/2012-08-09-neon-extload.ll @@ -18,7 +18,7 @@ define void @test_v2i8tov2i32() { %i32val = sext <2 x i8> %i8val to <2 x i32> store <2 x i32> %i32val, <2 x i32>* @var_v2i32 -; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :16] +; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16] ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]] ; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}} @@ -32,7 +32,7 @@ define void @test_v2i8tov2i64() { %i64val = sext <2 x i8> %i8val to <2 x i64> store <2 x i64> %i64val, <2 x i64>* @var_v2i64 -; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}, :16] +; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}:16] ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]] ; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}} ; CHECK: vmovl.s32 {{q[0-9]+}}, {{d[0-9]+}} @@ -50,7 +50,7 @@ define void @test_v4i8tov4i16() { %i16val = sext <4 x i8> %i8val to <4 x i16> store <4 x i16> %i16val, <4 x i16>* @var_v4i16 -; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32] +; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32] ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]] ; CHECK-NOT: vmovl.s16 @@ -65,7 +65,7 @@ define void @test_v4i8tov4i32() { %i16val = sext <4 x i8> %i8val to <4 x i32> store <4 x i32> %i16val, <4 x i32>* @var_v4i32 -; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32] +; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32] ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]] ; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}} @@ -79,7 +79,7 @@ define void @test_v2i16tov2i32() { %i32val = sext <2 x i16> %i16val to <2 x i32> store <2 x i32> %i32val, <2 x i32>* @var_v2i32 -; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32] +; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32] ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]] ; CHECK-NOT: vmovl @@ -94,7 +94,7 @@ define void @test_v2i16tov2i64() { %i64val = sext <2 x i16> %i16val to <2 x i64> store <2 x i64> %i64val, <2 x i64>* @var_v2i64 -; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32] +; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32] ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]] ; CHECK: vmovl.s32 {{q[0-9]+}}, d[[LOAD]] diff --git a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll new file mode 100644 index 000000000000..2f55204aa407 --- /dev/null +++ b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll @@ -0,0 +1,150 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +; PR12281 +; Test generataion of code for vmull instruction when multiplying 128-bit +; vectors that were created by sign-extending smaller vector sizes. +; +; The vmull operation requires 64-bit vectors, so we must extend the original +; vector size to 64 bits for vmull operation. +; Previously failed with an assertion because the <4 x i8> vector was too small +; for vmull. + +; Vector x Constant +; v4i8 +; +define void @sextload_v4i8_c(<4 x i8>* %v) nounwind { +;CHECK: sextload_v4i8_c: +entry: + %0 = load <4 x i8>* %v, align 8 + %v0 = sext <4 x i8> %0 to <4 x i32> +;CHECK: vmull + %v1 = mul <4 x i32> %v0, + store <4 x i32> %v1, <4 x i32>* undef, align 8 + ret void; +} + +; v2i8 +; +define void @sextload_v2i8_c(<2 x i8>* %v) nounwind { +;CHECK: sextload_v2i8_c: +entry: + %0 = load <2 x i8>* %v, align 8 + %v0 = sext <2 x i8> %0 to <2 x i64> +;CHECK: vmull + %v1 = mul <2 x i64> %v0, + store <2 x i64> %v1, <2 x i64>* undef, align 8 + ret void; +} + +; v2i16 +; +define void @sextload_v2i16_c(<2 x i16>* %v) nounwind { +;CHECK: sextload_v2i16_c: +entry: + %0 = load <2 x i16>* %v, align 8 + %v0 = sext <2 x i16> %0 to <2 x i64> +;CHECK: vmull + %v1 = mul <2 x i64> %v0, + store <2 x i64> %v1, <2 x i64>* undef, align 8 + ret void; +} + + +; Vector x Vector +; v4i8 +; +define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind { +;CHECK: sextload_v4i8_v: +entry: + %0 = load <4 x i8>* %v, align 8 + %v0 = sext <4 x i8> %0 to <4 x i32> + + %1 = load <4 x i8>* %p, align 8 + %v2 = sext <4 x i8> %1 to <4 x i32> +;CHECK: vmull + %v1 = mul <4 x i32> %v0, %v2 + store <4 x i32> %v1, <4 x i32>* undef, align 8 + ret void; +} + +; v2i8 +; +define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind { +;CHECK: sextload_v2i8_v: +entry: + %0 = load <2 x i8>* %v, align 8 + %v0 = sext <2 x i8> %0 to <2 x i64> + + %1 = load <2 x i8>* %p, align 8 + %v2 = sext <2 x i8> %1 to <2 x i64> +;CHECK: vmull + %v1 = mul <2 x i64> %v0, %v2 + store <2 x i64> %v1, <2 x i64>* undef, align 8 + ret void; +} + +; v2i16 +; +define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind { +;CHECK: sextload_v2i16_v: +entry: + %0 = load <2 x i16>* %v, align 8 + %v0 = sext <2 x i16> %0 to <2 x i64> + + %1 = load <2 x i16>* %p, align 8 + %v2 = sext <2 x i16> %1 to <2 x i64> +;CHECK: vmull + %v1 = mul <2 x i64> %v0, %v2 + store <2 x i64> %v1, <2 x i64>* undef, align 8 + ret void; +} + + +; Vector(small) x Vector(big) +; v4i8 x v4i16 +; +define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind { +;CHECK: sextload_v4i8_vs: +entry: + %0 = load <4 x i8>* %v, align 8 + %v0 = sext <4 x i8> %0 to <4 x i32> + + %1 = load <4 x i16>* %p, align 8 + %v2 = sext <4 x i16> %1 to <4 x i32> +;CHECK: vmull + %v1 = mul <4 x i32> %v0, %v2 + store <4 x i32> %v1, <4 x i32>* undef, align 8 + ret void; +} + +; v2i8 +; v2i8 x v2i16 +define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind { +;CHECK: sextload_v2i8_vs: +entry: + %0 = load <2 x i8>* %v, align 8 + %v0 = sext <2 x i8> %0 to <2 x i64> + + %1 = load <2 x i16>* %p, align 8 + %v2 = sext <2 x i16> %1 to <2 x i64> +;CHECK: vmull + %v1 = mul <2 x i64> %v0, %v2 + store <2 x i64> %v1, <2 x i64>* undef, align 8 + ret void; +} + +; v2i16 +; v2i16 x v2i32 +define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind { +;CHECK: sextload_v2i16_vs: +entry: + %0 = load <2 x i16>* %v, align 8 + %v0 = sext <2 x i16> %0 to <2 x i64> + + %1 = load <2 x i32>* %p, align 8 + %v2 = sext <2 x i32> %1 to <2 x i64> +;CHECK: vmull + %v1 = mul <2 x i64> %v0, %v2 + store <2 x i64> %v1, <2 x i64>* undef, align 8 + ret void; +} diff --git a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll index b5f6d311cb9c..b0644d17431d 100644 --- a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll +++ b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll @@ -19,7 +19,7 @@ entry: ; CHECK: bfc [[REG]], #0, #3 %0 = va_arg i8** %g, double call void @llvm.va_end(i8* %g1) - + ret void } diff --git a/test/CodeGen/ARM/2012-11-14-subs_carry.ll b/test/CodeGen/ARM/2012-11-14-subs_carry.ll new file mode 100644 index 000000000000..38700f3a8d10 --- /dev/null +++ b/test/CodeGen/ARM/2012-11-14-subs_carry.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s + +;CHECK: foo +;CHECK: adds +;CHECK-NEXT: adc +;CHECK-NEXT: bx + +;rdar://12028498 + +define i32 @foo() nounwind ssp { +entry: + %tmp2 = zext i32 3 to i64 + br label %bug_block + +bug_block: + %tmp410 = and i64 1031, 1647010 + %tmp411 = and i64 %tmp2, -211 + %tmp412 = shl i64 %tmp410, %tmp2 + %tmp413 = shl i64 %tmp411, %tmp2 + %tmp415 = and i64 %tmp413, 1 + %tmp420 = xor i64 0, %tmp415 + %tmp421 = and i64 %tmp412, %tmp415 + %tmp422 = shl i64 %tmp421, 1 + br label %finish + +finish: + %tmp423 = lshr i64 %tmp422, 32 + %tmp424 = trunc i64 %tmp423 to i32 + ret i32 %tmp424 +} + diff --git a/test/CodeGen/ARM/2013-01-21-PR14992.ll b/test/CodeGen/ARM/2013-01-21-PR14992.ll new file mode 100644 index 000000000000..38b9e0e8f086 --- /dev/null +++ b/test/CodeGen/ARM/2013-01-21-PR14992.ll @@ -0,0 +1,28 @@ +;PR14492 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA +;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s +;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s + +;EXPECTED: foo: +;CHECK: foo: +define i32 @foo(i32* %a) nounwind optsize { +entry: + %0 = load i32* %a, align 4, !tbaa !0 + %arrayidx1 = getelementptr inbounds i32* %a, i32 1 + %1 = load i32* %arrayidx1, align 4, !tbaa !0 + %arrayidx2 = getelementptr inbounds i32* %a, i32 2 + %2 = load i32* %arrayidx2, align 4, !tbaa !0 + %add.ptr = getelementptr inbounds i32* %a, i32 3 +;Make sure we do not have a duplicated register in the front of the reg list +;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}}, +;CHECK-NOT: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], [[REG]], + tail call void @bar(i32* %add.ptr) nounwind optsize + %add = add nsw i32 %1, %0 + %add3 = add nsw i32 %add, %2 + ret i32 %add3 +} + +declare void @bar(i32*) optsize + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/ARM/2013-02-27-expand-vfma.ll b/test/CodeGen/ARM/2013-02-27-expand-vfma.ll new file mode 100644 index 000000000000..0e3bf2371061 --- /dev/null +++ b/test/CodeGen/ARM/2013-02-27-expand-vfma.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4 + +define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind { +; CHECK: muladd: +; CHECK: fmaf +; CHECK: fmaf +; CHECK: fmaf +; CHECK: fmaf +; CHECK-NOT: fmaf + +; CHECK-VFP4: vfma.f32 + %tmp = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %c, <4 x float> %a) #2 + ret <4 x float> %tmp +} + +declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 + +define <2 x float> @muladd2(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind { +; CHECK: muladd2: +; CHECK: fmaf +; CHECK: fmaf +; CHECK-NOT: fmaf + +; CHECK-VFP4: vfma.f32 + %tmp = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 x float> %c, <2 x float> %a) #2 + ret <2 x float> %tmp +} + +declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 + diff --git a/test/CodeGen/ARM/2013-04-05-overridden-loads-PR14824.ll b/test/CodeGen/ARM/2013-04-05-overridden-loads-PR14824.ll new file mode 100644 index 000000000000..2561686c1f83 --- /dev/null +++ b/test/CodeGen/ARM/2013-04-05-overridden-loads-PR14824.ll @@ -0,0 +1,110 @@ +; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp | FileCheck %s +; The test is presented by Jiangning Liu. +;CHECK-NOT: vldmia + +define void @sample_test(<8 x i64> * %secondSource, <8 x i64> * %source, <8 x i64> * %dest) nounwind { +entry: + %s0 = load <8 x i64> * %source, align 64 + %s1 = load <8 x i64> * %secondSource, align 64 + %s2 = bitcast <8 x i64> %s0 to i512 + %data.i.i.48.extract.shift = lshr i512 %s2, 384 + %data.i.i.48.extract.trunc = trunc i512 %data.i.i.48.extract.shift to i64 + %arrayidx64 = getelementptr inbounds <8 x i64> * %source, i32 6 + %s120 = load <8 x i64> * %arrayidx64, align 64 + %arrayidx67 = getelementptr inbounds <8 x i64> * %secondSource, i32 6 + %s121 = load <8 x i64> * %arrayidx67, align 64 + %s122 = bitcast <8 x i64> %s120 to i512 + %data.i.i677.48.extract.shift = lshr i512 %s122, 384 + %data.i.i677.48.extract.trunc = trunc i512 %data.i.i677.48.extract.shift to i64 + %s123 = insertelement <8 x i64> undef, i64 %data.i.i677.48.extract.trunc, i32 0 + %data.i.i677.32.extract.shift = lshr i512 %s122, 256 + %data.i.i677.32.extract.trunc = trunc i512 %data.i.i677.32.extract.shift to i64 + %s124 = insertelement <8 x i64> %s123, i64 %data.i.i677.32.extract.trunc, i32 1 + %data.i.i677.16.extract.shift = lshr i512 %s122, 128 + %data.i.i677.16.extract.trunc = trunc i512 %data.i.i677.16.extract.shift to i64 + %s125 = insertelement <8 x i64> %s124, i64 %data.i.i677.16.extract.trunc, i32 2 + %data.i.i677.56.extract.shift = lshr i512 %s122, 448 + %data.i.i677.56.extract.trunc = trunc i512 %data.i.i677.56.extract.shift to i64 + %s126 = insertelement <8 x i64> %s125, i64 %data.i.i677.56.extract.trunc, i32 3 + %data.i.i677.24.extract.shift = lshr i512 %s122, 192 + %data.i.i677.24.extract.trunc = trunc i512 %data.i.i677.24.extract.shift to i64 + %s127 = insertelement <8 x i64> %s126, i64 %data.i.i677.24.extract.trunc, i32 4 + %s128 = insertelement <8 x i64> %s127, i64 %data.i.i677.32.extract.trunc, i32 5 + %s129 = insertelement <8 x i64> %s128, i64 %data.i.i677.16.extract.trunc, i32 6 + %s130 = insertelement <8 x i64> %s129, i64 %data.i.i677.56.extract.trunc, i32 7 + %s131 = bitcast <8 x i64> %s121 to i512 + %data.i1.i676.48.extract.shift = lshr i512 %s131, 384 + %data.i1.i676.48.extract.trunc = trunc i512 %data.i1.i676.48.extract.shift to i64 + %s132 = insertelement <8 x i64> undef, i64 %data.i1.i676.48.extract.trunc, i32 0 + %data.i1.i676.32.extract.shift = lshr i512 %s131, 256 + %data.i1.i676.32.extract.trunc = trunc i512 %data.i1.i676.32.extract.shift to i64 + %s133 = insertelement <8 x i64> %s132, i64 %data.i1.i676.32.extract.trunc, i32 1 + %data.i1.i676.16.extract.shift = lshr i512 %s131, 128 + %data.i1.i676.16.extract.trunc = trunc i512 %data.i1.i676.16.extract.shift to i64 + %s134 = insertelement <8 x i64> %s133, i64 %data.i1.i676.16.extract.trunc, i32 2 + %data.i1.i676.56.extract.shift = lshr i512 %s131, 448 + %data.i1.i676.56.extract.trunc = trunc i512 %data.i1.i676.56.extract.shift to i64 + %s135 = insertelement <8 x i64> %s134, i64 %data.i1.i676.56.extract.trunc, i32 3 + %data.i1.i676.24.extract.shift = lshr i512 %s131, 192 + %data.i1.i676.24.extract.trunc = trunc i512 %data.i1.i676.24.extract.shift to i64 + %s136 = insertelement <8 x i64> %s135, i64 %data.i1.i676.24.extract.trunc, i32 4 + %s137 = insertelement <8 x i64> %s136, i64 %data.i1.i676.32.extract.trunc, i32 5 + %s138 = insertelement <8 x i64> %s137, i64 %data.i1.i676.16.extract.trunc, i32 6 + %s139 = insertelement <8 x i64> %s138, i64 %data.i1.i676.56.extract.trunc, i32 7 + %vecinit28.i.i699 = shufflevector <8 x i64> %s139, <8 x i64> %s130, <8 x i32> + %vecinit35.i.i700 = shufflevector <8 x i64> %vecinit28.i.i699, <8 x i64> %s139, <8 x i32> + %vecinit42.i.i701 = shufflevector <8 x i64> %vecinit35.i.i700, <8 x i64> %s139, <8 x i32> + %vecinit49.i.i702 = shufflevector <8 x i64> %vecinit42.i.i701, <8 x i64> %s130, <8 x i32> + %arrayidx72 = getelementptr inbounds <8 x i64> * %dest, i32 6 + store <8 x i64> %vecinit49.i.i702, <8 x i64> * %arrayidx72, align 64 + %arrayidx75 = getelementptr inbounds <8 x i64> * %source, i32 7 + %s140 = load <8 x i64> * %arrayidx75, align 64 + %arrayidx78 = getelementptr inbounds <8 x i64> * %secondSource, i32 7 + %s141 = load <8 x i64> * %arrayidx78, align 64 + %s142 = bitcast <8 x i64> %s140 to i512 + %data.i.i650.32.extract.shift = lshr i512 %s142, 256 + %data.i.i650.32.extract.trunc = trunc i512 %data.i.i650.32.extract.shift to i64 + %s143 = insertelement <8 x i64> undef, i64 %data.i.i650.32.extract.trunc, i32 0 + %s144 = insertelement <8 x i64> %s143, i64 %data.i.i650.32.extract.trunc, i32 1 + %data.i.i650.16.extract.shift = lshr i512 %s142, 128 + %data.i.i650.16.extract.trunc = trunc i512 %data.i.i650.16.extract.shift to i64 + %s145 = insertelement <8 x i64> %s144, i64 %data.i.i650.16.extract.trunc, i32 2 + %data.i.i650.8.extract.shift = lshr i512 %s142, 64 + %data.i.i650.8.extract.trunc = trunc i512 %data.i.i650.8.extract.shift to i64 + %s146 = insertelement <8 x i64> %s145, i64 %data.i.i650.8.extract.trunc, i32 3 + %s147 = insertelement <8 x i64> %s146, i64 %data.i.i650.8.extract.trunc, i32 4 + %data.i.i650.48.extract.shift = lshr i512 %s142, 384 + %data.i.i650.48.extract.trunc = trunc i512 %data.i.i650.48.extract.shift to i64 + %s148 = insertelement <8 x i64> %s147, i64 %data.i.i650.48.extract.trunc, i32 5 + %s149 = insertelement <8 x i64> %s148, i64 %data.i.i650.16.extract.trunc, i32 6 + %data.i.i650.0.extract.trunc = trunc i512 %s142 to i64 + %s150 = insertelement <8 x i64> %s149, i64 %data.i.i650.0.extract.trunc, i32 7 + %s151 = bitcast <8 x i64> %s141 to i512 + %data.i1.i649.32.extract.shift = lshr i512 %s151, 256 + %data.i1.i649.32.extract.trunc = trunc i512 %data.i1.i649.32.extract.shift to i64 + %s152 = insertelement <8 x i64> undef, i64 %data.i1.i649.32.extract.trunc, i32 0 + %s153 = insertelement <8 x i64> %s152, i64 %data.i1.i649.32.extract.trunc, i32 1 + %data.i1.i649.16.extract.shift = lshr i512 %s151, 128 + %data.i1.i649.16.extract.trunc = trunc i512 %data.i1.i649.16.extract.shift to i64 + %s154 = insertelement <8 x i64> %s153, i64 %data.i1.i649.16.extract.trunc, i32 2 + %data.i1.i649.8.extract.shift = lshr i512 %s151, 64 + %data.i1.i649.8.extract.trunc = trunc i512 %data.i1.i649.8.extract.shift to i64 + %s155 = insertelement <8 x i64> %s154, i64 %data.i1.i649.8.extract.trunc, i32 3 + %s156 = insertelement <8 x i64> %s155, i64 %data.i1.i649.8.extract.trunc, i32 4 + %data.i1.i649.48.extract.shift = lshr i512 %s151, 384 + %data.i1.i649.48.extract.trunc = trunc i512 %data.i1.i649.48.extract.shift to i64 + %s157 = insertelement <8 x i64> %s156, i64 %data.i1.i649.48.extract.trunc, i32 5 + %s158 = insertelement <8 x i64> %s157, i64 %data.i1.i649.16.extract.trunc, i32 6 + %data.i1.i649.0.extract.trunc = trunc i512 %s151 to i64 + %s159 = insertelement <8 x i64> %s158, i64 %data.i1.i649.0.extract.trunc, i32 7 + %vecinit7.i.i669 = shufflevector <8 x i64> %s159, <8 x i64> %s150, <8 x i32> + %vecinit14.i.i670 = shufflevector <8 x i64> %vecinit7.i.i669, <8 x i64> %s150, <8 x i32> + %vecinit21.i.i671 = shufflevector <8 x i64> %vecinit14.i.i670, <8 x i64> %s150, <8 x i32> + %vecinit28.i.i672 = shufflevector <8 x i64> %vecinit21.i.i671, <8 x i64> %s150, <8 x i32> + %vecinit35.i.i673 = shufflevector <8 x i64> %vecinit28.i.i672, <8 x i64> %s159, <8 x i32> + %vecinit42.i.i674 = shufflevector <8 x i64> %vecinit35.i.i673, <8 x i64> %s159, <8 x i32> + %vecinit49.i.i675 = shufflevector <8 x i64> %vecinit42.i.i674, <8 x i64> %s159, <8 x i32> + %arrayidx83 = getelementptr inbounds <8 x i64> * %dest, i32 7 + store <8 x i64> %vecinit49.i.i675, <8 x i64> * %arrayidx83, align 64 + ret void +} diff --git a/test/CodeGen/ARM/DbgValueOtherTargets.test b/test/CodeGen/ARM/DbgValueOtherTargets.test new file mode 100644 index 000000000000..bf90891de0a7 --- /dev/null +++ b/test/CodeGen/ARM/DbgValueOtherTargets.test @@ -0,0 +1 @@ +RUN: llc -O0 -march=arm -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/ARM/MergeConsecutiveStores.ll b/test/CodeGen/ARM/MergeConsecutiveStores.ll new file mode 100644 index 000000000000..06c87e986a83 --- /dev/null +++ b/test/CodeGen/ARM/MergeConsecutiveStores.ll @@ -0,0 +1,98 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s + +; Make sure that we merge the consecutive load/store sequence below and use a +; word (16 bit) instead of a byte copy. +; CHECK: MergeLoadStoreBaseIndexOffset +; CHECK: ldrh [[REG:r[0-9]+]], [{{.*}}] +; CHECK: strh [[REG]], [r1], #2 +define void @MergeLoadStoreBaseIndexOffset(i32* %a, i8* %b, i8* %c, i32 %n) { + br label %1 + +;