========================================================
Architecture & Platform Information for Compiler Writers
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.. contents::
:local:
.. note::
This document is a work-in-progress. Additions and clarifications are
welcome.
Hardware
========
ARM
---
* `ARM documentation `_ (`Processor Cores `_ Cores)
* `ABI `_
AArch64
-------
* `ARMv8 Instruction Set Overview `_
Itanium (ia64)
--------------
* `Itanium documentation `_
MIPS
----
* `MIPS Processor Architecture `_
PowerPC
-------
IBM - Official manuals and docs
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
* `Power Instruction Set Architecture, Versions 2.03 through 2.06 (authentication required, free sign-up) `_
* `PowerPC Compiler Writer's Guide `_
* `Intro to PowerPC Architecture `_
* `PowerPC Processor Manuals (embedded) `_
* `Various IBM specifications and white papers `_
* `IBM AIX/5L for POWER Assembly Reference `_
Other documents, collections, notes
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
* `PowerPC ABI documents `_
* `PowerPC64 alignment of long doubles (from GCC) `_
* `Long branch stubs for powerpc64-linux (from binutils) `_
SPARC
-----
* `SPARC resources `_
* `SPARC standards `_
X86
---
AMD - Official manuals and docs
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
* `AMD processor manuals `_
* `X86-64 ABI `_
Intel - Official manuals and docs
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
* `Intel 64 and IA-32 manuals `_
* `Intel Itanium documentation `_
Other x86-specific information
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
* `Calling conventions for different C++ compilers and operating systems `_
Other relevant lists
--------------------
* `GCC reading list `_
ABI
===
Linux
-----
* `PowerPC 64-bit ELF ABI Supplement `_
* `Procedure Call Standard for the AArch64 Architecture `_
* `ELF for the ARM 64-bit Architecture (AArch64) `_
OS X
----
* `Mach-O Runtime Architecture `_
* `Notes on Mach-O ABI `_
NVPTX
=====
* `CUDA Documentation `_ includes the PTX
ISA and Driver API documentation
Miscellaneous Resources
=======================
* `Executable File Format library `_
* `GCC prefetch project `_ page has a
good survey of the prefetching capabilities of a variety of modern
processors.