1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
|
; RUN: opt -O3 -S < %s | FileCheck %s
; Show 'optnone' suppresses optimizations.
; Two attribute groups that differ only by 'optnone'.
; 'optnone' requires 'noinline' so #0 is 'noinline' by itself,
; even though it would otherwise be irrelevant to this example.
attributes #0 = { noinline }
attributes #1 = { noinline optnone }
; int iadd(int a, int b){ return a + b; }
define i32 @iadd_optimize(i32 %a, i32 %b) #0 {
entry:
%a.addr = alloca i32, align 4
%b.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
store i32 %b, i32* %b.addr, align 4
%0 = load i32* %a.addr, align 4
%1 = load i32* %b.addr, align 4
%add = add nsw i32 %0, %1
ret i32 %add
}
; CHECK-LABEL: @iadd_optimize
; CHECK-NOT: alloca
; CHECK-NOT: store
; CHECK-NOT: load
; CHECK: ret
define i32 @iadd_optnone(i32 %a, i32 %b) #1 {
entry:
%a.addr = alloca i32, align 4
%b.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
store i32 %b, i32* %b.addr, align 4
%0 = load i32* %a.addr, align 4
%1 = load i32* %b.addr, align 4
%add = add nsw i32 %0, %1
ret i32 %add
}
; CHECK-LABEL: @iadd_optnone
; CHECK: alloca i32
; CHECK: alloca i32
; CHECK: store i32
; CHECK: store i32
; CHECK: load i32
; CHECK: load i32
; CHECK: add nsw i32
; CHECK: ret i32
; float fsub(float a, float b){ return a - b; }
define float @fsub_optimize(float %a, float %b) #0 {
entry:
%a.addr = alloca float, align 4
%b.addr = alloca float, align 4
store float %a, float* %a.addr, align 4
store float %b, float* %b.addr, align 4
%0 = load float* %a.addr, align 4
%1 = load float* %b.addr, align 4
%sub = fsub float %0, %1
ret float %sub
}
; CHECK-LABEL: @fsub_optimize
; CHECK-NOT: alloca
; CHECK-NOT: store
; CHECK-NOT: load
; CHECK: ret
define float @fsub_optnone(float %a, float %b) #1 {
entry:
%a.addr = alloca float, align 4
%b.addr = alloca float, align 4
store float %a, float* %a.addr, align 4
store float %b, float* %b.addr, align 4
%0 = load float* %a.addr, align 4
%1 = load float* %b.addr, align 4
%sub = fsub float %0, %1
ret float %sub
}
; CHECK-LABEL: @fsub_optnone
; CHECK: alloca float
; CHECK: alloca float
; CHECK: store float
; CHECK: store float
; CHECK: load float
; CHECK: load float
; CHECK: fsub float
; CHECK: ret float
; typedef float __attribute__((ext_vector_type(4))) float4;
; float4 vmul(float4 a, float4 b){ return a * b; }
define <4 x float> @vmul_optimize(<4 x float> %a, <4 x float> %b) #0 {
entry:
%a.addr = alloca <4 x float>, align 16
%b.addr = alloca <4 x float>, align 16
store <4 x float> %a, <4 x float>* %a.addr, align 16
store <4 x float> %b, <4 x float>* %b.addr, align 16
%0 = load <4 x float>* %a.addr, align 16
%1 = load <4 x float>* %b.addr, align 16
%mul = fmul <4 x float> %0, %1
ret <4 x float> %mul
}
; CHECK-LABEL: @vmul_optimize
; CHECK-NOT: alloca
; CHECK-NOT: store
; CHECK-NOT: load
; CHECK: ret
define <4 x float> @vmul_optnone(<4 x float> %a, <4 x float> %b) #1 {
entry:
%a.addr = alloca <4 x float>, align 16
%b.addr = alloca <4 x float>, align 16
store <4 x float> %a, <4 x float>* %a.addr, align 16
store <4 x float> %b, <4 x float>* %b.addr, align 16
%0 = load <4 x float>* %a.addr, align 16
%1 = load <4 x float>* %b.addr, align 16
%mul = fmul <4 x float> %0, %1
ret <4 x float> %mul
}
; CHECK-LABEL: @vmul_optnone
; CHECK: alloca <4 x float>
; CHECK: alloca <4 x float>
; CHECK: store <4 x float>
; CHECK: store <4 x float>
; CHECK: load <4 x float>
; CHECK: load <4 x float>
; CHECK: fmul <4 x float>
; CHECK: ret
|
