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<title>src/sys/amd64/include/pcpu.h, branch release/8.2.0</title>
<subtitle>FreeBSD source tree</subtitle>
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<updated>2010-08-05T22:01:14Z</updated>
<entry>
<title>MFC 210623:</title>
<updated>2010-08-05T22:01:14Z</updated>
<author>
<name>John Baldwin</name>
<email>jhb@FreeBSD.org</email>
</author>
<published>2010-08-05T22:01:14Z</published>
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<id>urn:sha1:d4b6c4d58ad6c82c6042ff2a46487ab537fe4c22</id>
<content type='text'>
Mark the __curthread() functions as __pure2 and remove the volatile keyword
from the inline assembly.  This allows the compiler to cache invocations of
curthread since it's value does not change within a thread context.
</content>
</entry>
<entry>
<title>MFC 208507,208556,208621:</title>
<updated>2010-07-14T21:10:14Z</updated>
<author>
<name>John Baldwin</name>
<email>jhb@FreeBSD.org</email>
</author>
<published>2010-07-14T21:10:14Z</published>
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<id>urn:sha1:f2d982501bf5e798a804cbf500705a0db5dbb8ad</id>
<content type='text'>
Add support for corrected machine check interrupts.  CMCI is a new local
APIC interrupt that fires when a threshold of corrected machine check
events is reached.  CMCI also includes a count of events when reporting
corrected errors in the bank's status register.  Note that individual
banks may or may not support CMCI.  If they do, each bank includes its own
threshold register that determines when the interrupt fires.  Currently
the code uses a very simple strategy where it doubles the threshold on
each interrupt until it succeeds in throttling the interrupt to occur
only once a minute (this interval can be tuned via sysctl).  The threshold
is also adjusted on each hourly poll which will lower the threshold once
events stop occurring.
</content>
</entry>
<entry>
<title>Fix XENHVM build.</title>
<updated>2009-05-06T17:48:39Z</updated>
<author>
<name>Doug Rabson</name>
<email>dfr@FreeBSD.org</email>
</author>
<published>2009-05-06T17:48:39Z</published>
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<id>urn:sha1:8480241102f2c23920e7450bd9ad517ebf054697</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Save and restore segment registers on amd64 when entering and leaving</title>
<updated>2009-04-01T13:09:26Z</updated>
<author>
<name>Konstantin Belousov</name>
<email>kib@FreeBSD.org</email>
</author>
<published>2009-04-01T13:09:26Z</published>
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<id>urn:sha1:2c66cccab7ceceb3eed086da3b2dedfc77ce72de</id>
<content type='text'>
the kernel on amd64. Fill and read segment registers for mcontext and
signals. Handle traps caused by restoration of the
invalidated selectors.

Implement user-mode creation and manipulation of the process-specific
LDT descriptors for amd64, see sysarch(2).

Implement support for TSS i/o port access permission bitmap for amd64.

Context-switch LDT and TSS. Do not save and restore segment registers on
the context switch, that is handled by kernel enter/leave trampolines
now. Remove segment restore code from the signal trampolines for
freebsd/amd64, freebsd/ia32 and linux/i386 for the same reason.

Implement amd64-specific compat shims for sysarch.

Linuxolator (temporary ?) switched to use gsbase for thread_area pointer.

TODO:
Currently, gdb is not adapted to show segment registers from struct reg.
Also, no machine-depended ptrace command is added to set segment
registers for debugged process.

In collaboration with:	pho
Discussed with:	peter
Reviewed by:	jhb
Linuxolator tested by:	dchagin
</content>
</entry>
<entry>
<title>Merge in support for Xen HVM on amd64 architecture.</title>
<updated>2009-03-11T15:30:12Z</updated>
<author>
<name>Doug Rabson</name>
<email>dfr@FreeBSD.org</email>
</author>
<published>2009-03-11T15:30:12Z</published>
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<id>urn:sha1:126780243806a6b6cf345b9b548f68010e921aec</id>
<content type='text'>
</content>
</entry>
<entry>
<title>The pcb_gs32p should be per-cpu, not per-thread pointer. This is</title>
<updated>2008-09-08T09:59:05Z</updated>
<author>
<name>Konstantin Belousov</name>
<email>kib@FreeBSD.org</email>
</author>
<published>2008-09-08T09:59:05Z</published>
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<id>urn:sha1:3bd5e467b2152635867ff255ac3ad273bb3325d2</id>
<content type='text'>
location in GDT where the segment descriptor from pcb_gs32sd is
copied, and the location is in GDT local to CPU.

Noted and reviewed by:	peter
MFC after:	1 week
</content>
</entry>
<entry>
<title>Export 'struct pcpu' to userland w/o requiring _KERNEL.  A few ports</title>
<updated>2008-08-19T19:53:52Z</updated>
<author>
<name>John Baldwin</name>
<email>jhb@FreeBSD.org</email>
</author>
<published>2008-08-19T19:53:52Z</published>
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<id>urn:sha1:70d12a18f21f17d8beb0fbead08f76ae36cc25e2</id>
<content type='text'>
already define _KERNEL to get to this and I'm about to add hooks to
libkvm to access per-CPU data.

MFC after:	1 week
</content>
</entry>
<entry>
<title> - Add an integer argument to idle to indicate how likely we are to wake</title>
<updated>2008-04-25T05:18:50Z</updated>
<author>
<name>Jeff Roberson</name>
<email>jeff@FreeBSD.org</email>
</author>
<published>2008-04-25T05:18:50Z</published>
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<id>urn:sha1:6c47aaae12ea84af9d94e32796fccb873af36a0e</id>
<content type='text'>
   from idle over the next tick.
 - Add a new MD routine, cpu_wake_idle() to wakeup idle threads who are
   suspended in cpu specific states.  This function can fail and cause the
   scheduler to fall back to another mechanism (ipi).
 - Implement support for mwait in cpu_idle() on i386/amd64 machines that
   support it.  mwait is a higher performance way to synchronize cpus
   as compared to hlt &amp; ipis.
 - Allow selecting the idle routine by name via sysctl machdep.idle.  This
   replaces machdep.cpu_idle_hlt.  Only idle routines supported by the
   current machine are permitted.

Sponsored by:	Nokia
</content>
</entry>
<entry>
<title>Rework the PCPU_* (MD) interface:</title>
<updated>2007-06-04T21:38:48Z</updated>
<author>
<name>Attilio Rao</name>
<email>attilio@FreeBSD.org</email>
</author>
<published>2007-06-04T21:38:48Z</published>
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<id>urn:sha1:6759608248f30eb575170c0700cc99140e0bdc35</id>
<content type='text'>
- Rename PCPU_LAZY_INC into PCPU_INC
- Add the PCPU_ADD interface which just does an add on the pcpu member
  given a specific value.

Note that for most architectures PCPU_INC and PCPU_ADD are not safe.
This is a point that needs some discussions/work in the next days.

Reviewed by: alc, bde
Approved by: jeff (mentor)
</content>
</entry>
<entry>
<title>Push down the implementation of PCPU_LAZY_INC() into the machine-dependent</title>
<updated>2007-03-11T05:54:29Z</updated>
<author>
<name>Alan Cox</name>
<email>alc@FreeBSD.org</email>
</author>
<published>2007-03-11T05:54:29Z</published>
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<id>urn:sha1:c640357f04dba4c8a42e43a1c44a85f97d359302</id>
<content type='text'>
header file.  Reimplement PCPU_LAZY_INC() on amd64 and i386 making it
atomic with respect to interrupts.

Reviewed by: bde, jhb
</content>
</entry>
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