src/sys/amd64/include/specialreg.h, branch stable/13FreeBSD source treehttps://cgit-dev.freebsd.org/src/atom?h=stable%2F132023-08-23T17:43:22Zsys: Remove $FreeBSD$: one-line .c comment pattern2023-08-23T17:43:22ZWarner Loshimp@FreeBSD.org2023-08-22T01:31:15Zurn:sha1:4fbf14e22d7b83de7080a8e491ba14a5785a0ff4
Remove /^/[*/]\s*\$FreeBSD\$.*\n/
Similar commit in current:
(cherry picked from commit 71625ec9ad2a)
Copy i386 specialreg.h to x86 and merge with amd64 specialreg.h. Replace2012-03-19T21:34:11ZTijl Coosemanstijl@FreeBSD.org2012-03-19T21:34:11Zurn:sha1:2c7879ea84b08a108da3bed4bc901a8e53a03a41
amd64/i386/pc98 specialreg.h with stubs.
Add definitions related to XCR0.2012-01-17T07:23:43ZKonstantin Belousovkib@FreeBSD.org2012-01-17T07:23:43Zurn:sha1:79937651efe294c6f935516ef2a3b168475eac37
MFC after: 1 week
Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features.2011-05-17T22:36:16ZJung-uk Kimjkim@FreeBSD.org2011-05-17T22:36:16Zurn:sha1:2b052e43be6a1e94b620193c6244542fdaa835e9
Note AMD dropped SSE5 extensions in order to avoid ISA overlap with Intel
AVX instructions. The SSE5 bit was recycled as XOP extended instruction
bit, CVT16 was deprecated in favor of F16C (half-precision float conversion
instructions for AVX), and the remaining FMA4 (4-operand FMA instructions)
gained a separate CPUID bit. Replace non-existent references with today's
CPUID specifications.
prepare code that does topology detection for amd cpus for bulldozer2011-05-06T13:51:54ZAndriy Gaponavg@FreeBSD.org2011-05-06T13:51:54Zurn:sha1:fdf30d59a69e04ce448694c1249c514685440f07
This also introduces a new detection path for family 10h and newer
pre-bulldozer cpus, pre-10h hardware should not be affected.
Tested by: Gary Jennejohn <gljennjohn@googlemail.com>
(with pre-10h hardware)
MFC after: 2 weeks
Define "Hypervisor Present" bit. This bit is used by several hypervisors to2011-04-28T22:23:39ZJung-uk Kimjkim@FreeBSD.org2011-04-28T22:23:39Zurn:sha1:c34e9dbee11c6e0a20362595a3d511bef146957e
identify CPUs running under emulation. Currently QEMU-KVM, Xen-HVM, VMware,
and MS Hyper-V are known to set this bit.
MFC after: 3 days
Add definitions for CPUID instruction 6, ECX information.2011-04-12T22:12:23ZJung-uk Kimjkim@FreeBSD.org2011-04-12T22:12:23Zurn:sha1:373117495457537763d4868ac2e7ecdec1b5c876specialreg.h: add definitions for some useful bits found in CPUID.6 EAX and ECX2010-11-23T13:55:30ZAndriy Gaponavg@FreeBSD.org2010-11-23T13:55:30Zurn:sha1:9b984feb3de32c59e4385449fc4f185dcdbb3404
CPUID.6 is defined as Thermal and Power Management Leaf by both Intel
and AMD.
Reviewed by: jhb
MFC after: 7 days
specialreg.h: add definitions for MPERF/APERF pair of MSRs2010-11-19T15:07:36ZAndriy Gaponavg@FreeBSD.org2010-11-19T15:07:36Zurn:sha1:b43d29256512d968a027fa478227f92bee82a7a9
These MSRs can be used to determine actual (average) performance as
compared to a maximum defined performance.
Availability of these MSRs is indicated by bit0 in CPUID.6.ECX on both
Intel and AMD processors.
MFC after: 5 days
specialreg.h: add AMD-specific "Hardware Configuration Register" MSR2010-11-19T15:00:20ZAndriy Gaponavg@FreeBSD.org2010-11-19T15:00:20Zurn:sha1:7af7c7624a8246f2d1803a367cbd113cbf34d5b1
It seems that this MSR has been available in a range of AMD processors
families for quite a while now.
Note1: not all AMD MSRs that are found in amd64 specialreg.h are also in
the i386 version.
Note2: perhaps some additional name component is needed to distinguish
AMD-specific MSRs.
MFC after: 5 days