src/sys/arm/include/armreg.h, branch release/10.4.0

MFC r278518: Resolve cache line size from CP15 instead of hard-coded 32.

2015-05-23T22:48:54Z

MFC r272356, r275639, r276638:

2015-02-13T02:02:12Z

Split syscall handling out to a separate file. Include sys/kernel.h to pick up the definition of hz in syscall.c Add a new trap-v6.c which has support for all armv7 exceptions.

MFC r271394, r271398:

2015-02-12T03:50:33Z

Add more register values to armreg.h and remove CPU_CONTROL_32BP_ENABLE from asm.h as they were already defined in armreg.h. Unify interrupts bit definition and usage. While here remove PSR_C_bit.

MFC 263910, 263913, 263914, 263933, 263934, 263935, 263936, 263981, 263982,

2014-05-17T19:37:04Z

Add more flags for the fpexc register from the ARM1176JZF-S Manual Initialise fpscr to a sane value when we create the pcb. This sets NaNs to be the default NaN and for denormalised numbers to be flushed to zero. VFP fixes/cleanups for ARM11: * Save the required VFP registers on context switch. If the exception bit is set we need to save and restore the FPINST register, and if the fp2v bit is also set we need to save and restore FPINST2. * Move saving and restoring the floating point control registers to C. * Clear the fpexc exception and fp2v flags on a floating-point exception. * Signal a SIGFPE if the fpexc exception flag is set on an undefined instruction. This is how the ARM core signals to software there is a floating-point exception. Add Cortex-A15 cpu id revisions. Exynos/Arndale... - Merge SoC-common parts - Enable iicbus device - Directly call kmem_alloc_contig to allocate framebuffer memory and pass VM_MEMATTR_UNCACHEABLE (no-cache, no-buffer). This fixes screen refreshing problem when data is updated too slowly. - Add support for keyboard used in Samsung Chromebook (ARM machine) Support covers device drivers for: - Interrupt Combiner - gpio/pad, External Interrupts Controller (pad) - I2C Interface - Chrome Embedded Controller - Chrome Keyboard - Use new gpio dev class in EHCI driver - Expand device tree information - Release i2c bus on detach.

MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,

2014-05-17T13:53:38Z

263030, 263033, 263034, 263056, 263057, Remove all the redundant external declarations of exception vectors and runtime setting of the pointers that's scattered around various places. Remove all traces of support for ARM chips prior to the arm9 series. Make the default exception handler vectors point to where I thought they were already pointing: the default handlers (not a panic that says there is no default handler). Eliminate irq_dispatch.S. Move the data items it contained into arm/intr.c and the functionality it provided into arm/exception.S. Move the exception vector table (so-called "page0" data) into exception.S and eliminate vectors.S. Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code using it doesn't have to have an "AST_LOCALS" macro somewhere in the file. Arrange for arm fork_trampoline() to return to userland via the standard swi_exit code in exception.S instead of having its own inline expansion of the DO_AST and PULLFRAME macros. Now that the PUSHFRAME and PULLFRAME macros are used only in the swi entry/exit code, they don't need to be macros. Except that didn't work and the whole change was reverted. Remove some unnecessary indirection and jump right to the handler functions. Use panic rather than printf to "handle" an arm26 address exception (should never happen on arm32). Remove the unreferenced DATA() macro. Remove #include from files that don't need it.

MFC r261803, r261808, r261814, r261815, r261816, r261817, r261818, r261826,

2014-05-15T22:03:24Z

r261848, r261855 On armv6 and later, use the WriteNotRead bit of the fault status register to decide what protections are required by the faulting access. Use the right symbols for determining arm architecture. Include the necessary header file which has the new FAULT_WNR symbol defined in it. Allow the kernel to be loaded at any 1MiB address. This requirement is because we use the 1MiB section maps as they only need a single pagetable. Add function for configuring Vybrid PLL4 (Audio) clock frequency output. imx6 changes ... - Fix the definition of the SDHCI_STATE_DAT and SDHCI_STATE_CMD fields, and add SDHCI_RETUNE_REQUEST. None of these are actually used in the code yet. - Write translation code for the SDHCI_PRESENT_STATE register. Freescale moved some bits around in their version of the register, adjust things so that the sdhci code sees the standard layout. - Add standard non-removable and cd-gpios properties to the usdhc devices. That generates references to gpio devices, so uncomment them even though there isn't a gpio driver to do anything with them yet. - Add handling of standard "non-removable" property, and also some workaround code so that if card detect is wired to a gpio pin, for now we just treat it the same as non-removable (because there isn't a gpio driver yet). - Enable both sdcard slots, but not the sdio-based wifi that we don't yet have a driver for. - Remove a couple obsolete function declarations.

MFC r258359, r258742, r258845, r259936, r259640

2014-05-14T17:40:18Z

Apply access flags for managed and unmanaged pages properly on ARMv6/v7 Set the PGA_WRITEABLE flag when the protections indicate write access, not just when the current access is a write. Enable missing Access Flag for secondary cores on ARMv6/v7 Add identification and necessary type checks for Krait CPU cores.

MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281,

2014-05-14T16:32:27Z

r257282, r257332 Wait for DesignWare UART transfers completion before accessing line control Enable UART busy detection handling for Armada XP - based board Enable SATA interface on Armada XP Run mvs SATA driver on Armada XP instead of old mv_sata Retire arm_remap_nocache() and the data and constants associated with it. Remove hard-coded mappings related to Armada XP support Fix-up DTB for Armada XP registers' base according to the actual settings Change Armada XP kernel load address to the u-boot's end address Remove not working and deprecated PJ4Bv6 support Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU Add missing ARMv6 CPU functions to ARM Makefile

MFC r258779,r258780,r258787,r258822:

2014-02-04T03:36:42Z

Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result. Similar to the (1 << 31) case it is not defined to do (2 << 30). This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD.

Add identification for Cortex-A7 (R0) cores.

2013-08-01T10:06:19Z

Reviewed by: cognet@