src/sys/arm/include/cpu.h, branch releng/12.2

MFC r353165: align use of cp15_pmccntr_get with its availability

2019-10-30T16:41:57Z

MFC 340164,340168,340170: Add custom cpu_lock_delay() for x86.

2018-11-08T22:39:38Z

340164: Add a KPI for the delay while spinning on a spin lock. Replace a call to DELAY(1) with a new cpu_lock_delay() KPI. Currently cpu_lock_delay() is defined to DELAY(1) on all platforms. However, platforms with a DELAY() implementation that uses spin locks should implement a custom cpu_lock_delay() doesn't use locks. 340168: Add a delay_tsc() static function for when DELAY() uses the TSC. This uses slightly simpler logic than the existing code by using the full 64-bit counter and thus not having to worry about counter overflow. 340170: Add a custom implementation of cpu_lock_delay() for x86. Avoid using DELAY() since it can try to use spin locks on CPUs without a P-state invariant TSC. For cpu_lock_delay(), always use the TSC if it exists (even if it is not P-state invariant) to delay for a microsecond. If the TSC does not exist, read from I/O port 0x84 to delay instead. PR: 228768 Approved by: re (gjb)

Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't

2016-05-25T19:44:26Z

have ACLE support built in. The ACLE (ARM C Language Extensions) defines a set of standardized symbols which indicate the architecture version and features available. ACLE support is built in to modern compilers (both clang and gcc), but absent from gcc prior to 4.4. ARM (the company) provides the acle-compat.h header file to define the right symbols for older versions of gcc. Basically, acle-compat.h does for arm about the same thing cdefs.h does for freebsd: defines standardized macros that work no matter which compiler you use. If ARM hadn't provided this file we would have ended up with a big #ifdef __arm__ section in cdefs.h with our own compatibility shims. Remove #include from the zillion other places (an ever-growing list) that it appears. Since style(9) requires sys/types.h or sys/param.h early in the include list, and both of those lead to including cdefs.h, only a couple special cases still need to include acle-compat.h directly. Loves it: imp

ARM: Introduce new cpu-v4.h header and move all ARMv4 specific code

2016-02-05T09:46:24Z

from cpu-v6.h to it. Remove unneeded cpu-v6.h includes.

Now that the PMU implementation is independent of HWPMC

2015-11-09T17:57:32Z

as of r288992 use it to manage the CCNT. Use the CNNT for get_cyclecount() instead of binuptime() when device pmu is compiled in; if it fails to attach, fall back to the former method. Enable by default for the BeagleBoneBlack configuration. Optained from: Cambridge/L41 Sponsored by: DARPA/AFRL Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D3837

Move the inclusion of cpu-v6.h inside the #ifdef _KERNEL block, so that

2015-01-08T03:59:03Z

userland programs (which probably don't actually need machine/cpu.h) compile.

Add accessors for the ARM CP15 performance monitor registers. Also ensure

2015-01-08T01:28:46Z

that some #ifdef SMP code is also conditional on __ARM_ARCH >= 7; we don't support SMP on armv6, but some drivers and modules are compiled with it forced on via the compiler command line.

Different versions of the ARM processor use different registers.

2014-06-17T21:48:04Z

Fix the code used on a Raspberry Pi. Reviewed by: markm@

Give suitably-endowed ARMs a register similar to the x86 TSC register.

2014-05-14T19:11:15Z

Here, "suitably endowed" means that the System Control Coprocessor (#15) has Performance Monitoring Registers, including a CCNT (Cycle Count) register. The CCNT register is used in a way similar to the TSC register in x86 processors by the get_cyclecount(9) function. The entropy-harvesting thread is a heavy user of this function, and will benefit from not having to call binuptime(9) instead. One problem with the CCNT register is that it is 32-bit only, so the upper 32-bits of the returned number are always 0. The entropy harvester does not care, but in case any one else does, follow-up work may include an interrup trap to increment an upper-32-bit counter on CCNT overflow. Another problem is that the CCNT register is not readable in user-mode code; in can be made readable by userland, but then it is also writable, and so is a good chunk of the PMU system. For that reason, the CCNT is not enabled for user-mode access in this commit. Like the x86, there is one CCNT per core, so they don't all run in perfect sync. Reviewed by: ian@ (an earlier version) Tested by: ian@ (same earlier version) Committed from: WANDBOARD-QUAD

Pass the pagetable used from locore.S to initarm to allow it to map data

2014-02-09T15:54:31Z

in as required.