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<title>src/sys/dev/ahci, branch release/12.3.0</title>
<subtitle>FreeBSD source tree</subtitle>
<id>https://cgit-dev.freebsd.org/src/atom?h=release%2F12.3.0</id>
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<updated>2021-04-14T01:03:12Z</updated>
<entry>
<title>Add IDs for ASMedia ASM116x PCIe 3.0 AHCI controllers.</title>
<updated>2021-04-14T01:03:12Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2021-04-07T19:03:36Z</published>
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<id>urn:sha1:6c4ea5bb59ac83aed1bb9ea75ef230d34cba2c24</id>
<content type='text'>
MFC after:	1 week

(cherry picked from commit 5a8d32b53b919d82d6a3aa9f155bd2a00fb51dc2)
</content>
</entry>
<entry>
<title>Add Intel Gemini Lake AHCI ID.</title>
<updated>2021-01-22T16:43:45Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2021-01-15T14:53:35Z</published>
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<id>urn:sha1:bec67897b0c501f6bc32a6f5072087e11fe5622a</id>
<content type='text'>
Submitted by:	Dmitry Luhtionov &lt;dmitryluhtionov@gmail.com&gt;

(cherry picked from commit 006e2b2b8285842216ceb914a4cf828c89c2d7f7)
</content>
</entry>
<entry>
<title>MFC r366922, r367915, r367916:</title>
<updated>2020-11-24T00:30:47Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-11-24T00:30:47Z</published>
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<id>urn:sha1:ca128d1881eeb8fc9b322c5754dbd20452bbd6bc</id>
<content type='text'>
Pass lower 3 bits of sector_count for FPDMA commands.

When this code was written those bits were N/A, but now the lowest bit
is Rebuild Assist Recovery Control (RARC).
</content>
</entry>
<entry>
<title>MFC r367261: Add icc (Isochronous Command Completion) ccb_ataio field.</title>
<updated>2020-11-09T01:14:22Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-11-09T01:14:22Z</published>
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<id>urn:sha1:c86acfda01778b27c5651618fcde6c9ef888391b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>MFC r363955: Add Intel Apollo Lake AHCI ID.</title>
<updated>2020-08-13T00:40:40Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-08-13T00:40:40Z</published>
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<id>urn:sha1:604fbe3b17411aba882b3ff461d5b70eeac91411</id>
<content type='text'>
</content>
</entry>
<entry>
<title>MFC r361816: Limit AHCI to only one MSI if more is not needed.</title>
<updated>2020-06-19T00:43:44Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-06-19T00:43:44Z</published>
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<id>urn:sha1:5f094a129f8039439c6ac92ee5b78d196f192880</id>
<content type='text'>
My AMD Ryzen system has 4 AHCI controllers, each supporting 16 MSI vectors.
Since two of the controllers have only one SATA port, limit to single MSI
saves system 30 interrupt vectors for free.

It may be possible to also limit number of MSI vectors to 4 and 8 for the
other two controllers, but according to the AHCI specification after that
controllers may revert to only one vector, that would be a bigger loss to
risk.
</content>
</entry>
<entry>
<title>MFC r347440, r347929-r347930, r349588</title>
<updated>2020-06-16T20:35:01Z</updated>
<author>
<name>Emmanuel Vadot</name>
<email>manu@FreeBSD.org</email>
</author>
<published>2020-06-16T20:35:01Z</published>
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<id>urn:sha1:a5bd46772016c1ec8be88487bd0e3260b6278f33</id>
<content type='text'>
r347440:
ahci: Check if bus is cache-coherent

We do this for FDT systems but not for ACPI ones.
Check the presence of the _CCA attribute.

Sponsored by: Ampere Computing, LLC
Reviewed by:	andrew
Differential Revision:	https://reviews.freebsd.org/D20144

r347929:
pci: ecam: Do not warn on mismatch of bus_end

We cannot know the bus end number before parsing the MCFG table
so don't set the bus_end before that. If the MCFG table doesn't
exist we will set the configuration base address based on the _CBA
value and set the bus_end to the maximal number allowed by PCI.

Sponsored by: Ampere Computing, LLC

Differential Revision:	https://reviews.freebsd.org/D20213

r347930:
pci: ecam: Correctly parse memory and IO region

When activating a resource do not compare the resource id to the adress.
Treat IO region as MEMORY region too.

Submitted by:	Tuan Phan &lt;tphan@amperecomputing.com&gt; (Original Version)
Sponsored by:	Ampere Computing, LLC
Differential Revision:	https://reviews.freebsd.org/D20214

r349588:
arm64: efi: Map memory IO region as device

Reviewed by:	andrew
Sponsored by:	Ampere Computing, LLC
</content>
</entry>
<entry>
<title>MFC r359499: Add ID for JMicron JMB582/JMB585 AHCI controller.</title>
<updated>2020-04-15T13:59:51Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-04-15T13:59:51Z</published>
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<id>urn:sha1:928341e8cff36b8f829b5433271fb014dd10667c</id>
<content type='text'>
JMB582 has 2 6Gbps SATA ports and PCIe 3.0 x1.
JMB585 has 5 6Gbps SATA ports and PCIe 3.0 x2.

Both chips support AHCI v1.31, Port Multiplier with FBS and 8 MSI vectors.
</content>
</entry>
<entry>
<title>MFC r359499: Add ID for JMicron JMB582/JMB585 AHCI controller.</title>
<updated>2020-04-15T13:58:42Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-04-15T13:58:42Z</published>
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<id>urn:sha1:d128823127ef133f3bd080d574ce49d55a9e6acf</id>
<content type='text'>
JMB582 has 2 6Gbps SATA ports and PCIe 3.0 x1.
JMB585 has 5 6Gbps SATA ports and PCIe 3.0 x2.

Both chips support AHCI v1.31, Port Multiplier with FBS and 8 MSI vectors.
</content>
</entry>
<entry>
<title>MFC r357919: Add Hygon PCI ID and description for AHCI SATA controller.</title>
<updated>2020-02-21T04:28:42Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-02-21T04:28:42Z</published>
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</content>
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