src/sys/dev/ahci, branch releng/12.2

MFC r363955: Add Intel Apollo Lake AHCI ID.

2020-08-13T00:40:40Z

MFC r361816: Limit AHCI to only one MSI if more is not needed.

2020-06-19T00:43:44Z

My AMD Ryzen system has 4 AHCI controllers, each supporting 16 MSI vectors. Since two of the controllers have only one SATA port, limit to single MSI saves system 30 interrupt vectors for free. It may be possible to also limit number of MSI vectors to 4 and 8 for the other two controllers, but according to the AHCI specification after that controllers may revert to only one vector, that would be a bigger loss to risk.

MFC r347440, r347929-r347930, r349588

2020-06-16T20:35:01Z

r347440: ahci: Check if bus is cache-coherent We do this for FDT systems but not for ACPI ones. Check the presence of the _CCA attribute. Sponsored by: Ampere Computing, LLC Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D20144 r347929: pci: ecam: Do not warn on mismatch of bus_end We cannot know the bus end number before parsing the MCFG table so don't set the bus_end before that. If the MCFG table doesn't exist we will set the configuration base address based on the _CBA value and set the bus_end to the maximal number allowed by PCI. Sponsored by: Ampere Computing, LLC Differential Revision: https://reviews.freebsd.org/D20213 r347930: pci: ecam: Correctly parse memory and IO region When activating a resource do not compare the resource id to the adress. Treat IO region as MEMORY region too. Submitted by: Tuan Phan (Original Version) Sponsored by: Ampere Computing, LLC Differential Revision: https://reviews.freebsd.org/D20214 r349588: arm64: efi: Map memory IO region as device Reviewed by: andrew Sponsored by: Ampere Computing, LLC

MFC r359499: Add ID for JMicron JMB582/JMB585 AHCI controller.

2020-04-15T13:59:51Z

JMB582 has 2 6Gbps SATA ports and PCIe 3.0 x1. JMB585 has 5 6Gbps SATA ports and PCIe 3.0 x2. Both chips support AHCI v1.31, Port Multiplier with FBS and 8 MSI vectors.

MFC r359499: Add ID for JMicron JMB582/JMB585 AHCI controller.

2020-04-15T13:58:42Z

JMB582 has 2 6Gbps SATA ports and PCIe 3.0 x1. JMB585 has 5 6Gbps SATA ports and PCIe 3.0 x2. Both chips support AHCI v1.31, Port Multiplier with FBS and 8 MSI vectors.

MFC r357919: Add Hygon PCI ID and description for AHCI SATA controller.

2020-02-21T04:28:42Z

MFC r355113: Add some IDs of Intel Wildcat Point-LP.

2019-12-03T14:47:50Z

MFC r351589: Fix AHCI Enclosure Management, broken by r351356.

2019-11-20T23:49:47Z

ivars value of -1 was used to distinguish EM device, and r351356 left some wrong checks for it. Give EM device separate flag there instead.

MFC r351356:

2019-09-05T23:02:08Z

Create a AHCI attachment for nvme.

MFC r349321: Improve AHCI Enclosure Management and SES interoperation.

2019-07-08T10:21:38Z

Since SES specs do not define mechanism to map enclosure slots to SATA disks, AHCI EM code I written many years ago appeared quite useless, that always bugged me. I was thinking whether it was a good idea, but if LSI HBAs do that, why I shouldn't? This change introduces simple non-standard mechanism for the mapping into both AHCI EM and SES code, that makes AHCI EM on capable controllers (most of Intel's) a first-class SES citizen, allowing it to report disk physical path to GEOM, show devices inserted into each enclosure slot in `sesutil map` and `getencstat`, control locate and fault LEDs for specific devices with `sesutil locate adaX on` and `sesutil fault adaX on`, etc. I've successfully tested this on Supermicro X10DRH-i motherboard connected with sideband cable of its S-SATA Mini-SAS connector to SAS815TQ backplane. It can indicate with LEDs Locate, Fault and Rebuild/Remap SES statuses for each disk identical to real SES of Supermicro SAS2 backplanes. Relnotes: yes