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<title>src/sys/dev/hwpmc, branch releng/12.2</title>
<subtitle>FreeBSD source tree</subtitle>
<id>https://cgit-dev.freebsd.org/src/atom?h=releng%2F12.2</id>
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<updated>2020-08-19T13:07:04Z</updated>
<entry>
<title>MFC r359438 and r359477:</title>
<updated>2020-08-19T13:07:04Z</updated>
<author>
<name>Hans Petter Selasky</name>
<email>hselasky@FreeBSD.org</email>
</author>
<published>2020-08-19T13:07:04Z</published>
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<id>urn:sha1:898a95874a5bde996e5e3455d62aa3e5f927b7c1</id>
<content type='text'>
Remove the "config" taskqgroup and its KPIs.

Equivalent functionality is already provided by taskqueue(9), just use
that instead.

Interfaces may be detached from a taskqueue_thread task, for example by
prison_complete(), so after r359438, when draining the queue we may end
up deadlocking.
</content>
</entry>
<entry>
<title>MFC r363630:</title>
<updated>2020-08-04T12:04:47Z</updated>
<author>
<name>Ryan Moeller</name>
<email>freqlabs@FreeBSD.org</email>
</author>
<published>2020-08-04T12:04:47Z</published>
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<id>urn:sha1:83fbe66ef7255fa4d1223ea0bd82fc54e1e8122d</id>
<content type='text'>
libpmc: Use known pmc_cpuid buffer size

Use the existing PMC_CPUID_LEN to size pmc_cpuid in the kernel and various
buffers for reading it in libpmc.  This avoids some extra syscalls and
malloc/frees.

While in here, use strlcpy to copy a user-provided cpuid string instead of
memcpy, to make sure we terminate the buffer.

Reviewed by:    mav
Sponsored by:   iXsystems, Inc.
Differential Revision:  https://reviews.freebsd.org/D25679
</content>
</entry>
<entry>
<title>MFC r363206:</title>
<updated>2020-07-28T02:53:44Z</updated>
<author>
<name>Ryan Moeller</name>
<email>freqlabs@FreeBSD.org</email>
</author>
<published>2020-07-28T02:53:44Z</published>
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<id>urn:sha1:898b2ca1291b8959e9959ca861fe30f457594353</id>
<content type='text'>
hwpmc: Always set pmc_cpuid to something

pmc_cpuid was uninitialized for most AMD processor families.  We can still
populate this string for unimplemented families.

Also added a CPUID_TO_STEPPING macro and converted existing code to use it.

Reviewed by:    mav
Sponsored by:   iXsystems, Inc.
Differential Revision:  https://reviews.freebsd.org/D25673
</content>
</entry>
<entry>
<title>MFC r363144, r363188: Add stepping to the kern.hwpmc.cpuid string on x86.</title>
<updated>2020-07-20T13:50:10Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-07-20T13:50:10Z</published>
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<id>urn:sha1:c4896d816f6081b194d261e03f5beade4a3730b2</id>
<content type='text'>
It follows the equivalent Linux change to be able to differentiate
skylakex and cascadelakex, sharing the same model but not stepping.
</content>
</entry>
<entry>
<title>MFC r360266: Add family 0x5F (Denverton) to PMC_CPU_INTEL_ATOM_GOLDMONT.</title>
<updated>2020-05-01T00:40:18Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-05-01T00:40:18Z</published>
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<id>urn:sha1:2b136caaf356a9aaa9fdafa0b81a4f7cfba0730d</id>
<content type='text'>
According to the 325462-071US document, they should be the same.
</content>
</entry>
<entry>
<title>MFC r359667 (by mw): Add hwpmc support for Intel Atom Goldmont microarchitecture</title>
<updated>2020-04-24T15:02:05Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-04-24T15:02:05Z</published>
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<id>urn:sha1:5bddeab3424b5190e40894a76b50fc650728496a</id>
<content type='text'>
Recognize new micro-architecture in hwpmc_intel driver. Based on Intel
document 325462-071US. Tested with tools/test/hwpmc/pmctest.py
on Atom E3930 SoC.
</content>
</entry>
<entry>
<title>MFC r354470 (by gallatin): hwpmc : fix AMD perf counter MSR access</title>
<updated>2020-04-24T14:47:55Z</updated>
<author>
<name>Alexander Motin</name>
<email>mav@FreeBSD.org</email>
</author>
<published>2020-04-24T14:47:55Z</published>
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<id>urn:sha1:84e82cf5f5e2559ab73b47a6bba291eb4c673517</id>
<content type='text'>
- amd_intr() does not account for the offset (0x200) in the counter
MSR address and ends up accessing invalid regions while reading
counter value after the 4th counter (0xC001000[8,9,..]) and
erroneously updates the counter values for counters [1-4].

- amd_intr() should only check core pmcs for interrupts since
 other types of pmcs (L3,DF) cannot generate interrupts.

- fix pmc NMI's being ignored due to NMI latency on newer AMD processors

Note that this fixes a kernel panic due to GPFs accessing MSRs on
higher core count AMD cpus (seen on both Rome 7502P, and
Threadripper 2990WX 32-core CPUs)
</content>
</entry>
<entry>
<title>MFC r359437:</title>
<updated>2020-04-06T14:58:24Z</updated>
<author>
<name>Mark Johnston</name>
<email>markj@FreeBSD.org</email>
</author>
<published>2020-04-06T14:58:24Z</published>
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<id>urn:sha1:3bc47a0786de1cb45a75a3b5e5b09fd8e5831fe4</id>
<content type='text'>
Fix accounting of hwpmc's thread descriptor freelist.
</content>
</entry>
<entry>
<title>Fix sample check in hwpmc</title>
<updated>2020-03-12T20:59:00Z</updated>
<author>
<name>Matt Macy</name>
<email>mmacy@FreeBSD.org</email>
</author>
<published>2020-03-12T20:59:00Z</published>
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<id>urn:sha1:5fc79c36bfb40bbf7263a186838ce0a898454c91</id>
<content type='text'>
Don't drop samples with callchain pending

Tested by: mjg@

MFC of r353483
</content>
</entry>
<entry>
<title>MFC r357670:</title>
<updated>2020-02-14T13:26:45Z</updated>
<author>
<name>Konstantin Belousov</name>
<email>kib@FreeBSD.org</email>
</author>
<published>2020-02-14T13:26:45Z</published>
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<id>urn:sha1:d4081c82eda3f34ff8ca91b0ff14b0acbadf33eb</id>
<content type='text'>
pmc: Add Hygon Dhyana support.
</content>
</entry>
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