FreeBSD source tree https://cgit-dev.freebsd.org/src/atom?h=release%2F10.1.0 2014-05-14T16:32:27Z 2014-05-14T16:32:27Z Ian Lepore ian@FreeBSD.org 2014-05-14T16:32:27Z urn:sha1:a464a7e4042cdb30ffb99d34a2f209c7989629b3 r257282, r257332 Wait for DesignWare UART transfers completion before accessing line control Enable UART busy detection handling for Armada XP - based board Enable SATA interface on Armada XP Run mvs SATA driver on Armada XP instead of old mv_sata Retire arm_remap_nocache() and the data and constants associated with it. Remove hard-coded mappings related to Armada XP support Fix-up DTB for Armada XP registers' base according to the actual settings Change Armada XP kernel load address to the u-boot's end address Remove not working and deprecated PJ4Bv6 support Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU Add missing ARMv6 CPU functions to ARM Makefile 2013-03-01T01:42:31Z Ganbold Tsagaankhuu ganbold@FreeBSD.org 2013-03-01T01:42:31Z urn:sha1:ac4adddf040f1010f08e284f71e1bb2f92b4d43a A10 uart is derived from Synopsys DesignWare uart and requires to read Uart Status Register when IIR_BUSY has detected. Also this change includes FDT check, where it checks device specific properties defined in dts and sets the busy_detect variable. broken_txfifo is also needed to be set in order to make it work for A10 uart case. Reviewed by: marcel@ Approved by: gonzo@ 2010-01-11T04:13:06Z Warner Losh imp@FreeBSD.org 2010-01-11T04:13:06Z urn:sha1:18f323353c3aa8b0add9ea0e1b434f9229621394 Defintions for cavium uart (do they belong here?) 2009-06-21T19:17:22Z Sam Leffler sam@FreeBSD.org 2009-06-21T19:17:22Z urn:sha1:04ddfac3390b5b7fc9d57edf2ad2b7fb5c3e692c 2008-09-07T04:35:04Z Yoshihiro Takahashi nyan@FreeBSD.org 2008-09-07T04:35:04Z urn:sha1:ebd2b744768169ad575024ce4c1033833a220c6d - Move i8255 related defines into a separate file. 2008-08-29T12:25:58Z Yoshihiro Takahashi nyan@FreeBSD.org 2008-08-29T12:25:58Z urn:sha1:5798cf97e910447c5dbee9d70706a276b163b5a4 2008-03-03T18:20:17Z Rafal Jaworowski raj@FreeBSD.org 2008-03-03T18:20:17Z urn:sha1:e1ef781113fba635a7fa4a979607261385971992 The QUICC engine is found on various Freescale parts including MPC85xx, and provides multiple generic time-division serial channel resources, which are in turn muxed/demuxed by the Serial Communications Controller (SCC). Along with core QUICC/SCC functionality a uart(4)-compliant device driver is provided which allows for serial ports over QUICC/SCC. Approved by: cognet (mentor) Obtained from: Juniper MFp4: e500 2006-09-08T21:46:01Z Jung-uk Kim jkim@FreeBSD.org 2006-09-08T21:46:01Z urn:sha1:0da90eb878fdcd8c766c609afbf5f53cc56858e7 2006-07-06T21:12:18Z Jung-uk Kim jkim@FreeBSD.org 2006-07-06T21:12:18Z urn:sha1:50d99d1a52d3bc87a4897cc87db950960060e35e Use it to reset controller and to select data rate. According to Intel 80277AA datasheet, software reset behaves the same as DOR reset except that it is self clearing. National Semiconductor PC8477B datasheet says the same. As a side effect, we no longer use Configuration Control Register (CCR) at 0x3f7 for these controllers, which is often missing in modern hardware. 2006-05-23T00:41:12Z Benno Rice benno@FreeBSD.org 2006-05-23T00:41:12Z urn:sha1:58957d87173648541b214726c95eb4614ba31848 - Rename REG_DL to REG_DLL and REG_DLH. - Always treat DLL and DLH as two separate 8-bit registers instead of one 16-bit register. Additionally, remove the probe for the high 4 bits of IER being 0 and don't assume we can always read/write 0 to/from those bits. These changes allow uart(4) to drive the UARTs on the Intel XScale PXA255. Reviewed by: marcel