FreeBSD source tree https://cgit-dev.freebsd.org/src/atom?h=releng%2F7.3 2010-01-08T10:14:27Z 2010-01-08T10:14:27Z Gavin Atkinson gavin@FreeBSD.org 2010-01-08T10:14:27Z urn:sha1:8ebb1029bb320954b81b5bde58ef5cf51a9d1767 Set the locally-assigned bit in the randomly generated Ethernet address if we end up having to generate one. PR: kern/133239 Discussed with: yongari Approved by: ed (mentor, implicit) 2009-11-29T18:54:21Z Pyun YongHyeon yongari@FreeBSD.org 2009-11-29T18:54:21Z urn:sha1:dcba6ae0a450db491794e94a28d933c85af211ae Remove unnecessary device reinitialization. 2009-01-12T03:26:52Z Pyun YongHyeon yongari@FreeBSD.org 2009-01-12T03:26:52Z urn:sha1:a6d8fd35bfef0c59d1ed4574c4d34910c3e452e9 Add HW MAC counter support for newer JMC250/JMC260 revisions. 2009-01-12T02:51:29Z Pyun YongHyeon yongari@FreeBSD.org 2009-01-12T02:51:29Z urn:sha1:681c67176fa9fcd7b508fb076c80e267eb73183d Add support for newer JMC250/JMC260 revisions. o Chip full mask revision 2 or later controllers have to set correct Tx MAC and Tx offload clock depending on negotiated link speed. o JMC260 chip full mask revision 2 has a silicon bug that can't handle 64bit DMA addressing. Add workaround to the bug by limiting DMA address space to be within 32bit. o Valid FIFO space of receive control and status register was changed on chip full mask revision 2 or later controllers. For these controllers, use default 16QW as it's supposed to be the safest value for maximum PCIe compatibility. JMicron confirmed performance will not be reduced even if the FIFO space is set to 16QW. o When interface is put into suspend/shutdown state, remove Tx MAC and Tx offload clock to save more power. We don't need Tx clock at all in this state. o Added new register definition for chip full mask revision 2 or later controllers. 2008-10-19T06:38:34Z Pyun YongHyeon yongari@FreeBSD.org 2008-10-19T06:38:34Z urn:sha1:66c3173529eed7a866d6eb0184e078d0f48fccac Read PCI device id instead of PCI revision id. Also checks the read device id is JMC260 family. Previously it just verified the deivce is JMC260 Rev A0. This will make it easy for newer JMC2xx support. Pointed out by: bouyer at NetBSD MFC r183859: Make sure to read the last byte of EEPROM descriptor. Previously the last byte of the ethernet address was not read which in turn resulted in getting 5 out of the 6 bytes of ethernet address and always returned ENOENT. I did not notice the bug on FPGA version because of additional configuration data in EEPROM. Pointed out by: bouyer at NetBSD Approved by: re (gnn) 2008-09-26T00:52:51Z Pyun YongHyeon yongari@FreeBSD.org 2008-09-26T00:52:51Z urn:sha1:1cb1a10c9e5f9c991b666482f823ca18aa825193 Add workaround for occasional packet loss issue of JMC250 A2 when it runs on half-duplex media. While I'm here add register definition for GPREG1. ATM the GPREG1 register is only valid for JMC250 A1/A2. Submitted by: Ethan at JMicron Approved by: re (kensmith) 2008-09-17T03:51:32Z Pyun YongHyeon yongari@FreeBSD.org 2008-09-17T03:51:32Z urn:sha1:5a710461e8c1d098013d568d9d3d3183ca4aa24b r182887: Fix typo which resulted in invalid configuration for JMC260. r182888: Add workaround for CRC errors seen at 100Mbps on JMC250 A2. While here update chip revision number of JMC250/JMC260 from the latest datasheet. Approved by: re (kensmith) 2008-08-04T01:13:53Z Pyun YongHyeon yongari@FreeBSD.org 2008-08-04T01:13:53Z urn:sha1:84c7f2c1c3892846d4bdbd82f3f0704628bb8ab0 conditional compilation directive. 2008-07-31T01:13:19Z Pyun YongHyeon yongari@FreeBSD.org 2008-07-31T01:13:19Z urn:sha1:208762a771f68b14cacefdfd7bfc18e9339b3ee9 Fix buffer discard index. While I'm here dicard all buffers if errored frame is part of multi-segmented frames. 2008-07-24T00:30:35Z Pyun YongHyeon yongari@FreeBSD.org 2008-07-24T00:30:35Z urn:sha1:2b14c882c44a8b682b81ce0c236e25355085e4f0 Correct 1000Mbps link handling logic for JMC250. This should make jme(4) run on 1000Mbps link.