src/sys/dev/mmc, branch releng/12.4

MFC r360007:

2020-06-19T18:14:45Z

Revert r359965 This cause board without a cd-gpio to not schedule a card detection.

MFC r360008-r360009, r360011

2020-06-19T18:10:39Z

r360008: mmc_fdt_helpers: Always init the timout We use the taskqueue to schedule card detection so always init it. This is a proper solution instead of r359965. MFH: r359924 r360009: mmc_fdt_helpers: Drain the cd pin taskqueue in mmc_fdt_gpio_teardown We have no use for it now. r360011: arm: allwinner: aw_mmc: Make it possible to unload the module While here, add a makefile in sys/modules/allwinner so it is built. Also add the PNP info so devmatch will load this module automatically.

MFC r359924-r359925, r359927, r359932, r359965

2020-06-19T18:05:14Z

r359924: Those functions are here to help fdt mmc controller drivers to parse the dts to find the supported speeds and the regulators. Not all DTS have every settings properly defined so host controller will still have to add some caps themselves. It also add a mmc_fdt_gpio_setup function which will read the cd-gpios property and register it as the CD pin. If the pin support interrupts one will be registered and the cd_helper function will be called. If the pin doesn't support interrupts the internal taskqueue will poll for change and call the same cd_helper function. mmc_fdt_gpio_setup will also parse the wp-gpio property and MMC drivers can know the write-protect pin value by calling the mmc_fdt_gpio_get_readonly function. Differential Revision: https://reviews.freebsd.org/D23267 r359925: arm: allwinner: aw_mmc: Use the mmc_fdt_helper The fdt properties are now parsed via the help of mmc_fdt_helper functions. This also adds card detection. Note that on some boards (like the Pine64) card detection is broken due to a missing resistor on the cd pin. Differential Revision: https://reviews.freebsd.org/D23268 r359927: arm: dwmmc: Use mmc_fdt_helpers Use the mmc_fdt_parse function instead of parsing everything in the driver. r359932: files: Add mmc_fdt_helpers for mmccam enabled config X-MFC-With: r359924 r359965: mmc_fdt_helpers: Do not schedule a card detection is there is no cd gpio If the fdt node doesn't have a cd-gpios properties or if the node is set as non-removable we do not init the card detection timeout task as it is useless so don't schedule it too. X-MFC-With: r359924

MFC r358450, r358635

2020-06-19T17:52:48Z

r358450: mmc: dwmmc: Fix off by one error The IVAR_MAX_DATA is supposed to have the number of descriptor X the mmc block size and desc_count contain all this information + 1. Reported by: phk r358635: dwmmc: Rework the DMA engine Each segment can be up to 4096 bytes in chain structure according to the RK3399 TRM Part 2. Set the buffers in full ring where the last one point to the first one. Correctly reports the MMC_IVAR_MAX_DATA. Use CACHE_LINE_SIZE for bus_dma alignment.

MFC r349584, r349728, r349731, r350440, r350443, r351185, r353493, r353575, r355625, r355627, r355629, r356813

2020-06-18T21:44:49Z

r349584: Since r349571 we need all the accessor to be present for set or get otherwise we panic. dwmmc don't handle VCCQ (voltage for the IO line of the SD/eMMC) or TIMING. Add the needed accessor in the {read,write}_ivar functions. Reviewed by: imp (previous version) r349728 by imp: Implement missing MMCBR ivars All MMCBR bridges have to implement all the MMCBR variables. This implements them for everybody that currently doesn't. A common routine for this should be written. r349731 by imp: Fix cut-and-pasto that slipped through my testing. r350440 by br: Add support for the SD/MMC controller found in Terasic DE10-Pro (an Intel Stratix 10 GX/SX FPGA Development Kit). Set the bus speed manually due to lack of clock management support. Sponsored by: DARPA, AFRL r350443 by br: Fix MMCCAM kernel build. Sponsored by: DARPA, AFRL r351185 by mmel: Enhance support of extres in dwmmc driver. Handle all clocks, regulators and resets defined by dwmmc bindings. r353493 by br: Fix the driver attachment in cases when the external resource devices (resets, regulators, clocks) are not available. Rely on a system initialization done by a bootloader in that cases. This fixes operation on Terasic DE10-Pro (an Intel Stratix 10 development kit). Sponsored by: DARPA, AFRL r353575 by br: Fix dwmmc(4) driver attachment when ext_resources are not present. Ignore only ENOENT (no DTS properties found) and ENODEV (driver not present) non-zero return values from ext_resources. Reviewed by: manu Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D22043 r355625: dwmmc: Add a detach method This method will disable the regulators, clocks and assert the reset of the module. It will also detach it's children (the mmc device) and release it's resources. While here enable the regulators on attach as we need them to power up the sdcard or emmc. r355627: dwmmc: Handle the card detect interrupt The driver used to always add the mmc device as it's child even it no card was detected. Add a function that will detect if the card is present or not and that will attach/detach the mmc device. The function is either call on attach (as we won't have the interrupt fired) or from two taskqueues. The first taskqueue will directly call the function when the sdcard was present and is now removed and the other one will delay a bit the attach when we didn't had a card and now have one. This is mostly based on comments from the sdhci driver where it describe a situation when the CD pin is detected before the others pins are connected. r355629: dwmmc: Use device_delete_children Instead of first detaching the children(s) and then delete them, use the device_delete_children function that does all of that. Suggested by: ian r356813: dwmmc: Remove max_hz from the softc We never use it so directly set the value to the mmc host structure.

MFC r353354:

2019-11-28T18:18:10Z

dwmmc: Reset the dma controller at attach If the bootloader enabled DMA we need to fully reset the DMA controller otherwise we might have some stale data in it that provoke weird behavior.

MFC r350231: Correct spelling, partion -> partition.

2019-08-11T22:32:52Z

MFC r341381-r341383, r341385, r343950, r344527, r344576-r344580, r344585, r344589-r344590, r344623, r344626-r344627

2019-08-07T18:26:32Z

r341381: arm64: rockchip: Add RK3399_CLK_PLL PLLs on the RK3399 are different than the ones on the RK3328. Add a new type and some dedicated recalc and set_freq functions. Rename the RK3328 dedicated rk_clk_pll function with rk3328_ prefix. r341382: arm64/rockchip: add RK3399 support Add CRU (Clock and Reset Unit) driver for RK3399. Add support in rk_pinctrl driver. Submitted by: Greg V (Original version) Differential Revision: https://reviews.freebsd.org/D16732 r341383: arm64: rockchip: rk_i2c: Use correct clock While here add RK3399 support and call clk_set_assigned to set the correct clock set in the DTS. r341385: arm64: rockchip: rk805: Add basic support for RK808 PMIC RK808 PMIC is the companion chip for RK3399 SoC. Add basic regulator support in RK805 since they are similar. r343950: arm64: Fix compile when removing SOC_ROCKCHIP_* options Make every rockchip file depend on the multiple soc_rockchip options While here make rk_i2c and rk_gpio depend on their device options. Reported by: sbruno r344527: arm64: rockchip: clk: Set the write mask when setting the clock mux RockChip clocks have a write mask in the upper 16bits of the mux register which wasn't set in the set_mux function. Also the wrong parent was tested instead of the real current one, when switch parent, test with the current one before. Pointy Hat: manu r344576: arm64: rockchip: clk: rk_clk_composite: Properly use the mask bits RockChip clocks register have a write mask in the upper 16 bits, if a 1 is present the corresponding bit in the lower 16 ones is set. Use this instead of always setting the mask to 0xFFFF0000. This avoids a read of the register. While here add some debug printf useful for debuging clock problems r344577: arm64: rockchip: clk: ARM CLK improvement RockChip clocks register have a write mask in the upper 16 bits, if a 1 is present the corresponding bit in the lower 16 ones is set. Use this instead of always setting the mask to 0xFFFF0000. This avoids a read of the register. While here set the parent after changing its freqeuncy, this reduce the time between changing the parent and changing the divider for the arm clock. r344578: arm64: rockchip: rk3328_pll: Multiple improvement RockChip clocks register have a write mask in the upper 16 bits, if a 1 is present the corresponding bit in the lower 16 ones is set. Use this instead of always setting the mask to 0xFFFF0000. This avoids a read of the register. While here, when switching PLL frequency, first switch it to slow mode. When set to slow mode the PLL clock will be the external oscillator. Changing the PLL parameters while its output is used can cause hang (sometimes). r344579: arm64: rockchip: rk805: Add LDO regulators Add the 3 LDO regulator found in the RK805 Power Management IC. r344580: arm64: rockchip: rk805: Map the regulator No map function was provided before so every regulator lookup resolved the regulator with id 1, as it uses the default mapper, which is wrong. Correctly map the regulators. While here remove some debug printfs and make them disable by default. r344585: arm64: rockchip: rk_pinctrl: Fix two banks in RK3328 The last two banks don't have 3 bits for the pin function but only 2. This fixes eMMC on the Rock64. r344589: arm64: rockchip: rk3399_pll: Switch to slow mode when changing the freq Like r344578 but for RK3399. This solve some hangs when switching between frequency. r344590: arm64: rockchip: rk3399_pll: Fix copy paste RK3399 PLLs don't have mode_reg, use the correct register. r344623: arm64: rockchip: clk_pll: Multiple improvement Remove the mode_val from the clock definition as it's a bit unreadable. Use mode_shift to represent which bit control the mode in the register. Simplify some case where we can avoid a register read before changing it. Set the PLL back to normal mode after the PLL have stabilized. Discussed with: mmel r344626: arm64: rockchip: rk3399_clk: Add sd clock definitions r344627: mmc: dwmmc: Match on "rockchip,rk3288-dw-mshc" compatible This is the common denominator for rockchip compatible from RK3288 to RK3399. The other compatible are generally present in the DTS but the controllers are the same.

MFC: r340495

2018-11-21T18:53:13Z

- Restore setting the clock for devices which support the default/legacy transfer mode only (lost with r321385). [1] - Similarly, don't try to set the power class on MMC devices that comply to version 4.0 of the system specification but are operated in default/ legacy transfer or 1-bit bus mode as no power class is specified for these cases. Trying to set a power class nevertheless resulted in an - albeit harmless - error message. PR: 231713 [1]

Avoid uninitialized read of ext_csd.

2018-09-06T21:24:14Z

Reported by: Coverity CID: 1395275 Approved by: re (gjb, kib)