src/sys/dev/sge, branch release/8.1.0

MFC r208806:

2010-06-08T19:26:22Z

Don't blindly set IFF_DRV_OACTIVE when sge_encap() fails. If there is no queued frame, IFF_DRV_OACTIVE would never be cleared. Submitted by: Nikolay Denev < ndenev <> gmail at com > Approved by: re (bz)

MFC r208512:

2010-05-31T22:03:56Z

sge_encap() can sometimes return an error with m_head set to NULL. Make sure not to requeue freed mbuf in sge_start_locked(). This should fix NULL pointer dereference panic. Reported by: Nikolay Denev gmail dot com> Submitted by: jhb Approved by: re (bz)

MFC r207852:

2010-05-17T17:12:35Z

SiS190 supports RX 10 bytes padding, CRC stripping as well as VLAN hardware tag insertion/stripping. Remove conditional code that disables these hardware features on SiS190. Also nuke RX fixup code which is no more required on strict-alignment architectures because SiS190 supports RX 10 bytes padding. Now all hardware features except jumbo frame and WOL are supported. Thanks to Masa Murayama who confirmed SiS190 also has the same hardware features of SiS191. I guess the only difference between SiS191 and SiS190 would be jumbo frame support. It will be implemented in near future.

MFC r207851:

2010-05-17T17:02:42Z

Implement TSO and TSO over VLAN. Increase number of allowed fragmentation of mbuf chain to 32 from 16 because TSO can send 64KB sized packet which in turn requires long list of mbuf chain. Due to lack of documentation, I'm not sure whether driver have to pull up ethernet/IP/TCP header with options to make controller work but driver have to parse TCP header to update pseudo TCP checksum anyway. The controller expects pseudo TCP checksum computed by upper stack and the checksum should follow the MS NDIS specification to make TSO work. Tested by: xclin cs dot nctu dot edu dot tw >

MFC r207628,207635:

2010-05-10T19:47:37Z

r207628: Enable multi-descriptor transmisstion for fragmented mbufs. There is no more need to defragment mbufs. After transmitting the multi-fragmented frame, the controller updates only the first descriptor of multi-descriptor transmission so it's driver's responsibility to clear OWN bits of remaining descriptor of multi-descriptor transmission. It seems the controller behaves much like jme(4) controllers in descriptor handling. r207635: Free entire mbuf chain instead of the first mbuf.

MFC r207545,207625:

2010-05-10T18:37:46Z

r207545: Fix wrong dma tag usage. Previously it used TX descriptor ring dma tag which should be TX mbuf dma tag. r207625: Remove clearing RxHashTable2 register. The register is reprogrammed in sge_rxfilter().

MFC r207380:

2010-05-06T18:34:15Z

Enable VLAN hardware tag insertion/stripping. Due to lack of SiS190 controller, I'm not sure whether this is also applicable to SiS190 so this feature is only activated on SiS191 controller. In theory, controller reinitialization is not needed when VLAN tag configuration is changed, but xclin said controller was not stable whenever toggling VLAN tag bit. To address that, sge(4) reinitialize controller for VLAN configuration which seems to work as expected. VLAN tag information for TX/RX descriptor and configure bit of RxMacControl register was found by xclin. Submitted by: xclin cs dot nctu dot edu dot tw > (initial version) Tested by: xclin cs dot nctu dot edu dot tw >

MFC r207379:

2010-05-06T18:30:46Z

Enable FCS stripping and padding 10 bytes bit of RX MAC control register. Due to lack of SiS190 controller, I'm not sure whether this is also applicable to SiS190 so this feature is only activated on SiS191 controller. The controller can pad 10 bytes before DMAing a received frame to RX buffer and received bytes include the padded bytes. This padding is very useful on strict-alignment architectures because driver does not have to copy received frame to align IP header on 4 bytes boundary. It also gives better RX performance on non-strict alignment architectures. Special thanks to xclin to give me valuable register information. Without his enthusiastic trial and errors this wouldn't be even possible. While I'm here tighten validity check of received frame. Controller clears RDS_CRCOK bit when it received bad CRC frames. xclin found that using loop back testing. Tested by: xclin cs dot nctu dot edu dot tw >

MFC r207375-207377.

2010-05-06T18:17:36Z

r207375: Preserve unknown bits of RX MAC control register when driver programs RX filter configuration. It seems RX MAC control register is one of key registers to get various offloading features as well as performance. Blindly clearing unrelated bits can result in unexpected results. Tested by: xclin cs dot nctu dot edu dot tw > r207376: Remove wrong link state chage. r207377: Explicitly marks SiS190 to differentiate it from SiS191.

MFC r207071:

2010-04-26T18:07:55Z

Intialize interrupt moderation control register. The magic value was chosen by lots of trial and errors. The chosen value shows good interrupt moderation without additional latency. Without this change, controller can generate more than 140k interrupts per second under high network load. Submitted by: xclin cs dot nctu dot edu dot tw >