<feed xmlns='http://www.w3.org/2005/Atom'>
<title>src/sys/dev/uart, branch releng/14.4</title>
<subtitle>FreeBSD source tree</subtitle>
<id>https://cgit-dev.freebsd.org/src/atom?h=releng%2F14.4</id>
<link rel='self' href='https://cgit-dev.freebsd.org/src/atom?h=releng%2F14.4'/>
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<updated>2026-02-12T21:24:22Z</updated>
<entry>
<title>uart: Add ns8250 ACPI entry for SPCR rev 2</title>
<updated>2026-02-12T21:24:22Z</updated>
<author>
<name>Colin Percival</name>
<email>cperciva@FreeBSD.org</email>
</author>
<published>2026-02-08T00:42:03Z</published>
<link rel='alternate' type='text/html' href='https://cgit-dev.freebsd.org/src/commit/?id=fce4758b7126adfa047e774241302a7e763b19c7'/>
<id>urn:sha1:fce4758b7126adfa047e774241302a7e763b19c7</id>
<content type='text'>
This is an MFC "in spirit" of a685a263b803; the code in this area has
been significantly restructured between 14.x and 15.x, but the general
concept of adding ACPI_DBG2_16550_WITH_GAS (aka 0x12) as a recognized
flavour of ns8250 UART which can be configured via SPCR remains.

Approved by:	re (cperciva)
Reviewed by:	imp
Tested by:	David Woodhouse
Sponsored by:	Amazon
Differential Revision:	https://reviews.freebsd.org/D55173

(cherry picked from commit 1dd5b197b72357dfe50d6da2c9cb5b34bf4bf64b)
</content>
</entry>
<entry>
<title>ns8250: use LSR_THRE instead of LSR_TEMT for checking tx flush</title>
<updated>2025-06-27T07:37:55Z</updated>
<author>
<name>Andriy Gapon</name>
<email>avg@FreeBSD.org</email>
</author>
<published>2024-11-10T11:15:30Z</published>
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<id>urn:sha1:ec88c48413850768692a92736229e85b5d262935</id>
<content type='text'>
LSR_TEMT bit is set if both transmit hold and shift registers are
empty, but the flush command flushes only the hold register.

While here, update the diagnostic message to report which registers
could not be flushed.

(cherry picked from commit 0d2fd5b99c95329085d0700a4dd38507a054a50d)
</content>
</entry>
<entry>
<title>uart: Add support for Brainboxes / Intashield serial cards.</title>
<updated>2025-01-11T08:09:41Z</updated>
<author>
<name>Yoshihiro Takahashi</name>
<email>nyan@FreeBSD.org</email>
</author>
<published>2024-12-31T09:04:27Z</published>
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<id>urn:sha1:e5869ff39d4a66ebf8940355df3f62663babbb26</id>
<content type='text'>
PR:		283226
Reported by:	Cameron Williams

(cherry picked from commit 41b30bbc1a57b60afee9acdd6ad240c92ef13790)
</content>
</entry>
<entry>
<title>dev/uart: Add APMC0D08 as found in the Intel E2100</title>
<updated>2024-09-02T08:48:54Z</updated>
<author>
<name>Andrew Turner</name>
<email>andrew@FreeBSD.org</email>
</author>
<published>2024-07-23T09:18:36Z</published>
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<id>urn:sha1:75861a57b6fd721e47c8a7cb43c4882c200cca1d</id>
<content type='text'>
This uart has the requirement for 32-bit sized and aligned memory
accesses. It is also described in the Serial Port Console Redirection
Table (SPCR) with a different interface type value.

Reviewed by:	imp
Sponsored by:	Arm Ltd
Differential Revision:	https://reviews.freebsd.org/D45834

(cherry picked from commit 9840598aa31f2a89272f5bef6545e316f254f0c6)
</content>
</entry>
<entry>
<title>uart: Split out initilisation of the acpi devinfo</title>
<updated>2024-09-02T08:43:42Z</updated>
<author>
<name>Andrew Turner</name>
<email>andrew@FreeBSD.org</email>
</author>
<published>2024-03-12T18:06:18Z</published>
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<id>urn:sha1:f48bd7527bba62d4d8019fd4bbdb966aecdbac0b</id>
<content type='text'>
Split out the common parts of building the uart devinfo from ACPI
tables from the SPCR parser. This will be used when we support the DBG2
table to find the debug uart to be used by the kernel gdb stub.

Reviewed by:	imp
Sponsored by:	Arm Ltd
Differential Revision:	https://reviews.freebsd.org/D44357

(cherry picked from commit 473c0b44ae8c51b2aebc51887714b2ed14de50bf)
</content>
</entry>
<entry>
<title>uart: Use device_set_descf()</title>
<updated>2024-06-09T13:37:58Z</updated>
<author>
<name>Mark Johnston</name>
<email>markj@FreeBSD.org</email>
</author>
<published>2024-02-04T23:55:00Z</published>
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<id>urn:sha1:d73f9fc2641eeff30a904d5901c926cec3e3ef5c</id>
<content type='text'>
No functional change intended.

MFC after:	1 week

(cherry picked from commit 66d2d42a1f26a6ef868d7d46f87d6fad0bc099aa)
</content>
</entry>
<entry>
<title>Add support for Intel Atom S1200 UART</title>
<updated>2024-04-24T23:57:55Z</updated>
<author>
<name>Henrich Hartzer</name>
<email>henrichhartzer@tuta.io</email>
</author>
<published>2024-04-19T22:52:49Z</published>
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<id>urn:sha1:c7a5881d7a6a37881bb65837e42829ee68a3883c</id>
<content type='text'>
PR: 278316

Signed-off-by: Henrich Hartzer &lt;henrichhartzer@tuta.io&gt;
Reviewed by: imp
Pull Request: https://github.com/freebsd/freebsd-src/pull/1164
(cherry picked from commit 1f2776e123603042944aad9f41ceb46b5b28d8ae)
</content>
</entry>
<entry>
<title>dev/uart: Support 8-byte register access</title>
<updated>2024-02-19T13:17:56Z</updated>
<author>
<name>Andrew Turner</name>
<email>andrew@FreeBSD.org</email>
</author>
<published>2024-01-09T13:29:47Z</published>
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<id>urn:sha1:f8c7bbd1c93fc46610e2757760a0b55a31371780</id>
<content type='text'>
While we only support 4-byte registers in the uart code the physical
access may be to an 8-byte register. Support this as an option on
non-i386. On i386 we lack the needed 8-byte bus_space functions.

ACPI has an option for 8-byte register io width, and FDT can be given
any size. Support these sizes, even if we don't expect to see hardware
with an 8-byte io width.

Reviewed by:	imp
Sponsored by:	Arm Ltd
Differential Revision:	https://reviews.freebsd.org/D43374

(cherry picked from commit a9fc9d6d15f006feb6d7ddb036e020d5f9d19fce)
</content>
</entry>
<entry>
<title>uart(4): Honor hardware state of NS8250-class for tsw_busy</title>
<updated>2024-01-18T20:14:46Z</updated>
<author>
<name>Marius Strobl</name>
<email>marius@FreeBSD.org</email>
</author>
<published>2024-01-12T22:27:07Z</published>
<link rel='alternate' type='text/html' href='https://cgit-dev.freebsd.org/src/commit/?id=8595e76a9f1a5bcf057afe6d28846099287a26b7'/>
<id>urn:sha1:8595e76a9f1a5bcf057afe6d28846099287a26b7</id>
<content type='text'>
In 9750d9e5, I brought the equivalent of the TS_BUSY flag back in a
mostly hardware-agnostic way in order to fix tty_drain() and, thus,
TIOCDRAIN for UARTs with TX FIFOs. This proved to be sufficient for
fixing the regression reported. So in light of the release cycle of
FreeBSD 10.3, I decided that this change was be good enough for the
time being and opted to go with the smallest possible yet generic
(for all UARTs driven by uart(4)) solution addressing the problem at
hand.

However, at least for the NS8250-class the above isn't a complete
fix as these UARTs only trigger an interrupt when the TX FIFO became
empty. At this point, there still can be an outstanding character
left in the transmit shift register as indicated via the LSR. Thus,
this change adds the 3rd (besides the tty(4) and generic uart(4) bits)
part I had in my tree ever since, adding a uart_txbusy method to be
queried in addition for tsw_busy and hooking it up as appropriate
for the NS8250-class.

As it turns out, the exact equivalent of this 3rd part later on was
implemented for uftdi(4) in 9ad221a5.

While at it, explain the rational behind the deliberately missing
locking in uart_tty_busy() (also applying to the generic sc_txbusy
testing already present).

(cherry picked from commit 353e4c5a068d06b0d6dcfa9eb736ecb16e9eae45)
</content>
</entry>
<entry>
<title>sys: Remove $FreeBSD$: one-line sh pattern</title>
<updated>2023-08-16T17:54:58Z</updated>
<author>
<name>Warner Losh</name>
<email>imp@FreeBSD.org</email>
</author>
<published>2023-08-16T17:54:58Z</published>
<link rel='alternate' type='text/html' href='https://cgit-dev.freebsd.org/src/commit/?id=031beb4e239bfce798af17f5fe8dba8bcaf13d99'/>
<id>urn:sha1:031beb4e239bfce798af17f5fe8dba8bcaf13d99</id>
<content type='text'>
Remove /^\s*#[#!]?\s*\$FreeBSD\$.*$\n/
</content>
</entry>
</feed>
