src/sys/dev/usb/controller, branch release/12.3.0

Fix a common typo in source code comments

2021-08-19T07:36:32Z

- s/aligment/alignment/ (cherry picked from commit a1581cd73594bbbde638859c31226c2c21be1ab3)

MFC c834f30a0c16:

2021-01-12T16:47:35Z

Add new PCI ID for XHCI(4). Submitted by: Dmitry Luhtionov Sponsored by: Mellanox Technologies // NVIDIA Networking

MFC 1622a498525b:

2021-01-12T16:44:02Z

No need to stop XHCI endpoints in disabled state. Some AMD XHCI implementations apparently assert a permanent internal failure if this happens. Submitted by: ali.abdallah@suse.com PR: 251503 Sponsored by: Mellanox Technologies // NVIDIA Networking

MFC r367614:

2020-12-01T12:32:35Z

When doing a USB alternate setting on an USB interface we need to re-configure the XHCI endpoint context. Differential Revision: https://reviews.freebsd.org/D27174 Sponsored by: Mellanox Technologies // NVIDIA Networking

MFC r366978:

2020-11-06T00:35:36Z

xhci: Handle the case when MSI-X BAR is the same as IO BAR.

MFC r365402: musb/allwinner: add support for configuring phy as well as device mode

2020-10-19T07:03:04Z

At least on Orange Pi PC Plus even the host mode does not work without enabling the phy and setting it to the host mode. The driver will now parse dr_mode property and will try to configure itself and the phy accordingly. OTG mode is not supported yet, so it is treated as the device / peripheral mode. The phy is enabled -- powered on -- only for the host mode. The device mode requires support from a phy driver, e.g., aw_usbphy on Allwinner platform. aw_usbphy does not support the device mode, so it cannnot work yet.

MFC r365401: musb/allwinner: add H3 support

2020-10-19T06:44:07Z

MFC r365400: musb/allwinner: apply register filter in awusbdrd_bs_r_2() as well

2020-10-12T10:53:35Z

MFC r365398,r365399: Allwinner USB DRD support (musb_otg)

2020-10-12T10:51:34Z

Allwinner USB DRD is based on the Mentor USB OTG controller, with a different register layout and a few missing registers. The code is by Andrew Turner (andrew).

MFC r365918:

2020-09-26T08:44:16Z

Fix for use of the XHCI driver on Cortex-A72 by adding a missing cache flush operation before writing to the XHCI_ERSTBA_LO/HI register(s). PR: 237666 Discussed with: Mark Millard Sponsored by: Mellanox Technologies // Nvidia