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<title>src/sys/mips/include/cpuinfo.h, branch main</title>
<subtitle>FreeBSD source tree</subtitle>
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<updated>2021-12-31T03:57:24Z</updated>
<entry>
<title>mips: Remove sys/mips</title>
<updated>2021-12-31T03:57:24Z</updated>
<author>
<name>Warner Losh</name>
<email>imp@FreeBSD.org</email>
</author>
<published>2021-12-31T03:56:09Z</published>
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<id>urn:sha1:c09981f1422ef0d44042dacc5d1265392fba39f1</id>
<content type='text'>
Remove sys/mips as the next step of decomissioning mips from the tree.
Remove mips special cases from the kernel make files. Remove the mips
specific linker scripts.

Sponsored by:		Netflix
</content>
</entry>
<entry>
<title>spdx: initial adoption of licensing ID tags.</title>
<updated>2017-11-18T14:26:50Z</updated>
<author>
<name>Pedro F. Giffuni</name>
<email>pfg@FreeBSD.org</email>
</author>
<published>2017-11-18T14:26:50Z</published>
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<id>urn:sha1:df57947f083046d50552e99b91074927d2458708</id>
<content type='text'>
The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

Special thanks to Wind River for providing access to "The Duke of
Highlander" tool: an older (2014) run over FreeBSD tree was useful as a
starting point.

Initially, only tag files that use BSD 4-Clause "Original" license.

RelNotes:	yes
Differential Revision:	https://reviews.freebsd.org/D13133
</content>
</entry>
<entry>
<title>Add initial support for the floating point implementation register.</title>
<updated>2017-05-09T17:35:16Z</updated>
<author>
<name>John Baldwin</name>
<email>jhb@FreeBSD.org</email>
</author>
<published>2017-05-09T17:35:16Z</published>
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<id>urn:sha1:4a0f7f1c1046663c0b20f00a1f8520d915bde379</id>
<content type='text'>
- Save the current FIR in the global 'cpuinfo' structure in a new
  'fpu_id' member.
- Decode flags in the FIR when displaying other CPU flags during boot.
- Use the existing "dummy" slot in the floating point register structure
  to export the FIR in process core dumps and via ptrace().  Note that
  while the FIR register is not volatile, this practice of storing the FIR
  in the floating-point register set is used in other OS's.

Reviewed by:	kan
MFC after:	1 month
Sponsored by:	DARPA / AFRL
Differential Revision:	https://reviews.freebsd.org/D10617
</content>
</entry>
<entry>
<title>Revert prior commit to restore the files mangled by my "fixing" merge</title>
<updated>2017-03-01T02:10:40Z</updated>
<author>
<name>Warner Losh</name>
<email>imp@FreeBSD.org</email>
</author>
<published>2017-03-01T02:10:40Z</published>
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<id>urn:sha1:43b96a4eb563c4ea90d64abed86d3ee9eaa35feb</id>
<content type='text'>
conflicts for a git rebase I tried to do.
</content>
</entry>
<entry>
<title>Renumber copyright clause 4</title>
<updated>2017-02-28T23:42:47Z</updated>
<author>
<name>Warner Losh</name>
<email>imp@FreeBSD.org</email>
</author>
<published>2017-02-28T23:42:47Z</published>
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<id>urn:sha1:fbbd9655e5107c68e4e0146ff22b73d7350475bc</id>
<content type='text'>
Renumber cluase 4 to 3, per what everybody else did when BSD granted
them permission to remove clause 3. My insistance on keeping the same
numbering for legal reasons is too pedantic, so give up on that point.

Submitted by:	Jan Schaumann &lt;jschauma@stevens.edu&gt;
Pull Request:	https://github.com/freebsd/freebsd/pull/96
</content>
</entry>
<entry>
<title>[mips] add support for using the MIPS user register for TLS data.</title>
<updated>2016-08-07T01:29:55Z</updated>
<author>
<name>Adrian Chadd</name>
<email>adrian@FreeBSD.org</email>
</author>
<published>2016-08-07T01:29:55Z</published>
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<id>urn:sha1:b812fe4d6b6194455394db22be9fb9e490756e35</id>
<content type='text'>
This work, originally from Stacey Son, uses the MIPS UserReg for
reading the TLS data, and will fall back to the normal syscall path
when it isn't supported.

This code dynamically patches cpu_switch() to bypass the UserReg
instruction so to avoid generating a machine exception.

Thanks to sson for the original work, and to Dan Nelson for
bringing it to date and testing it on MIPS32 with me.

Tested:

* mips64 (sson)
* mips74k (dnelson_1901@yahoo.com) - AR9344 SoC, UserReg support
* mips24k (adrian) - AR9331 SoC, no UserReg support

Obtained from:	sson, dnelson_1901@yahoo.com
</content>
</entry>
<entry>
<title>[mips] Add TLB pagemask probing code, and print out the allowable page sizes.</title>
<updated>2015-12-22T15:59:41Z</updated>
<author>
<name>Adrian Chadd</name>
<email>adrian@FreeBSD.org</email>
</author>
<published>2015-12-22T15:59:41Z</published>
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<id>urn:sha1:7b61491a8d46e86a52d73c4fab1642f2e84ddb6d</id>
<content type='text'>
This is from Stacey's work on larger kernel stack sizes for MIPS.  Thanks!

Submitted by:	sson
</content>
</entry>
<entry>
<title>Add L2-cache writeback/flush operations. Supported 32,128-byte line-size,</title>
<updated>2014-11-20T17:06:41Z</updated>
<author>
<name>Ruslan Bukin</name>
<email>br@FreeBSD.org</email>
</author>
<published>2014-11-20T17:06:41Z</published>
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<id>urn:sha1:209fe5ef9aa255c97f6d9e260bb6cadcdda146e5</id>
<content type='text'>
else ignored. Cavium Networks also ignored as it has non-standard config
registers.

Obtained from:	NetBSD
Sponsored by:	DARPA, AFRL
</content>
</entry>
<entry>
<title>Remove some unused cruft.</title>
<updated>2010-03-04T05:37:19Z</updated>
<author>
<name>Neel Natu</name>
<email>neel@FreeBSD.org</email>
</author>
<published>2010-03-04T05:37:19Z</published>
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<id>urn:sha1:cefb7b77f8726bd524532a249adeab09b60444fc</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Add support for CPUs with cache coherent DMA. The two main changes are:</title>
<updated>2010-03-04T05:23:08Z</updated>
<author>
<name>Neel Natu</name>
<email>neel@FreeBSD.org</email>
</author>
<published>2010-03-04T05:23:08Z</published>
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<id>urn:sha1:6be470c07701f0972b7c16f25305c259748cacd1</id>
<content type='text'>
- We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT
  requests on these CPUs.

- The bus_dmamap_sync() is a no-op for these CPUs.

A side-effect of this change is rename DMAMAP_COHERENT flag to
DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately.

Reviewed by: gonzo, imp
</content>
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