MFC r323001:

In compiler-rt, a few assembler implementations for i386 floating point
conversion functions use SSE2 instructions, but these are not guarded by
#ifdef __SSE2__, and there is no implementation using general purpose
registers.  For these functions, use the generic C variants instead,
otherwise they will cause SIGILL on older processors.

Approved by:	re (kib)
Reported by:	bsdpr@phoe.frmug.org
PR:		221733

MFC r323014:

Follow-up to r323001: if the actually selected CPUTYPE is capable of
SSE2 instructions, we can use them.

Suggested by:	jkim
PR:		221733

1 files changed, 17 insertions, 6 deletions

diff --git a/lib/libcompiler_rt/Makefile b/lib/libcompiler_rt/Makefile
index 8c560d7b3681..7ccccca22a69 100644
--- a/lib/libcompiler_rt/Makefile
+++ b/lib/libcompiler_rt/Makefile
@@ -65,15 +65,9 @@ SRCF=	absvdi2 \
 	fixunsxfti \
 	fixxfdi \
 	fixxfti \
-	floatdidf \
-	floatdisf \
-	floatdixf \
 	floattidf \
 	floattisf \
 	floattixf \
-	floatundidf \
-	floatundisf \
-	floatundixf \
 	floatunsidf \
 	floatunsisf \
 	floatuntidf \
@@ -126,6 +120,23 @@ SRCF=	absvdi2 \
 	umoddi3 \
 	umodti3
 
+# Avoid using SSE2 instructions on i386, if unsupported.
+.if ${MACHINE_CPUARCH} == "i386" && empty(MACHINE_CPU:Msse2)
+SRCS+=		floatdidf.c
+SRCS+=		floatdisf.c
+SRCS+=		floatdixf.c
+SRCS+=		floatundidf.c
+SRCS+=		floatundisf.c
+SRCS+=		floatundixf.c
+.else
+SRCF+=		floatdidf
+SRCF+=		floatdisf
+SRCF+=		floatdixf
+SRCF+=		floatundidf
+SRCF+=		floatundisf
+SRCF+=		floatundixf
+.endif
+
 # These are already shipped by libc.a on arm and mips
 .if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "mips"
 SRCF+=	adddf3 \