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authorWarner Losh <imp@FreeBSD.org>2015-02-27 22:16:54 +0000
committerWarner Losh <imp@FreeBSD.org>2015-02-27 22:16:54 +0000
commitda75c2cc5808a45edc76752ba495dcc5dcd4346c (patch)
tree74a0899e9f467d761efca9e14d7d3213fb899de8 /Bindings/arm/fsl.txt
parentab9104d36764981b663e037d0e48496993a070a4 (diff)
downloadsrc-da75c2cc5808a45edc76752ba495dcc5dcd4346c.tar.gz
src-da75c2cc5808a45edc76752ba495dcc5dcd4346c.zip
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diff --git a/Bindings/arm/fsl.txt b/Bindings/arm/fsl.txt
index e935d7d4ac43..a5462b6b3c30 100644
--- a/Bindings/arm/fsl.txt
+++ b/Bindings/arm/fsl.txt
@@ -74,3 +74,61 @@ Required root node properties:
i.MX6q generic board
Required root node properties:
- compatible = "fsl,imx6q";
+
+Freescale Vybrid Platform Device Tree Bindings
+----------------------------------------------
+
+For the Vybrid SoC familiy all variants with DDR controller are supported,
+which is the VF5xx and VF6xx series. Out of historical reasons, in most
+places the kernel uses vf610 to refer to the whole familiy.
+
+Required root node compatible property (one of them):
+ - compatible = "fsl,vf500";
+ - compatible = "fsl,vf510";
+ - compatible = "fsl,vf600";
+ - compatible = "fsl,vf610";
+
+Freescale LS1021A Platform Device Tree Bindings
+------------------------------------------------
+
+Required root node compatible properties:
+ - compatible = "fsl,ls1021a";
+
+Freescale LS1021A SoC-specific Device Tree Bindings
+-------------------------------------------
+
+Freescale SCFG
+ SCFG is the supplemental configuration unit, that provides SoC specific
+configuration and status registers for the chip. Such as getting PEX port
+status.
+ Required properties:
+ - compatible: should be "fsl,ls1021a-scfg"
+ - reg: should contain base address and length of SCFG memory-mapped registers
+
+Example:
+ scfg: scfg@1570000 {
+ compatible = "fsl,ls1021a-scfg";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ };
+
+Freescale DCFG
+ DCFG is the device configuration unit, that provides general purpose
+configuration and status for the device. Such as setting the secondary
+core start address and release the secondary core from holdoff and startup.
+ Required properties:
+ - compatible: should be "fsl,ls1021a-dcfg"
+ - reg : should contain base address and length of DCFG memory-mapped registers
+
+Example:
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1021a-dcfg";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ };
+
+Freescale LS2085A SoC Device Tree Bindings
+------------------------------------------
+
+LS2085A ARMv8 based Simulator model
+Required root node properties:
+ - compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
+