diff options
author | Emmanuel Vadot <manu@FreeBSD.org> | 2020-04-14 16:56:11 +0000 |
---|---|---|
committer | Emmanuel Vadot <manu@FreeBSD.org> | 2020-04-14 16:56:11 +0000 |
commit | 937eaf8bbdcf7e2cd3231b71940f9221e6857210 (patch) | |
tree | f35da0d4b9188f1cb082442854ce86fcca10b7b4 /Bindings/clock/fsl,sai-clock.yaml | |
parent | 995ee34fd27211af598f9adf111cb49609d1b3de (diff) | |
download | src-937eaf8bbdcf7e2cd3231b71940f9221e6857210.tar.gz src-937eaf8bbdcf7e2cd3231b71940f9221e6857210.zip |
Notes
Diffstat (limited to 'Bindings/clock/fsl,sai-clock.yaml')
-rw-r--r-- | Bindings/clock/fsl,sai-clock.yaml | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/Bindings/clock/fsl,sai-clock.yaml b/Bindings/clock/fsl,sai-clock.yaml new file mode 100644 index 000000000000..fc3bdfdc091a --- /dev/null +++ b/Bindings/clock/fsl,sai-clock.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale SAI bitclock-as-a-clock binding + +maintainers: + - Michael Walle <michael@walle.cc> + +description: | + It is possible to use the BCLK pin of a SAI module as a generic clock + output. Some SoC are very constrained in their pin multiplexer + configuration. Eg. pins can only be changed groups. For example, on the + LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI, + the second pins are wasted. Using this binding it is possible to use the + clock of the second SAI as a MCLK clock for an audio codec, for example. + + This is a composite of a gated clock and a divider clock. + +properties: + compatible: + const: fsl,vf610-sai-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mclk: clock-mclk@f130080 { + compatible = "fsl,vf610-sai-clock"; + reg = <0x0 0xf130080 0x0 0x80>; + #clock-cells = <0>; + clocks = <&parentclk>; + }; + }; |