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| author | Emmanuel Vadot <manu@FreeBSD.org> | 2017-10-21 15:18:20 +0000 |
|---|---|---|
| committer | Emmanuel Vadot <manu@FreeBSD.org> | 2017-10-21 15:18:20 +0000 |
| commit | d5464ff11700ac44568e6816e00d1d1427cc46ae (patch) | |
| tree | 1c388ab705b506c8d0e3f16710bfaa2cbc623262 /Bindings/iommu/arm,smmu-v3.txt | |
| parent | f3f213a6f94d330b77b3910f4c66b62aeec50645 (diff) | |
| download | src-d5464ff11700ac44568e6816e00d1d1427cc46ae.tar.gz src-d5464ff11700ac44568e6816e00d1d1427cc46ae.zip | |
Notes
Diffstat (limited to 'Bindings/iommu/arm,smmu-v3.txt')
| -rw-r--r-- | Bindings/iommu/arm,smmu-v3.txt | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Bindings/iommu/arm,smmu-v3.txt b/Bindings/iommu/arm,smmu-v3.txt index be57550e14e4..c9abbf3e4f68 100644 --- a/Bindings/iommu/arm,smmu-v3.txt +++ b/Bindings/iommu/arm,smmu-v3.txt @@ -26,6 +26,12 @@ the PCIe specification. * "priq" - PRI Queue not empty * "cmdq-sync" - CMD_SYNC complete * "gerror" - Global Error activated + * "combined" - The combined interrupt is optional, + and should only be provided if the + hardware supports just a single, + combined interrupt line. + If provided, then the combined interrupt + will be used in preference to any others. - #iommu-cells : See the generic IOMMU binding described in devicetree/bindings/pci/pci-iommu.txt @@ -49,6 +55,12 @@ the PCIe specification. - hisilicon,broken-prefetch-cmd : Avoid sending CMD_PREFETCH_* commands to the SMMU. +- cavium,cn9900-broken-page1-regspace + : Replaces all page 1 offsets used for EVTQ_PROD/CONS, + PRIQ_PROD/CONS register access with page 0 offsets. + Set for Cavium ThunderX2 silicon that doesn't support + SMMU page1 register space. + ** Example smmu@2b400000 { |