diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2023-04-14 21:41:27 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2023-06-22 18:20:56 +0000 |
| commit | bdd1243df58e60e85101c09001d9812a789b6bc4 (patch) | |
| tree | a1ce621c7301dd47ba2ddc3b8eaa63b441389481 /contrib/llvm-project/llvm/lib/CodeGen/MachineStableHash.cpp | |
| parent | 781624ca2d054430052c828ba8d2c2eaf2d733e7 (diff) | |
| parent | e3b557809604d036af6e00c60f012c2025b59a5e (diff) | |
Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/MachineStableHash.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/MachineStableHash.cpp | 30 |
1 files changed, 25 insertions, 5 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/MachineStableHash.cpp b/contrib/llvm-project/llvm/lib/CodeGen/MachineStableHash.cpp index b546a5082b07..9628e4c5aeb5 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/MachineStableHash.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/MachineStableHash.cpp @@ -63,7 +63,7 @@ STATISTIC(StableHashBailingMetadataUnsupported, stable_hash llvm::stableHashValue(const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_Register: - if (Register::isVirtualRegister(MO.getReg())) { + if (MO.getReg().isVirtual()) { const MachineRegisterInfo &MRI = MO.getParent()->getMF()->getRegInfo(); SmallVector<unsigned> DefOpcodes; for (auto &Def : MRI.def_instructions(MO.getReg())) @@ -119,8 +119,26 @@ stable_hash llvm::stableHashValue(const MachineOperand &MO) { stable_hash_combine_string(MO.getSymbolName())); case MachineOperand::MO_RegisterMask: - case MachineOperand::MO_RegisterLiveOut: - return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask()); + case MachineOperand::MO_RegisterLiveOut: { + if (const MachineInstr *MI = MO.getParent()) { + if (const MachineBasicBlock *MBB = MI->getParent()) { + if (const MachineFunction *MF = MBB->getParent()) { + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); + unsigned RegMaskSize = + MachineOperand::getRegMaskSize(TRI->getNumRegs()); + const uint32_t *RegMask = MO.getRegMask(); + std::vector<llvm::stable_hash> RegMaskHashes(RegMask, + RegMask + RegMaskSize); + return hash_combine(MO.getType(), MO.getTargetFlags(), + stable_hash_combine_array(RegMaskHashes.data(), + RegMaskHashes.size())); + } + } + } + + assert(0 && "MachineOperand not associated with any MachineFunction"); + return hash_combine(MO.getType(), MO.getTargetFlags()); + } case MachineOperand::MO_ShuffleMask: { std::vector<llvm::stable_hash> ShuffleMaskHashes; @@ -147,6 +165,9 @@ stable_hash llvm::stableHashValue(const MachineOperand &MO) { case MachineOperand::MO_Predicate: return stable_hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate()); + case MachineOperand::MO_DbgInstrRef: + return stable_hash_combine(MO.getType(), MO.getInstrRefInstrIndex(), + MO.getInstrRefOpIndex()); } llvm_unreachable("Invalid machine operand type"); } @@ -164,8 +185,7 @@ stable_hash llvm::stableHashValue(const MachineInstr &MI, bool HashVRegs, HashComponents.push_back(MI.getOpcode()); HashComponents.push_back(MI.getFlags()); for (const MachineOperand &MO : MI.operands()) { - if (!HashVRegs && MO.isReg() && MO.isDef() && - Register::isVirtualRegister(MO.getReg())) + if (!HashVRegs && MO.isReg() && MO.isDef() && MO.getReg().isVirtual()) continue; // Skip virtual register defs. if (MO.isCPI()) { |