1 files changed, 38 insertions, 133 deletions

diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 21fee2441f32..0c6c17d5a0b6 100644
--- a/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -83,7 +83,8 @@ static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
 template <std::size_t N>
 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
                                         const MCPhysReg (&Regs)[N]) {
-  assert(RegNo < N && "Invalid register number");
+  if (RegNo >= N)
+    return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
   return MCDisassembler::Success;
 }
@@ -112,6 +113,14 @@ static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
   return decodeRegisterClass(Inst, RegNo, FRegs);
 }
 
+static DecodeStatus DecodeFpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  if (RegNo > 30 || (RegNo & 1))
+    return MCDisassembler::Fail;
+  return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
+}
+
 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const MCDisassembler *Decoder) {
@@ -239,7 +248,8 @@ template <unsigned N>
 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
                                       int64_t Address,
                                       const MCDisassembler *Decoder) {
-  assert(isUInt<N>(Imm) && "Invalid immediate");
+  if (!isUInt<N>(Imm))
+    return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
@@ -248,7 +258,8 @@ template <unsigned N>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
                                       int64_t Address,
                                       const MCDisassembler *Decoder) {
-  assert(isUInt<N>(Imm) && "Invalid immediate");
+  if (!isUInt<N>(Imm))
+    return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
   return MCDisassembler::Success;
 }
@@ -271,171 +282,64 @@ static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
-                                        int64_t Address,
-                                        const MCDisassembler *Decoder) {
-  // Decode the memri field (imm, reg), which has the low 16-bits as the
-  // displacement and the next 5 bits as the register #.
-
-  uint64_t Base = Imm >> 16;
-  uint64_t Disp = Imm & 0xFFFF;
-
-  assert(Base < 32 && "Invalid base register");
-
-  switch (Inst.getOpcode()) {
-  default: break;
-  case PPC::LBZU:
-  case PPC::LHAU:
-  case PPC::LHZU:
-  case PPC::LWZU:
-  case PPC::LFSU:
-  case PPC::LFDU:
-    // Add the tied output operand.
-    Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
-    break;
-  case PPC::STBU:
-  case PPC::STHU:
-  case PPC::STWU:
-  case PPC::STFSU:
-  case PPC::STFDU:
-    Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
-    break;
-  }
-
-  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
+static DecodeStatus decodeDispRIXOperand(MCInst &Inst, uint64_t Imm,
                                          int64_t Address,
                                          const MCDisassembler *Decoder) {
-  // Decode the memrix field (imm, reg), which has the low 14-bits as the
-  // displacement and the next 5 bits as the register #.
-
-  uint64_t Base = Imm >> 14;
-  uint64_t Disp = Imm & 0x3FFF;
-
-  assert(Base < 32 && "Invalid base register");
-
-  if (Inst.getOpcode() == PPC::LDU)
-    // Add the tied output operand.
-    Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
-  else if (Inst.getOpcode() == PPC::STDU)
-    Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
-
-  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
+  // The rix displacement is an immediate shifted by 2
+  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 2)));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm,
+static DecodeStatus decodeDispRIHashOperand(MCInst &Inst, uint64_t Imm,
                                             int64_t Address,
                                             const MCDisassembler *Decoder) {
-  // Decode the memrix field for a hash store or hash check operation.
-  // The field is composed of a register and an immediate value that is 6 bits
+  // Decode the disp field for a hash store or hash check operation.
+  // The field is composed of an immediate value that is 6 bits
   // and covers the range -8 to -512. The immediate is always negative and 2s
   // complement which is why we sign extend a 7 bit value.
-  const uint64_t Base = Imm >> 6;
   const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
 
-  assert(Base < 32 && "Invalid base register");
-
   Inst.addOperand(MCOperand::createImm(Disp));
-  Inst.addOperand(MCOperand::createReg(RRegs[Base]));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
+static DecodeStatus decodeDispRIX16Operand(MCInst &Inst, uint64_t Imm,
                                            int64_t Address,
                                            const MCDisassembler *Decoder) {
-  // Decode the memrix16 field (imm, reg), which has the low 12-bits as the
-  // displacement with 16-byte aligned, and the next 5 bits as the register #.
-
-  uint64_t Base = Imm >> 12;
-  uint64_t Disp = Imm & 0xFFF;
-
-  assert(Base < 32 && "Invalid base register");
-
-  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
+  // The rix16 displacement has 12-bits which are shifted by 4.
+  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 4)));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
-                                               int64_t Address,
-                                               const MCDisassembler *Decoder) {
-  // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
-  // displacement, and the next 5 bits as an immediate 0.
-  uint64_t Base = Imm >> 34;
-  uint64_t Disp = Imm & 0x3FFFFFFFFUL;
-
-  assert(Base < 32 && "Invalid base register");
-
-  Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
-  return decodeImmZeroOperand(Inst, Base, Address, Decoder);
-}
-
-static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
+static DecodeStatus decodeDispSPE8Operand(MCInst &Inst, uint64_t Imm,
                                           int64_t Address,
                                           const MCDisassembler *Decoder) {
-  // Decode the memri34 field (imm, reg), which has the low 34-bits as the
-  // displacement, and the next 5 bits as the register #.
-  uint64_t Base = Imm >> 34;
-  uint64_t Disp = Imm & 0x3FFFFFFFFUL;
-
-  assert(Base < 32 && "Invalid base register");
-
-  Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
-  return MCDisassembler::Success;
-}
+  // Decode the dispSPE8 field, which has 5-bits, 8-byte aligned.
 
-static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
-                                       int64_t Address,
-                                       const MCDisassembler *Decoder) {
-  // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
-  // displacement with 8-byte aligned, and the next 5 bits as the register #.
-
-  uint64_t Base = Imm >> 5;
   uint64_t Disp = Imm & 0x1F;
 
-  assert(Base < 32 && "Invalid base register");
-
   Inst.addOperand(MCOperand::createImm(Disp << 3));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
-                                       int64_t Address,
-                                       const MCDisassembler *Decoder) {
-  // Decode the spe4disp field (imm, reg), which has the low 5-bits as the
-  // displacement with 4-byte aligned, and the next 5 bits as the register #.
+static DecodeStatus decodeDispSPE4Operand(MCInst &Inst, uint64_t Imm,
+                                          int64_t Address,
+                                          const MCDisassembler *Decoder) {
+  // Decode the dispSPE8 field, which has 5-bits, 4-byte aligned.
 
-  uint64_t Base = Imm >> 5;
   uint64_t Disp = Imm & 0x1F;
 
-  assert(Base < 32 && "Invalid base register");
-
   Inst.addOperand(MCOperand::createImm(Disp << 2));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
-                                       int64_t Address,
-                                       const MCDisassembler *Decoder) {
-  // Decode the spe2disp field (imm, reg), which has the low 5-bits as the
-  // displacement with 2-byte aligned, and the next 5 bits as the register #.
+static DecodeStatus decodeDispSPE2Operand(MCInst &Inst, uint64_t Imm,
+                                          int64_t Address,
+                                          const MCDisassembler *Decoder) {
+  // Decode the dispSPE8 field, which has 5-bits, 2-byte aligned.
 
-  uint64_t Base = Imm >> 5;
   uint64_t Disp = Imm & 0x1F;
-
-  assert(Base < 32 && "Invalid base register");
-
   Inst.addOperand(MCOperand::createImm(Disp << 1));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
@@ -444,8 +348,9 @@ static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
                                         const MCDisassembler *Decoder) {
   // The cr bit encoding is 0x80 >> cr_reg_num.
 
-  unsigned Zeros = countTrailingZeros(Imm);
-  assert(Zeros < 8 && "Invalid CR bit value");
+  unsigned Zeros = llvm::countr_zero(Imm);
+  if (Zeros >= 8)
+    return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
   return MCDisassembler::Success;
@@ -468,7 +373,7 @@ DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
   // TODO: In this function we call decodeInstruction several times with
   //       different decoder tables. It may be possible to only call once by
   //       looking at the top 6 bits of the instruction.
-  if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) {
+  if (STI.hasFeature(PPC::FeaturePrefixInstrs) && Bytes.size() >= 8) {
     uint32_t Prefix = ReadFunc(Bytes.data());
     uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
     uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
@@ -490,7 +395,7 @@ DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
   // Read the instruction in the proper endianness.
   uint64_t Inst = ReadFunc(Bytes.data());
 
-  if (STI.getFeatureBits()[PPC::FeatureSPE]) {
+  if (STI.hasFeature(PPC::FeatureSPE)) {
     DecodeStatus result =
         decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
     if (result != MCDisassembler::Fail)