diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-05-03 20:26:11 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-05-03 20:26:11 +0000 |
| commit | 148779df305667b6942fee7e758fdf81a6498f38 (patch) | |
| tree | 976d85fb9cb4bc8ed54348b045f742be90e10c57 /lib/Target/AArch64/AArch64CallLowering.cpp | |
| parent | a303c417bbdb53703c2c17398b08486bde78f1f6 (diff) | |
Notes
Diffstat (limited to 'lib/Target/AArch64/AArch64CallLowering.cpp')
| -rw-r--r-- | lib/Target/AArch64/AArch64CallLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/AArch64/AArch64CallLowering.cpp b/lib/Target/AArch64/AArch64CallLowering.cpp index b2f55a7e1e09..ff3e4c40e2c2 100644 --- a/lib/Target/AArch64/AArch64CallLowering.cpp +++ b/lib/Target/AArch64/AArch64CallLowering.cpp @@ -247,7 +247,7 @@ bool AArch64CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, unsigned i = 0; for (auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; - setArgFlags(OrigArg, i + 1, DL, F); + setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); bool Split = false; LLT Ty = MRI.getType(VRegs[i]); unsigned Dst = VRegs[i]; |