diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-12-18 20:10:56 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-12-18 20:10:56 +0000 |
| commit | 044eb2f6afba375a914ac9d8024f8f5142bb912e (patch) | |
| tree | 1475247dc9f9fe5be155ebd4c9069c75aadf8c20 /lib/Target/AArch64/AArch64SchedCyclone.td | |
| parent | eb70dddbd77e120e5d490bd8fbe7ff3f8fa81c6b (diff) | |
Notes
Diffstat (limited to 'lib/Target/AArch64/AArch64SchedCyclone.td')
| -rw-r--r-- | lib/Target/AArch64/AArch64SchedCyclone.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64SchedCyclone.td b/lib/Target/AArch64/AArch64SchedCyclone.td index 9fd3ae6818e5..7a474ba8ef9b 100644 --- a/lib/Target/AArch64/AArch64SchedCyclone.td +++ b/lib/Target/AArch64/AArch64SchedCyclone.td @@ -18,6 +18,8 @@ def CycloneModel : SchedMachineModel { let LoadLatency = 4; // Optimistic load latency. let MispredictPenalty = 16; // 14-19 cycles are typical. let CompleteModel = 1; + + list<Predicate> UnsupportedFeatures = [HasSVE]; } //===----------------------------------------------------------------------===// |