diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-05-16 19:46:52 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-05-16 19:46:52 +0000 |
| commit | 6b3f41ed88e8e440e11a4fbf20b6600529f80049 (patch) | |
| tree | 928b056f24a634d628c80238dbbf10d41b1a71d5 /lib/Target/AArch64/AArch64TargetTransformInfo.h | |
| parent | c46e6a5940c50058e00c0c5f9123fd82e338d29a (diff) | |
Notes
Diffstat (limited to 'lib/Target/AArch64/AArch64TargetTransformInfo.h')
| -rw-r--r-- | lib/Target/AArch64/AArch64TargetTransformInfo.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64TargetTransformInfo.h b/lib/Target/AArch64/AArch64TargetTransformInfo.h index e37c003e064c..280d97f3c502 100644 --- a/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -43,6 +43,9 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> { VECTOR_LDST_FOUR_ELEMENTS }; + bool isWideningInstruction(Type *Ty, unsigned Opcode, + ArrayRef<const Value *> Args); + public: explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F) : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), @@ -84,6 +87,10 @@ public: return 64; } + unsigned getMinVectorRegisterBitWidth() { + return ST->getMinVectorRegisterBitWidth(); + } + unsigned getMaxInterleaveFactor(unsigned VF); int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, @@ -134,6 +141,10 @@ public: unsigned getMinPrefetchStride(); unsigned getMaxPrefetchIterationsAhead(); + + bool shouldExpandReduction(const IntrinsicInst *II) const { + return false; + } /// @} }; |
