diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2011-12-09 18:27:22 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2011-12-09 18:27:22 +0000 |
| commit | d4c8b5d2e851b0e8a063c6bf8543a4823a26c15a (patch) | |
| tree | d5baf24dba561bcf8bc6ec60db36bfc5586f6378 /lib/Target/ARM/ARMInstrThumb2.td | |
| parent | 30815c536baacc07e925f0aef23a5395883173dc (diff) | |
Notes
Diffstat (limited to 'lib/Target/ARM/ARMInstrThumb2.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 471ec2967487..05dcc8993969 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1538,8 +1538,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin, let Inst{21} = 0; // No writeback let Inst{20} = L_bit; let Inst{19-16} = Rn; - let Inst{15} = 0; - let Inst{14-0} = regs{14-0}; + let Inst{15-0} = regs; } def IA_UPD : T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), @@ -1554,8 +1553,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin, let Inst{21} = 1; // Writeback let Inst{20} = L_bit; let Inst{19-16} = Rn; - let Inst{15} = 0; - let Inst{14-0} = regs{14-0}; + let Inst{15-0} = regs; } def DB : T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), @@ -1570,8 +1568,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin, let Inst{21} = 0; // No writeback let Inst{20} = L_bit; let Inst{19-16} = Rn; - let Inst{15} = 0; - let Inst{14-0} = regs{14-0}; + let Inst{15-0} = regs; } def DB_UPD : T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), @@ -1586,8 +1583,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin, let Inst{21} = 1; // Writeback let Inst{20} = L_bit; let Inst{19-16} = Rn; - let Inst{15} = 0; - let Inst{14-0} = regs{14-0}; + let Inst{15-0} = regs; } } |