diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
| commit | 01095a5d43bbfde13731688ddcf6048ebb8b7721 (patch) | |
| tree | 4def12e759965de927d963ac65840d663ef9d1ea /lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | |
| parent | f0f4822ed4b66e3579e92a89f368f8fb860e218e (diff) | |
Notes
Diffstat (limited to 'lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp')
| -rw-r--r-- | lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 4a9c3413cb29..7bc08ecfcab6 100644 --- a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -16,7 +16,7 @@ #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonInstPrinter.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixedLenDisassembler.h" @@ -30,7 +30,6 @@ #include "llvm/Support/MemoryObject.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/TargetRegistry.h" -#include <vector> using namespace llvm; using namespace Hexagon; @@ -382,7 +381,8 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; else if (SubregBit) - // Subreg bit should not be set for non-doublevector newvalue producers + // Hexagon PRM 10.11 New-value operands + // Nt[0] is reserved and should always be encoded as zero. return MCDisassembler::Fail; assert(Producer != Hexagon::NoRegister); MCO.setReg(Producer); @@ -1459,6 +1459,7 @@ void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode, operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); Op = MCOperand::createReg(operand); MI->addOperand(Op); + break; case Hexagon::V4_SA1_and1: case Hexagon::V4_SA1_dec: case Hexagon::V4_SA1_inc: |