diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-04-26 19:45:00 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-04-26 19:45:00 +0000 |
| commit | 12f3ca4cdb95b193af905a00e722a4dcb40b3de3 (patch) | |
| tree | ae1a7fcfc24a8d4b23206c57121c3f361d4b7f84 /lib/Target/Hexagon/HexagonAsmPrinter.cpp | |
| parent | d99dafe2e4a385dd2a6c76da6d8258deb100657b (diff) | |
Diffstat (limited to 'lib/Target/Hexagon/HexagonAsmPrinter.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonAsmPrinter.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp index fda23f8f6b05..c8483f7e6e76 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -286,9 +286,9 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo(); const MachineFunction &MF = *MI.getParent()->getParent(); const auto &HST = MF.getSubtarget<HexagonSubtarget>(); - unsigned VectorSize = HST.useHVXSglOps() - ? Hexagon::VectorRegsRegClass.getSize() - : Hexagon::VectorRegs128BRegClass.getSize(); + const auto &VecRC = HST.useHVXSglOps() ? Hexagon::VectorRegsRegClass + : Hexagon::VectorRegs128BRegClass; + unsigned VectorSize = HST.getRegisterInfo()->getSpillSize(VecRC); switch (Inst.getOpcode()) { default: return; |