diff options
author | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
commit | 71d5a2540a98c81f5bcaeb48805e0e2881f530ef (patch) | |
tree | 5343938942df402b49ec7300a1c25a2d4ccd5821 /lib/Target/Hexagon/HexagonVLIWPacketizer.h | |
parent | 31bbf64f3a4974a2d6c8b3b27ad2f519caf74057 (diff) |
Diffstat (limited to 'lib/Target/Hexagon/HexagonVLIWPacketizer.h')
-rw-r--r-- | lib/Target/Hexagon/HexagonVLIWPacketizer.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.h b/lib/Target/Hexagon/HexagonVLIWPacketizer.h index b28b926ec300..3f28dc5b79ce 100644 --- a/lib/Target/Hexagon/HexagonVLIWPacketizer.h +++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.h @@ -7,6 +7,9 @@ #include "llvm/CodeGen/ScheduleDAGInstrs.h" namespace llvm { +class HexagonInstrInfo; +class HexagonRegisterInfo; + class HexagonPacketizerList : public VLIWPacketizerList { // Vector of instructions assigned to the packet that has just been created. std::vector<MachineInstr*> OldPacketMIs; @@ -109,6 +112,7 @@ protected: void reserveResourcesForConstExt(); bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J); bool hasControlDependence(const MachineInstr &I, const MachineInstr &J); + bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J); bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J); bool producesStall(const MachineInstr &MI); }; |