vendor/llvm/llvm-trunk-r321017

116 files changed, 24355 insertions, 24103 deletions

diff --git a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
index d901abbd1692..387296c69c39 100644
--- a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -47,6 +47,7 @@
 #include "llvm/Support/Format.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/SMLoc.h"
+#include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
@@ -60,9 +61,6 @@
 
 using namespace llvm;
 
-static cl::opt<bool> EnableFutureRegs("mfuture-regs",
-                                      cl::desc("Enable future registers"));
-
 static cl::opt<bool> WarnMissingParenthesis(
     "mwarn-missing-parenthesis",
     cl::desc("Warn for missing parenthesis around predicate registers"),
@@ -95,13 +93,20 @@ class HexagonAsmParser : public MCTargetAsmParser {
   }
 
   MCAsmParser &Parser;
-  MCAssembler *Assembler;
-  MCInstrInfo const &MCII;
   MCInst MCB;
   bool InBrackets;
 
   MCAsmParser &getParser() const { return Parser; }
-  MCAssembler *getAssembler() const { return Assembler; }
+  MCAssembler *getAssembler() const {
+    MCAssembler *Assembler = nullptr;
+    // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
+    if (!Parser.getStreamer().hasRawTextSupport()) {
+      MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
+      Assembler = &MES->getAssembler();
+    }
+    return Assembler;
+  }
+
   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
 
   bool equalIsAsmAssignment() override { return false; }
@@ -124,7 +129,7 @@ class HexagonAsmParser : public MCTargetAsmParser {
   bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
                            OperandVector &InstOperands, uint64_t &ErrorInfo,
                            bool MatchingInlineAsm);
-
+  void eatToEndOfPacket();
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
@@ -155,18 +160,12 @@ class HexagonAsmParser : public MCTargetAsmParser {
 public:
   HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
                    const MCInstrInfo &MII, const MCTargetOptions &Options)
-    : MCTargetAsmParser(Options, _STI), Parser(_Parser),
-      MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
+    : MCTargetAsmParser(Options, _STI, MII), Parser(_Parser),
+      InBrackets(false) {
+    MCB.setOpcode(Hexagon::BUNDLE);
     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
 
     MCAsmParserExtension::Initialize(_Parser);
-
-    Assembler = nullptr;
-    // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
-    if (!Parser.getStreamer().hasRawTextSupport()) {
-      MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
-      Assembler = &MES->getAssembler();
-    }
   }
 
   bool splitIdentifier(OperandVector &Operands);
@@ -191,6 +190,7 @@ public:
 /// instruction.
 struct HexagonOperand : public MCParsedAsmOperand {
   enum KindTy { Token, Immediate, Register } Kind;
+  MCContext &Context;
 
   SMLoc StartLoc, EndLoc;
 
@@ -217,10 +217,12 @@ struct HexagonOperand : public MCParsedAsmOperand {
     struct ImmTy Imm;
   };
 
-  HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
+  HexagonOperand(KindTy K, MCContext &Context)
+      : MCParsedAsmOperand(), Kind(K), Context(Context) {}
 
 public:
-  HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() {
+  HexagonOperand(const HexagonOperand &o)
+      : MCParsedAsmOperand(), Context(o.Context) {
     Kind = o.Kind;
     StartLoc = o.StartLoc;
     EndLoc = o.EndLoc;
@@ -393,9 +395,13 @@ public:
       return;
     }
     int64_t Extended = SignExtend64(Value, 32);
+    HexagonMCExpr *NewExpr = HexagonMCExpr::create(
+        MCConstantExpr::create(Extended, Context), Context);
     if ((Extended < 0) != (Value < 0))
-      Expr->setSignMismatch();
-    Inst.addOperand(MCOperand::createExpr(Expr));
+      NewExpr->setSignMismatch();
+    NewExpr->setMustExtend(Expr->mustExtend());
+    NewExpr->setMustNotExtend(Expr->mustNotExtend());
+    Inst.addOperand(MCOperand::createExpr(NewExpr));
   }
 
   void addn1ConstOperands(MCInst &Inst, unsigned N) const {
@@ -409,8 +415,9 @@ public:
 
   void print(raw_ostream &OS) const override;
 
-  static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) {
-    HexagonOperand *Op = new HexagonOperand(Token);
+  static std::unique_ptr<HexagonOperand> CreateToken(MCContext &Context,
+                                                     StringRef Str, SMLoc S) {
+    HexagonOperand *Op = new HexagonOperand(Token, Context);
     Op->Tok.Data = Str.data();
     Op->Tok.Length = Str.size();
     Op->StartLoc = S;
@@ -418,18 +425,18 @@ public:
     return std::unique_ptr<HexagonOperand>(Op);
   }
 
-  static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S,
-                                                   SMLoc E) {
-    HexagonOperand *Op = new HexagonOperand(Register);
+  static std::unique_ptr<HexagonOperand>
+  CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) {
+    HexagonOperand *Op = new HexagonOperand(Register, Context);
     Op->Reg.RegNum = RegNum;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return std::unique_ptr<HexagonOperand>(Op);
   }
 
-  static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S,
-                                                   SMLoc E) {
-    HexagonOperand *Op = new HexagonOperand(Immediate);
+  static std::unique_ptr<HexagonOperand>
+  CreateImm(MCContext &Context, const MCExpr *Val, SMLoc S, SMLoc E) {
+    HexagonOperand *Op = new HexagonOperand(Immediate, Context);
     Op->Imm.Val = Val;
     Op->StartLoc = S;
     Op->EndLoc = E;
@@ -462,9 +469,9 @@ bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
   MCB.setLoc(IDLoc);
   // Check the bundle for errors.
   const MCRegisterInfo *RI = getContext().getRegisterInfo();
-  HexagonMCChecker Check(getContext(), MCII, getSTI(), MCB, *RI);
+  HexagonMCChecker Check(getContext(), MII, getSTI(), MCB, *RI);
 
-  bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(),
+  bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MII, getSTI(),
                                                         getContext(), MCB,
                                                         &Check);
 
@@ -481,8 +488,8 @@ bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
     // 4 or less we have a packet that is too big.
     if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {
       Error(IDLoc, "invalid instruction packet: out of slots");
-      return true; // Error
     }
+    return true; // Error
   }
 
   return false; // No error
@@ -494,13 +501,23 @@ bool HexagonAsmParser::matchBundleOptions() {
     if (!Parser.getTok().is(AsmToken::Colon))
       return false;
     Lex();
+    char const *MemNoShuffMsg =
+        "invalid instruction packet: mem_noshuf specifier not "
+        "supported with this architecture";
     StringRef Option = Parser.getTok().getString();
+    auto IDLoc = Parser.getTok().getLoc();
     if (Option.compare_lower("endloop0") == 0)
       HexagonMCInstrInfo::setInnerLoop(MCB);
     else if (Option.compare_lower("endloop1") == 0)
       HexagonMCInstrInfo::setOuterLoop(MCB);
+    else if (Option.compare_lower("mem_noshuf") == 0)
+      if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])
+        HexagonMCInstrInfo::setMemReorderDisabled(MCB);
+      else
+        return getParser().Error(IDLoc, MemNoShuffMsg);
     else
-      return true;
+      return getParser().Error(IDLoc, llvm::Twine("'") + Option +
+                                          "' is not a valid bundle option");
     Lex();
   }
 }
@@ -513,13 +530,13 @@ void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
   NewInst.setOpcode(MCI.getOpcode());
   for (MCOperand &I : MCI)
     if (I.isImm()) {
-      int64_t Value (I.getImm());
+      int64_t Value(I.getImm());
       NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
           MCConstantExpr::create(Value, getContext()), getContext())));
     } else {
       if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() &&
           WarnSignedMismatch)
-        Warning (MCI.getLoc(), "Signed/Unsigned mismatch");
+        Warning(MCI.getLoc(), "Signed/Unsigned mismatch");
       NewInst.addOperand(I);
     }
   MCI = NewInst;
@@ -573,6 +590,15 @@ bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
   llvm_unreachable("Implement any new match types added!");
 }
 
+void HexagonAsmParser::eatToEndOfPacket() {
+  assert(InBrackets);
+  MCAsmLexer &Lexer = getLexer();
+  while (!Lexer.is(AsmToken::RCurly))
+    Lexer.Lex();
+  Lexer.Lex();
+  InBrackets = false;
+}
+
 bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                                OperandVector &Operands,
                                                MCStreamer &Out,
@@ -587,6 +613,7 @@ bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     assert(Operands.size() == 1 && "Brackets should be by themselves");
     if (InBrackets) {
       getParser().Error(IDLoc, "Already in a packet");
+      InBrackets = false;
       return true;
     }
     InBrackets = true;
@@ -605,10 +632,13 @@ bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   }
   MCInst *SubInst = new (getParser().getContext()) MCInst;
   if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
-                          MatchingInlineAsm))
+                          MatchingInlineAsm)) {
+    if (InBrackets)
+      eatToEndOfPacket();
     return true;
+  }
   HexagonMCInstrInfo::extendIfNeeded(
-      getParser().getContext(), MCII, MCB, *SubInst);
+      getParser().getContext(), MII, MCB, *SubInst);
   MCB.addOperand(MCOperand::createInst(SubInst));
   if (!InBrackets)
     return finishBundle(IDLoc, Out);
@@ -854,10 +884,11 @@ bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {
   do {
     std::pair<StringRef, StringRef> HeadTail = String.split('.');
     if (!HeadTail.first.empty())
-      Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc));
+      Operands.push_back(
+          HexagonOperand::CreateToken(getContext(), HeadTail.first, Loc));
     if (!HeadTail.second.empty())
       Operands.push_back(HexagonOperand::CreateToken(
-          String.substr(HeadTail.first.size(), 1), Loc));
+          getContext(), String.substr(HeadTail.first.size(), 1), Loc));
     String = HeadTail.second;
   } while (!String.empty());
   return false;
@@ -879,38 +910,43 @@ bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
       case Hexagon::P3:
         if (previousEqual(Operands, 0, "if")) {
           if (WarnMissingParenthesis)
-            Warning (Begin, "Missing parenthesis around predicate register");
+            Warning(Begin, "Missing parenthesis around predicate register");
           static char const *LParen = "(";
           static char const *RParen = ")";
-          Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));
-          Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
+          Operands.push_back(
+              HexagonOperand::CreateToken(getContext(), LParen, Begin));
+          Operands.push_back(
+              HexagonOperand::CreateReg(getContext(), Register, Begin, End));
           const AsmToken &MaybeDotNew = Lexer.getTok();
           if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
               MaybeDotNew.getString().equals_lower(".new"))
             splitIdentifier(Operands);
-          Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
+          Operands.push_back(
+              HexagonOperand::CreateToken(getContext(), RParen, Begin));
           return false;
         }
         if (previousEqual(Operands, 0, "!") &&
             previousEqual(Operands, 1, "if")) {
           if (WarnMissingParenthesis)
-            Warning (Begin, "Missing parenthesis around predicate register");
+            Warning(Begin, "Missing parenthesis around predicate register");
           static char const *LParen = "(";
           static char const *RParen = ")";
-          Operands.insert(Operands.end () - 1,
-                          HexagonOperand::CreateToken(LParen, Begin));
-          Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
+          Operands.insert(Operands.end() - 1, HexagonOperand::CreateToken(
+                                                  getContext(), LParen, Begin));
+          Operands.push_back(
+              HexagonOperand::CreateReg(getContext(), Register, Begin, End));
           const AsmToken &MaybeDotNew = Lexer.getTok();
           if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
               MaybeDotNew.getString().equals_lower(".new"))
             splitIdentifier(Operands);
-          Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
+          Operands.push_back(
+              HexagonOperand::CreateToken(getContext(), RParen, Begin));
           return false;
         }
         break;
       }
-    Operands.push_back(HexagonOperand::CreateReg(
-        Register, Begin, End));
+    Operands.push_back(
+        HexagonOperand::CreateReg(getContext(), Register, Begin, End));
     return false;
   }
   return splitIdentifier(Operands);
@@ -932,10 +968,9 @@ bool HexagonAsmParser::isLabel(AsmToken &Token) {
     return true;
   if (!matchRegister(String.lower()))
     return true;
-  (void)Second;
   assert(Second.is(AsmToken::Colon));
-  StringRef Raw (String.data(), Third.getString().data() - String.data() +
-                 Third.getString().size());
+  StringRef Raw(String.data(), Third.getString().data() - String.data() +
+                                   Third.getString().size());
   std::string Collapsed = Raw;
   Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end());
   StringRef Whole = Collapsed;
@@ -945,7 +980,8 @@ bool HexagonAsmParser::isLabel(AsmToken &Token) {
   return false;
 }
 
-bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) {
+bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious,
+                                                   SMLoc &Loc) {
   if (!Contigious && ErrorNoncontigiousRegister) {
     Error(Loc, "Register name is not contigious");
     return true;
@@ -955,7 +991,8 @@ bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc)
   return false;
 }
 
-bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
+bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+                                     SMLoc &EndLoc) {
   MCAsmLexer &Lexer = getLexer();
   StartLoc = getLexer().getLoc();
   SmallVector<AsmToken, 5> Lookahead;
@@ -964,19 +1001,19 @@ bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &En
   bool NeededWorkaround = false;
   while (Again) {
     AsmToken const &Token = Lexer.getTok();
-    RawString = StringRef(RawString.data(),
-                          Token.getString().data() - RawString.data () +
-                          Token.getString().size());
+    RawString = StringRef(RawString.data(), Token.getString().data() -
+                                                RawString.data() +
+                                                Token.getString().size());
     Lookahead.push_back(Token);
     Lexer.Lex();
     bool Contigious = Lexer.getTok().getString().data() ==
                       Lookahead.back().getString().data() +
-                      Lookahead.back().getString().size();
+                          Lookahead.back().getString().size();
     bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||
                 Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
                 Lexer.is(AsmToken::Colon);
-    bool Workaround = Lexer.is(AsmToken::Colon) ||
-                      Lookahead.back().is(AsmToken::Colon);
+    bool Workaround =
+        Lexer.is(AsmToken::Colon) || Lookahead.back().is(AsmToken::Colon);
     Again = (Contigious && Type) || (Workaround && Type);
     NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));
   }
@@ -1006,10 +1043,10 @@ bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &En
   std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
   unsigned ColonReg = matchRegister(ColonSplit.first.lower());
   if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
-    Lexer.UnLex(Lookahead.back());
-    Lookahead.pop_back();
-    Lexer.UnLex(Lookahead.back());
-    Lookahead.pop_back();
+    do {
+      Lexer.UnLex(Lookahead.back());
+      Lookahead.pop_back();
+    } while (!Lookahead.empty () && !Lexer.is(AsmToken::Colon));
     RegNo = ColonReg;
     EndLoc = Lexer.getLoc();
     if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
@@ -1037,19 +1074,18 @@ bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) {
   return false;
 }
 
-bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {
+bool HexagonAsmParser::parseExpression(MCExpr const *&Expr) {
   SmallVector<AsmToken, 4> Tokens;
   MCAsmLexer &Lexer = getLexer();
   bool Done = false;
-  static char const * Comma = ",";
+  static char const *Comma = ",";
   do {
-    Tokens.emplace_back (Lexer.getTok());
+    Tokens.emplace_back(Lexer.getTok());
     Lex();
-    switch (Tokens.back().getKind())
-    {
+    switch (Tokens.back().getKind()) {
     case AsmToken::TokenKind::Hash:
-      if (Tokens.size () > 1)
-        if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) {
+      if (Tokens.size() > 1)
+        if ((Tokens.end() - 2)->getKind() == AsmToken::TokenKind::Plus) {
           Tokens.insert(Tokens.end() - 2,
                         AsmToken(AsmToken::TokenKind::Comma, Comma));
           Done = true;
@@ -1068,7 +1104,8 @@ bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {
     Lexer.UnLex(Tokens.back());
     Tokens.pop_back();
   }
-  return getParser().parseExpression(Expr);
+  SMLoc Loc = Lexer.getLoc();
+  return getParser().parseExpression(Expr, Loc);
 }
 
 bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
@@ -1079,7 +1116,8 @@ bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
     bool Error = parseExpression(Expr);
     Expr = HexagonMCExpr::create(Expr, getContext());
     if (!Error)
-      Operands.push_back(HexagonOperand::CreateImm(Expr, Loc, Loc));
+      Operands.push_back(
+          HexagonOperand::CreateImm(getContext(), Expr, Loc, Loc));
     return Error;
   }
   return parseOperand(Operands);
@@ -1092,6 +1130,7 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
   while (true) {
     AsmToken const &Token = Parser.getTok();
     switch (Token.getKind()) {
+    case AsmToken::Eof:
     case AsmToken::EndOfStatement: {
       Lex();
       return false;
@@ -1099,15 +1138,15 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
     case AsmToken::LCurly: {
       if (!Operands.empty())
         return true;
-      Operands.push_back(
-          HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
+      Operands.push_back(HexagonOperand::CreateToken(
+          getContext(), Token.getString(), Token.getLoc()));
       Lex();
       return false;
     }
     case AsmToken::RCurly: {
       if (Operands.empty()) {
-        Operands.push_back(
-            HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
+        Operands.push_back(HexagonOperand::CreateToken(
+            getContext(), Token.getString(), Token.getLoc()));
         Lex();
       }
       return false;
@@ -1123,9 +1162,9 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
     case AsmToken::LessEqual:
     case AsmToken::LessLess: {
       Operands.push_back(HexagonOperand::CreateToken(
-          Token.getString().substr(0, 1), Token.getLoc()));
+          getContext(), Token.getString().substr(0, 1), Token.getLoc()));
       Operands.push_back(HexagonOperand::CreateToken(
-          Token.getString().substr(1, 1), Token.getLoc()));
+          getContext(), Token.getString().substr(1, 1), Token.getLoc()));
       Lex();
       continue;
     }
@@ -1134,8 +1173,8 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
       bool ImplicitExpression = implicitExpressionLocation(Operands);
       SMLoc ExprLoc = Lexer.getLoc();
       if (!ImplicitExpression)
-        Operands.push_back(
-          HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
+        Operands.push_back(HexagonOperand::CreateToken(
+            getContext(), Token.getString(), Token.getLoc()));
       Lex();
       bool MustExtend = false;
       bool HiOnly = false;
@@ -1172,16 +1211,15 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
       if (Expr->evaluateAsAbsolute(Value)) {
         if (HiOnly)
           Expr = MCBinaryExpr::createLShr(
-              Expr,  MCConstantExpr::create(16, Context), Context);
+              Expr, MCConstantExpr::create(16, Context), Context);
         if (HiOnly || LoOnly)
-          Expr = MCBinaryExpr::createAnd(Expr,
-              MCConstantExpr::create(0xffff, Context),
-                                    Context);
+          Expr = MCBinaryExpr::createAnd(
+              Expr, MCConstantExpr::create(0xffff, Context), Context);
       } else {
         MCValue Value;
         if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) {
           if (!Value.isAbsolute()) {
-            switch(Value.getAccessVariant()) {
+            switch (Value.getAccessVariant()) {
             case MCSymbolRefExpr::VariantKind::VK_TPREL:
             case MCSymbolRefExpr::VariantKind::VK_DTPREL:
               // Don't lazy extend these expression variants
@@ -1197,7 +1235,7 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
       HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);
       HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
       std::unique_ptr<HexagonOperand> Operand =
-          HexagonOperand::CreateImm(Expr, ExprLoc, ExprLoc);
+          HexagonOperand::CreateImm(getContext(), Expr, ExprLoc, ExprLoc);
       Operands.push_back(std::move(Operand));
       continue;
     }
@@ -1210,15 +1248,14 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
 }
 
 bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
-                                        StringRef Name,
-                                        AsmToken ID,
+                                        StringRef Name, AsmToken ID,
                                         OperandVector &Operands) {
   getLexer().UnLex(ID);
   return parseInstruction(Operands);
 }
 
-static MCInst makeCombineInst(int opCode, MCOperand &Rdd,
-                              MCOperand &MO1, MCOperand &MO2) {
+static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1,
+                              MCOperand &MO2) {
   MCInst TmpInst;
   TmpInst.setOpcode(opCode);
   TmpInst.addOperand(Rdd);
@@ -1287,6 +1324,13 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
   bool is32bit = false; // used to distinguish between CONST32 and CONST64
   switch (Inst.getOpcode()) {
   default:
+    if (HexagonMCInstrInfo::getDesc(MII, Inst).isPseudo()) {
+      SMDiagnostic Diag = getSourceManager().GetMessage(
+          IDLoc, SourceMgr::DK_Error,
+          "Found pseudo instruction with no expansion");
+      Diag.print("", errs());
+      report_fatal_error("Invalid pseudo instruction");
+    }
     break;
 
   case Hexagon::A2_iconst: {
@@ -1320,8 +1364,10 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
 
   case Hexagon::C2_cmpgei: {
     MCOperand &MO = Inst.getOperand(2);
-    MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
-        MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
+    MO.setExpr(HexagonMCExpr::create(
+        MCBinaryExpr::createSub(MO.getExpr(),
+                                MCConstantExpr::create(1, Context), Context),
+        Context));
     Inst.setOpcode(Hexagon::C2_cmpgti);
     break;
   }
@@ -1342,8 +1388,10 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
       TmpInst.addOperand(Rt);
       Inst = TmpInst;
     } else {
-      MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
-          MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
+      MO.setExpr(HexagonMCExpr::create(
+          MCBinaryExpr::createSub(MO.getExpr(),
+                                  MCConstantExpr::create(1, Context), Context),
+          Context));
       Inst.setOpcode(Hexagon::C2_cmpgtui);
     }
     break;
@@ -1510,7 +1558,7 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
 
         TmpInst.addOperand(MO_0);
         TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
-          MCSymbolRefExpr::create(Sym, getContext()), getContext())));
+            MCSymbolRefExpr::create(Sym, getContext()), getContext())));
         Inst = TmpInst;
       }
     }
@@ -1541,7 +1589,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
           MCConstantExpr::create(s8, Context), Context))); // upper 32
       auto Expr = HexagonMCExpr::create(
           MCConstantExpr::create(Lo_32(Value), Context), Context);
-      HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
+      HexagonMCInstrInfo::setMustExtend(
+          *Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
       MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
       Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
     } else {
@@ -1589,15 +1638,16 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
   case Hexagon::S2_tableidxh_goodsyntax: {
     MCInst TmpInst;
     MCOperand &Rx = Inst.getOperand(0);
-    MCOperand &_dst_ = Inst.getOperand(1);
     MCOperand &Rs = Inst.getOperand(2);
     MCOperand &Imm4 = Inst.getOperand(3);
     MCOperand &Imm6 = Inst.getOperand(4);
-    Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
-        Imm6.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
+    Imm6.setExpr(HexagonMCExpr::create(
+        MCBinaryExpr::createSub(Imm6.getExpr(),
+                                MCConstantExpr::create(1, Context), Context),
+        Context));
     TmpInst.setOpcode(Hexagon::S2_tableidxh);
     TmpInst.addOperand(Rx);
-    TmpInst.addOperand(_dst_);
+    TmpInst.addOperand(Rx);
     TmpInst.addOperand(Rs);
     TmpInst.addOperand(Imm4);
     TmpInst.addOperand(Imm6);
@@ -1608,15 +1658,16 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
   case Hexagon::S2_tableidxw_goodsyntax: {
     MCInst TmpInst;
     MCOperand &Rx = Inst.getOperand(0);
-    MCOperand &_dst_ = Inst.getOperand(1);
     MCOperand &Rs = Inst.getOperand(2);
     MCOperand &Imm4 = Inst.getOperand(3);
     MCOperand &Imm6 = Inst.getOperand(4);
-    Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
-        Imm6.getExpr(), MCConstantExpr::create(2, Context), Context), Context));
+    Imm6.setExpr(HexagonMCExpr::create(
+        MCBinaryExpr::createSub(Imm6.getExpr(),
+                                MCConstantExpr::create(2, Context), Context),
+        Context));
     TmpInst.setOpcode(Hexagon::S2_tableidxw);
     TmpInst.addOperand(Rx);
-    TmpInst.addOperand(_dst_);
+    TmpInst.addOperand(Rx);
     TmpInst.addOperand(Rs);
     TmpInst.addOperand(Imm4);
     TmpInst.addOperand(Imm6);
@@ -1627,15 +1678,16 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
   case Hexagon::S2_tableidxd_goodsyntax: {
     MCInst TmpInst;
     MCOperand &Rx = Inst.getOperand(0);
-    MCOperand &_dst_ = Inst.getOperand(1);
     MCOperand &Rs = Inst.getOperand(2);
     MCOperand &Imm4 = Inst.getOperand(3);
     MCOperand &Imm6 = Inst.getOperand(4);
-    Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
-        Imm6.getExpr(), MCConstantExpr::create(3, Context), Context), Context));
+    Imm6.setExpr(HexagonMCExpr::create(
+        MCBinaryExpr::createSub(Imm6.getExpr(),
+                                MCConstantExpr::create(3, Context), Context),
+        Context));
     TmpInst.setOpcode(Hexagon::S2_tableidxd);
     TmpInst.addOperand(Rx);
-    TmpInst.addOperand(_dst_);
+    TmpInst.addOperand(Rx);
     TmpInst.addOperand(Rs);
     TmpInst.addOperand(Imm4);
     TmpInst.addOperand(Imm6);
@@ -1656,21 +1708,15 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
     bool Absolute = Expr.evaluateAsAbsolute(Value);
     assert(Absolute);
     (void)Absolute;
-    if (!HexagonMCInstrInfo::mustExtend(Expr)) {
-      if (Value < 0 && Value > -256) {
-        Imm.setExpr(HexagonMCExpr::create(
-            MCConstantExpr::create(Value * -1, Context), Context));
-        TmpInst.setOpcode(Hexagon::M2_mpysin);
-      } else if (Value < 256 && Value >= 0)
-        TmpInst.setOpcode(Hexagon::M2_mpysip);
-      else
-        return Match_InvalidOperand;
-    } else {
-      if (Value >= 0)
-        TmpInst.setOpcode(Hexagon::M2_mpysip);
-      else
-        return Match_InvalidOperand;
-    }
+    if (!HexagonMCInstrInfo::mustExtend(Expr) &&
+        ((Value <= -256) || Value >= 256))
+      return Match_InvalidOperand;
+    if (Value < 0 && Value > -256) {
+      Imm.setExpr(HexagonMCExpr::create(
+          MCConstantExpr::create(Value * -1, Context), Context));
+      TmpInst.setOpcode(Hexagon::M2_mpysin);
+    } else
+      TmpInst.setOpcode(Hexagon::M2_mpysip);
     TmpInst.addOperand(Rd);
     TmpInst.addOperand(Rs);
     TmpInst.addOperand(Imm);
@@ -1953,7 +1999,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
     break;
   case Hexagon::A2_zxtb: {
     Inst.setOpcode(Hexagon::A2_andir);
-    Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, Context)));
+    Inst.addOperand(
+        MCOperand::createExpr(MCConstantExpr::create(255, Context)));
     break;
   }
   } // switch
diff --git a/lib/Target/Hexagon/BitTracker.cpp b/lib/Target/Hexagon/BitTracker.cpp
index 5b02aa3ca3ae..15d6a05a0078 100644
--- a/lib/Target/Hexagon/BitTracker.cpp
+++ b/lib/Target/Hexagon/BitTracker.cpp
@@ -1,4 +1,4 @@
-//===--- BitTracker.cpp ---------------------------------------------------===//
+//===- BitTracker.cpp -----------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -18,16 +18,16 @@
 // A "ref" value is associated with a BitRef structure, which indicates
 // which virtual register, and which bit in that register is the origin
 // of the value. For example, given an instruction
-//   vreg2 = ASL vreg1, 1
-// assuming that nothing is known about bits of vreg1, bit 1 of vreg2
-// will be a "ref" to (vreg1, 0). If there is a subsequent instruction
-//   vreg3 = ASL vreg2, 2
-// then bit 3 of vreg3 will be a "ref" to (vreg1, 0) as well.
+//   %2 = ASL %1, 1
+// assuming that nothing is known about bits of %1, bit 1 of %2
+// will be a "ref" to (%1, 0). If there is a subsequent instruction
+//   %3 = ASL %2, 2
+// then bit 3 of %3 will be a "ref" to (%1, 0) as well.
 // The "bottom" case means that the bit's value cannot be determined,
 // and that this virtual register actually defines it. The "bottom" case
 // is discussed in detail in BitTracker.h. In fact, "bottom" is a "ref
-// to self", so for the vreg1 above, the bit 0 of it will be a "ref" to
-// (vreg1, 0), bit 1 will be a "ref" to (vreg1, 1), etc.
+// to self", so for the %1 above, the bit 0 of it will be a "ref" to
+// (%1, 0), bit 1 will be a "ref" to (%1, 1), etc.
 //
 // The tracker implements the Wegman-Zadeck algorithm, originally developed
 // for SSA-based constant propagation. Each register is represented as
@@ -61,21 +61,21 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <cassert>
 #include <cstdint>
 #include <iterator>
 
 using namespace llvm;
 
-typedef BitTracker BT;
+using BT = BitTracker;
 
 namespace {
 
-  // Local trickery to pretty print a register (without the whole "%vreg"
+  // Local trickery to pretty print a register (without the whole "%number"
   // business).
   struct printv {
     printv(unsigned r) : R(r) {}
@@ -181,12 +181,13 @@ namespace llvm {
 } // end namespace llvm
 
 void BitTracker::print_cells(raw_ostream &OS) const {
-  for (CellMapType::iterator I = Map.begin(), E = Map.end(); I != E; ++I)
-    dbgs() << PrintReg(I->first, &ME.TRI) << " -> " << I->second << "\n";
+  for (const std::pair<unsigned, RegisterCell> P : Map)
+    dbgs() << printReg(P.first, &ME.TRI) << " -> " << P.second << "\n";
 }
 
 BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F)
-    : Trace(false), ME(E), MF(F), MRI(F.getRegInfo()), Map(*new CellMapType) {}
+    : ME(E), MF(F), MRI(F.getRegInfo()), Map(*new CellMapType), Trace(false) {
+}
 
 BitTracker::~BitTracker() {
   delete &Map;
@@ -335,20 +336,13 @@ uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const {
   // 1. find a physical register PhysR from the same class as RR.Reg,
   // 2. find a physical register PhysS that corresponds to PhysR:RR.Sub,
   // 3. find a register class that contains PhysS.
-  unsigned PhysR;
   if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) {
-    const TargetRegisterClass *VC = MRI.getRegClass(RR.Reg);
-    assert(VC->begin() != VC->end() && "Empty register class");
-    PhysR = *VC->begin();
-  } else {
-    assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg));
-    PhysR = RR.Reg;
+    const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub);
+    return TRI.getRegSizeInBits(VC);
   }
-
-  unsigned PhysS = (RR.Sub == 0) ? PhysR : TRI.getSubReg(PhysR, RR.Sub);
-  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PhysS);
-  uint16_t BW = TRI.getRegSizeInBits(*RC);
-  return BW;
+  assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg));
+  unsigned PhysR = (RR.Sub == 0) ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub);
+  return getPhysRegBitWidth(PhysR);
 }
 
 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR,
@@ -717,6 +711,12 @@ BT::BitMask BT::MachineEvaluator::mask(unsigned Reg, unsigned Sub) const {
   return BitMask(0, W-1);
 }
 
+uint16_t BT::MachineEvaluator::getPhysRegBitWidth(unsigned Reg) const {
+  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
+  const TargetRegisterClass &PC = *TRI.getMinimalPhysRegClass(Reg);
+  return TRI.getRegSizeInBits(PC);
+}
+
 bool BT::MachineEvaluator::evaluate(const MachineInstr &MI,
                                     const CellMapType &Inputs,
                                     CellMapType &Outputs) const {
@@ -763,12 +763,39 @@ bool BT::MachineEvaluator::evaluate(const MachineInstr &MI,
   return true;
 }
 
+bool BT::UseQueueType::Cmp::operator()(const MachineInstr *InstA,
+                                       const MachineInstr *InstB) const {
+  // This is a comparison function for a priority queue: give higher priority
+  // to earlier instructions.
+  // This operator is used as "less", so returning "true" gives InstB higher
+  // priority (because then InstA < InstB).
+  if (InstA == InstB)
+    return false;
+  const MachineBasicBlock *BA = InstA->getParent();
+  const MachineBasicBlock *BB = InstB->getParent();
+  if (BA != BB) {
+    // If the blocks are different, ideally the dominating block would
+    // have a higher priority, but it may be too expensive to check.
+    return BA->getNumber() > BB->getNumber();
+  }
+
+  MachineBasicBlock::const_iterator ItA = InstA->getIterator();
+  MachineBasicBlock::const_iterator ItB = InstB->getIterator();
+  MachineBasicBlock::const_iterator End = BA->end();
+  while (ItA != End) {
+    if (ItA == ItB)
+      return false;   // ItA was before ItB.
+    ++ItA;
+  }
+  return true;
+}
+
 // Main W-Z implementation.
 
 void BT::visitPHI(const MachineInstr &PI) {
   int ThisN = PI.getParent()->getNumber();
   if (Trace)
-    dbgs() << "Visit FI(BB#" << ThisN << "): " << PI;
+    dbgs() << "Visit FI(" << printMBBReference(*PI.getParent()) << "): " << PI;
 
   const MachineOperand &MD = PI.getOperand(0);
   assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition");
@@ -785,7 +812,8 @@ void BT::visitPHI(const MachineInstr &PI) {
     const MachineBasicBlock *PB = PI.getOperand(i + 1).getMBB();
     int PredN = PB->getNumber();
     if (Trace)
-      dbgs() << "  edge BB#" << PredN << "->BB#" << ThisN;
+      dbgs() << "  edge " << printMBBReference(*PB) << "->"
+             << printMBBReference(*PI.getParent());
     if (!EdgeExec.count(CFGEdge(PredN, ThisN))) {
       if (Trace)
         dbgs() << " not executable\n";
@@ -795,14 +823,14 @@ void BT::visitPHI(const MachineInstr &PI) {
     RegisterRef RU = PI.getOperand(i);
     RegisterCell ResC = ME.getCell(RU, Map);
     if (Trace)
-      dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
+      dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
              << " cell: " << ResC << "\n";
     Changed |= DefC.meet(ResC, DefRR.Reg);
   }
 
   if (Changed) {
     if (Trace)
-      dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
+      dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
              << " cell: " << DefC << "\n";
     ME.putCell(DefRR, DefC, Map);
     visitUsesOf(DefRR.Reg);
@@ -810,10 +838,8 @@ void BT::visitPHI(const MachineInstr &PI) {
 }
 
 void BT::visitNonBranch(const MachineInstr &MI) {
-  if (Trace) {
-    int ThisN = MI.getParent()->getNumber();
-    dbgs() << "Visit MI(BB#" << ThisN << "): " << MI;
-  }
+  if (Trace)
+    dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI;
   if (MI.isDebugValue())
     return;
   assert(!MI.isBranch() && "Unexpected branch instruction");
@@ -827,22 +853,20 @@ void BT::visitNonBranch(const MachineInstr &MI) {
       if (!MO.isReg() || !MO.isUse())
         continue;
       RegisterRef RU(MO);
-      dbgs() << "  input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
+      dbgs() << "  input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
              << " cell: " << ME.getCell(RU, Map) << "\n";
     }
     dbgs() << "Outputs:\n";
-    for (CellMapType::iterator I = ResMap.begin(), E = ResMap.end();
-         I != E; ++I) {
-      RegisterRef RD(I->first);
-      dbgs() << "  " << PrintReg(I->first, &ME.TRI) << " cell: "
+    for (const std::pair<unsigned, RegisterCell> &P : ResMap) {
+      RegisterRef RD(P.first);
+      dbgs() << "  " << printReg(P.first, &ME.TRI) << " cell: "
              << ME.getCell(RD, ResMap) << "\n";
     }
   }
 
   // Iterate over all definitions of the instruction, and update the
   // cells accordingly.
-  for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
-    const MachineOperand &MO = MI.getOperand(i);
+  for (const MachineOperand &MO : MI.operands()) {
     // Visit register defs only.
     if (!MO.isReg() || !MO.isDef())
       continue;
@@ -900,7 +924,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
     BTs.clear();
     const MachineInstr &MI = *It;
     if (Trace)
-      dbgs() << "Visit BR(BB#" << ThisN << "): " << MI;
+      dbgs() << "Visit BR(" << printMBBReference(B) << "): " << MI;
     assert(MI.isBranch() && "Expecting branch instruction");
     InstrExec.insert(&MI);
     bool Eval = ME.evaluate(MI, Map, BTs, FallsThrough);
@@ -916,7 +940,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
       if (Trace) {
         dbgs() << "  adding targets:";
         for (unsigned i = 0, n = BTs.size(); i < n; ++i)
-          dbgs() << " BB#" << BTs[i]->getNumber();
+          dbgs() << " " << printMBBReference(*BTs[i]);
         if (FallsThrough)
           dbgs() << "\n  falls through\n";
         else
@@ -927,13 +951,11 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
     ++It;
   } while (FallsThrough && It != End);
 
-  typedef MachineBasicBlock::const_succ_iterator succ_iterator;
   if (!DefaultToAll) {
     // Need to add all CFG successors that lead to EH landing pads.
     // There won't be explicit branches to these blocks, but they must
     // be processed.
-    for (succ_iterator I = B.succ_begin(), E = B.succ_end(); I != E; ++I) {
-      const MachineBasicBlock *SB = *I;
+    for (const MachineBasicBlock *SB : B.successors()) {
       if (SB->isEHPad())
         Targets.insert(SB);
     }
@@ -944,33 +966,21 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
         Targets.insert(&*Next);
     }
   } else {
-    for (succ_iterator I = B.succ_begin(), E = B.succ_end(); I != E; ++I)
-      Targets.insert(*I);
+    for (const MachineBasicBlock *SB : B.successors())
+      Targets.insert(SB);
   }
 
-  for (unsigned i = 0, n = Targets.size(); i < n; ++i) {
-    int TargetN = Targets[i]->getNumber();
-    FlowQ.push(CFGEdge(ThisN, TargetN));
-  }
+  for (const MachineBasicBlock *TB : Targets)
+    FlowQ.push(CFGEdge(ThisN, TB->getNumber()));
 }
 
 void BT::visitUsesOf(unsigned Reg) {
   if (Trace)
-    dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n";
+    dbgs() << "queuing uses of modified reg " << printReg(Reg, &ME.TRI)
+           << " cell: " << ME.getCell(Reg, Map) << '\n';
 
-  typedef MachineRegisterInfo::use_nodbg_iterator use_iterator;
-  use_iterator End = MRI.use_nodbg_end();
-  for (use_iterator I = MRI.use_nodbg_begin(Reg); I != End; ++I) {
-    MachineInstr *UseI = I->getParent();
-    if (!InstrExec.count(UseI))
-      continue;
-    if (UseI->isPHI())
-      visitPHI(*UseI);
-    else if (!UseI->isBranch())
-      visitNonBranch(*UseI);
-    else
-      visitBranchesFrom(*UseI);
-  }
+  for (MachineInstr &UseI : MRI.use_nodbg_instructions(Reg))
+    UseQ.push(&UseI);
 }
 
 BT::RegisterCell BT::get(RegisterRef RR) const {
@@ -992,8 +1002,8 @@ void BT::subst(RegisterRef OldRR, RegisterRef NewRR) {
   (void)NME;
   assert((OME-OMB == NME-NMB) &&
          "Substituting registers of different lengths");
-  for (CellMapType::iterator I = Map.begin(), E = Map.end(); I != E; ++I) {
-    RegisterCell &RC = I->second;
+  for (std::pair<const unsigned, RegisterCell> &P : Map) {
+    RegisterCell &RC = P.second;
     for (uint16_t i = 0, w = RC.width(); i < w; ++i) {
       BitValue &V = RC[i];
       if (V.Type != BitValue::Ref || V.RefI.Reg != OldRR.Reg)
@@ -1020,6 +1030,8 @@ void BT::visit(const MachineInstr &MI) {
   assert(!MI.isBranch() && "Only non-branches are allowed");
   InstrExec.insert(&MI);
   visitNonBranch(MI);
+  // Make sure to flush all the pending use updates.
+  runUseQueue();
   // The call to visitNonBranch could propagate the changes until a branch
   // is actually visited. This could result in adding CFG edges to the flow
   // queue. Since the queue won't be processed, clear it.
@@ -1035,35 +1047,13 @@ void BT::reset() {
   ReachedBB.reserve(MF.size());
 }
 
-void BT::run() {
-  reset();
-  assert(FlowQ.empty());
-
-  typedef GraphTraits<const MachineFunction*> MachineFlowGraphTraits;
-  const MachineBasicBlock *Entry = MachineFlowGraphTraits::getEntryNode(&MF);
-
-  unsigned MaxBN = 0;
-  for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
-       I != E; ++I) {
-    assert(I->getNumber() >= 0 && "Disconnected block");
-    unsigned BN = I->getNumber();
-    if (BN > MaxBN)
-      MaxBN = BN;
-  }
-
-  // Keep track of visited blocks.
-  BitVector BlockScanned(MaxBN+1);
-
-  int EntryN = Entry->getNumber();
-  // Generate a fake edge to get something to start with.
-  FlowQ.push(CFGEdge(-1, EntryN));
-
+void BT::runEdgeQueue(BitVector &BlockScanned) {
   while (!FlowQ.empty()) {
     CFGEdge Edge = FlowQ.front();
     FlowQ.pop();
 
     if (EdgeExec.count(Edge))
-      continue;
+      return;
     EdgeExec.insert(Edge);
     ReachedBB.insert(Edge.second);
 
@@ -1080,7 +1070,7 @@ void BT::run() {
     // then the instructions have already been processed. Any updates to
     // the cells would now only happen through visitUsesOf...
     if (BlockScanned[Edge.second])
-      continue;
+      return;
     BlockScanned[Edge.second] = true;
 
     // Visit non-branch instructions.
@@ -1104,6 +1094,50 @@ void BT::run() {
       visitBranchesFrom(*It);
     }
   } // while (!FlowQ->empty())
+}
+
+void BT::runUseQueue() {
+  while (!UseQ.empty()) {
+    MachineInstr &UseI = *UseQ.front();
+    UseQ.pop();
+
+    if (!InstrExec.count(&UseI))
+      continue;
+    if (UseI.isPHI())
+      visitPHI(UseI);
+    else if (!UseI.isBranch())
+      visitNonBranch(UseI);
+    else
+      visitBranchesFrom(UseI);
+  }
+}
+
+void BT::run() {
+  reset();
+  assert(FlowQ.empty());
+
+  using MachineFlowGraphTraits = GraphTraits<const MachineFunction*>;
+  const MachineBasicBlock *Entry = MachineFlowGraphTraits::getEntryNode(&MF);
+
+  unsigned MaxBN = 0;
+  for (const MachineBasicBlock &B : MF) {
+    assert(B.getNumber() >= 0 && "Disconnected block");
+    unsigned BN = B.getNumber();
+    if (BN > MaxBN)
+      MaxBN = BN;
+  }
+
+  // Keep track of visited blocks.
+  BitVector BlockScanned(MaxBN+1);
+
+  int EntryN = Entry->getNumber();
+  // Generate a fake edge to get something to start with.
+  FlowQ.push(CFGEdge(-1, EntryN));
+
+  while (!FlowQ.empty() || !UseQ.empty()) {
+    runEdgeQueue(BlockScanned);
+    runUseQueue();
+  }
 
   if (Trace)
     print_cells(dbgs() << "Cells after propagation:\n");
diff --git a/lib/Target/Hexagon/BitTracker.h b/lib/Target/Hexagon/BitTracker.h
index 7f49f430382d..5df6b61710f6 100644
--- a/lib/Target/Hexagon/BitTracker.h
+++ b/lib/Target/Hexagon/BitTracker.h
@@ -1,4 +1,4 @@
-//===--- BitTracker.h -------------------------------------------*- C++ -*-===//
+//===- BitTracker.h ---------------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -13,7 +13,6 @@
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"
-#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include <cassert>
 #include <cstdint>
@@ -24,11 +23,15 @@
 
 namespace llvm {
 
+class BitVector;
 class ConstantInt;
 class MachineRegisterInfo;
 class MachineBasicBlock;
+class MachineFunction;
 class MachineInstr;
 class raw_ostream;
+class TargetRegisterClass;
+class TargetRegisterInfo;
 
 struct BitTracker {
   struct BitRef;
@@ -38,9 +41,8 @@ struct BitTracker {
   struct RegisterCell;
   struct MachineEvaluator;
 
-  typedef SetVector<const MachineBasicBlock *> BranchTargetList;
-
-  typedef std::map<unsigned, RegisterCell> CellMapType;
+  using BranchTargetList = SetVector<const MachineBasicBlock *>;
+  using CellMapType = std::map<unsigned, RegisterCell>;
 
   BitTracker(const MachineEvaluator &E, MachineFunction &F);
   ~BitTracker();
@@ -62,23 +64,55 @@ private:
   void visitNonBranch(const MachineInstr &MI);
   void visitBranchesFrom(const MachineInstr &BI);
   void visitUsesOf(unsigned Reg);
+
+  using CFGEdge = std::pair<int, int>;
+  using EdgeSetType = std::set<CFGEdge>;
+  using InstrSetType = std::set<const MachineInstr *>;
+  using EdgeQueueType = std::queue<CFGEdge>;
+
+  // Priority queue of instructions using modified registers, ordered by
+  // their relative position in a basic block.
+  struct UseQueueType {
+    unsigned size() const {
+      return Uses.size();
+    }
+    bool empty() const {
+      return size() == 0;
+    }
+    MachineInstr *front() const {
+      return Uses.top();
+    }
+    void push(MachineInstr *MI) {
+      if (Set.insert(MI).second)
+        Uses.push(MI);
+    }
+    void pop() {
+      Set.erase(front());
+      Uses.pop();
+    }
+  private:
+    struct Cmp {
+      bool operator()(const MachineInstr *MI, const MachineInstr *MJ) const;
+    };
+    std::priority_queue<MachineInstr*, std::vector<MachineInstr*>, Cmp> Uses;
+    DenseSet<MachineInstr*> Set; // Set to avoid adding duplicate entries.
+  };
+
   void reset();
+  void runEdgeQueue(BitVector &BlockScanned);
+  void runUseQueue();
 
-  typedef std::pair<int,int> CFGEdge;
-  typedef std::set<CFGEdge> EdgeSetType;
-  typedef std::set<const MachineInstr *> InstrSetType;
-  typedef std::queue<CFGEdge> EdgeQueueType;
+  const MachineEvaluator &ME;
+  MachineFunction &MF;
+  MachineRegisterInfo &MRI;
+  CellMapType &Map;
 
   EdgeSetType EdgeExec;         // Executable flow graph edges.
   InstrSetType InstrExec;       // Executable instructions.
+  UseQueueType UseQ;            // Work queue of register uses.
   EdgeQueueType FlowQ;          // Work queue of CFG edges.
   DenseSet<unsigned> ReachedBB; // Cache of reached blocks.
   bool Trace;                   // Enable tracing for debugging.
-
-  const MachineEvaluator &ME;
-  MachineFunction &MF;
-  MachineRegisterInfo &MRI;
-  CellMapType &Map;
 };
 
 // Abstraction of a reference to bit at position Pos from a register Reg.
@@ -301,7 +335,7 @@ private:
   // The DefaultBitN is here only to avoid frequent reallocation of the
   // memory in the vector.
   static const unsigned DefaultBitN = 32;
-  typedef SmallVector<BitValue, DefaultBitN> BitValueList;
+  using BitValueList = SmallVector<BitValue, DefaultBitN>;
   BitValueList Bits;
 
   friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
@@ -434,6 +468,16 @@ struct BitTracker::MachineEvaluator {
   // has been successfully computed, "false" otherwise.
   virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
                         BranchTargetList &Targets, bool &FallsThru) const = 0;
+  // Given a register class RC, return a register class that should be assumed
+  // when a register from class RC is used with a subregister of index Idx.
+  virtual const TargetRegisterClass&
+  composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const {
+    if (Idx == 0)
+      return RC;
+    llvm_unreachable("Unimplemented composeWithSubRegIndex");
+  }
+  // Return the size in bits of the physical register Reg.
+  virtual uint16_t getPhysRegBitWidth(unsigned Reg) const;
 
   const TargetRegisterInfo &TRI;
   MachineRegisterInfo &MRI;
diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt
index 2f3dd3326fcc..1c36093923ac 100644
--- a/lib/Target/Hexagon/CMakeLists.txt
+++ b/lib/Target/Hexagon/CMakeLists.txt
@@ -20,12 +20,14 @@ add_llvm_target(HexagonCodeGen
   HexagonBranchRelaxation.cpp
   HexagonCFGOptimizer.cpp
   HexagonCommonGEP.cpp
+  HexagonConstExtenders.cpp
   HexagonConstPropagation.cpp
   HexagonCopyToCombine.cpp
   HexagonEarlyIfConv.cpp
   HexagonExpandCondsets.cpp
   HexagonFixupHwLoops.cpp
   HexagonFrameLowering.cpp
+  HexagonGatherPacketize.cpp
   HexagonGenExtract.cpp
   HexagonGenInsert.cpp
   HexagonGenMux.cpp
@@ -34,7 +36,9 @@ add_llvm_target(HexagonCodeGen
   HexagonHazardRecognizer.cpp
   HexagonInstrInfo.cpp
   HexagonISelDAGToDAG.cpp
+  HexagonISelDAGToDAGHVX.cpp
   HexagonISelLowering.cpp
+  HexagonISelLoweringHVX.cpp
   HexagonLoopIdiomRecognition.cpp
   HexagonMachineFunctionInfo.cpp
   HexagonMachineScheduler.cpp
@@ -53,6 +57,7 @@ add_llvm_target(HexagonCodeGen
   HexagonTargetMachine.cpp
   HexagonTargetObjectFile.cpp
   HexagonTargetTransformInfo.cpp
+  HexagonVectorLoopCarriedReuse.cpp
   HexagonVectorPrint.cpp
   HexagonVLIWPacketizer.cpp
   RDFCopy.cpp
@@ -66,3 +71,4 @@ add_subdirectory(AsmParser)
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(Disassembler)
+
diff --git a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index 586220dfec26..481b692ae8bf 100644
--- a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -1,4 +1,4 @@
-//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
+//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -24,6 +24,7 @@
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Endian.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
@@ -35,7 +36,7 @@
 using namespace llvm;
 using namespace Hexagon;
 
-typedef MCDisassembler::DecodeStatus DecodeStatus;
+using DecodeStatus = MCDisassembler::DecodeStatus;
 
 namespace {
 
@@ -44,10 +45,12 @@ class HexagonDisassembler : public MCDisassembler {
 public:
   std::unique_ptr<MCInstrInfo const> const MCII;
   std::unique_ptr<MCInst *> CurrentBundle;
+  mutable MCInst const *CurrentExtender;
 
   HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
                       MCInstrInfo const *MCII)
-      : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {}
+      : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
+        CurrentExtender(nullptr) {}
 
   DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
                                     ArrayRef<uint8_t> Bytes, uint64_t Address,
@@ -57,39 +60,38 @@ public:
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
                               raw_ostream &VStream,
                               raw_ostream &CStream) const override;
-  void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const;
+  void remapInstruction(MCInst &Instr) const;
 };
 
-namespace {
-  uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI,
-                     int64_t Value) {
-    MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex(
-      MCB, HexagonMCInstrInfo::bundleSize(MCB));
-    if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
-      return Value;
-    unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
-    uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
-    int64_t Bits;
-    bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits);
-    assert(Success); (void)Success;
-    uint32_t Upper26 = static_cast<uint32_t>(Bits);
-    uint32_t Operand = Upper26 | Lower6;
-    return Operand;
-  }
-  HexagonDisassembler const &disassembler(void const *Decoder) {
-    return *static_cast<HexagonDisassembler const *>(Decoder);
-  }
-  template <size_t T>
-  void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
-    HexagonDisassembler const &Disassembler = disassembler(Decoder);
-    int64_t FullValue =
-        fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI,
-                  SignExtend64<T>(tmp));
-    int64_t Extended = SignExtend64<32>(FullValue);
-    HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
-  }
+static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
+                          int64_t Value) {
+  MCInstrInfo MCII = *Disassembler.MCII;
+  if (!Disassembler.CurrentExtender ||
+      MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
+    return Value;
+  unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
+  uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
+  int64_t Bits;
+  bool Success =
+      Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
+          Bits);
+  assert(Success);
+  (void)Success;
+  uint64_t Upper26 = static_cast<uint64_t>(Bits);
+  uint64_t Operand = Upper26 | Lower6;
+  return Operand;
+}
+static HexagonDisassembler const &disassembler(void const *Decoder) {
+  return *static_cast<HexagonDisassembler const *>(Decoder);
+}
+template <size_t T>
+static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
+  HexagonDisassembler const &Disassembler = disassembler(Decoder);
+  int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
+  int64_t Extended = SignExtend64<32>(FullValue);
+  HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
+}
 }
-} // end anonymous namespace
 
 // Forward declare these because the auto-generated code will reference them.
 // Definitions are further down.
@@ -104,24 +106,24 @@ static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst,
 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
                                                    uint64_t Address,
                                                    const void *Decoder);
-static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                  uint64_t Address,
-                                                  const void *Decoder);
+static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t Address,
+                                             const void *Decoder);
 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                   uint64_t Address,
                                                   const void *Decoder);
 static DecodeStatus
 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                          uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                  uint64_t Address,
-                                                  const void *Decoder);
+static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t Address,
+                                             const void *Decoder);
 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                 uint64_t Address,
                                                 const void *Decoder);
-static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                   uint64_t Address,
-                                                   const void *Decoder);
+static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t Address,
+                                             const void *Decoder);
 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
                                                const void *Decoder);
@@ -136,24 +138,64 @@ static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
                                        uint64_t Address, const void *Decoder);
 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
                                     uint64_t /*Address*/, const void *Decoder);
-static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
-                                 const void *Decoder);
-static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
-                                   const void *Decoder);
-static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
-                                   const void *Decoder);
-static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
-                                   const void *Decoder);
-static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
-                                   const void *Decoder);
-static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
-                                   const void *Decoder);
-static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
-                                   const void *Decoder);
 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
                                     const void *Decoder);
 
-#include "HexagonDepDecoders.h"
+static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const void *Decoder) {
+  signedDecoder<4>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
+static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                    const void *Decoder) {
+  signedDecoder<14>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
+static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const void *Decoder) {
+  signedDecoder<8>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
+static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const void *Decoder) {
+  signedDecoder<7>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
+static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                    const void *Decoder) {
+  signedDecoder<12>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
+static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const void *Decoder) {
+  signedDecoder<3>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
+static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                    const void *Decoder) {
+  signedDecoder<13>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
+static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const void *Decoder) {
+  signedDecoder<6>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
+static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const void *Decoder) {
+  signedDecoder<9>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
+static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const void *Decoder) {
+  signedDecoder<5>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
+static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const void *Decoder) {
+  signedDecoder<6>(MI, tmp, Decoder);
+  return MCDisassembler::Success;
+}
 #include "HexagonGenDisassemblerTables.inc"
 
 static MCDisassembler *createHexagonDisassembler(const Target &T,
@@ -177,7 +219,8 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
   Size = 0;
 
   *CurrentBundle = &MI;
-  MI = HexagonMCInstrInfo::createBundle();
+  MI.setOpcode(Hexagon::BUNDLE);
+  MI.addOperand(MCOperand::createImm(0));
   while (Result == Success && !Complete) {
     if (Bytes.size() < HEXAGON_INSTR_SIZE)
       return MCDisassembler::Fail;
@@ -195,11 +238,90 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                            *getContext().getRegisterInfo(), false);
   if (!Checker.check())
     return MCDisassembler::Fail;
+  remapInstruction(MI);
   return MCDisassembler::Success;
 }
 
-namespace {
-void adjustDuplex(MCInst &MI, MCContext &Context) {
+void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
+  for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
+    auto &MI = const_cast<MCInst &>(*I.getInst());
+    switch (MI.getOpcode()) {
+    case Hexagon::S2_allocframe:
+      if (MI.getOperand(0).getReg() == Hexagon::R29) {
+        MI.setOpcode(Hexagon::S6_allocframe_to_raw);
+        MI.erase(MI.begin () + 1);
+        MI.erase(MI.begin ());
+      }
+      break;
+    case Hexagon::L2_deallocframe:
+      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+          MI.getOperand(1).getReg() == Hexagon::R30) {
+        MI.setOpcode(L6_deallocframe_map_to_raw);
+        MI.erase(MI.begin () + 1);
+        MI.erase(MI.begin ());
+      }
+      break;
+    case Hexagon::L4_return:
+      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+          MI.getOperand(1).getReg() == Hexagon::R30) {
+        MI.setOpcode(L6_return_map_to_raw);
+        MI.erase(MI.begin () + 1);
+        MI.erase(MI.begin ());
+      }
+      break;
+    case Hexagon::L4_return_t:
+      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+          MI.getOperand(2).getReg() == Hexagon::R30) {
+        MI.setOpcode(L4_return_map_to_raw_t);
+        MI.erase(MI.begin () + 2);
+        MI.erase(MI.begin ());
+      }
+      break;
+    case Hexagon::L4_return_f:
+      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+          MI.getOperand(2).getReg() == Hexagon::R30) {
+        MI.setOpcode(L4_return_map_to_raw_f);
+        MI.erase(MI.begin () + 2);
+        MI.erase(MI.begin ());
+      }
+      break;
+    case Hexagon::L4_return_tnew_pt:
+      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+          MI.getOperand(2).getReg() == Hexagon::R30) {
+        MI.setOpcode(L4_return_map_to_raw_tnew_pt);
+        MI.erase(MI.begin () + 2);
+        MI.erase(MI.begin ());
+      }
+      break;
+    case Hexagon::L4_return_fnew_pt:
+      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+          MI.getOperand(2).getReg() == Hexagon::R30) {
+        MI.setOpcode(L4_return_map_to_raw_fnew_pt);
+        MI.erase(MI.begin () + 2);
+        MI.erase(MI.begin ());
+      }
+      break;
+    case Hexagon::L4_return_tnew_pnt:
+      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+          MI.getOperand(2).getReg() == Hexagon::R30) {
+        MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
+        MI.erase(MI.begin () + 2);
+        MI.erase(MI.begin ());
+      }
+      break;
+    case Hexagon::L4_return_fnew_pnt:
+      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+          MI.getOperand(2).getReg() == Hexagon::R30) {
+        MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
+        MI.erase(MI.begin () + 2);
+        MI.erase(MI.begin ());
+      }
+      break;
+    }
+  }
+}
+
+static void adjustDuplex(MCInst &MI, MCContext &Context) {
   switch (MI.getOpcode()) {
   case Hexagon::SA1_setin1:
     MI.insert(MI.begin() + 1,
@@ -213,7 +335,6 @@ void adjustDuplex(MCInst &MI, MCContext &Context) {
     break;
   }
 }
-}
 
 DecodeStatus HexagonDisassembler::getSingleInstruction(
     MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
@@ -233,7 +354,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(
       return DecodeStatus::Fail;
   }
 
-  MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex(
+  CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
       MCB, HexagonMCInstrInfo::bundleSize(MCB));
 
   DecodeStatus Result = DecodeStatus::Fail;
@@ -309,8 +430,12 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(
     MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
     MCInst *MILow = new (getContext()) MCInst;
     MCInst *MIHigh = new (getContext()) MCInst;
+    auto TmpExtender = CurrentExtender;
+    CurrentExtender =
+        nullptr; // constant extenders in duplex must always be in slot 1
     Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
                                this, STI);
+    CurrentExtender = TmpExtender;
     if (Result != DecodeStatus::Success)
       return DecodeStatus::Fail;
     adjustDuplex(*MILow, getContext());
@@ -329,7 +454,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(
         HexagonII::INST_PARSE_PACKET_END)
       Complete = true;
 
-    if (Extender != nullptr)
+    if (CurrentExtender != nullptr)
       Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
                                  Address, this, STI);
 
@@ -388,25 +513,29 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(
     unsigned Lookback = (Register & 0x6) >> 1;
     unsigned Offset = 1;
     bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
+    bool PrevVector = false;
     auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
     auto i = Instructions.end() - 1;
     for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
       if (i == n)
         // Couldn't find producer
         return MCDisassembler::Fail;
-      if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst()))
+      bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
+      if (Vector && !CurrentVector)
         // Skip scalars when calculating distances for vectors
         ++Lookback;
-      if (HexagonMCInstrInfo::isImmext(*i->getInst()))
+      if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
         ++Lookback;
+      PrevVector = CurrentVector;
       if (Offset == Lookback)
         break;
     }
     auto const &Inst = *i->getInst();
     bool SubregBit = (Register & 0x1) != 0;
-    if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
+    if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
       // If subreg bit is set we're selecting the second produced newvalue
-      unsigned Producer =
+      unsigned Producer = SubregBit ?
+          HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() :
           HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
       assert(Producer != Hexagon::NoRegister);
       MCO.setReg(Producer);
@@ -425,7 +554,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(
       return MCDisassembler::Fail;
   }
 
-  if (Extender != nullptr) {
+  if (CurrentExtender != nullptr) {
     MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
                              ? *MI.getOperand(1).getInst()
                              : MI;
@@ -481,10 +610,10 @@ static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst,
   return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
 }
 
-static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                  uint64_t /*Address*/,
-                                                  const void *Decoder) {
-  static const MCPhysReg VecRegDecoderTable[] = {
+static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t /*Address*/,
+                                             const void *Decoder) {
+  static const MCPhysReg HvxVRDecoderTable[] = {
       Hexagon::V0,  Hexagon::V1,  Hexagon::V2,  Hexagon::V3,  Hexagon::V4,
       Hexagon::V5,  Hexagon::V6,  Hexagon::V7,  Hexagon::V8,  Hexagon::V9,
       Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
@@ -493,7 +622,7 @@ static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
       Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
       Hexagon::V30, Hexagon::V31};
 
-  return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable);
+  return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
 }
 
 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
@@ -517,16 +646,16 @@ static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(
   return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
 }
 
-static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                  uint64_t /*Address*/,
-                                                  const void *Decoder) {
-  static const MCPhysReg VecDblRegDecoderTable[] = {
+static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t /*Address*/,
+                                             const void *Decoder) {
+  static const MCPhysReg HvxWRDecoderTable[] = {
       Hexagon::W0,  Hexagon::W1,  Hexagon::W2,  Hexagon::W3,
       Hexagon::W4,  Hexagon::W5,  Hexagon::W6,  Hexagon::W7,
       Hexagon::W8,  Hexagon::W9,  Hexagon::W10, Hexagon::W11,
       Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15};
 
-  return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable));
+  return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable));
 }
 
 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
@@ -538,19 +667,20 @@ static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
   return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
 }
 
-static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                   uint64_t /*Address*/,
-                                                   const void *Decoder) {
-  static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
-                                                     Hexagon::Q2, Hexagon::Q3};
+static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t /*Address*/,
+                                             const void *Decoder) {
+  static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
+                                                Hexagon::Q2, Hexagon::Q3};
 
-  return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable);
+  return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
 }
 
 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t /*Address*/,
                                                const void *Decoder) {
   using namespace Hexagon;
+
   static const MCPhysReg CtrlRegDecoderTable[] = {
     /*  0 */  SA0,        LC0,        SA1,        LC1,
     /*  4 */  P3_0,       C5,         M0,         M1,
@@ -578,6 +708,7 @@ static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
                                                  uint64_t /*Address*/,
                                                  const void *Decoder) {
   using namespace Hexagon;
+
   static const MCPhysReg CtrlReg64DecoderTable[] = {
     /*  0 */  C1_0,       0,          C3_2,       0,
     /*  4 */  C5_4,       0,          C7_6,       0,
@@ -623,8 +754,7 @@ static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
                                        uint64_t /*Address*/,
                                        const void *Decoder) {
   HexagonDisassembler const &Disassembler = disassembler(Decoder);
-  int64_t FullValue =
-      fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, tmp);
+  int64_t FullValue = fullValue(Disassembler, MI, tmp);
   assert(FullValue >= 0 && "Negative in unsigned decoder");
   HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
   return MCDisassembler::Success;
@@ -647,13 +777,9 @@ static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
   // r13_2 is not extendable, so if there are no extent bits, it's r13_2
   if (Bits == 0)
     Bits = 15;
-  uint32_t FullValue =
-      fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI,
-                SignExtend64(tmp, Bits));
-  int64_t Extended = SignExtend64<32>(FullValue) + Address;
+  uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
+  uint32_t Extended = FullValue + Address;
   if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4))
     HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
   return MCDisassembler::Success;
 }
-
-
diff --git a/lib/Target/Hexagon/Hexagon.h b/lib/Target/Hexagon/Hexagon.h
index ed7d9578902e..66b387b62c6c 100644
--- a/lib/Target/Hexagon/Hexagon.h
+++ b/lib/Target/Hexagon/Hexagon.h
@@ -43,7 +43,7 @@
 #define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"
 
 #include "MCTargetDesc/HexagonMCTargetDesc.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td
index 4767165141a3..6292e2a7a4ea 100644
--- a/lib/Target/Hexagon/Hexagon.td
+++ b/lib/Target/Hexagon/Hexagon.td
@@ -25,12 +25,36 @@ include "llvm/Target/Target.td"
 include "HexagonDepArch.td"
 
 // Hexagon ISA Extensions
-def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true",
-      "Hexagon HVX instructions">;
-def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true",
-      "Hexagon HVX Double instructions">;
+def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
+      "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
+def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
+      "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
+      [ExtensionHVX]>;
+def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
+      "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
+      [ExtensionHVX,ExtensionHVXV60]>;
+def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
+      "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
+      [ExtensionHVX,ExtensionHVXV60, ExtensionHVXV62]>;
+def ExtensionHVX64B
+    : SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true",
+                       "Hexagon HVX 64B instructions", [ExtensionHVX]>;
+def ExtensionHVX128B
+    : SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true",
+                       "Hexagon HVX 128B instructions", [ExtensionHVX]>;
+
+// This is an alias to ExtensionHVX128B to accept the hvx-double as
+// an acceptable subtarget feature.
+def ExtensionHVXDbl
+    : SubtargetFeature<"hvx-double", "UseHVX128BOps", "true",
+                       "Hexagon HVX 128B instructions", [ExtensionHVX128B]>;
+
 def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
       "Use constant-extended calls">;
+def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
+      "Supports mem_noshuf feature">;
+def FeatureDuplex : SubtargetFeature<"duplex", "EnableDuplex", "true",
+      "Enable generation of duplex instruction">;
 
 //===----------------------------------------------------------------------===//
 // Hexagon Instruction Predicate Definitions.
@@ -38,32 +62,45 @@ def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
 
 def UseMEMOP           : Predicate<"HST->useMemOps()">;
 def IEEERndNearV5T     : Predicate<"HST->modeIEEERndNear()">;
-def UseHVXDbl          : Predicate<"HST->useHVXDblOps()">,
-                         AssemblerPredicate<"ExtensionHVXDbl">;
-def UseHVXSgl          : Predicate<"HST->useHVXSglOps()">;
-def UseHVX             : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">,
-                         AssemblerPredicate<"ExtensionHVX">;
+def UseHVX64B          : Predicate<"HST->useHVX64BOps()">,
+                         AssemblerPredicate<"ExtensionHVX64B">;
+def UseHVX128B         : Predicate<"HST->useHVX128BOps()">,
+                         AssemblerPredicate<"ExtensionHVX128B">;
+def UseHVX             : Predicate<"HST->useHVXOps()">,
+                         AssemblerPredicate<"ExtensionHVXV60">;
+def UseHVXV60          : Predicate<"HST->useHVXOps()">,
+                         AssemblerPredicate<"ExtensionHVXV60">;
+def UseHVXV62          : Predicate<"HST->useHVXOps()">,
+                         AssemblerPredicate<"ExtensionHVXV62">;
+def UseHVXV65          : Predicate<"HST->useHVXOps()">,
+                         AssemblerPredicate<"ExtensionHVXV65">;
+
+def Hvx64     : HwMode<"+hvx-length64b">;
+def Hvx64old  : HwMode<"-hvx-double">;
+def Hvx128    : HwMode<"+hvx-length128b">;
+def Hvx128old : HwMode<"+hvx-double">;
 
 //===----------------------------------------------------------------------===//
 // Classes used for relation maps.
 //===----------------------------------------------------------------------===//
 
 class ImmRegShl;
+// ImmRegRel - Filter class used to relate instructions having reg-reg form
+// with their reg-imm counterparts.
+class ImmRegRel;
 // PredRel - Filter class used to relate non-predicated instructions with their
 // predicated forms.
 class PredRel;
 // PredNewRel - Filter class used to relate predicated instructions with their
 // predicate-new forms.
 class PredNewRel: PredRel;
-// ImmRegRel - Filter class used to relate instructions having reg-reg form
-// with their reg-imm counterparts.
-class ImmRegRel;
 // NewValueRel - Filter class used to relate regular store instructions with
 // their new-value store form.
 class NewValueRel: PredNewRel;
 // NewValueRel - Filter class used to relate load/store instructions having
 // different addressing modes with each other.
 class AddrModeRel: NewValueRel;
+class PostInc_BaseImm;
 class IntrinsicsRel;
 
 //===----------------------------------------------------------------------===//
@@ -155,7 +192,7 @@ def getNonNVStore : InstrMapping {
   let ValueCols = [["false"]];
 }
 
-def getBaseWithImmOffset : InstrMapping {
+def changeAddrMode_abs_io: InstrMapping {
   let FilterClass = "AddrModeRel";
   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
                    "isFloat"];
@@ -164,7 +201,7 @@ def getBaseWithImmOffset : InstrMapping {
   let ValueCols = [["BaseImmOffset"]];
 }
 
-def getAbsoluteForm : InstrMapping {
+def changeAddrMode_io_abs: InstrMapping {
   let FilterClass = "AddrModeRel";
   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
                    "isFloat"];
@@ -173,7 +210,7 @@ def getAbsoluteForm : InstrMapping {
   let ValueCols = [["Absolute"]];
 }
 
-def getBaseWithRegOffset : InstrMapping {
+def changeAddrMode_io_rr: InstrMapping {
   let FilterClass = "AddrModeRel";
   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
   let ColFields = ["addrMode"];
@@ -181,7 +218,7 @@ def getBaseWithRegOffset : InstrMapping {
   let ValueCols = [["BaseRegOffset"]];
 }
 
-def xformRegToImmOffset : InstrMapping {
+def changeAddrMode_rr_io: InstrMapping {
   let FilterClass = "AddrModeRel";
   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
   let ColFields = ["addrMode"];
@@ -189,7 +226,23 @@ def xformRegToImmOffset : InstrMapping {
   let ValueCols = [["BaseImmOffset"]];
 }
 
-def getBaseWithLongOffset : InstrMapping {
+def changeAddrMode_pi_io: InstrMapping {
+  let FilterClass = "PostInc_BaseImm";
+  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
+  let ColFields = ["addrMode"];
+  let KeyCol = ["PostInc"];
+  let ValueCols = [["BaseImmOffset"]];
+}
+
+def changeAddrMode_io_pi: InstrMapping {
+  let FilterClass = "PostInc_BaseImm";
+  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
+  let ColFields = ["addrMode"];
+  let KeyCol = ["BaseImmOffset"];
+  let ValueCols = [["PostInc"]];
+}
+
+def changeAddrMode_rr_ur: InstrMapping {
   let FilterClass = "ImmRegShl";
   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
   let ColFields = ["addrMode"];
@@ -197,6 +250,14 @@ def getBaseWithLongOffset : InstrMapping {
   let ValueCols = [["BaseLongOffset"]];
 }
 
+def changeAddrMode_ur_rr : InstrMapping {
+  let FilterClass = "ImmRegShl";
+  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
+  let ColFields = ["addrMode"];
+  let KeyCol = ["BaseLongOffset"];
+  let ValueCols = [["BaseRegOffset"]];
+}
+
 def getRegForm : InstrMapping {
   let FilterClass = "ImmRegRel";
   let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
@@ -205,14 +266,6 @@ def getRegForm : InstrMapping {
   let ValueCols = [["reg"]];
 }
 
-def getRegShlForm : InstrMapping {
-  let FilterClass = "ImmRegShl";
-  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
-  let ColFields = ["InputType"];
-  let KeyCol = ["imm"];
-  let ValueCols = [["reg"]];
-}
-
 def notTakenBranchPrediction : InstrMapping {
   let FilterClass = "PredRel";
   let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
@@ -237,7 +290,7 @@ def getRealHWInstr : InstrMapping {
   let ValueCols = [["Pseudo"], ["Real"]];
 }
 //===----------------------------------------------------------------------===//
-// Register File, Calling Conv, Instruction Descriptions
+// Register File, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 include "HexagonSchedule.td"
 include "HexagonRegisterInfo.td"
@@ -249,10 +302,11 @@ include "HexagonDepInstrFormats.td"
 include "HexagonDepInstrInfo.td"
 include "HexagonPseudo.td"
 include "HexagonPatterns.td"
+include "HexagonPatternsV65.td"
 include "HexagonDepMappings.td"
 include "HexagonIntrinsics.td"
-include "HexagonIntrinsicsDerived.td"
 include "HexagonMapAsm2IntrinV62.gen.td"
+include "HexagonMapAsm2IntrinV65.gen.td"
 
 def HexagonInstrInfo : InstrInfo;
 
@@ -265,15 +319,18 @@ class Proc<string Name, SchedMachineModel Model,
  : ProcessorModel<Name, Model, Features>;
 
 def : Proc<"hexagonv4",  HexagonModelV4,
-           [ArchV4]>;
+           [ArchV4, FeatureDuplex]>;
 def : Proc<"hexagonv5",  HexagonModelV4,
-           [ArchV4, ArchV5]>;
+           [ArchV4, ArchV5, FeatureDuplex]>;
 def : Proc<"hexagonv55", HexagonModelV55,
-           [ArchV4, ArchV5, ArchV55]>;
+           [ArchV4, ArchV5, ArchV55, FeatureDuplex]>;
 def : Proc<"hexagonv60", HexagonModelV60,
-           [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>;
+           [ArchV4, ArchV5, ArchV55, ArchV60, FeatureDuplex]>;
 def : Proc<"hexagonv62", HexagonModelV62,
-           [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ExtensionHVX]>;
+           [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, FeatureDuplex]>;
+def : Proc<"hexagonv65", HexagonModelV65,
+           [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
+            FeatureMemNoShuf, FeatureDuplex]>;
 
 //===----------------------------------------------------------------------===//
 // Declare the target which we are implementing
@@ -287,11 +344,17 @@ def HexagonAsmParser : AsmParser {
 def HexagonAsmParserVariant : AsmParserVariant {
   int Variant = 0;
   string TokenizingCharacters = "#()=:.<>!+*-|^&";
+  string BreakCharacters = "";
+}
+
+def HexagonAsmWriter : AsmWriter {
+  string AsmWriterClassName  = "InstPrinter";
+  bit isMCAsmWriter = 1;
 }
 
 def Hexagon : Target {
-  // Pull in Instruction Info:
   let InstructionSet = HexagonInstrInfo;
   let AssemblyParsers = [HexagonAsmParser];
   let AssemblyParserVariants = [HexagonAsmParserVariant];
+  let AssemblyWriters = [HexagonAsmWriter];
 }
diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
index e689483a0999..68b1fe6bf4b1 100644
--- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -1,4 +1,4 @@
-//===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly --===//
+//===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -15,50 +15,50 @@
 
 #include "HexagonAsmPrinter.h"
 #include "Hexagon.h"
-#include "HexagonMachineFunctionInfo.h"
+#include "HexagonInstrInfo.h"
+#include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
-#include "HexagonTargetMachine.h"
 #include "MCTargetDesc/HexagonInstPrinter.h"
+#include "MCTargetDesc/HexagonMCExpr.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
-#include "MCTargetDesc/HexagonMCShuffler.h"
+#include "MCTargetDesc/HexagonMCTargetDesc.h"
 #include "llvm/ADT/StringExtras.h"
-#include "llvm/Analysis/ConstantFolding.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/Twine.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/IR/Constants.h"
-#include "llvm/IR/DataLayout.h"
-#include "llvm/IR/DerivedTypes.h"
-#include "llvm/IR/Mangler.h"
-#include "llvm/IR/Module.h"
-#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCSection.h"
+#include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
+#include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/Format.h"
-#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <string>
 
 using namespace llvm;
 
 namespace llvm {
-  void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
-                        MCInst &MCB, HexagonAsmPrinter &AP);
-}
+
+void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
+                      MCInst &MCB, HexagonAsmPrinter &AP);
+
+} // end namespace llvm
 
 #define DEBUG_TYPE "asm-printer"
 
@@ -78,7 +78,7 @@ inline static unsigned getHexagonRegisterPair(unsigned Reg,
 
 HexagonAsmPrinter::HexagonAsmPrinter(TargetMachine &TM,
                                      std::unique_ptr<MCStreamer> Streamer)
-    : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr) {}
+    : AsmPrinter(TM, std::move(Streamer)) {}
 
 void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
                                      raw_ostream &O) {
@@ -106,14 +106,12 @@ void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
   }
 }
 
-//
 // isBlockOnlyReachableByFallthrough - We need to override this since the
 // default AsmPrinter does not print labels for any basic block that
 // is only reachable by a fall through. That works for all cases except
 // for the case in which the basic block is reachable by a fall through but
 // through an indirect from a jump table. In this case, the jump table
 // will contain a label not defined by AsmPrinter.
-//
 bool HexagonAsmPrinter::
 isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
   if (MBB->hasAddressTaken())
@@ -121,9 +119,7 @@ isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
   return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
 }
 
-
 /// PrintAsmOperand - Print out an operand for an inline asm expression.
-///
 bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                         unsigned AsmVariant,
                                         const char *ExtraCode,
@@ -285,10 +281,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   MCInst &MappedInst = static_cast <MCInst &>(Inst);
   const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
   const MachineFunction &MF = *MI.getParent()->getParent();
-  const auto &HST = MF.getSubtarget<HexagonSubtarget>();
-  const auto &VecRC = HST.useHVXSglOps() ? Hexagon::VectorRegsRegClass
-                                         : Hexagon::VectorRegs128BRegClass;
-  unsigned VectorSize = HST.getRegisterInfo()->getSpillSize(VecRC);
+  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
+  unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
 
   switch (Inst.getOpcode()) {
   default: return;
@@ -306,35 +300,30 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
     break;
   }
 
-  case Hexagon::A2_tfrf: {
+  case Hexagon::A2_tfrf:
     Inst.setOpcode(Hexagon::A2_paddif);
     Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
     break;
-  }
 
-  case Hexagon::A2_tfrt: {
+  case Hexagon::A2_tfrt:
     Inst.setOpcode(Hexagon::A2_paddit);
     Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
     break;
-  }
 
-  case Hexagon::A2_tfrfnew: {
+  case Hexagon::A2_tfrfnew:
     Inst.setOpcode(Hexagon::A2_paddifnew);
     Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
     break;
-  }
 
-  case Hexagon::A2_tfrtnew: {
+  case Hexagon::A2_tfrtnew:
     Inst.setOpcode(Hexagon::A2_padditnew);
     Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
     break;
-  }
 
-  case Hexagon::A2_zxtb: {
+  case Hexagon::A2_zxtb:
     Inst.setOpcode(Hexagon::A2_andir);
     Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, OutContext)));
     break;
-  }
 
   // "$dst = CONST64(#$src1)",
   case Hexagon::CONST64:
@@ -386,7 +375,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   // 3 register pairs.
   case Hexagon::M2_vrcmpys_acc_s1: {
     MCOperand &Rt = Inst.getOperand(3);
-    assert (Rt.isReg() && "Expected register and none was found");
+    assert(Rt.isReg() && "Expected register and none was found");
     unsigned Reg = RI->getEncodingValue(Rt.getReg());
     if (Reg & 1)
       MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
@@ -397,7 +386,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   }
   case Hexagon::M2_vrcmpys_s1: {
     MCOperand &Rt = Inst.getOperand(2);
-    assert (Rt.isReg() && "Expected register and none was found");
+    assert(Rt.isReg() && "Expected register and none was found");
     unsigned Reg = RI->getEncodingValue(Rt.getReg());
     if (Reg & 1)
       MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
@@ -409,7 +398,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
 
   case Hexagon::M2_vrcmpys_s1rp: {
     MCOperand &Rt = Inst.getOperand(2);
-    assert (Rt.isReg() && "Expected register and none was found");
+    assert(Rt.isReg() && "Expected register and none was found");
     unsigned Reg = RI->getEncodingValue(Rt.getReg());
     if (Reg & 1)
       MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
@@ -421,7 +410,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
 
   case Hexagon::A4_boundscheck: {
     MCOperand &Rs = Inst.getOperand(1);
-    assert (Rs.isReg() && "Expected register and none was found");
+    assert(Rs.isReg() && "Expected register and none was found");
     unsigned Reg = RI->getEncodingValue(Rs.getReg());
     if (Reg & 1) // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
       MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);
@@ -430,15 +419,17 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
     Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
     return;
   }
+
   case Hexagon::PS_call_nr:
     Inst.setOpcode(Hexagon::J2_call);
     break;
+
   case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
     MCOperand &MO = MappedInst.getOperand(2);
     int64_t Imm;
     MCExpr const *Expr = MO.getExpr();
     bool Success = Expr->evaluateAsAbsolute(Imm);
-    assert (Success && "Expected immediate and none was found");
+    assert(Success && "Expected immediate and none was found");
     (void)Success;
     MCInst TmpInst;
     if (Imm == 0) {
@@ -458,13 +449,14 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
     MappedInst = TmpInst;
     return;
   }
+
   case Hexagon::S5_vasrhrnd_goodsyntax:
   case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
     MCOperand &MO2 = MappedInst.getOperand(2);
     MCExpr const *Expr = MO2.getExpr();
     int64_t Imm;
     bool Success = Expr->evaluateAsAbsolute(Imm);
-    assert (Success && "Expected immediate and none was found");
+    assert(Success && "Expected immediate and none was found");
     (void)Success;
     MCInst TmpInst;
     if (Imm == 0) {
@@ -493,13 +485,14 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
     MappedInst = TmpInst;
     return;
   }
+
   // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
   case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
     MCOperand &MO = Inst.getOperand(2);
     MCExpr const *Expr = MO.getExpr();
     int64_t Imm;
     bool Success = Expr->evaluateAsAbsolute(Imm);
-    assert (Success && "Expected immediate and none was found");
+    assert(Success && "Expected immediate and none was found");
     (void)Success;
     MCInst TmpInst;
     if (Imm == 0) {
@@ -541,6 +534,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
     MappedInst = TmpInst;
     return;
   }
+
   // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
   case Hexagon::A2_tfrp: {
     MCOperand &MO = MappedInst.getOperand(1);
@@ -566,6 +560,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
                           : Hexagon::C2_ccombinewf);
     return;
   }
+
   case Hexagon::A2_tfrptnew:
   case Hexagon::A2_tfrpfnew: {
     MCOperand &MO = MappedInst.getOperand(2);
@@ -598,7 +593,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
 
   case Hexagon::A2_addsp: {
     MCOperand &Rt = Inst.getOperand(1);
-    assert (Rt.isReg() && "Expected register and none was found");
+    assert(Rt.isReg() && "Expected register and none was found");
     unsigned Reg = RI->getEncodingValue(Rt.getReg());
     if (Reg & 1)
       MappedInst.setOpcode(Hexagon::A2_addsph);
@@ -607,11 +602,11 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
     return;
   }
-  case Hexagon::V6_vd0:
-  case Hexagon::V6_vd0_128B: {
+
+  case Hexagon::V6_vd0: {
     MCInst TmpInst;
-    assert (Inst.getOperand(0).isReg() &&
-            "Expected register and none was found");
+    assert(Inst.getOperand(0).isReg() &&
+           "Expected register and none was found");
 
     TmpInst.setOpcode(Hexagon::V6_vxor);
     TmpInst.addOperand(Inst.getOperand(0));
@@ -620,7 +615,18 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
     MappedInst = TmpInst;
     return;
   }
+  case Hexagon::V6_vdd0: {
+    MCInst TmpInst;
+    assert (Inst.getOperand(0).isReg() &&
+            "Expected register and none was found");
 
+    TmpInst.setOpcode(Hexagon::V6_vsubw_dv);
+    TmpInst.addOperand(Inst.getOperand(0));
+    TmpInst.addOperand(Inst.getOperand(0));
+    TmpInst.addOperand(Inst.getOperand(0));
+    MappedInst = TmpInst;
+    return;
+  }
   case Hexagon::V6_vL32Ub_pi:
   case Hexagon::V6_vL32b_cur_pi:
   case Hexagon::V6_vL32b_nt_cur_pi:
@@ -628,13 +634,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   case Hexagon::V6_vL32b_nt_pi:
   case Hexagon::V6_vL32b_nt_tmp_pi:
   case Hexagon::V6_vL32b_tmp_pi:
-  case Hexagon::V6_vL32Ub_pi_128B:
-  case Hexagon::V6_vL32b_cur_pi_128B:
-  case Hexagon::V6_vL32b_nt_cur_pi_128B:
-  case Hexagon::V6_vL32b_pi_128B:
-  case Hexagon::V6_vL32b_nt_pi_128B:
-  case Hexagon::V6_vL32b_nt_tmp_pi_128B:
-  case Hexagon::V6_vL32b_tmp_pi_128B:
     MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
     return;
 
@@ -645,13 +644,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   case Hexagon::V6_vL32b_nt_cur_ai:
   case Hexagon::V6_vL32b_nt_tmp_ai:
   case Hexagon::V6_vL32b_tmp_ai:
-  case Hexagon::V6_vL32Ub_ai_128B:
-  case Hexagon::V6_vL32b_ai_128B:
-  case Hexagon::V6_vL32b_cur_ai_128B:
-  case Hexagon::V6_vL32b_nt_ai_128B:
-  case Hexagon::V6_vL32b_nt_cur_ai_128B:
-  case Hexagon::V6_vL32b_nt_tmp_ai_128B:
-  case Hexagon::V6_vL32b_tmp_ai_128B:
     MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
     return;
 
@@ -660,11 +652,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   case Hexagon::V6_vS32b_nt_new_pi:
   case Hexagon::V6_vS32b_nt_pi:
   case Hexagon::V6_vS32b_pi:
-  case Hexagon::V6_vS32Ub_pi_128B:
-  case Hexagon::V6_vS32b_new_pi_128B:
-  case Hexagon::V6_vS32b_nt_new_pi_128B:
-  case Hexagon::V6_vS32b_nt_pi_128B:
-  case Hexagon::V6_vS32b_pi_128B:
     MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
     return;
 
@@ -673,11 +660,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   case Hexagon::V6_vS32b_new_ai:
   case Hexagon::V6_vS32b_nt_ai:
   case Hexagon::V6_vS32b_nt_new_ai:
-  case Hexagon::V6_vS32Ub_ai_128B:
-  case Hexagon::V6_vS32b_ai_128B:
-  case Hexagon::V6_vS32b_new_ai_128B:
-  case Hexagon::V6_vS32b_nt_ai_128B:
-  case Hexagon::V6_vS32b_nt_new_ai_128B:
     MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
     return;
 
@@ -693,18 +675,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   case Hexagon::V6_vL32b_pred_pi:
   case Hexagon::V6_vL32b_tmp_npred_pi:
   case Hexagon::V6_vL32b_tmp_pred_pi:
-  case Hexagon::V6_vL32b_cur_npred_pi_128B:
-  case Hexagon::V6_vL32b_cur_pred_pi_128B:
-  case Hexagon::V6_vL32b_npred_pi_128B:
-  case Hexagon::V6_vL32b_nt_cur_npred_pi_128B:
-  case Hexagon::V6_vL32b_nt_cur_pred_pi_128B:
-  case Hexagon::V6_vL32b_nt_npred_pi_128B:
-  case Hexagon::V6_vL32b_nt_pred_pi_128B:
-  case Hexagon::V6_vL32b_nt_tmp_npred_pi_128B:
-  case Hexagon::V6_vL32b_nt_tmp_pred_pi_128B:
-  case Hexagon::V6_vL32b_pred_pi_128B:
-  case Hexagon::V6_vL32b_tmp_npred_pi_128B:
-  case Hexagon::V6_vL32b_tmp_pred_pi_128B:
     MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext);
     return;
 
@@ -720,18 +690,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   case Hexagon::V6_vL32b_pred_ai:
   case Hexagon::V6_vL32b_tmp_npred_ai:
   case Hexagon::V6_vL32b_tmp_pred_ai:
-  case Hexagon::V6_vL32b_cur_npred_ai_128B:
-  case Hexagon::V6_vL32b_cur_pred_ai_128B:
-  case Hexagon::V6_vL32b_npred_ai_128B:
-  case Hexagon::V6_vL32b_nt_cur_npred_ai_128B:
-  case Hexagon::V6_vL32b_nt_cur_pred_ai_128B:
-  case Hexagon::V6_vL32b_nt_npred_ai_128B:
-  case Hexagon::V6_vL32b_nt_pred_ai_128B:
-  case Hexagon::V6_vL32b_nt_tmp_npred_ai_128B:
-  case Hexagon::V6_vL32b_nt_tmp_pred_ai_128B:
-  case Hexagon::V6_vL32b_pred_ai_128B:
-  case Hexagon::V6_vL32b_tmp_npred_ai_128B:
-  case Hexagon::V6_vL32b_tmp_pred_ai_128B:
     MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
     return;
 
@@ -749,20 +707,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   case Hexagon::V6_vS32b_nt_qpred_pi:
   case Hexagon::V6_vS32b_pred_pi:
   case Hexagon::V6_vS32b_qpred_pi:
-  case Hexagon::V6_vS32Ub_npred_pi_128B:
-  case Hexagon::V6_vS32Ub_pred_pi_128B:
-  case Hexagon::V6_vS32b_new_npred_pi_128B:
-  case Hexagon::V6_vS32b_new_pred_pi_128B:
-  case Hexagon::V6_vS32b_npred_pi_128B:
-  case Hexagon::V6_vS32b_nqpred_pi_128B:
-  case Hexagon::V6_vS32b_nt_new_npred_pi_128B:
-  case Hexagon::V6_vS32b_nt_new_pred_pi_128B:
-  case Hexagon::V6_vS32b_nt_npred_pi_128B:
-  case Hexagon::V6_vS32b_nt_nqpred_pi_128B:
-  case Hexagon::V6_vS32b_nt_pred_pi_128B:
-  case Hexagon::V6_vS32b_nt_qpred_pi_128B:
-  case Hexagon::V6_vS32b_pred_pi_128B:
-  case Hexagon::V6_vS32b_qpred_pi_128B:
     MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
     return;
 
@@ -780,31 +724,27 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
   case Hexagon::V6_vS32b_nt_qpred_ai:
   case Hexagon::V6_vS32b_pred_ai:
   case Hexagon::V6_vS32b_qpred_ai:
-  case Hexagon::V6_vS32Ub_npred_ai_128B:
-  case Hexagon::V6_vS32Ub_pred_ai_128B:
-  case Hexagon::V6_vS32b_new_npred_ai_128B:
-  case Hexagon::V6_vS32b_new_pred_ai_128B:
-  case Hexagon::V6_vS32b_npred_ai_128B:
-  case Hexagon::V6_vS32b_nqpred_ai_128B:
-  case Hexagon::V6_vS32b_nt_new_npred_ai_128B:
-  case Hexagon::V6_vS32b_nt_new_pred_ai_128B:
-  case Hexagon::V6_vS32b_nt_npred_ai_128B:
-  case Hexagon::V6_vS32b_nt_nqpred_ai_128B:
-  case Hexagon::V6_vS32b_nt_pred_ai_128B:
-  case Hexagon::V6_vS32b_nt_qpred_ai_128B:
-  case Hexagon::V6_vS32b_pred_ai_128B:
-  case Hexagon::V6_vS32b_qpred_ai_128B:
     MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
     return;
+
+  // V65+
+  case Hexagon::V6_vS32b_srls_ai:
+    MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
+    return;
+
+  case Hexagon::V6_vS32b_srls_pi:
+    MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
+    return;
+
   }
 }
 
-
 /// printMachineInstruction -- Print out a single Hexagon MI in Darwin syntax to
 /// the current output stream.
-///
 void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
-  MCInst MCB = HexagonMCInstrInfo::createBundle();
+  MCInst MCB;
+  MCB.setOpcode(Hexagon::BUNDLE);
+  MCB.addOperand(MCOperand::createImm(0));
   const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
 
   if (MI->isBundle()) {
diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.h b/lib/Target/Hexagon/HexagonAsmPrinter.h
index 775da03e0f8c..4b8865672cf4 100755
--- a/lib/Target/Hexagon/HexagonAsmPrinter.h
+++ b/lib/Target/Hexagon/HexagonAsmPrinter.h
@@ -1,4 +1,4 @@
-//===-- HexagonAsmPrinter.h - Print machine code to an Hexagon .s file ----===//
+//===- HexagonAsmPrinter.h - Print machine code to an Hexagon .s file -----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -15,14 +15,20 @@
 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONASMPRINTER_H
 
 #include "Hexagon.h"
-#include "HexagonTargetMachine.h"
+#include "HexagonSubtarget.h"
 #include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Support/raw_ostream.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include <memory>
 
 namespace llvm {
+
+class MachineInstr;
+class MCInst;
+class raw_ostream;
+class TargetMachine;
+
   class HexagonAsmPrinter : public AsmPrinter {
-    const HexagonSubtarget *Subtarget;
+    const HexagonSubtarget *Subtarget = nullptr;
 
   public:
     explicit HexagonAsmPrinter(TargetMachine &TM,
@@ -45,7 +51,6 @@ namespace llvm {
     void HexagonProcessInstruction(MCInst &Inst,
                                    const MachineInstr &MBB);
 
-
     void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          unsigned AsmVariant, const char *ExtraCode,
@@ -57,6 +62,6 @@ namespace llvm {
     static const char *getRegisterName(unsigned RegNo);
   };
 
-} // end of llvm namespace
+} // end namespace llvm
 
-#endif
+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONASMPRINTER_H
diff --git a/lib/Target/Hexagon/HexagonBitSimplify.cpp b/lib/Target/Hexagon/HexagonBitSimplify.cpp
index d75d95a6baea..9e73766b6fdc 100644
--- a/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonBitSimplify.cpp -------------------------------------------===//
+//===- HexagonBitSimplify.cpp ---------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,10 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "BitTracker.h"
 #include "HexagonBitTracker.h"
-#include "HexagonTargetMachine.h"
+#include "HexagonInstrInfo.h"
+#include "HexagonRegisterInfo.h"
+#include "HexagonSubtarget.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
@@ -22,16 +26,16 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
@@ -52,10 +56,10 @@ static cl::opt<bool> GenBitSplit("hexbit-bitsplit", cl::Hidden,
   cl::init(true), cl::desc("Generate bitsplit instructions"));
 
 static cl::opt<unsigned> MaxExtract("hexbit-max-extract", cl::Hidden,
-  cl::init(UINT_MAX));
+  cl::init(std::numeric_limits<unsigned>::max()));
 static unsigned CountExtract = 0;
 static cl::opt<unsigned> MaxBitSplit("hexbit-max-bitsplit", cl::Hidden,
-  cl::init(UINT_MAX));
+  cl::init(std::numeric_limits<unsigned>::max()));
 static unsigned CountBitSplit = 0;
 
 namespace llvm {
@@ -169,7 +173,7 @@ namespace {
   raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) {
     OS << '{';
     for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))
-      OS << ' ' << PrintReg(R, P.TRI);
+      OS << ' ' << printReg(R, P.TRI);
     OS << " }";
     return OS;
   }
@@ -180,7 +184,7 @@ namespace {
   public:
     static char ID;
 
-    HexagonBitSimplify() : MachineFunctionPass(ID), MDT(nullptr) {
+    HexagonBitSimplify() : MachineFunctionPass(ID) {
       initializeHexagonBitSimplifyPass(*PassRegistry::getPassRegistry());
     }
 
@@ -227,15 +231,14 @@ namespace {
         const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI);
 
   private:
-    MachineDominatorTree *MDT;
+    MachineDominatorTree *MDT = nullptr;
 
     bool visitBlock(MachineBasicBlock &B, Transformation &T, RegisterSet &AVs);
     static bool hasTiedUse(unsigned Reg, MachineRegisterInfo &MRI,
         unsigned NewSub = Hexagon::NoSubRegister);
   };
 
-  char HexagonBitSimplify::ID = 0;
-  typedef HexagonBitSimplify HBS;
+  using HBS = HexagonBitSimplify;
 
   // The purpose of this class is to provide a common facility to traverse
   // the function top-down or bottom-up via the dominator tree, and keep
@@ -252,6 +255,8 @@ namespace {
 
 } // end anonymous namespace
 
+char HexagonBitSimplify::ID = 0;
+
 INITIALIZE_PASS_BEGIN(HexagonBitSimplify, "hexbit",
       "Hexagon bit simplification", false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
@@ -415,8 +420,7 @@ bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
 
   switch (RC->getID()) {
     case Hexagon::DoubleRegsRegClassID:
-    case Hexagon::VecDblRegsRegClassID:
-    case Hexagon::VecDblRegs128BRegClassID:
+    case Hexagon::HvxWRRegClassID:
       Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 2;
       if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
         Begin = Width;
@@ -435,7 +439,7 @@ bool HexagonBitSimplify::parseRegSequence(const MachineInstr &I,
       const MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::REG_SEQUENCE);
   unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm();
-  auto *DstRC = MRI.getRegClass(I.getOperand(0).getReg());
+  auto &DstRC = *MRI.getRegClass(I.getOperand(0).getReg());
   auto &HRI = static_cast<const HexagonRegisterInfo&>(
                   *MRI.getTargetRegisterInfo());
   unsigned SubLo = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_lo);
@@ -891,7 +895,7 @@ bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN,
 }
 
 // Calculate the register class that matches Reg:Sub. For example, if
-// vreg1 is a double register, then vreg1:isub_hi would match the "int"
+// %1 is a double register, then %1:isub_hi would match the "int"
 // register class.
 const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
       const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) {
@@ -905,20 +909,17 @@ const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
 
   auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void {
     (void)HRI;
-    assert(Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo) ||
-           Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
+    assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) ||
+           Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_hi));
   };
 
   switch (RC->getID()) {
     case Hexagon::DoubleRegsRegClassID:
       VerifySR(RC, RR.Sub);
       return &Hexagon::IntRegsRegClass;
-    case Hexagon::VecDblRegsRegClassID:
-      VerifySR(RC, RR.Sub);
-      return &Hexagon::VectorRegsRegClass;
-    case Hexagon::VecDblRegs128BRegClassID:
+    case Hexagon::HvxWRRegClassID:
       VerifySR(RC, RR.Sub);
-      return &Hexagon::VectorRegs128BRegClass;
+      return &Hexagon::HvxVRRegClass;
   }
   return nullptr;
 }
@@ -1245,11 +1246,11 @@ bool RedundantInstrElimination::computeUsedBits(unsigned Reg, BitVector &Bits) {
 // holds the bits for the entire register. To keep track of that, the
 // argument Begin indicates where in Bits is the lowest-significant bit
 // of the register used in operand OpN. For example, in instruction:
-//   vreg1 = S2_lsr_i_r vreg2:isub_hi, 10
+//   %1 = S2_lsr_i_r %2:isub_hi, 10
 // the operand 1 is a 32-bit register, which happens to be a subregister
-// of the 64-bit register vreg2, and that subregister starts at position 32.
+// of the 64-bit register %2, and that subregister starts at position 32.
 // In this case Begin=32, since Bits[32] would be the lowest-significant bit
-// of vreg2:isub_hi.
+// of %2:isub_hi.
 bool RedundantInstrElimination::computeUsedBits(const MachineInstr &MI,
       unsigned OpN, BitVector &Bits, uint16_t Begin) {
   unsigned Opc = MI.getOpcode();
@@ -1314,7 +1315,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
 
     if (MI->getOpcode() == TargetOpcode::COPY)
       continue;
-    if (MI->hasUnmodeledSideEffects() || MI->isInlineAsm())
+    if (MI->isPHI() || MI->hasUnmodeledSideEffects() || MI->isInlineAsm())
       continue;
     unsigned NumD = MI->getDesc().getNumDefs();
     if (NumD != 1)
@@ -1324,8 +1325,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
     if (!BT.has(RD.Reg))
       continue;
     const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg);
-    auto At = MI->isPHI() ? B.getFirstNonPHI()
-                          : MachineBasicBlock::iterator(MI);
+    auto At = MachineBasicBlock::iterator(MI);
 
     // Find a source operand that is equal to the result.
     for (auto &Op : MI->uses()) {
@@ -1356,11 +1356,11 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
       // This pass can create copies between registers that don't have the
       // exact same values. Updating the tracker has to involve updating
       // all dependent cells. Example:
-      //   vreg1 = inst vreg2     ; vreg1 != vreg2, but used bits are equal
+      //   %1  = inst %2     ; %1 != %2, but used bits are equal
       //
-      //   vreg3 = copy vreg2     ; <- inserted
-      //     ... = vreg3          ; <- replaced from vreg2
-      // Indirectly, we can create a "copy" between vreg1 and vreg2 even
+      //   %3  = copy %2     ; <- inserted
+      //   ... = %3          ; <- replaced from %2
+      // Indirectly, we can create a "copy" between %1 and %2 even
       // though their exact values do not match.
       BT.visit(*CopyI);
       Changed = true;
@@ -1622,11 +1622,10 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B,
       }
 
       if (FRC == &Hexagon::DoubleRegsRegClass ||
-          FRC == &Hexagon::VecDblRegsRegClass ||
-          FRC == &Hexagon::VecDblRegs128BRegClass) {
+          FRC == &Hexagon::HvxWRRegClass) {
         // Try to generate REG_SEQUENCE.
-        unsigned SubLo = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_lo);
-        unsigned SubHi = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_hi);
+        unsigned SubLo = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_lo);
+        unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi);
         BitTracker::RegisterRef TL = { R, SubLo };
         BitTracker::RegisterRef TH = { R, SubHi };
         BitTracker::RegisterRef ML, MH;
@@ -1660,7 +1659,6 @@ bool CopyPropagation::isCopyReg(unsigned Opc, bool NoConv) {
     case Hexagon::A2_tfrp:
     case Hexagon::A2_combinew:
     case Hexagon::V6_vcombine:
-    case Hexagon::V6_vcombine_128B:
       return NoConv;
     default:
       break;
@@ -1690,7 +1688,7 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) {
     case TargetOpcode::REG_SEQUENCE: {
       BitTracker::RegisterRef SL, SH;
       if (HBS::parseRegSequence(MI, SL, SH, MRI)) {
-        const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
+        const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
         unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
         unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);
         Changed  = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI);
@@ -1699,9 +1697,8 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) {
       break;
     }
     case Hexagon::A2_combinew:
-    case Hexagon::V6_vcombine:
-    case Hexagon::V6_vcombine_128B: {
-      const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
+    case Hexagon::V6_vcombine: {
+      const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
       unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
       unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);
       BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
@@ -2316,10 +2313,10 @@ bool BitSimplification::genBitSplit(MachineInstr *MI,
 
 // Check for tstbit simplification opportunity, where the bit being checked
 // can be tracked back to another register. For example:
-//   vreg2 = S2_lsr_i_r  vreg1, 5
-//   vreg3 = S2_tstbit_i vreg2, 0
+//   %2 = S2_lsr_i_r  %1, 5
+//   %3 = S2_tstbit_i %2, 0
 // =>
-//   vreg3 = S2_tstbit_i vreg1, 5
+//   %3 = S2_tstbit_i %1, 5
 bool BitSimplification::simplifyTstbit(MachineInstr *MI,
       BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) {
   unsigned Opc = MI->getOpcode();
@@ -2456,7 +2453,7 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI,
     return false;
 
   DEBUG({
-    dbgs() << __func__ << " on reg: " << PrintReg(RD.Reg, &HRI, RD.Sub)
+    dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub)
            << ", MI: " << *MI;
     dbgs() << "Cell: " << RC << '\n';
     dbgs() << "Expected bitfield size: " << Len << " bits, "
@@ -2634,7 +2631,7 @@ bool BitSimplification::processBlock(MachineBasicBlock &B,
 }
 
 bool HexagonBitSimplify::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   auto &HST = MF.getSubtarget<HexagonSubtarget>();
@@ -2767,31 +2764,32 @@ namespace {
   public:
     static char ID;
 
-    HexagonLoopRescheduling() : MachineFunctionPass(ID),
-        HII(nullptr), HRI(nullptr), MRI(nullptr), BTP(nullptr) {
+    HexagonLoopRescheduling() : MachineFunctionPass(ID) {
       initializeHexagonLoopReschedulingPass(*PassRegistry::getPassRegistry());
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
   private:
-    const HexagonInstrInfo *HII;
-    const HexagonRegisterInfo *HRI;
-    MachineRegisterInfo *MRI;
-    BitTracker *BTP;
+    const HexagonInstrInfo *HII = nullptr;
+    const HexagonRegisterInfo *HRI = nullptr;
+    MachineRegisterInfo *MRI = nullptr;
+    BitTracker *BTP = nullptr;
 
     struct LoopCand {
       LoopCand(MachineBasicBlock *lb, MachineBasicBlock *pb,
             MachineBasicBlock *eb) : LB(lb), PB(pb), EB(eb) {}
+
       MachineBasicBlock *LB, *PB, *EB;
     };
-    typedef std::vector<MachineInstr*> InstrList;
+    using InstrList = std::vector<MachineInstr *>;
     struct InstrGroup {
       BitTracker::RegisterRef Inp, Out;
       InstrList Ins;
     };
     struct PhiInfo {
       PhiInfo(MachineInstr &P, MachineBasicBlock &B);
+
       unsigned DefR;
       BitTracker::RegisterRef LR, PR; // Loop Register, Preheader Register
       MachineBasicBlock *LB, *PB;     // Loop Block, Preheader Block
@@ -2979,7 +2977,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB,
 }
 
 bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
-  DEBUG(dbgs() << "Processing loop in BB#" << C.LB->getNumber() << "\n");
+  DEBUG(dbgs() << "Processing loop in " << printMBBReference(*C.LB) << "\n");
   std::vector<PhiInfo> Phis;
   for (auto &I : *C.LB) {
     if (!I.isPHI())
@@ -3006,9 +3004,9 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
   DEBUG({
     dbgs() << "Phis: {";
     for (auto &I : Phis) {
-      dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi("
-             << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
-             << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
+      dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi("
+             << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
+             << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
              << I.LB->getNumber() << ')';
     }
     dbgs() << " }\n";
@@ -3079,7 +3077,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
   // to the beginning of the loop, that input register would need to be
   // the loop-carried register (through a phi node) instead of the (currently
   // loop-carried) output register.
-  typedef std::vector<InstrGroup> InstrGroupList;
+  using InstrGroupList = std::vector<InstrGroup>;
   InstrGroupList Groups;
 
   for (unsigned i = 0, n = ShufIns.size(); i < n; ++i) {
@@ -3128,8 +3126,8 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
     for (unsigned i = 0, n = Groups.size(); i < n; ++i) {
       InstrGroup &G = Groups[i];
       dbgs() << "Group[" << i << "] inp: "
-             << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub)
-             << "  out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
+             << printReg(G.Inp.Reg, HRI, G.Inp.Sub)
+             << "  out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
       for (unsigned j = 0, m = G.Ins.size(); j < m; ++j)
         dbgs() << "  " << *G.Ins[j];
     }
@@ -3183,7 +3181,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
 }
 
 bool HexagonLoopRescheduling::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   auto &HST = MF.getSubtarget<HexagonSubtarget>();
diff --git a/lib/Target/Hexagon/HexagonBitTracker.cpp b/lib/Target/Hexagon/HexagonBitTracker.cpp
index 3de531088240..b6e220beb0c6 100644
--- a/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonBitTracker.cpp --------------------------------------------===//
+//===- HexagonBitTracker.cpp ----------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -11,20 +11,22 @@
 #include "Hexagon.h"
 #include "HexagonInstrInfo.h"
 #include "HexagonRegisterInfo.h"
-#include "HexagonTargetMachine.h"
+#include "HexagonSubtarget.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/Argument.h"
 #include "llvm/IR/Attributes.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Type.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <cassert>
 #include <cstddef>
 #include <cstdint>
@@ -34,7 +36,7 @@
 
 using namespace llvm;
 
-typedef BitTracker BT;
+using BT = BitTracker;
 
 HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
                                    MachineRegisterInfo &mri,
@@ -58,10 +60,8 @@ HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
   // der the initial sequence of formal parameters that are known to be
   // passed via registers.
   unsigned InVirtReg, InPhysReg = 0;
-  const Function &F = *MF.getFunction();
-  typedef Function::const_arg_iterator arg_iterator;
-  for (arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
-    const Argument &Arg = *I;
+
+  for (const Argument &Arg : MF.getFunction().args()) {
     Type *ATy = Arg.getType();
     unsigned Width = 0;
     if (ATy->isIntegerTy())
@@ -88,30 +88,69 @@ HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
 }
 
 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
-  using namespace Hexagon;
-
   if (Sub == 0)
     return MachineEvaluator::mask(Reg, 0);
-  const TargetRegisterClass *RC = MRI.getRegClass(Reg);
-  unsigned ID = RC->getID();
+  const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
+  unsigned ID = RC.getID();
   uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
   auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
   bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
   switch (ID) {
-    case DoubleRegsRegClassID:
-    case VecDblRegsRegClassID:
-    case VecDblRegs128BRegClassID:
+    case Hexagon::DoubleRegsRegClassID:
+    case Hexagon::HvxWRRegClassID:
       return IsSubLo ? BT::BitMask(0, RW-1)
                      : BT::BitMask(RW, 2*RW-1);
     default:
       break;
   }
 #ifndef NDEBUG
-  dbgs() << PrintReg(Reg, &TRI, Sub) << '\n';
+  dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
+         << TRI.getRegClassName(&RC) << '\n';
 #endif
   llvm_unreachable("Unexpected register/subregister");
 }
 
+uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const {
+  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
+
+  using namespace Hexagon;
+  for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass})
+    if (RC.contains(Reg))
+      return TRI.getRegSizeInBits(RC);
+  // Default treatment for other physical registers.
+  if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
+    return TRI.getRegSizeInBits(*RC);
+
+  llvm_unreachable(
+      (Twine("Unhandled physical register") + TRI.getName(Reg)).str().c_str());
+}
+
+const TargetRegisterClass &HexagonEvaluator::composeWithSubRegIndex(
+      const TargetRegisterClass &RC, unsigned Idx) const {
+  if (Idx == 0)
+    return RC;
+
+#ifndef NDEBUG
+  const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
+  bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
+  bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
+  assert(IsSubLo != IsSubHi && "Must refer to either low or high subreg");
+#endif
+
+  switch (RC.getID()) {
+    case Hexagon::DoubleRegsRegClassID:
+      return Hexagon::IntRegsRegClass;
+    case Hexagon::HvxWRRegClassID:
+      return Hexagon::HvxVRRegClass;
+    default:
+      break;
+  }
+#ifndef NDEBUG
+  dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n';
+#endif
+  llvm_unreachable("Unimplemented combination of reg class/subreg idx");
+}
+
 namespace {
 
 class RegisterRefs {
@@ -147,8 +186,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI,
   unsigned NumDefs = 0;
 
   // Sanity verification: there should not be any defs with subregisters.
-  for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
-    const MachineOperand &MO = MI.getOperand(i);
+  for (const MachineOperand &MO : MI.operands()) {
     if (!MO.isReg() || !MO.isDef())
       continue;
     NumDefs++;
@@ -197,8 +235,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI,
   // checking what kind of operand a given instruction has individually
   // for each instruction, do it here. Global symbols as operands gene-
   // rally do not provide any useful information.
-  for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
-    const MachineOperand &MO = MI.getOperand(i);
+  for (const MachineOperand &MO : MI.operands()) {
     if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
         MO.isCPI())
       return false;
@@ -700,7 +737,6 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI,
     case A4_combineri:
     case A2_combinew:
     case V6_vcombine:
-    case V6_vcombine_128B:
       assert(W0 % 2 == 0);
       return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
     case A2_combine_ll:
@@ -1212,10 +1248,8 @@ unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
 }
 
 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
-  typedef MachineRegisterInfo::livein_iterator iterator;
-  for (iterator I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) {
-    if (I->first == PReg)
-      return I->second;
-  }
+  for (std::pair<unsigned,unsigned> P : MRI.liveins())
+    if (P.first == PReg)
+      return P.second;
   return 0;
 }
diff --git a/lib/Target/Hexagon/HexagonBitTracker.h b/lib/Target/Hexagon/HexagonBitTracker.h
index 2cbf65e66ca6..d9dd04e1b088 100644
--- a/lib/Target/Hexagon/HexagonBitTracker.h
+++ b/lib/Target/Hexagon/HexagonBitTracker.h
@@ -1,4 +1,4 @@
-//===--- HexagonBitTracker.h ------------------------------------*- C++ -*-===//
+//===- HexagonBitTracker.h --------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -18,12 +18,16 @@ namespace llvm {
 
 class HexagonInstrInfo;
 class HexagonRegisterInfo;
+class MachineFrameInfo;
+class MachineFunction;
+class MachineInstr;
+class MachineRegisterInfo;
 
 struct HexagonEvaluator : public BitTracker::MachineEvaluator {
-  typedef BitTracker::CellMapType CellMapType;
-  typedef BitTracker::RegisterRef RegisterRef;
-  typedef BitTracker::RegisterCell RegisterCell;
-  typedef BitTracker::BranchTargetList BranchTargetList;
+  using CellMapType = BitTracker::CellMapType;
+  using RegisterRef = BitTracker::RegisterRef;
+  using RegisterCell = BitTracker::RegisterCell;
+  using BranchTargetList = BitTracker::BranchTargetList;
 
   HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
                    const HexagonInstrInfo &tii, MachineFunction &mf);
@@ -35,6 +39,11 @@ struct HexagonEvaluator : public BitTracker::MachineEvaluator {
 
   BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override;
 
+  uint16_t getPhysRegBitWidth(unsigned Reg) const override;
+
+  const TargetRegisterClass &composeWithSubRegIndex(
+        const TargetRegisterClass &RC, unsigned Idx) const override;
+
   MachineFunction &MF;
   MachineFrameInfo &MFI;
   const HexagonInstrInfo &TII;
@@ -59,7 +68,7 @@ private:
     uint16_t Width = 0;
   };
   // Map VR -> extension type.
-  typedef DenseMap<unsigned, ExtType> RegExtMap;
+  using RegExtMap = DenseMap<unsigned, ExtType>;
   RegExtMap VRX;
 };
 
diff --git a/lib/Target/Hexagon/HexagonBlockRanges.cpp b/lib/Target/Hexagon/HexagonBlockRanges.cpp
index 1640b40c164f..ff915ca59dae 100644
--- a/lib/Target/Hexagon/HexagonBlockRanges.cpp
+++ b/lib/Target/Hexagon/HexagonBlockRanges.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonBlockRanges.cpp -------------------------------------------===//
+//===- HexagonBlockRanges.cpp ---------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,8 +7,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "hbr"
-
 #include "HexagonBlockRanges.h"
 #include "HexagonInstrInfo.h"
 #include "HexagonSubtarget.h"
@@ -17,18 +15,23 @@
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <algorithm>
 #include <cassert>
+#include <cstdint>
 #include <iterator>
 #include <map>
+#include <utility>
 
 using namespace llvm;
 
+#define DEBUG_TYPE "hbr"
+
 bool HexagonBlockRanges::IndexRange::overlaps(const IndexRange &A) const {
   // If A contains start(), or "this" contains A.start(), then overlap.
   IndexType S = start(), E = end(), AS = A.start(), AE = A.end();
@@ -365,7 +368,7 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap,
       }
     }
     // Defs and clobbers can overlap, e.g.
-    // %D0<def,dead> = COPY %vreg5, %R0<imp-def>, %R1<imp-def>
+    // dead %d0 = COPY %5, implicit-def %r0, implicit-def %r1
     for (RegisterRef R : Defs)
       Clobbers.erase(R);
 
@@ -528,7 +531,7 @@ raw_ostream &llvm::operator<<(raw_ostream &OS,
                               const HexagonBlockRanges::PrintRangeMap &P) {
   for (auto &I : P.Map) {
     const HexagonBlockRanges::RangeList &RL = I.second;
-    OS << PrintReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n";
+    OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n";
   }
   return OS;
 }
diff --git a/lib/Target/Hexagon/HexagonBlockRanges.h b/lib/Target/Hexagon/HexagonBlockRanges.h
index 769ec7044a0e..4da5a970a659 100644
--- a/lib/Target/Hexagon/HexagonBlockRanges.h
+++ b/lib/Target/Hexagon/HexagonBlockRanges.h
@@ -1,4 +1,4 @@
-//===--- HexagonBlockRanges.h -----------------------------------*- C++ -*-===//
+//===- HexagonBlockRanges.h -------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,11 +6,11 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
-#ifndef HEXAGON_BLOCK_RANGES_H
-#define HEXAGON_BLOCK_RANGES_H
+
+#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONBLOCKRANGES_H
+#define LLVM_LIB_TARGET_HEXAGON_HEXAGONBLOCKRANGES_H
 
 #include "llvm/ADT/BitVector.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
 #include <cassert>
 #include <map>
 #include <set>
@@ -23,6 +23,7 @@ class HexagonSubtarget;
 class MachineBasicBlock;
 class MachineFunction;
 class MachineInstr;
+class MachineRegisterInfo;
 class raw_ostream;
 class TargetInstrInfo;
 class TargetRegisterInfo;
@@ -32,11 +33,12 @@ struct HexagonBlockRanges {
 
   struct RegisterRef {
     unsigned Reg, Sub;
+
     bool operator<(RegisterRef R) const {
       return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
     }
   };
-  typedef std::set<RegisterRef> RegisterSet;
+  using RegisterSet = std::set<RegisterRef>;
 
   // This is to represent an "index", which is an abstraction of a position
   // of an instruction within a basic block.
@@ -49,7 +51,7 @@ struct HexagonBlockRanges {
       First = 11  // 10th + 1st
     };
 
-    IndexType() : Index(None) {}
+    IndexType() {}
     IndexType(unsigned Idx) : Index(Idx) {}
 
     static bool isInstr(IndexType X) { return X.Index >= First; }
@@ -68,7 +70,7 @@ struct HexagonBlockRanges {
     bool operator>  (IndexType Idx) const;
     bool operator>= (IndexType Idx) const;
 
-    unsigned Index;
+    unsigned Index = None;
   };
 
   // A range of indices, essentially a representation of a live range.
@@ -138,7 +140,8 @@ struct HexagonBlockRanges {
     std::map<IndexType,MachineInstr*> Map;
   };
 
-  typedef std::map<RegisterRef,RangeList> RegToRangeMap;
+  using RegToRangeMap = std::map<RegisterRef, RangeList>;
+
   RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap);
   RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap);
   static RegisterSet expandToSubRegs(RegisterRef R,
@@ -241,4 +244,4 @@ raw_ostream &operator<< (raw_ostream &OS,
 
 } // end namespace llvm
 
-#endif // HEXAGON_BLOCK_RANGES_H
+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONBLOCKRANGES_H
diff --git a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
index c7b422e7efd0..a22ac8c9fdf5 100644
--- a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
+++ b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
@@ -1,4 +1,5 @@
-//===-- HexagonCFGOptimizer.cpp - CFG optimizations -----------------------===//
+//===- HexagonCFGOptimizer.cpp - CFG optimizations ------------------------===//
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
@@ -7,53 +8,54 @@
 //===----------------------------------------------------------------------===//
 
 #include "Hexagon.h"
-#include "HexagonMachineFunctionInfo.h"
-#include "HexagonSubtarget.h"
-#include "HexagonTargetMachine.h"
-#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineLoopInfo.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/ErrorHandling.h"
+#include <cassert>
+#include <vector>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "hexagon_cfg"
 
 namespace llvm {
-  FunctionPass *createHexagonCFGOptimizer();
-  void initializeHexagonCFGOptimizerPass(PassRegistry&);
-}
 
+FunctionPass *createHexagonCFGOptimizer();
+void initializeHexagonCFGOptimizerPass(PassRegistry&);
+
+} // end namespace llvm
 
 namespace {
 
 class HexagonCFGOptimizer : public MachineFunctionPass {
-
 private:
   void InvertAndChangeJumpTarget(MachineInstr &, MachineBasicBlock *);
   bool isOnFallThroughPath(MachineBasicBlock *MBB);
 
 public:
   static char ID;
+
   HexagonCFGOptimizer() : MachineFunctionPass(ID) {
     initializeHexagonCFGOptimizerPass(*PassRegistry::getPassRegistry());
   }
 
   StringRef getPassName() const override { return "Hexagon CFG Optimizer"; }
   bool runOnMachineFunction(MachineFunction &Fn) override;
+
   MachineFunctionProperties getRequiredProperties() const override {
     return MachineFunctionProperties().set(
         MachineFunctionProperties::Property::NoVRegs);
   }
 };
 
+} // end anonymous namespace
 
 char HexagonCFGOptimizer::ID = 0;
 
@@ -72,7 +74,6 @@ static bool IsConditionalBranch(int Opc) {
   return false;
 }
 
-
 static bool IsUnconditionalJump(int Opc) {
   return (Opc == Hexagon::J2_jump);
 }
@@ -86,19 +87,15 @@ void HexagonCFGOptimizer::InvertAndChangeJumpTarget(
   case Hexagon::J2_jumpt:
     NewOpcode = Hexagon::J2_jumpf;
     break;
-
   case Hexagon::J2_jumpf:
     NewOpcode = Hexagon::J2_jumpt;
     break;
-
   case Hexagon::J2_jumptnewpt:
     NewOpcode = Hexagon::J2_jumpfnewpt;
     break;
-
   case Hexagon::J2_jumpfnewpt:
     NewOpcode = Hexagon::J2_jumptnewpt;
     break;
-
   default:
     llvm_unreachable("Cannot handle this case");
   }
@@ -117,7 +114,7 @@ bool HexagonCFGOptimizer::isOnFallThroughPath(MachineBasicBlock *MBB) {
 }
 
 bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
-  if (skipFunction(*Fn.getFunction()))
+  if (skipFunction(Fn.getFunction()))
     return false;
 
   // Loop over all of the basic blocks.
@@ -131,8 +128,6 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
       MachineInstr &MI = *MII;
       int Opc = MI.getOpcode();
       if (IsConditionalBranch(Opc)) {
-
-        //
         // (Case 1) Transform the code if the following condition occurs:
         //   BB1: if (p0) jump BB3
         //   ...falls-through to BB2 ...
@@ -160,7 +155,6 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
         //   Remove BB2
         //   BB3: ...
         //   BB4: ...
-        //
         unsigned NumSuccs = MBB->succ_size();
         MachineBasicBlock::succ_iterator SI = MBB->succ_begin();
         MachineBasicBlock* FirstSucc = *SI;
@@ -200,7 +194,7 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
             // Check if the layout successor of BB2 is BB3.
             bool case1 = LayoutSucc->isLayoutSuccessor(JumpAroundTarget);
             bool case2 = JumpAroundTarget->isSuccessor(UncondTarget) &&
-              JumpAroundTarget->size() >= 1 &&
+              !JumpAroundTarget->empty() &&
               IsUnconditionalJump(JumpAroundTarget->back().getOpcode()) &&
               JumpAroundTarget->pred_size() == 1 &&
               JumpAroundTarget->succ_size() == 1;
@@ -223,11 +217,9 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
                   UncondTarget->moveAfter(JumpAroundTarget);
               }
 
-              //
               // Correct live-in information. Is used by post-RA scheduler
               // The live-in to LayoutSucc is now all values live-in to
               // JumpAroundTarget.
-              //
               std::vector<MachineBasicBlock::RegisterMaskPair> OrigLiveIn(
                   LayoutSucc->livein_begin(), LayoutSucc->livein_end());
               std::vector<MachineBasicBlock::RegisterMaskPair> NewLiveIn(
@@ -245,8 +237,6 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
   }
   return true;
 }
-}
-
 
 //===----------------------------------------------------------------------===//
 //                         Public Constructor Functions
diff --git a/lib/Target/Hexagon/HexagonCommonGEP.cpp b/lib/Target/Hexagon/HexagonCommonGEP.cpp
index b5b46f2b7d19..7e3d049d337f 100644
--- a/lib/Target/Hexagon/HexagonCommonGEP.cpp
+++ b/lib/Target/Hexagon/HexagonCommonGEP.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonCommonGEP.cpp ---------------------------------------------===//
+//===- HexagonCommonGEP.cpp -----------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -11,6 +11,7 @@
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/FoldingSet.h"
+#include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Analysis/LoopInfo.h"
@@ -66,12 +67,12 @@ namespace llvm {
 namespace {
 
   struct GepNode;
-  typedef std::set<GepNode*> NodeSet;
-  typedef std::map<GepNode*,Value*> NodeToValueMap;
-  typedef std::vector<GepNode*> NodeVect;
-  typedef std::map<GepNode*,NodeVect> NodeChildrenMap;
-  typedef std::set<Use*> UseSet;
-  typedef std::map<GepNode*,UseSet> NodeToUsesMap;
+  using NodeSet = std::set<GepNode *>;
+  using NodeToValueMap = std::map<GepNode *, Value *>;
+  using NodeVect = std::vector<GepNode *>;
+  using NodeChildrenMap = std::map<GepNode *, NodeVect>;
+  using UseSet = std::set<Use *>;
+  using NodeToUsesMap = std::map<GepNode *, UseSet>;
 
   // Numbering map for gep nodes. Used to keep track of ordering for
   // gep nodes.
@@ -114,9 +115,9 @@ namespace {
     }
 
   private:
-    typedef std::map<Value*,GepNode*> ValueToNodeMap;
-    typedef std::vector<Value*> ValueVect;
-    typedef std::map<GepNode*,ValueVect> NodeToValuesMap;
+    using ValueToNodeMap = std::map<Value *, GepNode *>;
+    using ValueVect = std::vector<Value *>;
+    using NodeToValuesMap = std::map<GepNode *, ValueVect>;
 
     void getBlockTraversalOrder(BasicBlock *Root, ValueVect &Order);
     bool isHandledGepForm(GetElementPtrInst *GepI);
@@ -160,6 +161,7 @@ namespace {
 } // end anonymous namespace
 
 char HexagonCommonGEP::ID = 0;
+
 INITIALIZE_PASS_BEGIN(HexagonCommonGEP, "hcommgep", "Hexagon Common GEP",
       false, false)
 INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
@@ -179,15 +181,15 @@ namespace {
       InBounds  = 0x08
     };
 
-    uint32_t Flags;
+    uint32_t Flags = 0;
     union {
       GepNode *Parent;
       Value *BaseVal;
     };
-    Value *Idx;
-    Type *PTy;  // Type of the pointer operand.
+    Value *Idx = nullptr;
+    Type *PTy = nullptr;  // Type of the pointer operand.
 
-    GepNode() : Flags(0), Parent(nullptr), Idx(nullptr), PTy(nullptr) {}
+    GepNode() : Parent(nullptr) {}
     GepNode(const GepNode *N) : Flags(N->Flags), Idx(N->Idx), PTy(N->PTy) {
       if (Flags & Root)
         BaseVal = N->BaseVal;
@@ -267,7 +269,8 @@ namespace {
 
   template <typename NodeContainer>
   void dump_node_container(raw_ostream &OS, const NodeContainer &S) {
-    typedef typename NodeContainer::const_iterator const_iterator;
+    using const_iterator = typename NodeContainer::const_iterator;
+
     for (const_iterator I = S.begin(), E = S.end(); I != E; ++I)
       OS << *I << ' ' << **I << '\n';
   }
@@ -282,7 +285,8 @@ namespace {
   raw_ostream &operator<< (raw_ostream &OS,
                            const NodeToUsesMap &M) LLVM_ATTRIBUTE_UNUSED;
   raw_ostream &operator<< (raw_ostream &OS, const NodeToUsesMap &M){
-    typedef NodeToUsesMap::const_iterator const_iterator;
+    using const_iterator = NodeToUsesMap::const_iterator;
+
     for (const_iterator I = M.begin(), E = M.end(); I != E; ++I) {
       const UseSet &Us = I->second;
       OS << I->first << " -> #" << Us.size() << '{';
@@ -300,6 +304,7 @@ namespace {
 
   struct in_set {
     in_set(const NodeSet &S) : NS(S) {}
+
     bool operator() (GepNode *N) const {
       return NS.find(N) != NS.end();
     }
@@ -426,7 +431,8 @@ void HexagonCommonGEP::collect() {
 
 static void invert_find_roots(const NodeVect &Nodes, NodeChildrenMap &NCM,
                               NodeVect &Roots) {
-    typedef NodeVect::const_iterator const_iterator;
+    using const_iterator = NodeVect::const_iterator;
+
     for (const_iterator I = Nodes.begin(), E = Nodes.end(); I != E; ++I) {
       GepNode *N = *I;
       if (N->Flags & GepNode::Root) {
@@ -458,9 +464,9 @@ static void nodes_for_root(GepNode *Root, NodeChildrenMap &NCM,
 
 namespace {
 
-  typedef std::set<NodeSet> NodeSymRel;
-  typedef std::pair<GepNode*,GepNode*> NodePair;
-  typedef std::set<NodePair> NodePairSet;
+  using NodeSymRel = std::set<NodeSet>;
+  using NodePair = std::pair<GepNode *, GepNode *>;
+  using NodePairSet = std::set<NodePair>;
 
 } // end anonymous namespace
 
@@ -529,7 +535,7 @@ void HexagonCommonGEP::common() {
   // To do this we need to compare all pairs of nodes. To save time,
   // first, partition the set of all nodes into sets of potentially equal
   // nodes, and then compare pairs from within each partition.
-  typedef std::map<unsigned,NodeSet> NodeSetMap;
+  using NodeSetMap = std::map<unsigned, NodeSet>;
   NodeSetMap MaybeEq;
 
   for (NodeVect::iterator I = Nodes.begin(), E = Nodes.end(); I != E; ++I) {
@@ -588,7 +594,7 @@ void HexagonCommonGEP::common() {
   });
 
   // Create a projection from a NodeSet to the minimal element in it.
-  typedef std::map<const NodeSet*,GepNode*> ProjMap;
+  using ProjMap = std::map<const NodeSet *, GepNode *>;
   ProjMap PM;
   for (NodeSymRel::iterator I = EqRel.begin(), E = EqRel.end(); I != E; ++I) {
     const NodeSet &S = *I;
@@ -717,7 +723,9 @@ static BasicBlock *nearest_common_dominatee(DominatorTree *DT, T &Blocks) {
 template <typename T>
 static BasicBlock::iterator first_use_of_in_block(T &Values, BasicBlock *B) {
     BasicBlock::iterator FirstUse = B->end(), BEnd = B->end();
-    typedef typename T::iterator iterator;
+
+    using iterator = typename T::iterator;
+
     for (iterator I = Values.begin(), E = Values.end(); I != E; ++I) {
       Value *V = *I;
       // If V is used in a PHI node, the use belongs to the incoming block,
@@ -1247,7 +1255,9 @@ void HexagonCommonGEP::removeDeadCode() {
   for (unsigned i = BO.size(); i > 0; --i) {
     BasicBlock *B = cast<BasicBlock>(BO[i-1]);
     BasicBlock::InstListType &IL = B->getInstList();
-    typedef BasicBlock::InstListType::reverse_iterator reverse_iterator;
+
+    using reverse_iterator = BasicBlock::InstListType::reverse_iterator;
+
     ValueVect Ins;
     for (reverse_iterator I = IL.rbegin(), E = IL.rend(); I != E; ++I)
       Ins.push_back(&*I);
diff --git a/lib/Target/Hexagon/HexagonConstExtenders.cpp b/lib/Target/Hexagon/HexagonConstExtenders.cpp
new file mode 100644
index 000000000000..294a6da69f51
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -0,0 +1,1874 @@
+//===- HexagonConstExtenders.cpp ------------------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "HexagonInstrInfo.h"
+#include "HexagonRegisterInfo.h"
+#include "HexagonSubtarget.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Pass.h"
+#include <map>
+#include <set>
+#include <utility>
+#include <vector>
+
+#define DEBUG_TYPE "hexagon-cext-opt"
+
+using namespace llvm;
+
+static cl::opt<unsigned> CountThreshold("hexagon-cext-threshold",
+  cl::init(3), cl::Hidden, cl::ZeroOrMore,
+  cl::desc("Minimum number of extenders to trigger replacement"));
+
+static cl::opt<unsigned> ReplaceLimit("hexagon-cext-limit", cl::init(0),
+  cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum number of replacements"));
+
+namespace llvm {
+  void initializeHexagonConstExtendersPass(PassRegistry&);
+  FunctionPass *createHexagonConstExtenders();
+}
+
+namespace {
+  struct OffsetRange {
+    int32_t Min = INT_MIN, Max = INT_MAX;
+    uint8_t Align = 1;
+
+    OffsetRange() = default;
+    OffsetRange(int32_t L, int32_t H, uint8_t A)
+      : Min(L), Max(H), Align(A) {}
+    OffsetRange &intersect(OffsetRange A) {
+      Align = std::max(Align, A.Align);
+      Min = std::max(Min, A.Min);
+      Max = std::min(Max, A.Max);
+      // Canonicalize empty ranges.
+      if (Min > Max)
+        std::tie(Min, Max, Align) = std::make_tuple(0, -1, 1);
+      return *this;
+    }
+    OffsetRange &shift(int32_t S) {
+      assert(alignTo(std::abs(S), Align) == uint64_t(std::abs(S)));
+      Min += S;
+      Max += S;
+      return *this;
+    }
+    OffsetRange &extendBy(int32_t D) {
+      // If D < 0, extend Min, otherwise extend Max.
+      if (D < 0)
+        Min = (INT_MIN-D < Min) ? Min+D : INT_MIN;
+      else
+        Max = (INT_MAX-D > Max) ? Max+D : INT_MAX;
+      return *this;
+    }
+    bool empty() const {
+      return Min > Max;
+    }
+    bool contains(int32_t V) const {
+      return Min <= V && V <= Max && (V % Align) == 0;
+    }
+    bool operator==(const OffsetRange &R) const {
+      return Min == R.Min && Max == R.Max && Align == R.Align;
+    }
+    bool operator!=(const OffsetRange &R) const {
+      return !operator==(R);
+    }
+    bool operator<(const OffsetRange &R) const {
+      if (Min != R.Min)
+        return Min < R.Min;
+      if (Max != R.Max)
+        return Max < R.Max;
+      return Align < R.Align;
+    }
+    static OffsetRange zero() { return {0, 0, 1}; }
+  };
+
+  struct RangeTree {
+    struct Node {
+      Node(const OffsetRange &R) : MaxEnd(R.Max), Range(R) {}
+      unsigned Height = 1;
+      unsigned Count = 1;
+      int32_t MaxEnd;
+      const OffsetRange &Range;
+      Node *Left = nullptr, *Right = nullptr;
+    };
+
+    Node *Root = nullptr;
+
+    void add(const OffsetRange &R) {
+      Root = add(Root, R);
+    }
+    void erase(const Node *N) {
+      Root = remove(Root, N);
+      delete N;
+    }
+    void order(SmallVectorImpl<Node*> &Seq) const {
+      order(Root, Seq);
+    }
+    SmallVector<Node*,8> nodesWith(int32_t P, bool CheckAlign = true) {
+      SmallVector<Node*,8> Nodes;
+      nodesWith(Root, P, CheckAlign, Nodes);
+      return Nodes;
+    }
+    void dump() const;
+    ~RangeTree() {
+      SmallVector<Node*,8> Nodes;
+      order(Nodes);
+      for (Node *N : Nodes)
+        delete N;
+    }
+
+  private:
+    void dump(const Node *N) const;
+    void order(Node *N, SmallVectorImpl<Node*> &Seq) const;
+    void nodesWith(Node *N, int32_t P, bool CheckA,
+                   SmallVectorImpl<Node*> &Seq) const;
+
+    Node *add(Node *N, const OffsetRange &R);
+    Node *remove(Node *N, const Node *D);
+    Node *rotateLeft(Node *Lower, Node *Higher);
+    Node *rotateRight(Node *Lower, Node *Higher);
+    unsigned height(Node *N) {
+      return N != nullptr ? N->Height : 0;
+    }
+    Node *update(Node *N) {
+      assert(N != nullptr);
+      N->Height = 1 + std::max(height(N->Left), height(N->Right));
+      if (N->Left)
+        N->MaxEnd = std::max(N->MaxEnd, N->Left->MaxEnd);
+      if (N->Right)
+        N->MaxEnd = std::max(N->MaxEnd, N->Right->MaxEnd);
+      return N;
+    }
+    Node *rebalance(Node *N) {
+      assert(N != nullptr);
+      int32_t Balance = height(N->Right) - height(N->Left);
+      if (Balance < -1)
+        return rotateRight(N->Left, N);
+      if (Balance > 1)
+        return rotateLeft(N->Right, N);
+      return N;
+    }
+  };
+
+  struct Loc {
+    MachineBasicBlock *Block = nullptr;
+    MachineBasicBlock::iterator At;
+
+    Loc(MachineBasicBlock *B, MachineBasicBlock::iterator It)
+      : Block(B), At(It) {
+      if (B->end() == It) {
+        Pos = -1;
+      } else {
+        assert(It->getParent() == B);
+        Pos = std::distance(B->begin(), It);
+      }
+    }
+    bool operator<(Loc A) const {
+      if (Block != A.Block)
+        return Block->getNumber() < A.Block->getNumber();
+      if (A.Pos == -1)
+        return Pos != A.Pos;
+      return Pos != -1 && Pos < A.Pos;
+    }
+  private:
+    int Pos = 0;
+  };
+
+  struct HexagonConstExtenders : public MachineFunctionPass {
+    static char ID;
+    HexagonConstExtenders() : MachineFunctionPass(ID) {}
+
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
+      AU.addRequired<MachineDominatorTree>();
+      AU.addPreserved<MachineDominatorTree>();
+      MachineFunctionPass::getAnalysisUsage(AU);
+    }
+
+    StringRef getPassName() const override {
+      return "Hexagon constant-extender optimization";
+    }
+    bool runOnMachineFunction(MachineFunction &MF) override;
+
+  private:
+    struct Register {
+      Register() = default;
+      Register(unsigned R, unsigned S) : Reg(R), Sub(S) {}
+      Register(const MachineOperand &Op)
+        : Reg(Op.getReg()), Sub(Op.getSubReg()) {}
+      Register &operator=(const MachineOperand &Op) {
+        if (Op.isReg()) {
+          Reg = Op.getReg();
+          Sub = Op.getSubReg();
+        } else if (Op.isFI()) {
+          Reg = TargetRegisterInfo::index2StackSlot(Op.getIndex());
+        }
+        return *this;
+      }
+      bool isVReg() const {
+        return Reg != 0 && !TargetRegisterInfo::isStackSlot(Reg) &&
+               TargetRegisterInfo::isVirtualRegister(Reg);
+      }
+      bool isSlot() const {
+        return Reg != 0 && TargetRegisterInfo::isStackSlot(Reg);
+      }
+      operator MachineOperand() const {
+        if (isVReg())
+          return MachineOperand::CreateReg(Reg, /*Def*/false, /*Imp*/false,
+                          /*Kill*/false, /*Dead*/false, /*Undef*/false,
+                          /*EarlyClobber*/false, Sub);
+        if (TargetRegisterInfo::isStackSlot(Reg)) {
+          int FI = TargetRegisterInfo::stackSlot2Index(Reg);
+          return MachineOperand::CreateFI(FI);
+        }
+        llvm_unreachable("Cannot create MachineOperand");
+      }
+      bool operator==(Register R) const { return Reg == R.Reg && Sub == R.Sub; }
+      bool operator!=(Register R) const { return !operator==(R); }
+      bool operator<(Register R) const {
+        // For std::map.
+        return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
+      }
+      unsigned Reg = 0, Sub = 0;
+    };
+
+    struct ExtExpr {
+      // A subexpression in which the extender is used. In general, this
+      // represents an expression where adding D to the extender will be
+      // equivalent to adding D to the expression as a whole. In other
+      // words, expr(add(##V,D) = add(expr(##V),D).
+
+      // The original motivation for this are the io/ur addressing modes,
+      // where the offset is extended. Consider the io example:
+      // In memw(Rs+##V), the ##V could be replaced by a register Rt to
+      // form the rr mode: memw(Rt+Rs<<0). In such case, however, the
+      // register Rt must have exactly the value of ##V. If there was
+      // another instruction memw(Rs+##V+4), it would need a different Rt.
+      // Now, if Rt was initialized as "##V+Rs<<0", both of these
+      // instructions could use the same Rt, just with different offsets.
+      // Here it's clear that "initializer+4" should be the same as if
+      // the offset 4 was added to the ##V in the initializer.
+
+      // The only kinds of expressions that support the requirement of
+      // commuting with addition are addition and subtraction from ##V.
+      // Include shifting the Rs to account for the ur addressing mode:
+      //   ##Val + Rs << S
+      //   ##Val - Rs
+      Register Rs;
+      unsigned S = 0;
+      bool Neg = false;
+
+      ExtExpr() = default;
+      ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {}
+      // Expression is trivial if it does not modify the extender.
+      bool trivial() const {
+        return Rs.Reg == 0;
+      }
+      bool operator==(const ExtExpr &Ex) const {
+        return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg;
+      }
+      bool operator!=(const ExtExpr &Ex) const {
+        return !operator==(Ex);
+      }
+      bool operator<(const ExtExpr &Ex) const {
+        if (Rs != Ex.Rs)
+          return Rs < Ex.Rs;
+        if (S != Ex.S)
+          return S < Ex.S;
+        return !Neg && Ex.Neg;
+      }
+    };
+
+    struct ExtDesc {
+      MachineInstr *UseMI = nullptr;
+      unsigned OpNum = -1u;
+      // The subexpression in which the extender is used (e.g. address
+      // computation).
+      ExtExpr Expr;
+      // Optional register that is assigned the value of Expr.
+      Register Rd;
+      // Def means that the output of the instruction may differ from the
+      // original by a constant c, and that the difference can be corrected
+      // by adding/subtracting c in all users of the defined register.
+      bool IsDef = false;
+
+      MachineOperand &getOp() {
+        return UseMI->getOperand(OpNum);
+      }
+      const MachineOperand &getOp() const {
+        return UseMI->getOperand(OpNum);
+      }
+    };
+
+    struct ExtRoot {
+      union {
+        const ConstantFP *CFP;  // MO_FPImmediate
+        const char *SymbolName; // MO_ExternalSymbol
+        const GlobalValue *GV;  // MO_GlobalAddress
+        const BlockAddress *BA; // MO_BlockAddress
+        int64_t ImmVal;         // MO_Immediate, MO_TargetIndex,
+                                // and MO_ConstantPoolIndex
+      } V;
+      unsigned Kind;            // Same as in MachineOperand.
+      unsigned char TF;         // TargetFlags.
+
+      ExtRoot(const MachineOperand &Op);
+      bool operator==(const ExtRoot &ER) const {
+        return Kind == ER.Kind && V.ImmVal == ER.V.ImmVal;
+      }
+      bool operator!=(const ExtRoot &ER) const {
+        return !operator==(ER);
+      }
+      bool operator<(const ExtRoot &ER) const;
+    };
+
+    struct ExtValue : public ExtRoot {
+      int32_t Offset;
+
+      ExtValue(const MachineOperand &Op);
+      ExtValue(const ExtDesc &ED) : ExtValue(ED.getOp()) {}
+      ExtValue(const ExtRoot &ER, int32_t Off) : ExtRoot(ER), Offset(Off) {}
+      bool operator<(const ExtValue &EV) const;
+      bool operator==(const ExtValue &EV) const {
+        return ExtRoot(*this) == ExtRoot(EV) && Offset == EV.Offset;
+      }
+      bool operator!=(const ExtValue &EV) const {
+        return !operator==(EV);
+      }
+      explicit operator MachineOperand() const;
+    };
+
+    using IndexList = SetVector<unsigned>;
+    using ExtenderInit = std::pair<ExtValue, ExtExpr>;
+    using AssignmentMap = std::map<ExtenderInit, IndexList>;
+    using LocDefMap = std::map<Loc, IndexList>;
+
+    const HexagonInstrInfo *HII = nullptr;
+    const HexagonRegisterInfo *HRI = nullptr;
+    MachineDominatorTree *MDT = nullptr;
+    MachineRegisterInfo *MRI = nullptr;
+    std::vector<ExtDesc> Extenders;
+    std::vector<unsigned> NewRegs;
+
+    bool isStoreImmediate(unsigned Opc) const;
+    bool isRegOffOpcode(unsigned ExtOpc) const ;
+    unsigned getRegOffOpcode(unsigned ExtOpc) const;
+    unsigned getDirectRegReplacement(unsigned ExtOpc) const;
+    OffsetRange getOffsetRange(Register R, const MachineInstr &MI) const;
+    OffsetRange getOffsetRange(const ExtDesc &ED) const;
+    OffsetRange getOffsetRange(Register Rd) const;
+
+    void recordExtender(MachineInstr &MI, unsigned OpNum);
+    void collectInstr(MachineInstr &MI);
+    void collect(MachineFunction &MF);
+    void assignInits(const ExtRoot &ER, unsigned Begin, unsigned End,
+                     AssignmentMap &IMap);
+    void calculatePlacement(const ExtenderInit &ExtI, const IndexList &Refs,
+                            LocDefMap &Defs);
+    Register insertInitializer(Loc DefL, const ExtenderInit &ExtI);
+    bool replaceInstrExact(const ExtDesc &ED, Register ExtR);
+    bool replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
+                          Register ExtR, int32_t &Diff);
+    bool replaceInstr(unsigned Idx, Register ExtR, const ExtenderInit &ExtI);
+    bool replaceExtenders(const AssignmentMap &IMap);
+
+    unsigned getOperandIndex(const MachineInstr &MI,
+                             const MachineOperand &Op) const;
+    const MachineOperand &getPredicateOp(const MachineInstr &MI) const;
+    const MachineOperand &getLoadResultOp(const MachineInstr &MI) const;
+    const MachineOperand &getStoredValueOp(const MachineInstr &MI) const;
+
+    friend struct PrintRegister;
+    friend struct PrintExpr;
+    friend struct PrintInit;
+    friend struct PrintIMap;
+    friend raw_ostream &operator<< (raw_ostream &OS,
+                                    const struct PrintRegister &P);
+    friend raw_ostream &operator<< (raw_ostream &OS, const struct PrintExpr &P);
+    friend raw_ostream &operator<< (raw_ostream &OS, const struct PrintInit &P);
+    friend raw_ostream &operator<< (raw_ostream &OS, const ExtDesc &ED);
+    friend raw_ostream &operator<< (raw_ostream &OS, const ExtRoot &ER);
+    friend raw_ostream &operator<< (raw_ostream &OS, const ExtValue &EV);
+    friend raw_ostream &operator<< (raw_ostream &OS, const OffsetRange &OR);
+    friend raw_ostream &operator<< (raw_ostream &OS, const struct PrintIMap &P);
+  };
+
+  using HCE = HexagonConstExtenders;
+
+  LLVM_ATTRIBUTE_UNUSED
+  raw_ostream &operator<< (raw_ostream &OS, const OffsetRange &OR) {
+    if (OR.Min > OR.Max)
+      OS << '!';
+    OS << '[' << OR.Min << ',' << OR.Max << "]a" << unsigned(OR.Align);
+    return OS;
+  }
+
+  struct PrintRegister {
+    PrintRegister(HCE::Register R, const HexagonRegisterInfo &I)
+      : Rs(R), HRI(I) {}
+    HCE::Register Rs;
+    const HexagonRegisterInfo &HRI;
+  };
+
+  LLVM_ATTRIBUTE_UNUSED
+  raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &P) {
+    if (P.Rs.Reg != 0)
+      OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);
+    else
+      OS << "noreg";
+    return OS;
+  }
+
+  struct PrintExpr {
+    PrintExpr(const HCE::ExtExpr &E, const HexagonRegisterInfo &I)
+      : Ex(E), HRI(I) {}
+    const HCE::ExtExpr &Ex;
+    const HexagonRegisterInfo &HRI;
+  };
+
+  LLVM_ATTRIBUTE_UNUSED
+  raw_ostream &operator<< (raw_ostream &OS, const PrintExpr &P) {
+    OS << "## " << (P.Ex.Neg ? "- " : "+ ");
+    if (P.Ex.Rs.Reg != 0)
+      OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
+    else
+      OS << "__";
+    OS << " << " << P.Ex.S;
+    return OS;
+  }
+
+  struct PrintInit {
+    PrintInit(const HCE::ExtenderInit &EI, const HexagonRegisterInfo &I)
+      : ExtI(EI), HRI(I) {}
+    const HCE::ExtenderInit &ExtI;
+    const HexagonRegisterInfo &HRI;
+  };
+
+  LLVM_ATTRIBUTE_UNUSED
+  raw_ostream &operator<< (raw_ostream &OS, const PrintInit &P) {
+    OS << '[' << P.ExtI.first << ", "
+       << PrintExpr(P.ExtI.second, P.HRI) << ']';
+    return OS;
+  }
+
+  LLVM_ATTRIBUTE_UNUSED
+  raw_ostream &operator<< (raw_ostream &OS, const HCE::ExtDesc &ED) {
+    assert(ED.OpNum != -1u);
+    const MachineBasicBlock &MBB = *ED.getOp().getParent()->getParent();
+    const MachineFunction &MF = *MBB.getParent();
+    const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
+    OS << "bb#" << MBB.getNumber() << ": ";
+    if (ED.Rd.Reg != 0)
+      OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
+    else
+      OS << "__";
+    OS << " = " << PrintExpr(ED.Expr, HRI);
+    if (ED.IsDef)
+      OS << ", def";
+    return OS;
+  }
+
+  LLVM_ATTRIBUTE_UNUSED
+  raw_ostream &operator<< (raw_ostream &OS, const HCE::ExtRoot &ER) {
+    switch (ER.Kind) {
+      case MachineOperand::MO_Immediate:
+        OS << "imm:" << ER.V.ImmVal;
+        break;
+      case MachineOperand::MO_FPImmediate:
+        OS << "fpi:" << *ER.V.CFP;
+        break;
+      case MachineOperand::MO_ExternalSymbol:
+        OS << "sym:" << *ER.V.SymbolName;
+        break;
+      case MachineOperand::MO_GlobalAddress:
+        OS << "gad:" << ER.V.GV->getName();
+        break;
+      case MachineOperand::MO_BlockAddress:
+        OS << "blk:" << *ER.V.BA;
+        break;
+      case MachineOperand::MO_TargetIndex:
+        OS << "tgi:" << ER.V.ImmVal;
+        break;
+      case MachineOperand::MO_ConstantPoolIndex:
+        OS << "cpi:" << ER.V.ImmVal;
+        break;
+      case MachineOperand::MO_JumpTableIndex:
+        OS << "jti:" << ER.V.ImmVal;
+        break;
+      default:
+        OS << "???:" << ER.V.ImmVal;
+        break;
+    }
+    return OS;
+  }
+
+  LLVM_ATTRIBUTE_UNUSED
+  raw_ostream &operator<< (raw_ostream &OS, const HCE::ExtValue &EV) {
+    OS << HCE::ExtRoot(EV) << "  off:" << EV.Offset;
+    return OS;
+  }
+
+  struct PrintIMap {
+    PrintIMap(const HCE::AssignmentMap &M, const HexagonRegisterInfo &I)
+      : IMap(M), HRI(I) {}
+    const HCE::AssignmentMap &IMap;
+    const HexagonRegisterInfo &HRI;
+  };
+
+  LLVM_ATTRIBUTE_UNUSED
+  raw_ostream &operator<< (raw_ostream &OS, const PrintIMap &P) {
+    OS << "{\n";
+    for (const std::pair<HCE::ExtenderInit,HCE::IndexList> &Q : P.IMap) {
+      OS << "  " << PrintInit(Q.first, P.HRI) << " -> {";
+      for (unsigned I : Q.second)
+        OS << ' ' << I;
+      OS << " }\n";
+    }
+    OS << "}\n";
+    return OS;
+  }
+}
+
+INITIALIZE_PASS_BEGIN(HexagonConstExtenders, "hexagon-cext-opt",
+      "Hexagon constant-extender optimization", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_END(HexagonConstExtenders, "hexagon-cext-opt",
+      "Hexagon constant-extender optimization", false, false)
+
+static unsigned ReplaceCounter = 0;
+
+char HCE::ID = 0;
+
+#ifndef NDEBUG
+LLVM_DUMP_METHOD void RangeTree::dump() const {
+  dbgs() << "Root: " << Root << '\n';
+  if (Root)
+    dump(Root);
+}
+
+LLVM_DUMP_METHOD void RangeTree::dump(const Node *N) const {
+  dbgs() << "Node: " << N << '\n';
+  dbgs() << "  Height: " << N->Height << '\n';
+  dbgs() << "  Count: " << N->Count << '\n';
+  dbgs() << "  MaxEnd: " << N->MaxEnd << '\n';
+  dbgs() << "  Range: " << N->Range << '\n';
+  dbgs() << "  Left: " << N->Left << '\n';
+  dbgs() << "  Right: " << N->Right << "\n\n";
+
+  if (N->Left)
+    dump(N->Left);
+  if (N->Right)
+    dump(N->Right);
+}
+#endif
+
+void RangeTree::order(Node *N, SmallVectorImpl<Node*> &Seq) const {
+  if (N == nullptr)
+    return;
+  order(N->Left, Seq);
+  Seq.push_back(N);
+  order(N->Right, Seq);
+}
+
+void RangeTree::nodesWith(Node *N, int32_t P, bool CheckA,
+      SmallVectorImpl<Node*> &Seq) const {
+  if (N == nullptr || N->MaxEnd < P)
+    return;
+  nodesWith(N->Left, P, CheckA, Seq);
+  if (N->Range.Min <= P) {
+    if ((CheckA && N->Range.contains(P)) || (!CheckA && P <= N->Range.Max))
+      Seq.push_back(N);
+    nodesWith(N->Right, P, CheckA, Seq);
+  }
+}
+
+RangeTree::Node *RangeTree::add(Node *N, const OffsetRange &R) {
+  if (N == nullptr)
+    return new Node(R);
+
+  if (N->Range == R) {
+    N->Count++;
+    return N;
+  }
+
+  if (R < N->Range)
+    N->Left = add(N->Left, R);
+  else
+    N->Right = add(N->Right, R);
+  return rebalance(update(N));
+}
+
+RangeTree::Node *RangeTree::remove(Node *N, const Node *D) {
+  assert(N != nullptr);
+
+  if (N != D) {
+    assert(N->Range != D->Range && "N and D should not be equal");
+    if (D->Range < N->Range)
+      N->Left = remove(N->Left, D);
+    else
+      N->Right = remove(N->Right, D);
+    return rebalance(update(N));
+  }
+
+  // We got to the node we need to remove. If any of its children are
+  // missing, simply replace it with the other child.
+  if (N->Left == nullptr || N->Right == nullptr)
+    return (N->Left == nullptr) ? N->Right : N->Left;
+
+  // Find the rightmost child of N->Left, remove it and plug it in place
+  // of N.
+  Node *M = N->Left;
+  while (M->Right)
+    M = M->Right;
+  M->Left = remove(N->Left, M);
+  M->Right = N->Right;
+  return rebalance(update(M));
+}
+
+RangeTree::Node *RangeTree::rotateLeft(Node *Lower, Node *Higher) {
+  assert(Higher->Right == Lower);
+  // The Lower node is on the right from Higher. Make sure that Lower's
+  // balance is greater to the right. Otherwise the rotation will create
+  // an unbalanced tree again.
+  if (height(Lower->Left) > height(Lower->Right))
+    Lower = rotateRight(Lower->Left, Lower);
+  assert(height(Lower->Left) <= height(Lower->Right));
+  Higher->Right = Lower->Left;
+  update(Higher);
+  Lower->Left = Higher;
+  update(Lower);
+  return Lower;
+}
+
+RangeTree::Node *RangeTree::rotateRight(Node *Lower, Node *Higher) {
+  assert(Higher->Left == Lower);
+  // The Lower node is on the left from Higher. Make sure that Lower's
+  // balance is greater to the left. Otherwise the rotation will create
+  // an unbalanced tree again.
+  if (height(Lower->Left) < height(Lower->Right))
+    Lower = rotateLeft(Lower->Right, Lower);
+  assert(height(Lower->Left) >= height(Lower->Right));
+  Higher->Left = Lower->Right;
+  update(Higher);
+  Lower->Right = Higher;
+  update(Lower);
+  return Lower;
+}
+
+
+HCE::ExtRoot::ExtRoot(const MachineOperand &Op) {
+  // Always store ImmVal, since it's the field used for comparisons.
+  V.ImmVal = 0;
+  if (Op.isImm())
+    ; // Keep 0. Do not use Op.getImm() for value here (treat 0 as the root).
+  else if (Op.isFPImm())
+    V.CFP = Op.getFPImm();
+  else if (Op.isSymbol())
+    V.SymbolName = Op.getSymbolName();
+  else if (Op.isGlobal())
+    V.GV = Op.getGlobal();
+  else if (Op.isBlockAddress())
+    V.BA = Op.getBlockAddress();
+  else if (Op.isCPI() || Op.isTargetIndex() || Op.isJTI())
+    V.ImmVal = Op.getIndex();
+  else
+    llvm_unreachable("Unexpected operand type");
+
+  Kind = Op.getType();
+  TF = Op.getTargetFlags();
+}
+
+bool HCE::ExtRoot::operator< (const HCE::ExtRoot &ER) const {
+  if (Kind != ER.Kind)
+    return Kind < ER.Kind;
+  switch (Kind) {
+    case MachineOperand::MO_Immediate:
+    case MachineOperand::MO_TargetIndex:
+    case MachineOperand::MO_ConstantPoolIndex:
+    case MachineOperand::MO_JumpTableIndex:
+      return V.ImmVal < ER.V.ImmVal;
+    case MachineOperand::MO_FPImmediate: {
+      const APFloat &ThisF = V.CFP->getValueAPF();
+      const APFloat &OtherF = ER.V.CFP->getValueAPF();
+      return ThisF.bitcastToAPInt().ult(OtherF.bitcastToAPInt());
+    }
+    case MachineOperand::MO_ExternalSymbol:
+      return StringRef(V.SymbolName) < StringRef(ER.V.SymbolName);
+    case MachineOperand::MO_GlobalAddress:
+      assert(V.GV->hasName() && ER.V.GV->hasName());
+      return V.GV->getName() < ER.V.GV->getName();
+    case MachineOperand::MO_BlockAddress: {
+      const BasicBlock *ThisB = V.BA->getBasicBlock();
+      const BasicBlock *OtherB = ER.V.BA->getBasicBlock();
+      assert(ThisB->getParent() == OtherB->getParent());
+      const Function &F = *ThisB->getParent();
+      return std::distance(F.begin(), ThisB->getIterator()) <
+             std::distance(F.begin(), OtherB->getIterator());
+    }
+  }
+  return V.ImmVal < ER.V.ImmVal;
+}
+
+HCE::ExtValue::ExtValue(const MachineOperand &Op) : ExtRoot(Op) {
+  if (Op.isImm())
+    Offset = Op.getImm();
+  else if (Op.isFPImm() || Op.isJTI())
+    Offset = 0;
+  else if (Op.isSymbol() || Op.isGlobal() || Op.isBlockAddress() ||
+           Op.isCPI() || Op.isTargetIndex())
+    Offset = Op.getOffset();
+  else
+    llvm_unreachable("Unexpected operand type");
+}
+
+bool HCE::ExtValue::operator< (const HCE::ExtValue &EV) const {
+  const ExtRoot &ER = *this;
+  if (!(ER == ExtRoot(EV)))
+    return ER < EV;
+  return Offset < EV.Offset;
+}
+
+HCE::ExtValue::operator MachineOperand() const {
+  switch (Kind) {
+    case MachineOperand::MO_Immediate:
+      return MachineOperand::CreateImm(V.ImmVal + Offset);
+    case MachineOperand::MO_FPImmediate:
+      assert(Offset == 0);
+      return MachineOperand::CreateFPImm(V.CFP);
+    case MachineOperand::MO_ExternalSymbol:
+      assert(Offset == 0);
+      return MachineOperand::CreateES(V.SymbolName, TF);
+    case MachineOperand::MO_GlobalAddress:
+      return MachineOperand::CreateGA(V.GV, Offset, TF);
+    case MachineOperand::MO_BlockAddress:
+      return MachineOperand::CreateBA(V.BA, Offset, TF);
+    case MachineOperand::MO_TargetIndex:
+      return MachineOperand::CreateTargetIndex(V.ImmVal, Offset, TF);
+    case MachineOperand::MO_ConstantPoolIndex:
+      return MachineOperand::CreateCPI(V.ImmVal, Offset, TF);
+    case MachineOperand::MO_JumpTableIndex:
+      assert(Offset == 0);
+    default:
+      llvm_unreachable("Unhandled kind");
+ }
+}
+
+bool HCE::isStoreImmediate(unsigned Opc) const {
+  switch (Opc) {
+    case Hexagon::S4_storeirbt_io:
+    case Hexagon::S4_storeirbf_io:
+    case Hexagon::S4_storeirht_io:
+    case Hexagon::S4_storeirhf_io:
+    case Hexagon::S4_storeirit_io:
+    case Hexagon::S4_storeirif_io:
+    case Hexagon::S4_storeirb_io:
+    case Hexagon::S4_storeirh_io:
+    case Hexagon::S4_storeiri_io:
+      return true;
+    default:
+      break;
+  }
+  return false;
+}
+
+bool HCE::isRegOffOpcode(unsigned Opc) const {
+  switch (Opc) {
+    case Hexagon::L2_loadrub_io:
+    case Hexagon::L2_loadrb_io:
+    case Hexagon::L2_loadruh_io:
+    case Hexagon::L2_loadrh_io:
+    case Hexagon::L2_loadri_io:
+    case Hexagon::L2_loadrd_io:
+    case Hexagon::L2_loadbzw2_io:
+    case Hexagon::L2_loadbzw4_io:
+    case Hexagon::L2_loadbsw2_io:
+    case Hexagon::L2_loadbsw4_io:
+    case Hexagon::L2_loadalignh_io:
+    case Hexagon::L2_loadalignb_io:
+    case Hexagon::L2_ploadrubt_io:
+    case Hexagon::L2_ploadrubf_io:
+    case Hexagon::L2_ploadrbt_io:
+    case Hexagon::L2_ploadrbf_io:
+    case Hexagon::L2_ploadruht_io:
+    case Hexagon::L2_ploadruhf_io:
+    case Hexagon::L2_ploadrht_io:
+    case Hexagon::L2_ploadrhf_io:
+    case Hexagon::L2_ploadrit_io:
+    case Hexagon::L2_ploadrif_io:
+    case Hexagon::L2_ploadrdt_io:
+    case Hexagon::L2_ploadrdf_io:
+    case Hexagon::S2_storerb_io:
+    case Hexagon::S2_storerh_io:
+    case Hexagon::S2_storerf_io:
+    case Hexagon::S2_storeri_io:
+    case Hexagon::S2_storerd_io:
+    case Hexagon::S2_pstorerbt_io:
+    case Hexagon::S2_pstorerbf_io:
+    case Hexagon::S2_pstorerht_io:
+    case Hexagon::S2_pstorerhf_io:
+    case Hexagon::S2_pstorerft_io:
+    case Hexagon::S2_pstorerff_io:
+    case Hexagon::S2_pstorerit_io:
+    case Hexagon::S2_pstorerif_io:
+    case Hexagon::S2_pstorerdt_io:
+    case Hexagon::S2_pstorerdf_io:
+    case Hexagon::A2_addi:
+      return true;
+    default:
+      break;
+  }
+  return false;
+}
+
+unsigned HCE::getRegOffOpcode(unsigned ExtOpc) const {
+  // If there exists an instruction that takes a register and offset,
+  // that corresponds to the ExtOpc, return it, otherwise return 0.
+  using namespace Hexagon;
+  switch (ExtOpc) {
+    case A2_tfrsi:    return A2_addi;
+    default:
+      break;
+  }
+  const MCInstrDesc &D = HII->get(ExtOpc);
+  if (D.mayLoad() || D.mayStore()) {
+    uint64_t F = D.TSFlags;
+    unsigned AM = (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
+    switch (AM) {
+      case HexagonII::Absolute:
+      case HexagonII::AbsoluteSet:
+      case HexagonII::BaseLongOffset:
+        switch (ExtOpc) {
+          case PS_loadrubabs:
+          case L4_loadrub_ap:
+          case L4_loadrub_ur:     return L2_loadrub_io;
+          case PS_loadrbabs:
+          case L4_loadrb_ap:
+          case L4_loadrb_ur:      return L2_loadrb_io;
+          case PS_loadruhabs:
+          case L4_loadruh_ap:
+          case L4_loadruh_ur:     return L2_loadruh_io;
+          case PS_loadrhabs:
+          case L4_loadrh_ap:
+          case L4_loadrh_ur:      return L2_loadrh_io;
+          case PS_loadriabs:
+          case L4_loadri_ap:
+          case L4_loadri_ur:      return L2_loadri_io;
+          case PS_loadrdabs:
+          case L4_loadrd_ap:
+          case L4_loadrd_ur:      return L2_loadrd_io;
+          case L4_loadbzw2_ap:
+          case L4_loadbzw2_ur:    return L2_loadbzw2_io;
+          case L4_loadbzw4_ap:
+          case L4_loadbzw4_ur:    return L2_loadbzw4_io;
+          case L4_loadbsw2_ap:
+          case L4_loadbsw2_ur:    return L2_loadbsw2_io;
+          case L4_loadbsw4_ap:
+          case L4_loadbsw4_ur:    return L2_loadbsw4_io;
+          case L4_loadalignh_ap:
+          case L4_loadalignh_ur:  return L2_loadalignh_io;
+          case L4_loadalignb_ap:
+          case L4_loadalignb_ur:  return L2_loadalignb_io;
+          case L4_ploadrubt_abs:  return L2_ploadrubt_io;
+          case L4_ploadrubf_abs:  return L2_ploadrubf_io;
+          case L4_ploadrbt_abs:   return L2_ploadrbt_io;
+          case L4_ploadrbf_abs:   return L2_ploadrbf_io;
+          case L4_ploadruht_abs:  return L2_ploadruht_io;
+          case L4_ploadruhf_abs:  return L2_ploadruhf_io;
+          case L4_ploadrht_abs:   return L2_ploadrht_io;
+          case L4_ploadrhf_abs:   return L2_ploadrhf_io;
+          case L4_ploadrit_abs:   return L2_ploadrit_io;
+          case L4_ploadrif_abs:   return L2_ploadrif_io;
+          case L4_ploadrdt_abs:   return L2_ploadrdt_io;
+          case L4_ploadrdf_abs:   return L2_ploadrdf_io;
+          case PS_storerbabs:
+          case S4_storerb_ap:
+          case S4_storerb_ur:     return S2_storerb_io;
+          case PS_storerhabs:
+          case S4_storerh_ap:
+          case S4_storerh_ur:     return S2_storerh_io;
+          case PS_storerfabs:
+          case S4_storerf_ap:
+          case S4_storerf_ur:     return S2_storerf_io;
+          case PS_storeriabs:
+          case S4_storeri_ap:
+          case S4_storeri_ur:     return S2_storeri_io;
+          case PS_storerdabs:
+          case S4_storerd_ap:
+          case S4_storerd_ur:     return S2_storerd_io;
+          case S4_pstorerbt_abs:  return S2_pstorerbt_io;
+          case S4_pstorerbf_abs:  return S2_pstorerbf_io;
+          case S4_pstorerht_abs:  return S2_pstorerht_io;
+          case S4_pstorerhf_abs:  return S2_pstorerhf_io;
+          case S4_pstorerft_abs:  return S2_pstorerft_io;
+          case S4_pstorerff_abs:  return S2_pstorerff_io;
+          case S4_pstorerit_abs:  return S2_pstorerit_io;
+          case S4_pstorerif_abs:  return S2_pstorerif_io;
+          case S4_pstorerdt_abs:  return S2_pstorerdt_io;
+          case S4_pstorerdf_abs:  return S2_pstorerdf_io;
+          default:
+            break;
+        }
+        break;
+      case HexagonII::BaseImmOffset:
+        if (!isStoreImmediate(ExtOpc))
+          return ExtOpc;
+        break;
+      default:
+        break;
+    }
+  }
+  return 0;
+}
+
+unsigned HCE::getDirectRegReplacement(unsigned ExtOpc) const {
+  switch (ExtOpc) {
+    case Hexagon::A2_addi:          return Hexagon::A2_add;
+    case Hexagon::A2_andir:         return Hexagon::A2_and;
+    case Hexagon::A2_combineii:     return Hexagon::A4_combineri;
+    case Hexagon::A2_orir:          return Hexagon::A2_or;
+    case Hexagon::A2_paddif:        return Hexagon::A2_paddf;
+    case Hexagon::A2_paddit:        return Hexagon::A2_paddt;
+    case Hexagon::A2_subri:         return Hexagon::A2_sub;
+    case Hexagon::A2_tfrsi:         return TargetOpcode::COPY;
+    case Hexagon::A4_cmpbeqi:       return Hexagon::A4_cmpbeq;
+    case Hexagon::A4_cmpbgti:       return Hexagon::A4_cmpbgt;
+    case Hexagon::A4_cmpbgtui:      return Hexagon::A4_cmpbgtu;
+    case Hexagon::A4_cmpheqi:       return Hexagon::A4_cmpheq;
+    case Hexagon::A4_cmphgti:       return Hexagon::A4_cmphgt;
+    case Hexagon::A4_cmphgtui:      return Hexagon::A4_cmphgtu;
+    case Hexagon::A4_combineii:     return Hexagon::A4_combineir;
+    case Hexagon::A4_combineir:     return TargetOpcode::REG_SEQUENCE;
+    case Hexagon::A4_combineri:     return TargetOpcode::REG_SEQUENCE;
+    case Hexagon::A4_rcmpeqi:       return Hexagon::A4_rcmpeq;
+    case Hexagon::A4_rcmpneqi:      return Hexagon::A4_rcmpneq;
+    case Hexagon::C2_cmoveif:       return Hexagon::A2_tfrpf;
+    case Hexagon::C2_cmoveit:       return Hexagon::A2_tfrpt;
+    case Hexagon::C2_cmpeqi:        return Hexagon::C2_cmpeq;
+    case Hexagon::C2_cmpgti:        return Hexagon::C2_cmpgt;
+    case Hexagon::C2_cmpgtui:       return Hexagon::C2_cmpgtu;
+    case Hexagon::C2_muxii:         return Hexagon::C2_muxir;
+    case Hexagon::C2_muxir:         return Hexagon::C2_mux;
+    case Hexagon::C2_muxri:         return Hexagon::C2_mux;
+    case Hexagon::C4_cmpltei:       return Hexagon::C4_cmplte;
+    case Hexagon::C4_cmplteui:      return Hexagon::C4_cmplteu;
+    case Hexagon::C4_cmpneqi:       return Hexagon::C4_cmpneq;
+    case Hexagon::M2_accii:         return Hexagon::M2_acci;        // T -> T
+    /* No M2_macsin */
+    case Hexagon::M2_macsip:        return Hexagon::M2_maci;        // T -> T
+    case Hexagon::M2_mpysin:        return Hexagon::M2_mpyi;
+    case Hexagon::M2_mpysip:        return Hexagon::M2_mpyi;
+    case Hexagon::M2_mpysmi:        return Hexagon::M2_mpyi;
+    case Hexagon::M2_naccii:        return Hexagon::M2_nacci;       // T -> T
+    case Hexagon::M4_mpyri_addi:    return Hexagon::M4_mpyri_addr;
+    case Hexagon::M4_mpyri_addr:    return Hexagon::M4_mpyrr_addr;  // _ -> T
+    case Hexagon::M4_mpyrr_addi:    return Hexagon::M4_mpyrr_addr;  // _ -> T
+    case Hexagon::S4_addaddi:       return Hexagon::M2_acci;        // _ -> T
+    case Hexagon::S4_addi_asl_ri:   return Hexagon::S2_asl_i_r_acc; // T -> T
+    case Hexagon::S4_addi_lsr_ri:   return Hexagon::S2_lsr_i_r_acc; // T -> T
+    case Hexagon::S4_andi_asl_ri:   return Hexagon::S2_asl_i_r_and; // T -> T
+    case Hexagon::S4_andi_lsr_ri:   return Hexagon::S2_lsr_i_r_and; // T -> T
+    case Hexagon::S4_ori_asl_ri:    return Hexagon::S2_asl_i_r_or;  // T -> T
+    case Hexagon::S4_ori_lsr_ri:    return Hexagon::S2_lsr_i_r_or;  // T -> T
+    case Hexagon::S4_subaddi:       return Hexagon::M2_subacc;      // _ -> T
+    case Hexagon::S4_subi_asl_ri:   return Hexagon::S2_asl_i_r_nac; // T -> T
+    case Hexagon::S4_subi_lsr_ri:   return Hexagon::S2_lsr_i_r_nac; // T -> T
+
+    // Store-immediates:
+    case Hexagon::S4_storeirbf_io:  return Hexagon::S2_pstorerbf_io;
+    case Hexagon::S4_storeirb_io:   return Hexagon::S2_storerb_io;
+    case Hexagon::S4_storeirbt_io:  return Hexagon::S2_pstorerbt_io;
+    case Hexagon::S4_storeirhf_io:  return Hexagon::S2_pstorerhf_io;
+    case Hexagon::S4_storeirh_io:   return Hexagon::S2_storerh_io;
+    case Hexagon::S4_storeirht_io:  return Hexagon::S2_pstorerht_io;
+    case Hexagon::S4_storeirif_io:  return Hexagon::S2_pstorerif_io;
+    case Hexagon::S4_storeiri_io:   return Hexagon::S2_storeri_io;
+    case Hexagon::S4_storeirit_io:  return Hexagon::S2_pstorerit_io;
+
+    default:
+      break;
+  }
+  return 0;
+}
+
+// Return the allowable deviation from the current value of Rb which the
+// instruction MI can accommodate.
+// The instruction MI is a user of register Rb, which is defined via an
+// extender. It may be possible for MI to be tweaked to work for a register
+// defined with a slightly different value. For example
+//   ... = L2_loadrub_io Rb, 0
+// can be modifed to be
+//   ... = L2_loadrub_io Rb', 1
+// if Rb' = Rb-1.
+OffsetRange HCE::getOffsetRange(Register Rb, const MachineInstr &MI) const {
+  unsigned Opc = MI.getOpcode();
+  // Instructions that are constant-extended may be replaced with something
+  // else that no longer offers the same range as the original.
+  if (!isRegOffOpcode(Opc) || HII->isConstExtended(MI))
+    return OffsetRange::zero();
+
+  if (Opc == Hexagon::A2_addi) {
+    const MachineOperand &Op1 = MI.getOperand(1), &Op2 = MI.getOperand(2);
+    if (Rb != Register(Op1) || !Op2.isImm())
+      return OffsetRange::zero();
+    OffsetRange R = { -(1<<15)+1, (1<<15)-1, 1 };
+    return R.shift(Op2.getImm());
+  }
+
+  // HII::getBaseAndOffsetPosition returns the increment position as "offset".
+  if (HII->isPostIncrement(MI))
+    return OffsetRange::zero();
+
+  const MCInstrDesc &D = HII->get(Opc);
+  assert(D.mayLoad() || D.mayStore());
+
+  unsigned BaseP, OffP;
+  if (!HII->getBaseAndOffsetPosition(MI, BaseP, OffP) ||
+      Rb != Register(MI.getOperand(BaseP)) ||
+      !MI.getOperand(OffP).isImm())
+    return OffsetRange::zero();
+
+  uint64_t F = (D.TSFlags >> HexagonII::MemAccessSizePos) &
+                  HexagonII::MemAccesSizeMask;
+  uint8_t A = HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(F));
+  unsigned L = Log2_32(A);
+  unsigned S = 10+L;  // sint11_L
+  int32_t Min = -alignDown((1<<S)-1, A);
+
+  // The range will be shifted by Off. To prefer non-negative offsets,
+  // adjust Max accordingly.
+  int32_t Off = MI.getOperand(OffP).getImm();
+  int32_t Max = Off >= 0 ? 0 : -Off;
+
+  OffsetRange R = { Min, Max, A };
+  return R.shift(Off);
+}
+
+// Return the allowable deviation from the current value of the extender ED,
+// for which the instruction corresponding to ED can be modified without
+// using an extender.
+// The instruction uses the extender directly. It will be replaced with
+// another instruction, say MJ, where the extender will be replaced with a
+// register. MJ can allow some variability with respect to the value of
+// that register, as is the case with indexed memory instructions.
+OffsetRange HCE::getOffsetRange(const ExtDesc &ED) const {
+  // The only way that there can be a non-zero range available is if
+  // the instruction using ED will be converted to an indexed memory
+  // instruction.
+  unsigned IdxOpc = getRegOffOpcode(ED.UseMI->getOpcode());
+  switch (IdxOpc) {
+    case 0:
+      return OffsetRange::zero();
+    case Hexagon::A2_addi:    // s16
+      return { -32767, 32767, 1 };
+    case Hexagon::A2_subri:   // s10
+      return { -511, 511, 1 };
+  }
+
+  if (!ED.UseMI->mayLoad() && !ED.UseMI->mayStore())
+    return OffsetRange::zero();
+  const MCInstrDesc &D = HII->get(IdxOpc);
+  uint64_t F = (D.TSFlags >> HexagonII::MemAccessSizePos) &
+                  HexagonII::MemAccesSizeMask;
+  uint8_t A = HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(F));
+  unsigned L = Log2_32(A);
+  unsigned S = 10+L;  // sint11_L
+  int32_t Min = -alignDown((1<<S)-1, A);
+  int32_t Max = 0;  // Force non-negative offsets.
+  return { Min, Max, A };
+}
+
+// Get the allowable deviation from the current value of Rd by checking
+// all uses of Rd.
+OffsetRange HCE::getOffsetRange(Register Rd) const {
+  OffsetRange Range;
+  for (const MachineOperand &Op : MRI->use_operands(Rd.Reg)) {
+    // Make sure that the register being used by this operand is identical
+    // to the register that was defined: using a different subregister
+    // precludes any non-trivial range.
+    if (Rd != Register(Op))
+      return OffsetRange::zero();
+    Range.intersect(getOffsetRange(Rd, *Op.getParent()));
+  }
+  return Range;
+}
+
+void HCE::recordExtender(MachineInstr &MI, unsigned OpNum) {
+  unsigned Opc = MI.getOpcode();
+  ExtDesc ED;
+  ED.OpNum = OpNum;
+
+  bool IsLoad = MI.mayLoad();
+  bool IsStore = MI.mayStore();
+
+  if (IsLoad || IsStore) {
+    unsigned AM = HII->getAddrMode(MI);
+    switch (AM) {
+      // (Re: ##Off + Rb<<S) = Rd: ##Val
+      case HexagonII::Absolute:       // (__: ## + __<<_)
+        break;
+      case HexagonII::AbsoluteSet:    // (Rd: ## + __<<_)
+        ED.Rd = MI.getOperand(OpNum-1);
+        ED.IsDef = true;
+        break;
+      case HexagonII::BaseImmOffset:  // (__: ## + Rs<<0)
+        // Store-immediates are treated as non-memory operations, since
+        // it's the value being stored that is extended (as opposed to
+        // a part of the address).
+        if (!isStoreImmediate(Opc))
+          ED.Expr.Rs = MI.getOperand(OpNum-1);
+        break;
+      case HexagonII::BaseLongOffset: // (__: ## + Rs<<S)
+        ED.Expr.Rs = MI.getOperand(OpNum-2);
+        ED.Expr.S = MI.getOperand(OpNum-1).getImm();
+        break;
+      default:
+        llvm_unreachable("Unhandled memory instruction");
+    }
+  } else {
+    switch (Opc) {
+      case Hexagon::A2_tfrsi:         // (Rd: ## + __<<_)
+        ED.Rd = MI.getOperand(0);
+        ED.IsDef = true;
+        break;
+      case Hexagon::A2_combineii:     // (Rd: ## + __<<_)
+      case Hexagon::A4_combineir:
+        ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_hi };
+        ED.IsDef = true;
+        break;
+      case Hexagon::A4_combineri:     // (Rd: ## + __<<_)
+        ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_lo };
+        ED.IsDef = true;
+        break;
+      case Hexagon::A2_addi:          // (Rd: ## + Rs<<0)
+        ED.Rd = MI.getOperand(0);
+        ED.Expr.Rs = MI.getOperand(OpNum-1);
+        break;
+      case Hexagon::M2_accii:         // (__: ## + Rs<<0)
+      case Hexagon::M2_naccii:
+      case Hexagon::S4_addaddi:
+        ED.Expr.Rs = MI.getOperand(OpNum-1);
+        break;
+      case Hexagon::A2_subri:         // (Rd: ## - Rs<<0)
+        ED.Rd = MI.getOperand(0);
+        ED.Expr.Rs = MI.getOperand(OpNum+1);
+        ED.Expr.Neg = true;
+        break;
+      case Hexagon::S4_subaddi:       // (__: ## - Rs<<0)
+        ED.Expr.Rs = MI.getOperand(OpNum+1);
+        ED.Expr.Neg = true;
+      default:                        // (__: ## + __<<_)
+        break;
+    }
+  }
+
+  ED.UseMI = &MI;
+  Extenders.push_back(ED);
+}
+
+void HCE::collectInstr(MachineInstr &MI) {
+  if (!HII->isConstExtended(MI))
+    return;
+
+  // Skip some non-convertible instructions.
+  unsigned Opc = MI.getOpcode();
+  switch (Opc) {
+    case Hexagon::M2_macsin:  // There is no Rx -= mpyi(Rs,Rt).
+    case Hexagon::C4_addipc:
+    case Hexagon::S4_or_andi:
+    case Hexagon::S4_or_andix:
+    case Hexagon::S4_or_ori:
+      return;
+  }
+  recordExtender(MI, HII->getCExtOpNum(MI));
+}
+
+void HCE::collect(MachineFunction &MF) {
+  Extenders.clear();
+  for (MachineBasicBlock &MBB : MF)
+    for (MachineInstr &MI : MBB)
+      collectInstr(MI);
+}
+
+void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End,
+      AssignmentMap &IMap) {
+  // Sanity check: make sure that all extenders in the range [Begin..End)
+  // share the same root ER.
+  for (unsigned I = Begin; I != End; ++I)
+    assert(ER == ExtRoot(Extenders[I].getOp()));
+
+  // Construct the list of ranges, such that for each P in Ranges[I],
+  // a register Reg = ER+P can be used in place of Extender[I]. If the
+  // instruction allows, uses in the form of Reg+Off are considered
+  // (here, Off = required_value - P).
+  std::vector<OffsetRange> Ranges(End-Begin);
+
+  // For each extender that is a def, visit all uses of the defined register,
+  // and produce an offset range that works for all uses. The def doesn't
+  // have to be checked, because it can become dead if all uses can be updated
+  // to use a different reg/offset.
+  for (unsigned I = Begin; I != End; ++I) {
+    const ExtDesc &ED = Extenders[I];
+    if (!ED.IsDef)
+      continue;
+    ExtValue EV(ED);
+    DEBUG(dbgs() << " =" << I << ". " << EV << "  " << ED << '\n');
+    assert(ED.Rd.Reg != 0);
+    Ranges[I-Begin] = getOffsetRange(ED.Rd).shift(EV.Offset);
+    // A2_tfrsi is a special case: it will be replaced with A2_addi, which
+    // has a 16-bit signed offset. This means that A2_tfrsi not only has a
+    // range coming from its uses, but also from the fact that its replacement
+    // has a range as well.
+    if (ED.UseMI->getOpcode() == Hexagon::A2_tfrsi) {
+      int32_t D = alignDown(32767, Ranges[I-Begin].Align); // XXX hardcoded
+      Ranges[I-Begin].extendBy(-D).extendBy(D);
+    }
+  }
+
+  // Visit all non-def extenders. For each one, determine the offset range
+  // available for it.
+  for (unsigned I = Begin; I != End; ++I) {
+    const ExtDesc &ED = Extenders[I];
+    if (ED.IsDef)
+      continue;
+    ExtValue EV(ED);
+    DEBUG(dbgs() << "  " << I << ". " << EV << "  " << ED << '\n');
+    OffsetRange Dev = getOffsetRange(ED);
+    Ranges[I-Begin].intersect(Dev.shift(EV.Offset));
+  }
+
+  // Here for each I there is a corresponding Range[I]. Construct the
+  // inverse map, that to each range will assign the set of indexes in
+  // [Begin..End) that this range corresponds to.
+  std::map<OffsetRange, IndexList> RangeMap;
+  for (unsigned I = Begin; I != End; ++I)
+    RangeMap[Ranges[I-Begin]].insert(I);
+
+  DEBUG({
+    dbgs() << "Ranges\n";
+    for (unsigned I = Begin; I != End; ++I)
+      dbgs() << "  " << I << ". " << Ranges[I-Begin] << '\n';
+    dbgs() << "RangeMap\n";
+    for (auto &P : RangeMap) {
+      dbgs() << "  " << P.first << " ->";
+      for (unsigned I : P.second)
+        dbgs() << ' ' << I;
+      dbgs() << '\n';
+    }
+  });
+
+  // Select the definition points, and generate the assignment between
+  // these points and the uses.
+
+  // For each candidate offset, keep a pair CandData consisting of
+  // the total number of ranges containing that candidate, and the
+  // vector of corresponding RangeTree nodes.
+  using CandData = std::pair<unsigned, SmallVector<RangeTree::Node*,8>>;
+  std::map<int32_t, CandData> CandMap;
+
+  RangeTree Tree;
+  for (const OffsetRange &R : Ranges)
+    Tree.add(R);
+  SmallVector<RangeTree::Node*,8> Nodes;
+  Tree.order(Nodes);
+
+  auto MaxAlign = [](const SmallVectorImpl<RangeTree::Node*> &Nodes) {
+    uint8_t Align = 1;
+    for (RangeTree::Node *N : Nodes)
+      Align = std::max(Align, N->Range.Align);
+    return Align;
+  };
+
+  // Construct the set of all potential definition points from the endpoints
+  // of the ranges. If a given endpoint also belongs to a different range,
+  // but with a higher alignment, also consider the more-highly-aligned
+  // value of this endpoint.
+  std::set<int32_t> CandSet;
+  for (RangeTree::Node *N : Nodes) {
+    const OffsetRange &R = N->Range;
+    uint8_t A0 = MaxAlign(Tree.nodesWith(R.Min, false));
+    CandSet.insert(R.Min);
+    if (R.Align < A0)
+      CandSet.insert(R.Min < 0 ? -alignDown(-R.Min, A0) : alignTo(R.Min, A0));
+    uint8_t A1 = MaxAlign(Tree.nodesWith(R.Max, false));
+    CandSet.insert(R.Max);
+    if (R.Align < A1)
+      CandSet.insert(R.Max < 0 ? -alignTo(-R.Max, A1) : alignDown(R.Max, A1));
+  }
+
+  // Build the assignment map: candidate C -> { list of extender indexes }.
+  // This has to be done iteratively:
+  // - pick the candidate that covers the maximum number of extenders,
+  // - add the candidate to the map,
+  // - remove the extenders from the pool.
+  while (true) {
+    using CMap = std::map<int32_t,unsigned>;
+    CMap Counts;
+    for (auto It = CandSet.begin(), Et = CandSet.end(); It != Et; ) {
+      auto &&V = Tree.nodesWith(*It);
+      unsigned N = std::accumulate(V.begin(), V.end(), 0u,
+                    [](unsigned Acc, const RangeTree::Node *N) {
+                      return Acc + N->Count;
+                    });
+      if (N != 0)
+        Counts.insert({*It, N});
+      It = (N != 0) ? std::next(It) : CandSet.erase(It);
+    }
+    if (Counts.empty())
+      break;
+
+    // Find the best candidate with respect to the number of extenders covered.
+    auto BestIt = std::max_element(Counts.begin(), Counts.end(),
+                    [](const CMap::value_type &A, const CMap::value_type &B) {
+                      return A.second < B.second ||
+                             (A.second == B.second && A < B);
+                    });
+    int32_t Best = BestIt->first;
+    ExtValue BestV(ER, Best);
+    for (RangeTree::Node *N : Tree.nodesWith(Best)) {
+      for (unsigned I : RangeMap[N->Range])
+        IMap[{BestV,Extenders[I].Expr}].insert(I);
+      Tree.erase(N);
+    }
+  }
+
+  DEBUG(dbgs() << "IMap (before fixup) = " << PrintIMap(IMap, *HRI));
+
+  // There is some ambiguity in what initializer should be used, if the
+  // descriptor's subexpression is non-trivial: it can be the entire
+  // subexpression (which is what has been done so far), or it can be
+  // the extender's value itself, if all corresponding extenders have the
+  // exact value of the initializer (i.e. require offset of 0).
+
+  // To reduce the number of initializers, merge such special cases.
+  for (std::pair<const ExtenderInit,IndexList> &P : IMap) {
+    // Skip trivial initializers.
+    if (P.first.second.trivial())
+      continue;
+    // If the corresponding trivial initializer does not exist, skip this
+    // entry.
+    const ExtValue &EV = P.first.first;
+    AssignmentMap::iterator F = IMap.find({EV, ExtExpr()});
+    if (F == IMap.end())
+      continue;
+    // Finally, check if all extenders have the same value as the initializer.
+    auto SameValue = [&EV,this](unsigned I) {
+      const ExtDesc &ED = Extenders[I];
+      return ExtValue(ED).Offset == EV.Offset;
+    };
+    if (all_of(P.second, SameValue)) {
+      F->second.insert(P.second.begin(), P.second.end());
+      P.second.clear();
+    }
+  }
+
+  DEBUG(dbgs() << "IMap (after fixup) = " << PrintIMap(IMap, *HRI));
+}
+
+void HCE::calculatePlacement(const ExtenderInit &ExtI, const IndexList &Refs,
+      LocDefMap &Defs) {
+  if (Refs.empty())
+    return;
+
+  // The placement calculation is somewhat simple right now: it finds a
+  // single location for the def that dominates all refs. Since this may
+  // place the def far from the uses, producing several locations for
+  // defs that collectively dominate all refs could be better.
+  // For now only do the single one.
+  DenseSet<MachineBasicBlock*> Blocks;
+  DenseSet<MachineInstr*> RefMIs;
+  const ExtDesc &ED0 = Extenders[Refs[0]];
+  MachineBasicBlock *DomB = ED0.UseMI->getParent();
+  RefMIs.insert(ED0.UseMI);
+  Blocks.insert(DomB);
+  for (unsigned i = 1, e = Refs.size(); i != e; ++i) {
+    const ExtDesc &ED = Extenders[Refs[i]];
+    MachineBasicBlock *MBB = ED.UseMI->getParent();
+    RefMIs.insert(ED.UseMI);
+    DomB = MDT->findNearestCommonDominator(DomB, MBB);
+    Blocks.insert(MBB);
+  }
+
+#ifndef NDEBUG
+  // The block DomB should be dominated by the def of each register used
+  // in the initializer.
+  Register Rs = ExtI.second.Rs;  // Only one reg allowed now.
+  const MachineInstr *DefI = Rs.isVReg() ? MRI->getVRegDef(Rs.Reg) : nullptr;
+
+  // This should be guaranteed given that the entire expression is used
+  // at each instruction in Refs. Add an assertion just in case.
+  assert(!DefI || MDT->dominates(DefI->getParent(), DomB));
+#endif
+
+  MachineBasicBlock::iterator It;
+  if (Blocks.count(DomB)) {
+    // Try to find the latest possible location for the def.
+    MachineBasicBlock::iterator End = DomB->end();
+    for (It = DomB->begin(); It != End; ++It)
+      if (RefMIs.count(&*It))
+        break;
+    assert(It != End && "Should have found a ref in DomB");
+  } else {
+    // DomB does not contain any refs.
+    It = DomB->getFirstTerminator();
+  }
+  Loc DefLoc(DomB, It);
+  Defs.emplace(DefLoc, Refs);
+}
+
+HCE::Register HCE::insertInitializer(Loc DefL, const ExtenderInit &ExtI) {
+  unsigned DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
+  MachineBasicBlock &MBB = *DefL.Block;
+  MachineBasicBlock::iterator At = DefL.At;
+  DebugLoc dl = DefL.Block->findDebugLoc(DefL.At);
+  const ExtValue &EV = ExtI.first;
+  MachineOperand ExtOp(EV);
+
+  const ExtExpr &Ex = ExtI.second;
+  const MachineInstr *InitI = nullptr;
+
+  if (Ex.Rs.isSlot()) {
+    assert(Ex.S == 0 && "Cannot have a shift of a stack slot");
+    assert(!Ex.Neg && "Cannot subtract a stack slot");
+    // DefR = PS_fi Rb,##EV
+    InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR)
+              .add(MachineOperand(Ex.Rs))
+              .add(ExtOp);
+  } else {
+    assert((Ex.Rs.Reg == 0 || Ex.Rs.isVReg()) && "Expecting virtual register");
+    if (Ex.trivial()) {
+      // DefR = ##EV
+      InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR)
+                .add(ExtOp);
+    } else if (Ex.S == 0) {
+      if (Ex.Neg) {
+        // DefR = sub(##EV,Rb)
+        InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR)
+                  .add(ExtOp)
+                  .add(MachineOperand(Ex.Rs));
+      } else {
+        // DefR = add(Rb,##EV)
+        InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR)
+                  .add(MachineOperand(Ex.Rs))
+                  .add(ExtOp);
+      }
+    } else {
+      unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri
+                               : Hexagon::S4_addi_asl_ri;
+      // DefR = add(##EV,asl(Rb,S))
+      InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR)
+                .add(ExtOp)
+                .add(MachineOperand(Ex.Rs))
+                .addImm(Ex.S);
+    }
+  }
+
+  assert(InitI);
+  (void)InitI;
+  DEBUG(dbgs() << "Inserted def in bb#" << MBB.getNumber()
+               << " for initializer: " << PrintInit(ExtI, *HRI)
+               << "\n  " << *InitI);
+  return { DefR, 0 };
+}
+
+// Replace the extender at index Idx with the register ExtR.
+bool HCE::replaceInstrExact(const ExtDesc &ED, Register ExtR) {
+  MachineInstr &MI = *ED.UseMI;
+  MachineBasicBlock &MBB = *MI.getParent();
+  MachineBasicBlock::iterator At = MI.getIterator();
+  DebugLoc dl = MI.getDebugLoc();
+  unsigned ExtOpc = MI.getOpcode();
+
+  // With a few exceptions, direct replacement amounts to creating an
+  // instruction with a corresponding register opcode, with all operands
+  // the same, except for the register used in place of the extender.
+  unsigned RegOpc = getDirectRegReplacement(ExtOpc);
+
+  if (RegOpc == TargetOpcode::REG_SEQUENCE) {
+    if (ExtOpc == Hexagon::A4_combineri)
+      BuildMI(MBB, At, dl, HII->get(RegOpc))
+        .add(MI.getOperand(0))
+        .add(MI.getOperand(1))
+        .addImm(Hexagon::isub_hi)
+        .add(MachineOperand(ExtR))
+        .addImm(Hexagon::isub_lo);
+    else if (ExtOpc == Hexagon::A4_combineir)
+      BuildMI(MBB, At, dl, HII->get(RegOpc))
+        .add(MI.getOperand(0))
+        .add(MachineOperand(ExtR))
+        .addImm(Hexagon::isub_hi)
+        .add(MI.getOperand(2))
+        .addImm(Hexagon::isub_lo);
+    else
+      llvm_unreachable("Unexpected opcode became REG_SEQUENCE");
+    MBB.erase(MI);
+    return true;
+  }
+  if (ExtOpc == Hexagon::C2_cmpgei || ExtOpc == Hexagon::C2_cmpgeui) {
+    unsigned NewOpc = ExtOpc == Hexagon::C2_cmpgei ? Hexagon::C2_cmplt
+                                                   : Hexagon::C2_cmpltu;
+    BuildMI(MBB, At, dl, HII->get(NewOpc))
+      .add(MI.getOperand(0))
+      .add(MachineOperand(ExtR))
+      .add(MI.getOperand(1));
+    MBB.erase(MI);
+    return true;
+  }
+
+  if (RegOpc != 0) {
+    MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(RegOpc));
+    unsigned RegN = ED.OpNum;
+    // Copy all operands except the one that has the extender.
+    for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
+      if (i != RegN)
+        MIB.add(MI.getOperand(i));
+      else
+        MIB.add(MachineOperand(ExtR));
+    }
+    MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+    MBB.erase(MI);
+    return true;
+  }
+
+  if ((MI.mayLoad() || MI.mayStore()) && !isStoreImmediate(ExtOpc)) {
+    // For memory instructions, there is an asymmetry in the addressing
+    // modes. Addressing modes allowing extenders can be replaced with
+    // addressing modes that use registers, but the order of operands
+    // (or even their number) may be different.
+    // Replacements:
+    //   BaseImmOffset (io)  -> BaseRegOffset (rr)
+    //   BaseLongOffset (ur) -> BaseRegOffset (rr)
+    unsigned RegOpc, Shift;
+    unsigned AM = HII->getAddrMode(MI);
+    if (AM == HexagonII::BaseImmOffset) {
+      RegOpc = HII->changeAddrMode_io_rr(ExtOpc);
+      Shift = 0;
+    } else if (AM == HexagonII::BaseLongOffset) {
+      // Loads:  Rd = L4_loadri_ur Rs, S, ##
+      // Stores: S4_storeri_ur Rs, S, ##, Rt
+      RegOpc = HII->changeAddrMode_ur_rr(ExtOpc);
+      Shift = MI.getOperand(MI.mayLoad() ? 2 : 1).getImm();
+    } else {
+      llvm_unreachable("Unexpected addressing mode");
+    }
+#ifndef NDEBUG
+    if (RegOpc == -1u) {
+      dbgs() << "\nExtOpc: " << HII->getName(ExtOpc) << " has no rr version\n";
+      llvm_unreachable("No corresponding rr instruction");
+    }
+#endif
+
+    unsigned BaseP, OffP;
+    HII->getBaseAndOffsetPosition(MI, BaseP, OffP);
+
+    // Build an rr instruction: (RegOff + RegBase<<0)
+    MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(RegOpc));
+    // First, add the def for loads.
+    if (MI.mayLoad())
+      MIB.add(getLoadResultOp(MI));
+    // Handle possible predication.
+    if (HII->isPredicated(MI))
+      MIB.add(getPredicateOp(MI));
+    // Build the address.
+    MIB.add(MachineOperand(ExtR));      // RegOff
+    MIB.add(MI.getOperand(BaseP));      // RegBase
+    MIB.addImm(Shift);                  // << Shift
+    // Add the stored value for stores.
+    if (MI.mayStore())
+      MIB.add(getStoredValueOp(MI));
+    MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+    MBB.erase(MI);
+    return true;
+  }
+
+#ifndef NDEBUG
+  dbgs() << '\n' << MI;
+#endif
+  llvm_unreachable("Unhandled exact replacement");
+  return false;
+}
+
+// Replace the extender ED with a form corresponding to the initializer ExtI.
+bool HCE::replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
+      Register ExtR, int32_t &Diff) {
+  MachineInstr &MI = *ED.UseMI;
+  MachineBasicBlock &MBB = *MI.getParent();
+  MachineBasicBlock::iterator At = MI.getIterator();
+  DebugLoc dl = MI.getDebugLoc();
+  unsigned ExtOpc = MI.getOpcode();
+
+  if (ExtOpc == Hexagon::A2_tfrsi) {
+    // A2_tfrsi is a special case: it's replaced with A2_addi, which introduces
+    // another range. One range is the one that's common to all tfrsi's uses,
+    // this one is the range of immediates in A2_addi. When calculating ranges,
+    // the addi's 16-bit argument was included, so now we need to make it such
+    // that the produced value is in the range for the uses alone.
+    // Most of the time, simply adding Diff will make the addi produce exact
+    // result, but if Diff is outside of the 16-bit range, some adjustment
+    // will be needed.
+    unsigned IdxOpc = getRegOffOpcode(ExtOpc);
+    assert(IdxOpc == Hexagon::A2_addi);
+
+    // Clamp Diff to the 16 bit range.
+    int32_t D = isInt<16>(Diff) ? Diff : (Diff > 32767 ? 32767 : -32767);
+    BuildMI(MBB, At, dl, HII->get(IdxOpc))
+      .add(MI.getOperand(0))
+      .add(MachineOperand(ExtR))
+      .addImm(D);
+    Diff -= D;
+#ifndef NDEBUG
+    // Make sure the output is within allowable range for uses.
+    OffsetRange Uses = getOffsetRange(MI.getOperand(0));
+    if (!Uses.contains(Diff))
+      dbgs() << "Diff: " << Diff << " out of range " << Uses
+             << " for " << MI;
+    assert(Uses.contains(Diff));
+#endif
+    MBB.erase(MI);
+    return true;
+  }
+
+  const ExtValue &EV = ExtI.first; (void)EV;
+  const ExtExpr &Ex = ExtI.second; (void)Ex;
+
+  if (ExtOpc == Hexagon::A2_addi || ExtOpc == Hexagon::A2_subri) {
+    // If addi/subri are replaced with the exactly matching initializer,
+    // they amount to COPY.
+    // Check that the initializer is an exact match (for simplicity).
+#ifndef NDEBUG
+    bool IsAddi = ExtOpc == Hexagon::A2_addi;
+    const MachineOperand &RegOp = MI.getOperand(IsAddi ? 1 : 2);
+    const MachineOperand &ImmOp = MI.getOperand(IsAddi ? 2 : 1);
+    assert(Ex.Rs == RegOp && EV == ImmOp && Ex.Neg != IsAddi &&
+           "Initializer mismatch");
+#endif
+    BuildMI(MBB, At, dl, HII->get(TargetOpcode::COPY))
+      .add(MI.getOperand(0))
+      .add(MachineOperand(ExtR));
+    Diff = 0;
+    MBB.erase(MI);
+    return true;
+  }
+  if (ExtOpc == Hexagon::M2_accii || ExtOpc == Hexagon::M2_naccii ||
+      ExtOpc == Hexagon::S4_addaddi || ExtOpc == Hexagon::S4_subaddi) {
+    // M2_accii:    add(Rt,add(Rs,V)) (tied)
+    // M2_naccii:   sub(Rt,add(Rs,V))
+    // S4_addaddi:  add(Rt,add(Rs,V))
+    // S4_subaddi:  add(Rt,sub(V,Rs))
+    // Check that Rs and V match the initializer expression. The Rs+V is the
+    // combination that is considered "subexpression" for V, although Rx+V
+    // would also be valid.
+#ifndef NDEBUG
+    bool IsSub = ExtOpc == Hexagon::S4_subaddi;
+    Register Rs = MI.getOperand(IsSub ? 3 : 2);
+    ExtValue V = MI.getOperand(IsSub ? 2 : 3);
+    assert(EV == V && Rs == Ex.Rs && IsSub == Ex.Neg && "Initializer mismatch");
+#endif
+    unsigned NewOpc = ExtOpc == Hexagon::M2_naccii ? Hexagon::A2_sub
+                                                   : Hexagon::A2_add;
+    BuildMI(MBB, At, dl, HII->get(NewOpc))
+      .add(MI.getOperand(0))
+      .add(MI.getOperand(1))
+      .add(MachineOperand(ExtR));
+    MBB.erase(MI);
+    return true;
+  }
+
+  if (MI.mayLoad() || MI.mayStore()) {
+    unsigned IdxOpc = getRegOffOpcode(ExtOpc);
+    assert(IdxOpc && "Expecting indexed opcode");
+    MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(IdxOpc));
+    // Construct the new indexed instruction.
+    // First, add the def for loads.
+    if (MI.mayLoad())
+      MIB.add(getLoadResultOp(MI));
+    // Handle possible predication.
+    if (HII->isPredicated(MI))
+      MIB.add(getPredicateOp(MI));
+    // Build the address.
+    MIB.add(MachineOperand(ExtR));
+    MIB.addImm(Diff);
+    // Add the stored value for stores.
+    if (MI.mayStore())
+      MIB.add(getStoredValueOp(MI));
+    MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+    MBB.erase(MI);
+    return true;
+  }
+
+#ifndef NDEBUG
+  dbgs() << '\n' << PrintInit(ExtI, *HRI) << "  " << MI;
+#endif
+  llvm_unreachable("Unhandled expr replacement");
+  return false;
+}
+
+bool HCE::replaceInstr(unsigned Idx, Register ExtR, const ExtenderInit &ExtI) {
+  if (ReplaceLimit.getNumOccurrences()) {
+    if (ReplaceLimit <= ReplaceCounter)
+      return false;
+    ++ReplaceCounter;
+  }
+  const ExtDesc &ED = Extenders[Idx];
+  assert((!ED.IsDef || ED.Rd.Reg != 0) && "Missing Rd for def");
+  const ExtValue &DefV = ExtI.first;
+  assert(ExtRoot(ExtValue(ED)) == ExtRoot(DefV) && "Extender root mismatch");
+  const ExtExpr &DefEx = ExtI.second;
+
+  ExtValue EV(ED);
+  int32_t Diff = EV.Offset - DefV.Offset;
+  const MachineInstr &MI = *ED.UseMI;
+  DEBUG(dbgs() << __func__ << " Idx:" << Idx << " ExtR:"
+               << PrintRegister(ExtR, *HRI) << " Diff:" << Diff << '\n');
+
+  // These two addressing modes must be converted into indexed forms
+  // regardless of what the initializer looks like.
+  bool IsAbs = false, IsAbsSet = false;
+  if (MI.mayLoad() || MI.mayStore()) {
+    unsigned AM = HII->getAddrMode(MI);
+    IsAbs = AM == HexagonII::Absolute;
+    IsAbsSet = AM == HexagonII::AbsoluteSet;
+  }
+
+  // If it's a def, remember all operands that need to be updated.
+  // If ED is a def, and Diff is not 0, then all uses of the register Rd
+  // defined by ED must be in the form (Rd, imm), i.e. the immediate offset
+  // must follow the Rd in the operand list.
+  std::vector<std::pair<MachineInstr*,unsigned>> RegOps;
+  if (ED.IsDef && Diff != 0) {
+    for (MachineOperand &Op : MRI->use_operands(ED.Rd.Reg)) {
+      MachineInstr &UI = *Op.getParent();
+      RegOps.push_back({&UI, getOperandIndex(UI, Op)});
+    }
+  }
+
+  // Replace the instruction.
+  bool Replaced = false;
+  if (Diff == 0 && DefEx.trivial() && !IsAbs && !IsAbsSet)
+    Replaced = replaceInstrExact(ED, ExtR);
+  else
+    Replaced = replaceInstrExpr(ED, ExtI, ExtR, Diff);
+
+  if (Diff != 0 && Replaced && ED.IsDef) {
+    // Update offsets of the def's uses.
+    for (std::pair<MachineInstr*,unsigned> P : RegOps) {
+      unsigned J = P.second;
+      assert(P.first->getNumOperands() > J+1 &&
+             P.first->getOperand(J+1).isImm());
+      MachineOperand &ImmOp = P.first->getOperand(J+1);
+      ImmOp.setImm(ImmOp.getImm() + Diff);
+    }
+    // If it was an absolute-set instruction, the "set" part has been removed.
+    // ExtR will now be the register with the extended value, and since all
+    // users of Rd have been updated, all that needs to be done is to replace
+    // Rd with ExtR.
+    if (IsAbsSet) {
+      assert(ED.Rd.Sub == 0 && ExtR.Sub == 0);
+      MRI->replaceRegWith(ED.Rd.Reg, ExtR.Reg);
+    }
+  }
+
+  return Replaced;
+}
+
+bool HCE::replaceExtenders(const AssignmentMap &IMap) {
+  LocDefMap Defs;
+  bool Changed = false;
+
+  for (const std::pair<ExtenderInit,IndexList> &P : IMap) {
+    const IndexList &Idxs = P.second;
+    if (Idxs.size() < CountThreshold)
+      continue;
+
+    Defs.clear();
+    calculatePlacement(P.first, Idxs, Defs);
+    for (const std::pair<Loc,IndexList> &Q : Defs) {
+      Register DefR = insertInitializer(Q.first, P.first);
+      NewRegs.push_back(DefR.Reg);
+      for (unsigned I : Q.second)
+        Changed |= replaceInstr(I, DefR, P.first);
+    }
+  }
+  return Changed;
+}
+
+unsigned HCE::getOperandIndex(const MachineInstr &MI,
+      const MachineOperand &Op) const {
+  for (unsigned i = 0, n = MI.getNumOperands(); i != n; ++i)
+    if (&MI.getOperand(i) == &Op)
+      return i;
+  llvm_unreachable("Not an operand of MI");
+}
+
+const MachineOperand &HCE::getPredicateOp(const MachineInstr &MI) const {
+  assert(HII->isPredicated(MI));
+  for (const MachineOperand &Op : MI.operands()) {
+    if (!Op.isReg() || !Op.isUse() ||
+        MRI->getRegClass(Op.getReg()) != &Hexagon::PredRegsRegClass)
+      continue;
+    assert(Op.getSubReg() == 0 && "Predicate register with a subregister");
+    return Op;
+  }
+  llvm_unreachable("Predicate operand not found");
+}
+
+const MachineOperand &HCE::getLoadResultOp(const MachineInstr &MI) const {
+  assert(MI.mayLoad());
+  return MI.getOperand(0);
+}
+
+const MachineOperand &HCE::getStoredValueOp(const MachineInstr &MI) const {
+  assert(MI.mayStore());
+  return MI.getOperand(MI.getNumExplicitOperands()-1);
+}
+
+bool HCE::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(MF.getFunction()))
+    return false;
+  DEBUG(MF.print(dbgs() << "Before " << getPassName() << '\n', nullptr));
+
+  HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
+  HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
+  MDT = &getAnalysis<MachineDominatorTree>();
+  MRI = &MF.getRegInfo();
+  AssignmentMap IMap;
+
+  collect(MF);
+  std::sort(Extenders.begin(), Extenders.end(),
+    [](const ExtDesc &A, const ExtDesc &B) {
+      return ExtValue(A) < ExtValue(B);
+    });
+
+  bool Changed = false;
+  DEBUG(dbgs() << "Collected " << Extenders.size() << " extenders\n");
+  for (unsigned I = 0, E = Extenders.size(); I != E; ) {
+    unsigned B = I;
+    const ExtRoot &T = Extenders[B].getOp();
+    while (I != E && ExtRoot(Extenders[I].getOp()) == T)
+      ++I;
+
+    IMap.clear();
+    assignInits(T, B, I, IMap);
+    Changed |= replaceExtenders(IMap);
+  }
+
+  DEBUG({
+    if (Changed)
+      MF.print(dbgs() << "After " << getPassName() << '\n', nullptr);
+    else
+      dbgs() << "No changes\n";
+  });
+  return Changed;
+}
+
+FunctionPass *llvm::createHexagonConstExtenders() {
+  return new HexagonConstExtenders();
+}
diff --git a/lib/Target/Hexagon/HexagonConstPropagation.cpp b/lib/Target/Hexagon/HexagonConstPropagation.cpp
index 49ddd6961f8a..8ac96f3a4bfa 100644
--- a/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonConstPropagation.cpp --------------------------------------===//
+//===- HexagonConstPropagation.cpp ----------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -25,14 +25,17 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/Constants.h"
+#include "llvm/IR/Type.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/Casting.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <cassert>
 #include <cstdint>
 #include <cstring>
@@ -85,7 +88,7 @@ namespace {
       : Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
 
     void print(const TargetRegisterInfo *TRI = nullptr) const {
-      dbgs() << PrintReg(Reg, TRI, SubReg);
+      dbgs() << printReg(Reg, TRI, SubReg);
     }
 
     bool operator== (const Register &R) const {
@@ -167,10 +170,12 @@ namespace {
     bool convertToProperty();
   };
 
+#ifndef NDEBUG
   raw_ostream &operator<< (raw_ostream &os, const LatticeCell &L) {
     L.print(os);
     return os;
   }
+#endif
 
   class MachineConstEvaluator;
 
@@ -182,7 +187,7 @@ namespace {
 
     // Mapping: vreg -> cell
     // The keys are registers _without_ subregisters. This won't allow
-    // definitions in the form of "vreg:subreg<def> = ...". Such definitions
+    // definitions in the form of "vreg:subreg = ...". Such definitions
     // would be questionable from the point of view of SSA, since the "vreg"
     // could not be initialized in its entirety (specifically, an instruction
     // defining the "other part" of "vreg" would also count as a definition
@@ -224,7 +229,8 @@ namespace {
       void print(raw_ostream &os, const TargetRegisterInfo &TRI) const;
 
     private:
-      typedef std::map<unsigned,LatticeCell> MapType;
+      using MapType = std::map<unsigned, LatticeCell>;
+
       MapType Map;
       // To avoid creating "top" entries, return a const reference to
       // this cell in "get". Also, have a "Bottom" cell to return from
@@ -232,7 +238,8 @@ namespace {
       LatticeCell Top, Bottom;
 
     public:
-      typedef MapType::const_iterator const_iterator;
+      using const_iterator = MapType::const_iterator;
+
       const_iterator begin() const { return Map.begin(); }
       const_iterator end() const { return Map.end(); }
     };
@@ -254,10 +261,10 @@ namespace {
     MachineRegisterInfo      *MRI;
     MachineConstEvaluator    &MCE;
 
-    typedef std::pair<unsigned,unsigned> CFGEdge;
-    typedef std::set<CFGEdge> SetOfCFGEdge;
-    typedef std::set<const MachineInstr*> SetOfInstr;
-    typedef std::queue<CFGEdge> QueueOfCFGEdge;
+    using CFGEdge = std::pair<unsigned, unsigned>;
+    using SetOfCFGEdge = std::set<CFGEdge>;
+    using SetOfInstr = std::set<const MachineInstr *>;
+    using QueueOfCFGEdge = std::queue<CFGEdge>;
 
     LatticeCell     Bottom;
     CellMap         Cells;
@@ -273,7 +280,7 @@ namespace {
   public:
     MachineConstEvaluator(MachineFunction &Fn)
       : TRI(*Fn.getSubtarget().getRegisterInfo()),
-        MF(Fn), CX(Fn.getFunction()->getContext()) {}
+        MF(Fn), CX(Fn.getFunction().getContext()) {}
     virtual ~MachineConstEvaluator() = default;
 
     // The required interface:
@@ -291,7 +298,7 @@ namespace {
     // - A function "rewrite", that given the cell map after propagation,
     //   could rewrite instruction MI in a more beneficial form. Return
     //   "true" if a change has been made, "false" otherwise.
-    typedef MachineConstPropagator::CellMap CellMap;
+    using CellMap = MachineConstPropagator::CellMap;
     virtual bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
                           CellMap &Outputs) = 0;
     virtual bool evaluate(const Register &R, const LatticeCell &SrcC,
@@ -458,6 +465,7 @@ bool LatticeCell::convertToProperty() {
   return true;
 }
 
+#ifndef NDEBUG
 void LatticeCell::print(raw_ostream &os) const {
   if (isProperty()) {
     os << "{ ";
@@ -495,6 +503,7 @@ void LatticeCell::print(raw_ostream &os) const {
   }
   os << " }";
 }
+#endif
 
 // "Meet" operation on two cells. This is the key of the propagation
 // algorithm.
@@ -597,16 +606,18 @@ uint32_t LatticeCell::properties() const {
   return Ps;
 }
 
+#ifndef NDEBUG
 void MachineConstPropagator::CellMap::print(raw_ostream &os,
       const TargetRegisterInfo &TRI) const {
   for (auto &I : Map)
-    dbgs() << "  " << PrintReg(I.first, &TRI) << " -> " << I.second << '\n';
+    dbgs() << "  " << printReg(I.first, &TRI) << " -> " << I.second << '\n';
 }
+#endif
 
 void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
   const MachineBasicBlock *MB = PN.getParent();
   unsigned MBN = MB->getNumber();
-  DEBUG(dbgs() << "Visiting FI(BB#" << MBN << "): " << PN);
+  DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN);
 
   const MachineOperand &MD = PN.getOperand(0);
   Register DefR(MD);
@@ -631,8 +642,8 @@ Bottomize:
     const MachineBasicBlock *PB = PN.getOperand(i+1).getMBB();
     unsigned PBN = PB->getNumber();
     if (!EdgeExec.count(CFGEdge(PBN, MBN))) {
-      DEBUG(dbgs() << "  edge BB#" << PBN << "->BB#" << MBN
-                   << " not executable\n");
+      DEBUG(dbgs() << "  edge " << printMBBReference(*PB) << "->"
+                   << printMBBReference(*MB) << " not executable\n");
       continue;
     }
     const MachineOperand &SO = PN.getOperand(i);
@@ -647,9 +658,8 @@ Bottomize:
 
     LatticeCell SrcC;
     bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC);
-    DEBUG(dbgs() << "  edge from BB#" << PBN << ": "
-                 << PrintReg(UseR.Reg, &MCE.TRI, UseR.SubReg)
-                 << SrcC << '\n');
+    DEBUG(dbgs() << "  edge from " << printMBBReference(*PB) << ": "
+                 << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC << '\n');
     Changed |= Eval ? DefC.meet(SrcC)
                     : DefC.setBottom();
     Cells.update(DefR.Reg, DefC);
@@ -661,7 +671,7 @@ Bottomize:
 }
 
 void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) {
-  DEBUG(dbgs() << "Visiting MI(BB#" << MI.getParent()->getNumber()
+  DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent())
                << "): " << MI);
   CellMap Outputs;
   bool Eval = MCE.evaluate(MI, Cells, Outputs);
@@ -718,8 +728,8 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) {
   while (It != End) {
     const MachineInstr &MI = *It;
     InstrExec.insert(&MI);
-    DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "(BB#"
-                 << MBN << "): " << MI);
+    DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "("
+                 << printMBBReference(B) << "): " << MI);
     // Do not evaluate subsequent branches if the evaluation of any of the
     // previous branches failed. Keep iterating over the branches only
     // to mark them as executable.
@@ -761,13 +771,14 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) {
 
   for (const MachineBasicBlock *TB : Targets) {
     unsigned TBN = TB->getNumber();
-    DEBUG(dbgs() << "  pushing edge BB#" << MBN << " -> BB#" << TBN << "\n");
+    DEBUG(dbgs() << "  pushing edge " << printMBBReference(B) << " -> "
+                 << printMBBReference(*TB) << "\n");
     FlowQ.push(CFGEdge(MBN, TBN));
   }
 }
 
 void MachineConstPropagator::visitUsesOf(unsigned Reg) {
-  DEBUG(dbgs() << "Visiting uses of " << PrintReg(Reg, &MCE.TRI)
+  DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI)
                << Cells.get(Reg) << '\n');
   for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
     // Do not process non-executable instructions. They can become exceutable
@@ -859,8 +870,10 @@ void MachineConstPropagator::propagate(MachineFunction &MF) {
     CFGEdge Edge = FlowQ.front();
     FlowQ.pop();
 
-    DEBUG(dbgs() << "Picked edge BB#" << Edge.first << "->BB#"
-                 << Edge.second << '\n');
+    DEBUG(dbgs() << "Picked edge "
+                 << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->"
+                 << printMBBReference(*MF.getBlockNumbered(Edge.second))
+                 << '\n');
     if (Edge.first != EntryNum)
       if (EdgeExec.count(Edge))
         continue;
@@ -923,7 +936,8 @@ void MachineConstPropagator::propagate(MachineFunction &MF) {
       for (const MachineBasicBlock *SB : B.successors()) {
         unsigned SN = SB->getNumber();
         if (!EdgeExec.count(CFGEdge(BN, SN)))
-          dbgs() << "  BB#" << BN << " -> BB#" << SN << '\n';
+          dbgs() << "  " << printMBBReference(B) << " -> "
+                 << printMBBReference(*SB) << '\n';
       }
     }
   });
@@ -1028,7 +1042,7 @@ bool MachineConstPropagator::rewrite(MachineFunction &MF) {
 // This is the constant propagation algorithm as described by Wegman-Zadeck.
 // Most of the terminology comes from there.
 bool MachineConstPropagator::run(MachineFunction &MF) {
-  DEBUG(MF.print(dbgs() << "Starting MachineConstPropagator\n", 0));
+  DEBUG(MF.print(dbgs() << "Starting MachineConstPropagator\n", nullptr));
 
   MRI = &MF.getRegInfo();
 
@@ -1043,7 +1057,7 @@ bool MachineConstPropagator::run(MachineFunction &MF) {
   DEBUG({
     dbgs() << "End of MachineConstPropagator (Changed=" << Changed << ")\n";
     if (Changed)
-      MF.print(dbgs(), 0);
+      MF.print(dbgs(), nullptr);
   });
   return Changed;
 }
@@ -1278,7 +1292,8 @@ bool MachineConstEvaluator::evaluateCMPpi(uint32_t Cmp, uint32_t Props,
 
 bool MachineConstEvaluator::evaluateCMPpp(uint32_t Cmp, uint32_t Props1,
       uint32_t Props2, bool &Result) {
-  typedef ConstantProperties P;
+  using P = ConstantProperties;
+
   if ((Props1 & P::NaN) && (Props2 & P::NaN))
     return false;
   if (!(Props1 & P::Finite) || !(Props2 & P::Finite))
@@ -1875,10 +1890,8 @@ namespace {
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override {
-      const Function *F = MF.getFunction();
-      if (!F)
-        return false;
-      if (skipFunction(*F))
+      const Function &F = MF.getFunction();
+      if (skipFunction(F))
         return false;
 
       HexagonConstEvaluator HCE(MF);
@@ -1886,10 +1899,10 @@ namespace {
     }
   };
 
-  char HexagonConstPropagation::ID = 0;
-
 } // end anonymous namespace
 
+char HexagonConstPropagation::ID = 0;
+
 INITIALIZE_PASS(HexagonConstPropagation, "hcp", "Hexagon Constant Propagation",
                 false, false)
 
@@ -1928,7 +1941,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
   if (MI.isRegSequence()) {
     unsigned Sub1 = MI.getOperand(2).getImm();
     unsigned Sub2 = MI.getOperand(4).getImm();
-    const TargetRegisterClass *DefRC = MRI->getRegClass(DefR.Reg);
+    const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg);
     unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo);
     unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi);
     if (Sub1 != SubLo && Sub1 != SubHi)
@@ -1962,7 +1975,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
     {
       const MachineOperand &VO = MI.getOperand(1);
       // The operand of CONST32 can be a blockaddress, e.g.
-      //   %vreg0<def> = CONST32 <blockaddress(@eat, %L)>
+      //   %0 = CONST32 <blockaddress(@eat, %l)>
       // Do this check for all instructions for safety.
       if (!VO.isImm())
         return false;
@@ -2192,7 +2205,8 @@ bool HexagonConstEvaluator::evaluate(const Register &R,
   if (Input.isBottom())
     return false;
 
-  typedef ConstantProperties P;
+  using P = ConstantProperties;
+
   if (Input.isProperty()) {
     uint32_t Ps = Input.properties();
     if (Ps & (P::Zero|P::NaN)) {
@@ -2775,7 +2789,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
       HasUse = true;
       // PHIs can legitimately have "top" cells after propagation.
       if (!MI.isPHI() && !Inputs.has(R.Reg)) {
-        dbgs() << "Top " << PrintReg(R.Reg, &HRI, R.SubReg)
+        dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg)
                << " in MI: " << MI;
         continue;
       }
@@ -2791,7 +2805,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
           if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
             continue;
           unsigned R = MO.getReg();
-          dbgs() << PrintReg(R, &TRI) << ": " << Inputs.get(R) << "\n";
+          dbgs() << printReg(R, &TRI) << ": " << Inputs.get(R) << "\n";
         }
       }
     }
@@ -2837,7 +2851,8 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
     if (!L.isSingle()) {
       // If this a zero/non-zero cell, we can fold a definition
       // of a predicate register.
-      typedef ConstantProperties P;
+      using P = ConstantProperties;
+
       uint64_t Ps = L.properties();
       if (!(Ps & (P::Zero|P::NonZero)))
         continue;
@@ -2908,7 +2923,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
   DEBUG({
     if (!NewInstrs.empty()) {
       MachineFunction &MF = *MI.getParent()->getParent();
-      dbgs() << "In function: " << MF.getFunction()->getName() << "\n";
+      dbgs() << "In function: " << MF.getName() << "\n";
       dbgs() << "Rewrite: for " << MI << "  created " << *NewInstrs[0];
       for (unsigned i = 1; i < NewInstrs.size(); ++i)
         dbgs() << "          " << *NewInstrs[i];
@@ -3039,7 +3054,9 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
       assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
       LatticeCell LS1, LS2;
       unsigned CopyOf = 0;
-      typedef ConstantProperties P;
+
+      using P = ConstantProperties;
+
       if (getCell(R1, Inputs, LS1) && (LS1.properties() & P::Zero))
         CopyOf = 2;
       else if (getCell(R2, Inputs, LS2) && (LS2.properties() & P::Zero))
@@ -3110,7 +3127,7 @@ bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI,
   if (BrI.getOpcode() == Hexagon::J2_jump)
     return false;
 
-  DEBUG(dbgs() << "Rewrite(BB#" << B.getNumber() << "):" << BrI);
+  DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI);
   bool Rewritten = false;
   if (NumTargets > 0) {
     assert(!FallsThru && "This should have been checked before");
@@ -3128,7 +3145,7 @@ bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI,
       BrI.setDesc(JD);
       while (BrI.getNumOperands() > 0)
         BrI.RemoveOperand(0);
-      // This ensures that all implicit operands (e.g. %R31<imp-def>, etc)
+      // This ensures that all implicit operands (e.g. implicit-def %r31, etc)
       // are present in the rewritten branch.
       for (auto &Op : NI->operands())
         BrI.addOperand(Op);
diff --git a/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 6b4f53428256..087a77203fcb 100644
--- a/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -21,12 +21,12 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/PassSupport.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 
 using namespace llvm;
 
@@ -161,7 +161,6 @@ static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII,
   }
 
   case Hexagon::V6_vassign:
-  case Hexagon::V6_vassign_128B:
     return true;
 
   default:
@@ -231,8 +230,7 @@ static bool isEvenReg(unsigned Reg) {
   assert(TargetRegisterInfo::isPhysicalRegister(Reg));
   if (Hexagon::IntRegsRegClass.contains(Reg))
     return (Reg - Hexagon::R0) % 2 == 0;
-  if (Hexagon::VectorRegsRegClass.contains(Reg) ||
-      Hexagon::VectorRegs128BRegClass.contains(Reg))
+  if (Hexagon::HvxVRRegClass.contains(Reg))
     return (Reg - Hexagon::V0) % 2 == 0;
   llvm_unreachable("Invalid register");
 }
@@ -253,7 +251,8 @@ static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg,
                                  const TargetRegisterInfo *TRI) {
   return (UseReg && (MI.modifiesRegister(UseReg, TRI))) ||
          MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) ||
-         MI.hasUnmodeledSideEffects() || MI.isInlineAsm() || MI.isDebugValue();
+         MI.hasUnmodeledSideEffects() || MI.isInlineAsm() ||
+         MI.isMetaInstruction();
 }
 
 static unsigned UseReg(const MachineOperand& MO) {
@@ -352,11 +351,11 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1,
       //   kill flag for a register (a removeRegisterKilled() analogous to
       //   addRegisterKilled) that handles aliased register correctly.
       //   * or has a killed aliased register use of I1's use reg
-      //           %D4<def> = A2_tfrpi 16
-      //           %R6<def> = A2_tfr %R9
-      //           %R8<def> = KILL %R8, %D4<imp-use,kill>
+      //           %d4 = A2_tfrpi 16
+      //           %r6 = A2_tfr %r9
+      //           %r8 = KILL %r8, implicit killed %d4
       //      If we want to move R6 = across the KILL instruction we would have
-      //      to remove the %D4<imp-use,kill> operand. For now, we are
+      //      to remove the implicit killed %d4 operand. For now, we are
       //      conservative and disallow the move.
       // we can't move I1 across it.
       if (MI.isDebugValue()) {
@@ -460,7 +459,7 @@ HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
 }
 
 bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   if (IsCombinesDisabled) return false;
@@ -472,8 +471,8 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
   TRI = ST->getRegisterInfo();
   TII = ST->getInstrInfo();
 
-  const Function *F = MF.getFunction();
-  bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
+  const Function &F = MF.getFunction();
+  bool OptForSize = F.hasFnAttribute(Attribute::OptimizeForSize);
 
   // Combine aggressively (for code size)
   ShouldCombineAggressively =
@@ -592,12 +591,9 @@ void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2,
   if (Hexagon::IntRegsRegClass.contains(LoRegDef)) {
     SuperRC = &Hexagon::DoubleRegsRegClass;
     SubLo = Hexagon::isub_lo;
-  } else if (Hexagon::VectorRegsRegClass.contains(LoRegDef)) {
+  } else if (Hexagon::HvxVRRegClass.contains(LoRegDef)) {
     assert(ST->useHVXOps());
-    if (ST->useHVXSglOps())
-      SuperRC = &Hexagon::VecDblRegsRegClass;
-    else
-      SuperRC = &Hexagon::VecDblRegs128BRegClass;
+    SuperRC = &Hexagon::HvxWRRegClass;
     SubLo = Hexagon::vsub_lo;
   } else
     llvm_unreachable("Unexpected register class");
@@ -874,12 +870,9 @@ void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
   unsigned NewOpc;
   if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) {
     NewOpc = Hexagon::A2_combinew;
-  } else if (Hexagon::VecDblRegsRegClass.contains(DoubleDestReg)) {
+  } else if (Hexagon::HvxWRRegClass.contains(DoubleDestReg)) {
     assert(ST->useHVXOps());
-    if (ST->useHVXSglOps())
-      NewOpc = Hexagon::V6_vcombine;
-    else
-      NewOpc = Hexagon::V6_vcombine_128B;
+    NewOpc = Hexagon::V6_vcombine;
   } else
     llvm_unreachable("Unexpected register");
 
diff --git a/lib/Target/Hexagon/HexagonDepArch.h b/lib/Target/Hexagon/HexagonDepArch.h
index 1009aa39cefb..dc75f8f63400 100644
--- a/lib/Target/Hexagon/HexagonDepArch.h
+++ b/lib/Target/Hexagon/HexagonDepArch.h
@@ -1,4 +1,4 @@
-//===--- HexagonDepArch.h -------------------------------------------------===//
+//===- HexagonDepArch.h ---------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,5 +6,16 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
+
 
-enum HexagonArchEnum { V4,V5,V55,V60,V62 };
+#ifndef HEXAGON_DEP_ARCH_H
+#define HEXAGON_DEP_ARCH_H
+namespace llvm {
+namespace Hexagon {
+enum class ArchEnum { V4,V5,V55,V60,V62,V65 };
+} // namespace Hexagon
+} // namespace llvm;
+#endif // HEXAGON_DEP_ARCH_H
diff --git a/lib/Target/Hexagon/HexagonDepArch.td b/lib/Target/Hexagon/HexagonDepArch.td
index 5b1d02c136f0..87dcd966f2ed 100644
--- a/lib/Target/Hexagon/HexagonDepArch.td
+++ b/lib/Target/Hexagon/HexagonDepArch.td
@@ -1,4 +1,4 @@
-//===--- HexagonDepArch.td ------------------------------------------------===//
+//===- HexagonDepArch.td --------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,14 +6,19 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
 
-def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "V62", "Enable Hexagon V62 architecture">;
+def ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architecture">;
+def HasV65T : Predicate<"HST->hasV65TOps()">, AssemblerPredicate<"ArchV65">;
+def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architecture">;
 def HasV62T : Predicate<"HST->hasV62TOps()">, AssemblerPredicate<"ArchV62">;
-def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Enable Hexagon V60 architecture">;
+def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architecture">;
 def HasV60T : Predicate<"HST->hasV60TOps()">, AssemblerPredicate<"ArchV60">;
-def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Enable Hexagon V55 architecture">;
+def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V55 architecture">;
 def HasV55T : Predicate<"HST->hasV55TOps()">, AssemblerPredicate<"ArchV55">;
-def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Enable Hexagon V4 architecture">;
+def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "Hexagon::ArchEnum::V4", "Enable Hexagon V4 architecture">;
 def HasV4T : Predicate<"HST->hasV4TOps()">, AssemblerPredicate<"ArchV4">;
-def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Enable Hexagon V5 architecture">;
+def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "Hexagon::ArchEnum::V5", "Enable Hexagon V5 architecture">;
 def HasV5T : Predicate<"HST->hasV5TOps()">, AssemblerPredicate<"ArchV5">;
diff --git a/lib/Target/Hexagon/HexagonDepDecoders.h b/lib/Target/Hexagon/HexagonDepDecoders.h
index aa9787ecf0c8..020362a95909 100644
--- a/lib/Target/Hexagon/HexagonDepDecoders.h
+++ b/lib/Target/Hexagon/HexagonDepDecoders.h
@@ -1,4 +1,4 @@
-//===--- HexagonDepDecoders.h ---------------------------------------------===//
+//===- HexagonDepDecoders.h -----------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,59 +6,8 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
+
 
-static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<4>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
-static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<14>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
-static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<8>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
-static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<7>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
-static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<12>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
-static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<3>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
-static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<13>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
-static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<6>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
-static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<9>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
-static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<5>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
-static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
-  signedDecoder<6>(MI, tmp, Decoder);
-  return MCDisassembler::Success;
-}
diff --git a/lib/Target/Hexagon/HexagonDepIICHVX.td b/lib/Target/Hexagon/HexagonDepIICHVX.td
index 1c1788264c66..b27cdae81a28 100644
--- a/lib/Target/Hexagon/HexagonDepIICHVX.td
+++ b/lib/Target/Hexagon/HexagonDepIICHVX.td
@@ -1,4 +1,4 @@
-//===--- HexagonDepIICHVX.td ----------------------------------------------===//
+//===- HexagonDepIICHVX.td ------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,11 +6,15 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
 
 def tc_0317c6ca : InstrItinClass;
 def tc_1b93bdc6 : InstrItinClass;
 def tc_2171ebae : InstrItinClass;
 def tc_28978789 : InstrItinClass;
+def tc_29841470 : InstrItinClass;
 def tc_316c637c : InstrItinClass;
 def tc_354299ad : InstrItinClass;
 def tc_35e92f8e : InstrItinClass;
@@ -20,39 +24,49 @@ def tc_41f4b64e : InstrItinClass;
 def tc_41f99e1c : InstrItinClass;
 def tc_45453b98 : InstrItinClass;
 def tc_4e2a5159 : InstrItinClass;
+def tc_4f190ba3 : InstrItinClass;
 def tc_4fd8566e : InstrItinClass;
 def tc_51cd3aab : InstrItinClass;
 def tc_5a9fc4ec : InstrItinClass;
+def tc_5c03dc63 : InstrItinClass;
 def tc_5c120602 : InstrItinClass;
 def tc_5cbf490b : InstrItinClass;
+def tc_63e3d94c : InstrItinClass;
 def tc_644584f8 : InstrItinClass;
+def tc_66bb62ea : InstrItinClass;
 def tc_69b6dd20 : InstrItinClass;
 def tc_6b78cf13 : InstrItinClass;
 def tc_6fd9ad30 : InstrItinClass;
 def tc_71337255 : InstrItinClass;
 def tc_72ad7b54 : InstrItinClass;
+def tc_7474003e : InstrItinClass;
 def tc_77a4c701 : InstrItinClass;
 def tc_7c3f55c4 : InstrItinClass;
 def tc_7e9f581b : InstrItinClass;
 def tc_7fa82b08 : InstrItinClass;
 def tc_7fa8b40f : InstrItinClass;
 def tc_85d237e3 : InstrItinClass;
+def tc_8a6eb39a : InstrItinClass;
 def tc_8b6a873f : InstrItinClass;
 def tc_908a4c8c : InstrItinClass;
 def tc_9311da3f : InstrItinClass;
+def tc_94f43c04 : InstrItinClass;
 def tc_9777e6bf : InstrItinClass;
 def tc_97c165b9 : InstrItinClass;
+def tc_98733e9d : InstrItinClass;
 def tc_99093773 : InstrItinClass;
 def tc_9b9642a1 : InstrItinClass;
 def tc_9c267309 : InstrItinClass;
 def tc_a3127e12 : InstrItinClass;
 def tc_a4c9df3b : InstrItinClass;
+def tc_a807365d : InstrItinClass;
 def tc_aedb9f9e : InstrItinClass;
 def tc_b06ab583 : InstrItinClass;
 def tc_b712833a : InstrItinClass;
 def tc_b77635b4 : InstrItinClass;
 def tc_bbaf280e : InstrItinClass;
 def tc_bf142ae2 : InstrItinClass;
+def tc_bfe309d5 : InstrItinClass;
 def tc_c00bf9c9 : InstrItinClass;
 def tc_c4b515c5 : InstrItinClass;
 def tc_cbf6d1dc : InstrItinClass;
@@ -65,14 +79,18 @@ def tc_d7bea0ec : InstrItinClass;
 def tc_d98f4d63 : InstrItinClass;
 def tc_da979fb3 : InstrItinClass;
 def tc_db5b9e2f : InstrItinClass;
+def tc_df54ad52 : InstrItinClass;
 def tc_e172d86a : InstrItinClass;
 def tc_e231aa4f : InstrItinClass;
 def tc_e3748cdf : InstrItinClass;
 def tc_e5053c8f : InstrItinClass;
 def tc_e6299d16 : InstrItinClass;
 def tc_eb669007 : InstrItinClass;
+def tc_ec58f88a : InstrItinClass;
 def tc_eda67dcd : InstrItinClass;
+def tc_ee927c0e : InstrItinClass;
 def tc_f3fc3f83 : InstrItinClass;
+def tc_fa99dc24 : InstrItinClass;
 
 class DepHVXItinV55 {
   list<InstrItinData> DepHVXItinV55_list = [
@@ -97,6 +115,11 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_ALL]>], [3, 2],
       [HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_29841470, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
@@ -146,6 +169,12 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
       [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [SLOT1], 0>,
@@ -163,6 +192,11 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
       [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
@@ -174,11 +208,23 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
       [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
       [HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_69b6dd20, /*SLOT23,VX*/
       [InstrStage<1, [SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
@@ -206,6 +252,11 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
       [HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
     InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/
       [InstrStage<1, [SLOT0, SLOT1], 0>,
        InstrStage<1, [CVI_LD]>], [9, 1, 2],
@@ -239,6 +290,11 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
       [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
+      [HVX_FWD]>,
+
     InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
@@ -254,6 +310,12 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
       [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_9777e6bf, /*SLOT0,VA*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
@@ -264,6 +326,12 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
       [HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_ST], 0>,
@@ -291,6 +359,12 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
       [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+       InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
     InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_ST], 0>,
@@ -323,6 +397,12 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
       [HVX_FWD, HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
@@ -386,6 +466,12 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
       [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/
       [InstrStage<1, [SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
@@ -418,15 +504,32 @@ class DepHVXItinV55 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
       [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/
       [InstrStage<1, [SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
       [HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+       InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
     InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
-      [HVX_FWD, HVX_FWD, HVX_FWD]>
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>
   ];
 }
 
@@ -453,6 +556,11 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_ALL]>], [3, 2],
       [HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_29841470, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
@@ -502,6 +610,12 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
       [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [SLOT1], 0>,
@@ -519,6 +633,11 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
       [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
@@ -530,11 +649,23 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
       [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
       [HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_69b6dd20, /*SLOT23,VX*/
       [InstrStage<1, [SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
@@ -562,6 +693,11 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
       [HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
     InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/
       [InstrStage<1, [SLOT0, SLOT1], 0>,
        InstrStage<1, [CVI_LD]>], [9, 1, 2],
@@ -595,6 +731,11 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
       [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
+      [HVX_FWD]>,
+
     InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
@@ -610,6 +751,12 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
       [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_9777e6bf, /*SLOT0,VA*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
@@ -620,6 +767,12 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
       [HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_ST], 0>,
@@ -647,6 +800,12 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
       [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+       InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
     InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_ST], 0>,
@@ -679,6 +838,12 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
       [HVX_FWD, HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
@@ -742,6 +907,12 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
       [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/
       [InstrStage<1, [SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
@@ -774,15 +945,32 @@ class DepHVXItinV60 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
       [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/
       [InstrStage<1, [SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
       [HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+       InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
     InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
-      [HVX_FWD, HVX_FWD, HVX_FWD]>
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>
   ];
 }
 
@@ -809,6 +997,11 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_ALL]>], [3, 2],
       [HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_29841470, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
@@ -858,6 +1051,12 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
       [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [SLOT1], 0>,
@@ -875,6 +1074,11 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
       [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
@@ -886,11 +1090,23 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
       [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
       [HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_69b6dd20, /*SLOT23,VX*/
       [InstrStage<1, [SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
@@ -918,6 +1134,11 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
       [HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
     InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/
       [InstrStage<1, [SLOT0, SLOT1], 0>,
        InstrStage<1, [CVI_LD]>], [9, 1, 2],
@@ -951,6 +1172,11 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
       [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
+      [HVX_FWD]>,
+
     InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
@@ -966,6 +1192,12 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
       [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_9777e6bf, /*SLOT0,VA*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
@@ -976,6 +1208,12 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
       [HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_ST], 0>,
@@ -1003,6 +1241,12 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
       [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+       InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
     InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/
       [InstrStage<1, [SLOT0], 0>,
        InstrStage<1, [CVI_ST], 0>,
@@ -1035,6 +1279,12 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
       [HVX_FWD, HVX_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
     InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
@@ -1098,6 +1348,12 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
       [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/
       [InstrStage<1, [SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
@@ -1130,14 +1386,472 @@ class DepHVXItinV62 {
        InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
       [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
     InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/
       [InstrStage<1, [SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
       [HVX_FWD, HVX_FWD, HVX_FWD]>,
 
+    InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+       InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
     InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
-      [HVX_FWD, HVX_FWD, HVX_FWD]>
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>
+  ];
+}
+
+class DepHVXItinV65 {
+  list<InstrItinData> DepHVXItinV65_list = [
+    InstrItinData <tc_0317c6ca, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 2, 1, 2, 7],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_1b93bdc6, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [1, 2, 5],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_2171ebae, /*SLOT0123,VA_DV*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 2, 7, 7],
+      [HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_28978789, /*SLOT0123,4SLOT*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ALL]>], [3, 2],
+      [HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_29841470, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
+      [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_354299ad, /*SLOT0,NOSLOT1,STORE,VP*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_XLANE]>], [1, 2, 5],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_35e92f8e, /*SLOT0,NOSLOT1,LOAD,VP*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_XLANE]>], [9, 1, 2],
+      [HVX_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_38208312, /*SLOT01,LOAD*/
+      [InstrStage<1, [SLOT0, SLOT1], 0>,
+       InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2],
+      [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_4105d6b5, /*SLOT0123,VP*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_XLANE]>], [9, 2],
+      [HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_41f4b64e, /*SLOT0123,VS*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_SHIFT]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_41f99e1c, /*SLOT23,VX_DV*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_45453b98, /*SLOT0123,VS*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_SHIFT]>], [9, 5, 5],
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_4e2a5159, /*SLOT0123,VP_VS*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_XLANE]>], [9, 3, 1, 2],
+      [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_51cd3aab, /*SLOT01,LOAD*/
+      [InstrStage<1, [SLOT0, SLOT1], 0>,
+       InstrStage<1, [CVI_LD]>], [9, 2, 1, 2],
+      [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5a9fc4ec, /*SLOT0123,VA*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
+      [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5cbf490b, /*SLOT01,LOAD,VA*/
+      [InstrStage<1, [SLOT0, SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
+      [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
+      [HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_69b6dd20, /*SLOT23,VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_6b78cf13, /*SLOT23,VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 2],
+      [HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_6fd9ad30, /*SLOT0,NOSLOT1,STORE,VP*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_XLANE]>], [3, 2, 1, 2, 5],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_71337255, /*SLOT0123,VA*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7],
+      [HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_72ad7b54, /*SLOT0123,VP_VS*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/
+      [InstrStage<1, [SLOT0, SLOT1], 0>,
+       InstrStage<1, [CVI_LD]>], [9, 1, 2],
+      [HVX_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_7c3f55c4, /*SLOT23,VX_DV*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_7e9f581b, /*SLOT23,VX_DV*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 2, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_7fa82b08, /*SLOT0,NOSLOT1,STORE,VP*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5],
+      [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_7fa8b40f, /*SLOT0123,VS*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_SHIFT]>], [9, 5, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_85d237e3, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
+      [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
+      [HVX_FWD]>,
+
+    InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_908a4c8c, /*SLOT23,VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 5],
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_9311da3f, /*SLOT23,VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_9777e6bf, /*SLOT0,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
+      [Hex_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_97c165b9, /*SLOT0123,VA_DV*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 7, 1, 2, 7],
+      [Hex_FWD, HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_9b9642a1, /*SLOT0123,VA*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7],
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_9c267309, /*SLOT01,LOAD*/
+      [InstrStage<1, [SLOT0, SLOT1], 0>,
+       InstrStage<1, [CVI_LD]>], [9, 3, 1, 2],
+      [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a3127e12, /*SLOT0123,VA*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7],
+      [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_a4c9df3b, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
+      [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+       InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_b06ab583, /*SLOT0123,VA*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7],
+      [HVX_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_b712833a, /*SLOT01,LOAD,VA*/
+      [InstrStage<1, [SLOT0, SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 1, 2],
+      [HVX_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b77635b4, /*SLOT0123,4SLOT*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ALL]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_bbaf280e, /*SLOT0123,VA*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7],
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_bf142ae2, /*SLOT0123,VP*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/
+      [InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c4b515c5, /*SLOT0123,VP*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_XLANE]>], [9, 5, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cbf6d1dc, /*SLOT0123,VP_VS*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cedf314b, /*SLOT0123,4SLOT*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ALL]>], [3],
+      [HVX_FWD]>,
+
+    InstrItinData <tc_d2cb81ea, /*SLOT0123,VS*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_SHIFT]>], [9, 5],
+      [HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_d5090f3e, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [2, 1, 2, 5],
+      [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_d642eff3, /*SLOT0,NOSLOT1,STORE,VP*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_XLANE]>], [2, 1, 2, 5],
+      [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_d725e5b0, /*SLOT23,VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d7bea0ec, /*SLOT0123,VP_VS*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_XLSHF]>], [9, 5],
+      [HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_d98f4d63, /*SLOT23,VX_DV*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_da979fb3, /*SLOT01,LOAD,VA*/
+      [InstrStage<1, [SLOT0, SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 2, 1, 2],
+      [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_db5b9e2f, /*SLOT0,STORE*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
+      [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
+      [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
+      [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_e231aa4f, /*SLOT23,VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_e3748cdf, /*SLOT0,STORE,VA*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_e5053c8f, /*SLOT0123,4SLOT*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ALL]>], [],
+      []>,
+
+    InstrItinData <tc_e6299d16, /*SLOT0123,VP*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_XLANE]>], [9, 5],
+      [HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_eb669007, /*SLOT01,LOAD,VA*/
+      [InstrStage<1, [SLOT0, SLOT1], 0>,
+       InstrStage<1, [CVI_LD], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
+      [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
+      [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+       InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
+      [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
+      [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
+      [HVX_FWD, HVX_FWD, Hex_FWD]>
   ];
 }
diff --git a/lib/Target/Hexagon/HexagonDepIICScalar.td b/lib/Target/Hexagon/HexagonDepIICScalar.td
index 261778bda724..083ec7753e04 100644
--- a/lib/Target/Hexagon/HexagonDepIICScalar.td
+++ b/lib/Target/Hexagon/HexagonDepIICScalar.td
@@ -1,4 +1,4 @@
-//===--- HexagonDepIICScalar.td -------------------------------------------===//
+//===- HexagonDepIICScalar.td ---------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,2499 +6,4185 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
 
-def tc_049dfb74 : InstrItinClass;
-def tc_0767081f : InstrItinClass;
-def tc_07ac815d : InstrItinClass;
-def tc_090485bb : InstrItinClass;
-def tc_09c86199 : InstrItinClass;
-def tc_09faec3b : InstrItinClass;
-def tc_0cb867f2 : InstrItinClass;
-def tc_1000eb10 : InstrItinClass;
-def tc_128719e8 : InstrItinClass;
-def tc_136c4786 : InstrItinClass;
-def tc_14da557c : InstrItinClass;
-def tc_1b6011fb : InstrItinClass;
-def tc_1b834fe7 : InstrItinClass;
-def tc_1e062b18 : InstrItinClass;
-def tc_1e69aa99 : InstrItinClass;
-def tc_1f9668cc : InstrItinClass;
-def tc_1fe8323c : InstrItinClass;
-def tc_20a8e109 : InstrItinClass;
-def tc_210b2456 : InstrItinClass;
-def tc_251c87b2 : InstrItinClass;
-def tc_261d9b78 : InstrItinClass;
-def tc_28d296df : InstrItinClass;
-def tc_29c14515 : InstrItinClass;
-def tc_2aaab1e0 : InstrItinClass;
-def tc_2c8fe5ae : InstrItinClass;
-def tc_2d1e6f5c : InstrItinClass;
-def tc_2e55aa16 : InstrItinClass;
-def tc_30665cb0 : InstrItinClass;
-def tc_336e698c : InstrItinClass;
-def tc_34e882a4 : InstrItinClass;
-def tc_35fb9d13 : InstrItinClass;
-def tc_37326008 : InstrItinClass;
-def tc_3993c58b : InstrItinClass;
-def tc_3b4892c6 : InstrItinClass;
-def tc_3bea1824 : InstrItinClass;
-def tc_3c10f809 : InstrItinClass;
-def tc_3d905451 : InstrItinClass;
-def tc_3e61d314 : InstrItinClass;
-def tc_3eab77bd : InstrItinClass;
-def tc_43068634 : InstrItinClass;
-def tc_45631a8d : InstrItinClass;
-def tc_47ab9233 : InstrItinClass;
-def tc_47f0b7ad : InstrItinClass;
-def tc_485bb57c : InstrItinClass;
-def tc_4997da4a : InstrItinClass;
-def tc_511f28f6 : InstrItinClass;
-def tc_537e2013 : InstrItinClass;
-def tc_53ee6546 : InstrItinClass;
-def tc_548f402d : InstrItinClass;
-def tc_5625c6c1 : InstrItinClass;
-def tc_580a779c : InstrItinClass;
-def tc_583510c7 : InstrItinClass;
-def tc_5d806107 : InstrItinClass;
-def tc_5fa2857c : InstrItinClass;
-def tc_5fe9fcd0 : InstrItinClass;
-def tc_6264c5e0 : InstrItinClass;
-def tc_639d93ee : InstrItinClass;
-def tc_63cd9d2d : InstrItinClass;
-def tc_65dc7cc4 : InstrItinClass;
-def tc_69bb508b : InstrItinClass;
-def tc_6c52d277 : InstrItinClass;
-def tc_6c576d46 : InstrItinClass;
-def tc_70cabf66 : InstrItinClass;
-def tc_7639d4b0 : InstrItinClass;
-def tc_7675c0e9 : InstrItinClass;
-def tc_76c4c5ef : InstrItinClass;
-def tc_77781686 : InstrItinClass;
-def tc_78b3c689 : InstrItinClass;
-def tc_7986ba30 : InstrItinClass;
-def tc_7bc567a7 : InstrItinClass;
-def tc_7c2dcd4d : InstrItinClass;
-def tc_7ca2ea10 : InstrItinClass;
-def tc_7d01cbdc : InstrItinClass;
-def tc_7d9a56cd : InstrItinClass;
-def tc_81a23d44 : InstrItinClass;
-def tc_821c4233 : InstrItinClass;
-def tc_82f0f122 : InstrItinClass;
-def tc_84630363 : InstrItinClass;
-def tc_86442910 : InstrItinClass;
-def tc_87601822 : InstrItinClass;
-def tc_88fa2da6 : InstrItinClass;
-def tc_8c8041e6 : InstrItinClass;
-def tc_8cb685d9 : InstrItinClass;
-def tc_8def9c57 : InstrItinClass;
-def tc_8f0a6bad : InstrItinClass;
-def tc_8fab9ac3 : InstrItinClass;
-def tc_92d1833c : InstrItinClass;
-def tc_94e6ffd9 : InstrItinClass;
-def tc_95c54f8b : InstrItinClass;
-def tc_9a13af9d : InstrItinClass;
-def tc_9b73d261 : InstrItinClass;
-def tc_9c18c9a5 : InstrItinClass;
-def tc_9c68db63 : InstrItinClass;
-def tc_9ce7a5ab : InstrItinClass;
-def tc_9da3628f : InstrItinClass;
-def tc_9dafb7d3 : InstrItinClass;
-def tc_9df8b0dc : InstrItinClass;
-def tc_9e86015f : InstrItinClass;
-def tc_9f518242 : InstrItinClass;
-def tc_a12a5971 : InstrItinClass;
-def tc_a1fb80e1 : InstrItinClass;
-def tc_a333d2a9 : InstrItinClass;
-def tc_a4567c39 : InstrItinClass;
-def tc_a87879e8 : InstrItinClass;
-def tc_a9c993d9 : InstrItinClass;
-def tc_aad55963 : InstrItinClass;
-def tc_ab1b5e74 : InstrItinClass;
-def tc_ae0722f7 : InstrItinClass;
-def tc_ae2c2dc2 : InstrItinClass;
-def tc_ae762521 : InstrItinClass;
-def tc_b08b653e : InstrItinClass;
-def tc_b08be45e : InstrItinClass;
-def tc_b0f50e3c : InstrItinClass;
-def tc_b189ad4c : InstrItinClass;
-def tc_b324366f : InstrItinClass;
-def tc_b5bfaa60 : InstrItinClass;
-def tc_b5f5a094 : InstrItinClass;
-def tc_b86c7e8b : InstrItinClass;
-def tc_baccf077 : InstrItinClass;
-def tc_bc5561d8 : InstrItinClass;
-def tc_bcf0e36e : InstrItinClass;
-def tc_bd16579e : InstrItinClass;
-def tc_be995eaf : InstrItinClass;
-def tc_bf6fa601 : InstrItinClass;
-def tc_c0cd91a8 : InstrItinClass;
-def tc_c14739d5 : InstrItinClass;
-def tc_c1dbc916 : InstrItinClass;
-def tc_c58f771a : InstrItinClass;
-def tc_c85212ca : InstrItinClass;
-def tc_c8f9a6f6 : InstrItinClass;
-def tc_ca280e8b : InstrItinClass;
-def tc_cbe45117 : InstrItinClass;
-def tc_cd321066 : InstrItinClass;
-def tc_d108a090 : InstrItinClass;
-def tc_d1b5a4b6 : InstrItinClass;
-def tc_d2609065 : InstrItinClass;
-def tc_d267fa19 : InstrItinClass;
-def tc_d2a33af5 : InstrItinClass;
-def tc_d63b71d1 : InstrItinClass;
-def tc_d6a805a8 : InstrItinClass;
-def tc_d95f4e98 : InstrItinClass;
-def tc_da79106e : InstrItinClass;
-def tc_dbe218dd : InstrItinClass;
-def tc_dcfee7ae : InstrItinClass;
-def tc_e17ce9ad : InstrItinClass;
-def tc_e2480a7f : InstrItinClass;
-def tc_e2c08bb4 : InstrItinClass;
-def tc_e2c31426 : InstrItinClass;
-def tc_e578178f : InstrItinClass;
-def tc_e836c161 : InstrItinClass;
-def tc_e8c7a357 : InstrItinClass;
-def tc_eb07ef6f : InstrItinClass;
-def tc_ecfaae86 : InstrItinClass;
-def tc_ef0ebaaa : InstrItinClass;
-def tc_ef2676fd : InstrItinClass;
-def tc_f027ebe9 : InstrItinClass;
-def tc_f055fbb6 : InstrItinClass;
-def tc_f1240c08 : InstrItinClass;
-def tc_f16d5b17 : InstrItinClass;
-def tc_f1aa2cdb : InstrItinClass;
-def tc_f26aa619 : InstrItinClass;
-def tc_f4608adc : InstrItinClass;
-def tc_faab1248 : InstrItinClass;
-def tc_fcee8723 : InstrItinClass;
-def tc_feb4974b : InstrItinClass;
+def tc_0077f68c : InstrItinClass;
+def tc_00afc57e : InstrItinClass;
+def tc_00e7c26e : InstrItinClass;
+def tc_03220ffa : InstrItinClass;
+def tc_038a1342 : InstrItinClass;
+def tc_04c9decc : InstrItinClass;
+def tc_05b6c987 : InstrItinClass;
+def tc_0a2b8c7c : InstrItinClass;
+def tc_0cd51c76 : InstrItinClass;
+def tc_0dc560de : InstrItinClass;
+def tc_0fc1ae07 : InstrItinClass;
+def tc_10b97e27 : InstrItinClass;
+def tc_128f96e3 : InstrItinClass;
+def tc_1372bca1 : InstrItinClass;
+def tc_1432937d : InstrItinClass;
+def tc_14cd4cfa : InstrItinClass;
+def tc_15411484 : InstrItinClass;
+def tc_16d0d8d5 : InstrItinClass;
+def tc_181af5d0 : InstrItinClass;
+def tc_1853ea6d : InstrItinClass;
+def tc_1b82a277 : InstrItinClass;
+def tc_1b9c9ee5 : InstrItinClass;
+def tc_1c0005f9 : InstrItinClass;
+def tc_1d5a38a8 : InstrItinClass;
+def tc_1e856f58 : InstrItinClass;
+def tc_20280784 : InstrItinClass;
+def tc_234a11a5 : InstrItinClass;
+def tc_238d91d2 : InstrItinClass;
+def tc_29175780 : InstrItinClass;
+def tc_29641329 : InstrItinClass;
+def tc_2a160009 : InstrItinClass;
+def tc_2b2f4060 : InstrItinClass;
+def tc_2b6f77c6 : InstrItinClass;
+def tc_2e00db30 : InstrItinClass;
+def tc_2f185f5c : InstrItinClass;
+def tc_2fc0c436 : InstrItinClass;
+def tc_351fed2d : InstrItinClass;
+def tc_3669266a : InstrItinClass;
+def tc_367f7f3d : InstrItinClass;
+def tc_36c68ad1 : InstrItinClass;
+def tc_395dc00f : InstrItinClass;
+def tc_3bc2c5d3 : InstrItinClass;
+def tc_3cb8ea06 : InstrItinClass;
+def tc_3d04548d : InstrItinClass;
+def tc_3da80ba5 : InstrItinClass;
+def tc_3e07fb90 : InstrItinClass;
+def tc_41d5298e : InstrItinClass;
+def tc_4403ca65 : InstrItinClass;
+def tc_44126683 : InstrItinClass;
+def tc_452f85af : InstrItinClass;
+def tc_481e5e5c : InstrItinClass;
+def tc_49eb22c8 : InstrItinClass;
+def tc_4ca572d4 : InstrItinClass;
+def tc_4d9914c9 : InstrItinClass;
+def tc_4d99bca9 : InstrItinClass;
+def tc_4f7cd700 : InstrItinClass;
+def tc_513bef45 : InstrItinClass;
+def tc_51b866be : InstrItinClass;
+def tc_523fcf30 : InstrItinClass;
+def tc_5274e61a : InstrItinClass;
+def tc_52d7bbea : InstrItinClass;
+def tc_53173427 : InstrItinClass;
+def tc_53bc8a6a : InstrItinClass;
+def tc_53bdb2f6 : InstrItinClass;
+def tc_540fdfbc : InstrItinClass;
+def tc_55050d58 : InstrItinClass;
+def tc_56d25411 : InstrItinClass;
+def tc_57288781 : InstrItinClass;
+def tc_594ab548 : InstrItinClass;
+def tc_5acef64a : InstrItinClass;
+def tc_5ba5997d : InstrItinClass;
+def tc_5eb851fc : InstrItinClass;
+def tc_5f6847a1 : InstrItinClass;
+def tc_60571023 : InstrItinClass;
+def tc_609d2efe : InstrItinClass;
+def tc_60d76817 : InstrItinClass;
+def tc_60f5738d : InstrItinClass;
+def tc_63fe3df7 : InstrItinClass;
+def tc_66888ded : InstrItinClass;
+def tc_6792d5ff : InstrItinClass;
+def tc_681a2300 : InstrItinClass;
+def tc_68cb12ce : InstrItinClass;
+def tc_6aa5711a : InstrItinClass;
+def tc_6ac37025 : InstrItinClass;
+def tc_6ebb4a12 : InstrItinClass;
+def tc_6efc556e : InstrItinClass;
+def tc_73043bf4 : InstrItinClass;
+def tc_746baa8e : InstrItinClass;
+def tc_74e47fd9 : InstrItinClass;
+def tc_7934b9df : InstrItinClass;
+def tc_7a830544 : InstrItinClass;
+def tc_7f881c76 : InstrItinClass;
+def tc_84df2cd3 : InstrItinClass;
+def tc_85523bcb : InstrItinClass;
+def tc_855b0b61 : InstrItinClass;
+def tc_87735c3b : InstrItinClass;
+def tc_88fa1a78 : InstrItinClass;
+def tc_897d1a9d : InstrItinClass;
+def tc_8b15472a : InstrItinClass;
+def tc_8bb285ec : InstrItinClass;
+def tc_8fd5f294 : InstrItinClass;
+def tc_8fe6b782 : InstrItinClass;
+def tc_90f3e30c : InstrItinClass;
+def tc_976ddc4f : InstrItinClass;
+def tc_97743097 : InstrItinClass;
+def tc_999d32db : InstrItinClass;
+def tc_99be14ca : InstrItinClass;
+def tc_9c00ce8d : InstrItinClass;
+def tc_9c98e8af : InstrItinClass;
+def tc_9d5941c7 : InstrItinClass;
+def tc_9ef61e5c : InstrItinClass;
+def tc_9faf76ae : InstrItinClass;
+def tc_9fdb5406 : InstrItinClass;
+def tc_a21dc435 : InstrItinClass;
+def tc_a27582fa : InstrItinClass;
+def tc_a46f0df5 : InstrItinClass;
+def tc_a788683e : InstrItinClass;
+def tc_a8acdac0 : InstrItinClass;
+def tc_a904d137 : InstrItinClass;
+def tc_adb14c66 : InstrItinClass;
+def tc_b13761ae : InstrItinClass;
+def tc_b166348b : InstrItinClass;
+def tc_b44c6e2a : InstrItinClass;
+def tc_b5a33b22 : InstrItinClass;
+def tc_b77c481f : InstrItinClass;
+def tc_b7dd427e : InstrItinClass;
+def tc_b9488031 : InstrItinClass;
+def tc_b9c0b731 : InstrItinClass;
+def tc_b9c4623f : InstrItinClass;
+def tc_bad2bcaf : InstrItinClass;
+def tc_bcc96cee : InstrItinClass;
+def tc_bd90564c : InstrItinClass;
+def tc_bde7aaf4 : InstrItinClass;
+def tc_be706f30 : InstrItinClass;
+def tc_c2f7d806 : InstrItinClass;
+def tc_c5e2426d : InstrItinClass;
+def tc_c6aa82f7 : InstrItinClass;
+def tc_c6ce9b3f : InstrItinClass;
+def tc_c6ebf8dd : InstrItinClass;
+def tc_c74f796f : InstrItinClass;
+def tc_c82dc1ff : InstrItinClass;
+def tc_caaebcba : InstrItinClass;
+def tc_cd7374a0 : InstrItinClass;
+def tc_cde8b071 : InstrItinClass;
+def tc_cf47a43f : InstrItinClass;
+def tc_cf59f215 : InstrItinClass;
+def tc_d088982c : InstrItinClass;
+def tc_d1090e34 : InstrItinClass;
+def tc_d24b2d85 : InstrItinClass;
+def tc_d580173f : InstrItinClass;
+def tc_d6bf0472 : InstrItinClass;
+def tc_d9709180 : InstrItinClass;
+def tc_d9f95eef : InstrItinClass;
+def tc_daa058fa : InstrItinClass;
+def tc_dbdffe3d : InstrItinClass;
+def tc_e0739b8c : InstrItinClass;
+def tc_e1e0a2dc : InstrItinClass;
+def tc_e1e99bfa : InstrItinClass;
+def tc_e216a5db : InstrItinClass;
+def tc_e421e012 : InstrItinClass;
+def tc_e6b38e01 : InstrItinClass;
+def tc_e7624c08 : InstrItinClass;
+def tc_e7d02c66 : InstrItinClass;
+def tc_e913dc32 : InstrItinClass;
+def tc_e9c822f7 : InstrItinClass;
+def tc_e9fae2d6 : InstrItinClass;
+def tc_ef20db1c : InstrItinClass;
+def tc_ef52ed71 : InstrItinClass;
+def tc_ef84f62f : InstrItinClass;
+def tc_f2704b9a : InstrItinClass;
+def tc_f3eaa14b : InstrItinClass;
+def tc_f47d212f : InstrItinClass;
+def tc_f49e76f4 : InstrItinClass;
+def tc_f4f43fb5 : InstrItinClass;
+def tc_f7dd9c9f : InstrItinClass;
+def tc_f86c328a : InstrItinClass;
+def tc_f8eeed7a : InstrItinClass;
+def tc_fcab4871 : InstrItinClass;
+def tc_ff9ee76e : InstrItinClass;
 
 class DepScalarItinV4 {
   list<InstrItinData> DepScalarItinV4_list = [
-    InstrItinData <tc_049dfb74, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_0767081f, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_07ac815d, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_090485bb, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_09c86199, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_09faec3b, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_0cb867f2, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_1000eb10, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_128719e8, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_136c4786, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_14da557c, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_1b6011fb, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_1b834fe7, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_1e062b18, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_1e69aa99, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_1f9668cc, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_1fe8323c, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_20a8e109, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_210b2456, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_251c87b2, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_261d9b78, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_28d296df, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_29c14515, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_2aaab1e0, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_2c8fe5ae, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_2d1e6f5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_2e55aa16, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_30665cb0, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_336e698c, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_34e882a4, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_35fb9d13, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_37326008, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_3993c58b, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_3b4892c6, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_3bea1824, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_3c10f809, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_3d905451, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_3e61d314, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_3eab77bd, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_43068634, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_45631a8d, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_47ab9233, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_47f0b7ad, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_485bb57c, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_4997da4a, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_511f28f6, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_537e2013, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_53ee6546, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_548f402d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_5625c6c1, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_580a779c, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_583510c7, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_5d806107, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_5fa2857c, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_5fe9fcd0, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_6264c5e0, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_639d93ee, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_63cd9d2d, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_65dc7cc4, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_69bb508b, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_6c52d277, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_6c576d46, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_70cabf66, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_7639d4b0, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_7675c0e9, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_76c4c5ef, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_77781686, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_78b3c689, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_7986ba30, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_7bc567a7, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_7c2dcd4d, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_7ca2ea10, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_7d01cbdc, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_7d9a56cd, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_81a23d44, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_821c4233, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_82f0f122, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_84630363, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_86442910, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_87601822, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_88fa2da6, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_8c8041e6, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_8cb685d9, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_8def9c57, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_8f0a6bad, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_8fab9ac3, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_92d1833c, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_94e6ffd9, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_95c54f8b, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_9a13af9d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_9b73d261, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_9c18c9a5, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_9c68db63, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_9ce7a5ab, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_9da3628f, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_9dafb7d3, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_9df8b0dc, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_9e86015f, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_9f518242, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_a12a5971, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_a1fb80e1, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_a333d2a9, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_a4567c39, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_a87879e8, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_a9c993d9, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_aad55963, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_ab1b5e74, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_ae0722f7, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_ae2c2dc2, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_ae762521, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_b08b653e, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_b08be45e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_b0f50e3c, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_b189ad4c, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_b324366f, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_b5bfaa60, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_b5f5a094, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_b86c7e8b, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_baccf077, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_bc5561d8, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_bcf0e36e, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_bd16579e, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_be995eaf, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_bf6fa601, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_c0cd91a8, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_c14739d5, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_c1dbc916, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_c58f771a, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_c85212ca, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_c8f9a6f6, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_ca280e8b, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_cbe45117, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_cd321066, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_d108a090, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_d1b5a4b6, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_d2609065, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_d267fa19, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_d2a33af5, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_d63b71d1, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_d6a805a8, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_d95f4e98, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_da79106e, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_dbe218dd, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_dcfee7ae, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_e17ce9ad, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_e2480a7f, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_e2c08bb4, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_e2c31426, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_e578178f, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_e836c161, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_e8c7a357, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_eb07ef6f, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_ecfaae86, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_ef0ebaaa, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_ef2676fd, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_f027ebe9, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_f055fbb6, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_f1240c08, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_f16d5b17, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_f1aa2cdb, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_f26aa619, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_f4608adc, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_faab1248, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_fcee8723, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_feb4974b, [InstrStage<1, [SLOT3]>]>  ];
+    InstrItinData <tc_0077f68c, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_00afc57e, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_00e7c26e, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_03220ffa, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_038a1342, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_04c9decc, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_05b6c987, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_0a2b8c7c, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_0cd51c76, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_0dc560de, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_0fc1ae07, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_10b97e27, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_128f96e3, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_1372bca1, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_1432937d, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_14cd4cfa, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_15411484, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_16d0d8d5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_181af5d0, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_1853ea6d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_1b82a277, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_1b9c9ee5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_1c0005f9, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_1d5a38a8, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_1e856f58, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_20280784, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_234a11a5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_238d91d2, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_29175780, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_29641329, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_2a160009, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_2b2f4060, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_2b6f77c6, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_2e00db30, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_2f185f5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_2fc0c436, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_351fed2d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_3669266a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_367f7f3d, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_36c68ad1, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_395dc00f, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_3bc2c5d3, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_3cb8ea06, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_3d04548d, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_3da80ba5, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_3e07fb90, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_41d5298e, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_4403ca65, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_44126683, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_452f85af, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_481e5e5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_49eb22c8, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_4ca572d4, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_4d9914c9, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_4d99bca9, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_4f7cd700, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_513bef45, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_51b866be, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_523fcf30, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_5274e61a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_52d7bbea, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_53173427, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_53bc8a6a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_53bdb2f6, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_540fdfbc, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_55050d58, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_56d25411, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_57288781, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_594ab548, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_5acef64a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_5ba5997d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_5eb851fc, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_5f6847a1, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_60571023, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_609d2efe, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_60d76817, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_60f5738d, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_63fe3df7, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_66888ded, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_6792d5ff, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_681a2300, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_68cb12ce, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_6aa5711a, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_6ac37025, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_6ebb4a12, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_6efc556e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_73043bf4, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_746baa8e, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_74e47fd9, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_7934b9df, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_7a830544, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_7f881c76, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_84df2cd3, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_85523bcb, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_855b0b61, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_87735c3b, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_88fa1a78, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_897d1a9d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_8b15472a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_8bb285ec, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_8fd5f294, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_8fe6b782, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_90f3e30c, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_976ddc4f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_97743097, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_999d32db, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_99be14ca, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_9c00ce8d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_9c98e8af, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_9d5941c7, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_9ef61e5c, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_9faf76ae, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_9fdb5406, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_a21dc435, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_a27582fa, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_a46f0df5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_a788683e, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_a8acdac0, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_a904d137, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_adb14c66, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_b13761ae, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_b166348b, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_b44c6e2a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_b5a33b22, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_b77c481f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_b7dd427e, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_b9488031, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_b9c0b731, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_b9c4623f, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_bad2bcaf, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_bcc96cee, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_bd90564c, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_bde7aaf4, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_be706f30, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c2f7d806, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c5e2426d, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_c6aa82f7, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c6ce9b3f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c6ebf8dd, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c74f796f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c82dc1ff, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_caaebcba, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_cd7374a0, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_cde8b071, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_cf47a43f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_cf59f215, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_d088982c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_d1090e34, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_d24b2d85, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_d580173f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_d6bf0472, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_d9709180, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_d9f95eef, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_daa058fa, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_dbdffe3d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_e0739b8c, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_e1e0a2dc, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_e1e99bfa, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_e216a5db, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_e421e012, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_e6b38e01, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_e7624c08, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_e7d02c66, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_e913dc32, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_e9c822f7, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_e9fae2d6, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_ef20db1c, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_ef52ed71, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_ef84f62f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_f2704b9a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_f3eaa14b, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_f47d212f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_f49e76f4, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_f4f43fb5, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_f7dd9c9f, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_f86c328a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_f8eeed7a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_fcab4871, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_ff9ee76e, [InstrStage<1, [SLOT0]>]>  ];
 }
 
 class DepScalarItinV5 {
   list<InstrItinData> DepScalarItinV5_list = [
-    InstrItinData <tc_049dfb74, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_0767081f, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_07ac815d, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_090485bb, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_09c86199, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_09faec3b, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_0cb867f2, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_1000eb10, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_128719e8, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_136c4786, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_14da557c, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_1b6011fb, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_1b834fe7, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_1e062b18, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_1e69aa99, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_1f9668cc, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_1fe8323c, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_20a8e109, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_210b2456, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_251c87b2, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_261d9b78, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_28d296df, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_29c14515, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_2aaab1e0, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_2c8fe5ae, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_2d1e6f5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_2e55aa16, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_30665cb0, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_336e698c, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_34e882a4, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_35fb9d13, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_37326008, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_3993c58b, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_3b4892c6, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_3bea1824, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_3c10f809, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_3d905451, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_3e61d314, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_3eab77bd, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_43068634, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_45631a8d, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_47ab9233, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_47f0b7ad, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_485bb57c, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_4997da4a, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_511f28f6, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_537e2013, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_53ee6546, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_548f402d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_5625c6c1, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_580a779c, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_583510c7, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_5d806107, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_5fa2857c, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_5fe9fcd0, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_6264c5e0, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_639d93ee, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_63cd9d2d, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_65dc7cc4, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_69bb508b, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_6c52d277, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_6c576d46, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_70cabf66, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_7639d4b0, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_7675c0e9, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_76c4c5ef, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_77781686, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_78b3c689, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_7986ba30, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_7bc567a7, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_7c2dcd4d, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_7ca2ea10, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_7d01cbdc, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_7d9a56cd, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_81a23d44, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_821c4233, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_82f0f122, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_84630363, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_86442910, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_87601822, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_88fa2da6, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_8c8041e6, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_8cb685d9, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_8def9c57, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_8f0a6bad, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_8fab9ac3, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_92d1833c, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_94e6ffd9, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_95c54f8b, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_9a13af9d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_9b73d261, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_9c18c9a5, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_9c68db63, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_9ce7a5ab, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_9da3628f, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_9dafb7d3, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_9df8b0dc, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_9e86015f, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_9f518242, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_a12a5971, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_a1fb80e1, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_a333d2a9, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_a4567c39, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_a87879e8, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_a9c993d9, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_aad55963, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_ab1b5e74, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_ae0722f7, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_ae2c2dc2, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_ae762521, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_b08b653e, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_b08be45e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_b0f50e3c, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_b189ad4c, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_b324366f, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_b5bfaa60, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_b5f5a094, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_b86c7e8b, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_baccf077, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_bc5561d8, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_bcf0e36e, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_bd16579e, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_be995eaf, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_bf6fa601, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_c0cd91a8, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_c14739d5, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_c1dbc916, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_c58f771a, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_c85212ca, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_c8f9a6f6, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_ca280e8b, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_cbe45117, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_cd321066, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_d108a090, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_d1b5a4b6, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_d2609065, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_d267fa19, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_d2a33af5, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_d63b71d1, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_d6a805a8, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_d95f4e98, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_da79106e, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_dbe218dd, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_dcfee7ae, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_e17ce9ad, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_e2480a7f, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_e2c08bb4, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_e2c31426, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_e578178f, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_e836c161, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_e8c7a357, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_eb07ef6f, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_ecfaae86, [InstrStage<1, [SLOT2]>]>,
-    InstrItinData <tc_ef0ebaaa, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_ef2676fd, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_f027ebe9, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_f055fbb6, [InstrStage<1, [SLOT3]>]>,
-    InstrItinData <tc_f1240c08, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_f16d5b17, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-    InstrItinData <tc_f1aa2cdb, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_f26aa619, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_f4608adc, [InstrStage<1, [SLOT0]>]>,
-    InstrItinData <tc_faab1248, [InstrStage<1, [SLOT2, SLOT3]>]>,
-    InstrItinData <tc_fcee8723, [InstrStage<1, [SLOT0, SLOT1]>]>,
-    InstrItinData <tc_feb4974b, [InstrStage<1, [SLOT3]>]>  ];
+    InstrItinData <tc_0077f68c, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_00afc57e, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_00e7c26e, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_03220ffa, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_038a1342, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_04c9decc, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_05b6c987, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_0a2b8c7c, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_0cd51c76, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_0dc560de, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_0fc1ae07, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_10b97e27, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_128f96e3, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_1372bca1, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_1432937d, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_14cd4cfa, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_15411484, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_16d0d8d5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_181af5d0, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_1853ea6d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_1b82a277, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_1b9c9ee5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_1c0005f9, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_1d5a38a8, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_1e856f58, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_20280784, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_234a11a5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_238d91d2, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_29175780, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_29641329, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_2a160009, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_2b2f4060, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_2b6f77c6, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_2e00db30, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_2f185f5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_2fc0c436, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_351fed2d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_3669266a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_367f7f3d, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_36c68ad1, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_395dc00f, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_3bc2c5d3, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_3cb8ea06, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_3d04548d, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_3da80ba5, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_3e07fb90, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_41d5298e, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_4403ca65, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_44126683, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_452f85af, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_481e5e5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_49eb22c8, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_4ca572d4, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_4d9914c9, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_4d99bca9, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_4f7cd700, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_513bef45, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_51b866be, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_523fcf30, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_5274e61a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_52d7bbea, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_53173427, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_53bc8a6a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_53bdb2f6, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_540fdfbc, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_55050d58, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_56d25411, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_57288781, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_594ab548, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_5acef64a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_5ba5997d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_5eb851fc, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_5f6847a1, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_60571023, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_609d2efe, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_60d76817, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_60f5738d, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_63fe3df7, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_66888ded, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_6792d5ff, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_681a2300, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_68cb12ce, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_6aa5711a, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_6ac37025, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_6ebb4a12, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_6efc556e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_73043bf4, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_746baa8e, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_74e47fd9, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_7934b9df, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_7a830544, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_7f881c76, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_84df2cd3, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_85523bcb, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_855b0b61, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_87735c3b, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_88fa1a78, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_897d1a9d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_8b15472a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_8bb285ec, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_8fd5f294, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_8fe6b782, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_90f3e30c, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_976ddc4f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_97743097, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_999d32db, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_99be14ca, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_9c00ce8d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_9c98e8af, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_9d5941c7, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_9ef61e5c, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_9faf76ae, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_9fdb5406, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_a21dc435, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_a27582fa, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_a46f0df5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_a788683e, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_a8acdac0, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_a904d137, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_adb14c66, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_b13761ae, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_b166348b, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_b44c6e2a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_b5a33b22, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_b77c481f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_b7dd427e, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_b9488031, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_b9c0b731, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_b9c4623f, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_bad2bcaf, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_bcc96cee, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_bd90564c, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_bde7aaf4, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_be706f30, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c2f7d806, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c5e2426d, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_c6aa82f7, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c6ce9b3f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c6ebf8dd, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c74f796f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_c82dc1ff, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_caaebcba, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_cd7374a0, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_cde8b071, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_cf47a43f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_cf59f215, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_d088982c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_d1090e34, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_d24b2d85, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_d580173f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_d6bf0472, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+    InstrItinData <tc_d9709180, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_d9f95eef, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_daa058fa, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_dbdffe3d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_e0739b8c, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_e1e0a2dc, [InstrStage<1, [SLOT2]>]>,
+    InstrItinData <tc_e1e99bfa, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_e216a5db, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_e421e012, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_e6b38e01, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_e7624c08, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_e7d02c66, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_e913dc32, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_e9c822f7, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_e9fae2d6, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_ef20db1c, [InstrStage<1, [SLOT3]>]>,
+    InstrItinData <tc_ef52ed71, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_ef84f62f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_f2704b9a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_f3eaa14b, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_f47d212f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_f49e76f4, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_f4f43fb5, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_f7dd9c9f, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_f86c328a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+    InstrItinData <tc_f8eeed7a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+    InstrItinData <tc_fcab4871, [InstrStage<1, [SLOT0]>]>,
+    InstrItinData <tc_ff9ee76e, [InstrStage<1, [SLOT0]>]>  ];
 }
 
 class DepScalarItinV55 {
   list<InstrItinData> DepScalarItinV55_list = [
-    InstrItinData <tc_049dfb74, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [1],
+    InstrItinData <tc_0077f68c, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_0767081f, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+    InstrItinData <tc_00afc57e, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_07ac815d, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [2, 1],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_00e7c26e, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_090485bb, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_03220ffa, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_09c86199, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_038a1342, /*tc_3*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_09faec3b, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 2],
+    InstrItinData <tc_04c9decc, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_0cb867f2, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [4, 2, 2],
+    InstrItinData <tc_05b6c987, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1000eb10, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [2, 2],
+    InstrItinData <tc_0a2b8c7c, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_128719e8, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
+    InstrItinData <tc_0cd51c76, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_136c4786, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
+    InstrItinData <tc_0dc560de, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0fc1ae07, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_10b97e27, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_128f96e3, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1372bca1, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_14da557c, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_1432937d, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1b6011fb, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+    InstrItinData <tc_14cd4cfa, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_15411484, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_16d0d8d5, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1b834fe7, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+    InstrItinData <tc_181af5d0, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [3, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1e062b18, /*tc_1*/
+    InstrItinData <tc_1853ea6d, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1b82a277, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_1b9c9ee5, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1e69aa99, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_1c0005f9, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1f9668cc, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [3, 1],
+    InstrItinData <tc_1d5a38a8, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1e856f58, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_20280784, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1fe8323c, /*tc_2*/
-      [InstrStage<1, [SLOT3]>], [4, 2],
+    InstrItinData <tc_234a11a5, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_20a8e109, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_238d91d2, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_210b2456, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_29175780, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_251c87b2, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_29641329, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_261d9b78, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_2a160009, /*tc_2early*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
 
-    InstrItinData <tc_28d296df, /*tc_1*/
+    InstrItinData <tc_2b2f4060, /*tc_1*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_29c14515, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [4, 1],
+    InstrItinData <tc_2b6f77c6, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_2e00db30, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_2f185f5c, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2aaab1e0, /*tc_3*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1],
+    InstrItinData <tc_2fc0c436, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2c8fe5ae, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 2, 3],
+    InstrItinData <tc_351fed2d, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_3669266a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_367f7f3d, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_36c68ad1, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [],
+      []>,
+
+    InstrItinData <tc_395dc00f, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 3, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2d1e6f5c, /*tc_3*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3bc2c5d3, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [2],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_2e55aa16, /*tc_3*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3cb8ea06, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_3d04548d, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_30665cb0, /*tc_st*/
+    InstrItinData <tc_3da80ba5, /*tc_ld*/
       [InstrStage<1, [SLOT0]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_336e698c, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+    InstrItinData <tc_3e07fb90, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_41d5298e, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_4403ca65, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_44126683, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_34e882a4, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [1],
+    InstrItinData <tc_452f85af, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_35fb9d13, /*tc_2early*/
-      [InstrStage<1, [SLOT0]>], [],
+    InstrItinData <tc_481e5e5c, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_49eb22c8, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_4ca572d4, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [],
       []>,
 
-    InstrItinData <tc_37326008, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_4d9914c9, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_4d99bca9, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3993c58b, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [4, 3, 1],
+    InstrItinData <tc_4f7cd700, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_513bef45, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 2, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3b4892c6, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [4, 2],
+    InstrItinData <tc_51b866be, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_523fcf30, /*tc_3stall*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5274e61a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_52d7bbea, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+      []>,
+
+    InstrItinData <tc_53173427, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [1, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3bea1824, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+    InstrItinData <tc_53bc8a6a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3c10f809, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_53bdb2f6, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3d905451, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_540fdfbc, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3e61d314, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [1, 3, 2],
+    InstrItinData <tc_55050d58, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3eab77bd, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_56d25411, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_43068634, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+    InstrItinData <tc_57288781, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_594ab548, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_45631a8d, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+    InstrItinData <tc_5acef64a, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_47ab9233, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_5ba5997d, /*tc_2*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_47f0b7ad, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_5eb851fc, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_485bb57c, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_5f6847a1, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_4997da4a, /*tc_3x*/
+    InstrItinData <tc_60571023, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_609d2efe, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_60d76817, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [],
+      []>,
+
+    InstrItinData <tc_60f5738d, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_511f28f6, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_63fe3df7, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_66888ded, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_537e2013, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_6792d5ff, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_681a2300, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_68cb12ce, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_53ee6546, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+    InstrItinData <tc_6aa5711a, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_6ac37025, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_548f402d, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_6ebb4a12, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5625c6c1, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_6efc556e, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+      []>,
 
-    InstrItinData <tc_580a779c, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [3, 1, 2],
+    InstrItinData <tc_73043bf4, /*tc_2early*/
+      [InstrStage<1, [SLOT3]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_746baa8e, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_74e47fd9, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_7934b9df, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_7a830544, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_583510c7, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+    InstrItinData <tc_7f881c76, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_84df2cd3, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5d806107, /*tc_3stall*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+    InstrItinData <tc_85523bcb, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5fa2857c, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
+    InstrItinData <tc_855b0b61, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5fe9fcd0, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+    InstrItinData <tc_87735c3b, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_88fa1a78, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_897d1a9d, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_6264c5e0, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+    InstrItinData <tc_8b15472a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_639d93ee, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2],
+    InstrItinData <tc_8bb285ec, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_63cd9d2d, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_8fd5f294, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_65dc7cc4, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
-    InstrItinData <tc_69bb508b, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_8fe6b782, /*tc_2*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_6c52d277, /*tc_st*/
+    InstrItinData <tc_90f3e30c, /*tc_2early*/
       [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_6c576d46, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 3],
+    InstrItinData <tc_976ddc4f, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_97743097, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_999d32db, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_99be14ca, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_70cabf66, /*tc_ld*/
+    InstrItinData <tc_9c00ce8d, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_9c98e8af, /*tc_ld*/
       [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7639d4b0, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
+    InstrItinData <tc_9d5941c7, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7675c0e9, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
+    InstrItinData <tc_9ef61e5c, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_76c4c5ef, /*tc_2*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_9faf76ae, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_77781686, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+    InstrItinData <tc_9fdb5406, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_78b3c689, /*tc_1*/
+    InstrItinData <tc_a21dc435, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a27582fa, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_a46f0df5, /*tc_2early*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7986ba30, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 3],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_a788683e, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7bc567a7, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
+    InstrItinData <tc_a8acdac0, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a904d137, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_adb14c66, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7c2dcd4d, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3],
-      [Hex_FWD]>,
+    InstrItinData <tc_b13761ae, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [],
+      []>,
 
-    InstrItinData <tc_7ca2ea10, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_b166348b, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b44c6e2a, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7d01cbdc, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [4, 1, 1],
+    InstrItinData <tc_b5a33b22, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7d9a56cd, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
+    InstrItinData <tc_b77c481f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b7dd427e, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b9488031, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b9c0b731, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_81a23d44, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_b9c4623f, /*tc_2*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_821c4233, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+    InstrItinData <tc_bad2bcaf, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bcc96cee, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bd90564c, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bde7aaf4, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_82f0f122, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [4, 1],
+    InstrItinData <tc_be706f30, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_84630363, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [2, 1],
+    InstrItinData <tc_c2f7d806, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_86442910, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [],
-      []>,
+    InstrItinData <tc_c5e2426d, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_87601822, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_c6aa82f7, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_88fa2da6, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_c6ce9b3f, /*tc_3*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8c8041e6, /*tc_3x*/
+    InstrItinData <tc_c6ebf8dd, /*tc_3stall*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8cb685d9, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
+    InstrItinData <tc_c74f796f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8def9c57, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+    InstrItinData <tc_c82dc1ff, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_caaebcba, /*tc_3*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8f0a6bad, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+    InstrItinData <tc_cd7374a0, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cde8b071, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cf47a43f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8fab9ac3, /*tc_st*/
+    InstrItinData <tc_cf59f215, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d088982c, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d1090e34, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d24b2d85, /*tc_st*/
       [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_92d1833c, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2],
+    InstrItinData <tc_d580173f, /*tc_3*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d6bf0472, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d9709180, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d9f95eef, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_daa058fa, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_dbdffe3d, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_94e6ffd9, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+    InstrItinData <tc_e0739b8c, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_95c54f8b, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [],
+    InstrItinData <tc_e1e0a2dc, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [],
       []>,
 
-    InstrItinData <tc_9a13af9d, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
-      [Hex_FWD]>,
-
-    InstrItinData <tc_9b73d261, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e1e99bfa, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9c18c9a5, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_e216a5db, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9c68db63, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
+    InstrItinData <tc_e421e012, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9ce7a5ab, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [4, 2, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e6b38e01, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9da3628f, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
+    InstrItinData <tc_e7624c08, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [3],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_e7d02c66, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9dafb7d3, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e913dc32, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9df8b0dc, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e9c822f7, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_9e86015f, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 3],
+    InstrItinData <tc_e9fae2d6, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9f518242, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_ef20db1c, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a12a5971, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
+    InstrItinData <tc_ef52ed71, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a1fb80e1, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [2, 1],
+    InstrItinData <tc_ef84f62f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f2704b9a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a333d2a9, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2],
-      [Hex_FWD]>,
+    InstrItinData <tc_f3eaa14b, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a4567c39, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+    InstrItinData <tc_f47d212f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a87879e8, /*tc_3stall*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_f49e76f4, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a9c993d9, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 2],
+    InstrItinData <tc_f4f43fb5, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_aad55963, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+    InstrItinData <tc_f7dd9c9f, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f86c328a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f8eeed7a, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_fcab4871, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [],
       []>,
 
-    InstrItinData <tc_ab1b5e74, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_ff9ee76e, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 3],
+      [Hex_FWD, Hex_FWD]>
+  ];
+}
+
+class DepScalarItinV60 {
+  list<InstrItinData> DepScalarItinV60_list = [
+    InstrItinData <tc_0077f68c, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_00afc57e, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ae0722f7, /*tc_3*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
+    InstrItinData <tc_00e7c26e, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_03220ffa, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_038a1342, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ae2c2dc2, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
+    InstrItinData <tc_04c9decc, /*tc_3stall*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ae762521, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
+    InstrItinData <tc_05b6c987, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0a2b8c7c, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0cd51c76, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b08b653e, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [1],
+    InstrItinData <tc_0dc560de, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0fc1ae07, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_b08be45e, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_10b97e27, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b0f50e3c, /*tc_2*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_128f96e3, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1372bca1, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b189ad4c, /*tc_2early*/
+    InstrItinData <tc_1432937d, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_14cd4cfa, /*tc_2early*/
       [InstrStage<1, [SLOT2]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_b324366f, /*tc_2early*/
-      [InstrStage<1, [SLOT3]>], [1, 2],
+    InstrItinData <tc_15411484, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_16d0d8d5, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_181af5d0, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [3, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b5bfaa60, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+    InstrItinData <tc_1853ea6d, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1b82a277, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_1b9c9ee5, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1c0005f9, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b5f5a094, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+    InstrItinData <tc_1d5a38a8, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b86c7e8b, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_1e856f58, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_20280784, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_baccf077, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_234a11a5, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bc5561d8, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_238d91d2, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bcf0e36e, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [],
-      []>,
+    InstrItinData <tc_29175780, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bd16579e, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_29641329, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_be995eaf, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
+    InstrItinData <tc_2a160009, /*tc_2early*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_2b2f4060, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bf6fa601, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+    InstrItinData <tc_2b6f77c6, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c0cd91a8, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_2e00db30, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
 
-    InstrItinData <tc_c14739d5, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+    InstrItinData <tc_2f185f5c, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c1dbc916, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+    InstrItinData <tc_2fc0c436, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_351fed2d, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c58f771a, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3669266a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_c85212ca, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+    InstrItinData <tc_367f7f3d, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_36c68ad1, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [],
+      []>,
+
+    InstrItinData <tc_395dc00f, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 3, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c8f9a6f6, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [2],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_ca280e8b, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+    InstrItinData <tc_3cb8ea06, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_cbe45117, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [2],
+    InstrItinData <tc_3d04548d, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_3da80ba5, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_cd321066, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3e07fb90, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d108a090, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2],
+    InstrItinData <tc_41d5298e, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_4403ca65, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_44126683, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d1b5a4b6, /*tc_1*/
+    InstrItinData <tc_452f85af, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_481e5e5c, /*tc_2early*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d2609065, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_49eb22c8, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d267fa19, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [],
+    InstrItinData <tc_4ca572d4, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
       []>,
 
-    InstrItinData <tc_d2a33af5, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_4d9914c9, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d63b71d1, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_4d99bca9, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d6a805a8, /*tc_3x*/
+    InstrItinData <tc_4f7cd700, /*tc_3stall*/
       [InstrStage<1, [SLOT3]>], [2, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d95f4e98, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2, 2],
+    InstrItinData <tc_513bef45, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_51b866be, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_523fcf30, /*tc_3stall*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_da79106e, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 2],
+    InstrItinData <tc_5274e61a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_52d7bbea, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+      []>,
+
+    InstrItinData <tc_53173427, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_53bc8a6a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_dbe218dd, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [3, 2],
+    InstrItinData <tc_53bdb2f6, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_540fdfbc, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_55050d58, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_56d25411, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_dcfee7ae, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [4, 2],
+    InstrItinData <tc_57288781, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e17ce9ad, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+    InstrItinData <tc_594ab548, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e2480a7f, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
+    InstrItinData <tc_5acef64a, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5ba5997d, /*tc_2*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5eb851fc, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [2, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5f6847a1, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_60571023, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e2c08bb4, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+    InstrItinData <tc_609d2efe, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e2c31426, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+    InstrItinData <tc_60d76817, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
       []>,
 
-    InstrItinData <tc_e578178f, /*tc_ld*/
+    InstrItinData <tc_60f5738d, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_63fe3df7, /*tc_ld*/
       [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e836c161, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_66888ded, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e8c7a357, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+    InstrItinData <tc_6792d5ff, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_681a2300, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_68cb12ce, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_eb07ef6f, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [1, 2],
+    InstrItinData <tc_6aa5711a, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ecfaae86, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [1],
-      [Hex_FWD]>,
+    InstrItinData <tc_6ac37025, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ef0ebaaa, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [1, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_6ebb4a12, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ef2676fd, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [],
+    InstrItinData <tc_6efc556e, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
       []>,
 
-    InstrItinData <tc_f027ebe9, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [2],
-      [Hex_FWD]>,
+    InstrItinData <tc_73043bf4, /*tc_2early*/
+      [InstrStage<1, [SLOT3]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_746baa8e, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_74e47fd9, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f055fbb6, /*tc_3x*/
+    InstrItinData <tc_7934b9df, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [2, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f1240c08, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+    InstrItinData <tc_7a830544, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f16d5b17, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_7f881c76, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_84df2cd3, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_85523bcb, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_855b0b61, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_87735c3b, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_88fa1a78, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f1aa2cdb, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1],
+    InstrItinData <tc_897d1a9d, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f26aa619, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+    InstrItinData <tc_8b15472a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_8bb285ec, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_f4608adc, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [1, 1],
+    InstrItinData <tc_8fd5f294, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_8fe6b782, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_90f3e30c, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_faab1248, /*tc_2*/
+    InstrItinData <tc_976ddc4f, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_fcee8723, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+    InstrItinData <tc_97743097, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_999d32db, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_99be14ca, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_feb4974b, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [2, 2],
-      [Hex_FWD, Hex_FWD]>
-  ];
-}
+    InstrItinData <tc_9c00ce8d, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-class DepScalarItinV60 {
-  list<InstrItinData> DepScalarItinV60_list = [
-    InstrItinData <tc_049dfb74, /*tc_2early*/
+    InstrItinData <tc_9c98e8af, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_9d5941c7, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_9ef61e5c, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_9faf76ae, /*tc_2early*/
       [InstrStage<1, [SLOT2]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_0767081f, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+    InstrItinData <tc_9fdb5406, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a21dc435, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_07ac815d, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [2, 1],
+    InstrItinData <tc_a27582fa, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_a46f0df5, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_090485bb, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+    InstrItinData <tc_a788683e, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a8acdac0, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_09c86199, /*tc_4x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
+    InstrItinData <tc_a904d137, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_adb14c66, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b13761ae, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [],
+      []>,
+
+    InstrItinData <tc_b166348b, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_09faec3b, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 2],
+    InstrItinData <tc_b44c6e2a, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_0cb867f2, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [4, 2, 2],
+    InstrItinData <tc_b5a33b22, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1000eb10, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [2, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_b77c481f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_128719e8, /*tc_ld*/
+    InstrItinData <tc_b7dd427e, /*tc_ld*/
       [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_136c4786, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
+    InstrItinData <tc_b9488031, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_14da557c, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
+    InstrItinData <tc_b9c0b731, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b9c4623f, /*tc_2*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bad2bcaf, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bcc96cee, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bd90564c, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bde7aaf4, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_be706f30, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c2f7d806, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c5e2426d, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c6aa82f7, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c6ce9b3f, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c6ebf8dd, /*tc_3stall*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c74f796f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c82dc1ff, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_caaebcba, /*tc_3stall*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cd7374a0, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cde8b071, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cf47a43f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1b6011fb, /*tc_1*/
+    InstrItinData <tc_cf59f215, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d088982c, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d1090e34, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d24b2d85, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d580173f, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d6bf0472, /*tc_1*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1b834fe7, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+    InstrItinData <tc_d9709180, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d9f95eef, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_daa058fa, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1e062b18, /*tc_1*/
+    InstrItinData <tc_dbdffe3d, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1e69aa99, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e0739b8c, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1f9668cc, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [3, 1],
+    InstrItinData <tc_e1e0a2dc, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [],
+      []>,
+
+    InstrItinData <tc_e1e99bfa, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1fe8323c, /*tc_2*/
+    InstrItinData <tc_e216a5db, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_e421e012, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_e6b38e01, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_20a8e109, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+    InstrItinData <tc_e7624c08, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_e7d02c66, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_210b2456, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
+    InstrItinData <tc_e913dc32, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_251c87b2, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e9c822f7, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_261d9b78, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
+    InstrItinData <tc_e9fae2d6, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_ef20db1c, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_ef52ed71, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_28d296df, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
+    InstrItinData <tc_ef84f62f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_29c14515, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [4, 1],
+    InstrItinData <tc_f2704b9a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2aaab1e0, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+    InstrItinData <tc_f3eaa14b, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f47d212f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2c8fe5ae, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 2, 3],
+    InstrItinData <tc_f49e76f4, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2d1e6f5c, /*tc_4x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
+    InstrItinData <tc_f4f43fb5, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f7dd9c9f, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f86c328a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2e55aa16, /*tc_4x*/
+    InstrItinData <tc_f8eeed7a, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_fcab4871, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_ff9ee76e, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 3],
+      [Hex_FWD, Hex_FWD]>
+  ];
+}
+
+class DepScalarItinV60se {
+  list<InstrItinData> DepScalarItinV60se_list = [
+    InstrItinData <tc_0077f68c, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_00afc57e, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_00e7c26e, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_03220ffa, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_038a1342, /*tc_4x*/
       [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_30665cb0, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1],
+    InstrItinData <tc_04c9decc, /*tc_3stall*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_05b6c987, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0a2b8c7c, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0cd51c76, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0dc560de, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0fc1ae07, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_336e698c, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+    InstrItinData <tc_10b97e27, /*tc_2early*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_ST]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_128f96e3, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1372bca1, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_34e882a4, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [1],
+    InstrItinData <tc_1432937d, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_14cd4cfa, /*tc_2early*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_ST]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_35fb9d13, /*tc_2early*/
-      [InstrStage<1, [SLOT0]>], [],
-      []>,
+    InstrItinData <tc_15411484, /*tc_2early*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_ST]>], [1],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_37326008, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_16d0d8d5, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_181af5d0, /*tc_2early*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1853ea6d, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3993c58b, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 3, 2],
+    InstrItinData <tc_1b82a277, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_1b9c9ee5, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1c0005f9, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1d5a38a8, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1e856f58, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_20280784, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_234a11a5, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_238d91d2, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3b4892c6, /*tc_3x*/
+    InstrItinData <tc_29175780, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3bea1824, /*tc_4x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
+    InstrItinData <tc_29641329, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3c10f809, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+    InstrItinData <tc_2a160009, /*tc_2early*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [],
+      []>,
+
+    InstrItinData <tc_2b2f4060, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3d905451, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+    InstrItinData <tc_2b6f77c6, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_2e00db30, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_2f185f5c, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_2fc0c436, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3e61d314, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [2, 3, 2],
+    InstrItinData <tc_351fed2d, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_3669266a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_367f7f3d, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_36c68ad1, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [],
+      []>,
+
+    InstrItinData <tc_395dc00f, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 3, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3eab77bd, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
+    InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_3cb8ea06, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_3d04548d, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_3da80ba5, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_3e07fb90, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_43068634, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+    InstrItinData <tc_41d5298e, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_45631a8d, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+    InstrItinData <tc_4403ca65, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_44126683, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_452f85af, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_481e5e5c, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_47ab9233, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_49eb22c8, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_47f0b7ad, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
+    InstrItinData <tc_4ca572d4, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
+      []>,
+
+    InstrItinData <tc_4d9914c9, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_485bb57c, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+    InstrItinData <tc_4d99bca9, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_4f7cd700, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [2, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_4997da4a, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [1],
-      [Hex_FWD]>,
+    InstrItinData <tc_513bef45, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_511f28f6, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_51b866be, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_537e2013, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_523fcf30, /*tc_3stall*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5274e61a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_52d7bbea, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [],
+      []>,
+
+    InstrItinData <tc_53173427, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_53ee6546, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+    InstrItinData <tc_53bc8a6a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_548f402d, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_53bdb2f6, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5625c6c1, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_540fdfbc, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_580a779c, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 2],
+    InstrItinData <tc_55050d58, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_583510c7, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+    InstrItinData <tc_56d25411, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_57288781, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_594ab548, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5d806107, /*tc_3stall*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+    InstrItinData <tc_5acef64a, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5ba5997d, /*tc_2*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5fa2857c, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
+    InstrItinData <tc_5eb851fc, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [2, 3, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5fe9fcd0, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+    InstrItinData <tc_5f6847a1, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_6264c5e0, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_60571023, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_639d93ee, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2],
+    InstrItinData <tc_609d2efe, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_60d76817, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
+      []>,
+
+    InstrItinData <tc_60f5738d, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_63cd9d2d, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_63fe3df7, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_66888ded, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_65dc7cc4, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_6792d5ff, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_69bb508b, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_681a2300, /*tc_3stall*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_ST]>], [2],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_6c52d277, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+    InstrItinData <tc_68cb12ce, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_6c576d46, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 3],
+    InstrItinData <tc_6aa5711a, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_6ac37025, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_70cabf66, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+    InstrItinData <tc_6ebb4a12, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_6efc556e, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+      []>,
+
+    InstrItinData <tc_73043bf4, /*tc_2early*/
+      [InstrStage<1, [SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7639d4b0, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_746baa8e, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7675c0e9, /*tc_st*/
+    InstrItinData <tc_74e47fd9, /*tc_st*/
       [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_76c4c5ef, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_7934b9df, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_7a830544, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_77781686, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+    InstrItinData <tc_7f881c76, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_84df2cd3, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_85523bcb, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_855b0b61, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_87735c3b, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_78b3c689, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_88fa1a78, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7986ba30, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 3],
+    InstrItinData <tc_897d1a9d, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7bc567a7, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_8b15472a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7c2dcd4d, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+    InstrItinData <tc_8bb285ec, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_7ca2ea10, /*tc_2*/
+    InstrItinData <tc_8fd5f294, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_8fe6b782, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_90f3e30c, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_976ddc4f, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7d01cbdc, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [4, 1, 1],
+    InstrItinData <tc_97743097, /*tc_2early*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_ST]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_999d32db, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_99be14ca, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7d9a56cd, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
+    InstrItinData <tc_9c00ce8d, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_81a23d44, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_9c98e8af, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_821c4233, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_9d5941c7, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_9ef61e5c, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_82f0f122, /*tc_3x*/
+    InstrItinData <tc_9faf76ae, /*tc_2early*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_ST]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_9fdb5406, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a21dc435, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_84630363, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [2, 1],
+    InstrItinData <tc_a27582fa, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_a46f0df5, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_86442910, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [],
+    InstrItinData <tc_a788683e, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a8acdac0, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a904d137, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_adb14c66, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b13761ae, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [],
       []>,
 
-    InstrItinData <tc_87601822, /*tc_2*/
+    InstrItinData <tc_b166348b, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b44c6e2a, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_88fa2da6, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_b5a33b22, /*tc_2early*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8c8041e6, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+    InstrItinData <tc_b77c481f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8cb685d9, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
+    InstrItinData <tc_b7dd427e, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b9488031, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b9c0b731, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8def9c57, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+    InstrItinData <tc_b9c4623f, /*tc_2*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bad2bcaf, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8f0a6bad, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+    InstrItinData <tc_bcc96cee, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8fab9ac3, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_bd90564c, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_92d1833c, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2],
+    InstrItinData <tc_bde7aaf4, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_94e6ffd9, /*tc_2*/
+    InstrItinData <tc_be706f30, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c2f7d806, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_95c54f8b, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [],
-      []>,
+    InstrItinData <tc_c5e2426d, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9a13af9d, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+    InstrItinData <tc_c6aa82f7, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c6ce9b3f, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c6ebf8dd, /*tc_3stall*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c74f796f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c82dc1ff, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_9b73d261, /*tc_st*/
+    InstrItinData <tc_caaebcba, /*tc_3stall*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cd7374a0, /*tc_st*/
       [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9c18c9a5, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_cde8b071, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9c68db63, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
+    InstrItinData <tc_cf47a43f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cf59f215, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d088982c, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d1090e34, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d24b2d85, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9ce7a5ab, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_d580173f, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9da3628f, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
+    InstrItinData <tc_d6bf0472, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9dafb7d3, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
+    InstrItinData <tc_d9709180, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d9f95eef, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9df8b0dc, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
+    InstrItinData <tc_daa058fa, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_dbdffe3d, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9e86015f, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 3],
+    InstrItinData <tc_e0739b8c, /*tc_2early*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_ST]>], [2, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9f518242, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_e1e0a2dc, /*tc_3stall*/
+      [InstrStage<1, [SLOT2], 0>,
+       InstrStage<1, [CVI_ST]>], [],
+      []>,
+
+    InstrItinData <tc_e1e99bfa, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_e216a5db, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a12a5971, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e421e012, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a1fb80e1, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [2, 1],
+    InstrItinData <tc_e6b38e01, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a333d2a9, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2],
+    InstrItinData <tc_e7624c08, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [3],
       [Hex_FWD]>,
 
-    InstrItinData <tc_a4567c39, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+    InstrItinData <tc_e7d02c66, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a87879e8, /*tc_3stall*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e913dc32, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a9c993d9, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 2],
+    InstrItinData <tc_e9c822f7, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_e9fae2d6, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3], 0>,
+       InstrStage<1, [CVI_ST]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_ef20db1c, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_ef52ed71, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_ef84f62f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f2704b9a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f3eaa14b, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f47d212f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f49e76f4, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_aad55963, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+    InstrItinData <tc_f4f43fb5, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f7dd9c9f, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f86c328a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f8eeed7a, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_fcab4871, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_ST]>], [],
       []>,
 
-    InstrItinData <tc_ab1b5e74, /*tc_2*/
+    InstrItinData <tc_ff9ee76e, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 3],
+      [Hex_FWD, Hex_FWD]>
+  ];
+}
+
+class DepScalarItinV62 {
+  list<InstrItinData> DepScalarItinV62_list = [
+    InstrItinData <tc_0077f68c, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_00afc57e, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ae0722f7, /*tc_3stall*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
+    InstrItinData <tc_00e7c26e, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_03220ffa, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_038a1342, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ae2c2dc2, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
+    InstrItinData <tc_04c9decc, /*tc_3stall*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ae762521, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
+    InstrItinData <tc_05b6c987, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0a2b8c7c, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0cd51c76, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b08b653e, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [1],
+    InstrItinData <tc_0dc560de, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0fc1ae07, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_b08be45e, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_10b97e27, /*tc_3*/
+      [InstrStage<1, [SLOT2]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b0f50e3c, /*tc_2*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_128f96e3, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1372bca1, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b189ad4c, /*tc_3stall*/
+    InstrItinData <tc_1432937d, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_14cd4cfa, /*tc_2early*/
       [InstrStage<1, [SLOT2]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_b324366f, /*tc_2early*/
-      [InstrStage<1, [SLOT3]>], [1, 2],
+    InstrItinData <tc_15411484, /*tc_3*/
+      [InstrStage<1, [SLOT2]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_16d0d8d5, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_181af5d0, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [3, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b5bfaa60, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+    InstrItinData <tc_1853ea6d, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1b82a277, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_1b9c9ee5, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1c0005f9, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b5f5a094, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+    InstrItinData <tc_1d5a38a8, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b86c7e8b, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_1e856f58, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_20280784, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_baccf077, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_234a11a5, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bc5561d8, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_238d91d2, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bcf0e36e, /*tc_3stall*/
-      [InstrStage<1, [SLOT3]>], [],
-      []>,
+    InstrItinData <tc_29175780, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bd16579e, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_29641329, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_be995eaf, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
+    InstrItinData <tc_2a160009, /*tc_2early*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_2b2f4060, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bf6fa601, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+    InstrItinData <tc_2b6f77c6, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c0cd91a8, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_2e00db30, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
 
-    InstrItinData <tc_c14739d5, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+    InstrItinData <tc_2f185f5c, /*tc_3*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c1dbc916, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+    InstrItinData <tc_2fc0c436, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_351fed2d, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c58f771a, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3669266a, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_c85212ca, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+    InstrItinData <tc_367f7f3d, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_36c68ad1, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [],
+      []>,
+
+    InstrItinData <tc_395dc00f, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 3, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c8f9a6f6, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [2],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_ca280e8b, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+    InstrItinData <tc_3cb8ea06, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_cbe45117, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [2],
+    InstrItinData <tc_3d04548d, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_3da80ba5, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_cd321066, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3e07fb90, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d108a090, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2],
+    InstrItinData <tc_41d5298e, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_4403ca65, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_44126683, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d1b5a4b6, /*tc_1*/
+    InstrItinData <tc_452f85af, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_481e5e5c, /*tc_2early*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d2609065, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_49eb22c8, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d267fa19, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [],
+    InstrItinData <tc_4ca572d4, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
       []>,
 
-    InstrItinData <tc_d2a33af5, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_4d9914c9, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d63b71d1, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_4d99bca9, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d6a805a8, /*tc_3stall*/
+    InstrItinData <tc_4f7cd700, /*tc_3stall*/
       [InstrStage<1, [SLOT3]>], [2, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d95f4e98, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
+    InstrItinData <tc_513bef45, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_51b866be, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_523fcf30, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_da79106e, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 2],
+    InstrItinData <tc_5274e61a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_52d7bbea, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+      []>,
+
+    InstrItinData <tc_53173427, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_53bc8a6a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_dbe218dd, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 2],
+    InstrItinData <tc_53bdb2f6, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_540fdfbc, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_55050d58, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_56d25411, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_dcfee7ae, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 2],
+    InstrItinData <tc_57288781, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e17ce9ad, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+    InstrItinData <tc_594ab548, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e2480a7f, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
+    InstrItinData <tc_5acef64a, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5ba5997d, /*tc_2*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5eb851fc, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [2, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_5f6847a1, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_60571023, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e2c08bb4, /*tc_3stall*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+    InstrItinData <tc_609d2efe, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e2c31426, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+    InstrItinData <tc_60d76817, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
       []>,
 
-    InstrItinData <tc_e578178f, /*tc_ld*/
+    InstrItinData <tc_60f5738d, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_63fe3df7, /*tc_ld*/
       [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e836c161, /*tc_4x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_66888ded, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e8c7a357, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+    InstrItinData <tc_6792d5ff, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_681a2300, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_68cb12ce, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_eb07ef6f, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [1, 2],
+    InstrItinData <tc_6aa5711a, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ecfaae86, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [1],
-      [Hex_FWD]>,
+    InstrItinData <tc_6ac37025, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ef0ebaaa, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [1, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_6ebb4a12, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ef2676fd, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [],
+    InstrItinData <tc_6efc556e, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
       []>,
 
-    InstrItinData <tc_f027ebe9, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [2],
-      [Hex_FWD]>,
+    InstrItinData <tc_73043bf4, /*tc_2early*/
+      [InstrStage<1, [SLOT3]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_746baa8e, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_74e47fd9, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f055fbb6, /*tc_3x*/
+    InstrItinData <tc_7934b9df, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [2, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f1240c08, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_7a830544, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f16d5b17, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_7f881c76, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_84df2cd3, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_85523bcb, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_855b0b61, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_87735c3b, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_88fa1a78, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f1aa2cdb, /*tc_4x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
+    InstrItinData <tc_897d1a9d, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f26aa619, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+    InstrItinData <tc_8b15472a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_8bb285ec, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_f4608adc, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [1, 1],
+    InstrItinData <tc_8fd5f294, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_8fe6b782, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_90f3e30c, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_faab1248, /*tc_2*/
+    InstrItinData <tc_976ddc4f, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_fcee8723, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+    InstrItinData <tc_97743097, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_999d32db, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_99be14ca, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_feb4974b, /*tc_3stall*/
-      [InstrStage<1, [SLOT3]>], [2, 2],
-      [Hex_FWD, Hex_FWD]>
-  ];
-}
+    InstrItinData <tc_9c00ce8d, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-class DepScalarItinV62 {
-  list<InstrItinData> DepScalarItinV62_list = [
-    InstrItinData <tc_049dfb74, /*tc_2early*/
+    InstrItinData <tc_9c98e8af, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_9d5941c7, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_9ef61e5c, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_9faf76ae, /*tc_2early*/
       [InstrStage<1, [SLOT2]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_0767081f, /*tc_3*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+    InstrItinData <tc_9fdb5406, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a21dc435, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_07ac815d, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [2, 1],
+    InstrItinData <tc_a27582fa, /*tc_3*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_a46f0df5, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_090485bb, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+    InstrItinData <tc_a788683e, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a8acdac0, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_09c86199, /*tc_4x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
+    InstrItinData <tc_a904d137, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_adb14c66, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b13761ae, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [],
+      []>,
+
+    InstrItinData <tc_b166348b, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_09faec3b, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 2],
+    InstrItinData <tc_b44c6e2a, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_0cb867f2, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [4, 2, 2],
+    InstrItinData <tc_b5a33b22, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1000eb10, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [2, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_b77c481f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_128719e8, /*tc_ld*/
+    InstrItinData <tc_b7dd427e, /*tc_ld*/
       [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_136c4786, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
+    InstrItinData <tc_b9488031, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_14da557c, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
+    InstrItinData <tc_b9c0b731, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1b6011fb, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+    InstrItinData <tc_b9c4623f, /*tc_2*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bad2bcaf, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bcc96cee, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1b834fe7, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
+    InstrItinData <tc_bd90564c, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1e062b18, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_bde7aaf4, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1e69aa99, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_be706f30, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1f9668cc, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [3, 1],
+    InstrItinData <tc_c2f7d806, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_1fe8323c, /*tc_2*/
-      [InstrStage<1, [SLOT3]>], [4, 2],
+    InstrItinData <tc_c5e2426d, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_20a8e109, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+    InstrItinData <tc_c6aa82f7, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c6ce9b3f, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_210b2456, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
+    InstrItinData <tc_c6ebf8dd, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c74f796f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_251c87b2, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
+    InstrItinData <tc_c82dc1ff, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_caaebcba, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_261d9b78, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_cd7374a0, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_28d296df, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
+    InstrItinData <tc_cde8b071, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cf47a43f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_29c14515, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [4, 1],
+    InstrItinData <tc_cf59f215, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2aaab1e0, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_d088982c, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2c8fe5ae, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 2, 3],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_d1090e34, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d24b2d85, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2d1e6f5c, /*tc_4x*/
+    InstrItinData <tc_d580173f, /*tc_4x*/
       [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_2e55aa16, /*tc_4x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
+    InstrItinData <tc_d6bf0472, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d9709180, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d9f95eef, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_30665cb0, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1],
-      [Hex_FWD]>,
+    InstrItinData <tc_daa058fa, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_336e698c, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+    InstrItinData <tc_dbdffe3d, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_34e882a4, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [1],
-      [Hex_FWD]>,
+    InstrItinData <tc_e0739b8c, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_35fb9d13, /*tc_2early*/
-      [InstrStage<1, [SLOT0]>], [],
+    InstrItinData <tc_e1e0a2dc, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [],
       []>,
 
-    InstrItinData <tc_37326008, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e1e99bfa, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3993c58b, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 3, 2],
+    InstrItinData <tc_e216a5db, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3b4892c6, /*tc_3x*/
+    InstrItinData <tc_e421e012, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_e6b38e01, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3bea1824, /*tc_4x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e7624c08, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_3c10f809, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+    InstrItinData <tc_e7d02c66, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3d905451, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+    InstrItinData <tc_e913dc32, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_3e61d314, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [2, 3, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e9c822f7, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_3eab77bd, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_e9fae2d6, /*tc_2early*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_43068634, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_ef20db1c, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_45631a8d, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+    InstrItinData <tc_ef52ed71, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_47ab9233, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_ef84f62f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_47f0b7ad, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
+    InstrItinData <tc_f2704b9a, /*tc_2early*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_485bb57c, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+    InstrItinData <tc_f3eaa14b, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_4997da4a, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [1],
-      [Hex_FWD]>,
+    InstrItinData <tc_f47d212f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_511f28f6, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_f49e76f4, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_537e2013, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
-      [Hex_FWD, Hex_FWD]>,
-
-    InstrItinData <tc_53ee6546, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+    InstrItinData <tc_f4f43fb5, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_548f402d, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_f7dd9c9f, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5625c6c1, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
+    InstrItinData <tc_f86c328a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_580a779c, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
-    InstrItinData <tc_583510c7, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+    InstrItinData <tc_f8eeed7a, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5d806107, /*tc_3x*/
+    InstrItinData <tc_fcab4871, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_ff9ee76e, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 3],
+      [Hex_FWD, Hex_FWD]>
+  ];
+}
+
+class DepScalarItinV65 {
+  list<InstrItinData> DepScalarItinV65_list = [
+    InstrItinData <tc_0077f68c, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_00afc57e, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_00e7c26e, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_03220ffa, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_038a1342, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_04c9decc, /*tc_3stall*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5fa2857c, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
+    InstrItinData <tc_05b6c987, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_5fe9fcd0, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_0a2b8c7c, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_6264c5e0, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+    InstrItinData <tc_0cd51c76, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_0dc560de, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_639d93ee, /*tc_3*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [2],
+    InstrItinData <tc_0fc1ae07, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_63cd9d2d, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_10b97e27, /*tc_3*/
+      [InstrStage<1, [SLOT2]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_128f96e3, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_1372bca1, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_65dc7cc4, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_1432937d, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_69bb508b, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
+    InstrItinData <tc_14cd4cfa, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_15411484, /*tc_3*/
+      [InstrStage<1, [SLOT2]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_16d0d8d5, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_6c52d277, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+    InstrItinData <tc_181af5d0, /*tc_1*/
+      [InstrStage<1, [SLOT2]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_6c576d46, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 3],
+    InstrItinData <tc_1853ea6d, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_70cabf66, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_1b82a277, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_7639d4b0, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_1b9c9ee5, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7675c0e9, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_1c0005f9, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_76c4c5ef, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_1d5a38a8, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_77781686, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_1e856f58, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_78b3c689, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_20280784, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7986ba30, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 3],
+    InstrItinData <tc_234a11a5, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_238d91d2, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7bc567a7, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_29175780, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7c2dcd4d, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3],
-      [Hex_FWD]>,
+    InstrItinData <tc_29641329, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_2a160009, /*tc_2early*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
 
-    InstrItinData <tc_7ca2ea10, /*tc_2*/
+    InstrItinData <tc_2b2f4060, /*tc_2latepred*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_2b6f77c6, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_7d01cbdc, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [4, 1, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_2e00db30, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
 
-    InstrItinData <tc_7d9a56cd, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
+    InstrItinData <tc_2f185f5c, /*tc_3*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_2fc0c436, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_81a23d44, /*tc_2early*/
+    InstrItinData <tc_351fed2d, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_821c4233, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
-    InstrItinData <tc_82f0f122, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [4, 1],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3669266a, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_84630363, /*tc_3*/
-      [InstrStage<1, [SLOT2]>], [2, 1],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_367f7f3d, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
 
-    InstrItinData <tc_86442910, /*tc_ld*/
+    InstrItinData <tc_36c68ad1, /*tc_ld*/
       [InstrStage<1, [SLOT0, SLOT1]>], [],
       []>,
 
-    InstrItinData <tc_87601822, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_395dc00f, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 3, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_88fa2da6, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+    InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_3cb8ea06, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8c8041e6, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3d04548d, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8cb685d9, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_3da80ba5, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_8def9c57, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+    InstrItinData <tc_3e07fb90, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8f0a6bad, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+    InstrItinData <tc_41d5298e, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_8fab9ac3, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
+    InstrItinData <tc_4403ca65, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_92d1833c, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 2],
+    InstrItinData <tc_44126683, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_94e6ffd9, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
-      [Hex_FWD, Hex_FWD]>,
-
-    InstrItinData <tc_95c54f8b, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [],
-      []>,
-
-    InstrItinData <tc_9a13af9d, /*tc_1*/
+    InstrItinData <tc_452f85af, /*tc_1*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_9b73d261, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_481e5e5c, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9c18c9a5, /*tc_1*/
+    InstrItinData <tc_49eb22c8, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9c68db63, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_4ca572d4, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
+      []>,
+
+    InstrItinData <tc_4d9914c9, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_4d99bca9, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9ce7a5ab, /*tc_newvjump*/
+    InstrItinData <tc_4f7cd700, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_513bef45, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_51b866be, /*tc_newvjump*/
       [InstrStage<1, [SLOT0]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9da3628f, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_523fcf30, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9dafb7d3, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
+    InstrItinData <tc_5274e61a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9df8b0dc, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_52d7bbea, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+      []>,
 
-    InstrItinData <tc_9e86015f, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [2, 3],
+    InstrItinData <tc_53173427, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_9f518242, /*tc_1*/
+    InstrItinData <tc_53bc8a6a, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a12a5971, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_53bdb2f6, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a1fb80e1, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [2, 1],
+    InstrItinData <tc_540fdfbc, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_55050d58, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_56d25411, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a333d2a9, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
-      [Hex_FWD]>,
+    InstrItinData <tc_57288781, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a4567c39, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+    InstrItinData <tc_594ab548, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a87879e8, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_5acef64a, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_a9c993d9, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 2],
+    InstrItinData <tc_5ba5997d, /*tc_2*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_aad55963, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
-      []>,
+    InstrItinData <tc_5eb851fc, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [2, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ab1b5e74, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_5f6847a1, /*tc_2latepred*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ae0722f7, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1],
+    InstrItinData <tc_60571023, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ae2c2dc2, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
+    InstrItinData <tc_609d2efe, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ae762521, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_60d76817, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
+      []>,
 
-    InstrItinData <tc_b08b653e, /*tc_2early*/
-      [InstrStage<1, [SLOT2]>], [1],
+    InstrItinData <tc_60f5738d, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1],
       [Hex_FWD]>,
 
-    InstrItinData <tc_b08be45e, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
+    InstrItinData <tc_63fe3df7, /*tc_latepredldaia*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 4, 3, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_66888ded, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b0f50e3c, /*tc_2*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_6792d5ff, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b189ad4c, /*tc_3stall*/
+    InstrItinData <tc_681a2300, /*tc_3stall*/
       [InstrStage<1, [SLOT2]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_b324366f, /*tc_2early*/
-      [InstrStage<1, [SLOT3]>], [1, 2],
+    InstrItinData <tc_68cb12ce, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b5bfaa60, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
+    InstrItinData <tc_6aa5711a, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b5f5a094, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+    InstrItinData <tc_6ac37025, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_b86c7e8b, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_6ebb4a12, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_6efc556e, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+      []>,
+
+    InstrItinData <tc_73043bf4, /*tc_1*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_baccf077, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
+    InstrItinData <tc_746baa8e, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_74e47fd9, /*tc_latepredstaia*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bc5561d8, /*tc_3x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
+    InstrItinData <tc_7934b9df, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_7a830544, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_7f881c76, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_84df2cd3, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_85523bcb, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_855b0b61, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_87735c3b, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bcf0e36e, /*tc_3stall*/
-      [InstrStage<1, [SLOT3]>], [],
-      []>,
+    InstrItinData <tc_88fa1a78, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bd16579e, /*tc_2*/
+    InstrItinData <tc_897d1a9d, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_be995eaf, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
+    InstrItinData <tc_8b15472a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_bf6fa601, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+    InstrItinData <tc_8bb285ec, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_8fd5f294, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c0cd91a8, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_8fe6b782, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c14739d5, /*tc_st*/
+    InstrItinData <tc_90f3e30c, /*tc_1*/
       [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c1dbc916, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+    InstrItinData <tc_976ddc4f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_97743097, /*tc_1*/
+      [InstrStage<1, [SLOT2]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c58f771a, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_999d32db, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [1],
+      [Hex_FWD]>,
 
-    InstrItinData <tc_c85212ca, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+    InstrItinData <tc_99be14ca, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_c8f9a6f6, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
+    InstrItinData <tc_9c00ce8d, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ca280e8b, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+    InstrItinData <tc_9c98e8af, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_cbe45117, /*tc_2early*/
+    InstrItinData <tc_9d5941c7, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_9ef61e5c, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_9faf76ae, /*tc_1*/
       [InstrStage<1, [SLOT2]>], [2],
       [Hex_FWD]>,
 
-    InstrItinData <tc_cd321066, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_9fdb5406, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d108a090, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_a21dc435, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d1b5a4b6, /*tc_1*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+    InstrItinData <tc_a27582fa, /*tc_3*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [2],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_a46f0df5, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a788683e, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_a8acdac0, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d2609065, /*tc_1*/
+    InstrItinData <tc_a904d137, /*tc_1*/
       [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d267fa19, /*tc_2early*/
+    InstrItinData <tc_adb14c66, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b13761ae, /*tc_3stall*/
       [InstrStage<1, [SLOT2]>], [],
       []>,
 
-    InstrItinData <tc_d2a33af5, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_b166348b, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d63b71d1, /*tc_2early*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+    InstrItinData <tc_b44c6e2a, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d6a805a8, /*tc_3stall*/
-      [InstrStage<1, [SLOT3]>], [2, 1],
+    InstrItinData <tc_b5a33b22, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [4, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b77c481f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b7dd427e, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b9488031, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b9c0b731, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_b9c4623f, /*tc_2*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_d95f4e98, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
+    InstrItinData <tc_bad2bcaf, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_da79106e, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [1, 2, 2],
+    InstrItinData <tc_bcc96cee, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bd90564c, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_bde7aaf4, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_dbe218dd, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 2],
+    InstrItinData <tc_be706f30, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_dcfee7ae, /*tc_newvjump*/
-      [InstrStage<1, [SLOT0]>], [3, 2],
+    InstrItinData <tc_c2f7d806, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e17ce9ad, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_c5e2426d, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e2480a7f, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
-      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_c6aa82f7, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e2c08bb4, /*tc_3stall*/
+    InstrItinData <tc_c6ce9b3f, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_c6ebf8dd, /*tc_3x*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e2c31426, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
-      []>,
+    InstrItinData <tc_c74f796f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e578178f, /*tc_ld*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
+    InstrItinData <tc_c82dc1ff, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [1],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_caaebcba, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e836c161, /*tc_4x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
-      [Hex_FWD, Hex_FWD]>,
+    InstrItinData <tc_cd7374a0, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_e8c7a357, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+    InstrItinData <tc_cde8b071, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_eb07ef6f, /*tc_2early*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2],
+    InstrItinData <tc_cf47a43f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_cf59f215, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ecfaae86, /*tc_3*/
-      [InstrStage<1, [SLOT2]>], [1],
-      [Hex_FWD]>,
+    InstrItinData <tc_d088982c, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ef0ebaaa, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [1, 2],
+    InstrItinData <tc_d1090e34, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_ef2676fd, /*tc_st*/
-      [InstrStage<1, [SLOT0]>], [],
-      []>,
+    InstrItinData <tc_d24b2d85, /*tc_latepredstaia*/
+      [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f027ebe9, /*tc_ld*/
-      [InstrStage<1, [SLOT0]>], [2],
-      [Hex_FWD]>,
+    InstrItinData <tc_d580173f, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f055fbb6, /*tc_3x*/
-      [InstrStage<1, [SLOT3]>], [2, 1],
+    InstrItinData <tc_d6bf0472, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d9709180, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_d9f95eef, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_daa058fa, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f1240c08, /*tc_2*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+    InstrItinData <tc_dbdffe3d, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f16d5b17, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+    InstrItinData <tc_e0739b8c, /*tc_1*/
+      [InstrStage<1, [SLOT2]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f1aa2cdb, /*tc_4x*/
-      [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
+    InstrItinData <tc_e1e0a2dc, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [],
+      []>,
+
+    InstrItinData <tc_e1e99bfa, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_e216a5db, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_f26aa619, /*tc_1*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [3],
+    InstrItinData <tc_e421e012, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_e6b38e01, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_e7624c08, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [3],
       [Hex_FWD]>,
 
-    InstrItinData <tc_f4608adc, /*tc_3stall*/
-      [InstrStage<1, [SLOT0]>], [1, 1],
+    InstrItinData <tc_e7d02c66, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_e913dc32, /*tc_3x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_e9c822f7, /*tc_2latepred*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4],
+      [Hex_FWD]>,
+
+    InstrItinData <tc_e9fae2d6, /*tc_1*/
+      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_ef20db1c, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_ef52ed71, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_ef84f62f, /*tc_2*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f2704b9a, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
       [Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_faab1248, /*tc_2*/
+    InstrItinData <tc_f3eaa14b, /*tc_4x*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
+      [Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f47d212f, /*tc_ld*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f49e76f4, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_fcee8723, /*tc_st*/
-      [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+    InstrItinData <tc_f4f43fb5, /*tc_ld*/
+      [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
-    InstrItinData <tc_feb4974b, /*tc_3stall*/
-      [InstrStage<1, [SLOT3]>], [2, 2],
+    InstrItinData <tc_f7dd9c9f, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2, 3],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f86c328a, /*tc_st*/
+      [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_f8eeed7a, /*tc_1*/
+      [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+      [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+    InstrItinData <tc_fcab4871, /*tc_newvjump*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
+    InstrItinData <tc_ff9ee76e, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [2, 3],
       [Hex_FWD, Hex_FWD]>
   ];
 }
diff --git a/lib/Target/Hexagon/HexagonDepITypes.h b/lib/Target/Hexagon/HexagonDepITypes.h
index be831b9501ea..7e06ccede6e7 100644
--- a/lib/Target/Hexagon/HexagonDepITypes.h
+++ b/lib/Target/Hexagon/HexagonDepITypes.h
@@ -1,4 +1,4 @@
-//===--- HexagonDepITypes.h -----------------------------------------------===//
+//===- HexagonDepITypes.h -------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,6 +6,9 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
 
 namespace llvm {
 namespace HexagonII {
@@ -15,8 +18,17 @@ enum Type {
   TypeALU32_ADDI = 2,
   TypeALU64 = 3,
   TypeCJ = 4,
+  TypeCOPROC_VX = 5,
   TypeCR = 6,
+  TypeCVI_4SLOT_MPY = 7,
+  TypeCVI_GATHER = 8,
+  TypeCVI_GATHER_RST = 9,
   TypeCVI_HIST = 10,
+  TypeCVI_SCATTER = 11,
+  TypeCVI_SCATTER_DV = 12,
+  TypeCVI_SCATTER_NEW_RST = 13,
+  TypeCVI_SCATTER_NEW_ST = 14,
+  TypeCVI_SCATTER_RST = 15,
   TypeCVI_VA = 16,
   TypeCVI_VA_DV = 17,
   TypeCVI_VINLANESAT = 18,
@@ -29,6 +41,7 @@ enum Type {
   TypeCVI_VP = 25,
   TypeCVI_VP_VS = 26,
   TypeCVI_VS = 27,
+  TypeCVI_VS_VX = 28,
   TypeCVI_VX = 29,
   TypeCVI_VX_DV = 30,
   TypeCVI_VX_LATE = 31,
diff --git a/lib/Target/Hexagon/HexagonDepITypes.td b/lib/Target/Hexagon/HexagonDepITypes.td
index ac1989e4dd82..0a385bf938fe 100644
--- a/lib/Target/Hexagon/HexagonDepITypes.td
+++ b/lib/Target/Hexagon/HexagonDepITypes.td
@@ -1,4 +1,4 @@
-//===--- HexagonDepITypes.td ----------------------------------------------===//
+//===- HexagonDepITypes.td ------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,6 +6,9 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
 
 class IType<bits<6> t> { bits<6> Value = t; }
 def TypeALU32_2op : IType<0>;
@@ -13,8 +16,17 @@ def TypeALU32_3op : IType<1>;
 def TypeALU32_ADDI : IType<2>;
 def TypeALU64 : IType<3>;
 def TypeCJ : IType<4>;
+def TypeCOPROC_VX : IType<5>;
 def TypeCR : IType<6>;
+def TypeCVI_4SLOT_MPY : IType<7>;
+def TypeCVI_GATHER : IType<8>;
+def TypeCVI_GATHER_RST : IType<9>;
 def TypeCVI_HIST : IType<10>;
+def TypeCVI_SCATTER : IType<11>;
+def TypeCVI_SCATTER_DV : IType<12>;
+def TypeCVI_SCATTER_NEW_RST : IType<13>;
+def TypeCVI_SCATTER_NEW_ST : IType<14>;
+def TypeCVI_SCATTER_RST : IType<15>;
 def TypeCVI_VA : IType<16>;
 def TypeCVI_VA_DV : IType<17>;
 def TypeCVI_VINLANESAT : IType<18>;
@@ -27,6 +39,7 @@ def TypeCVI_VM_VP_LDU : IType<24>;
 def TypeCVI_VP : IType<25>;
 def TypeCVI_VP_VS : IType<26>;
 def TypeCVI_VS : IType<27>;
+def TypeCVI_VS_VX : IType<28>;
 def TypeCVI_VX : IType<29>;
 def TypeCVI_VX_DV : IType<30>;
 def TypeCVI_VX_LATE : IType<31>;
diff --git a/lib/Target/Hexagon/HexagonDepInstrFormats.td b/lib/Target/Hexagon/HexagonDepInstrFormats.td
index 1b24be477158..9f98da3a1dee 100644
--- a/lib/Target/Hexagon/HexagonDepInstrFormats.td
+++ b/lib/Target/Hexagon/HexagonDepInstrFormats.td
@@ -1,4 +1,4 @@
-//===--- HexagonDepInstrFormats.td ----------------------------------------===//
+//===- HexagonDepInstrFormats.td ------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,6 +6,9 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
 
 class Enc_890909 : OpcodeHexagon {
   bits <5> Rs32;
@@ -15,6 +18,18 @@ class Enc_890909 : OpcodeHexagon {
   bits <2> Pe4;
   let Inst{6-5} = Pe4{1-0};
 }
+class Enc_9be1de : OpcodeHexagon {
+  bits <2> Qs4;
+  let Inst{6-5} = Qs4{1-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <5> Vw32;
+  let Inst{4-0} = Vw32{4-0};
+}
 class Enc_527412 : OpcodeHexagon {
   bits <2> Ps4;
   let Inst{17-16} = Ps4{1-0};
@@ -46,14 +61,23 @@ class Enc_27b757 : OpcodeHexagon {
   bits <5> Vs32;
   let Inst{4-0} = Vs32{4-0};
 }
-class Enc_5de85f : OpcodeHexagon {
+class Enc_8d04c3 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
+class Enc_1de724 : OpcodeHexagon {
   bits <11> Ii;
   let Inst{21-20} = Ii{10-9};
   let Inst{7-1} = Ii{8-2};
-  bits <5> Rt32;
-  let Inst{12-8} = Rt32{4-0};
-  bits <3> Ns8;
-  let Inst{18-16} = Ns8{2-0};
+  bits <4> Rs16;
+  let Inst{19-16} = Rs16{3-0};
+  bits <4> n1;
+  let Inst{28-28} = n1{3-3};
+  let Inst{24-22} = n1{2-0};
 }
 class Enc_0e41fa : OpcodeHexagon {
   bits <5> Vuu32;
@@ -63,12 +87,48 @@ class Enc_0e41fa : OpcodeHexagon {
   bits <5> Vd32;
   let Inst{4-0} = Vd32{4-0};
 }
+class Enc_2a736a : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{20-16} = Vuu32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
+class Enc_3d6d37 : OpcodeHexagon {
+  bits <2> Qs4;
+  let Inst{6-5} = Qs4{1-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vvv32;
+  let Inst{12-8} = Vvv32{4-0};
+  bits <5> Vw32;
+  let Inst{4-0} = Vw32{4-0};
+}
+class Enc_a641d0 : OpcodeHexagon {
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vvv32;
+  let Inst{12-8} = Vvv32{4-0};
+  bits <5> Vw32;
+  let Inst{4-0} = Vw32{4-0};
+}
 class Enc_802dc0 : OpcodeHexagon {
   bits <1> Ii;
   let Inst{8-8} = Ii{0-0};
   bits <2> Qv4;
   let Inst{23-22} = Qv4{1-0};
 }
+class Enc_6a4549 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_6b197f : OpcodeHexagon {
   bits <4> Ii;
   let Inst{8-5} = Ii{3-0};
@@ -77,6 +137,14 @@ class Enc_6b197f : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_1f3376 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <5> Vxx32;
+  let Inst{7-3} = Vxx32{4-0};
+}
 class Enc_1f5d8f : OpcodeHexagon {
   bits <1> Mu2;
   let Inst{13-13} = Mu2{0-0};
@@ -165,6 +233,14 @@ class Enc_7eee72 : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_310ba1 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rtt32;
+  let Inst{20-16} = Rtt32{4-0};
+  bits <5> Vx32;
+  let Inst{4-0} = Vx32{4-0};
+}
 class Enc_d7dc10 : OpcodeHexagon {
   bits <5> Rs32;
   let Inst{20-16} = Rs32{4-0};
@@ -191,6 +267,14 @@ class Enc_8dec2e : OpcodeHexagon {
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
+class Enc_28dcbb : OpcodeHexagon {
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vvv32;
+  let Inst{4-0} = Vvv32{4-0};
+}
 class Enc_eaa9f8 : OpcodeHexagon {
   bits <5> Vu32;
   let Inst{12-8} = Vu32{4-0};
@@ -207,6 +291,14 @@ class Enc_509701 : OpcodeHexagon {
   bits <5> Rdd32;
   let Inst{4-0} = Rdd32{4-0};
 }
+class Enc_c84567 : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{20-16} = Vuu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
 class Enc_830e5d : OpcodeHexagon {
   bits <8> Ii;
   let Inst{12-5} = Ii{7-0};
@@ -218,6 +310,12 @@ class Enc_830e5d : OpcodeHexagon {
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
+class Enc_ae0040 : OpcodeHexagon {
+  bits <5> Rs32;
+  let Inst{20-16} = Rs32{4-0};
+  bits <6> Sd64;
+  let Inst{5-0} = Sd64{5-0};
+}
 class Enc_79b8c8 : OpcodeHexagon {
   bits <6> Ii;
   let Inst{6-3} = Ii{5-2};
@@ -238,6 +336,16 @@ class Enc_58a8bf : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_e8ddd5 : OpcodeHexagon {
+  bits <16> Ii;
+  let Inst{21-21} = Ii{15-15};
+  let Inst{13-8} = Ii{14-9};
+  let Inst{2-0} = Ii{8-6};
+  bits <5> Vss32;
+  let Inst{7-3} = Vss32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_041d7b : OpcodeHexagon {
   bits <11> Ii;
   let Inst{21-20} = Ii{10-9};
@@ -261,6 +369,14 @@ class Enc_f44229 : OpcodeHexagon {
   bits <3> Nt8;
   let Inst{10-8} = Nt8{2-0};
 }
+class Enc_fc563d : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{20-16} = Vuu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_aad80c : OpcodeHexagon {
   bits <5> Vuu32;
   let Inst{12-8} = Vuu32{4-0};
@@ -432,6 +548,13 @@ class Enc_6a5972 : OpcodeHexagon {
   bits <4> Rt16;
   let Inst{11-8} = Rt16{3-0};
 }
+class Enc_ff3442 : OpcodeHexagon {
+  bits <4> Ii;
+  let Inst{13-13} = Ii{3-3};
+  let Inst{10-8} = Ii{2-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+}
 class Enc_53dca9 : OpcodeHexagon {
   bits <6> Ii;
   let Inst{11-8} = Ii{5-2};
@@ -456,6 +579,12 @@ class Enc_93af4c : OpcodeHexagon {
   bits <4> Rx16;
   let Inst{3-0} = Rx16{3-0};
 }
+class Enc_621fba : OpcodeHexagon {
+  bits <5> Rs32;
+  let Inst{20-16} = Rs32{4-0};
+  bits <5> Gd32;
+  let Inst{4-0} = Gd32{4-0};
+}
 class Enc_5bdd42 : OpcodeHexagon {
   bits <7> Ii;
   let Inst{8-5} = Ii{6-3};
@@ -464,6 +593,14 @@ class Enc_5bdd42 : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_ad9bef : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rtt32;
+  let Inst{20-16} = Rtt32{4-0};
+  bits <5> Vxx32;
+  let Inst{4-0} = Vxx32{4-0};
+}
 class Enc_71f1b4 : OpcodeHexagon {
   bits <6> Ii;
   let Inst{8-5} = Ii{5-2};
@@ -483,6 +620,12 @@ class Enc_14640c : OpcodeHexagon {
   let Inst{24-22} = n1{3-1};
   let Inst{13-13} = n1{0-0};
 }
+class Enc_2516bf : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_31db33 : OpcodeHexagon {
   bits <2> Qt4;
   let Inst{6-5} = Qt4{1-0};
@@ -513,6 +656,24 @@ class Enc_784502 : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_9a9d62 : OpcodeHexagon {
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Rt32;
+  let Inst{12-8} = Rt32{4-0};
+  bits <5> Vs32;
+  let Inst{7-3} = Vs32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
+class Enc_3a81ac : OpcodeHexagon {
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_6413b6 : OpcodeHexagon {
   bits <11> Ii;
   let Inst{21-20} = Ii{10-9};
@@ -592,6 +753,16 @@ class Enc_e39bb2 : OpcodeHexagon {
   bits <4> Rd16;
   let Inst{3-0} = Rd16{3-0};
 }
+class Enc_7db2f8 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{13-9} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{8-4} = Vv32{4-0};
+  bits <4> Vdd16;
+  let Inst{3-0} = Vdd16{3-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_1b64fb : OpcodeHexagon {
   bits <16> Ii;
   let Inst{26-25} = Ii{15-14};
@@ -670,6 +841,10 @@ class Enc_fcf7a7 : OpcodeHexagon {
   bits <2> Pd4;
   let Inst{1-0} = Pd4{1-0};
 }
+class Enc_2c3281 : OpcodeHexagon {
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
 class Enc_55355c : OpcodeHexagon {
   bits <2> Ii;
   let Inst{13-13} = Ii{1-1};
@@ -745,6 +920,10 @@ class Enc_fef969 : OpcodeHexagon {
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
+class Enc_b2ffce : OpcodeHexagon {
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_63eaeb : OpcodeHexagon {
   bits <2> Ii;
   let Inst{1-0} = Ii{1-0};
@@ -769,6 +948,12 @@ class Enc_372c9d : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_9e9047 : OpcodeHexagon {
+  bits <2> Pt4;
+  let Inst{9-8} = Pt4{1-0};
+  bits <5> Rs32;
+  let Inst{20-16} = Rs32{4-0};
+}
 class Enc_4dff07 : OpcodeHexagon {
   bits <2> Qv4;
   let Inst{12-11} = Qv4{1-0};
@@ -815,6 +1000,16 @@ class Enc_b388cf : OpcodeHexagon {
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
+class Enc_880793 : OpcodeHexagon {
+  bits <3> Qt8;
+  let Inst{2-0} = Qt8{2-0};
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
 class Enc_ad1c74 : OpcodeHexagon {
   bits <11> Ii;
   let Inst{21-20} = Ii{10-9};
@@ -854,6 +1049,16 @@ class Enc_5e87ce : OpcodeHexagon {
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
+class Enc_158beb : OpcodeHexagon {
+  bits <2> Qs4;
+  let Inst{6-5} = Qs4{1-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vv32;
+  let Inst{4-0} = Vv32{4-0};
+}
 class Enc_f7ea77 : OpcodeHexagon {
   bits <11> Ii;
   let Inst{21-20} = Ii{10-9};
@@ -897,6 +1102,14 @@ class Enc_226535 : OpcodeHexagon {
   bits <5> Rt32;
   let Inst{4-0} = Rt32{4-0};
 }
+class Enc_96f0fd : OpcodeHexagon {
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vx32;
+  let Inst{7-3} = Vx32{4-0};
+  bits <3> Qdd8;
+  let Inst{2-0} = Qdd8{2-0};
+}
 class Enc_31aa6a : OpcodeHexagon {
   bits <5> Ii;
   let Inst{6-3} = Ii{4-1};
@@ -907,6 +1120,12 @@ class Enc_31aa6a : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_932b58 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+}
 class Enc_397f23 : OpcodeHexagon {
   bits <8> Ii;
   let Inst{13-13} = Ii{7-7};
@@ -973,6 +1192,14 @@ class Enc_01d3d0 : OpcodeHexagon {
   bits <5> Vdd32;
   let Inst{4-0} = Vdd32{4-0};
 }
+class Enc_3126d7 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
 class Enc_b0e9d8 : OpcodeHexagon {
   bits <10> Ii;
   let Inst{21-21} = Ii{9-9};
@@ -1049,6 +1276,12 @@ class Enc_88c16c : OpcodeHexagon {
   bits <5> Rxx32;
   let Inst{4-0} = Rxx32{4-0};
 }
+class Enc_e7408c : OpcodeHexagon {
+  bits <6> Sss64;
+  let Inst{21-16} = Sss64{5-0};
+  bits <5> Rdd32;
+  let Inst{4-0} = Rdd32{4-0};
+}
 class Enc_770858 : OpcodeHexagon {
   bits <2> Ps4;
   let Inst{6-5} = Ps4{1-0};
@@ -1090,6 +1323,16 @@ class Enc_412ff0 : OpcodeHexagon {
   bits <5> Rxx32;
   let Inst{12-8} = Rxx32{4-0};
 }
+class Enc_8e9fbd : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <3> Rt8;
+  let Inst{2-0} = Rt8{2-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+  bits <5> Vy32;
+  let Inst{12-8} = Vy32{4-0};
+}
 class Enc_c9a18e : OpcodeHexagon {
   bits <11> Ii;
   let Inst{21-20} = Ii{10-9};
@@ -1134,6 +1377,16 @@ class Enc_d6990d : OpcodeHexagon {
   bits <5> Vxx32;
   let Inst{4-0} = Vxx32{4-0};
 }
+class Enc_6c4697 : OpcodeHexagon {
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Rt32;
+  let Inst{12-8} = Rt32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_6c9440 : OpcodeHexagon {
   bits <10> Ii;
   let Inst{21-21} = Ii{9-9};
@@ -1278,6 +1531,12 @@ class Enc_a803e0 : OpcodeHexagon {
   bits <5> Rs32;
   let Inst{20-16} = Rs32{4-0};
 }
+class Enc_fde0e3 : OpcodeHexagon {
+  bits <5> Rtt32;
+  let Inst{20-16} = Rtt32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_45364e : OpcodeHexagon {
   bits <5> Vu32;
   let Inst{12-8} = Vu32{4-0};
@@ -1298,6 +1557,12 @@ class Enc_b909d2 : OpcodeHexagon {
   let Inst{13-13} = n1{1-1};
   let Inst{8-8} = n1{0-0};
 }
+class Enc_790d6e : OpcodeHexagon {
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_e6c957 : OpcodeHexagon {
   bits <10> Ii;
   let Inst{21-21} = Ii{9-9};
@@ -1358,6 +1623,14 @@ class Enc_0ed752 : OpcodeHexagon {
   bits <5> Cdd32;
   let Inst{4-0} = Cdd32{4-0};
 }
+class Enc_908985 : OpcodeHexagon {
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vss32;
+  let Inst{7-3} = Vss32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_143445 : OpcodeHexagon {
   bits <13> Ii;
   let Inst{26-25} = Ii{12-11};
@@ -1385,6 +1658,16 @@ class Enc_3e3989 : OpcodeHexagon {
   let Inst{25-22} = n1{4-1};
   let Inst{8-8} = n1{0-0};
 }
+class Enc_12dd8f : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <3> Rt8;
+  let Inst{2-0} = Rt8{2-0};
+  bits <5> Vx32;
+  let Inst{7-3} = Vx32{4-0};
+}
 class Enc_152467 : OpcodeHexagon {
   bits <5> Ii;
   let Inst{8-5} = Ii{4-1};
@@ -1393,6 +1676,14 @@ class Enc_152467 : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_6b1bc4 : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{20-16} = Vuu32{4-0};
+  bits <3> Qt8;
+  let Inst{10-8} = Qt8{2-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
 class Enc_daea09 : OpcodeHexagon {
   bits <17> Ii;
   let Inst{23-22} = Ii{16-15};
@@ -1421,6 +1712,32 @@ class Enc_a198f6 : OpcodeHexagon {
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
+class Enc_a265b7 : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{20-16} = Vuu32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
+class Enc_4e4a80 : OpcodeHexagon {
+  bits <2> Qs4;
+  let Inst{6-5} = Qs4{1-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vvv32;
+  let Inst{4-0} = Vvv32{4-0};
+}
+class Enc_8d5d98 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <3> Rt8;
+  let Inst{2-0} = Rt8{2-0};
+  bits <5> Vxx32;
+  let Inst{7-3} = Vxx32{4-0};
+}
 class Enc_3dac0b : OpcodeHexagon {
   bits <2> Qt4;
   let Inst{6-5} = Qt4{1-0};
@@ -1463,6 +1780,16 @@ class Enc_2df31d : OpcodeHexagon {
   bits <4> Rd16;
   let Inst{3-0} = Rd16{3-0};
 }
+class Enc_b0e553 : OpcodeHexagon {
+  bits <16> Ii;
+  let Inst{21-21} = Ii{15-15};
+  let Inst{13-8} = Ii{14-9};
+  let Inst{2-0} = Ii{8-6};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_25bef0 : OpcodeHexagon {
   bits <16> Ii;
   let Inst{26-25} = Ii{15-14};
@@ -1482,6 +1809,12 @@ class Enc_f82302 : OpcodeHexagon {
   let Inst{26-25} = n1{2-1};
   let Inst{23-23} = n1{0-0};
 }
+class Enc_44271f : OpcodeHexagon {
+  bits <5> Gs32;
+  let Inst{20-16} = Gs32{4-0};
+  bits <5> Rd32;
+  let Inst{4-0} = Rd32{4-0};
+}
 class Enc_83ee64 : OpcodeHexagon {
   bits <5> Ii;
   let Inst{12-8} = Ii{4-0};
@@ -1524,6 +1857,14 @@ class Enc_4df4e9 : OpcodeHexagon {
   bits <3> Nt8;
   let Inst{10-8} = Nt8{2-0};
 }
+class Enc_263841 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rtt32;
+  let Inst{20-16} = Rtt32{4-0};
+  bits <5> Vd32;
+  let Inst{4-0} = Vd32{4-0};
+}
 class Enc_91b9fe : OpcodeHexagon {
   bits <5> Ii;
   let Inst{6-3} = Ii{4-1};
@@ -1564,6 +1905,11 @@ class Enc_bd1cbc : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_d0fe02 : OpcodeHexagon {
+  bits <5> Rxx32;
+  let Inst{20-16} = Rxx32{4-0};
+  bits <0> sgp10;
+}
 class Enc_a30110 : OpcodeHexagon {
   bits <5> Vu32;
   let Inst{12-8} = Vu32{4-0};
@@ -1583,6 +1929,16 @@ class Enc_f3f408 : OpcodeHexagon {
   bits <5> Vd32;
   let Inst{4-0} = Vd32{4-0};
 }
+class Enc_ce4c54 : OpcodeHexagon {
+  bits <16> Ii;
+  let Inst{21-21} = Ii{15-15};
+  let Inst{13-8} = Ii{14-9};
+  let Inst{2-0} = Ii{8-6};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_690862 : OpcodeHexagon {
   bits <13> Ii;
   let Inst{26-25} = Ii{12-11};
@@ -1593,6 +1949,20 @@ class Enc_690862 : OpcodeHexagon {
   bits <3> Nt8;
   let Inst{10-8} = Nt8{2-0};
 }
+class Enc_e570b0 : OpcodeHexagon {
+  bits <5> Rtt32;
+  let Inst{20-16} = Rtt32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
+class Enc_3c46e8 : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{12-8} = Vuu32{4-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
 class Enc_2a3787 : OpcodeHexagon {
   bits <13> Ii;
   let Inst{26-25} = Ii{12-11};
@@ -1640,6 +2010,22 @@ class Enc_729ff7 : OpcodeHexagon {
   bits <5> Rdd32;
   let Inst{4-0} = Rdd32{4-0};
 }
+class Enc_5883d0 : OpcodeHexagon {
+  bits <16> Ii;
+  let Inst{21-21} = Ii{15-15};
+  let Inst{13-8} = Ii{14-9};
+  let Inst{2-0} = Ii{8-6};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
+class Enc_ff0e49 : OpcodeHexagon {
+  bits <5> Rss32;
+  let Inst{20-16} = Rss32{4-0};
+  bits <6> Sdd64;
+  let Inst{5-0} = Sdd64{5-0};
+}
 class Enc_217147 : OpcodeHexagon {
   bits <2> Qv4;
   let Inst{23-22} = Qv4{1-0};
@@ -1674,6 +2060,14 @@ class Enc_541f26 : OpcodeHexagon {
   bits <5> Rt32;
   let Inst{12-8} = Rt32{4-0};
 }
+class Enc_9aae4a : OpcodeHexagon {
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vx32;
+  let Inst{7-3} = Vx32{4-0};
+  bits <3> Qd8;
+  let Inst{2-0} = Qd8{2-0};
+}
 class Enc_724154 : OpcodeHexagon {
   bits <6> II;
   let Inst{5-0} = II{5-0};
@@ -1781,6 +2175,12 @@ class Enc_22c845 : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_ed5027 : OpcodeHexagon {
+  bits <5> Rss32;
+  let Inst{20-16} = Rss32{4-0};
+  bits <5> Gdd32;
+  let Inst{4-0} = Gdd32{4-0};
+}
 class Enc_9b0bc1 : OpcodeHexagon {
   bits <2> Pu4;
   let Inst{6-5} = Pu4{1-0};
@@ -1828,6 +2228,12 @@ class Enc_96ce4f : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_2bbae6 : OpcodeHexagon {
+  bits <6> Ss64;
+  let Inst{21-16} = Ss64{5-0};
+  bits <5> Rd32;
+  let Inst{4-0} = Rd32{4-0};
+}
 class Enc_143a3c : OpcodeHexagon {
   bits <6> Ii;
   let Inst{13-8} = Ii{5-0};
@@ -1959,6 +2365,26 @@ class Enc_b43b67 : OpcodeHexagon {
   bits <2> Qx4;
   let Inst{6-5} = Qx4{1-0};
 }
+class Enc_1cd70f : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <3> Rt8;
+  let Inst{2-0} = Rt8{2-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
+class Enc_3a527f : OpcodeHexagon {
+  bits <16> Ii;
+  let Inst{21-21} = Ii{15-15};
+  let Inst{13-8} = Ii{14-9};
+  let Inst{2-0} = Ii{8-6};
+  bits <5> Vs32;
+  let Inst{7-3} = Vs32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_4aca3a : OpcodeHexagon {
   bits <11> Ii;
   let Inst{21-20} = Ii{10-9};
@@ -1977,6 +2403,12 @@ class Enc_b38ffc : OpcodeHexagon {
   bits <4> Rt16;
   let Inst{3-0} = Rt16{3-0};
 }
+class Enc_5c3a80 : OpcodeHexagon {
+  bits <3> Qt8;
+  let Inst{10-8} = Qt8{2-0};
+  bits <3> Qd8;
+  let Inst{5-3} = Qd8{2-0};
+}
 class Enc_cda00a : OpcodeHexagon {
   bits <12> Ii;
   let Inst{19-16} = Ii{11-8};
@@ -1994,6 +2426,24 @@ class Enc_2fbf3c : OpcodeHexagon {
   bits <4> Rd16;
   let Inst{3-0} = Rd16{3-0};
 }
+class Enc_a4ae28 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <3> Qd8;
+  let Inst{5-3} = Qd8{2-0};
+}
+class Enc_dd5f9f : OpcodeHexagon {
+  bits <3> Qtt8;
+  let Inst{2-0} = Qtt8{2-0};
+  bits <5> Vuu32;
+  let Inst{20-16} = Vuu32{4-0};
+  bits <5> Vvv32;
+  let Inst{12-8} = Vvv32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
 class Enc_70b24b : OpcodeHexagon {
   bits <6> Ii;
   let Inst{8-5} = Ii{5-2};
@@ -2040,6 +2490,16 @@ class Enc_08d755 : OpcodeHexagon {
   bits <2> Pd4;
   let Inst{1-0} = Pd4{1-0};
 }
+class Enc_a7ca29 : OpcodeHexagon {
+  bits <3> Qt8;
+  let Inst{2-0} = Qt8{2-0};
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_1178da : OpcodeHexagon {
   bits <3> Ii;
   let Inst{7-5} = Ii{2-0};
@@ -2058,6 +2518,14 @@ class Enc_8dbe85 : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_17a474 : OpcodeHexagon {
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vs32;
+  let Inst{7-3} = Vs32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_5a18b3 : OpcodeHexagon {
   bits <11> Ii;
   let Inst{21-20} = Ii{10-9};
@@ -2118,6 +2586,14 @@ class Enc_12b6e9 : OpcodeHexagon {
   bits <5> Rdd32;
   let Inst{4-0} = Rdd32{4-0};
 }
+class Enc_9a895f : OpcodeHexagon {
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_6f70ca : OpcodeHexagon {
   bits <8> Ii;
   let Inst{8-4} = Ii{7-3};
@@ -2130,6 +2606,12 @@ class Enc_7222b7 : OpcodeHexagon {
 }
 class Enc_e3b0c4 : OpcodeHexagon {
 }
+class Enc_d7e8ba : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
 class Enc_a255dc : OpcodeHexagon {
   bits <3> Ii;
   let Inst{10-8} = Ii{2-0};
@@ -2138,6 +2620,24 @@ class Enc_a255dc : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_cb785b : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rtt32;
+  let Inst{20-16} = Rtt32{4-0};
+  bits <5> Vdd32;
+  let Inst{4-0} = Vdd32{4-0};
+}
+class Enc_5b76ab : OpcodeHexagon {
+  bits <10> Ii;
+  let Inst{21-21} = Ii{9-9};
+  let Inst{13-8} = Ii{8-3};
+  let Inst{2-0} = Ii{2-0};
+  bits <5> Vs32;
+  let Inst{7-3} = Vs32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_cb4b4e : OpcodeHexagon {
   bits <2> Pu4;
   let Inst{6-5} = Pu4{1-0};
@@ -2148,6 +2648,24 @@ class Enc_cb4b4e : OpcodeHexagon {
   bits <5> Rdd32;
   let Inst{4-0} = Rdd32{4-0};
 }
+class Enc_fbacc2 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <3> Rt8;
+  let Inst{2-0} = Rt8{2-0};
+  bits <5> Vxx32;
+  let Inst{7-3} = Vxx32{4-0};
+  bits <5> Vy32;
+  let Inst{12-8} = Vy32{4-0};
+}
+class Enc_2ad23d : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <5> Vx32;
+  let Inst{7-3} = Vx32{4-0};
+}
 class Enc_9cdba7 : OpcodeHexagon {
   bits <8> Ii;
   let Inst{12-5} = Ii{7-0};
@@ -2165,6 +2683,10 @@ class Enc_5cd7e9 : OpcodeHexagon {
   bits <5> Ryy32;
   let Inst{4-0} = Ryy32{4-0};
 }
+class Enc_e7c9de : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+}
 class Enc_454a26 : OpcodeHexagon {
   bits <2> Pt4;
   let Inst{9-8} = Pt4{1-0};
@@ -2193,6 +2715,16 @@ class Enc_c175d0 : OpcodeHexagon {
   bits <4> Rd16;
   let Inst{3-0} = Rd16{3-0};
 }
+class Enc_16c48b : OpcodeHexagon {
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <5> Vw32;
+  let Inst{4-0} = Vw32{4-0};
+}
 class Enc_895bd9 : OpcodeHexagon {
   bits <2> Qu4;
   let Inst{9-8} = Qu4{1-0};
@@ -2254,6 +2786,14 @@ class Enc_d2c7f1 : OpcodeHexagon {
   bits <2> Pe4;
   let Inst{6-5} = Pe4{1-0};
 }
+class Enc_dcfcbb : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vvv32;
+  let Inst{12-8} = Vvv32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_3680c2 : OpcodeHexagon {
   bits <7> Ii;
   let Inst{11-5} = Ii{6-0};
@@ -2282,6 +2822,32 @@ class Enc_e957fb : OpcodeHexagon {
   bits <5> Rt32;
   let Inst{12-8} = Rt32{4-0};
 }
+class Enc_2146c1 : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{20-16} = Vuu32{4-0};
+  bits <5> Vvv32;
+  let Inst{12-8} = Vvv32{4-0};
+  bits <3> Qss8;
+  let Inst{2-0} = Qss8{2-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
+class Enc_a662ae : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{20-16} = Vuu32{4-0};
+  bits <5> Vvv32;
+  let Inst{12-8} = Vvv32{4-0};
+  bits <3> Rt8;
+  let Inst{2-0} = Rt8{2-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
+class Enc_8f7cc3 : OpcodeHexagon {
+  bits <3> Qtt8;
+  let Inst{10-8} = Qtt8{2-0};
+  bits <3> Qdd8;
+  let Inst{5-3} = Qdd8{2-0};
+}
 class Enc_c9e3bc : OpcodeHexagon {
   bits <4> Ii;
   let Inst{13-13} = Ii{3-3};
@@ -2314,6 +2880,40 @@ class Enc_0b2e5b : OpcodeHexagon {
   bits <5> Vd32;
   let Inst{4-0} = Vd32{4-0};
 }
+class Enc_6f83e7 : OpcodeHexagon {
+  bits <2> Qv4;
+  let Inst{23-22} = Qv4{1-0};
+  bits <5> Vd32;
+  let Inst{4-0} = Vd32{4-0};
+}
+class Enc_46f33d : OpcodeHexagon {
+  bits <5> Rss32;
+  let Inst{20-16} = Rss32{4-0};
+  bits <5> Rt32;
+  let Inst{12-8} = Rt32{4-0};
+}
+class Enc_c1652e : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <3> Qd8;
+  let Inst{5-3} = Qd8{2-0};
+}
+class Enc_b5b643 : OpcodeHexagon {
+  bits <5> Rtt32;
+  let Inst{20-16} = Rtt32{4-0};
+  bits <5> Vx32;
+  let Inst{7-3} = Vx32{4-0};
+}
+class Enc_85daf5 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rtt32;
+  let Inst{20-16} = Rtt32{4-0};
+  bits <5> Vx32;
+  let Inst{7-3} = Vx32{4-0};
+}
 class Enc_d483b9 : OpcodeHexagon {
   bits <1> Ii;
   let Inst{5-5} = Ii{0-0};
@@ -2346,6 +2946,26 @@ class Enc_70fb07 : OpcodeHexagon {
   bits <5> Rxx32;
   let Inst{4-0} = Rxx32{4-0};
 }
+class Enc_6c9ee0 : OpcodeHexagon {
+  bits <3> Ii;
+  let Inst{10-8} = Ii{2-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
+class Enc_72a92d : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{12-8} = Vuu32{4-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vxx32;
+  let Inst{7-3} = Vxx32{4-0};
+}
+class Enc_44661f : OpcodeHexagon {
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_277737 : OpcodeHexagon {
   bits <8> Ii;
   let Inst{22-21} = Ii{7-6};
@@ -2496,6 +3116,14 @@ class Enc_8e583a : OpcodeHexagon {
   let Inst{25-23} = n1{3-1};
   let Inst{13-13} = n1{0-0};
 }
+class Enc_334c2b : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{12-8} = Vuu32{4-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_b886fd : OpcodeHexagon {
   bits <5> Ii;
   let Inst{6-3} = Ii{4-1};
@@ -2549,12 +3177,36 @@ class Enc_8dbdfe : OpcodeHexagon {
   bits <3> Nt8;
   let Inst{10-8} = Nt8{2-0};
 }
+class Enc_7dc746 : OpcodeHexagon {
+  bits <3> Quu8;
+  let Inst{10-8} = Quu8{2-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <3> Qdd8;
+  let Inst{5-3} = Qdd8{2-0};
+}
 class Enc_90cd8b : OpcodeHexagon {
   bits <5> Rss32;
   let Inst{20-16} = Rss32{4-0};
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
+class Enc_b8513b : OpcodeHexagon {
+  bits <5> Vuu32;
+  let Inst{20-16} = Vuu32{4-0};
+  bits <5> Vvv32;
+  let Inst{12-8} = Vvv32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
+class Enc_b3bac4 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rtt32;
+  let Inst{20-16} = Rtt32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+}
 class Enc_bd0b33 : OpcodeHexagon {
   bits <10> Ii;
   let Inst{21-21} = Ii{9-9};
@@ -2564,6 +3216,24 @@ class Enc_bd0b33 : OpcodeHexagon {
   bits <2> Pd4;
   let Inst{1-0} = Pd4{1-0};
 }
+class Enc_843e80 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vd32;
+  let Inst{7-3} = Vd32{4-0};
+  bits <3> Qxx8;
+  let Inst{2-0} = Qxx8{2-0};
+}
+class Enc_8b8927 : OpcodeHexagon {
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <1> Mu2;
+  let Inst{13-13} = Mu2{0-0};
+  bits <5> Vv32;
+  let Inst{4-0} = Vv32{4-0};
+}
 class Enc_c7cd90 : OpcodeHexagon {
   bits <4> Ii;
   let Inst{6-3} = Ii{3-0};
@@ -2711,15 +3381,24 @@ class Enc_1a9974 : OpcodeHexagon {
   bits <5> Rtt32;
   let Inst{4-0} = Rtt32{4-0};
 }
-class Enc_1de724 : OpcodeHexagon {
+class Enc_9ce456 : OpcodeHexagon {
+  bits <10> Ii;
+  let Inst{21-21} = Ii{9-9};
+  let Inst{13-8} = Ii{8-3};
+  let Inst{2-0} = Ii{2-0};
+  bits <5> Vss32;
+  let Inst{7-3} = Vss32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
+class Enc_5de85f : OpcodeHexagon {
   bits <11> Ii;
   let Inst{21-20} = Ii{10-9};
   let Inst{7-1} = Ii{8-2};
-  bits <4> Rs16;
-  let Inst{19-16} = Rs16{3-0};
-  bits <4> n1;
-  let Inst{28-28} = n1{3-3};
-  let Inst{24-22} = n1{2-0};
+  bits <5> Rt32;
+  let Inst{12-8} = Rt32{4-0};
+  bits <3> Ns8;
+  let Inst{18-16} = Ns8{2-0};
 }
 class Enc_dd766a : OpcodeHexagon {
   bits <5> Vu32;
@@ -2737,6 +3416,14 @@ class Enc_0b51ce : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_b5e54d : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rs32;
+  let Inst{20-16} = Rs32{4-0};
+  bits <5> Rdd32;
+  let Inst{4-0} = Rdd32{4-0};
+}
 class Enc_b4e6cf : OpcodeHexagon {
   bits <10> Ii;
   let Inst{21-21} = Ii{9-9};
@@ -2755,6 +3442,12 @@ class Enc_44215c : OpcodeHexagon {
   bits <3> Nt8;
   let Inst{10-8} = Nt8{2-0};
 }
+class Enc_0aa344 : OpcodeHexagon {
+  bits <5> Gss32;
+  let Inst{20-16} = Gss32{4-0};
+  bits <5> Rdd32;
+  let Inst{4-0} = Rdd32{4-0};
+}
 class Enc_a21d47 : OpcodeHexagon {
   bits <6> Ii;
   let Inst{10-5} = Ii{5-0};
@@ -2786,6 +3479,16 @@ class Enc_645d54 : OpcodeHexagon {
   bits <5> Rdd32;
   let Inst{4-0} = Rdd32{4-0};
 }
+class Enc_b5d5a7 : OpcodeHexagon {
+  bits <16> Ii;
+  let Inst{21-21} = Ii{15-15};
+  let Inst{13-8} = Ii{14-9};
+  let Inst{2-0} = Ii{8-6};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vs32;
+  let Inst{7-3} = Vs32{4-0};
+}
 class Enc_667b39 : OpcodeHexagon {
   bits <5> Css32;
   let Inst{20-16} = Css32{4-0};
@@ -2843,6 +3546,16 @@ class Enc_b8c967 : OpcodeHexagon {
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
+class Enc_f106e0 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{8-4} = Vv32{4-0};
+  bits <5> Vt32;
+  let Inst{13-9} = Vt32{4-0};
+  bits <4> Vdd16;
+  let Inst{3-0} = Vdd16{3-0};
+}
 class Enc_fb6577 : OpcodeHexagon {
   bits <2> Pu4;
   let Inst{9-8} = Pu4{1-0};
@@ -2851,6 +3564,20 @@ class Enc_fb6577 : OpcodeHexagon {
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
+class Enc_37c406 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vv32;
+  let Inst{12-8} = Vv32{4-0};
+  bits <3> Rt8;
+  let Inst{2-0} = Rt8{2-0};
+  bits <4> Vdd16;
+  let Inst{7-4} = Vdd16{3-0};
+}
+class Enc_403871 : OpcodeHexagon {
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_2bae10 : OpcodeHexagon {
   bits <4> Ii;
   let Inst{10-8} = Ii{3-1};
@@ -2859,6 +3586,22 @@ class Enc_2bae10 : OpcodeHexagon {
   bits <4> Rd16;
   let Inst{3-0} = Rd16{3-0};
 }
+class Enc_f3adb6 : OpcodeHexagon {
+  bits <16> Ii;
+  let Inst{21-21} = Ii{15-15};
+  let Inst{13-8} = Ii{14-9};
+  let Inst{2-0} = Ii{8-6};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
+class Enc_aac08c : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <5> Vx32;
+  let Inst{7-3} = Vx32{4-0};
+}
 class Enc_c4dc92 : OpcodeHexagon {
   bits <2> Qv4;
   let Inst{23-22} = Qv4{1-0};
@@ -3000,6 +3743,13 @@ class Enc_134437 : OpcodeHexagon {
   bits <2> Qd4;
   let Inst{1-0} = Qd4{1-0};
 }
+class Enc_33f8ba : OpcodeHexagon {
+  bits <8> Ii;
+  let Inst{12-8} = Ii{7-3};
+  let Inst{4-2} = Ii{2-0};
+  bits <5> Rx32;
+  let Inst{20-16} = Rx32{4-0};
+}
 class Enc_97d666 : OpcodeHexagon {
   bits <4> Rs16;
   let Inst{7-4} = Rs16{3-0};
@@ -3016,6 +3766,16 @@ class Enc_f82eaf : OpcodeHexagon {
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
+class Enc_57e245 : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <3> Rt8;
+  let Inst{2-0} = Rt8{2-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+  bits <5> Vy32;
+  let Inst{12-8} = Vy32{4-0};
+}
 class Enc_69d63b : OpcodeHexagon {
   bits <11> Ii;
   let Inst{21-20} = Ii{10-9};
@@ -3082,6 +3842,24 @@ class Enc_7eaeb6 : OpcodeHexagon {
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_274a4c : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{20-16} = Vu32{4-0};
+  bits <3> Rt8;
+  let Inst{2-0} = Rt8{2-0};
+  bits <5> Vx32;
+  let Inst{7-3} = Vx32{4-0};
+  bits <5> Vy32;
+  let Inst{12-8} = Vy32{4-0};
+}
+class Enc_aceeef : OpcodeHexagon {
+  bits <5> Vu32;
+  let Inst{12-8} = Vu32{4-0};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
 class Enc_f55a0c : OpcodeHexagon {
   bits <6> Ii;
   let Inst{11-8} = Ii{5-2};
@@ -3120,6 +3898,16 @@ class Enc_7b523d : OpcodeHexagon {
   bits <5> Vxx32;
   let Inst{4-0} = Vxx32{4-0};
 }
+class Enc_c39a8b : OpcodeHexagon {
+  bits <16> Ii;
+  let Inst{21-21} = Ii{15-15};
+  let Inst{13-8} = Ii{14-9};
+  let Inst{2-0} = Ii{8-6};
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vss32;
+  let Inst{7-3} = Vss32{4-0};
+}
 class Enc_47ef61 : OpcodeHexagon {
   bits <3> Ii;
   let Inst{7-5} = Ii{2-0};
@@ -3229,6 +4017,16 @@ class Enc_eca7c8 : OpcodeHexagon {
   bits <5> Rt32;
   let Inst{4-0} = Rt32{4-0};
 }
+class Enc_598f6c : OpcodeHexagon {
+  bits <5> Rtt32;
+  let Inst{12-8} = Rtt32{4-0};
+}
+class Enc_41dcc3 : OpcodeHexagon {
+  bits <5> Rt32;
+  let Inst{20-16} = Rt32{4-0};
+  bits <5> Vdd32;
+  let Inst{7-3} = Vdd32{4-0};
+}
 class Enc_4b39e4 : OpcodeHexagon {
   bits <3> Ii;
   let Inst{7-5} = Ii{2-0};
diff --git a/lib/Target/Hexagon/HexagonDepInstrInfo.td b/lib/Target/Hexagon/HexagonDepInstrInfo.td
index 30ebf89c9808..6e16762ac0eb 100644
--- a/lib/Target/Hexagon/HexagonDepInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonDepInstrInfo.td
@@ -1,4 +1,4 @@
-//===--- HexagonDepInstrInfo.td -------------------------------------------===//
+//===- HexagonDepInstrInfo.td ---------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,12 +6,15 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
 
 def A2_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = abs($Rs32)",
-tc_94e6ffd9, TypeS_2op>, Enc_5e2823 {
+tc_c2f7d806, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10001100100;
 let hasNewValue = 1;
@@ -22,7 +25,7 @@ def A2_absp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = abs($Rss32)",
-tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb {
+tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10000000100;
 let prefersSlot3 = 1;
@@ -31,7 +34,7 @@ def A2_abssat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = abs($Rs32):sat",
-tc_94e6ffd9, TypeS_2op>, Enc_5e2823 {
+tc_c2f7d806, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000101;
 let Inst{31-21} = 0b10001100100;
 let hasNewValue = 1;
@@ -43,7 +46,7 @@ def A2_add : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = add($Rs32,$Rt32)",
-tc_548f402d, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
+tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110011000;
@@ -59,7 +62,7 @@ def A2_addh_h16_hh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.h,$Rs32.h):<<16",
-tc_bd16579e, TypeALU64>, Enc_bd6011 {
+tc_897d1a9d, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101010;
@@ -71,7 +74,7 @@ def A2_addh_h16_hl : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.h,$Rs32.l):<<16",
-tc_bd16579e, TypeALU64>, Enc_bd6011 {
+tc_897d1a9d, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101010;
@@ -83,7 +86,7 @@ def A2_addh_h16_lh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.l,$Rs32.h):<<16",
-tc_bd16579e, TypeALU64>, Enc_bd6011 {
+tc_897d1a9d, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101010;
@@ -95,7 +98,7 @@ def A2_addh_h16_ll : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.l,$Rs32.l):<<16",
-tc_bd16579e, TypeALU64>, Enc_bd6011 {
+tc_897d1a9d, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101010;
@@ -107,7 +110,7 @@ def A2_addh_h16_sat_hh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101010;
@@ -120,7 +123,7 @@ def A2_addh_h16_sat_hl : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101010;
@@ -133,7 +136,7 @@ def A2_addh_h16_sat_lh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101010;
@@ -146,7 +149,7 @@ def A2_addh_h16_sat_ll : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101010;
@@ -159,7 +162,7 @@ def A2_addh_l16_hl : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.l,$Rs32.h)",
-tc_7ca2ea10, TypeALU64>, Enc_bd6011 {
+tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101000;
@@ -171,7 +174,7 @@ def A2_addh_l16_ll : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.l,$Rs32.l)",
-tc_7ca2ea10, TypeALU64>, Enc_bd6011 {
+tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101000;
@@ -183,7 +186,7 @@ def A2_addh_l16_sat_hl : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.l,$Rs32.h):sat",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101000;
@@ -196,7 +199,7 @@ def A2_addh_l16_sat_ll : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = add($Rt32.l,$Rs32.l):sat",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101000;
@@ -209,7 +212,7 @@ def A2_addi : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rd32 = add($Rs32,#$Ii)",
-tc_548f402d, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel {
+tc_b9488031, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel {
 let Inst{31-28} = 0b1011;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -228,7 +231,7 @@ def A2_addp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = add($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011000;
@@ -239,7 +242,7 @@ def A2_addpsat : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = add($Rss32,$Rtt32):sat",
-tc_47ab9233, TypeALU64>, Enc_a56825 {
+tc_b44c6e2a, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011011;
@@ -251,7 +254,7 @@ def A2_addsat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = add($Rs32,$Rt32):sat",
-tc_b0f50e3c, TypeALU32_3op>, Enc_5ab2be {
+tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110110010;
@@ -266,14 +269,14 @@ def A2_addsp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "$Rdd32 = add($Rs32,$Rtt32)",
-tc_bd16579e, TypeALU64> {
+tc_897d1a9d, TypeALU64> {
 let isPseudo = 1;
 }
 def A2_addsph : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = add($Rss32,$Rtt32):raw:hi",
-tc_bd16579e, TypeALU64>, Enc_a56825 {
+tc_897d1a9d, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011011;
@@ -283,7 +286,7 @@ def A2_addspl : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = add($Rss32,$Rtt32):raw:lo",
-tc_bd16579e, TypeALU64>, Enc_a56825 {
+tc_897d1a9d, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011011;
@@ -293,7 +296,7 @@ def A2_and : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = and($Rs32,$Rt32)",
-tc_548f402d, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
+tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110001000;
@@ -309,7 +312,7 @@ def A2_andir : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rd32 = and($Rs32,#$Ii)",
-tc_548f402d, TypeALU32_2op>, Enc_140c83, ImmRegRel {
+tc_b9488031, TypeALU32_2op>, Enc_140c83, ImmRegRel {
 let Inst{31-22} = 0b0111011000;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -325,7 +328,7 @@ def A2_andp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = and($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011111;
@@ -335,7 +338,7 @@ def A2_aslh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = aslh($Rs32)",
-tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel {
+tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b01110000000;
 let hasNewValue = 1;
@@ -347,7 +350,7 @@ def A2_asrh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = asrh($Rs32)",
-tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel {
+tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b01110000001;
 let hasNewValue = 1;
@@ -359,7 +362,7 @@ def A2_combine_hh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = combine($Rt32.h,$Rs32.h)",
-tc_548f402d, TypeALU32_3op>, Enc_bd6011 {
+tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110011100;
@@ -371,7 +374,7 @@ def A2_combine_hl : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = combine($Rt32.h,$Rs32.l)",
-tc_548f402d, TypeALU32_3op>, Enc_bd6011 {
+tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110011101;
@@ -383,7 +386,7 @@ def A2_combine_lh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = combine($Rt32.l,$Rs32.h)",
-tc_548f402d, TypeALU32_3op>, Enc_bd6011 {
+tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110011110;
@@ -395,7 +398,7 @@ def A2_combine_ll : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = combine($Rt32.l,$Rs32.l)",
-tc_548f402d, TypeALU32_3op>, Enc_bd6011 {
+tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110011111;
@@ -407,7 +410,7 @@ def A2_combineii : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins s32_0Imm:$Ii, s8_0Imm:$II),
 "$Rdd32 = combine(#$Ii,#$II)",
-tc_548f402d, TypeALU32_2op>, Enc_18c338 {
+tc_b9488031, TypeALU32_2op>, Enc_18c338 {
 let Inst{31-23} = 0b011111000;
 let isReMaterializable = 1;
 let isAsCheapAsAMove = 1;
@@ -422,7 +425,7 @@ def A2_combinew : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = combine($Rs32,$Rt32)",
-tc_548f402d, TypeALU32_3op>, Enc_be32a5, PredNewRel {
+tc_b9488031, TypeALU32_3op>, Enc_be32a5, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110101000;
@@ -434,7 +437,7 @@ def A2_max : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = max($Rs32,$Rt32)",
-tc_47ab9233, TypeALU64>, Enc_5ab2be {
+tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101110;
@@ -446,7 +449,7 @@ def A2_maxp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = max($Rss32,$Rtt32)",
-tc_47ab9233, TypeALU64>, Enc_a56825 {
+tc_b44c6e2a, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011110;
@@ -456,7 +459,7 @@ def A2_maxu : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = maxu($Rs32,$Rt32)",
-tc_47ab9233, TypeALU64>, Enc_5ab2be {
+tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101110;
@@ -468,7 +471,7 @@ def A2_maxup : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = maxu($Rss32,$Rtt32)",
-tc_47ab9233, TypeALU64>, Enc_a56825 {
+tc_b44c6e2a, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011110;
@@ -478,7 +481,7 @@ def A2_min : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = min($Rt32,$Rs32)",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101101;
@@ -490,7 +493,7 @@ def A2_minp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = min($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011101;
@@ -500,7 +503,7 @@ def A2_minu : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = minu($Rt32,$Rs32)",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101101;
@@ -512,7 +515,7 @@ def A2_minup : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = minu($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011101;
@@ -522,7 +525,7 @@ def A2_neg : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = neg($Rs32)",
-tc_f16d5b17, TypeALU32_2op> {
+tc_68cb12ce, TypeALU32_2op> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -532,7 +535,7 @@ def A2_negp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = neg($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb {
+tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000101;
 let Inst{31-21} = 0b10000000100;
 }
@@ -540,7 +543,7 @@ def A2_negsat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = neg($Rs32):sat",
-tc_94e6ffd9, TypeS_2op>, Enc_5e2823 {
+tc_c2f7d806, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10001100100;
 let hasNewValue = 1;
@@ -552,7 +555,7 @@ def A2_nop : HInst<
 (outs),
 (ins),
 "nop",
-tc_e2c31426, TypeALU32_2op>, Enc_e3b0c4 {
+tc_6efc556e, TypeALU32_2op>, Enc_e3b0c4 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-16} = 0b0111111100000000;
 }
@@ -560,7 +563,7 @@ def A2_not : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = not($Rs32)",
-tc_f16d5b17, TypeALU32_2op> {
+tc_68cb12ce, TypeALU32_2op> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -570,7 +573,7 @@ def A2_notp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = not($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb {
+tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10000000100;
 }
@@ -578,7 +581,7 @@ def A2_or : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = or($Rs32,$Rt32)",
-tc_548f402d, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
+tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110001001;
@@ -594,7 +597,7 @@ def A2_orir : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rd32 = or($Rs32,#$Ii)",
-tc_548f402d, TypeALU32_2op>, Enc_140c83, ImmRegRel {
+tc_b9488031, TypeALU32_2op>, Enc_140c83, ImmRegRel {
 let Inst{31-22} = 0b0111011010;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -610,7 +613,7 @@ def A2_orp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = or($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011111;
@@ -620,7 +623,7 @@ def A2_paddf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pu4) $Rd32 = add($Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111011000;
@@ -636,7 +639,7 @@ def A2_paddfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)",
-tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111011000;
@@ -653,7 +656,7 @@ def A2_paddif : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
 "if (!$Pu4) $Rd32 = add($Rs32,#$Ii)",
-tc_1b6011fb, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
+tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
 let Inst{13-13} = 0b0;
 let Inst{31-23} = 0b011101001;
 let isPredicated = 1;
@@ -673,7 +676,7 @@ def A2_paddifnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
 "if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)",
-tc_28d296df, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
+tc_2b2f4060, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
 let Inst{13-13} = 0b1;
 let Inst{31-23} = 0b011101001;
 let isPredicated = 1;
@@ -694,7 +697,7 @@ def A2_paddit : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
 "if ($Pu4) $Rd32 = add($Rs32,#$Ii)",
-tc_1b6011fb, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
+tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
 let Inst{13-13} = 0b0;
 let Inst{31-23} = 0b011101000;
 let isPredicated = 1;
@@ -713,7 +716,7 @@ def A2_padditnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
 "if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)",
-tc_28d296df, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
+tc_2b2f4060, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
 let Inst{13-13} = 0b1;
 let Inst{31-23} = 0b011101000;
 let isPredicated = 1;
@@ -733,7 +736,7 @@ def A2_paddt : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pu4) $Rd32 = add($Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111011000;
@@ -748,7 +751,7 @@ def A2_paddtnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)",
-tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111011000;
@@ -764,7 +767,7 @@ def A2_pandf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pu4) $Rd32 = and($Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111001000;
@@ -778,7 +781,7 @@ def A2_pandfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)",
-tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111001000;
@@ -793,7 +796,7 @@ def A2_pandt : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pu4) $Rd32 = and($Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111001000;
@@ -806,7 +809,7 @@ def A2_pandtnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)",
-tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111001000;
@@ -820,7 +823,7 @@ def A2_porf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pu4) $Rd32 = or($Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111001001;
@@ -834,7 +837,7 @@ def A2_porfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)",
-tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111001001;
@@ -849,7 +852,7 @@ def A2_port : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pu4) $Rd32 = or($Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111001001;
@@ -862,7 +865,7 @@ def A2_portnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)",
-tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111001001;
@@ -876,7 +879,7 @@ def A2_psubf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
 "if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111011001;
@@ -890,7 +893,7 @@ def A2_psubfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
 "if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
-tc_28d296df, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111011001;
@@ -905,7 +908,7 @@ def A2_psubt : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
 "if ($Pu4) $Rd32 = sub($Rt32,$Rs32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111011001;
@@ -918,7 +921,7 @@ def A2_psubtnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
 "if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
-tc_28d296df, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111011001;
@@ -932,7 +935,7 @@ def A2_pxorf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111001011;
@@ -946,7 +949,7 @@ def A2_pxorfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
-tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111001011;
@@ -961,7 +964,7 @@ def A2_pxort : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pu4) $Rd32 = xor($Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111001011;
@@ -974,7 +977,7 @@ def A2_pxortnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
-tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111001011;
@@ -988,7 +991,7 @@ def A2_roundsat : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = round($Rss32):sat",
-tc_94e6ffd9, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
+tc_c2f7d806, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10001000110;
 let hasNewValue = 1;
@@ -1000,7 +1003,7 @@ def A2_sat : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = sat($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_90cd8b {
+tc_cde8b071, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001000110;
 let hasNewValue = 1;
@@ -1011,7 +1014,7 @@ def A2_satb : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = satb($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_5e2823 {
+tc_cde8b071, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000111;
 let Inst{31-21} = 0b10001100110;
 let hasNewValue = 1;
@@ -1022,7 +1025,7 @@ def A2_sath : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = sath($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_5e2823 {
+tc_cde8b071, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10001100110;
 let hasNewValue = 1;
@@ -1033,7 +1036,7 @@ def A2_satub : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = satub($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_5e2823 {
+tc_cde8b071, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10001100110;
 let hasNewValue = 1;
@@ -1044,7 +1047,7 @@ def A2_satuh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = satuh($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_5e2823 {
+tc_cde8b071, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000101;
 let Inst{31-21} = 0b10001100110;
 let hasNewValue = 1;
@@ -1055,7 +1058,7 @@ def A2_sub : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32,$Rs32)",
-tc_548f402d, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel {
+tc_b9488031, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110011001;
@@ -1070,7 +1073,7 @@ def A2_subh_h16_hh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.h,$Rs32.h):<<16",
-tc_bd16579e, TypeALU64>, Enc_bd6011 {
+tc_897d1a9d, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101011;
@@ -1082,7 +1085,7 @@ def A2_subh_h16_hl : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.h,$Rs32.l):<<16",
-tc_bd16579e, TypeALU64>, Enc_bd6011 {
+tc_897d1a9d, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101011;
@@ -1094,7 +1097,7 @@ def A2_subh_h16_lh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.l,$Rs32.h):<<16",
-tc_bd16579e, TypeALU64>, Enc_bd6011 {
+tc_897d1a9d, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101011;
@@ -1106,7 +1109,7 @@ def A2_subh_h16_ll : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.l,$Rs32.l):<<16",
-tc_bd16579e, TypeALU64>, Enc_bd6011 {
+tc_897d1a9d, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101011;
@@ -1118,7 +1121,7 @@ def A2_subh_h16_sat_hh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101011;
@@ -1131,7 +1134,7 @@ def A2_subh_h16_sat_hl : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101011;
@@ -1144,7 +1147,7 @@ def A2_subh_h16_sat_lh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101011;
@@ -1157,7 +1160,7 @@ def A2_subh_h16_sat_ll : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101011;
@@ -1170,7 +1173,7 @@ def A2_subh_l16_hl : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.l,$Rs32.h)",
-tc_7ca2ea10, TypeALU64>, Enc_bd6011 {
+tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101001;
@@ -1182,7 +1185,7 @@ def A2_subh_l16_ll : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.l,$Rs32.l)",
-tc_7ca2ea10, TypeALU64>, Enc_bd6011 {
+tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101001;
@@ -1194,7 +1197,7 @@ def A2_subh_l16_sat_hl : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.l,$Rs32.h):sat",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101001;
@@ -1207,7 +1210,7 @@ def A2_subh_l16_sat_ll : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32.l,$Rs32.l):sat",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101001;
@@ -1220,7 +1223,7 @@ def A2_subp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = sub($Rtt32,$Rss32)",
-tc_9c18c9a5, TypeALU64>, Enc_ea23e4 {
+tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011001;
@@ -1229,7 +1232,7 @@ def A2_subri : HInst<
 (outs IntRegs:$Rd32),
 (ins s32_0Imm:$Ii, IntRegs:$Rs32),
 "$Rd32 = sub(#$Ii,$Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel {
+tc_b9488031, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel {
 let Inst{31-22} = 0b0111011001;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -1245,7 +1248,7 @@ def A2_subsat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32,$Rs32):sat",
-tc_b0f50e3c, TypeALU32_3op>, Enc_bd6011 {
+tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110110110;
@@ -1259,7 +1262,7 @@ def A2_svaddh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = vaddh($Rs32,$Rt32)",
-tc_548f402d, TypeALU32_3op>, Enc_5ab2be {
+tc_b9488031, TypeALU32_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110110000;
@@ -1272,7 +1275,7 @@ def A2_svaddhs : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = vaddh($Rs32,$Rt32):sat",
-tc_b0f50e3c, TypeALU32_3op>, Enc_5ab2be {
+tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110110001;
@@ -1287,7 +1290,7 @@ def A2_svadduhs : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = vadduh($Rs32,$Rt32):sat",
-tc_b0f50e3c, TypeALU32_3op>, Enc_5ab2be {
+tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110110011;
@@ -1302,13 +1305,12 @@ def A2_svavgh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = vavgh($Rs32,$Rt32)",
-tc_511f28f6, TypeALU32_3op>, Enc_5ab2be {
+tc_b9488031, TypeALU32_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110111000;
 let hasNewValue = 1;
 let opNewValue = 0;
-let prefersSlot3 = 1;
 let InputType = "reg";
 let isCommutable = 1;
 }
@@ -1316,13 +1318,12 @@ def A2_svavghs : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = vavgh($Rs32,$Rt32):rnd",
-tc_76c4c5ef, TypeALU32_3op>, Enc_5ab2be {
+tc_8fe6b782, TypeALU32_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110111001;
 let hasNewValue = 1;
 let opNewValue = 0;
-let prefersSlot3 = 1;
 let InputType = "reg";
 let isCommutable = 1;
 }
@@ -1330,20 +1331,19 @@ def A2_svnavgh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = vnavgh($Rt32,$Rs32)",
-tc_511f28f6, TypeALU32_3op>, Enc_bd6011 {
+tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110111011;
 let hasNewValue = 1;
 let opNewValue = 0;
-let prefersSlot3 = 1;
 let InputType = "reg";
 }
 def A2_svsubh : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = vsubh($Rt32,$Rs32)",
-tc_548f402d, TypeALU32_3op>, Enc_bd6011 {
+tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110110100;
@@ -1355,7 +1355,7 @@ def A2_svsubhs : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = vsubh($Rt32,$Rs32):sat",
-tc_b0f50e3c, TypeALU32_3op>, Enc_bd6011 {
+tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110110101;
@@ -1369,7 +1369,7 @@ def A2_svsubuhs : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = vsubuh($Rt32,$Rs32):sat",
-tc_b0f50e3c, TypeALU32_3op>, Enc_bd6011 {
+tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110110111;
@@ -1383,7 +1383,7 @@ def A2_swiz : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = swiz($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_5e2823 {
+tc_cde8b071, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000111;
 let Inst{31-21} = 0b10001100100;
 let hasNewValue = 1;
@@ -1393,7 +1393,7 @@ def A2_sxtb : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = sxtb($Rs32)",
-tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel {
+tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b01110000101;
 let hasNewValue = 1;
@@ -1405,7 +1405,7 @@ def A2_sxth : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = sxth($Rs32)",
-tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel {
+tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b01110000111;
 let hasNewValue = 1;
@@ -1417,7 +1417,7 @@ def A2_sxtw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = sxtw($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 {
+tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10000100010;
 }
@@ -1425,7 +1425,7 @@ def A2_tfr : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = $Rs32",
-tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel {
+tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b01110000011;
 let hasNewValue = 1;
@@ -1438,7 +1438,7 @@ def A2_tfrcrr : HInst<
 (outs IntRegs:$Rd32),
 (ins CtrRegs:$Cs32),
 "$Rd32 = $Cs32",
-tc_3b4892c6, TypeCR>, Enc_0cb018 {
+tc_29175780, TypeCR>, Enc_0cb018 {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b01101010000;
 let hasNewValue = 1;
@@ -1448,7 +1448,7 @@ def A2_tfrf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) $Rd32 = $Rs32",
-tc_1b6011fb, TypeALU32_2op>, PredNewRel, ImmRegRel {
+tc_d6bf0472, TypeALU32_2op>, PredNewRel, ImmRegRel {
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let hasNewValue = 1;
@@ -1463,7 +1463,7 @@ def A2_tfrfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4.new) $Rd32 = $Rs32",
-tc_28d296df, TypeALU32_2op>, PredNewRel, ImmRegRel {
+tc_2b2f4060, TypeALU32_2op>, PredNewRel, ImmRegRel {
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let hasNewValue = 1;
@@ -1479,7 +1479,7 @@ def A2_tfrih : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, u16_0Imm:$Ii),
 "$Rx32.h = #$Ii",
-tc_548f402d, TypeALU32_2op>, Enc_51436c {
+tc_b9488031, TypeALU32_2op>, Enc_51436c {
 let Inst{21-21} = 0b1;
 let Inst{31-24} = 0b01110010;
 let hasNewValue = 1;
@@ -1490,7 +1490,7 @@ def A2_tfril : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, u16_0Imm:$Ii),
 "$Rx32.l = #$Ii",
-tc_548f402d, TypeALU32_2op>, Enc_51436c {
+tc_b9488031, TypeALU32_2op>, Enc_51436c {
 let Inst{21-21} = 0b1;
 let Inst{31-24} = 0b01110001;
 let hasNewValue = 1;
@@ -1501,7 +1501,7 @@ def A2_tfrp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = $Rss32",
-tc_548f402d, TypeALU32_2op>, PredNewRel {
+tc_b9488031, TypeALU32_2op>, PredNewRel {
 let BaseOpcode = "A2_tfrp";
 let isPredicable = 1;
 let isPseudo = 1;
@@ -1510,7 +1510,7 @@ def A2_tfrpf : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
 "if (!$Pu4) $Rdd32 = $Rss32",
-tc_548f402d, TypeALU32_2op>, PredNewRel {
+tc_b9488031, TypeALU32_2op>, PredNewRel {
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let BaseOpcode = "A2_tfrp";
@@ -1520,7 +1520,7 @@ def A2_tfrpfnew : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
 "if (!$Pu4.new) $Rdd32 = $Rss32",
-tc_b08be45e, TypeALU32_2op>, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, PredNewRel {
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isPredicatedNew = 1;
@@ -1531,7 +1531,7 @@ def A2_tfrpi : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins s8_0Imm:$Ii),
 "$Rdd32 = #$Ii",
-tc_548f402d, TypeALU64> {
+tc_b9488031, TypeALU64> {
 let isReMaterializable = 1;
 let isAsCheapAsAMove = 1;
 let isMoveImm = 1;
@@ -1541,7 +1541,7 @@ def A2_tfrpt : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
 "if ($Pu4) $Rdd32 = $Rss32",
-tc_548f402d, TypeALU32_2op>, PredNewRel {
+tc_b9488031, TypeALU32_2op>, PredNewRel {
 let isPredicated = 1;
 let BaseOpcode = "A2_tfrp";
 let isPseudo = 1;
@@ -1550,7 +1550,7 @@ def A2_tfrptnew : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
 "if ($Pu4.new) $Rdd32 = $Rss32",
-tc_b08be45e, TypeALU32_2op>, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, PredNewRel {
 let isPredicated = 1;
 let isPredicatedNew = 1;
 let BaseOpcode = "A2_tfrp";
@@ -1560,7 +1560,7 @@ def A2_tfrrcr : HInst<
 (outs CtrRegs:$Cd32),
 (ins IntRegs:$Rs32),
 "$Cd32 = $Rs32",
-tc_82f0f122, TypeCR>, Enc_bd811a {
+tc_a21dc435, TypeCR>, Enc_bd811a {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b01100010001;
 let hasNewValue = 1;
@@ -1570,7 +1570,7 @@ def A2_tfrsi : HInst<
 (outs IntRegs:$Rd32),
 (ins s32_0Imm:$Ii),
 "$Rd32 = #$Ii",
-tc_f16d5b17, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel {
+tc_68cb12ce, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel {
 let Inst{21-21} = 0b0;
 let Inst{31-24} = 0b01111000;
 let hasNewValue = 1;
@@ -1592,7 +1592,7 @@ def A2_tfrt : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) $Rd32 = $Rs32",
-tc_1b6011fb, TypeALU32_2op>, PredNewRel, ImmRegRel {
+tc_d6bf0472, TypeALU32_2op>, PredNewRel, ImmRegRel {
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -1606,7 +1606,7 @@ def A2_tfrtnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4.new) $Rd32 = $Rs32",
-tc_28d296df, TypeALU32_2op>, PredNewRel, ImmRegRel {
+tc_2b2f4060, TypeALU32_2op>, PredNewRel, ImmRegRel {
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -1621,7 +1621,7 @@ def A2_vabsh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = vabsh($Rss32)",
-tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb {
+tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10000000010;
 let prefersSlot3 = 1;
@@ -1630,7 +1630,7 @@ def A2_vabshsat : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = vabsh($Rss32):sat",
-tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb {
+tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000101;
 let Inst{31-21} = 0b10000000010;
 let prefersSlot3 = 1;
@@ -1640,7 +1640,7 @@ def A2_vabsw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = vabsw($Rss32)",
-tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb {
+tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10000000010;
 let prefersSlot3 = 1;
@@ -1649,7 +1649,7 @@ def A2_vabswsat : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = vabsw($Rss32):sat",
-tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb {
+tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000111;
 let Inst{31-21} = 0b10000000010;
 let prefersSlot3 = 1;
@@ -1659,7 +1659,7 @@ def A2_vaddb_map : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vaddb($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeMAPPING> {
+tc_540fdfbc, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -1667,7 +1667,7 @@ def A2_vaddh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vaddh($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011000;
@@ -1676,7 +1676,7 @@ def A2_vaddhs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vaddh($Rss32,$Rtt32):sat",
-tc_47ab9233, TypeALU64>, Enc_a56825 {
+tc_b44c6e2a, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011000;
@@ -1687,7 +1687,7 @@ def A2_vaddub : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vaddub($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011000;
@@ -1696,7 +1696,7 @@ def A2_vaddubs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vaddub($Rss32,$Rtt32):sat",
-tc_47ab9233, TypeALU64>, Enc_a56825 {
+tc_b44c6e2a, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011000;
@@ -1707,7 +1707,7 @@ def A2_vadduhs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vadduh($Rss32,$Rtt32):sat",
-tc_47ab9233, TypeALU64>, Enc_a56825 {
+tc_b44c6e2a, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011000;
@@ -1718,7 +1718,7 @@ def A2_vaddw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vaddw($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011000;
@@ -1727,7 +1727,7 @@ def A2_vaddws : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vaddw($Rss32,$Rtt32):sat",
-tc_47ab9233, TypeALU64>, Enc_a56825 {
+tc_b44c6e2a, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011000;
@@ -1738,17 +1738,16 @@ def A2_vavgh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavgh($Rss32,$Rtt32)",
-tc_cd321066, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011010;
-let prefersSlot3 = 1;
 }
 def A2_vavghcr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavgh($Rss32,$Rtt32):crnd",
-tc_63cd9d2d, TypeALU64>, Enc_a56825 {
+tc_2b6f77c6, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011010;
@@ -1758,87 +1757,79 @@ def A2_vavghr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavgh($Rss32,$Rtt32):rnd",
-tc_37326008, TypeALU64>, Enc_a56825 {
+tc_dbdffe3d, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011010;
-let prefersSlot3 = 1;
 }
 def A2_vavgub : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavgub($Rss32,$Rtt32)",
-tc_cd321066, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011010;
-let prefersSlot3 = 1;
 }
 def A2_vavgubr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavgub($Rss32,$Rtt32):rnd",
-tc_37326008, TypeALU64>, Enc_a56825 {
+tc_dbdffe3d, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011010;
-let prefersSlot3 = 1;
 }
 def A2_vavguh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavguh($Rss32,$Rtt32)",
-tc_cd321066, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011010;
-let prefersSlot3 = 1;
 }
 def A2_vavguhr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavguh($Rss32,$Rtt32):rnd",
-tc_37326008, TypeALU64>, Enc_a56825 {
+tc_dbdffe3d, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011010;
-let prefersSlot3 = 1;
 }
 def A2_vavguw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavguw($Rss32,$Rtt32)",
-tc_cd321066, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011011;
-let prefersSlot3 = 1;
 }
 def A2_vavguwr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavguw($Rss32,$Rtt32):rnd",
-tc_37326008, TypeALU64>, Enc_a56825 {
+tc_dbdffe3d, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011011;
-let prefersSlot3 = 1;
 }
 def A2_vavgw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavgw($Rss32,$Rtt32)",
-tc_cd321066, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011011;
-let prefersSlot3 = 1;
 }
 def A2_vavgwcr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavgw($Rss32,$Rtt32):crnd",
-tc_63cd9d2d, TypeALU64>, Enc_a56825 {
+tc_2b6f77c6, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011011;
@@ -1848,17 +1839,16 @@ def A2_vavgwr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vavgw($Rss32,$Rtt32):rnd",
-tc_37326008, TypeALU64>, Enc_a56825 {
+tc_dbdffe3d, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011011;
-let prefersSlot3 = 1;
 }
 def A2_vcmpbeq : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = vcmpb.eq($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b110000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010000;
@@ -1867,7 +1857,7 @@ def A2_vcmpbgtu : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = vcmpb.gtu($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b111000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010000;
@@ -1876,7 +1866,7 @@ def A2_vcmpheq : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = vcmph.eq($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b011000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010000;
@@ -1885,7 +1875,7 @@ def A2_vcmphgt : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = vcmph.gt($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b100000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010000;
@@ -1894,7 +1884,7 @@ def A2_vcmphgtu : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = vcmph.gtu($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b101000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010000;
@@ -1903,7 +1893,7 @@ def A2_vcmpweq : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = vcmpw.eq($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010000;
@@ -1912,7 +1902,7 @@ def A2_vcmpwgt : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = vcmpw.gt($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b001000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010000;
@@ -1921,7 +1911,7 @@ def A2_vcmpwgtu : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = vcmpw.gtu($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b010000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010000;
@@ -1930,7 +1920,7 @@ def A2_vconj : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = vconj($Rss32):sat",
-tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb {
+tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000111;
 let Inst{31-21} = 0b10000000100;
 let prefersSlot3 = 1;
@@ -1940,7 +1930,7 @@ def A2_vmaxb : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vmaxb($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011110;
@@ -1950,7 +1940,7 @@ def A2_vmaxh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vmaxh($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011110;
@@ -1960,7 +1950,7 @@ def A2_vmaxub : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vmaxub($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011110;
@@ -1970,7 +1960,7 @@ def A2_vmaxuh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vmaxuh($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011110;
@@ -1980,7 +1970,7 @@ def A2_vmaxuw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vmaxuw($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011101;
@@ -1990,7 +1980,7 @@ def A2_vmaxw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vmaxw($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011110;
@@ -2000,7 +1990,7 @@ def A2_vminb : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vminb($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011110;
@@ -2010,7 +2000,7 @@ def A2_vminh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vminh($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011101;
@@ -2020,7 +2010,7 @@ def A2_vminub : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vminub($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011101;
@@ -2030,7 +2020,7 @@ def A2_vminuh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vminuh($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011101;
@@ -2040,7 +2030,7 @@ def A2_vminuw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vminuw($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011101;
@@ -2050,7 +2040,7 @@ def A2_vminw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vminw($Rtt32,$Rss32)",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011101;
@@ -2060,17 +2050,16 @@ def A2_vnavgh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vnavgh($Rtt32,$Rss32)",
-tc_cd321066, TypeALU64>, Enc_ea23e4 {
+tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011100;
-let prefersSlot3 = 1;
 }
 def A2_vnavghcr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat",
-tc_63cd9d2d, TypeALU64>, Enc_ea23e4 {
+tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011100;
@@ -2081,7 +2070,7 @@ def A2_vnavghr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat",
-tc_63cd9d2d, TypeALU64>, Enc_ea23e4 {
+tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011100;
@@ -2092,17 +2081,16 @@ def A2_vnavgw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vnavgw($Rtt32,$Rss32)",
-tc_cd321066, TypeALU64>, Enc_ea23e4 {
+tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011100;
-let prefersSlot3 = 1;
 }
 def A2_vnavgwcr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat",
-tc_63cd9d2d, TypeALU64>, Enc_ea23e4 {
+tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011100;
@@ -2113,7 +2101,7 @@ def A2_vnavgwr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat",
-tc_63cd9d2d, TypeALU64>, Enc_ea23e4 {
+tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011100;
@@ -2124,7 +2112,7 @@ def A2_vraddub : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vraddub($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000010;
@@ -2134,7 +2122,7 @@ def A2_vraddub_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vraddub($Rss32,$Rtt32)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010010;
@@ -2145,7 +2133,7 @@ def A2_vrsadub : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrsadub($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000010;
@@ -2155,7 +2143,7 @@ def A2_vrsadub_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrsadub($Rss32,$Rtt32)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010010;
@@ -2166,7 +2154,7 @@ def A2_vsubb_map : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vsubb($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeMAPPING> {
+tc_540fdfbc, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -2174,7 +2162,7 @@ def A2_vsubh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vsubh($Rtt32,$Rss32)",
-tc_9c18c9a5, TypeALU64>, Enc_ea23e4 {
+tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011001;
@@ -2183,7 +2171,7 @@ def A2_vsubhs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vsubh($Rtt32,$Rss32):sat",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011001;
@@ -2194,7 +2182,7 @@ def A2_vsubub : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vsubub($Rtt32,$Rss32)",
-tc_9c18c9a5, TypeALU64>, Enc_ea23e4 {
+tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011001;
@@ -2203,7 +2191,7 @@ def A2_vsububs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vsubub($Rtt32,$Rss32):sat",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011001;
@@ -2214,7 +2202,7 @@ def A2_vsubuhs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vsubuh($Rtt32,$Rss32):sat",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011001;
@@ -2225,7 +2213,7 @@ def A2_vsubw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vsubw($Rtt32,$Rss32)",
-tc_9c18c9a5, TypeALU64>, Enc_ea23e4 {
+tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011001;
@@ -2234,7 +2222,7 @@ def A2_vsubws : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vsubw($Rtt32,$Rss32):sat",
-tc_47ab9233, TypeALU64>, Enc_ea23e4 {
+tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011001;
@@ -2245,7 +2233,7 @@ def A2_xor : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = xor($Rs32,$Rt32)",
-tc_548f402d, TypeALU32_3op>, Enc_5ab2be, PredNewRel {
+tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110001011;
@@ -2260,7 +2248,7 @@ def A2_xorp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = xor($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeALU64>, Enc_a56825 {
+tc_540fdfbc, TypeALU64>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011111;
@@ -2270,7 +2258,7 @@ def A2_zxtb : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = zxtb($Rs32)",
-tc_548f402d, TypeALU32_2op>, PredNewRel {
+tc_b9488031, TypeALU32_2op>, PredNewRel {
 let hasNewValue = 1;
 let opNewValue = 0;
 let BaseOpcode = "A2_zxtb";
@@ -2282,7 +2270,7 @@ def A2_zxth : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = zxth($Rs32)",
-tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel {
+tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b01110000110;
 let hasNewValue = 1;
@@ -2294,7 +2282,7 @@ def A4_addp_c : HInst<
 (outs DoubleRegs:$Rdd32, PredRegs:$Px4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
 "$Rdd32 = add($Rss32,$Rtt32,$Px4):carry",
-tc_a87879e8, TypeS_3op>, Enc_2b3f60 {
+tc_523fcf30, TypeS_3op>, Enc_2b3f60 {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000010110;
@@ -2305,7 +2293,7 @@ def A4_andn : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = and($Rt32,~$Rs32)",
-tc_548f402d, TypeALU32_3op>, Enc_bd6011 {
+tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110001100;
@@ -2317,7 +2305,7 @@ def A4_andnp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = and($Rtt32,~$Rss32)",
-tc_9c18c9a5, TypeALU64>, Enc_ea23e4 {
+tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011111;
@@ -2326,7 +2314,7 @@ def A4_bitsplit : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = bitsplit($Rs32,$Rt32)",
-tc_7ca2ea10, TypeALU64>, Enc_be32a5 {
+tc_1b9c9ee5, TypeALU64>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010100001;
@@ -2336,7 +2324,7 @@ def A4_bitspliti : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rdd32 = bitsplit($Rs32,#$Ii)",
-tc_7ca2ea10, TypeS_2op>, Enc_311abd {
+tc_1b9c9ee5, TypeS_2op>, Enc_311abd {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001000110;
@@ -2346,14 +2334,14 @@ def A4_boundscheck : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "$Pd4 = boundscheck($Rs32,$Rtt32)",
-tc_c58f771a, TypeALU64> {
+tc_1e856f58, TypeALU64> {
 let isPseudo = 1;
 }
 def A4_boundscheck_hi : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b101000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11010010000;
@@ -2362,7 +2350,7 @@ def A4_boundscheck_lo : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b100000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11010010000;
@@ -2371,7 +2359,7 @@ def A4_cmpbeq : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmpb.eq($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b110000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111110;
@@ -2384,7 +2372,7 @@ def A4_cmpbeqi : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u8_0Imm:$Ii),
 "$Pd4 = cmpb.eq($Rs32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_08d755, ImmRegRel {
+tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
 let Inst{4-2} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11011101000;
@@ -2397,7 +2385,7 @@ def A4_cmpbgt : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmpb.gt($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b010000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111110;
@@ -2409,7 +2397,7 @@ def A4_cmpbgti : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, s8_0Imm:$Ii),
 "$Pd4 = cmpb.gt($Rs32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_08d755, ImmRegRel {
+tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
 let Inst{4-2} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11011101001;
@@ -2421,7 +2409,7 @@ def A4_cmpbgtu : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmpb.gtu($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b111000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111110;
@@ -2433,7 +2421,7 @@ def A4_cmpbgtui : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
 "$Pd4 = cmpb.gtu($Rs32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_02553a, ImmRegRel {
+tc_7a830544, TypeALU64>, Enc_02553a, ImmRegRel {
 let Inst{4-2} = 0b000;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b11011101010;
@@ -2450,7 +2438,7 @@ def A4_cmpheq : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmph.eq($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b011000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111110;
@@ -2463,7 +2451,7 @@ def A4_cmpheqi : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Pd4 = cmph.eq($Rs32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_08d755, ImmRegRel {
+tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
 let Inst{4-2} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11011101000;
@@ -2481,7 +2469,7 @@ def A4_cmphgt : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmph.gt($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b100000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111110;
@@ -2493,7 +2481,7 @@ def A4_cmphgti : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Pd4 = cmph.gt($Rs32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_08d755, ImmRegRel {
+tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
 let Inst{4-2} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11011101001;
@@ -2510,7 +2498,7 @@ def A4_cmphgtu : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmph.gtu($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b101000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111110;
@@ -2522,7 +2510,7 @@ def A4_cmphgtui : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
 "$Pd4 = cmph.gtu($Rs32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_02553a, ImmRegRel {
+tc_7a830544, TypeALU64>, Enc_02553a, ImmRegRel {
 let Inst{4-2} = 0b010;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b11011101010;
@@ -2539,7 +2527,7 @@ def A4_combineii : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins s8_0Imm:$Ii, u32_0Imm:$II),
 "$Rdd32 = combine(#$Ii,#$II)",
-tc_548f402d, TypeALU32_2op>, Enc_f0cca7 {
+tc_b9488031, TypeALU32_2op>, Enc_f0cca7 {
 let Inst{31-21} = 0b01111100100;
 let isExtendable = 1;
 let opExtendable = 2;
@@ -2551,7 +2539,7 @@ def A4_combineir : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins s32_0Imm:$Ii, IntRegs:$Rs32),
 "$Rdd32 = combine(#$Ii,$Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_9cdba7 {
+tc_b9488031, TypeALU32_2op>, Enc_9cdba7 {
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b01110011001;
 let isExtendable = 1;
@@ -2564,7 +2552,7 @@ def A4_combineri : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rdd32 = combine($Rs32,#$Ii)",
-tc_548f402d, TypeALU32_2op>, Enc_9cdba7 {
+tc_b9488031, TypeALU32_2op>, Enc_9cdba7 {
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b01110011000;
 let isExtendable = 1;
@@ -2577,7 +2565,7 @@ def A4_cround_ri : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = cround($Rs32,#$Ii)",
-tc_63cd9d2d, TypeS_2op>, Enc_a05677 {
+tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100111;
@@ -2589,7 +2577,7 @@ def A4_cround_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = cround($Rs32,$Rt32)",
-tc_63cd9d2d, TypeS_3op>, Enc_5ab2be {
+tc_2b6f77c6, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110110;
@@ -2601,14 +2589,14 @@ def A4_ext : HInst<
 (outs),
 (ins u26_6Imm:$Ii),
 "immext(#$Ii)",
-tc_9a13af9d, TypeEXTENDER>, Enc_2b518f {
+tc_452f85af, TypeEXTENDER>, Enc_2b518f {
 let Inst{31-28} = 0b0000;
 }
 def A4_modwrapu : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = modwrap($Rs32,$Rt32)",
-tc_47ab9233, TypeALU64>, Enc_5ab2be {
+tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011111;
@@ -2620,7 +2608,7 @@ def A4_orn : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = or($Rt32,~$Rs32)",
-tc_548f402d, TypeALU32_3op>, Enc_bd6011 {
+tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110001101;
@@ -2632,7 +2620,7 @@ def A4_ornp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = or($Rtt32,~$Rss32)",
-tc_9c18c9a5, TypeALU64>, Enc_ea23e4 {
+tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010011111;
@@ -2641,7 +2629,7 @@ def A4_paslhf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) $Rd32 = aslh($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1010;
 let Inst{31-21} = 0b01110000000;
@@ -2655,7 +2643,7 @@ def A4_paslhfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4.new) $Rd32 = aslh($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1011;
 let Inst{31-21} = 0b01110000000;
@@ -2670,7 +2658,7 @@ def A4_paslht : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) $Rd32 = aslh($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1000;
 let Inst{31-21} = 0b01110000000;
@@ -2683,7 +2671,7 @@ def A4_paslhtnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4.new) $Rd32 = aslh($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1001;
 let Inst{31-21} = 0b01110000000;
@@ -2697,7 +2685,7 @@ def A4_pasrhf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) $Rd32 = asrh($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1010;
 let Inst{31-21} = 0b01110000001;
@@ -2711,7 +2699,7 @@ def A4_pasrhfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4.new) $Rd32 = asrh($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1011;
 let Inst{31-21} = 0b01110000001;
@@ -2726,7 +2714,7 @@ def A4_pasrht : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) $Rd32 = asrh($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1000;
 let Inst{31-21} = 0b01110000001;
@@ -2739,7 +2727,7 @@ def A4_pasrhtnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4.new) $Rd32 = asrh($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1001;
 let Inst{31-21} = 0b01110000001;
@@ -2753,7 +2741,7 @@ def A4_psxtbf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) $Rd32 = sxtb($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1010;
 let Inst{31-21} = 0b01110000101;
@@ -2767,7 +2755,7 @@ def A4_psxtbfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4.new) $Rd32 = sxtb($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1011;
 let Inst{31-21} = 0b01110000101;
@@ -2782,7 +2770,7 @@ def A4_psxtbt : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) $Rd32 = sxtb($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1000;
 let Inst{31-21} = 0b01110000101;
@@ -2795,7 +2783,7 @@ def A4_psxtbtnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4.new) $Rd32 = sxtb($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1001;
 let Inst{31-21} = 0b01110000101;
@@ -2809,7 +2797,7 @@ def A4_psxthf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) $Rd32 = sxth($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1010;
 let Inst{31-21} = 0b01110000111;
@@ -2823,7 +2811,7 @@ def A4_psxthfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4.new) $Rd32 = sxth($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1011;
 let Inst{31-21} = 0b01110000111;
@@ -2838,7 +2826,7 @@ def A4_psxtht : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) $Rd32 = sxth($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1000;
 let Inst{31-21} = 0b01110000111;
@@ -2851,7 +2839,7 @@ def A4_psxthtnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4.new) $Rd32 = sxth($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1001;
 let Inst{31-21} = 0b01110000111;
@@ -2865,7 +2853,7 @@ def A4_pzxtbf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) $Rd32 = zxtb($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1010;
 let Inst{31-21} = 0b01110000100;
@@ -2879,7 +2867,7 @@ def A4_pzxtbfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4.new) $Rd32 = zxtb($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1011;
 let Inst{31-21} = 0b01110000100;
@@ -2894,7 +2882,7 @@ def A4_pzxtbt : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) $Rd32 = zxtb($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1000;
 let Inst{31-21} = 0b01110000100;
@@ -2907,7 +2895,7 @@ def A4_pzxtbtnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4.new) $Rd32 = zxtb($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1001;
 let Inst{31-21} = 0b01110000100;
@@ -2921,7 +2909,7 @@ def A4_pzxthf : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) $Rd32 = zxth($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1010;
 let Inst{31-21} = 0b01110000110;
@@ -2935,7 +2923,7 @@ def A4_pzxthfnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4.new) $Rd32 = zxth($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1011;
 let Inst{31-21} = 0b01110000110;
@@ -2950,7 +2938,7 @@ def A4_pzxtht : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) $Rd32 = zxth($Rs32)",
-tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1000;
 let Inst{31-21} = 0b01110000110;
@@ -2963,7 +2951,7 @@ def A4_pzxthtnew : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4.new) $Rd32 = zxth($Rs32)",
-tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1001;
 let Inst{31-21} = 0b01110000110;
@@ -2977,7 +2965,7 @@ def A4_rcmpeq : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = cmp.eq($Rs32,$Rt32)",
-tc_548f402d, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
+tc_b9488031, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110011010;
@@ -2991,7 +2979,7 @@ def A4_rcmpeqi : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rd32 = cmp.eq($Rs32,#$Ii)",
-tc_548f402d, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
+tc_b9488031, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b01110011010;
 let hasNewValue = 1;
@@ -3008,7 +2996,7 @@ def A4_rcmpneq : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = !cmp.eq($Rs32,$Rt32)",
-tc_548f402d, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
+tc_b9488031, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110011011;
@@ -3022,7 +3010,7 @@ def A4_rcmpneqi : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rd32 = !cmp.eq($Rs32,#$Ii)",
-tc_548f402d, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
+tc_b9488031, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b01110011011;
 let hasNewValue = 1;
@@ -3039,7 +3027,7 @@ def A4_round_ri : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = round($Rs32,#$Ii)",
-tc_63cd9d2d, TypeS_2op>, Enc_a05677 {
+tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100111;
@@ -3051,7 +3039,7 @@ def A4_round_ri_sat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = round($Rs32,#$Ii):sat",
-tc_63cd9d2d, TypeS_2op>, Enc_a05677 {
+tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100111;
@@ -3064,7 +3052,7 @@ def A4_round_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = round($Rs32,$Rt32)",
-tc_63cd9d2d, TypeS_3op>, Enc_5ab2be {
+tc_2b6f77c6, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110110;
@@ -3076,7 +3064,7 @@ def A4_round_rr_sat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = round($Rs32,$Rt32):sat",
-tc_63cd9d2d, TypeS_3op>, Enc_5ab2be {
+tc_2b6f77c6, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110110;
@@ -3089,7 +3077,7 @@ def A4_subp_c : HInst<
 (outs DoubleRegs:$Rdd32, PredRegs:$Px4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
 "$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry",
-tc_a87879e8, TypeS_3op>, Enc_2b3f60 {
+tc_523fcf30, TypeS_3op>, Enc_2b3f60 {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000010111;
@@ -3100,7 +3088,7 @@ def A4_tfrcpp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins CtrRegs64:$Css32),
 "$Rdd32 = $Css32",
-tc_3b4892c6, TypeCR>, Enc_667b39 {
+tc_29175780, TypeCR>, Enc_667b39 {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b01101000000;
 }
@@ -3108,7 +3096,7 @@ def A4_tfrpcp : HInst<
 (outs CtrRegs64:$Cdd32),
 (ins DoubleRegs:$Rss32),
 "$Cdd32 = $Rss32",
-tc_82f0f122, TypeCR>, Enc_0ed752 {
+tc_a21dc435, TypeCR>, Enc_0ed752 {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b01100011001;
 }
@@ -3116,7 +3104,7 @@ def A4_tlbmatch : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Pd4 = tlbmatch($Rss32,$Rt32)",
-tc_e2c08bb4, TypeALU64>, Enc_03833b {
+tc_04c9decc, TypeALU64>, Enc_03833b {
 let Inst{7-2} = 0b011000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11010010000;
@@ -3126,7 +3114,7 @@ def A4_vcmpbeq_any : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11010010000;
@@ -3135,7 +3123,7 @@ def A4_vcmpbeqi : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, u8_0Imm:$Ii),
 "$Pd4 = vcmpb.eq($Rss32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_0d8adb {
+tc_7a830544, TypeALU64>, Enc_0d8adb {
 let Inst{4-2} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11011100000;
@@ -3144,7 +3132,7 @@ def A4_vcmpbgt : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = vcmpb.gt($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b010000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11010010000;
@@ -3153,7 +3141,7 @@ def A4_vcmpbgti : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
 "$Pd4 = vcmpb.gt($Rss32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_0d8adb {
+tc_7a830544, TypeALU64>, Enc_0d8adb {
 let Inst{4-2} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11011100001;
@@ -3162,7 +3150,7 @@ def A4_vcmpbgtui : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
 "$Pd4 = vcmpb.gtu($Rss32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_3680c2 {
+tc_7a830544, TypeALU64>, Enc_3680c2 {
 let Inst{4-2} = 0b000;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b11011100010;
@@ -3171,7 +3159,7 @@ def A4_vcmpheqi : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
 "$Pd4 = vcmph.eq($Rss32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_0d8adb {
+tc_7a830544, TypeALU64>, Enc_0d8adb {
 let Inst{4-2} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11011100000;
@@ -3180,7 +3168,7 @@ def A4_vcmphgti : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
 "$Pd4 = vcmph.gt($Rss32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_0d8adb {
+tc_7a830544, TypeALU64>, Enc_0d8adb {
 let Inst{4-2} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11011100001;
@@ -3189,7 +3177,7 @@ def A4_vcmphgtui : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
 "$Pd4 = vcmph.gtu($Rss32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_3680c2 {
+tc_7a830544, TypeALU64>, Enc_3680c2 {
 let Inst{4-2} = 0b010;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b11011100010;
@@ -3198,7 +3186,7 @@ def A4_vcmpweqi : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
 "$Pd4 = vcmpw.eq($Rss32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_0d8adb {
+tc_7a830544, TypeALU64>, Enc_0d8adb {
 let Inst{4-2} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11011100000;
@@ -3207,7 +3195,7 @@ def A4_vcmpwgti : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
 "$Pd4 = vcmpw.gt($Rss32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_0d8adb {
+tc_7a830544, TypeALU64>, Enc_0d8adb {
 let Inst{4-2} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11011100001;
@@ -3216,7 +3204,7 @@ def A4_vcmpwgtui : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
 "$Pd4 = vcmpw.gtu($Rss32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_3680c2 {
+tc_7a830544, TypeALU64>, Enc_3680c2 {
 let Inst{4-2} = 0b100;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b11011100010;
@@ -3225,7 +3213,7 @@ def A4_vrmaxh : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
 "$Rxx32 = vrmaxh($Rss32,$Ru32)",
-tc_2aaab1e0, TypeS_3op>, Enc_412ff0 {
+tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011001;
@@ -3236,7 +3224,7 @@ def A4_vrmaxuh : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
 "$Rxx32 = vrmaxuh($Rss32,$Ru32)",
-tc_2aaab1e0, TypeS_3op>, Enc_412ff0 {
+tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11001011001;
@@ -3247,7 +3235,7 @@ def A4_vrmaxuw : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
 "$Rxx32 = vrmaxuw($Rss32,$Ru32)",
-tc_2aaab1e0, TypeS_3op>, Enc_412ff0 {
+tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11001011001;
@@ -3258,7 +3246,7 @@ def A4_vrmaxw : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
 "$Rxx32 = vrmaxw($Rss32,$Ru32)",
-tc_2aaab1e0, TypeS_3op>, Enc_412ff0 {
+tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011001;
@@ -3269,7 +3257,7 @@ def A4_vrminh : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
 "$Rxx32 = vrminh($Rss32,$Ru32)",
-tc_2aaab1e0, TypeS_3op>, Enc_412ff0 {
+tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011001;
@@ -3280,7 +3268,7 @@ def A4_vrminuh : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
 "$Rxx32 = vrminuh($Rss32,$Ru32)",
-tc_2aaab1e0, TypeS_3op>, Enc_412ff0 {
+tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11001011001;
@@ -3291,7 +3279,7 @@ def A4_vrminuw : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
 "$Rxx32 = vrminuw($Rss32,$Ru32)",
-tc_2aaab1e0, TypeS_3op>, Enc_412ff0 {
+tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11001011001;
@@ -3302,7 +3290,7 @@ def A4_vrminw : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
 "$Rxx32 = vrminw($Rss32,$Ru32)",
-tc_2aaab1e0, TypeS_3op>, Enc_412ff0 {
+tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011001;
@@ -3313,7 +3301,7 @@ def A5_ACS : HInst<
 (outs DoubleRegs:$Rxx32, PredRegs:$Pe4),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)",
-tc_ae0722f7, TypeM>, Enc_831a7d, Requires<[HasV55T]> {
+tc_caaebcba, TypeM>, Enc_831a7d, Requires<[HasV55T]> {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010101;
@@ -3326,7 +3314,7 @@ def A5_vaddhubs : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rd32 = vaddhub($Rss32,$Rtt32):sat",
-tc_63cd9d2d, TypeS_3op>, Enc_d2216a, Requires<[HasV5T]> {
+tc_2b6f77c6, TypeS_3op>, Enc_d2216a, Requires<[HasV5T]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001010;
@@ -3335,11 +3323,20 @@ let opNewValue = 0;
 let prefersSlot3 = 1;
 let Defs = [USR_OVF];
 }
+def A6_vcmpbeq_notany : HInst<
+(outs PredRegs:$Pd4),
+(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
+"$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))",
+tc_55050d58, TypeALU64>, Enc_fcf7a7, Requires<[HasV65T]> {
+let Inst{7-2} = 0b001000;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b11010010000;
+}
 def A6_vminub_RdP : HInst<
 (outs DoubleRegs:$Rdd32, PredRegs:$Pe4),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)",
-tc_583510c7, TypeM>, Enc_d2c7f1, Requires<[HasV62T]> {
+tc_ef84f62f, TypeM>, Enc_d2c7f1, Requires<[HasV62T]> {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010111;
@@ -3350,7 +3347,7 @@ def C2_all8 : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4),
 "$Pd4 = all8($Ps4)",
-tc_81a23d44, TypeCR>, Enc_65d691 {
+tc_f2704b9a, TypeCR>, Enc_65d691 {
 let Inst{13-2} = 0b000000000000;
 let Inst{31-18} = 0b01101011101000;
 }
@@ -3358,7 +3355,7 @@ def C2_and : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Pt4, PredRegs:$Ps4),
 "$Pd4 = and($Pt4,$Ps4)",
-tc_d63b71d1, TypeCR>, Enc_454a26 {
+tc_53bc8a6a, TypeCR>, Enc_454a26 {
 let Inst{7-2} = 0b000000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011000000;
@@ -3367,7 +3364,7 @@ def C2_andn : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Pt4, PredRegs:$Ps4),
 "$Pd4 = and($Pt4,!$Ps4)",
-tc_d63b71d1, TypeCR>, Enc_454a26 {
+tc_53bc8a6a, TypeCR>, Enc_454a26 {
 let Inst{7-2} = 0b000000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011011000;
@@ -3376,7 +3373,7 @@ def C2_any8 : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4),
 "$Pd4 = any8($Ps4)",
-tc_81a23d44, TypeCR>, Enc_65d691 {
+tc_f2704b9a, TypeCR>, Enc_65d691 {
 let Inst{13-2} = 0b000000000000;
 let Inst{31-18} = 0b01101011100000;
 }
@@ -3384,7 +3381,7 @@ def C2_bitsclr : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = bitsclr($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111100;
@@ -3393,7 +3390,7 @@ def C2_bitsclri : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u6_0Imm:$Ii),
 "$Pd4 = bitsclr($Rs32,#$Ii)",
-tc_5fa2857c, TypeS_2op>, Enc_5d6c34 {
+tc_7a830544, TypeS_2op>, Enc_5d6c34 {
 let Inst{7-2} = 0b000000;
 let Inst{31-21} = 0b10000101100;
 }
@@ -3401,7 +3398,7 @@ def C2_bitsset : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = bitsset($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111010;
@@ -3410,7 +3407,7 @@ def C2_ccombinewf : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111101000;
@@ -3422,7 +3419,7 @@ def C2_ccombinewnewf : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
-tc_28d296df, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111101000;
@@ -3435,7 +3432,7 @@ def C2_ccombinewnewt : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
-tc_28d296df, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
+tc_2b2f4060, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11111101000;
@@ -3447,7 +3444,7 @@ def C2_ccombinewt : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
+tc_d6bf0472, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11111101000;
@@ -3458,7 +3455,7 @@ def C2_cmoveif : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
 "if (!$Pu4) $Rd32 = #$Ii",
-tc_548f402d, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
+tc_b9488031, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
 let Inst{13-13} = 0b0;
 let Inst{20-20} = 0b0;
 let Inst{31-23} = 0b011111101;
@@ -3480,7 +3477,7 @@ def C2_cmoveit : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
 "if ($Pu4) $Rd32 = #$Ii",
-tc_548f402d, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
+tc_b9488031, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
 let Inst{13-13} = 0b0;
 let Inst{20-20} = 0b0;
 let Inst{31-23} = 0b011111100;
@@ -3501,7 +3498,7 @@ def C2_cmovenewif : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
 "if (!$Pu4.new) $Rd32 = #$Ii",
-tc_b08be45e, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
 let Inst{13-13} = 0b1;
 let Inst{20-20} = 0b0;
 let Inst{31-23} = 0b011111101;
@@ -3524,7 +3521,7 @@ def C2_cmovenewit : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
 "if ($Pu4.new) $Rd32 = #$Ii",
-tc_b08be45e, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
+tc_5f6847a1, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
 let Inst{13-13} = 0b1;
 let Inst{20-20} = 0b0;
 let Inst{31-23} = 0b011111100;
@@ -3546,7 +3543,7 @@ def C2_cmpeq : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmp.eq($Rs32,$Rt32)",
-tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
+tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110010000;
@@ -3559,7 +3556,7 @@ def C2_cmpeqi : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Pd4 = cmp.eq($Rs32,#$Ii)",
-tc_9df8b0dc, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
+tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
 let Inst{4-2} = 0b000;
 let Inst{31-22} = 0b0111010100;
 let CextOpcode = "C2_cmpeq";
@@ -3575,7 +3572,7 @@ def C2_cmpeqp : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = cmp.eq($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010100;
@@ -3586,7 +3583,7 @@ def C2_cmpgei : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, s8_0Imm:$Ii),
 "$Pd4 = cmp.ge($Rs32,#$Ii)",
-tc_9df8b0dc, TypeALU32_2op> {
+tc_6ebb4a12, TypeALU32_2op> {
 let isCompare = 1;
 let isPseudo = 1;
 }
@@ -3594,7 +3591,7 @@ def C2_cmpgeui : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u8_0Imm:$Ii),
 "$Pd4 = cmp.geu($Rs32,#$Ii)",
-tc_9df8b0dc, TypeALU32_2op> {
+tc_6ebb4a12, TypeALU32_2op> {
 let isCompare = 1;
 let isPseudo = 1;
 }
@@ -3602,7 +3599,7 @@ def C2_cmpgt : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmp.gt($Rs32,$Rt32)",
-tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
+tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110010010;
@@ -3614,7 +3611,7 @@ def C2_cmpgti : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Pd4 = cmp.gt($Rs32,#$Ii)",
-tc_9df8b0dc, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
+tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
 let Inst{4-2} = 0b000;
 let Inst{31-22} = 0b0111010101;
 let CextOpcode = "C2_cmpgt";
@@ -3630,7 +3627,7 @@ def C2_cmpgtp : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = cmp.gt($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b010000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010100;
@@ -3640,7 +3637,7 @@ def C2_cmpgtu : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmp.gtu($Rs32,$Rt32)",
-tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
+tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110010011;
@@ -3652,7 +3649,7 @@ def C2_cmpgtui : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
 "$Pd4 = cmp.gtu($Rs32,#$Ii)",
-tc_9df8b0dc, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
+tc_6ebb4a12, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
 let Inst{4-2} = 0b000;
 let Inst{31-21} = 0b01110101100;
 let CextOpcode = "C2_cmpgtu";
@@ -3668,7 +3665,7 @@ def C2_cmpgtup : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = cmp.gtu($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7 {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
 let Inst{7-2} = 0b100000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010100;
@@ -3678,7 +3675,7 @@ def C2_cmplt : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmp.lt($Rs32,$Rt32)",
-tc_9df8b0dc, TypeALU32_3op> {
+tc_6ebb4a12, TypeALU32_3op> {
 let isCompare = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
@@ -3687,7 +3684,7 @@ def C2_cmpltu : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = cmp.ltu($Rs32,$Rt32)",
-tc_9df8b0dc, TypeALU32_3op> {
+tc_6ebb4a12, TypeALU32_3op> {
 let isCompare = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
@@ -3696,7 +3693,7 @@ def C2_mask : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4),
 "$Rdd32 = mask($Pt4)",
-tc_b86c7e8b, TypeS_2op>, Enc_78e566 {
+tc_cde8b071, TypeS_2op>, Enc_78e566 {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b0000;
 let Inst{31-16} = 0b1000011000000000;
@@ -3705,7 +3702,7 @@ def C2_mux : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mux($Pu4,$Rs32,$Rt32)",
-tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54 {
+tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54 {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110100000;
@@ -3717,7 +3714,7 @@ def C2_muxii : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II),
 "$Rd32 = mux($Pu4,#$Ii,#$II)",
-tc_1b6011fb, TypeALU32_2op>, Enc_830e5d {
+tc_d6bf0472, TypeALU32_2op>, Enc_830e5d {
 let Inst{31-25} = 0b0111101;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -3731,7 +3728,7 @@ def C2_muxir : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rd32 = mux($Pu4,$Rs32,#$Ii)",
-tc_1b6011fb, TypeALU32_2op>, Enc_e38e1f {
+tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f {
 let Inst{13-13} = 0b0;
 let Inst{31-23} = 0b011100110;
 let hasNewValue = 1;
@@ -3747,7 +3744,7 @@ def C2_muxri : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32),
 "$Rd32 = mux($Pu4,#$Ii,$Rs32)",
-tc_1b6011fb, TypeALU32_2op>, Enc_e38e1f {
+tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f {
 let Inst{13-13} = 0b0;
 let Inst{31-23} = 0b011100111;
 let hasNewValue = 1;
@@ -3763,7 +3760,7 @@ def C2_not : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4),
 "$Pd4 = not($Ps4)",
-tc_81a23d44, TypeCR>, Enc_65d691 {
+tc_f2704b9a, TypeCR>, Enc_65d691 {
 let Inst{13-2} = 0b000000000000;
 let Inst{31-18} = 0b01101011110000;
 }
@@ -3771,7 +3768,7 @@ def C2_or : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Pt4, PredRegs:$Ps4),
 "$Pd4 = or($Pt4,$Ps4)",
-tc_d63b71d1, TypeCR>, Enc_454a26 {
+tc_53bc8a6a, TypeCR>, Enc_454a26 {
 let Inst{7-2} = 0b000000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011001000;
@@ -3780,7 +3777,7 @@ def C2_orn : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Pt4, PredRegs:$Ps4),
 "$Pd4 = or($Pt4,!$Ps4)",
-tc_d63b71d1, TypeCR>, Enc_454a26 {
+tc_53bc8a6a, TypeCR>, Enc_454a26 {
 let Inst{7-2} = 0b000000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011111000;
@@ -3789,7 +3786,7 @@ def C2_pxfer_map : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4),
 "$Pd4 = $Ps4",
-tc_d63b71d1, TypeMAPPING> {
+tc_53bc8a6a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -3797,7 +3794,7 @@ def C2_tfrpr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Ps4),
 "$Rd32 = $Ps4",
-tc_b86c7e8b, TypeS_2op>, Enc_f5e933 {
+tc_cde8b071, TypeS_2op>, Enc_f5e933 {
 let Inst{13-5} = 0b000000000;
 let Inst{31-18} = 0b10001001010000;
 let hasNewValue = 1;
@@ -3807,7 +3804,7 @@ def C2_tfrrp : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32),
 "$Pd4 = $Rs32",
-tc_47f0b7ad, TypeS_2op>, Enc_48b75f {
+tc_351fed2d, TypeS_2op>, Enc_48b75f {
 let Inst{13-2} = 0b000000000000;
 let Inst{31-21} = 0b10000101010;
 }
@@ -3815,7 +3812,7 @@ def C2_vitpack : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Ps4, PredRegs:$Pt4),
 "$Rd32 = vitpack($Ps4,$Pt4)",
-tc_7ca2ea10, TypeS_2op>, Enc_527412 {
+tc_1b9c9ee5, TypeS_2op>, Enc_527412 {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b10001001000000;
@@ -3827,7 +3824,7 @@ def C2_vmux : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)",
-tc_d1b5a4b6, TypeALU64>, Enc_329361 {
+tc_f8eeed7a, TypeALU64>, Enc_329361 {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010001000;
@@ -3836,7 +3833,7 @@ def C2_xor : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4),
 "$Pd4 = xor($Ps4,$Pt4)",
-tc_d63b71d1, TypeCR>, Enc_284ebb {
+tc_53bc8a6a, TypeCR>, Enc_284ebb {
 let Inst{7-2} = 0b000000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011010000;
@@ -3845,7 +3842,7 @@ def C4_addipc : HInst<
 (outs IntRegs:$Rd32),
 (ins u32_0Imm:$Ii),
 "$Rd32 = add(pc,#$Ii)",
-tc_1fe8323c, TypeCR>, Enc_607661 {
+tc_b9c4623f, TypeCR>, Enc_607661 {
 let Inst{6-5} = 0b00;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0110101001001001;
@@ -3861,7 +3858,7 @@ def C4_and_and : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
 "$Pd4 = and($Ps4,and($Pt4,$Pu4))",
-tc_43068634, TypeCR>, Enc_9ac432 {
+tc_481e5e5c, TypeCR>, Enc_9ac432 {
 let Inst{5-2} = 0b0000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011000100;
@@ -3870,7 +3867,7 @@ def C4_and_andn : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
 "$Pd4 = and($Ps4,and($Pt4,!$Pu4))",
-tc_43068634, TypeCR>, Enc_9ac432 {
+tc_481e5e5c, TypeCR>, Enc_9ac432 {
 let Inst{5-2} = 0b0000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011100100;
@@ -3879,7 +3876,7 @@ def C4_and_or : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
 "$Pd4 = and($Ps4,or($Pt4,$Pu4))",
-tc_43068634, TypeCR>, Enc_9ac432 {
+tc_481e5e5c, TypeCR>, Enc_9ac432 {
 let Inst{5-2} = 0b0000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011001100;
@@ -3888,7 +3885,7 @@ def C4_and_orn : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
 "$Pd4 = and($Ps4,or($Pt4,!$Pu4))",
-tc_43068634, TypeCR>, Enc_9ac432 {
+tc_481e5e5c, TypeCR>, Enc_9ac432 {
 let Inst{5-2} = 0b0000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011101100;
@@ -3897,7 +3894,7 @@ def C4_cmplte : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = !cmp.gt($Rs32,$Rt32)",
-tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
+tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b000100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110010010;
@@ -3909,7 +3906,7 @@ def C4_cmpltei : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Pd4 = !cmp.gt($Rs32,#$Ii)",
-tc_9df8b0dc, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
+tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
 let Inst{4-2} = 0b100;
 let Inst{31-22} = 0b0111010101;
 let CextOpcode = "C4_cmplte";
@@ -3925,7 +3922,7 @@ def C4_cmplteu : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = !cmp.gtu($Rs32,$Rt32)",
-tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
+tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b000100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110010011;
@@ -3937,7 +3934,7 @@ def C4_cmplteui : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
 "$Pd4 = !cmp.gtu($Rs32,#$Ii)",
-tc_9df8b0dc, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
+tc_6ebb4a12, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
 let Inst{4-2} = 0b100;
 let Inst{31-21} = 0b01110101100;
 let CextOpcode = "C4_cmplteu";
@@ -3953,7 +3950,7 @@ def C4_cmpneq : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = !cmp.eq($Rs32,$Rt32)",
-tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
+tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
 let Inst{7-2} = 0b000100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110010000;
@@ -3966,7 +3963,7 @@ def C4_cmpneqi : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Pd4 = !cmp.eq($Rs32,#$Ii)",
-tc_9df8b0dc, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
+tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
 let Inst{4-2} = 0b100;
 let Inst{31-22} = 0b0111010100;
 let CextOpcode = "C4_cmpneq";
@@ -3982,7 +3979,7 @@ def C4_fastcorner9 : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4),
 "$Pd4 = fastcorner9($Ps4,$Pt4)",
-tc_d63b71d1, TypeCR>, Enc_284ebb {
+tc_53bc8a6a, TypeCR>, Enc_284ebb {
 let Inst{7-2} = 0b100100;
 let Inst{13-10} = 0b1000;
 let Inst{31-18} = 0b01101011000000;
@@ -3991,7 +3988,7 @@ def C4_fastcorner9_not : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4),
 "$Pd4 = !fastcorner9($Ps4,$Pt4)",
-tc_d63b71d1, TypeCR>, Enc_284ebb {
+tc_53bc8a6a, TypeCR>, Enc_284ebb {
 let Inst{7-2} = 0b100100;
 let Inst{13-10} = 0b1000;
 let Inst{31-18} = 0b01101011000100;
@@ -4000,7 +3997,7 @@ def C4_nbitsclr : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = !bitsclr($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111101;
@@ -4009,7 +4006,7 @@ def C4_nbitsclri : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u6_0Imm:$Ii),
 "$Pd4 = !bitsclr($Rs32,#$Ii)",
-tc_5fa2857c, TypeS_2op>, Enc_5d6c34 {
+tc_7a830544, TypeS_2op>, Enc_5d6c34 {
 let Inst{7-2} = 0b000000;
 let Inst{31-21} = 0b10000101101;
 }
@@ -4017,7 +4014,7 @@ def C4_nbitsset : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = !bitsset($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111011;
@@ -4026,7 +4023,7 @@ def C4_or_and : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
 "$Pd4 = or($Ps4,and($Pt4,$Pu4))",
-tc_43068634, TypeCR>, Enc_9ac432 {
+tc_481e5e5c, TypeCR>, Enc_9ac432 {
 let Inst{5-2} = 0b0000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011010100;
@@ -4035,7 +4032,7 @@ def C4_or_andn : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
 "$Pd4 = or($Ps4,and($Pt4,!$Pu4))",
-tc_43068634, TypeCR>, Enc_9ac432 {
+tc_481e5e5c, TypeCR>, Enc_9ac432 {
 let Inst{5-2} = 0b0000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011110100;
@@ -4044,7 +4041,7 @@ def C4_or_or : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
 "$Pd4 = or($Ps4,or($Pt4,$Pu4))",
-tc_43068634, TypeCR>, Enc_9ac432 {
+tc_481e5e5c, TypeCR>, Enc_9ac432 {
 let Inst{5-2} = 0b0000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011011100;
@@ -4053,7 +4050,7 @@ def C4_or_orn : HInst<
 (outs PredRegs:$Pd4),
 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
 "$Pd4 = or($Ps4,or($Pt4,!$Pu4))",
-tc_43068634, TypeCR>, Enc_9ac432 {
+tc_481e5e5c, TypeCR>, Enc_9ac432 {
 let Inst{5-2} = 0b0000;
 let Inst{13-10} = 0b0000;
 let Inst{31-18} = 0b01101011111100;
@@ -4062,7 +4059,7 @@ def F2_conv_d2df : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = convert_d2df($Rss32)",
-tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000011;
 let Inst{31-21} = 0b10000000111;
 let isFP = 1;
@@ -4072,7 +4069,7 @@ def F2_conv_d2sf : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = convert_d2sf($Rss32)",
-tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10001000010;
 let hasNewValue = 1;
@@ -4084,7 +4081,7 @@ def F2_conv_df2d : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = convert_df2d($Rss32)",
-tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10000000111;
 let isFP = 1;
@@ -4094,7 +4091,7 @@ def F2_conv_df2d_chop : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = convert_df2d($Rss32):chop",
-tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10000000111;
 let isFP = 1;
@@ -4104,7 +4101,7 @@ def F2_conv_df2sf : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = convert_df2sf($Rss32)",
-tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10001000000;
 let hasNewValue = 1;
@@ -4116,7 +4113,7 @@ def F2_conv_df2ud : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = convert_df2ud($Rss32)",
-tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10000000111;
 let isFP = 1;
@@ -4126,7 +4123,7 @@ def F2_conv_df2ud_chop : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = convert_df2ud($Rss32):chop",
-tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000111;
 let Inst{31-21} = 0b10000000111;
 let isFP = 1;
@@ -4136,7 +4133,7 @@ def F2_conv_df2uw : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = convert_df2uw($Rss32)",
-tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10001000011;
 let hasNewValue = 1;
@@ -4148,7 +4145,7 @@ def F2_conv_df2uw_chop : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = convert_df2uw($Rss32):chop",
-tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10001000101;
 let hasNewValue = 1;
@@ -4160,7 +4157,7 @@ def F2_conv_df2w : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = convert_df2w($Rss32)",
-tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10001000100;
 let hasNewValue = 1;
@@ -4172,7 +4169,7 @@ def F2_conv_df2w_chop : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = convert_df2w($Rss32):chop",
-tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10001000111;
 let hasNewValue = 1;
@@ -4184,7 +4181,7 @@ def F2_conv_sf2d : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = convert_sf2d($Rs32)",
-tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10000100100;
 let isFP = 1;
@@ -4194,7 +4191,7 @@ def F2_conv_sf2d_chop : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = convert_sf2d($Rs32):chop",
-tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10000100100;
 let isFP = 1;
@@ -4204,7 +4201,7 @@ def F2_conv_sf2df : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = convert_sf2df($Rs32)",
-tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10000100100;
 let isFP = 1;
@@ -4214,7 +4211,7 @@ def F2_conv_sf2ud : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = convert_sf2ud($Rs32)",
-tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000011;
 let Inst{31-21} = 0b10000100100;
 let isFP = 1;
@@ -4224,7 +4221,7 @@ def F2_conv_sf2ud_chop : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = convert_sf2ud($Rs32):chop",
-tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000101;
 let Inst{31-21} = 0b10000100100;
 let isFP = 1;
@@ -4234,7 +4231,7 @@ def F2_conv_sf2uw : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = convert_sf2uw($Rs32)",
-tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001011011;
 let hasNewValue = 1;
@@ -4246,7 +4243,7 @@ def F2_conv_sf2uw_chop : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = convert_sf2uw($Rs32):chop",
-tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10001011011;
 let hasNewValue = 1;
@@ -4258,7 +4255,7 @@ def F2_conv_sf2w : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = convert_sf2w($Rs32)",
-tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001011100;
 let hasNewValue = 1;
@@ -4270,7 +4267,7 @@ def F2_conv_sf2w_chop : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = convert_sf2w($Rs32):chop",
-tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10001011100;
 let hasNewValue = 1;
@@ -4282,7 +4279,7 @@ def F2_conv_ud2df : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = convert_ud2df($Rss32)",
-tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000010;
 let Inst{31-21} = 0b10000000111;
 let isFP = 1;
@@ -4292,7 +4289,7 @@ def F2_conv_ud2sf : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = convert_ud2sf($Rss32)",
-tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10001000001;
 let hasNewValue = 1;
@@ -4304,7 +4301,7 @@ def F2_conv_uw2df : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = convert_uw2df($Rs32)",
-tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b10000100100;
 let isFP = 1;
@@ -4314,7 +4311,7 @@ def F2_conv_uw2sf : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = convert_uw2sf($Rs32)",
-tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001011001;
 let hasNewValue = 1;
@@ -4326,7 +4323,7 @@ def F2_conv_w2df : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = convert_w2df($Rs32)",
-tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000010;
 let Inst{31-21} = 0b10000100100;
 let isFP = 1;
@@ -4336,7 +4333,7 @@ def F2_conv_w2sf : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = convert_w2sf($Rs32)",
-tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001011010;
 let hasNewValue = 1;
@@ -4348,7 +4345,7 @@ def F2_dfclass : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
 "$Pd4 = dfclass($Rss32,#$Ii)",
-tc_5fa2857c, TypeALU64>, Enc_1f19b5, Requires<[HasV5T]> {
+tc_7a830544, TypeALU64>, Enc_1f19b5, Requires<[HasV5T]> {
 let Inst{4-2} = 0b100;
 let Inst{13-10} = 0b0000;
 let Inst{31-21} = 0b11011100100;
@@ -4359,7 +4356,7 @@ def F2_dfcmpeq : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = dfcmp.eq($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010111;
@@ -4371,7 +4368,7 @@ def F2_dfcmpge : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = dfcmp.ge($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
 let Inst{7-2} = 0b010000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010111;
@@ -4383,7 +4380,7 @@ def F2_dfcmpgt : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = dfcmp.gt($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
 let Inst{7-2} = 0b001000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010111;
@@ -4395,7 +4392,7 @@ def F2_dfcmpuo : HInst<
 (outs PredRegs:$Pd4),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Pd4 = dfcmp.uo($Rss32,$Rtt32)",
-tc_c58f771a, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
+tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> {
 let Inst{7-2} = 0b011000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010010111;
@@ -4407,7 +4404,7 @@ def F2_dfimm_n : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins u10_0Imm:$Ii),
 "$Rdd32 = dfmake(#$Ii):neg",
-tc_485bb57c, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> {
+tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> {
 let Inst{20-16} = 0b00000;
 let Inst{31-22} = 0b1101100101;
 let prefersSlot3 = 1;
@@ -4416,7 +4413,7 @@ def F2_dfimm_p : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins u10_0Imm:$Ii),
 "$Rdd32 = dfmake(#$Ii):pos",
-tc_485bb57c, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> {
+tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> {
 let Inst{20-16} = 0b00000;
 let Inst{31-22} = 0b1101100100;
 let prefersSlot3 = 1;
@@ -4425,7 +4422,7 @@ def F2_sfadd : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = sfadd($Rs32,$Rt32)",
-tc_3bea1824, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
+tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101011000;
@@ -4439,7 +4436,7 @@ def F2_sfclass : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Pd4 = sfclass($Rs32,#$Ii)",
-tc_5fa2857c, TypeS_2op>, Enc_83ee64, Requires<[HasV5T]> {
+tc_7a830544, TypeS_2op>, Enc_83ee64, Requires<[HasV5T]> {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10000101111;
@@ -4450,7 +4447,7 @@ def F2_sfcmpeq : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = sfcmp.eq($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
 let Inst{7-2} = 0b011000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111111;
@@ -4462,7 +4459,7 @@ def F2_sfcmpge : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = sfcmp.ge($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111111;
@@ -4474,7 +4471,7 @@ def F2_sfcmpgt : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = sfcmp.gt($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
 let Inst{7-2} = 0b100000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111111;
@@ -4486,7 +4483,7 @@ def F2_sfcmpuo : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = sfcmp.uo($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> {
 let Inst{7-2} = 0b001000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111111;
@@ -4498,7 +4495,7 @@ def F2_sffixupd : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = sffixupd($Rs32,$Rt32)",
-tc_3bea1824, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
+tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101011110;
@@ -4510,7 +4507,7 @@ def F2_sffixupn : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = sffixupn($Rs32,$Rt32)",
-tc_3bea1824, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
+tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101011110;
@@ -4522,7 +4519,7 @@ def F2_sffixupr : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = sffixupr($Rs32)",
-tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
+tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001011101;
 let hasNewValue = 1;
@@ -4533,7 +4530,7 @@ def F2_sffma : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += sfmpy($Rs32,$Rt32)",
-tc_2d1e6f5c, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
+tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111000;
@@ -4547,7 +4544,7 @@ def F2_sffma_lib : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += sfmpy($Rs32,$Rt32):lib",
-tc_2d1e6f5c, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
+tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111000;
@@ -4561,7 +4558,7 @@ def F2_sffma_sc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4),
 "$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale",
-tc_2e55aa16, TypeM>, Enc_437f33, Requires<[HasV5T]> {
+tc_038a1342, TypeM>, Enc_437f33, Requires<[HasV5T]> {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111011;
@@ -4575,7 +4572,7 @@ def F2_sffms : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= sfmpy($Rs32,$Rt32)",
-tc_2d1e6f5c, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
+tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111000;
@@ -4589,7 +4586,7 @@ def F2_sffms_lib : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= sfmpy($Rs32,$Rt32):lib",
-tc_2d1e6f5c, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
+tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111000;
@@ -4603,7 +4600,7 @@ def F2_sfimm_n : HInst<
 (outs IntRegs:$Rd32),
 (ins u10_0Imm:$Ii),
 "$Rd32 = sfmake(#$Ii):neg",
-tc_485bb57c, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> {
+tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> {
 let Inst{20-16} = 0b00000;
 let Inst{31-22} = 0b1101011001;
 let hasNewValue = 1;
@@ -4614,7 +4611,7 @@ def F2_sfimm_p : HInst<
 (outs IntRegs:$Rd32),
 (ins u10_0Imm:$Ii),
 "$Rd32 = sfmake(#$Ii):pos",
-tc_485bb57c, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> {
+tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> {
 let Inst{20-16} = 0b00000;
 let Inst{31-22} = 0b1101011000;
 let hasNewValue = 1;
@@ -4625,7 +4622,7 @@ def F2_sfinvsqrta : HInst<
 (outs IntRegs:$Rd32, PredRegs:$Pe4),
 (ins IntRegs:$Rs32),
 "$Rd32,$Pe4 = sfinvsqrta($Rs32)",
-tc_f1aa2cdb, TypeS_2op>, Enc_890909, Requires<[HasV5T]> {
+tc_4d99bca9, TypeS_2op>, Enc_890909, Requires<[HasV5T]> {
 let Inst{13-7} = 0b0000000;
 let Inst{31-21} = 0b10001011111;
 let hasNewValue = 1;
@@ -4637,7 +4634,7 @@ def F2_sfmax : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = sfmax($Rs32,$Rt32)",
-tc_f1240c08, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
+tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101011100;
@@ -4651,7 +4648,7 @@ def F2_sfmin : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = sfmin($Rs32,$Rt32)",
-tc_f1240c08, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
+tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101011100;
@@ -4665,7 +4662,7 @@ def F2_sfmpy : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = sfmpy($Rs32,$Rt32)",
-tc_3bea1824, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
+tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101011010;
@@ -4679,7 +4676,7 @@ def F2_sfrecipa : HInst<
 (outs IntRegs:$Rd32, PredRegs:$Pe4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)",
-tc_09c86199, TypeM>, Enc_a94f3b, Requires<[HasV5T]> {
+tc_9c00ce8d, TypeM>, Enc_a94f3b, Requires<[HasV5T]> {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101011111;
@@ -4692,7 +4689,7 @@ def F2_sfsub : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = sfsub($Rs32,$Rt32)",
-tc_3bea1824, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
+tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101011000;
@@ -4705,11 +4702,13 @@ def J2_call : HInst<
 (outs),
 (ins a30_2Imm:$Ii),
 "call $Ii",
-tc_639d93ee, TypeJ>, Enc_81ac1d, PredRel {
+tc_a27582fa, TypeJ>, Enc_81ac1d, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{31-25} = 0b0101101;
 let isCall = 1;
 let prefersSlot3 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [R29];
 let Defs = [PC, R31];
 let BaseOpcode = "J2_call";
@@ -4725,7 +4724,7 @@ def J2_callf : HInst<
 (outs),
 (ins PredRegs:$Pu4, a30_2Imm:$Ii),
 "if (!$Pu4) call $Ii",
-tc_0767081f, TypeJ>, Enc_daea09, PredRel {
+tc_2f185f5c, TypeJ>, Enc_daea09, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{12-10} = 0b000;
 let Inst{21-21} = 0b1;
@@ -4734,6 +4733,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isCall = 1;
 let prefersSlot3 = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [R29];
 let Defs = [PC, R31];
 let BaseOpcode = "J2_call";
@@ -4749,12 +4751,12 @@ def J2_callr : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "callr $Rs32",
-tc_ecfaae86, TypeJ>, Enc_ecbcc8 {
+tc_15411484, TypeJ>, Enc_ecbcc8 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b01010000101;
-let cofMax1 = 1;
 let isCall = 1;
 let prefersSlot3 = 1;
+let cofMax1 = 1;
 let Uses = [R29];
 let Defs = [PC, R31];
 let hasSideEffects = 1;
@@ -4763,15 +4765,15 @@ def J2_callrf : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) callr $Rs32",
-tc_84630363, TypeJ>, Enc_88d4d9 {
+tc_10b97e27, TypeJ>, Enc_88d4d9 {
 let Inst{7-0} = 0b00000000;
 let Inst{13-10} = 0b0000;
 let Inst{31-21} = 0b01010001001;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
-let cofMax1 = 1;
 let isCall = 1;
 let prefersSlot3 = 1;
+let cofMax1 = 1;
 let Uses = [R29];
 let Defs = [PC, R31];
 let hasSideEffects = 1;
@@ -4781,14 +4783,14 @@ def J2_callrt : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) callr $Rs32",
-tc_84630363, TypeJ>, Enc_88d4d9 {
+tc_10b97e27, TypeJ>, Enc_88d4d9 {
 let Inst{7-0} = 0b00000000;
 let Inst{13-10} = 0b0000;
 let Inst{31-21} = 0b01010001000;
 let isPredicated = 1;
-let cofMax1 = 1;
 let isCall = 1;
 let prefersSlot3 = 1;
+let cofMax1 = 1;
 let Uses = [R29];
 let Defs = [PC, R31];
 let hasSideEffects = 1;
@@ -4798,7 +4800,7 @@ def J2_callt : HInst<
 (outs),
 (ins PredRegs:$Pu4, a30_2Imm:$Ii),
 "if ($Pu4) call $Ii",
-tc_0767081f, TypeJ>, Enc_daea09, PredRel {
+tc_2f185f5c, TypeJ>, Enc_daea09, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{12-10} = 0b000;
 let Inst{21-21} = 0b0;
@@ -4806,6 +4808,9 @@ let Inst{31-24} = 0b01011101;
 let isPredicated = 1;
 let isCall = 1;
 let prefersSlot3 = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [R29];
 let Defs = [PC, R31];
 let BaseOpcode = "J2_call";
@@ -4821,7 +4826,7 @@ def J2_endloop0 : HInst<
 (outs),
 (ins),
 "endloop0",
-tc_aad55963, TypeJ> {
+tc_52d7bbea, TypeJ> {
 let Uses = [LC0, SA0];
 let Defs = [LC0, P3, PC, USR];
 let isBranch = 1;
@@ -4832,7 +4837,7 @@ def J2_endloop01 : HInst<
 (outs),
 (ins),
 "endloop01",
-tc_aad55963, TypeJ> {
+tc_52d7bbea, TypeJ> {
 let Uses = [LC0, LC1, SA0, SA1];
 let Defs = [LC0, LC1, P3, PC, USR];
 let isPseudo = 1;
@@ -4841,7 +4846,7 @@ def J2_endloop1 : HInst<
 (outs),
 (ins),
 "endloop1",
-tc_aad55963, TypeJ> {
+tc_52d7bbea, TypeJ> {
 let Uses = [LC1, SA1];
 let Defs = [LC1, PC];
 let isBranch = 1;
@@ -4852,11 +4857,13 @@ def J2_jump : HInst<
 (outs),
 (ins b30_2Imm:$Ii),
 "jump $Ii",
-tc_a333d2a9, TypeJ>, Enc_81ac1d, PredNewRel {
+tc_3669266a, TypeJ>, Enc_81ac1d, PredNewRel {
 let Inst{0-0} = 0b0;
 let Inst{31-25} = 0b0101100;
 let isTerminator = 1;
 let isBranch = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "imm";
 let BaseOpcode = "J2_jump";
@@ -4872,7 +4879,7 @@ def J2_jumpf : HInst<
 (outs),
 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
 "if (!$Pu4) jump:nt $Ii",
-tc_1b834fe7, TypeJ>, Enc_daea09, PredNewRel {
+tc_e9fae2d6, TypeJ>, Enc_daea09, PredNewRel {
 let Inst{0-0} = 0b0;
 let Inst{12-10} = 0b000;
 let Inst{21-21} = 0b1;
@@ -4881,6 +4888,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "imm";
 let BaseOpcode = "J2_jump";
@@ -4895,7 +4905,7 @@ def J2_jumpf_nopred_map : HInst<
 (outs),
 (ins PredRegs:$Pu4, b15_2Imm:$Ii),
 "if (!$Pu4) jump $Ii",
-tc_1b834fe7, TypeMAPPING>, Requires<[HasV60T]> {
+tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60T]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -4903,7 +4913,7 @@ def J2_jumpfnew : HInst<
 (outs),
 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
 "if (!$Pu4.new) jump:nt $Ii",
-tc_537e2013, TypeJ>, Enc_daea09, PredNewRel {
+tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
 let Inst{0-0} = 0b0;
 let Inst{12-10} = 0b010;
 let Inst{21-21} = 0b1;
@@ -4913,6 +4923,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "imm";
 let BaseOpcode = "J2_jump";
@@ -4927,7 +4940,7 @@ def J2_jumpfnewpt : HInst<
 (outs),
 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
 "if (!$Pu4.new) jump:t $Ii",
-tc_537e2013, TypeJ>, Enc_daea09, PredNewRel {
+tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
 let Inst{0-0} = 0b0;
 let Inst{12-10} = 0b110;
 let Inst{21-21} = 0b1;
@@ -4937,6 +4950,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "imm";
 let BaseOpcode = "J2_jump";
@@ -4951,7 +4967,7 @@ def J2_jumpfpt : HInst<
 (outs),
 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
 "if (!$Pu4) jump:t $Ii",
-tc_b5bfaa60, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel {
+tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel {
 let Inst{0-0} = 0b0;
 let Inst{12-10} = 0b100;
 let Inst{21-21} = 0b1;
@@ -4960,6 +4976,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "imm";
 let BaseOpcode = "J2_jump";
@@ -4974,7 +4993,7 @@ def J2_jumpr : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "jumpr $Rs32",
-tc_b08b653e, TypeJ>, Enc_ecbcc8, PredNewRel {
+tc_9faf76ae, TypeJ>, Enc_ecbcc8, PredNewRel {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b01010010100;
 let isTerminator = 1;
@@ -4991,7 +5010,7 @@ def J2_jumprf : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) jumpr:nt $Rs32",
-tc_07ac815d, TypeJ>, Enc_88d4d9, PredNewRel {
+tc_e0739b8c, TypeJ>, Enc_88d4d9, PredNewRel {
 let Inst{7-0} = 0b00000000;
 let Inst{13-10} = 0b0000;
 let Inst{31-21} = 0b01010011011;
@@ -5010,7 +5029,7 @@ def J2_jumprf_nopred_map : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) jumpr $Rs32",
-tc_07ac815d, TypeMAPPING>, Requires<[HasV60T]> {
+tc_e0739b8c, TypeMAPPING>, Requires<[HasV60T]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -5018,7 +5037,7 @@ def J2_jumprfnew : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4.new) jumpr:nt $Rs32",
-tc_1f9668cc, TypeJ>, Enc_88d4d9, PredNewRel {
+tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
 let Inst{7-0} = 0b00000000;
 let Inst{13-10} = 0b0010;
 let Inst{31-21} = 0b01010011011;
@@ -5027,8 +5046,8 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isPredicatedNew = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "reg";
 let BaseOpcode = "J2_jumpr";
@@ -5038,7 +5057,7 @@ def J2_jumprfnewpt : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4.new) jumpr:t $Rs32",
-tc_1f9668cc, TypeJ>, Enc_88d4d9, PredNewRel {
+tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
 let Inst{7-0} = 0b00000000;
 let Inst{13-10} = 0b0110;
 let Inst{31-21} = 0b01010011011;
@@ -5047,8 +5066,8 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isPredicatedNew = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "reg";
 let BaseOpcode = "J2_jumpr";
@@ -5058,7 +5077,7 @@ def J2_jumprfpt : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if (!$Pu4) jumpr:t $Rs32",
-tc_a1fb80e1, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel {
+tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel {
 let Inst{7-0} = 0b00000000;
 let Inst{13-10} = 0b0100;
 let Inst{31-21} = 0b01010011011;
@@ -5077,7 +5096,7 @@ def J2_jumprgtez : HInst<
 (outs),
 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
 "if ($Rs32>=#0) jump:nt $Ii",
-tc_b324366f, TypeCR>, Enc_0fa531 {
+tc_73043bf4, TypeCR>, Enc_0fa531 {
 let Inst{0-0} = 0b0;
 let Inst{12-12} = 0b0;
 let Inst{31-22} = 0b0110000101;
@@ -5085,6 +5104,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let isTaken = Inst{12};
 }
@@ -5092,7 +5114,7 @@ def J2_jumprgtezpt : HInst<
 (outs),
 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
 "if ($Rs32>=#0) jump:t $Ii",
-tc_b324366f, TypeCR>, Enc_0fa531 {
+tc_73043bf4, TypeCR>, Enc_0fa531 {
 let Inst{0-0} = 0b0;
 let Inst{12-12} = 0b1;
 let Inst{31-22} = 0b0110000101;
@@ -5100,6 +5122,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let isTaken = Inst{12};
 }
@@ -5107,7 +5132,7 @@ def J2_jumprltez : HInst<
 (outs),
 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
 "if ($Rs32<=#0) jump:nt $Ii",
-tc_b324366f, TypeCR>, Enc_0fa531 {
+tc_73043bf4, TypeCR>, Enc_0fa531 {
 let Inst{0-0} = 0b0;
 let Inst{12-12} = 0b0;
 let Inst{31-22} = 0b0110000111;
@@ -5115,6 +5140,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let isTaken = Inst{12};
 }
@@ -5122,7 +5150,7 @@ def J2_jumprltezpt : HInst<
 (outs),
 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
 "if ($Rs32<=#0) jump:t $Ii",
-tc_b324366f, TypeCR>, Enc_0fa531 {
+tc_73043bf4, TypeCR>, Enc_0fa531 {
 let Inst{0-0} = 0b0;
 let Inst{12-12} = 0b1;
 let Inst{31-22} = 0b0110000111;
@@ -5130,6 +5158,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let isTaken = Inst{12};
 }
@@ -5137,7 +5168,7 @@ def J2_jumprnz : HInst<
 (outs),
 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
 "if ($Rs32==#0) jump:nt $Ii",
-tc_b324366f, TypeCR>, Enc_0fa531 {
+tc_73043bf4, TypeCR>, Enc_0fa531 {
 let Inst{0-0} = 0b0;
 let Inst{12-12} = 0b0;
 let Inst{31-22} = 0b0110000110;
@@ -5145,6 +5176,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let isTaken = Inst{12};
 }
@@ -5152,7 +5186,7 @@ def J2_jumprnzpt : HInst<
 (outs),
 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
 "if ($Rs32==#0) jump:t $Ii",
-tc_b324366f, TypeCR>, Enc_0fa531 {
+tc_73043bf4, TypeCR>, Enc_0fa531 {
 let Inst{0-0} = 0b0;
 let Inst{12-12} = 0b1;
 let Inst{31-22} = 0b0110000110;
@@ -5160,6 +5194,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let isTaken = Inst{12};
 }
@@ -5167,7 +5204,7 @@ def J2_jumprt : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) jumpr:nt $Rs32",
-tc_07ac815d, TypeJ>, Enc_88d4d9, PredNewRel {
+tc_e0739b8c, TypeJ>, Enc_88d4d9, PredNewRel {
 let Inst{7-0} = 0b00000000;
 let Inst{13-10} = 0b0000;
 let Inst{31-21} = 0b01010011010;
@@ -5185,7 +5222,7 @@ def J2_jumprt_nopred_map : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) jumpr $Rs32",
-tc_07ac815d, TypeMAPPING>, Requires<[HasV60T]> {
+tc_e0739b8c, TypeMAPPING>, Requires<[HasV60T]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -5193,7 +5230,7 @@ def J2_jumprtnew : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4.new) jumpr:nt $Rs32",
-tc_1f9668cc, TypeJ>, Enc_88d4d9, PredNewRel {
+tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
 let Inst{7-0} = 0b00000000;
 let Inst{13-10} = 0b0010;
 let Inst{31-21} = 0b01010011010;
@@ -5201,8 +5238,8 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isPredicatedNew = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "reg";
 let BaseOpcode = "J2_jumpr";
@@ -5212,7 +5249,7 @@ def J2_jumprtnewpt : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4.new) jumpr:t $Rs32",
-tc_1f9668cc, TypeJ>, Enc_88d4d9, PredNewRel {
+tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
 let Inst{7-0} = 0b00000000;
 let Inst{13-10} = 0b0110;
 let Inst{31-21} = 0b01010011010;
@@ -5220,8 +5257,8 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isPredicatedNew = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "reg";
 let BaseOpcode = "J2_jumpr";
@@ -5231,7 +5268,7 @@ def J2_jumprtpt : HInst<
 (outs),
 (ins PredRegs:$Pu4, IntRegs:$Rs32),
 "if ($Pu4) jumpr:t $Rs32",
-tc_a1fb80e1, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel {
+tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel {
 let Inst{7-0} = 0b00000000;
 let Inst{13-10} = 0b0100;
 let Inst{31-21} = 0b01010011010;
@@ -5249,7 +5286,7 @@ def J2_jumprz : HInst<
 (outs),
 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
 "if ($Rs32!=#0) jump:nt $Ii",
-tc_b324366f, TypeCR>, Enc_0fa531 {
+tc_73043bf4, TypeCR>, Enc_0fa531 {
 let Inst{0-0} = 0b0;
 let Inst{12-12} = 0b0;
 let Inst{31-22} = 0b0110000100;
@@ -5257,6 +5294,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let isTaken = Inst{12};
 }
@@ -5264,7 +5304,7 @@ def J2_jumprzpt : HInst<
 (outs),
 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
 "if ($Rs32!=#0) jump:t $Ii",
-tc_b324366f, TypeCR>, Enc_0fa531 {
+tc_73043bf4, TypeCR>, Enc_0fa531 {
 let Inst{0-0} = 0b0;
 let Inst{12-12} = 0b1;
 let Inst{31-22} = 0b0110000100;
@@ -5272,6 +5312,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let isTaken = Inst{12};
 }
@@ -5279,7 +5322,7 @@ def J2_jumpt : HInst<
 (outs),
 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
 "if ($Pu4) jump:nt $Ii",
-tc_1b834fe7, TypeJ>, Enc_daea09, PredNewRel {
+tc_e9fae2d6, TypeJ>, Enc_daea09, PredNewRel {
 let Inst{0-0} = 0b0;
 let Inst{12-10} = 0b000;
 let Inst{21-21} = 0b0;
@@ -5287,6 +5330,9 @@ let Inst{31-24} = 0b01011100;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "imm";
 let BaseOpcode = "J2_jump";
@@ -5301,7 +5347,7 @@ def J2_jumpt_nopred_map : HInst<
 (outs),
 (ins PredRegs:$Pu4, b15_2Imm:$Ii),
 "if ($Pu4) jump $Ii",
-tc_1b834fe7, TypeMAPPING>, Requires<[HasV60T]> {
+tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60T]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -5309,7 +5355,7 @@ def J2_jumptnew : HInst<
 (outs),
 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
 "if ($Pu4.new) jump:nt $Ii",
-tc_537e2013, TypeJ>, Enc_daea09, PredNewRel {
+tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
 let Inst{0-0} = 0b0;
 let Inst{12-10} = 0b010;
 let Inst{21-21} = 0b0;
@@ -5318,6 +5364,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "imm";
 let BaseOpcode = "J2_jump";
@@ -5332,7 +5381,7 @@ def J2_jumptnewpt : HInst<
 (outs),
 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
 "if ($Pu4.new) jump:t $Ii",
-tc_537e2013, TypeJ>, Enc_daea09, PredNewRel {
+tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
 let Inst{0-0} = 0b0;
 let Inst{12-10} = 0b110;
 let Inst{21-21} = 0b0;
@@ -5341,6 +5390,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "imm";
 let BaseOpcode = "J2_jump";
@@ -5355,7 +5407,7 @@ def J2_jumptpt : HInst<
 (outs),
 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
 "if ($Pu4) jump:t $Ii",
-tc_b5bfaa60, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel {
+tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel {
 let Inst{0-0} = 0b0;
 let Inst{12-10} = 0b100;
 let Inst{21-21} = 0b0;
@@ -5363,6 +5415,9 @@ let Inst{31-24} = 0b01011100;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let InputType = "imm";
 let BaseOpcode = "J2_jump";
@@ -5377,10 +5432,12 @@ def J2_loop0i : HInst<
 (outs),
 (ins b30_2Imm:$Ii, u10_0Imm:$II),
 "loop0($Ii,#$II)",
-tc_1000eb10, TypeCR>, Enc_4dc228 {
+tc_cf59f215, TypeCR>, Enc_4dc228 {
 let Inst{2-2} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01101001000;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
 let Defs = [LC0, SA0, USR];
 let isExtendable = 1;
 let opExtendable = 0;
@@ -5392,11 +5449,13 @@ def J2_loop0r : HInst<
 (outs),
 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
 "loop0($Ii,$Rs32)",
-tc_f055fbb6, TypeCR>, Enc_864a5a {
+tc_7934b9df, TypeCR>, Enc_864a5a {
 let Inst{2-0} = 0b000;
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01100000000;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
 let Defs = [LC0, SA0, USR];
 let isExtendable = 1;
 let opExtendable = 0;
@@ -5408,10 +5467,12 @@ def J2_loop1i : HInst<
 (outs),
 (ins b30_2Imm:$Ii, u10_0Imm:$II),
 "loop1($Ii,#$II)",
-tc_1000eb10, TypeCR>, Enc_4dc228 {
+tc_cf59f215, TypeCR>, Enc_4dc228 {
 let Inst{2-2} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01101001001;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
 let Defs = [LC1, SA1];
 let isExtendable = 1;
 let opExtendable = 0;
@@ -5423,11 +5484,13 @@ def J2_loop1r : HInst<
 (outs),
 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
 "loop1($Ii,$Rs32)",
-tc_f055fbb6, TypeCR>, Enc_864a5a {
+tc_7934b9df, TypeCR>, Enc_864a5a {
 let Inst{2-0} = 0b000;
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01100000001;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
 let Defs = [LC1, SA1];
 let isExtendable = 1;
 let opExtendable = 0;
@@ -5439,7 +5502,7 @@ def J2_pause : HInst<
 (outs),
 (ins u8_0Imm:$Ii),
 "pause(#$Ii)",
-tc_b189ad4c, TypeJ>, Enc_a51a9a {
+tc_681a2300, TypeJ>, Enc_a51a9a {
 let Inst{1-0} = 0b00;
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
@@ -5450,11 +5513,13 @@ def J2_ploop1si : HInst<
 (outs),
 (ins b30_2Imm:$Ii, u10_0Imm:$II),
 "p3 = sp1loop0($Ii,#$II)",
-tc_feb4974b, TypeCR>, Enc_4dc228 {
+tc_c5e2426d, TypeCR>, Enc_4dc228 {
 let Inst{2-2} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01101001101;
 let isPredicateLate = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
 let Defs = [LC0, P3, SA0, USR];
 let isExtendable = 1;
 let opExtendable = 0;
@@ -5466,12 +5531,14 @@ def J2_ploop1sr : HInst<
 (outs),
 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
 "p3 = sp1loop0($Ii,$Rs32)",
-tc_d6a805a8, TypeCR>, Enc_864a5a {
+tc_4f7cd700, TypeCR>, Enc_864a5a {
 let Inst{2-0} = 0b000;
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01100000101;
 let isPredicateLate = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
 let Defs = [LC0, P3, SA0, USR];
 let isExtendable = 1;
 let opExtendable = 0;
@@ -5483,11 +5550,13 @@ def J2_ploop2si : HInst<
 (outs),
 (ins b30_2Imm:$Ii, u10_0Imm:$II),
 "p3 = sp2loop0($Ii,#$II)",
-tc_feb4974b, TypeCR>, Enc_4dc228 {
+tc_c5e2426d, TypeCR>, Enc_4dc228 {
 let Inst{2-2} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01101001110;
 let isPredicateLate = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
 let Defs = [LC0, P3, SA0, USR];
 let isExtendable = 1;
 let opExtendable = 0;
@@ -5499,12 +5568,14 @@ def J2_ploop2sr : HInst<
 (outs),
 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
 "p3 = sp2loop0($Ii,$Rs32)",
-tc_d6a805a8, TypeCR>, Enc_864a5a {
+tc_4f7cd700, TypeCR>, Enc_864a5a {
 let Inst{2-0} = 0b000;
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01100000110;
 let isPredicateLate = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
 let Defs = [LC0, P3, SA0, USR];
 let isExtendable = 1;
 let opExtendable = 0;
@@ -5516,11 +5587,13 @@ def J2_ploop3si : HInst<
 (outs),
 (ins b30_2Imm:$Ii, u10_0Imm:$II),
 "p3 = sp3loop0($Ii,#$II)",
-tc_feb4974b, TypeCR>, Enc_4dc228 {
+tc_c5e2426d, TypeCR>, Enc_4dc228 {
 let Inst{2-2} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01101001111;
 let isPredicateLate = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
 let Defs = [LC0, P3, SA0, USR];
 let isExtendable = 1;
 let opExtendable = 0;
@@ -5532,12 +5605,14 @@ def J2_ploop3sr : HInst<
 (outs),
 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
 "p3 = sp3loop0($Ii,$Rs32)",
-tc_d6a805a8, TypeCR>, Enc_864a5a {
+tc_4f7cd700, TypeCR>, Enc_864a5a {
 let Inst{2-0} = 0b000;
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01100000111;
 let isPredicateLate = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
 let Defs = [LC0, P3, SA0, USR];
 let isExtendable = 1;
 let opExtendable = 0;
@@ -5549,7 +5624,7 @@ def J2_trap0 : HInst<
 (outs),
 (ins u8_0Imm:$Ii),
 "trap0(#$Ii)",
-tc_cbe45117, TypeJ>, Enc_a51a9a {
+tc_14cd4cfa, TypeJ>, Enc_a51a9a {
 let Inst{1-0} = 0b00;
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
@@ -5560,7 +5635,7 @@ def J4_cmpeq_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -5569,8 +5644,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqr";
 let isTaken = Inst{13};
@@ -5585,7 +5661,7 @@ def J4_cmpeq_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -5594,8 +5670,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqr";
 let isTaken = Inst{13};
@@ -5610,7 +5687,7 @@ def J4_cmpeq_fp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b00;
 let Inst{31-22} = 0b0001010001;
@@ -5619,6 +5696,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqp0";
@@ -5633,7 +5713,7 @@ def J4_cmpeq_fp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b10;
 let Inst{31-22} = 0b0001010001;
@@ -5642,6 +5722,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqp0";
@@ -5656,7 +5739,7 @@ def J4_cmpeq_fp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-22} = 0b0001010001;
@@ -5665,6 +5748,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqp1";
@@ -5679,7 +5765,7 @@ def J4_cmpeq_fp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b11;
 let Inst{31-22} = 0b0001010001;
@@ -5688,6 +5774,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqp1";
@@ -5702,7 +5791,7 @@ def J4_cmpeq_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -5710,8 +5799,9 @@ let Inst{31-22} = 0b0010000000;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqr";
 let isTaken = Inst{13};
@@ -5726,7 +5816,7 @@ def J4_cmpeq_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -5734,8 +5824,9 @@ let Inst{31-22} = 0b0010000000;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqr";
 let isTaken = Inst{13};
@@ -5750,7 +5841,7 @@ def J4_cmpeq_tp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b00;
 let Inst{31-22} = 0b0001010000;
@@ -5758,6 +5849,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqp0";
@@ -5772,7 +5866,7 @@ def J4_cmpeq_tp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b10;
 let Inst{31-22} = 0b0001010000;
@@ -5780,6 +5874,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqp0";
@@ -5794,7 +5891,7 @@ def J4_cmpeq_tp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-22} = 0b0001010000;
@@ -5802,6 +5899,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqp1";
@@ -5816,7 +5916,7 @@ def J4_cmpeq_tp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b11;
 let Inst{31-22} = 0b0001010000;
@@ -5824,6 +5924,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqp1";
@@ -5838,7 +5941,7 @@ def J4_cmpeqi_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -5847,8 +5950,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqi";
 let isTaken = Inst{13};
@@ -5863,7 +5967,7 @@ def J4_cmpeqi_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -5872,8 +5976,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqi";
 let isTaken = Inst{13};
@@ -5888,7 +5993,7 @@ def J4_cmpeqi_fp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001000001;
@@ -5897,6 +6002,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqip0";
@@ -5911,7 +6019,7 @@ def J4_cmpeqi_fp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001000001;
@@ -5920,6 +6028,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqip0";
@@ -5934,7 +6045,7 @@ def J4_cmpeqi_fp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001001001;
@@ -5943,6 +6054,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqip1";
@@ -5957,7 +6071,7 @@ def J4_cmpeqi_fp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001001001;
@@ -5966,6 +6080,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqip1";
@@ -5980,7 +6097,7 @@ def J4_cmpeqi_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -5988,8 +6105,9 @@ let Inst{31-22} = 0b0010010000;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqi";
 let isTaken = Inst{13};
@@ -6004,7 +6122,7 @@ def J4_cmpeqi_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (cmp.eq($Ns8.new,#$II)) jump:t $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -6012,8 +6130,9 @@ let Inst{31-22} = 0b0010010000;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqi";
 let isTaken = Inst{13};
@@ -6028,7 +6147,7 @@ def J4_cmpeqi_tp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001000000;
@@ -6036,6 +6155,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqip0";
@@ -6050,7 +6172,7 @@ def J4_cmpeqi_tp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001000000;
@@ -6058,6 +6180,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqip0";
@@ -6072,7 +6197,7 @@ def J4_cmpeqi_tp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001001000;
@@ -6080,6 +6205,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqip1";
@@ -6094,7 +6222,7 @@ def J4_cmpeqi_tp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001001000;
@@ -6102,6 +6230,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqip1";
@@ -6116,7 +6247,7 @@ def J4_cmpeqn1_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
 "if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
-tc_09faec3b, TypeNCJ>, Enc_e90a15, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_e90a15, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000000;
 let Inst{19-19} = 0b0;
@@ -6125,8 +6256,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqn1r";
 let isTaken = Inst{13};
@@ -6141,7 +6273,7 @@ def J4_cmpeqn1_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
 "if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
-tc_09faec3b, TypeNCJ>, Enc_5a18b3, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_5a18b3, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100000;
 let Inst{19-19} = 0b0;
@@ -6150,8 +6282,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqn1r";
 let isTaken = Inst{13};
@@ -6166,7 +6299,7 @@ def J4_cmpeqn1_fp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_1de724, PredRel {
+tc_99be14ca, TypeCJ>, Enc_1de724, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000000;
 let Inst{31-22} = 0b0001000111;
@@ -6175,6 +6308,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqn1p0";
@@ -6189,7 +6325,7 @@ def J4_cmpeqn1_fp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14640c, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14640c, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100000;
 let Inst{31-22} = 0b0001000111;
@@ -6198,6 +6334,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqn1p0";
@@ -6212,7 +6351,7 @@ def J4_cmpeqn1_fp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_668704, PredRel {
+tc_99be14ca, TypeCJ>, Enc_668704, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000000;
 let Inst{31-22} = 0b0001001111;
@@ -6221,6 +6360,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqn1p1";
@@ -6235,7 +6377,7 @@ def J4_cmpeqn1_fp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_800e04, PredRel {
+tc_99be14ca, TypeCJ>, Enc_800e04, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100000;
 let Inst{31-22} = 0b0001001111;
@@ -6244,6 +6386,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqn1p1";
@@ -6258,7 +6403,7 @@ def J4_cmpeqn1_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
 "if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
-tc_09faec3b, TypeNCJ>, Enc_4aca3a, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_4aca3a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000000;
 let Inst{19-19} = 0b0;
@@ -6266,8 +6411,9 @@ let Inst{31-22} = 0b0010011000;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqn1r";
 let isTaken = Inst{13};
@@ -6282,7 +6428,7 @@ def J4_cmpeqn1_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
 "if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
-tc_09faec3b, TypeNCJ>, Enc_f7ea77, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_f7ea77, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100000;
 let Inst{19-19} = 0b0;
@@ -6290,8 +6436,9 @@ let Inst{31-22} = 0b0010011000;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpeqn1r";
 let isTaken = Inst{13};
@@ -6306,7 +6453,7 @@ def J4_cmpeqn1_tp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_405228, PredRel {
+tc_99be14ca, TypeCJ>, Enc_405228, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000000;
 let Inst{31-22} = 0b0001000110;
@@ -6314,6 +6461,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqn1p0";
@@ -6328,7 +6478,7 @@ def J4_cmpeqn1_tp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_3a2484, PredRel {
+tc_99be14ca, TypeCJ>, Enc_3a2484, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100000;
 let Inst{31-22} = 0b0001000110;
@@ -6336,6 +6486,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpeqn1p0";
@@ -6350,7 +6503,7 @@ def J4_cmpeqn1_tp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_736575, PredRel {
+tc_99be14ca, TypeCJ>, Enc_736575, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000000;
 let Inst{31-22} = 0b0001001110;
@@ -6358,6 +6511,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqn1p1";
@@ -6372,7 +6528,7 @@ def J4_cmpeqn1_tp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_8e583a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_8e583a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100000;
 let Inst{31-22} = 0b0001001110;
@@ -6380,6 +6536,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpeqn1p1";
@@ -6394,7 +6553,7 @@ def J4_cmpgt_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -6403,8 +6562,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtr";
 let isTaken = Inst{13};
@@ -6419,7 +6579,7 @@ def J4_cmpgt_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -6428,8 +6588,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtr";
 let isTaken = Inst{13};
@@ -6444,7 +6605,7 @@ def J4_cmpgt_fp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b00;
 let Inst{31-22} = 0b0001010011;
@@ -6453,6 +6614,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtp0";
@@ -6467,7 +6631,7 @@ def J4_cmpgt_fp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b10;
 let Inst{31-22} = 0b0001010011;
@@ -6476,6 +6640,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtp0";
@@ -6490,7 +6657,7 @@ def J4_cmpgt_fp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-22} = 0b0001010011;
@@ -6499,6 +6666,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtp1";
@@ -6513,7 +6683,7 @@ def J4_cmpgt_fp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b11;
 let Inst{31-22} = 0b0001010011;
@@ -6522,6 +6692,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtp1";
@@ -6536,7 +6709,7 @@ def J4_cmpgt_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -6544,8 +6717,9 @@ let Inst{31-22} = 0b0010000010;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtr";
 let isTaken = Inst{13};
@@ -6560,7 +6734,7 @@ def J4_cmpgt_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -6568,8 +6742,9 @@ let Inst{31-22} = 0b0010000010;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtr";
 let isTaken = Inst{13};
@@ -6584,7 +6759,7 @@ def J4_cmpgt_tp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b00;
 let Inst{31-22} = 0b0001010010;
@@ -6592,6 +6767,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtp0";
@@ -6606,7 +6784,7 @@ def J4_cmpgt_tp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b10;
 let Inst{31-22} = 0b0001010010;
@@ -6614,6 +6792,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtp0";
@@ -6628,7 +6809,7 @@ def J4_cmpgt_tp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-22} = 0b0001010010;
@@ -6636,6 +6817,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtp1";
@@ -6650,7 +6834,7 @@ def J4_cmpgt_tp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b11;
 let Inst{31-22} = 0b0001010010;
@@ -6658,6 +6842,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtp1";
@@ -6672,7 +6859,7 @@ def J4_cmpgti_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -6681,8 +6868,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtir";
 let isTaken = Inst{13};
@@ -6697,7 +6885,7 @@ def J4_cmpgti_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -6706,8 +6894,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtir";
 let isTaken = Inst{13};
@@ -6722,7 +6911,7 @@ def J4_cmpgti_fp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001000011;
@@ -6731,6 +6920,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtip0";
@@ -6745,7 +6937,7 @@ def J4_cmpgti_fp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001000011;
@@ -6754,6 +6946,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtip0";
@@ -6768,7 +6963,7 @@ def J4_cmpgti_fp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001001011;
@@ -6777,6 +6972,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtip1";
@@ -6791,7 +6989,7 @@ def J4_cmpgti_fp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001001011;
@@ -6800,6 +6998,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtip1";
@@ -6814,7 +7015,7 @@ def J4_cmpgti_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -6822,8 +7023,9 @@ let Inst{31-22} = 0b0010010010;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtir";
 let isTaken = Inst{13};
@@ -6838,7 +7040,7 @@ def J4_cmpgti_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (cmp.gt($Ns8.new,#$II)) jump:t $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -6846,8 +7048,9 @@ let Inst{31-22} = 0b0010010010;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtir";
 let isTaken = Inst{13};
@@ -6862,7 +7065,7 @@ def J4_cmpgti_tp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001000010;
@@ -6870,6 +7073,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtip0";
@@ -6884,7 +7090,7 @@ def J4_cmpgti_tp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001000010;
@@ -6892,6 +7098,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtip0";
@@ -6906,7 +7115,7 @@ def J4_cmpgti_tp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001001010;
@@ -6914,6 +7123,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtip1";
@@ -6928,7 +7140,7 @@ def J4_cmpgti_tp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001001010;
@@ -6936,6 +7148,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtip1";
@@ -6950,7 +7165,7 @@ def J4_cmpgtn1_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
 "if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
-tc_09faec3b, TypeNCJ>, Enc_3694bd, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_3694bd, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000000;
 let Inst{19-19} = 0b0;
@@ -6959,8 +7174,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtn1r";
 let isTaken = Inst{13};
@@ -6975,7 +7191,7 @@ def J4_cmpgtn1_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
 "if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
-tc_09faec3b, TypeNCJ>, Enc_a6853f, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_a6853f, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100000;
 let Inst{19-19} = 0b0;
@@ -6984,8 +7200,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtn1r";
 let isTaken = Inst{13};
@@ -7000,7 +7217,7 @@ def J4_cmpgtn1_fp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_a42857, PredRel {
+tc_99be14ca, TypeCJ>, Enc_a42857, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000001;
 let Inst{31-22} = 0b0001000111;
@@ -7009,6 +7226,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtn1p0";
@@ -7023,7 +7243,7 @@ def J4_cmpgtn1_fp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_f6fe0b, PredRel {
+tc_99be14ca, TypeCJ>, Enc_f6fe0b, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100001;
 let Inst{31-22} = 0b0001000111;
@@ -7032,6 +7252,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtn1p0";
@@ -7046,7 +7269,7 @@ def J4_cmpgtn1_fp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_3e3989, PredRel {
+tc_99be14ca, TypeCJ>, Enc_3e3989, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000001;
 let Inst{31-22} = 0b0001001111;
@@ -7055,6 +7278,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtn1p1";
@@ -7069,7 +7295,7 @@ def J4_cmpgtn1_fp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_b909d2, PredRel {
+tc_99be14ca, TypeCJ>, Enc_b909d2, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100001;
 let Inst{31-22} = 0b0001001111;
@@ -7078,6 +7304,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtn1p1";
@@ -7092,7 +7321,7 @@ def J4_cmpgtn1_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
 "if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
-tc_09faec3b, TypeNCJ>, Enc_f82302, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_f82302, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000000;
 let Inst{19-19} = 0b0;
@@ -7100,8 +7329,9 @@ let Inst{31-22} = 0b0010011010;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtn1r";
 let isTaken = Inst{13};
@@ -7116,7 +7346,7 @@ def J4_cmpgtn1_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
 "if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
-tc_09faec3b, TypeNCJ>, Enc_6413b6, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_6413b6, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100000;
 let Inst{19-19} = 0b0;
@@ -7124,8 +7354,9 @@ let Inst{31-22} = 0b0010011010;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtn1r";
 let isTaken = Inst{13};
@@ -7140,7 +7371,7 @@ def J4_cmpgtn1_tp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_b78edd, PredRel {
+tc_99be14ca, TypeCJ>, Enc_b78edd, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000001;
 let Inst{31-22} = 0b0001000110;
@@ -7148,6 +7379,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtn1p0";
@@ -7162,7 +7396,7 @@ def J4_cmpgtn1_tp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_041d7b, PredRel {
+tc_99be14ca, TypeCJ>, Enc_041d7b, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100001;
 let Inst{31-22} = 0b0001000110;
@@ -7170,6 +7404,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtn1p0";
@@ -7184,7 +7421,7 @@ def J4_cmpgtn1_tp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_b1e1fb, PredRel {
+tc_99be14ca, TypeCJ>, Enc_b1e1fb, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000001;
 let Inst{31-22} = 0b0001001110;
@@ -7192,6 +7429,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtn1p1";
@@ -7206,7 +7446,7 @@ def J4_cmpgtn1_tp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
 "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_178717, PredRel {
+tc_99be14ca, TypeCJ>, Enc_178717, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100001;
 let Inst{31-22} = 0b0001001110;
@@ -7214,6 +7454,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtn1p1";
@@ -7228,7 +7471,7 @@ def J4_cmpgtu_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -7237,8 +7480,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtur";
 let isTaken = Inst{13};
@@ -7253,7 +7497,7 @@ def J4_cmpgtu_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -7262,8 +7506,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtur";
 let isTaken = Inst{13};
@@ -7278,7 +7523,7 @@ def J4_cmpgtu_fp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b00;
 let Inst{31-22} = 0b0001010101;
@@ -7287,6 +7532,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtup0";
@@ -7301,7 +7549,7 @@ def J4_cmpgtu_fp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b10;
 let Inst{31-22} = 0b0001010101;
@@ -7310,6 +7558,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtup0";
@@ -7324,7 +7575,7 @@ def J4_cmpgtu_fp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-22} = 0b0001010101;
@@ -7333,6 +7584,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtup1";
@@ -7347,7 +7601,7 @@ def J4_cmpgtu_fp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b11;
 let Inst{31-22} = 0b0001010101;
@@ -7356,6 +7610,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtup1";
@@ -7370,7 +7627,7 @@ def J4_cmpgtu_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -7378,8 +7635,9 @@ let Inst{31-22} = 0b0010000100;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtur";
 let isTaken = Inst{13};
@@ -7394,7 +7652,7 @@ def J4_cmpgtu_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
 "if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
-tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel {
+tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -7402,8 +7660,9 @@ let Inst{31-22} = 0b0010000100;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtur";
 let isTaken = Inst{13};
@@ -7418,7 +7677,7 @@ def J4_cmpgtu_tp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b00;
 let Inst{31-22} = 0b0001010100;
@@ -7426,6 +7685,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtup0";
@@ -7440,7 +7702,7 @@ def J4_cmpgtu_tp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b10;
 let Inst{31-22} = 0b0001010100;
@@ -7448,6 +7710,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtup0";
@@ -7462,7 +7727,7 @@ def J4_cmpgtu_tp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-22} = 0b0001010100;
@@ -7470,6 +7735,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtup1";
@@ -7484,7 +7752,7 @@ def J4_cmpgtu_tp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
 "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii",
-tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel {
+tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b11;
 let Inst{31-22} = 0b0001010100;
@@ -7492,6 +7760,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtup1";
@@ -7506,7 +7777,7 @@ def J4_cmpgtui_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -7515,8 +7786,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtuir";
 let isTaken = Inst{13};
@@ -7531,7 +7803,7 @@ def J4_cmpgtui_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -7540,8 +7812,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtuir";
 let isTaken = Inst{13};
@@ -7556,7 +7829,7 @@ def J4_cmpgtui_fp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001000101;
@@ -7565,6 +7838,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtuip0";
@@ -7579,7 +7855,7 @@ def J4_cmpgtui_fp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001000101;
@@ -7588,6 +7864,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtuip0";
@@ -7602,7 +7881,7 @@ def J4_cmpgtui_fp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001001101;
@@ -7611,6 +7890,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtuip1";
@@ -7625,7 +7907,7 @@ def J4_cmpgtui_fp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001001101;
@@ -7634,6 +7916,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtuip1";
@@ -7648,7 +7933,7 @@ def J4_cmpgtui_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -7656,8 +7941,9 @@ let Inst{31-22} = 0b0010010100;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtuir";
 let isTaken = Inst{13};
@@ -7672,7 +7958,7 @@ def J4_cmpgtui_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
 "if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
-tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel {
+tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -7680,8 +7966,9 @@ let Inst{31-22} = 0b0010010100;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpgtuir";
 let isTaken = Inst{13};
@@ -7696,7 +7983,7 @@ def J4_cmpgtui_tp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001000100;
@@ -7704,6 +7991,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtuip0";
@@ -7718,7 +8008,7 @@ def J4_cmpgtui_tp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001000100;
@@ -7726,6 +8016,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let BaseOpcode = "J4_cmpgtuip0";
@@ -7740,7 +8033,7 @@ def J4_cmpgtui_tp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-22} = 0b0001001100;
@@ -7748,6 +8041,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtuip1";
@@ -7762,7 +8058,7 @@ def J4_cmpgtui_tp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
 "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii",
-tc_d108a090, TypeCJ>, Enc_14d27a, PredRel {
+tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-22} = 0b0001001100;
@@ -7770,6 +8066,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let BaseOpcode = "J4_cmpgtuip1";
@@ -7784,7 +8083,7 @@ def J4_cmplt_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
-tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel {
+tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -7793,8 +8092,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpltr";
 let isTaken = Inst{13};
@@ -7809,7 +8109,7 @@ def J4_cmplt_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
-tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel {
+tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -7818,8 +8118,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpltr";
 let isTaken = Inst{13};
@@ -7834,7 +8135,7 @@ def J4_cmplt_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
-tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel {
+tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -7842,8 +8143,9 @@ let Inst{31-22} = 0b0010000110;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpltr";
 let isTaken = Inst{13};
@@ -7858,7 +8160,7 @@ def J4_cmplt_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
-tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel {
+tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -7866,8 +8168,9 @@ let Inst{31-22} = 0b0010000110;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpltr";
 let isTaken = Inst{13};
@@ -7882,7 +8185,7 @@ def J4_cmpltu_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
-tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel {
+tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -7891,8 +8194,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpltur";
 let isTaken = Inst{13};
@@ -7907,7 +8211,7 @@ def J4_cmpltu_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
-tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel {
+tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -7916,8 +8220,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpltur";
 let isTaken = Inst{13};
@@ -7932,7 +8237,7 @@ def J4_cmpltu_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
-tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel {
+tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{19-19} = 0b0;
@@ -7940,8 +8245,9 @@ let Inst{31-22} = 0b0010001000;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpltur";
 let isTaken = Inst{13};
@@ -7956,7 +8262,7 @@ def J4_cmpltu_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
-tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel {
+tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
 let Inst{0-0} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{19-19} = 0b0;
@@ -7964,8 +8270,9 @@ let Inst{31-22} = 0b0010001000;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let BaseOpcode = "J4_cmpltur";
 let isTaken = Inst{13};
@@ -7980,7 +8287,7 @@ def J4_hintjumpr : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "hintjr($Rs32)",
-tc_b08b653e, TypeJ>, Enc_ecbcc8 {
+tc_9faf76ae, TypeJ>, Enc_ecbcc8 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b01010010101;
 let isTerminator = 1;
@@ -7992,13 +8299,15 @@ def J4_jumpseti : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins u6_0Imm:$II, b30_2Imm:$Ii),
 "$Rd16 = #$II ; jump $Ii",
-tc_1e062b18, TypeCJ>, Enc_9e4c3f {
+tc_49eb22c8, TypeCJ>, Enc_9e4c3f {
 let Inst{0-0} = 0b0;
 let Inst{31-22} = 0b0001011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let isTerminator = 1;
 let isBranch = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let isExtendable = 1;
 let opExtendable = 2;
@@ -8010,7 +8319,7 @@ def J4_jumpsetr : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
 "$Rd16 = $Rs16 ; jump $Ii",
-tc_1e062b18, TypeCJ>, Enc_66bce1 {
+tc_49eb22c8, TypeCJ>, Enc_66bce1 {
 let Inst{0-0} = 0b0;
 let Inst{13-12} = 0b00;
 let Inst{31-22} = 0b0001011100;
@@ -8018,6 +8327,8 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isTerminator = 1;
 let isBranch = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Defs = [PC];
 let isExtendable = 1;
 let opExtendable = 2;
@@ -8029,7 +8340,7 @@ def J4_tstbit0_f_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (!tstbit($Ns8.new,#0)) jump:nt $Ii",
-tc_dbe218dd, TypeNCJ>, Enc_69d63b {
+tc_746baa8e, TypeNCJ>, Enc_69d63b {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000000;
 let Inst{19-19} = 0b0;
@@ -8038,8 +8349,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let isTaken = Inst{13};
 let isExtendable = 1;
@@ -8053,7 +8365,7 @@ def J4_tstbit0_f_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (!tstbit($Ns8.new,#0)) jump:t $Ii",
-tc_dbe218dd, TypeNCJ>, Enc_69d63b {
+tc_746baa8e, TypeNCJ>, Enc_69d63b {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100000;
 let Inst{19-19} = 0b0;
@@ -8062,8 +8374,9 @@ let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let isTaken = Inst{13};
 let isExtendable = 1;
@@ -8077,7 +8390,7 @@ def J4_tstbit0_fp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
 "p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii",
-tc_eb07ef6f, TypeCJ>, Enc_ad1c74 {
+tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000011;
 let Inst{31-22} = 0b0001000111;
@@ -8086,6 +8399,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let isTaken = Inst{13};
@@ -8099,7 +8415,7 @@ def J4_tstbit0_fp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
 "p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii",
-tc_eb07ef6f, TypeCJ>, Enc_ad1c74 {
+tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100011;
 let Inst{31-22} = 0b0001000111;
@@ -8108,6 +8424,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let isTaken = Inst{13};
@@ -8121,7 +8440,7 @@ def J4_tstbit0_fp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
 "p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii",
-tc_eb07ef6f, TypeCJ>, Enc_ad1c74 {
+tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000011;
 let Inst{31-22} = 0b0001001111;
@@ -8130,6 +8449,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let isTaken = Inst{13};
@@ -8143,7 +8465,7 @@ def J4_tstbit0_fp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
 "p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii",
-tc_eb07ef6f, TypeCJ>, Enc_ad1c74 {
+tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100011;
 let Inst{31-22} = 0b0001001111;
@@ -8152,6 +8474,9 @@ let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let isTaken = Inst{13};
@@ -8165,7 +8490,7 @@ def J4_tstbit0_t_jumpnv_nt : HInst<
 (outs),
 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (tstbit($Ns8.new,#0)) jump:nt $Ii",
-tc_dbe218dd, TypeNCJ>, Enc_69d63b {
+tc_746baa8e, TypeNCJ>, Enc_69d63b {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000000;
 let Inst{19-19} = 0b0;
@@ -8173,8 +8498,9 @@ let Inst{31-22} = 0b0010010110;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let isTaken = Inst{13};
 let isExtendable = 1;
@@ -8188,7 +8514,7 @@ def J4_tstbit0_t_jumpnv_t : HInst<
 (outs),
 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
 "if (tstbit($Ns8.new,#0)) jump:t $Ii",
-tc_dbe218dd, TypeNCJ>, Enc_69d63b {
+tc_746baa8e, TypeNCJ>, Enc_69d63b {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100000;
 let Inst{19-19} = 0b0;
@@ -8196,8 +8522,9 @@ let Inst{31-22} = 0b0010010110;
 let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
-let cofMax1 = 1;
 let isNewValue = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let Defs = [PC];
 let isTaken = Inst{13};
 let isExtendable = 1;
@@ -8211,7 +8538,7 @@ def J4_tstbit0_tp0_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
 "p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii",
-tc_eb07ef6f, TypeCJ>, Enc_ad1c74 {
+tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000011;
 let Inst{31-22} = 0b0001000110;
@@ -8219,6 +8546,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let isTaken = Inst{13};
@@ -8232,7 +8562,7 @@ def J4_tstbit0_tp0_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
 "p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii",
-tc_eb07ef6f, TypeCJ>, Enc_ad1c74 {
+tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100011;
 let Inst{31-22} = 0b0001000110;
@@ -8240,6 +8570,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P0];
 let Defs = [P0, PC];
 let isTaken = Inst{13};
@@ -8253,7 +8586,7 @@ def J4_tstbit0_tp1_jump_nt : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
 "p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii",
-tc_eb07ef6f, TypeCJ>, Enc_ad1c74 {
+tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b000011;
 let Inst{31-22} = 0b0001001110;
@@ -8261,6 +8594,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let isTaken = Inst{13};
@@ -8274,7 +8610,7 @@ def J4_tstbit0_tp1_jump_t : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
 "p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii",
-tc_eb07ef6f, TypeCJ>, Enc_ad1c74 {
+tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
 let Inst{0-0} = 0b0;
 let Inst{13-8} = 0b100011;
 let Inst{31-22} = 0b0001001110;
@@ -8282,6 +8618,9 @@ let isPredicated = 1;
 let isTerminator = 1;
 let isBranch = 1;
 let isPredicatedNew = 1;
+let cofRelax1 = 1;
+let cofRelax2 = 1;
+let cofMax1 = 1;
 let Uses = [P1];
 let Defs = [P1, PC];
 let isTaken = Inst{13};
@@ -8292,24 +8631,22 @@ let opExtentBits = 11;
 let opExtentAlign = 2;
 }
 def L2_deallocframe : HInst<
-(outs),
-(ins),
-"deallocframe",
-tc_c1dbc916, TypeLD>, Enc_3a3d62 {
-let Inst{4-0} = 0b11110;
+(outs DoubleRegs:$Rdd32),
+(ins IntRegs:$Rs32),
+"$Rdd32 = deallocframe($Rs32):raw",
+tc_d1090e34, TypeLD>, Enc_3a3d62 {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10010000000;
-let Inst{20-16} = 0b11110;
 let accessSize = DoubleWordAccess;
 let mayLoad = 1;
-let Uses = [R30];
-let Defs = [R29, R30, R31];
+let Uses = [FRAMEKEY];
+let Defs = [R29];
 }
 def L2_loadalignb_io : HInst<
 (outs DoubleRegs:$Ryy32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Ryy32 = memb_fifo($Rs32+#$Ii)",
-tc_14da557c, TypeLD>, Enc_a27588 {
+tc_ef52ed71, TypeLD>, Enc_a27588 {
 let Inst{24-21} = 0b0100;
 let Inst{31-27} = 0b10010;
 let addrMode = BaseImmOffset;
@@ -8326,7 +8663,7 @@ def L2_loadalignb_pbr : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Ryy32 = memb_fifo($Rx32++$Mu2:brev)",
-tc_ae762521, TypeLD>, Enc_1f5d8f {
+tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011110100;
 let accessSize = ByteAccess;
@@ -8337,7 +8674,7 @@ def L2_loadalignb_pci : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
 "$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))",
-tc_d2a33af5, TypeLD>, Enc_74aef2 {
+tc_03220ffa, TypeLD>, Enc_74aef2 {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011000100;
 let addrMode = PostInc;
@@ -8350,7 +8687,7 @@ def L2_loadalignb_pcr : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))",
-tc_ae762521, TypeLD>, Enc_1f5d8f {
+tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011000100;
 let addrMode = PostInc;
@@ -8363,7 +8700,7 @@ def L2_loadalignb_pi : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii),
 "$Ryy32 = memb_fifo($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_6b197f {
+tc_bad2bcaf, TypeLD>, Enc_6b197f {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011010100;
 let addrMode = PostInc;
@@ -8375,7 +8712,7 @@ def L2_loadalignb_pr : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Ryy32 = memb_fifo($Rx32++$Mu2)",
-tc_ae762521, TypeLD>, Enc_1f5d8f {
+tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011100100;
 let addrMode = PostInc;
@@ -8387,7 +8724,7 @@ def L2_loadalignb_zomap : HInst<
 (outs DoubleRegs:$Ryy32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
 "$Ryy32 = memb_fifo($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let Constraints = "$Ryy32 = $Ryy32in";
@@ -8396,7 +8733,7 @@ def L2_loadalignh_io : HInst<
 (outs DoubleRegs:$Ryy32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii),
 "$Ryy32 = memh_fifo($Rs32+#$Ii)",
-tc_14da557c, TypeLD>, Enc_5cd7e9 {
+tc_ef52ed71, TypeLD>, Enc_5cd7e9 {
 let Inst{24-21} = 0b0010;
 let Inst{31-27} = 0b10010;
 let addrMode = BaseImmOffset;
@@ -8413,7 +8750,7 @@ def L2_loadalignh_pbr : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Ryy32 = memh_fifo($Rx32++$Mu2:brev)",
-tc_ae762521, TypeLD>, Enc_1f5d8f {
+tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011110010;
 let accessSize = HalfWordAccess;
@@ -8424,7 +8761,7 @@ def L2_loadalignh_pci : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
 "$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))",
-tc_d2a33af5, TypeLD>, Enc_9e2e1c {
+tc_03220ffa, TypeLD>, Enc_9e2e1c {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011000010;
 let addrMode = PostInc;
@@ -8437,7 +8774,7 @@ def L2_loadalignh_pcr : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))",
-tc_ae762521, TypeLD>, Enc_1f5d8f {
+tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011000010;
 let addrMode = PostInc;
@@ -8450,7 +8787,7 @@ def L2_loadalignh_pi : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii),
 "$Ryy32 = memh_fifo($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_bd1cbc {
+tc_bad2bcaf, TypeLD>, Enc_bd1cbc {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011010010;
 let addrMode = PostInc;
@@ -8462,7 +8799,7 @@ def L2_loadalignh_pr : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Ryy32 = memh_fifo($Rx32++$Mu2)",
-tc_ae762521, TypeLD>, Enc_1f5d8f {
+tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011100010;
 let addrMode = PostInc;
@@ -8474,7 +8811,7 @@ def L2_loadalignh_zomap : HInst<
 (outs DoubleRegs:$Ryy32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
 "$Ryy32 = memh_fifo($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let Constraints = "$Ryy32 = $Ryy32in";
@@ -8483,7 +8820,7 @@ def L2_loadbsw2_io : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
 "$Rd32 = membh($Rs32+#$Ii)",
-tc_bf6fa601, TypeLD>, Enc_de0214 {
+tc_7f881c76, TypeLD>, Enc_de0214 {
 let Inst{24-21} = 0b0001;
 let Inst{31-27} = 0b10010;
 let hasNewValue = 1;
@@ -8501,7 +8838,7 @@ def L2_loadbsw2_pbr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = membh($Rx32++$Mu2:brev)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011110001;
 let hasNewValue = 1;
@@ -8514,7 +8851,7 @@ def L2_loadbsw2_pci : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
 "$Rd32 = membh($Rx32++#$Ii:circ($Mu2))",
-tc_3eab77bd, TypeLD>, Enc_e83554 {
+tc_4403ca65, TypeLD>, Enc_e83554 {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011000001;
 let hasNewValue = 1;
@@ -8529,7 +8866,7 @@ def L2_loadbsw2_pcr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = membh($Rx32++I:circ($Mu2))",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011000001;
 let hasNewValue = 1;
@@ -8544,7 +8881,7 @@ def L2_loadbsw2_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
 "$Rd32 = membh($Rx32++#$Ii)",
-tc_65dc7cc4, TypeLD>, Enc_152467 {
+tc_2fc0c436, TypeLD>, Enc_152467 {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011010001;
 let hasNewValue = 1;
@@ -8558,7 +8895,7 @@ def L2_loadbsw2_pr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = membh($Rx32++$Mu2)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011100001;
 let hasNewValue = 1;
@@ -8572,7 +8909,7 @@ def L2_loadbsw2_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = membh($Rs32)",
-tc_bf6fa601, TypeMAPPING> {
+tc_7f881c76, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -8582,7 +8919,7 @@ def L2_loadbsw4_io : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, s30_2Imm:$Ii),
 "$Rdd32 = membh($Rs32+#$Ii)",
-tc_bf6fa601, TypeLD>, Enc_2d7491 {
+tc_7f881c76, TypeLD>, Enc_2d7491 {
 let Inst{24-21} = 0b0111;
 let Inst{31-27} = 0b10010;
 let addrMode = BaseImmOffset;
@@ -8598,7 +8935,7 @@ def L2_loadbsw4_pbr : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rdd32 = membh($Rx32++$Mu2:brev)",
-tc_65dc7cc4, TypeLD>, Enc_7eee72 {
+tc_2fc0c436, TypeLD>, Enc_7eee72 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011110111;
 let accessSize = WordAccess;
@@ -8609,7 +8946,7 @@ def L2_loadbsw4_pci : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
 "$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))",
-tc_3eab77bd, TypeLD>, Enc_70b24b {
+tc_4403ca65, TypeLD>, Enc_70b24b {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011000111;
 let addrMode = PostInc;
@@ -8622,7 +8959,7 @@ def L2_loadbsw4_pcr : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rdd32 = membh($Rx32++I:circ($Mu2))",
-tc_65dc7cc4, TypeLD>, Enc_7eee72 {
+tc_2fc0c436, TypeLD>, Enc_7eee72 {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011000111;
 let addrMode = PostInc;
@@ -8635,7 +8972,7 @@ def L2_loadbsw4_pi : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_2Imm:$Ii),
 "$Rdd32 = membh($Rx32++#$Ii)",
-tc_65dc7cc4, TypeLD>, Enc_71f1b4 {
+tc_2fc0c436, TypeLD>, Enc_71f1b4 {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011010111;
 let addrMode = PostInc;
@@ -8647,7 +8984,7 @@ def L2_loadbsw4_pr : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rdd32 = membh($Rx32++$Mu2)",
-tc_65dc7cc4, TypeLD>, Enc_7eee72 {
+tc_2fc0c436, TypeLD>, Enc_7eee72 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011100111;
 let addrMode = PostInc;
@@ -8659,7 +8996,7 @@ def L2_loadbsw4_zomap : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = membh($Rs32)",
-tc_bf6fa601, TypeMAPPING> {
+tc_7f881c76, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -8667,7 +9004,7 @@ def L2_loadbzw2_io : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
 "$Rd32 = memubh($Rs32+#$Ii)",
-tc_bf6fa601, TypeLD>, Enc_de0214 {
+tc_7f881c76, TypeLD>, Enc_de0214 {
 let Inst{24-21} = 0b0011;
 let Inst{31-27} = 0b10010;
 let hasNewValue = 1;
@@ -8685,7 +9022,7 @@ def L2_loadbzw2_pbr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memubh($Rx32++$Mu2:brev)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011110011;
 let hasNewValue = 1;
@@ -8698,7 +9035,7 @@ def L2_loadbzw2_pci : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
 "$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))",
-tc_3eab77bd, TypeLD>, Enc_e83554 {
+tc_4403ca65, TypeLD>, Enc_e83554 {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011000011;
 let hasNewValue = 1;
@@ -8713,7 +9050,7 @@ def L2_loadbzw2_pcr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memubh($Rx32++I:circ($Mu2))",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011000011;
 let hasNewValue = 1;
@@ -8728,7 +9065,7 @@ def L2_loadbzw2_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
 "$Rd32 = memubh($Rx32++#$Ii)",
-tc_65dc7cc4, TypeLD>, Enc_152467 {
+tc_2fc0c436, TypeLD>, Enc_152467 {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011010011;
 let hasNewValue = 1;
@@ -8742,7 +9079,7 @@ def L2_loadbzw2_pr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memubh($Rx32++$Mu2)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011100011;
 let hasNewValue = 1;
@@ -8756,7 +9093,7 @@ def L2_loadbzw2_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = memubh($Rs32)",
-tc_bf6fa601, TypeMAPPING> {
+tc_7f881c76, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -8766,7 +9103,7 @@ def L2_loadbzw4_io : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, s30_2Imm:$Ii),
 "$Rdd32 = memubh($Rs32+#$Ii)",
-tc_bf6fa601, TypeLD>, Enc_2d7491 {
+tc_7f881c76, TypeLD>, Enc_2d7491 {
 let Inst{24-21} = 0b0101;
 let Inst{31-27} = 0b10010;
 let addrMode = BaseImmOffset;
@@ -8782,7 +9119,7 @@ def L2_loadbzw4_pbr : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rdd32 = memubh($Rx32++$Mu2:brev)",
-tc_65dc7cc4, TypeLD>, Enc_7eee72 {
+tc_2fc0c436, TypeLD>, Enc_7eee72 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011110101;
 let accessSize = WordAccess;
@@ -8793,7 +9130,7 @@ def L2_loadbzw4_pci : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
 "$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))",
-tc_3eab77bd, TypeLD>, Enc_70b24b {
+tc_4403ca65, TypeLD>, Enc_70b24b {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011000101;
 let addrMode = PostInc;
@@ -8806,7 +9143,7 @@ def L2_loadbzw4_pcr : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rdd32 = memubh($Rx32++I:circ($Mu2))",
-tc_65dc7cc4, TypeLD>, Enc_7eee72 {
+tc_2fc0c436, TypeLD>, Enc_7eee72 {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011000101;
 let addrMode = PostInc;
@@ -8819,7 +9156,7 @@ def L2_loadbzw4_pi : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_2Imm:$Ii),
 "$Rdd32 = memubh($Rx32++#$Ii)",
-tc_65dc7cc4, TypeLD>, Enc_71f1b4 {
+tc_2fc0c436, TypeLD>, Enc_71f1b4 {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011010101;
 let addrMode = PostInc;
@@ -8831,7 +9168,7 @@ def L2_loadbzw4_pr : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rdd32 = memubh($Rx32++$Mu2)",
-tc_65dc7cc4, TypeLD>, Enc_7eee72 {
+tc_2fc0c436, TypeLD>, Enc_7eee72 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011100101;
 let addrMode = PostInc;
@@ -8843,7 +9180,7 @@ def L2_loadbzw4_zomap : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = memubh($Rs32)",
-tc_bf6fa601, TypeMAPPING> {
+tc_7f881c76, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -8851,7 +9188,7 @@ def L2_loadrb_io : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rd32 = memb($Rs32+#$Ii)",
-tc_bf6fa601, TypeLD>, Enc_211aaa, AddrModeRel {
+tc_7f881c76, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1000;
 let Inst{31-27} = 0b10010;
 let hasNewValue = 1;
@@ -8872,7 +9209,7 @@ def L2_loadrb_pbr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memb($Rx32++$Mu2:brev)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011111000;
 let hasNewValue = 1;
@@ -8885,7 +9222,7 @@ def L2_loadrb_pci : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
 "$Rd32 = memb($Rx32++#$Ii:circ($Mu2))",
-tc_3eab77bd, TypeLD>, Enc_e0a47a {
+tc_4403ca65, TypeLD>, Enc_e0a47a {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011001000;
 let hasNewValue = 1;
@@ -8900,7 +9237,7 @@ def L2_loadrb_pcr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memb($Rx32++I:circ($Mu2))",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011001000;
 let hasNewValue = 1;
@@ -8915,7 +9252,7 @@ def L2_loadrb_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_0Imm:$Ii),
 "$Rd32 = memb($Rx32++#$Ii)",
-tc_65dc7cc4, TypeLD>, Enc_222336, PredNewRel {
+tc_2fc0c436, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011011000;
 let hasNewValue = 1;
@@ -8923,6 +9260,7 @@ let opNewValue = 0;
 let addrMode = PostInc;
 let accessSize = ByteAccess;
 let mayLoad = 1;
+let CextOpcode = "L2_loadrb";
 let BaseOpcode = "L2_loadrb_pi";
 let isPredicable = 1;
 let Constraints = "$Rx32 = $Rx32in";
@@ -8931,7 +9269,7 @@ def L2_loadrb_pr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memb($Rx32++$Mu2)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011101000;
 let hasNewValue = 1;
@@ -8945,7 +9283,7 @@ def L2_loadrb_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = memb($Rs32)",
-tc_bf6fa601, TypeMAPPING> {
+tc_7f881c76, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -8955,7 +9293,7 @@ def L2_loadrbgp : HInst<
 (outs IntRegs:$Rd32),
 (ins u32_0Imm:$Ii),
 "$Rd32 = memb(gp+#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_25bef0, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
 let Inst{24-21} = 0b1000;
 let Inst{31-27} = 0b01001;
 let hasNewValue = 1;
@@ -8974,7 +9312,7 @@ def L2_loadrd_io : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, s29_3Imm:$Ii),
 "$Rdd32 = memd($Rs32+#$Ii)",
-tc_bf6fa601, TypeLD>, Enc_fa3ba4, AddrModeRel {
+tc_7f881c76, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1110;
 let Inst{31-27} = 0b10010;
 let addrMode = BaseImmOffset;
@@ -8993,7 +9331,7 @@ def L2_loadrd_pbr : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rdd32 = memd($Rx32++$Mu2:brev)",
-tc_65dc7cc4, TypeLD>, Enc_7eee72 {
+tc_2fc0c436, TypeLD>, Enc_7eee72 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011111110;
 let accessSize = DoubleWordAccess;
@@ -9004,7 +9342,7 @@ def L2_loadrd_pci : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2),
 "$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))",
-tc_3eab77bd, TypeLD>, Enc_b05839 {
+tc_4403ca65, TypeLD>, Enc_b05839 {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011001110;
 let addrMode = PostInc;
@@ -9017,7 +9355,7 @@ def L2_loadrd_pcr : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rdd32 = memd($Rx32++I:circ($Mu2))",
-tc_65dc7cc4, TypeLD>, Enc_7eee72 {
+tc_2fc0c436, TypeLD>, Enc_7eee72 {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011001110;
 let addrMode = PostInc;
@@ -9030,12 +9368,13 @@ def L2_loadrd_pi : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_3Imm:$Ii),
 "$Rdd32 = memd($Rx32++#$Ii)",
-tc_65dc7cc4, TypeLD>, Enc_5bdd42, PredNewRel {
+tc_2fc0c436, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011011110;
 let addrMode = PostInc;
 let accessSize = DoubleWordAccess;
 let mayLoad = 1;
+let CextOpcode = "L2_loadrd";
 let BaseOpcode = "L2_loadrd_pi";
 let isPredicable = 1;
 let Constraints = "$Rx32 = $Rx32in";
@@ -9044,7 +9383,7 @@ def L2_loadrd_pr : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rdd32 = memd($Rx32++$Mu2)",
-tc_65dc7cc4, TypeLD>, Enc_7eee72 {
+tc_2fc0c436, TypeLD>, Enc_7eee72 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011101110;
 let addrMode = PostInc;
@@ -9056,7 +9395,7 @@ def L2_loadrd_zomap : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = memd($Rs32)",
-tc_bf6fa601, TypeMAPPING> {
+tc_7f881c76, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -9064,7 +9403,7 @@ def L2_loadrdgp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins u29_3Imm:$Ii),
 "$Rdd32 = memd(gp+#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_509701, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_509701, AddrModeRel {
 let Inst{24-21} = 0b1110;
 let Inst{31-27} = 0b01001;
 let accessSize = DoubleWordAccess;
@@ -9081,7 +9420,7 @@ def L2_loadrh_io : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
 "$Rd32 = memh($Rs32+#$Ii)",
-tc_bf6fa601, TypeLD>, Enc_de0214, AddrModeRel {
+tc_7f881c76, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1010;
 let Inst{31-27} = 0b10010;
 let hasNewValue = 1;
@@ -9102,7 +9441,7 @@ def L2_loadrh_pbr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memh($Rx32++$Mu2:brev)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011111010;
 let hasNewValue = 1;
@@ -9115,7 +9454,7 @@ def L2_loadrh_pci : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
 "$Rd32 = memh($Rx32++#$Ii:circ($Mu2))",
-tc_3eab77bd, TypeLD>, Enc_e83554 {
+tc_4403ca65, TypeLD>, Enc_e83554 {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011001010;
 let hasNewValue = 1;
@@ -9130,7 +9469,7 @@ def L2_loadrh_pcr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memh($Rx32++I:circ($Mu2))",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011001010;
 let hasNewValue = 1;
@@ -9145,7 +9484,7 @@ def L2_loadrh_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
 "$Rd32 = memh($Rx32++#$Ii)",
-tc_65dc7cc4, TypeLD>, Enc_152467, PredNewRel {
+tc_2fc0c436, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011011010;
 let hasNewValue = 1;
@@ -9153,6 +9492,7 @@ let opNewValue = 0;
 let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
+let CextOpcode = "L2_loadrh";
 let BaseOpcode = "L2_loadrh_pi";
 let isPredicable = 1;
 let Constraints = "$Rx32 = $Rx32in";
@@ -9161,7 +9501,7 @@ def L2_loadrh_pr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memh($Rx32++$Mu2)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011101010;
 let hasNewValue = 1;
@@ -9175,7 +9515,7 @@ def L2_loadrh_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = memh($Rs32)",
-tc_bf6fa601, TypeMAPPING> {
+tc_7f881c76, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -9185,7 +9525,7 @@ def L2_loadrhgp : HInst<
 (outs IntRegs:$Rd32),
 (ins u31_1Imm:$Ii),
 "$Rd32 = memh(gp+#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_8df4be, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
 let Inst{24-21} = 0b1010;
 let Inst{31-27} = 0b01001;
 let hasNewValue = 1;
@@ -9204,7 +9544,7 @@ def L2_loadri_io : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s30_2Imm:$Ii),
 "$Rd32 = memw($Rs32+#$Ii)",
-tc_bf6fa601, TypeLD>, Enc_2a3787, AddrModeRel {
+tc_7f881c76, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1100;
 let Inst{31-27} = 0b10010;
 let hasNewValue = 1;
@@ -9225,7 +9565,7 @@ def L2_loadri_pbr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memw($Rx32++$Mu2:brev)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011111100;
 let hasNewValue = 1;
@@ -9238,7 +9578,7 @@ def L2_loadri_pci : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
 "$Rd32 = memw($Rx32++#$Ii:circ($Mu2))",
-tc_3eab77bd, TypeLD>, Enc_27fd0e {
+tc_4403ca65, TypeLD>, Enc_27fd0e {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011001100;
 let hasNewValue = 1;
@@ -9253,7 +9593,7 @@ def L2_loadri_pcr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memw($Rx32++I:circ($Mu2))",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011001100;
 let hasNewValue = 1;
@@ -9268,7 +9608,7 @@ def L2_loadri_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_2Imm:$Ii),
 "$Rd32 = memw($Rx32++#$Ii)",
-tc_65dc7cc4, TypeLD>, Enc_3d920a, PredNewRel {
+tc_2fc0c436, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011011100;
 let hasNewValue = 1;
@@ -9276,6 +9616,7 @@ let opNewValue = 0;
 let addrMode = PostInc;
 let accessSize = WordAccess;
 let mayLoad = 1;
+let CextOpcode = "L2_loadri";
 let BaseOpcode = "L2_loadri_pi";
 let isPredicable = 1;
 let Constraints = "$Rx32 = $Rx32in";
@@ -9284,7 +9625,7 @@ def L2_loadri_pr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memw($Rx32++$Mu2)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011101100;
 let hasNewValue = 1;
@@ -9298,7 +9639,7 @@ def L2_loadri_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = memw($Rs32)",
-tc_bf6fa601, TypeMAPPING> {
+tc_7f881c76, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -9308,7 +9649,7 @@ def L2_loadrigp : HInst<
 (outs IntRegs:$Rd32),
 (ins u30_2Imm:$Ii),
 "$Rd32 = memw(gp+#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
 let Inst{24-21} = 0b1100;
 let Inst{31-27} = 0b01001;
 let hasNewValue = 1;
@@ -9327,7 +9668,7 @@ def L2_loadrub_io : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rd32 = memub($Rs32+#$Ii)",
-tc_bf6fa601, TypeLD>, Enc_211aaa, AddrModeRel {
+tc_7f881c76, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1001;
 let Inst{31-27} = 0b10010;
 let hasNewValue = 1;
@@ -9348,7 +9689,7 @@ def L2_loadrub_pbr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memub($Rx32++$Mu2:brev)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011111001;
 let hasNewValue = 1;
@@ -9361,7 +9702,7 @@ def L2_loadrub_pci : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
 "$Rd32 = memub($Rx32++#$Ii:circ($Mu2))",
-tc_3eab77bd, TypeLD>, Enc_e0a47a {
+tc_4403ca65, TypeLD>, Enc_e0a47a {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011001001;
 let hasNewValue = 1;
@@ -9376,7 +9717,7 @@ def L2_loadrub_pcr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memub($Rx32++I:circ($Mu2))",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011001001;
 let hasNewValue = 1;
@@ -9391,7 +9732,7 @@ def L2_loadrub_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_0Imm:$Ii),
 "$Rd32 = memub($Rx32++#$Ii)",
-tc_65dc7cc4, TypeLD>, Enc_222336, PredNewRel {
+tc_2fc0c436, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011011001;
 let hasNewValue = 1;
@@ -9399,6 +9740,7 @@ let opNewValue = 0;
 let addrMode = PostInc;
 let accessSize = ByteAccess;
 let mayLoad = 1;
+let CextOpcode = "L2_loadrub";
 let BaseOpcode = "L2_loadrub_pi";
 let isPredicable = 1;
 let Constraints = "$Rx32 = $Rx32in";
@@ -9407,7 +9749,7 @@ def L2_loadrub_pr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memub($Rx32++$Mu2)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011101001;
 let hasNewValue = 1;
@@ -9421,7 +9763,7 @@ def L2_loadrub_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = memub($Rs32)",
-tc_bf6fa601, TypeMAPPING> {
+tc_7f881c76, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -9431,7 +9773,7 @@ def L2_loadrubgp : HInst<
 (outs IntRegs:$Rd32),
 (ins u32_0Imm:$Ii),
 "$Rd32 = memub(gp+#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_25bef0, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
 let Inst{24-21} = 0b1001;
 let Inst{31-27} = 0b01001;
 let hasNewValue = 1;
@@ -9450,7 +9792,7 @@ def L2_loadruh_io : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
 "$Rd32 = memuh($Rs32+#$Ii)",
-tc_bf6fa601, TypeLD>, Enc_de0214, AddrModeRel {
+tc_7f881c76, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1011;
 let Inst{31-27} = 0b10010;
 let hasNewValue = 1;
@@ -9471,7 +9813,7 @@ def L2_loadruh_pbr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memuh($Rx32++$Mu2:brev)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011111011;
 let hasNewValue = 1;
@@ -9484,7 +9826,7 @@ def L2_loadruh_pci : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
 "$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))",
-tc_3eab77bd, TypeLD>, Enc_e83554 {
+tc_4403ca65, TypeLD>, Enc_e83554 {
 let Inst{12-9} = 0b0000;
 let Inst{31-21} = 0b10011001011;
 let hasNewValue = 1;
@@ -9499,7 +9841,7 @@ def L2_loadruh_pcr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memuh($Rx32++I:circ($Mu2))",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00010000;
 let Inst{31-21} = 0b10011001011;
 let hasNewValue = 1;
@@ -9514,7 +9856,7 @@ def L2_loadruh_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
 "$Rd32 = memuh($Rx32++#$Ii)",
-tc_65dc7cc4, TypeLD>, Enc_152467, PredNewRel {
+tc_2fc0c436, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
 let Inst{13-9} = 0b00000;
 let Inst{31-21} = 0b10011011011;
 let hasNewValue = 1;
@@ -9522,6 +9864,7 @@ let opNewValue = 0;
 let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
+let CextOpcode = "L2_loadruh";
 let BaseOpcode = "L2_loadruh_pi";
 let isPredicable = 1;
 let Constraints = "$Rx32 = $Rx32in";
@@ -9530,7 +9873,7 @@ def L2_loadruh_pr : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Rd32 = memuh($Rx32++$Mu2)",
-tc_65dc7cc4, TypeLD>, Enc_74d4e5 {
+tc_2fc0c436, TypeLD>, Enc_74d4e5 {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b10011101011;
 let hasNewValue = 1;
@@ -9544,7 +9887,7 @@ def L2_loadruh_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = memuh($Rs32)",
-tc_bf6fa601, TypeMAPPING> {
+tc_7f881c76, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -9554,7 +9897,7 @@ def L2_loadruhgp : HInst<
 (outs IntRegs:$Rd32),
 (ins u31_1Imm:$Ii),
 "$Rd32 = memuh(gp+#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_8df4be, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
 let Inst{24-21} = 0b1011;
 let Inst{31-27} = 0b01001;
 let hasNewValue = 1;
@@ -9573,7 +9916,7 @@ def L2_loadw_locked : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = memw_locked($Rs32)",
-tc_29c14515, TypeLD>, Enc_5e2823 {
+tc_6aa5711a, TypeLD>, Enc_5e2823 {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10010010000;
 let hasNewValue = 1;
@@ -9586,7 +9929,7 @@ def L2_ploadrbf_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
 "if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_a21d47, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000101000;
 let isPredicated = 1;
@@ -9608,7 +9951,7 @@ def L2_ploadrbf_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
 "if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_f4413a, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011011000;
 let isPredicated = 1;
@@ -9625,7 +9968,7 @@ def L2_ploadrbf_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4) $Rd32 = memb($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -9635,7 +9978,7 @@ def L2_ploadrbfnew_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_a21d47, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000111000;
 let isPredicated = 1;
@@ -9658,7 +10001,7 @@ def L2_ploadrbfnew_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_f4413a, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011011000;
 let isPredicated = 1;
@@ -9676,7 +10019,7 @@ def L2_ploadrbfnew_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4.new) $Rd32 = memb($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -9686,7 +10029,7 @@ def L2_ploadrbt_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
 "if ($Pt4) $Rd32 = memb($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_a21d47, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000001000;
 let isPredicated = 1;
@@ -9707,7 +10050,7 @@ def L2_ploadrbt_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
 "if ($Pt4) $Rd32 = memb($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_f4413a, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011011000;
 let isPredicated = 1;
@@ -9723,7 +10066,7 @@ def L2_ploadrbt_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4) $Rd32 = memb($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -9733,7 +10076,7 @@ def L2_ploadrbtnew_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_a21d47, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000011000;
 let isPredicated = 1;
@@ -9755,7 +10098,7 @@ def L2_ploadrbtnew_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_f4413a, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011011000;
 let isPredicated = 1;
@@ -9772,7 +10115,7 @@ def L2_ploadrbtnew_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4.new) $Rd32 = memb($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -9782,7 +10125,7 @@ def L2_ploadrdf_io : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
 "if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000101110;
 let isPredicated = 1;
@@ -9802,7 +10145,7 @@ def L2_ploadrdf_pi : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
 "if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_9d1247, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_9d1247, PredNewRel {
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011011110;
 let isPredicated = 1;
@@ -9817,7 +10160,7 @@ def L2_ploadrdf_zomap : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4) $Rdd32 = memd($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -9825,7 +10168,7 @@ def L2_ploadrdfnew_io : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
 "if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000111110;
 let isPredicated = 1;
@@ -9846,7 +10189,7 @@ def L2_ploadrdfnew_pi : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
 "if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_9d1247, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_9d1247, PredNewRel {
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011011110;
 let isPredicated = 1;
@@ -9862,7 +10205,7 @@ def L2_ploadrdfnew_zomap : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4.new) $Rdd32 = memd($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -9870,7 +10213,7 @@ def L2_ploadrdt_io : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
 "if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000001110;
 let isPredicated = 1;
@@ -9889,7 +10232,7 @@ def L2_ploadrdt_pi : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
 "if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_9d1247, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_9d1247, PredNewRel {
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011011110;
 let isPredicated = 1;
@@ -9903,7 +10246,7 @@ def L2_ploadrdt_zomap : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4) $Rdd32 = memd($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -9911,7 +10254,7 @@ def L2_ploadrdtnew_io : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
 "if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000011110;
 let isPredicated = 1;
@@ -9931,7 +10274,7 @@ def L2_ploadrdtnew_pi : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
 "if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_9d1247, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_9d1247, PredNewRel {
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011011110;
 let isPredicated = 1;
@@ -9946,7 +10289,7 @@ def L2_ploadrdtnew_zomap : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4.new) $Rdd32 = memd($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -9954,7 +10297,7 @@ def L2_ploadrhf_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
 "if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_a198f6, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000101010;
 let isPredicated = 1;
@@ -9976,7 +10319,7 @@ def L2_ploadrhf_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
 "if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_733b27, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011011010;
 let isPredicated = 1;
@@ -9993,7 +10336,7 @@ def L2_ploadrhf_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4) $Rd32 = memh($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10003,7 +10346,7 @@ def L2_ploadrhfnew_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_a198f6, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000111010;
 let isPredicated = 1;
@@ -10026,7 +10369,7 @@ def L2_ploadrhfnew_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_733b27, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011011010;
 let isPredicated = 1;
@@ -10044,7 +10387,7 @@ def L2_ploadrhfnew_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4.new) $Rd32 = memh($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10054,7 +10397,7 @@ def L2_ploadrht_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
 "if ($Pt4) $Rd32 = memh($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_a198f6, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000001010;
 let isPredicated = 1;
@@ -10075,7 +10418,7 @@ def L2_ploadrht_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
 "if ($Pt4) $Rd32 = memh($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_733b27, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011011010;
 let isPredicated = 1;
@@ -10091,7 +10434,7 @@ def L2_ploadrht_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4) $Rd32 = memh($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10101,7 +10444,7 @@ def L2_ploadrhtnew_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_a198f6, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000011010;
 let isPredicated = 1;
@@ -10123,7 +10466,7 @@ def L2_ploadrhtnew_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_733b27, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011011010;
 let isPredicated = 1;
@@ -10140,7 +10483,7 @@ def L2_ploadrhtnew_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4.new) $Rd32 = memh($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10150,7 +10493,7 @@ def L2_ploadrif_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
 "if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000101100;
 let isPredicated = 1;
@@ -10172,7 +10515,7 @@ def L2_ploadrif_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
 "if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_b97f71, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_b97f71, PredNewRel {
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011011100;
 let isPredicated = 1;
@@ -10189,7 +10532,7 @@ def L2_ploadrif_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4) $Rd32 = memw($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10199,7 +10542,7 @@ def L2_ploadrifnew_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000111100;
 let isPredicated = 1;
@@ -10222,7 +10565,7 @@ def L2_ploadrifnew_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_b97f71, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_b97f71, PredNewRel {
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011011100;
 let isPredicated = 1;
@@ -10240,7 +10583,7 @@ def L2_ploadrifnew_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4.new) $Rd32 = memw($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10250,7 +10593,7 @@ def L2_ploadrit_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
 "if ($Pt4) $Rd32 = memw($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000001100;
 let isPredicated = 1;
@@ -10271,7 +10614,7 @@ def L2_ploadrit_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
 "if ($Pt4) $Rd32 = memw($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_b97f71, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_b97f71, PredNewRel {
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011011100;
 let isPredicated = 1;
@@ -10287,7 +10630,7 @@ def L2_ploadrit_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4) $Rd32 = memw($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10297,7 +10640,7 @@ def L2_ploadritnew_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000011100;
 let isPredicated = 1;
@@ -10319,7 +10662,7 @@ def L2_ploadritnew_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_b97f71, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_b97f71, PredNewRel {
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011011100;
 let isPredicated = 1;
@@ -10336,7 +10679,7 @@ def L2_ploadritnew_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4.new) $Rd32 = memw($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10346,7 +10689,7 @@ def L2_ploadrubf_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
 "if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_a21d47, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000101001;
 let isPredicated = 1;
@@ -10368,7 +10711,7 @@ def L2_ploadrubf_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
 "if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_f4413a, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011011001;
 let isPredicated = 1;
@@ -10385,7 +10728,7 @@ def L2_ploadrubf_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4) $Rd32 = memub($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10395,7 +10738,7 @@ def L2_ploadrubfnew_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_a21d47, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000111001;
 let isPredicated = 1;
@@ -10418,7 +10761,7 @@ def L2_ploadrubfnew_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_f4413a, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011011001;
 let isPredicated = 1;
@@ -10436,7 +10779,7 @@ def L2_ploadrubfnew_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4.new) $Rd32 = memub($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10446,7 +10789,7 @@ def L2_ploadrubt_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
 "if ($Pt4) $Rd32 = memub($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_a21d47, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000001001;
 let isPredicated = 1;
@@ -10467,7 +10810,7 @@ def L2_ploadrubt_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
 "if ($Pt4) $Rd32 = memub($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_f4413a, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011011001;
 let isPredicated = 1;
@@ -10483,7 +10826,7 @@ def L2_ploadrubt_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4) $Rd32 = memub($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10493,7 +10836,7 @@ def L2_ploadrubtnew_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_a21d47, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000011001;
 let isPredicated = 1;
@@ -10515,7 +10858,7 @@ def L2_ploadrubtnew_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_f4413a, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011011001;
 let isPredicated = 1;
@@ -10532,7 +10875,7 @@ def L2_ploadrubtnew_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4.new) $Rd32 = memub($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10542,7 +10885,7 @@ def L2_ploadruhf_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
 "if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_a198f6, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000101011;
 let isPredicated = 1;
@@ -10564,7 +10907,7 @@ def L2_ploadruhf_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
 "if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_733b27, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011011011;
 let isPredicated = 1;
@@ -10581,7 +10924,7 @@ def L2_ploadruhf_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4) $Rd32 = memuh($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10591,7 +10934,7 @@ def L2_ploadruhfnew_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_a198f6, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000111011;
 let isPredicated = 1;
@@ -10614,7 +10957,7 @@ def L2_ploadruhfnew_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_733b27, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011011011;
 let isPredicated = 1;
@@ -10632,7 +10975,7 @@ def L2_ploadruhfnew_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if (!$Pt4.new) $Rd32 = memuh($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10642,7 +10985,7 @@ def L2_ploadruht_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
 "if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)",
-tc_14da557c, TypeV2LDST>, Enc_a198f6, AddrModeRel {
+tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000001011;
 let isPredicated = 1;
@@ -10663,7 +11006,7 @@ def L2_ploadruht_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
 "if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)",
-tc_ae762521, TypeLD>, Enc_733b27, PredNewRel {
+tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011011011;
 let isPredicated = 1;
@@ -10679,7 +11022,7 @@ def L2_ploadruht_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4) $Rd32 = memuh($Rs32)",
-tc_14da557c, TypeMAPPING> {
+tc_ef52ed71, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10689,7 +11032,7 @@ def L2_ploadruhtnew_io : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
-tc_65dc7cc4, TypeV2LDST>, Enc_a198f6, AddrModeRel {
+tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b01000011011;
 let isPredicated = 1;
@@ -10711,7 +11054,7 @@ def L2_ploadruhtnew_pi : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Rx32),
 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
-tc_e578178f, TypeLD>, Enc_733b27, PredNewRel {
+tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011011011;
 let isPredicated = 1;
@@ -10728,7 +11071,7 @@ def L2_ploadruhtnew_zomap : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, IntRegs:$Rs32),
 "if ($Pt4.new) $Rd32 = memuh($Rs32)",
-tc_65dc7cc4, TypeMAPPING> {
+tc_2fc0c436, TypeMAPPING> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -10738,13 +11081,14 @@ def L4_add_memopb_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
 "memb($Rs32+#$Ii) += $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_d44e31 {
+tc_44126683, TypeV4LDST>, Enc_d44e31 {
 let Inst{6-5} = 0b00;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110000;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -10756,7 +11100,7 @@ def L4_add_memopb_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memb($Rs32) += $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -10764,13 +11108,14 @@ def L4_add_memoph_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "memh($Rs32+#$Ii) += $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_163a3c {
+tc_44126683, TypeV4LDST>, Enc_163a3c {
 let Inst{6-5} = 0b00;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110001;
 let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -10782,7 +11127,7 @@ def L4_add_memoph_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memh($Rs32) += $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -10790,13 +11135,14 @@ def L4_add_memopw_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
 "memw($Rs32+#$Ii) += $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_226535 {
+tc_44126683, TypeV4LDST>, Enc_226535 {
 let Inst{6-5} = 0b00;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110010;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -10808,7 +11154,7 @@ def L4_add_memopw_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memw($Rs32) += $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -10816,13 +11162,14 @@ def L4_and_memopb_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
 "memb($Rs32+#$Ii) &= $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_d44e31 {
+tc_44126683, TypeV4LDST>, Enc_d44e31 {
 let Inst{6-5} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110000;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -10834,7 +11181,7 @@ def L4_and_memopb_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memb($Rs32) &= $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -10842,13 +11189,14 @@ def L4_and_memoph_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "memh($Rs32+#$Ii) &= $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_163a3c {
+tc_44126683, TypeV4LDST>, Enc_163a3c {
 let Inst{6-5} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110001;
 let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -10860,7 +11208,7 @@ def L4_and_memoph_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memh($Rs32) &= $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -10868,13 +11216,14 @@ def L4_and_memopw_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
 "memw($Rs32+#$Ii) &= $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_226535 {
+tc_44126683, TypeV4LDST>, Enc_226535 {
 let Inst{6-5} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110010;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -10886,7 +11235,7 @@ def L4_and_memopw_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memw($Rs32) &= $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -10894,13 +11243,14 @@ def L4_iadd_memopb_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
 "memb($Rs32+#$Ii) += #$II",
-tc_da79106e, TypeV4LDST>, Enc_46c951 {
+tc_44126683, TypeV4LDST>, Enc_46c951 {
 let Inst{6-5} = 0b00;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111000;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -10912,7 +11262,7 @@ def L4_iadd_memopb_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memb($Rs32) += #$II",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -10920,13 +11270,14 @@ def L4_iadd_memoph_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
 "memh($Rs32+#$Ii) += #$II",
-tc_da79106e, TypeV4LDST>, Enc_e66a97 {
+tc_44126683, TypeV4LDST>, Enc_e66a97 {
 let Inst{6-5} = 0b00;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111001;
 let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -10938,7 +11289,7 @@ def L4_iadd_memoph_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memh($Rs32) += #$II",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -10946,13 +11297,14 @@ def L4_iadd_memopw_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
 "memw($Rs32+#$Ii) += #$II",
-tc_da79106e, TypeV4LDST>, Enc_84b2cd {
+tc_44126683, TypeV4LDST>, Enc_84b2cd {
 let Inst{6-5} = 0b00;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111010;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -10964,7 +11316,7 @@ def L4_iadd_memopw_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memw($Rs32) += #$II",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -10972,13 +11324,14 @@ def L4_iand_memopb_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
 "memb($Rs32+#$Ii) = clrbit(#$II)",
-tc_da79106e, TypeV4LDST>, Enc_46c951 {
+tc_44126683, TypeV4LDST>, Enc_46c951 {
 let Inst{6-5} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111000;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -10990,7 +11343,7 @@ def L4_iand_memopb_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memb($Rs32) = clrbit(#$II)",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -10998,13 +11351,14 @@ def L4_iand_memoph_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
 "memh($Rs32+#$Ii) = clrbit(#$II)",
-tc_da79106e, TypeV4LDST>, Enc_e66a97 {
+tc_44126683, TypeV4LDST>, Enc_e66a97 {
 let Inst{6-5} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111001;
 let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11016,7 +11370,7 @@ def L4_iand_memoph_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memh($Rs32) = clrbit(#$II)",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11024,13 +11378,14 @@ def L4_iand_memopw_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
 "memw($Rs32+#$Ii) = clrbit(#$II)",
-tc_da79106e, TypeV4LDST>, Enc_84b2cd {
+tc_44126683, TypeV4LDST>, Enc_84b2cd {
 let Inst{6-5} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111010;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11042,7 +11397,7 @@ def L4_iand_memopw_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memw($Rs32) = clrbit(#$II)",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11050,13 +11405,14 @@ def L4_ior_memopb_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
 "memb($Rs32+#$Ii) = setbit(#$II)",
-tc_da79106e, TypeV4LDST>, Enc_46c951 {
+tc_44126683, TypeV4LDST>, Enc_46c951 {
 let Inst{6-5} = 0b11;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111000;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11068,7 +11424,7 @@ def L4_ior_memopb_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memb($Rs32) = setbit(#$II)",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11076,13 +11432,14 @@ def L4_ior_memoph_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
 "memh($Rs32+#$Ii) = setbit(#$II)",
-tc_da79106e, TypeV4LDST>, Enc_e66a97 {
+tc_44126683, TypeV4LDST>, Enc_e66a97 {
 let Inst{6-5} = 0b11;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111001;
 let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11094,7 +11451,7 @@ def L4_ior_memoph_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memh($Rs32) = setbit(#$II)",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11102,13 +11459,14 @@ def L4_ior_memopw_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
 "memw($Rs32+#$Ii) = setbit(#$II)",
-tc_da79106e, TypeV4LDST>, Enc_84b2cd {
+tc_44126683, TypeV4LDST>, Enc_84b2cd {
 let Inst{6-5} = 0b11;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111010;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11120,7 +11478,7 @@ def L4_ior_memopw_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memw($Rs32) = setbit(#$II)",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11128,13 +11486,14 @@ def L4_isub_memopb_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
 "memb($Rs32+#$Ii) -= #$II",
-tc_da79106e, TypeV4LDST>, Enc_46c951 {
+tc_44126683, TypeV4LDST>, Enc_46c951 {
 let Inst{6-5} = 0b01;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111000;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11146,7 +11505,7 @@ def L4_isub_memopb_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memb($Rs32) -= #$II",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11154,13 +11513,14 @@ def L4_isub_memoph_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
 "memh($Rs32+#$Ii) -= #$II",
-tc_da79106e, TypeV4LDST>, Enc_e66a97 {
+tc_44126683, TypeV4LDST>, Enc_e66a97 {
 let Inst{6-5} = 0b01;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111001;
 let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11172,7 +11532,7 @@ def L4_isub_memoph_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memh($Rs32) -= #$II",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11180,13 +11540,14 @@ def L4_isub_memopw_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
 "memw($Rs32+#$Ii) -= #$II",
-tc_da79106e, TypeV4LDST>, Enc_84b2cd {
+tc_44126683, TypeV4LDST>, Enc_84b2cd {
 let Inst{6-5} = 0b01;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111111010;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11198,7 +11559,7 @@ def L4_isub_memopw_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, u5_0Imm:$II),
 "memw($Rs32) -= #$II",
-tc_da79106e, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11206,12 +11567,10 @@ def L4_loadalignb_ap : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Re32),
 (ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
 "$Ryy32 = memb_fifo($Re32=#$II)",
-tc_261d9b78, TypeLD>, Enc_f394d3 {
+tc_5acef64a, TypeLD>, Enc_f394d3 {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011010100;
-let hasNewValue = 1;
-let opNewValue = 1;
 let addrMode = AbsoluteSet;
 let accessSize = ByteAccess;
 let mayLoad = 1;
@@ -11228,7 +11587,7 @@ def L4_loadalignb_ur : HInst<
 (outs DoubleRegs:$Ryy32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)",
-tc_baccf077, TypeLD>, Enc_04c959 {
+tc_0cd51c76, TypeLD>, Enc_04c959 {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011100100;
 let addrMode = BaseLongOffset;
@@ -11248,12 +11607,10 @@ def L4_loadalignh_ap : HInst<
 (outs DoubleRegs:$Ryy32, IntRegs:$Re32),
 (ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
 "$Ryy32 = memh_fifo($Re32=#$II)",
-tc_261d9b78, TypeLD>, Enc_f394d3 {
+tc_5acef64a, TypeLD>, Enc_f394d3 {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011010010;
-let hasNewValue = 1;
-let opNewValue = 1;
 let addrMode = AbsoluteSet;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
@@ -11270,7 +11627,7 @@ def L4_loadalignh_ur : HInst<
 (outs DoubleRegs:$Ryy32),
 (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)",
-tc_baccf077, TypeLD>, Enc_04c959 {
+tc_0cd51c76, TypeLD>, Enc_04c959 {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011100010;
 let addrMode = BaseLongOffset;
@@ -11290,14 +11647,12 @@ def L4_loadbsw2_ap : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Re32),
 (ins u32_0Imm:$II),
 "$Rd32 = membh($Re32=#$II)",
-tc_b5f5a094, TypeLD>, Enc_323f2d {
+tc_b77c481f, TypeLD>, Enc_323f2d {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011010001;
 let hasNewValue = 1;
 let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
 let addrMode = AbsoluteSet;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
@@ -11313,7 +11668,7 @@ def L4_loadbsw2_ur : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Rd32 = membh($Rt32<<#$Ii+#$II)",
-tc_7d9a56cd, TypeLD>, Enc_4f677b {
+tc_cf47a43f, TypeLD>, Enc_4f677b {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011100001;
 let hasNewValue = 1;
@@ -11334,12 +11689,10 @@ def L4_loadbsw4_ap : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Re32),
 (ins u32_0Imm:$II),
 "$Rdd32 = membh($Re32=#$II)",
-tc_b5f5a094, TypeLD>, Enc_7fa7f6 {
+tc_b77c481f, TypeLD>, Enc_7fa7f6 {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011010111;
-let hasNewValue = 1;
-let opNewValue = 1;
 let addrMode = AbsoluteSet;
 let accessSize = WordAccess;
 let mayLoad = 1;
@@ -11355,7 +11708,7 @@ def L4_loadbsw4_ur : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Rdd32 = membh($Rt32<<#$Ii+#$II)",
-tc_7d9a56cd, TypeLD>, Enc_6185fe {
+tc_cf47a43f, TypeLD>, Enc_6185fe {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011100111;
 let addrMode = BaseLongOffset;
@@ -11374,14 +11727,12 @@ def L4_loadbzw2_ap : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Re32),
 (ins u32_0Imm:$II),
 "$Rd32 = memubh($Re32=#$II)",
-tc_b5f5a094, TypeLD>, Enc_323f2d {
+tc_b77c481f, TypeLD>, Enc_323f2d {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011010011;
 let hasNewValue = 1;
 let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
 let addrMode = AbsoluteSet;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
@@ -11397,7 +11748,7 @@ def L4_loadbzw2_ur : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Rd32 = memubh($Rt32<<#$Ii+#$II)",
-tc_7d9a56cd, TypeLD>, Enc_4f677b {
+tc_cf47a43f, TypeLD>, Enc_4f677b {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011100011;
 let hasNewValue = 1;
@@ -11418,12 +11769,10 @@ def L4_loadbzw4_ap : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Re32),
 (ins u32_0Imm:$II),
 "$Rdd32 = memubh($Re32=#$II)",
-tc_b5f5a094, TypeLD>, Enc_7fa7f6 {
+tc_b77c481f, TypeLD>, Enc_7fa7f6 {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011010101;
-let hasNewValue = 1;
-let opNewValue = 1;
 let addrMode = AbsoluteSet;
 let accessSize = WordAccess;
 let mayLoad = 1;
@@ -11439,7 +11788,7 @@ def L4_loadbzw4_ur : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Rdd32 = memubh($Rt32<<#$Ii+#$II)",
-tc_7d9a56cd, TypeLD>, Enc_6185fe {
+tc_cf47a43f, TypeLD>, Enc_6185fe {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011100101;
 let addrMode = BaseLongOffset;
@@ -11458,7 +11807,7 @@ def L4_loadd_locked : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = memd_locked($Rs32)",
-tc_29c14515, TypeLD>, Enc_3a3d62 {
+tc_6aa5711a, TypeLD>, Enc_3a3d62 {
 let Inst{13-5} = 0b010000000;
 let Inst{31-21} = 0b10010010000;
 let accessSize = DoubleWordAccess;
@@ -11469,14 +11818,12 @@ def L4_loadrb_ap : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Re32),
 (ins u32_0Imm:$II),
 "$Rd32 = memb($Re32=#$II)",
-tc_b5f5a094, TypeLD>, Enc_323f2d {
+tc_b77c481f, TypeLD>, Enc_323f2d {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011011000;
 let hasNewValue = 1;
 let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
 let addrMode = AbsoluteSet;
 let accessSize = ByteAccess;
 let mayLoad = 1;
@@ -11492,7 +11839,7 @@ def L4_loadrb_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "$Rd32 = memb($Rs32+$Rt32<<#$Ii)",
-tc_5625c6c1, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
+tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111010000;
 let hasNewValue = 1;
@@ -11509,7 +11856,7 @@ def L4_loadrb_ur : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Rd32 = memb($Rt32<<#$Ii+#$II)",
-tc_7d9a56cd, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
+tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011101000;
 let hasNewValue = 1;
@@ -11531,12 +11878,10 @@ def L4_loadrd_ap : HInst<
 (outs DoubleRegs:$Rdd32, IntRegs:$Re32),
 (ins u32_0Imm:$II),
 "$Rdd32 = memd($Re32=#$II)",
-tc_b5f5a094, TypeLD>, Enc_7fa7f6 {
+tc_b77c481f, TypeLD>, Enc_7fa7f6 {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011011110;
-let hasNewValue = 1;
-let opNewValue = 1;
 let addrMode = AbsoluteSet;
 let accessSize = DoubleWordAccess;
 let mayLoad = 1;
@@ -11552,7 +11897,7 @@ def L4_loadrd_rr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "$Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
-tc_5625c6c1, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl {
+tc_f47d212f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111010110;
 let addrMode = BaseRegOffset;
@@ -11567,7 +11912,7 @@ def L4_loadrd_ur : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Rdd32 = memd($Rt32<<#$Ii+#$II)",
-tc_7d9a56cd, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl {
+tc_cf47a43f, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011101110;
 let addrMode = BaseLongOffset;
@@ -11587,14 +11932,12 @@ def L4_loadrh_ap : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Re32),
 (ins u32_0Imm:$II),
 "$Rd32 = memh($Re32=#$II)",
-tc_b5f5a094, TypeLD>, Enc_323f2d {
+tc_b77c481f, TypeLD>, Enc_323f2d {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011011010;
 let hasNewValue = 1;
 let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
 let addrMode = AbsoluteSet;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
@@ -11610,7 +11953,7 @@ def L4_loadrh_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "$Rd32 = memh($Rs32+$Rt32<<#$Ii)",
-tc_5625c6c1, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
+tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111010010;
 let hasNewValue = 1;
@@ -11627,7 +11970,7 @@ def L4_loadrh_ur : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Rd32 = memh($Rt32<<#$Ii+#$II)",
-tc_7d9a56cd, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
+tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011101010;
 let hasNewValue = 1;
@@ -11649,14 +11992,12 @@ def L4_loadri_ap : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Re32),
 (ins u32_0Imm:$II),
 "$Rd32 = memw($Re32=#$II)",
-tc_b5f5a094, TypeLD>, Enc_323f2d {
+tc_b77c481f, TypeLD>, Enc_323f2d {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011011100;
 let hasNewValue = 1;
 let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
 let addrMode = AbsoluteSet;
 let accessSize = WordAccess;
 let mayLoad = 1;
@@ -11672,7 +12013,7 @@ def L4_loadri_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "$Rd32 = memw($Rs32+$Rt32<<#$Ii)",
-tc_5625c6c1, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
+tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111010100;
 let hasNewValue = 1;
@@ -11689,7 +12030,7 @@ def L4_loadri_ur : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Rd32 = memw($Rt32<<#$Ii+#$II)",
-tc_7d9a56cd, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
+tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011101100;
 let hasNewValue = 1;
@@ -11711,14 +12052,12 @@ def L4_loadrub_ap : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Re32),
 (ins u32_0Imm:$II),
 "$Rd32 = memub($Re32=#$II)",
-tc_b5f5a094, TypeLD>, Enc_323f2d {
+tc_b77c481f, TypeLD>, Enc_323f2d {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011011001;
 let hasNewValue = 1;
 let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
 let addrMode = AbsoluteSet;
 let accessSize = ByteAccess;
 let mayLoad = 1;
@@ -11734,7 +12073,7 @@ def L4_loadrub_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "$Rd32 = memub($Rs32+$Rt32<<#$Ii)",
-tc_5625c6c1, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
+tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111010001;
 let hasNewValue = 1;
@@ -11751,7 +12090,7 @@ def L4_loadrub_ur : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Rd32 = memub($Rt32<<#$Ii+#$II)",
-tc_7d9a56cd, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
+tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011101001;
 let hasNewValue = 1;
@@ -11773,14 +12112,12 @@ def L4_loadruh_ap : HInst<
 (outs IntRegs:$Rd32, IntRegs:$Re32),
 (ins u32_0Imm:$II),
 "$Rd32 = memuh($Re32=#$II)",
-tc_b5f5a094, TypeLD>, Enc_323f2d {
+tc_b77c481f, TypeLD>, Enc_323f2d {
 let Inst{7-7} = 0b0;
 let Inst{13-12} = 0b01;
 let Inst{31-21} = 0b10011011011;
 let hasNewValue = 1;
 let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
 let addrMode = AbsoluteSet;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
@@ -11796,7 +12133,7 @@ def L4_loadruh_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "$Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
-tc_5625c6c1, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
+tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111010011;
 let hasNewValue = 1;
@@ -11813,7 +12150,7 @@ def L4_loadruh_ur : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
 "$Rd32 = memuh($Rt32<<#$Ii+#$II)",
-tc_7d9a56cd, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
+tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
 let Inst{12-12} = 0b1;
 let Inst{31-21} = 0b10011101011;
 let hasNewValue = 1;
@@ -11835,13 +12172,14 @@ def L4_or_memopb_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
 "memb($Rs32+#$Ii) |= $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_d44e31 {
+tc_44126683, TypeV4LDST>, Enc_d44e31 {
 let Inst{6-5} = 0b11;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110000;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11853,7 +12191,7 @@ def L4_or_memopb_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memb($Rs32) |= $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11861,13 +12199,14 @@ def L4_or_memoph_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "memh($Rs32+#$Ii) |= $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_163a3c {
+tc_44126683, TypeV4LDST>, Enc_163a3c {
 let Inst{6-5} = 0b11;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110001;
 let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11879,7 +12218,7 @@ def L4_or_memoph_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memh($Rs32) |= $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11887,13 +12226,14 @@ def L4_or_memopw_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
 "memw($Rs32+#$Ii) |= $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_226535 {
+tc_44126683, TypeV4LDST>, Enc_226535 {
 let Inst{6-5} = 0b11;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110010;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -11905,7 +12245,7 @@ def L4_or_memopw_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memw($Rs32) |= $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -11913,7 +12253,7 @@ def L4_ploadrbf_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4) $Rd32 = memb(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011111000;
@@ -11938,7 +12278,7 @@ def L4_ploadrbf_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110001000;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -11955,7 +12295,7 @@ def L4_ploadrbfnew_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memb(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011111000;
@@ -11981,7 +12321,7 @@ def L4_ploadrbfnew_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110011000;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -11999,7 +12339,7 @@ def L4_ploadrbt_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4) $Rd32 = memb(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011111000;
@@ -12023,7 +12363,7 @@ def L4_ploadrbt_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110000000;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -12039,7 +12379,7 @@ def L4_ploadrbtnew_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memb(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011111000;
@@ -12064,7 +12404,7 @@ def L4_ploadrbtnew_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110010000;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -12081,7 +12421,7 @@ def L4_ploadrdf_abs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4) $Rdd32 = memd(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2a7b91, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2a7b91, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011111110;
@@ -12104,7 +12444,7 @@ def L4_ploadrdf_rr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_98c0b8, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_98c0b8, AddrModeRel {
 let Inst{31-21} = 0b00110001110;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -12119,7 +12459,7 @@ def L4_ploadrdfnew_abs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4.new) $Rdd32 = memd(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2a7b91, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2a7b91, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011111110;
@@ -12143,7 +12483,7 @@ def L4_ploadrdfnew_rr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_98c0b8, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_98c0b8, AddrModeRel {
 let Inst{31-21} = 0b00110011110;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -12159,7 +12499,7 @@ def L4_ploadrdt_abs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4) $Rdd32 = memd(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2a7b91, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2a7b91, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011111110;
@@ -12181,7 +12521,7 @@ def L4_ploadrdt_rr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_98c0b8, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_98c0b8, AddrModeRel {
 let Inst{31-21} = 0b00110000110;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -12195,7 +12535,7 @@ def L4_ploadrdtnew_abs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4.new) $Rdd32 = memd(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2a7b91, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2a7b91, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011111110;
@@ -12218,7 +12558,7 @@ def L4_ploadrdtnew_rr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_98c0b8, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_98c0b8, AddrModeRel {
 let Inst{31-21} = 0b00110010110;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -12233,7 +12573,7 @@ def L4_ploadrhf_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4) $Rd32 = memh(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011111010;
@@ -12258,7 +12598,7 @@ def L4_ploadrhf_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110001010;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -12275,7 +12615,7 @@ def L4_ploadrhfnew_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memh(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011111010;
@@ -12301,7 +12641,7 @@ def L4_ploadrhfnew_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110011010;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -12319,7 +12659,7 @@ def L4_ploadrht_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4) $Rd32 = memh(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011111010;
@@ -12343,7 +12683,7 @@ def L4_ploadrht_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110000010;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -12359,7 +12699,7 @@ def L4_ploadrhtnew_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memh(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011111010;
@@ -12384,7 +12724,7 @@ def L4_ploadrhtnew_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110010010;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -12401,7 +12741,7 @@ def L4_ploadrif_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4) $Rd32 = memw(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011111100;
@@ -12426,7 +12766,7 @@ def L4_ploadrif_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110001100;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -12443,7 +12783,7 @@ def L4_ploadrifnew_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memw(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011111100;
@@ -12469,7 +12809,7 @@ def L4_ploadrifnew_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110011100;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -12487,7 +12827,7 @@ def L4_ploadrit_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4) $Rd32 = memw(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011111100;
@@ -12511,7 +12851,7 @@ def L4_ploadrit_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110000100;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -12527,7 +12867,7 @@ def L4_ploadritnew_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memw(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011111100;
@@ -12552,7 +12892,7 @@ def L4_ploadritnew_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110010100;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -12569,7 +12909,7 @@ def L4_ploadrubf_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4) $Rd32 = memub(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011111001;
@@ -12594,7 +12934,7 @@ def L4_ploadrubf_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110001001;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -12611,7 +12951,7 @@ def L4_ploadrubfnew_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memub(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011111001;
@@ -12637,7 +12977,7 @@ def L4_ploadrubfnew_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110011001;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -12655,7 +12995,7 @@ def L4_ploadrubt_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4) $Rd32 = memub(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011111001;
@@ -12679,7 +13019,7 @@ def L4_ploadrubt_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110000001;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -12695,7 +13035,7 @@ def L4_ploadrubtnew_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memub(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011111001;
@@ -12720,7 +13060,7 @@ def L4_ploadrubtnew_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110010001;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -12737,7 +13077,7 @@ def L4_ploadruhf_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4) $Rd32 = memuh(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b101;
 let Inst{31-21} = 0b10011111011;
@@ -12762,7 +13102,7 @@ def L4_ploadruhf_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110001011;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -12779,7 +13119,7 @@ def L4_ploadruhfnew_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if (!$Pt4.new) $Rd32 = memuh(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b111;
 let Inst{31-21} = 0b10011111011;
@@ -12805,7 +13145,7 @@ def L4_ploadruhfnew_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110011011;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -12823,7 +13163,7 @@ def L4_ploadruht_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4) $Rd32 = memuh(#$Ii)",
-tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b100;
 let Inst{31-21} = 0b10011111011;
@@ -12847,7 +13187,7 @@ def L4_ploadruht_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
-tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110000011;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -12863,7 +13203,7 @@ def L4_ploadruhtnew_abs : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
 "if ($Pt4.new) $Rd32 = memuh(#$Ii)",
-tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel {
+tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
 let Inst{7-5} = 0b100;
 let Inst{13-11} = 0b110;
 let Inst{31-21} = 0b10011111011;
@@ -12888,7 +13228,7 @@ def L4_ploadruhtnew_rr : HInst<
 (outs IntRegs:$Rd32),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
-tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel {
+tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
 let Inst{31-21} = 0b00110010011;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -12902,163 +13242,204 @@ let InputType = "reg";
 let BaseOpcode = "L4_loadruh_rr";
 }
 def L4_return : HInst<
-(outs),
-(ins),
-"dealloc_return",
-tc_dcfee7ae, TypeLD>, Enc_3a3d62, PredNewRel {
-let Inst{4-0} = 0b11110;
+(outs DoubleRegs:$Rdd32),
+(ins IntRegs:$Rs32),
+"$Rdd32 = dealloc_return($Rs32):raw",
+tc_3d04548d, TypeLD>, Enc_3a3d62, PredNewRel {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10010110000;
-let Inst{20-16} = 0b11110;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
+let mayLoad = 1;
 let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let mayLoad = 1;
-let Uses = [R30];
-let Defs = [PC, R29, R30, R31];
+let Uses = [FRAMEKEY];
+let Defs = [PC, R29];
 let BaseOpcode = "L4_return";
 let isBarrier = 1;
 let isPredicable = 1;
 let isTaken = 1;
 }
 def L4_return_f : HInst<
-(outs),
-(ins PredRegs:$Pv4),
-"if (!$Pv4) dealloc_return",
-tc_9ce7a5ab, TypeLD>, Enc_b7fad3, PredNewRel {
-let Inst{4-0} = 0b11110;
+(outs DoubleRegs:$Rdd32),
+(ins PredRegs:$Pv4, IntRegs:$Rs32),
+"if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw",
+tc_513bef45, TypeLD>, Enc_b7fad3, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1100;
 let Inst{31-21} = 0b10010110000;
-let Inst{20-16} = 0b11110;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [R30];
-let Defs = [PC, R29, R30, R31];
+let Uses = [FRAMEKEY];
+let Defs = [PC, R29];
 let BaseOpcode = "L4_return";
 let isTaken = Inst{12};
 }
 def L4_return_fnew_pnt : HInst<
-(outs),
-(ins PredRegs:$Pv4),
-"if (!$Pv4.new) dealloc_return:nt",
-tc_3993c58b, TypeLD>, Enc_b7fad3, PredNewRel {
-let Inst{4-0} = 0b11110;
+(outs DoubleRegs:$Rdd32),
+(ins PredRegs:$Pv4, IntRegs:$Rs32),
+"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
+tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1010;
 let Inst{31-21} = 0b10010110000;
-let Inst{20-16} = 0b11110;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let isPredicatedNew = 1;
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [R30];
-let Defs = [PC, R29, R30, R31];
+let Uses = [FRAMEKEY];
+let Defs = [PC, R29];
 let BaseOpcode = "L4_return";
 let isTaken = Inst{12};
 }
 def L4_return_fnew_pt : HInst<
-(outs),
-(ins PredRegs:$Pv4),
-"if (!$Pv4.new) dealloc_return:t",
-tc_3993c58b, TypeLD>, Enc_b7fad3, PredNewRel {
-let Inst{4-0} = 0b11110;
+(outs DoubleRegs:$Rdd32),
+(ins PredRegs:$Pv4, IntRegs:$Rs32),
+"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
+tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b1110;
 let Inst{31-21} = 0b10010110000;
-let Inst{20-16} = 0b11110;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let isPredicatedNew = 1;
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [R30];
-let Defs = [PC, R29, R30, R31];
+let Uses = [FRAMEKEY];
+let Defs = [PC, R29];
 let BaseOpcode = "L4_return";
 let isTaken = Inst{12};
 }
-def L4_return_t : HInst<
+def L4_return_map_to_raw_f : HInst<
+(outs),
+(ins PredRegs:$Pv4),
+"if (!$Pv4) dealloc_return",
+tc_513bef45, TypeMAPPING>, Requires<[HasV65T]> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+}
+def L4_return_map_to_raw_fnew_pnt : HInst<
+(outs),
+(ins PredRegs:$Pv4),
+"if (!$Pv4.new) dealloc_return:nt",
+tc_395dc00f, TypeMAPPING>, Requires<[HasV65T]> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+}
+def L4_return_map_to_raw_fnew_pt : HInst<
+(outs),
+(ins PredRegs:$Pv4),
+"if (!$Pv4.new) dealloc_return:t",
+tc_395dc00f, TypeMAPPING>, Requires<[HasV65T]> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+}
+def L4_return_map_to_raw_t : HInst<
 (outs),
 (ins PredRegs:$Pv4),
 "if ($Pv4) dealloc_return",
-tc_9ce7a5ab, TypeLD>, Enc_b7fad3, PredNewRel {
-let Inst{4-0} = 0b11110;
+tc_3bc2c5d3, TypeMAPPING>, Requires<[HasV65T]> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+}
+def L4_return_map_to_raw_tnew_pnt : HInst<
+(outs),
+(ins PredRegs:$Pv4),
+"if ($Pv4.new) dealloc_return:nt",
+tc_e7624c08, TypeMAPPING>, Requires<[HasV65T]> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+}
+def L4_return_map_to_raw_tnew_pt : HInst<
+(outs),
+(ins PredRegs:$Pv4),
+"if ($Pv4.new) dealloc_return:t",
+tc_e7624c08, TypeMAPPING>, Requires<[HasV65T]> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+}
+def L4_return_t : HInst<
+(outs DoubleRegs:$Rdd32),
+(ins PredRegs:$Pv4, IntRegs:$Rs32),
+"if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw",
+tc_513bef45, TypeLD>, Enc_b7fad3, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b0100;
 let Inst{31-21} = 0b10010110000;
-let Inst{20-16} = 0b11110;
 let isPredicated = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [R30];
-let Defs = [PC, R29, R30, R31];
+let Uses = [FRAMEKEY];
+let Defs = [PC, R29];
 let BaseOpcode = "L4_return";
 let isTaken = Inst{12};
 }
 def L4_return_tnew_pnt : HInst<
-(outs),
-(ins PredRegs:$Pv4),
-"if ($Pv4.new) dealloc_return:nt",
-tc_3993c58b, TypeLD>, Enc_b7fad3, PredNewRel {
-let Inst{4-0} = 0b11110;
+(outs DoubleRegs:$Rdd32),
+(ins PredRegs:$Pv4, IntRegs:$Rs32),
+"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
+tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b0010;
 let Inst{31-21} = 0b10010110000;
-let Inst{20-16} = 0b11110;
 let isPredicated = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let isPredicatedNew = 1;
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [R30];
-let Defs = [PC, R29, R30, R31];
+let Uses = [FRAMEKEY];
+let Defs = [PC, R29];
 let BaseOpcode = "L4_return";
 let isTaken = Inst{12};
 }
 def L4_return_tnew_pt : HInst<
-(outs),
-(ins PredRegs:$Pv4),
-"if ($Pv4.new) dealloc_return:t",
-tc_3993c58b, TypeLD>, Enc_b7fad3, PredNewRel {
-let Inst{4-0} = 0b11110;
+(outs DoubleRegs:$Rdd32),
+(ins PredRegs:$Pv4, IntRegs:$Rs32),
+"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
+tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
 let Inst{7-5} = 0b000;
 let Inst{13-10} = 0b0110;
 let Inst{31-21} = 0b10010110000;
-let Inst{20-16} = 0b11110;
 let isPredicated = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let isPredicatedNew = 1;
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [R30];
-let Defs = [PC, R29, R30, R31];
+let Uses = [FRAMEKEY];
+let Defs = [PC, R29];
 let BaseOpcode = "L4_return";
 let isTaken = Inst{12};
 }
@@ -13066,13 +13447,14 @@ def L4_sub_memopb_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
 "memb($Rs32+#$Ii) -= $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_d44e31 {
+tc_44126683, TypeV4LDST>, Enc_d44e31 {
 let Inst{6-5} = 0b01;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110000;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -13084,7 +13466,7 @@ def L4_sub_memopb_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memb($Rs32) -= $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -13092,13 +13474,14 @@ def L4_sub_memoph_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "memh($Rs32+#$Ii) -= $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_163a3c {
+tc_44126683, TypeV4LDST>, Enc_163a3c {
 let Inst{6-5} = 0b01;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110001;
 let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -13110,7 +13493,7 @@ def L4_sub_memoph_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memh($Rs32) -= $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -13118,13 +13501,14 @@ def L4_sub_memopw_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
 "memw($Rs32+#$Ii) -= $Rt32",
-tc_a9c993d9, TypeV4LDST>, Enc_226535 {
+tc_44126683, TypeV4LDST>, Enc_226535 {
 let Inst{6-5} = 0b01;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00111110010;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let isExtendable = 1;
 let opExtendable = 1;
@@ -13136,7 +13520,23 @@ def L4_sub_memopw_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memw($Rs32) -= $Rt32",
-tc_a9c993d9, TypeMAPPING> {
+tc_44126683, TypeMAPPING> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+}
+def L6_deallocframe_map_to_raw : HInst<
+(outs),
+(ins),
+"deallocframe",
+tc_d1090e34, TypeMAPPING>, Requires<[HasV65T]> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+}
+def L6_return_map_to_raw : HInst<
+(outs),
+(ins),
+"dealloc_return",
+tc_3d04548d, TypeMAPPING>, Requires<[HasV65T]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -13144,7 +13544,7 @@ def M2_acci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += add($Rs32,$Rt32)",
-tc_c0cd91a8, TypeM>, Enc_2ae154, ImmRegRel {
+tc_c74f796f, TypeM>, Enc_2ae154, ImmRegRel {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111000;
@@ -13159,7 +13559,7 @@ def M2_accii : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rx32 += add($Rs32,#$Ii)",
-tc_c0cd91a8, TypeM>, Enc_c90aca, ImmRegRel {
+tc_c74f796f, TypeM>, Enc_c90aca, ImmRegRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100010000;
 let hasNewValue = 1;
@@ -13178,7 +13578,7 @@ def M2_cmaci_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += cmpyi($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111000;
@@ -13189,7 +13589,7 @@ def M2_cmacr_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += cmpyr($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111000;
@@ -13200,7 +13600,7 @@ def M2_cmacs_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += cmpy($Rs32,$Rt32):sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111000;
@@ -13212,7 +13612,7 @@ def M2_cmacs_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111100;
@@ -13224,7 +13624,7 @@ def M2_cmacsc_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += cmpy($Rs32,$Rt32*):sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111010;
@@ -13236,7 +13636,7 @@ def M2_cmacsc_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111110;
@@ -13248,7 +13648,7 @@ def M2_cmpyi_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = cmpyi($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101000;
@@ -13258,7 +13658,7 @@ def M2_cmpyr_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = cmpyr($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101000;
@@ -13268,7 +13668,7 @@ def M2_cmpyrs_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = cmpy($Rs32,$Rt32):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101001;
@@ -13281,7 +13681,7 @@ def M2_cmpyrs_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101101;
@@ -13294,7 +13694,7 @@ def M2_cmpyrsc_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101011;
@@ -13307,7 +13707,7 @@ def M2_cmpyrsc_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101111;
@@ -13320,7 +13720,7 @@ def M2_cmpys_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = cmpy($Rs32,$Rt32):sat",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101000;
@@ -13331,7 +13731,7 @@ def M2_cmpys_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101100;
@@ -13342,7 +13742,7 @@ def M2_cmpysc_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = cmpy($Rs32,$Rt32*):sat",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101010;
@@ -13353,7 +13753,7 @@ def M2_cmpysc_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101110;
@@ -13364,7 +13764,7 @@ def M2_cnacs_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= cmpy($Rs32,$Rt32):sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111000;
@@ -13376,7 +13776,7 @@ def M2_cnacs_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111100;
@@ -13388,7 +13788,7 @@ def M2_cnacsc_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= cmpy($Rs32,$Rt32*):sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111010;
@@ -13400,7 +13800,7 @@ def M2_cnacsc_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111110;
@@ -13412,7 +13812,7 @@ def M2_dpmpyss_acc_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpy($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111000;
@@ -13423,7 +13823,7 @@ def M2_dpmpyss_nac_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpy($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111001;
@@ -13434,7 +13834,7 @@ def M2_dpmpyss_rnd_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32,$Rt32):rnd",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101001;
@@ -13446,7 +13846,7 @@ def M2_dpmpyss_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101000;
@@ -13456,7 +13856,7 @@ def M2_dpmpyuu_acc_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpyu($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111010;
@@ -13467,7 +13867,7 @@ def M2_dpmpyuu_nac_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpyu($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111011;
@@ -13478,7 +13878,7 @@ def M2_dpmpyuu_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpyu($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101010;
@@ -13488,7 +13888,7 @@ def M2_hmmpyh_rs1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101101;
@@ -13501,7 +13901,7 @@ def M2_hmmpyh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101101;
@@ -13514,7 +13914,7 @@ def M2_hmmpyl_rs1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101111;
@@ -13527,7 +13927,7 @@ def M2_hmmpyl_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101101;
@@ -13540,7 +13940,7 @@ def M2_maci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpyi($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_2ae154, ImmRegRel {
+tc_e913dc32, TypeM>, Enc_2ae154, ImmRegRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111000;
@@ -13555,7 +13955,7 @@ def M2_macsin : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
 "$Rx32 -= mpyi($Rs32,#$Ii)",
-tc_a12a5971, TypeM>, Enc_c90aca {
+tc_16d0d8d5, TypeM>, Enc_c90aca {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100001100;
 let hasNewValue = 1;
@@ -13573,7 +13973,7 @@ def M2_macsip : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
 "$Rx32 += mpyi($Rs32,#$Ii)",
-tc_a12a5971, TypeM>, Enc_c90aca, ImmRegRel {
+tc_16d0d8d5, TypeM>, Enc_c90aca, ImmRegRel {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100001000;
 let hasNewValue = 1;
@@ -13592,7 +13992,7 @@ def M2_mmachs_rs0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010001;
@@ -13604,7 +14004,7 @@ def M2_mmachs_rs1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010101;
@@ -13616,7 +14016,7 @@ def M2_mmachs_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpywoh($Rss32,$Rtt32):sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010000;
@@ -13628,7 +14028,7 @@ def M2_mmachs_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010100;
@@ -13640,7 +14040,7 @@ def M2_mmacls_rs0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010001;
@@ -13652,7 +14052,7 @@ def M2_mmacls_rs1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010101;
@@ -13664,7 +14064,7 @@ def M2_mmacls_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyweh($Rss32,$Rtt32):sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010000;
@@ -13676,7 +14076,7 @@ def M2_mmacls_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010100;
@@ -13688,7 +14088,7 @@ def M2_mmacuhs_rs0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010011;
@@ -13700,7 +14100,7 @@ def M2_mmacuhs_rs1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010111;
@@ -13712,7 +14112,7 @@ def M2_mmacuhs_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpywouh($Rss32,$Rtt32):sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010010;
@@ -13724,7 +14124,7 @@ def M2_mmacuhs_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010110;
@@ -13736,7 +14136,7 @@ def M2_mmaculs_rs0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010011;
@@ -13748,7 +14148,7 @@ def M2_mmaculs_rs1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010111;
@@ -13760,7 +14160,7 @@ def M2_mmaculs_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010010;
@@ -13772,7 +14172,7 @@ def M2_mmaculs_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010110;
@@ -13784,7 +14184,7 @@ def M2_mmpyh_rs0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000001;
@@ -13795,7 +14195,7 @@ def M2_mmpyh_rs1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000101;
@@ -13806,7 +14206,7 @@ def M2_mmpyh_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpywoh($Rss32,$Rtt32):sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000000;
@@ -13817,7 +14217,7 @@ def M2_mmpyh_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000100;
@@ -13828,7 +14228,7 @@ def M2_mmpyl_rs0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000001;
@@ -13839,7 +14239,7 @@ def M2_mmpyl_rs1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000101;
@@ -13850,7 +14250,7 @@ def M2_mmpyl_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpyweh($Rss32,$Rtt32):sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000000;
@@ -13861,7 +14261,7 @@ def M2_mmpyl_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000100;
@@ -13872,7 +14272,7 @@ def M2_mmpyuh_rs0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000011;
@@ -13883,7 +14283,7 @@ def M2_mmpyuh_rs1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000111;
@@ -13894,7 +14294,7 @@ def M2_mmpyuh_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpywouh($Rss32,$Rtt32):sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000010;
@@ -13905,7 +14305,7 @@ def M2_mmpyuh_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000110;
@@ -13916,7 +14316,7 @@ def M2_mmpyul_rs0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000011;
@@ -13927,7 +14327,7 @@ def M2_mmpyul_rs1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000111;
@@ -13938,7 +14338,7 @@ def M2_mmpyul_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000010;
@@ -13949,7 +14349,7 @@ def M2_mmpyul_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000110;
@@ -13960,7 +14360,7 @@ def M2_mpy_acc_hh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.h,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110000;
@@ -13973,7 +14373,7 @@ def M2_mpy_acc_hh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110100;
@@ -13986,7 +14386,7 @@ def M2_mpy_acc_hl_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.h,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110000;
@@ -13999,7 +14399,7 @@ def M2_mpy_acc_hl_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110100;
@@ -14012,7 +14412,7 @@ def M2_mpy_acc_lh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.l,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110000;
@@ -14025,7 +14425,7 @@ def M2_mpy_acc_lh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110100;
@@ -14038,7 +14438,7 @@ def M2_mpy_acc_ll_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.l,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110000;
@@ -14051,7 +14451,7 @@ def M2_mpy_acc_ll_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110100;
@@ -14064,7 +14464,7 @@ def M2_mpy_acc_sat_hh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.h,$Rt32.h):sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110000;
@@ -14078,7 +14478,7 @@ def M2_mpy_acc_sat_hh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110100;
@@ -14092,7 +14492,7 @@ def M2_mpy_acc_sat_hl_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.h,$Rt32.l):sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110000;
@@ -14106,7 +14506,7 @@ def M2_mpy_acc_sat_hl_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110100;
@@ -14120,7 +14520,7 @@ def M2_mpy_acc_sat_lh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.l,$Rt32.h):sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110000;
@@ -14134,7 +14534,7 @@ def M2_mpy_acc_sat_lh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110100;
@@ -14148,7 +14548,7 @@ def M2_mpy_acc_sat_ll_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.l,$Rt32.l):sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110000;
@@ -14162,7 +14562,7 @@ def M2_mpy_acc_sat_ll_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110100;
@@ -14176,7 +14576,7 @@ def M2_mpy_hh_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.h)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100000;
@@ -14188,7 +14588,7 @@ def M2_mpy_hh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100100;
@@ -14200,7 +14600,7 @@ def M2_mpy_hl_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.l)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100000;
@@ -14212,7 +14612,7 @@ def M2_mpy_hl_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100100;
@@ -14224,7 +14624,7 @@ def M2_mpy_lh_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.h)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100000;
@@ -14236,7 +14636,7 @@ def M2_mpy_lh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100100;
@@ -14248,7 +14648,7 @@ def M2_mpy_ll_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.l)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100000;
@@ -14260,7 +14660,7 @@ def M2_mpy_ll_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100100;
@@ -14272,7 +14672,7 @@ def M2_mpy_nac_hh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.h,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110001;
@@ -14285,7 +14685,7 @@ def M2_mpy_nac_hh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110101;
@@ -14298,7 +14698,7 @@ def M2_mpy_nac_hl_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.h,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110001;
@@ -14311,7 +14711,7 @@ def M2_mpy_nac_hl_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110101;
@@ -14324,7 +14724,7 @@ def M2_mpy_nac_lh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.l,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110001;
@@ -14337,7 +14737,7 @@ def M2_mpy_nac_lh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110101;
@@ -14350,7 +14750,7 @@ def M2_mpy_nac_ll_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.l,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110001;
@@ -14363,7 +14763,7 @@ def M2_mpy_nac_ll_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110101;
@@ -14376,7 +14776,7 @@ def M2_mpy_nac_sat_hh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.h,$Rt32.h):sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110001;
@@ -14390,7 +14790,7 @@ def M2_mpy_nac_sat_hh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110101;
@@ -14404,7 +14804,7 @@ def M2_mpy_nac_sat_hl_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.h,$Rt32.l):sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110001;
@@ -14418,7 +14818,7 @@ def M2_mpy_nac_sat_hl_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110101;
@@ -14432,7 +14832,7 @@ def M2_mpy_nac_sat_lh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.l,$Rt32.h):sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110001;
@@ -14446,7 +14846,7 @@ def M2_mpy_nac_sat_lh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110101;
@@ -14460,7 +14860,7 @@ def M2_mpy_nac_sat_ll_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.l,$Rt32.l):sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110001;
@@ -14474,7 +14874,7 @@ def M2_mpy_nac_sat_ll_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110101;
@@ -14488,7 +14888,7 @@ def M2_mpy_rnd_hh_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100001;
@@ -14500,7 +14900,7 @@ def M2_mpy_rnd_hh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100101;
@@ -14512,7 +14912,7 @@ def M2_mpy_rnd_hl_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100001;
@@ -14524,7 +14924,7 @@ def M2_mpy_rnd_hl_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100101;
@@ -14536,7 +14936,7 @@ def M2_mpy_rnd_lh_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100001;
@@ -14548,7 +14948,7 @@ def M2_mpy_rnd_lh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100101;
@@ -14560,7 +14960,7 @@ def M2_mpy_rnd_ll_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100001;
@@ -14572,7 +14972,7 @@ def M2_mpy_rnd_ll_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100101;
@@ -14584,7 +14984,7 @@ def M2_mpy_sat_hh_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.h):sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100000;
@@ -14597,7 +14997,7 @@ def M2_mpy_sat_hh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100100;
@@ -14610,7 +15010,7 @@ def M2_mpy_sat_hl_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.l):sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100000;
@@ -14623,7 +15023,7 @@ def M2_mpy_sat_hl_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100100;
@@ -14636,7 +15036,7 @@ def M2_mpy_sat_lh_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.h):sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100000;
@@ -14649,7 +15049,7 @@ def M2_mpy_sat_lh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100100;
@@ -14662,7 +15062,7 @@ def M2_mpy_sat_ll_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.l):sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100000;
@@ -14675,7 +15075,7 @@ def M2_mpy_sat_ll_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100100;
@@ -14688,7 +15088,7 @@ def M2_mpy_sat_rnd_hh_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100001;
@@ -14701,7 +15101,7 @@ def M2_mpy_sat_rnd_hh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100101;
@@ -14714,7 +15114,7 @@ def M2_mpy_sat_rnd_hl_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100001;
@@ -14727,7 +15127,7 @@ def M2_mpy_sat_rnd_hl_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100101;
@@ -14740,7 +15140,7 @@ def M2_mpy_sat_rnd_lh_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100001;
@@ -14753,7 +15153,7 @@ def M2_mpy_sat_rnd_lh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100101;
@@ -14766,7 +15166,7 @@ def M2_mpy_sat_rnd_ll_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100001;
@@ -14779,7 +15179,7 @@ def M2_mpy_sat_rnd_ll_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100101;
@@ -14792,7 +15192,7 @@ def M2_mpy_up : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101000;
@@ -14804,7 +15204,7 @@ def M2_mpy_up_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32,$Rt32):<<1",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101101;
@@ -14816,7 +15216,7 @@ def M2_mpy_up_s1_sat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpy($Rs32,$Rt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101111;
@@ -14829,7 +15229,7 @@ def M2_mpyd_acc_hh_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpy($Rs32.h,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110000;
@@ -14840,7 +15240,7 @@ def M2_mpyd_acc_hh_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110100;
@@ -14851,7 +15251,7 @@ def M2_mpyd_acc_hl_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpy($Rs32.h,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110000;
@@ -14862,7 +15262,7 @@ def M2_mpyd_acc_hl_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110100;
@@ -14873,7 +15273,7 @@ def M2_mpyd_acc_lh_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpy($Rs32.l,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110000;
@@ -14884,7 +15284,7 @@ def M2_mpyd_acc_lh_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110100;
@@ -14895,7 +15295,7 @@ def M2_mpyd_acc_ll_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpy($Rs32.l,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110000;
@@ -14906,7 +15306,7 @@ def M2_mpyd_acc_ll_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110100;
@@ -14917,7 +15317,7 @@ def M2_mpyd_hh_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.h,$Rt32.h)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100000;
@@ -14927,7 +15327,7 @@ def M2_mpyd_hh_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100100;
@@ -14937,7 +15337,7 @@ def M2_mpyd_hl_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.h,$Rt32.l)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100000;
@@ -14947,7 +15347,7 @@ def M2_mpyd_hl_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100100;
@@ -14957,7 +15357,7 @@ def M2_mpyd_lh_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.l,$Rt32.h)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100000;
@@ -14967,7 +15367,7 @@ def M2_mpyd_lh_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100100;
@@ -14977,7 +15377,7 @@ def M2_mpyd_ll_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.l,$Rt32.l)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100000;
@@ -14987,7 +15387,7 @@ def M2_mpyd_ll_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100100;
@@ -14997,7 +15397,7 @@ def M2_mpyd_nac_hh_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpy($Rs32.h,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110001;
@@ -15008,7 +15408,7 @@ def M2_mpyd_nac_hh_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110101;
@@ -15019,7 +15419,7 @@ def M2_mpyd_nac_hl_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpy($Rs32.h,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110001;
@@ -15030,7 +15430,7 @@ def M2_mpyd_nac_hl_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110101;
@@ -15041,7 +15441,7 @@ def M2_mpyd_nac_lh_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpy($Rs32.l,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110001;
@@ -15052,7 +15452,7 @@ def M2_mpyd_nac_lh_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110101;
@@ -15063,7 +15463,7 @@ def M2_mpyd_nac_ll_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpy($Rs32.l,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110001;
@@ -15074,7 +15474,7 @@ def M2_mpyd_nac_ll_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110101;
@@ -15085,7 +15485,7 @@ def M2_mpyd_rnd_hh_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100001;
@@ -15095,7 +15495,7 @@ def M2_mpyd_rnd_hh_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100101;
@@ -15105,7 +15505,7 @@ def M2_mpyd_rnd_hl_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100001;
@@ -15115,7 +15515,7 @@ def M2_mpyd_rnd_hl_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100101;
@@ -15125,7 +15525,7 @@ def M2_mpyd_rnd_lh_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100001;
@@ -15135,7 +15535,7 @@ def M2_mpyd_rnd_lh_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100101;
@@ -15145,7 +15545,7 @@ def M2_mpyd_rnd_ll_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100001;
@@ -15155,7 +15555,7 @@ def M2_mpyd_rnd_ll_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100101;
@@ -15165,7 +15565,7 @@ def M2_mpyi : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyi($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_5ab2be, ImmRegRel {
+tc_8fd5f294, TypeM>, Enc_5ab2be, ImmRegRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101000;
@@ -15179,7 +15579,7 @@ def M2_mpysin : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u8_0Imm:$Ii),
 "$Rd32 = -mpyi($Rs32,#$Ii)",
-tc_ae2c2dc2, TypeM>, Enc_b8c967 {
+tc_1853ea6d, TypeM>, Enc_b8c967 {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100000100;
 let hasNewValue = 1;
@@ -15190,7 +15590,7 @@ def M2_mpysip : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
 "$Rd32 = +mpyi($Rs32,#$Ii)",
-tc_ae2c2dc2, TypeM>, Enc_b8c967 {
+tc_1853ea6d, TypeM>, Enc_b8c967 {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100000000;
 let hasNewValue = 1;
@@ -15206,7 +15606,7 @@ def M2_mpysmi : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, m32_0Imm:$Ii),
 "$Rd32 = mpyi($Rs32,#$Ii)",
-tc_ae2c2dc2, TypeM>, ImmRegRel {
+tc_1853ea6d, TypeM>, ImmRegRel {
 let hasNewValue = 1;
 let opNewValue = 0;
 let CextOpcode = "M2_mpyi";
@@ -15222,7 +15622,7 @@ def M2_mpysu_up : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpysu($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101011;
@@ -15234,7 +15634,7 @@ def M2_mpyu_acc_hh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpyu($Rs32.h,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110010;
@@ -15247,7 +15647,7 @@ def M2_mpyu_acc_hh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110110;
@@ -15260,7 +15660,7 @@ def M2_mpyu_acc_hl_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpyu($Rs32.h,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110010;
@@ -15273,7 +15673,7 @@ def M2_mpyu_acc_hl_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110110;
@@ -15286,7 +15686,7 @@ def M2_mpyu_acc_lh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpyu($Rs32.l,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110010;
@@ -15299,7 +15699,7 @@ def M2_mpyu_acc_lh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110110;
@@ -15312,7 +15712,7 @@ def M2_mpyu_acc_ll_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpyu($Rs32.l,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110010;
@@ -15325,7 +15725,7 @@ def M2_mpyu_acc_ll_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110110;
@@ -15338,7 +15738,7 @@ def M2_mpyu_hh_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyu($Rs32.h,$Rt32.h)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100010;
@@ -15350,7 +15750,7 @@ def M2_mpyu_hh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100110;
@@ -15362,7 +15762,7 @@ def M2_mpyu_hl_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyu($Rs32.h,$Rt32.l)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100010;
@@ -15374,7 +15774,7 @@ def M2_mpyu_hl_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100110;
@@ -15386,7 +15786,7 @@ def M2_mpyu_lh_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyu($Rs32.l,$Rt32.h)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100010;
@@ -15398,7 +15798,7 @@ def M2_mpyu_lh_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100110;
@@ -15410,7 +15810,7 @@ def M2_mpyu_ll_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyu($Rs32.l,$Rt32.l)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100010;
@@ -15422,7 +15822,7 @@ def M2_mpyu_ll_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101100110;
@@ -15434,7 +15834,7 @@ def M2_mpyu_nac_hh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpyu($Rs32.h,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110011;
@@ -15447,7 +15847,7 @@ def M2_mpyu_nac_hh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110111;
@@ -15460,7 +15860,7 @@ def M2_mpyu_nac_hl_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpyu($Rs32.h,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110011;
@@ -15473,7 +15873,7 @@ def M2_mpyu_nac_hl_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110111;
@@ -15486,7 +15886,7 @@ def M2_mpyu_nac_lh_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpyu($Rs32.l,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110011;
@@ -15499,7 +15899,7 @@ def M2_mpyu_nac_lh_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110111;
@@ -15512,7 +15912,7 @@ def M2_mpyu_nac_ll_s0 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpyu($Rs32.l,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110011;
@@ -15525,7 +15925,7 @@ def M2_mpyu_nac_ll_s1 : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101110111;
@@ -15538,7 +15938,7 @@ def M2_mpyu_up : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyu($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101010;
@@ -15550,7 +15950,7 @@ def M2_mpyud_acc_hh_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpyu($Rs32.h,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110010;
@@ -15561,7 +15961,7 @@ def M2_mpyud_acc_hh_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110110;
@@ -15572,7 +15972,7 @@ def M2_mpyud_acc_hl_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpyu($Rs32.h,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110010;
@@ -15583,7 +15983,7 @@ def M2_mpyud_acc_hl_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110110;
@@ -15594,7 +15994,7 @@ def M2_mpyud_acc_lh_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpyu($Rs32.l,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110010;
@@ -15605,7 +16005,7 @@ def M2_mpyud_acc_lh_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110110;
@@ -15616,7 +16016,7 @@ def M2_mpyud_acc_ll_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpyu($Rs32.l,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110010;
@@ -15627,7 +16027,7 @@ def M2_mpyud_acc_ll_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110110;
@@ -15638,7 +16038,7 @@ def M2_mpyud_hh_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpyu($Rs32.h,$Rt32.h)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100010;
@@ -15648,7 +16048,7 @@ def M2_mpyud_hh_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100110;
@@ -15658,7 +16058,7 @@ def M2_mpyud_hl_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpyu($Rs32.h,$Rt32.l)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100010;
@@ -15668,7 +16068,7 @@ def M2_mpyud_hl_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100110;
@@ -15678,7 +16078,7 @@ def M2_mpyud_lh_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpyu($Rs32.l,$Rt32.h)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100010;
@@ -15688,7 +16088,7 @@ def M2_mpyud_lh_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100110;
@@ -15698,7 +16098,7 @@ def M2_mpyud_ll_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpyu($Rs32.l,$Rt32.l)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100010;
@@ -15708,7 +16108,7 @@ def M2_mpyud_ll_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100100110;
@@ -15718,7 +16118,7 @@ def M2_mpyud_nac_hh_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpyu($Rs32.h,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110011;
@@ -15729,7 +16129,7 @@ def M2_mpyud_nac_hh_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110111;
@@ -15740,7 +16140,7 @@ def M2_mpyud_nac_hl_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpyu($Rs32.h,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110011;
@@ -15751,7 +16151,7 @@ def M2_mpyud_nac_hl_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110111;
@@ -15762,7 +16162,7 @@ def M2_mpyud_nac_lh_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpyu($Rs32.l,$Rt32.h)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110011;
@@ -15773,7 +16173,7 @@ def M2_mpyud_nac_lh_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110111;
@@ -15784,7 +16184,7 @@ def M2_mpyud_nac_ll_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpyu($Rs32.l,$Rt32.l)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110011;
@@ -15795,7 +16195,7 @@ def M2_mpyud_nac_ll_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100110111;
@@ -15806,7 +16206,7 @@ def M2_mpyui : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = mpyui($Rs32,$Rt32)",
-tc_8c8041e6, TypeM> {
+tc_8fd5f294, TypeM> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -15816,7 +16216,7 @@ def M2_nacci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= add($Rs32,$Rt32)",
-tc_c0cd91a8, TypeM>, Enc_2ae154 {
+tc_c74f796f, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111100;
@@ -15830,7 +16230,7 @@ def M2_naccii : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rx32 -= add($Rs32,#$Ii)",
-tc_c0cd91a8, TypeM>, Enc_c90aca {
+tc_c74f796f, TypeM>, Enc_c90aca {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100010100;
 let hasNewValue = 1;
@@ -15848,7 +16248,7 @@ def M2_subacc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rx32 += sub($Rt32,$Rs32)",
-tc_c0cd91a8, TypeM>, Enc_a568d4 {
+tc_c74f796f, TypeM>, Enc_a568d4 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111000;
@@ -15862,7 +16262,7 @@ def M2_vabsdiffh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vabsdiffh($Rtt32,$Rss32)",
-tc_63cd9d2d, TypeM>, Enc_ea23e4 {
+tc_2b6f77c6, TypeM>, Enc_ea23e4 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000011;
@@ -15872,7 +16272,7 @@ def M2_vabsdiffw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vabsdiffw($Rtt32,$Rss32)",
-tc_63cd9d2d, TypeM>, Enc_ea23e4 {
+tc_2b6f77c6, TypeM>, Enc_ea23e4 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000001;
@@ -15882,7 +16282,7 @@ def M2_vcmac_s0_sat_i : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vcmpyi($Rss32,$Rtt32):sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010010;
@@ -15894,7 +16294,7 @@ def M2_vcmac_s0_sat_r : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vcmpyr($Rss32,$Rtt32):sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010001;
@@ -15906,7 +16306,7 @@ def M2_vcmpy_s0_sat_i : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vcmpyi($Rss32,$Rtt32):sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000010;
@@ -15917,7 +16317,7 @@ def M2_vcmpy_s0_sat_r : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vcmpyr($Rss32,$Rtt32):sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000001;
@@ -15928,7 +16328,7 @@ def M2_vcmpy_s1_sat_i : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000110;
@@ -15939,7 +16339,7 @@ def M2_vcmpy_s1_sat_r : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000101;
@@ -15950,7 +16350,7 @@ def M2_vdmacs_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vdmpy($Rss32,$Rtt32):sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010000;
@@ -15962,7 +16362,7 @@ def M2_vdmacs_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010100;
@@ -15974,7 +16374,7 @@ def M2_vdmpyrs_s0 : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_d2216a {
+tc_8fd5f294, TypeM>, Enc_d2216a {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101001000;
@@ -15987,7 +16387,7 @@ def M2_vdmpyrs_s1 : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_d2216a {
+tc_8fd5f294, TypeM>, Enc_d2216a {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101001100;
@@ -16000,7 +16400,7 @@ def M2_vdmpys_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vdmpy($Rss32,$Rtt32):sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000000;
@@ -16011,7 +16411,7 @@ def M2_vdmpys_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000100;
@@ -16022,7 +16422,7 @@ def M2_vmac2 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += vmpyh($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111001;
@@ -16033,7 +16433,7 @@ def M2_vmac2es : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyeh($Rss32,$Rtt32)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010001;
@@ -16044,7 +16444,7 @@ def M2_vmac2es_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyeh($Rss32,$Rtt32):sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010000;
@@ -16056,7 +16456,7 @@ def M2_vmac2es_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010100;
@@ -16068,7 +16468,7 @@ def M2_vmac2s_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += vmpyh($Rs32,$Rt32):sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111000;
@@ -16080,7 +16480,7 @@ def M2_vmac2s_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111100;
@@ -16092,7 +16492,7 @@ def M2_vmac2su_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += vmpyhsu($Rs32,$Rt32):sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111011;
@@ -16104,7 +16504,7 @@ def M2_vmac2su_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111111;
@@ -16116,7 +16516,7 @@ def M2_vmpy2es_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpyeh($Rss32,$Rtt32):sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000000;
@@ -16127,7 +16527,7 @@ def M2_vmpy2es_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000100;
@@ -16138,7 +16538,7 @@ def M2_vmpy2s_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = vmpyh($Rs32,$Rt32):sat",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101000;
@@ -16149,7 +16549,7 @@ def M2_vmpy2s_s0pack : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101001;
@@ -16162,7 +16562,7 @@ def M2_vmpy2s_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101100;
@@ -16173,7 +16573,7 @@ def M2_vmpy2s_s1pack : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat",
-tc_8c8041e6, TypeM>, Enc_5ab2be {
+tc_8fd5f294, TypeM>, Enc_5ab2be {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101101101;
@@ -16186,7 +16586,7 @@ def M2_vmpy2su_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = vmpyhsu($Rs32,$Rt32):sat",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101000;
@@ -16197,7 +16597,7 @@ def M2_vmpy2su_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101100;
@@ -16208,7 +16608,7 @@ def M2_vraddh : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rd32 = vraddh($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_d2216a {
+tc_8fd5f294, TypeM>, Enc_d2216a {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101001001;
@@ -16220,7 +16620,7 @@ def M2_vradduh : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rd32 = vradduh($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_d2216a {
+tc_8fd5f294, TypeM>, Enc_d2216a {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101001000;
@@ -16232,7 +16632,7 @@ def M2_vrcmaci_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrcmpyi($Rss32,$Rtt32)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010000;
@@ -16243,7 +16643,7 @@ def M2_vrcmaci_s0c : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrcmpyi($Rss32,$Rtt32*)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010010;
@@ -16254,7 +16654,7 @@ def M2_vrcmacr_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrcmpyr($Rss32,$Rtt32)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010000;
@@ -16265,7 +16665,7 @@ def M2_vrcmacr_s0c : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrcmpyr($Rss32,$Rtt32*)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010011;
@@ -16276,7 +16676,7 @@ def M2_vrcmpyi_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrcmpyi($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000000;
@@ -16286,7 +16686,7 @@ def M2_vrcmpyi_s0c : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrcmpyi($Rss32,$Rtt32*)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000010;
@@ -16296,7 +16696,7 @@ def M2_vrcmpyr_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrcmpyr($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000000;
@@ -16306,7 +16706,7 @@ def M2_vrcmpyr_s0c : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrcmpyr($Rss32,$Rtt32*)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000011;
@@ -16316,7 +16716,7 @@ def M2_vrcmpys_acc_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat",
-tc_8cb685d9, TypeM> {
+tc_e913dc32, TypeM> {
 let isPseudo = 1;
 let Constraints = "$Rxx32 = $Rxx32in";
 }
@@ -16324,7 +16724,7 @@ def M2_vrcmpys_acc_s1_h : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010101;
@@ -16336,7 +16736,7 @@ def M2_vrcmpys_acc_s1_l : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010111;
@@ -16348,14 +16748,14 @@ def M2_vrcmpys_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat",
-tc_8c8041e6, TypeM> {
+tc_8fd5f294, TypeM> {
 let isPseudo = 1;
 }
 def M2_vrcmpys_s1_h : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000101;
@@ -16366,7 +16766,7 @@ def M2_vrcmpys_s1_l : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000111;
@@ -16377,7 +16777,7 @@ def M2_vrcmpys_s1rp : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat",
-tc_8c8041e6, TypeM> {
+tc_8fd5f294, TypeM> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -16386,7 +16786,7 @@ def M2_vrcmpys_s1rp_h : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi",
-tc_8c8041e6, TypeM>, Enc_d2216a {
+tc_8fd5f294, TypeM>, Enc_d2216a {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101001101;
@@ -16399,7 +16799,7 @@ def M2_vrcmpys_s1rp_l : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo",
-tc_8c8041e6, TypeM>, Enc_d2216a {
+tc_8fd5f294, TypeM>, Enc_d2216a {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101001101;
@@ -16412,7 +16812,7 @@ def M2_vrmac_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrmpyh($Rss32,$Rtt32)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010000;
@@ -16423,7 +16823,7 @@ def M2_vrmpy_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrmpyh($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000000;
@@ -16433,7 +16833,7 @@ def M2_xor_xacc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 ^= xor($Rs32,$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111100;
@@ -16447,7 +16847,7 @@ def M4_and_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 &= and($Rs32,$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111010;
@@ -16461,7 +16861,7 @@ def M4_and_andn : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 &= and($Rs32,~$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111001;
@@ -16475,7 +16875,7 @@ def M4_and_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 &= or($Rs32,$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111010;
@@ -16489,7 +16889,7 @@ def M4_and_xor : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 &= xor($Rs32,$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111010;
@@ -16503,7 +16903,7 @@ def M4_cmpyi_wh : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat",
-tc_8c8041e6, TypeS_3op>, Enc_3d5b28 {
+tc_8fd5f294, TypeS_3op>, Enc_3d5b28 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000101000;
@@ -16516,7 +16916,7 @@ def M4_cmpyi_whc : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat",
-tc_8c8041e6, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> {
+tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000101000;
@@ -16529,7 +16929,7 @@ def M4_cmpyr_wh : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat",
-tc_8c8041e6, TypeS_3op>, Enc_3d5b28 {
+tc_8fd5f294, TypeS_3op>, Enc_3d5b28 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000101000;
@@ -16542,7 +16942,7 @@ def M4_cmpyr_whc : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat",
-tc_8c8041e6, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> {
+tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000101000;
@@ -16555,7 +16955,7 @@ def M4_mac_up_s1_sat : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += mpy($Rs32,$Rt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111011;
@@ -16570,7 +16970,7 @@ def M4_mpyri_addi : HInst<
 (outs IntRegs:$Rd32),
 (ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
 "$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
-tc_a12a5971, TypeALU64>, Enc_322e1b, ImmRegRel {
+tc_16d0d8d5, TypeALU64>, Enc_322e1b, ImmRegRel {
 let Inst{31-24} = 0b11011000;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -16586,7 +16986,7 @@ def M4_mpyri_addr : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
 "$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
-tc_a12a5971, TypeALU64>, Enc_420cf3, ImmRegRel {
+tc_16d0d8d5, TypeALU64>, Enc_420cf3, ImmRegRel {
 let Inst{31-23} = 0b110111111;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -16603,7 +17003,7 @@ def M4_mpyri_addr_u2 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
 "$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
-tc_69bb508b, TypeALU64>, Enc_277737 {
+tc_bcc96cee, TypeALU64>, Enc_277737 {
 let Inst{31-23} = 0b110111110;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -16613,7 +17013,7 @@ def M4_mpyrr_addi : HInst<
 (outs IntRegs:$Rd32),
 (ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
-tc_8cb685d9, TypeALU64>, Enc_a7b8e8, ImmRegRel {
+tc_e913dc32, TypeALU64>, Enc_a7b8e8, ImmRegRel {
 let Inst{31-23} = 0b110101110;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -16630,7 +17030,7 @@ def M4_mpyrr_addr : HInst<
 (outs IntRegs:$Ry32),
 (ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
 "$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
-tc_8cb685d9, TypeM>, Enc_7f1a05, ImmRegRel {
+tc_e913dc32, TypeM>, Enc_7f1a05, ImmRegRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100011000;
@@ -16645,7 +17045,7 @@ def M4_nac_up_s1_sat : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= mpy($Rs32,$Rt32):<<1:sat",
-tc_8cb685d9, TypeM>, Enc_2ae154 {
+tc_e913dc32, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111011;
@@ -16660,7 +17060,7 @@ def M4_or_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 |= and($Rs32,$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111010;
@@ -16674,7 +17074,7 @@ def M4_or_andn : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 |= and($Rs32,~$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111001;
@@ -16688,7 +17088,7 @@ def M4_or_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 |= or($Rs32,$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111110;
@@ -16702,7 +17102,7 @@ def M4_or_xor : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 |= xor($Rs32,$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111110;
@@ -16716,7 +17116,7 @@ def M4_pmpyw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = pmpyw($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101010;
@@ -16726,7 +17126,7 @@ def M4_pmpyw_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 ^= pmpyw($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111001;
@@ -16737,7 +17137,7 @@ def M4_vpmpyh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = vpmpyh($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101110;
@@ -16747,7 +17147,7 @@ def M4_vpmpyh_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 ^= vpmpyh($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111101;
@@ -16758,7 +17158,7 @@ def M4_vrmpyeh_acc_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrmpyweh($Rss32,$Rtt32)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010001;
@@ -16769,7 +17169,7 @@ def M4_vrmpyeh_acc_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010101;
@@ -16780,7 +17180,7 @@ def M4_vrmpyeh_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrmpyweh($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000010;
@@ -16790,7 +17190,7 @@ def M4_vrmpyeh_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000110;
@@ -16800,7 +17200,7 @@ def M4_vrmpyoh_acc_s0 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrmpywoh($Rss32,$Rtt32)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010011;
@@ -16811,7 +17211,7 @@ def M4_vrmpyoh_acc_s1 : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010111;
@@ -16822,7 +17222,7 @@ def M4_vrmpyoh_s0 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrmpywoh($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000001;
@@ -16832,7 +17232,7 @@ def M4_vrmpyoh_s1 : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000101;
@@ -16842,7 +17242,7 @@ def M4_xor_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 ^= and($Rs32,$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111110;
@@ -16856,7 +17256,7 @@ def M4_xor_andn : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 ^= and($Rs32,~$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111001;
@@ -16870,7 +17270,7 @@ def M4_xor_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 ^= or($Rs32,$Rt32)",
-tc_3c10f809, TypeM>, Enc_2ae154 {
+tc_84df2cd3, TypeM>, Enc_2ae154 {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101111110;
@@ -16884,7 +17284,7 @@ def M4_xor_xacc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 ^= xor($Rss32,$Rtt32)",
-tc_3c10f809, TypeS_3op>, Enc_88c16c {
+tc_84df2cd3, TypeS_3op>, Enc_88c16c {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001010100;
@@ -16895,7 +17295,7 @@ def M5_vdmacbsu : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat",
-tc_8cb685d9, TypeM>, Enc_88c16c, Requires<[HasV5T]> {
+tc_e913dc32, TypeM>, Enc_88c16c, Requires<[HasV5T]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010001;
@@ -16907,7 +17307,7 @@ def M5_vdmpybsu : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat",
-tc_8c8041e6, TypeM>, Enc_a56825, Requires<[HasV5T]> {
+tc_8fd5f294, TypeM>, Enc_a56825, Requires<[HasV5T]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000101;
@@ -16918,7 +17318,7 @@ def M5_vmacbsu : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += vmpybsu($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111110;
@@ -16929,7 +17329,7 @@ def M5_vmacbuu : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rxx32 += vmpybu($Rs32,$Rt32)",
-tc_8cb685d9, TypeM>, Enc_61f0b0 {
+tc_e913dc32, TypeM>, Enc_61f0b0 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100111100;
@@ -16940,7 +17340,7 @@ def M5_vmpybsu : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = vmpybsu($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101010;
@@ -16950,7 +17350,7 @@ def M5_vmpybuu : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = vmpybu($Rs32,$Rt32)",
-tc_8c8041e6, TypeM>, Enc_be32a5 {
+tc_8fd5f294, TypeM>, Enc_be32a5 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11100101100;
@@ -16960,7 +17360,7 @@ def M5_vrmacbsu : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrmpybsu($Rss32,$Rtt32)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010110;
@@ -16971,7 +17371,7 @@ def M5_vrmacbuu : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 += vrmpybu($Rss32,$Rtt32)",
-tc_8cb685d9, TypeM>, Enc_88c16c {
+tc_e913dc32, TypeM>, Enc_88c16c {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101010100;
@@ -16982,7 +17382,7 @@ def M5_vrmpybsu : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrmpybsu($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000110;
@@ -16992,7 +17392,7 @@ def M5_vrmpybuu : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vrmpybu($Rss32,$Rtt32)",
-tc_8c8041e6, TypeM>, Enc_a56825 {
+tc_8fd5f294, TypeM>, Enc_a56825 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000100;
@@ -17002,7 +17402,7 @@ def M6_vabsdiffb : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vabsdiffb($Rtt32,$Rss32)",
-tc_faab1248, TypeM>, Enc_ea23e4, Requires<[HasV62T]> {
+tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62T]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000111;
@@ -17012,7 +17412,7 @@ def M6_vabsdiffub : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = vabsdiffub($Rtt32,$Rss32)",
-tc_faab1248, TypeM>, Enc_ea23e4, Requires<[HasV62T]> {
+tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62T]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11101000101;
@@ -17022,7 +17422,7 @@ def PS_loadrbabs : HInst<
 (outs IntRegs:$Rd32),
 (ins u32_0Imm:$Ii),
 "$Rd32 = memb(#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_25bef0, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
 let Inst{24-21} = 0b1000;
 let Inst{31-27} = 0b01001;
 let hasNewValue = 1;
@@ -17045,7 +17445,7 @@ def PS_loadrdabs : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins u29_3Imm:$Ii),
 "$Rdd32 = memd(#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_509701, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_509701, AddrModeRel {
 let Inst{24-21} = 0b1110;
 let Inst{31-27} = 0b01001;
 let addrMode = Absolute;
@@ -17066,7 +17466,7 @@ def PS_loadrhabs : HInst<
 (outs IntRegs:$Rd32),
 (ins u31_1Imm:$Ii),
 "$Rd32 = memh(#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_8df4be, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
 let Inst{24-21} = 0b1010;
 let Inst{31-27} = 0b01001;
 let hasNewValue = 1;
@@ -17089,7 +17489,7 @@ def PS_loadriabs : HInst<
 (outs IntRegs:$Rd32),
 (ins u30_2Imm:$Ii),
 "$Rd32 = memw(#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
 let Inst{24-21} = 0b1100;
 let Inst{31-27} = 0b01001;
 let hasNewValue = 1;
@@ -17112,7 +17512,7 @@ def PS_loadrubabs : HInst<
 (outs IntRegs:$Rd32),
 (ins u32_0Imm:$Ii),
 "$Rd32 = memub(#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_25bef0, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
 let Inst{24-21} = 0b1001;
 let Inst{31-27} = 0b01001;
 let hasNewValue = 1;
@@ -17135,7 +17535,7 @@ def PS_loadruhabs : HInst<
 (outs IntRegs:$Rd32),
 (ins u31_1Imm:$Ii),
 "$Rd32 = memuh(#$Ii)",
-tc_70cabf66, TypeV2LDST>, Enc_8df4be, AddrModeRel {
+tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
 let Inst{24-21} = 0b1011;
 let Inst{31-27} = 0b01001;
 let hasNewValue = 1;
@@ -17158,7 +17558,7 @@ def PS_storerbabs : HInst<
 (outs),
 (ins u32_0Imm:$Ii, IntRegs:$Rt32),
 "memb(#$Ii) = $Rt32",
-tc_c14739d5, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
+tc_a788683e, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
 let Inst{24-21} = 0b0000;
 let Inst{31-27} = 0b01001;
 let addrMode = Absolute;
@@ -17180,7 +17580,7 @@ def PS_storerbnewabs : HInst<
 (outs),
 (ins u32_0Imm:$Ii, IntRegs:$Nt8),
 "memb(#$Ii) = $Nt8.new",
-tc_9e86015f, TypeV2LDST>, Enc_ad1831, AddrModeRel {
+tc_ff9ee76e, TypeV2LDST>, Enc_ad1831, AddrModeRel {
 let Inst{12-11} = 0b00;
 let Inst{24-21} = 0b0101;
 let Inst{31-27} = 0b01001;
@@ -17189,6 +17589,7 @@ let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let BaseOpcode = "S2_storerbabs";
@@ -17205,7 +17606,7 @@ def PS_storerdabs : HInst<
 (outs),
 (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
 "memd(#$Ii) = $Rtt32",
-tc_c14739d5, TypeV2LDST>, Enc_5c124a, AddrModeRel {
+tc_a788683e, TypeV2LDST>, Enc_5c124a, AddrModeRel {
 let Inst{24-21} = 0b0110;
 let Inst{31-27} = 0b01001;
 let addrMode = Absolute;
@@ -17226,7 +17627,7 @@ def PS_storerfabs : HInst<
 (outs),
 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
 "memh(#$Ii) = $Rt32.h",
-tc_c14739d5, TypeV2LDST>, Enc_fda92c, AddrModeRel {
+tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
 let Inst{24-21} = 0b0011;
 let Inst{31-27} = 0b01001;
 let addrMode = Absolute;
@@ -17247,7 +17648,7 @@ def PS_storerhabs : HInst<
 (outs),
 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
 "memh(#$Ii) = $Rt32",
-tc_c14739d5, TypeV2LDST>, Enc_fda92c, AddrModeRel {
+tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
 let Inst{24-21} = 0b0010;
 let Inst{31-27} = 0b01001;
 let addrMode = Absolute;
@@ -17269,7 +17670,7 @@ def PS_storerhnewabs : HInst<
 (outs),
 (ins u31_1Imm:$Ii, IntRegs:$Nt8),
 "memh(#$Ii) = $Nt8.new",
-tc_9e86015f, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
+tc_ff9ee76e, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
 let Inst{12-11} = 0b01;
 let Inst{24-21} = 0b0101;
 let Inst{31-27} = 0b01001;
@@ -17278,6 +17679,7 @@ let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerhabs";
@@ -17294,7 +17696,7 @@ def PS_storeriabs : HInst<
 (outs),
 (ins u30_2Imm:$Ii, IntRegs:$Rt32),
 "memw(#$Ii) = $Rt32",
-tc_c14739d5, TypeV2LDST>, Enc_541f26, AddrModeRel {
+tc_a788683e, TypeV2LDST>, Enc_541f26, AddrModeRel {
 let Inst{24-21} = 0b0100;
 let Inst{31-27} = 0b01001;
 let addrMode = Absolute;
@@ -17316,7 +17718,7 @@ def PS_storerinewabs : HInst<
 (outs),
 (ins u30_2Imm:$Ii, IntRegs:$Nt8),
 "memw(#$Ii) = $Nt8.new",
-tc_9e86015f, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
+tc_ff9ee76e, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
 let Inst{12-11} = 0b10;
 let Inst{24-21} = 0b0101;
 let Inst{31-27} = 0b01001;
@@ -17325,6 +17727,7 @@ let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeriabs";
@@ -17341,7 +17744,7 @@ def S2_addasl_rrri : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii),
 "$Rd32 = addasl($Rt32,$Rs32,#$Ii)",
-tc_090485bb, TypeS_3op>, Enc_47ef61 {
+tc_c74f796f, TypeS_3op>, Enc_47ef61 {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000100000;
 let hasNewValue = 1;
@@ -17349,24 +17752,26 @@ let opNewValue = 0;
 let prefersSlot3 = 1;
 }
 def S2_allocframe : HInst<
-(outs),
-(ins u11_3Imm:$Ii),
-"allocframe(#$Ii)",
-tc_0cb867f2, TypeST>, Enc_22c845 {
+(outs IntRegs:$Rx32),
+(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
+"allocframe($Rx32,#$Ii):raw",
+tc_e216a5db, TypeST>, Enc_22c845 {
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b10100000100;
-let Inst{20-16} = 0b11101;
+let hasNewValue = 1;
+let opNewValue = 0;
 let addrMode = BaseImmOffset;
 let accessSize = DoubleWordAccess;
 let mayStore = 1;
-let Uses = [R29, R30, R31];
-let Defs = [R29, R30];
+let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
+let Defs = [R30];
+let Constraints = "$Rx32 = $Rx32in";
 }
 def S2_asl_i_p : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rdd32 = asl($Rss32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_5eac98 {
+tc_540fdfbc, TypeS_2op>, Enc_5eac98 {
 let Inst{7-5} = 0b010;
 let Inst{31-21} = 0b10000000000;
 }
@@ -17374,7 +17779,7 @@ def S2_asl_i_p_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 += asl($Rss32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_70fb07 {
+tc_c74f796f, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b110;
 let Inst{31-21} = 0b10000010000;
 let prefersSlot3 = 1;
@@ -17384,7 +17789,7 @@ def S2_asl_i_p_and : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 &= asl($Rss32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_70fb07 {
+tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b010;
 let Inst{31-21} = 0b10000010010;
 let prefersSlot3 = 1;
@@ -17394,7 +17799,7 @@ def S2_asl_i_p_nac : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 -= asl($Rss32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_70fb07 {
+tc_c74f796f, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b010;
 let Inst{31-21} = 0b10000010000;
 let prefersSlot3 = 1;
@@ -17404,7 +17809,7 @@ def S2_asl_i_p_or : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 |= asl($Rss32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_70fb07 {
+tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b110;
 let Inst{31-21} = 0b10000010010;
 let prefersSlot3 = 1;
@@ -17414,7 +17819,7 @@ def S2_asl_i_p_xacc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 ^= asl($Rss32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_70fb07 {
+tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b010;
 let Inst{31-21} = 0b10000010100;
 let prefersSlot3 = 1;
@@ -17424,7 +17829,7 @@ def S2_asl_i_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = asl($Rs32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_a05677 {
+tc_540fdfbc, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100000;
@@ -17435,7 +17840,7 @@ def S2_asl_i_r_acc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 += asl($Rs32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_28a2dc {
+tc_c74f796f, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110000;
@@ -17448,7 +17853,7 @@ def S2_asl_i_r_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 &= asl($Rs32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_28a2dc {
+tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110010;
@@ -17461,7 +17866,7 @@ def S2_asl_i_r_nac : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 -= asl($Rs32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_28a2dc {
+tc_c74f796f, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110000;
@@ -17474,7 +17879,7 @@ def S2_asl_i_r_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 |= asl($Rs32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_28a2dc {
+tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110010;
@@ -17487,7 +17892,7 @@ def S2_asl_i_r_sat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = asl($Rs32,#$Ii):sat",
-tc_47ab9233, TypeS_2op>, Enc_a05677 {
+tc_b44c6e2a, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100010;
@@ -17500,7 +17905,7 @@ def S2_asl_i_r_xacc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 ^= asl($Rs32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_28a2dc {
+tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110100;
@@ -17513,7 +17918,7 @@ def S2_asl_i_vh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
 "$Rdd32 = vaslh($Rss32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_12b6e9 {
+tc_540fdfbc, TypeS_2op>, Enc_12b6e9 {
 let Inst{7-5} = 0b010;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b10000000100;
@@ -17522,7 +17927,7 @@ def S2_asl_i_vw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
 "$Rdd32 = vaslw($Rss32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_7e5a82 {
+tc_540fdfbc, TypeS_2op>, Enc_7e5a82 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10000000010;
@@ -17531,7 +17936,7 @@ def S2_asl_r_p : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = asl($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011100;
@@ -17540,7 +17945,7 @@ def S2_asl_r_p_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 += asl($Rss32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_1aa186 {
+tc_c74f796f, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011110;
@@ -17551,7 +17956,7 @@ def S2_asl_r_p_and : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 &= asl($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011010;
@@ -17562,7 +17967,7 @@ def S2_asl_r_p_nac : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 -= asl($Rss32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_1aa186 {
+tc_c74f796f, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011100;
@@ -17573,7 +17978,7 @@ def S2_asl_r_p_or : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 |= asl($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011000;
@@ -17584,7 +17989,7 @@ def S2_asl_r_p_xor : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 ^= asl($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011011;
@@ -17595,7 +18000,7 @@ def S2_asl_r_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = asl($Rs32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_5ab2be {
+tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110010;
@@ -17606,7 +18011,7 @@ def S2_asl_r_r_acc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += asl($Rs32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_2ae154 {
+tc_c74f796f, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100110;
@@ -17619,7 +18024,7 @@ def S2_asl_r_r_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 &= asl($Rs32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_2ae154 {
+tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100010;
@@ -17632,7 +18037,7 @@ def S2_asl_r_r_nac : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= asl($Rs32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_2ae154 {
+tc_c74f796f, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100100;
@@ -17645,7 +18050,7 @@ def S2_asl_r_r_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 |= asl($Rs32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_2ae154 {
+tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100000;
@@ -17658,7 +18063,7 @@ def S2_asl_r_r_sat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = asl($Rs32,$Rt32):sat",
-tc_47ab9233, TypeS_3op>, Enc_5ab2be {
+tc_b44c6e2a, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110000;
@@ -17671,7 +18076,7 @@ def S2_asl_r_vh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vaslh($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011010;
@@ -17680,7 +18085,7 @@ def S2_asl_r_vw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vaslw($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011000;
@@ -17689,7 +18094,7 @@ def S2_asr_i_p : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rdd32 = asr($Rss32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_5eac98 {
+tc_540fdfbc, TypeS_2op>, Enc_5eac98 {
 let Inst{7-5} = 0b000;
 let Inst{31-21} = 0b10000000000;
 }
@@ -17697,7 +18102,7 @@ def S2_asr_i_p_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 += asr($Rss32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_70fb07 {
+tc_c74f796f, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b100;
 let Inst{31-21} = 0b10000010000;
 let prefersSlot3 = 1;
@@ -17707,7 +18112,7 @@ def S2_asr_i_p_and : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 &= asr($Rss32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_70fb07 {
+tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b000;
 let Inst{31-21} = 0b10000010010;
 let prefersSlot3 = 1;
@@ -17717,7 +18122,7 @@ def S2_asr_i_p_nac : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 -= asr($Rss32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_70fb07 {
+tc_c74f796f, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b000;
 let Inst{31-21} = 0b10000010000;
 let prefersSlot3 = 1;
@@ -17727,7 +18132,7 @@ def S2_asr_i_p_or : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 |= asr($Rss32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_70fb07 {
+tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b100;
 let Inst{31-21} = 0b10000010010;
 let prefersSlot3 = 1;
@@ -17737,7 +18142,7 @@ def S2_asr_i_p_rnd : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rdd32 = asr($Rss32,#$Ii):rnd",
-tc_63cd9d2d, TypeS_2op>, Enc_5eac98, Requires<[HasV5T]> {
+tc_2b6f77c6, TypeS_2op>, Enc_5eac98, Requires<[HasV5T]> {
 let Inst{7-5} = 0b111;
 let Inst{31-21} = 0b10000000110;
 let prefersSlot3 = 1;
@@ -17746,14 +18151,14 @@ def S2_asr_i_p_rnd_goodsyntax : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rdd32 = asrrnd($Rss32,#$Ii)",
-tc_63cd9d2d, TypeS_2op>, Requires<[HasV5T]> {
+tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> {
 let isPseudo = 1;
 }
 def S2_asr_i_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = asr($Rs32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_a05677 {
+tc_540fdfbc, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100000;
@@ -17764,7 +18169,7 @@ def S2_asr_i_r_acc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 += asr($Rs32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_28a2dc {
+tc_c74f796f, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110000;
@@ -17777,7 +18182,7 @@ def S2_asr_i_r_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 &= asr($Rs32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_28a2dc {
+tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110010;
@@ -17790,7 +18195,7 @@ def S2_asr_i_r_nac : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 -= asr($Rs32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_28a2dc {
+tc_c74f796f, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110000;
@@ -17803,7 +18208,7 @@ def S2_asr_i_r_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 |= asr($Rs32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_28a2dc {
+tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110010;
@@ -17816,7 +18221,7 @@ def S2_asr_i_r_rnd : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = asr($Rs32,#$Ii):rnd",
-tc_63cd9d2d, TypeS_2op>, Enc_a05677 {
+tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100010;
@@ -17828,7 +18233,7 @@ def S2_asr_i_r_rnd_goodsyntax : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = asrrnd($Rs32,#$Ii)",
-tc_63cd9d2d, TypeS_2op> {
+tc_2b6f77c6, TypeS_2op> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -17837,7 +18242,7 @@ def S2_asr_i_svw_trun : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
 "$Rd32 = vasrw($Rss32,#$Ii)",
-tc_7ca2ea10, TypeS_2op>, Enc_8dec2e {
+tc_1b9c9ee5, TypeS_2op>, Enc_8dec2e {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001000110;
@@ -17849,7 +18254,7 @@ def S2_asr_i_vh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
 "$Rdd32 = vasrh($Rss32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_12b6e9 {
+tc_540fdfbc, TypeS_2op>, Enc_12b6e9 {
 let Inst{7-5} = 0b000;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b10000000100;
@@ -17858,7 +18263,7 @@ def S2_asr_i_vw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
 "$Rdd32 = vasrw($Rss32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_7e5a82 {
+tc_540fdfbc, TypeS_2op>, Enc_7e5a82 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10000000010;
@@ -17867,7 +18272,7 @@ def S2_asr_r_p : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = asr($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011100;
@@ -17876,7 +18281,7 @@ def S2_asr_r_p_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 += asr($Rss32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_1aa186 {
+tc_c74f796f, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011110;
@@ -17887,7 +18292,7 @@ def S2_asr_r_p_and : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 &= asr($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011010;
@@ -17898,7 +18303,7 @@ def S2_asr_r_p_nac : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 -= asr($Rss32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_1aa186 {
+tc_c74f796f, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011100;
@@ -17909,7 +18314,7 @@ def S2_asr_r_p_or : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 |= asr($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011000;
@@ -17920,7 +18325,7 @@ def S2_asr_r_p_xor : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 ^= asr($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011011;
@@ -17931,7 +18336,7 @@ def S2_asr_r_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = asr($Rs32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_5ab2be {
+tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110010;
@@ -17942,7 +18347,7 @@ def S2_asr_r_r_acc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += asr($Rs32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_2ae154 {
+tc_c74f796f, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100110;
@@ -17955,7 +18360,7 @@ def S2_asr_r_r_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 &= asr($Rs32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_2ae154 {
+tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100010;
@@ -17968,7 +18373,7 @@ def S2_asr_r_r_nac : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= asr($Rs32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_2ae154 {
+tc_c74f796f, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100100;
@@ -17981,7 +18386,7 @@ def S2_asr_r_r_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 |= asr($Rs32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_2ae154 {
+tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100000;
@@ -17994,7 +18399,7 @@ def S2_asr_r_r_sat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = asr($Rs32,$Rt32):sat",
-tc_47ab9233, TypeS_3op>, Enc_5ab2be {
+tc_b44c6e2a, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110000;
@@ -18007,7 +18412,7 @@ def S2_asr_r_svw_trun : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rd32 = vasrw($Rss32,$Rt32)",
-tc_7ca2ea10, TypeS_3op>, Enc_3d5b28 {
+tc_1b9c9ee5, TypeS_3op>, Enc_3d5b28 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000101000;
@@ -18019,7 +18424,7 @@ def S2_asr_r_vh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vasrh($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011010;
@@ -18028,7 +18433,7 @@ def S2_asr_r_vw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vasrw($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011000;
@@ -18037,7 +18442,7 @@ def S2_brev : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = brev($Rs32)",
-tc_ab1b5e74, TypeS_2op>, Enc_5e2823 {
+tc_d088982c, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10001100010;
 let hasNewValue = 1;
@@ -18048,7 +18453,7 @@ def S2_brevp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = brev($Rss32)",
-tc_ab1b5e74, TypeS_2op>, Enc_b9c5fb {
+tc_d088982c, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10000000110;
 let prefersSlot3 = 1;
@@ -18057,7 +18462,7 @@ def S2_cabacdecbin : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = decbin($Rss32,$Rtt32)",
-tc_5d806107, TypeS_3op>, Enc_a56825 {
+tc_c6ebf8dd, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001110;
@@ -18069,7 +18474,7 @@ def S2_cl0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = cl0($Rs32)",
-tc_ab1b5e74, TypeS_2op>, Enc_5e2823 {
+tc_d088982c, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000101;
 let Inst{31-21} = 0b10001100000;
 let hasNewValue = 1;
@@ -18080,7 +18485,7 @@ def S2_cl0p : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = cl0($Rss32)",
-tc_ab1b5e74, TypeS_2op>, Enc_90cd8b {
+tc_d088982c, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000010;
 let Inst{31-21} = 0b10001000010;
 let hasNewValue = 1;
@@ -18091,7 +18496,7 @@ def S2_cl1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = cl1($Rs32)",
-tc_ab1b5e74, TypeS_2op>, Enc_5e2823 {
+tc_d088982c, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10001100000;
 let hasNewValue = 1;
@@ -18102,7 +18507,7 @@ def S2_cl1p : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = cl1($Rss32)",
-tc_ab1b5e74, TypeS_2op>, Enc_90cd8b {
+tc_d088982c, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10001000010;
 let hasNewValue = 1;
@@ -18113,7 +18518,7 @@ def S2_clb : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = clb($Rs32)",
-tc_ab1b5e74, TypeS_2op>, Enc_5e2823 {
+tc_d088982c, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10001100000;
 let hasNewValue = 1;
@@ -18124,7 +18529,7 @@ def S2_clbnorm : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = normamt($Rs32)",
-tc_ab1b5e74, TypeS_2op>, Enc_5e2823 {
+tc_d088982c, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000111;
 let Inst{31-21} = 0b10001100000;
 let hasNewValue = 1;
@@ -18135,7 +18540,7 @@ def S2_clbp : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = clb($Rss32)",
-tc_ab1b5e74, TypeS_2op>, Enc_90cd8b {
+tc_d088982c, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001000010;
 let hasNewValue = 1;
@@ -18146,7 +18551,7 @@ def S2_clrbit_i : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = clrbit($Rs32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_a05677 {
+tc_540fdfbc, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100110;
@@ -18157,7 +18562,7 @@ def S2_clrbit_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = clrbit($Rs32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_5ab2be {
+tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110100;
@@ -18168,7 +18573,7 @@ def S2_ct0 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = ct0($Rs32)",
-tc_ab1b5e74, TypeS_2op>, Enc_5e2823 {
+tc_d088982c, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10001100010;
 let hasNewValue = 1;
@@ -18179,7 +18584,7 @@ def S2_ct0p : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = ct0($Rss32)",
-tc_ab1b5e74, TypeS_2op>, Enc_90cd8b {
+tc_d088982c, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000010;
 let Inst{31-21} = 0b10001000111;
 let hasNewValue = 1;
@@ -18190,7 +18595,7 @@ def S2_ct1 : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = ct1($Rs32)",
-tc_ab1b5e74, TypeS_2op>, Enc_5e2823 {
+tc_d088982c, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000101;
 let Inst{31-21} = 0b10001100010;
 let hasNewValue = 1;
@@ -18201,7 +18606,7 @@ def S2_ct1p : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = ct1($Rss32)",
-tc_ab1b5e74, TypeS_2op>, Enc_90cd8b {
+tc_d088982c, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10001000111;
 let hasNewValue = 1;
@@ -18212,7 +18617,7 @@ def S2_deinterleave : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = deinterleave($Rss32)",
-tc_ab1b5e74, TypeS_2op>, Enc_b9c5fb {
+tc_d088982c, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10000000110;
 let prefersSlot3 = 1;
@@ -18221,7 +18626,7 @@ def S2_extractu : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
 "$Rd32 = extractu($Rs32,#$Ii,#$II)",
-tc_c0cd91a8, TypeS_2op>, Enc_b388cf {
+tc_c74f796f, TypeS_2op>, Enc_b388cf {
 let Inst{13-13} = 0b0;
 let Inst{31-23} = 0b100011010;
 let hasNewValue = 1;
@@ -18232,7 +18637,7 @@ def S2_extractu_rp : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "$Rd32 = extractu($Rs32,$Rtt32)",
-tc_87601822, TypeS_3op>, Enc_e07374 {
+tc_2b6f77c6, TypeS_3op>, Enc_e07374 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001001000;
@@ -18244,7 +18649,7 @@ def S2_extractup : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
 "$Rdd32 = extractu($Rss32,#$Ii,#$II)",
-tc_c0cd91a8, TypeS_2op>, Enc_b84c4c {
+tc_c74f796f, TypeS_2op>, Enc_b84c4c {
 let Inst{31-24} = 0b10000001;
 let prefersSlot3 = 1;
 }
@@ -18252,7 +18657,7 @@ def S2_extractup_rp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = extractu($Rss32,$Rtt32)",
-tc_87601822, TypeS_3op>, Enc_a56825 {
+tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001000;
@@ -18262,7 +18667,7 @@ def S2_insert : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
 "$Rx32 = insert($Rs32,#$Ii,#$II)",
-tc_d95f4e98, TypeS_2op>, Enc_a1e29d {
+tc_87735c3b, TypeS_2op>, Enc_a1e29d {
 let Inst{13-13} = 0b0;
 let Inst{31-23} = 0b100011110;
 let hasNewValue = 1;
@@ -18274,7 +18679,7 @@ def S2_insert_rp : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "$Rx32 = insert($Rs32,$Rtt32)",
-tc_3c10f809, TypeS_3op>, Enc_179b35 {
+tc_84df2cd3, TypeS_3op>, Enc_179b35 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001000000;
@@ -18287,7 +18692,7 @@ def S2_insertp : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
 "$Rxx32 = insert($Rss32,#$Ii,#$II)",
-tc_d95f4e98, TypeS_2op>, Enc_143a3c {
+tc_87735c3b, TypeS_2op>, Enc_143a3c {
 let Inst{31-24} = 0b10000011;
 let prefersSlot3 = 1;
 let Constraints = "$Rxx32 = $Rxx32in";
@@ -18296,7 +18701,7 @@ def S2_insertp_rp : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rxx32 = insert($Rss32,$Rtt32)",
-tc_3c10f809, TypeS_3op>, Enc_88c16c {
+tc_84df2cd3, TypeS_3op>, Enc_88c16c {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001010000;
@@ -18307,7 +18712,7 @@ def S2_interleave : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = interleave($Rss32)",
-tc_ab1b5e74, TypeS_2op>, Enc_b9c5fb {
+tc_d088982c, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000101;
 let Inst{31-21} = 0b10000000110;
 let prefersSlot3 = 1;
@@ -18316,7 +18721,7 @@ def S2_lfsp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = lfs($Rss32,$Rtt32)",
-tc_87601822, TypeS_3op>, Enc_a56825 {
+tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001100;
@@ -18326,7 +18731,7 @@ def S2_lsl_r_p : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = lsl($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011100;
@@ -18335,7 +18740,7 @@ def S2_lsl_r_p_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 += lsl($Rss32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_1aa186 {
+tc_c74f796f, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011110;
@@ -18346,7 +18751,7 @@ def S2_lsl_r_p_and : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 &= lsl($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011010;
@@ -18357,7 +18762,7 @@ def S2_lsl_r_p_nac : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 -= lsl($Rss32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_1aa186 {
+tc_c74f796f, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011100;
@@ -18368,7 +18773,7 @@ def S2_lsl_r_p_or : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 |= lsl($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011000;
@@ -18379,7 +18784,7 @@ def S2_lsl_r_p_xor : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 ^= lsl($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011011;
@@ -18390,7 +18795,7 @@ def S2_lsl_r_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = lsl($Rs32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_5ab2be {
+tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110010;
@@ -18401,7 +18806,7 @@ def S2_lsl_r_r_acc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += lsl($Rs32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_2ae154 {
+tc_c74f796f, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100110;
@@ -18414,7 +18819,7 @@ def S2_lsl_r_r_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 &= lsl($Rs32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_2ae154 {
+tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100010;
@@ -18427,7 +18832,7 @@ def S2_lsl_r_r_nac : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= lsl($Rs32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_2ae154 {
+tc_c74f796f, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100100;
@@ -18440,7 +18845,7 @@ def S2_lsl_r_r_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 |= lsl($Rs32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_2ae154 {
+tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100000;
@@ -18453,7 +18858,7 @@ def S2_lsl_r_vh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vlslh($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011010;
@@ -18462,7 +18867,7 @@ def S2_lsl_r_vw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vlslw($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011000;
@@ -18471,7 +18876,7 @@ def S2_lsr_i_p : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rdd32 = lsr($Rss32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_5eac98 {
+tc_540fdfbc, TypeS_2op>, Enc_5eac98 {
 let Inst{7-5} = 0b001;
 let Inst{31-21} = 0b10000000000;
 }
@@ -18479,7 +18884,7 @@ def S2_lsr_i_p_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 += lsr($Rss32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_70fb07 {
+tc_c74f796f, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b101;
 let Inst{31-21} = 0b10000010000;
 let prefersSlot3 = 1;
@@ -18489,7 +18894,7 @@ def S2_lsr_i_p_and : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 &= lsr($Rss32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_70fb07 {
+tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b001;
 let Inst{31-21} = 0b10000010010;
 let prefersSlot3 = 1;
@@ -18499,7 +18904,7 @@ def S2_lsr_i_p_nac : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 -= lsr($Rss32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_70fb07 {
+tc_c74f796f, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b001;
 let Inst{31-21} = 0b10000010000;
 let prefersSlot3 = 1;
@@ -18509,7 +18914,7 @@ def S2_lsr_i_p_or : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 |= lsr($Rss32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_70fb07 {
+tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b101;
 let Inst{31-21} = 0b10000010010;
 let prefersSlot3 = 1;
@@ -18519,7 +18924,7 @@ def S2_lsr_i_p_xacc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 ^= lsr($Rss32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_70fb07 {
+tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
 let Inst{7-5} = 0b001;
 let Inst{31-21} = 0b10000010100;
 let prefersSlot3 = 1;
@@ -18529,7 +18934,7 @@ def S2_lsr_i_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = lsr($Rs32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_a05677 {
+tc_540fdfbc, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100000;
@@ -18540,7 +18945,7 @@ def S2_lsr_i_r_acc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 += lsr($Rs32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_28a2dc {
+tc_c74f796f, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110000;
@@ -18553,7 +18958,7 @@ def S2_lsr_i_r_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 &= lsr($Rs32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_28a2dc {
+tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110010;
@@ -18566,7 +18971,7 @@ def S2_lsr_i_r_nac : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 -= lsr($Rs32,#$Ii)",
-tc_c0cd91a8, TypeS_2op>, Enc_28a2dc {
+tc_c74f796f, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110000;
@@ -18579,7 +18984,7 @@ def S2_lsr_i_r_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 |= lsr($Rs32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_28a2dc {
+tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110010;
@@ -18592,7 +18997,7 @@ def S2_lsr_i_r_xacc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 ^= lsr($Rs32,#$Ii)",
-tc_3c10f809, TypeS_2op>, Enc_28a2dc {
+tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110100;
@@ -18605,7 +19010,7 @@ def S2_lsr_i_vh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
 "$Rdd32 = vlsrh($Rss32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_12b6e9 {
+tc_540fdfbc, TypeS_2op>, Enc_12b6e9 {
 let Inst{7-5} = 0b001;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b10000000100;
@@ -18614,7 +19019,7 @@ def S2_lsr_i_vw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
 "$Rdd32 = vlsrw($Rss32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_7e5a82 {
+tc_540fdfbc, TypeS_2op>, Enc_7e5a82 {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10000000010;
@@ -18623,7 +19028,7 @@ def S2_lsr_r_p : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = lsr($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011100;
@@ -18632,7 +19037,7 @@ def S2_lsr_r_p_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 += lsr($Rss32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_1aa186 {
+tc_c74f796f, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011110;
@@ -18643,7 +19048,7 @@ def S2_lsr_r_p_and : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 &= lsr($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011010;
@@ -18654,7 +19059,7 @@ def S2_lsr_r_p_nac : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 -= lsr($Rss32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_1aa186 {
+tc_c74f796f, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011100;
@@ -18665,7 +19070,7 @@ def S2_lsr_r_p_or : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 |= lsr($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011000;
@@ -18676,7 +19081,7 @@ def S2_lsr_r_p_xor : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 ^= lsr($Rss32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_1aa186 {
+tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001011011;
@@ -18687,7 +19092,7 @@ def S2_lsr_r_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = lsr($Rs32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_5ab2be {
+tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110010;
@@ -18698,7 +19103,7 @@ def S2_lsr_r_r_acc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 += lsr($Rs32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_2ae154 {
+tc_c74f796f, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100110;
@@ -18711,7 +19116,7 @@ def S2_lsr_r_r_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 &= lsr($Rs32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_2ae154 {
+tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100010;
@@ -18724,7 +19129,7 @@ def S2_lsr_r_r_nac : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 -= lsr($Rs32,$Rt32)",
-tc_c0cd91a8, TypeS_3op>, Enc_2ae154 {
+tc_c74f796f, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100100;
@@ -18737,7 +19142,7 @@ def S2_lsr_r_r_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rx32 |= lsr($Rs32,$Rt32)",
-tc_3c10f809, TypeS_3op>, Enc_2ae154 {
+tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001100000;
@@ -18750,7 +19155,7 @@ def S2_lsr_r_vh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vlsrh($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011010;
@@ -18759,7 +19164,7 @@ def S2_lsr_r_vw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vlsrw($Rss32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_927852 {
+tc_540fdfbc, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011000;
@@ -18768,7 +19173,7 @@ def S2_packhl : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = packhl($Rs32,$Rt32)",
-tc_548f402d, TypeALU32_3op>, Enc_be32a5 {
+tc_b9488031, TypeALU32_3op>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11110101100;
@@ -18778,7 +19183,7 @@ def S2_parityp : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rd32 = parity($Rss32,$Rtt32)",
-tc_87601822, TypeALU64>, Enc_d2216a {
+tc_2b6f77c6, TypeALU64>, Enc_d2216a {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010000000;
@@ -18790,7 +19195,7 @@ def S2_pstorerbf_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memb($Rs32+#$Ii) = $Rt32",
-tc_3d905451, TypeV2LDST>, Enc_da8d43, AddrModeRel {
+tc_8b15472a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000100000;
 let isPredicated = 1;
@@ -18812,7 +19217,7 @@ def S2_pstorerbf_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memb($Rx32++#$Ii) = $Rt32",
-tc_9b73d261, TypeST>, Enc_cc449f, AddrModeRel {
+tc_cd7374a0, TypeST>, Enc_cc449f, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
@@ -18830,7 +19235,7 @@ def S2_pstorerbf_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pv4) memb($Rs32) = $Rt32",
-tc_3d905451, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -18838,7 +19243,7 @@ def S2_pstorerbfnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32",
-tc_7675c0e9, TypeST>, Enc_cc449f, AddrModeRel {
+tc_74e47fd9, TypeST>, Enc_cc449f, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -18857,7 +19262,7 @@ def S2_pstorerbnewf_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new",
-tc_9da3628f, TypeV2LDST>, Enc_585242, AddrModeRel {
+tc_594ab548, TypeV2LDST>, Enc_585242, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b01000100101;
@@ -18867,6 +19272,7 @@ let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let InputType = "imm";
@@ -18882,7 +19288,7 @@ def S2_pstorerbnewf_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new",
-tc_e2480a7f, TypeST>, Enc_52a5dd, AddrModeRel {
+tc_d9f95eef, TypeST>, Enc_52a5dd, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b0;
 let Inst{13-11} = 0b100;
@@ -18893,6 +19299,7 @@ let addrMode = PostInc;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let BaseOpcode = "S2_storerb_pi";
@@ -18903,7 +19310,7 @@ def S2_pstorerbnewf_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if (!$Pv4) memb($Rs32) = $Nt8.new",
-tc_9da3628f, TypeMAPPING> {
+tc_594ab548, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -18912,7 +19319,7 @@ def S2_pstorerbnewfnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
-tc_8fab9ac3, TypeST>, Enc_52a5dd, AddrModeRel {
+tc_d24b2d85, TypeST>, Enc_52a5dd, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b100;
@@ -18924,6 +19331,7 @@ let accessSize = ByteAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let BaseOpcode = "S2_storerb_pi";
@@ -18934,7 +19342,7 @@ def S2_pstorerbnewt_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new",
-tc_9da3628f, TypeV2LDST>, Enc_585242, AddrModeRel {
+tc_594ab548, TypeV2LDST>, Enc_585242, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b01000000101;
@@ -18943,6 +19351,7 @@ let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let InputType = "imm";
@@ -18958,7 +19367,7 @@ def S2_pstorerbnewt_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new",
-tc_e2480a7f, TypeST>, Enc_52a5dd, AddrModeRel {
+tc_d9f95eef, TypeST>, Enc_52a5dd, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b0;
 let Inst{13-11} = 0b100;
@@ -18968,6 +19377,7 @@ let addrMode = PostInc;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let BaseOpcode = "S2_storerb_pi";
@@ -18978,7 +19388,7 @@ def S2_pstorerbnewt_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if ($Pv4) memb($Rs32) = $Nt8.new",
-tc_9da3628f, TypeMAPPING> {
+tc_594ab548, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -18987,7 +19397,7 @@ def S2_pstorerbnewtnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
-tc_8fab9ac3, TypeST>, Enc_52a5dd, AddrModeRel {
+tc_d24b2d85, TypeST>, Enc_52a5dd, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b100;
@@ -18998,6 +19408,7 @@ let accessSize = ByteAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let BaseOpcode = "S2_storerb_pi";
@@ -19008,7 +19419,7 @@ def S2_pstorerbt_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memb($Rs32+#$Ii) = $Rt32",
-tc_3d905451, TypeV2LDST>, Enc_da8d43, AddrModeRel {
+tc_8b15472a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000000000;
 let isPredicated = 1;
@@ -19029,7 +19440,7 @@ def S2_pstorerbt_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memb($Rx32++#$Ii) = $Rt32",
-tc_9b73d261, TypeST>, Enc_cc449f, AddrModeRel {
+tc_cd7374a0, TypeST>, Enc_cc449f, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
@@ -19046,7 +19457,7 @@ def S2_pstorerbt_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pv4) memb($Rs32) = $Rt32",
-tc_3d905451, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -19054,7 +19465,7 @@ def S2_pstorerbtnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32",
-tc_7675c0e9, TypeST>, Enc_cc449f, AddrModeRel {
+tc_74e47fd9, TypeST>, Enc_cc449f, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -19072,7 +19483,7 @@ def S2_pstorerdf_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
 "if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32",
-tc_3d905451, TypeV2LDST>, Enc_57a33e, AddrModeRel {
+tc_8b15472a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000100110;
 let isPredicated = 1;
@@ -19093,7 +19504,7 @@ def S2_pstorerdf_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
 "if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32",
-tc_9b73d261, TypeST>, Enc_9a33d5, AddrModeRel {
+tc_cd7374a0, TypeST>, Enc_9a33d5, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
@@ -19111,7 +19522,7 @@ def S2_pstorerdf_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "if (!$Pv4) memd($Rs32) = $Rtt32",
-tc_3d905451, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -19119,7 +19530,7 @@ def S2_pstorerdfnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
 "if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
-tc_7675c0e9, TypeST>, Enc_9a33d5, AddrModeRel {
+tc_74e47fd9, TypeST>, Enc_9a33d5, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -19138,7 +19549,7 @@ def S2_pstorerdt_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
 "if ($Pv4) memd($Rs32+#$Ii) = $Rtt32",
-tc_3d905451, TypeV2LDST>, Enc_57a33e, AddrModeRel {
+tc_8b15472a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000000110;
 let isPredicated = 1;
@@ -19158,7 +19569,7 @@ def S2_pstorerdt_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
 "if ($Pv4) memd($Rx32++#$Ii) = $Rtt32",
-tc_9b73d261, TypeST>, Enc_9a33d5, AddrModeRel {
+tc_cd7374a0, TypeST>, Enc_9a33d5, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
@@ -19175,7 +19586,7 @@ def S2_pstorerdt_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "if ($Pv4) memd($Rs32) = $Rtt32",
-tc_3d905451, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -19183,7 +19594,7 @@ def S2_pstorerdtnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
 "if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
-tc_7675c0e9, TypeST>, Enc_9a33d5, AddrModeRel {
+tc_74e47fd9, TypeST>, Enc_9a33d5, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -19201,7 +19612,7 @@ def S2_pstorerff_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h",
-tc_3d905451, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
+tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000100011;
 let isPredicated = 1;
@@ -19222,7 +19633,7 @@ def S2_pstorerff_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h",
-tc_9b73d261, TypeST>, Enc_b886fd, AddrModeRel {
+tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
@@ -19240,7 +19651,7 @@ def S2_pstorerff_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pv4) memh($Rs32) = $Rt32.h",
-tc_3d905451, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -19248,7 +19659,7 @@ def S2_pstorerffnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
-tc_7675c0e9, TypeST>, Enc_b886fd, AddrModeRel {
+tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -19267,7 +19678,7 @@ def S2_pstorerft_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h",
-tc_3d905451, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
+tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000000011;
 let isPredicated = 1;
@@ -19287,7 +19698,7 @@ def S2_pstorerft_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h",
-tc_9b73d261, TypeST>, Enc_b886fd, AddrModeRel {
+tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
@@ -19304,7 +19715,7 @@ def S2_pstorerft_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pv4) memh($Rs32) = $Rt32.h",
-tc_3d905451, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -19312,7 +19723,7 @@ def S2_pstorerftnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
-tc_7675c0e9, TypeST>, Enc_b886fd, AddrModeRel {
+tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -19330,7 +19741,7 @@ def S2_pstorerhf_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32",
-tc_3d905451, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
+tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000100010;
 let isPredicated = 1;
@@ -19352,7 +19763,7 @@ def S2_pstorerhf_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32",
-tc_9b73d261, TypeST>, Enc_b886fd, AddrModeRel {
+tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
@@ -19370,7 +19781,7 @@ def S2_pstorerhf_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pv4) memh($Rs32) = $Rt32",
-tc_3d905451, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -19378,7 +19789,7 @@ def S2_pstorerhfnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32",
-tc_7675c0e9, TypeST>, Enc_b886fd, AddrModeRel {
+tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -19397,7 +19808,7 @@ def S2_pstorerhnewf_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new",
-tc_9da3628f, TypeV2LDST>, Enc_f44229, AddrModeRel {
+tc_594ab548, TypeV2LDST>, Enc_f44229, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b01;
 let Inst{31-21} = 0b01000100101;
@@ -19407,6 +19818,7 @@ let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let InputType = "imm";
@@ -19422,7 +19834,7 @@ def S2_pstorerhnewf_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new",
-tc_e2480a7f, TypeST>, Enc_31aa6a, AddrModeRel {
+tc_d9f95eef, TypeST>, Enc_31aa6a, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b0;
 let Inst{13-11} = 0b101;
@@ -19433,6 +19845,7 @@ let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerh_pi";
@@ -19443,7 +19856,7 @@ def S2_pstorerhnewf_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if (!$Pv4) memh($Rs32) = $Nt8.new",
-tc_9da3628f, TypeMAPPING> {
+tc_594ab548, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -19452,7 +19865,7 @@ def S2_pstorerhnewfnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
-tc_8fab9ac3, TypeST>, Enc_31aa6a, AddrModeRel {
+tc_d24b2d85, TypeST>, Enc_31aa6a, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b101;
@@ -19464,6 +19877,7 @@ let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerh_pi";
@@ -19474,7 +19888,7 @@ def S2_pstorerhnewt_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new",
-tc_9da3628f, TypeV2LDST>, Enc_f44229, AddrModeRel {
+tc_594ab548, TypeV2LDST>, Enc_f44229, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b01;
 let Inst{31-21} = 0b01000000101;
@@ -19483,6 +19897,7 @@ let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let InputType = "imm";
@@ -19498,7 +19913,7 @@ def S2_pstorerhnewt_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new",
-tc_e2480a7f, TypeST>, Enc_31aa6a, AddrModeRel {
+tc_d9f95eef, TypeST>, Enc_31aa6a, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b0;
 let Inst{13-11} = 0b101;
@@ -19508,6 +19923,7 @@ let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerh_pi";
@@ -19518,7 +19934,7 @@ def S2_pstorerhnewt_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if ($Pv4) memh($Rs32) = $Nt8.new",
-tc_9da3628f, TypeMAPPING> {
+tc_594ab548, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -19527,7 +19943,7 @@ def S2_pstorerhnewtnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
-tc_8fab9ac3, TypeST>, Enc_31aa6a, AddrModeRel {
+tc_d24b2d85, TypeST>, Enc_31aa6a, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b101;
@@ -19538,6 +19954,7 @@ let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerh_pi";
@@ -19548,7 +19965,7 @@ def S2_pstorerht_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memh($Rs32+#$Ii) = $Rt32",
-tc_3d905451, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
+tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000000010;
 let isPredicated = 1;
@@ -19569,7 +19986,7 @@ def S2_pstorerht_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memh($Rx32++#$Ii) = $Rt32",
-tc_9b73d261, TypeST>, Enc_b886fd, AddrModeRel {
+tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
@@ -19586,7 +20003,7 @@ def S2_pstorerht_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pv4) memh($Rs32) = $Rt32",
-tc_3d905451, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -19594,7 +20011,7 @@ def S2_pstorerhtnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32",
-tc_7675c0e9, TypeST>, Enc_b886fd, AddrModeRel {
+tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -19612,7 +20029,7 @@ def S2_pstorerif_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memw($Rs32+#$Ii) = $Rt32",
-tc_3d905451, TypeV2LDST>, Enc_397f23, AddrModeRel {
+tc_8b15472a, TypeV2LDST>, Enc_397f23, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000100100;
 let isPredicated = 1;
@@ -19634,7 +20051,7 @@ def S2_pstorerif_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memw($Rx32++#$Ii) = $Rt32",
-tc_9b73d261, TypeST>, Enc_7eaeb6, AddrModeRel {
+tc_cd7374a0, TypeST>, Enc_7eaeb6, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
@@ -19652,7 +20069,7 @@ def S2_pstorerif_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pv4) memw($Rs32) = $Rt32",
-tc_3d905451, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -19660,7 +20077,7 @@ def S2_pstorerifnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32",
-tc_7675c0e9, TypeST>, Enc_7eaeb6, AddrModeRel {
+tc_74e47fd9, TypeST>, Enc_7eaeb6, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -19680,7 +20097,7 @@ def S2_pstorerinewf_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new",
-tc_9da3628f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
+tc_594ab548, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b10;
 let Inst{31-21} = 0b01000100101;
@@ -19690,6 +20107,7 @@ let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let InputType = "imm";
@@ -19705,7 +20123,7 @@ def S2_pstorerinewf_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new",
-tc_e2480a7f, TypeST>, Enc_65f095, AddrModeRel {
+tc_d9f95eef, TypeST>, Enc_65f095, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b0;
 let Inst{13-11} = 0b110;
@@ -19716,6 +20134,7 @@ let addrMode = PostInc;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeri_pi";
@@ -19726,7 +20145,7 @@ def S2_pstorerinewf_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if (!$Pv4) memw($Rs32) = $Nt8.new",
-tc_9da3628f, TypeMAPPING> {
+tc_594ab548, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -19735,7 +20154,7 @@ def S2_pstorerinewfnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
-tc_8fab9ac3, TypeST>, Enc_65f095, AddrModeRel {
+tc_d24b2d85, TypeST>, Enc_65f095, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b110;
@@ -19747,6 +20166,7 @@ let accessSize = WordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeri_pi";
@@ -19757,7 +20177,7 @@ def S2_pstorerinewt_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new",
-tc_9da3628f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
+tc_594ab548, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b10;
 let Inst{31-21} = 0b01000000101;
@@ -19766,6 +20186,7 @@ let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let InputType = "imm";
@@ -19781,7 +20202,7 @@ def S2_pstorerinewt_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new",
-tc_e2480a7f, TypeST>, Enc_65f095, AddrModeRel {
+tc_d9f95eef, TypeST>, Enc_65f095, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b0;
 let Inst{13-11} = 0b110;
@@ -19791,6 +20212,7 @@ let addrMode = PostInc;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeri_pi";
@@ -19801,7 +20223,7 @@ def S2_pstorerinewt_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if ($Pv4) memw($Rs32) = $Nt8.new",
-tc_9da3628f, TypeMAPPING> {
+tc_594ab548, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -19810,7 +20232,7 @@ def S2_pstorerinewtnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
-tc_8fab9ac3, TypeST>, Enc_65f095, AddrModeRel {
+tc_d24b2d85, TypeST>, Enc_65f095, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b110;
@@ -19821,6 +20243,7 @@ let accessSize = WordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeri_pi";
@@ -19831,7 +20254,7 @@ def S2_pstorerit_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memw($Rs32+#$Ii) = $Rt32",
-tc_3d905451, TypeV2LDST>, Enc_397f23, AddrModeRel {
+tc_8b15472a, TypeV2LDST>, Enc_397f23, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000000100;
 let isPredicated = 1;
@@ -19852,7 +20275,7 @@ def S2_pstorerit_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memw($Rx32++#$Ii) = $Rt32",
-tc_9b73d261, TypeST>, Enc_7eaeb6, AddrModeRel {
+tc_cd7374a0, TypeST>, Enc_7eaeb6, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
@@ -19869,7 +20292,7 @@ def S2_pstorerit_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pv4) memw($Rs32) = $Rt32",
-tc_3d905451, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -19877,7 +20300,7 @@ def S2_pstoreritnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32",
-tc_7675c0e9, TypeST>, Enc_7eaeb6, AddrModeRel {
+tc_74e47fd9, TypeST>, Enc_7eaeb6, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -19895,7 +20318,7 @@ def S2_setbit_i : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = setbit($Rs32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_a05677 {
+tc_540fdfbc, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100110;
@@ -19906,7 +20329,7 @@ def S2_setbit_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = setbit($Rs32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_5ab2be {
+tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110100;
@@ -19917,7 +20340,7 @@ def S2_shuffeb : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = shuffeb($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_a56825 {
+tc_540fdfbc, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001000;
@@ -19926,7 +20349,7 @@ def S2_shuffeh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = shuffeh($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_a56825 {
+tc_540fdfbc, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001000;
@@ -19935,7 +20358,7 @@ def S2_shuffob : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = shuffob($Rtt32,$Rss32)",
-tc_9c18c9a5, TypeS_3op>, Enc_ea23e4 {
+tc_540fdfbc, TypeS_3op>, Enc_ea23e4 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001000;
@@ -19944,7 +20367,7 @@ def S2_shuffoh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
 "$Rdd32 = shuffoh($Rtt32,$Rss32)",
-tc_9c18c9a5, TypeS_3op>, Enc_ea23e4 {
+tc_540fdfbc, TypeS_3op>, Enc_ea23e4 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001100;
@@ -19953,7 +20376,7 @@ def S2_storerb_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
 "memb($Rs32+#$Ii) = $Rt32",
-tc_53ee6546, TypeST>, Enc_448f7f, AddrModeRel {
+tc_05b6c987, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1000;
 let Inst{31-27} = 0b10100;
 let addrMode = BaseImmOffset;
@@ -19974,7 +20397,7 @@ def S2_storerb_pbr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memb($Rx32++$Mu2:brev) = $Rt32",
-tc_20a8e109, TypeST>, Enc_d5c73f, AddrModeRel {
+tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
 let Inst{7-0} = 0b00000000;
 let Inst{31-21} = 0b10101111000;
 let accessSize = ByteAccess;
@@ -19987,7 +20410,7 @@ def S2_storerb_pci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
 "memb($Rx32++#$Ii:circ($Mu2)) = $Rt32",
-tc_251c87b2, TypeST>, Enc_b15941 {
+tc_9fdb5406, TypeST>, Enc_b15941, AddrModeRel {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{31-21} = 0b10101001000;
@@ -19995,6 +20418,7 @@ let addrMode = PostInc;
 let accessSize = ByteAccess;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storerb_pci";
 let isNVStorable = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20002,13 +20426,14 @@ def S2_storerb_pcr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memb($Rx32++I:circ($Mu2)) = $Rt32",
-tc_20a8e109, TypeST>, Enc_d5c73f {
+tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
 let Inst{7-0} = 0b00000010;
 let Inst{31-21} = 0b10101001000;
 let addrMode = PostInc;
 let accessSize = ByteAccess;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storerb_pcr";
 let isNVStorable = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20016,7 +20441,7 @@ def S2_storerb_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
 "memb($Rx32++#$Ii) = $Rt32",
-tc_20a8e109, TypeST>, Enc_10bc21, AddrModeRel {
+tc_f86c328a, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
@@ -20024,6 +20449,7 @@ let Inst{31-21} = 0b10101011000;
 let addrMode = PostInc;
 let accessSize = ByteAccess;
 let mayStore = 1;
+let CextOpcode = "S2_storerb";
 let BaseOpcode = "S2_storerb_pi";
 let isPredicable = 1;
 let isNVStorable = 1;
@@ -20033,7 +20459,7 @@ def S2_storerb_pr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memb($Rx32++$Mu2) = $Rt32",
-tc_20a8e109, TypeST>, Enc_d5c73f {
+tc_f86c328a, TypeST>, Enc_d5c73f {
 let Inst{7-0} = 0b00000000;
 let Inst{31-21} = 0b10101101000;
 let addrMode = PostInc;
@@ -20046,7 +20472,7 @@ def S2_storerb_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memb($Rs32) = $Rt32",
-tc_53ee6546, TypeMAPPING> {
+tc_05b6c987, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -20054,7 +20480,7 @@ def S2_storerbgp : HInst<
 (outs),
 (ins u32_0Imm:$Ii, IntRegs:$Rt32),
 "memb(gp+#$Ii) = $Rt32",
-tc_c14739d5, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
+tc_a788683e, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
 let Inst{24-21} = 0b0000;
 let Inst{31-27} = 0b01001;
 let accessSize = ByteAccess;
@@ -20072,7 +20498,7 @@ def S2_storerbnew_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8),
 "memb($Rs32+#$Ii) = $Nt8.new",
-tc_6c576d46, TypeST>, Enc_4df4e9, AddrModeRel {
+tc_f7dd9c9f, TypeST>, Enc_4df4e9, AddrModeRel {
 let Inst{12-11} = 0b00;
 let Inst{24-21} = 0b1101;
 let Inst{31-27} = 0b10100;
@@ -20080,6 +20506,7 @@ let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let InputType = "imm";
@@ -20096,13 +20523,14 @@ def S2_storerbnew_pbr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
 "memb($Rx32++$Mu2:brev) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_8dbe85, AddrModeRel {
+tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
 let Inst{7-0} = 0b00000000;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b10101111101;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let BaseOpcode = "S2_storerb_pbr";
 let opNewValue = 3;
@@ -20112,7 +20540,7 @@ def S2_storerbnew_pci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
 "memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
-tc_9c68db63, TypeST>, Enc_96ce4f {
+tc_9d5941c7, TypeST>, Enc_96ce4f, AddrModeRel {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{12-11} = 0b00;
@@ -20121,8 +20549,10 @@ let addrMode = PostInc;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storerb_pci";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20130,7 +20560,7 @@ def S2_storerbnew_pcr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
 "memb($Rx32++I:circ($Mu2)) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_8dbe85 {
+tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
 let Inst{7-0} = 0b00000010;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b10101001101;
@@ -20138,8 +20568,10 @@ let addrMode = PostInc;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storerb_pcr";
 let opNewValue = 3;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20147,7 +20579,7 @@ def S2_storerbnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
 "memb($Rx32++#$Ii) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_c7cd90, AddrModeRel {
+tc_e7d02c66, TypeST>, Enc_c7cd90, AddrModeRel {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{13-11} = 0b000;
@@ -20156,6 +20588,7 @@ let addrMode = PostInc;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let BaseOpcode = "S2_storerb_pi";
 let isPredicable = 1;
@@ -20167,7 +20600,7 @@ def S2_storerbnew_pr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
 "memb($Rx32++$Mu2) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_8dbe85 {
+tc_e7d02c66, TypeST>, Enc_8dbe85 {
 let Inst{7-0} = 0b00000000;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b10101101101;
@@ -20175,6 +20608,7 @@ let addrMode = PostInc;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let opNewValue = 3;
 let Constraints = "$Rx32 = $Rx32in";
@@ -20183,7 +20617,7 @@ def S2_storerbnew_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Nt8),
 "memb($Rs32) = $Nt8.new",
-tc_6c576d46, TypeMAPPING> {
+tc_f7dd9c9f, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 1;
@@ -20192,13 +20626,14 @@ def S2_storerbnewgp : HInst<
 (outs),
 (ins u32_0Imm:$Ii, IntRegs:$Nt8),
 "memb(gp+#$Ii) = $Nt8.new",
-tc_9e86015f, TypeV2LDST>, Enc_ad1831, AddrModeRel {
+tc_ff9ee76e, TypeV2LDST>, Enc_ad1831, AddrModeRel {
 let Inst{12-11} = 0b00;
 let Inst{24-21} = 0b0101;
 let Inst{31-27} = 0b01001;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let Uses = [GP];
 let BaseOpcode = "S2_storerbabs";
@@ -20213,7 +20648,7 @@ def S2_storerd_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
 "memd($Rs32+#$Ii) = $Rtt32",
-tc_53ee6546, TypeST>, Enc_ce6828, AddrModeRel {
+tc_05b6c987, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1110;
 let Inst{31-27} = 0b10100;
 let addrMode = BaseImmOffset;
@@ -20233,7 +20668,7 @@ def S2_storerd_pbr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
 "memd($Rx32++$Mu2:brev) = $Rtt32",
-tc_20a8e109, TypeST>, Enc_928ca1 {
+tc_f86c328a, TypeST>, Enc_928ca1 {
 let Inst{7-0} = 0b00000000;
 let Inst{31-21} = 0b10101111110;
 let accessSize = DoubleWordAccess;
@@ -20244,7 +20679,7 @@ def S2_storerd_pci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32),
 "memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32",
-tc_251c87b2, TypeST>, Enc_395cc4 {
+tc_9fdb5406, TypeST>, Enc_395cc4 {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{31-21} = 0b10101001110;
@@ -20258,7 +20693,7 @@ def S2_storerd_pcr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
 "memd($Rx32++I:circ($Mu2)) = $Rtt32",
-tc_20a8e109, TypeST>, Enc_928ca1 {
+tc_f86c328a, TypeST>, Enc_928ca1 {
 let Inst{7-0} = 0b00000010;
 let Inst{31-21} = 0b10101001110;
 let addrMode = PostInc;
@@ -20271,7 +20706,7 @@ def S2_storerd_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
 "memd($Rx32++#$Ii) = $Rtt32",
-tc_20a8e109, TypeST>, Enc_85bf58, AddrModeRel {
+tc_f86c328a, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
@@ -20288,7 +20723,7 @@ def S2_storerd_pr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
 "memd($Rx32++$Mu2) = $Rtt32",
-tc_20a8e109, TypeST>, Enc_928ca1 {
+tc_f86c328a, TypeST>, Enc_928ca1 {
 let Inst{7-0} = 0b00000000;
 let Inst{31-21} = 0b10101101110;
 let addrMode = PostInc;
@@ -20300,7 +20735,7 @@ def S2_storerd_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "memd($Rs32) = $Rtt32",
-tc_53ee6546, TypeMAPPING> {
+tc_05b6c987, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -20308,7 +20743,7 @@ def S2_storerdgp : HInst<
 (outs),
 (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
 "memd(gp+#$Ii) = $Rtt32",
-tc_c14739d5, TypeV2LDST>, Enc_5c124a, AddrModeRel {
+tc_a788683e, TypeV2LDST>, Enc_5c124a, AddrModeRel {
 let Inst{24-21} = 0b0110;
 let Inst{31-27} = 0b01001;
 let accessSize = DoubleWordAccess;
@@ -20325,7 +20760,7 @@ def S2_storerf_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
 "memh($Rs32+#$Ii) = $Rt32.h",
-tc_53ee6546, TypeST>, Enc_e957fb, AddrModeRel {
+tc_05b6c987, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1011;
 let Inst{31-27} = 0b10100;
 let addrMode = BaseImmOffset;
@@ -20345,7 +20780,7 @@ def S2_storerf_pbr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memh($Rx32++$Mu2:brev) = $Rt32.h",
-tc_20a8e109, TypeST>, Enc_d5c73f {
+tc_f86c328a, TypeST>, Enc_d5c73f {
 let Inst{7-0} = 0b00000000;
 let Inst{31-21} = 0b10101111011;
 let accessSize = HalfWordAccess;
@@ -20356,7 +20791,7 @@ def S2_storerf_pci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
 "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h",
-tc_251c87b2, TypeST>, Enc_935d9b {
+tc_9fdb5406, TypeST>, Enc_935d9b {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{31-21} = 0b10101001011;
@@ -20370,7 +20805,7 @@ def S2_storerf_pcr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memh($Rx32++I:circ($Mu2)) = $Rt32.h",
-tc_20a8e109, TypeST>, Enc_d5c73f {
+tc_f86c328a, TypeST>, Enc_d5c73f {
 let Inst{7-0} = 0b00000010;
 let Inst{31-21} = 0b10101001011;
 let addrMode = PostInc;
@@ -20383,7 +20818,7 @@ def S2_storerf_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
 "memh($Rx32++#$Ii) = $Rt32.h",
-tc_20a8e109, TypeST>, Enc_052c7d, AddrModeRel {
+tc_f86c328a, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
@@ -20400,7 +20835,7 @@ def S2_storerf_pr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memh($Rx32++$Mu2) = $Rt32.h",
-tc_20a8e109, TypeST>, Enc_d5c73f {
+tc_f86c328a, TypeST>, Enc_d5c73f {
 let Inst{7-0} = 0b00000000;
 let Inst{31-21} = 0b10101101011;
 let addrMode = PostInc;
@@ -20412,7 +20847,7 @@ def S2_storerf_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memh($Rs32) = $Rt32.h",
-tc_53ee6546, TypeMAPPING> {
+tc_05b6c987, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -20420,7 +20855,7 @@ def S2_storerfgp : HInst<
 (outs),
 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
 "memh(gp+#$Ii) = $Rt32.h",
-tc_c14739d5, TypeV2LDST>, Enc_fda92c, AddrModeRel {
+tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
 let Inst{24-21} = 0b0011;
 let Inst{31-27} = 0b01001;
 let accessSize = HalfWordAccess;
@@ -20437,7 +20872,7 @@ def S2_storerh_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
 "memh($Rs32+#$Ii) = $Rt32",
-tc_53ee6546, TypeST>, Enc_e957fb, AddrModeRel {
+tc_05b6c987, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1010;
 let Inst{31-27} = 0b10100;
 let addrMode = BaseImmOffset;
@@ -20458,7 +20893,7 @@ def S2_storerh_pbr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memh($Rx32++$Mu2:brev) = $Rt32",
-tc_20a8e109, TypeST>, Enc_d5c73f, AddrModeRel {
+tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
 let Inst{7-0} = 0b00000000;
 let Inst{31-21} = 0b10101111010;
 let accessSize = HalfWordAccess;
@@ -20471,7 +20906,7 @@ def S2_storerh_pci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
 "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32",
-tc_251c87b2, TypeST>, Enc_935d9b {
+tc_9fdb5406, TypeST>, Enc_935d9b, AddrModeRel {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{31-21} = 0b10101001010;
@@ -20479,6 +20914,7 @@ let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storerh_pci";
 let isNVStorable = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20486,13 +20922,14 @@ def S2_storerh_pcr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memh($Rx32++I:circ($Mu2)) = $Rt32",
-tc_20a8e109, TypeST>, Enc_d5c73f {
+tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
 let Inst{7-0} = 0b00000010;
 let Inst{31-21} = 0b10101001010;
 let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storerh_pcr";
 let isNVStorable = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20500,7 +20937,7 @@ def S2_storerh_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
 "memh($Rx32++#$Ii) = $Rt32",
-tc_20a8e109, TypeST>, Enc_052c7d, AddrModeRel {
+tc_f86c328a, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
@@ -20508,6 +20945,7 @@ let Inst{31-21} = 0b10101011010;
 let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let mayStore = 1;
+let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerh_pi";
 let isPredicable = 1;
 let isNVStorable = 1;
@@ -20517,7 +20955,7 @@ def S2_storerh_pr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memh($Rx32++$Mu2) = $Rt32",
-tc_20a8e109, TypeST>, Enc_d5c73f {
+tc_f86c328a, TypeST>, Enc_d5c73f {
 let Inst{7-0} = 0b00000000;
 let Inst{31-21} = 0b10101101010;
 let addrMode = PostInc;
@@ -20530,7 +20968,7 @@ def S2_storerh_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memh($Rs32) = $Rt32",
-tc_53ee6546, TypeMAPPING> {
+tc_05b6c987, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -20538,7 +20976,7 @@ def S2_storerhgp : HInst<
 (outs),
 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
 "memh(gp+#$Ii) = $Rt32",
-tc_c14739d5, TypeV2LDST>, Enc_fda92c, AddrModeRel {
+tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
 let Inst{24-21} = 0b0010;
 let Inst{31-27} = 0b01001;
 let accessSize = HalfWordAccess;
@@ -20556,7 +20994,7 @@ def S2_storerhnew_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8),
 "memh($Rs32+#$Ii) = $Nt8.new",
-tc_6c576d46, TypeST>, Enc_0d8870, AddrModeRel {
+tc_f7dd9c9f, TypeST>, Enc_0d8870, AddrModeRel {
 let Inst{12-11} = 0b01;
 let Inst{24-21} = 0b1101;
 let Inst{31-27} = 0b10100;
@@ -20564,6 +21002,7 @@ let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let InputType = "imm";
@@ -20580,13 +21019,14 @@ def S2_storerhnew_pbr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
 "memh($Rx32++$Mu2:brev) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_8dbe85, AddrModeRel {
+tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
 let Inst{7-0} = 0b00000000;
 let Inst{12-11} = 0b01;
 let Inst{31-21} = 0b10101111101;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let BaseOpcode = "S2_storerh_pbr";
 let opNewValue = 3;
@@ -20596,7 +21036,7 @@ def S2_storerhnew_pci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
 "memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
-tc_9c68db63, TypeST>, Enc_91b9fe {
+tc_9d5941c7, TypeST>, Enc_91b9fe, AddrModeRel {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{12-11} = 0b01;
@@ -20605,8 +21045,10 @@ let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storerh_pci";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20614,7 +21056,7 @@ def S2_storerhnew_pcr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
 "memh($Rx32++I:circ($Mu2)) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_8dbe85 {
+tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
 let Inst{7-0} = 0b00000010;
 let Inst{12-11} = 0b01;
 let Inst{31-21} = 0b10101001101;
@@ -20622,8 +21064,10 @@ let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storerh_pcr";
 let opNewValue = 3;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20631,7 +21075,7 @@ def S2_storerhnew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
 "memh($Rx32++#$Ii) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_e26546, AddrModeRel {
+tc_e7d02c66, TypeST>, Enc_e26546, AddrModeRel {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{13-11} = 0b001;
@@ -20640,6 +21084,7 @@ let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let BaseOpcode = "S2_storerh_pi";
 let isNVStorable = 1;
@@ -20651,7 +21096,7 @@ def S2_storerhnew_pr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
 "memh($Rx32++$Mu2) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_8dbe85 {
+tc_e7d02c66, TypeST>, Enc_8dbe85 {
 let Inst{7-0} = 0b00000000;
 let Inst{12-11} = 0b01;
 let Inst{31-21} = 0b10101101101;
@@ -20659,6 +21104,7 @@ let addrMode = PostInc;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let opNewValue = 3;
 let Constraints = "$Rx32 = $Rx32in";
@@ -20667,7 +21113,7 @@ def S2_storerhnew_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Nt8),
 "memh($Rs32) = $Nt8.new",
-tc_6c576d46, TypeMAPPING> {
+tc_f7dd9c9f, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 1;
@@ -20676,13 +21122,14 @@ def S2_storerhnewgp : HInst<
 (outs),
 (ins u31_1Imm:$Ii, IntRegs:$Nt8),
 "memh(gp+#$Ii) = $Nt8.new",
-tc_9e86015f, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
+tc_ff9ee76e, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
 let Inst{12-11} = 0b01;
 let Inst{24-21} = 0b0101;
 let Inst{31-27} = 0b01001;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let Uses = [GP];
 let BaseOpcode = "S2_storerhabs";
@@ -20697,7 +21144,7 @@ def S2_storeri_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
 "memw($Rs32+#$Ii) = $Rt32",
-tc_53ee6546, TypeST>, Enc_143445, AddrModeRel {
+tc_05b6c987, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm {
 let Inst{24-21} = 0b1100;
 let Inst{31-27} = 0b10100;
 let addrMode = BaseImmOffset;
@@ -20718,7 +21165,7 @@ def S2_storeri_pbr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memw($Rx32++$Mu2:brev) = $Rt32",
-tc_20a8e109, TypeST>, Enc_d5c73f, AddrModeRel {
+tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
 let Inst{7-0} = 0b00000000;
 let Inst{31-21} = 0b10101111100;
 let accessSize = WordAccess;
@@ -20731,7 +21178,7 @@ def S2_storeri_pci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
 "memw($Rx32++#$Ii:circ($Mu2)) = $Rt32",
-tc_251c87b2, TypeST>, Enc_79b8c8 {
+tc_9fdb5406, TypeST>, Enc_79b8c8, AddrModeRel {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{31-21} = 0b10101001100;
@@ -20739,6 +21186,7 @@ let addrMode = PostInc;
 let accessSize = WordAccess;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storeri_pci";
 let isNVStorable = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20746,13 +21194,14 @@ def S2_storeri_pcr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memw($Rx32++I:circ($Mu2)) = $Rt32",
-tc_20a8e109, TypeST>, Enc_d5c73f {
+tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
 let Inst{7-0} = 0b00000010;
 let Inst{31-21} = 0b10101001100;
 let addrMode = PostInc;
 let accessSize = WordAccess;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storeri_pcr";
 let isNVStorable = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20760,7 +21209,7 @@ def S2_storeri_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
 "memw($Rx32++#$Ii) = $Rt32",
-tc_20a8e109, TypeST>, Enc_db40cd, AddrModeRel {
+tc_f86c328a, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
@@ -20768,6 +21217,7 @@ let Inst{31-21} = 0b10101011100;
 let addrMode = PostInc;
 let accessSize = WordAccess;
 let mayStore = 1;
+let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeri_pi";
 let isPredicable = 1;
 let isNVStorable = 1;
@@ -20777,7 +21227,7 @@ def S2_storeri_pr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
 "memw($Rx32++$Mu2) = $Rt32",
-tc_20a8e109, TypeST>, Enc_d5c73f {
+tc_f86c328a, TypeST>, Enc_d5c73f {
 let Inst{7-0} = 0b00000000;
 let Inst{31-21} = 0b10101101100;
 let addrMode = PostInc;
@@ -20790,7 +21240,7 @@ def S2_storeri_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memw($Rs32) = $Rt32",
-tc_53ee6546, TypeMAPPING> {
+tc_05b6c987, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -20798,7 +21248,7 @@ def S2_storerigp : HInst<
 (outs),
 (ins u30_2Imm:$Ii, IntRegs:$Rt32),
 "memw(gp+#$Ii) = $Rt32",
-tc_c14739d5, TypeV2LDST>, Enc_541f26, AddrModeRel {
+tc_a788683e, TypeV2LDST>, Enc_541f26, AddrModeRel {
 let Inst{24-21} = 0b0100;
 let Inst{31-27} = 0b01001;
 let accessSize = WordAccess;
@@ -20816,7 +21266,7 @@ def S2_storerinew_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8),
 "memw($Rs32+#$Ii) = $Nt8.new",
-tc_6c576d46, TypeST>, Enc_690862, AddrModeRel {
+tc_f7dd9c9f, TypeST>, Enc_690862, AddrModeRel {
 let Inst{12-11} = 0b10;
 let Inst{24-21} = 0b1101;
 let Inst{31-27} = 0b10100;
@@ -20824,6 +21274,7 @@ let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let InputType = "imm";
@@ -20840,13 +21291,14 @@ def S2_storerinew_pbr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
 "memw($Rx32++$Mu2:brev) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_8dbe85, AddrModeRel {
+tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
 let Inst{7-0} = 0b00000000;
 let Inst{12-11} = 0b10;
 let Inst{31-21} = 0b10101111101;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let BaseOpcode = "S2_storeri_pbr";
 let opNewValue = 3;
@@ -20856,7 +21308,7 @@ def S2_storerinew_pci : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
 "memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
-tc_9c68db63, TypeST>, Enc_3f97c8 {
+tc_9d5941c7, TypeST>, Enc_3f97c8, AddrModeRel {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{12-11} = 0b10;
@@ -20865,8 +21317,10 @@ let addrMode = PostInc;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storeri_pci";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20874,7 +21328,7 @@ def S2_storerinew_pcr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
 "memw($Rx32++I:circ($Mu2)) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_8dbe85 {
+tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
 let Inst{7-0} = 0b00000010;
 let Inst{12-11} = 0b10;
 let Inst{31-21} = 0b10101001101;
@@ -20882,8 +21336,10 @@ let addrMode = PostInc;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let Uses = [CS];
+let BaseOpcode = "S2_storeri_pcr";
 let opNewValue = 3;
 let Constraints = "$Rx32 = $Rx32in";
 }
@@ -20891,7 +21347,7 @@ def S2_storerinew_pi : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
 "memw($Rx32++#$Ii) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_223005, AddrModeRel {
+tc_e7d02c66, TypeST>, Enc_223005, AddrModeRel {
 let Inst{2-0} = 0b000;
 let Inst{7-7} = 0b0;
 let Inst{13-11} = 0b010;
@@ -20900,6 +21356,7 @@ let addrMode = PostInc;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let BaseOpcode = "S2_storeri_pi";
 let isPredicable = 1;
@@ -20910,7 +21367,7 @@ def S2_storerinew_pr : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
 "memw($Rx32++$Mu2) = $Nt8.new",
-tc_c8f9a6f6, TypeST>, Enc_8dbe85 {
+tc_e7d02c66, TypeST>, Enc_8dbe85 {
 let Inst{7-0} = 0b00000000;
 let Inst{12-11} = 0b10;
 let Inst{31-21} = 0b10101101101;
@@ -20918,6 +21375,7 @@ let addrMode = PostInc;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let opNewValue = 3;
 let Constraints = "$Rx32 = $Rx32in";
@@ -20926,7 +21384,7 @@ def S2_storerinew_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Nt8),
 "memw($Rs32) = $Nt8.new",
-tc_6c576d46, TypeMAPPING> {
+tc_f7dd9c9f, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 1;
@@ -20935,13 +21393,14 @@ def S2_storerinewgp : HInst<
 (outs),
 (ins u30_2Imm:$Ii, IntRegs:$Nt8),
 "memw(gp+#$Ii) = $Nt8.new",
-tc_9e86015f, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
+tc_ff9ee76e, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
 let Inst{12-11} = 0b10;
 let Inst{24-21} = 0b0101;
 let Inst{31-27} = 0b01001;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let Uses = [GP];
 let BaseOpcode = "S2_storeriabs";
@@ -20956,7 +21415,7 @@ def S2_storew_locked : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "memw_locked($Rs32,$Pd4) = $Rt32",
-tc_7d01cbdc, TypeST>, Enc_c2b48e {
+tc_1372bca1, TypeST>, Enc_c2b48e {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10100000101;
@@ -20969,7 +21428,7 @@ def S2_svsathb : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = vsathb($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_5e2823 {
+tc_cde8b071, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001100100;
 let hasNewValue = 1;
@@ -20980,7 +21439,7 @@ def S2_svsathub : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = vsathub($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_5e2823 {
+tc_cde8b071, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000010;
 let Inst{31-21} = 0b10001100100;
 let hasNewValue = 1;
@@ -20991,7 +21450,7 @@ def S2_tableidxb : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
 "$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw",
-tc_d95f4e98, TypeS_2op>, Enc_cd82bc {
+tc_87735c3b, TypeS_2op>, Enc_cd82bc {
 let Inst{31-22} = 0b1000011100;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -21002,7 +21461,7 @@ def S2_tableidxb_goodsyntax : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
 "$Rx32 = tableidxb($Rs32,#$Ii,#$II)",
-tc_d95f4e98, TypeS_2op> {
+tc_87735c3b, TypeS_2op> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -21013,7 +21472,7 @@ def S2_tableidxd : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
 "$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw",
-tc_d95f4e98, TypeS_2op>, Enc_cd82bc {
+tc_87735c3b, TypeS_2op>, Enc_cd82bc {
 let Inst{31-22} = 0b1000011111;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -21024,7 +21483,7 @@ def S2_tableidxd_goodsyntax : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
 "$Rx32 = tableidxd($Rs32,#$Ii,#$II)",
-tc_d95f4e98, TypeS_2op> {
+tc_87735c3b, TypeS_2op> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -21034,7 +21493,7 @@ def S2_tableidxh : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
 "$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw",
-tc_d95f4e98, TypeS_2op>, Enc_cd82bc {
+tc_87735c3b, TypeS_2op>, Enc_cd82bc {
 let Inst{31-22} = 0b1000011101;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -21045,7 +21504,7 @@ def S2_tableidxh_goodsyntax : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
 "$Rx32 = tableidxh($Rs32,#$Ii,#$II)",
-tc_d95f4e98, TypeS_2op> {
+tc_87735c3b, TypeS_2op> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -21055,7 +21514,7 @@ def S2_tableidxw : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
 "$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw",
-tc_d95f4e98, TypeS_2op>, Enc_cd82bc {
+tc_87735c3b, TypeS_2op>, Enc_cd82bc {
 let Inst{31-22} = 0b1000011110;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -21066,7 +21525,7 @@ def S2_tableidxw_goodsyntax : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
 "$Rx32 = tableidxw($Rs32,#$Ii,#$II)",
-tc_d95f4e98, TypeS_2op> {
+tc_87735c3b, TypeS_2op> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -21076,7 +21535,7 @@ def S2_togglebit_i : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = togglebit($Rs32,#$Ii)",
-tc_9c18c9a5, TypeS_2op>, Enc_a05677 {
+tc_540fdfbc, TypeS_2op>, Enc_a05677 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100110;
@@ -21087,7 +21546,7 @@ def S2_togglebit_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = togglebit($Rs32,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_5ab2be {
+tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110100;
@@ -21098,7 +21557,7 @@ def S2_tstbit_i : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Pd4 = tstbit($Rs32,#$Ii)",
-tc_5fa2857c, TypeS_2op>, Enc_83ee64 {
+tc_7a830544, TypeS_2op>, Enc_83ee64 {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10000101000;
@@ -21107,7 +21566,7 @@ def S2_tstbit_r : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = tstbit($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111000;
@@ -21116,7 +21575,7 @@ def S2_valignib : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii),
 "$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)",
-tc_d1b5a4b6, TypeS_3op>, Enc_729ff7 {
+tc_f8eeed7a, TypeS_3op>, Enc_729ff7 {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000000000;
 }
@@ -21124,7 +21583,7 @@ def S2_valignrb : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4),
 "$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)",
-tc_d1b5a4b6, TypeS_3op>, Enc_8c6530 {
+tc_f8eeed7a, TypeS_3op>, Enc_8c6530 {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000010000;
@@ -21133,7 +21592,7 @@ def S2_vcnegh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vcnegh($Rss32,$Rt32)",
-tc_47ab9233, TypeS_3op>, Enc_927852 {
+tc_b44c6e2a, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011110;
@@ -21144,7 +21603,7 @@ def S2_vcrotate : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rdd32 = vcrotate($Rss32,$Rt32)",
-tc_63cd9d2d, TypeS_3op>, Enc_927852 {
+tc_2b6f77c6, TypeS_3op>, Enc_927852 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000011110;
@@ -21155,7 +21614,7 @@ def S2_vrcnegh : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
 "$Rxx32 += vrcnegh($Rss32,$Rt32)",
-tc_8cb685d9, TypeS_3op>, Enc_1aa186 {
+tc_e913dc32, TypeS_3op>, Enc_1aa186 {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b11001011001;
@@ -21166,7 +21625,7 @@ def S2_vrndpackwh : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = vrndwh($Rss32)",
-tc_88fa2da6, TypeS_2op>, Enc_90cd8b {
+tc_d088982c, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10001000100;
 let hasNewValue = 1;
@@ -21177,7 +21636,7 @@ def S2_vrndpackwhs : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = vrndwh($Rss32):sat",
-tc_94e6ffd9, TypeS_2op>, Enc_90cd8b {
+tc_c2f7d806, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10001000100;
 let hasNewValue = 1;
@@ -21189,7 +21648,7 @@ def S2_vsathb : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = vsathb($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_90cd8b {
+tc_cde8b071, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10001000000;
 let hasNewValue = 1;
@@ -21200,7 +21659,7 @@ def S2_vsathb_nopack : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = vsathb($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb {
+tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000111;
 let Inst{31-21} = 0b10000000000;
 let Defs = [USR_OVF];
@@ -21209,7 +21668,7 @@ def S2_vsathub : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = vsathub($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_90cd8b {
+tc_cde8b071, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001000000;
 let hasNewValue = 1;
@@ -21220,7 +21679,7 @@ def S2_vsathub_nopack : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = vsathub($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb {
+tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10000000000;
 let Defs = [USR_OVF];
@@ -21229,7 +21688,7 @@ def S2_vsatwh : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = vsatwh($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_90cd8b {
+tc_cde8b071, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000010;
 let Inst{31-21} = 0b10001000000;
 let hasNewValue = 1;
@@ -21240,7 +21699,7 @@ def S2_vsatwh_nopack : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = vsatwh($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb {
+tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10000000000;
 let Defs = [USR_OVF];
@@ -21249,7 +21708,7 @@ def S2_vsatwuh : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = vsatwuh($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_90cd8b {
+tc_cde8b071, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10001000000;
 let hasNewValue = 1;
@@ -21260,7 +21719,7 @@ def S2_vsatwuh_nopack : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32),
 "$Rdd32 = vsatwuh($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb {
+tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
 let Inst{13-5} = 0b000000101;
 let Inst{31-21} = 0b10000000000;
 let Defs = [USR_OVF];
@@ -21269,7 +21728,7 @@ def S2_vsplatrb : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32),
 "$Rd32 = vsplatb($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_5e2823 {
+tc_cde8b071, TypeS_2op>, Enc_5e2823 {
 let Inst{13-5} = 0b000000111;
 let Inst{31-21} = 0b10001100010;
 let hasNewValue = 1;
@@ -21281,7 +21740,7 @@ def S2_vsplatrh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = vsplath($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 {
+tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
 let Inst{13-5} = 0b000000010;
 let Inst{31-21} = 0b10000100010;
 let isReMaterializable = 1;
@@ -21291,7 +21750,7 @@ def S2_vspliceib : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii),
 "$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)",
-tc_d1b5a4b6, TypeS_3op>, Enc_d50cd3 {
+tc_f8eeed7a, TypeS_3op>, Enc_d50cd3 {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000000100;
 }
@@ -21299,7 +21758,7 @@ def S2_vsplicerb : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4),
 "$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)",
-tc_d1b5a4b6, TypeS_3op>, Enc_dbd70c {
+tc_f8eeed7a, TypeS_3op>, Enc_dbd70c {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000010100;
@@ -21308,7 +21767,7 @@ def S2_vsxtbh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = vsxtbh($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 {
+tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10000100000;
 let isReMaterializable = 1;
@@ -21318,7 +21777,7 @@ def S2_vsxthw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = vsxthw($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 {
+tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10000100000;
 let isReMaterializable = 1;
@@ -21328,7 +21787,7 @@ def S2_vtrunehb : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = vtrunehb($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_90cd8b {
+tc_cde8b071, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000010;
 let Inst{31-21} = 0b10001000100;
 let hasNewValue = 1;
@@ -21338,7 +21797,7 @@ def S2_vtrunewh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vtrunewh($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_a56825 {
+tc_540fdfbc, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001100;
@@ -21347,7 +21806,7 @@ def S2_vtrunohb : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = vtrunohb($Rss32)",
-tc_b86c7e8b, TypeS_2op>, Enc_90cd8b {
+tc_cde8b071, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001000100;
 let hasNewValue = 1;
@@ -21357,7 +21816,7 @@ def S2_vtrunowh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vtrunowh($Rss32,$Rtt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_a56825 {
+tc_540fdfbc, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001100;
@@ -21366,7 +21825,7 @@ def S2_vzxtbh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = vzxtbh($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 {
+tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
 let Inst{13-5} = 0b000000010;
 let Inst{31-21} = 0b10000100000;
 let isReMaterializable = 1;
@@ -21376,7 +21835,7 @@ def S2_vzxthw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = vzxthw($Rs32)",
-tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 {
+tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
 let Inst{13-5} = 0b000000110;
 let Inst{31-21} = 0b10000100000;
 let isReMaterializable = 1;
@@ -21386,7 +21845,7 @@ def S4_addaddi : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
 "$Rd32 = add($Rs32,add($Ru32,#$Ii))",
-tc_090485bb, TypeALU64>, Enc_8b8d61 {
+tc_c74f796f, TypeALU64>, Enc_8b8d61 {
 let Inst{31-23} = 0b110110110;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -21401,7 +21860,7 @@ def S4_addi_asl_ri : HInst<
 (outs IntRegs:$Rx32),
 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
 "$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
-tc_c0cd91a8, TypeALU64>, Enc_c31910 {
+tc_c74f796f, TypeALU64>, Enc_c31910 {
 let Inst{2-0} = 0b100;
 let Inst{4-4} = 0b0;
 let Inst{31-24} = 0b11011110;
@@ -21419,7 +21878,7 @@ def S4_addi_lsr_ri : HInst<
 (outs IntRegs:$Rx32),
 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
 "$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
-tc_c0cd91a8, TypeALU64>, Enc_c31910 {
+tc_c74f796f, TypeALU64>, Enc_c31910 {
 let Inst{2-0} = 0b100;
 let Inst{4-4} = 0b1;
 let Inst{31-24} = 0b11011110;
@@ -21437,7 +21896,7 @@ def S4_andi_asl_ri : HInst<
 (outs IntRegs:$Rx32),
 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
 "$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
-tc_3c10f809, TypeALU64>, Enc_c31910 {
+tc_84df2cd3, TypeALU64>, Enc_c31910 {
 let Inst{2-0} = 0b000;
 let Inst{4-4} = 0b0;
 let Inst{31-24} = 0b11011110;
@@ -21455,7 +21914,7 @@ def S4_andi_lsr_ri : HInst<
 (outs IntRegs:$Rx32),
 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
 "$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
-tc_3c10f809, TypeALU64>, Enc_c31910 {
+tc_84df2cd3, TypeALU64>, Enc_c31910 {
 let Inst{2-0} = 0b000;
 let Inst{4-4} = 0b1;
 let Inst{31-24} = 0b11011110;
@@ -21473,7 +21932,7 @@ def S4_clbaddi : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s6_0Imm:$Ii),
 "$Rd32 = add(clb($Rs32),#$Ii)",
-tc_87601822, TypeS_2op>, Enc_9fae8a {
+tc_2b6f77c6, TypeS_2op>, Enc_9fae8a {
 let Inst{7-5} = 0b000;
 let Inst{31-21} = 0b10001100001;
 let hasNewValue = 1;
@@ -21484,7 +21943,7 @@ def S4_clbpaddi : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, s6_0Imm:$Ii),
 "$Rd32 = add(clb($Rss32),#$Ii)",
-tc_87601822, TypeS_2op>, Enc_a1640c {
+tc_2b6f77c6, TypeS_2op>, Enc_a1640c {
 let Inst{7-5} = 0b010;
 let Inst{31-21} = 0b10001000011;
 let hasNewValue = 1;
@@ -21495,7 +21954,7 @@ def S4_clbpnorm : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = normamt($Rss32)",
-tc_ab1b5e74, TypeS_2op>, Enc_90cd8b {
+tc_d088982c, TypeS_2op>, Enc_90cd8b {
 let Inst{13-5} = 0b000000000;
 let Inst{31-21} = 0b10001000011;
 let hasNewValue = 1;
@@ -21506,7 +21965,7 @@ def S4_extract : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
 "$Rd32 = extract($Rs32,#$Ii,#$II)",
-tc_c0cd91a8, TypeS_2op>, Enc_b388cf {
+tc_c74f796f, TypeS_2op>, Enc_b388cf {
 let Inst{13-13} = 0b0;
 let Inst{31-23} = 0b100011011;
 let hasNewValue = 1;
@@ -21517,7 +21976,7 @@ def S4_extract_rp : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "$Rd32 = extract($Rs32,$Rtt32)",
-tc_87601822, TypeS_3op>, Enc_e07374 {
+tc_2b6f77c6, TypeS_3op>, Enc_e07374 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11001001000;
@@ -21529,7 +21988,7 @@ def S4_extractp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
 "$Rdd32 = extract($Rss32,#$Ii,#$II)",
-tc_c0cd91a8, TypeS_2op>, Enc_b84c4c {
+tc_c74f796f, TypeS_2op>, Enc_b84c4c {
 let Inst{31-24} = 0b10001010;
 let prefersSlot3 = 1;
 }
@@ -21537,7 +21996,7 @@ def S4_extractp_rp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = extract($Rss32,$Rtt32)",
-tc_87601822, TypeS_3op>, Enc_a56825 {
+tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001110;
@@ -21547,7 +22006,7 @@ def S4_lsli : HInst<
 (outs IntRegs:$Rd32),
 (ins s6_0Imm:$Ii, IntRegs:$Rt32),
 "$Rd32 = lsl(#$Ii,$Rt32)",
-tc_9c18c9a5, TypeS_3op>, Enc_fef969 {
+tc_540fdfbc, TypeS_3op>, Enc_fef969 {
 let Inst{7-6} = 0b11;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000110100;
@@ -21558,7 +22017,7 @@ def S4_ntstbit_i : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Pd4 = !tstbit($Rs32,#$Ii)",
-tc_5fa2857c, TypeS_2op>, Enc_83ee64 {
+tc_7a830544, TypeS_2op>, Enc_83ee64 {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10000101001;
@@ -21567,7 +22026,7 @@ def S4_ntstbit_r : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Pd4 = !tstbit($Rs32,$Rt32)",
-tc_c58f771a, TypeS_3op>, Enc_c2b48e {
+tc_1e856f58, TypeS_3op>, Enc_c2b48e {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000111001;
@@ -21576,7 +22035,7 @@ def S4_or_andi : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rx32 |= and($Rs32,#$Ii)",
-tc_3c10f809, TypeALU64>, Enc_b0e9d8 {
+tc_84df2cd3, TypeALU64>, Enc_b0e9d8 {
 let Inst{31-22} = 0b1101101000;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -21593,7 +22052,7 @@ def S4_or_andix : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
 "$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
-tc_3c10f809, TypeALU64>, Enc_b4e6cf {
+tc_84df2cd3, TypeALU64>, Enc_b4e6cf {
 let Inst{31-22} = 0b1101101001;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -21609,7 +22068,7 @@ def S4_or_ori : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
 "$Rx32 |= or($Rs32,#$Ii)",
-tc_3c10f809, TypeALU64>, Enc_b0e9d8 {
+tc_84df2cd3, TypeALU64>, Enc_b0e9d8 {
 let Inst{31-22} = 0b1101101010;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -21626,7 +22085,7 @@ def S4_ori_asl_ri : HInst<
 (outs IntRegs:$Rx32),
 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
 "$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
-tc_3c10f809, TypeALU64>, Enc_c31910 {
+tc_84df2cd3, TypeALU64>, Enc_c31910 {
 let Inst{2-0} = 0b010;
 let Inst{4-4} = 0b0;
 let Inst{31-24} = 0b11011110;
@@ -21644,7 +22103,7 @@ def S4_ori_lsr_ri : HInst<
 (outs IntRegs:$Rx32),
 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
 "$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
-tc_3c10f809, TypeALU64>, Enc_c31910 {
+tc_84df2cd3, TypeALU64>, Enc_c31910 {
 let Inst{2-0} = 0b010;
 let Inst{4-4} = 0b1;
 let Inst{31-24} = 0b11011110;
@@ -21662,7 +22121,7 @@ def S4_parity : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = parity($Rs32,$Rt32)",
-tc_87601822, TypeALU64>, Enc_5ab2be {
+tc_2b6f77c6, TypeALU64>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101111;
@@ -21674,7 +22133,7 @@ def S4_pstorerbf_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memb(#$Ii) = $Rt32",
-tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
@@ -21699,7 +22158,7 @@ def S4_pstorerbf_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel {
+tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110101000;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -21715,7 +22174,7 @@ def S4_pstorerbfnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memb(#$Ii) = $Rt32",
-tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -21741,7 +22200,7 @@ def S4_pstorerbfnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32",
-tc_20a8e109, TypeV2LDST>, Enc_da8d43, AddrModeRel {
+tc_f86c328a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000110000;
 let isPredicated = 1;
@@ -21764,7 +22223,7 @@ def S4_pstorerbfnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel {
+tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110111000;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -21781,7 +22240,7 @@ def S4_pstorerbfnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pv4.new) memb($Rs32) = $Rt32",
-tc_20a8e109, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -21789,7 +22248,7 @@ def S4_pstorerbnewf_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memb(#$Ii) = $Nt8.new",
-tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel {
+tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b000;
@@ -21801,6 +22260,7 @@ let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let BaseOpcode = "S2_storerbabs";
@@ -21816,7 +22276,7 @@ def S4_pstorerbnewf_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b00;
 let Inst{31-21} = 0b00110101101;
 let isPredicated = 1;
@@ -21825,6 +22285,7 @@ let addrMode = BaseRegOffset;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let InputType = "reg";
@@ -21835,7 +22296,7 @@ def S4_pstorerbnewfnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memb(#$Ii) = $Nt8.new",
-tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel {
+tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b100;
@@ -21848,6 +22309,7 @@ let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let BaseOpcode = "S2_storerbabs";
@@ -21863,7 +22325,7 @@ def S4_pstorerbnewfnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
-tc_c8f9a6f6, TypeV2LDST>, Enc_585242, AddrModeRel {
+tc_e7d02c66, TypeV2LDST>, Enc_585242, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b01000110101;
@@ -21874,6 +22336,7 @@ let accessSize = ByteAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let InputType = "imm";
@@ -21889,7 +22352,7 @@ def S4_pstorerbnewfnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b00;
 let Inst{31-21} = 0b00110111101;
 let isPredicated = 1;
@@ -21899,6 +22362,7 @@ let accessSize = ByteAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let InputType = "reg";
@@ -21909,7 +22373,7 @@ def S4_pstorerbnewfnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if (!$Pv4.new) memb($Rs32) = $Nt8.new",
-tc_c8f9a6f6, TypeMAPPING> {
+tc_e7d02c66, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -21918,7 +22382,7 @@ def S4_pstorerbnewt_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memb(#$Ii) = $Nt8.new",
-tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel {
+tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b000;
@@ -21929,6 +22393,7 @@ let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let BaseOpcode = "S2_storerbabs";
@@ -21944,7 +22409,7 @@ def S4_pstorerbnewt_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b00;
 let Inst{31-21} = 0b00110100101;
 let isPredicated = 1;
@@ -21952,6 +22417,7 @@ let addrMode = BaseRegOffset;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let InputType = "reg";
@@ -21962,7 +22428,7 @@ def S4_pstorerbnewtnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memb(#$Ii) = $Nt8.new",
-tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel {
+tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b100;
@@ -21974,6 +22440,7 @@ let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let BaseOpcode = "S2_storerbabs";
@@ -21989,7 +22456,7 @@ def S4_pstorerbnewtnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
-tc_c8f9a6f6, TypeV2LDST>, Enc_585242, AddrModeRel {
+tc_e7d02c66, TypeV2LDST>, Enc_585242, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b01000010101;
@@ -21999,6 +22466,7 @@ let accessSize = ByteAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let InputType = "imm";
@@ -22014,7 +22482,7 @@ def S4_pstorerbnewtnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b00;
 let Inst{31-21} = 0b00110110101;
 let isPredicated = 1;
@@ -22023,6 +22491,7 @@ let accessSize = ByteAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let InputType = "reg";
@@ -22033,7 +22502,7 @@ def S4_pstorerbnewtnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if ($Pv4.new) memb($Rs32) = $Nt8.new",
-tc_c8f9a6f6, TypeMAPPING> {
+tc_e7d02c66, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -22042,7 +22511,7 @@ def S4_pstorerbt_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memb(#$Ii) = $Rt32",
-tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
@@ -22066,7 +22535,7 @@ def S4_pstorerbt_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel {
+tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110100000;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -22081,7 +22550,7 @@ def S4_pstorerbtnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memb(#$Ii) = $Rt32",
-tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -22106,7 +22575,7 @@ def S4_pstorerbtnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32",
-tc_20a8e109, TypeV2LDST>, Enc_da8d43, AddrModeRel {
+tc_f86c328a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000010000;
 let isPredicated = 1;
@@ -22128,7 +22597,7 @@ def S4_pstorerbtnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel {
+tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110110000;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -22144,7 +22613,7 @@ def S4_pstorerbtnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pv4.new) memb($Rs32) = $Rt32",
-tc_20a8e109, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -22152,7 +22621,7 @@ def S4_pstorerdf_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
 "if (!$Pv4) memd(#$Ii) = $Rtt32",
-tc_c85212ca, TypeST>, Enc_50b5ac, AddrModeRel {
+tc_238d91d2, TypeST>, Enc_50b5ac, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
@@ -22176,7 +22645,7 @@ def S4_pstorerdf_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
 "if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
-tc_7bc567a7, TypeST>, Enc_1a9974, AddrModeRel {
+tc_5274e61a, TypeST>, Enc_1a9974, AddrModeRel {
 let Inst{31-21} = 0b00110101110;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -22191,7 +22660,7 @@ def S4_pstorerdfnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
 "if (!$Pv4.new) memd(#$Ii) = $Rtt32",
-tc_336e698c, TypeST>, Enc_50b5ac, AddrModeRel {
+tc_66888ded, TypeST>, Enc_50b5ac, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -22216,7 +22685,7 @@ def S4_pstorerdfnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
 "if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
-tc_20a8e109, TypeV2LDST>, Enc_57a33e, AddrModeRel {
+tc_f86c328a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000110110;
 let isPredicated = 1;
@@ -22238,7 +22707,7 @@ def S4_pstorerdfnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
 "if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
-tc_7639d4b0, TypeST>, Enc_1a9974, AddrModeRel {
+tc_3e07fb90, TypeST>, Enc_1a9974, AddrModeRel {
 let Inst{31-21} = 0b00110111110;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -22254,7 +22723,7 @@ def S4_pstorerdfnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "if (!$Pv4.new) memd($Rs32) = $Rtt32",
-tc_20a8e109, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -22262,7 +22731,7 @@ def S4_pstorerdt_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
 "if ($Pv4) memd(#$Ii) = $Rtt32",
-tc_c85212ca, TypeST>, Enc_50b5ac, AddrModeRel {
+tc_238d91d2, TypeST>, Enc_50b5ac, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
@@ -22285,7 +22754,7 @@ def S4_pstorerdt_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
 "if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
-tc_7bc567a7, TypeST>, Enc_1a9974, AddrModeRel {
+tc_5274e61a, TypeST>, Enc_1a9974, AddrModeRel {
 let Inst{31-21} = 0b00110100110;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -22299,7 +22768,7 @@ def S4_pstorerdtnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
 "if ($Pv4.new) memd(#$Ii) = $Rtt32",
-tc_336e698c, TypeST>, Enc_50b5ac, AddrModeRel {
+tc_66888ded, TypeST>, Enc_50b5ac, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -22323,7 +22792,7 @@ def S4_pstorerdtnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
 "if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
-tc_20a8e109, TypeV2LDST>, Enc_57a33e, AddrModeRel {
+tc_f86c328a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000010110;
 let isPredicated = 1;
@@ -22344,7 +22813,7 @@ def S4_pstorerdtnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
 "if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
-tc_7639d4b0, TypeST>, Enc_1a9974, AddrModeRel {
+tc_3e07fb90, TypeST>, Enc_1a9974, AddrModeRel {
 let Inst{31-21} = 0b00110110110;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -22359,7 +22828,7 @@ def S4_pstorerdtnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "if ($Pv4.new) memd($Rs32) = $Rtt32",
-tc_20a8e109, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -22367,7 +22836,7 @@ def S4_pstorerff_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memh(#$Ii) = $Rt32.h",
-tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
@@ -22391,7 +22860,7 @@ def S4_pstorerff_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
-tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel {
+tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110101011;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -22406,7 +22875,7 @@ def S4_pstorerffnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memh(#$Ii) = $Rt32.h",
-tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -22431,7 +22900,7 @@ def S4_pstorerffnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
-tc_20a8e109, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
+tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000110011;
 let isPredicated = 1;
@@ -22453,7 +22922,7 @@ def S4_pstorerffnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
-tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel {
+tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110111011;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -22469,7 +22938,7 @@ def S4_pstorerffnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pv4.new) memh($Rs32) = $Rt32.h",
-tc_20a8e109, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -22477,7 +22946,7 @@ def S4_pstorerft_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memh(#$Ii) = $Rt32.h",
-tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
@@ -22500,7 +22969,7 @@ def S4_pstorerft_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
-tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel {
+tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110100011;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -22514,7 +22983,7 @@ def S4_pstorerftnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memh(#$Ii) = $Rt32.h",
-tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -22538,7 +23007,7 @@ def S4_pstorerftnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
-tc_20a8e109, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
+tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000010011;
 let isPredicated = 1;
@@ -22559,7 +23028,7 @@ def S4_pstorerftnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
-tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel {
+tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110110011;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -22574,7 +23043,7 @@ def S4_pstorerftnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pv4.new) memh($Rs32) = $Rt32.h",
-tc_20a8e109, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -22582,7 +23051,7 @@ def S4_pstorerhf_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memh(#$Ii) = $Rt32",
-tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
@@ -22607,7 +23076,7 @@ def S4_pstorerhf_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel {
+tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110101010;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -22623,7 +23092,7 @@ def S4_pstorerhfnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memh(#$Ii) = $Rt32",
-tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -22649,7 +23118,7 @@ def S4_pstorerhfnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32",
-tc_20a8e109, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
+tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000110010;
 let isPredicated = 1;
@@ -22672,7 +23141,7 @@ def S4_pstorerhfnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel {
+tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110111010;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -22689,7 +23158,7 @@ def S4_pstorerhfnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pv4.new) memh($Rs32) = $Rt32",
-tc_20a8e109, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -22697,7 +23166,7 @@ def S4_pstorerhnewf_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memh(#$Ii) = $Nt8.new",
-tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel {
+tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b001;
@@ -22709,6 +23178,7 @@ let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerhabs";
@@ -22724,7 +23194,7 @@ def S4_pstorerhnewf_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b01;
 let Inst{31-21} = 0b00110101101;
 let isPredicated = 1;
@@ -22733,6 +23203,7 @@ let addrMode = BaseRegOffset;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let InputType = "reg";
@@ -22743,7 +23214,7 @@ def S4_pstorerhnewfnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memh(#$Ii) = $Nt8.new",
-tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel {
+tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b101;
@@ -22756,6 +23227,7 @@ let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerhabs";
@@ -22771,7 +23243,7 @@ def S4_pstorerhnewfnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
-tc_c8f9a6f6, TypeV2LDST>, Enc_f44229, AddrModeRel {
+tc_e7d02c66, TypeV2LDST>, Enc_f44229, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b01;
 let Inst{31-21} = 0b01000110101;
@@ -22782,6 +23254,7 @@ let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let InputType = "imm";
@@ -22797,7 +23270,7 @@ def S4_pstorerhnewfnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b01;
 let Inst{31-21} = 0b00110111101;
 let isPredicated = 1;
@@ -22807,6 +23280,7 @@ let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let InputType = "reg";
@@ -22817,7 +23291,7 @@ def S4_pstorerhnewfnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if (!$Pv4.new) memh($Rs32) = $Nt8.new",
-tc_c8f9a6f6, TypeMAPPING> {
+tc_e7d02c66, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -22826,7 +23300,7 @@ def S4_pstorerhnewt_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memh(#$Ii) = $Nt8.new",
-tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel {
+tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b001;
@@ -22837,6 +23311,7 @@ let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerhabs";
@@ -22852,7 +23327,7 @@ def S4_pstorerhnewt_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b01;
 let Inst{31-21} = 0b00110100101;
 let isPredicated = 1;
@@ -22860,6 +23335,7 @@ let addrMode = BaseRegOffset;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let InputType = "reg";
@@ -22870,7 +23346,7 @@ def S4_pstorerhnewtnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memh(#$Ii) = $Nt8.new",
-tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel {
+tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b101;
@@ -22882,6 +23358,7 @@ let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerhabs";
@@ -22897,7 +23374,7 @@ def S4_pstorerhnewtnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
-tc_c8f9a6f6, TypeV2LDST>, Enc_f44229, AddrModeRel {
+tc_e7d02c66, TypeV2LDST>, Enc_f44229, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b01;
 let Inst{31-21} = 0b01000010101;
@@ -22907,6 +23384,7 @@ let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let InputType = "imm";
@@ -22922,7 +23400,7 @@ def S4_pstorerhnewtnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b01;
 let Inst{31-21} = 0b00110110101;
 let isPredicated = 1;
@@ -22931,6 +23409,7 @@ let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let InputType = "reg";
@@ -22941,7 +23420,7 @@ def S4_pstorerhnewtnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if ($Pv4.new) memh($Rs32) = $Nt8.new",
-tc_c8f9a6f6, TypeMAPPING> {
+tc_e7d02c66, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -22950,7 +23429,7 @@ def S4_pstorerht_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memh(#$Ii) = $Rt32",
-tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
@@ -22974,7 +23453,7 @@ def S4_pstorerht_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel {
+tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110100010;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -22989,7 +23468,7 @@ def S4_pstorerhtnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memh(#$Ii) = $Rt32",
-tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -23014,7 +23493,7 @@ def S4_pstorerhtnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32",
-tc_20a8e109, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
+tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000010010;
 let isPredicated = 1;
@@ -23036,7 +23515,7 @@ def S4_pstorerhtnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel {
+tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110110010;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -23052,7 +23531,7 @@ def S4_pstorerhtnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pv4.new) memh($Rs32) = $Rt32",
-tc_20a8e109, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23060,7 +23539,7 @@ def S4_pstorerif_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memw(#$Ii) = $Rt32",
-tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
@@ -23085,7 +23564,7 @@ def S4_pstorerif_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel {
+tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110101100;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -23101,7 +23580,7 @@ def S4_pstorerifnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memw(#$Ii) = $Rt32",
-tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -23127,7 +23606,7 @@ def S4_pstorerifnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32",
-tc_20a8e109, TypeV2LDST>, Enc_397f23, AddrModeRel {
+tc_f86c328a, TypeV2LDST>, Enc_397f23, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000110100;
 let isPredicated = 1;
@@ -23150,7 +23629,7 @@ def S4_pstorerifnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel {
+tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110111100;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -23167,7 +23646,7 @@ def S4_pstorerifnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if (!$Pv4.new) memw($Rs32) = $Rt32",
-tc_20a8e109, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23175,7 +23654,7 @@ def S4_pstorerinewf_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memw(#$Ii) = $Nt8.new",
-tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel {
+tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b010;
@@ -23187,6 +23666,7 @@ let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeriabs";
@@ -23202,7 +23682,7 @@ def S4_pstorerinewf_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b10;
 let Inst{31-21} = 0b00110101101;
 let isPredicated = 1;
@@ -23211,6 +23691,7 @@ let addrMode = BaseRegOffset;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let InputType = "reg";
@@ -23221,7 +23702,7 @@ def S4_pstorerinewfnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memw(#$Ii) = $Nt8.new",
-tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel {
+tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b1;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b110;
@@ -23234,6 +23715,7 @@ let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeriabs";
@@ -23249,7 +23731,7 @@ def S4_pstorerinewfnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
-tc_c8f9a6f6, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
+tc_e7d02c66, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b10;
 let Inst{31-21} = 0b01000110101;
@@ -23260,6 +23742,7 @@ let accessSize = WordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let InputType = "imm";
@@ -23275,7 +23758,7 @@ def S4_pstorerinewfnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b10;
 let Inst{31-21} = 0b00110111101;
 let isPredicated = 1;
@@ -23285,6 +23768,7 @@ let accessSize = WordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let InputType = "reg";
@@ -23295,7 +23779,7 @@ def S4_pstorerinewfnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if (!$Pv4.new) memw($Rs32) = $Nt8.new",
-tc_c8f9a6f6, TypeMAPPING> {
+tc_e7d02c66, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -23304,7 +23788,7 @@ def S4_pstorerinewt_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memw(#$Ii) = $Nt8.new",
-tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel {
+tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b010;
@@ -23315,6 +23799,7 @@ let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeriabs";
@@ -23330,7 +23815,7 @@ def S4_pstorerinewt_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b10;
 let Inst{31-21} = 0b00110100101;
 let isPredicated = 1;
@@ -23338,6 +23823,7 @@ let addrMode = BaseRegOffset;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let InputType = "reg";
@@ -23348,7 +23834,7 @@ def S4_pstorerinewtnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memw(#$Ii) = $Nt8.new",
-tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel {
+tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-11} = 0b110;
@@ -23360,6 +23846,7 @@ let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeriabs";
@@ -23375,7 +23862,7 @@ def S4_pstorerinewtnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
-tc_c8f9a6f6, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
+tc_e7d02c66, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{12-11} = 0b10;
 let Inst{31-21} = 0b01000010101;
@@ -23385,6 +23872,7 @@ let accessSize = WordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let InputType = "imm";
@@ -23400,7 +23888,7 @@ def S4_pstorerinewtnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel {
+tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
 let Inst{4-3} = 0b10;
 let Inst{31-21} = 0b00110110101;
 let isPredicated = 1;
@@ -23409,6 +23897,7 @@ let accessSize = WordAccess;
 let isNVStore = 1;
 let isPredicatedNew = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let InputType = "reg";
@@ -23419,7 +23908,7 @@ def S4_pstorerinewtnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
 "if ($Pv4.new) memw($Rs32) = $Nt8.new",
-tc_c8f9a6f6, TypeMAPPING> {
+tc_e7d02c66, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let opNewValue = 2;
@@ -23428,7 +23917,7 @@ def S4_pstorerit_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memw(#$Ii) = $Rt32",
-tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b0;
@@ -23452,7 +23941,7 @@ def S4_pstorerit_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel {
+tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110100100;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -23467,7 +23956,7 @@ def S4_pstoreritnew_abs : HInst<
 (outs),
 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memw(#$Ii) = $Rt32",
-tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel {
+tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
@@ -23492,7 +23981,7 @@ def S4_pstoreritnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32",
-tc_20a8e109, TypeV2LDST>, Enc_397f23, AddrModeRel {
+tc_f86c328a, TypeV2LDST>, Enc_397f23, AddrModeRel {
 let Inst{2-2} = 0b0;
 let Inst{31-21} = 0b01000010100;
 let isPredicated = 1;
@@ -23514,7 +24003,7 @@ def S4_pstoreritnew_rr : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel {
+tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
 let Inst{31-21} = 0b00110110100;
 let isPredicated = 1;
 let addrMode = BaseRegOffset;
@@ -23530,7 +24019,7 @@ def S4_pstoreritnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
 "if ($Pv4.new) memw($Rs32) = $Rt32",
-tc_20a8e109, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23538,7 +24027,7 @@ def S4_stored_locked : HInst<
 (outs PredRegs:$Pd4),
 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "memd_locked($Rs32,$Pd4) = $Rtt32",
-tc_7d01cbdc, TypeST>, Enc_d7dc10 {
+tc_1372bca1, TypeST>, Enc_d7dc10 {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10100000111;
@@ -23551,7 +24040,7 @@ def S4_storeirb_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
 "memb($Rs32+#$Ii) = #$II",
-tc_fcee8723, TypeST>, Enc_8203bb, PredNewRel {
+tc_05b6c987, TypeST>, Enc_8203bb, PredNewRel {
 let Inst{31-21} = 0b00111100000;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
@@ -23570,7 +24059,7 @@ def S4_storeirb_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, s8_0Imm:$II),
 "memb($Rs32) = #$II",
-tc_fcee8723, TypeMAPPING> {
+tc_05b6c987, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23578,7 +24067,7 @@ def S4_storeirbf_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
 "if (!$Pv4) memb($Rs32+#$Ii) = #$II",
-tc_1e69aa99, TypeST>, Enc_d7a65e, PredNewRel {
+tc_8b15472a, TypeST>, Enc_d7a65e, PredNewRel {
 let Inst{31-21} = 0b00111000100;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -23598,7 +24087,7 @@ def S4_storeirbf_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if (!$Pv4) memb($Rs32) = #$II",
-tc_1e69aa99, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23606,7 +24095,7 @@ def S4_storeirbfnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
 "if (!$Pv4.new) memb($Rs32+#$Ii) = #$II",
-tc_8f0a6bad, TypeST>, Enc_d7a65e, PredNewRel {
+tc_f86c328a, TypeST>, Enc_d7a65e, PredNewRel {
 let Inst{31-21} = 0b00111001100;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -23627,7 +24116,7 @@ def S4_storeirbfnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if (!$Pv4.new) memb($Rs32) = #$II",
-tc_8f0a6bad, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23635,7 +24124,7 @@ def S4_storeirbt_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
 "if ($Pv4) memb($Rs32+#$Ii) = #$II",
-tc_1e69aa99, TypeST>, Enc_d7a65e, PredNewRel {
+tc_8b15472a, TypeST>, Enc_d7a65e, PredNewRel {
 let Inst{31-21} = 0b00111000000;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
@@ -23654,7 +24143,7 @@ def S4_storeirbt_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if ($Pv4) memb($Rs32) = #$II",
-tc_1e69aa99, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23662,7 +24151,7 @@ def S4_storeirbtnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
 "if ($Pv4.new) memb($Rs32+#$Ii) = #$II",
-tc_8f0a6bad, TypeST>, Enc_d7a65e, PredNewRel {
+tc_f86c328a, TypeST>, Enc_d7a65e, PredNewRel {
 let Inst{31-21} = 0b00111001000;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
@@ -23682,7 +24171,7 @@ def S4_storeirbtnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if ($Pv4.new) memb($Rs32) = #$II",
-tc_8f0a6bad, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23690,7 +24179,7 @@ def S4_storeirh_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
 "memh($Rs32+#$Ii) = #$II",
-tc_fcee8723, TypeST>, Enc_a803e0, PredNewRel {
+tc_05b6c987, TypeST>, Enc_a803e0, PredNewRel {
 let Inst{31-21} = 0b00111100001;
 let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
@@ -23709,7 +24198,7 @@ def S4_storeirh_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, s8_0Imm:$II),
 "memh($Rs32) = #$II",
-tc_fcee8723, TypeMAPPING> {
+tc_05b6c987, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23717,7 +24206,7 @@ def S4_storeirhf_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
 "if (!$Pv4) memh($Rs32+#$Ii) = #$II",
-tc_1e69aa99, TypeST>, Enc_f20719, PredNewRel {
+tc_8b15472a, TypeST>, Enc_f20719, PredNewRel {
 let Inst{31-21} = 0b00111000101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -23737,7 +24226,7 @@ def S4_storeirhf_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if (!$Pv4) memh($Rs32) = #$II",
-tc_1e69aa99, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23745,7 +24234,7 @@ def S4_storeirhfnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
 "if (!$Pv4.new) memh($Rs32+#$Ii) = #$II",
-tc_8f0a6bad, TypeST>, Enc_f20719, PredNewRel {
+tc_f86c328a, TypeST>, Enc_f20719, PredNewRel {
 let Inst{31-21} = 0b00111001101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -23766,7 +24255,7 @@ def S4_storeirhfnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if (!$Pv4.new) memh($Rs32) = #$II",
-tc_8f0a6bad, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23774,7 +24263,7 @@ def S4_storeirht_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
 "if ($Pv4) memh($Rs32+#$Ii) = #$II",
-tc_1e69aa99, TypeST>, Enc_f20719, PredNewRel {
+tc_8b15472a, TypeST>, Enc_f20719, PredNewRel {
 let Inst{31-21} = 0b00111000001;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
@@ -23793,7 +24282,7 @@ def S4_storeirht_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if ($Pv4) memh($Rs32) = #$II",
-tc_1e69aa99, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23801,7 +24290,7 @@ def S4_storeirhtnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
 "if ($Pv4.new) memh($Rs32+#$Ii) = #$II",
-tc_8f0a6bad, TypeST>, Enc_f20719, PredNewRel {
+tc_f86c328a, TypeST>, Enc_f20719, PredNewRel {
 let Inst{31-21} = 0b00111001001;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
@@ -23821,7 +24310,7 @@ def S4_storeirhtnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if ($Pv4.new) memh($Rs32) = #$II",
-tc_8f0a6bad, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23829,7 +24318,7 @@ def S4_storeiri_io : HInst<
 (outs),
 (ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
 "memw($Rs32+#$Ii) = #$II",
-tc_fcee8723, TypeST>, Enc_f37377, PredNewRel {
+tc_05b6c987, TypeST>, Enc_f37377, PredNewRel {
 let Inst{31-21} = 0b00111100010;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
@@ -23848,7 +24337,7 @@ def S4_storeiri_zomap : HInst<
 (outs),
 (ins IntRegs:$Rs32, s8_0Imm:$II),
 "memw($Rs32) = #$II",
-tc_fcee8723, TypeMAPPING> {
+tc_05b6c987, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23856,7 +24345,7 @@ def S4_storeirif_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
 "if (!$Pv4) memw($Rs32+#$Ii) = #$II",
-tc_1e69aa99, TypeST>, Enc_5ccba9, PredNewRel {
+tc_8b15472a, TypeST>, Enc_5ccba9, PredNewRel {
 let Inst{31-21} = 0b00111000110;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -23876,7 +24365,7 @@ def S4_storeirif_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if (!$Pv4) memw($Rs32) = #$II",
-tc_1e69aa99, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23884,7 +24373,7 @@ def S4_storeirifnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
 "if (!$Pv4.new) memw($Rs32+#$Ii) = #$II",
-tc_8f0a6bad, TypeST>, Enc_5ccba9, PredNewRel {
+tc_f86c328a, TypeST>, Enc_5ccba9, PredNewRel {
 let Inst{31-21} = 0b00111001110;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -23905,7 +24394,7 @@ def S4_storeirifnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if (!$Pv4.new) memw($Rs32) = #$II",
-tc_8f0a6bad, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23913,7 +24402,7 @@ def S4_storeirit_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
 "if ($Pv4) memw($Rs32+#$Ii) = #$II",
-tc_1e69aa99, TypeST>, Enc_5ccba9, PredNewRel {
+tc_8b15472a, TypeST>, Enc_5ccba9, PredNewRel {
 let Inst{31-21} = 0b00111000010;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
@@ -23932,7 +24421,7 @@ def S4_storeirit_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if ($Pv4) memw($Rs32) = #$II",
-tc_1e69aa99, TypeMAPPING> {
+tc_8b15472a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23940,7 +24429,7 @@ def S4_storeiritnew_io : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
 "if ($Pv4.new) memw($Rs32+#$Ii) = #$II",
-tc_8f0a6bad, TypeST>, Enc_5ccba9, PredNewRel {
+tc_f86c328a, TypeST>, Enc_5ccba9, PredNewRel {
 let Inst{31-21} = 0b00111001010;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
@@ -23960,7 +24449,7 @@ def S4_storeiritnew_zomap : HInst<
 (outs),
 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
 "if ($Pv4.new) memw($Rs32) = #$II",
-tc_8f0a6bad, TypeMAPPING> {
+tc_f86c328a, TypeMAPPING> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
@@ -23968,12 +24457,10 @@ def S4_storerb_ap : HInst<
 (outs IntRegs:$Re32),
 (ins u32_0Imm:$II, IntRegs:$Rt32),
 "memb($Re32=#$II) = $Rt32",
-tc_336e698c, TypeST>, Enc_8bcba4, AddrModeRel {
+tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel {
 let Inst{7-6} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10101011000;
-let hasNewValue = 1;
-let opNewValue = 0;
 let addrMode = AbsoluteSet;
 let accessSize = ByteAccess;
 let isExtended = 1;
@@ -23991,7 +24478,7 @@ def S4_storerb_rr : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "memb($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_45631a8d, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
+tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111011000;
 let addrMode = BaseRegOffset;
@@ -24007,7 +24494,7 @@ def S4_storerb_ur : HInst<
 (outs),
 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
 "memb($Ru32<<#$Ii+#$II) = $Rt32",
-tc_a4567c39, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
+tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
 let Inst{7-7} = 0b1;
 let Inst{31-21} = 0b10101101000;
 let addrMode = BaseLongOffset;
@@ -24029,17 +24516,16 @@ def S4_storerbnew_ap : HInst<
 (outs IntRegs:$Re32),
 (ins u32_0Imm:$II, IntRegs:$Nt8),
 "memb($Re32=#$II) = $Nt8.new",
-tc_7986ba30, TypeST>, Enc_724154, AddrModeRel {
+tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel {
 let Inst{7-6} = 0b10;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b10101011101;
-let hasNewValue = 1;
-let opNewValue = 0;
 let addrMode = AbsoluteSet;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let BaseOpcode = "S2_storerb_ap";
 let DecoderNamespace = "MustExtend";
@@ -24054,13 +24540,14 @@ def S4_storerbnew_rr : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_be995eaf, TypeST>, Enc_c6220b, AddrModeRel {
+tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel {
 let Inst{6-3} = 0b0000;
 let Inst{31-21} = 0b00111011101;
 let addrMode = BaseRegOffset;
 let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let InputType = "reg";
@@ -24072,7 +24559,7 @@ def S4_storerbnew_ur : HInst<
 (outs),
 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
 "memb($Ru32<<#$Ii+#$II) = $Nt8.new",
-tc_210b2456, TypeST>, Enc_7eb485, AddrModeRel {
+tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel {
 let Inst{7-7} = 0b1;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b10101101101;
@@ -24081,6 +24568,7 @@ let accessSize = ByteAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerb";
 let BaseOpcode = "S4_storerb_ur";
@@ -24096,12 +24584,10 @@ def S4_storerd_ap : HInst<
 (outs IntRegs:$Re32),
 (ins u32_0Imm:$II, DoubleRegs:$Rtt32),
 "memd($Re32=#$II) = $Rtt32",
-tc_336e698c, TypeST>, Enc_c7a204 {
+tc_66888ded, TypeST>, Enc_c7a204 {
 let Inst{7-6} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10101011110;
-let hasNewValue = 1;
-let opNewValue = 0;
 let addrMode = AbsoluteSet;
 let accessSize = DoubleWordAccess;
 let isExtended = 1;
@@ -24118,7 +24604,7 @@ def S4_storerd_rr : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
 "memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
-tc_45631a8d, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl {
+tc_d9709180, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111011110;
 let addrMode = BaseRegOffset;
@@ -24133,7 +24619,7 @@ def S4_storerd_ur : HInst<
 (outs),
 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32),
 "memd($Ru32<<#$Ii+#$II) = $Rtt32",
-tc_a4567c39, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl {
+tc_0dc560de, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl {
 let Inst{7-7} = 0b1;
 let Inst{31-21} = 0b10101101110;
 let addrMode = BaseLongOffset;
@@ -24154,12 +24640,10 @@ def S4_storerf_ap : HInst<
 (outs IntRegs:$Re32),
 (ins u32_0Imm:$II, IntRegs:$Rt32),
 "memh($Re32=#$II) = $Rt32.h",
-tc_336e698c, TypeST>, Enc_8bcba4 {
+tc_66888ded, TypeST>, Enc_8bcba4 {
 let Inst{7-6} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10101011011;
-let hasNewValue = 1;
-let opNewValue = 0;
 let addrMode = AbsoluteSet;
 let accessSize = HalfWordAccess;
 let isExtended = 1;
@@ -24176,7 +24660,7 @@ def S4_storerf_rr : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
-tc_45631a8d, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
+tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111011011;
 let addrMode = BaseRegOffset;
@@ -24191,7 +24675,7 @@ def S4_storerf_ur : HInst<
 (outs),
 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
 "memh($Ru32<<#$Ii+#$II) = $Rt32.h",
-tc_a4567c39, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
+tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
 let Inst{7-7} = 0b1;
 let Inst{31-21} = 0b10101101011;
 let addrMode = BaseLongOffset;
@@ -24212,12 +24696,10 @@ def S4_storerh_ap : HInst<
 (outs IntRegs:$Re32),
 (ins u32_0Imm:$II, IntRegs:$Rt32),
 "memh($Re32=#$II) = $Rt32",
-tc_336e698c, TypeST>, Enc_8bcba4, AddrModeRel {
+tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel {
 let Inst{7-6} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10101011010;
-let hasNewValue = 1;
-let opNewValue = 0;
 let addrMode = AbsoluteSet;
 let accessSize = HalfWordAccess;
 let isExtended = 1;
@@ -24235,7 +24717,7 @@ def S4_storerh_rr : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "memh($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_45631a8d, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
+tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111011010;
 let addrMode = BaseRegOffset;
@@ -24251,7 +24733,7 @@ def S4_storerh_ur : HInst<
 (outs),
 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
 "memh($Ru32<<#$Ii+#$II) = $Rt32",
-tc_a4567c39, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
+tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
 let Inst{7-7} = 0b1;
 let Inst{31-21} = 0b10101101010;
 let addrMode = BaseLongOffset;
@@ -24273,17 +24755,16 @@ def S4_storerhnew_ap : HInst<
 (outs IntRegs:$Re32),
 (ins u32_0Imm:$II, IntRegs:$Nt8),
 "memh($Re32=#$II) = $Nt8.new",
-tc_7986ba30, TypeST>, Enc_724154, AddrModeRel {
+tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel {
 let Inst{7-6} = 0b10;
 let Inst{13-11} = 0b001;
 let Inst{31-21} = 0b10101011101;
-let hasNewValue = 1;
-let opNewValue = 0;
 let addrMode = AbsoluteSet;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let BaseOpcode = "S2_storerh_ap";
 let DecoderNamespace = "MustExtend";
@@ -24298,13 +24779,14 @@ def S4_storerhnew_rr : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_be995eaf, TypeST>, Enc_c6220b, AddrModeRel {
+tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel {
 let Inst{6-3} = 0b0001;
 let Inst{31-21} = 0b00111011101;
 let addrMode = BaseRegOffset;
 let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let InputType = "reg";
@@ -24316,7 +24798,7 @@ def S4_storerhnew_ur : HInst<
 (outs),
 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
 "memh($Ru32<<#$Ii+#$II) = $Nt8.new",
-tc_210b2456, TypeST>, Enc_7eb485, AddrModeRel {
+tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel {
 let Inst{7-7} = 0b1;
 let Inst{12-11} = 0b01;
 let Inst{31-21} = 0b10101101101;
@@ -24325,6 +24807,7 @@ let accessSize = HalfWordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storerh";
 let BaseOpcode = "S2_storerh_ur";
@@ -24340,12 +24823,10 @@ def S4_storeri_ap : HInst<
 (outs IntRegs:$Re32),
 (ins u32_0Imm:$II, IntRegs:$Rt32),
 "memw($Re32=#$II) = $Rt32",
-tc_336e698c, TypeST>, Enc_8bcba4, AddrModeRel {
+tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel {
 let Inst{7-6} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10101011100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let addrMode = AbsoluteSet;
 let accessSize = WordAccess;
 let isExtended = 1;
@@ -24363,7 +24844,7 @@ def S4_storeri_rr : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
 "memw($Rs32+$Ru32<<#$Ii) = $Rt32",
-tc_45631a8d, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
+tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
 let Inst{6-5} = 0b00;
 let Inst{31-21} = 0b00111011100;
 let addrMode = BaseRegOffset;
@@ -24379,7 +24860,7 @@ def S4_storeri_ur : HInst<
 (outs),
 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
 "memw($Ru32<<#$Ii+#$II) = $Rt32",
-tc_a4567c39, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
+tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
 let Inst{7-7} = 0b1;
 let Inst{31-21} = 0b10101101100;
 let addrMode = BaseLongOffset;
@@ -24401,17 +24882,16 @@ def S4_storerinew_ap : HInst<
 (outs IntRegs:$Re32),
 (ins u32_0Imm:$II, IntRegs:$Nt8),
 "memw($Re32=#$II) = $Nt8.new",
-tc_7986ba30, TypeST>, Enc_724154, AddrModeRel {
+tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel {
 let Inst{7-6} = 0b10;
 let Inst{13-11} = 0b010;
 let Inst{31-21} = 0b10101011101;
-let hasNewValue = 1;
-let opNewValue = 0;
 let addrMode = AbsoluteSet;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let BaseOpcode = "S2_storeri_ap";
 let DecoderNamespace = "MustExtend";
@@ -24426,13 +24906,14 @@ def S4_storerinew_rr : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
 "memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
-tc_be995eaf, TypeST>, Enc_c6220b, AddrModeRel {
+tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel {
 let Inst{6-3} = 0b0010;
 let Inst{31-21} = 0b00111011101;
 let addrMode = BaseRegOffset;
 let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let InputType = "reg";
@@ -24444,7 +24925,7 @@ def S4_storerinew_ur : HInst<
 (outs),
 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
 "memw($Ru32<<#$Ii+#$II) = $Nt8.new",
-tc_210b2456, TypeST>, Enc_7eb485, AddrModeRel {
+tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel {
 let Inst{7-7} = 0b1;
 let Inst{12-11} = 0b10;
 let Inst{31-21} = 0b10101101101;
@@ -24453,6 +24934,7 @@ let accessSize = WordAccess;
 let isNVStore = 1;
 let isNewValue = 1;
 let isExtended = 1;
+let isRestrictNoSlot1Store = 1;
 let mayStore = 1;
 let CextOpcode = "S2_storeri";
 let BaseOpcode = "S2_storeri_ur";
@@ -24468,7 +24950,7 @@ def S4_subaddi : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
 "$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
-tc_090485bb, TypeALU64>, Enc_8b8d61 {
+tc_c74f796f, TypeALU64>, Enc_8b8d61 {
 let Inst{31-23} = 0b110110111;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -24483,7 +24965,7 @@ def S4_subi_asl_ri : HInst<
 (outs IntRegs:$Rx32),
 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
 "$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
-tc_c0cd91a8, TypeALU64>, Enc_c31910 {
+tc_c74f796f, TypeALU64>, Enc_c31910 {
 let Inst{2-0} = 0b110;
 let Inst{4-4} = 0b0;
 let Inst{31-24} = 0b11011110;
@@ -24501,7 +24983,7 @@ def S4_subi_lsr_ri : HInst<
 (outs IntRegs:$Rx32),
 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
 "$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
-tc_c0cd91a8, TypeALU64>, Enc_c31910 {
+tc_c74f796f, TypeALU64>, Enc_c31910 {
 let Inst{2-0} = 0b110;
 let Inst{4-4} = 0b1;
 let Inst{31-24} = 0b11011110;
@@ -24519,7 +25001,7 @@ def S4_vrcrotate : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)",
-tc_6264c5e0, TypeS_3op>, Enc_645d54 {
+tc_b9c0b731, TypeS_3op>, Enc_645d54 {
 let Inst{7-6} = 0b11;
 let Inst{31-21} = 0b11000011110;
 let prefersSlot3 = 1;
@@ -24528,7 +25010,7 @@ def S4_vrcrotate_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
 "$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)",
-tc_bc5561d8, TypeS_3op>, Enc_b72622 {
+tc_60571023, TypeS_3op>, Enc_b72622 {
 let Inst{7-6} = 0b00;
 let Inst{31-21} = 0b11001011101;
 let prefersSlot3 = 1;
@@ -24538,7 +25020,7 @@ def S4_vxaddsubh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat",
-tc_47ab9233, TypeS_3op>, Enc_a56825 {
+tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001010;
@@ -24549,7 +25031,7 @@ def S4_vxaddsubhr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat",
-tc_63cd9d2d, TypeS_3op>, Enc_a56825 {
+tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001110;
@@ -24560,7 +25042,7 @@ def S4_vxaddsubw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat",
-tc_47ab9233, TypeS_3op>, Enc_a56825 {
+tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001010;
@@ -24571,7 +25053,7 @@ def S4_vxsubaddh : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat",
-tc_47ab9233, TypeS_3op>, Enc_a56825 {
+tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001010;
@@ -24582,7 +25064,7 @@ def S4_vxsubaddhr : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat",
-tc_63cd9d2d, TypeS_3op>, Enc_a56825 {
+tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001110;
@@ -24593,7 +25075,7 @@ def S4_vxsubaddw : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat",
-tc_47ab9233, TypeS_3op>, Enc_a56825 {
+tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001010;
@@ -24604,7 +25086,7 @@ def S5_asrhub_rnd_sat : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
 "$Rd32 = vasrhub($Rss32,#$Ii):raw",
-tc_63cd9d2d, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> {
+tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> {
 let Inst{7-5} = 0b100;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b10001000011;
@@ -24617,7 +25099,7 @@ def S5_asrhub_rnd_sat_goodsyntax : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
 "$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat",
-tc_63cd9d2d, TypeS_2op>, Requires<[HasV5T]> {
+tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -24626,7 +25108,7 @@ def S5_asrhub_sat : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
 "$Rd32 = vasrhub($Rss32,#$Ii):sat",
-tc_63cd9d2d, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> {
+tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> {
 let Inst{7-5} = 0b101;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b10001000011;
@@ -24639,7 +25121,7 @@ def S5_popcountp : HInst<
 (outs IntRegs:$Rd32),
 (ins DoubleRegs:$Rss32),
 "$Rd32 = popcount($Rss32)",
-tc_ca280e8b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
+tc_00afc57e, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> {
 let Inst{13-5} = 0b000000011;
 let Inst{31-21} = 0b10001000011;
 let hasNewValue = 1;
@@ -24650,7 +25132,7 @@ def S5_vasrhrnd : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
 "$Rdd32 = vasrh($Rss32,#$Ii):raw",
-tc_63cd9d2d, TypeS_2op>, Enc_12b6e9, Requires<[HasV5T]> {
+tc_2b6f77c6, TypeS_2op>, Enc_12b6e9, Requires<[HasV5T]> {
 let Inst{7-5} = 0b000;
 let Inst{13-12} = 0b00;
 let Inst{31-21} = 0b10000000001;
@@ -24660,14 +25142,22 @@ def S5_vasrhrnd_goodsyntax : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
 "$Rdd32 = vasrh($Rss32,#$Ii):rnd",
-tc_63cd9d2d, TypeS_2op>, Requires<[HasV5T]> {
+tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> {
+let isPseudo = 1;
+}
+def S6_allocframe_to_raw : HInst<
+(outs),
+(ins u11_3Imm:$Ii),
+"allocframe(#$Ii)",
+tc_e216a5db, TypeMAPPING>, Requires<[HasV65T]> {
 let isPseudo = 1;
+let isCodeGenOnly = 1;
 }
 def S6_rol_i_p : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rdd32 = rol($Rss32,#$Ii)",
-tc_9f518242, TypeS_2op>, Enc_5eac98, Requires<[HasV60T]> {
+tc_55050d58, TypeS_2op>, Enc_5eac98, Requires<[HasV60T]> {
 let Inst{7-5} = 0b011;
 let Inst{31-21} = 0b10000000000;
 }
@@ -24675,7 +25165,7 @@ def S6_rol_i_p_acc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 += rol($Rss32,#$Ii)",
-tc_e17ce9ad, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
+tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
 let Inst{7-5} = 0b111;
 let Inst{31-21} = 0b10000010000;
 let prefersSlot3 = 1;
@@ -24685,7 +25175,7 @@ def S6_rol_i_p_and : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 &= rol($Rss32,#$Ii)",
-tc_e17ce9ad, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
+tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
 let Inst{7-5} = 0b011;
 let Inst{31-21} = 0b10000010010;
 let prefersSlot3 = 1;
@@ -24695,7 +25185,7 @@ def S6_rol_i_p_nac : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 -= rol($Rss32,#$Ii)",
-tc_e17ce9ad, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
+tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
 let Inst{7-5} = 0b011;
 let Inst{31-21} = 0b10000010000;
 let prefersSlot3 = 1;
@@ -24705,7 +25195,7 @@ def S6_rol_i_p_or : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 |= rol($Rss32,#$Ii)",
-tc_e17ce9ad, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
+tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
 let Inst{7-5} = 0b111;
 let Inst{31-21} = 0b10000010010;
 let prefersSlot3 = 1;
@@ -24715,7 +25205,7 @@ def S6_rol_i_p_xacc : HInst<
 (outs DoubleRegs:$Rxx32),
 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
 "$Rxx32 ^= rol($Rss32,#$Ii)",
-tc_e17ce9ad, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
+tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> {
 let Inst{7-5} = 0b011;
 let Inst{31-21} = 0b10000010100;
 let prefersSlot3 = 1;
@@ -24725,7 +25215,7 @@ def S6_rol_i_r : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rd32 = rol($Rs32,#$Ii)",
-tc_9f518242, TypeS_2op>, Enc_a05677, Requires<[HasV60T]> {
+tc_55050d58, TypeS_2op>, Enc_a05677, Requires<[HasV60T]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001100000;
@@ -24736,7 +25226,7 @@ def S6_rol_i_r_acc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 += rol($Rs32,#$Ii)",
-tc_e17ce9ad, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
+tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110000;
@@ -24749,7 +25239,7 @@ def S6_rol_i_r_and : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 &= rol($Rs32,#$Ii)",
-tc_e17ce9ad, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
+tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110010;
@@ -24762,7 +25252,7 @@ def S6_rol_i_r_nac : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 -= rol($Rs32,#$Ii)",
-tc_e17ce9ad, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
+tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110000;
@@ -24775,7 +25265,7 @@ def S6_rol_i_r_or : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 |= rol($Rs32,#$Ii)",
-tc_e17ce9ad, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
+tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110010;
@@ -24788,7 +25278,7 @@ def S6_rol_i_r_xacc : HInst<
 (outs IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
 "$Rx32 ^= rol($Rs32,#$Ii)",
-tc_e17ce9ad, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
+tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10001110100;
@@ -24801,7 +25291,7 @@ def S6_vsplatrbp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32),
 "$Rdd32 = vsplatb($Rs32)",
-tc_78b3c689, TypeS_2op>, Enc_3a3d62, Requires<[HasV62T]> {
+tc_be706f30, TypeS_2op>, Enc_3a3d62, Requires<[HasV62T]> {
 let Inst{13-5} = 0b000000100;
 let Inst{31-21} = 0b10000100010;
 }
@@ -24809,7 +25299,7 @@ def S6_vtrunehb_ppp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vtrunehb($Rss32,$Rtt32)",
-tc_9f518242, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> {
+tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001100;
@@ -24818,7 +25308,7 @@ def S6_vtrunohb_ppp : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
 "$Rdd32 = vtrunohb($Rss32,$Rtt32)",
-tc_9f518242, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> {
+tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11000001100;
@@ -24827,7 +25317,7 @@ def SA1_addi : HInst<
 (outs GeneralSubRegs:$Rx16),
 (ins IntRegs:$Rx16in, s32_0Imm:$Ii),
 "$Rx16 = add($Rx16in,#$Ii)",
-tc_821c4233, TypeSUBINSN>, Enc_93af4c {
+tc_609d2efe, TypeSUBINSN>, Enc_93af4c {
 let Inst{12-11} = 0b00;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -24844,7 +25334,7 @@ def SA1_addrx : HInst<
 (outs GeneralSubRegs:$Rx16),
 (ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16),
 "$Rx16 = add($Rx16in,$Rs16)",
-tc_821c4233, TypeSUBINSN>, Enc_0527db {
+tc_609d2efe, TypeSUBINSN>, Enc_0527db {
 let Inst{12-8} = 0b11000;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -24856,7 +25346,7 @@ def SA1_addsp : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins u6_2Imm:$Ii),
 "$Rd16 = add(r29,#$Ii)",
-tc_d2609065, TypeSUBINSN>, Enc_2df31d {
+tc_a904d137, TypeSUBINSN>, Enc_2df31d {
 let Inst{12-10} = 0b011;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -24868,7 +25358,7 @@ def SA1_and1 : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16),
 "$Rd16 = and($Rs16,#1)",
-tc_d2609065, TypeSUBINSN>, Enc_97d666 {
+tc_a904d137, TypeSUBINSN>, Enc_97d666 {
 let Inst{12-8} = 0b10010;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -24879,7 +25369,7 @@ def SA1_clrf : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins),
 "if (!p0) $Rd16 = #0",
-tc_7c2dcd4d, TypeSUBINSN>, Enc_1f5ba6 {
+tc_1b82a277, TypeSUBINSN>, Enc_1f5ba6 {
 let Inst{12-4} = 0b110100111;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -24893,7 +25383,7 @@ def SA1_clrfnew : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins),
 "if (!p0.new) $Rd16 = #0",
-tc_f26aa619, TypeSUBINSN>, Enc_1f5ba6 {
+tc_e9c822f7, TypeSUBINSN>, Enc_1f5ba6 {
 let Inst{12-4} = 0b110100101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
@@ -24908,7 +25398,7 @@ def SA1_clrt : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins),
 "if (p0) $Rd16 = #0",
-tc_7c2dcd4d, TypeSUBINSN>, Enc_1f5ba6 {
+tc_1b82a277, TypeSUBINSN>, Enc_1f5ba6 {
 let Inst{12-4} = 0b110100110;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -24921,7 +25411,7 @@ def SA1_clrtnew : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins),
 "if (p0.new) $Rd16 = #0",
-tc_f26aa619, TypeSUBINSN>, Enc_1f5ba6 {
+tc_e9c822f7, TypeSUBINSN>, Enc_1f5ba6 {
 let Inst{12-4} = 0b110100100;
 let isPredicated = 1;
 let hasNewValue = 1;
@@ -24935,7 +25425,7 @@ def SA1_cmpeqi : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii),
 "p0 = cmp.eq($Rs16,#$Ii)",
-tc_e8c7a357, TypeSUBINSN>, Enc_63eaeb {
+tc_90f3e30c, TypeSUBINSN>, Enc_63eaeb {
 let Inst{3-2} = 0b00;
 let Inst{12-8} = 0b11001;
 let AsmVariantName = "NonParsable";
@@ -24946,7 +25436,7 @@ def SA1_combine0i : HInst<
 (outs GeneralDoubleLow8Regs:$Rdd8),
 (ins u2_0Imm:$Ii),
 "$Rdd8 = combine(#0,#$Ii)",
-tc_d2609065, TypeSUBINSN>, Enc_ed48be {
+tc_a904d137, TypeSUBINSN>, Enc_ed48be {
 let Inst{4-3} = 0b00;
 let Inst{12-7} = 0b111000;
 let hasNewValue = 1;
@@ -24958,7 +25448,7 @@ def SA1_combine1i : HInst<
 (outs GeneralDoubleLow8Regs:$Rdd8),
 (ins u2_0Imm:$Ii),
 "$Rdd8 = combine(#1,#$Ii)",
-tc_d2609065, TypeSUBINSN>, Enc_ed48be {
+tc_a904d137, TypeSUBINSN>, Enc_ed48be {
 let Inst{4-3} = 0b01;
 let Inst{12-7} = 0b111000;
 let hasNewValue = 1;
@@ -24970,7 +25460,7 @@ def SA1_combine2i : HInst<
 (outs GeneralDoubleLow8Regs:$Rdd8),
 (ins u2_0Imm:$Ii),
 "$Rdd8 = combine(#2,#$Ii)",
-tc_d2609065, TypeSUBINSN>, Enc_ed48be {
+tc_a904d137, TypeSUBINSN>, Enc_ed48be {
 let Inst{4-3} = 0b10;
 let Inst{12-7} = 0b111000;
 let hasNewValue = 1;
@@ -24982,7 +25472,7 @@ def SA1_combine3i : HInst<
 (outs GeneralDoubleLow8Regs:$Rdd8),
 (ins u2_0Imm:$Ii),
 "$Rdd8 = combine(#3,#$Ii)",
-tc_d2609065, TypeSUBINSN>, Enc_ed48be {
+tc_a904d137, TypeSUBINSN>, Enc_ed48be {
 let Inst{4-3} = 0b11;
 let Inst{12-7} = 0b111000;
 let hasNewValue = 1;
@@ -24994,7 +25484,7 @@ def SA1_combinerz : HInst<
 (outs GeneralDoubleLow8Regs:$Rdd8),
 (ins GeneralSubRegs:$Rs16),
 "$Rdd8 = combine($Rs16,#0)",
-tc_d2609065, TypeSUBINSN>, Enc_399e12 {
+tc_a904d137, TypeSUBINSN>, Enc_399e12 {
 let Inst{3-3} = 0b1;
 let Inst{12-8} = 0b11101;
 let hasNewValue = 1;
@@ -25006,7 +25496,7 @@ def SA1_combinezr : HInst<
 (outs GeneralDoubleLow8Regs:$Rdd8),
 (ins GeneralSubRegs:$Rs16),
 "$Rdd8 = combine(#0,$Rs16)",
-tc_d2609065, TypeSUBINSN>, Enc_399e12 {
+tc_a904d137, TypeSUBINSN>, Enc_399e12 {
 let Inst{3-3} = 0b0;
 let Inst{12-8} = 0b11101;
 let hasNewValue = 1;
@@ -25018,7 +25508,7 @@ def SA1_dec : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16, n1Const:$n1),
 "$Rd16 = add($Rs16,#$n1)",
-tc_821c4233, TypeSUBINSN>, Enc_ee5ed0 {
+tc_609d2efe, TypeSUBINSN>, Enc_ee5ed0 {
 let Inst{12-8} = 0b10011;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25029,7 +25519,7 @@ def SA1_inc : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16),
 "$Rd16 = add($Rs16,#1)",
-tc_d2609065, TypeSUBINSN>, Enc_97d666 {
+tc_a904d137, TypeSUBINSN>, Enc_97d666 {
 let Inst{12-8} = 0b10001;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25040,7 +25530,7 @@ def SA1_seti : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins u32_0Imm:$Ii),
 "$Rd16 = #$Ii",
-tc_d2609065, TypeSUBINSN>, Enc_e39bb2 {
+tc_a904d137, TypeSUBINSN>, Enc_e39bb2 {
 let Inst{12-10} = 0b010;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25056,7 +25546,7 @@ def SA1_setin1 : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins n1Const:$n1),
 "$Rd16 = #$n1",
-tc_d2609065, TypeSUBINSN>, Enc_7a0ea6 {
+tc_a904d137, TypeSUBINSN>, Enc_7a0ea6 {
 let Inst{12-4} = 0b110100000;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25067,7 +25557,7 @@ def SA1_sxtb : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16),
 "$Rd16 = sxtb($Rs16)",
-tc_d2609065, TypeSUBINSN>, Enc_97d666 {
+tc_a904d137, TypeSUBINSN>, Enc_97d666 {
 let Inst{12-8} = 0b10101;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25078,7 +25568,7 @@ def SA1_sxth : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16),
 "$Rd16 = sxth($Rs16)",
-tc_d2609065, TypeSUBINSN>, Enc_97d666 {
+tc_a904d137, TypeSUBINSN>, Enc_97d666 {
 let Inst{12-8} = 0b10100;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25089,7 +25579,7 @@ def SA1_tfr : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16),
 "$Rd16 = $Rs16",
-tc_d2609065, TypeSUBINSN>, Enc_97d666 {
+tc_a904d137, TypeSUBINSN>, Enc_97d666 {
 let Inst{12-8} = 0b10000;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25100,7 +25590,7 @@ def SA1_zxtb : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16),
 "$Rd16 = and($Rs16,#255)",
-tc_d2609065, TypeSUBINSN>, Enc_97d666 {
+tc_a904d137, TypeSUBINSN>, Enc_97d666 {
 let Inst{12-8} = 0b10111;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25111,7 +25601,7 @@ def SA1_zxth : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16),
 "$Rd16 = zxth($Rs16)",
-tc_d2609065, TypeSUBINSN>, Enc_97d666 {
+tc_a904d137, TypeSUBINSN>, Enc_97d666 {
 let Inst{12-8} = 0b10110;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25122,7 +25612,7 @@ def SL1_loadri_io : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
 "$Rd16 = memw($Rs16+#$Ii)",
-tc_bf6fa601, TypeSUBINSN>, Enc_53dca9 {
+tc_7f881c76, TypeSUBINSN>, Enc_53dca9 {
 let Inst{12-12} = 0b0;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25136,7 +25626,7 @@ def SL1_loadrub_io : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
 "$Rd16 = memub($Rs16+#$Ii)",
-tc_bf6fa601, TypeSUBINSN>, Enc_c175d0 {
+tc_7f881c76, TypeSUBINSN>, Enc_c175d0 {
 let Inst{12-12} = 0b1;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25150,12 +25640,12 @@ def SL2_deallocframe : HInst<
 (outs),
 (ins),
 "deallocframe",
-tc_86442910, TypeSUBINSN>, Enc_e3b0c4 {
+tc_36c68ad1, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111100000000;
 let accessSize = DoubleWordAccess;
 let AsmVariantName = "NonParsable";
 let mayLoad = 1;
-let Uses = [R30];
+let Uses = [FRAMEKEY, R30];
 let Defs = [R30, R29, R31];
 let DecoderNamespace = "SUBINSN_L2";
 }
@@ -25163,12 +25653,12 @@ def SL2_jumpr31 : HInst<
 (outs),
 (ins),
 "jumpr r31",
-tc_35fb9d13, TypeSUBINSN>, Enc_e3b0c4 {
+tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111111000000;
 let isTerminator = 1;
 let isIndirectBranch = 1;
-let cofMax1 = 1;
 let AsmVariantName = "NonParsable";
+let cofMax1 = 1;
 let isReturn = 1;
 let Uses = [R31];
 let Defs = [PC];
@@ -25178,14 +25668,14 @@ def SL2_jumpr31_f : HInst<
 (outs),
 (ins),
 "if (!p0) jumpr r31",
-tc_35fb9d13, TypeSUBINSN>, Enc_e3b0c4 {
+tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111111000101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
-let cofMax1 = 1;
 let AsmVariantName = "NonParsable";
+let cofMax1 = 1;
 let isReturn = 1;
 let Uses = [P0, R31];
 let Defs = [PC];
@@ -25196,15 +25686,15 @@ def SL2_jumpr31_fnew : HInst<
 (outs),
 (ins),
 "if (!p0.new) jumpr:nt r31",
-tc_35fb9d13, TypeSUBINSN>, Enc_e3b0c4 {
+tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111111000111;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
-let cofMax1 = 1;
 let AsmVariantName = "NonParsable";
 let isPredicatedNew = 1;
+let cofMax1 = 1;
 let isReturn = 1;
 let Uses = [P0, R31];
 let Defs = [PC];
@@ -25215,13 +25705,13 @@ def SL2_jumpr31_t : HInst<
 (outs),
 (ins),
 "if (p0) jumpr r31",
-tc_35fb9d13, TypeSUBINSN>, Enc_e3b0c4 {
+tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111111000100;
 let isPredicated = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
-let cofMax1 = 1;
 let AsmVariantName = "NonParsable";
+let cofMax1 = 1;
 let isReturn = 1;
 let Uses = [P0, R31];
 let Defs = [PC];
@@ -25232,14 +25722,14 @@ def SL2_jumpr31_tnew : HInst<
 (outs),
 (ins),
 "if (p0.new) jumpr:nt r31",
-tc_35fb9d13, TypeSUBINSN>, Enc_e3b0c4 {
+tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111111000110;
 let isPredicated = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
-let cofMax1 = 1;
 let AsmVariantName = "NonParsable";
 let isPredicatedNew = 1;
+let cofMax1 = 1;
 let isReturn = 1;
 let Uses = [P0, R31];
 let Defs = [PC];
@@ -25250,7 +25740,7 @@ def SL2_loadrb_io : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii),
 "$Rd16 = memb($Rs16+#$Ii)",
-tc_bf6fa601, TypeSUBINSN>, Enc_2fbf3c {
+tc_7f881c76, TypeSUBINSN>, Enc_2fbf3c {
 let Inst{12-11} = 0b10;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25264,7 +25754,7 @@ def SL2_loadrd_sp : HInst<
 (outs GeneralDoubleLow8Regs:$Rdd8),
 (ins u5_3Imm:$Ii),
 "$Rdd8 = memd(r29+#$Ii)",
-tc_70cabf66, TypeSUBINSN>, Enc_86a14b {
+tc_9c98e8af, TypeSUBINSN>, Enc_86a14b {
 let Inst{12-8} = 0b11110;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25279,7 +25769,7 @@ def SL2_loadrh_io : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
 "$Rd16 = memh($Rs16+#$Ii)",
-tc_bf6fa601, TypeSUBINSN>, Enc_2bae10 {
+tc_7f881c76, TypeSUBINSN>, Enc_2bae10 {
 let Inst{12-11} = 0b00;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25293,7 +25783,7 @@ def SL2_loadri_sp : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins u5_2Imm:$Ii),
 "$Rd16 = memw(r29+#$Ii)",
-tc_70cabf66, TypeSUBINSN>, Enc_51635c {
+tc_9c98e8af, TypeSUBINSN>, Enc_51635c {
 let Inst{12-9} = 0b1110;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25308,7 +25798,7 @@ def SL2_loadruh_io : HInst<
 (outs GeneralSubRegs:$Rd16),
 (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
 "$Rd16 = memuh($Rs16+#$Ii)",
-tc_bf6fa601, TypeSUBINSN>, Enc_2bae10 {
+tc_7f881c76, TypeSUBINSN>, Enc_2bae10 {
 let Inst{12-11} = 0b01;
 let hasNewValue = 1;
 let opNewValue = 0;
@@ -25322,16 +25812,17 @@ def SL2_return : HInst<
 (outs),
 (ins),
 "dealloc_return",
-tc_95c54f8b, TypeSUBINSN>, Enc_e3b0c4 {
+tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111101000000;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let AsmVariantName = "NonParsable";
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [R30];
+let Uses = [FRAMEKEY, R30];
 let Defs = [PC, R30, R29, R31];
 let DecoderNamespace = "SUBINSN_L2";
 }
@@ -25339,18 +25830,19 @@ def SL2_return_f : HInst<
 (outs),
 (ins),
 "if (!p0) dealloc_return",
-tc_95c54f8b, TypeSUBINSN>, Enc_e3b0c4 {
+tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111101000101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let AsmVariantName = "NonParsable";
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [P0, R30];
+let Uses = [FRAMEKEY, P0, R30];
 let Defs = [PC, R30, R29, R31];
 let isTaken = Inst{4};
 let DecoderNamespace = "SUBINSN_L2";
@@ -25359,19 +25851,20 @@ def SL2_return_fnew : HInst<
 (outs),
 (ins),
 "if (!p0.new) dealloc_return:nt",
-tc_95c54f8b, TypeSUBINSN>, Enc_e3b0c4 {
+tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111101000111;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let AsmVariantName = "NonParsable";
 let isPredicatedNew = 1;
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [P0, R30];
+let Uses = [FRAMEKEY, P0, R30];
 let Defs = [PC, R30, R29, R31];
 let isTaken = Inst{4};
 let DecoderNamespace = "SUBINSN_L2";
@@ -25380,17 +25873,18 @@ def SL2_return_t : HInst<
 (outs),
 (ins),
 "if (p0) dealloc_return",
-tc_95c54f8b, TypeSUBINSN>, Enc_e3b0c4 {
+tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111101000100;
 let isPredicated = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let AsmVariantName = "NonParsable";
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [P0, R30];
+let Uses = [FRAMEKEY, P0, R30];
 let Defs = [PC, R30, R29, R31];
 let isTaken = Inst{4};
 let DecoderNamespace = "SUBINSN_L2";
@@ -25399,18 +25893,19 @@ def SL2_return_tnew : HInst<
 (outs),
 (ins),
 "if (p0.new) dealloc_return:nt",
-tc_95c54f8b, TypeSUBINSN>, Enc_e3b0c4 {
+tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
 let Inst{12-0} = 0b1111101000110;
 let isPredicated = 1;
 let isTerminator = 1;
 let isIndirectBranch = 1;
 let accessSize = DoubleWordAccess;
-let cofMax1 = 1;
 let AsmVariantName = "NonParsable";
 let isPredicatedNew = 1;
 let mayLoad = 1;
+let cofMax1 = 1;
+let isRestrictNoSlot1Store = 1;
 let isReturn = 1;
-let Uses = [P0, R30];
+let Uses = [FRAMEKEY, P0, R30];
 let Defs = [PC, R30, R29, R31];
 let isTaken = Inst{4};
 let DecoderNamespace = "SUBINSN_L2";
@@ -25419,7 +25914,7 @@ def SS1_storeb_io : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16),
 "memb($Rs16+#$Ii) = $Rt16",
-tc_53ee6546, TypeSUBINSN>, Enc_b38ffc {
+tc_05b6c987, TypeSUBINSN>, Enc_b38ffc {
 let Inst{12-12} = 0b1;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
@@ -25431,7 +25926,7 @@ def SS1_storew_io : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16),
 "memw($Rs16+#$Ii) = $Rt16",
-tc_53ee6546, TypeSUBINSN>, Enc_f55a0c {
+tc_05b6c987, TypeSUBINSN>, Enc_f55a0c {
 let Inst{12-12} = 0b0;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
@@ -25443,14 +25938,14 @@ def SS2_allocframe : HInst<
 (outs),
 (ins u5_3Imm:$Ii),
 "allocframe(#$Ii)",
-tc_f027ebe9, TypeSUBINSN>, Enc_6f70ca {
+tc_0fc1ae07, TypeSUBINSN>, Enc_6f70ca {
 let Inst{3-0} = 0b0000;
 let Inst{12-9} = 0b1110;
 let addrMode = BaseImmOffset;
 let accessSize = DoubleWordAccess;
 let AsmVariantName = "NonParsable";
 let mayStore = 1;
-let Uses = [R30, R29, R31];
+let Uses = [FRAMEKEY, FRAMELIMIT, R30, R29, R31];
 let Defs = [R30, R29];
 let DecoderNamespace = "SUBINSN_S2";
 }
@@ -25458,7 +25953,7 @@ def SS2_storebi0 : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
 "memb($Rs16+#$Ii) = #0",
-tc_6c52d277, TypeSUBINSN>, Enc_84d359 {
+tc_57288781, TypeSUBINSN>, Enc_84d359 {
 let Inst{12-8} = 0b10010;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
@@ -25470,7 +25965,7 @@ def SS2_storebi1 : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
 "memb($Rs16+#$Ii) = #1",
-tc_6c52d277, TypeSUBINSN>, Enc_84d359 {
+tc_57288781, TypeSUBINSN>, Enc_84d359 {
 let Inst{12-8} = 0b10011;
 let addrMode = BaseImmOffset;
 let accessSize = ByteAccess;
@@ -25482,7 +25977,7 @@ def SS2_stored_sp : HInst<
 (outs),
 (ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8),
 "memd(r29+#$Ii) = $Rtt8",
-tc_c14739d5, TypeSUBINSN>, Enc_b8309d {
+tc_a788683e, TypeSUBINSN>, Enc_b8309d {
 let Inst{12-9} = 0b0101;
 let addrMode = BaseImmOffset;
 let accessSize = DoubleWordAccess;
@@ -25495,7 +25990,7 @@ def SS2_storeh_io : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16),
 "memh($Rs16+#$Ii) = $Rt16",
-tc_53ee6546, TypeSUBINSN>, Enc_625deb {
+tc_05b6c987, TypeSUBINSN>, Enc_625deb {
 let Inst{12-11} = 0b00;
 let addrMode = BaseImmOffset;
 let accessSize = HalfWordAccess;
@@ -25507,7 +26002,7 @@ def SS2_storew_sp : HInst<
 (outs),
 (ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16),
 "memw(r29+#$Ii) = $Rt16",
-tc_c14739d5, TypeSUBINSN>, Enc_87c142 {
+tc_a788683e, TypeSUBINSN>, Enc_87c142 {
 let Inst{12-9} = 0b0100;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
@@ -25520,7 +26015,7 @@ def SS2_storewi0 : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
 "memw($Rs16+#$Ii) = #0",
-tc_6c52d277, TypeSUBINSN>, Enc_a6ce9c {
+tc_57288781, TypeSUBINSN>, Enc_a6ce9c {
 let Inst{12-8} = 0b10000;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
@@ -25532,7 +26027,7 @@ def SS2_storewi1 : HInst<
 (outs),
 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
 "memw($Rs16+#$Ii) = #1",
-tc_6c52d277, TypeSUBINSN>, Enc_a6ce9c {
+tc_57288781, TypeSUBINSN>, Enc_a6ce9c {
 let Inst{12-8} = 0b10001;
 let addrMode = BaseImmOffset;
 let accessSize = WordAccess;
@@ -25541,324 +26036,136 @@ let mayStore = 1;
 let DecoderNamespace = "SUBINSN_S2";
 }
 def V6_MAP_equb : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_MAP_equb_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_MAP_equb_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_MAP_equb_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_MAP_equb_ior : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_MAP_equb_ior_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_MAP_equb_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_MAP_equb_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_MAP_equh : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_MAP_equh_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_MAP_equh_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_MAP_equh_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_MAP_equh_ior : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_MAP_equh_ior_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_MAP_equh_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_MAP_equh_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_MAP_equw : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_MAP_equw_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_MAP_equw_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_MAP_equw_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_MAP_equw_ior : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_MAP_equw_ior_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_MAP_equw_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_MAP_equw_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_extractw : HInst<
 (outs IntRegs:$Rd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rs32),
-"$Rd32 = vextract($Vu32,$Rs32)",
-tc_9777e6bf, TypeLD>, Enc_50e578, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b10010010000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isSolo = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_extractw_128B : HInst<
-(outs IntRegs:$Rd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rs32),
+(ins HvxVR:$Vu32, IntRegs:$Rs32),
 "$Rd32 = vextract($Vu32,$Rs32)",
-tc_9777e6bf, TypeLD>, Enc_50e578, Requires<[HasV60T,UseHVX]> {
+tc_9777e6bf, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10010010000;
@@ -25867,505 +26174,252 @@ let opNewValue = 0;
 let isSolo = 1;
 let mayLoad = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_extractw_alt : HInst<
 (outs IntRegs:$Rd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rs32),
-"$Rd32.w = vextract($Vu32,$Rs32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_extractw_alt_128B : HInst<
-(outs IntRegs:$Rd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rs32),
+(ins HvxVR:$Vu32, IntRegs:$Rs32),
 "$Rd32.w = vextract($Vu32,$Rs32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_hi : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecDblRegs:$Vss32),
+(outs HvxVR:$Vd32),
+(ins HvxWR:$Vss32),
 "$Vd32 = hi($Vss32)",
-CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> {
+CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_hi_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecDblRegs128B:$Vss32),
-"$Vd32 = hi($Vss32)",
-CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_ld0 : HInst<
-(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32),
-"$Vd32 = vmem($Rt32)",
-PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_ld0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32),
 "$Vd32 = vmem($Rt32)",
-PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_ldcnp0 : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if (!$Pv4) $Vd32.cur = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_ldcnp0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if (!$Pv4) $Vd32.cur = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_ldcnpnt0 : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if (!$Pv4) $Vd32.cur = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_ldcnpnt0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_ldcp0 : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if ($Pv4) $Vd32.cur = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_ldcp0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if ($Pv4) $Vd32.cur = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_ldcpnt0 : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if ($Pv4) $Vd32.cur = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_ldcpnt0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if ($Pv4) $Vd32.cur = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_ldnp0 : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if (!$Pv4) $Vd32 = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_ldnp0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if (!$Pv4) $Vd32 = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_ldnpnt0 : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if (!$Pv4) $Vd32 = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_ldnpnt0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if (!$Pv4) $Vd32 = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_ldnt0 : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32),
 "$Vd32 = vmem($Rt32):nt",
-PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_ldnt0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+def V6_ldntnt0 : HInst<
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32),
 "$Vd32 = vmem($Rt32):nt",
-PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[HasV62T]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_ldp0 : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if ($Pv4) $Vd32 = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_ldp0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if ($Pv4) $Vd32 = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_ldpnt0 : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if ($Pv4) $Vd32 = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_ldpnt0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if ($Pv4) $Vd32 = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_ldtnp0 : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if (!$Pv4) $Vd32.tmp = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_ldtnp0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if (!$Pv4) $Vd32.tmp = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_ldtnpnt0 : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_ldtnpnt0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_ldtp0 : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if ($Pv4) $Vd32.tmp = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_ldtp0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if ($Pv4) $Vd32.tmp = vmem($Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_ldtpnt0 : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32),
-"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_ldtpnt0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32),
 "if ($Pv4) $Vd32.tmp = vmem($Rt32):nt",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_ldu0 : HInst<
-(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32),
-"$Vd32 = vmemu($Rt32)",
-PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_ldu0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32),
 "$Vd32 = vmemu($Rt32)",
-PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_lo : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecDblRegs:$Vss32),
-"$Vd32 = lo($Vss32)",
-CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_lo_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecDblRegs128B:$Vss32),
+(outs HvxVR:$Vd32),
+(ins HvxWR:$Vss32),
 "$Vd32 = lo($Vss32)",
-CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> {
+CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_lvsplatb : HInst<
-(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32),
-"$Vd32.b = vsplat($Rt32)",
-tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[HasV62T,UseHVX]> {
-let Inst{13-5} = 0b000000010;
-let Inst{31-21} = 0b00011001110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_lvsplatb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32),
 "$Vd32.b = vsplat($Rt32)",
-tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[HasV62T,UseHVX]> {
+tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> {
 let Inst{13-5} = 0b000000010;
 let Inst{31-21} = 0b00011001110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_lvsplath : HInst<
-(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32),
-"$Vd32.h = vsplat($Rt32)",
-tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[HasV62T,UseHVX]> {
-let Inst{13-5} = 0b000000001;
-let Inst{31-21} = 0b00011001110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_lvsplath_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32),
 "$Vd32.h = vsplat($Rt32)",
-tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[HasV62T,UseHVX]> {
+tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b00011001110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_lvsplatw : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32),
 "$Vd32 = vsplat($Rt32)",
-tc_6b78cf13, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[HasV60T,UseHVX]> {
+tc_6b78cf13, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> {
 let Inst{13-5} = 0b000000001;
 let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_lvsplatw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins IntRegs:$Rt32),
-"$Vd32 = vsplat($Rt32)",
-tc_6b78cf13, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[HasV60T,UseHVX]> {
-let Inst{13-5} = 0b000000001;
-let Inst{31-21} = 0b00011001101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_pred_and : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4),
-"$Qd4 = and($Qs4,$Qt4)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000000;
-let Inst{13-10} = 0b0000;
-let Inst{21-16} = 0b000011;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_pred_and_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4),
+(outs HvxQR:$Qd4),
+(ins HvxQR:$Qs4, HvxQR:$Qt4),
 "$Qd4 = and($Qs4,$Qt4)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000000;
 let Inst{13-10} = 0b0000;
 let Inst{21-16} = 0b000011;
@@ -26373,26 +26427,12 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_pred_and_n : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4),
-"$Qd4 = and($Qs4,!$Qt4)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000101;
-let Inst{13-10} = 0b0000;
-let Inst{21-16} = 0b000011;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_pred_and_n_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4),
+(outs HvxQR:$Qd4),
+(ins HvxQR:$Qs4, HvxQR:$Qt4),
 "$Qd4 = and($Qs4,!$Qt4)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000101;
 let Inst{13-10} = 0b0000;
 let Inst{21-16} = 0b000011;
@@ -26400,13 +26440,12 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_pred_not : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VecPredRegs:$Qs4),
+(outs HvxQR:$Qd4),
+(ins HvxQR:$Qs4),
 "$Qd4 = not($Qs4)",
-tc_71337255, TypeCVI_VA>, Enc_bfbf03, Requires<[HasV60T,UseHVX]> {
+tc_71337255, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000010;
 let Inst{13-10} = 0b0000;
 let Inst{31-16} = 0b0001111000000011;
@@ -26414,37 +26453,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_pred_not_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VecPredRegs128B:$Qs4),
-"$Qd4 = not($Qs4)",
-tc_71337255, TypeCVI_VA>, Enc_bfbf03, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000010;
-let Inst{13-10} = 0b0000;
-let Inst{31-16} = 0b0001111000000011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_pred_or : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4),
-"$Qd4 = or($Qs4,$Qt4)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000001;
-let Inst{13-10} = 0b0000;
-let Inst{21-16} = 0b000011;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_pred_or_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4),
+(outs HvxQR:$Qd4),
+(ins HvxQR:$Qs4, HvxQR:$Qt4),
 "$Qd4 = or($Qs4,$Qt4)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000001;
 let Inst{13-10} = 0b0000;
 let Inst{21-16} = 0b000011;
@@ -26452,13 +26465,12 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_pred_or_n : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4),
+(outs HvxQR:$Qd4),
+(ins HvxQR:$Qs4, HvxQR:$Qt4),
 "$Qd4 = or($Qs4,!$Qt4)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000100;
 let Inst{13-10} = 0b0000;
 let Inst{21-16} = 0b000011;
@@ -26467,84 +26479,33 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_pred_or_n_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4),
-"$Qd4 = or($Qs4,!$Qt4)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000100;
-let Inst{13-10} = 0b0000;
-let Inst{21-16} = 0b000011;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_pred_scalar2 : HInst<
-(outs VecPredRegs:$Qd4),
-(ins IntRegs:$Rt32),
-"$Qd4 = vsetq($Rt32)",
-tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[HasV60T,UseHVX]> {
-let Inst{13-2} = 0b000000010001;
-let Inst{31-21} = 0b00011001101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_pred_scalar2_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
+(outs HvxQR:$Qd4),
 (ins IntRegs:$Rt32),
 "$Qd4 = vsetq($Rt32)",
-tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[HasV60T,UseHVX]> {
+tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> {
 let Inst{13-2} = 0b000000010001;
 let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_pred_scalar2v2 : HInst<
-(outs VecPredRegs:$Qd4),
-(ins IntRegs:$Rt32),
-"$Qd4 = vsetq2($Rt32)",
-tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[HasV62T,UseHVX]> {
-let Inst{13-2} = 0b000000010011;
-let Inst{31-21} = 0b00011001101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_pred_scalar2v2_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
+(outs HvxQR:$Qd4),
 (ins IntRegs:$Rt32),
 "$Qd4 = vsetq2($Rt32)",
-tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[HasV62T,UseHVX]> {
+tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> {
 let Inst{13-2} = 0b000000010011;
 let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_pred_xor : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4),
-"$Qd4 = xor($Qs4,$Qt4)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000011;
-let Inst{13-10} = 0b0000;
-let Inst{21-16} = 0b000011;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_pred_xor_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4),
+(outs HvxQR:$Qd4),
+(ins HvxQR:$Qs4, HvxQR:$Qt4),
 "$Qd4 = xor($Qs4,$Qt4)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000011;
 let Inst{13-10} = 0b0000;
 let Inst{21-16} = 0b000011;
@@ -26552,26 +26513,12 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_shuffeqh : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4),
-"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV62T,UseHVX]> {
-let Inst{7-2} = 0b000110;
-let Inst{13-10} = 0b0000;
-let Inst{21-16} = 0b000011;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_shuffeqh_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4),
+(outs HvxQR:$Qd4),
+(ins HvxQR:$Qs4, HvxQR:$Qt4),
 "$Qd4.b = vshuffe($Qs4.h,$Qt4.h)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV62T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
 let Inst{7-2} = 0b000110;
 let Inst{13-10} = 0b0000;
 let Inst{21-16} = 0b000011;
@@ -26579,26 +26526,12 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_shuffeqw : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4),
-"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV62T,UseHVX]> {
-let Inst{7-2} = 0b000111;
-let Inst{13-10} = 0b0000;
-let Inst{21-16} = 0b000011;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_shuffeqw_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4),
+(outs HvxQR:$Qd4),
+(ins HvxQR:$Qs4, HvxQR:$Qt4),
 "$Qd4.h = vshuffe($Qs4.w,$Qt4.w)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV62T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
 let Inst{7-2} = 0b000111;
 let Inst{13-10} = 0b0000;
 let Inst{21-16} = 0b000011;
@@ -26606,473 +26539,242 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_st0 : HInst<
 (outs),
-(ins IntRegs:$Rt32, VectorRegs:$Vs32),
-"vmem($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_st0_128B : HInst<
-(outs),
-(ins IntRegs:$Rt32, VectorRegs128B:$Vs32),
+(ins IntRegs:$Rt32, HvxVR:$Vs32),
 "vmem($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_stn0 : HInst<
 (outs),
-(ins IntRegs:$Rt32, VectorRegs:$Os8),
-"vmem($Rt32) = $Os8.new",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let opNewValue = 1;
-}
-def V6_stn0_128B : HInst<
-(outs),
-(ins IntRegs:$Rt32, VectorRegs128B:$Os8),
+(ins IntRegs:$Rt32, HvxVR:$Os8),
 "vmem($Rt32) = $Os8.new",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let opNewValue = 1;
 }
 def V6_stnnt0 : HInst<
 (outs),
-(ins IntRegs:$Rt32, VectorRegs:$Os8),
+(ins IntRegs:$Rt32, HvxVR:$Os8),
 "vmem($Rt32):nt = $Os8.new",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 1;
 }
-def V6_stnnt0_128B : HInst<
-(outs),
-(ins IntRegs:$Rt32, VectorRegs128B:$Os8),
-"vmem($Rt32):nt = $Os8.new",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 1;
-}
 def V6_stnp0 : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32),
-"if (!$Pv4) vmem($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_stnp0_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
 "if (!$Pv4) vmem($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_stnpnt0 : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32),
-"if (!$Pv4) vmem($Rt32):nt = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_stnpnt0_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
 "if (!$Pv4) vmem($Rt32):nt = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_stnq0 : HInst<
 (outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
 "if (!$Qv4) vmem($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_stnq0_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32),
-"if (!$Qv4) vmem($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_stnqnt0 : HInst<
 (outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32),
-"if (!$Qv4) vmem($Rt32):nt = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_stnqnt0_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
 "if (!$Qv4) vmem($Rt32):nt = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_stnt0 : HInst<
 (outs),
-(ins IntRegs:$Rt32, VectorRegs:$Vs32),
+(ins IntRegs:$Rt32, HvxVR:$Vs32),
 "vmem($Rt32):nt = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_stnt0_128B : HInst<
-(outs),
-(ins IntRegs:$Rt32, VectorRegs128B:$Vs32),
-"vmem($Rt32):nt = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_stp0 : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32),
-"if ($Pv4) vmem($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_stp0_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
 "if ($Pv4) vmem($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_stpnt0 : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
 "if ($Pv4) vmem($Rt32):nt = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_stpnt0_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32),
-"if ($Pv4) vmem($Rt32):nt = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_stq0 : HInst<
 (outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
 "if ($Qv4) vmem($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_stq0_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32),
-"if ($Qv4) vmem($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_stqnt0 : HInst<
 (outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32),
-"if ($Qv4) vmem($Rt32):nt = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_stqnt0_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
 "if ($Qv4) vmem($Rt32):nt = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_stu0 : HInst<
 (outs),
-(ins IntRegs:$Rt32, VectorRegs:$Vs32),
-"vmemu($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_stu0_128B : HInst<
-(outs),
-(ins IntRegs:$Rt32, VectorRegs128B:$Vs32),
+(ins IntRegs:$Rt32, HvxVR:$Vs32),
 "vmemu($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_stunp0 : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32),
-"if (!$Pv4) vmemu($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_stunp0_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
 "if (!$Pv4) vmemu($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_stup0 : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
 "if ($Pv4) vmemu($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_stup0_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32),
-"if ($Pv4) vmemu($Rt32) = $Vs32",
-PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> {
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vL32Ub_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii),
-"$Vd32 = vmemu($Rt32+#$Ii)",
-tc_35e92f8e, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32Ub_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
 "$Vd32 = vmemu($Rt32+#$Ii)",
-tc_35e92f8e, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
+tc_35e92f8e, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32Ub_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
-"$Vd32 = vmemu($Rx32++#$Ii)",
-tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32Ub_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
 "$Vd32 = vmemu($Rx32++#$Ii)",
-tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
+tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_pi";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32Ub_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2),
-"$Vd32 = vmemu($Rx32++$Mu2)",
-tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
-let Inst{12-5} = 0b00000111;
-let Inst{31-21} = 0b00101011000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32Ub_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Vd32 = vmemu($Rx32++$Mu2)",
-tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
+tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> {
 let Inst{12-5} = 0b00000111;
 let Inst{31-21} = 0b00101011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_ai : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
 "$Vd32 = vmem($Rt32+#$Ii)",
-tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
+tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b000;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isCVLoadable = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii),
-"$Vd32 = vmem($Rt32+#$Ii)",
-tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_ai";
 let isCVLoadable = 1;
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_cur_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii),
-"$Vd32.cur = vmem($Rt32+#$Ii)",
-tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_cur_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
 "$Vd32.cur = vmem($Rt32+#$Ii)",
-tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
+tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b001;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_cur_ai";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_cur_npred_ai : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b101;
 let Inst{31-21} = 0b00101000100;
 let isPredicated = 1;
@@ -27080,36 +26782,19 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_cur_ai";
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vL32b_cur_npred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{31-21} = 0b00101000100;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vL32b_cur_npred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001100;
@@ -27118,58 +26803,20 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_cur_pi";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vL32b_cur_npred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001100;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vL32b_cur_npred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000101;
-let Inst{31-21} = 0b00101011100;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_cur_npred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000101;
 let Inst{31-21} = 0b00101011100;
 let isPredicated = 1;
@@ -27177,126 +26824,80 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_cur_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_cur_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
-"$Vd32.cur = vmem($Rx32++#$Ii)",
-tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_cur_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
 "$Vd32.cur = vmem($Rx32++#$Ii)",
-tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
+tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b001;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_cur_pi";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_cur_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2),
-"$Vd32.cur = vmem($Rx32++$Mu2)",
-tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
-let Inst{12-5} = 0b00000001;
-let Inst{31-21} = 0b00101011000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_cur_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Vd32.cur = vmem($Rx32++$Mu2)",
-tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
+tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
 let Inst{12-5} = 0b00000001;
 let Inst{31-21} = 0b00101011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_cur_ppu";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_cur_pred_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{31-21} = 0b00101000100;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_cur_pred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b100;
 let Inst{31-21} = 0b00101000100;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_cur_ai";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_cur_pred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001100;
@@ -27304,75 +26905,40 @@ let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_cur_pi";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vL32b_cur_pred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001100;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vL32b_cur_pred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000100;
-let Inst{31-21} = 0b00101011100;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_cur_pred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000100;
 let Inst{31-21} = 0b00101011100;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_cur_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_npred_ai : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b011;
 let Inst{31-21} = 0b00101000100;
 let isPredicated = 1;
@@ -27380,34 +26946,18 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_ai";
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vL32b_npred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{31-21} = 0b00101000100;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vL32b_npred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001100;
@@ -27416,55 +26966,19 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_pi";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vL32b_npred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001100;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vL32b_npred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000011;
-let Inst{31-21} = 0b00101011100;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_npred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000011;
 let Inst{31-21} = 0b00101011100;
 let isPredicated = 1;
@@ -27472,111 +26986,61 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii),
-"$Vd32 = vmem($Rt32+#$Ii):nt",
-tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let isCVLoadable = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_nt_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
 "$Vd32 = vmem($Rt32+#$Ii):nt",
-tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
+tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b000;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_ai";
 let isCVLoadable = 1;
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_nt_cur_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii),
-"$Vd32.cur = vmem($Rt32+#$Ii):nt",
-tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_nt_cur_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
 "$Vd32.cur = vmem($Rt32+#$Ii):nt",
-tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
+tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b001;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_cur_ai";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_nt_cur_npred_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{31-21} = 0b00101000110;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_nt_cur_npred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b101;
 let Inst{31-21} = 0b00101000110;
 let isPredicated = 1;
@@ -27584,19 +27048,20 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_cur_ai";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_nt_cur_npred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001110;
@@ -27605,61 +27070,21 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_cur_pi";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vL32b_nt_cur_npred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001110;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vL32b_nt_cur_npred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000101;
-let Inst{31-21} = 0b00101011110;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_cur_npred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000101;
 let Inst{31-21} = 0b00101011110;
 let isPredicated = 1;
@@ -27667,153 +27092,84 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_cur_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_cur_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
 "$Vd32.cur = vmem($Rx32++#$Ii):nt",
-tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
+tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b001;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_cur_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
-"$Vd32.cur = vmem($Rx32++#$Ii):nt",
-tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_cur_pi";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_cur_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Vd32.cur = vmem($Rx32++$Mu2):nt",
-tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
+tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
 let Inst{12-5} = 0b00000001;
 let Inst{31-21} = 0b00101011010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_cur_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2),
-"$Vd32.cur = vmem($Rx32++$Mu2):nt",
-tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
-let Inst{12-5} = 0b00000001;
-let Inst{31-21} = 0b00101011010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_cur_ppu";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_cur_pred_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{31-21} = 0b00101000110;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_nt_cur_pred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b100;
 let Inst{31-21} = 0b00101000110;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_cur_ai";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_nt_cur_pred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001110;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_cur_pred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001110;
@@ -27821,77 +27177,42 @@ let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_cur_pi";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_cur_pred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000100;
-let Inst{31-21} = 0b00101011110;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let CVINew = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_cur_pred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000100;
 let Inst{31-21} = 0b00101011110;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let CVINew = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_cur_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_npred_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{31-21} = 0b00101000110;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_nt_npred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b011;
 let Inst{31-21} = 0b00101000110;
 let isPredicated = 1;
@@ -27899,18 +27220,19 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_ai";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_nt_npred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001110;
@@ -27919,58 +27241,20 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_pi";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vL32b_nt_npred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001110;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vL32b_nt_npred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000011;
-let Inst{31-21} = 0b00101011110;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_npred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000011;
 let Inst{31-21} = 0b00101011110;
 let isPredicated = 1;
@@ -27978,149 +27262,82 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
 "$Vd32 = vmem($Rx32++#$Ii):nt",
-tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
+tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b000;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let isCVLoadable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
-"$Vd32 = vmem($Rx32++#$Ii):nt",
-tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_pi";
 let isCVLoadable = 1;
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Vd32 = vmem($Rx32++$Mu2):nt",
-tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
+tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b00101011010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let isCVLoadable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2),
-"$Vd32 = vmem($Rx32++$Mu2):nt",
-tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
-let Inst{12-5} = 0b00000000;
-let Inst{31-21} = 0b00101011010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_ppu";
 let isCVLoadable = 1;
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_pred_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{31-21} = 0b00101000110;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_nt_pred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b010;
 let Inst{31-21} = 0b00101000110;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_ai";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_nt_pred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001110;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_pred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001110;
@@ -28128,91 +27345,60 @@ let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_pi";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_pred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000010;
-let Inst{31-21} = 0b00101011110;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_pred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000010;
 let Inst{31-21} = 0b00101011110;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_tmp_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii),
-"$Vd32.tmp = vmem($Rt32+#$Ii):nt",
-tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_nt_tmp_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
 "$Vd32.tmp = vmem($Rt32+#$Ii):nt",
-tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
+tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b010;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_tmp_ai";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_nt_tmp_npred_ai : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
-tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b111;
 let Inst{31-21} = 0b00101000110;
 let isPredicated = 1;
@@ -28220,56 +27406,19 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_tmp_ai";
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vL32b_nt_tmp_npred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
-tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{31-21} = 0b00101000110;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vL32b_nt_tmp_npred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001110;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_tmp_npred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001110;
@@ -28278,19 +27427,20 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_tmp_pi";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_tmp_npred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000111;
 let Inst{31-21} = 0b00101011110;
 let isPredicated = 1;
@@ -28298,164 +27448,80 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vL32b_nt_tmp_npred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000111;
-let Inst{31-21} = 0b00101011110;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vL32b_nt_tmp_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
 "$Vd32.tmp = vmem($Rx32++#$Ii):nt",
-tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
+tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b010;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_tmp_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
-"$Vd32.tmp = vmem($Rx32++#$Ii):nt",
-tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_tmp_pi";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_tmp_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2),
-"$Vd32.tmp = vmem($Rx32++$Mu2):nt",
-tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
-let Inst{12-5} = 0b00000010;
-let Inst{31-21} = 0b00101011010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_tmp_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Vd32.tmp = vmem($Rx32++$Mu2):nt",
-tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
+tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
 let Inst{12-5} = 0b00000010;
 let Inst{31-21} = 0b00101011010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_tmp_pred_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
-tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{31-21} = 0b00101000110;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_nt_tmp_pred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
-tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b110;
 let Inst{31-21} = 0b00101000110;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_tmp_ai";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_nt_tmp_pred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001110;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_tmp_pred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001110;
@@ -28463,161 +27529,99 @@ let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_tmp_pi";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_nt_tmp_pred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000110;
-let Inst{31-21} = 0b00101011110;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isNonTemporal = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_nt_tmp_pred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000110;
 let Inst{31-21} = 0b00101011110;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
 let isNonTemporal = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
 "$Vd32 = vmem($Rx32++#$Ii)",
-tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
+tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b000;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isCVLoadable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
-"$Vd32 = vmem($Rx32++#$Ii)",
-tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_pi";
 let isCVLoadable = 1;
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2),
-"$Vd32 = vmem($Rx32++$Mu2)",
-tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
-let Inst{12-5} = 0b00000000;
-let Inst{31-21} = 0b00101011000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let isCVLoadable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Vd32 = vmem($Rx32++$Mu2)",
-tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
+tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b00101011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_ppu";
 let isCVLoadable = 1;
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_pred_ai : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b010;
 let Inst{31-21} = 0b00101000100;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_ai";
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vL32b_pred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
-tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{31-21} = 0b00101000100;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vL32b_pred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001100;
@@ -28625,104 +27629,57 @@ let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_pi";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vL32b_pred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001100;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vL32b_pred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000010;
-let Inst{31-21} = 0b00101011100;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_pred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)",
-tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000010;
 let Inst{31-21} = 0b00101011100;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_tmp_ai : HInst<
-(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii),
-"$Vd32.tmp = vmem($Rt32+#$Ii)",
-tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL32b_tmp_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+(outs HvxVR:$Vd32),
 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
 "$Vd32.tmp = vmem($Rt32+#$Ii)",
-tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> {
+tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b010;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_tmp_ai";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vL32b_tmp_npred_ai : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
-tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b111;
 let Inst{31-21} = 0b00101000100;
 let isPredicated = 1;
@@ -28730,53 +27687,18 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_tmp_ai";
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vL32b_tmp_npred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
-tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{31-21} = 0b00101000100;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vL32b_tmp_npred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001100;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_tmp_npred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001100;
@@ -28785,36 +27707,19 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_tmp_pi";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_tmp_npred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000111;
-let Inst{31-21} = 0b00101011100;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_tmp_npred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000111;
 let Inst{31-21} = 0b00101011100;
 let isPredicated = 1;
@@ -28822,119 +27727,76 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_tmp_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_tmp_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
 "$Vd32.tmp = vmem($Rx32++#$Ii)",
-tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
+tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
 let Inst{7-5} = 0b010;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_tmp_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
-"$Vd32.tmp = vmem($Rx32++#$Ii)",
-tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_tmp_pi";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_tmp_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2),
-"$Vd32.tmp = vmem($Rx32++$Mu2)",
-tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
-let Inst{12-5} = 0b00000010;
-let Inst{31-21} = 0b00101011000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_tmp_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
 "$Vd32.tmp = vmem($Rx32++$Mu2)",
-tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> {
+tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
 let Inst{12-5} = 0b00000010;
 let Inst{31-21} = 0b00101011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_tmp_ppu";
+let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vL32b_tmp_pred_ai : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
 "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
-tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
+tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b110;
 let Inst{31-21} = 0b00101000100;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_tmp_ai";
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vL32b_tmp_pred_ai_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
-"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
-tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{31-21} = 0b00101000100;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vL32b_tmp_pred_pi : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
 "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
+tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001100;
@@ -28942,396 +27804,198 @@ let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_tmp_pi";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vL32b_tmp_pred_pi_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
-"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001100;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vL32b_tmp_pred_ppu : HInst<
-(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
-"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
-let Inst{10-5} = 0b000110;
-let Inst{31-21} = 0b00101011100;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isCVLoad = 1;
-let mayLoad = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL32b_tmp_pred_ppu_128B : HInst<
-(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
+(outs HvxVR:$Vd32, IntRegs:$Rx32),
 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
 "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
-tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> {
+tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
 let Inst{10-5} = 0b000110;
 let Inst{31-21} = 0b00101011100;
 let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isCVLoad = 1;
 let mayLoad = 1;
+let isRestrictNoSlot1Store = 1;
+let BaseOpcode = "V6_vL32b_tmp_ppu";
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vS32Ub_ai : HInst<
 (outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "vmemu($Rt32+#$Ii) = $Vs32",
-tc_354299ad, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_354299ad, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b111;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000001;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32Ub_ai";
 let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vS32Ub_ai_128B : HInst<
-(outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
-"vmemu($Rt32+#$Ii) = $Vs32",
-tc_354299ad, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b111;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000001;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32Ub_ai_128B";
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vS32Ub_npred_ai : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
-tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b111;
 let Inst{31-21} = 0b00101000101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32Ub_ai";
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vS32Ub_npred_ai_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
-tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b111;
-let Inst{31-21} = 0b00101000101;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32Ub_ai_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vS32Ub_npred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
-tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32Ub_pi";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32Ub_npred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
-tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001101;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32Ub_pi_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32Ub_npred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32",
-tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{10-5} = 0b000111;
 let Inst{31-21} = 0b00101011101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32Ub_ppu";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32Ub_npred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
-"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32",
-tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{10-5} = 0b000111;
-let Inst{31-21} = 0b00101011101;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32Ub_ppu_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32Ub_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "vmemu($Rx32++#$Ii) = $Vs32",
-tc_7fa82b08, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_7fa82b08, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b111;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001001;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32Ub_pi";
 let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32Ub_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
-"vmemu($Rx32++#$Ii) = $Vs32",
-tc_7fa82b08, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b111;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001001;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32Ub_pi_128B";
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32Ub_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
+(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "vmemu($Rx32++$Mu2) = $Vs32",
-tc_7fa82b08, TypeCVI_VM_STU>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_7fa82b08, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{12-5} = 0b00000111;
 let Inst{31-21} = 0b00101011001;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32Ub_ppu";
 let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32Ub_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
-"vmemu($Rx32++$Mu2) = $Vs32",
-tc_7fa82b08, TypeCVI_VM_STU>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{12-5} = 0b00000111;
-let Inst{31-21} = 0b00101011001;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32Ub_ppu_128B";
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32Ub_pred_ai : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
-tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b110;
 let Inst{31-21} = 0b00101000101;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32Ub_ai";
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vS32Ub_pred_ai_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
-tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b110;
-let Inst{31-21} = 0b00101000101;
-let isPredicated = 1;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32Ub_ai_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vS32Ub_pred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
-tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001101;
 let isPredicated = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32Ub_pi";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32Ub_pred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
-tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001101;
-let isPredicated = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32Ub_pi_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32Ub_pred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32",
-tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{10-5} = 0b000110;
 let Inst{31-21} = 0b00101011101;
 let isPredicated = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32Ub_ppu";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32Ub_pred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
-"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32",
-tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{10-5} = 0b000110;
-let Inst{31-21} = 0b00101011101;
-let isPredicated = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32Ub_ppu_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_ai : HInst<
 (outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "vmem($Rt32+#$Ii) = $Vs32",
-tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b000;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000001;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_ai";
 let isNVStorable = 1;
 let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vS32b_ai_128B : HInst<
-(outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
-"vmem($Rt32+#$Ii) = $Vs32",
-tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b000;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000001;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let isNVStorable = 1;
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vS32b_new_ai : HInst<
 (outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
 "vmem($Rt32+#$Ii) = $Os8.new",
-tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b00100;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000001;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29341,37 +28005,17 @@ let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 2;
 }
-def V6_vS32b_new_ai_128B : HInst<
-(outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
-"vmem($Rt32+#$Ii) = $Os8.new",
-tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b00100;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000001;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 2;
-}
 def V6_vS32b_new_npred_ai : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
 "if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
-tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b01101;
 let Inst{31-21} = 0b00101000101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29380,38 +28024,18 @@ let BaseOpcode = "V6_vS32b_ai";
 let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 3;
 }
-def V6_vS32b_new_npred_ai_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
-"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
-tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b01101;
-let Inst{31-21} = 0b00101000101;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 3;
-}
 def V6_vS32b_new_npred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
 "if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b01101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29421,39 +28045,17 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_new_npred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
-"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b01101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001101;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 4;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_new_npred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
 "if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{10-3} = 0b00001101;
 let Inst{31-21} = 0b00101011101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29463,37 +28065,16 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_new_npred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8),
-"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{10-3} = 0b00001101;
-let Inst{31-21} = 0b00101011101;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ppu_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 4;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_new_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
 "vmem($Rx32++#$Ii) = $Os8.new",
-tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b00100;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001001;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29504,36 +28085,15 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 3;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_new_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
-"vmem($Rx32++#$Ii) = $Os8.new",
-tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b00100;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001001;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 3;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_new_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8),
+(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
 "vmem($Rx32++$Mu2) = $Os8.new",
-tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{12-3} = 0b0000000100;
 let Inst{31-21} = 0b00101011001;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29544,36 +28104,16 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 3;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_new_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8),
-"vmem($Rx32++$Mu2) = $Os8.new",
-tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{12-3} = 0b0000000100;
-let Inst{31-21} = 0b00101011001;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ppu_128B";
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 3;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_new_pred_ai : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
 "if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
-tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b01000;
 let Inst{31-21} = 0b00101000101;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29582,36 +28122,17 @@ let BaseOpcode = "V6_vS32b_ai";
 let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 3;
 }
-def V6_vS32b_new_pred_ai_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
-"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
-tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b01000;
-let Inst{31-21} = 0b00101000101;
-let isPredicated = 1;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 3;
-}
 def V6_vS32b_new_pred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
 "if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b01000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001101;
 let isPredicated = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29621,37 +28142,16 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_new_pred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
-"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b01000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001101;
-let isPredicated = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 4;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_new_pred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
 "if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{10-3} = 0b00001000;
 let Inst{31-21} = 0b00101011101;
 let isPredicated = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29661,222 +28161,106 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_new_pred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8),
-"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{10-3} = 0b00001000;
-let Inst{31-21} = 0b00101011101;
-let isPredicated = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ppu_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 4;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_npred_ai : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
-tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b001;
 let Inst{31-21} = 0b00101000101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_ai";
 let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vS32b_npred_ai_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
-tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b001;
-let Inst{31-21} = 0b00101000101;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vS32b_npred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_pi";
 let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_npred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001101;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_npred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{10-5} = 0b000001;
 let Inst{31-21} = 0b00101011101;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_ppu";
 let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_npred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
-"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{10-5} = 0b000001;
-let Inst{31-21} = 0b00101011101;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ppu_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nqpred_ai : HInst<
 (outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
-"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
-tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{31-21} = 0b00101000100;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vS32b_nqpred_ai_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
-tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> {
+tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{31-21} = 0b00101000100;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vS32b_nqpred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
-"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001100;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vS32b_nqpred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> {
+tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001100;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vS32b_nqpred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> {
+tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
 let Inst{10-5} = 0b000001;
 let Inst{31-21} = 0b00101011100;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nqpred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
-"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> {
-let Inst{10-5} = 0b000001;
-let Inst{31-21} = 0b00101011100;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_ai : HInst<
 (outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "vmem($Rt32+#$Ii):nt = $Vs32",
-tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b000;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000011;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_ai";
@@ -29884,34 +28268,16 @@ let isNVStorable = 1;
 let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vS32b_nt_ai_128B : HInst<
-(outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
-"vmem($Rt32+#$Ii):nt = $Vs32",
-tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b000;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000011;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let isNVStorable = 1;
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vS32b_nt_new_ai : HInst<
 (outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
 "vmem($Rt32+#$Ii):nt = $Os8.new",
-tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b00100;
 let Inst{12-11} = 0b00;
 let Inst{31-21} = 0b00101000011;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29922,38 +28288,17 @@ let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 2;
 }
-def V6_vS32b_nt_new_ai_128B : HInst<
-(outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
-"vmem($Rt32+#$Ii):nt = $Os8.new",
-tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b00100;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000011;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 2;
-}
 def V6_vS32b_nt_new_npred_ai : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
 "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
-tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b01111;
 let Inst{31-21} = 0b00101000111;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -29963,39 +28308,18 @@ let BaseOpcode = "V6_vS32b_ai";
 let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 3;
 }
-def V6_vS32b_nt_new_npred_ai_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
-"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
-tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b01111;
-let Inst{31-21} = 0b00101000111;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 3;
-}
 def V6_vS32b_nt_new_npred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
 "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b01111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001111;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -30006,40 +28330,17 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_new_npred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
-"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b01111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001111;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 4;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_new_npred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
 "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{10-3} = 0b00001111;
 let Inst{31-21} = 0b00101011111;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -30050,38 +28351,16 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_new_npred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8),
-"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{10-3} = 0b00001111;
-let Inst{31-21} = 0b00101011111;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ppu_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 4;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_new_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
 "vmem($Rx32++#$Ii):nt = $Os8.new",
-tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b00100;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001011;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -30093,37 +28372,15 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 3;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_new_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
-"vmem($Rx32++#$Ii):nt = $Os8.new",
-tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b00100;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001011;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 3;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_new_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8),
+(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
 "vmem($Rx32++$Mu2):nt = $Os8.new",
-tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{12-3} = 0b0000000100;
 let Inst{31-21} = 0b00101011011;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -30135,37 +28392,16 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 3;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_new_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8),
-"vmem($Rx32++$Mu2):nt = $Os8.new",
-tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{12-3} = 0b0000000100;
-let Inst{31-21} = 0b00101011011;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ppu_128B";
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 3;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_new_pred_ai : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
 "if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
-tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b01010;
 let Inst{31-21} = 0b00101000111;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -30175,37 +28411,17 @@ let BaseOpcode = "V6_vS32b_ai";
 let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 3;
 }
-def V6_vS32b_nt_new_pred_ai_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
-"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
-tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b01010;
-let Inst{31-21} = 0b00101000111;
-let isPredicated = 1;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 3;
-}
 def V6_vS32b_nt_new_pred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
 "if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-3} = 0b01010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001111;
 let isPredicated = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -30216,38 +28432,16 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_new_pred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
-"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-3} = 0b01010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001111;
-let isPredicated = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 4;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_new_pred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
 "if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{10-3} = 0b00001010;
 let Inst{31-21} = 0b00101011111;
 let isPredicated = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNVStore = 1;
 let CVINew = 1;
 let isNewValue = 1;
@@ -30258,74 +28452,35 @@ let DecoderNamespace = "EXT_mmvec";
 let opNewValue = 4;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_new_pred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8),
-"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
-tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{10-3} = 0b00001010;
-let Inst{31-21} = 0b00101011111;
-let isPredicated = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNVStore = 1;
-let CVINew = 1;
-let isNewValue = 1;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ppu_128B";
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let opNewValue = 4;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_npred_ai : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
-tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b001;
 let Inst{31-21} = 0b00101000111;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_ai";
 let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vS32b_nt_npred_ai_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
-tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b001;
-let Inst{31-21} = 0b00101000111;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vS32b_nt_npred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001111;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_pi";
@@ -30333,37 +28488,17 @@ let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_npred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001111;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_npred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{10-5} = 0b000001;
 let Inst{31-21} = 0b00101011111;
 let isPredicated = 1;
 let isPredicatedFalse = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_ppu";
@@ -30371,122 +28506,58 @@ let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_npred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
-"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{10-5} = 0b000001;
-let Inst{31-21} = 0b00101011111;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ppu_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_nqpred_ai : HInst<
 (outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
-"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
-tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{31-21} = 0b00101000110;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vS32b_nt_nqpred_ai_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
-tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> {
+tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{31-21} = 0b00101000110;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vS32b_nt_nqpred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
-"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001110;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vS32b_nt_nqpred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> {
+tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001110;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vS32b_nt_nqpred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
-"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> {
-let Inst{10-5} = 0b000001;
-let Inst{31-21} = 0b00101011110;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vS32b_nt_nqpred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> {
+tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
 let Inst{10-5} = 0b000001;
 let Inst{31-21} = 0b00101011110;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vS32b_nt_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "vmem($Rx32++#$Ii):nt = $Vs32",
-tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b000;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001011;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_pi";
@@ -30495,34 +28566,15 @@ let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
-"vmem($Rx32++#$Ii):nt = $Vs32",
-tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b000;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001011;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let isNVStorable = 1;
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
+(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "vmem($Rx32++$Mu2):nt = $Vs32",
-tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b00101011011;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_ppu";
@@ -30531,68 +28583,33 @@ let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
-"vmem($Rx32++$Mu2):nt = $Vs32",
-tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{12-5} = 0b00000000;
-let Inst{31-21} = 0b00101011011;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ppu_128B";
-let isNVStorable = 1;
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_pred_ai : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
-tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b000;
 let Inst{31-21} = 0b00101000111;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_ai";
 let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vS32b_nt_pred_ai_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
-tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b000;
-let Inst{31-21} = 0b00101000111;
-let isPredicated = 1;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vS32b_nt_pred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001111;
 let isPredicated = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_pi";
@@ -30600,35 +28617,16 @@ let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_pred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001111;
-let isPredicated = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_pred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{10-5} = 0b000000;
 let Inst{31-21} = 0b00101011111;
 let isPredicated = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_ppu";
@@ -30636,121 +28634,58 @@ let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_nt_pred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
-"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{10-5} = 0b000000;
-let Inst{31-21} = 0b00101011111;
-let isPredicated = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ppu_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_nt_qpred_ai : HInst<
 (outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
-"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
-tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{31-21} = 0b00101000110;
-let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vS32b_nt_qpred_ai_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
-tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> {
+tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{31-21} = 0b00101000110;
 let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vS32b_nt_qpred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
-"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001110;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vS32b_nt_qpred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> {
+tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001110;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vS32b_nt_qpred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
-"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> {
-let Inst{10-5} = 0b000000;
-let Inst{31-21} = 0b00101011110;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let isNonTemporal = 1;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vS32b_nt_qpred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> {
+tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
 let Inst{10-5} = 0b000000;
 let Inst{31-21} = 0b00101011110;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let isNonTemporal = 1;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vS32b_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "vmem($Rx32++#$Ii) = $Vs32",
-tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b000;
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b00101001001;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_pi";
 let isNVStorable = 1;
@@ -30758,478 +28693,317 @@ let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
-"vmem($Rx32++#$Ii) = $Vs32",
-tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b000;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001001;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let isNVStorable = 1;
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
-"vmem($Rx32++$Mu2) = $Vs32",
-tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{12-5} = 0b00000000;
-let Inst{31-21} = 0b00101011001;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let mayStore = 1;
-let isNVStorable = 1;
-let isPredicable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vS32b_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
+(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "vmem($Rx32++$Mu2) = $Vs32",
-tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{12-5} = 0b00000000;
 let Inst{31-21} = 0b00101011001;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let isNVStorable = 1;
 let isPredicable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vS32b_pred_ai : HInst<
 (outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
-tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
+tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b000;
 let Inst{31-21} = 0b00101000101;
 let isPredicated = 1;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_ai";
 let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vS32b_pred_ai_128B : HInst<
-(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
-tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel {
-let Inst{7-5} = 0b000;
-let Inst{31-21} = 0b00101000101;
-let isPredicated = 1;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_ai_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vS32b_pred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]> {
+tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001101;
 let isPredicated = 1;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let BaseOpcode = "V6_vS32b_pi";
 let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_pred_pi_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001101;
-let isPredicated = 1;
-let addrMode = PostInc;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let BaseOpcode = "V6_vS32b_pi_128B";
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32b_pred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
-"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]> {
-let Inst{10-5} = 0b000000;
-let Inst{31-21} = 0b00101011101;
-let isPredicated = 1;
-let addrMode = PostInc;
-let accessSize = Vector64Access;
-let mayStore = 1;
-let isNVStorable = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vS32b_pred_ppu_128B : HInst<
-(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
 "if ($Pv4) vmem($Rx32++$Mu2) = $Vs32",
-tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]> {
+tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
 let Inst{10-5} = 0b000000;
 let Inst{31-21} = 0b00101011101;
 let isPredicated = 1;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
+let BaseOpcode = "V6_vS32b_ppu";
 let isNVStorable = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
 def V6_vS32b_qpred_ai : HInst<
 (outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
 "if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
-tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> {
+tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{31-21} = 0b00101000100;
 let addrMode = BaseImmOffset;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vS32b_qpred_ai_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
-tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{31-21} = 0b00101000100;
-let addrMode = BaseImmOffset;
-let accessSize = Vector128Access;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vS32b_qpred_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
+(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
 "if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> {
+tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00101001100;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_qpred_pi_128B : HInst<
+def V6_vS32b_qpred_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
-"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00101001100;
+(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
+"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
+tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
+let Inst{10-5} = 0b000000;
+let Inst{31-21} = 0b00101011100;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_qpred_ppu : HInst<
+def V6_vS32b_srls_ai : HInst<
+(outs),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
+"vmem($Rt32+#$Ii):scatter_release",
+tc_29841470, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> {
+let Inst{7-0} = 0b00101000;
+let Inst{12-11} = 0b00;
+let Inst{31-21} = 0b00101000001;
+let addrMode = BaseImmOffset;
+let accessSize = HVXVectorAccess;
+let CVINew = 1;
+let mayStore = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vS32b_srls_pi : HInst<
 (outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32),
-"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> {
-let Inst{10-5} = 0b000000;
-let Inst{31-21} = 0b00101011100;
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
+"vmem($Rx32++#$Ii):scatter_release",
+tc_5c03dc63, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> {
+let Inst{7-0} = 0b00101000;
+let Inst{13-11} = 0b000;
+let Inst{31-21} = 0b00101001001;
 let addrMode = PostInc;
-let accessSize = Vector64Access;
+let accessSize = HVXVectorAccess;
+let CVINew = 1;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS32b_qpred_ppu_128B : HInst<
+def V6_vS32b_srls_ppu : HInst<
 (outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32),
-"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
-tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> {
-let Inst{10-5} = 0b000000;
-let Inst{31-21} = 0b00101011100;
+(ins IntRegs:$Rx32in, ModRegs:$Mu2),
+"vmem($Rx32++$Mu2):scatter_release",
+tc_5c03dc63, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> {
+let Inst{12-0} = 0b0000000101000;
+let Inst{31-21} = 0b00101011001;
 let addrMode = PostInc;
-let accessSize = Vector128Access;
+let accessSize = HVXVectorAccess;
+let CVINew = 1;
 let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vabsdiffh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
+def V6_vabsb : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
+"$Vd32.b = vabs($Vu32.b)",
+tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100110;
+let Inst{31-16} = 0b0001111000000001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vabsdiffh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100110;
+def V6_vabsb_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
+"$Vd32 = vabsb($Vu32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
+let isPseudo = 1;
 let isCodeGenOnly = 1;
+let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vabsdiffh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vabsdiffh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vabsb_sat : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
+"$Vd32.b = vabs($Vu32.b):sat",
+tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b101;
+let Inst{13-13} = 0b0;
+let Inst{31-16} = 0b0001111000000001;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vabsdiffh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vabsdiffh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vabsb_sat_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
+"$Vd32 = vabsb($Vu32):sat",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vabsdiffub : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
+def V6_vabsdiffh : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
+tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
+let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vabsdiffub_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+def V6_vabsdiffh_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32 = vabsdiffh($Vu32,$Vv32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
+let hasNewValue = 1;
+let opNewValue = 0;
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vabsdiffub : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vabsdiffub_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vabsdiffub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vabsdiffub_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vabsdiffub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vabsdiffuh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vabsdiffuh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vabsdiffuh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vabsdiffuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vabsdiffuh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vabsdiffuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vabsdiffw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vabsdiffw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vabsdiffw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vabsdiffw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vabsdiffw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vabsdiffw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vabsh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32.h = vabs($Vu32.h)",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vabsh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.h = vabs($Vu32.h)",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vabsh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vabsh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vabsh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
-"$Vd32 = vabsh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vabsh_sat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.h = vabs($Vu32.h):sat",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000000;
@@ -31237,239 +29011,147 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vabsh_sat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
-"$Vd32.h = vabs($Vu32.h):sat",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000000;
+def V6_vabsh_sat_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
+"$Vd32 = vabsh($Vu32):sat",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
+let isPseudo = 1;
 let isCodeGenOnly = 1;
+let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vabsh_sat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32 = vabsh($Vu32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vabsub_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
+"$Vd32.ub = vabs($Vu32.b)",
+tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vabsh_sat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
-"$Vd32 = vabsh($Vu32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vabsuh_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
+"$Vd32.uh = vabs($Vu32.h)",
+tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vabsw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32.w = vabs($Vu32.w)",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000000;
+def V6_vabsuw_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
+"$Vd32.uw = vabs($Vu32.w)",
+tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isPseudo = 1;
+let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vabsw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+def V6_vabsw : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.w = vabs($Vu32.w)",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vabsw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32 = vabsw($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vabsw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vabsw($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vabsw_sat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32.w = vabs($Vu32.w):sat",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vabsw_sat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.w = vabs($Vu32.w):sat",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vabsw_sat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32 = vabsw($Vu32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vabsw_sat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vabsw($Vu32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vadd($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vadd($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vaddb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vaddb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddb_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddb_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddb_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vaddb($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddb_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32 = vaddb($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddbnq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4) $Vx32.b += $Vu32.b",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000001;
@@ -31480,69 +29162,24 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vaddbnq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
-"if (!$Qv4) $Vx32.b += $Vu32.b",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000001;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vaddbnq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if (!$Qv4.b) $Vx32.b += $Vu32.b",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vaddbnq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4.b) $Vx32.b += $Vu32.b",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vaddbq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if ($Qv4) $Vx32.b += $Vu32.b",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000001;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vaddbq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4) $Vx32.b += $Vu32.b",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000001;
@@ -31551,14 +29188,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vaddbq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4.b) $Vx32.b += $Vu32.b",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -31567,73 +29203,34 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vaddbq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
-"if ($Qv4.b) $Vx32.b += $Vu32.b",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vaddbsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddbsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vadd($Vu32.b,$Vv32.b):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddbsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vaddb($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddbsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vaddb($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddbsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011110101;
@@ -31641,176 +29238,82 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddbsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011110101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddbsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vaddb($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddbsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vaddb($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddcarry : HInst<
-(outs VectorRegs:$Vd32, VecPredRegs:$Qx4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, VecPredRegs:$Qx4in),
-"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry",
-tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[HasV62T,UseHVX]> {
-let Inst{7-7} = 0b0;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vaddcarry_128B : HInst<
-(outs VectorRegs128B:$Vd32, VecPredRegs128B:$Qx4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, VecPredRegs128B:$Qx4in),
+(outs HvxVR:$Vd32, HvxQR:$Qx4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
 "$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry",
-tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[HasV62T,UseHVX]> {
+tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100101;
 let hasNewValue = 1;
 let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vaddclbh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011111000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddclbh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddclbw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011111000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddclbw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vadd($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vadd($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vaddh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vaddh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddh_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100011;
@@ -31818,62 +29321,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddh_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddh_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vaddh($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddh_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vaddh($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddhnq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if (!$Qv4) $Vx32.h += $Vu32.h",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000001;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vaddhnq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4) $Vx32.h += $Vu32.h",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000001;
@@ -31882,41 +29345,26 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vaddhnq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if (!$Qv4.h) $Vx32.h += $Vu32.h",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vaddhnq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4.h) $Vx32.h += $Vu32.h",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vaddhq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4) $Vx32.h += $Vu32.h",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000001;
@@ -31927,27 +29375,11 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vaddhq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
-"if ($Qv4) $Vx32.h += $Vu32.h",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000001;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vaddhq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4.h) $Vx32.h += $Vu32.h",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -31956,25 +29388,11 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vaddhq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
-"if ($Qv4.h) $Vx32.h += $Vu32.h",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vaddhsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vadd($Vu32.h,$Vv32.h):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100010;
@@ -31982,134 +29400,57 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddhsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddhsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vaddh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddhsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vaddh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddhsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddhsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddhsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vaddh($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddhsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32 = vaddh($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddhw : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32.w = vadd($Vu32.h,$Vv32.h)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddhw_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.w = vadd($Vu32.h,$Vv32.h)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddhw_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32.w += vadd($Vu32.h,$Vv32.h)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vaddhw_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32.w += vadd($Vu32.h,$Vv32.h)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100001;
@@ -32117,64 +29458,37 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vaddhw_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32 += vaddh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vaddhw_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32 += vaddh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vaddhw_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vaddh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddhw_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vaddh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddubh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100101;
@@ -32182,38 +29496,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddubh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddubh_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vaddubh_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100010;
@@ -32221,112 +29508,60 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vaddubh_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32 += vaddub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vaddubh_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32 += vaddub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vaddubh_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vaddub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddubh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vdd32 = vaddub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddubsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddubsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddubsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vaddub($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddubsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vaddub($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddubsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100011;
@@ -32334,72 +29569,34 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddubsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddubsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vaddub($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddubsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vaddub($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddububb_sat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011110101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddububb_sat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011110101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vadduhsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100010;
@@ -32407,120 +29604,57 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vadduhsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vadduhsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vadduh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vadduhsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vadduh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vadduhsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vadduhsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vadduhsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vadduh($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vadduhsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vadduh($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vadduhw : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vadduhw_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vadduhw_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100010;
@@ -32530,76 +29664,35 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vadduhw_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vadduhw_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32 += vadduh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vadduhw_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32 += vadduh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vadduhw_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vadduh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vadduhw_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vdd32 = vadduh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vadduwsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111011;
@@ -32607,47 +29700,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vadduwsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vadduwsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vadduw($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vadduwsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vadduw($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vadduwsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011110101;
@@ -32655,158 +29723,68 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vadduwsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011110101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vadduwsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vadduw($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vadduwsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32 = vadduw($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vadd($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vadd($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vaddw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vaddw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddw_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddw_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddw_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vaddw($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddw_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vaddw($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddwnq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if (!$Qv4) $Vx32.w += $Vu32.w",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000001;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vaddwnq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4) $Vx32.w += $Vu32.w",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000001;
@@ -32815,56 +29793,26 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vaddwnq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if (!$Qv4.w) $Vx32.w += $Vu32.w",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vaddwnq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4.w) $Vx32.w += $Vu32.w",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vaddwq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if ($Qv4) $Vx32.w += $Vu32.w",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000001;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vaddwq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4) $Vx32.w += $Vu32.w",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000001;
@@ -32873,14 +29821,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vaddwq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4.w) $Vx32.w += $Vu32.w",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -32889,73 +29836,34 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vaddwq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
-"if ($Qv4.w) $Vx32.w += $Vu32.w",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vaddwsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddwsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vadd($Vu32.w,$Vv32.w):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddwsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vaddw($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddwsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vaddw($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaddwsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100100;
@@ -32963,47 +29871,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaddwsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaddwsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vaddw($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaddwsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vaddw($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_valignb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32 = valign($Vu32,$Vv32,$Rt8)",
-tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
+tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011011;
@@ -33011,111 +29894,46 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_valignb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32 = valign($Vu32,$Vv32,$Rt8)",
-tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_valignbi : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
 "$Vd32 = valign($Vu32,$Vv32,#$Ii)",
-tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV60T,UseHVX]> {
+tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011110001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_valignbi_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii),
-"$Vd32 = valign($Vu32,$Vv32,#$Ii)",
-tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV60T,UseHVX]> {
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011110001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vand : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vand($Vu32,$Vv32)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vand_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vand($Vu32,$Vv32)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vandnqrt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecPredRegs:$Qu4, IntRegs:$Rt32),
-"$Vd32 = vand(!$Qu4,$Rt32)",
-tc_e231aa4f, TypeCVI_VX>, Enc_7b7ba8, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-10} = 0b0001;
-let Inst{31-21} = 0b00011001101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vandnqrt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxQR:$Qu4, IntRegs:$Rt32),
 "$Vd32 = vand(!$Qu4,$Rt32)",
-tc_e231aa4f, TypeCVI_VX>, Enc_7b7ba8, Requires<[HasV62T,UseHVX]> {
+tc_e231aa4f, TypeCVI_VX>, Enc_7b7ba8, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b101;
 let Inst{13-10} = 0b0001;
 let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vandnqrt_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32),
-"$Vx32 |= vand(!$Qu4,$Rt32)",
-tc_9311da3f, TypeCVI_VX>, Enc_895bd9, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-10} = 0b1001;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vandnqrt_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
 "$Vx32 |= vand(!$Qu4,$Rt32)",
-tc_9311da3f, TypeCVI_VX>, Enc_895bd9, Requires<[HasV62T,UseHVX]> {
+tc_9311da3f, TypeCVI_VX>, Enc_895bd9, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b011;
 let Inst{13-10} = 0b1001;
 let Inst{31-21} = 0b00011001011;
@@ -33123,103 +29941,49 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vandnqrt_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32),
-"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vandnqrt_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
 "$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vandnqrt_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecPredRegs:$Qu4, IntRegs:$Rt32),
-"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vandnqrt_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxQR:$Qu4, IntRegs:$Rt32),
 "$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vandqrt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecPredRegs:$Qu4, IntRegs:$Rt32),
-"$Vd32 = vand($Qu4,$Rt32)",
-tc_e231aa4f, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-10} = 0b0000;
-let Inst{31-21} = 0b00011001101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vandqrt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxQR:$Qu4, IntRegs:$Rt32),
 "$Vd32 = vand($Qu4,$Rt32)",
-tc_e231aa4f, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[HasV60T,UseHVX]> {
+tc_e231aa4f, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-10} = 0b0000;
 let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vandqrt_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32),
-"$Vx32 |= vand($Qu4,$Rt32)",
-tc_9311da3f, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-10} = 0b1000;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vandqrt_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
 "$Vx32 |= vand($Qu4,$Rt32)",
-tc_9311da3f, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[HasV60T,UseHVX]> {
+tc_9311da3f, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-10} = 0b1000;
 let Inst{31-21} = 0b00011001011;
@@ -33227,14 +29991,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vandqrt_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
 "$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -33243,61 +30006,22 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vandqrt_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32),
-"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vandqrt_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecPredRegs:$Qu4, IntRegs:$Rt32),
-"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vandqrt_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxQR:$Qu4, IntRegs:$Rt32),
 "$Vd32.ub = vand($Qu4.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vandvnqv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vu32),
-"$Vd32 = vand(!$Qv4,$Vu32)",
-tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000011;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vandvnqv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxQR:$Qv4, HvxVR:$Vu32),
 "$Vd32 = vand(!$Qv4,$Vu32)",
-tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000011;
@@ -33305,13 +30029,12 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vandvqv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxQR:$Qv4, HvxVR:$Vu32),
 "$Vd32 = vand($Qv4,$Vu32)",
-tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000011;
@@ -33320,129 +30043,57 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vandvqv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vu32),
-"$Vd32 = vand($Qv4,$Vu32)",
-tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000011;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vandvrt : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Qd4 = vand($Vu32,$Rt32)",
-tc_e231aa4f, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b010010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vandvrt_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Qd4 = vand($Vu32,$Rt32)",
-tc_e231aa4f, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[HasV60T,UseHVX]> {
+tc_e231aa4f, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b010010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vandvrt_acc : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Qx4 |= vand($Vu32,$Rt32)",
-tc_9311da3f, TypeCVI_VX_LATE>, Enc_adf111, Requires<[HasV60T,UseHVX]> {
+tc_9311da3f, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b100000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_vandvrt_acc_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Qx4 |= vand($Vu32,$Rt32)",
-tc_9311da3f, TypeCVI_VX_LATE>, Enc_adf111, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b100000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_vandvrt_acc_alt : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vandvrt_acc_alt_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vandvrt_alt : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vandvrt_alt_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Qd4.ub = vand($Vu32.ub,$Rt32.ub)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaslh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.h = vasl($Vu32.h,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001100;
@@ -33450,120 +30101,84 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaslh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32.h = vasl($Vu32.h,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001100;
+def V6_vaslh_acc : HInst<
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
+"$Vx32.h += vasl($Vu32.h,$Rt32)",
+tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b101;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
+let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vaslh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vaslh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vaslh_acc_alt : HInst<
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
+"$Vx32 += vaslh($Vu32,$Rt32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vaslh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+def V6_vaslh_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vaslh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaslhv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vasl($Vu32.h,$Vv32.h)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaslhv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vasl($Vu32.h,$Vv32.h)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaslhv_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vaslh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaslhv_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vaslh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaslw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.w = vasl($Vu32.w,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaslw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.w = vasl($Vu32.w,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vaslw_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.w += vasl($Vu32.w,$Rt32)",
-tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001011;
@@ -33573,76 +30188,35 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vaslw_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32.w += vasl($Vu32.w,$Rt32)",
-tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vaslw_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vaslw($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vaslw_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vaslw($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vaslw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vaslw($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaslw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vaslw($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaslwv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vasl($Vu32.w,$Vv32.w)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111101;
@@ -33650,47 +30224,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vaslwv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.w = vasl($Vu32.w,$Vv32.w)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vaslwv_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vaslw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vaslwv_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vaslw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.h = vasr($Vu32.h,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001011;
@@ -33698,70 +30247,59 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vasrh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32.h = vasr($Vu32.h,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001011;
+def V6_vasrh_acc : HInst<
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
+"$Vx32.h += vasr($Vu32.h,$Rt32)",
+tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b111;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011001100;
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
+let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vasrh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vasrh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vasrh_acc_alt : HInst<
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
+"$Vx32 += vasrh($Vu32,$Rt32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vasrh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+def V6_vasrh_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vasrh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrhbrndsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrhbrndsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-24} = 0b00011011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrhbrndsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat",
 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
 let hasNewValue = 1;
@@ -33770,58 +30308,32 @@ let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
 def V6_vasrhbsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrhbsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> {
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrhubrndsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrhubrndsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrhubrndsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat",
 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
 let hasNewValue = 1;
@@ -33830,33 +30342,20 @@ let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
 def V6_vasrhubsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrhubsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrhubsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat",
 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
 let hasNewValue = 1;
@@ -33865,108 +30364,93 @@ let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
 def V6_vasrhv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vasr($Vu32.h,$Vv32.h)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrhv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vasr($Vu32.h,$Vv32.h)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrhv_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vasrh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vasrhv_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vasrh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vasruhubrndsat : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
+"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat",
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b111;
+let Inst{13-13} = 0b0;
+let Inst{31-24} = 0b00011000;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vasruwuhrndsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
+def V6_vasruhubsat : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
+"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat",
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b101;
+let Inst{13-13} = 0b1;
 let Inst{31-24} = 0b00011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vasruwuhrndsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+def V6_vasruwuhrndsat : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> {
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vasrw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.w = vasr($Vu32.w,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001011;
+def V6_vasruwuhsat : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
+"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat",
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b100;
+let Inst{13-13} = 0b1;
+let Inst{31-24} = 0b00011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vasrw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+def V6_vasrw : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.w = vasr($Vu32.w,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrw_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.w += vasr($Vu32.w,$Rt32)",
-tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001011;
@@ -33976,76 +30460,35 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vasrw_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32.w += vasr($Vu32.w,$Rt32)",
-tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vasrw_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vasrw($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vasrw_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vasrw($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vasrw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vasrw($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vasrw($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrwh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011011;
@@ -34053,22 +30496,9 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vasrwh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vasrwh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)",
 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
 let hasNewValue = 1;
@@ -34077,33 +30507,20 @@ let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
 def V6_vasrwhrndsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrwhrndsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrwhrndsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat",
 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
 let hasNewValue = 1;
@@ -34112,10 +30529,10 @@ let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
 def V6_vasrwhsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011011;
@@ -34123,22 +30540,9 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vasrwhsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vasrwhsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat",
 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
 let hasNewValue = 1;
@@ -34147,58 +30551,32 @@ let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
 def V6_vasrwuhrndsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrwuhrndsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> {
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrwuhsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrwuhsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
-tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
+tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrwuhsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat",
 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> {
 let hasNewValue = 1;
@@ -34207,58 +30585,33 @@ let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
 def V6_vasrwv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vasr($Vu32.w,$Vv32.w)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrwv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vasr($Vu32.w,$Vv32.w)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vasrwv_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vasrw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vasrwv_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vasrw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vassign : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = $Vu32",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b1;
 let Inst{31-16} = 0b0001111000000011;
@@ -34266,237 +30619,159 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vassign_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
-"$Vd32 = $Vu32",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
+def V6_vassignp : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32),
+"$Vdd32 = $Vuu32",
+CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> {
+let hasNewValue = 1;
+let opNewValue = 0;
+let isPseudo = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vavgb : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32.b = vavg($Vu32.b,$Vv32.b)",
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b1;
-let Inst{31-16} = 0b0001111000000011;
+let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vassignp : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32),
-"$Vdd32 = $Vuu32",
-CVI_VA, TypeCVI_VA_DV>, Requires<[HasV60T,UseHVX]> {
+def V6_vavgb_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32 = vavgb($Vu32,$Vv32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
+let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vassignp_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32),
-"$Vdd32 = $Vuu32",
-CVI_VA, TypeCVI_VA_DV>, Requires<[HasV60T,UseHVX]> {
+def V6_vavgbrnd : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd",
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b101;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isPseudo = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vavgh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vavg($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100110;
+def V6_vavgbrnd_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32 = vavgb($Vu32,$Vv32):rnd",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isPseudo = 1;
+let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vavgh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+def V6_vavgh : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vavg($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vavgh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vavgh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vavgh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vavgh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vavghrnd : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vavghrnd_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vavghrnd_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vavgh($Vu32,$Vv32):rnd",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vavghrnd_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vavgh($Vu32,$Vv32):rnd",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vavgub : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vavgub_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vavgub_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vavgub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vavgub_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vavgub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vavgubrnd : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vavgubrnd_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vavgubrnd_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vavgub($Vu32,$Vv32):rnd",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vavgubrnd_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vavgub($Vu32,$Vv32):rnd",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vavguh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100110;
@@ -34504,204 +30779,137 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vavguh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vavguh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vavguh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vavguh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vavguh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vavguhrnd : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vavguhrnd_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vavguhrnd_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vavguh($Vu32,$Vv32):rnd",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vavguhrnd_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vavguh($Vu32,$Vv32):rnd",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vavguw : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)",
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b010;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011111000;
+let hasNewValue = 1;
+let opNewValue = 0;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vavguw_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32 = vavguw($Vu32,$Vv32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vavgw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vavg($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100110;
+def V6_vavguwrnd : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd",
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b011;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011111000;
+let hasNewValue = 1;
+let opNewValue = 0;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vavguwrnd_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32 = vavguw($Vu32,$Vv32):rnd",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isPseudo = 1;
+let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vavgw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+def V6_vavgw : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vavg($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vavgw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vavgw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vavgw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vavgw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vavgwrnd : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vavgwrnd_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vavgwrnd_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vavgw($Vu32,$Vv32):rnd",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vavgwrnd_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vavgw($Vu32,$Vv32):rnd",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vccombine : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins PredRegs:$Ps4, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
-tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[HasV60T,UseHVX]> {
-let Inst{7-7} = 0b0;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011010011;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vccombine_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins PredRegs:$Ps4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
 "if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
-tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[HasV60T,UseHVX]> {
+tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011010011;
@@ -34709,61 +30917,35 @@ let isPredicated = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vcl0h : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32.uh = vcl0($Vu32.uh)",
-tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vcl0h_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.uh = vcl0($Vu32.uh)",
-tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vcl0h_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32 = vcl0h($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vcl0h_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vcl0h($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vcl0w : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.uw = vcl0($Vu32.uw)",
-tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000010;
@@ -34771,47 +30953,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vcl0w_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
-"$Vd32.uw = vcl0($Vu32.uw)",
-tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vcl0w_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32 = vcl0w($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vcl0w_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vcl0w($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vcmov : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Ps4, VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins PredRegs:$Ps4, HvxVR:$Vu32),
 "if ($Ps4) $Vd32 = $Vu32",
-tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[HasV60T,UseHVX]> {
+tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001101000000000;
@@ -34820,38 +30977,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vcmov_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Ps4, VectorRegs128B:$Vu32),
-"if ($Ps4) $Vd32 = $Vu32",
-tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[HasV60T,UseHVX]> {
-let Inst{7-7} = 0b0;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001101000000000;
-let isPredicated = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vcombine : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vcombine($Vu32,$Vv32)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isRegSequence = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vcombine_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vcombine($Vu32,$Vv32)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111010;
@@ -34859,51 +30989,34 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isRegSequence = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vd0 : HInst<
-(outs VectorRegs:$Vd32),
+(outs HvxVR:$Vd32),
 (ins),
 "$Vd32 = #0",
-CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> {
+CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vd0_128B : HInst<
-(outs VectorRegs128B:$Vd32),
+def V6_vdd0 : HInst<
+(outs HvxWR:$Vdd32),
 (ins),
-"$Vd32 = #0",
-CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> {
+"$Vdd32 = #0",
+tc_8a6eb39a, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdeal : HInst<
-(outs VectorRegs:$Vy32, VectorRegs:$Vx32),
-(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32),
-"vdeal($Vy32,$Vx32,$Rt32)",
-tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
-}
-def V6_vdeal_128B : HInst<
-(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32),
+(outs HvxVR:$Vy32, HvxVR:$Vx32),
+(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
 "vdeal($Vy32,$Vx32,$Rt32)",
-tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[HasV60T,UseHVX]> {
+tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001111;
@@ -34912,14 +31025,13 @@ let opNewValue = 0;
 let hasNewValue2 = 1;
 let opNewValue2 = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
 }
 def V6_vdealb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.b = vdeal($Vu32.b)",
-tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000000;
@@ -34928,217 +31040,103 @@ let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
 def V6_vdealb4w : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vdeale($Vu32.b,$Vv32.b)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdealb4w_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vdeale($Vu32.b,$Vv32.b)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdealb4w_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vdealb4w($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdealb4w_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vdealb4w($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
-def V6_vdealb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
-"$Vd32.b = vdeal($Vu32.b)",
-tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdealb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32 = vdealb($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdealb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vdealb($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdealh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32.h = vdeal($Vu32.h)",
-tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdealh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.h = vdeal($Vu32.h)",
-tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdealh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vdealh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vdealh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
-"$Vd32 = vdealh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vdealvdd : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)",
-tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b1;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdealvdd_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)",
-tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> {
+tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b1;
 let Inst{31-24} = 0b00011011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdelta : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vdelta($Vu32,$Vv32)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdelta_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vdelta($Vu32,$Vv32)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpybus : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpybus_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpybus_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001000;
@@ -35148,26 +31146,11 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vdmpybus_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vdmpybus_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vdmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -35176,48 +31159,22 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vdmpybus_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vdmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vdmpybus_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vdmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vdmpybus_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vdmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vdmpybus_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001000;
@@ -35225,38 +31182,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vdmpybus_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vdmpybus_dv_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vdmpybus_dv_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001000;
@@ -35264,103 +31194,49 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vdmpybus_dv_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vxx32 += vdmpybus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vdmpybus_dv_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32 += vdmpybus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vdmpybus_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32 = vdmpybus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpybus_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32 = vdmpybus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpyhb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpyhb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.w = vdmpy($Vu32.h,$Rt32.b)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpyhb_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vdmpyhb_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.w += vdmpy($Vu32.h,$Rt32.b)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001000;
@@ -35368,14 +31244,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vdmpyhb_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vdmpyhb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -35384,87 +31259,34 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vdmpyhb_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vdmpyhb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vdmpyhb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vdmpyhb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpyhb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vdmpyhb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpyhb_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpyhb_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpyhb_dv_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vdmpyhb_dv_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001001;
@@ -35472,14 +31294,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vdmpyhb_dv_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32 += vdmpyhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -35488,48 +31309,22 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vdmpyhb_dv_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vxx32 += vdmpyhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vdmpyhb_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32 = vdmpyhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vdmpyhb_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vdd32 = vdmpyhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vdmpyhisat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001001;
@@ -35537,38 +31332,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vdmpyhisat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vdmpyhisat_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vdmpyhisat_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001001;
@@ -35576,89 +31344,49 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vdmpyhisat_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vx32 += vdmpyh($Vuu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vdmpyhisat_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vx32 += vdmpyh($Vuu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vdmpyhisat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vd32 = vdmpyh($Vuu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpyhisat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vd32 = vdmpyh($Vuu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpyhsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpyhsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpyhsat_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001001;
@@ -35668,76 +31396,35 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vdmpyhsat_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vdmpyhsat_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vdmpyh($Vu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vdmpyhsat_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vdmpyh($Vu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vdmpyhsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vdmpyh($Vu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpyhsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vdmpyh($Vu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpyhsuisat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001001;
@@ -35745,38 +31432,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vdmpyhsuisat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vdmpyhsuisat_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vdmpyhsuisat_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001001;
@@ -35784,89 +31444,49 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vdmpyhsuisat_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vdmpyhsuisat_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vdmpyhsuisat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vdmpyhsuisat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vdmpyhsusat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpyhsusat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpyhsusat_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001001;
@@ -35876,115 +31496,47 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vdmpyhsusat_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vdmpyhsusat_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vdmpyhsusat_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vdmpyhsu($Vu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vdmpyhsusat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpyhsusat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vdmpyhsu($Vu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpyhvsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdmpyhvsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vdmpyhvsat_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vdmpyhvsat_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100000;
@@ -35992,64 +31544,37 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vdmpyhvsat_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32 += vdmpyh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vdmpyhvsat_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32 += vdmpyh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vdmpyhvsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vdmpyh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vdmpyhvsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vdmpyh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vdsaduh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001000;
@@ -36057,24 +31582,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vdsaduh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vdsaduh_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001011;
@@ -36084,616 +31596,361 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vdsaduh_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vdsaduh_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vxx32 += vdsaduh($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vdsaduh_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32 += vdsaduh($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vdsaduh_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32 = vdsaduh($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vdsaduh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32 = vdsaduh($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_veqb : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_veqb_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_veqb_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_veqb_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_veqb_or : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b010000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_veqb_or_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b010000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_veqb_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b100000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_veqb_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b100000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_veqh : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_veqh_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_veqh_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_veqh_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_veqh_or : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b010001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_veqh_or_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b010001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_veqh_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b100001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_veqh_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b100001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_veqw : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_veqw_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_veqw_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_veqw_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_veqw_or : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b010010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_veqw_or_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b010010;
+def V6_veqw_xor : HInst<
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
+"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
+let Inst{7-2} = 0b100010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
+let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Qx4 = $Qx4in";
+}
+def V6_vgathermh : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
+"vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
+tc_66bb62ea, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
+let Inst{12-5} = 0b00001000;
+let Inst{31-21} = 0b00101111000;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isAccumulator = 1;
+let accessSize = HalfWordAccess;
+let isCVLoad = 1;
+let hasTmpDst = 1;
+let mayLoad = 1;
+let Defs = [VTMP];
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_veqw_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b100010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
+def V6_vgathermhq : HInst<
+(outs),
+(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
+"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
+tc_63e3d94c, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
+let Inst{12-7} = 0b001010;
+let Inst{31-21} = 0b00101111000;
 let hasNewValue = 1;
 let opNewValue = 0;
+let accessSize = HalfWordAccess;
+let isCVLoad = 1;
+let hasTmpDst = 1;
+let mayLoad = 1;
+let Defs = [VTMP];
 let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_veqw_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b100010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
+def V6_vgathermhw : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
+"vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
+tc_bfe309d5, TypeCVI_GATHER>, Enc_28dcbb, Requires<[UseHVXV65]> {
+let Inst{12-5} = 0b00010000;
+let Inst{31-21} = 0b00101111000;
 let hasNewValue = 1;
 let opNewValue = 0;
+let accessSize = HalfWordAccess;
+let isCVLoad = 1;
+let hasTmpDst = 1;
+let mayLoad = 1;
+let Defs = [VTMP];
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_vgtb : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111100;
+def V6_vgathermhwq : HInst<
+(outs),
+(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
+"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
+tc_98733e9d, TypeCVI_GATHER>, Enc_4e4a80, Requires<[UseHVXV65]> {
+let Inst{12-7} = 0b001100;
+let Inst{31-21} = 0b00101111000;
 let hasNewValue = 1;
 let opNewValue = 0;
+let accessSize = HalfWordAccess;
+let isCVLoad = 1;
+let hasTmpDst = 1;
+let mayLoad = 1;
+let Defs = [VTMP];
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vgtb_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111100;
+def V6_vgathermw : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
+"vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
+tc_66bb62ea, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
+let Inst{12-5} = 0b00000000;
+let Inst{31-21} = 0b00101111000;
 let hasNewValue = 1;
 let opNewValue = 0;
+let accessSize = WordAccess;
+let isCVLoad = 1;
+let hasTmpDst = 1;
+let mayLoad = 1;
+let Defs = [VTMP];
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vgtb_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000100;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
+def V6_vgathermwq : HInst<
+(outs),
+(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
+"if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
+tc_63e3d94c, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
+let Inst{12-7} = 0b001000;
+let Inst{31-21} = 0b00101111000;
 let hasNewValue = 1;
 let opNewValue = 0;
+let accessSize = WordAccess;
+let isCVLoad = 1;
+let hasTmpDst = 1;
+let mayLoad = 1;
+let Defs = [VTMP];
 let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_vgtb_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+def V6_vgtb : HInst<
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
+tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000100;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
+let Inst{13-13} = 0b0;
+let Inst{31-21} = 0b00011111100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_vgtb_or : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b010100;
+def V6_vgtb_and : HInst<
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
+"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
+let Inst{7-2} = 0b000100;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_vgtb_or_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+def V6_vgtb_or : HInst<
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b010100;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgtb_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b100100;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgtb_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b100100;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgth : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vgth_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vgth_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000101;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_vgth_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000101;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_vgth_or : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b010101;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgth_or_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b010101;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgth_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b100101;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgth_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b100101;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgtub : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b001000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111100;
@@ -36701,215 +31958,91 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vgtub_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b001000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vgtub_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b001000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_vgtub_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b001000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_vgtub_or : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b011000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_vgtub_or_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b011000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_vgtub_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b101000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgtub_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b101000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgtuh : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b001001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vgtuh_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b001001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vgtuh_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b001001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgtuh_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b001001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgtuh_or : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b011001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgtuh_or_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b011001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgtuh_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b101001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgtuh_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b101001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgtuw : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b001010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111100;
@@ -36917,328 +32050,145 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vgtuw_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b001010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vgtuw_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b001010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgtuw_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b001010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgtuw_or : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b011010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgtuw_or_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b011010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgtuw_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b101010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_vgtuw_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b101010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_vgtw : HInst<
-(outs VecPredRegs:$Qd4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vgtw_128B : HInst<
-(outs VecPredRegs128B:$Qd4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qd4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vgtw_and : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b000110;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Qx4 = $Qx4in";
 }
-def V6_vgtw_and_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b000110;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Qx4 = $Qx4in";
-}
 def V6_vgtw_or : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b010110;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgtw_or_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b010110;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vgtw_xor : HInst<
-(outs VecPredRegs:$Qx4),
-(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
-let Inst{7-2} = 0b100110;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vgtw_xor_128B : HInst<
-(outs VecPredRegs128B:$Qx4),
-(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxQR:$Qx4),
+(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)",
-tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
 let Inst{7-2} = 0b100110;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vhist : HInst<
 (outs),
 (ins),
 "vhist",
-tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV60T,UseHVX]> {
-let Inst{13-0} = 0b10000010000000;
-let Inst{31-16} = 0b0001111000000000;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vhist_128B : HInst<
-(outs),
-(ins),
-"vhist",
-tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV60T,UseHVX]> {
+tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> {
 let Inst{13-0} = 0b10000010000000;
 let Inst{31-16} = 0b0001111000000000;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vhistq : HInst<
 (outs),
-(ins VecPredRegs:$Qv4),
-"vhist($Qv4)",
-tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV60T,UseHVX]> {
-let Inst{13-0} = 0b10000010000000;
-let Inst{21-16} = 0b000010;
-let Inst{31-24} = 0b00011110;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vhistq_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4),
+(ins HvxQR:$Qv4),
 "vhist($Qv4)",
-tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV60T,UseHVX]> {
+tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> {
 let Inst{13-0} = 0b10000010000000;
 let Inst{21-16} = 0b000010;
 let Inst{31-24} = 0b00011110;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vinsertwr : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, IntRegs:$Rt32),
-"$Vx32.w = vinsert($Rt32)",
-tc_e231aa4f, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[HasV60T,UseHVX]> {
-let Inst{13-5} = 0b100000001;
-let Inst{31-21} = 0b00011001101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vinsertwr_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, IntRegs:$Rt32),
 "$Vx32.w = vinsert($Rt32)",
-tc_e231aa4f, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[HasV60T,UseHVX]> {
+tc_e231aa4f, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> {
 let Inst{13-5} = 0b100000001;
 let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vlalignb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)",
-tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vlalignb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32 = vlalign($Vu32,$Vv32,$Rt8)",
-tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
+tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vlalignbi : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
 "$Vd32 = vlalign($Vu32,$Vv32,#$Ii)",
-tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV60T,UseHVX]> {
+tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011110011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vlalignbi_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii),
-"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)",
-tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV60T,UseHVX]> {
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011110011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vlsrb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.ub = vlsr($Vu32.ub,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV62T,UseHVX]> {
+tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001100;
@@ -37246,72 +32196,34 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vlsrb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32.ub = vlsr($Vu32.ub,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vlsrh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.uh = vlsr($Vu32.uh,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vlsrh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.uh = vlsr($Vu32.uh,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vlsrh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vlsrh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vlsrh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vlsrh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vlsrhv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vlsr($Vu32.h,$Vv32.h)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111101;
@@ -37319,47 +32231,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vlsrhv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.h = vlsr($Vu32.h,$Vv32.h)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vlsrhv_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vlsrh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vlsrhv_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vlsrh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vlsrw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.uw = vlsr($Vu32.uw,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001100;
@@ -37367,159 +32254,81 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vlsrw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32.uw = vlsr($Vu32.uw,$Rt32)",
-tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vlsrw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vlsrw($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vlsrw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vlsrw($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vlsrwv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vlsr($Vu32.w,$Vv32.w)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vlsrwv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vlsr($Vu32.w,$Vv32.w)",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vlsrwv_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vlsrw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vlsrwv_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vlsrw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vlut4 : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)",
+tc_fa99dc24, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b100;
+let Inst{13-13} = 0b0;
+let Inst{31-21} = 0b00011001011;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vlutvvb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)",
-tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vlutvvb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)",
-tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> {
+tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-24} = 0b00011011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vlutvvb_nm : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch",
-tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vlutvvb_nm_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch",
-tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV62T,UseHVX]> {
+tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vlutvvb_oracc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)",
-tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_245865, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b1;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vlutvvb_oracc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)",
-tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_245865, Requires<[HasV60T,UseHVX]> {
+tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b1;
 let Inst{31-24} = 0b00011011;
@@ -37527,64 +32336,37 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vlutvvb_oracci : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii),
-"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)",
-tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_cd4705, Requires<[HasV62T,UseHVX]> {
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vlutvvb_oracci_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
 "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)",
-tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_cd4705, Requires<[HasV62T,UseHVX]> {
+tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> {
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vlutvvbi : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii),
-"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)",
-tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV62T,UseHVX]> {
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011110001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vlutvvbi_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
 "$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)",
-tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV62T,UseHVX]> {
+tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011110001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vlutvwh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)",
-tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> {
+tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b1;
 let Inst{31-24} = 0b00011011;
@@ -37592,63 +32374,23 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vlutvwh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
-"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)",
-tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b1;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vlutvwh_nm : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch",
-tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-24} = 0b00011000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vlutvwh_nm_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch",
-tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV62T,UseHVX]> {
+tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-24} = 0b00011000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vlutvwh_oracc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)",
-tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_7b523d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b1;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vlutvwh_oracc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)",
-tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_7b523d, Requires<[HasV60T,UseHVX]> {
+tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b1;
 let Inst{31-24} = 0b00011011;
@@ -37656,14 +32398,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vlutvwh_oracci : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
 "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)",
-tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_1178da, Requires<[HasV62T,UseHVX]> {
+tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> {
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100111;
 let hasNewValue = 1;
@@ -37672,48 +32413,22 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vlutvwh_oracci_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii),
-"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)",
-tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_1178da, Requires<[HasV62T,UseHVX]> {
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vlutvwhi : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii),
-"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)",
-tc_4e2a5159, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[HasV62T,UseHVX]> {
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011110011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vlutvwhi_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
 "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)",
-tc_4e2a5159, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[HasV62T,UseHVX]> {
+tc_4e2a5159, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> {
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011110011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmaxb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vmax($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111001;
@@ -37721,191 +32436,91 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmaxb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.b = vmax($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmaxb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmaxb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmaxb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vmaxb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmaxh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vmax($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmaxh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vmax($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmaxh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vmaxh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmaxh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmaxh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmaxub : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmaxub_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmaxub_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vmaxub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmaxub_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmaxub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmaxuh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmaxuh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmaxuh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmaxuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmaxuh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vmaxuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmaxw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vmax($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111001;
@@ -37913,191 +32528,91 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmaxw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.w = vmax($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmaxw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmaxw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmaxw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vmaxw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vminb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vmin($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vminb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vmin($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vminb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vminb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vminb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vminb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vminh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vmin($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vminh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vmin($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vminh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vminh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vminh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vminh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vminub : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vminub_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vminub_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vminub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vminub_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vminub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vminuh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111000;
@@ -38105,120 +32620,57 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vminuh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vminuh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vminuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vminuh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vminuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vminw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vmin($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vminw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vmin($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vminw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vminw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vminw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vminw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpabus : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpabus_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpabus_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001001;
@@ -38228,26 +32680,11 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpabus_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpabus_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32 += vmpabus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -38256,169 +32693,130 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpabus_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vxx32 += vmpabus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vmpabus_alt : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
+"$Vdd32 = vmpabus($Vuu32,$Rt32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
-let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpabus_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32 = vmpabus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vmpabusv : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
+"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
+let Inst{7-5} = 0b011;
+let Inst{13-13} = 0b0;
+let Inst{31-21} = 0b00011100001;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpabus_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vdd32 = vmpabus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vmpabusv_alt : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
+"$Vdd32 = vmpabus($Vuu32,$Vvv32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vmpabusv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+def V6_vmpabuu : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
+"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)",
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100001;
+let Inst{31-21} = 0b00011001011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpabusv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100001;
+def V6_vmpabuu_acc : HInst<
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
+"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)",
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b100;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
+let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpabusv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vmpabus($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vmpabuu_acc_alt : HInst<
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
+"$Vxx32 += vmpabuu($Vuu32,$Rt32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpabusv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32 = vmpabus($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vmpabuu_alt : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
+"$Vdd32 = vmpabuu($Vuu32,$Rt32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpabuuv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpabuuv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpabuuv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vmpabuu($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpabuuv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32 = vmpabuu($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpahb : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpahb_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpahb_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001001;
@@ -38428,115 +32826,60 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpahb_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpahb_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vxx32 += vmpahb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpahb_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32 += vmpahb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpahb_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32 = vmpahb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpahb_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32 = vmpahb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vmpauhb : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
+def V6_vmpahhsat : HInst<
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat",
+tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b100;
+let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpauhb_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+def V6_vmpauhb : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV62T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpauhb_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpauhb_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV62T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001100;
@@ -38544,89 +32887,75 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpauhb_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vxx32 += vmpauhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpauhb_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32 += vmpauhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpauhb_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32 = vmpauhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpauhb_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vdd32 = vmpauhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+def V6_vmpauhuhsat : HInst<
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
+tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b101;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011001100;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
+let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpybus : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001001;
+def V6_vmpsuhuhsat : HInst<
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
+tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b110;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011001100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpybus_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+def V6_vmpybus : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpybus_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001001;
@@ -38636,76 +32965,35 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpybus_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpybus_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vxx32 += vmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpybus_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vxx32 += vmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpybus_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vdd32 = vmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpybus_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vdd32 = vmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpybusv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100000;
@@ -38713,38 +33001,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpybusv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpybusv_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpybusv_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100000;
@@ -38752,14 +33013,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpybusv_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32 += vmpybus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -38768,87 +33028,34 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpybusv_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vxx32 += vmpybus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpybusv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vmpybus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpybusv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vdd32 = vmpybus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpybv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpybv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.h = vmpy($Vu32.b,$Vv32.b)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpybv_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpybv_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32.h += vmpy($Vu32.b,$Vv32.b)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100000;
@@ -38856,137 +33063,72 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpybv_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32 += vmpyb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpybv_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32 += vmpyb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpybv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vmpyb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpybv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vmpyb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyewuh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyewuh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vmpye($Vu32.w,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyewuh_64 : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011110101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyewuh_64_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vmpye($Vu32.w,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV62T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011110101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyewuh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vmpyewuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyewuh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmpyewuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vdd32.w = vmpy($Vu32.h,$Rt32.h)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001010;
@@ -38994,61 +33136,49 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpyh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001010;
+def V6_vmpyh_acc : HInst<
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
+"$Vxx32.w += vmpy($Vu32.h,$Rt32.h)",
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b110;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
+let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpyh_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vdd32 = vmpyh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vmpyh_acc_alt : HInst<
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
+"$Vxx32 += vmpyh($Vu32,$Rt32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpyh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+def V6_vmpyh_alt : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vdd32 = vmpyh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyhsat_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpyhsat_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001010;
@@ -39056,14 +33186,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpyhsat_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vxx32 += vmpyh($Vu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -39072,73 +33201,34 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpyhsat_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vxx32 += vmpyh($Vu32,$Rt32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpyhsrs : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyhsrs_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyhsrs_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpyhsrs_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpyhss : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001010;
@@ -39146,72 +33236,34 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpyhss_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpyhss_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyhss_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyhus : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyhus_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyhus_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100001;
@@ -39221,101 +33273,47 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpyhus_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpyhus_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32 += vmpyhus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpyhus_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32 += vmpyhus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpyhus_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vmpyhus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyhus_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vmpyhus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyhv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyhv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.w = vmpy($Vu32.h,$Vv32.h)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyhv_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32.w += vmpy($Vu32.h,$Vv32.h)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100000;
@@ -39325,149 +33323,70 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpyhv_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpyhv_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32 += vmpyh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpyhv_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32 += vmpyh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpyhv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vmpyh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyhv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vmpyh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyhvsrs : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyhvsrs_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyhvsrs_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpyhvsrs_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpyieoh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyieoh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyiewh_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32.w += vmpyie($Vu32.w,$Vv32.h)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100010;
@@ -39477,92 +33396,36 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpyiewh_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vmpyiewh_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32 += vmpyiewh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vmpyiewh_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32 += vmpyiewh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vmpyiewuh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyiewuh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyiewuh_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vmpyiewuh_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100001;
@@ -39570,103 +33433,49 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vmpyiewuh_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32 += vmpyiewuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vmpyiewuh_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32 += vmpyiewuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vmpyiewuh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vmpyiewuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyiewuh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmpyiewuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyih : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyih_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vmpyi($Vu32.h,$Vv32.h)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyih_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vmpyih_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32.h += vmpyi($Vu32.h,$Vv32.h)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100001;
@@ -39674,14 +33483,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vmpyih_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32 += vmpyih($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -39690,73 +33498,34 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpyih_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vx32 += vmpyih($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vmpyih_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vmpyih($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyih_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmpyih($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyihb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyihb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.h = vmpyi($Vu32.h,$Rt32.b)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyihb_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.h += vmpyi($Vu32.h,$Rt32.b)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001011;
@@ -39766,76 +33535,35 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpyihb_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vmpyihb_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vmpyihb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vmpyihb_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vmpyihb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vmpyihb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vmpyihb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpyihb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vmpyihb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpyiowh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vmpyio($Vu32.w,$Vv32.h)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111110;
@@ -39843,72 +33571,34 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpyiowh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpyiowh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vmpyiowh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyiowh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmpyiowh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyiwb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyiwb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.w = vmpyi($Vu32.w,$Rt32.b)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyiwb_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.w += vmpyi($Vu32.w,$Rt32.b)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001010;
@@ -39918,101 +33608,47 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpyiwb_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vmpyiwb_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vmpyiwb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vmpyiwb_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vmpyiwb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vmpyiwb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vmpyiwb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyiwb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vmpyiwb($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyiwh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyiwh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.w = vmpyi($Vu32.w,$Rt32.h)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyiwh_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.w += vmpyi($Vu32.w,$Rt32.h)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001010;
@@ -40022,101 +33658,47 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpyiwh_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vmpyiwh_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vmpyiwh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vmpyiwh_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vmpyiwh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vmpyiwh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vmpyiwh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyiwh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vmpyiwh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyiwub : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyiwub_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV62T,UseHVX]> {
+tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyiwub_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV62T,UseHVX]> {
+tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001100;
@@ -40126,26 +33708,11 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpyiwub_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vmpyiwub_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vmpyiwub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -40154,87 +33721,34 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpyiwub_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vmpyiwub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vmpyiwub_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vmpyiwub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpyiwub_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vmpyiwub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpyowh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyowh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyowh_64_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpyowh_64_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32 += vmpyo($Vu32.w,$Vv32.h)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100001;
@@ -40242,99 +33756,47 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpyowh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyowh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyowh_rnd : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyowh_rnd_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyowh_rnd_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyowh_rnd_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyowh_rnd_sacc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vmpyowh_rnd_sacc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100001;
@@ -40342,39 +33804,25 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vmpyowh_rnd_sacc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vmpyowh_rnd_sacc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vmpyowh_sacc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100001;
@@ -40384,76 +33832,35 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpyowh_sacc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vmpyowh_sacc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vmpyowh_sacc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vmpyub : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyub_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyub_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001100;
@@ -40463,76 +33870,35 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpyub_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpyub_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vxx32 += vmpyub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpyub_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vxx32 += vmpyub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpyub_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vdd32 = vmpyub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpyub_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vdd32 = vmpyub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpyubv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100000;
@@ -40540,24 +33906,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpyubv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vmpyubv_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100000;
@@ -40567,115 +33920,47 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpyubv_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpyubv_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32 += vmpyub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpyubv_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32 += vmpyub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpyubv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vmpyub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyubv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vmpyub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyuh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyuh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyuh_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpyuh_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001010;
@@ -40683,14 +33968,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpyuh_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vxx32 += vmpyuh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -40699,87 +33983,60 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpyuh_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vxx32 += vmpyuh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpyuh_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vdd32 = vmpyuh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmpyuh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vdd32 = vmpyuh($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vmpyuhe : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
+"$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)",
+tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b010;
+let Inst{13-13} = 0b0;
+let Inst{31-21} = 0b00011001011;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vmpyuhv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100001;
+def V6_vmpyuhe_acc : HInst<
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
+"$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)",
+tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b011;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011001100;
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vmpyuhv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+def V6_vmpyuhv : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmpyuhv_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vmpyuhv_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100001;
@@ -40787,14 +34044,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vmpyuhv_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vxx32 += vmpyuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -40803,48 +34059,22 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vmpyuhv_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vxx32 += vmpyuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vmpyuhv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vmpyuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vmpyuhv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vmpyuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vmux : HInst<
-(outs VectorRegs:$Vd32),
-(ins VecPredRegs:$Qt4, VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vmux($Qt4,$Vu32,$Vv32)",
-tc_a3127e12, TypeCVI_VA>, Enc_31db33, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011110111;
@@ -40852,182 +34082,103 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vmux_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VecPredRegs128B:$Qt4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vmux($Qt4,$Vu32,$Vv32)",
-tc_a3127e12, TypeCVI_VA>, Enc_31db33, Requires<[HasV60T,UseHVX]> {
-let Inst{7-7} = 0b0;
+def V6_vnavgb : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32.b = vnavg($Vu32.b,$Vv32.b)",
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011110111;
+let Inst{31-21} = 0b00011111000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vnavgh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vnavg($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100111;
+def V6_vnavgb_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
+"$Vd32 = vnavgb($Vu32,$Vv32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isPseudo = 1;
+let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vnavgh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+def V6_vnavgh : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vnavg($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vnavgh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vnavgh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vnavgh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vnavgh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vnavgub : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vnavgub_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vnavgub_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vnavgub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vnavgub_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vnavgub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vnavgw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vnavg($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vnavgw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vnavg($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vnavgw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vnavgw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vnavgw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vnavgw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vnccombine : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins PredRegs:$Ps4, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
-tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[HasV60T,UseHVX]> {
-let Inst{7-7} = 0b0;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011010010;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vnccombine_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins PredRegs:$Ps4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
 "if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
-tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[HasV60T,UseHVX]> {
+tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011010010;
@@ -41036,27 +34187,12 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vncmov : HInst<
-(outs VectorRegs:$Vd32),
-(ins PredRegs:$Ps4, VectorRegs:$Vu32),
-"if (!$Ps4) $Vd32 = $Vu32",
-tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[HasV60T,UseHVX]> {
-let Inst{7-7} = 0b0;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001101000100000;
-let isPredicated = 1;
-let isPredicatedFalse = 1;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vncmov_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Ps4, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins PredRegs:$Ps4, HvxVR:$Vu32),
 "if (!$Ps4) $Vd32 = $Vu32",
-tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[HasV60T,UseHVX]> {
+tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001101000100000;
@@ -41065,13 +34201,12 @@ let isPredicatedFalse = 1;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vnormamth : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.h = vnormamt($Vu32.h)",
-tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000011;
@@ -41079,95 +34214,45 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vnormamth_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
-"$Vd32.h = vnormamt($Vu32.h)",
-tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vnormamth_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32 = vnormamth($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vnormamth_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vnormamth($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vnormamtw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32.w = vnormamt($Vu32.w)",
-tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vnormamtw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.w = vnormamt($Vu32.w)",
-tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vnormamtw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32 = vnormamtw($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vnormamtw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vnormamtw($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vnot : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vnot($Vu32)",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000000;
@@ -41175,49 +34260,23 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vnot_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
-"$Vd32 = vnot($Vu32)",
-tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vor : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vor($Vu32,$Vv32)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vor_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vor($Vu32,$Vv32)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackeb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vpacke($Vu32.h,$Vv32.h)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111110;
@@ -41225,47 +34284,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vpackeb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.b = vpacke($Vu32.h,$Vv32.h)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vpackeb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vpackeb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vpackeb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vpackeb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vpackeh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vpacke($Vu32.w,$Vv32.w)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111110;
@@ -41273,383 +34307,219 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vpackeh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.h = vpacke($Vu32.w,$Vv32.w)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vpackeh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vpackeh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpackeh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vpackeh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackhb_sat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpackhb_sat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vpack($Vu32.h,$Vv32.h):sat",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackhb_sat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vpackhb($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpackhb_sat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vpackhb($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackhub_sat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpackhub_sat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackhub_sat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vpackhub($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpackhub_sat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vpackhub($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackob : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vpacko($Vu32.h,$Vv32.h)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpackob_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vpacko($Vu32.h,$Vv32.h)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackob_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vpackob($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vpackob_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vpackob($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vpackoh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vpacko($Vu32.w,$Vv32.w)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpackoh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vpacko($Vu32.w,$Vv32.w)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackoh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vpackoh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpackoh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vpackoh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackwh_sat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpackwh_sat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vpack($Vu32.w,$Vv32.w):sat",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackwh_sat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vpackwh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vpackwh_sat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vpackwh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vpackwuh_sat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpackwuh_sat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpackwuh_sat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vpackwuh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vpackwuh_sat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vpackwuh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vpopcounth : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32.h = vpopcount($Vu32.h)",
-tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vpopcounth_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.h = vpopcount($Vu32.h)",
-tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vpopcounth_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vpopcounth($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vpopcounth_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
-"$Vd32 = vpopcounth($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vprefixqb : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxQR:$Qv4),
+"$Vd32.b = prefixsum($Qv4)",
+tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
+let Inst{13-5} = 0b100000010;
+let Inst{21-16} = 0b000011;
+let Inst{31-24} = 0b00011110;
+let hasNewValue = 1;
+let opNewValue = 0;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vprefixqh : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxQR:$Qv4),
+"$Vd32.h = prefixsum($Qv4)",
+tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
+let Inst{13-5} = 0b100001010;
+let Inst{21-16} = 0b000011;
+let Inst{31-24} = 0b00011110;
+let hasNewValue = 1;
+let opNewValue = 0;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vprefixqw : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxQR:$Qv4),
+"$Vd32.w = prefixsum($Qv4)",
+tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
+let Inst{13-5} = 0b100010010;
+let Inst{21-16} = 0b000011;
+let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrdelta : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vrdelta($Vu32,$Vv32)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111001;
@@ -41657,63 +34527,73 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vrdelta_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vrdelta($Vu32,$Vv32)",
-tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
+def V6_vrmpybub_rtt : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
+tc_a807365d, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111001;
+let Inst{31-21} = 0b00011001110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
-def V6_vrmpybus : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001000;
+def V6_vrmpybub_rtt_acc : HInst<
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
+tc_ee927c0e, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b000;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vrmpybus_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001000;
+def V6_vrmpybub_rtt_acc_alt : HInst<
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
+let isPseudo = 1;
+let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Vxx32 = $Vxx32in";
+}
+def V6_vrmpybub_rtt_alt : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
+let hasNewValue = 1;
+let opNewValue = 0;
+let isPseudo = 1;
 let isCodeGenOnly = 1;
+let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vrmpybus_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b1;
+def V6_vrmpybus : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
+"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
+tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
+let Inst{7-5} = 0b100;
+let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001000;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vrmpybus_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+def V6_vrmpybus_acc : HInst<
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001000;
@@ -41721,14 +34601,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vrmpybus_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vrmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -41737,73 +34616,34 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vrmpybus_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vrmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vrmpybus_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vrmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrmpybus_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vrmpybus($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrmpybusi : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
-tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> {
-let Inst{7-6} = 0b10;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrmpybusi_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
-tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> {
+tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
 let Inst{7-6} = 0b10;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrmpybusi_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
-tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> {
+tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
 let Inst{7-6} = 0b10;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001010;
@@ -41813,76 +34653,35 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vrmpybusi_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
-tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-6} = 0b10;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vrmpybusi_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vrmpybusi_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vrmpybusi_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vrmpybusi_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vrmpybusv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100000;
@@ -41890,38 +34689,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vrmpybusv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vrmpybusv_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vrmpybusv_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100000;
@@ -41929,103 +34701,49 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vrmpybusv_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32 += vrmpybus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vrmpybusv_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32 += vrmpybus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vrmpybusv_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vrmpybus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrmpybusv_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vrmpybus($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrmpybv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrmpybv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vrmpy($Vu32.b,$Vv32.b)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrmpybv_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vrmpybv_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32.w += vrmpy($Vu32.b,$Vv32.b)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100000;
@@ -42033,103 +34751,49 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vrmpybv_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32 += vrmpyb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vrmpybv_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32 += vrmpyb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vrmpybv_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vrmpyb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vrmpybv_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vrmpyb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vrmpyub : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrmpyub_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)",
-tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrmpyub_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vrmpyub_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)",
-tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> {
+tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001000;
@@ -42137,14 +34801,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vrmpyub_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vx32 += vrmpyub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -42153,87 +34816,84 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vrmpyub_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vx32 += vrmpyub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vrmpyub_alt : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
+"$Vd32 = vrmpyub($Vu32,$Rt32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
-let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vrmpyub_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vrmpyub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vrmpyub_rtt : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
+tc_a807365d, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b100;
+let Inst{13-13} = 0b0;
+let Inst{31-21} = 0b00011001110;
 let hasNewValue = 1;
 let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vrmpyub_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vrmpyub($Vu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+def V6_vrmpyub_rtt_acc : HInst<
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
+tc_ee927c0e, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b111;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b00011001101;
+let hasNewValue = 1;
+let opNewValue = 0;
+let isAccumulator = 1;
+let DecoderNamespace = "EXT_mmvec";
+let Constraints = "$Vxx32 = $Vxx32in";
+}
+def V6_vrmpyub_rtt_acc_alt : HInst<
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
+let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vrmpyubi : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
-tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> {
-let Inst{7-6} = 0b11;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001101;
+def V6_vrmpyub_rtt_alt : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
+"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isPseudo = 1;
+let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vrmpyubi_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+def V6_vrmpyubi : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
-tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> {
+tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
 let Inst{7-6} = 0b11;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrmpyubi_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
-tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-6} = 0b11;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vrmpyubi_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
-tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> {
+tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
 let Inst{7-6} = 0b11;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001011;
@@ -42241,103 +34901,49 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vrmpyubi_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vrmpyubi_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vrmpyubi_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrmpyubi_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrmpyubv : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrmpyubv_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)",
-tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrmpyubv_acc : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vrmpyubv_acc_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)",
-tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> {
+tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100000;
@@ -42345,64 +34951,37 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vrmpyubv_acc_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vx32 += vrmpyub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vrmpyubv_acc_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vx32),
+(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vx32 += vrmpyub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vrmpyubv_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vrmpyub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrmpyubv_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vrmpyub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vror : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, IntRegs:$Rt32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, IntRegs:$Rt32),
 "$Vd32 = vror($Vu32,$Rt32)",
-tc_bf142ae2, TypeCVI_VP>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
+tc_bf142ae2, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001011;
@@ -42410,351 +34989,161 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vror_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, IntRegs:$Rt32),
-"$Vd32 = vror($Vu32,$Rt32)",
-tc_bf142ae2, TypeCVI_VP>, Enc_b087ac, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vroundhb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vround($Vu32.h,$Vv32.h):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vroundhb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vround($Vu32.h,$Vv32.h):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vroundhb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vroundhb($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vroundhb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vroundhb($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vroundhub : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vroundhub_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vround($Vu32.h,$Vv32.h):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vroundhub_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vroundhub($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vroundhub_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vroundhub($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vrounduhub : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrounduhub_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrounduhub_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vrounduhub($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vrounduhub_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vrounduhub($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vrounduwuh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrounduwuh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111111;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrounduwuh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vrounduwuh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrounduwuh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vrounduwuh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vroundwh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vround($Vu32.w,$Vv32.w):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vroundwh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vround($Vu32.w,$Vv32.w):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vroundwh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vroundwh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vroundwh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vroundwh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vroundwuh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vroundwuh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vround($Vu32.w,$Vv32.w):sat",
-tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vroundwuh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vroundwuh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vroundwuh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vroundwuh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrsadubi : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
-tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> {
-let Inst{7-6} = 0b11;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrsadubi_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
-tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> {
+tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
 let Inst{7-6} = 0b11;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vrsadubi_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
-tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-6} = 0b11;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vrsadubi_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
-tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> {
+tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
 let Inst{7-6} = 0b11;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001010;
@@ -42762,14 +35151,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vrsadubi_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -42778,144 +35166,68 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vrsadubi_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vrsadubi_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
-"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vrsadubi_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
 "$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsathub : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vsat($Vu32.h,$Vv32.h)",
-tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsathub_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vsat($Vu32.h,$Vv32.h)",
-tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsathub_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsathub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsathub_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vsathub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsatuwuh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsatuwuh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsatuwuh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsatuwuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsatuwuh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vsatuwuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsatwh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vsat($Vu32.w,$Vv32.w)",
-tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111011;
@@ -42923,206 +35235,277 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsatwh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.h = vsat($Vu32.w,$Vv32.w)",
-tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsatwh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vsatwh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsatwh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsatwh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsb : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
-"$Vdd32.h = vsxt($Vu32.b)",
-tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsb_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32.h = vsxt($Vu32.b)",
-tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
+tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsb_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32 = vsxtb($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsb_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
-"$Vdd32 = vsxtb($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+def V6_vscattermh : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
+tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b001;
+let Inst{31-21} = 0b00101111001;
+let accessSize = HalfWordAccess;
+let mayStore = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermh_add : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32",
+tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b101;
+let Inst{31-21} = 0b00101111001;
+let accessSize = HalfWordAccess;
+let isAccumulator = 1;
+let mayStore = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermh_add_alt : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
+let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermh_alt : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
+let isPseudo = 1;
 let isCodeGenOnly = 1;
+let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
-"$Vdd32.w = vsxt($Vu32.h)",
-tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000010;
-let hasNewValue = 1;
-let opNewValue = 0;
+def V6_vscattermhq : HInst<
+(outs),
+(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
+tc_df54ad52, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
+let Inst{7-7} = 0b1;
+let Inst{31-21} = 0b00101111100;
+let accessSize = HalfWordAccess;
+let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
-"$Vdd32.w = vsxt($Vu32.h)",
-tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
+def V6_vscattermhq_alt : HInst<
+(outs),
+(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermhw : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
+tc_ec58f88a, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b010;
+let Inst{31-21} = 0b00101111001;
+let accessSize = HalfWordAccess;
+let mayStore = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermhw_add : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32",
+tc_ec58f88a, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b110;
+let Inst{31-21} = 0b00101111001;
+let accessSize = HalfWordAccess;
+let isAccumulator = 1;
+let mayStore = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermhwq : HInst<
+(outs),
+(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
+"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
+tc_94f43c04, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> {
+let Inst{7-7} = 0b0;
+let Inst{31-21} = 0b00101111101;
+let accessSize = HalfWordAccess;
+let mayStore = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermw : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
+tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
+let Inst{7-5} = 0b000;
+let Inst{31-21} = 0b00101111001;
+let accessSize = WordAccess;
+let mayStore = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermw_add : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32",
+tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
 let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000010;
-let hasNewValue = 1;
-let opNewValue = 0;
+let Inst{31-21} = 0b00101111001;
+let accessSize = WordAccess;
+let isAccumulator = 1;
+let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermw_add_alt : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
+let isAccumulator = 1;
+let isPseudo = 1;
 let isCodeGenOnly = 1;
+let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsh_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
-"$Vdd32 = vsxth($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+def V6_vscattermw_alt : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
-"$Vdd32 = vsxth($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
+def V6_vscattermwh_add_alt : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
+let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermwh_alt : HInst<
+(outs),
+(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
+"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
+let isPseudo = 1;
 let isCodeGenOnly = 1;
+let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vshufeh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
+def V6_vscattermwhq_alt : HInst<
+(outs),
+(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
+"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermwq : HInst<
+(outs),
+(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
+tc_df54ad52, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
+let Inst{7-7} = 0b0;
+let Inst{31-21} = 0b00101111100;
+let accessSize = WordAccess;
+let mayStore = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vscattermwq_alt : HInst<
+(outs),
+(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
+"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vsh : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
+"$Vdd32.w = vsxt($Vu32.h)",
+tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
+let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111010;
+let Inst{31-16} = 0b0001111000000010;
+let hasNewValue = 1;
+let opNewValue = 0;
+let DecoderNamespace = "EXT_mmvec";
+}
+def V6_vsh_alt : HInst<
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
+"$Vdd32 = vsxth($Vu32)",
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
+let isPseudo = 1;
+let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vshufeh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+def V6_vshufeh : HInst<
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vshuffe($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshufeh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vshuffeh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshufeh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vshuffeh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshuff : HInst<
-(outs VectorRegs:$Vy32, VectorRegs:$Vx32),
-(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32),
-"vshuff($Vy32,$Vx32,$Rt32)",
-tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
-}
-def V6_vshuff_128B : HInst<
-(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32),
+(outs HvxVR:$Vy32, HvxVR:$Vx32),
+(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
 "vshuff($Vy32,$Vx32,$Rt32)",
-tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[HasV60T,UseHVX]> {
+tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001111;
@@ -43131,231 +35514,117 @@ let opNewValue = 0;
 let hasNewValue2 = 1;
 let opNewValue2 = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
 }
 def V6_vshuffb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32.b = vshuff($Vu32.b)",
-tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshuffb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.b = vshuff($Vu32.b)",
-tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshuffb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32 = vshuffb($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshuffb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vshuffb($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshuffeb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshuffeb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vshuffe($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshuffeb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vshuffeb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vshuffeb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vshuffeb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vshuffh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32.h = vshuff($Vu32.h)",
-tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshuffh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32.h = vshuff($Vu32.h)",
-tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> {
+tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshuffh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32),
-"$Vd32 = vshuffh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshuffh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32),
 "$Vd32 = vshuffh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshuffob : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshuffob_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vshuffo($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshuffob_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vshuffob($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vshuffob_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vshuffob($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vshuffvdd : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8),
-"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)",
-tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b1;
-let Inst{31-24} = 0b00011011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshuffvdd_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
 "$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)",
-tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> {
+tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b1;
 let Inst{31-24} = 0b00011011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshufoeb : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111010;
@@ -43363,47 +35632,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vshufoeb_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vshufoeb_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vshuffoeb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vshufoeb_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vdd32 = vshuffoeb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vshufoeh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111010;
@@ -43411,205 +35655,91 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vshufoeh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vshufoeh_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vshuffoeh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshufoeh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vshuffoeh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshufoh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshufoh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vshuffo($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vshufoh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vshuffoh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vshufoh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vshuffoh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubb : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.b = vsub($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubb_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vsub($Vu32.b,$Vv32.b)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubb_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vsubb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubb_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsubb($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubb_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubb_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubb_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vsubb($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsubb_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32 = vsubb($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsubbnq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if (!$Qv4) $Vx32.b -= $Vu32.b",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000010;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vsubbnq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4) $Vx32.b -= $Vu32.b",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000010;
@@ -43617,39 +35747,25 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vsubbnq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if (!$Qv4.b) $Vx32.b -= $Vu32.b",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vsubbnq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4.b) $Vx32.b -= $Vu32.b",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vsubbq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4) $Vx32.b -= $Vu32.b",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000001;
@@ -43659,51 +35775,23 @@ let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vsubbq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
-"if ($Qv4) $Vx32.b -= $Vu32.b",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000001;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vsubbq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if ($Qv4.b) $Vx32.b -= $Vu32.b",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vsubbq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4.b) $Vx32.b -= $Vu32.b",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vsubbsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.b = vsub($Vu32.b,$Vv32.b):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111001;
@@ -43711,222 +35799,104 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsubbsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsubbsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsubb($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsubbsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vsubb($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsubbsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011110101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubbsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011110101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubbsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vsubb($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubbsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vsubb($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubcarry : HInst<
-(outs VectorRegs:$Vd32, VecPredRegs:$Qx4),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32, VecPredRegs:$Qx4in),
-"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry",
-tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[HasV62T,UseHVX]> {
-let Inst{7-7} = 0b1;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011100101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Qx4 = $Qx4in";
-}
-def V6_vsubcarry_128B : HInst<
-(outs VectorRegs128B:$Vd32, VecPredRegs128B:$Qx4),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, VecPredRegs128B:$Qx4in),
+(outs HvxVR:$Vd32, HvxQR:$Qx4),
+(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
 "$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry",
-tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[HasV62T,UseHVX]> {
+tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
 let Inst{7-7} = 0b1;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011100101;
 let hasNewValue = 1;
 let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Qx4 = $Qx4in";
 }
 def V6_vsubh : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vsub($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubh_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vsub($Vu32.h,$Vv32.h)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubh_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vsubh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubh_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsubh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubh_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubh_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100100;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubh_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vsubh($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubh_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vsubh($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubhnq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4) $Vx32.h -= $Vu32.h",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000010;
@@ -43936,65 +35906,23 @@ let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vsubhnq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
-"if (!$Qv4) $Vx32.h -= $Vu32.h",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000010;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vsubhnq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if (!$Qv4.h) $Vx32.h -= $Vu32.h",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vsubhnq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4.h) $Vx32.h -= $Vu32.h",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vsubhq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if ($Qv4) $Vx32.h -= $Vu32.h",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000001;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vsubhq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4) $Vx32.h -= $Vu32.h",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000001;
@@ -44002,14 +35930,13 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vsubhq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4.h) $Vx32.h -= $Vu32.h",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -44017,264 +35944,126 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vsubhq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
-"if ($Qv4.h) $Vx32.h -= $Vu32.h",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vsubhsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubhsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.h = vsub($Vu32.h,$Vv32.h):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubhsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsubh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsubhsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vsubh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsubhsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubhsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubhsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vsubh($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubhsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vsubh($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubhw : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32.w = vsub($Vu32.h,$Vv32.h)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubhw_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.w = vsub($Vu32.h,$Vv32.h)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubhw_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vsubh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubhw_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vsubh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsububh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsububh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsububh_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vsubub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsububh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vsubub($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsububsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsububsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsububsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vsubub($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsububsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsubub($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsububsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100100;
@@ -44282,120 +36071,57 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsububsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsububsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vsubub($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsububsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vsubub($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubububb_sat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011110101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubububb_sat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011110101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubuhsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubuhsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubuhsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsubuh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsubuhsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vd32 = vsubuh($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsubuhsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100100;
@@ -44403,47 +36129,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsubuhsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsubuhsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vsubuh($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsubuhsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsubuhw : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
+tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b110;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100101;
@@ -44451,191 +36152,91 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsubuhw_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
-"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)",
-tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b110;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsubuhw_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vsubuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubuhw_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vsubuh($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubuwsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011111110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubuwsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011111110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubuwsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vsubuw($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubuwsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsubuw($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubuwsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011110101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubuwsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011110101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubuwsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubuwsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vsubuw($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubw : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vsub($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubw_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vsub($Vu32.w,$Vv32.w)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100010;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubw_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vsubw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubw_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsubw($Vu32,$Vv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubw_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b101;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100100;
@@ -44643,61 +36244,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vsubw_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
-"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b101;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100100;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vsubw_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vsubw($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubw_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vsubw($Vuu32,$Vvv32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubwnq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if (!$Qv4) $Vx32.w -= $Vu32.w",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000010;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vsubwnq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4) $Vx32.w -= $Vu32.w",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000010;
@@ -44705,14 +36267,13 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vsubwnq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if (!$Qv4.w) $Vx32.w -= $Vu32.w",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -44720,38 +36281,11 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vsubwnq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
-"if (!$Qv4.w) $Vx32.w -= $Vu32.w",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vsubwq : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
-"if ($Qv4) $Vx32.w -= $Vu32.w",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{21-16} = 0b000010;
-let Inst{31-24} = 0b00011110;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vx32 = $Vx32in";
-}
-def V6_vsubwq_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4) $Vx32.w -= $Vu32.w",
-tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> {
+tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{21-16} = 0b000010;
@@ -44759,14 +36293,13 @@ let Inst{31-24} = 0b00011110;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vx32 = $Vx32in";
 }
 def V6_vsubwq_alt : HInst<
-(outs VectorRegs:$Vx32),
-(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32),
+(outs HvxVR:$Vx32),
+(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
 "if ($Qv4.w) $Vx32.w -= $Vu32.w",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
@@ -44774,184 +36307,81 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vx32 = $Vx32in";
 }
-def V6_vsubwq_alt_128B : HInst<
-(outs VectorRegs128B:$Vx32),
-(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32),
-"if ($Qv4.w) $Vx32.w -= $Vu32.w",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vx32 = $Vx32in";
-}
 def V6_vsubwsat : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100011;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubwsat_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32.w = vsub($Vu32.w,$Vv32.w):sat",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100011;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubwsat_alt : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vsubw($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubwsat_alt_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vsubw($Vu32,$Vv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubwsat_dv : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubwsat_dv_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat",
-tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> {
+tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vsubwsat_dv_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32),
-"$Vdd32 = vsubw($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vsubwsat_dv_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
 "$Vdd32 = vsubw($Vuu32,$Vvv32):sat",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vswap : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecPredRegs:$Qt4, VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)",
-tc_316c637c, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[HasV60T,UseHVX]> {
-let Inst{7-7} = 0b0;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011110101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vswap_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecPredRegs128B:$Qt4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxWR:$Vdd32),
+(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vdd32 = vswap($Qt4,$Vu32,$Vv32)",
-tc_316c637c, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[HasV60T,UseHVX]> {
+tc_316c637c, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> {
 let Inst{7-7} = 0b0;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011110101;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vtmpyb : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vtmpyb_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vtmpyb_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vtmpyb_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001000;
@@ -44959,14 +36389,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vtmpyb_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32 += vtmpyb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -44975,87 +36404,34 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vtmpyb_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vxx32 += vtmpyb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vtmpyb_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32 = vtmpyb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vtmpyb_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32 = vtmpyb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vtmpybus : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vtmpybus_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001000;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vtmpybus_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vtmpybus_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001000;
@@ -45063,14 +36439,13 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vtmpybus_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32 += vtmpybus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
@@ -45079,48 +36454,22 @@ let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vtmpybus_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vxx32 += vtmpybus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vtmpybus_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32 = vtmpybus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vtmpybus_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32 = vtmpybus($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vtmpyhb : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
+tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011001101;
@@ -45128,24 +36477,11 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vtmpyhb_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)",
-tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b100;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011001101;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vtmpyhb_acc : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
+tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b1;
 let Inst{31-21} = 0b00011001000;
@@ -45155,90 +36491,35 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vtmpyhb_acc_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
-"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)",
-tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b1;
-let Inst{31-21} = 0b00011001000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vtmpyhb_acc_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vxx32 += vtmpyhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vtmpyhb_acc_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vxx32 += vtmpyhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vtmpyhb_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VecDblRegs:$Vuu32, IntRegs:$Rt32),
-"$Vdd32 = vtmpyhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vtmpyhb_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32),
+(outs HvxWR:$Vdd32),
+(ins HvxWR:$Vuu32, IntRegs:$Rt32),
 "$Vdd32 = vtmpyhb($Vuu32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vtran2x2_map : HInst<
-(outs VectorRegs:$Vy32, VectorRegs:$Vx32),
-(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32),
-"vtrans2x2($Vy32,$Vx32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let hasNewValue2 = 1;
-let opNewValue2 = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
-}
-def V6_vtran2x2_map_128B : HInst<
-(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32),
-(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32),
+(outs HvxVR:$Vy32, HvxVR:$Vx32),
+(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
 "vtrans2x2($Vy32,$Vx32,$Rt32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let hasNewValue2 = 1;
@@ -45246,124 +36527,59 @@ let opNewValue2 = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
 }
 def V6_vunpackb : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
-"$Vdd32.h = vunpack($Vu32.b)",
-tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vunpackb_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32.h = vunpack($Vu32.b)",
-tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
+tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vunpackb_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
-"$Vdd32 = vunpackb($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vunpackb_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32 = vunpackb($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vunpackh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
-"$Vdd32.w = vunpack($Vu32.h)",
-tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b011;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vunpackh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32.w = vunpack($Vu32.h)",
-tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
+tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b011;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vunpackh_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32 = vunpackh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vunpackh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
-"$Vdd32 = vunpackh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vunpackob : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32),
-"$Vxx32.h |= vunpacko($Vu32.b)",
-tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b1;
-let Inst{31-16} = 0b0001111000000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vunpackob_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
 "$Vxx32.h |= vunpacko($Vu32.b)",
-tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[HasV60T,UseHVX]> {
+tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b1;
 let Inst{31-16} = 0b0001111000000000;
@@ -45371,39 +36587,25 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vunpackob_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32),
-"$Vxx32 |= vunpackob($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vunpackob_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
 "$Vxx32 |= vunpackob($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vunpackoh : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
 "$Vxx32.w |= vunpacko($Vu32.h)",
-tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[HasV60T,UseHVX]> {
+tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b1;
 let Inst{31-16} = 0b0001111000000000;
@@ -45413,53 +36615,24 @@ let isAccumulator = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Vxx32 = $Vxx32in";
 }
-def V6_vunpackoh_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32),
-"$Vxx32.w |= vunpacko($Vu32.h)",
-tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b1;
-let Inst{31-16} = 0b0001111000000000;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-let Constraints = "$Vxx32 = $Vxx32in";
-}
 def V6_vunpackoh_alt : HInst<
-(outs VecDblRegs:$Vxx32),
-(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32),
-"$Vxx32 |= vunpackoh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isAccumulator = 1;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Vxx32 = $Vxx32in";
-}
-def V6_vunpackoh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vxx32),
-(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32),
+(outs HvxWR:$Vxx32),
+(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
 "$Vxx32 |= vunpackoh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isAccumulator = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 let Constraints = "$Vxx32 = $Vxx32in";
 }
 def V6_vunpackub : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32.uh = vunpack($Vu32.ub)",
-tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
+tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000001;
@@ -45467,47 +36640,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vunpackub_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
-"$Vdd32.uh = vunpack($Vu32.ub)",
-tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vunpackub_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32 = vunpackub($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vunpackub_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
-"$Vdd32 = vunpackub($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vunpackuh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32.uw = vunpack($Vu32.uh)",
-tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
+tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000001;
@@ -45515,236 +36663,112 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vunpackuh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
-"$Vdd32.uw = vunpack($Vu32.uh)",
-tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vunpackuh_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
-"$Vdd32 = vunpackuh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vunpackuh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32 = vunpackuh($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vwhist128 : HInst<
 (outs),
 (ins),
 "vwhist128",
-tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> {
-let Inst{13-0} = 0b10010010000000;
-let Inst{31-16} = 0b0001111000000000;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vwhist128_128B : HInst<
-(outs),
-(ins),
-"vwhist128",
-tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> {
+tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
 let Inst{13-0} = 0b10010010000000;
 let Inst{31-16} = 0b0001111000000000;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vwhist128m : HInst<
 (outs),
 (ins u1_0Imm:$Ii),
 "vwhist128(#$Ii)",
-tc_b77635b4, TypeCVI_HIST>, Enc_efaed8, Requires<[HasV62T,UseHVX]> {
-let Inst{7-0} = 0b10000000;
-let Inst{13-9} = 0b10011;
-let Inst{31-16} = 0b0001111000000000;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vwhist128m_128B : HInst<
-(outs),
-(ins u1_0Imm:$Ii),
-"vwhist128(#$Ii)",
-tc_b77635b4, TypeCVI_HIST>, Enc_efaed8, Requires<[HasV62T,UseHVX]> {
+tc_b77635b4, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> {
 let Inst{7-0} = 0b10000000;
 let Inst{13-9} = 0b10011;
 let Inst{31-16} = 0b0001111000000000;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vwhist128q : HInst<
 (outs),
-(ins VecPredRegs:$Qv4),
+(ins HvxQR:$Qv4),
 "vwhist128($Qv4)",
-tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> {
+tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
 let Inst{13-0} = 0b10010010000000;
 let Inst{21-16} = 0b000010;
 let Inst{31-24} = 0b00011110;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vwhist128q_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4),
-"vwhist128($Qv4)",
-tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> {
-let Inst{13-0} = 0b10010010000000;
-let Inst{21-16} = 0b000010;
-let Inst{31-24} = 0b00011110;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vwhist128qm : HInst<
 (outs),
-(ins VecPredRegs:$Qv4, u1_0Imm:$Ii),
+(ins HvxQR:$Qv4, u1_0Imm:$Ii),
 "vwhist128($Qv4,#$Ii)",
-tc_28978789, TypeCVI_HIST>, Enc_802dc0, Requires<[HasV62T,UseHVX]> {
+tc_28978789, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> {
 let Inst{7-0} = 0b10000000;
 let Inst{13-9} = 0b10011;
 let Inst{21-16} = 0b000010;
 let Inst{31-24} = 0b00011110;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vwhist128qm_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4, u1_0Imm:$Ii),
-"vwhist128($Qv4,#$Ii)",
-tc_28978789, TypeCVI_HIST>, Enc_802dc0, Requires<[HasV62T,UseHVX]> {
-let Inst{7-0} = 0b10000000;
-let Inst{13-9} = 0b10011;
-let Inst{21-16} = 0b000010;
-let Inst{31-24} = 0b00011110;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vwhist256 : HInst<
 (outs),
 (ins),
 "vwhist256",
-tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> {
+tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
 let Inst{13-0} = 0b10001010000000;
 let Inst{31-16} = 0b0001111000000000;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vwhist256_128B : HInst<
-(outs),
-(ins),
-"vwhist256",
-tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> {
-let Inst{13-0} = 0b10001010000000;
-let Inst{31-16} = 0b0001111000000000;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vwhist256_sat : HInst<
 (outs),
 (ins),
 "vwhist256:sat",
-tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> {
-let Inst{13-0} = 0b10001110000000;
-let Inst{31-16} = 0b0001111000000000;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vwhist256_sat_128B : HInst<
-(outs),
-(ins),
-"vwhist256:sat",
-tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> {
+tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
 let Inst{13-0} = 0b10001110000000;
 let Inst{31-16} = 0b0001111000000000;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vwhist256q : HInst<
 (outs),
-(ins VecPredRegs:$Qv4),
-"vwhist256($Qv4)",
-tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> {
-let Inst{13-0} = 0b10001010000000;
-let Inst{21-16} = 0b000010;
-let Inst{31-24} = 0b00011110;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vwhist256q_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4),
+(ins HvxQR:$Qv4),
 "vwhist256($Qv4)",
-tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> {
+tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
 let Inst{13-0} = 0b10001010000000;
 let Inst{21-16} = 0b000010;
 let Inst{31-24} = 0b00011110;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vwhist256q_sat : HInst<
 (outs),
-(ins VecPredRegs:$Qv4),
-"vwhist256($Qv4):sat",
-tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> {
-let Inst{13-0} = 0b10001110000000;
-let Inst{21-16} = 0b000010;
-let Inst{31-24} = 0b00011110;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vwhist256q_sat_128B : HInst<
-(outs),
-(ins VecPredRegs128B:$Qv4),
+(ins HvxQR:$Qv4),
 "vwhist256($Qv4):sat",
-tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> {
+tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
 let Inst{13-0} = 0b10001110000000;
 let Inst{21-16} = 0b000010;
 let Inst{31-24} = 0b00011110;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vxor : HInst<
-(outs VectorRegs:$Vd32),
-(ins VectorRegs:$Vu32, VectorRegs:$Vv32),
-"$Vd32 = vxor($Vu32,$Vv32)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b111;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b00011100001;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vxor_128B : HInst<
-(outs VectorRegs128B:$Vd32),
-(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32),
+(outs HvxVR:$Vd32),
+(ins HvxVR:$Vu32, HvxVR:$Vv32),
 "$Vd32 = vxor($Vu32,$Vv32)",
-tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> {
+tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b111;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b00011100001;
 let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vzb : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32.uh = vzxt($Vu32.ub)",
-tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
+tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b001;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000010;
@@ -45752,47 +36776,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vzb_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
-"$Vdd32.uh = vzxt($Vu32.ub)",
-tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vzb_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
-"$Vdd32 = vzxtb($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vzb_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32 = vzxtb($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
 }
 def V6_vzh : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32.uw = vzxt($Vu32.uh)",
-tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
+tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
 let Inst{7-5} = 0b010;
 let Inst{13-13} = 0b0;
 let Inst{31-16} = 0b0001111000000010;
@@ -45800,47 +36799,22 @@ let hasNewValue = 1;
 let opNewValue = 0;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vzh_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
-"$Vdd32.uw = vzxt($Vu32.uh)",
-tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-16} = 0b0001111000000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def V6_vzh_alt : HInst<
-(outs VecDblRegs:$Vdd32),
-(ins VectorRegs:$Vu32),
+(outs HvxWR:$Vdd32),
+(ins HvxVR:$Vu32),
 "$Vdd32 = vzxth($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
+PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
 let hasNewValue = 1;
 let opNewValue = 0;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";
 }
-def V6_vzh_alt_128B : HInst<
-(outs VecDblRegs128B:$Vdd32),
-(ins VectorRegs128B:$Vu32),
-"$Vdd32 = vzxth($Vu32)",
-PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> {
-let hasNewValue = 1;
-let opNewValue = 0;
-let isPseudo = 1;
-let isCodeGenOnly = 1;
-let DecoderNamespace = "EXT_mmvec";
-let isCodeGenOnly = 1;
-}
 def Y2_barrier : HInst<
 (outs),
 (ins),
 "barrier",
-tc_ef2676fd, TypeST>, Enc_e3b0c4 {
+tc_367f7f3d, TypeST>, Enc_e3b0c4 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-16} = 0b1010100000000000;
 let isSoloAX = 1;
@@ -45850,7 +36824,7 @@ def Y2_break : HInst<
 (outs),
 (ins),
 "brkpt",
-tc_bcf0e36e, TypeCR>, Enc_e3b0c4 {
+tc_4ca572d4, TypeCR>, Enc_e3b0c4 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-16} = 0b0110110000100000;
 let isSolo = 1;
@@ -45859,27 +36833,27 @@ def Y2_dccleana : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "dccleana($Rs32)",
-tc_30665cb0, TypeST>, Enc_ecbcc8 {
+tc_00e7c26e, TypeST>, Enc_ecbcc8 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b10100000000;
-let isSoloAin1 = 1;
+let isRestrictSlot1AOK = 1;
 let hasSideEffects = 1;
 }
 def Y2_dccleaninva : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "dccleaninva($Rs32)",
-tc_30665cb0, TypeST>, Enc_ecbcc8 {
+tc_00e7c26e, TypeST>, Enc_ecbcc8 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b10100000010;
-let isSoloAin1 = 1;
+let isRestrictSlot1AOK = 1;
 let hasSideEffects = 1;
 }
 def Y2_dcfetch : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "dcfetch($Rs32)",
-tc_34e882a4, TypeMAPPING> {
+tc_3da80ba5, TypeMAPPING> {
 let hasSideEffects = 1;
 let isPseudo = 1;
 let isCodeGenOnly = 1;
@@ -45888,38 +36862,39 @@ def Y2_dcfetchbo : HInst<
 (outs),
 (ins IntRegs:$Rs32, u11_3Imm:$Ii),
 "dcfetch($Rs32+#$Ii)",
-tc_ef0ebaaa, TypeLD>, Enc_2d829e {
+tc_4d9914c9, TypeLD>, Enc_2d829e {
 let Inst{13-11} = 0b000;
 let Inst{31-21} = 0b10010100000;
 let addrMode = BaseImmOffset;
+let isRestrictNoSlot1Store = 1;
 let hasSideEffects = 1;
 }
 def Y2_dcinva : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "dcinva($Rs32)",
-tc_30665cb0, TypeST>, Enc_ecbcc8 {
+tc_00e7c26e, TypeST>, Enc_ecbcc8 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b10100000001;
-let isSoloAin1 = 1;
+let isRestrictSlot1AOK = 1;
 let hasSideEffects = 1;
 }
 def Y2_dczeroa : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "dczeroa($Rs32)",
-tc_30665cb0, TypeST>, Enc_ecbcc8 {
+tc_00e7c26e, TypeST>, Enc_ecbcc8 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b10100000110;
-let isSoloAin1 = 1;
-let hasSideEffects = 1;
+let isRestrictSlot1AOK = 1;
 let mayStore = 1;
+let hasSideEffects = 1;
 }
 def Y2_icinva : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "icinva($Rs32)",
-tc_049dfb74, TypeJ>, Enc_ecbcc8 {
+tc_999d32db, TypeJ>, Enc_ecbcc8 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b01010110110;
 let isSolo = 1;
@@ -45928,7 +36903,7 @@ def Y2_isync : HInst<
 (outs),
 (ins),
 "isync",
-tc_d267fa19, TypeJ>, Enc_e3b0c4 {
+tc_b13761ae, TypeJ>, Enc_e3b0c4 {
 let Inst{13-0} = 0b00000000000010;
 let Inst{31-16} = 0b0101011111000000;
 let isSolo = 1;
@@ -45937,7 +36912,7 @@ def Y2_syncht : HInst<
 (outs),
 (ins),
 "syncht",
-tc_ef2676fd, TypeST>, Enc_e3b0c4 {
+tc_367f7f3d, TypeST>, Enc_e3b0c4 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-16} = 0b1010100001000000;
 let isSolo = 1;
@@ -45946,7 +36921,7 @@ def Y4_l2fetch : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "l2fetch($Rs32,$Rt32)",
-tc_f4608adc, TypeST>, Enc_ca3887 {
+tc_daa058fa, TypeST>, Enc_ca3887 {
 let Inst{7-0} = 0b00000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10100110000;
@@ -45958,7 +36933,7 @@ def Y4_trace : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "trace($Rs32)",
-tc_4997da4a, TypeCR>, Enc_ecbcc8 {
+tc_c82dc1ff, TypeCR>, Enc_ecbcc8 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b01100010010;
 let isSoloAX = 1;
@@ -45967,7 +36942,7 @@ def Y5_l2fetch : HInst<
 (outs),
 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
 "l2fetch($Rs32,$Rtt32)",
-tc_f4608adc, TypeST>, Enc_e6abcf, Requires<[HasV5T]> {
+tc_daa058fa, TypeST>, Enc_e6abcf, Requires<[HasV5T]> {
 let Inst{7-0} = 0b00000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10100110100;
@@ -45979,7 +36954,7 @@ def dep_A2_addsat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rd32 = add($Rs32,$Rt32):sat:deprecated",
-tc_47ab9233, TypeALU64>, Enc_5ab2be {
+tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101100;
@@ -45992,7 +36967,7 @@ def dep_A2_subsat : HInst<
 (outs IntRegs:$Rd32),
 (ins IntRegs:$Rt32, IntRegs:$Rs32),
 "$Rd32 = sub($Rt32,$Rs32):sat:deprecated",
-tc_47ab9233, TypeALU64>, Enc_bd6011 {
+tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
 let Inst{7-5} = 0b100;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010101100;
@@ -46005,7 +36980,7 @@ def dep_S2_packhl : HInst<
 (outs DoubleRegs:$Rdd32),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "$Rdd32 = packhl($Rs32,$Rt32):deprecated",
-tc_9c18c9a5, TypeALU64>, Enc_be32a5 {
+tc_540fdfbc, TypeALU64>, Enc_be32a5 {
 let Inst{7-5} = 0b000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b11010100000;
diff --git a/lib/Target/Hexagon/HexagonDepMappings.td b/lib/Target/Hexagon/HexagonDepMappings.td
index 77a56a9adf10..7a156c39da9c 100644
--- a/lib/Target/Hexagon/HexagonDepMappings.td
+++ b/lib/Target/Hexagon/HexagonDepMappings.td
@@ -1,4 +1,4 @@
-//===--- HexagonDepMappings.td --------------------------------------------===//
+//===- HexagonDepMappings.td ----------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,649 +6,470 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
 
-def A2_negAlias : InstAlias<"$Rd32=neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>;
-def A2_notAlias : InstAlias<"$Rd32=not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>;
-def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32=$Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
-def A2_tfrfnewAlias : InstAlias<"if (!$Pu4.new) $Rd32=$Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
-def A2_tfrtAlias : InstAlias<"if ($Pu4) $Rd32=$Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
-def A2_tfrtnewAlias : InstAlias<"if ($Pu4.new) $Rd32=$Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
-def A2_vaddb_mapAlias : InstAlias<"$Rdd32=vaddb($Rss32,$Rtt32)", (A2_vaddub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>;
-def A2_vsubb_mapAlias : InstAlias<"$Rdd32=vsubb($Rss32,$Rtt32)", (A2_vsubub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>;
-def A2_zxtbAlias : InstAlias<"$Rd32=zxtb($Rs32)", (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255)>;
-def C2_cmpltAlias : InstAlias<"$Pd4=cmp.lt($Rs32,$Rt32)", (C2_cmpgt PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>;
-def C2_cmpltuAlias : InstAlias<"$Pd4=cmp.ltu($Rs32,$Rt32)", (C2_cmpgtu PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>;
-def C2_pxfer_mapAlias : InstAlias<"$Pd4=$Ps4", (C2_or PredRegs:$Pd4, PredRegs:$Ps4, PredRegs:$Ps4)>;
+def A2_negAlias : InstAlias<"$Rd32 = neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>;
+def A2_notAlias : InstAlias<"$Rd32 = not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>;
+def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32 = $Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
+def A2_tfrfnewAlias : InstAlias<"if (!$Pu4.new) $Rd32 = $Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
+def A2_tfrtAlias : InstAlias<"if ($Pu4) $Rd32 = $Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
+def A2_tfrtnewAlias : InstAlias<"if ($Pu4.new) $Rd32 = $Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
+def A2_vaddb_mapAlias : InstAlias<"$Rdd32 = vaddb($Rss32,$Rtt32)", (A2_vaddub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>;
+def A2_vsubb_mapAlias : InstAlias<"$Rdd32 = vsubb($Rss32,$Rtt32)", (A2_vsubub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>;
+def A2_zxtbAlias : InstAlias<"$Rd32 = zxtb($Rs32)", (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255)>;
+def C2_cmpltAlias : InstAlias<"$Pd4 = cmp.lt($Rs32,$Rt32)", (C2_cmpgt PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>;
+def C2_cmpltuAlias : InstAlias<"$Pd4 = cmp.ltu($Rs32,$Rt32)", (C2_cmpgtu PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>;
+def C2_pxfer_mapAlias : InstAlias<"$Pd4 = $Ps4", (C2_or PredRegs:$Pd4, PredRegs:$Ps4, PredRegs:$Ps4)>;
 def J2_jumpf_nopred_mapAlias : InstAlias<"if (!$Pu4) jump $Ii", (J2_jumpf PredRegs:$Pu4, b30_2Imm:$Ii)>;
 def J2_jumprf_nopred_mapAlias : InstAlias<"if (!$Pu4) jumpr $Rs32", (J2_jumprf PredRegs:$Pu4, IntRegs:$Rs32)>;
 def J2_jumprt_nopred_mapAlias : InstAlias<"if ($Pu4) jumpr $Rs32", (J2_jumprt PredRegs:$Pu4, IntRegs:$Rs32)>;
 def J2_jumpt_nopred_mapAlias : InstAlias<"if ($Pu4) jump $Ii", (J2_jumpt PredRegs:$Pu4, b30_2Imm:$Ii)>;
-def L2_loadalignb_zomapAlias : InstAlias<"$Ryy32=memb_fifo($Rs32)", (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>;
-def L2_loadalignh_zomapAlias : InstAlias<"$Ryy32=memh_fifo($Rs32)", (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>;
-def L2_loadbsw2_zomapAlias : InstAlias<"$Rd32=membh($Rs32)", (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
-def L2_loadbsw4_zomapAlias : InstAlias<"$Rdd32=membh($Rs32)", (L2_loadbsw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>;
-def L2_loadbzw2_zomapAlias : InstAlias<"$Rd32=memubh($Rs32)", (L2_loadbzw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
-def L2_loadbzw4_zomapAlias : InstAlias<"$Rdd32=memubh($Rs32)", (L2_loadbzw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>;
-def L2_loadrb_zomapAlias : InstAlias<"$Rd32=memb($Rs32)", (L2_loadrb_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
-def L2_loadrd_zomapAlias : InstAlias<"$Rdd32=memd($Rs32)", (L2_loadrd_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>;
-def L2_loadrh_zomapAlias : InstAlias<"$Rd32=memh($Rs32)", (L2_loadrh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
-def L2_loadri_zomapAlias : InstAlias<"$Rd32=memw($Rs32)", (L2_loadri_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
-def L2_loadrub_zomapAlias : InstAlias<"$Rd32=memub($Rs32)", (L2_loadrub_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
-def L2_loadruh_zomapAlias : InstAlias<"$Rd32=memuh($Rs32)", (L2_loadruh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
-def L2_ploadrbf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memb($Rs32)", (L2_ploadrbf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrbfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memb($Rs32)", (L2_ploadrbfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrbt_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memb($Rs32)", (L2_ploadrbt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrbtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memb($Rs32)", (L2_ploadrbtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrdf_zomapAlias : InstAlias<"if (!$Pt4) $Rdd32=memd($Rs32)", (L2_ploadrdf_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrdfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rdd32=memd($Rs32)", (L2_ploadrdfnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrdt_zomapAlias : InstAlias<"if ($Pt4) $Rdd32=memd($Rs32)", (L2_ploadrdt_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrdtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rdd32=memd($Rs32)", (L2_ploadrdtnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memh($Rs32)", (L2_ploadrhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memh($Rs32)", (L2_ploadrhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrht_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memh($Rs32)", (L2_ploadrht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memh($Rs32)", (L2_ploadrhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrif_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memw($Rs32)", (L2_ploadrif_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrifnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memw($Rs32)", (L2_ploadrifnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrit_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memw($Rs32)", (L2_ploadrit_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadritnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memw($Rs32)", (L2_ploadritnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrubf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memub($Rs32)", (L2_ploadrubf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrubfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memub($Rs32)", (L2_ploadrubfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrubt_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memub($Rs32)", (L2_ploadrubt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadrubtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memub($Rs32)", (L2_ploadrubtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadruhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memuh($Rs32)", (L2_ploadruhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadruhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memuh($Rs32)", (L2_ploadruhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadruht_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memuh($Rs32)", (L2_ploadruht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L2_ploadruhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memuh($Rs32)", (L2_ploadruhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
-def L4_add_memopb_zomapAlias : InstAlias<"memb($Rs32)+=$Rt32", (L4_add_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_add_memoph_zomapAlias : InstAlias<"memh($Rs32)+=$Rt32", (L4_add_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_add_memopw_zomapAlias : InstAlias<"memw($Rs32)+=$Rt32", (L4_add_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_and_memopb_zomapAlias : InstAlias<"memb($Rs32)&=$Rt32", (L4_and_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_and_memoph_zomapAlias : InstAlias<"memh($Rs32)&=$Rt32", (L4_and_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_and_memopw_zomapAlias : InstAlias<"memw($Rs32)&=$Rt32", (L4_and_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_iadd_memopb_zomapAlias : InstAlias<"memb($Rs32)+=#$II", (L4_iadd_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_iadd_memoph_zomapAlias : InstAlias<"memh($Rs32)+=#$II", (L4_iadd_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_iadd_memopw_zomapAlias : InstAlias<"memw($Rs32)+=#$II", (L4_iadd_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_iand_memopb_zomapAlias : InstAlias<"memb($Rs32)=clrbit(#$II)", (L4_iand_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_iand_memoph_zomapAlias : InstAlias<"memh($Rs32)=clrbit(#$II)", (L4_iand_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_iand_memopw_zomapAlias : InstAlias<"memw($Rs32)=clrbit(#$II)", (L4_iand_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_ior_memopb_zomapAlias : InstAlias<"memb($Rs32)=setbit(#$II)", (L4_ior_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_ior_memoph_zomapAlias : InstAlias<"memh($Rs32)=setbit(#$II)", (L4_ior_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_ior_memopw_zomapAlias : InstAlias<"memw($Rs32)=setbit(#$II)", (L4_ior_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_isub_memopb_zomapAlias : InstAlias<"memb($Rs32)-=#$II", (L4_isub_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_isub_memoph_zomapAlias : InstAlias<"memh($Rs32)-=#$II", (L4_isub_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_isub_memopw_zomapAlias : InstAlias<"memw($Rs32)-=#$II", (L4_isub_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
-def L4_or_memopb_zomapAlias : InstAlias<"memb($Rs32)|=$Rt32", (L4_or_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_or_memoph_zomapAlias : InstAlias<"memh($Rs32)|=$Rt32", (L4_or_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_or_memopw_zomapAlias : InstAlias<"memw($Rs32)|=$Rt32", (L4_or_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_sub_memopb_zomapAlias : InstAlias<"memb($Rs32)-=$Rt32", (L4_sub_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_sub_memoph_zomapAlias : InstAlias<"memh($Rs32)-=$Rt32", (L4_sub_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def L4_sub_memopw_zomapAlias : InstAlias<"memw($Rs32)-=$Rt32", (L4_sub_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def M2_mpyuiAlias : InstAlias<"$Rd32=mpyui($Rs32,$Rt32)", (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32)>;
-def S2_pstorerbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=$Rt32", (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_pstorerbnewf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=$Nt8.new", (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S2_pstorerbnewt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=$Nt8.new", (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S2_pstorerbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=$Rt32", (S2_pstorerbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_pstorerdf_zomapAlias : InstAlias<"if (!$Pv4) memd($Rs32)=$Rtt32", (S2_pstorerdf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
-def S2_pstorerdt_zomapAlias : InstAlias<"if ($Pv4) memd($Rs32)=$Rtt32", (S2_pstorerdt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
-def S2_pstorerff_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Rt32.h", (S2_pstorerff_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_pstorerft_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Rt32.h", (S2_pstorerft_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_pstorerhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Rt32", (S2_pstorerhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_pstorerhnewf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Nt8.new", (S2_pstorerhnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S2_pstorerhnewt_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Nt8.new", (S2_pstorerhnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S2_pstorerht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Rt32", (S2_pstorerht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_pstorerif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=$Rt32", (S2_pstorerif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_pstorerinewf_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=$Nt8.new", (S2_pstorerinewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S2_pstorerinewt_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=$Nt8.new", (S2_pstorerinewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S2_pstorerit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=$Rt32", (S2_pstorerit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_storerb_zomapAlias : InstAlias<"memb($Rs32)=$Rt32", (S2_storerb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_storerbnew_zomapAlias : InstAlias<"memb($Rs32)=$Nt8.new", (S2_storerbnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S2_storerd_zomapAlias : InstAlias<"memd($Rs32)=$Rtt32", (S2_storerd_io IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
-def S2_storerf_zomapAlias : InstAlias<"memh($Rs32)=$Rt32.h", (S2_storerf_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_storerh_zomapAlias : InstAlias<"memh($Rs32)=$Rt32", (S2_storerh_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_storerhnew_zomapAlias : InstAlias<"memh($Rs32)=$Nt8.new", (S2_storerhnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S2_storeri_zomapAlias : InstAlias<"memw($Rs32)=$Rt32", (S2_storeri_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S2_storerinew_zomapAlias : InstAlias<"memw($Rs32)=$Nt8.new", (S2_storerinew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S2_tableidxb_goodsyntaxAlias : InstAlias<"$Rx32=tableidxb($Rs32,#$Ii,#$II)", (S2_tableidxb IntRegs:$Rx32, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II)>;
-def S4_pstorerbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=$Rt32", (S4_pstorerbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S4_pstorerbnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=$Nt8.new", (S4_pstorerbnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S4_pstorerbnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=$Nt8.new", (S4_pstorerbnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S4_pstorerbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=$Rt32", (S4_pstorerbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S4_pstorerdfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memd($Rs32)=$Rtt32", (S4_pstorerdfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
-def S4_pstorerdtnew_zomapAlias : InstAlias<"if ($Pv4.new) memd($Rs32)=$Rtt32", (S4_pstorerdtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
-def S4_pstorerffnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Rt32.h", (S4_pstorerffnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S4_pstorerftnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Rt32.h", (S4_pstorerftnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S4_pstorerhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Rt32", (S4_pstorerhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S4_pstorerhnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Nt8.new", (S4_pstorerhnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S4_pstorerhnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Nt8.new", (S4_pstorerhnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S4_pstorerhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Rt32", (S4_pstorerhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S4_pstorerifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=$Rt32", (S4_pstorerifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S4_pstorerinewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=$Nt8.new", (S4_pstorerinewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S4_pstorerinewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=$Nt8.new", (S4_pstorerinewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
-def S4_pstoreritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=$Rt32", (S4_pstoreritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
-def S4_storeirb_zomapAlias : InstAlias<"memb($Rs32)=#$II", (S4_storeirb_io IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=#$II", (S4_storeirbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=#$II", (S4_storeirbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=#$II", (S4_storeirbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=#$II", (S4_storeirbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirh_zomapAlias : InstAlias<"memh($Rs32)=#$II", (S4_storeirh_io IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=#$II", (S4_storeirhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=#$II", (S4_storeirhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=#$II", (S4_storeirht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=#$II", (S4_storeirhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeiri_zomapAlias : InstAlias<"memw($Rs32)=#$II", (S4_storeiri_io IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=#$II", (S4_storeirif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=#$II", (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeirit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=#$II", (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def S4_storeiritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=#$II", (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
-def V6_MAP_equbAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equb_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equb_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equb_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equb_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equb_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equb_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equb_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equhAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equh_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equh_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equh_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equh_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equh_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equh_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equh_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equwAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equw_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equw_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equw_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equw_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equw_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equw_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_MAP_equw_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_extractw_altAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>;
-def V6_extractw_alt_128BAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>;
-def V6_ld0Alias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
-def V6_ld0_128BAlias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
-def V6_ldnt0Alias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
-def V6_ldnt0_128BAlias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
-def V6_ldu0Alias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
-def V6_ldu0_128BAlias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
-def V6_st0Alias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_st0_128BAlias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stn0Alias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>;
-def V6_stn0_128BAlias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>;
-def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>;
-def V6_stnnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>;
-def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stnp0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stnpnt0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stnq0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stnqnt0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stp0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stpnt0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stq0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stqnt0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stu0Alias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stu0_128BAlias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stunp0_128BAlias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_stup0_128BAlias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
-def V6_vabsdiffh_altAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vabsdiffh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vabsdiffub_altAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vabsdiffub_alt_128BAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vabsdiffuh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vabsdiffw_altAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vabsdiffw_alt_128BAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vabsh_altAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsh_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsh_sat_altAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsh_sat_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsuh_alt_128BAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsuw_alt_128BAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsw_altAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsw_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsw_sat_altAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vabsw_sat_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddb_altAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddb_alt_128BAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vaddb_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddh_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddh_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vaddh_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddhsat_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddhsat_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vaddhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vaddhw_altAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddhw_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddubh_altAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddubh_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddubsat_altAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddubsat_alt_128BAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vaddubsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vadduhsat_altAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vadduhsat_alt_128BAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vadduhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vadduhw_altAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vadduhw_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddw_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddw_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vaddw_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vaddwsat_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddwsat_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vaddwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vandqrt_acc_alt_128BAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vandqrt_alt_128BAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vandvrt_acc_alt_128BAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vandvrt_alt_128BAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vaslh_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vaslh_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vaslhv_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaslhv_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaslw_acc_altAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vaslw_acc_alt_128BAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vaslw_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vaslw_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vaslwv_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vaslwv_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vasrh_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vasrh_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32=vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
-def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
-def V6_vasrhubsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
-def V6_vasrhv_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vasrhv_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vasrw_acc_altAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vasrw_acc_alt_128BAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vasrw_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vasrw_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vasrwh_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
-def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
-def V6_vasrwhsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
-def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32=vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
-def V6_vasrwv_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vasrwv_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavgh_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavgh_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavghrnd_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavghrnd_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavgub_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavgub_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavgubrnd_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavgubrnd_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavguh_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavguh_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavguhrnd_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavguhrnd_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavgw_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavgw_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavgwrnd_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vavgwrnd_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vcl0h_altAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vcl0h_alt_128BAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vcl0w_altAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vcl0w_alt_128BAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vd0Alias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>;
-def V6_vd0_128BAlias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>;
-def V6_vdd0Alias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>;
-def V6_vdd0_128BAlias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>;
-def V6_vdealb4w_altAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vdealb4w_alt_128BAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vdealb_altAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vdealb_alt_128BAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vdealh_altAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vdealh_alt_128BAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpybus_altAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpybus_alt_128BAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpybus_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpybus_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhb_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhb_altAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhb_alt_128BAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhb_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhb_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsuisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsuisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsusat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhsusat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vdmpyhvsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vdmpyhvsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdsaduh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdsaduh_altAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vdsaduh_alt_128BAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vlsrh_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vlsrh_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vlsrhv_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vlsrhv_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vlsrw_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vlsrw_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vlsrwv_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vlsrwv_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmaxh_altAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmaxh_alt_128BAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmaxub_altAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmaxub_alt_128BAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmaxuh_altAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmaxuh_alt_128BAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmaxw_altAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmaxw_alt_128BAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vminh_altAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vminh_alt_128BAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vminub_altAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vminub_alt_128BAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vminuh_altAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vminuh_alt_128BAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vminw_altAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vminw_alt_128BAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpabus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpabus_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpabus_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpabusv_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vmpabusv_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vmpabuuv_alt_128BAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpahb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpahb_altAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpahb_alt_128BAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpybus_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpybus_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpybusv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpybusv_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpybusv_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpybv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpybv_altAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpybv_alt_128BAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyewuh_altAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyh_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyh_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyhsat_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyhsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyhss_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyhss_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyhus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyhus_altAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyhus_alt_128BAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyhv_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyhvsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyiewh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyiewuh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyiewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyih_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyih_altAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyih_alt_128BAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyihb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyihb_altAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyihb_alt_128BAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyiowh_altAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyiowh_alt_128BAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyiwb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyiwb_altAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyiwb_alt_128BAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyiwh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyiwh_altAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyiwh_alt_128BAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyowh_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyowh_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyowh_rnd_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyub_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyub_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyub_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyubv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyubv_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyubv_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyuh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyuh_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyuh_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyuhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vmpyuhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vnavgh_altAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vnavgh_alt_128BAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vnavgub_altAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vnavgub_alt_128BAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vnavgw_altAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vnavgw_alt_128BAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vnormamth_altAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vnormamth_alt_128BAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vnormamtw_altAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vnormamtw_alt_128BAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vpackeb_altAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackeb_alt_128BAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackeh_altAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackeh_alt_128BAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackhb_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackhub_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackob_altAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackob_alt_128BAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackoh_altAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackoh_alt_128BAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackwh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpackwuh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vpopcounth_altAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vpopcounth_alt_128BAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vrmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vrmpybus_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vrmpybus_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrmpybusi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrmpybusi_alt_128BAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpybusv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpybusv_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpybusv_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpybv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpybv_altAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpybv_alt_128BAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vrmpyub_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vrmpyub_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vrmpyub_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrmpyubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrmpyubi_alt_128BAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpyubv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpyubv_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrmpyubv_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vroundhb_altAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vroundhb_alt_128BAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vroundhub_altAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vroundhub_alt_128BAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vroundwh_altAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vroundwh_alt_128BAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vroundwuh_altAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vroundwuh_alt_128BAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrsadubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrsadubi_altAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vrsadubi_alt_128BAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
-def V6_vsathub_altAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsathub_alt_128BAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsatwh_altAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsatwh_alt_128BAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsb_altAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsb_alt_128BAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsh_altAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsh_alt_128BAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vshufeh_altAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshufeh_alt_128BAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshuffb_altAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vshuffb_alt_128BAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vshuffeb_altAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshuffeb_alt_128BAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshuffh_altAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vshuffh_alt_128BAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vshuffob_altAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshuffob_alt_128BAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshufoeb_altAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshufoeb_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshufoeh_altAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshufoeh_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshufoh_altAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vshufoh_alt_128BAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubb_altAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubb_alt_128BAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubb_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubh_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubh_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubh_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubhsat_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubhsat_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubhw_altAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubhw_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsububh_altAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsububh_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsububsat_altAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsububsat_alt_128BAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsububsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubuhsat_altAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubuhsat_alt_128BAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubuhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubuhw_altAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubuhw_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubw_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubw_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubw_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vsubwsat_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubwsat_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
-def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vsubwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
-def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpyb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpyb_altAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpyb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpybus_altAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpybus_alt_128BAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpyhb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtmpyhb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtran2x2_mapAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vtran2x2_map_128BAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
-def V6_vunpackb_altAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vunpackb_alt_128BAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vunpackh_altAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vunpackh_alt_128BAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vunpackoh_altAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vunpackoh_alt_128BAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vunpackub_altAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vunpackub_alt_128BAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vunpackuh_altAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vunpackuh_alt_128BAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vzb_altAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vzb_alt_128BAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vzh_altAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
-def V6_vzh_alt_128BAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def L2_loadalignb_zomapAlias : InstAlias<"$Ryy32 = memb_fifo($Rs32)", (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>;
+def L2_loadalignh_zomapAlias : InstAlias<"$Ryy32 = memh_fifo($Rs32)", (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>;
+def L2_loadbsw2_zomapAlias : InstAlias<"$Rd32 = membh($Rs32)", (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadbsw4_zomapAlias : InstAlias<"$Rdd32 = membh($Rs32)", (L2_loadbsw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>;
+def L2_loadbzw2_zomapAlias : InstAlias<"$Rd32 = memubh($Rs32)", (L2_loadbzw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadbzw4_zomapAlias : InstAlias<"$Rdd32 = memubh($Rs32)", (L2_loadbzw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>;
+def L2_loadrb_zomapAlias : InstAlias<"$Rd32 = memb($Rs32)", (L2_loadrb_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadrd_zomapAlias : InstAlias<"$Rdd32 = memd($Rs32)", (L2_loadrd_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>;
+def L2_loadrh_zomapAlias : InstAlias<"$Rd32 = memh($Rs32)", (L2_loadrh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadri_zomapAlias : InstAlias<"$Rd32 = memw($Rs32)", (L2_loadri_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadrub_zomapAlias : InstAlias<"$Rd32 = memub($Rs32)", (L2_loadrub_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadruh_zomapAlias : InstAlias<"$Rd32 = memuh($Rs32)", (L2_loadruh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_ploadrbf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32 = memb($Rs32)", (L2_ploadrbf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrbfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32 = memb($Rs32)", (L2_ploadrbfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrbt_zomapAlias : InstAlias<"if ($Pt4) $Rd32 = memb($Rs32)", (L2_ploadrbt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrbtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32 = memb($Rs32)", (L2_ploadrbtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrdf_zomapAlias : InstAlias<"if (!$Pt4) $Rdd32 = memd($Rs32)", (L2_ploadrdf_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrdfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rdd32 = memd($Rs32)", (L2_ploadrdfnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrdt_zomapAlias : InstAlias<"if ($Pt4) $Rdd32 = memd($Rs32)", (L2_ploadrdt_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrdtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rdd32 = memd($Rs32)", (L2_ploadrdtnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32 = memh($Rs32)", (L2_ploadrhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32 = memh($Rs32)", (L2_ploadrhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrht_zomapAlias : InstAlias<"if ($Pt4) $Rd32 = memh($Rs32)", (L2_ploadrht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32 = memh($Rs32)", (L2_ploadrhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrif_zomapAlias : InstAlias<"if (!$Pt4) $Rd32 = memw($Rs32)", (L2_ploadrif_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrifnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32 = memw($Rs32)", (L2_ploadrifnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrit_zomapAlias : InstAlias<"if ($Pt4) $Rd32 = memw($Rs32)", (L2_ploadrit_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadritnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32 = memw($Rs32)", (L2_ploadritnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrubf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32 = memub($Rs32)", (L2_ploadrubf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrubfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32 = memub($Rs32)", (L2_ploadrubfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrubt_zomapAlias : InstAlias<"if ($Pt4) $Rd32 = memub($Rs32)", (L2_ploadrubt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrubtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32 = memub($Rs32)", (L2_ploadrubtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadruhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32 = memuh($Rs32)", (L2_ploadruhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadruhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32 = memuh($Rs32)", (L2_ploadruhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadruht_zomapAlias : InstAlias<"if ($Pt4) $Rd32 = memuh($Rs32)", (L2_ploadruht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadruhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32 = memuh($Rs32)", (L2_ploadruhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L4_add_memopb_zomapAlias : InstAlias<"memb($Rs32) += $Rt32", (L4_add_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_add_memoph_zomapAlias : InstAlias<"memh($Rs32) += $Rt32", (L4_add_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_add_memopw_zomapAlias : InstAlias<"memw($Rs32) += $Rt32", (L4_add_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_and_memopb_zomapAlias : InstAlias<"memb($Rs32) &= $Rt32", (L4_and_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_and_memoph_zomapAlias : InstAlias<"memh($Rs32) &= $Rt32", (L4_and_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_and_memopw_zomapAlias : InstAlias<"memw($Rs32) &= $Rt32", (L4_and_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_iadd_memopb_zomapAlias : InstAlias<"memb($Rs32) += #$II", (L4_iadd_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_iadd_memoph_zomapAlias : InstAlias<"memh($Rs32) += #$II", (L4_iadd_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_iadd_memopw_zomapAlias : InstAlias<"memw($Rs32) += #$II", (L4_iadd_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_iand_memopb_zomapAlias : InstAlias<"memb($Rs32) = clrbit(#$II)", (L4_iand_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_iand_memoph_zomapAlias : InstAlias<"memh($Rs32) = clrbit(#$II)", (L4_iand_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_iand_memopw_zomapAlias : InstAlias<"memw($Rs32) = clrbit(#$II)", (L4_iand_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_ior_memopb_zomapAlias : InstAlias<"memb($Rs32) = setbit(#$II)", (L4_ior_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_ior_memoph_zomapAlias : InstAlias<"memh($Rs32) = setbit(#$II)", (L4_ior_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_ior_memopw_zomapAlias : InstAlias<"memw($Rs32) = setbit(#$II)", (L4_ior_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_isub_memopb_zomapAlias : InstAlias<"memb($Rs32) -= #$II", (L4_isub_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_isub_memoph_zomapAlias : InstAlias<"memh($Rs32) -= #$II", (L4_isub_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_isub_memopw_zomapAlias : InstAlias<"memw($Rs32) -= #$II", (L4_isub_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_or_memopb_zomapAlias : InstAlias<"memb($Rs32) |= $Rt32", (L4_or_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_or_memoph_zomapAlias : InstAlias<"memh($Rs32) |= $Rt32", (L4_or_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_or_memopw_zomapAlias : InstAlias<"memw($Rs32) |= $Rt32", (L4_or_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_return_map_to_raw_fAlias : InstAlias<"if (!$Pv4) dealloc_return", (L4_return_f D15, PredRegs:$Pv4, R30)>;
+def L4_return_map_to_raw_fnew_pntAlias : InstAlias<"if (!$Pv4.new) dealloc_return:nt", (L4_return_fnew_pnt D15, PredRegs:$Pv4, R30)>;
+def L4_return_map_to_raw_fnew_ptAlias : InstAlias<"if (!$Pv4.new) dealloc_return:t", (L4_return_fnew_pt D15, PredRegs:$Pv4, R30)>;
+def L4_return_map_to_raw_tAlias : InstAlias<"if ($Pv4) dealloc_return", (L4_return_t D15, PredRegs:$Pv4, R30)>;
+def L4_return_map_to_raw_tnew_pntAlias : InstAlias<"if ($Pv4.new) dealloc_return:nt", (L4_return_tnew_pnt D15, PredRegs:$Pv4, R30)>;
+def L4_return_map_to_raw_tnew_ptAlias : InstAlias<"if ($Pv4.new) dealloc_return:t", (L4_return_tnew_pt D15, PredRegs:$Pv4, R30)>;
+def L4_sub_memopb_zomapAlias : InstAlias<"memb($Rs32) -= $Rt32", (L4_sub_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_sub_memoph_zomapAlias : InstAlias<"memh($Rs32) -= $Rt32", (L4_sub_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_sub_memopw_zomapAlias : InstAlias<"memw($Rs32) -= $Rt32", (L4_sub_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L6_deallocframe_map_to_rawAlias : InstAlias<"deallocframe", (L2_deallocframe D15, R30)>;
+def L6_return_map_to_rawAlias : InstAlias<"dealloc_return", (L4_return D15, R30)>;
+def M2_mpyuiAlias : InstAlias<"$Rd32 = mpyui($Rs32,$Rt32)", (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32)>;
+def S2_pstorerbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32) = $Rt32", (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerbnewf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32) = $Nt8.new", (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerbnewt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32) = $Nt8.new", (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32) = $Rt32", (S2_pstorerbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerdf_zomapAlias : InstAlias<"if (!$Pv4) memd($Rs32) = $Rtt32", (S2_pstorerdf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
+def S2_pstorerdt_zomapAlias : InstAlias<"if ($Pv4) memd($Rs32) = $Rtt32", (S2_pstorerdt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
+def S2_pstorerff_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32) = $Rt32.h", (S2_pstorerff_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerft_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32) = $Rt32.h", (S2_pstorerft_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32) = $Rt32", (S2_pstorerhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerhnewf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32) = $Nt8.new", (S2_pstorerhnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerhnewt_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32) = $Nt8.new", (S2_pstorerhnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32) = $Rt32", (S2_pstorerht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32) = $Rt32", (S2_pstorerif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerinewf_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32) = $Nt8.new", (S2_pstorerinewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerinewt_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32) = $Nt8.new", (S2_pstorerinewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32) = $Rt32", (S2_pstorerit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_storerb_zomapAlias : InstAlias<"memb($Rs32) = $Rt32", (S2_storerb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_storerbnew_zomapAlias : InstAlias<"memb($Rs32) = $Nt8.new", (S2_storerbnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_storerd_zomapAlias : InstAlias<"memd($Rs32) = $Rtt32", (S2_storerd_io IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
+def S2_storerf_zomapAlias : InstAlias<"memh($Rs32) = $Rt32.h", (S2_storerf_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_storerh_zomapAlias : InstAlias<"memh($Rs32) = $Rt32", (S2_storerh_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_storerhnew_zomapAlias : InstAlias<"memh($Rs32) = $Nt8.new", (S2_storerhnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_storeri_zomapAlias : InstAlias<"memw($Rs32) = $Rt32", (S2_storeri_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_storerinew_zomapAlias : InstAlias<"memw($Rs32) = $Nt8.new", (S2_storerinew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_tableidxb_goodsyntaxAlias : InstAlias<"$Rx32 = tableidxb($Rs32,#$Ii,#$II)", (S2_tableidxb IntRegs:$Rx32, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II)>;
+def S4_pstorerbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32) = $Rt32", (S4_pstorerbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerbnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32) = $Nt8.new", (S4_pstorerbnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstorerbnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32) = $Nt8.new", (S4_pstorerbnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstorerbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32) = $Rt32", (S4_pstorerbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerdfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memd($Rs32) = $Rtt32", (S4_pstorerdfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
+def S4_pstorerdtnew_zomapAlias : InstAlias<"if ($Pv4.new) memd($Rs32) = $Rtt32", (S4_pstorerdtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
+def S4_pstorerffnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32) = $Rt32.h", (S4_pstorerffnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerftnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32) = $Rt32.h", (S4_pstorerftnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32) = $Rt32", (S4_pstorerhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerhnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32) = $Nt8.new", (S4_pstorerhnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstorerhnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32) = $Nt8.new", (S4_pstorerhnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstorerhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32) = $Rt32", (S4_pstorerhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32) = $Rt32", (S4_pstorerifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerinewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32) = $Nt8.new", (S4_pstorerinewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstorerinewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32) = $Nt8.new", (S4_pstorerinewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstoreritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32) = $Rt32", (S4_pstoreritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_storeirb_zomapAlias : InstAlias<"memb($Rs32) = #$II", (S4_storeirb_io IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32) = #$II", (S4_storeirbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32) = #$II", (S4_storeirbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32) = #$II", (S4_storeirbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32) = #$II", (S4_storeirbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirh_zomapAlias : InstAlias<"memh($Rs32) = #$II", (S4_storeirh_io IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32) = #$II", (S4_storeirhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32) = #$II", (S4_storeirhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32) = #$II", (S4_storeirht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32) = #$II", (S4_storeirhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeiri_zomapAlias : InstAlias<"memw($Rs32) = #$II", (S4_storeiri_io IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32) = #$II", (S4_storeirif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32) = #$II", (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32) = #$II", (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeiritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32) = #$II", (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S6_allocframe_to_rawAlias : InstAlias<"allocframe(#$Ii)", (S2_allocframe R29, u11_3Imm:$Ii)>;
+def V6_MAP_equbAlias : InstAlias<"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equb_andAlias : InstAlias<"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equb_iorAlias : InstAlias<"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equb_xorAlias : InstAlias<"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equhAlias : InstAlias<"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equh_andAlias : InstAlias<"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equh_iorAlias : InstAlias<"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equh_xorAlias : InstAlias<"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equwAlias : InstAlias<"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equw_andAlias : InstAlias<"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equw_iorAlias : InstAlias<"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equw_xorAlias : InstAlias<"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_extractw_altAlias : InstAlias<"$Rd32.w = vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, HvxVR:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>;
+def V6_ld0Alias : InstAlias<"$Vd32 = vmem($Rt32)", (V6_vL32b_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldcnp0Alias : InstAlias<"if (!$Pv4) $Vd32.cur = vmem($Rt32)", (V6_vL32b_cur_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>;
+def V6_ldcnpnt0Alias : InstAlias<"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt", (V6_vL32b_nt_cur_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>;
+def V6_ldcp0Alias : InstAlias<"if ($Pv4) $Vd32.cur = vmem($Rt32)", (V6_vL32b_cur_pred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>;
+def V6_ldcpnt0Alias : InstAlias<"if ($Pv4) $Vd32.cur = vmem($Rt32):nt", (V6_vL32b_nt_cur_pred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>;
+def V6_ldnp0Alias : InstAlias<"if (!$Pv4) $Vd32 = vmem($Rt32)", (V6_vL32b_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>;
+def V6_ldnpnt0Alias : InstAlias<"if (!$Pv4) $Vd32 = vmem($Rt32):nt", (V6_vL32b_nt_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>;
+def V6_ldnt0Alias : InstAlias<"$Vd32 = vmem($Rt32):nt", (V6_vL32b_nt_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldntnt0Alias : InstAlias<"$Vd32 = vmem($Rt32):nt", (V6_vL32b_nt_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>;
+def V6_ldp0Alias : InstAlias<"if ($Pv4) $Vd32 = vmem($Rt32)", (V6_vL32b_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldpnt0Alias : InstAlias<"if ($Pv4) $Vd32 = vmem($Rt32):nt", (V6_vL32b_nt_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldtnp0Alias : InstAlias<"if (!$Pv4) $Vd32.tmp = vmem($Rt32)", (V6_vL32b_npred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldtnpnt0Alias : InstAlias<"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt", (V6_vL32b_nt_npred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldtp0Alias : InstAlias<"if ($Pv4) $Vd32.tmp = vmem($Rt32)", (V6_vL32b_tmp_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldtpnt0Alias : InstAlias<"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt", (V6_vL32b_nt_tmp_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldu0Alias : InstAlias<"$Vd32 = vmemu($Rt32)", (V6_vL32Ub_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_st0Alias : InstAlias<"vmem($Rt32) = $Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stn0Alias : InstAlias<"vmem($Rt32) = $Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8)>, Requires<[UseHVX]>;
+def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt = $Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8)>, Requires<[UseHVX]>;
+def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32) = $Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32) = $Vs32", (V6_vS32b_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32) = $Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32) = $Vs32", (V6_vS32b_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stu0Alias : InstAlias<"vmemu($Rt32) = $Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32) = $Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32) = $Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
+def V6_vabsb_altAlias : InstAlias<"$Vd32 = vabsb($Vu32)", (V6_vabsb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsb_sat_altAlias : InstAlias<"$Vd32 = vabsb($Vu32):sat", (V6_vabsb_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsdiffh_altAlias : InstAlias<"$Vd32 = vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsdiffub_altAlias : InstAlias<"$Vd32 = vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32 = vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsdiffw_altAlias : InstAlias<"$Vd32 = vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsh_altAlias : InstAlias<"$Vd32 = vabsh($Vu32)", (V6_vabsh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsh_sat_altAlias : InstAlias<"$Vd32 = vabsh($Vu32):sat", (V6_vabsh_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsub_altAlias : InstAlias<"$Vd32.ub = vabs($Vu32.b)", (V6_vabsb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh = vabs($Vu32.h)", (V6_vabsh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw = vabs($Vu32.w)", (V6_vabsw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsw_altAlias : InstAlias<"$Vd32 = vabsw($Vu32)", (V6_vabsw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsw_sat_altAlias : InstAlias<"$Vd32 = vabsw($Vu32):sat", (V6_vabsw_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddb_altAlias : InstAlias<"$Vd32 = vaddb($Vu32,$Vv32)", (V6_vaddb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32 = vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b += $Vu32.b", (V6_vaddbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b += $Vu32.b", (V6_vaddbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddbsat_altAlias : InstAlias<"$Vd32 = vaddb($Vu32,$Vv32):sat", (V6_vaddbsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddbsat_dv_altAlias : InstAlias<"$Vdd32 = vaddb($Vuu32,$Vvv32):sat", (V6_vaddbsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddh_altAlias : InstAlias<"$Vd32 = vaddh($Vu32,$Vv32)", (V6_vaddh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32 = vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h += $Vu32.h", (V6_vaddhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h += $Vu32.h", (V6_vaddhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddhsat_altAlias : InstAlias<"$Vd32 = vaddh($Vu32,$Vv32):sat", (V6_vaddhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32 = vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddhw_acc_altAlias : InstAlias<"$Vxx32 += vaddh($Vu32,$Vv32)", (V6_vaddhw_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddhw_altAlias : InstAlias<"$Vdd32 = vaddh($Vu32,$Vv32)", (V6_vaddhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddubh_acc_altAlias : InstAlias<"$Vxx32 += vaddub($Vu32,$Vv32)", (V6_vaddubh_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddubh_altAlias : InstAlias<"$Vdd32 = vaddub($Vu32,$Vv32)", (V6_vaddubh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddubsat_altAlias : InstAlias<"$Vd32 = vaddub($Vu32,$Vv32):sat", (V6_vaddubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32 = vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vadduhsat_altAlias : InstAlias<"$Vd32 = vadduh($Vu32,$Vv32):sat", (V6_vadduhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32 = vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vadduhw_acc_altAlias : InstAlias<"$Vxx32 += vadduh($Vu32,$Vv32)", (V6_vadduhw_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vadduhw_altAlias : InstAlias<"$Vdd32 = vadduh($Vu32,$Vv32)", (V6_vadduhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vadduwsat_altAlias : InstAlias<"$Vd32 = vadduw($Vu32,$Vv32):sat", (V6_vadduwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vadduwsat_dv_altAlias : InstAlias<"$Vdd32 = vadduw($Vuu32,$Vvv32):sat", (V6_vadduwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddw_altAlias : InstAlias<"$Vd32 = vaddw($Vu32,$Vv32)", (V6_vaddw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32 = vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w += $Vu32.w", (V6_vaddwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w += $Vu32.w", (V6_vaddwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddwsat_altAlias : InstAlias<"$Vd32 = vaddw($Vu32,$Vv32):sat", (V6_vaddwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32 = vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vandnqrt_acc_altAlias : InstAlias<"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)", (V6_vandnqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandnqrt_altAlias : InstAlias<"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)", (V6_vandnqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc HvxQR:$Qx4, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt HvxQR:$Qd4, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslh_acc_altAlias : InstAlias<"$Vx32 += vaslh($Vu32,$Rt32)", (V6_vaslh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslh_altAlias : InstAlias<"$Vd32 = vaslh($Vu32,$Rt32)", (V6_vaslh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslhv_altAlias : InstAlias<"$Vd32 = vaslh($Vu32,$Vv32)", (V6_vaslhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaslw_acc_altAlias : InstAlias<"$Vx32 += vaslw($Vu32,$Rt32)", (V6_vaslw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslw_altAlias : InstAlias<"$Vd32 = vaslw($Vu32,$Rt32)", (V6_vaslw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslwv_altAlias : InstAlias<"$Vd32 = vaslw($Vu32,$Vv32)", (V6_vaslwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vasrh_acc_altAlias : InstAlias<"$Vx32 += vasrh($Vu32,$Rt32)", (V6_vasrh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vasrh_altAlias : InstAlias<"$Vd32 = vasrh($Vu32,$Rt32)", (V6_vasrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrhubsat_altAlias : InstAlias<"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrhv_altAlias : InstAlias<"$Vd32 = vasrh($Vu32,$Vv32)", (V6_vasrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vasrw_acc_altAlias : InstAlias<"$Vx32 += vasrw($Vu32,$Rt32)", (V6_vasrw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vasrw_altAlias : InstAlias<"$Vd32 = vasrw($Vu32,$Rt32)", (V6_vasrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vasrwh_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrwhsat_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrwv_altAlias : InstAlias<"$Vd32 = vasrw($Vu32,$Vv32)", (V6_vasrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgb_altAlias : InstAlias<"$Vd32 = vavgb($Vu32,$Vv32)", (V6_vavgb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgbrnd_altAlias : InstAlias<"$Vd32 = vavgb($Vu32,$Vv32):rnd", (V6_vavgbrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgh_altAlias : InstAlias<"$Vd32 = vavgh($Vu32,$Vv32)", (V6_vavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavghrnd_altAlias : InstAlias<"$Vd32 = vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgub_altAlias : InstAlias<"$Vd32 = vavgub($Vu32,$Vv32)", (V6_vavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgubrnd_altAlias : InstAlias<"$Vd32 = vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavguh_altAlias : InstAlias<"$Vd32 = vavguh($Vu32,$Vv32)", (V6_vavguh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavguhrnd_altAlias : InstAlias<"$Vd32 = vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavguw_altAlias : InstAlias<"$Vd32 = vavguw($Vu32,$Vv32)", (V6_vavguw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavguwrnd_altAlias : InstAlias<"$Vd32 = vavguw($Vu32,$Vv32):rnd", (V6_vavguwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgw_altAlias : InstAlias<"$Vd32 = vavgw($Vu32,$Vv32)", (V6_vavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgwrnd_altAlias : InstAlias<"$Vd32 = vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vcl0h_altAlias : InstAlias<"$Vd32 = vcl0h($Vu32)", (V6_vcl0h HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vcl0w_altAlias : InstAlias<"$Vd32 = vcl0w($Vu32)", (V6_vcl0w HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vd0Alias : InstAlias<"$Vd32 = #0", (V6_vxor HvxVR:$Vd32, HvxVR:$Vd32, HvxVR:$Vd32)>, Requires<[UseHVX]>;
+def V6_vdd0Alias : InstAlias<"$Vdd32 = #0", (V6_vsubw_dv HvxWR:$Vdd32, W15, W15)>, Requires<[UseHVX]>;
+def V6_vdealb4w_altAlias : InstAlias<"$Vd32 = vdealb4w($Vu32,$Vv32)", (V6_vdealb4w HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vdealb_altAlias : InstAlias<"$Vd32 = vdealb($Vu32)", (V6_vdealb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vdealh_altAlias : InstAlias<"$Vd32 = vdealh($Vu32)", (V6_vdealh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32 += vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_altAlias : InstAlias<"$Vd32 = vdmpybus($Vu32,$Rt32)", (V6_vdmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32 += vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32 = vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32 += vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_altAlias : InstAlias<"$Vd32 = vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32 += vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32 = vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32 += vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32 = vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32 += vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32 = vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32 += vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32 = vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32 += vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdsaduh_altAlias : InstAlias<"$Vdd32 = vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vlsrh_altAlias : InstAlias<"$Vd32 = vlsrh($Vu32,$Rt32)", (V6_vlsrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vlsrhv_altAlias : InstAlias<"$Vd32 = vlsrh($Vu32,$Vv32)", (V6_vlsrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vlsrw_altAlias : InstAlias<"$Vd32 = vlsrw($Vu32,$Rt32)", (V6_vlsrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vlsrwv_altAlias : InstAlias<"$Vd32 = vlsrw($Vu32,$Vv32)", (V6_vlsrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxb_altAlias : InstAlias<"$Vd32 = vmaxb($Vu32,$Vv32)", (V6_vmaxb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxh_altAlias : InstAlias<"$Vd32 = vmaxh($Vu32,$Vv32)", (V6_vmaxh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxub_altAlias : InstAlias<"$Vd32 = vmaxub($Vu32,$Vv32)", (V6_vmaxub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxuh_altAlias : InstAlias<"$Vd32 = vmaxuh($Vu32,$Vv32)", (V6_vmaxuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxw_altAlias : InstAlias<"$Vd32 = vmaxw($Vu32,$Vv32)", (V6_vmaxw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminb_altAlias : InstAlias<"$Vd32 = vminb($Vu32,$Vv32)", (V6_vminb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminh_altAlias : InstAlias<"$Vd32 = vminh($Vu32,$Vv32)", (V6_vminh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminub_altAlias : InstAlias<"$Vd32 = vminub($Vu32,$Vv32)", (V6_vminub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminuh_altAlias : InstAlias<"$Vd32 = vminuh($Vu32,$Vv32)", (V6_vminuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminw_altAlias : InstAlias<"$Vd32 = vminw($Vu32,$Vv32)", (V6_vminw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32 += vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpabus_altAlias : InstAlias<"$Vdd32 = vmpabus($Vuu32,$Rt32)", (V6_vmpabus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpabusv_altAlias : InstAlias<"$Vdd32 = vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vmpabuu_acc_altAlias : InstAlias<"$Vxx32 += vmpabuu($Vuu32,$Rt32)", (V6_vmpabuu_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpabuu_altAlias : InstAlias<"$Vdd32 = vmpabuu($Vuu32,$Rt32)", (V6_vmpabuu HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32 = vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32 += vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpahb_altAlias : InstAlias<"$Vdd32 = vmpahb($Vuu32,$Rt32)", (V6_vmpahb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpauhb_acc_altAlias : InstAlias<"$Vxx32 += vmpauhb($Vuu32,$Rt32)", (V6_vmpauhb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpauhb_altAlias : InstAlias<"$Vdd32 = vmpauhb($Vuu32,$Rt32)", (V6_vmpauhb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32 += vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpybus_altAlias : InstAlias<"$Vdd32 = vmpybus($Vu32,$Rt32)", (V6_vmpybus HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32 += vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpybusv_altAlias : InstAlias<"$Vdd32 = vmpybus($Vu32,$Vv32)", (V6_vmpybusv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32 += vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpybv_altAlias : InstAlias<"$Vdd32 = vmpyb($Vu32,$Vv32)", (V6_vmpybv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyewuh_altAlias : InstAlias<"$Vd32 = vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyh_acc_altAlias : InstAlias<"$Vxx32 += vmpyh($Vu32,$Rt32)", (V6_vmpyh_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyh_altAlias : InstAlias<"$Vdd32 = vmpyh($Vu32,$Rt32)", (V6_vmpyh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32 += vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhss_altAlias : InstAlias<"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32 += vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhus_altAlias : InstAlias<"$Vdd32 = vmpyhus($Vu32,$Vv32)", (V6_vmpyhus HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32 += vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhv_altAlias : InstAlias<"$Vdd32 = vmpyh($Vu32,$Vv32)", (V6_vmpyhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32 += vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32 += vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32 = vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32 += vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyih_altAlias : InstAlias<"$Vd32 = vmpyih($Vu32,$Vv32)", (V6_vmpyih HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32 += vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyihb_altAlias : InstAlias<"$Vd32 = vmpyihb($Vu32,$Rt32)", (V6_vmpyihb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiowh_altAlias : InstAlias<"$Vd32 = vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32 += vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwb_altAlias : InstAlias<"$Vd32 = vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32 += vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwh_altAlias : InstAlias<"$Vd32 = vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwub_acc_altAlias : InstAlias<"$Vx32 += vmpyiwub($Vu32,$Rt32)", (V6_vmpyiwub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwub_altAlias : InstAlias<"$Vd32 = vmpyiwub($Vu32,$Rt32)", (V6_vmpyiwub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyowh_altAlias : InstAlias<"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32 += vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyub_altAlias : InstAlias<"$Vdd32 = vmpyub($Vu32,$Rt32)", (V6_vmpyub HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32 += vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyubv_altAlias : InstAlias<"$Vdd32 = vmpyub($Vu32,$Vv32)", (V6_vmpyubv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32 += vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyuh_altAlias : InstAlias<"$Vdd32 = vmpyuh($Vu32,$Rt32)", (V6_vmpyuh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32 += vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32 = vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnavgb_altAlias : InstAlias<"$Vd32 = vnavgb($Vu32,$Vv32)", (V6_vnavgb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnavgh_altAlias : InstAlias<"$Vd32 = vnavgh($Vu32,$Vv32)", (V6_vnavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnavgub_altAlias : InstAlias<"$Vd32 = vnavgub($Vu32,$Vv32)", (V6_vnavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnavgw_altAlias : InstAlias<"$Vd32 = vnavgw($Vu32,$Vv32)", (V6_vnavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnormamth_altAlias : InstAlias<"$Vd32 = vnormamth($Vu32)", (V6_vnormamth HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vnormamtw_altAlias : InstAlias<"$Vd32 = vnormamtw($Vu32)", (V6_vnormamtw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vpackeb_altAlias : InstAlias<"$Vd32 = vpackeb($Vu32,$Vv32)", (V6_vpackeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackeh_altAlias : InstAlias<"$Vd32 = vpackeh($Vu32,$Vv32)", (V6_vpackeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32 = vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32 = vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackob_altAlias : InstAlias<"$Vd32 = vpackob($Vu32,$Vv32)", (V6_vpackob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackoh_altAlias : InstAlias<"$Vd32 = vpackoh($Vu32,$Vv32)", (V6_vpackoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32 = vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32 = vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpopcounth_altAlias : InstAlias<"$Vd32 = vpopcounth($Vu32)", (V6_vpopcounth HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vrmpybub_rtt_acc_altAlias : InstAlias<"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)", (V6_vrmpybub_rtt_acc HvxWR:$Vxx32, HvxVR:$Vu32, DoubleRegs:$Rtt32)>, Requires<[UseHVX]>;
+def V6_vrmpybub_rtt_altAlias : InstAlias<"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)", (V6_vrmpybub_rtt HvxWR:$Vdd32, HvxVR:$Vu32, DoubleRegs:$Rtt32)>, Requires<[UseHVX]>;
+def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32 += vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpybus_altAlias : InstAlias<"$Vd32 = vrmpybus($Vu32,$Rt32)", (V6_vrmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32 += vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpybusv_altAlias : InstAlias<"$Vd32 = vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32 += vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpybv_altAlias : InstAlias<"$Vd32 = vrmpyb($Vu32,$Vv32)", (V6_vrmpybv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32 += vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpyub_altAlias : InstAlias<"$Vd32 = vrmpyub($Vu32,$Rt32)", (V6_vrmpyub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpyub_rtt_acc_altAlias : InstAlias<"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)", (V6_vrmpyub_rtt_acc HvxWR:$Vxx32, HvxVR:$Vu32, DoubleRegs:$Rtt32)>, Requires<[UseHVX]>;
+def V6_vrmpyub_rtt_altAlias : InstAlias<"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)", (V6_vrmpyub_rtt HvxWR:$Vdd32, HvxVR:$Vu32, DoubleRegs:$Rtt32)>, Requires<[UseHVX]>;
+def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32 += vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpyubv_altAlias : InstAlias<"$Vd32 = vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundhb_altAlias : InstAlias<"$Vd32 = vroundhb($Vu32,$Vv32):sat", (V6_vroundhb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundhub_altAlias : InstAlias<"$Vd32 = vroundhub($Vu32,$Vv32):sat", (V6_vroundhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrounduhub_altAlias : InstAlias<"$Vd32 = vrounduhub($Vu32,$Vv32):sat", (V6_vrounduhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrounduwuh_altAlias : InstAlias<"$Vd32 = vrounduwuh($Vu32,$Vv32):sat", (V6_vrounduwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundwh_altAlias : InstAlias<"$Vd32 = vroundwh($Vu32,$Vv32):sat", (V6_vroundwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundwuh_altAlias : InstAlias<"$Vd32 = vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrsadubi_altAlias : InstAlias<"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vsathub_altAlias : InstAlias<"$Vd32 = vsathub($Vu32,$Vv32)", (V6_vsathub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsatuwuh_altAlias : InstAlias<"$Vd32 = vsatuwuh($Vu32,$Vv32)", (V6_vsatuwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsatwh_altAlias : InstAlias<"$Vd32 = vsatwh($Vu32,$Vv32)", (V6_vsatwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsb_altAlias : InstAlias<"$Vdd32 = vsxtb($Vu32)", (V6_vsb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vscattermh_add_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h", (V6_vscattermh_add IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>;
+def V6_vscattermh_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", (V6_vscattermh IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>;
+def V6_vscattermhq_altAlias : InstAlias<"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", (V6_vscattermhq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>;
+def V6_vscattermw_add_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w", (V6_vscattermw_add IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>;
+def V6_vscattermw_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", (V6_vscattermw IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>;
+def V6_vscattermwh_add_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h", (V6_vscattermhw_add IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32)>, Requires<[UseHVX]>;
+def V6_vscattermwh_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", (V6_vscattermhw IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32)>, Requires<[UseHVX]>;
+def V6_vscattermwhq_altAlias : InstAlias<"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", (V6_vscattermhwq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32)>, Requires<[UseHVX]>;
+def V6_vscattermwq_altAlias : InstAlias<"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", (V6_vscattermwq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>;
+def V6_vsh_altAlias : InstAlias<"$Vdd32 = vsxth($Vu32)", (V6_vsh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vshufeh_altAlias : InstAlias<"$Vd32 = vshuffeh($Vu32,$Vv32)", (V6_vshufeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshuffb_altAlias : InstAlias<"$Vd32 = vshuffb($Vu32)", (V6_vshuffb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vshuffeb_altAlias : InstAlias<"$Vd32 = vshuffeb($Vu32,$Vv32)", (V6_vshuffeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshuffh_altAlias : InstAlias<"$Vd32 = vshuffh($Vu32)", (V6_vshuffh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vshuffob_altAlias : InstAlias<"$Vd32 = vshuffob($Vu32,$Vv32)", (V6_vshuffob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshufoeb_altAlias : InstAlias<"$Vdd32 = vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshufoeh_altAlias : InstAlias<"$Vdd32 = vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshufoh_altAlias : InstAlias<"$Vd32 = vshuffoh($Vu32,$Vv32)", (V6_vshufoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubb_altAlias : InstAlias<"$Vd32 = vsubb($Vu32,$Vv32)", (V6_vsubb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32 = vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b -= $Vu32.b", (V6_vsubbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b -= $Vu32.b", (V6_vsubbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubbsat_altAlias : InstAlias<"$Vd32 = vsubb($Vu32,$Vv32):sat", (V6_vsubbsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubbsat_dv_altAlias : InstAlias<"$Vdd32 = vsubb($Vuu32,$Vvv32):sat", (V6_vsubbsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubh_altAlias : InstAlias<"$Vd32 = vsubh($Vu32,$Vv32)", (V6_vsubh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32 = vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h -= $Vu32.h", (V6_vsubhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h -= $Vu32.h", (V6_vsubhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubhsat_altAlias : InstAlias<"$Vd32 = vsubh($Vu32,$Vv32):sat", (V6_vsubhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32 = vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubhw_altAlias : InstAlias<"$Vdd32 = vsubh($Vu32,$Vv32)", (V6_vsubhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsububh_altAlias : InstAlias<"$Vdd32 = vsubub($Vu32,$Vv32)", (V6_vsububh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsububsat_altAlias : InstAlias<"$Vd32 = vsubub($Vu32,$Vv32):sat", (V6_vsububsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32 = vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubuhsat_altAlias : InstAlias<"$Vd32 = vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubuhw_altAlias : InstAlias<"$Vdd32 = vsubuh($Vu32,$Vv32)", (V6_vsubuhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubuwsat_altAlias : InstAlias<"$Vd32 = vsubuw($Vu32,$Vv32):sat", (V6_vsubuwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubuwsat_dv_altAlias : InstAlias<"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat", (V6_vsubuwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubw_altAlias : InstAlias<"$Vd32 = vsubw($Vu32,$Vv32)", (V6_vsubw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32 = vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w -= $Vu32.w", (V6_vsubwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w -= $Vu32.w", (V6_vsubwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubwsat_altAlias : InstAlias<"$Vd32 = vsubw($Vu32,$Vv32):sat", (V6_vsubwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32 = vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32 += vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpyb_altAlias : InstAlias<"$Vdd32 = vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32 += vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpybus_altAlias : InstAlias<"$Vdd32 = vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32 += vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtran2x2_mapAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vunpackb_altAlias : InstAlias<"$Vdd32 = vunpackb($Vu32)", (V6_vunpackb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackh_altAlias : InstAlias<"$Vdd32 = vunpackh($Vu32)", (V6_vunpackh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackoh_altAlias : InstAlias<"$Vxx32 |= vunpackoh($Vu32)", (V6_vunpackoh HvxWR:$Vxx32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackub_altAlias : InstAlias<"$Vdd32 = vunpackub($Vu32)", (V6_vunpackub HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackuh_altAlias : InstAlias<"$Vdd32 = vunpackuh($Vu32)", (V6_vunpackuh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vzb_altAlias : InstAlias<"$Vdd32 = vzxtb($Vu32)", (V6_vzb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
+def V6_vzh_altAlias : InstAlias<"$Vdd32 = vzxth($Vu32)", (V6_vzh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
 def Y2_dcfetchAlias : InstAlias<"dcfetch($Rs32)", (Y2_dcfetchbo IntRegs:$Rs32, 0)>;
diff --git a/lib/Target/Hexagon/HexagonDepOperands.td b/lib/Target/Hexagon/HexagonDepOperands.td
index 0e83b2678732..9d960953f8f5 100644
--- a/lib/Target/Hexagon/HexagonDepOperands.td
+++ b/lib/Target/Hexagon/HexagonDepOperands.td
@@ -1,4 +1,4 @@
-//===--- HexagonDepOperands.td --------------------------------------------===//
+//===- HexagonDepOperands.td ----------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,10 +6,10 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
 
-def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; }
-def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; }
-def s3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 0>(N->getSExtValue());}]>;
 def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; }
 def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; }
 def s4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
@@ -61,6 +61,9 @@ def u1_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<1, 0>(N->getSExtVal
 def s31_1ImmOperand : AsmOperandClass { let Name = "s31_1Imm"; let RenderMethod = "addSignedImmOperands"; }
 def s31_1Imm : Operand<i32> { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1ImmDecoder"; }
 def s31_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 1>(N->getSExtValue());}]>;
+def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; }
+def s3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 0>(N->getSExtValue());}]>;
 def s30_2ImmOperand : AsmOperandClass { let Name = "s30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
 def s30_2Imm : Operand<i32> { let ParserMatchClass = s30_2ImmOperand; let DecoderMethod = "s30_2ImmDecoder"; }
 def s30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
diff --git a/lib/Target/Hexagon/HexagonDepTimingClasses.h b/lib/Target/Hexagon/HexagonDepTimingClasses.h
index 52963034543d..656c83f2d0c4 100644
--- a/lib/Target/Hexagon/HexagonDepTimingClasses.h
+++ b/lib/Target/Hexagon/HexagonDepTimingClasses.h
@@ -1,4 +1,4 @@
-//===--- HexagonDepTimingClasses.h ----------------------------------------===//
+//===- HexagonDepTimingClasses.h ------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,127 +6,134 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
+
+
+#ifndef TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
+#define TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
 
-static bool is_TC3x(unsigned SchedClass) {
+#include "HexagonInstrInfo.h"
+
+namespace llvm {
+
+inline bool is_TC3x(unsigned SchedClass) {
   switch (SchedClass) {
-  case Hexagon::Sched::tc_1000eb10:
-  case Hexagon::Sched::tc_2aaab1e0:
-  case Hexagon::Sched::tc_4997da4a:
-  case Hexagon::Sched::tc_5d806107:
-  case Hexagon::Sched::tc_6264c5e0:
-  case Hexagon::Sched::tc_69bb508b:
-  case Hexagon::Sched::tc_8c8041e6:
-  case Hexagon::Sched::tc_8cb685d9:
-  case Hexagon::Sched::tc_a12a5971:
-  case Hexagon::Sched::tc_ae0722f7:
-  case Hexagon::Sched::tc_ae2c2dc2:
-  case Hexagon::Sched::tc_bc5561d8:
-  case Hexagon::Sched::tc_d6a805a8:
-  case Hexagon::Sched::tc_f055fbb6:
-  case Hexagon::Sched::tc_feb4974b:
+  case Hexagon::Sched::tc_16d0d8d5:
+  case Hexagon::Sched::tc_1853ea6d:
+  case Hexagon::Sched::tc_60571023:
+  case Hexagon::Sched::tc_7934b9df:
+  case Hexagon::Sched::tc_8fd5f294:
+  case Hexagon::Sched::tc_b9c0b731:
+  case Hexagon::Sched::tc_bcc96cee:
+  case Hexagon::Sched::tc_c6ce9b3f:
+  case Hexagon::Sched::tc_c6ebf8dd:
+  case Hexagon::Sched::tc_c82dc1ff:
+  case Hexagon::Sched::tc_caaebcba:
+  case Hexagon::Sched::tc_cf59f215:
+  case Hexagon::Sched::tc_e913dc32:
     return true;
   default:
     return false;
   }
 }
 
-static bool is_TC2early(unsigned SchedClass) {
+inline bool is_TC2early(unsigned SchedClass) {
   switch (SchedClass) {
-  case Hexagon::Sched::tc_35fb9d13:
-  case Hexagon::Sched::tc_cbe45117:
+  case Hexagon::Sched::tc_14cd4cfa:
+  case Hexagon::Sched::tc_2a160009:
     return true;
   default:
     return false;
   }
 }
 
-static bool is_TC4x(unsigned SchedClass) {
+inline bool is_TC4x(unsigned SchedClass) {
   switch (SchedClass) {
-  case Hexagon::Sched::tc_09c86199:
-  case Hexagon::Sched::tc_2d1e6f5c:
-  case Hexagon::Sched::tc_2e55aa16:
-  case Hexagon::Sched::tc_3bea1824:
-  case Hexagon::Sched::tc_e836c161:
-  case Hexagon::Sched::tc_f1aa2cdb:
+  case Hexagon::Sched::tc_038a1342:
+  case Hexagon::Sched::tc_4d99bca9:
+  case Hexagon::Sched::tc_6792d5ff:
+  case Hexagon::Sched::tc_9c00ce8d:
+  case Hexagon::Sched::tc_d580173f:
+  case Hexagon::Sched::tc_f3eaa14b:
     return true;
   default:
     return false;
   }
 }
 
-static bool is_TC2(unsigned SchedClass) {
+inline bool is_TC2(unsigned SchedClass) {
   switch (SchedClass) {
-  case Hexagon::Sched::tc_090485bb:
-  case Hexagon::Sched::tc_1fe8323c:
-  case Hexagon::Sched::tc_37326008:
-  case Hexagon::Sched::tc_3c10f809:
-  case Hexagon::Sched::tc_47ab9233:
-  case Hexagon::Sched::tc_485bb57c:
-  case Hexagon::Sched::tc_511f28f6:
-  case Hexagon::Sched::tc_583510c7:
-  case Hexagon::Sched::tc_63cd9d2d:
-  case Hexagon::Sched::tc_76c4c5ef:
-  case Hexagon::Sched::tc_7ca2ea10:
-  case Hexagon::Sched::tc_87601822:
-  case Hexagon::Sched::tc_88fa2da6:
-  case Hexagon::Sched::tc_94e6ffd9:
-  case Hexagon::Sched::tc_ab1b5e74:
-  case Hexagon::Sched::tc_b0f50e3c:
-  case Hexagon::Sched::tc_bd16579e:
-  case Hexagon::Sched::tc_c0cd91a8:
-  case Hexagon::Sched::tc_ca280e8b:
-  case Hexagon::Sched::tc_cd321066:
-  case Hexagon::Sched::tc_d95f4e98:
-  case Hexagon::Sched::tc_e17ce9ad:
-  case Hexagon::Sched::tc_f1240c08:
-  case Hexagon::Sched::tc_faab1248:
+  case Hexagon::Sched::tc_00afc57e:
+  case Hexagon::Sched::tc_1b9c9ee5:
+  case Hexagon::Sched::tc_234a11a5:
+  case Hexagon::Sched::tc_2b6f77c6:
+  case Hexagon::Sched::tc_41d5298e:
+  case Hexagon::Sched::tc_5ba5997d:
+  case Hexagon::Sched::tc_84df2cd3:
+  case Hexagon::Sched::tc_87735c3b:
+  case Hexagon::Sched::tc_897d1a9d:
+  case Hexagon::Sched::tc_976ddc4f:
+  case Hexagon::Sched::tc_b44c6e2a:
+  case Hexagon::Sched::tc_b9c4623f:
+  case Hexagon::Sched::tc_c2f7d806:
+  case Hexagon::Sched::tc_c74f796f:
+  case Hexagon::Sched::tc_d088982c:
+  case Hexagon::Sched::tc_ef84f62f:
+  case Hexagon::Sched::tc_f49e76f4:
     return true;
   default:
     return false;
   }
 }
 
-static bool is_TC1(unsigned SchedClass) {
+inline bool is_TC1(unsigned SchedClass) {
   switch (SchedClass) {
-  case Hexagon::Sched::tc_07ac815d:
-  case Hexagon::Sched::tc_1b6011fb:
-  case Hexagon::Sched::tc_1b834fe7:
-  case Hexagon::Sched::tc_1e062b18:
-  case Hexagon::Sched::tc_1f9668cc:
-  case Hexagon::Sched::tc_43068634:
-  case Hexagon::Sched::tc_47f0b7ad:
-  case Hexagon::Sched::tc_537e2013:
-  case Hexagon::Sched::tc_548f402d:
-  case Hexagon::Sched::tc_5fa2857c:
-  case Hexagon::Sched::tc_5fe9fcd0:
-  case Hexagon::Sched::tc_78b3c689:
-  case Hexagon::Sched::tc_7c2dcd4d:
-  case Hexagon::Sched::tc_81a23d44:
-  case Hexagon::Sched::tc_821c4233:
-  case Hexagon::Sched::tc_92d1833c:
-  case Hexagon::Sched::tc_9a13af9d:
-  case Hexagon::Sched::tc_9c18c9a5:
-  case Hexagon::Sched::tc_9df8b0dc:
-  case Hexagon::Sched::tc_9f518242:
-  case Hexagon::Sched::tc_a1fb80e1:
-  case Hexagon::Sched::tc_a333d2a9:
-  case Hexagon::Sched::tc_a87879e8:
-  case Hexagon::Sched::tc_aad55963:
-  case Hexagon::Sched::tc_b08b653e:
-  case Hexagon::Sched::tc_b324366f:
-  case Hexagon::Sched::tc_b5bfaa60:
-  case Hexagon::Sched::tc_b86c7e8b:
-  case Hexagon::Sched::tc_c58f771a:
-  case Hexagon::Sched::tc_d108a090:
-  case Hexagon::Sched::tc_d1b5a4b6:
-  case Hexagon::Sched::tc_d2609065:
-  case Hexagon::Sched::tc_d63b71d1:
-  case Hexagon::Sched::tc_e2c31426:
-  case Hexagon::Sched::tc_e8c7a357:
-  case Hexagon::Sched::tc_eb07ef6f:
-  case Hexagon::Sched::tc_f16d5b17:
+  case Hexagon::Sched::tc_181af5d0:
+  case Hexagon::Sched::tc_1b82a277:
+  case Hexagon::Sched::tc_1e856f58:
+  case Hexagon::Sched::tc_351fed2d:
+  case Hexagon::Sched::tc_3669266a:
+  case Hexagon::Sched::tc_3cb8ea06:
+  case Hexagon::Sched::tc_452f85af:
+  case Hexagon::Sched::tc_481e5e5c:
+  case Hexagon::Sched::tc_49eb22c8:
+  case Hexagon::Sched::tc_523fcf30:
+  case Hexagon::Sched::tc_52d7bbea:
+  case Hexagon::Sched::tc_53bc8a6a:
+  case Hexagon::Sched::tc_540fdfbc:
+  case Hexagon::Sched::tc_55050d58:
+  case Hexagon::Sched::tc_609d2efe:
+  case Hexagon::Sched::tc_68cb12ce:
+  case Hexagon::Sched::tc_6ebb4a12:
+  case Hexagon::Sched::tc_6efc556e:
+  case Hexagon::Sched::tc_73043bf4:
+  case Hexagon::Sched::tc_7a830544:
+  case Hexagon::Sched::tc_855b0b61:
+  case Hexagon::Sched::tc_8fe6b782:
+  case Hexagon::Sched::tc_90f3e30c:
+  case Hexagon::Sched::tc_97743097:
+  case Hexagon::Sched::tc_99be14ca:
+  case Hexagon::Sched::tc_9faf76ae:
+  case Hexagon::Sched::tc_a46f0df5:
+  case Hexagon::Sched::tc_a904d137:
+  case Hexagon::Sched::tc_b9488031:
+  case Hexagon::Sched::tc_be706f30:
+  case Hexagon::Sched::tc_c6aa82f7:
+  case Hexagon::Sched::tc_cde8b071:
+  case Hexagon::Sched::tc_d6bf0472:
+  case Hexagon::Sched::tc_dbdffe3d:
+  case Hexagon::Sched::tc_e0739b8c:
+  case Hexagon::Sched::tc_e1e99bfa:
+  case Hexagon::Sched::tc_e9fae2d6:
+  case Hexagon::Sched::tc_f2704b9a:
+  case Hexagon::Sched::tc_f8eeed7a:
     return true;
   default:
     return false;
   }
 }
+} // namespace llvm
+
+#endif
diff --git a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index 80361015e649..0f1b9a4733c5 100644
--- a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonEarlyIfConv.cpp -------------------------------------------===//
+//===- HexagonEarlyIfConv.cpp ---------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -25,39 +25,39 @@
 //
 // Example:
 //
-//         %vreg40<def> = L2_loadrub_io %vreg39<kill>, 1
-//         %vreg41<def> = S2_tstbit_i %vreg40<kill>, 0
-//         J2_jumpt %vreg41<kill>, <BB#5>, %PC<imp-def,dead>
-//         J2_jump <BB#4>, %PC<imp-def,dead>
-//     Successors according to CFG: BB#4(62) BB#5(62)
+//         %40 = L2_loadrub_io killed %39, 1
+//         %41 = S2_tstbit_i killed %40, 0
+//         J2_jumpt killed %41, <%bb.5>, implicit dead %pc
+//         J2_jump <%bb.4>, implicit dead %pc
+//     Successors according to CFG: %bb.4(62) %bb.5(62)
 //
-// BB#4: derived from LLVM BB %if.then
-//     Predecessors according to CFG: BB#3
-//         %vreg11<def> = A2_addp %vreg6, %vreg10
-//         S2_storerd_io %vreg32, 16, %vreg11
-//     Successors according to CFG: BB#5
+// %bb.4: derived from LLVM BB %if.then
+//     Predecessors according to CFG: %bb.3
+//         %11 = A2_addp %6, %10
+//         S2_storerd_io %32, 16, %11
+//     Successors according to CFG: %bb.5
 //
-// BB#5: derived from LLVM BB %if.end
-//     Predecessors according to CFG: BB#3 BB#4
-//         %vreg12<def> = PHI %vreg6, <BB#3>, %vreg11, <BB#4>
-//         %vreg13<def> = A2_addp %vreg7, %vreg12
-//         %vreg42<def> = C2_cmpeqi %vreg9, 10
-//         J2_jumpf %vreg42<kill>, <BB#3>, %PC<imp-def,dead>
-//         J2_jump <BB#6>, %PC<imp-def,dead>
-//     Successors according to CFG: BB#6(4) BB#3(124)
+// %bb.5: derived from LLVM BB %if.end
+//     Predecessors according to CFG: %bb.3 %bb.4
+//         %12 = PHI %6, <%bb.3>, %11, <%bb.4>
+//         %13 = A2_addp %7, %12
+//         %42 = C2_cmpeqi %9, 10
+//         J2_jumpf killed %42, <%bb.3>, implicit dead %pc
+//         J2_jump <%bb.6>, implicit dead %pc
+//     Successors according to CFG: %bb.6(4) %bb.3(124)
 //
 // would become:
 //
-//         %vreg40<def> = L2_loadrub_io %vreg39<kill>, 1
-//         %vreg41<def> = S2_tstbit_i %vreg40<kill>, 0
-// spec->  %vreg11<def> = A2_addp %vreg6, %vreg10
-// pred->  S2_pstorerdf_io %vreg41, %vreg32, 16, %vreg11
-//         %vreg46<def> = PS_pselect %vreg41, %vreg6, %vreg11
-//         %vreg13<def> = A2_addp %vreg7, %vreg46
-//         %vreg42<def> = C2_cmpeqi %vreg9, 10
-//         J2_jumpf %vreg42<kill>, <BB#3>, %PC<imp-def,dead>
-//         J2_jump <BB#6>, %PC<imp-def,dead>
-//     Successors according to CFG: BB#6 BB#3
+//         %40 = L2_loadrub_io killed %39, 1
+//         %41 = S2_tstbit_i killed %40, 0
+// spec->  %11 = A2_addp %6, %10
+// pred->  S2_pstorerdf_io %41, %32, 16, %11
+//         %46 = PS_pselect %41, %6, %11
+//         %13 = A2_addp %7, %46
+//         %42 = C2_cmpeqi %9, 10
+//         J2_jumpf killed %42, <%bb.3>, implicit dead %pc
+//         J2_jump <%bb.6>, implicit dead %pc
+//     Successors according to CFG: %bb.6 %bb.3
 
 #include "Hexagon.h"
 #include "HexagonInstrInfo.h"
@@ -76,6 +76,7 @@
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/BranchProbability.h"
@@ -84,7 +85,6 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <cassert>
 #include <iterator>
 
@@ -99,17 +99,18 @@ namespace llvm {
 
 } // end namespace llvm
 
-namespace {
+static cl::opt<bool> EnableHexagonBP("enable-hexagon-br-prob", cl::Hidden,
+  cl::init(false), cl::desc("Enable branch probability info"));
+static cl::opt<unsigned> SizeLimit("eif-limit", cl::init(6), cl::Hidden,
+  cl::desc("Size limit in Hexagon early if-conversion"));
+static cl::opt<bool> SkipExitBranches("eif-no-loop-exit", cl::init(false),
+  cl::Hidden, cl::desc("Do not convert branches that may exit the loop"));
 
-  cl::opt<bool> EnableHexagonBP("enable-hexagon-br-prob", cl::Hidden,
-    cl::init(false), cl::desc("Enable branch probability info"));
-  cl::opt<unsigned> SizeLimit("eif-limit", cl::init(6), cl::Hidden,
-    cl::desc("Size limit in Hexagon early if-conversion"));
-  cl::opt<bool> SkipExitBranches("eif-no-loop-exit", cl::init(false),
-    cl::Hidden, cl::desc("Do not convert branches that may exit the loop"));
+namespace {
 
   struct PrintMB {
     PrintMB(const MachineBasicBlock *B) : MB(B) {}
+
     const MachineBasicBlock *MB;
   };
   raw_ostream &operator<< (raw_ostream &OS, const PrintMB &P) {
@@ -143,7 +144,7 @@ namespace {
                           const PrintFP &P) LLVM_ATTRIBUTE_UNUSED;
   raw_ostream &operator<<(raw_ostream &OS, const PrintFP &P) {
     OS << "{ SplitB:" << PrintMB(P.FP.SplitB)
-       << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI)
+       << ", PredR:" << printReg(P.FP.PredR, &P.TRI)
        << ", TrueB:" << PrintMB(P.FP.TrueB)
        << ", FalseB:" << PrintMB(P.FP.FalseB)
        << ", JoinB:" << PrintMB(P.FP.JoinB) << " }";
@@ -154,11 +155,7 @@ namespace {
   public:
     static char ID;
 
-    HexagonEarlyIfConversion() : MachineFunctionPass(ID),
-        HII(nullptr), TRI(nullptr), MFN(nullptr), MRI(nullptr), MDT(nullptr),
-        MLI(nullptr) {
-      initializeHexagonEarlyIfConversionPass(*PassRegistry::getPassRegistry());
-    }
+    HexagonEarlyIfConversion() : MachineFunctionPass(ID) {}
 
     StringRef getPassName() const override {
       return "Hexagon early if conversion";
@@ -175,7 +172,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
   private:
-    typedef DenseSet<MachineBasicBlock*> BlockSetType;
+    using BlockSetType = DenseSet<MachineBasicBlock *>;
 
     bool isPreheader(const MachineBasicBlock *B) const;
     bool matchFlowPattern(MachineBasicBlock *B, MachineLoop *L,
@@ -214,21 +211,21 @@ namespace {
     void mergeBlocks(MachineBasicBlock *PredB, MachineBasicBlock *SuccB);
     void simplifyFlowGraph(const FlowPattern &FP);
 
-    const HexagonInstrInfo *HII;
-    const TargetRegisterInfo *TRI;
-    MachineFunction *MFN;
-    MachineRegisterInfo *MRI;
-    MachineDominatorTree *MDT;
-    MachineLoopInfo *MLI;
+    const HexagonInstrInfo *HII = nullptr;
+    const TargetRegisterInfo *TRI = nullptr;
+    MachineFunction *MFN = nullptr;
+    MachineRegisterInfo *MRI = nullptr;
+    MachineDominatorTree *MDT = nullptr;
+    MachineLoopInfo *MLI = nullptr;
     BlockSetType Deleted;
     const MachineBranchProbabilityInfo *MBPI;
   };
 
-  char HexagonEarlyIfConversion::ID = 0;
-
 } // end anonymous namespace
 
-INITIALIZE_PASS(HexagonEarlyIfConversion, "hexagon-eif",
+char HexagonEarlyIfConversion::ID = 0;
+
+INITIALIZE_PASS(HexagonEarlyIfConversion, "hexagon-early-if",
   "Hexagon early if conversion", false, false)
 
 bool HexagonEarlyIfConversion::isPreheader(const MachineBasicBlock *B) const {
@@ -241,7 +238,7 @@ bool HexagonEarlyIfConversion::isPreheader(const MachineBasicBlock *B) const {
 
 bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
     MachineLoop *L, FlowPattern &FP) {
-  DEBUG(dbgs() << "Checking flow pattern at BB#" << B->getNumber() << "\n");
+  DEBUG(dbgs() << "Checking flow pattern at " << printMBBReference(*B) << "\n");
 
   // Interested only in conditional branches, no .new, no new-value, etc.
   // Check the terminators directly, it's easier than handling all responses
@@ -392,8 +389,7 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B)
         continue;
       switch (MRI->getRegClass(R)->getID()) {
         case Hexagon::PredRegsRegClassID:
-        case Hexagon::VecPredRegsRegClassID:
-        case Hexagon::VecPredRegs128BRegClassID:
+        case Hexagon::HvxQRRegClassID:
           break;
         default:
           continue;
@@ -540,7 +536,10 @@ bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const {
   auto TotalCount = [] (const MachineBasicBlock *B, unsigned &Spare) {
     if (!B)
       return 0u;
-    unsigned T = std::distance(B->begin(), B->getFirstTerminator());
+    unsigned T = std::count_if(B->begin(), B->getFirstTerminator(),
+                               [](const MachineInstr &MI) {
+                                 return !MI.isMetaInstruction();
+                               });
     if (T < HEXAGON_PACKET_SIZE)
       Spare += HEXAGON_PACKET_SIZE-T;
     return T;
@@ -593,7 +592,9 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B,
 
   // Visit all dominated blocks from the same loop first, then process B.
   MachineDomTreeNode *N = MDT->getNode(B);
-  typedef GraphTraits<MachineDomTreeNode*> GTN;
+
+  using GTN = GraphTraits<MachineDomTreeNode *>;
+
   // We will change CFG/DT during this traversal, so take precautions to
   // avoid problems related to invalidated iterators. In fact, processing
   // a child C of B cannot cause another child to be removed, but it can
@@ -601,7 +602,7 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B,
   // was removed. This new child C, however, would have been processed
   // prior to processing B, so there is no need to process it again.
   // Simply keep a list of children of B, and traverse that list.
-  typedef SmallVector<MachineDomTreeNode*,4> DTNodeVectType;
+  using DTNodeVectType = SmallVector<MachineDomTreeNode *, 4>;
   DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N));
   for (DTNodeVectType::iterator I = Cn.begin(), E = Cn.end(); I != E; ++I) {
     MachineBasicBlock *SB = (*I)->getBlock();
@@ -769,18 +770,12 @@ unsigned HexagonEarlyIfConversion::buildMux(MachineBasicBlock *B,
     case Hexagon::DoubleRegsRegClassID:
       Opc = Hexagon::PS_pselect;
       break;
-    case Hexagon::VectorRegsRegClassID:
+    case Hexagon::HvxVRRegClassID:
       Opc = Hexagon::PS_vselect;
       break;
-    case Hexagon::VecDblRegsRegClassID:
+    case Hexagon::HvxWRRegClassID:
       Opc = Hexagon::PS_wselect;
       break;
-    case Hexagon::VectorRegs128BRegClassID:
-      Opc = Hexagon::PS_vselect_128B;
-      break;
-    case Hexagon::VecDblRegs128BRegClassID:
-      Opc = Hexagon::PS_wselect_128B;
-      break;
     default:
       llvm_unreachable("unexpected register type");
   }
@@ -947,8 +942,10 @@ void HexagonEarlyIfConversion::removeBlock(MachineBasicBlock *B) {
   MachineDomTreeNode *IDN = N->getIDom();
   if (IDN) {
     MachineBasicBlock *IDB = IDN->getBlock();
-    typedef GraphTraits<MachineDomTreeNode*> GTN;
-    typedef SmallVector<MachineDomTreeNode*,4> DTNodeVectType;
+
+    using GTN = GraphTraits<MachineDomTreeNode *>;
+    using DTNodeVectType = SmallVector<MachineDomTreeNode *, 4>;
+
     DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N));
     for (DTNodeVectType::iterator I = Cn.begin(), E = Cn.end(); I != E; ++I) {
       MachineBasicBlock *SB = (*I)->getBlock();
@@ -1050,7 +1047,7 @@ void HexagonEarlyIfConversion::simplifyFlowGraph(const FlowPattern &FP) {
 }
 
 bool HexagonEarlyIfConversion::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   auto &ST = MF.getSubtarget<HexagonSubtarget>();
diff --git a/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index a2f6dd68c1a1..c2feaf5737b2 100644
--- a/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonExpandCondsets.cpp ----------------------------------------===//
+//===- HexagonExpandCondsets.cpp ------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -17,33 +17,33 @@
 //
 // Liveness tracking aside, the main functionality of this pass is divided
 // into two steps. The first step is to replace an instruction
-//   vreg0 = C2_mux vreg1, vreg2, vreg3
+//   %0 = C2_mux %1, %2, %3
 // with a pair of conditional transfers
-//   vreg0 = A2_tfrt vreg1, vreg2
-//   vreg0 = A2_tfrf vreg1, vreg3
+//   %0 = A2_tfrt %1, %2
+//   %0 = A2_tfrf %1, %3
 // It is the intention that the execution of this pass could be terminated
 // after this step, and the code generated would be functionally correct.
 //
-// If the uses of the source values vreg1 and vreg2 are kills, and their
+// If the uses of the source values %1 and %2 are kills, and their
 // definitions are predicable, then in the second step, the conditional
 // transfers will then be rewritten as predicated instructions. E.g.
-//   vreg0 = A2_or vreg1, vreg2
-//   vreg3 = A2_tfrt vreg99, vreg0<kill>
+//   %0 = A2_or %1, %2
+//   %3 = A2_tfrt %99, killed %0
 // will be rewritten as
-//   vreg3 = A2_port vreg99, vreg1, vreg2
+//   %3 = A2_port %99, %1, %2
 //
 // This replacement has two variants: "up" and "down". Consider this case:
-//   vreg0 = A2_or vreg1, vreg2
+//   %0 = A2_or %1, %2
 //   ... [intervening instructions] ...
-//   vreg3 = A2_tfrt vreg99, vreg0<kill>
+//   %3 = A2_tfrt %99, killed %0
 // variant "up":
-//   vreg3 = A2_port vreg99, vreg1, vreg2
-//   ... [intervening instructions, vreg0->vreg3] ...
+//   %3 = A2_port %99, %1, %2
+//   ... [intervening instructions, %0->vreg3] ...
 //   [deleted]
 // variant "down":
 //   [deleted]
 //   ... [intervening instructions] ...
-//   vreg3 = A2_port vreg99, vreg1, vreg2
+//   %3 = A2_port %99, %1, %2
 //
 // Both, one or none of these variants may be valid, and checks are made
 // to rule out inapplicable variants.
@@ -51,13 +51,13 @@
 // As an additional optimization, before either of the two steps above is
 // executed, the pass attempts to coalesce the target register with one of
 // the source registers, e.g. given an instruction
-//   vreg3 = C2_mux vreg0, vreg1, vreg2
-// vreg3 will be coalesced with either vreg1 or vreg2. If this succeeds,
+//   %3 = C2_mux %0, %1, %2
+// %3 will be coalesced with either %1 or %2. If this succeeds,
 // the instruction would then be (for example)
-//   vreg3 = C2_mux vreg0, vreg3, vreg2
+//   %3 = C2_mux %0, %3, %2
 // and, under certain circumstances, this could result in only one predicated
 // instruction:
-//   vreg3 = A2_tfrf vreg0, vreg2
+//   %3 = A2_tfrf %0, %2
 //
 
 // Splitting a definition of a register into two predicated transfers
@@ -65,18 +65,18 @@
 // will see both instructions as actual definitions, and will mark the
 // first one as dead. The definition is not actually dead, and this
 // situation will need to be fixed. For example:
-//   vreg1<def,dead> = A2_tfrt ...  ; marked as dead
-//   vreg1<def> = A2_tfrf ...
+//   dead %1 = A2_tfrt ...  ; marked as dead
+//   %1 = A2_tfrf ...
 //
 // Since any of the individual predicated transfers may end up getting
 // removed (in case it is an identity copy), some pre-existing def may
 // be marked as dead after live interval recomputation:
-//   vreg1<def,dead> = ...          ; marked as dead
+//   dead %1 = ...          ; marked as dead
 //   ...
-//   vreg1<def> = A2_tfrf ...       ; if A2_tfrt is removed
-// This case happens if vreg1 was used as a source in A2_tfrt, which means
+//   %1 = A2_tfrf ...       ; if A2_tfrt is removed
+// This case happens if %1 was used as a source in A2_tfrt, which means
 // that is it actually live at the A2_tfrf, and so the now dead definition
-// of vreg1 will need to be updated to non-dead at some point.
+// of %1 will need to be updated to non-dead at some point.
 //
 // This issue could be remedied by adding implicit uses to the predicated
 // transfers, but this will create a problem with subsequent predication,
@@ -87,12 +87,13 @@
 // to be added, and updating the live ranges will be more involved.
 
 #include "HexagonInstrInfo.h"
+#include "HexagonRegisterInfo.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/LiveInterval.h"
-#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -102,13 +103,16 @@
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/Function.h"
+#include "llvm/MC/LaneBitmask.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <cassert>
 #include <iterator>
 #include <set>
@@ -136,10 +140,7 @@ namespace {
   public:
     static char ID;
 
-    HexagonExpandCondsets() :
-        MachineFunctionPass(ID), HII(nullptr), TRI(nullptr), MRI(nullptr),
-        LIS(nullptr), CoaLimitActive(false),
-        TfrLimitActive(false), CoaCounter(0), TfrCounter(0) {
+    HexagonExpandCondsets() : MachineFunctionPass(ID) {
       if (OptCoaLimit.getPosition())
         CoaLimitActive = true, CoaLimit = OptCoaLimit;
       if (OptTfrLimit.getPosition())
@@ -161,14 +162,17 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
   private:
-    const HexagonInstrInfo *HII;
-    const TargetRegisterInfo *TRI;
+    const HexagonInstrInfo *HII = nullptr;
+    const TargetRegisterInfo *TRI = nullptr;
     MachineDominatorTree *MDT;
-    MachineRegisterInfo *MRI;
-    LiveIntervals *LIS;
-
-    bool CoaLimitActive, TfrLimitActive;
-    unsigned CoaLimit, TfrLimit, CoaCounter, TfrCounter;
+    MachineRegisterInfo *MRI = nullptr;
+    LiveIntervals *LIS = nullptr;
+    bool CoaLimitActive = false;
+    bool TfrLimitActive = false;
+    unsigned CoaLimit;
+    unsigned TfrLimit;
+    unsigned CoaCounter = 0;
+    unsigned TfrCounter = 0;
 
     struct RegisterRef {
       RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
@@ -186,9 +190,10 @@ namespace {
       unsigned Reg, Sub;
     };
 
-    typedef DenseMap<unsigned,unsigned> ReferenceMap;
+    using ReferenceMap = DenseMap<unsigned, unsigned>;
     enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
     enum { Exec_Then = 0x10, Exec_Else = 0x20 };
+
     unsigned getMaskForSub(unsigned Sub);
     bool isCondset(const MachineInstr &MI);
     LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
@@ -484,18 +489,33 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
     if (!HII->isPredicated(*DefI))
       continue;
     // Construct the set of all necessary implicit uses, based on the def
-    // operands in the instruction.
-    std::set<RegisterRef> ImpUses;
-    for (auto &Op : DefI->operands())
-      if (Op.isReg() && Op.isDef() && DefRegs.count(Op))
-        ImpUses.insert(Op);
+    // operands in the instruction. We need to tie the implicit uses to
+    // the corresponding defs.
+    std::map<RegisterRef,unsigned> ImpUses;
+    for (unsigned i = 0, e = DefI->getNumOperands(); i != e; ++i) {
+      MachineOperand &Op = DefI->getOperand(i);
+      if (!Op.isReg() || !DefRegs.count(Op))
+        continue;
+      if (Op.isDef()) {
+        ImpUses.insert({Op, i});
+      } else {
+        // This function can be called for the same register with different
+        // lane masks. If the def in this instruction was for the whole
+        // register, we can get here more than once. Avoid adding multiple
+        // implicit uses (or adding an implicit use when an explicit one is
+        // present).
+        ImpUses.erase(Op);
+      }
+    }
     if (ImpUses.empty())
       continue;
     MachineFunction &MF = *DefI->getParent()->getParent();
-    for (RegisterRef R : ImpUses)
+    for (std::pair<RegisterRef, unsigned> P : ImpUses) {
+      RegisterRef R = P.first;
       MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
+      DefI->tieOperands(P.second, DefI->getNumOperands()-1);
+    }
   }
-
 }
 
 void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
@@ -634,7 +654,7 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
       return false;
     TfrCounter++;
   }
-  DEBUG(dbgs() << "\nsplitting BB#" << MI.getParent()->getNumber() << ": "
+  DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) << ": "
                << MI);
   MachineOperand &MD = MI.getOperand(0);  // Definition
   MachineOperand &MP = MI.getOperand(1);  // Predicate register
@@ -740,8 +760,8 @@ MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
       if (RR.Reg != RD.Reg)
         continue;
       // If the "Reg" part agrees, there is still the subregister to check.
-      // If we are looking for vreg1:loreg, we can skip vreg1:hireg, but
-      // not vreg1 (w/o subregisters).
+      // If we are looking for %1:loreg, we can skip %1:hireg, but
+      // not %1 (w/o subregisters).
       if (RR.Sub == RD.Sub)
         return MI;
       if (RR.Sub == 0 || RD.Sub == 0)
@@ -1051,7 +1071,7 @@ bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
       bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs);
       if (!Done) {
         // If we didn't predicate I, we may need to remove it in case it is
-        // an "identity" copy, e.g.  vreg1 = A2_tfrt vreg2, vreg1.
+        // an "identity" copy, e.g.  %1 = A2_tfrt %2, %1.
         if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
           for (auto &Op : I->operands())
             if (Op.isReg())
@@ -1117,8 +1137,8 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
 
   DEBUG(dbgs() << "compatible registers: ("
                << (Overlap ? "overlap" : "disjoint") << ")\n  "
-               << PrintReg(R1.Reg, TRI, R1.Sub) << "  " << L1 << "\n  "
-               << PrintReg(R2.Reg, TRI, R2.Sub) << "  " << L2 << "\n");
+               << printReg(R1.Reg, TRI, R1.Sub) << "  " << L1 << "\n  "
+               << printReg(R2.Reg, TRI, R2.Sub) << "  " << L2 << "\n");
   if (R1.Sub || R2.Sub)
     return false;
   if (Overlap)
@@ -1133,7 +1153,7 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
   MRI->replaceRegWith(R2.Reg, R1.Reg);
 
   // Move all live segments from L2 to L1.
-  typedef DenseMap<VNInfo*,VNInfo*> ValueInfoMap;
+  using ValueInfoMap = DenseMap<VNInfo *, VNInfo *>;
   ValueInfoMap VM;
   for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
     VNInfo *NewVN, *OldVN = I->valno;
@@ -1178,18 +1198,18 @@ bool HexagonExpandCondsets::coalesceSegments(
     MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3);
     bool Done = false;
     // Consider this case:
-    //   vreg1 = instr1 ...
-    //   vreg2 = instr2 ...
-    //   vreg0 = C2_mux ..., vreg1, vreg2
-    // If vreg0 was coalesced with vreg1, we could end up with the following
+    //   %1 = instr1 ...
+    //   %2 = instr2 ...
+    //   %0 = C2_mux ..., %1, %2
+    // If %0 was coalesced with %1, we could end up with the following
     // code:
-    //   vreg0 = instr1 ...
-    //   vreg2 = instr2 ...
-    //   vreg0 = A2_tfrf ..., vreg2
+    //   %0 = instr1 ...
+    //   %2 = instr2 ...
+    //   %0 = A2_tfrf ..., %2
     // which will later become:
-    //   vreg0 = instr1 ...
-    //   vreg0 = instr2_cNotPt ...
-    // i.e. there will be an unconditional definition (instr1) of vreg0
+    //   %0 = instr1 ...
+    //   %0 = instr2_cNotPt ...
+    // i.e. there will be an unconditional definition (instr1) of %0
     // followed by a conditional one. The output dependency was there before
     // and it unavoidable, but if instr1 is predicable, we will no longer be
     // able to predicate it here.
@@ -1223,7 +1243,7 @@ bool HexagonExpandCondsets::coalesceSegments(
 }
 
 bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo());
@@ -1233,7 +1253,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
   MRI = &MF.getRegInfo();
 
   DEBUG(LIS->print(dbgs() << "Before expand-condsets\n",
-                   MF.getFunction()->getParent()));
+                   MF.getFunction().getParent()));
 
   bool Changed = false;
   std::set<unsigned> CoalUpd, PredUpd;
@@ -1261,7 +1281,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
           KillUpd.insert(Op.getReg());
   updateLiveness(KillUpd, false, true, false);
   DEBUG(LIS->print(dbgs() << "After coalescing\n",
-                   MF.getFunction()->getParent()));
+                   MF.getFunction().getParent()));
 
   // First, simply split all muxes into a pair of conditional transfers
   // and update the live intervals to reflect the new arrangement. The
@@ -1278,7 +1298,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
   // (because of predicated defs), so make sure they are left untouched.
   // Predication does not use live intervals.
   DEBUG(LIS->print(dbgs() << "After splitting\n",
-                   MF.getFunction()->getParent()));
+                   MF.getFunction().getParent()));
 
   // Traverse all blocks and collapse predicable instructions feeding
   // conditional transfers into predicated instructions.
@@ -1287,7 +1307,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
   for (auto &B : MF)
     Changed |= predicateInBlock(B, PredUpd);
   DEBUG(LIS->print(dbgs() << "After predicating\n",
-                   MF.getFunction()->getParent()));
+                   MF.getFunction().getParent()));
 
   PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
   updateLiveness(PredUpd, true, true, true);
@@ -1295,7 +1315,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
   DEBUG({
     if (Changed)
       LIS->print(dbgs() << "After expand-condsets\n",
-                 MF.getFunction()->getParent());
+                 MF.getFunction().getParent());
   });
 
   return Changed;
diff --git a/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
index 23d4e2610d9a..a842b672736c 100644
--- a/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
+++ b/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
@@ -19,8 +19,8 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/PassSupport.h"
-#include "llvm/Target/TargetInstrInfo.h"
 
 using namespace llvm;
 
@@ -89,7 +89,7 @@ static bool isHardwareLoop(const MachineInstr &MI) {
 }
 
 bool HexagonFixupHwLoops::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
   return fixupLoopInstrs(MF);
 }
@@ -138,7 +138,7 @@ bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) {
     MachineBasicBlock::iterator MIE = MBB.end();
     while (MII != MIE) {
       InstOffset += HII->getSize(*MII);
-      if (MII->isDebugValue()) {
+      if (MII->isMetaInstruction()) {
         ++MII;
         continue;
       }
diff --git a/lib/Target/Hexagon/HexagonFrameLowering.cpp b/lib/Target/Hexagon/HexagonFrameLowering.cpp
index e5e75198b2d1..65a2fc35b11b 100644
--- a/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -1,4 +1,4 @@
-//===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===//
+//===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -38,6 +38,8 @@
 #include "llvm/CodeGen/MachinePostDominators.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/IR/Attributes.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/Function.h"
 #include "llvm/MC/MCDwarf.h"
@@ -45,19 +47,19 @@
 #include "llvm/Pass.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetOptions.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
 #include <iterator>
 #include <limits>
 #include <map>
-#include <new>
 #include <utility>
 #include <vector>
 
@@ -223,7 +225,7 @@ namespace {
 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
   auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
   bool NeedCFI = MF.getMMI().hasDebugInfo() ||
-                 MF.getFunction()->needsUnwindTableEntry();
+                 MF.getFunction().needsUnwindTableEntry();
 
   if (!NeedCFI)
     return false;
@@ -334,6 +336,8 @@ static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
   /// in the block.
 static bool hasTailCall(const MachineBasicBlock &MBB) {
     MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
+    if (I == MBB.end())
+      return false;
     unsigned RetOpc = I->getOpcode();
     return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
 }
@@ -371,17 +375,17 @@ static bool isRestoreCall(unsigned Opc) {
 }
 
 static inline bool isOptNone(const MachineFunction &MF) {
-    return MF.getFunction()->hasFnAttribute(Attribute::OptimizeNone) ||
+    return MF.getFunction().hasFnAttribute(Attribute::OptimizeNone) ||
            MF.getTarget().getOptLevel() == CodeGenOpt::None;
 }
 
 static inline bool isOptSize(const MachineFunction &MF) {
-    const Function &F = *MF.getFunction();
+    const Function &F = MF.getFunction();
     return F.optForSize() && !F.optForMinSize();
 }
 
 static inline bool isMinSize(const MachineFunction &MF) {
-    return MF.getFunction()->optForMinSize();
+    return MF.getFunction().optForMinSize();
 }
 
 /// Implements shrink-wrapping of the stack frame. By default, stack frame
@@ -398,17 +402,17 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
     ShrinkCounter++;
   }
 
-  auto &HST = MF.getSubtarget<HexagonSubtarget>();
-  auto &HRI = *HST.getRegisterInfo();
+  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
 
   MachineDominatorTree MDT;
   MDT.runOnMachineFunction(MF);
   MachinePostDominatorTree MPT;
   MPT.runOnMachineFunction(MF);
 
-  typedef DenseMap<unsigned,unsigned> UnsignedMap;
+  using UnsignedMap = DenseMap<unsigned, unsigned>;
+  using RPOTType = ReversePostOrderTraversal<const MachineFunction *>;
+
   UnsignedMap RPO;
-  typedef ReversePostOrderTraversal<const MachineFunction*> RPOTType;
   RPOTType RPOT(&MF);
   unsigned RPON = 0;
   for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
@@ -441,7 +445,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
   DEBUG({
     dbgs() << "Blocks needing SF: {";
     for (auto &B : SFBlocks)
-      dbgs() << " BB#" << B->getNumber();
+      dbgs() << " " << printMBBReference(*B);
     dbgs() << " }\n";
   });
   // No frame needed?
@@ -462,12 +466,16 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
       break;
   }
   DEBUG({
-    dbgs() << "Computed dom block: BB#";
-    if (DomB) dbgs() << DomB->getNumber();
-    else      dbgs() << "<null>";
-    dbgs() << ", computed pdom block: BB#";
-    if (PDomB) dbgs() << PDomB->getNumber();
-    else       dbgs() << "<null>";
+    dbgs() << "Computed dom block: ";
+    if (DomB)
+      dbgs() << printMBBReference(*DomB);
+    else
+      dbgs() << "<null>";
+    dbgs() << ", computed pdom block: ";
+    if (PDomB)
+      dbgs() << printMBBReference(*PDomB);
+    else
+      dbgs() << "<null>";
     dbgs() << "\n";
   });
   if (!DomB || !PDomB)
@@ -495,8 +503,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
 /// in one place allows shrink-wrapping of the stack frame.
 void HexagonFrameLowering::emitPrologue(MachineFunction &MF,
                                         MachineBasicBlock &MBB) const {
-  auto &HST = MF.getSubtarget<HexagonSubtarget>();
-  auto &HRI = *HST.getRegisterInfo();
+  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
 
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
@@ -631,7 +638,9 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
 
   // Handle EH_RETURN.
   if (RetOpc == Hexagon::EH_RETURN_JMPR) {
-    BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe));
+    BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
+        .addDef(Hexagon::D15)
+        .addReg(Hexagon::R30);
     BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
         .addReg(SP)
         .addReg(Hexagon::R28);
@@ -677,11 +686,15 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
   // otherwise just add deallocframe. The function could be returning via a
   // tail call.
   if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
-    BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe));
+    BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
+      .addDef(Hexagon::D15)
+      .addReg(Hexagon::R30);
     return;
   }
   unsigned NewOpc = Hexagon::L4_return;
-  MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc));
+  MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
+      .addDef(Hexagon::D15)
+      .addReg(Hexagon::R30);
   // Transfer the function live-out registers.
   NewI->copyImplicitOps(MF, *RetI);
   MBB.erase(RetI);
@@ -704,10 +717,13 @@ void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
                                       MachineMemOperand::MOStore, 4, 4);
 
   DebugLoc dl = MBB.findDebugLoc(InsertPt);
+  unsigned SP = HRI.getStackRegister();
 
   if (NumBytes >= ALLOCFRAME_MAX) {
     // Emit allocframe(#0).
     BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
+      .addDef(SP)
+      .addReg(SP)
       .addImm(0)
       .addMemOperand(MMO);
 
@@ -718,6 +734,8 @@ void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
       .addImm(-int(NumBytes));
   } else {
     BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
+      .addDef(SP)
+      .addReg(SP)
       .addImm(NumBytes)
       .addMemOperand(MMO);
   }
@@ -942,7 +960,7 @@ void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
 }
 
 bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const {
-  if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
+  if (MF.getFunction().hasFnAttribute(Attribute::Naked))
     return false;
 
   auto &MFI = MF.getFrameInfo();
@@ -1370,7 +1388,7 @@ static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
   dbgs() << '{';
   for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
     unsigned R = x;
-    dbgs() << ' ' << PrintReg(R, &TRI);
+    dbgs() << ' ' << printReg(R, &TRI);
   }
   dbgs() << " }";
 }
@@ -1378,8 +1396,7 @@ static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
 
 bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
       const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
-  DEBUG(dbgs() << __func__ << " on "
-               << MF.getFunction()->getName() << '\n');
+  DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n');
   MachineFrameInfo &MFI = MF.getFrameInfo();
   BitVector SRegs(Hexagon::NUM_TARGET_REGS);
 
@@ -1392,7 +1409,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
   DEBUG(dbgs() << "Initial CS registers: {");
   for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
     unsigned R = CSI[i].getReg();
-    DEBUG(dbgs() << ' ' << PrintReg(R, TRI));
+    DEBUG(dbgs() << ' ' << printReg(R, TRI));
     for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
       SRegs[*SR] = true;
   }
@@ -1452,7 +1469,8 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
   // object for it.
   CSI.clear();
 
-  typedef TargetFrameLowering::SpillSlot SpillSlot;
+  using SpillSlot = TargetFrameLowering::SpillSlot;
+
   unsigned NumFixed;
   int MinOffset = 0;  // CS offsets are negative.
   const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
@@ -1488,7 +1506,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
     for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
       int FI = CSI[i].getFrameIdx();
       int Off = MFI.getObjectOffset(FI);
-      dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
+      dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
       if (Off >= 0)
         dbgs() << '+';
       dbgs() << Off;
@@ -1501,7 +1519,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
   bool MissedReg = false;
   for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
     unsigned R = x;
-    dbgs() << PrintReg(R, TRI) << ' ';
+    dbgs() << printReg(R, TRI) << ' ';
     MissedReg = true;
   }
   if (MissedReg)
@@ -1599,7 +1617,6 @@ bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
 bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
       MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
       const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
-  auto &HST = B.getParent()->getSubtarget<HexagonSubtarget>();
   MachineInstr *MI = &*It;
   if (!MI->getOperand(0).isFI())
     return false;
@@ -1608,10 +1625,7 @@ bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
   unsigned SrcR = MI->getOperand(2).getReg();
   bool IsKill = MI->getOperand(2).isKill();
   int FI = MI->getOperand(0).getIndex();
-
-  bool Is128B = HST.useHVXDblOps();
-  auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
-                     : &Hexagon::VectorRegs128BRegClass;
+  auto *RC = &Hexagon::HvxVRRegClass;
 
   // Insert transfer to general vector register.
   //   TmpR0 = A2_tfrsi 0x01010101
@@ -1623,8 +1637,7 @@ bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
   BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
     .addImm(0x01010101);
 
-  unsigned VandOpc = !Is128B ? Hexagon::V6_vandqrt : Hexagon::V6_vandqrt_128B;
-  BuildMI(B, It, DL, HII.get(VandOpc), TmpR1)
+  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
     .addReg(SrcR, getKillRegState(IsKill))
     .addReg(TmpR0, RegState::Kill);
 
@@ -1641,7 +1654,6 @@ bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
 bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
       MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
       const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
-  auto &HST = B.getParent()->getSubtarget<HexagonSubtarget>();
   MachineInstr *MI = &*It;
   if (!MI->getOperand(1).isFI())
     return false;
@@ -1649,10 +1661,7 @@ bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
   DebugLoc DL = MI->getDebugLoc();
   unsigned DstR = MI->getOperand(0).getReg();
   int FI = MI->getOperand(1).getIndex();
-
-  bool Is128B = HST.useHVXDblOps();
-  auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
-                     : &Hexagon::VectorRegs128BRegClass;
+  auto *RC = &Hexagon::HvxVRRegClass;
 
   // TmpR0 = A2_tfrsi 0x01010101
   // TmpR1 = load FI, 0
@@ -1662,12 +1671,12 @@ bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
 
   BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
     .addImm(0x01010101);
-  auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
+  MachineFunction &MF = *B.getParent();
+  auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
   HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
   expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
 
-  unsigned VandOpc = !Is128B ? Hexagon::V6_vandvrt : Hexagon::V6_vandvrt_128B;
-  BuildMI(B, It, DL, HII.get(VandOpc), DstR)
+  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
     .addReg(TmpR1, RegState::Kill)
     .addReg(TmpR0, RegState::Kill);
 
@@ -1681,7 +1690,6 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
       MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
       const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
   MachineFunction &MF = *B.getParent();
-  auto &HST = MF.getSubtarget<HexagonSubtarget>();
   auto &MFI = MF.getFrameInfo();
   auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
   MachineInstr *MI = &*It;
@@ -1712,21 +1720,15 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
   bool IsKill = MI->getOperand(2).isKill();
   int FI = MI->getOperand(0).getIndex();
 
-  bool Is128B = HST.useHVXDblOps();
-  const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass
-                           : Hexagon::VectorRegs128BRegClass;
-  unsigned Size = HRI.getSpillSize(RC);
-  unsigned NeedAlign = HRI.getSpillAlignment(RC);
+  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
+  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
   unsigned HasAlign = MFI.getObjectAlignment(FI);
   unsigned StoreOpc;
 
   // Store low part.
   if (LPR.contains(SrcLo)) {
-    if (NeedAlign <= HasAlign)
-      StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai  : Hexagon::V6_vS32b_ai_128B;
-    else
-      StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
-
+    StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
+                                     : Hexagon::V6_vS32Ub_ai;
     BuildMI(B, It, DL, HII.get(StoreOpc))
       .addFrameIndex(FI)
       .addImm(0)
@@ -1736,11 +1738,8 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
 
   // Store high part.
   if (LPR.contains(SrcHi)) {
-    if (NeedAlign <= MinAlign(HasAlign, Size))
-      StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai  : Hexagon::V6_vS32b_ai_128B;
-    else
-      StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
-
+    StoreOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vS32b_ai
+                                                     : Hexagon::V6_vS32Ub_ai;
     BuildMI(B, It, DL, HII.get(StoreOpc))
       .addFrameIndex(FI)
       .addImm(Size)
@@ -1756,7 +1755,6 @@ bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
       MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
       const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
   MachineFunction &MF = *B.getParent();
-  auto &HST = MF.getSubtarget<HexagonSubtarget>();
   auto &MFI = MF.getFrameInfo();
   auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
   MachineInstr *MI = &*It;
@@ -1769,31 +1767,22 @@ bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
   unsigned DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
   int FI = MI->getOperand(1).getIndex();
 
-  bool Is128B = HST.useHVXDblOps();
-  const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass
-                           : Hexagon::VectorRegs128BRegClass;
-  unsigned Size = HRI.getSpillSize(RC);
-  unsigned NeedAlign = HRI.getSpillAlignment(RC);
+  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
+  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
   unsigned HasAlign = MFI.getObjectAlignment(FI);
   unsigned LoadOpc;
 
   // Load low part.
-  if (NeedAlign <= HasAlign)
-    LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai  : Hexagon::V6_vL32b_ai_128B;
-  else
-    LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;
-
+  LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
+                                  : Hexagon::V6_vL32Ub_ai;
   BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
     .addFrameIndex(FI)
     .addImm(0)
     .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
 
   // Load high part.
-  if (NeedAlign <= MinAlign(HasAlign, Size))
-    LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai  : Hexagon::V6_vL32b_ai_128B;
-  else
-    LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;
-
+  LoadOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vL32b_ai
+                                                  : Hexagon::V6_vL32Ub_ai;
   BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
     .addFrameIndex(FI)
     .addImm(Size)
@@ -1807,30 +1796,21 @@ bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
       MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
       const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
   MachineFunction &MF = *B.getParent();
-  auto &HST = MF.getSubtarget<HexagonSubtarget>();
   auto &MFI = MF.getFrameInfo();
   MachineInstr *MI = &*It;
   if (!MI->getOperand(0).isFI())
     return false;
 
-  auto &HRI = *HST.getRegisterInfo();
+  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
   DebugLoc DL = MI->getDebugLoc();
   unsigned SrcR = MI->getOperand(2).getReg();
   bool IsKill = MI->getOperand(2).isKill();
   int FI = MI->getOperand(0).getIndex();
 
-  bool Is128B = HST.useHVXDblOps();
-  const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass
-                           : Hexagon::VectorRegs128BRegClass;
-  unsigned NeedAlign = HRI.getSpillAlignment(RC);
+  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
   unsigned HasAlign = MFI.getObjectAlignment(FI);
-  unsigned StoreOpc;
-
-  if (NeedAlign <= HasAlign)
-    StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B;
-  else
-    StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
-
+  unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
+                                            : Hexagon::V6_vS32Ub_ai;
   BuildMI(B, It, DL, HII.get(StoreOpc))
     .addFrameIndex(FI)
     .addImm(0)
@@ -1845,29 +1825,20 @@ bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
       MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
       const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
   MachineFunction &MF = *B.getParent();
-  auto &HST = MF.getSubtarget<HexagonSubtarget>();
   auto &MFI = MF.getFrameInfo();
   MachineInstr *MI = &*It;
   if (!MI->getOperand(1).isFI())
     return false;
 
-  auto &HRI = *HST.getRegisterInfo();
+  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
   DebugLoc DL = MI->getDebugLoc();
   unsigned DstR = MI->getOperand(0).getReg();
   int FI = MI->getOperand(1).getIndex();
 
-  bool Is128B = HST.useHVXDblOps();
-  const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass
-                           : Hexagon::VectorRegs128BRegClass;
-  unsigned NeedAlign = HRI.getSpillAlignment(RC);
+  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
   unsigned HasAlign = MFI.getObjectAlignment(FI);
-  unsigned LoadOpc;
-
-  if (NeedAlign <= HasAlign)
-    LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B;
-  else
-    LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;
-
+  unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
+                                           : Hexagon::V6_vL32Ub_ai;
   BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
     .addFrameIndex(FI)
     .addImm(0)
@@ -1879,8 +1850,7 @@ bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
 
 bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
       SmallVectorImpl<unsigned> &NewRegs) const {
-  auto &HST = MF.getSubtarget<HexagonSubtarget>();
-  auto &HII = *HST.getInstrInfo();
+  auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   bool Changed = false;
 
@@ -1905,23 +1875,17 @@ bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
           Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);
           break;
         case Hexagon::PS_vstorerq_ai:
-        case Hexagon::PS_vstorerq_ai_128B:
           Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);
           break;
         case Hexagon::PS_vloadrq_ai:
-        case Hexagon::PS_vloadrq_ai_128B:
           Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);
           break;
         case Hexagon::PS_vloadrw_ai:
         case Hexagon::PS_vloadrwu_ai:
-        case Hexagon::PS_vloadrw_ai_128B:
-        case Hexagon::PS_vloadrwu_ai_128B:
           Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);
           break;
         case Hexagon::PS_vstorerw_ai:
         case Hexagon::PS_vstorerwu_ai:
-        case Hexagon::PS_vstorerw_ai_128B:
-        case Hexagon::PS_vstorerwu_ai_128B:
           Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);
           break;
       }
@@ -1934,8 +1898,7 @@ bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
 void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
                                                 BitVector &SavedRegs,
                                                 RegScavenger *RS) const {
-  auto &HST = MF.getSubtarget<HexagonSubtarget>();
-  auto &HRI = *HST.getRegisterInfo();
+  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
 
   SavedRegs.resize(HRI.getNumRegs());
 
@@ -2019,11 +1982,11 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
   auto &MRI = MF.getRegInfo();
   HexagonBlockRanges HBR(MF);
 
-  typedef std::map<MachineBasicBlock*,HexagonBlockRanges::InstrIndexMap>
-      BlockIndexMap;
-  typedef std::map<MachineBasicBlock*,HexagonBlockRanges::RangeList>
-      BlockRangeMap;
-  typedef HexagonBlockRanges::IndexType IndexType;
+  using BlockIndexMap =
+      std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;
+  using BlockRangeMap =
+      std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;
+  using IndexType = HexagonBlockRanges::IndexType;
 
   struct SlotInfo {
     BlockRangeMap Map;
@@ -2063,7 +2026,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
     auto P = BlockIndexes.insert(
                 std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
     auto &IndexMap = P.first->second;
-    DEBUG(dbgs() << "Index map for BB#" << B.getNumber() << "\n"
+    DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
                  << IndexMap << '\n');
 
     for (auto &In : B) {
@@ -2099,7 +2062,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
         }
         if (!Bad) {
           // Check sizes.
-          unsigned S = (1U << (HII.getMemAccessSize(In) - 1));
+          unsigned S = HII.getMemAccessSize(In);
           if (SI.Size != 0 && SI.Size != S)
             Bad = true;
           else
@@ -2182,7 +2145,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
       else
         dbgs() << "<null>\n";
       for (auto &R : P.second.Map)
-        dbgs() << "  BB#" << R.first->getNumber() << " { " << R.second << "}\n";
+        dbgs() << "  " << printMBBReference(*R.first) << " { " << R.second
+               << "}\n";
     }
   });
 
@@ -2215,7 +2179,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
       auto &FIs = P.second;
       if (FIs.empty())
         continue;
-      dbgs() << "  BB#" << P.first->getNumber() << ": {";
+      dbgs() << "  " << printMBBReference(*P.first) << ": {";
       for (auto I : FIs) {
         dbgs() << " fi#" << I;
         if (LoxFIs.count(I))
@@ -2236,7 +2200,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
     HexagonBlockRanges::InstrIndexMap &IM = F->second;
     HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);
     HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);
-    DEBUG(dbgs() << "BB#" << B.getNumber() << " dead map\n"
+    DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
                  << HexagonBlockRanges::PrintRangeMap(DM, HRI));
 
     for (auto FI : BlockFIMap[&B]) {
@@ -2260,7 +2224,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
         auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
         // The this-> is needed to unconfuse MSVC.
         unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
-        DEBUG(dbgs() << "Replacement reg:" << PrintReg(FoundR, &HRI) << '\n');
+        DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) << '\n');
         if (FoundR == 0)
           continue;
 #ifndef NDEBUG
@@ -2308,7 +2272,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
           MachineInstr *CopyOut = nullptr;
           if (DstR != FoundR) {
             DebugLoc DL = MI.getDebugLoc();
-            unsigned MemSize = (1U << (HII.getMemAccessSize(MI) - 1));
+            unsigned MemSize = HII.getMemAccessSize(MI);
             assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
             unsigned CopyOpc = TargetOpcode::COPY;
             if (HII.isSignExtendingLoad(MI))
diff --git a/lib/Target/Hexagon/HexagonFrameLowering.h b/lib/Target/Hexagon/HexagonFrameLowering.h
index f4d4e1b61a26..988718860c5b 100644
--- a/lib/Target/Hexagon/HexagonFrameLowering.h
+++ b/lib/Target/Hexagon/HexagonFrameLowering.h
@@ -1,4 +1,4 @@
-//=- HexagonFrameLowering.h - Define frame lowering for Hexagon --*- C++ -*--=//
+//==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -15,13 +15,18 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/Target/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
 #include <vector>
 
 namespace llvm {
 
+class BitVector;
 class HexagonInstrInfo;
 class HexagonRegisterInfo;
+class MachineFunction;
+class MachineInstr;
+class MachineRegisterInfo;
+class TargetRegisterClass;
 
 class HexagonFrameLowering : public TargetFrameLowering {
 public:
@@ -43,7 +48,7 @@ public:
   }
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-      MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
+      MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI,
       const TargetRegisterInfo *TRI) const override {
     return true;
   }
@@ -52,11 +57,13 @@ public:
     // We always reserve call frame as a part of the initial stack allocation.
     return true;
   }
+
   bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override {
     // Override this function to avoid calling hasFP before CSI is set
     // (the default implementation calls hasFP).
     return true;
   }
+
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I) const override;
@@ -97,7 +104,7 @@ public:
   void insertCFIInstructions(MachineFunction &MF) const;
 
 private:
-  typedef std::vector<CalleeSavedInfo> CSIVect;
+  using CSIVect = std::vector<CalleeSavedInfo>;
 
   void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
       unsigned SP, unsigned CF) const;
diff --git a/lib/Target/Hexagon/HexagonGatherPacketize.cpp b/lib/Target/Hexagon/HexagonGatherPacketize.cpp
new file mode 100644
index 000000000000..253f09d12839
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonGatherPacketize.cpp
@@ -0,0 +1,104 @@
+//===- HexagonGatherPacketize.cpp -----------------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// This pass ensures that producer and consumer of VTMP are paired in a bundle.
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "gather-packetize"
+
+#include "HexagonTargetMachine.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBundle.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+using namespace llvm;
+
+cl::opt<bool> EnableGatherPacketize(
+    "hexagon-enable-gather-packetize", cl::Hidden, cl::init(true),
+    cl::desc("Generate gather packets before packetization"));
+
+namespace llvm {
+FunctionPass *createHexagonGatherPacketize();
+void initializeHexagonGatherPacketizePass(PassRegistry &);
+}
+
+namespace {
+class HexagonGatherPacketize : public MachineFunctionPass {
+public:
+  static char ID;
+  HexagonGatherPacketize() : MachineFunctionPass(ID) {
+    PassRegistry &Registry = *PassRegistry::getPassRegistry();
+    initializeHexagonGatherPacketizePass(Registry);
+  }
+
+  StringRef getPassName() const override {
+    return "Hexagon Gather Packetize Code";
+  }
+  bool runOnMachineFunction(MachineFunction &Fn) override;
+};
+
+char HexagonGatherPacketize::ID = 0;
+
+static inline bool isVtmpDef(const MachineInstr &MI) {
+  for (const MachineOperand &MO : MI.operands())
+    if (MO.isReg() && MO.isDef() && MO.isImplicit() &&
+        (MO.getReg() == Hexagon::VTMP)) {
+      return true;
+    }
+  return false;
+}
+
+static inline bool isVtmpUse(const MachineInstr &MI) {
+  return (MI.mayStore() && (MI.getOperand(2)).isReg() &&
+          ((MI.getOperand(2)).getReg() == Hexagon::VTMP));
+}
+
+bool HexagonGatherPacketize::runOnMachineFunction(MachineFunction &Fn) {
+  if (!EnableGatherPacketize)
+    return false;
+  auto &ST = Fn.getSubtarget<HexagonSubtarget>();
+  bool HasV65 = ST.hasV65TOps();
+  bool UseHVX = ST.useHVXOps();
+  if (!(HasV65 & UseHVX))
+    return false;
+
+  for (auto &MBB : Fn) {
+    bool VtmpDef = false;
+    MachineBasicBlock::iterator MII, MIE, DefMII;
+    for (MII = MBB.begin(), MIE = MBB.end(); MII != MIE; ++MII) {
+      MachineInstr &MI = *MII;
+      if (VtmpDef) {
+        if (!isVtmpUse(MI))
+          continue;
+        MBB.splice(std::next(DefMII), &MBB, MII);
+        finalizeBundle(MBB, DefMII.getInstrIterator(),
+                       std::next(MII).getInstrIterator());
+        VtmpDef = false;
+        continue;
+      }
+      if (!(isVtmpDef(MI)))
+        continue;
+      VtmpDef = true;
+      DefMII = MII;
+    }
+    assert(!VtmpDef && "VTMP producer and consumer not in same block");
+  }
+  return true;
+}
+}
+
+//===----------------------------------------------------------------------===//
+//                         Public Constructor Functions
+//===----------------------------------------------------------------------===//
+
+INITIALIZE_PASS(HexagonGatherPacketize, "hexagon-gather-packetize",
+                "Hexagon gather packetize Code", false, false)
+
+FunctionPass *llvm::createHexagonGatherPacketize() {
+  return new HexagonGatherPacketize();
+}
diff --git a/lib/Target/Hexagon/HexagonGenExtract.cpp b/lib/Target/Hexagon/HexagonGenExtract.cpp
index 7c6de6d513e8..08a016b74650 100644
--- a/lib/Target/Hexagon/HexagonGenExtract.cpp
+++ b/lib/Target/Hexagon/HexagonGenExtract.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonGenExtract.cpp --------------------------------------------===//
+//===- HexagonGenExtract.cpp ----------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -8,7 +8,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/APInt.h"
-#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/GraphTraits.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/CFG.h"
 #include "llvm/IR/Constants.h"
@@ -47,8 +47,8 @@ static cl::opt<bool> NeedAnd("extract-needand", cl::init(true), cl::Hidden,
 
 namespace llvm {
 
-  void initializeHexagonGenExtractPass(PassRegistry&);
-  FunctionPass *createHexagonGenExtract();
+void initializeHexagonGenExtractPass(PassRegistry&);
+FunctionPass *createHexagonGenExtract();
 
 } // end namespace llvm
 
@@ -58,7 +58,7 @@ namespace {
   public:
     static char ID;
 
-    HexagonGenExtract() : FunctionPass(ID), ExtractCount(0) {
+    HexagonGenExtract() : FunctionPass(ID) {
       initializeHexagonGenExtractPass(*PassRegistry::getPassRegistry());
     }
 
@@ -78,14 +78,14 @@ namespace {
     bool visitBlock(BasicBlock *B);
     bool convert(Instruction *In);
 
-    unsigned ExtractCount;
+    unsigned ExtractCount = 0;
     DominatorTree *DT;
   };
 
-  char HexagonGenExtract::ID = 0;
-
 } // end anonymous namespace
 
+char HexagonGenExtract::ID = 0;
+
 INITIALIZE_PASS_BEGIN(HexagonGenExtract, "hextract", "Hexagon generate "
   "\"extract\" instructions", false, false)
 INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
diff --git a/lib/Target/Hexagon/HexagonGenInsert.cpp b/lib/Target/Hexagon/HexagonGenInsert.cpp
index 0a955aedaf1a..c1841d735b8c 100644
--- a/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonGenInsert.cpp ---------------------------------------------===//
+//===- HexagonGenInsert.cpp -----------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -14,6 +14,7 @@
 #include "HexagonSubtarget.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/PostOrderIterator.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallSet.h"
@@ -27,6 +28,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
@@ -34,7 +36,6 @@
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/Timer.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
@@ -179,7 +180,7 @@ namespace {
   raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) {
     OS << '{';
     for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))
-      OS << ' ' << PrintReg(R, P.TRI);
+      OS << ' ' << printReg(R, P.TRI);
     OS << " }";
     return OS;
   }
@@ -190,7 +191,7 @@ namespace {
     UnsignedMap() = default;
 
   private:
-    typedef DenseMap<unsigned,unsigned> BaseType;
+    using BaseType = DenseMap<unsigned, unsigned>;
   };
 
   // A utility to establish an ordering between virtual registers:
@@ -273,7 +274,8 @@ namespace {
     const BitTracker &BT;
 
   private:
-    typedef std::vector<const BitTracker::RegisterCell*> CellVectType;
+    using CellVectType = std::vector<const BitTracker::RegisterCell *>;
+
     CellVectType CVect;
   };
 
@@ -367,7 +369,7 @@ bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const {
 namespace {
 
   class OrderedRegisterList {
-    typedef std::vector<unsigned> ListType;
+    using ListType = std::vector<unsigned>;
 
   public:
     OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {}
@@ -384,8 +386,9 @@ namespace {
       return Seq.size();
     }
 
-    typedef ListType::iterator iterator;
-    typedef ListType::const_iterator const_iterator;
+    using iterator = ListType::iterator;
+    using const_iterator = ListType::const_iterator;
+
     iterator begin() { return Seq.begin(); }
     iterator end() { return Seq.end(); }
     const_iterator begin() const { return Seq.begin(); }
@@ -416,7 +419,7 @@ namespace {
     for (OrderedRegisterList::const_iterator I = B; I != E; ++I) {
       if (I != B)
         OS << ", ";
-      OS << PrintReg(*I, P.TRI);
+      OS << printReg(*I, P.TRI);
     }
     OS << ')';
     return OS;
@@ -464,12 +467,12 @@ namespace {
 
   raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P) {
     unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR;
-    OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI)
+    OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI)
        << ",#" << P.IFR.Wdh << ",#" << P.IFR.Off << ')';
     return OS;
   }
 
-  typedef std::pair<IFRecord,RegisterSet> IFRecordWithRegSet;
+  using IFRecordWithRegSet = std::pair<IFRecord, RegisterSet>;
 
 } // end anonymous namespace
 
@@ -486,7 +489,7 @@ namespace {
   public:
     static char ID;
 
-    HexagonGenInsert() : MachineFunctionPass(ID), HII(nullptr), HRI(nullptr) {
+    HexagonGenInsert() : MachineFunctionPass(ID) {
       initializeHexagonGenInsertPass(*PassRegistry::getPassRegistry());
     }
 
@@ -503,7 +506,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
   private:
-    typedef DenseMap<std::pair<unsigned,unsigned>,unsigned> PairMapType;
+    using PairMapType = DenseMap<std::pair<unsigned, unsigned>, unsigned>;
 
     void buildOrderingMF(RegisterOrdering &RO) const;
     void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
@@ -539,13 +542,13 @@ namespace {
     bool removeDeadCode(MachineDomTreeNode *N);
 
     // IFRecord coupled with a set of potentially removable registers:
-    typedef std::vector<IFRecordWithRegSet> IFListType;
-    typedef DenseMap<unsigned,IFListType> IFMapType;  // vreg -> IFListType
+    using IFListType = std::vector<IFRecordWithRegSet>;
+    using IFMapType = DenseMap<unsigned, IFListType>; // vreg -> IFListType
 
     void dump_map() const;
 
-    const HexagonInstrInfo *HII;
-    const HexagonRegisterInfo *HRI;
+    const HexagonInstrInfo *HII = nullptr;
+    const HexagonRegisterInfo *HRI = nullptr;
 
     MachineFunction *MFN;
     MachineRegisterInfo *MRI;
@@ -557,14 +560,15 @@ namespace {
     IFMapType IFMap;
   };
 
-  char HexagonGenInsert::ID = 0;
-
 } // end anonymous namespace
 
+char HexagonGenInsert::ID = 0;
+
 void HexagonGenInsert::dump_map() const {
-  typedef IFMapType::const_iterator iterator;
+  using iterator = IFMapType::const_iterator;
+
   for (iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
-    dbgs() << "  " << PrintReg(I->first, HRI) << ":\n";
+    dbgs() << "  " << printReg(I->first, HRI) << ":\n";
     const IFListType &LL = I->second;
     for (unsigned i = 0, n = LL.size(); i < n; ++i)
       dbgs() << "    " << PrintIFR(LL[i].first, HRI) << ", "
@@ -574,12 +578,16 @@ void HexagonGenInsert::dump_map() const {
 
 void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const {
   unsigned Index = 0;
-  typedef MachineFunction::const_iterator mf_iterator;
+
+  using mf_iterator = MachineFunction::const_iterator;
+
   for (mf_iterator A = MFN->begin(), Z = MFN->end(); A != Z; ++A) {
     const MachineBasicBlock &B = *A;
     if (!CMS->BT.reached(&B))
       continue;
-    typedef MachineBasicBlock::const_iterator mb_iterator;
+
+    using mb_iterator = MachineBasicBlock::const_iterator;
+
     for (mb_iterator I = B.begin(), E = B.end(); I != E; ++I) {
       const MachineInstr *MI = &*I;
       for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
@@ -604,7 +612,9 @@ void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB,
   // ordering RB), and then sort it using the RegisterCell comparator.
   BitValueOrdering BVO(RB);
   RegisterCellLexCompare LexCmp(BVO, *CMS);
-  typedef std::vector<unsigned> SortableVectorType;
+
+  using SortableVectorType = std::vector<unsigned>;
+
   SortableVectorType VRs;
   for (RegisterOrdering::iterator I = RB.begin(), E = RB.end(); I != E; ++I)
     VRs.push_back(I->first);
@@ -736,7 +746,9 @@ unsigned HexagonGenInsert::distance(const MachineBasicBlock *FromB,
   unsigned ToRPO = RPO.lookup(ToN);
 
   unsigned MaxD = 0;
-  typedef MachineBasicBlock::const_pred_iterator pred_iterator;
+
+  using pred_iterator = MachineBasicBlock::const_pred_iterator;
+
   for (pred_iterator I = ToB->pred_begin(), E = ToB->pred_end(); I != E; ++I) {
     const MachineBasicBlock *PB = *I;
     // Skip back edges. Also, if FromB is a predecessor of ToB, the distance
@@ -769,23 +781,24 @@ unsigned HexagonGenInsert::distance(MachineBasicBlock::const_iterator FromI,
 bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
       OrderedRegisterList &AVs) {
   if (isDebug()) {
-    dbgs() << __func__ << ": " << PrintReg(VR, HRI)
+    dbgs() << __func__ << ": " << printReg(VR, HRI)
            << "  AVs: " << PrintORL(AVs, HRI) << "\n";
   }
   if (AVs.size() == 0)
     return false;
 
-  typedef OrderedRegisterList::iterator iterator;
+  using iterator = OrderedRegisterList::iterator;
+
   BitValueOrdering BVO(BaseOrd);
   const BitTracker::RegisterCell &RC = CMS->lookup(VR);
   uint16_t W = RC.width();
 
-  typedef std::pair<unsigned,uint16_t> RSRecord;  // (reg,shift)
-  typedef std::vector<RSRecord> RSListType;
+  using RSRecord = std::pair<unsigned, uint16_t>; // (reg,shift)
+  using RSListType = std::vector<RSRecord>;
   // Have a map, with key being the matching prefix length, and the value
   // being the list of pairs (R,S), where R's prefix matches VR at S.
   // (DenseMap<uint16_t,RSListType> fails to instantiate.)
-  typedef DenseMap<unsigned,RSListType> LRSMapType;
+  using LRSMapType = DenseMap<unsigned, RSListType>;
   LRSMapType LM;
 
   // Conceptually, rotate the cell RC right (i.e. towards the LSB) by S,
@@ -833,12 +846,12 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
   }
 
   if (isDebug()) {
-    dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n";
+    dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n";
     for (LRSMapType::iterator I = LM.begin(), E = LM.end(); I != E; ++I) {
       dbgs() << "  L=" << I->first << ':';
       const RSListType &LL = I->second;
       for (unsigned i = 0, n = LL.size(); i < n; ++i)
-        dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@"
+        dbgs() << " (" << printReg(LL[i].first, HRI) << ",@"
                << LL[i].second << ')';
       dbgs() << '\n';
     }
@@ -885,8 +898,8 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
         if (!isValidInsertForm(VR, SrcR, InsR, L, S))
           continue;
         if (isDebug()) {
-          dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI)
-                 << ',' << PrintReg(InsR, HRI) << ",#" << L << ",#"
+          dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI)
+                 << ',' << printReg(InsR, HRI) << ",#" << L << ",#"
                  << S << ")\n";
         }
         IFRecordWithRegSet RR(IFRecord(SrcR, InsR, L, S), RegisterSet());
@@ -902,7 +915,7 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
 void HexagonGenInsert::collectInBlock(MachineBasicBlock *B,
       OrderedRegisterList &AVs) {
   if (isDebug())
-    dbgs() << "visiting block BB#" << B->getNumber() << "\n";
+    dbgs() << "visiting block " << printMBBReference(*B) << "\n";
 
   // First, check if this block is reachable at all. If not, the bit tracker
   // will not have any information about registers in it.
@@ -1018,7 +1031,7 @@ void HexagonGenInsert::computeRemovableRegisters() {
 void HexagonGenInsert::pruneEmptyLists() {
   // Remove all entries from the map, where the register has no insert forms
   // associated with it.
-  typedef SmallVector<IFMapType::iterator,16> IterListType;
+  using IterListType = SmallVector<IFMapType::iterator, 16>;
   IterListType Prune;
   for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
     if (I->second.empty())
@@ -1093,10 +1106,10 @@ void HexagonGenInsert::pruneCoveredSets(unsigned VR) {
 
   // Now, remove those whose sets of potentially removable registers are
   // contained in another IF candidate for VR. For example, given these
-  // candidates for vreg45,
-  //   %vreg45:
-  //     (%vreg44,%vreg41,#9,#8), { %vreg42 }
-  //     (%vreg43,%vreg41,#9,#8), { %vreg42 %vreg44 }
+  // candidates for %45,
+  //   %45:
+  //     (%44,%41,#9,#8), { %42 }
+  //     (%43,%41,#9,#8), { %42 %44 }
   // remove the first one, since it is contained in the second one.
   for (unsigned i = 0, n = LL.size(); i < n; ) {
     const RegisterSet &RMi = LL[i].second;
@@ -1159,7 +1172,9 @@ void HexagonGenInsert::pruneCandidates() {
     pruneCoveredSets(I->first);
 
   UnsignedMap RPO;
-  typedef ReversePostOrderTraversal<const MachineFunction*> RPOTType;
+
+  using RPOTType = ReversePostOrderTraversal<const MachineFunction *>;
+
   RPOTType RPOT(MFN);
   unsigned RPON = 0;
   for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
@@ -1191,7 +1206,7 @@ namespace {
       : UseC(UC), BaseOrd(BO) {}
 
     bool operator() (const IFRecordWithRegSet &A,
-          const IFRecordWithRegSet &B) const;
+                     const IFRecordWithRegSet &B) const;
 
   private:
     void stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero,
@@ -1266,8 +1281,9 @@ void HexagonGenInsert::selectCandidates() {
   }
 
   for (unsigned R = AllRMs.find_first(); R; R = AllRMs.find_next(R)) {
-    typedef MachineRegisterInfo::use_nodbg_iterator use_iterator;
-    typedef SmallSet<const MachineInstr*,16> InstrSet;
+    using use_iterator = MachineRegisterInfo::use_nodbg_iterator;
+    using InstrSet = SmallSet<const MachineInstr *, 16>;
+
     InstrSet UIs;
     // Count as the number of instructions in which R is used, not the
     // number of operands.
@@ -1466,7 +1482,7 @@ bool HexagonGenInsert::removeDeadCode(MachineDomTreeNode *N) {
 }
 
 bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   bool Timing = OptTiming, TimingDetail = Timing && OptTimingDetail;
@@ -1508,7 +1524,7 @@ bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
     for (RegisterOrdering::iterator I = CellOrd.begin(), E = CellOrd.end();
         I != E; ++I) {
       unsigned VR = I->first, Pos = I->second;
-      dbgs() << PrintReg(VR, HRI) << " -> " << Pos << "\n";
+      dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n";
     }
   }
 
@@ -1561,7 +1577,9 @@ bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
   // Filter out vregs beyond the cutoff.
   if (VRegIndexCutoff.getPosition()) {
     unsigned Cutoff = VRegIndexCutoff;
-    typedef SmallVector<IFMapType::iterator,16> IterListType;
+
+    using IterListType = SmallVector<IFMapType::iterator, 16>;
+
     IterListType Out;
     for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
       unsigned Idx = TargetRegisterInfo::virtReg2Index(I->first);
diff --git a/lib/Target/Hexagon/HexagonGenMux.cpp b/lib/Target/Hexagon/HexagonGenMux.cpp
index 5abbcbba72dd..5a001d6ed9c1 100644
--- a/lib/Target/Hexagon/HexagonGenMux.cpp
+++ b/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonGenMux.cpp ------------------------------------------------===//
+//===- HexagonGenMux.cpp --------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -26,6 +26,7 @@
 #include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
 #include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/LivePhysRegs.h"
@@ -41,6 +42,7 @@
 #include "llvm/Pass.h"
 #include "llvm/Support/MathExtras.h"
 #include <algorithm>
+#include <cassert>
 #include <iterator>
 #include <limits>
 #include <utility>
@@ -109,9 +111,9 @@ namespace {
             Def2(&D2) {}
     };
 
-    typedef DenseMap<MachineInstr*,unsigned> InstrIndexMap;
-    typedef DenseMap<unsigned,DefUseInfo> DefUseInfoMap;
-    typedef SmallVector<MuxInfo,4> MuxInfoList;
+    using InstrIndexMap = DenseMap<MachineInstr *, unsigned>;
+    using DefUseInfoMap = DenseMap<unsigned, DefUseInfo>;
+    using MuxInfoList = SmallVector<MuxInfo, 4>;
 
     bool isRegPair(unsigned Reg) const {
       return Hexagon::DoubleRegsRegClass.contains(Reg);
@@ -129,10 +131,10 @@ namespace {
     bool genMuxInBlock(MachineBasicBlock &B);
   };
 
-  char HexagonGenMux::ID = 0;
-
 } // end anonymous namespace
 
+char HexagonGenMux::ID = 0;
+
 INITIALIZE_PASS(HexagonGenMux, "hexagon-gen-mux",
   "Hexagon generate mux instructions", false, false)
 
@@ -220,7 +222,8 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
   DefUseInfoMap DUM;
   buildMaps(B, I2X, DUM);
 
-  typedef DenseMap<unsigned,CondsetInfo> CondsetMap;
+  using CondsetMap = DenseMap<unsigned, CondsetInfo>;
+
   CondsetMap CM;
   MuxInfoList ML;
 
@@ -365,7 +368,7 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
 }
 
 bool HexagonGenMux::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
   HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
   HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
diff --git a/lib/Target/Hexagon/HexagonGenPredicate.cpp b/lib/Target/Hexagon/HexagonGenPredicate.cpp
index 2da211563e0a..9288ed03d4d2 100644
--- a/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonGenPredicate.cpp ------------------------------------------===//
+//===- HexagonGenPredicate.cpp --------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -19,13 +19,13 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <cassert>
 #include <iterator>
 #include <map>
@@ -74,15 +74,14 @@ namespace {
   raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
     LLVM_ATTRIBUTE_UNUSED;
   raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) {
-    return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
+    return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
   }
 
   class HexagonGenPredicate : public MachineFunctionPass {
   public:
     static char ID;
 
-    HexagonGenPredicate() : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr),
-        MRI(nullptr) {
+    HexagonGenPredicate() : MachineFunctionPass(ID) {
       initializeHexagonGenPredicatePass(*PassRegistry::getPassRegistry());
     }
 
@@ -99,13 +98,13 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
   private:
-    typedef SetVector<MachineInstr*> VectOfInst;
-    typedef std::set<Register> SetOfReg;
-    typedef std::map<Register,Register> RegToRegMap;
+    using VectOfInst = SetVector<MachineInstr *>;
+    using SetOfReg = std::set<Register>;
+    using RegToRegMap = std::map<Register, Register>;
 
-    const HexagonInstrInfo *TII;
-    const HexagonRegisterInfo *TRI;
-    MachineRegisterInfo *MRI;
+    const HexagonInstrInfo *TII = nullptr;
+    const HexagonRegisterInfo *TRI = nullptr;
+    MachineRegisterInfo *MRI = nullptr;
     SetOfReg PredGPRs;
     VectOfInst PUsers;
     RegToRegMap G2P;
@@ -122,10 +121,10 @@ namespace {
     bool eliminatePredCopies(MachineFunction &MF);
   };
 
-  char HexagonGenPredicate::ID = 0;
-
 } // end anonymous namespace
 
+char HexagonGenPredicate::ID = 0;
+
 INITIALIZE_PASS_BEGIN(HexagonGenPredicate, "hexagon-gen-pred",
   "Hexagon generate predicate operations", false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
@@ -224,11 +223,12 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) {
 
 void HexagonGenPredicate::processPredicateGPR(const Register &Reg) {
   DEBUG(dbgs() << __func__ << ": "
-               << PrintReg(Reg.R, TRI, Reg.S) << "\n");
-  typedef MachineRegisterInfo::use_iterator use_iterator;
+               << printReg(Reg.R, TRI, Reg.S) << "\n");
+  using use_iterator = MachineRegisterInfo::use_iterator;
+
   use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end();
   if (I == E) {
-    DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n');
+    DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n');
     MachineInstr *DefI = MRI->getVRegDef(Reg.R);
     DefI->eraseFromParent();
     return;
@@ -492,7 +492,7 @@ bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
 }
 
 bool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
@@ -512,7 +512,8 @@ bool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) {
     Again = false;
     VectOfInst Processed, Copy;
 
-    typedef VectOfInst::iterator iterator;
+    using iterator = VectOfInst::iterator;
+
     Copy = PUsers;
     for (iterator I = Copy.begin(), E = Copy.end(); I != E; ++I) {
       MachineInstr *MI = *I;
diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 86a8089401c2..715fd52f3acd 100644
--- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1,4 +1,4 @@
-//===-- HexagonHardwareLoops.cpp - Identify and generate hardware loops ---===//
+//===- HexagonHardwareLoops.cpp - Identify and generate hardware loops ----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -27,6 +27,8 @@
 
 #include "HexagonInstrInfo.h"
 #include "HexagonSubtarget.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
@@ -40,6 +42,7 @@
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/Pass.h"
@@ -48,13 +51,13 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <cassert>
 #include <cstdint>
 #include <cstdlib>
 #include <iterator>
 #include <map>
 #include <set>
+#include <string>
 #include <utility>
 #include <vector>
 
@@ -108,9 +111,7 @@ namespace {
   public:
     static char ID;
 
-    HexagonHardwareLoops() : MachineFunctionPass(ID) {
-      initializeHexagonHardwareLoopsPass(*PassRegistry::getPassRegistry());
-    }
+    HexagonHardwareLoops() : MachineFunctionPass(ID) {}
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
@@ -123,7 +124,7 @@ namespace {
     }
 
   private:
-    typedef std::map<unsigned, MachineInstr *> LoopFeederMap;
+    using LoopFeederMap = std::map<unsigned, MachineInstr *>;
 
     /// Kinds of comparisons in the compare instructions.
     struct Comparison {
@@ -275,7 +276,7 @@ namespace {
     /// value, either directly, or via a register.
     void setImmediate(MachineOperand &MO, int64_t Val);
 
-    /// \brief Fix the data flow of the induction varible.
+    /// \brief Fix the data flow of the induction variable.
     /// The desired flow is: phi ---> bump -+-> comparison-in-latch.
     ///                                     |
     ///                                     +-> back to phi
@@ -344,17 +345,19 @@ namespace {
       assert(isReg() && "Wrong CountValue accessor");
       return Contents.R.Reg;
     }
+
     unsigned getSubReg() const {
       assert(isReg() && "Wrong CountValue accessor");
       return Contents.R.Sub;
     }
+
     unsigned getImm() const {
       assert(isImm() && "Wrong CountValue accessor");
       return Contents.ImmVal;
     }
 
     void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {
-      if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
+      if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }
       if (isImm()) { OS << Contents.ImmVal; }
     }
   };
@@ -374,7 +377,7 @@ FunctionPass *llvm::createHexagonHardwareLoops() {
 
 bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) {
   DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   bool Changed = false;
@@ -410,17 +413,18 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L,
 
   // This pair represents an induction register together with an immediate
   // value that will be added to it in each loop iteration.
-  typedef std::pair<unsigned,int64_t> RegisterBump;
+  using RegisterBump = std::pair<unsigned, int64_t>;
 
   // Mapping:  R.next -> (R, bump), where R, R.next and bump are derived
   // from an induction operation
   //   R.next = R + bump
   // where bump is an immediate value.
-  typedef std::map<unsigned,RegisterBump> InductionMap;
+  using InductionMap = std::map<unsigned, RegisterBump>;
 
   InductionMap IndMap;
 
-  typedef MachineBasicBlock::instr_iterator instr_iterator;
+  using instr_iterator = MachineBasicBlock::instr_iterator;
+
   for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
        I != E && I->isPHI(); ++I) {
     MachineInstr *Phi = &*I;
@@ -507,8 +511,8 @@ HexagonHardwareLoops::getComparisonKind(unsigned CondOpc,
                                         int64_t IVBump) const {
   Comparison::Kind Cmp = (Comparison::Kind)0;
   switch (CondOpc) {
-  case Hexagon::C2_cmpeqi:
   case Hexagon::C2_cmpeq:
+  case Hexagon::C2_cmpeqi:
   case Hexagon::C2_cmpeqp:
     Cmp = Comparison::EQ;
     break;
@@ -516,21 +520,35 @@ HexagonHardwareLoops::getComparisonKind(unsigned CondOpc,
   case Hexagon::C4_cmpneqi:
     Cmp = Comparison::NE;
     break;
+  case Hexagon::C2_cmplt:
+    Cmp = Comparison::LTs;
+    break;
+  case Hexagon::C2_cmpltu:
+    Cmp = Comparison::LTu;
+    break;
   case Hexagon::C4_cmplte:
+  case Hexagon::C4_cmpltei:
     Cmp = Comparison::LEs;
     break;
   case Hexagon::C4_cmplteu:
+  case Hexagon::C4_cmplteui:
     Cmp = Comparison::LEu;
     break;
-  case Hexagon::C2_cmpgtui:
+  case Hexagon::C2_cmpgt:
+  case Hexagon::C2_cmpgti:
+  case Hexagon::C2_cmpgtp:
+    Cmp = Comparison::GTs;
+    break;
   case Hexagon::C2_cmpgtu:
+  case Hexagon::C2_cmpgtui:
   case Hexagon::C2_cmpgtup:
     Cmp = Comparison::GTu;
     break;
-  case Hexagon::C2_cmpgti:
-  case Hexagon::C2_cmpgt:
-  case Hexagon::C2_cmpgtp:
-    Cmp = Comparison::GTs;
+  case Hexagon::C2_cmpgei:
+    Cmp = Comparison::GEs;
+    break;
+  case Hexagon::C2_cmpgeui:
+    Cmp = Comparison::GEs;
     break;
   default:
     return (Comparison::Kind)0;
@@ -679,15 +697,21 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
   if (InitialValue->isReg()) {
     unsigned R = InitialValue->getReg();
     MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
-    if (!MDT->properlyDominates(DefBB, Header))
-      return nullptr;
+    if (!MDT->properlyDominates(DefBB, Header)) {
+      int64_t V;
+      if (!checkForImmediate(*InitialValue, V))
+        return nullptr;
+    }
     OldInsts.push_back(MRI->getVRegDef(R));
   }
   if (EndValue->isReg()) {
     unsigned R = EndValue->getReg();
     MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
-    if (!MDT->properlyDominates(DefBB, Header))
-      return nullptr;
+    if (!MDT->properlyDominates(DefBB, Header)) {
+      int64_t V;
+      if (!checkForImmediate(*EndValue, V))
+        return nullptr;
+    }
     OldInsts.push_back(MRI->getVRegDef(R));
   }
 
@@ -970,6 +994,7 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI,
 
   // Check if the instruction defines a hardware loop register.
   using namespace Hexagon;
+
   static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 };
   static const unsigned Regs1[]  = { LC1, SA1 };
   auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, array_lengthof(Regs01))
@@ -986,7 +1011,7 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI,
 bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L,
     bool IsInnerHWLoop) const {
   const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks();
-  DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber(););
+  DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0]));
   for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
     MachineBasicBlock *MBB = Blocks[i];
     for (MachineBasicBlock::iterator
@@ -1017,7 +1042,7 @@ bool HexagonHardwareLoops::isDead(const MachineInstr *MI,
     if (MRI->use_nodbg_empty(Reg))
       continue;
 
-    typedef MachineRegisterInfo::use_nodbg_iterator use_nodbg_iterator;
+    using use_nodbg_iterator = MachineRegisterInfo::use_nodbg_iterator;
 
     // This instruction has users, but if the only user is the phi node for the
     // parent block, and the only use of that phi node is this instruction, then
@@ -1231,7 +1256,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L,
     // if the immediate fits in the instructions.  Otherwise, we need to
     // create a new virtual register.
     int64_t CountImm = TripCount->getImm();
-    if (!TII->isValidOffset(LOOP_i, CountImm)) {
+    if (!TII->isValidOffset(LOOP_i, CountImm, TRI)) {
       unsigned CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
       BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg)
         .addImm(CountImm);
@@ -1300,7 +1325,8 @@ bool HexagonHardwareLoops::orderBumpCompare(MachineInstr *BumpI,
   if (CmpI->getParent() != BB)
     return false;
 
-  typedef MachineBasicBlock::instr_iterator instr_iterator;
+  using instr_iterator = MachineBasicBlock::instr_iterator;
+
   // Check if things are in order to begin with.
   for (instr_iterator I(BumpI), E = BB->instr_end(); I != E; ++I)
     if (&*I == CmpI)
@@ -1341,7 +1367,7 @@ bool HexagonHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A,
                                         LoopFeederMap &LoopFeederPhi) const {
   if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) {
     const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks();
-    DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber(););
+    DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0]));
     // Ignore all BBs that form Loop.
     for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
       MachineBasicBlock *MBB = Blocks[i];
@@ -1493,14 +1519,13 @@ bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO,
     case Hexagon::A2_tfrsi:
     case Hexagon::A2_tfrpi:
     case Hexagon::CONST32:
-    case Hexagon::CONST64: {
+    case Hexagon::CONST64:
       // Call recursively to avoid an extra check whether operand(1) is
       // indeed an immediate (it could be a global address, for example),
       // plus we can handle COPY at the same time.
       if (!checkForImmediate(DI->getOperand(1), TV))
         return false;
       break;
-    }
     case Hexagon::A2_combineii:
     case Hexagon::A4_combineir:
     case Hexagon::A4_combineii:
@@ -1589,17 +1614,18 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
 
   // These data structures follow the same concept as the corresponding
   // ones in findInductionRegister (where some comments are).
-  typedef std::pair<unsigned,int64_t> RegisterBump;
-  typedef std::pair<unsigned,RegisterBump> RegisterInduction;
-  typedef std::set<RegisterInduction> RegisterInductionSet;
+  using RegisterBump = std::pair<unsigned, int64_t>;
+  using RegisterInduction = std::pair<unsigned, RegisterBump>;
+  using RegisterInductionSet = std::set<RegisterInduction>;
 
   // Register candidates for induction variables, with their associated bumps.
   RegisterInductionSet IndRegs;
 
   // Look for induction patterns:
-  //   vreg1 = PHI ..., [ latch, vreg2 ]
-  //   vreg2 = ADD vreg1, imm
-  typedef MachineBasicBlock::instr_iterator instr_iterator;
+  //   %1 = PHI ..., [ latch, %2 ]
+  //   %2 = ADD %1, imm
+  using instr_iterator = MachineBasicBlock::instr_iterator;
+
   for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
        I != E && I->isPHI(); ++I) {
     MachineInstr *Phi = &*I;
@@ -1694,7 +1720,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
     MachineOperand &MO = PredDef->getOperand(i);
     if (MO.isReg()) {
       // Skip all implicit references.  In one case there was:
-      //   %vreg140<def> = FCMPUGT32_rr %vreg138, %vreg139, %USR<imp-use>
+      //   %140 = FCMPUGT32_rr %138, %139, implicit %usr
       if (MO.isImplicit())
         continue;
       if (MO.isUse()) {
@@ -1834,18 +1860,19 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
   DebugLoc DL;
 
 #ifndef NDEBUG
-  if ((PHFn != "") && (PHFn != MF->getName()))
+  if ((!PHFn.empty()) && (PHFn != MF->getName()))
     return nullptr;
 #endif
 
   if (!Latch || !ExitingBlock || Header->hasAddressTaken())
     return nullptr;
 
-  typedef MachineBasicBlock::instr_iterator instr_iterator;
+  using instr_iterator = MachineBasicBlock::instr_iterator;
 
   // Verify that all existing predecessors have analyzable branches
   // (or no branches at all).
-  typedef std::vector<MachineBasicBlock*> MBBVector;
+  using MBBVector = std::vector<MachineBasicBlock *>;
+
   MBBVector Preds(Header->pred_begin(), Header->pred_end());
   SmallVector<MachineOperand,2> Tmp1;
   MachineBasicBlock *TB = nullptr, *FB = nullptr;
diff --git a/lib/Target/Hexagon/HexagonIICHVX.td b/lib/Target/Hexagon/HexagonIICHVX.td
index 1493d52f08e8..a804c5a80d03 100644
--- a/lib/Target/Hexagon/HexagonIICHVX.td
+++ b/lib/Target/Hexagon/HexagonIICHVX.td
@@ -7,6 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+def CVI_GATHER_PSEUDO : InstrItinClass;
 def CVI_VA            : InstrItinClass;
 
 class HVXItin {
@@ -14,5 +15,14 @@ class HVXItin {
     InstrItinData<CVI_VA,
       [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
        InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>],
-      [9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>];
+      [9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+    // Used by Gather Pseudo Instructions which are expanded into
+    // V6_vgather* and V6_vS32b_new_ai. Even though these instructions
+    // use CVI_ST resource, it's not included below to avoid having more than
+    // 4 InstrStages and thus changing 'MaxResTerms' to 5.
+    InstrItinData <CVI_GATHER_PSEUDO,
+      [InstrStage<1, [SLOT0], 0>,
+       InstrStage<1, [CVI_LD], 0>, InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [CVI_MPY01, CVI_XLSHF]>]>];
 }
diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 0163b2e2bdc4..a6ac4e3df745 100644
--- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "Hexagon.h"
+#include "HexagonISelDAGToDAG.h"
 #include "HexagonISelLowering.h"
 #include "HexagonMachineFunctionInfo.h"
 #include "HexagonTargetMachine.h"
@@ -43,109 +44,15 @@ cl::opt<bool>
 RebalanceOnlyImbalancedTrees("rebalance-only-imbal", cl::Hidden,
   cl::init(false), cl::desc("Rebalance address tree only if it is imbalanced"));
 
+static cl::opt<bool> CheckSingleUse("hexagon-isel-su", cl::Hidden,
+  cl::init(true), cl::desc("Enable checking of SDNode's single-use status"));
+
 //===----------------------------------------------------------------------===//
 // Instruction Selector Implementation
 //===----------------------------------------------------------------------===//
 
-//===--------------------------------------------------------------------===//
-/// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
-/// instructions for SelectionDAG operations.
-///
-namespace {
-class HexagonDAGToDAGISel : public SelectionDAGISel {
-  const HexagonSubtarget *HST;
-  const HexagonInstrInfo *HII;
-  const HexagonRegisterInfo *HRI;
-public:
-  explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
-                               CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
-        HRI(nullptr) {}
-
-  bool runOnMachineFunction(MachineFunction &MF) override {
-    // Reset the subtarget each time through.
-    HST = &MF.getSubtarget<HexagonSubtarget>();
-    HII = HST->getInstrInfo();
-    HRI = HST->getRegisterInfo();
-    SelectionDAGISel::runOnMachineFunction(MF);
-    return true;
-  }
-
-  bool ComplexPatternFuncMutatesDAG() const override {
-    return true;
-  }
-  void PreprocessISelDAG() override;
-  void EmitFunctionEntryCode() override;
-
-  void Select(SDNode *N) override;
-
-  // Complex Pattern Selectors.
-  inline bool SelectAddrGA(SDValue &N, SDValue &R);
-  inline bool SelectAddrGP(SDValue &N, SDValue &R);
-  bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
-  bool SelectAddrFI(SDValue &N, SDValue &R);
-  bool DetectUseSxtw(SDValue &N, SDValue &R);
-
-  StringRef getPassName() const override {
-    return "Hexagon DAG->DAG Pattern Instruction Selection";
-  }
-
-  // Generate a machine instruction node corresponding to the circ/brev
-  // load intrinsic.
-  MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN);
-  // Given the circ/brev load intrinsic and the already generated machine
-  // instruction, generate the appropriate store (that is a part of the
-  // intrinsic's functionality).
-  SDNode *StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN);
-
-  void SelectFrameIndex(SDNode *N);
-  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
-  /// inline asm expressions.
-  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                    unsigned ConstraintID,
-                                    std::vector<SDValue> &OutOps) override;
-  bool tryLoadOfLoadIntrinsic(LoadSDNode *N);
-  void SelectLoad(SDNode *N);
-  void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
-  void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
-  void SelectStore(SDNode *N);
-  void SelectSHL(SDNode *N);
-  void SelectZeroExtend(SDNode *N);
-  void SelectIntrinsicWChain(SDNode *N);
-  void SelectIntrinsicWOChain(SDNode *N);
-  void SelectConstant(SDNode *N);
-  void SelectConstantFP(SDNode *N);
-  void SelectBitcast(SDNode *N);
-
-  // Include the pieces autogenerated from the target description.
-  #include "HexagonGenDAGISel.inc"
-
-private:
-  bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
-  bool isOrEquivalentToAdd(const SDNode *N) const;
-  bool isAlignedMemNode(const MemSDNode *N) const;
-  bool isSmallStackStore(const StoreSDNode *N) const;
-  bool isPositiveHalfWord(const SDNode *N) const;
-
-  // DAG preprocessing functions.
-  void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
-  void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
-  void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
-  void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
-
-  SmallDenseMap<SDNode *,int> RootWeights;
-  SmallDenseMap<SDNode *,int> RootHeights;
-  SmallDenseMap<const Value *,int> GAUsesInFunction;
-  int getWeight(SDNode *N);
-  int getHeight(SDNode *N);
-  SDValue getMultiplierForSHL(SDNode *N);
-  SDValue factorOutPowerOf2(SDValue V, unsigned Power);
-  unsigned getUsesInFunction(const Value *V);
-  SDValue balanceSubTree(SDNode *N, bool Factorize = false);
-  void rebalanceAddressTrees();
-}; // end HexagonDAGToDAGISel
-}  // end anonymous namespace
-
+#define GET_DAGISEL_BODY HexagonDAGToDAGISel
+#include "HexagonGenDAGISel.inc"
 
 /// createHexagonISelDag - This pass converts a legalized DAG into a
 /// Hexagon-specific DAG, ready for instruction scheduling.
@@ -241,30 +148,17 @@ void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
   case MVT::v32i16:
   case MVT::v16i32:
   case MVT::v8i64:
-    if (isAlignedMemNode(LD)) {
-      if (LD->isNonTemporal())
-        Opcode = IsValidInc ? Hexagon::V6_vL32b_nt_pi : Hexagon::V6_vL32b_nt_ai;
-      else
-        Opcode = IsValidInc ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32b_ai;
-    } else {
-      Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi : Hexagon::V6_vL32Ub_ai;
-    }
-    break;
-  // 128B
   case MVT::v128i8:
   case MVT::v64i16:
   case MVT::v32i32:
   case MVT::v16i64:
     if (isAlignedMemNode(LD)) {
       if (LD->isNonTemporal())
-        Opcode = IsValidInc ? Hexagon::V6_vL32b_nt_pi_128B
-                            : Hexagon::V6_vL32b_nt_ai_128B;
+        Opcode = IsValidInc ? Hexagon::V6_vL32b_nt_pi : Hexagon::V6_vL32b_nt_ai;
       else
-        Opcode = IsValidInc ? Hexagon::V6_vL32b_pi_128B
-                            : Hexagon::V6_vL32b_ai_128B;
+        Opcode = IsValidInc ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32b_ai;
     } else {
-      Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi_128B
-                          : Hexagon::V6_vL32Ub_ai_128B;
+      Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi : Hexagon::V6_vL32Ub_ai;
     }
     break;
   default:
@@ -533,35 +427,21 @@ void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl) {
   case MVT::i64:
     Opcode = IsValidInc ? Hexagon::S2_storerd_pi : Hexagon::S2_storerd_io;
     break;
-  // 64B
   case MVT::v64i8:
   case MVT::v32i16:
   case MVT::v16i32:
   case MVT::v8i64:
-    if (isAlignedMemNode(ST)) {
-      if (ST->isNonTemporal())
-        Opcode = IsValidInc ? Hexagon::V6_vS32b_nt_pi : Hexagon::V6_vS32b_nt_ai;
-      else
-        Opcode = IsValidInc ? Hexagon::V6_vS32b_pi : Hexagon::V6_vS32b_ai;
-    } else {
-      Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi : Hexagon::V6_vS32Ub_ai;
-    }
-    break;
-  // 128B
   case MVT::v128i8:
   case MVT::v64i16:
   case MVT::v32i32:
   case MVT::v16i64:
     if (isAlignedMemNode(ST)) {
       if (ST->isNonTemporal())
-        Opcode = IsValidInc ? Hexagon::V6_vS32b_nt_pi_128B
-                            : Hexagon::V6_vS32b_nt_ai_128B;
+        Opcode = IsValidInc ? Hexagon::V6_vS32b_nt_pi : Hexagon::V6_vS32b_nt_ai;
       else
-        Opcode = IsValidInc ? Hexagon::V6_vS32b_pi_128B
-                            : Hexagon::V6_vS32b_ai_128B;
+        Opcode = IsValidInc ? Hexagon::V6_vS32b_pi : Hexagon::V6_vS32b_ai;
     } else {
-      Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi_128B
-                          : Hexagon::V6_vS32Ub_ai_128B;
+      Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi : Hexagon::V6_vS32Ub_ai;
     }
     break;
   default:
@@ -761,6 +641,27 @@ void HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
     CurDAG->RemoveDeadNode(N);
     return;
   }
+
+  unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+  if (IntNo == Intrinsic::hexagon_V6_vgathermw ||
+      IntNo == Intrinsic::hexagon_V6_vgathermw_128B ||
+      IntNo == Intrinsic::hexagon_V6_vgathermh ||
+      IntNo == Intrinsic::hexagon_V6_vgathermh_128B ||
+      IntNo == Intrinsic::hexagon_V6_vgathermhw ||
+      IntNo == Intrinsic::hexagon_V6_vgathermhw_128B) {
+    SelectV65Gather(N);
+    return;
+  }
+  if (IntNo == Intrinsic::hexagon_V6_vgathermwq ||
+      IntNo == Intrinsic::hexagon_V6_vgathermwq_128B ||
+      IntNo == Intrinsic::hexagon_V6_vgathermhq ||
+      IntNo == Intrinsic::hexagon_V6_vgathermhq_128B ||
+      IntNo == Intrinsic::hexagon_V6_vgathermhwq ||
+      IntNo == Intrinsic::hexagon_V6_vgathermhwq_128B) {
+    SelectV65GatherPred(N);
+    return;
+  }
+
   SelectCode(N);
 }
 
@@ -774,6 +675,12 @@ void HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
   case Intrinsic::hexagon_S2_vsplatrh:
     Bits = 16;
     break;
+  case Intrinsic::hexagon_V6_vaddcarry:
+  case Intrinsic::hexagon_V6_vaddcarry_128B:
+  case Intrinsic::hexagon_V6_vsubcarry:
+  case Intrinsic::hexagon_V6_vsubcarry_128B:
+    SelectHVXDualOutput(N);
+    return;
   default:
     SelectCode(N);
     return;
@@ -874,7 +781,6 @@ void HexagonDAGToDAGISel::SelectBitcast(SDNode *N) {
   CurDAG->RemoveDeadNode(N);
 }
 
-
 void HexagonDAGToDAGISel::Select(SDNode *N) {
   if (N->isMachineOpcode())
     return N->setNodeId(-1);  // Already selected.
@@ -892,6 +798,13 @@ void HexagonDAGToDAGISel::Select(SDNode *N) {
   case ISD::INTRINSIC_WO_CHAIN:   return SelectIntrinsicWOChain(N);
   }
 
+  if (HST->useHVXOps()) {
+    switch (N->getOpcode()) {
+    case ISD::VECTOR_SHUFFLE:     return SelectHvxShuffle(N);
+    case HexagonISD::VROR:        return SelectHvxRor(N);
+    }
+  }
+
   SelectCode(N);
 }
 
@@ -1277,15 +1190,88 @@ bool HexagonDAGToDAGISel::SelectAddrFI(SDValue &N, SDValue &R) {
 }
 
 inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
-  return SelectGlobalAddress(N, R, false);
+  return SelectGlobalAddress(N, R, false, 0);
 }
 
 inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
-  return SelectGlobalAddress(N, R, true);
+  return SelectGlobalAddress(N, R, true, 0);
+}
+
+inline bool HexagonDAGToDAGISel::SelectAnyImm(SDValue &N, SDValue &R) {
+  return SelectAnyImmediate(N, R, 0);
+}
+
+inline bool HexagonDAGToDAGISel::SelectAnyImm0(SDValue &N, SDValue &R) {
+  return SelectAnyImmediate(N, R, 0);
+}
+inline bool HexagonDAGToDAGISel::SelectAnyImm1(SDValue &N, SDValue &R) {
+  return SelectAnyImmediate(N, R, 1);
+}
+inline bool HexagonDAGToDAGISel::SelectAnyImm2(SDValue &N, SDValue &R) {
+  return SelectAnyImmediate(N, R, 2);
+}
+inline bool HexagonDAGToDAGISel::SelectAnyImm3(SDValue &N, SDValue &R) {
+  return SelectAnyImmediate(N, R, 3);
+}
+
+inline bool HexagonDAGToDAGISel::SelectAnyInt(SDValue &N, SDValue &R) {
+  EVT T = N.getValueType();
+  if (!T.isInteger() || T.getSizeInBits() != 32 || !isa<ConstantSDNode>(N))
+    return false;
+  R = N;
+  return true;
+}
+
+bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R,
+                                             uint32_t LogAlign) {
+  auto IsAligned = [LogAlign] (uint64_t V) -> bool {
+    return alignTo(V, (uint64_t)1 << LogAlign) == V;
+  };
+
+  switch (N.getOpcode()) {
+  case ISD::Constant: {
+    if (N.getValueType() != MVT::i32)
+      return false;
+    int32_t V = cast<const ConstantSDNode>(N)->getZExtValue();
+    if (!IsAligned(V))
+      return false;
+    R = CurDAG->getTargetConstant(V, SDLoc(N), N.getValueType());
+    return true;
+  }
+  case HexagonISD::JT:
+  case HexagonISD::CP:
+    // These are assumed to always be aligned at at least 8-byte boundary.
+    if (LogAlign > 3)
+      return false;
+    R = N.getOperand(0);
+    return true;
+  case ISD::ExternalSymbol:
+    // Symbols may be aligned at any boundary.
+    if (LogAlign > 0)
+      return false;
+    R = N;
+    return true;
+  case ISD::BlockAddress:
+    // Block address is always aligned at at least 4-byte boundary.
+    if (LogAlign > 2 || !IsAligned(cast<BlockAddressSDNode>(N)->getOffset()))
+      return false;
+    R = N;
+    return true;
+  }
+
+  if (SelectGlobalAddress(N, R, false, LogAlign) ||
+      SelectGlobalAddress(N, R, true, LogAlign))
+    return true;
+
+  return false;
 }
 
 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
-                                              bool UseGP) {
+                                              bool UseGP, uint32_t LogAlign) {
+  auto IsAligned = [LogAlign] (uint64_t V) -> bool {
+    return alignTo(V, (uint64_t)1 << LogAlign) == V;
+  };
+
   switch (N.getOpcode()) {
   case ISD::ADD: {
     SDValue N0 = N.getOperand(0);
@@ -1297,6 +1283,9 @@ bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
       return false;
     if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
       SDValue Addr = N0.getOperand(0);
+      // For the purpose of alignment, sextvalue and zextvalue are the same.
+      if (!IsAligned(Const->getZExtValue()))
+        return false;
       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
         if (GA->getOpcode() == ISD::TargetGlobalAddress) {
           uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
@@ -1308,6 +1297,8 @@ bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
     }
     break;
   }
+  case HexagonISD::CP:
+  case HexagonISD::JT:
   case HexagonISD::CONST32:
     // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
     // want in the instruction.
@@ -1346,7 +1337,6 @@ bool HexagonDAGToDAGISel::DetectUseSxtw(SDValue &N, SDValue &R) {
 
   if (N.getValueType() != MVT::i64)
     return false;
-  EVT SrcVT;
   unsigned Opc = N.getOpcode();
   switch (Opc) {
     case ISD::SIGN_EXTEND:
@@ -1458,25 +1448,6 @@ bool HexagonDAGToDAGISel::keepsLowBits(const SDValue &Val, unsigned NumBits,
   return false;
 }
 
-
-bool HexagonDAGToDAGISel::isOrEquivalentToAdd(const SDNode *N) const {
-  assert(N->getOpcode() == ISD::OR);
-  auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
-  assert(C);
-
-  // Detect when "or" is used to add an offset to a stack object.
-  if (auto *FN = dyn_cast<FrameIndexSDNode>(N->getOperand(0))) {
-    MachineFrameInfo &MFI = MF->getFrameInfo();
-    unsigned A = MFI.getObjectAlignment(FN->getIndex());
-    assert(isPowerOf2_32(A));
-    int32_t Off = C->getSExtValue();
-    // If the alleged offset fits in the zero bits guaranteed by
-    // the alignment, then this or is really an add.
-    return (Off >= 0) && (((A-1) & Off) == unsigned(Off));
-  }
-  return false;
-}
-
 bool HexagonDAGToDAGISel::isAlignedMemNode(const MemSDNode *N) const {
   return N->getAlignment() >= N->getMemoryVT().getStoreSize();
 }
@@ -1508,6 +1479,10 @@ bool HexagonDAGToDAGISel::isPositiveHalfWord(const SDNode *N) const {
   return false;
 }
 
+bool HexagonDAGToDAGISel::hasOneUse(const SDNode *N) const {
+  return !CheckSingleUse || N->hasOneUse();
+}
+
 ////////////////////////////////////////////////////////////////////////////////
 // Rebalancing of address calculation trees
 
@@ -1771,10 +1746,10 @@ unsigned HexagonDAGToDAGISel::getUsesInFunction(const Value *V) {
     return GAUsesInFunction[V];
 
   unsigned Result = 0;
-  const Function *CurF = CurDAG->getMachineFunction().getFunction();
+  const Function &CurF = CurDAG->getMachineFunction().getFunction();
   for (const User *U : V->users()) {
     if (isa<Instruction>(U) &&
-        cast<Instruction>(U)->getParent()->getParent() == CurF)
+        cast<Instruction>(U)->getParent()->getParent() == &CurF)
       ++Result;
   }
 
diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/lib/Target/Hexagon/HexagonISelDAGToDAG.h
new file mode 100644
index 000000000000..fc66940ee52d
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.h
@@ -0,0 +1,151 @@
+//===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// Hexagon specific code to select Hexagon machine instructions for
+// SelectionDAG operations.
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
+#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
+
+#include "HexagonSubtarget.h"
+#include "HexagonTargetMachine.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/Support/CodeGen.h"
+
+#include <vector>
+
+namespace llvm {
+class MachineFunction;
+class HexagonInstrInfo;
+class HexagonRegisterInfo;
+class HexagonTargetLowering;
+
+class HexagonDAGToDAGISel : public SelectionDAGISel {
+  const HexagonSubtarget *HST;
+  const HexagonInstrInfo *HII;
+  const HexagonRegisterInfo *HRI;
+public:
+  explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
+                               CodeGenOpt::Level OptLevel)
+      : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
+        HRI(nullptr) {}
+
+  bool runOnMachineFunction(MachineFunction &MF) override {
+    // Reset the subtarget each time through.
+    HST = &MF.getSubtarget<HexagonSubtarget>();
+    HII = HST->getInstrInfo();
+    HRI = HST->getRegisterInfo();
+    SelectionDAGISel::runOnMachineFunction(MF);
+    return true;
+  }
+
+  bool ComplexPatternFuncMutatesDAG() const override {
+    return true;
+  }
+  void PreprocessISelDAG() override;
+  void EmitFunctionEntryCode() override;
+
+  void Select(SDNode *N) override;
+
+  // Complex Pattern Selectors.
+  inline bool SelectAddrGA(SDValue &N, SDValue &R);
+  inline bool SelectAddrGP(SDValue &N, SDValue &R);
+  inline bool SelectAnyImm(SDValue &N, SDValue &R);
+  inline bool SelectAnyInt(SDValue &N, SDValue &R);
+  bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign);
+  bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP,
+                           uint32_t LogAlign);
+  bool SelectAddrFI(SDValue &N, SDValue &R);
+  bool DetectUseSxtw(SDValue &N, SDValue &R);
+
+  inline bool SelectAnyImm0(SDValue &N, SDValue &R);
+  inline bool SelectAnyImm1(SDValue &N, SDValue &R);
+  inline bool SelectAnyImm2(SDValue &N, SDValue &R);
+  inline bool SelectAnyImm3(SDValue &N, SDValue &R);
+
+  StringRef getPassName() const override {
+    return "Hexagon DAG->DAG Pattern Instruction Selection";
+  }
+
+  // Generate a machine instruction node corresponding to the circ/brev
+  // load intrinsic.
+  MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN);
+  // Given the circ/brev load intrinsic and the already generated machine
+  // instruction, generate the appropriate store (that is a part of the
+  // intrinsic's functionality).
+  SDNode *StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN);
+
+  void SelectFrameIndex(SDNode *N);
+  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+  /// inline asm expressions.
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                    unsigned ConstraintID,
+                                    std::vector<SDValue> &OutOps) override;
+  bool tryLoadOfLoadIntrinsic(LoadSDNode *N);
+  void SelectLoad(SDNode *N);
+  void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
+  void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
+  void SelectStore(SDNode *N);
+  void SelectSHL(SDNode *N);
+  void SelectZeroExtend(SDNode *N);
+  void SelectIntrinsicWChain(SDNode *N);
+  void SelectIntrinsicWOChain(SDNode *N);
+  void SelectConstant(SDNode *N);
+  void SelectConstantFP(SDNode *N);
+  void SelectBitcast(SDNode *N);
+  void SelectV65Gather(SDNode *N);
+  void SelectV65GatherPred(SDNode *N);
+  void SelectHVXDualOutput(SDNode *N);
+
+  // Include the declarations autogenerated from the selection patterns.
+  #define GET_DAGISEL_DECL
+  #include "HexagonGenDAGISel.inc"
+
+private:
+  // This is really only to get access to ReplaceNode (which is a protected
+  // member). Any other members used by HvxSelector can be moved around to
+  // make them accessible).
+  friend struct HvxSelector;
+
+  SDValue selectUndef(const SDLoc &dl, MVT ResTy) {
+    SDNode *U = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy);
+    return SDValue(U, 0);
+  }
+
+  void SelectHvxShuffle(SDNode *N);
+  void SelectHvxRor(SDNode *N);
+
+  bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
+  bool isAlignedMemNode(const MemSDNode *N) const;
+  bool isSmallStackStore(const StoreSDNode *N) const;
+  bool isPositiveHalfWord(const SDNode *N) const;
+  bool hasOneUse(const SDNode *N) const;
+
+  // DAG preprocessing functions.
+  void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
+  void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
+  void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
+  void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
+
+  SmallDenseMap<SDNode *,int> RootWeights;
+  SmallDenseMap<SDNode *,int> RootHeights;
+  SmallDenseMap<const Value *,int> GAUsesInFunction;
+  int getWeight(SDNode *N);
+  int getHeight(SDNode *N);
+  SDValue getMultiplierForSHL(SDNode *N);
+  SDValue factorOutPowerOf2(SDValue V, unsigned Power);
+  unsigned getUsesInFunction(const Value *V);
+  SDValue balanceSubTree(SDNode *N, bool Factorize = false);
+  void rebalanceAddressTrees();
+}; // end HexagonDAGToDAGISel
+}
+
+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
new file mode 100644
index 000000000000..537f97c9a987
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
@@ -0,0 +1,2108 @@
+//===-- HexagonISelDAGToDAGHVX.cpp ----------------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Hexagon.h"
+#include "HexagonISelDAGToDAG.h"
+#include "HexagonISelLowering.h"
+#include "HexagonTargetMachine.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/IR/Intrinsics.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+
+#include <deque>
+#include <map>
+#include <set>
+#include <utility>
+#include <vector>
+
+#define DEBUG_TYPE "hexagon-isel"
+
+using namespace llvm;
+
+// --------------------------------------------------------------------
+// Implementation of permutation networks.
+
+// Implementation of the node routing through butterfly networks:
+// - Forward delta.
+// - Reverse delta.
+// - Benes.
+//
+//
+// Forward delta network consists of log(N) steps, where N is the number
+// of inputs. In each step, an input can stay in place, or it can get
+// routed to another position[1]. The step after that consists of two
+// networks, each half in size in terms of the number of nodes. In those
+// terms, in the given step, an input can go to either the upper or the
+// lower network in the next step.
+//
+// [1] Hexagon's vdelta/vrdelta allow an element to be routed to both
+// positions as long as there is no conflict.
+
+// Here's a delta network for 8 inputs, only the switching routes are
+// shown:
+//
+//         Steps:
+//         |- 1 ---------------|- 2 -----|- 3 -|
+//
+// Inp[0] ***                 ***       ***   *** Out[0]
+//           \               /   \     /   \ /
+//            \             /     \   /     X
+//             \           /       \ /     / \
+// Inp[1] ***   \         /   ***   X   ***   *** Out[1]
+//           \   \       /   /   \ / \ /
+//            \   \     /   /     X   X
+//             \   \   /   /     / \ / \
+// Inp[2] ***   \   \ /   /   ***   X   ***   *** Out[2]
+//           \   \   X   /   /     / \     \ /
+//            \   \ / \ /   /     /   \     X
+//             \   X   X   /     /     \   / \
+// Inp[3] ***   \ / \ / \ /   ***       ***   *** Out[3]
+//           \   X   X   X   /
+//            \ / \ / \ / \ /
+//             X   X   X   X
+//            / \ / \ / \ / \
+//           /   X   X   X   \
+// Inp[4] ***   / \ / \ / \   ***       ***   *** Out[4]
+//             /   X   X   \     \     /   \ /
+//            /   / \ / \   \     \   /     X
+//           /   /   X   \   \     \ /     / \
+// Inp[5] ***   /   / \   \   ***   X   ***   *** Out[5]
+//             /   /   \   \     \ / \ /
+//            /   /     \   \     X   X
+//           /   /       \   \   / \ / \
+// Inp[6] ***   /         \   ***   X   ***   *** Out[6]
+//             /           \       / \     \ /
+//            /             \     /   \     X
+//           /               \   /     \   / \
+// Inp[7] ***                 ***       ***   *** Out[7]
+//
+//
+// Reverse delta network is same as delta network, with the steps in
+// the opposite order.
+//
+//
+// Benes network is a forward delta network immediately followed by
+// a reverse delta network.
+
+
+// Graph coloring utility used to partition nodes into two groups:
+// they will correspond to nodes routed to the upper and lower networks.
+struct Coloring {
+  enum : uint8_t {
+    None = 0,
+    Red,
+    Black
+  };
+
+  using Node = int;
+  using MapType = std::map<Node,uint8_t>;
+  static constexpr Node Ignore = Node(-1);
+
+  Coloring(ArrayRef<Node> Ord) : Order(Ord) {
+    build();
+    if (!color())
+      Colors.clear();
+  }
+
+  const MapType &colors() const {
+    return Colors;
+  }
+
+  uint8_t other(uint8_t Color) {
+    if (Color == None)
+      return Red;
+    return Color == Red ? Black : Red;
+  }
+
+  void dump() const;
+
+private:
+  ArrayRef<Node> Order;
+  MapType Colors;
+  std::set<Node> Needed;
+
+  using NodeSet = std::set<Node>;
+  std::map<Node,NodeSet> Edges;
+
+  Node conj(Node Pos) {
+    Node Num = Order.size();
+    return (Pos < Num/2) ? Pos + Num/2 : Pos - Num/2;
+  }
+
+  uint8_t getColor(Node N) {
+    auto F = Colors.find(N);
+    return F != Colors.end() ? F->second : (uint8_t)None;
+  }
+
+  std::pair<bool,uint8_t> getUniqueColor(const NodeSet &Nodes);
+
+  void build();
+  bool color();
+};
+
+std::pair<bool,uint8_t> Coloring::getUniqueColor(const NodeSet &Nodes) {
+  uint8_t Color = None;
+  for (Node N : Nodes) {
+    uint8_t ColorN = getColor(N);
+    if (ColorN == None)
+      continue;
+    if (Color == None)
+      Color = ColorN;
+    else if (Color != None && Color != ColorN)
+      return { false, None };
+  }
+  return { true, Color };
+}
+
+void Coloring::build() {
+  // Add Order[P] and Order[conj(P)] to Edges.
+  for (unsigned P = 0; P != Order.size(); ++P) {
+    Node I = Order[P];
+    if (I != Ignore) {
+      Needed.insert(I);
+      Node PC = Order[conj(P)];
+      if (PC != Ignore && PC != I)
+        Edges[I].insert(PC);
+    }
+  }
+  // Add I and conj(I) to Edges.
+  for (unsigned I = 0; I != Order.size(); ++I) {
+    if (!Needed.count(I))
+      continue;
+    Node C = conj(I);
+    // This will create an entry in the edge table, even if I is not
+    // connected to any other node. This is necessary, because it still
+    // needs to be colored.
+    NodeSet &Is = Edges[I];
+    if (Needed.count(C))
+      Is.insert(C);
+  }
+}
+
+bool Coloring::color() {
+  SetVector<Node> FirstQ;
+  auto Enqueue = [this,&FirstQ] (Node N) {
+    SetVector<Node> Q;
+    Q.insert(N);
+    for (unsigned I = 0; I != Q.size(); ++I) {
+      NodeSet &Ns = Edges[Q[I]];
+      Q.insert(Ns.begin(), Ns.end());
+    }
+    FirstQ.insert(Q.begin(), Q.end());
+  };
+  for (Node N : Needed)
+    Enqueue(N);
+
+  for (Node N : FirstQ) {
+    if (Colors.count(N))
+      continue;
+    NodeSet &Ns = Edges[N];
+    auto P = getUniqueColor(Ns);
+    if (!P.first)
+      return false;
+    Colors[N] = other(P.second);
+  }
+
+  // First, color nodes that don't have any dups.
+  for (auto E : Edges) {
+    Node N = E.first;
+    if (!Needed.count(conj(N)) || Colors.count(N))
+      continue;
+    auto P = getUniqueColor(E.second);
+    if (!P.first)
+      return false;
+    Colors[N] = other(P.second);
+  }
+
+  // Now, nodes that are still uncolored. Since the graph can be modified
+  // in this step, create a work queue.
+  std::vector<Node> WorkQ;
+  for (auto E : Edges) {
+    Node N = E.first;
+    if (!Colors.count(N))
+      WorkQ.push_back(N);
+  }
+
+  for (unsigned I = 0; I < WorkQ.size(); ++I) {
+    Node N = WorkQ[I];
+    NodeSet &Ns = Edges[N];
+    auto P = getUniqueColor(Ns);
+    if (P.first) {
+      Colors[N] = other(P.second);
+      continue;
+    }
+
+    // Coloring failed. Split this node.
+    Node C = conj(N);
+    uint8_t ColorN = other(None);
+    uint8_t ColorC = other(ColorN);
+    NodeSet &Cs = Edges[C];
+    NodeSet CopyNs = Ns;
+    for (Node M : CopyNs) {
+      uint8_t ColorM = getColor(M);
+      if (ColorM == ColorC) {
+        // Connect M with C, disconnect M from N.
+        Cs.insert(M);
+        Edges[M].insert(C);
+        Ns.erase(M);
+        Edges[M].erase(N);
+      }
+    }
+    Colors[N] = ColorN;
+    Colors[C] = ColorC;
+  }
+
+  // Explicitly assign "None" all all uncolored nodes.
+  for (unsigned I = 0; I != Order.size(); ++I)
+    if (Colors.count(I) == 0)
+      Colors[I] = None;
+
+  return true;
+}
+
+LLVM_DUMP_METHOD
+void Coloring::dump() const {
+  dbgs() << "{ Order:   {";
+  for (unsigned I = 0; I != Order.size(); ++I) {
+    Node P = Order[I];
+    if (P != Ignore)
+      dbgs() << ' ' << P;
+    else
+      dbgs() << " -";
+  }
+  dbgs() << " }\n";
+  dbgs() << "  Needed: {";
+  for (Node N : Needed)
+    dbgs() << ' ' << N;
+  dbgs() << " }\n";
+
+  dbgs() << "  Edges: {\n";
+  for (auto E : Edges) {
+    dbgs() << "    " << E.first << " -> {";
+    for (auto N : E.second)
+      dbgs() << ' ' << N;
+    dbgs() << " }\n";
+  }
+  dbgs() << "  }\n";
+
+  static const char *const Names[] = { "None", "Red", "Black" };
+  dbgs() << "  Colors: {\n";
+  for (auto C : Colors)
+    dbgs() << "    " << C.first << " -> " << Names[C.second] << "\n";
+  dbgs() << "  }\n}\n";
+}
+
+// Base class of for reordering networks. They don't strictly need to be
+// permutations, as outputs with repeated occurrences of an input element
+// are allowed.
+struct PermNetwork {
+  using Controls = std::vector<uint8_t>;
+  using ElemType = int;
+  static constexpr ElemType Ignore = ElemType(-1);
+
+  enum : uint8_t {
+    None,
+    Pass,
+    Switch
+  };
+  enum : uint8_t {
+    Forward,
+    Reverse
+  };
+
+  PermNetwork(ArrayRef<ElemType> Ord, unsigned Mult = 1) {
+    Order.assign(Ord.data(), Ord.data()+Ord.size());
+    Log = 0;
+
+    unsigned S = Order.size();
+    while (S >>= 1)
+      ++Log;
+
+    Table.resize(Order.size());
+    for (RowType &Row : Table)
+      Row.resize(Mult*Log, None);
+  }
+
+  void getControls(Controls &V, unsigned StartAt, uint8_t Dir) const {
+    unsigned Size = Order.size();
+    V.resize(Size);
+    for (unsigned I = 0; I != Size; ++I) {
+      unsigned W = 0;
+      for (unsigned L = 0; L != Log; ++L) {
+        unsigned C = ctl(I, StartAt+L) == Switch;
+        if (Dir == Forward)
+          W |= C << (Log-1-L);
+        else
+          W |= C << L;
+      }
+      assert(isUInt<8>(W));
+      V[I] = uint8_t(W);
+    }
+  }
+
+  uint8_t ctl(ElemType Pos, unsigned Step) const {
+    return Table[Pos][Step];
+  }
+  unsigned size() const {
+    return Order.size();
+  }
+  unsigned steps() const {
+    return Log;
+  }
+
+protected:
+  unsigned Log;
+  std::vector<ElemType> Order;
+  using RowType = std::vector<uint8_t>;
+  std::vector<RowType> Table;
+};
+
+struct ForwardDeltaNetwork : public PermNetwork {
+  ForwardDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {}
+
+  bool run(Controls &V) {
+    if (!route(Order.data(), Table.data(), size(), 0))
+      return false;
+    getControls(V, 0, Forward);
+    return true;
+  }
+
+private:
+  bool route(ElemType *P, RowType *T, unsigned Size, unsigned Step);
+};
+
+struct ReverseDeltaNetwork : public PermNetwork {
+  ReverseDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {}
+
+  bool run(Controls &V) {
+    if (!route(Order.data(), Table.data(), size(), 0))
+      return false;
+    getControls(V, 0, Reverse);
+    return true;
+  }
+
+private:
+  bool route(ElemType *P, RowType *T, unsigned Size, unsigned Step);
+};
+
+struct BenesNetwork : public PermNetwork {
+  BenesNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord, 2) {}
+
+  bool run(Controls &F, Controls &R) {
+    if (!route(Order.data(), Table.data(), size(), 0))
+      return false;
+
+    getControls(F, 0, Forward);
+    getControls(R, Log, Reverse);
+    return true;
+  }
+
+private:
+  bool route(ElemType *P, RowType *T, unsigned Size, unsigned Step);
+};
+
+
+bool ForwardDeltaNetwork::route(ElemType *P, RowType *T, unsigned Size,
+                                unsigned Step) {
+  bool UseUp = false, UseDown = false;
+  ElemType Num = Size;
+
+  // Cannot use coloring here, because coloring is used to determine
+  // the "big" switch, i.e. the one that changes halves, and in a forward
+  // network, a color can be simultaneously routed to both halves in the
+  // step we're working on.
+  for (ElemType J = 0; J != Num; ++J) {
+    ElemType I = P[J];
+    // I is the position in the input,
+    // J is the position in the output.
+    if (I == Ignore)
+      continue;
+    uint8_t S;
+    if (I < Num/2)
+      S = (J < Num/2) ? Pass : Switch;
+    else
+      S = (J < Num/2) ? Switch : Pass;
+
+    // U is the element in the table that needs to be updated.
+    ElemType U = (S == Pass) ? I : (I < Num/2 ? I+Num/2 : I-Num/2);
+    if (U < Num/2)
+      UseUp = true;
+    else
+      UseDown = true;
+    if (T[U][Step] != S && T[U][Step] != None)
+      return false;
+    T[U][Step] = S;
+  }
+
+  for (ElemType J = 0; J != Num; ++J)
+    if (P[J] != Ignore && P[J] >= Num/2)
+      P[J] -= Num/2;
+
+  if (Step+1 < Log) {
+    if (UseUp   && !route(P,        T,        Size/2, Step+1))
+      return false;
+    if (UseDown && !route(P+Size/2, T+Size/2, Size/2, Step+1))
+      return false;
+  }
+  return true;
+}
+
+bool ReverseDeltaNetwork::route(ElemType *P, RowType *T, unsigned Size,
+                                unsigned Step) {
+  unsigned Pets = Log-1 - Step;
+  bool UseUp = false, UseDown = false;
+  ElemType Num = Size;
+
+  // In this step half-switching occurs, so coloring can be used.
+  Coloring G({P,Size});
+  const Coloring::MapType &M = G.colors();
+  if (M.empty())
+    return false;
+
+  uint8_t ColorUp = Coloring::None;
+  for (ElemType J = 0; J != Num; ++J) {
+    ElemType I = P[J];
+    // I is the position in the input,
+    // J is the position in the output.
+    if (I == Ignore)
+      continue;
+    uint8_t C = M.at(I);
+    if (C == Coloring::None)
+      continue;
+    // During "Step", inputs cannot switch halves, so if the "up" color
+    // is still unknown, make sure that it is selected in such a way that
+    // "I" will stay in the same half.
+    bool InpUp = I < Num/2;
+    if (ColorUp == Coloring::None)
+      ColorUp = InpUp ? C : G.other(C);
+    if ((C == ColorUp) != InpUp) {
+      // If I should go to a different half than where is it now, give up.
+      return false;
+    }
+
+    uint8_t S;
+    if (InpUp) {
+      S = (J < Num/2) ? Pass : Switch;
+      UseUp = true;
+    } else {
+      S = (J < Num/2) ? Switch : Pass;
+      UseDown = true;
+    }
+    T[J][Pets] = S;
+  }
+
+  // Reorder the working permutation according to the computed switch table
+  // for the last step (i.e. Pets).
+  for (ElemType J = 0, E = Size / 2; J != E; ++J) {
+    ElemType PJ = P[J];         // Current values of P[J]
+    ElemType PC = P[J+Size/2];  // and P[conj(J)]
+    ElemType QJ = PJ;           // New values of P[J]
+    ElemType QC = PC;           // and P[conj(J)]
+    if (T[J][Pets] == Switch)
+      QC = PJ;
+    if (T[J+Size/2][Pets] == Switch)
+      QJ = PC;
+    P[J] = QJ;
+    P[J+Size/2] = QC;
+  }
+
+  for (ElemType J = 0; J != Num; ++J)
+    if (P[J] != Ignore && P[J] >= Num/2)
+      P[J] -= Num/2;
+
+  if (Step+1 < Log) {
+    if (UseUp && !route(P, T, Size/2, Step+1))
+      return false;
+    if (UseDown && !route(P+Size/2, T+Size/2, Size/2, Step+1))
+      return false;
+  }
+  return true;
+}
+
+bool BenesNetwork::route(ElemType *P, RowType *T, unsigned Size,
+                         unsigned Step) {
+  Coloring G({P,Size});
+  const Coloring::MapType &M = G.colors();
+  if (M.empty())
+    return false;
+  ElemType Num = Size;
+
+  unsigned Pets = 2*Log-1 - Step;
+  bool UseUp = false, UseDown = false;
+
+  // Both assignments, i.e. Red->Up and Red->Down are valid, but they will
+  // result in different controls. Let's pick the one where the first
+  // control will be "Pass".
+  uint8_t ColorUp = Coloring::None;
+  for (ElemType J = 0; J != Num; ++J) {
+    ElemType I = P[J];
+    if (I == Ignore)
+      continue;
+    uint8_t C = M.at(I);
+    if (C == Coloring::None)
+      continue;
+    if (ColorUp == Coloring::None) {
+      ColorUp = (I < Num/2) ? Coloring::Red : Coloring::Black;
+    }
+    unsigned CI = (I < Num/2) ? I+Num/2 : I-Num/2;
+    if (C == ColorUp) {
+      if (I < Num/2)
+        T[I][Step] = Pass;
+      else
+        T[CI][Step] = Switch;
+      T[J][Pets] = (J < Num/2) ? Pass : Switch;
+      UseUp = true;
+    } else { // Down
+      if (I < Num/2)
+        T[CI][Step] = Switch;
+      else
+        T[I][Step] = Pass;
+      T[J][Pets] = (J < Num/2) ? Switch : Pass;
+      UseDown = true;
+    }
+  }
+
+  // Reorder the working permutation according to the computed switch table
+  // for the last step (i.e. Pets).
+  for (ElemType J = 0; J != Num/2; ++J) {
+    ElemType PJ = P[J];         // Current values of P[J]
+    ElemType PC = P[J+Num/2];   // and P[conj(J)]
+    ElemType QJ = PJ;           // New values of P[J]
+    ElemType QC = PC;           // and P[conj(J)]
+    if (T[J][Pets] == Switch)
+      QC = PJ;
+    if (T[J+Num/2][Pets] == Switch)
+      QJ = PC;
+    P[J] = QJ;
+    P[J+Num/2] = QC;
+  }
+
+  for (ElemType J = 0; J != Num; ++J)
+    if (P[J] != Ignore && P[J] >= Num/2)
+      P[J] -= Num/2;
+
+  if (Step+1 < Log) {
+    if (UseUp && !route(P, T, Size/2, Step+1))
+      return false;
+    if (UseDown && !route(P+Size/2, T+Size/2, Size/2, Step+1))
+      return false;
+  }
+  return true;
+}
+
+// --------------------------------------------------------------------
+// Support for building selection results (output instructions that are
+// parts of the final selection).
+
+struct OpRef {
+  OpRef(SDValue V) : OpV(V) {}
+  bool isValue() const { return OpV.getNode() != nullptr; }
+  bool isValid() const { return isValue() || !(OpN & Invalid); }
+  static OpRef res(int N) { return OpRef(Whole | (N & Index)); }
+  static OpRef fail() { return OpRef(Invalid); }
+
+  static OpRef lo(const OpRef &R) {
+    assert(!R.isValue());
+    return OpRef(R.OpN & (Undef | Index | LoHalf));
+  }
+  static OpRef hi(const OpRef &R) {
+    assert(!R.isValue());
+    return OpRef(R.OpN & (Undef | Index | HiHalf));
+  }
+  static OpRef undef(MVT Ty) { return OpRef(Undef | Ty.SimpleTy); }
+
+  // Direct value.
+  SDValue OpV = SDValue();
+
+  // Reference to the operand of the input node:
+  // If the 31st bit is 1, it's undef, otherwise, bits 28..0 are the
+  // operand index:
+  // If bit 30 is set, it's the high half of the operand.
+  // If bit 29 is set, it's the low half of the operand.
+  unsigned OpN = 0;
+
+  enum : unsigned {
+    Invalid = 0x10000000,
+    LoHalf  = 0x20000000,
+    HiHalf  = 0x40000000,
+    Whole   = LoHalf | HiHalf,
+    Undef   = 0x80000000,
+    Index   = 0x0FFFFFFF,  // Mask of the index value.
+    IndexBits = 28,
+  };
+
+  void print(raw_ostream &OS, const SelectionDAG &G) const;
+
+private:
+  OpRef(unsigned N) : OpN(N) {}
+};
+
+struct NodeTemplate {
+  NodeTemplate() = default;
+  unsigned Opc = 0;
+  MVT Ty = MVT::Other;
+  std::vector<OpRef> Ops;
+
+  void print(raw_ostream &OS, const SelectionDAG &G) const;
+};
+
+struct ResultStack {
+  ResultStack(SDNode *Inp)
+    : InpNode(Inp), InpTy(Inp->getValueType(0).getSimpleVT()) {}
+  SDNode *InpNode;
+  MVT InpTy;
+  unsigned push(const NodeTemplate &Res) {
+    List.push_back(Res);
+    return List.size()-1;
+  }
+  unsigned push(unsigned Opc, MVT Ty, std::vector<OpRef> &&Ops) {
+    NodeTemplate Res;
+    Res.Opc = Opc;
+    Res.Ty = Ty;
+    Res.Ops = Ops;
+    return push(Res);
+  }
+  bool empty() const { return List.empty(); }
+  unsigned size() const { return List.size(); }
+  unsigned top() const { return size()-1; }
+  const NodeTemplate &operator[](unsigned I) const { return List[I]; }
+  unsigned reset(unsigned NewTop) {
+    List.resize(NewTop+1);
+    return NewTop;
+  }
+
+  using BaseType = std::vector<NodeTemplate>;
+  BaseType::iterator begin() { return List.begin(); }
+  BaseType::iterator end()   { return List.end(); }
+  BaseType::const_iterator begin() const { return List.begin(); }
+  BaseType::const_iterator end() const   { return List.end(); }
+
+  BaseType List;
+
+  void print(raw_ostream &OS, const SelectionDAG &G) const;
+};
+
+void OpRef::print(raw_ostream &OS, const SelectionDAG &G) const {
+  if (isValue()) {
+    OpV.getNode()->print(OS, &G);
+    return;
+  }
+  if (OpN & Invalid) {
+    OS << "invalid";
+    return;
+  }
+  if (OpN & Undef) {
+    OS << "undef";
+    return;
+  }
+  if ((OpN & Whole) != Whole) {
+    assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf);
+    if (OpN & LoHalf)
+      OS << "lo ";
+    else
+      OS << "hi ";
+  }
+  OS << '#' << SignExtend32(OpN & Index, IndexBits);
+}
+
+void NodeTemplate::print(raw_ostream &OS, const SelectionDAG &G) const {
+  const TargetInstrInfo &TII = *G.getSubtarget().getInstrInfo();
+  OS << format("%8s", EVT(Ty).getEVTString().c_str()) << "  "
+     << TII.getName(Opc);
+  bool Comma = false;
+  for (const auto &R : Ops) {
+    if (Comma)
+      OS << ',';
+    Comma = true;
+    OS << ' ';
+    R.print(OS, G);
+  }
+}
+
+void ResultStack::print(raw_ostream &OS, const SelectionDAG &G) const {
+  OS << "Input node:\n";
+#ifndef NDEBUG
+  InpNode->dumpr(&G);
+#endif
+  OS << "Result templates:\n";
+  for (unsigned I = 0, E = List.size(); I != E; ++I) {
+    OS << '[' << I << "] ";
+    List[I].print(OS, G);
+    OS << '\n';
+  }
+}
+
+struct ShuffleMask {
+  ShuffleMask(ArrayRef<int> M) : Mask(M) {
+    for (unsigned I = 0, E = Mask.size(); I != E; ++I) {
+      int M = Mask[I];
+      if (M == -1)
+        continue;
+      MinSrc = (MinSrc == -1) ? M : std::min(MinSrc, M);
+      MaxSrc = (MaxSrc == -1) ? M : std::max(MaxSrc, M);
+    }
+  }
+
+  ArrayRef<int> Mask;
+  int MinSrc = -1, MaxSrc = -1;
+
+  ShuffleMask lo() const {
+    size_t H = Mask.size()/2;
+    return ShuffleMask({Mask.data(), H});
+  }
+  ShuffleMask hi() const {
+    size_t H = Mask.size()/2;
+    return ShuffleMask({Mask.data()+H, H});
+  }
+};
+
+// --------------------------------------------------------------------
+// The HvxSelector class.
+
+static const HexagonTargetLowering &getHexagonLowering(SelectionDAG &G) {
+  return static_cast<const HexagonTargetLowering&>(G.getTargetLoweringInfo());
+}
+static const HexagonSubtarget &getHexagonSubtarget(SelectionDAG &G) {
+  return static_cast<const HexagonSubtarget&>(G.getSubtarget());
+}
+
+namespace llvm {
+  struct HvxSelector {
+    const HexagonTargetLowering &Lower;
+    HexagonDAGToDAGISel &ISel;
+    SelectionDAG &DAG;
+    const HexagonSubtarget &HST;
+    const unsigned HwLen;
+
+    HvxSelector(HexagonDAGToDAGISel &HS, SelectionDAG &G)
+      : Lower(getHexagonLowering(G)),  ISel(HS), DAG(G),
+        HST(getHexagonSubtarget(G)), HwLen(HST.getVectorLength()) {}
+
+    MVT getSingleVT(MVT ElemTy) const {
+      unsigned NumElems = HwLen / (ElemTy.getSizeInBits()/8);
+      return MVT::getVectorVT(ElemTy, NumElems);
+    }
+
+    MVT getPairVT(MVT ElemTy) const {
+      unsigned NumElems = (2*HwLen) / (ElemTy.getSizeInBits()/8);
+      return MVT::getVectorVT(ElemTy, NumElems);
+    }
+
+    void selectShuffle(SDNode *N);
+    void selectRor(SDNode *N);
+
+  private:
+    void materialize(const ResultStack &Results);
+
+    SDValue getVectorConstant(ArrayRef<uint8_t> Data, const SDLoc &dl);
+
+    enum : unsigned {
+      None,
+      PackMux,
+    };
+    OpRef concat(OpRef Va, OpRef Vb, ResultStack &Results);
+    OpRef packs(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results,
+                MutableArrayRef<int> NewMask, unsigned Options = None);
+    OpRef packp(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results,
+                MutableArrayRef<int> NewMask);
+    OpRef zerous(ShuffleMask SM, OpRef Va, ResultStack &Results);
+    OpRef vmuxs(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
+                ResultStack &Results);
+    OpRef vmuxp(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
+                ResultStack &Results);
+
+    OpRef shuffs1(ShuffleMask SM, OpRef Va, ResultStack &Results);
+    OpRef shuffs2(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results);
+    OpRef shuffp1(ShuffleMask SM, OpRef Va, ResultStack &Results);
+    OpRef shuffp2(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results);
+
+    OpRef butterfly(ShuffleMask SM, OpRef Va, ResultStack &Results);
+    OpRef contracting(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results);
+    OpRef expanding(ShuffleMask SM, OpRef Va, ResultStack &Results);
+    OpRef perfect(ShuffleMask SM, OpRef Va, ResultStack &Results);
+
+    bool selectVectorConstants(SDNode *N);
+    bool scalarizeShuffle(ArrayRef<int> Mask, const SDLoc &dl, MVT ResTy,
+                          SDValue Va, SDValue Vb, SDNode *N);
+
+  };
+}
+
+// Return a submask of A that is shorter than A by |C| elements:
+// - if C > 0, return a submask of A that starts at position C,
+// - if C <= 0, return a submask of A that starts at 0 (reduce A by |C|).
+static ArrayRef<int> subm(ArrayRef<int> A, int C) {
+  if (C > 0)
+    return { A.data()+C, A.size()-C };
+  return { A.data(), A.size()+C };
+}
+
+static void splitMask(ArrayRef<int> Mask, MutableArrayRef<int> MaskL,
+                      MutableArrayRef<int> MaskR) {
+  unsigned VecLen = Mask.size();
+  assert(MaskL.size() == VecLen && MaskR.size() == VecLen);
+  for (unsigned I = 0; I != VecLen; ++I) {
+    int M = Mask[I];
+    if (M < 0) {
+      MaskL[I] = MaskR[I] = -1;
+    } else if (unsigned(M) < VecLen) {
+      MaskL[I] = M;
+      MaskR[I] = -1;
+    } else {
+      MaskL[I] = -1;
+      MaskR[I] = M-VecLen;
+    }
+  }
+}
+
+static std::pair<int,unsigned> findStrip(ArrayRef<int> A, int Inc,
+                                         unsigned MaxLen) {
+  assert(A.size() > 0 && A.size() >= MaxLen);
+  int F = A[0];
+  int E = F;
+  for (unsigned I = 1; I != MaxLen; ++I) {
+    if (A[I] - E != Inc)
+      return { F, I };
+    E = A[I];
+  }
+  return { F, MaxLen };
+}
+
+static bool isUndef(ArrayRef<int> Mask) {
+  for (int Idx : Mask)
+    if (Idx != -1)
+      return false;
+  return true;
+}
+
+static bool isIdentity(ArrayRef<int> Mask) {
+  for (int I = 0, E = Mask.size(); I != E; ++I) {
+    int M = Mask[I];
+    if (M >= 0 && M != I)
+      return false;
+  }
+  return true;
+}
+
+static bool isPermutation(ArrayRef<int> Mask) {
+  // Check by adding all numbers only works if there is no overflow.
+  assert(Mask.size() < 0x00007FFF && "Sanity failure");
+  int Sum = 0;
+  for (int Idx : Mask) {
+    if (Idx == -1)
+      return false;
+    Sum += Idx;
+  }
+  int N = Mask.size();
+  return 2*Sum == N*(N-1);
+}
+
+bool HvxSelector::selectVectorConstants(SDNode *N) {
+  // Constant vectors are generated as loads from constant pools.
+  // Since they are generated during the selection process, the main
+  // selection algorithm is not aware of them. Select them directly
+  // here.
+  if (!N->isMachineOpcode() && N->getOpcode() == ISD::LOAD) {
+    SDValue Addr = cast<LoadSDNode>(N)->getBasePtr();
+    unsigned AddrOpc = Addr.getOpcode();
+    if (AddrOpc == HexagonISD::AT_PCREL || AddrOpc == HexagonISD::CP) {
+      if (Addr.getOperand(0).getOpcode() == ISD::TargetConstantPool) {
+        ISel.Select(N);
+        return true;
+      }
+    }
+  }
+
+  bool Selected = false;
+  for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I)
+    Selected = selectVectorConstants(N->getOperand(I).getNode()) || Selected;
+  return Selected;
+}
+
+void HvxSelector::materialize(const ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {
+    dbgs() << "Materializing\n";
+    Results.print(dbgs(), DAG);
+  });
+  if (Results.empty())
+    return;
+  const SDLoc &dl(Results.InpNode);
+  std::vector<SDValue> Output;
+
+  for (unsigned I = 0, E = Results.size(); I != E; ++I) {
+    const NodeTemplate &Node = Results[I];
+    std::vector<SDValue> Ops;
+    for (const OpRef &R : Node.Ops) {
+      assert(R.isValid());
+      if (R.isValue()) {
+        Ops.push_back(R.OpV);
+        continue;
+      }
+      if (R.OpN & OpRef::Undef) {
+        MVT::SimpleValueType SVT = MVT::SimpleValueType(R.OpN & OpRef::Index);
+        Ops.push_back(ISel.selectUndef(dl, MVT(SVT)));
+        continue;
+      }
+      // R is an index of a result.
+      unsigned Part = R.OpN & OpRef::Whole;
+      int Idx = SignExtend32(R.OpN & OpRef::Index, OpRef::IndexBits);
+      if (Idx < 0)
+        Idx += I;
+      assert(Idx >= 0 && unsigned(Idx) < Output.size());
+      SDValue Op = Output[Idx];
+      MVT OpTy = Op.getValueType().getSimpleVT();
+      if (Part != OpRef::Whole) {
+        assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf);
+        if (Op.getOpcode() == HexagonISD::VCOMBINE) {
+          Op = (Part == OpRef::HiHalf) ? Op.getOperand(0) : Op.getOperand(1);
+        } else {
+          MVT HalfTy = MVT::getVectorVT(OpTy.getVectorElementType(),
+                                        OpTy.getVectorNumElements()/2);
+          unsigned Sub = (Part == OpRef::LoHalf) ? Hexagon::vsub_lo
+                                                 : Hexagon::vsub_hi;
+          Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op);
+        }
+      }
+      Ops.push_back(Op);
+    } // for (Node : Results)
+
+    assert(Node.Ty != MVT::Other);
+    SDNode *ResN = (Node.Opc == TargetOpcode::COPY)
+                      ? Ops.front().getNode()
+                      : DAG.getMachineNode(Node.Opc, dl, Node.Ty, Ops);
+    Output.push_back(SDValue(ResN, 0));
+  }
+
+  SDNode *OutN = Output.back().getNode();
+  SDNode *InpN = Results.InpNode;
+  DEBUG_WITH_TYPE("isel", {
+    dbgs() << "Generated node:\n";
+    OutN->dumpr(&DAG);
+  });
+
+  ISel.ReplaceNode(InpN, OutN);
+  selectVectorConstants(OutN);
+  DAG.RemoveDeadNodes();
+}
+
+OpRef HvxSelector::concat(OpRef Lo, OpRef Hi, ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  const SDLoc &dl(Results.InpNode);
+  Results.push(TargetOpcode::REG_SEQUENCE, getPairVT(MVT::i8), {
+    DAG.getTargetConstant(Hexagon::HvxWRRegClassID, dl, MVT::i32),
+    Lo, DAG.getTargetConstant(Hexagon::vsub_lo, dl, MVT::i32),
+    Hi, DAG.getTargetConstant(Hexagon::vsub_hi, dl, MVT::i32),
+  });
+  return OpRef::res(Results.top());
+}
+
+// Va, Vb are single vectors, SM can be arbitrarily long.
+OpRef HvxSelector::packs(ShuffleMask SM, OpRef Va, OpRef Vb,
+                         ResultStack &Results, MutableArrayRef<int> NewMask,
+                         unsigned Options) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  if (!Va.isValid() || !Vb.isValid())
+    return OpRef::fail();
+
+  int VecLen = SM.Mask.size();
+  MVT Ty = getSingleVT(MVT::i8);
+
+  if (SM.MaxSrc - SM.MinSrc < int(HwLen)) {
+    if (SM.MaxSrc < int(HwLen)) {
+      memcpy(NewMask.data(), SM.Mask.data(), sizeof(int)*VecLen);
+      return Va;
+    }
+    if (SM.MinSrc >= int(HwLen)) {
+      for (int I = 0; I != VecLen; ++I) {
+        int M = SM.Mask[I];
+        if (M != -1)
+          M -= HwLen;
+        NewMask[I] = M;
+      }
+      return Vb;
+    }
+    const SDLoc &dl(Results.InpNode);
+    SDValue S = DAG.getTargetConstant(SM.MinSrc, dl, MVT::i32);
+    if (isUInt<3>(SM.MinSrc)) {
+      Results.push(Hexagon::V6_valignbi, Ty, {Vb, Va, S});
+    } else {
+      Results.push(Hexagon::A2_tfrsi, MVT::i32, {S});
+      unsigned Top = Results.top();
+      Results.push(Hexagon::V6_valignb, Ty, {Vb, Va, OpRef::res(Top)});
+    }
+    for (int I = 0; I != VecLen; ++I) {
+      int M = SM.Mask[I];
+      if (M != -1)
+        M -= SM.MinSrc;
+      NewMask[I] = M;
+    }
+    return OpRef::res(Results.top());
+  }
+
+  if (Options & PackMux) {
+    // If elements picked from Va and Vb have all different (source) indexes
+    // (relative to the start of the argument), do a mux, and update the mask.
+    BitVector Picked(HwLen);
+    SmallVector<uint8_t,128> MuxBytes(HwLen);
+    bool CanMux = true;
+    for (int I = 0; I != VecLen; ++I) {
+      int M = SM.Mask[I];
+      if (M == -1)
+        continue;
+      if (M >= int(HwLen))
+        M -= HwLen;
+      else
+        MuxBytes[M] = 0xFF;
+      if (Picked[M]) {
+        CanMux = false;
+        break;
+      }
+      NewMask[I] = M;
+    }
+    if (CanMux)
+      return vmuxs(MuxBytes, Va, Vb, Results);
+  }
+
+  return OpRef::fail();
+}
+
+OpRef HvxSelector::packp(ShuffleMask SM, OpRef Va, OpRef Vb,
+                         ResultStack &Results, MutableArrayRef<int> NewMask) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  unsigned HalfMask = 0;
+  unsigned LogHw = Log2_32(HwLen);
+  for (int M : SM.Mask) {
+    if (M == -1)
+      continue;
+    HalfMask |= (1u << (M >> LogHw));
+  }
+
+  if (HalfMask == 0)
+    return OpRef::undef(getPairVT(MVT::i8));
+
+  // If more than two halves are used, bail.
+  // TODO: be more aggressive here?
+  if (countPopulation(HalfMask) > 2)
+    return OpRef::fail();
+
+  MVT HalfTy = getSingleVT(MVT::i8);
+
+  OpRef Inp[2] = { Va, Vb };
+  OpRef Out[2] = { OpRef::undef(HalfTy), OpRef::undef(HalfTy) };
+
+  uint8_t HalfIdx[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
+  unsigned Idx = 0;
+  for (unsigned I = 0; I != 4; ++I) {
+    if ((HalfMask & (1u << I)) == 0)
+      continue;
+    assert(Idx < 2);
+    OpRef Op = Inp[I/2];
+    Out[Idx] = (I & 1) ? OpRef::hi(Op) : OpRef::lo(Op);
+    HalfIdx[I] = Idx++;
+  }
+
+  int VecLen = SM.Mask.size();
+  for (int I = 0; I != VecLen; ++I) {
+    int M = SM.Mask[I];
+    if (M >= 0) {
+      uint8_t Idx = HalfIdx[M >> LogHw];
+      assert(Idx == 0 || Idx == 1);
+      M = (M & (HwLen-1)) + HwLen*Idx;
+    }
+    NewMask[I] = M;
+  }
+
+  return concat(Out[0], Out[1], Results);
+}
+
+OpRef HvxSelector::zerous(ShuffleMask SM, OpRef Va, ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+
+  int VecLen = SM.Mask.size();
+  SmallVector<uint8_t,128> UsedBytes(VecLen);
+  bool HasUnused = false;
+  for (int I = 0; I != VecLen; ++I) {
+    if (SM.Mask[I] != -1)
+      UsedBytes[I] = 0xFF;
+    else
+      HasUnused = true;
+  }
+  if (!HasUnused)
+    return Va;
+  SDValue B = getVectorConstant(UsedBytes, SDLoc(Results.InpNode));
+  Results.push(Hexagon::V6_vand, getSingleVT(MVT::i8), {Va, OpRef(B)});
+  return OpRef::res(Results.top());
+}
+
+OpRef HvxSelector::vmuxs(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
+                         ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  MVT ByteTy = getSingleVT(MVT::i8);
+  MVT BoolTy = MVT::getVectorVT(MVT::i1, 8*HwLen); // XXX
+  const SDLoc &dl(Results.InpNode);
+  SDValue B = getVectorConstant(Bytes, dl);
+  Results.push(Hexagon::V6_vd0, ByteTy, {});
+  Results.push(Hexagon::V6_veqb, BoolTy, {OpRef(B), OpRef::res(-1)});
+  Results.push(Hexagon::V6_vmux, ByteTy, {OpRef::res(-1), Vb, Va});
+  return OpRef::res(Results.top());
+}
+
+OpRef HvxSelector::vmuxp(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
+                         ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  size_t S = Bytes.size() / 2;
+  OpRef L = vmuxs({Bytes.data(),   S}, OpRef::lo(Va), OpRef::lo(Vb), Results);
+  OpRef H = vmuxs({Bytes.data()+S, S}, OpRef::hi(Va), OpRef::hi(Vb), Results);
+  return concat(L, H, Results);
+}
+
+OpRef HvxSelector::shuffs1(ShuffleMask SM, OpRef Va, ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  unsigned VecLen = SM.Mask.size();
+  assert(HwLen == VecLen);
+  (void)VecLen;
+  assert(all_of(SM.Mask, [this](int M) { return M == -1 || M < int(HwLen); }));
+
+  if (isIdentity(SM.Mask))
+    return Va;
+  if (isUndef(SM.Mask))
+    return OpRef::undef(getSingleVT(MVT::i8));
+
+  OpRef P = perfect(SM, Va, Results);
+  if (P.isValid())
+    return P;
+  return butterfly(SM, Va, Results);
+}
+
+OpRef HvxSelector::shuffs2(ShuffleMask SM, OpRef Va, OpRef Vb,
+                           ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  if (isUndef(SM.Mask))
+    return OpRef::undef(getSingleVT(MVT::i8));
+
+  OpRef C = contracting(SM, Va, Vb, Results);
+  if (C.isValid())
+    return C;
+
+  int VecLen = SM.Mask.size();
+  SmallVector<int,128> NewMask(VecLen);
+  OpRef P = packs(SM, Va, Vb, Results, NewMask);
+  if (P.isValid())
+    return shuffs1(ShuffleMask(NewMask), P, Results);
+
+  SmallVector<int,128> MaskL(VecLen), MaskR(VecLen);
+  splitMask(SM.Mask, MaskL, MaskR);
+
+  OpRef L = shuffs1(ShuffleMask(MaskL), Va, Results);
+  OpRef R = shuffs1(ShuffleMask(MaskR), Vb, Results);
+  if (!L.isValid() || !R.isValid())
+    return OpRef::fail();
+
+  SmallVector<uint8_t,128> Bytes(VecLen);
+  for (int I = 0; I != VecLen; ++I) {
+    if (MaskL[I] != -1)
+      Bytes[I] = 0xFF;
+  }
+  return vmuxs(Bytes, L, R, Results);
+}
+
+OpRef HvxSelector::shuffp1(ShuffleMask SM, OpRef Va, ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  int VecLen = SM.Mask.size();
+
+  if (isIdentity(SM.Mask))
+    return Va;
+  if (isUndef(SM.Mask))
+    return OpRef::undef(getPairVT(MVT::i8));
+
+  SmallVector<int,128> PackedMask(VecLen);
+  OpRef P = packs(SM, OpRef::lo(Va), OpRef::hi(Va), Results, PackedMask);
+  if (P.isValid()) {
+    ShuffleMask PM(PackedMask);
+    OpRef E = expanding(PM, P, Results);
+    if (E.isValid())
+      return E;
+
+    OpRef L = shuffs1(PM.lo(), P, Results);
+    OpRef H = shuffs1(PM.hi(), P, Results);
+    if (L.isValid() && H.isValid())
+      return concat(L, H, Results);
+  }
+
+  OpRef R = perfect(SM, Va, Results);
+  if (R.isValid())
+    return R;
+  // TODO commute the mask and try the opposite order of the halves.
+
+  OpRef L = shuffs2(SM.lo(), OpRef::lo(Va), OpRef::hi(Va), Results);
+  OpRef H = shuffs2(SM.hi(), OpRef::lo(Va), OpRef::hi(Va), Results);
+  if (L.isValid() && H.isValid())
+    return concat(L, H, Results);
+
+  return OpRef::fail();
+}
+
+OpRef HvxSelector::shuffp2(ShuffleMask SM, OpRef Va, OpRef Vb,
+                           ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  if (isUndef(SM.Mask))
+    return OpRef::undef(getPairVT(MVT::i8));
+
+  int VecLen = SM.Mask.size();
+  SmallVector<int,256> PackedMask(VecLen);
+  OpRef P = packp(SM, Va, Vb, Results, PackedMask);
+  if (P.isValid())
+    return shuffp1(ShuffleMask(PackedMask), P, Results);
+
+  SmallVector<int,256> MaskL(VecLen), MaskR(VecLen);
+  OpRef L = shuffp1(ShuffleMask(MaskL), Va, Results);
+  OpRef R = shuffp1(ShuffleMask(MaskR), Vb, Results);
+  if (!L.isValid() || !R.isValid())
+    return OpRef::fail();
+
+  // Mux the results.
+  SmallVector<uint8_t,256> Bytes(VecLen);
+  for (int I = 0; I != VecLen; ++I) {
+    if (MaskL[I] != -1)
+      Bytes[I] = 0xFF;
+  }
+  return vmuxp(Bytes, L, R, Results);
+}
+
+bool HvxSelector::scalarizeShuffle(ArrayRef<int> Mask, const SDLoc &dl,
+                                   MVT ResTy, SDValue Va, SDValue Vb,
+                                   SDNode *N) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  MVT ElemTy = ResTy.getVectorElementType();
+  assert(ElemTy == MVT::i8);
+  unsigned VecLen = Mask.size();
+  bool HavePairs = (2*HwLen == VecLen);
+  MVT SingleTy = getSingleVT(MVT::i8);
+
+  SmallVector<SDValue,128> Ops;
+  for (int I : Mask) {
+    if (I < 0) {
+      Ops.push_back(ISel.selectUndef(dl, ElemTy));
+      continue;
+    }
+    SDValue Vec;
+    unsigned M = I;
+    if (M < VecLen) {
+      Vec = Va;
+    } else {
+      Vec = Vb;
+      M -= VecLen;
+    }
+    if (HavePairs) {
+      if (M < HwLen) {
+        Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, Vec);
+      } else {
+        Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, Vec);
+        M -= HwLen;
+      }
+    }
+    SDValue Idx = DAG.getConstant(M, dl, MVT::i32);
+    SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemTy, {Vec, Idx});
+    SDValue L = Lower.LowerOperation(Ex, DAG);
+    assert(L.getNode());
+    Ops.push_back(L);
+  }
+
+  SDValue LV;
+  if (2*HwLen == VecLen) {
+    SDValue B0 = DAG.getBuildVector(SingleTy, dl, {Ops.data(), HwLen});
+    SDValue L0 = Lower.LowerOperation(B0, DAG);
+    SDValue B1 = DAG.getBuildVector(SingleTy, dl, {Ops.data()+HwLen, HwLen});
+    SDValue L1 = Lower.LowerOperation(B1, DAG);
+    // XXX CONCAT_VECTORS is legal for HVX vectors. Legalizing (lowering)
+    // functions may expect to be called only for illegal operations, so
+    // make sure that they are not called for legal ones. Develop a better
+    // mechanism for dealing with this.
+    LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1});
+  } else {
+    SDValue BV = DAG.getBuildVector(ResTy, dl, Ops);
+    LV = Lower.LowerOperation(BV, DAG);
+  }
+
+  assert(!N->use_empty());
+  ISel.ReplaceNode(N, LV.getNode());
+  DAG.RemoveDeadNodes();
+
+  std::deque<SDNode*> SubNodes;
+  SubNodes.push_back(LV.getNode());
+  for (unsigned I = 0; I != SubNodes.size(); ++I) {
+    for (SDValue Op : SubNodes[I]->ops())
+      SubNodes.push_back(Op.getNode());
+  }
+  while (!SubNodes.empty()) {
+    SDNode *S = SubNodes.front();
+    SubNodes.pop_front();
+    if (S->use_empty())
+      continue;
+    // This isn't great, but users need to be selected before any nodes that
+    // they use. (The reason is to match larger patterns, and avoid nodes that
+    // cannot be matched on their own, e.g. ValueType, TokenFactor, etc.).
+    bool PendingUser = llvm::any_of(S->uses(), [&SubNodes](const SDNode *U) {
+                         return llvm::any_of(SubNodes, [U](const SDNode *T) {
+                           return T == U;
+                         });
+                       });
+    if (PendingUser)
+      SubNodes.push_back(S);
+    else
+      ISel.Select(S);
+  }
+
+  DAG.RemoveDeadNodes();
+  return true;
+}
+
+OpRef HvxSelector::contracting(ShuffleMask SM, OpRef Va, OpRef Vb,
+                               ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  if (!Va.isValid() || !Vb.isValid())
+    return OpRef::fail();
+
+  // Contracting shuffles, i.e. instructions that always discard some bytes
+  // from the operand vectors.
+  //
+  // V6_vshuff{e,o}b
+  // V6_vdealb4w
+  // V6_vpack{e,o}{b,h}
+
+  int VecLen = SM.Mask.size();
+  std::pair<int,unsigned> Strip = findStrip(SM.Mask, 1, VecLen);
+  MVT ResTy = getSingleVT(MVT::i8);
+
+  // The following shuffles only work for bytes and halfwords. This requires
+  // the strip length to be 1 or 2.
+  if (Strip.second != 1 && Strip.second != 2)
+    return OpRef::fail();
+
+  // The patterns for the shuffles, in terms of the starting offsets of the
+  // consecutive strips (L = length of the strip, N = VecLen):
+  //
+  // vpacke:    0, 2L, 4L ... N+0, N+2L, N+4L ...      L = 1 or 2
+  // vpacko:    L, 3L, 5L ... N+L, N+3L, N+5L ...      L = 1 or 2
+  //
+  // vshuffe:   0, N+0, 2L, N+2L, 4L ...               L = 1 or 2
+  // vshuffo:   L, N+L, 3L, N+3L, 5L ...               L = 1 or 2
+  //
+  // vdealb4w:  0, 4, 8 ... 2, 6, 10 ... N+0, N+4, N+8 ... N+2, N+6, N+10 ...
+
+  // The value of the element in the mask following the strip will decide
+  // what kind of a shuffle this can be.
+  int NextInMask = SM.Mask[Strip.second];
+
+  // Check if NextInMask could be 2L, 3L or 4, i.e. if it could be a mask
+  // for vpack or vdealb4w. VecLen > 4, so NextInMask for vdealb4w would
+  // satisfy this.
+  if (NextInMask < VecLen) {
+    // vpack{e,o} or vdealb4w
+    if (Strip.first == 0 && Strip.second == 1 && NextInMask == 4) {
+      int N = VecLen;
+      // Check if this is vdealb4w (L=1).
+      for (int I = 0; I != N/4; ++I)
+        if (SM.Mask[I] != 4*I)
+          return OpRef::fail();
+      for (int I = 0; I != N/4; ++I)
+        if (SM.Mask[I+N/4] != 2 + 4*I)
+          return OpRef::fail();
+      for (int I = 0; I != N/4; ++I)
+        if (SM.Mask[I+N/2] != N + 4*I)
+          return OpRef::fail();
+      for (int I = 0; I != N/4; ++I)
+        if (SM.Mask[I+3*N/4] != N+2 + 4*I)
+          return OpRef::fail();
+      // Matched mask for vdealb4w.
+      Results.push(Hexagon::V6_vdealb4w, ResTy, {Vb, Va});
+      return OpRef::res(Results.top());
+    }
+
+    // Check if this is vpack{e,o}.
+    int N = VecLen;
+    int L = Strip.second;
+    // Check if the first strip starts at 0 or at L.
+    if (Strip.first != 0 && Strip.first != L)
+      return OpRef::fail();
+    // Examine the rest of the mask.
+    for (int I = L; I < N; I += L) {
+      auto S = findStrip(subm(SM.Mask,I), 1, N-I);
+      // Check whether the mask element at the beginning of each strip
+      // increases by 2L each time.
+      if (S.first - Strip.first != 2*I)
+        return OpRef::fail();
+      // Check whether each strip is of the same length.
+      if (S.second != unsigned(L))
+        return OpRef::fail();
+    }
+
+    // Strip.first == 0  =>  vpacke
+    // Strip.first == L  =>  vpacko
+    assert(Strip.first == 0 || Strip.first == L);
+    using namespace Hexagon;
+    NodeTemplate Res;
+    Res.Opc = Strip.second == 1 // Number of bytes.
+                  ? (Strip.first == 0 ? V6_vpackeb : V6_vpackob)
+                  : (Strip.first == 0 ? V6_vpackeh : V6_vpackoh);
+    Res.Ty = ResTy;
+    Res.Ops = { Vb, Va };
+    Results.push(Res);
+    return OpRef::res(Results.top());
+  }
+
+  // Check if this is vshuff{e,o}.
+  int N = VecLen;
+  int L = Strip.second;
+  std::pair<int,unsigned> PrevS = Strip;
+  bool Flip = false;
+  for (int I = L; I < N; I += L) {
+    auto S = findStrip(subm(SM.Mask,I), 1, N-I);
+    if (S.second != PrevS.second)
+      return OpRef::fail();
+    int Diff = Flip ? PrevS.first - S.first + 2*L
+                    : S.first - PrevS.first;
+    if (Diff != N)
+      return OpRef::fail();
+    Flip ^= true;
+    PrevS = S;
+  }
+  // Strip.first == 0  =>  vshuffe
+  // Strip.first == L  =>  vshuffo
+  assert(Strip.first == 0 || Strip.first == L);
+  using namespace Hexagon;
+  NodeTemplate Res;
+  Res.Opc = Strip.second == 1 // Number of bytes.
+                ? (Strip.first == 0 ? V6_vshuffeb : V6_vshuffob)
+                : (Strip.first == 0 ?  V6_vshufeh :  V6_vshufoh);
+  Res.Ty = ResTy;
+  Res.Ops = { Vb, Va };
+  Results.push(Res);
+  return OpRef::res(Results.top());
+}
+
+OpRef HvxSelector::expanding(ShuffleMask SM, OpRef Va, ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  // Expanding shuffles (using all elements and inserting into larger vector):
+  //
+  // V6_vunpacku{b,h} [*]
+  //
+  // [*] Only if the upper elements (filled with 0s) are "don't care" in Mask.
+  //
+  // Note: V6_vunpacko{b,h} are or-ing the high byte/half in the result, so
+  // they are not shuffles.
+  //
+  // The argument is a single vector.
+
+  int VecLen = SM.Mask.size();
+  assert(2*HwLen == unsigned(VecLen) && "Expecting vector-pair type");
+
+  std::pair<int,unsigned> Strip = findStrip(SM.Mask, 1, VecLen);
+
+  // The patterns for the unpacks, in terms of the starting offsets of the
+  // consecutive strips (L = length of the strip, N = VecLen):
+  //
+  // vunpacku:  0, -1, L, -1, 2L, -1 ...
+
+  if (Strip.first != 0)
+    return OpRef::fail();
+
+  // The vunpackus only handle byte and half-word.
+  if (Strip.second != 1 && Strip.second != 2)
+    return OpRef::fail();
+
+  int N = VecLen;
+  int L = Strip.second;
+
+  // First, check the non-ignored strips.
+  for (int I = 2*L; I < 2*N; I += 2*L) {
+    auto S = findStrip(subm(SM.Mask,I), 1, N-I);
+    if (S.second != unsigned(L))
+      return OpRef::fail();
+    if (2*S.first != I)
+      return OpRef::fail();
+  }
+  // Check the -1s.
+  for (int I = L; I < 2*N; I += 2*L) {
+    auto S = findStrip(subm(SM.Mask,I), 0, N-I);
+    if (S.first != -1 || S.second != unsigned(L))
+      return OpRef::fail();
+  }
+
+  unsigned Opc = Strip.second == 1 ? Hexagon::V6_vunpackub
+                                   : Hexagon::V6_vunpackuh;
+  Results.push(Opc, getPairVT(MVT::i8), {Va});
+  return OpRef::res(Results.top());
+}
+
+OpRef HvxSelector::perfect(ShuffleMask SM, OpRef Va, ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  // V6_vdeal{b,h}
+  // V6_vshuff{b,h}
+
+  // V6_vshufoe{b,h}  those are quivalent to vshuffvdd(..,{1,2})
+  // V6_vshuffvdd (V6_vshuff)
+  // V6_dealvdd (V6_vdeal)
+
+  int VecLen = SM.Mask.size();
+  assert(isPowerOf2_32(VecLen) && Log2_32(VecLen) <= 8);
+  unsigned LogLen = Log2_32(VecLen);
+  unsigned HwLog = Log2_32(HwLen);
+  // The result length must be the same as the length of a single vector,
+  // or a vector pair.
+  assert(LogLen == HwLog || LogLen == HwLog+1);
+  bool Extend = (LogLen == HwLog);
+
+  if (!isPermutation(SM.Mask))
+    return OpRef::fail();
+
+  SmallVector<unsigned,8> Perm(LogLen);
+
+  // Check if this could be a perfect shuffle, or a combination of perfect
+  // shuffles.
+  //
+  // Consider this permutation (using hex digits to make the ASCII diagrams
+  // easier to read):
+  //   { 0, 8, 1, 9, 2, A, 3, B, 4, C, 5, D, 6, E, 7, F }.
+  // This is a "deal" operation: divide the input into two halves, and
+  // create the output by picking elements by alternating between these two
+  // halves:
+  //   0 1 2 3 4 5 6 7    -->    0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F  [*]
+  //   8 9 A B C D E F
+  //
+  // Aside from a few special explicit cases (V6_vdealb, etc.), HVX provides
+  // a somwehat different mechanism that could be used to perform shuffle/
+  // deal operations: a 2x2 transpose.
+  // Consider the halves of inputs again, they can be interpreted as a 2x8
+  // matrix. A 2x8 matrix can be looked at four 2x2 matrices concatenated
+  // together. Now, when considering 2 elements at a time, it will be a 2x4
+  // matrix (with elements 01, 23, 45, etc.), or two 2x2 matrices:
+  //   01 23  45 67
+  //   89 AB  CD EF
+  // With groups of 4, this will become a single 2x2 matrix, and so on.
+  //
+  // The 2x2 transpose instruction works by transposing each of the 2x2
+  // matrices (or "sub-matrices"), given a specific group size. For example,
+  // if the group size is 1 (i.e. each element is its own group), there
+  // will be four transposes of the four 2x2 matrices that form the 2x8.
+  // For example, with the inputs as above, the result will be:
+  //   0 8  2 A  4 C  6 E
+  //   1 9  3 B  5 D  7 F
+  // Now, this result can be tranposed again, but with the group size of 2:
+  //   08 19  4C 5D
+  //   2A 3B  6E 7F
+  // If we then transpose that result, but with the group size of 4, we get:
+  //   0819 2A3B
+  //   4C5D 6E7F
+  // If we concatenate these two rows, it will be
+  //   0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F
+  // which is the same as the "deal" [*] above.
+  //
+  // In general, a "deal" of individual elements is a series of 2x2 transposes,
+  // with changing group size. HVX has two instructions:
+  //   Vdd = V6_vdealvdd Vu, Vv, Rt
+  //   Vdd = V6_shufvdd  Vu, Vv, Rt
+  // that perform exactly that. The register Rt controls which transposes are
+  // going to happen: a bit at position n (counting from 0) indicates that a
+  // transpose with a group size of 2^n will take place. If multiple bits are
+  // set, multiple transposes will happen: vdealvdd will perform them starting
+  // with the largest group size, vshuffvdd will do them in the reverse order.
+  //
+  // The main observation is that each 2x2 transpose corresponds to swapping
+  // columns of bits in the binary representation of the values.
+  //
+  // The numbers {3,2,1,0} and the log2 of the number of contiguous 1 bits
+  // in a given column. The * denote the columns that will be swapped.
+  // The transpose with the group size 2^n corresponds to swapping columns
+  // 3 (the highest log) and log2(n):
+  //
+  //     3 2 1 0         0 2 1 3         0 2 3 1
+  //     *     *             * *           * *
+  //  0  0 0 0 0      0  0 0 0 0      0  0 0 0 0      0  0 0 0 0
+  //  1  0 0 0 1      8  1 0 0 0      8  1 0 0 0      8  1 0 0 0
+  //  2  0 0 1 0      2  0 0 1 0      1  0 0 0 1      1  0 0 0 1
+  //  3  0 0 1 1      A  1 0 1 0      9  1 0 0 1      9  1 0 0 1
+  //  4  0 1 0 0      4  0 1 0 0      4  0 1 0 0      2  0 0 1 0
+  //  5  0 1 0 1      C  1 1 0 0      C  1 1 0 0      A  1 0 1 0
+  //  6  0 1 1 0      6  0 1 1 0      5  0 1 0 1      3  0 0 1 1
+  //  7  0 1 1 1      E  1 1 1 0      D  1 1 0 1      B  1 0 1 1
+  //  8  1 0 0 0      1  0 0 0 1      2  0 0 1 0      4  0 1 0 0
+  //  9  1 0 0 1      9  1 0 0 1      A  1 0 1 0      C  1 1 0 0
+  //  A  1 0 1 0      3  0 0 1 1      3  0 0 1 1      5  0 1 0 1
+  //  B  1 0 1 1      B  1 0 1 1      B  1 0 1 1      D  1 1 0 1
+  //  C  1 1 0 0      5  0 1 0 1      6  0 1 1 0      6  0 1 1 0
+  //  D  1 1 0 1      D  1 1 0 1      E  1 1 1 0      E  1 1 1 0
+  //  E  1 1 1 0      7  0 1 1 1      7  0 1 1 1      7  0 1 1 1
+  //  F  1 1 1 1      F  1 1 1 1      F  1 1 1 1      F  1 1 1 1
+
+  auto XorPow2 = [] (ArrayRef<int> Mask, unsigned Num) {
+    unsigned X = Mask[0] ^ Mask[Num/2];
+    // Check that the first half has the X's bits clear.
+    if ((Mask[0] & X) != 0)
+      return 0u;
+    for (unsigned I = 1; I != Num/2; ++I) {
+      if (unsigned(Mask[I] ^ Mask[I+Num/2]) != X)
+        return 0u;
+      if ((Mask[I] & X) != 0)
+        return 0u;
+    }
+    return X;
+  };
+
+  // Create a vector of log2's for each column: Perm[i] corresponds to
+  // the i-th bit (lsb is 0).
+  assert(VecLen > 2);
+  for (unsigned I = VecLen; I >= 2; I >>= 1) {
+    // Examine the initial segment of Mask of size I.
+    unsigned X = XorPow2(SM.Mask, I);
+    if (!isPowerOf2_32(X))
+      return OpRef::fail();
+    // Check the other segments of Mask.
+    for (int J = 0; J < VecLen; J += I) {
+      if (XorPow2(subm(SM.Mask, -J), I) != X)
+        return OpRef::fail();
+    }
+    Perm[Log2_32(X)] = Log2_32(I)-1;
+  }
+
+  // Once we have Perm, represent it as cycles. Denote the maximum log2
+  // (equal to log2(VecLen)-1) as M. The cycle containing M can then be
+  // written as (M a1 a2 a3 ... an). That cycle can be broken up into
+  // simple swaps as (M a1)(M a2)(M a3)...(M an), with the composition
+  // order being from left to right. Any (contiguous) segment where the
+  // values ai, ai+1...aj are either all increasing or all decreasing,
+  // can be implemented via a single vshuffvdd/vdealvdd respectively.
+  //
+  // If there is a cycle (a1 a2 ... an) that does not involve M, it can
+  // be written as (M an)(a1 a2 ... an)(M a1). The first two cycles can
+  // then be folded to get (M a1 a2 ... an)(M a1), and the above procedure
+  // can be used to generate a sequence of vshuffvdd/vdealvdd.
+  //
+  // Example:
+  // Assume M = 4 and consider a permutation (0 1)(2 3). It can be written
+  // as (4 0 1)(4 0) composed with (4 2 3)(4 2), or simply
+  //   (4 0 1)(4 0)(4 2 3)(4 2).
+  // It can then be expanded into swaps as
+  //   (4 0)(4 1)(4 0)(4 2)(4 3)(4 2),
+  // and broken up into "increasing" segments as
+  //   [(4 0)(4 1)] [(4 0)(4 2)(4 3)] [(4 2)].
+  // This is equivalent to
+  //   (4 0 1)(4 0 2 3)(4 2),
+  // which can be implemented as 3 vshufvdd instructions.
+
+  using CycleType = SmallVector<unsigned,8>;
+  std::set<CycleType> Cycles;
+  std::set<unsigned> All;
+
+  for (unsigned I : Perm)
+    All.insert(I);
+
+  // If the cycle contains LogLen-1, move it to the front of the cycle.
+  // Otherwise, return the cycle unchanged.
+  auto canonicalize = [LogLen](const CycleType &C) -> CycleType {
+    unsigned LogPos, N = C.size();
+    for (LogPos = 0; LogPos != N; ++LogPos)
+      if (C[LogPos] == LogLen-1)
+        break;
+    if (LogPos == N)
+      return C;
+
+    CycleType NewC(C.begin()+LogPos, C.end());
+    NewC.append(C.begin(), C.begin()+LogPos);
+    return NewC;
+  };
+
+  auto pfs = [](const std::set<CycleType> &Cs, unsigned Len) {
+    // Ordering: shuff: 5 0 1 2 3 4, deal: 5 4 3 2 1 0 (for Log=6),
+    // for bytes zero is included, for halfwords is not.
+    if (Cs.size() != 1)
+      return 0u;
+    const CycleType &C = *Cs.begin();
+    if (C[0] != Len-1)
+      return 0u;
+    int D = Len - C.size();
+    if (D != 0 && D != 1)
+      return 0u;
+
+    bool IsDeal = true, IsShuff = true;
+    for (unsigned I = 1; I != Len-D; ++I) {
+      if (C[I] != Len-1-I)
+        IsDeal = false;
+      if (C[I] != I-(1-D))  // I-1, I
+        IsShuff = false;
+    }
+    // At most one, IsDeal or IsShuff, can be non-zero.
+    assert(!(IsDeal || IsShuff) || IsDeal != IsShuff);
+    static unsigned Deals[] = { Hexagon::V6_vdealb, Hexagon::V6_vdealh };
+    static unsigned Shufs[] = { Hexagon::V6_vshuffb, Hexagon::V6_vshuffh };
+    return IsDeal ? Deals[D] : (IsShuff ? Shufs[D] : 0);
+  };
+
+  while (!All.empty()) {
+    unsigned A = *All.begin();
+    All.erase(A);
+    CycleType C;
+    C.push_back(A);
+    for (unsigned B = Perm[A]; B != A; B = Perm[B]) {
+      C.push_back(B);
+      All.erase(B);
+    }
+    if (C.size() <= 1)
+      continue;
+    Cycles.insert(canonicalize(C));
+  }
+
+  MVT SingleTy = getSingleVT(MVT::i8);
+  MVT PairTy = getPairVT(MVT::i8);
+
+  // Recognize patterns for V6_vdeal{b,h} and V6_vshuff{b,h}.
+  if (unsigned(VecLen) == HwLen) {
+    if (unsigned SingleOpc = pfs(Cycles, LogLen)) {
+      Results.push(SingleOpc, SingleTy, {Va});
+      return OpRef::res(Results.top());
+    }
+  }
+
+  SmallVector<unsigned,8> SwapElems;
+  if (HwLen == unsigned(VecLen))
+    SwapElems.push_back(LogLen-1);
+
+  for (const CycleType &C : Cycles) {
+    unsigned First = (C[0] == LogLen-1) ? 1 : 0;
+    SwapElems.append(C.begin()+First, C.end());
+    if (First == 0)
+      SwapElems.push_back(C[0]);
+  }
+
+  const SDLoc &dl(Results.InpNode);
+  OpRef Arg = !Extend ? Va
+                      : concat(Va, OpRef::undef(SingleTy), Results);
+
+  for (unsigned I = 0, E = SwapElems.size(); I != E; ) {
+    bool IsInc = I == E-1 || SwapElems[I] < SwapElems[I+1];
+    unsigned S = (1u << SwapElems[I]);
+    if (I < E-1) {
+      while (++I < E-1 && IsInc == (SwapElems[I] < SwapElems[I+1]))
+        S |= 1u << SwapElems[I];
+      // The above loop will not add a bit for the final SwapElems[I+1],
+      // so add it here.
+      S |= 1u << SwapElems[I];
+    }
+    ++I;
+
+    NodeTemplate Res;
+    Results.push(Hexagon::A2_tfrsi, MVT::i32,
+                 { DAG.getTargetConstant(S, dl, MVT::i32) });
+    Res.Opc = IsInc ? Hexagon::V6_vshuffvdd : Hexagon::V6_vdealvdd;
+    Res.Ty = PairTy;
+    Res.Ops = { OpRef::hi(Arg), OpRef::lo(Arg), OpRef::res(-1) };
+    Results.push(Res);
+    Arg = OpRef::res(Results.top());
+  }
+
+  return !Extend ? Arg : OpRef::lo(Arg);
+}
+
+OpRef HvxSelector::butterfly(ShuffleMask SM, OpRef Va, ResultStack &Results) {
+  DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
+  // Butterfly shuffles.
+  //
+  // V6_vdelta
+  // V6_vrdelta
+  // V6_vror
+
+  // The assumption here is that all elements picked by Mask are in the
+  // first operand to the vector_shuffle. This assumption is enforced
+  // by the caller.
+
+  MVT ResTy = getSingleVT(MVT::i8);
+  PermNetwork::Controls FC, RC;
+  const SDLoc &dl(Results.InpNode);
+  int VecLen = SM.Mask.size();
+
+  for (int M : SM.Mask) {
+    if (M != -1 && M >= VecLen)
+      return OpRef::fail();
+  }
+
+  // Try the deltas/benes for both single vectors and vector pairs.
+  ForwardDeltaNetwork FN(SM.Mask);
+  if (FN.run(FC)) {
+    SDValue Ctl = getVectorConstant(FC, dl);
+    Results.push(Hexagon::V6_vdelta, ResTy, {Va, OpRef(Ctl)});
+    return OpRef::res(Results.top());
+  }
+
+  // Try reverse delta.
+  ReverseDeltaNetwork RN(SM.Mask);
+  if (RN.run(RC)) {
+    SDValue Ctl = getVectorConstant(RC, dl);
+    Results.push(Hexagon::V6_vrdelta, ResTy, {Va, OpRef(Ctl)});
+    return OpRef::res(Results.top());
+  }
+
+  // Do Benes.
+  BenesNetwork BN(SM.Mask);
+  if (BN.run(FC, RC)) {
+    SDValue CtlF = getVectorConstant(FC, dl);
+    SDValue CtlR = getVectorConstant(RC, dl);
+    Results.push(Hexagon::V6_vdelta, ResTy, {Va, OpRef(CtlF)});
+    Results.push(Hexagon::V6_vrdelta, ResTy,
+                 {OpRef::res(-1), OpRef(CtlR)});
+    return OpRef::res(Results.top());
+  }
+
+  return OpRef::fail();
+}
+
+SDValue HvxSelector::getVectorConstant(ArrayRef<uint8_t> Data,
+                                       const SDLoc &dl) {
+  SmallVector<SDValue, 128> Elems;
+  for (uint8_t C : Data)
+    Elems.push_back(DAG.getConstant(C, dl, MVT::i8));
+  MVT VecTy = MVT::getVectorVT(MVT::i8, Data.size());
+  SDValue BV = DAG.getBuildVector(VecTy, dl, Elems);
+  SDValue LV = Lower.LowerOperation(BV, DAG);
+  DAG.RemoveDeadNode(BV.getNode());
+  return LV;
+}
+
+void HvxSelector::selectShuffle(SDNode *N) {
+  DEBUG_WITH_TYPE("isel", {
+    dbgs() << "Starting " << __func__ << " on node:\n";
+    N->dump(&DAG);
+  });
+  MVT ResTy = N->getValueType(0).getSimpleVT();
+  // Assume that vector shuffles operate on vectors of bytes.
+  assert(ResTy.isVector() && ResTy.getVectorElementType() == MVT::i8);
+
+  auto *SN = cast<ShuffleVectorSDNode>(N);
+  std::vector<int> Mask(SN->getMask().begin(), SN->getMask().end());
+  // This shouldn't really be necessary. Is it?
+  for (int &Idx : Mask)
+    if (Idx != -1 && Idx < 0)
+      Idx = -1;
+
+  unsigned VecLen = Mask.size();
+  bool HavePairs = (2*HwLen == VecLen);
+  assert(ResTy.getSizeInBits() / 8 == VecLen);
+
+  // Vd = vector_shuffle Va, Vb, Mask
+  //
+
+  bool UseLeft = false, UseRight = false;
+  for (unsigned I = 0; I != VecLen; ++I) {
+    if (Mask[I] == -1)
+      continue;
+    unsigned Idx = Mask[I];
+    assert(Idx < 2*VecLen);
+    if (Idx < VecLen)
+      UseLeft = true;
+    else
+      UseRight = true;
+  }
+
+  DEBUG_WITH_TYPE("isel", {
+    dbgs() << "VecLen=" << VecLen << " HwLen=" << HwLen << " UseLeft="
+           << UseLeft << " UseRight=" << UseRight << " HavePairs="
+           << HavePairs << '\n';
+  });
+  // If the mask is all -1's, generate "undef".
+  if (!UseLeft && !UseRight) {
+    ISel.ReplaceNode(N, ISel.selectUndef(SDLoc(SN), ResTy).getNode());
+    DAG.RemoveDeadNode(N);
+    return;
+  }
+
+  SDValue Vec0 = N->getOperand(0);
+  SDValue Vec1 = N->getOperand(1);
+  ResultStack Results(SN);
+  Results.push(TargetOpcode::COPY, ResTy, {Vec0});
+  Results.push(TargetOpcode::COPY, ResTy, {Vec1});
+  OpRef Va = OpRef::res(Results.top()-1);
+  OpRef Vb = OpRef::res(Results.top());
+
+  OpRef Res = !HavePairs ? shuffs2(ShuffleMask(Mask), Va, Vb, Results)
+                         : shuffp2(ShuffleMask(Mask), Va, Vb, Results);
+
+  bool Done = Res.isValid();
+  if (Done) {
+    // Make sure that Res is on the stack before materializing.
+    Results.push(TargetOpcode::COPY, ResTy, {Res});
+    materialize(Results);
+  } else {
+    Done = scalarizeShuffle(Mask, SDLoc(N), ResTy, Vec0, Vec1, N);
+  }
+
+  if (!Done) {
+#ifndef NDEBUG
+    dbgs() << "Unhandled shuffle:\n";
+    SN->dumpr(&DAG);
+#endif
+    llvm_unreachable("Failed to select vector shuffle");
+  }
+}
+
+void HvxSelector::selectRor(SDNode *N) {
+  // If this is a rotation by less than 8, use V6_valignbi.
+  MVT Ty = N->getValueType(0).getSimpleVT();
+  const SDLoc &dl(N);
+  SDValue VecV = N->getOperand(0);
+  SDValue RotV = N->getOperand(1);
+  SDNode *NewN = nullptr;
+
+  if (auto *CN = dyn_cast<ConstantSDNode>(RotV.getNode())) {
+    unsigned S = CN->getZExtValue();
+    if (S % HST.getVectorLength() == 0) {
+      NewN = VecV.getNode();
+    } else if (isUInt<3>(S)) {
+      SDValue C = DAG.getTargetConstant(S, dl, MVT::i32);
+      NewN = DAG.getMachineNode(Hexagon::V6_valignbi, dl, Ty,
+                                {VecV, VecV, C});
+    }
+  }
+
+  if (!NewN)
+    NewN = DAG.getMachineNode(Hexagon::V6_vror, dl, Ty, {VecV, RotV});
+
+  ISel.ReplaceNode(N, NewN);
+  DAG.RemoveDeadNode(N);
+}
+
+void HexagonDAGToDAGISel::SelectHvxShuffle(SDNode *N) {
+  HvxSelector(*this, *CurDAG).selectShuffle(N);
+}
+
+void HexagonDAGToDAGISel::SelectHvxRor(SDNode *N) {
+  HvxSelector(*this, *CurDAG).selectRor(N);
+}
+
+void HexagonDAGToDAGISel::SelectV65GatherPred(SDNode *N) {
+  const SDLoc &dl(N);
+  SDValue Chain = N->getOperand(0);
+  SDValue Address = N->getOperand(2);
+  SDValue Predicate = N->getOperand(3);
+  SDValue Base = N->getOperand(4);
+  SDValue Modifier = N->getOperand(5);
+  SDValue Offset = N->getOperand(6);
+
+  unsigned Opcode;
+  unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+  switch (IntNo) {
+  default:
+    llvm_unreachable("Unexpected HVX gather intrinsic.");
+  case Intrinsic::hexagon_V6_vgathermhq:
+  case Intrinsic::hexagon_V6_vgathermhq_128B:
+    Opcode = Hexagon::V6_vgathermhq_pseudo;
+    break;
+  case Intrinsic::hexagon_V6_vgathermwq:
+  case Intrinsic::hexagon_V6_vgathermwq_128B:
+    Opcode = Hexagon::V6_vgathermwq_pseudo;
+    break;
+  case Intrinsic::hexagon_V6_vgathermhwq:
+  case Intrinsic::hexagon_V6_vgathermhwq_128B:
+    Opcode = Hexagon::V6_vgathermhwq_pseudo;
+    break;
+  }
+
+  SDVTList VTs = CurDAG->getVTList(MVT::Other);
+  SDValue Ops[] = { Address, Predicate, Base, Modifier, Offset, Chain };
+  SDNode *Result = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
+
+  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
+  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
+  cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
+
+  ReplaceUses(N, Result);
+  CurDAG->RemoveDeadNode(N);
+}
+
+void HexagonDAGToDAGISel::SelectV65Gather(SDNode *N) {
+  const SDLoc &dl(N);
+  SDValue Chain = N->getOperand(0);
+  SDValue Address = N->getOperand(2);
+  SDValue Base = N->getOperand(3);
+  SDValue Modifier = N->getOperand(4);
+  SDValue Offset = N->getOperand(5);
+
+  unsigned Opcode;
+  unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+  switch (IntNo) {
+  default:
+    llvm_unreachable("Unexpected HVX gather intrinsic.");
+  case Intrinsic::hexagon_V6_vgathermh:
+  case Intrinsic::hexagon_V6_vgathermh_128B:
+    Opcode = Hexagon::V6_vgathermh_pseudo;
+    break;
+  case Intrinsic::hexagon_V6_vgathermw:
+  case Intrinsic::hexagon_V6_vgathermw_128B:
+    Opcode = Hexagon::V6_vgathermw_pseudo;
+    break;
+  case Intrinsic::hexagon_V6_vgathermhw:
+  case Intrinsic::hexagon_V6_vgathermhw_128B:
+    Opcode = Hexagon::V6_vgathermhw_pseudo;
+    break;
+  }
+
+  SDVTList VTs = CurDAG->getVTList(MVT::Other);
+  SDValue Ops[] = { Address, Base, Modifier, Offset, Chain };
+  SDNode *Result = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
+
+  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
+  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
+  cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
+
+  ReplaceUses(N, Result);
+  CurDAG->RemoveDeadNode(N);
+}
+
+void HexagonDAGToDAGISel::SelectHVXDualOutput(SDNode *N) {
+  unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+  SDNode *Result;
+  switch (IID) {
+  case Intrinsic::hexagon_V6_vaddcarry: {
+    SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),
+                                    N->getOperand(3) };
+    SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1);
+    Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops);
+    break;
+  }
+  case Intrinsic::hexagon_V6_vaddcarry_128B: {
+    SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),
+                                    N->getOperand(3) };
+    SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1);
+    Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops);
+    break;
+  }
+  case Intrinsic::hexagon_V6_vsubcarry: {
+    SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),
+                                    N->getOperand(3) };
+    SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1);
+    Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs, Ops);
+    break;
+  }
+  case Intrinsic::hexagon_V6_vsubcarry_128B: {
+    SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),
+                                    N->getOperand(3) };
+    SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1);
+    Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs, Ops);
+    break;
+  }
+  default:
+    llvm_unreachable("Unexpected HVX dual output intrinsic.");
+  }
+  ReplaceUses(N, Result);
+  ReplaceUses(SDValue(N, 0), SDValue(Result, 0));
+  ReplaceUses(SDValue(N, 1), SDValue(Result, 1));
+  CurDAG->RemoveDeadNode(N);
+}
+
+
diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp
index 3997702bc962..586363335df1 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -29,6 +29,7 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RuntimeLibcalls.h"
 #include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/CallingConv.h"
@@ -50,7 +51,6 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetCallingConv.h"
 #include "llvm/Target/TargetMachine.h"
 #include <algorithm>
 #include <cassert>
@@ -129,7 +129,10 @@ namespace {
 
 // Implement calling convention for Hexagon.
 
-static bool isHvxVectorType(MVT ty);
+static const MVT LegalV64[] =  { MVT::v64i8,  MVT::v32i16,  MVT::v16i32 };
+static const MVT LegalW64[] =  { MVT::v128i8, MVT::v64i16,  MVT::v32i32 };
+static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16,  MVT::v32i32 };
+static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
 
 static bool
 CC_Hexagon(unsigned ValNo, MVT ValVT,
@@ -224,19 +227,19 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
     return false;
   }
-  if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
+  if (LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
       LocVT == MVT::v64i8 || LocVT == MVT::v512i1) {
     Offset = State.AllocateStack(64, 64);
     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
     return false;
   }
-  if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
+  if (LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
       LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {
     Offset = State.AllocateStack(128, 128);
     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
     return false;
   }
-  if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
+  if (LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
       LocVT == MVT::v256i8) {
     Offset = State.AllocateStack(256, 256);
     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
@@ -291,7 +294,8 @@ static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT,
     return false;
   }
 
-  if (isHvxVectorType(LocVT)) {
+  auto &HST = State.getMachineFunction().getSubtarget<HexagonSubtarget>();
+  if (HST.isHVXVectorType(LocVT)) {
     if (!CC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
       return false;
   }
@@ -356,11 +360,9 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
   };
   auto &MF = State.getMachineFunction();
   auto &HST = MF.getSubtarget<HexagonSubtarget>();
-  bool UseHVX = HST.useHVXOps();
-  bool UseHVXDbl = HST.useHVXDblOps();
 
-  if ((UseHVX && !UseHVXDbl) &&
-      (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
+  if (HST.useHVX64BOps() &&
+      (LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
        LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
     if (unsigned Reg = State.AllocateReg(VecLstS)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
@@ -370,9 +372,8 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
     return false;
   }
-  if ((UseHVX && !UseHVXDbl) &&
-      (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
-       LocVT == MVT::v128i8)) {
+  if (HST.useHVX64BOps() && (LocVT == MVT::v32i32 ||
+                             LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) {
     if (unsigned Reg = State.AllocateReg(VecLstD)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
@@ -382,9 +383,8 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
     return false;
   }
   // 128B Mode
-  if ((UseHVX && UseHVXDbl) &&
-      (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
-       LocVT == MVT::v256i8)) {
+  if (HST.useHVX128BOps() && (LocVT == MVT::v64i32 ||
+                              LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) {
     if (unsigned Reg = State.AllocateReg(VecLstD)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
@@ -393,8 +393,8 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
     return false;
   }
-  if ((UseHVX && UseHVXDbl) &&
-      (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
+  if (HST.useHVX128BOps() &&
+      (LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
        LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
     if (unsigned Reg = State.AllocateReg(VecLstS)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
@@ -412,8 +412,6 @@ static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
   auto &MF = State.getMachineFunction();
   auto &HST = MF.getSubtarget<HexagonSubtarget>();
-  bool UseHVX = HST.useHVXOps();
-  bool UseHVXDbl = HST.useHVXDblOps();
 
   if (LocVT == MVT::i1) {
     // Return values of type MVT::i1 still need to be assigned to R0, but
@@ -436,19 +434,18 @@ static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
     LocVT = MVT::i64;
     LocInfo = CCValAssign::BCvt;
   } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 ||
-             LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
-             LocVT == MVT::v512i1) {
+             LocVT == MVT::v16i32 || LocVT == MVT::v512i1) {
     LocVT = MVT::v16i32;
     ValVT = MVT::v16i32;
     LocInfo = CCValAssign::Full;
   } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
-             LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
-             (LocVT == MVT::v1024i1 && UseHVX && UseHVXDbl)) {
+             LocVT == MVT::v32i32 ||
+             (LocVT == MVT::v1024i1 && HST.useHVX128BOps())) {
     LocVT = MVT::v32i32;
     ValVT = MVT::v32i32;
     LocInfo = CCValAssign::Full;
   } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 ||
-             LocVT == MVT::v64i32 || LocVT == MVT::v32i64) {
+             LocVT == MVT::v64i32) {
     LocVT = MVT::v64i32;
     ValVT = MVT::v64i32;
     LocInfo = CCValAssign::Full;
@@ -506,8 +503,6 @@ static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
   auto &MF = State.getMachineFunction();
   auto &HST = MF.getSubtarget<HexagonSubtarget>();
-  bool UseHVX = HST.useHVXOps();
-  bool UseHVXDbl = HST.useHVXDblOps();
 
   if (LocVT == MVT::v16i32) {
     if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
@@ -515,7 +510,7 @@ static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
       return false;
     }
   } else if (LocVT == MVT::v32i32) {
-    unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
+    unsigned Req = HST.useHVX128BOps() ? Hexagon::V0 : Hexagon::W0;
     if (unsigned Reg = State.AllocateReg(Req)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
@@ -561,28 +556,6 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
                        MachinePointerInfo(), MachinePointerInfo());
 }
 
-static bool isHvxVectorType(MVT Ty) {
-  switch (Ty.SimpleTy) {
-  case MVT::v8i64:
-  case MVT::v16i32:
-  case MVT::v32i16:
-  case MVT::v64i8:
-  case MVT::v16i64:
-  case MVT::v32i32:
-  case MVT::v64i16:
-  case MVT::v128i8:
-  case MVT::v32i64:
-  case MVT::v64i32:
-  case MVT::v128i16:
-  case MVT::v256i8:
-  case MVT::v512i1:
-  case MVT::v1024i1:
-    return true;
-  default:
-    return false;
-  }
-}
-
 bool
 HexagonTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
@@ -685,13 +658,14 @@ SDValue HexagonTargetLowering::LowerCallResult(
       // as an implicit def to the call (EmitMachineNode).
       RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
       Glue = TPR.getValue(1);
+      Chain = TPR.getValue(0);
     } else {
       RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
                                   RVLocs[i].getValVT(), Glue);
       Glue = RetVal.getValue(2);
+      Chain = RetVal.getValue(1);
     }
     InVals.push_back(RetVal.getValue(0));
-    Chain = RetVal.getValue(1);
   }
 
   return Chain;
@@ -743,12 +717,12 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   else
     CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
 
-  auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
+  auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
   if (Attr.getValueAsString() == "true")
     IsTailCall = false;
 
   if (IsTailCall) {
-    bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
+    bool StructAttrFlag = MF.getFunction().hasStructRetAttr();
     IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
                                                    IsVarArg, IsStructRet,
                                                    StructAttrFlag,
@@ -781,7 +755,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
     SDValue Arg = OutVals[i];
     ISD::ArgFlagsTy Flags = Outs[i].Flags;
     // Record if we need > 8 byte alignment on an argument.
-    bool ArgAlign = isHvxVectorType(VA.getValVT());
+    bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
     NeedsArgAlign |= ArgAlign;
 
     // Promote the value if needed.
@@ -835,9 +809,9 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
     DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
     // V6 vectors passed by value have 64 or 128 byte alignment depending
     // on whether we are 64 byte vector mode or 128 byte.
-    bool UseHVXDbl = Subtarget.useHVXDblOps();
+    bool UseHVX128B = Subtarget.useHVX128BOps();
     assert(Subtarget.useHVXOps());
-    const unsigned ObjAlign = UseHVXDbl ? 128 : 64;
+    const unsigned ObjAlign = UseHVX128B ? 128 : 64;
     LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
     MFI.ensureMaxAlignment(LargestAlignSeen);
   }
@@ -947,18 +921,16 @@ static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
     return false;
 
   auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
-  bool UseHVX = HST.useHVXOps();
-  bool UseHVXDbl = HST.useHVXDblOps();
 
-  bool ValidHVXDblType =
-    (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
+  bool ValidHVX128BType =
+      HST.useHVX128BOps() && (VT == MVT::v32i32 ||
                               VT == MVT::v64i16 || VT == MVT::v128i8);
   bool ValidHVXType =
-    UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
+      HST.useHVX64BOps() && (VT == MVT::v16i32 ||
                              VT == MVT::v32i16 || VT == MVT::v64i8);
 
-  if (ValidHVXDblType || ValidHVXType ||
-      VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
+  if (ValidHVX128BType || ValidHVXType || VT == MVT::i64 || VT == MVT::i32 ||
+      VT == MVT::i16 || VT == MVT::i8) {
     IsInc = (Ptr->getOpcode() == ISD::ADD);
     Base = Ptr->getOperand(0);
     Offset = Ptr->getOperand(1);
@@ -979,7 +951,6 @@ bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
                                                        SelectionDAG &DAG) const
 {
   EVT VT;
-  SDValue Ptr;
 
   if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
     VT  = LD->getMemoryVT();
@@ -1145,7 +1116,6 @@ SDValue HexagonTargetLowering::LowerFormalArguments(
   // callee return the result direclty through R0/R1.
 
   SmallVector<SDValue, 8> MemOps;
-  bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
 
   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
     CCValAssign &VA = ArgLocs[i];
@@ -1162,7 +1132,7 @@ SDValue HexagonTargetLowering::LowerFormalArguments(
       EVT RegVT = VA.getLocVT();
       if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
           RegVT == MVT::i32 || RegVT == MVT::f32) {
-        unsigned VReg = 
+        unsigned VReg =
           RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
@@ -1188,38 +1158,38 @@ SDValue HexagonTargetLowering::LowerFormalArguments(
         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
 
       // Single Vector
-      } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 ||
+      } else if ((RegVT == MVT::v16i32 ||
                   RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {
         unsigned VReg =
-          RegInfo.createVirtualRegister(&Hexagon::VectorRegsRegClass);
+          RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
-    } else if (UseHVX && UseHVXDbl &&
-               ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
-                 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
+      } else if (Subtarget.useHVX128BOps() &&
+                 ((RegVT == MVT::v32i32 ||
+                   RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
         unsigned VReg =
-          RegInfo.createVirtualRegister(&Hexagon::VectorRegs128BRegClass);
+          RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
 
       // Double Vector
-      } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
+      } else if ((RegVT == MVT::v32i32 ||
                   RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {
         unsigned VReg =
-          RegInfo.createVirtualRegister(&Hexagon::VecDblRegsRegClass);
+          RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
-      } else if (UseHVX && UseHVXDbl &&
-                ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
-                  RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
+      } else if (Subtarget.useHVX128BOps() &&
+                 ((RegVT == MVT::v64i32 ||
+                   RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
         unsigned VReg =
-          RegInfo.createVirtualRegister(&Hexagon::VecDblRegs128BRegClass);
+          RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
       } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) {
         assert(0 && "need to support VecPred regs");
         unsigned VReg =
-          RegInfo.createVirtualRegister(&Hexagon::VecPredRegsRegClass);
+          RegInfo.createVirtualRegister(&Hexagon::HvxQRRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
       } else {
@@ -1302,6 +1272,9 @@ SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
 
   SDValue LHS = Op.getOperand(0);
   SDValue RHS = Op.getOperand(1);
+  if (Subtarget.useHVXOps() && Subtarget.isHVXVectorType(ty(LHS)))
+    return LowerHvxSetCC(Op, DAG);
+
   SDValue Cmp = Op.getOperand(2);
   ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
 
@@ -1364,10 +1337,44 @@ HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
   return SDValue();
 }
 
+static Constant *convert_i1_to_i8(const Constant *ConstVal) {
+  SmallVector<Constant *, 128> NewConst;
+  const ConstantVector *CV = dyn_cast<ConstantVector>(ConstVal);
+  if (!CV)
+    return nullptr;
+
+  LLVMContext &Ctx = ConstVal->getContext();
+  IRBuilder<> IRB(Ctx);
+  unsigned NumVectorElements = CV->getNumOperands();
+  assert(isPowerOf2_32(NumVectorElements) &&
+         "conversion only supported for pow2 VectorSize!");
+
+  for (unsigned i = 0; i < NumVectorElements / 8; ++i) {
+    uint8_t x = 0;
+    for (unsigned j = 0; j < 8; ++j) {
+      uint8_t y = CV->getOperand(i * 8 + j)->getUniqueInteger().getZExtValue();
+      x |= y << (7 - j);
+    }
+    assert((x == 0 || x == 255) && "Either all 0's or all 1's expected!");
+    NewConst.push_back(IRB.getInt8(x));
+  }
+  return ConstantVector::get(NewConst);
+}
+
 SDValue
 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
   EVT ValTy = Op.getValueType();
   ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
+  Constant *CVal = nullptr;
+  bool isVTi1Type = false;
+  if (const Constant *ConstVal = dyn_cast<Constant>(CPN->getConstVal())) {
+    Type *CValTy = ConstVal->getType();
+    if (CValTy->isVectorTy() &&
+        CValTy->getVectorElementType()->isIntegerTy(1)) {
+      CVal = convert_i1_to_i8(ConstVal);
+      isVTi1Type = (CVal != nullptr);
+    }
+  }
   unsigned Align = CPN->getAlignment();
   bool IsPositionIndependent = isPositionIndependent();
   unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
@@ -1377,6 +1384,8 @@ HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
   if (CPN->isMachineConstantPoolEntry())
     T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
                                   TF);
+  else if (isVTi1Type)
+    T = DAG.getTargetConstantPool(CVal, ValTy, Align, Offset, TF);
   else
     T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset,
                                   TF);
@@ -1675,9 +1684,6 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
       Subtarget(ST) {
   bool IsV4 = !Subtarget.hasV5TOps();
   auto &HRI = *Subtarget.getRegisterInfo();
-  bool UseHVX = Subtarget.useHVXOps();
-  bool UseHVXSgl = Subtarget.useHVXSglOps();
-  bool UseHVXDbl = Subtarget.useHVXDblOps();
 
   setPrefLoopAlignment(4);
   setPrefFunctionAlignment(4);
@@ -1722,26 +1728,28 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   }
 
   if (Subtarget.hasV60TOps()) {
-    if (Subtarget.useHVXSglOps()) {
-      addRegisterClass(MVT::v64i8,  &Hexagon::VectorRegsRegClass);
-      addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass);
-      addRegisterClass(MVT::v16i32, &Hexagon::VectorRegsRegClass);
-      addRegisterClass(MVT::v8i64,  &Hexagon::VectorRegsRegClass);
-      addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass);
-      addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass);
-      addRegisterClass(MVT::v32i32, &Hexagon::VecDblRegsRegClass);
-      addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass);
-      addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass);
-    } else if (Subtarget.useHVXDblOps()) {
-      addRegisterClass(MVT::v128i8,  &Hexagon::VectorRegs128BRegClass);
-      addRegisterClass(MVT::v64i16,  &Hexagon::VectorRegs128BRegClass);
-      addRegisterClass(MVT::v32i32,  &Hexagon::VectorRegs128BRegClass);
-      addRegisterClass(MVT::v16i64,  &Hexagon::VectorRegs128BRegClass);
-      addRegisterClass(MVT::v256i8,  &Hexagon::VecDblRegs128BRegClass);
-      addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass);
-      addRegisterClass(MVT::v64i32,  &Hexagon::VecDblRegs128BRegClass);
-      addRegisterClass(MVT::v32i64,  &Hexagon::VecDblRegs128BRegClass);
-      addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass);
+    if (Subtarget.useHVX64BOps()) {
+      addRegisterClass(MVT::v64i8,  &Hexagon::HvxVRRegClass);
+      addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
+      addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
+      addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass);
+      addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass);
+      addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
+      addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass);
+      addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
+      addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
+      addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass);
+    } else if (Subtarget.useHVX128BOps()) {
+      addRegisterClass(MVT::v128i8,  &Hexagon::HvxVRRegClass);
+      addRegisterClass(MVT::v64i16,  &Hexagon::HvxVRRegClass);
+      addRegisterClass(MVT::v32i32,  &Hexagon::HvxVRRegClass);
+      addRegisterClass(MVT::v256i8,  &Hexagon::HvxWRRegClass);
+      addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass);
+      addRegisterClass(MVT::v64i32,  &Hexagon::HvxWRRegClass);
+      addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
+      addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
+      addRegisterClass(MVT::v128i1, &Hexagon::HvxQRRegClass);
+      addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass);
     }
   }
 
@@ -1946,6 +1954,15 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::SRL, VT, Custom);
   }
 
+  // Extending loads from (native) vectors of i8 into (native) vectors of i16
+  // are legal.
+  setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
+  setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
+
   // Types natively supported:
   for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
                        MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32,
@@ -1970,36 +1987,68 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8,  Custom);
 
-  if (UseHVX) {
-    if (UseHVXSgl) {
-      setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8,  Custom);
-      setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16,  Custom);
-      setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32,  Custom);
-      setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64,  Custom);
-      // We try to generate the vpack{e/o} instructions. If we fail
-      // we fall back upon ExpandOp.
-      setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8,  Custom);
-      setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
-      setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom);
-      setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom);
-      setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
-    } else if (UseHVXDbl) {
-      setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8,  Custom);
-      setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);
-      setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32,  Custom);
-      setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64,  Custom);
-      // We try to generate the vpack{e/o} instructions. If we fail
-      // we fall back upon ExpandOp.
-      setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v128i8,  Custom);
-      setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i16,  Custom);
-      setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
-      setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v128i8, Custom);
-      setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i16, Custom);
-      setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
-    } else {
-      llvm_unreachable("Unrecognized HVX mode");
+  auto setPromoteTo = [this] (unsigned Opc, MVT FromTy, MVT ToTy) {
+    setOperationAction(Opc, FromTy, Promote);
+    AddPromotedToType(Opc, FromTy, ToTy);
+  };
+
+  if (Subtarget.useHVXOps()) {
+    bool Use64b = Subtarget.useHVX64BOps();
+    ArrayRef<MVT> LegalV = Use64b ? LegalV64 : LegalV128;
+    ArrayRef<MVT> LegalW = Use64b ? LegalW64 : LegalW128;
+    MVT ByteV = Use64b ?  MVT::v64i8 : MVT::v128i8;
+    MVT ByteW = Use64b ? MVT::v128i8 : MVT::v256i8;
+
+    setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal);
+    setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal);
+    setOperationAction(ISD::CONCAT_VECTORS, ByteW, Legal);
+    setOperationAction(ISD::AND,            ByteV, Legal);
+    setOperationAction(ISD::OR,             ByteV, Legal);
+    setOperationAction(ISD::XOR,            ByteV, Legal);
+
+    for (MVT T : LegalV) {
+      setIndexedLoadAction(ISD::POST_INC,  T, Legal);
+      setIndexedStoreAction(ISD::POST_INC, T, Legal);
+
+      setOperationAction(ISD::ADD,     T, Legal);
+      setOperationAction(ISD::SUB,     T, Legal);
+      setOperationAction(ISD::VSELECT, T, Legal);
+      if (T != ByteV) {
+        setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
+        setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal);
+      }
+
+      setOperationAction(ISD::MUL,                T, Custom);
+      setOperationAction(ISD::SETCC,              T, Custom);
+      setOperationAction(ISD::BUILD_VECTOR,       T, Custom);
+      setOperationAction(ISD::INSERT_SUBVECTOR,   T, Custom);
+      setOperationAction(ISD::INSERT_VECTOR_ELT,  T, Custom);
+      setOperationAction(ISD::EXTRACT_SUBVECTOR,  T, Custom);
+      setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom);
+      if (T != ByteV)
+        setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom);
+    }
+
+    for (MVT T : LegalV) {
+      if (T == ByteV)
+        continue;
+      // Promote all shuffles and concats to operate on vectors of bytes.
+      setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV);
+      setPromoteTo(ISD::CONCAT_VECTORS, T, ByteV);
+      setPromoteTo(ISD::AND,            T, ByteV);
+      setPromoteTo(ISD::OR,             T, ByteV);
+      setPromoteTo(ISD::XOR,            T, ByteV);
+    }
+
+    for (MVT T : LegalW) {
+      if (T == ByteW)
+        continue;
+      // Promote all shuffles and concats to operate on vectors of bytes.
+      setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW);
+      setPromoteTo(ISD::CONCAT_VECTORS, T, ByteW);
     }
   }
+
   // Subtarget-specific operation actions.
   //
   if (Subtarget.hasV5TOps()) {
@@ -2061,20 +2110,6 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
     setIndexedStoreAction(ISD::POST_INC, VT, Legal);
   }
 
-  if (UseHVXSgl) {
-    for (MVT VT : {MVT::v64i8,  MVT::v32i16, MVT::v16i32, MVT::v8i64,
-                   MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {
-      setIndexedLoadAction(ISD::POST_INC, VT, Legal);
-      setIndexedStoreAction(ISD::POST_INC, VT, Legal);
-    }
-  } else if (UseHVXDbl) {
-    for (MVT VT : {MVT::v128i8, MVT::v64i16,  MVT::v32i32, MVT::v16i64,
-                   MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) {
-      setIndexedLoadAction(ISD::POST_INC, VT, Legal);
-      setIndexedStoreAction(ISD::POST_INC, VT, Legal);
-    }
-  }
-
   computeRegisterProperties(&HRI);
 
   //
@@ -2208,7 +2243,6 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case HexagonISD::INSERT:        return "HexagonISD::INSERT";
   case HexagonISD::INSERTRP:      return "HexagonISD::INSERTRP";
   case HexagonISD::JT:            return "HexagonISD::JT";
-  case HexagonISD::PACKHL:        return "HexagonISD::PACKHL";
   case HexagonISD::RET_FLAG:      return "HexagonISD::RET_FLAG";
   case HexagonISD::TC_RETURN:     return "HexagonISD::TC_RETURN";
   case HexagonISD::VCOMBINE:      return "HexagonISD::VCOMBINE";
@@ -2218,12 +2252,54 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case HexagonISD::VASR:          return "HexagonISD::VASR";
   case HexagonISD::VLSR:          return "HexagonISD::VLSR";
   case HexagonISD::VSPLAT:        return "HexagonISD::VSPLAT";
+  case HexagonISD::VEXTRACTW:     return "HexagonISD::VEXTRACTW";
+  case HexagonISD::VINSERTW0:     return "HexagonISD::VINSERTW0";
+  case HexagonISD::VROR:          return "HexagonISD::VROR";
   case HexagonISD::READCYCLE:     return "HexagonISD::READCYCLE";
   case HexagonISD::OP_END:        break;
   }
   return nullptr;
 }
 
+/// Given an intrinsic, checks if on the target the intrinsic will need to map
+/// to a MemIntrinsicNode (touches memory). If this is the case, it returns
+/// true and store the intrinsic information into the IntrinsicInfo that was
+/// passed to the function.
+bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
+                                               const CallInst &I,
+                                               MachineFunction &MF,
+                                               unsigned Intrinsic) const {
+  switch (Intrinsic) {
+  case Intrinsic::hexagon_V6_vgathermw:
+  case Intrinsic::hexagon_V6_vgathermw_128B:
+  case Intrinsic::hexagon_V6_vgathermh:
+  case Intrinsic::hexagon_V6_vgathermh_128B:
+  case Intrinsic::hexagon_V6_vgathermhw:
+  case Intrinsic::hexagon_V6_vgathermhw_128B:
+  case Intrinsic::hexagon_V6_vgathermwq:
+  case Intrinsic::hexagon_V6_vgathermwq_128B:
+  case Intrinsic::hexagon_V6_vgathermhq:
+  case Intrinsic::hexagon_V6_vgathermhq_128B:
+  case Intrinsic::hexagon_V6_vgathermhwq:
+  case Intrinsic::hexagon_V6_vgathermhwq_128B: {
+    const Module &M = *I.getParent()->getParent()->getParent();
+    Info.opc = ISD::INTRINSIC_W_CHAIN;
+    Type *VecTy = I.getArgOperand(1)->getType();
+    Info.memVT = MVT::getVT(VecTy);
+    Info.ptrVal = I.getArgOperand(0);
+    Info.offset = 0;
+    Info.align = M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8;
+    Info.flags = MachineMemOperand::MOLoad |
+                 MachineMemOperand::MOStore |
+                 MachineMemOperand::MOVolatile;
+    return true;
+  }
+  default:
+    break;
+  }
+  return false;
+}
+
 bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
   EVT MTy1 = EVT::getEVT(Ty1);
   EVT MTy2 = EVT::getEVT(Ty2);
@@ -2245,44 +2321,24 @@ bool HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
 // Should we expand the build vector with shuffles?
 bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
       unsigned DefinedValues) const {
-  // Hexagon vector shuffle operates on element sizes of bytes or halfwords
-  EVT EltVT = VT.getVectorElementType();
-  int EltBits = EltVT.getSizeInBits();
-  if ((EltBits != 8) && (EltBits != 16))
-    return false;
-
-  return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
+  return false;
 }
 
-static StridedLoadKind isStridedLoad(const ArrayRef<int> &Mask) {
-  int even_start = -2;
-  int odd_start = -1;
-  size_t mask_len = Mask.size();
-  for (auto idx : Mask) {
-    if ((idx - even_start) == 2)
-      even_start = idx;
-    else
-      break;
-  }
-  if (even_start == (int)(mask_len * 2) - 2)
-    return StridedLoadKind::Even;
-  for (auto idx : Mask) {
-    if ((idx - odd_start) == 2)
-      odd_start = idx;
-    else
-      break;
-  }
-  if (odd_start == (int)(mask_len * 2) - 1)
-    return StridedLoadKind::Odd;
-
-  return StridedLoadKind::NoPattern;
+bool HexagonTargetLowering::isShuffleMaskLegal(ArrayRef<int> Mask,
+                                               EVT VT) const {
+  return true;
 }
 
-bool HexagonTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
-      EVT VT) const {
-  if (Subtarget.useHVXOps())
-    return isStridedLoad(Mask) != StridedLoadKind::NoPattern;
-  return true;
+TargetLoweringBase::LegalizeTypeAction
+HexagonTargetLowering::getPreferredVectorAction(EVT VT) const {
+  if (Subtarget.useHVXOps()) {
+    // If the size of VT is at least half of the vector length,
+    // widen the vector. Note: the threshold was not selected in
+    // any scientific way.
+    if (VT.getSizeInBits() >= Subtarget.getVectorLength()*8/2)
+      return TargetLoweringBase::TypeWidenVector;
+  }
+  return TargetLowering::getPreferredVectorAction(VT);
 }
 
 // Lower a vector shuffle (V1, V2, V3).  V1 and V2 are the two vectors
@@ -2295,7 +2351,6 @@ HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
   SDValue V2 = Op.getOperand(1);
   SDLoc dl(Op);
   EVT VT = Op.getValueType();
-  bool UseHVX = Subtarget.useHVXOps();
 
   if (V2.isUndef())
     V2 = V1;
@@ -2327,27 +2382,6 @@ HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
                        DAG.getConstant(Lane, dl, MVT::i32));
   }
 
-  if (UseHVX) {
-    ArrayRef<int> Mask = SVN->getMask();
-    size_t MaskLen = Mask.size();
-    unsigned SizeInBits = VT.getScalarSizeInBits() * MaskLen;
-
-    if ((Subtarget.useHVXSglOps() && SizeInBits == 64 * 8) ||
-        (Subtarget.useHVXDblOps() && SizeInBits == 128 * 8)) {
-      StridedLoadKind Pattern = isStridedLoad(Mask);
-      if (Pattern == StridedLoadKind::NoPattern)
-        return SDValue();
-
-      unsigned Opc = Pattern == StridedLoadKind::Even ? HexagonISD::VPACKE
-                                                      : HexagonISD::VPACKO;
-      return DAG.getNode(Opc, dl, VT, {Op.getOperand(1), Op.getOperand(0)});
-    }
-    // We used to assert in the "else" part here, but that is bad for Halide
-    // Halide creates intermediate double registers by interleaving two
-    // concatenated vector registers. The interleaving requires vector_shuffle
-    // nodes and we shouldn't barf on a double register result of a
-    // vector_shuffle because it is most likely an intermediate result.
-  }
   // FIXME: We need to support more general vector shuffles.  See
   // below the comment from the ARM backend that deals in the general
   // case with the vector shuffles.  For now, let expand handle these.
@@ -2430,392 +2464,314 @@ HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
 }
 
 SDValue
-HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
-  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
-  SDLoc dl(Op);
-  EVT VT = Op.getValueType();
-
-  unsigned Size = VT.getSizeInBits();
+HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
+                                     MVT VecTy, SelectionDAG &DAG) const {
+  MVT ElemTy = VecTy.getVectorElementType();
+  assert(VecTy.getVectorNumElements() == Elem.size());
 
-  // Only handle vectors of 64 bits or shorter.
-  if (Size > 64)
-    return SDValue();
-
-  unsigned NElts = BVN->getNumOperands();
-
-  // Try to generate a SPLAT instruction.
-  if (VT == MVT::v4i8 || VT == MVT::v4i16 || VT == MVT::v2i32) {
-    APInt APSplatBits, APSplatUndef;
-    unsigned SplatBitSize;
-    bool HasAnyUndefs;
-    if (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
-                             HasAnyUndefs, 0, false)) {
-      if (SplatBitSize == VT.getVectorElementType().getSizeInBits()) {
-        unsigned ZV = APSplatBits.getZExtValue();
-        assert(SplatBitSize <= 32 && "Can only handle up to i32");
-        // Sign-extend the splat value from SplatBitSize to 32.
-        int32_t SV = SplatBitSize < 32
-                        ? int32_t(ZV << (32-SplatBitSize)) >> (32-SplatBitSize)
-                        : int32_t(ZV);
-        return DAG.getNode(HexagonISD::VSPLAT, dl, VT,
-                           DAG.getConstant(SV, dl, MVT::i32));
-      }
-    }
-  }
-
-  // Try to generate COMBINE to build v2i32 vectors.
-  if (VT.getSimpleVT() == MVT::v2i32) {
-    SDValue V0 = BVN->getOperand(0);
-    SDValue V1 = BVN->getOperand(1);
-
-    if (V0.isUndef())
-      V0 = DAG.getConstant(0, dl, MVT::i32);
-    if (V1.isUndef())
-      V1 = DAG.getConstant(0, dl, MVT::i32);
-
-    ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
-    ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
-    // If the element isn't a constant, it is in a register:
-    // generate a COMBINE Register Register instruction.
-    if (!C0 || !C1)
-      return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
-
-    // If one of the operands is an 8 bit integer constant, generate
-    // a COMBINE Immediate Immediate instruction.
-    if (isInt<8>(C0->getSExtValue()) ||
-        isInt<8>(C1->getSExtValue()))
-      return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
+  SmallVector<ConstantSDNode*,4> Consts;
+  bool AllConst = true;
+  for (SDValue V : Elem) {
+    if (isUndef(V))
+      V = DAG.getConstant(0, dl, ElemTy);
+    auto *C = dyn_cast<ConstantSDNode>(V.getNode());
+    Consts.push_back(C);
+    AllConst = AllConst && C != nullptr;
   }
 
-  // Try to generate a S2_packhl to build v2i16 vectors.
-  if (VT.getSimpleVT() == MVT::v2i16) {
-    for (unsigned i = 0, e = NElts; i != e; ++i) {
-      if (BVN->getOperand(i).isUndef())
-        continue;
-      ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
-      // If the element isn't a constant, it is in a register:
-      // generate a S2_packhl instruction.
-      if (!Cst) {
-        SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
-                                   BVN->getOperand(1), BVN->getOperand(0));
+  unsigned First, Num = Elem.size();
+  for (First = 0; First != Num; ++First)
+    if (!isUndef(Elem[First]))
+      break;
+  if (First == Num)
+    return DAG.getUNDEF(VecTy);
 
-        return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::v2i16,
-                                          pack);
-      }
+  if (ElemTy == MVT::i16) {
+    assert(Elem.size() == 2);
+    if (AllConst) {
+      uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
+                   Consts[1]->getZExtValue() << 16;
+      return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32));
     }
+    SDValue N = getNode(Hexagon::A2_combine_ll, dl, MVT::i32,
+                        {Elem[1], Elem[0]}, DAG);
+    return DAG.getBitcast(MVT::v2i16, N);
   }
 
-  // In the general case, generate a CONST32 or a CONST64 for constant vectors,
-  // and insert_vector_elt for all the other cases.
-  uint64_t Res = 0;
-  unsigned EltSize = Size / NElts;
-  SDValue ConstVal;
-  uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
-  bool HasNonConstantElements = false;
+  // First try generating a constant.
+  assert(ElemTy == MVT::i8 && Num == 4);
+  if (AllConst) {
+    int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
+                (Consts[1]->getZExtValue() & 0xFF) << 8 |
+                (Consts[1]->getZExtValue() & 0xFF) << 16 |
+                Consts[2]->getZExtValue() << 24;
+    return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
+  }
 
-  for (unsigned i = 0, e = NElts; i != e; ++i) {
-    // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
-    // combine, const64, etc. are Big Endian.
-    unsigned OpIdx = NElts - i - 1;
-    SDValue Operand = BVN->getOperand(OpIdx);
-    if (Operand.isUndef())
+  // Then try splat.
+  bool IsSplat = true;
+  for (unsigned i = 0; i != Num; ++i) {
+    if (i == First)
       continue;
-
-    int64_t Val = 0;
-    if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
-      Val = Cst->getSExtValue();
-    else
-      HasNonConstantElements = true;
-
-    Val &= Mask;
-    Res = (Res << EltSize) | Val;
+    if (Elem[i] == Elem[First] || isUndef(Elem[i]))
+      continue;
+    IsSplat = false;
+    break;
   }
+  if (IsSplat)
+    return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Elem[First]);
 
-  if (Size > 64)
-    return SDValue();
+  // Generate
+  //   (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
+  //   (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
+  SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
+  SDValue V0 = DAG.getZeroExtendInReg(Elem[0], dl, MVT::i8);
+  SDValue V1 = DAG.getZeroExtendInReg(Elem[1], dl, MVT::i8);
+  SDValue V2 = DAG.getZeroExtendInReg(Elem[2], dl, MVT::i8);
+  SDValue V3 = DAG.getZeroExtendInReg(Elem[3], dl, MVT::i8);
 
-  if (Size == 64)
-    ConstVal = DAG.getConstant(Res, dl, MVT::i64);
-  else
-    ConstVal = DAG.getConstant(Res, dl, MVT::i32);
+  SDValue V4 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V1, S8});
+  SDValue V5 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V3, S8});
+  SDValue V6 = DAG.getNode(ISD::OR, dl, MVT::i32, {V0, V4});
+  SDValue V7 = DAG.getNode(ISD::OR, dl, MVT::i32, {V2, V5});
 
-  // When there are non constant operands, add them with INSERT_VECTOR_ELT to
-  // ConstVal, the constant part of the vector.
-  if (HasNonConstantElements) {
-    EVT EltVT = VT.getVectorElementType();
-    SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
-    SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
-                                  DAG.getConstant(32, dl, MVT::i64));
+  SDValue T0 = getNode(Hexagon::A2_combine_ll, dl, MVT::i32, {V7, V6}, DAG);
+  return DAG.getBitcast(MVT::v4i8, T0);
+}
 
-    for (unsigned i = 0, e = NElts; i != e; ++i) {
-      // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
-      // is Big Endian.
-      unsigned OpIdx = NElts - i - 1;
-      SDValue Operand = BVN->getOperand(OpIdx);
-      if (isa<ConstantSDNode>(Operand))
-        // This operand is already in ConstVal.
-        continue;
+SDValue
+HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
+                                     MVT VecTy, SelectionDAG &DAG) const {
+  MVT ElemTy = VecTy.getVectorElementType();
+  assert(VecTy.getVectorNumElements() == Elem.size());
 
-      if (VT.getSizeInBits() == 64 &&
-          Operand.getValueSizeInBits() == 32) {
-        SDValue C = DAG.getConstant(0, dl, MVT::i32);
-        Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
-      }
+  SmallVector<ConstantSDNode*,8> Consts;
+  bool AllConst = true;
+  for (SDValue V : Elem) {
+    if (isUndef(V))
+      V = DAG.getConstant(0, dl, ElemTy);
+    auto *C = dyn_cast<ConstantSDNode>(V.getNode());
+    Consts.push_back(C);
+    AllConst = AllConst && C != nullptr;
+  }
 
-      SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
-      SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
-      SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
-      const SDValue Ops[] = {ConstVal, Operand, Combined};
+  unsigned First, Num = Elem.size();
+  for (First = 0; First != Num; ++First)
+    if (!isUndef(Elem[First]))
+      break;
+  if (First == Num)
+    return DAG.getUNDEF(VecTy);
 
-      if (VT.getSizeInBits() == 32)
-        ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
-      else
-        ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
+  // First try splat if possible.
+  if (ElemTy == MVT::i16) {
+    bool IsSplat = true;
+    for (unsigned i = 0; i != Num; ++i) {
+      if (i == First)
+        continue;
+      if (Elem[i] == Elem[First] || isUndef(Elem[i]))
+        continue;
+      IsSplat = false;
+      break;
     }
+    if (IsSplat)
+      return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Elem[First]);
+  }
+
+  // Then try constant.
+  if (AllConst) {
+    uint64_t Val = 0;
+    unsigned W = ElemTy.getSizeInBits();
+    uint64_t Mask = (ElemTy == MVT::i8)  ? 0xFFull
+                  : (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
+    for (unsigned i = 0; i != Num; ++i)
+      Val = (Val << W) | (Consts[i]->getZExtValue() & Mask);
+    SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
+    return DAG.getBitcast(VecTy, V0);
   }
 
-  return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
+  // Build two 32-bit vectors and concatenate.
+  MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
+  SDValue L = (ElemTy == MVT::i32)
+                ? Elem[0]
+                : buildVector32({Elem.data(), Num/2}, dl, HalfTy, DAG);
+  SDValue H = (ElemTy == MVT::i32)
+                ? Elem[1]
+                : buildVector32({Elem.data()+Num/2, Num/2}, dl, HalfTy, DAG);
+  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L});
 }
 
 SDValue
-HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
-                                           SelectionDAG &DAG) const {
-  SDLoc dl(Op);
-  bool UseHVX = Subtarget.useHVXOps();
-  EVT VT = Op.getValueType();
-  unsigned NElts = Op.getNumOperands();
-  SDValue Vec0 = Op.getOperand(0);
-  EVT VecVT = Vec0.getValueType();
-  unsigned Width = VecVT.getSizeInBits();
-
-  if (NElts == 2) {
-    MVT ST = VecVT.getSimpleVT();
-    // We are trying to concat two v2i16 to a single v4i16, or two v4i8
-    // into a single v8i8.
-    if (ST == MVT::v2i16 || ST == MVT::v4i8)
-      return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0);
+HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
+                                     const SDLoc &dl, MVT ValTy, MVT ResTy,
+                                     SelectionDAG &DAG) const {
+  MVT VecTy = ty(VecV);
+  assert(!ValTy.isVector() ||
+         VecTy.getVectorElementType() == ValTy.getVectorElementType());
+  unsigned VecWidth = VecTy.getSizeInBits();
+  unsigned ValWidth = ValTy.getSizeInBits();
+  unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
+  assert(VecWidth == 32 || VecWidth == 64);
+  assert((VecWidth % ElemWidth) == 0);
 
-    if (UseHVX) {
-      assert((Width ==  64*8 && Subtarget.useHVXSglOps()) ||
-             (Width == 128*8 && Subtarget.useHVXDblOps()));
-      SDValue Vec1 = Op.getOperand(1);
-      MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32;
-      MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32;
-      SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
-      SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
-      SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);
-      return DAG.getNode(ISD::BITCAST, dl, VT, VC);
-    }
-  }
+  // Cast everything to scalar integer types.
+  MVT ScalarTy = tyScalar(VecTy);
+  VecV = DAG.getBitcast(ScalarTy, VecV);
 
-  if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64)
-    return SDValue();
+  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
+  SDValue ExtV;
 
-  SDValue C0 = DAG.getConstant(0, dl, MVT::i64);
-  SDValue C32 = DAG.getConstant(32, dl, MVT::i64);
-  SDValue W = DAG.getConstant(Width, dl, MVT::i64);
-  // Create the "width" part of the argument to insert_rp/insertp_rp.
-  SDValue S = DAG.getNode(ISD::SHL, dl, MVT::i64, W, C32);
-  SDValue V = C0;
-
-  for (unsigned i = 0, e = NElts; i != e; ++i) {
-    unsigned N = NElts-i-1;
-    SDValue OpN = Op.getOperand(N);
-
-    if (VT.getSizeInBits() == 64 && OpN.getValueSizeInBits() == 32) {
-      SDValue C = DAG.getConstant(0, dl, MVT::i32);
-      OpN = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, OpN);
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
+    unsigned Off = C->getZExtValue() * ElemWidth;
+    if (VecWidth == 64 && ValWidth == 32) {
+      assert(Off == 0 || Off == 32);
+      unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
+      ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV);
+    } else if (Off == 0 && (ValWidth % 8) == 0) {
+      ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
+    } else {
+      SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
+      // The return type of EXTRACTU must be the same as the type of the
+      // input vector.
+      ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
+                         {VecV, WidthV, OffV});
     }
-    SDValue Idx = DAG.getConstant(N, dl, MVT::i64);
-    SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, W);
-    SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, S, Offset);
-    if (VT.getSizeInBits() == 32)
-      V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, {V, OpN, Or});
-    else if (VT.getSizeInBits() == 64)
-      V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, {V, OpN, Or});
-    else
-      return SDValue();
+  } else {
+    if (ty(IdxV) != MVT::i32)
+      IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
+    SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
+                               DAG.getConstant(ElemWidth, dl, MVT::i32));
+    // EXTRACTURP takes width/offset in a 64-bit pair.
+    SDValue CombV = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
+                                  {WidthV, OffV});
+    ExtV = DAG.getNode(HexagonISD::EXTRACTURP, dl, ScalarTy,
+                       {VecV, CombV});
   }
 
-  return DAG.getNode(ISD::BITCAST, dl, VT, V);
+  // Cast ExtV to the requested result type.
+  ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
+  ExtV = DAG.getBitcast(ResTy, ExtV);
+  return ExtV;
 }
 
 SDValue
-HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op,
-                                                  SelectionDAG &DAG) const {
-  EVT VT = Op.getOperand(0).getValueType();
-  SDLoc dl(Op);
-  bool UseHVX = Subtarget.useHVXOps();
-  bool UseHVXSgl = Subtarget.useHVXSglOps();
-  // Just in case...
+HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
+                                    const SDLoc &dl, MVT ValTy,
+                                    SelectionDAG &DAG) const {
+  MVT VecTy = ty(VecV);
+  unsigned VecWidth = VecTy.getSizeInBits();
+  unsigned ValWidth = ValTy.getSizeInBits();
+  assert(VecWidth == 32 || VecWidth == 64);
+  assert((VecWidth % ValWidth) == 0);
 
-  if (!VT.isVector() || !UseHVX)
-    return SDValue();
+  // Cast everything to scalar integer types.
+  MVT ScalarTy = MVT::getIntegerVT(VecWidth);
+  // The actual type of ValV may be different than ValTy (which is related
+  // to the vector type).
+  unsigned VW = ty(ValV).getSizeInBits();
+  ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
+  VecV = DAG.getBitcast(ScalarTy, VecV);
+  if (VW != VecWidth)
+    ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);
 
-  EVT ResVT = Op.getValueType();
-  unsigned ResSize = ResVT.getSizeInBits();
-  unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8);
-  unsigned OpSize = VT.getSizeInBits();
+  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
+  SDValue InsV;
 
-  // We deal only with cases where the result is the vector size
-  // and the vector operand is a double register.
-  if (!(ResVT.isByteSized() && ResSize == VectorSizeInBits) ||
-      !(VT.isByteSized() && OpSize == 2 * VectorSizeInBits))
-    return SDValue();
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
+    unsigned W = C->getZExtValue() * ValWidth;
+    SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
+    InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
+                       {VecV, ValV, WidthV, OffV});
+  } else {
+    if (ty(IdxV) != MVT::i32)
+      IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
+    SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
+    // INSERTRP takes width/offset in a 64-bit pair.
+    SDValue CombV = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
+                                  {WidthV, OffV});
+    InsV = DAG.getNode(HexagonISD::INSERTRP, dl, ScalarTy,
+                       {VecV, ValV, CombV});
+  }
 
-  ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
-  if (!Cst)
-    return SDValue();
-  unsigned Val = Cst->getZExtValue();
+  return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
+}
 
-  // These two will get lowered to an appropriate EXTRACT_SUBREG in ISel.
-  if (Val == 0) {
-    SDValue Vec = Op.getOperand(0);
-    return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResVT, Vec);
+SDValue
+HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
+  MVT VecTy = ty(Op);
+  unsigned BW = VecTy.getSizeInBits();
+  if (BW == 32 || BW == 64) {
+    SmallVector<SDValue,8> Ops;
+    for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
+      Ops.push_back(Op.getOperand(i));
+    if (BW == 32)
+      return buildVector32(Ops, SDLoc(Op), VecTy, DAG);
+    return buildVector64(Ops, SDLoc(Op), VecTy, DAG);
   }
 
-  if (ResVT.getVectorNumElements() == Val) {
-    SDValue Vec = Op.getOperand(0);
-    return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResVT, Vec);
-  }
+  if (Subtarget.useHVXOps() && Subtarget.isHVXVectorType(VecTy))
+    return LowerHvxBuildVector(Op, DAG);
 
   return SDValue();
 }
 
 SDValue
-HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
+HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
                                            SelectionDAG &DAG) const {
-  // If we are dealing with EXTRACT_SUBVECTOR on a HVX type, we may
-  // be able to simplify it to an EXTRACT_SUBREG.
-  if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && Subtarget.useHVXOps() &&
-      isHvxVectorType(Op.getValueType().getSimpleVT()))
-    return LowerEXTRACT_SUBVECTOR_HVX(Op, DAG);
-
-  EVT VT = Op.getValueType();
-  int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
-  SDLoc dl(Op);
-  SDValue Idx = Op.getOperand(1);
-  SDValue Vec = Op.getOperand(0);
-  EVT VecVT = Vec.getValueType();
-  EVT EltVT = VecVT.getVectorElementType();
-  int EltSize = EltVT.getSizeInBits();
-  SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
-                                  EltSize : VTN * EltSize, dl, MVT::i64);
-
-  // Constant element number.
-  if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
-    uint64_t X = CI->getZExtValue();
-    SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
-    const SDValue Ops[] = {Vec, Width, Offset};
-
-    ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
-    assert(CW && "Non constant width in LowerEXTRACT_VECTOR");
-
-    SDValue N;
-    MVT SVT = VecVT.getSimpleVT();
-    uint64_t W = CW->getZExtValue();
-
-    if (W == 32) {
-      // Translate this node into EXTRACT_SUBREG.
-      unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
-
-      if (X == 0)
-        Subreg = Hexagon::isub_lo;
-      else if (SVT == MVT::v2i32 && X == 1)
-        Subreg = Hexagon::isub_hi;
-      else if (SVT == MVT::v4i16 && X == 2)
-        Subreg = Hexagon::isub_hi;
-      else if (SVT == MVT::v8i8 && X == 4)
-        Subreg = Hexagon::isub_hi;
-      else
-        llvm_unreachable("Bad offset");
-      N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
-
-    } else if (SVT.getSizeInBits() == 32) {
-      N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
-    } else if (SVT.getSizeInBits() == 64) {
-      N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
-      if (VT.getSizeInBits() == 32)
-        N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
-    } else
-      return SDValue();
+  MVT VecTy = ty(Op);
+  assert(!Subtarget.useHVXOps() || !Subtarget.isHVXVectorType(VecTy));
 
-    return DAG.getNode(ISD::BITCAST, dl, VT, N);
+  if (VecTy.getSizeInBits() == 64) {
+    assert(Op.getNumOperands() == 2);
+    return DAG.getNode(HexagonISD::COMBINE, SDLoc(Op), VecTy, Op.getOperand(1),
+                       Op.getOperand(0));
   }
 
-  // Variable element number.
-  SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
-                               DAG.getConstant(EltSize, dl, MVT::i32));
-  SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
-                                DAG.getConstant(32, dl, MVT::i64));
-  SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
-
-  const SDValue Ops[] = {Vec, Combined};
-
-  SDValue N;
-  if (VecVT.getSizeInBits() == 32) {
-    N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
-  } else {
-    N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
-    if (VT.getSizeInBits() == 32)
-      N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
-  }
-  return DAG.getNode(ISD::BITCAST, dl, VT, N);
+  return SDValue();
 }
 
 SDValue
-HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
-                                          SelectionDAG &DAG) const {
-  EVT VT = Op.getValueType();
-  int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
-  SDLoc dl(Op);
+HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
+                                               SelectionDAG &DAG) const {
   SDValue Vec = Op.getOperand(0);
-  SDValue Val = Op.getOperand(1);
-  SDValue Idx = Op.getOperand(2);
-  EVT VecVT = Vec.getValueType();
-  EVT EltVT = VecVT.getVectorElementType();
-  int EltSize = EltVT.getSizeInBits();
-  SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
-                                  EltSize : VTN * EltSize, dl, MVT::i64);
+  MVT VecTy = ty(Vec);
+  if (Subtarget.useHVXOps() && Subtarget.isHVXVectorType(VecTy))
+    return LowerHvxExtractElement(Op, DAG);
 
-  if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
-    SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
-    const SDValue Ops[] = {Vec, Val, Width, Offset};
-
-    SDValue N;
-    if (VT.getSizeInBits() == 32)
-      N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
-    else if (VT.getSizeInBits() == 64)
-      N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
-    else
-      return SDValue();
+  MVT ElemTy = ty(Vec).getVectorElementType();
+  return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
+}
 
-    return DAG.getNode(ISD::BITCAST, dl, VT, N);
-  }
+SDValue
+HexagonTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
+                                              SelectionDAG &DAG) const {
+  SDValue Vec = Op.getOperand(0);
+  MVT VecTy = ty(Vec);
+  if (Subtarget.useHVXOps() && Subtarget.isHVXVectorType(VecTy))
+    return LowerHvxExtractSubvector(Op, DAG);
 
-  // Variable element number.
-  SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
-                               DAG.getConstant(EltSize, dl, MVT::i32));
-  SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
-                                DAG.getConstant(32, dl, MVT::i64));
-  SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
+  return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ty(Op), ty(Op), DAG);
+}
 
-  if (VT.getSizeInBits() == 64 && Val.getValueSizeInBits() == 32) {
-    SDValue C = DAG.getConstant(0, dl, MVT::i32);
-    Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
-  }
+SDValue
+HexagonTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
+                                              SelectionDAG &DAG) const {
+  MVT VecTy = ty(Op);
+  if (Subtarget.useHVXOps() && Subtarget.isHVXVectorType(VecTy))
+    return LowerHvxInsertElement(Op, DAG);
 
-  const SDValue Ops[] = {Vec, Val, Combined};
+  return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
+                      SDLoc(Op), VecTy.getVectorElementType(), DAG);
+}
 
-  SDValue N;
-  if (VT.getSizeInBits() == 32)
-    N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
-  else if (VT.getSizeInBits() == 64)
-    N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
-  else
-    return SDValue();
+SDValue
+HexagonTargetLowering::LowerINSERT_SUBVECTOR(SDValue Op,
+                                             SelectionDAG &DAG) const {
+  if (Subtarget.useHVXOps() && Subtarget.isHVXVectorType(ty(Op)))
+    return LowerHvxInsertSubvector(Op, DAG);
 
-  return DAG.getNode(ISD::BITCAST, dl, VT, N);
+  SDValue ValV = Op.getOperand(1);
+  return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
+                      SDLoc(Op), ty(ValV), DAG);
 }
 
 bool
@@ -2870,10 +2826,10 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
 #endif
       llvm_unreachable("Should not custom lower this!");
     case ISD::CONCAT_VECTORS:       return LowerCONCAT_VECTORS(Op, DAG);
-    case ISD::INSERT_SUBVECTOR:     return LowerINSERT_VECTOR(Op, DAG);
-    case ISD::INSERT_VECTOR_ELT:    return LowerINSERT_VECTOR(Op, DAG);
-    case ISD::EXTRACT_SUBVECTOR:    return LowerEXTRACT_VECTOR(Op, DAG);
-    case ISD::EXTRACT_VECTOR_ELT:   return LowerEXTRACT_VECTOR(Op, DAG);
+    case ISD::INSERT_SUBVECTOR:     return LowerINSERT_SUBVECTOR(Op, DAG);
+    case ISD::INSERT_VECTOR_ELT:    return LowerINSERT_VECTOR_ELT(Op, DAG);
+    case ISD::EXTRACT_SUBVECTOR:    return LowerEXTRACT_SUBVECTOR(Op, DAG);
+    case ISD::EXTRACT_VECTOR_ELT:   return LowerEXTRACT_VECTOR_ELT(Op, DAG);
     case ISD::BUILD_VECTOR:         return LowerBUILD_VECTOR(Op, DAG);
     case ISD::VECTOR_SHUFFLE:       return LowerVECTOR_SHUFFLE(Op, DAG);
     case ISD::SRA:
@@ -2899,7 +2855,12 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
     case ISD::INLINEASM:            return LowerINLINEASM(Op, DAG);
     case ISD::PREFETCH:             return LowerPREFETCH(Op, DAG);
     case ISD::READCYCLECOUNTER:     return LowerREADCYCLECOUNTER(Op, DAG);
+    case ISD::MUL:
+      if (Subtarget.useHVXOps())
+        return LowerHvxMul(Op, DAG);
+      break;
   }
+  return SDValue();
 }
 
 /// Returns relocation base for the given PIC jumptable.
@@ -2923,7 +2884,11 @@ HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
       case 'q':
       case 'v':
         if (Subtarget.useHVXOps())
-          return C_Register;
+          return C_RegisterClass;
+        break;
+      case 'a':
+        return C_RegisterClass;
+      default:
         break;
     }
   }
@@ -2933,49 +2898,53 @@ HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
 std::pair<unsigned, const TargetRegisterClass*>
 HexagonTargetLowering::getRegForInlineAsmConstraint(
     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
-  bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
 
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     case 'r':   // R0-R31
       switch (VT.SimpleTy) {
       default:
-        llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
+        return {0u, nullptr};
       case MVT::i1:
       case MVT::i8:
       case MVT::i16:
       case MVT::i32:
       case MVT::f32:
-        return std::make_pair(0U, &Hexagon::IntRegsRegClass);
+        return {0u, &Hexagon::IntRegsRegClass};
       case MVT::i64:
       case MVT::f64:
-        return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
+        return {0u, &Hexagon::DoubleRegsRegClass};
       }
+      break;
+    case 'a': // M0-M1
+      if (VT != MVT::i32)
+        return {0u, nullptr};
+      return {0u, &Hexagon::ModRegsRegClass};
     case 'q': // q0-q3
       switch (VT.getSizeInBits()) {
       default:
-        llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size");
+        return {0u, nullptr};
       case 512:
-        return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
       case 1024:
-        return std::make_pair(0U, &Hexagon::VecPredRegs128BRegClass);
+        return {0u, &Hexagon::HvxQRRegClass};
       }
+      break;
     case 'v': // V0-V31
       switch (VT.getSizeInBits()) {
       default:
-        llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size");
+        return {0u, nullptr};
       case 512:
-        return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
+        return {0u, &Hexagon::HvxVRRegClass};
       case 1024:
-        if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
-          return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
-        return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
+        if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps())
+          return {0u, &Hexagon::HvxVRRegClass};
+        return {0u, &Hexagon::HvxWRRegClass};
       case 2048:
-        return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
+        return {0u, &Hexagon::HvxWRRegClass};
       }
-
+      break;
     default:
-      llvm_unreachable("Unknown asm register class");
+      return {0u, nullptr};
     }
   }
 
@@ -2993,7 +2962,7 @@ bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
 /// AM is legal for this target, for a load/store of the specified type.
 bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
                                                   const AddrMode &AM, Type *Ty,
-                                                  unsigned AS) const {
+                                                  unsigned AS, Instruction *I) const {
   if (Ty->isSized()) {
     // When LSR detects uses of the same base address to access different
     // types (e.g. unions), it will assume a conservative type for these
@@ -3055,8 +3024,8 @@ bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
                                  const SmallVectorImpl<SDValue> &OutVals,
                                  const SmallVectorImpl<ISD::InputArg> &Ins,
                                  SelectionDAG& DAG) const {
-  const Function *CallerF = DAG.getMachineFunction().getFunction();
-  CallingConv::ID CallerCC = CallerF->getCallingConv();
+  const Function &CallerF = DAG.getMachineFunction().getFunction();
+  CallingConv::ID CallerCC = CallerF.getCallingConv();
   bool CCMatch = CallerCC == CalleeCC;
 
   // ***************************************************************************
@@ -3142,9 +3111,6 @@ bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
   case MVT::v16i32:
   case MVT::v32i32:
   case MVT::v64i32:
-  case MVT::v8i64:
-  case MVT::v16i64:
-  case MVT::v32i64:
     return true;
   }
   return false;
@@ -3162,24 +3128,21 @@ HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
   case MVT::v64i8:
   case MVT::v32i16:
   case MVT::v16i32:
-  case MVT::v8i64:
-    RRC = &Hexagon::VectorRegsRegClass;
+    RRC = &Hexagon::HvxVRRegClass;
     break;
   case MVT::v128i8:
   case MVT::v64i16:
   case MVT::v32i32:
-  case MVT::v16i64:
     if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
-        Subtarget.useHVXDblOps())
-      RRC = &Hexagon::VectorRegs128BRegClass;
+        Subtarget.useHVX128BOps())
+      RRC = &Hexagon::HvxVRRegClass;
     else
-      RRC = &Hexagon::VecDblRegsRegClass;
+      RRC = &Hexagon::HvxWRRegClass;
     break;
   case MVT::v256i8:
   case MVT::v128i16:
   case MVT::v64i32:
-  case MVT::v32i64:
-    RRC = &Hexagon::VecDblRegs128BRegClass;
+    RRC = &Hexagon::HvxWRRegClass;
     break;
   }
   return std::make_pair(RRC, Cost);
diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h
index d66cbc95e918..0619e2e4e7f9 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/lib/Target/Hexagon/HexagonISelLowering.h
@@ -20,10 +20,10 @@
 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/InlineAsm.h"
-#include "llvm/Target/TargetLowering.h"
 #include <cstdint>
 #include <utility>
 
@@ -51,7 +51,6 @@ namespace HexagonISD {
       CP,          // Constant pool.
 
       COMBINE,
-      PACKHL,
       VSPLAT,
       VASL,
       VASR,
@@ -64,6 +63,9 @@ namespace HexagonISD {
       VCOMBINE,
       VPACKE,
       VPACKO,
+      VEXTRACTW,
+      VINSERTW0,
+      VROR,
       TC_RETURN,
       EH_RETURN,
       DCFETCH,
@@ -89,6 +91,8 @@ namespace HexagonISD {
     explicit HexagonTargetLowering(const TargetMachine &TM,
                                    const HexagonSubtarget &ST);
 
+    bool isHVXVectorType(MVT Ty) const;
+
     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
     /// for tail call optimization. Targets which want to do tail call
     /// optimization should implement this function.
@@ -98,6 +102,10 @@ namespace HexagonISD {
         const SmallVectorImpl<SDValue> &OutVals,
         const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
 
+    bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
+                            MachineFunction &MF,
+                            unsigned Intrinsic) const override;
+
     bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
     bool isTruncateFree(EVT VT1, EVT VT2) const override;
 
@@ -113,18 +121,22 @@ namespace HexagonISD {
     bool shouldExpandBuildVectorWithShuffles(EVT VT,
         unsigned DefinedValues) const override;
 
-    bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, EVT VT)
+    bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
+    TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
         const override;
 
     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
     const char *getTargetNodeName(unsigned Opcode) const override;
+
+    SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
+
     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
@@ -231,7 +243,8 @@ namespace HexagonISD {
     /// mode is legal for a load/store of any legal type.
     /// TODO: Handle pre/postinc as well.
     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
-                               Type *Ty, unsigned AS) const override;
+                               Type *Ty, unsigned AS,
+                               Instruction *I = nullptr) const override;
     /// Return true if folding a constant offset with the given GlobalAddress
     /// is legal.  It is frequently not legal in PIC relocation models.
     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
@@ -269,7 +282,77 @@ namespace HexagonISD {
       return AtomicExpansionKind::LLSC;
     }
 
-  protected:
+  private:
+    SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
+                          SelectionDAG &DAG) const;
+    SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
+                          SelectionDAG &DAG) const;
+    SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
+                          MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
+    SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
+                         const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
+    bool isUndef(SDValue Op) const {
+      if (Op.isMachineOpcode())
+        return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
+      return Op.getOpcode() == ISD::UNDEF;
+    }
+    SDValue getNode(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
+                    ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
+      SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
+      return SDValue(N, 0);
+    }
+
+    using VectorPair = std::pair<SDValue, SDValue>;
+    using TypePair = std::pair<MVT, MVT>;
+
+    SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
+                   const SDLoc &dl, SelectionDAG &DAG) const;
+
+    MVT ty(SDValue Op) const {
+      return Op.getValueType().getSimpleVT();
+    }
+    TypePair ty(const VectorPair &Ops) const {
+      return { Ops.first.getValueType().getSimpleVT(),
+               Ops.second.getValueType().getSimpleVT() };
+    }
+    MVT tyScalar(MVT Ty) const {
+      if (!Ty.isVector())
+        return Ty;
+      return MVT::getIntegerVT(Ty.getSizeInBits());
+    }
+    MVT tyVector(MVT Ty, MVT ElemTy) const {
+      if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)
+        return Ty;
+      unsigned TyWidth = Ty.getSizeInBits(), ElemWidth = ElemTy.getSizeInBits();
+      assert((TyWidth % ElemWidth) == 0);
+      return MVT::getVectorVT(ElemTy, TyWidth/ElemWidth);
+    }
+
+    MVT typeJoin(const TypePair &Tys) const;
+    TypePair typeSplit(MVT Ty) const;
+    MVT typeExtElem(MVT VecTy, unsigned Factor) const;
+    MVT typeTruncElem(MVT VecTy, unsigned Factor) const;
+
+    SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,
+                   SelectionDAG &DAG) const;
+    VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
+    SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;
+
+    SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
+                               SelectionDAG &DAG) const;
+    SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;
+    SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1,
+                           ArrayRef<int> Mask, SelectionDAG &DAG) const;
+
+    SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerHvxMul(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
+
     std::pair<const TargetRegisterClass*, uint8_t>
     findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
         const override;
diff --git a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
new file mode 100644
index 000000000000..c1d44cb0e7de
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -0,0 +1,463 @@
+//===-- HexagonISelLoweringHVX.cpp --- Lowering HVX operations ------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "HexagonISelLowering.h"
+#include "HexagonRegisterInfo.h"
+#include "HexagonSubtarget.h"
+
+using namespace llvm;
+
+SDValue
+HexagonTargetLowering::getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
+                              const SDLoc &dl, SelectionDAG &DAG) const {
+  SmallVector<SDValue,4> IntOps;
+  IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32));
+  for (const SDValue &Op : Ops)
+    IntOps.push_back(Op);
+  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps);
+}
+
+MVT
+HexagonTargetLowering::typeJoin(const TypePair &Tys) const {
+  assert(Tys.first.getVectorElementType() == Tys.second.getVectorElementType());
+
+  MVT ElemTy = Tys.first.getVectorElementType();
+  return MVT::getVectorVT(ElemTy, Tys.first.getVectorNumElements() +
+                                  Tys.second.getVectorNumElements());
+}
+
+HexagonTargetLowering::TypePair
+HexagonTargetLowering::typeSplit(MVT VecTy) const {
+  assert(VecTy.isVector());
+  unsigned NumElem = VecTy.getVectorNumElements();
+  assert((NumElem % 2) == 0 && "Expecting even-sized vector type");
+  MVT HalfTy = MVT::getVectorVT(VecTy.getVectorElementType(), NumElem/2);
+  return { HalfTy, HalfTy };
+}
+
+MVT
+HexagonTargetLowering::typeExtElem(MVT VecTy, unsigned Factor) const {
+  MVT ElemTy = VecTy.getVectorElementType();
+  MVT NewElemTy = MVT::getIntegerVT(ElemTy.getSizeInBits() * Factor);
+  return MVT::getVectorVT(NewElemTy, VecTy.getVectorNumElements());
+}
+
+MVT
+HexagonTargetLowering::typeTruncElem(MVT VecTy, unsigned Factor) const {
+  MVT ElemTy = VecTy.getVectorElementType();
+  MVT NewElemTy = MVT::getIntegerVT(ElemTy.getSizeInBits() / Factor);
+  return MVT::getVectorVT(NewElemTy, VecTy.getVectorNumElements());
+}
+
+SDValue
+HexagonTargetLowering::opCastElem(SDValue Vec, MVT ElemTy,
+                                  SelectionDAG &DAG) const {
+  if (ty(Vec).getVectorElementType() == ElemTy)
+    return Vec;
+  MVT CastTy = tyVector(Vec.getValueType().getSimpleVT(), ElemTy);
+  return DAG.getBitcast(CastTy, Vec);
+}
+
+SDValue
+HexagonTargetLowering::opJoin(const VectorPair &Ops, const SDLoc &dl,
+                              SelectionDAG &DAG) const {
+  return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)),
+                     Ops.second, Ops.first);
+}
+
+HexagonTargetLowering::VectorPair
+HexagonTargetLowering::opSplit(SDValue Vec, const SDLoc &dl,
+                               SelectionDAG &DAG) const {
+  TypePair Tys = typeSplit(ty(Vec));
+  return DAG.SplitVector(Vec, dl, Tys.first, Tys.second);
+}
+
+SDValue
+HexagonTargetLowering::convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
+                                          SelectionDAG &DAG) const {
+  if (ElemIdx.getValueType().getSimpleVT() != MVT::i32)
+    ElemIdx = DAG.getBitcast(MVT::i32, ElemIdx);
+
+  unsigned ElemWidth = ElemTy.getSizeInBits();
+  if (ElemWidth == 8)
+    return ElemIdx;
+
+  unsigned L = Log2_32(ElemWidth/8);
+  const SDLoc &dl(ElemIdx);
+  return DAG.getNode(ISD::SHL, dl, MVT::i32,
+                     {ElemIdx, DAG.getConstant(L, dl, MVT::i32)});
+}
+
+SDValue
+HexagonTargetLowering::getIndexInWord32(SDValue Idx, MVT ElemTy,
+                                        SelectionDAG &DAG) const {
+  unsigned ElemWidth = ElemTy.getSizeInBits();
+  assert(ElemWidth >= 8 && ElemWidth <= 32);
+  if (ElemWidth == 32)
+    return Idx;
+
+  if (ty(Idx) != MVT::i32)
+    Idx = DAG.getBitcast(MVT::i32, Idx);
+  const SDLoc &dl(Idx);
+  SDValue Mask = DAG.getConstant(32/ElemWidth - 1, dl, MVT::i32);
+  SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask});
+  return SubIdx;
+}
+
+SDValue
+HexagonTargetLowering::getByteShuffle(const SDLoc &dl, SDValue Op0,
+                                      SDValue Op1, ArrayRef<int> Mask,
+                                      SelectionDAG &DAG) const {
+  MVT OpTy = ty(Op0);
+  assert(OpTy == ty(Op1));
+
+  MVT ElemTy = OpTy.getVectorElementType();
+  if (ElemTy == MVT::i8)
+    return DAG.getVectorShuffle(OpTy, dl, Op0, Op1, Mask);
+  assert(ElemTy.getSizeInBits() >= 8);
+
+  MVT ResTy = tyVector(OpTy, MVT::i8);
+  unsigned ElemSize = ElemTy.getSizeInBits() / 8;
+
+  SmallVector<int,128> ByteMask;
+  for (int M : Mask) {
+    if (M < 0) {
+      for (unsigned I = 0; I != ElemSize; ++I)
+        ByteMask.push_back(-1);
+    } else {
+      int NewM = M*ElemSize;
+      for (unsigned I = 0; I != ElemSize; ++I)
+        ByteMask.push_back(NewM+I);
+    }
+  }
+  assert(ResTy.getVectorNumElements() == ByteMask.size());
+  return DAG.getVectorShuffle(ResTy, dl, opCastElem(Op0, MVT::i8, DAG),
+                              opCastElem(Op1, MVT::i8, DAG), ByteMask);
+}
+
+SDValue
+HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG)
+      const {
+  const SDLoc &dl(Op);
+  BuildVectorSDNode *BN = cast<BuildVectorSDNode>(Op.getNode());
+  bool IsConst = BN->isConstant();
+  MachineFunction &MF = DAG.getMachineFunction();
+  MVT VecTy = ty(Op);
+
+  if (IsConst) {
+    SmallVector<Constant*, 128> Elems;
+    for (SDValue V : BN->op_values()) {
+      if (auto *C = dyn_cast<ConstantSDNode>(V.getNode()))
+        Elems.push_back(const_cast<ConstantInt*>(C->getConstantIntValue()));
+    }
+    Constant *CV = ConstantVector::get(Elems);
+    unsigned Align = VecTy.getSizeInBits() / 8;
+    SDValue CP = LowerConstantPool(DAG.getConstantPool(CV, VecTy, Align), DAG);
+    return DAG.getLoad(VecTy, dl, DAG.getEntryNode(), CP,
+                       MachinePointerInfo::getConstantPool(MF), Align);
+  }
+
+  unsigned NumOps = Op.getNumOperands();
+  unsigned HwLen = Subtarget.getVectorLength();
+  unsigned ElemSize = VecTy.getVectorElementType().getSizeInBits() / 8;
+  assert(ElemSize*NumOps == HwLen);
+
+  SmallVector<SDValue,32> Words;
+  SmallVector<SDValue,32> Ops;
+  for (unsigned i = 0; i != NumOps; ++i)
+    Ops.push_back(Op.getOperand(i));
+
+  if (VecTy.getVectorElementType() != MVT::i32) {
+    assert(ElemSize < 4 && "vNi64 should have been promoted to vNi32");
+    assert((ElemSize == 1 || ElemSize == 2) && "Invalid element size");
+    unsigned OpsPerWord = (ElemSize == 1) ? 4 : 2;
+    MVT PartVT = MVT::getVectorVT(VecTy.getVectorElementType(), OpsPerWord);
+    for (unsigned i = 0; i != NumOps; i += OpsPerWord) {
+      SDValue W = buildVector32({&Ops[i], OpsPerWord}, dl, PartVT, DAG);
+      Words.push_back(DAG.getBitcast(MVT::i32, W));
+    }
+  } else {
+    Words.assign(Ops.begin(), Ops.end());
+  }
+
+  // Construct two halves in parallel, then or them together.
+  assert(4*Words.size() == Subtarget.getVectorLength());
+  SDValue HalfV0 = getNode(Hexagon::V6_vd0, dl, VecTy, {}, DAG);
+  SDValue HalfV1 = getNode(Hexagon::V6_vd0, dl, VecTy, {}, DAG);
+  SDValue S = DAG.getConstant(4, dl, MVT::i32);
+  unsigned NumWords = Words.size();
+  for (unsigned i = 0; i != NumWords/2; ++i) {
+    SDValue N = DAG.getNode(HexagonISD::VINSERTW0, dl, VecTy,
+                            {HalfV0, Words[i]});
+    SDValue M = DAG.getNode(HexagonISD::VINSERTW0, dl, VecTy,
+                            {HalfV1, Words[i+NumWords/2]});
+    HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {N, S});
+    HalfV1 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {M, S});
+  }
+
+  HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy,
+                       {HalfV0, DAG.getConstant(HwLen/2, dl, MVT::i32)});
+  SDValue DstV = DAG.getNode(ISD::OR, dl, VecTy, {HalfV0, HalfV1});
+  return DstV;
+}
+
+SDValue
+HexagonTargetLowering::LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG)
+      const {
+  // Change the type of the extracted element to i32.
+  SDValue VecV = Op.getOperand(0);
+  MVT ElemTy = ty(VecV).getVectorElementType();
+  unsigned ElemWidth = ElemTy.getSizeInBits();
+  assert(ElemWidth >= 8 && ElemWidth <= 32);
+  (void)ElemWidth;
+
+  const SDLoc &dl(Op);
+  SDValue IdxV = Op.getOperand(1);
+  if (ty(IdxV) != MVT::i32)
+    IdxV = DAG.getBitcast(MVT::i32, IdxV);
+
+  SDValue ByteIdx = convertToByteIndex(IdxV, ElemTy, DAG);
+  SDValue ExWord = DAG.getNode(HexagonISD::VEXTRACTW, dl, MVT::i32,
+                               {VecV, ByteIdx});
+  if (ElemTy == MVT::i32)
+    return ExWord;
+
+  // Have an extracted word, need to extract the smaller element out of it.
+  // 1. Extract the bits of (the original) IdxV that correspond to the index
+  //    of the desired element in the 32-bit word.
+  SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG);
+  // 2. Extract the element from the word.
+  SDValue ExVec = DAG.getBitcast(tyVector(ty(ExWord), ElemTy), ExWord);
+  return extractVector(ExVec, SubIdx, dl, ElemTy, MVT::i32, DAG);
+}
+
+SDValue
+HexagonTargetLowering::LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG)
+      const {
+  const SDLoc &dl(Op);
+  SDValue VecV = Op.getOperand(0);
+  SDValue ValV = Op.getOperand(1);
+  SDValue IdxV = Op.getOperand(2);
+  MVT ElemTy = ty(VecV).getVectorElementType();
+  unsigned ElemWidth = ElemTy.getSizeInBits();
+  assert(ElemWidth >= 8 && ElemWidth <= 32);
+  (void)ElemWidth;
+
+  auto InsertWord = [&DAG,&dl,this] (SDValue VecV, SDValue ValV,
+                                     SDValue ByteIdxV) {
+    MVT VecTy = ty(VecV);
+    unsigned HwLen = Subtarget.getVectorLength();
+    SDValue MaskV = DAG.getNode(ISD::AND, dl, MVT::i32,
+                                {ByteIdxV, DAG.getConstant(-4, dl, MVT::i32)});
+    SDValue RotV = DAG.getNode(HexagonISD::VROR, dl, VecTy, {VecV, MaskV});
+    SDValue InsV = DAG.getNode(HexagonISD::VINSERTW0, dl, VecTy, {RotV, ValV});
+    SDValue SubV = DAG.getNode(ISD::SUB, dl, MVT::i32,
+                               {DAG.getConstant(HwLen/4, dl, MVT::i32), MaskV});
+    SDValue TorV = DAG.getNode(HexagonISD::VROR, dl, VecTy, {InsV, SubV});
+    return TorV;
+  };
+
+  SDValue ByteIdx = convertToByteIndex(IdxV, ElemTy, DAG);
+  if (ElemTy == MVT::i32)
+    return InsertWord(VecV, ValV, ByteIdx);
+
+  // If this is not inserting a 32-bit word, convert it into such a thing.
+  // 1. Extract the existing word from the target vector.
+  SDValue WordIdx = DAG.getNode(ISD::SRL, dl, MVT::i32,
+                                {ByteIdx, DAG.getConstant(2, dl, MVT::i32)});
+  SDValue Ex0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
+                            {opCastElem(VecV, MVT::i32, DAG), WordIdx});
+  SDValue Ext = LowerHvxExtractElement(Ex0, DAG);
+
+  // 2. Treating the extracted word as a 32-bit vector, insert the given
+  //    value into it.
+  SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG);
+  MVT SubVecTy = tyVector(ty(Ext), ElemTy);
+  SDValue Ins = insertVector(DAG.getBitcast(SubVecTy, Ext),
+                             ValV, SubIdx, dl, ElemTy, DAG);
+
+  // 3. Insert the 32-bit word back into the original vector.
+  return InsertWord(VecV, Ins, ByteIdx);
+}
+
+SDValue
+HexagonTargetLowering::LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG)
+      const {
+  SDValue SrcV = Op.getOperand(0);
+  MVT SrcTy = ty(SrcV);
+  unsigned SrcElems = SrcTy.getVectorNumElements();
+  SDValue IdxV = Op.getOperand(1);
+  unsigned Idx = cast<ConstantSDNode>(IdxV.getNode())->getZExtValue();
+  MVT DstTy = ty(Op);
+  assert(Idx == 0 || DstTy.getVectorNumElements() % Idx == 0);
+  const SDLoc &dl(Op);
+  if (Idx == 0)
+    return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, DstTy, SrcV);
+  if (Idx == SrcElems/2)
+    return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, DstTy, SrcV);
+  return SDValue();
+}
+
+SDValue
+HexagonTargetLowering::LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG)
+      const {
+  // Idx may be variable.
+  SDValue IdxV = Op.getOperand(2);
+  auto *IdxN = dyn_cast<ConstantSDNode>(IdxV.getNode());
+  if (!IdxN)
+    return SDValue();
+  unsigned Idx = IdxN->getZExtValue();
+
+  SDValue DstV = Op.getOperand(0);
+  SDValue SrcV = Op.getOperand(1);
+  MVT DstTy = ty(DstV);
+  MVT SrcTy = ty(SrcV);
+  unsigned DstElems = DstTy.getVectorNumElements();
+  unsigned SrcElems = SrcTy.getVectorNumElements();
+  if (2*SrcElems != DstElems)
+    return SDValue();
+
+  const SDLoc &dl(Op);
+  if (Idx == 0)
+    return DAG.getTargetInsertSubreg(Hexagon::vsub_lo, dl, DstTy, DstV, SrcV);
+  if (Idx == SrcElems)
+    return DAG.getTargetInsertSubreg(Hexagon::vsub_hi, dl, DstTy, DstV, SrcV);
+  return SDValue();
+}
+
+SDValue
+HexagonTargetLowering::LowerHvxMul(SDValue Op, SelectionDAG &DAG) const {
+  MVT ResTy = ty(Op);
+  if (!ResTy.isVector())
+    return SDValue();
+  const SDLoc &dl(Op);
+  SmallVector<int,256> ShuffMask;
+
+  MVT ElemTy = ResTy.getVectorElementType();
+  unsigned VecLen = ResTy.getVectorNumElements();
+  SDValue Vs = Op.getOperand(0);
+  SDValue Vt = Op.getOperand(1);
+
+  switch (ElemTy.SimpleTy) {
+    case MVT::i8:
+    case MVT::i16: {
+      // For i8 vectors Vs = (a0, a1, ...), Vt = (b0, b1, ...),
+      // V6_vmpybv Vs, Vt produces a pair of i16 vectors Hi:Lo,
+      // where Lo = (a0*b0, a2*b2, ...), Hi = (a1*b1, a3*b3, ...).
+      // For i16, use V6_vmpyhv, which behaves in an analogous way to
+      // V6_vmpybv: results Lo and Hi are products of even/odd elements
+      // respectively.
+      MVT ExtTy = typeExtElem(ResTy, 2);
+      unsigned MpyOpc = ElemTy == MVT::i8 ? Hexagon::V6_vmpybv
+                                          : Hexagon::V6_vmpyhv;
+      SDValue M = getNode(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG);
+
+      // Discard high halves of the resulting values, collect the low halves.
+      for (unsigned I = 0; I < VecLen; I += 2) {
+        ShuffMask.push_back(I);         // Pick even element.
+        ShuffMask.push_back(I+VecLen);  // Pick odd element.
+      }
+      VectorPair P = opSplit(opCastElem(M, ElemTy, DAG), dl, DAG);
+      return getByteShuffle(dl, P.first, P.second, ShuffMask, DAG);
+    }
+    case MVT::i32: {
+      // Use the following sequence for signed word multiply:
+      // T0 = V6_vmpyiowh Vs, Vt
+      // T1 = V6_vaslw T0, 16
+      // T2 = V6_vmpyiewuh_acc T1, Vs, Vt
+      SDValue S16 = DAG.getConstant(16, dl, MVT::i32);
+      SDValue T0 = getNode(Hexagon::V6_vmpyiowh, dl, ResTy, {Vs, Vt}, DAG);
+      SDValue T1 = getNode(Hexagon::V6_vaslw, dl, ResTy, {T0, S16}, DAG);
+      SDValue T2 = getNode(Hexagon::V6_vmpyiewuh_acc, dl, ResTy,
+                           {T1, Vs, Vt}, DAG);
+      return T2;
+    }
+    default:
+      break;
+  }
+  return SDValue();
+}
+
+SDValue
+HexagonTargetLowering::LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const {
+  MVT VecTy = ty(Op.getOperand(0));
+  assert(VecTy == ty(Op.getOperand(1)));
+
+  SDValue Cmp = Op.getOperand(2);
+  ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
+  bool Negate = false, Swap = false;
+
+  // HVX has instructions for SETEQ, SETGT, SETUGT. The other comparisons
+  // can be arranged as operand-swapped/negated versions of these. Since
+  // the generated code will have the original CC expressed as
+  //   (negate (swap-op NewCmp)),
+  // the condition code for the NewCmp should be calculated from the original
+  // CC by applying these operations in the reverse order.
+
+  switch (CC) {
+    case ISD::SETNE:    // !eq
+    case ISD::SETLE:    // !gt
+    case ISD::SETGE:    // !lt
+    case ISD::SETULE:   // !ugt
+    case ISD::SETUGE:   // !ult
+      CC = ISD::getSetCCInverse(CC, true);
+      Negate = true;
+      break;
+    default:
+      break;
+  }
+
+  switch (CC) {
+    case ISD::SETLT:    // swap gt
+    case ISD::SETULT:   // swap ugt
+      CC = ISD::getSetCCSwappedOperands(CC);
+      Swap = true;
+      break;
+    default:
+      break;
+  }
+
+  assert(CC == ISD::SETEQ || CC == ISD::SETGT || CC == ISD::SETUGT);
+
+  MVT ElemTy = VecTy.getVectorElementType();
+  unsigned ElemWidth = ElemTy.getSizeInBits();
+  assert(isPowerOf2_32(ElemWidth));
+
+  auto getIdx = [] (unsigned Code) {
+    static const unsigned Idx[] = { ISD::SETEQ, ISD::SETGT, ISD::SETUGT };
+    for (unsigned I = 0, E = array_lengthof(Idx); I != E; ++I)
+      if (Code == Idx[I])
+        return I;
+    llvm_unreachable("Unhandled CondCode");
+  };
+
+  static unsigned OpcTable[3][3] = {
+    //           SETEQ             SETGT,            SETUGT
+    /* Byte */ { Hexagon::V6_veqb, Hexagon::V6_vgtb, Hexagon::V6_vgtub },
+    /* Half */ { Hexagon::V6_veqh, Hexagon::V6_vgth, Hexagon::V6_vgtuh },
+    /* Word */ { Hexagon::V6_veqw, Hexagon::V6_vgtw, Hexagon::V6_vgtuw }
+  };
+
+  unsigned CmpOpc = OpcTable[Log2_32(ElemWidth)-3][getIdx(CC)];
+
+  MVT ResTy = ty(Op);
+  const SDLoc &dl(Op);
+  SDValue OpL = Swap ? Op.getOperand(1) : Op.getOperand(0);
+  SDValue OpR = Swap ? Op.getOperand(0) : Op.getOperand(1);
+  SDValue CmpV = getNode(CmpOpc, dl, ResTy, {OpL, OpR}, DAG);
+  return Negate ? getNode(Hexagon::V6_pred_not, dl, ResTy, {CmpV}, DAG)
+                : CmpV;
+}
+
+SDValue
+HexagonTargetLowering::LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const {
+  // Sign- and zero-extends are legal.
+  assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG);
+  return DAG.getZeroExtendVectorInReg(Op.getOperand(0), SDLoc(Op), ty(Op));
+}
diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td
index 636a439ba6a9..1bb3bc1ea31b 100644
--- a/lib/Target/Hexagon/HexagonInstrFormats.td
+++ b/lib/Target/Hexagon/HexagonInstrFormats.td
@@ -24,14 +24,14 @@ class MemAccessSize<bits<4> value> {
   bits<4> Value = value;
 }
 
-// MemAccessSize is represented as 1+log2(N) where N is size in bits.
-def NoMemAccess      : MemAccessSize<0>;// Not a memory access instruction.
-def ByteAccess       : MemAccessSize<1>;// Byte access instruction (memb).
-def HalfWordAccess   : MemAccessSize<2>;// Half word access instruction (memh).
-def WordAccess       : MemAccessSize<3>;// Word access instruction (memw).
-def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
-def Vector64Access   : MemAccessSize<7>;// Vector access instruction (memv)
-def Vector128Access  : MemAccessSize<8>;// Vector access instruction (memv)
+// These numbers must match the MemAccessSize enumeration values in
+// HexagonBaseInfo.h.
+def NoMemAccess      : MemAccessSize<0>;
+def ByteAccess       : MemAccessSize<1>;
+def HalfWordAccess   : MemAccessSize<2>;
+def WordAccess       : MemAccessSize<3>;
+def DoubleWordAccess : MemAccessSize<4>;
+def HVXVectorAccess  : MemAccessSize<5>;
 
 
 //===----------------------------------------------------------------------===//
@@ -77,9 +77,9 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
   // Packed only with A or X-type instructions.
   bits<1> isSoloAX = 0;
   let TSFlags{7} = isSoloAX;
-  // Only A-type instruction in first slot or nothing.
-  bits<1> isSoloAin1 = 0;
-  let TSFlags{8} = isSoloAin1;
+  // Restricts slot 1 to ALU-only instructions.
+  bits<1> isRestrictSlot1AOK = 0;
+  let TSFlags{8} = isRestrictSlot1AOK;
 
   // Predicated instructions.
   bits<1> isPredicated = 0;
@@ -121,6 +121,16 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
   bits<2> opExtentAlign = 0;
   let TSFlags{34-33} = opExtentAlign; // Alignment exponent before extending.
 
+  bit cofMax1 = 0;
+  let TSFlags{35} = cofMax1;
+  bit cofRelax1 = 0;
+  let TSFlags{36} = cofRelax1;
+  bit cofRelax2 = 0;
+  let TSFlags{37} = cofRelax2;
+
+  bit isRestrictNoSlot1Store = 0;
+  let TSFlags{38} = isRestrictNoSlot1Store;
+
   // Addressing mode for load/store instructions.
   AddrModeType addrMode = NoAddrMode;
   let TSFlags{43-41} = addrMode.Value;
@@ -135,6 +145,9 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
   bits<1> isFP = 0;
   let TSFlags {49} = isFP; // Floating-point.
 
+  bits<1> isSomeOK = 0;
+  let TSFlags {50} = isSomeOK; // Relax some grouping constraints.
+
   bits<1> hasNewValue2 = 0;
   let TSFlags{51} = hasNewValue2; // Second New-value producer insn.
   bits<3> opNewValue2 = 0;
@@ -146,8 +159,8 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
   bits<1> prefersSlot3 = 0;
   let TSFlags{56} = prefersSlot3; // Complex XU
 
-  bit cofMax1 = 0;
-  let TSFlags{60} = cofMax1;
+  bits<1> hasTmpDst = 0;
+  let TSFlags{59} = hasTmpDst;  // v65 : 'fake" register VTMP is set
 
   bit CVINew = 0;
   let TSFlags{61} = CVINew;
@@ -229,15 +242,8 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 include "HexagonInstrFormatsV4.td"
 
 //===----------------------------------------------------------------------===//
-// V55 Instruction Format Definitions +
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// V60 Instruction Format Definitions +
+// V60+ Instruction Format Definitions +
 //===----------------------------------------------------------------------===//
 
 include "HexagonInstrFormatsV60.td"
-
-//===----------------------------------------------------------------------===//
-// V62 Instruction Format Definitions +
-//===----------------------------------------------------------------------===//
+include "HexagonInstrFormatsV65.td"
diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV65.td b/lib/Target/Hexagon/HexagonInstrFormatsV65.td
new file mode 100644
index 000000000000..cddb8777b417
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonInstrFormatsV65.td
@@ -0,0 +1,32 @@
+//==- HexagonInstrFormatsV65.td - Hexagon Instruction Formats -*- tablegen -==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the Hexagon V60 instruction classes in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+//----------------------------------------------------------------------------//
+//                         Hexagon Intruction Flags +
+//
+//                        *** Must match BaseInfo.h ***
+//----------------------------------------------------------------------------//
+
+//----------------------------------------------------------------------------//
+//                         Intruction Classes Definitions +
+//----------------------------------------------------------------------------//
+
+class CVI_VA_Resource_NoOpcode<dag outs, dag ins, string asmstr,
+                       list<dag> pattern = [], string cstr = "",
+                       InstrItinClass itin = CVI_VA>
+   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>;
+
+class CVI_GATHER_TMP_LD_Resource_NoOpcode<dag outs, dag ins, string asmstr,
+                        list<dag> pattern = [], string cstr = "",
+                        InstrItinClass itin = CVI_GATHER_PSEUDO>
+   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_GATHER>;
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index c77c669f4ca7..b82a0157e81f 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1,4 +1,4 @@
-//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
+//===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -13,9 +13,11 @@
 
 #include "HexagonInstrInfo.h"
 #include "Hexagon.h"
+#include "HexagonFrameLowering.h"
 #include "HexagonHazardRecognizer.h"
 #include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
+#include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
@@ -32,7 +34,13 @@
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/DebugLoc.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrItineraries.h"
@@ -43,13 +51,14 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/Target/TargetMachine.h"
 #include <cassert>
 #include <cctype>
 #include <cstdint>
 #include <cstring>
 #include <iterator>
+#include <string>
+#include <utility>
 
 using namespace llvm;
 
@@ -91,9 +100,7 @@ static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
   cl::init(true), cl::Hidden, cl::ZeroOrMore,
   cl::desc("Use the DFA based hazard recognizer."));
 
-///
 /// Constants for Hexagon instructions.
-///
 const int Hexagon_MEMW_OFFSET_MAX = 4095;
 const int Hexagon_MEMW_OFFSET_MIN = -4096;
 const int Hexagon_MEMD_OFFSET_MAX = 8191;
@@ -104,25 +111,13 @@ const int Hexagon_MEMB_OFFSET_MAX = 1023;
 const int Hexagon_MEMB_OFFSET_MIN = -1024;
 const int Hexagon_ADDI_OFFSET_MAX = 32767;
 const int Hexagon_ADDI_OFFSET_MIN = -32768;
-const int Hexagon_MEMD_AUTOINC_MAX = 56;
-const int Hexagon_MEMD_AUTOINC_MIN = -64;
-const int Hexagon_MEMW_AUTOINC_MAX = 28;
-const int Hexagon_MEMW_AUTOINC_MIN = -32;
-const int Hexagon_MEMH_AUTOINC_MAX = 14;
-const int Hexagon_MEMH_AUTOINC_MIN = -16;
-const int Hexagon_MEMB_AUTOINC_MAX = 7;
-const int Hexagon_MEMB_AUTOINC_MIN = -8;
-const int Hexagon_MEMV_AUTOINC_MAX = 192;   // #s3
-const int Hexagon_MEMV_AUTOINC_MIN = -256;  // #s3
-const int Hexagon_MEMV_AUTOINC_MAX_128B = 384;  // #s3
-const int Hexagon_MEMV_AUTOINC_MIN_128B = -512; // #s3
 
 // Pin the vtable to this file.
 void HexagonInstrInfo::anchor() {}
 
 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
-    : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
-      RI() {}
+  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
+    Subtarget(ST) {}
 
 static bool isIntRegForSubInst(unsigned Reg) {
   return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
@@ -251,18 +246,12 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   case Hexagon::L2_loadrd_io:
   case Hexagon::V6_vL32b_ai:
   case Hexagon::V6_vL32b_nt_ai:
-  case Hexagon::V6_vL32b_ai_128B:
-  case Hexagon::V6_vL32b_nt_ai_128B:
   case Hexagon::V6_vL32Ub_ai:
-  case Hexagon::V6_vL32Ub_ai_128B:
   case Hexagon::LDriw_pred:
   case Hexagon::LDriw_mod:
   case Hexagon::PS_vloadrq_ai:
   case Hexagon::PS_vloadrw_ai:
-  case Hexagon::PS_vloadrw_nt_ai:
-  case Hexagon::PS_vloadrq_ai_128B:
-  case Hexagon::PS_vloadrw_ai_128B:
-  case Hexagon::PS_vloadrw_nt_ai_128B: {
+  case Hexagon::PS_vloadrw_nt_ai: {
     const MachineOperand OpFI = MI.getOperand(1);
     if (!OpFI.isFI())
       return 0;
@@ -306,15 +295,11 @@ unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
   case Hexagon::S2_storeri_io:
   case Hexagon::S2_storerd_io:
   case Hexagon::V6_vS32b_ai:
-  case Hexagon::V6_vS32b_ai_128B:
   case Hexagon::V6_vS32Ub_ai:
-  case Hexagon::V6_vS32Ub_ai_128B:
   case Hexagon::STriw_pred:
   case Hexagon::STriw_mod:
   case Hexagon::PS_vstorerq_ai:
-  case Hexagon::PS_vstorerw_ai:
-  case Hexagon::PS_vstorerq_ai_128B:
-  case Hexagon::PS_vstorerw_ai_128B: {
+  case Hexagon::PS_vstorerw_ai: {
     const MachineOperand &OpFI = MI.getOperand(0);
     if (!OpFI.isFI())
       return 0;
@@ -362,7 +347,6 @@ unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
 /// Cond[1] = R
 /// Cond[2] = Imm
-///
 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                      MachineBasicBlock *&TBB,
                                      MachineBasicBlock *&FBB,
@@ -479,7 +463,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
       Cond.push_back(LastInst->getOperand(1));
       return false;
     }
-    DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
+    DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
                  << " with one jump\n";);
     // Otherwise, don't know what this is.
     return true;
@@ -527,7 +511,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
     FBB = LastInst->getOperand(0).getMBB();
     return false;
   }
-  DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
+  DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
                << " with two jumps";);
   // Otherwise, can't handle this.
   return true;
@@ -537,7 +521,7 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
                                         int *BytesRemoved) const {
   assert(!BytesRemoved && "code size not handled");
 
-  DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
+  DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
   MachineBasicBlock::iterator I = MBB.end();
   unsigned Count = 0;
   while (I != MBB.begin()) {
@@ -599,7 +583,7 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
       SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
       MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
                                          VisitedBBs);
-      assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
+      assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
       Loop->getOperand(0).setMBB(TBB);
       // Add the ENDLOOP after the finding the LOOP0.
       BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
@@ -609,7 +593,7 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
       // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
       // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
       unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
-      DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
+      DEBUG(dbgs() << "\nInserting NVJump for " << printMBBReference(MBB););
       if (Cond[2].isReg()) {
         unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
         BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
@@ -640,7 +624,7 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
     SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
     MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
                                        VisitedBBs);
-    assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
+    assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
     Loop->getOperand(0).setMBB(TBB);
     // Add the ENDLOOP after the finding the LOOP0.
     BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
@@ -715,10 +699,11 @@ unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB,
   unsigned NewLoopCount = createVR(MF, MVT::i32);
   MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
     addReg(LoopCount).addImm(-1);
+  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
   // Update the previously generated instructions with the new loop counter.
   for (SmallVectorImpl<MachineInstr *>::iterator I = PrevInsts.begin(),
          E = PrevInsts.end(); I != E; ++I)
-    (*I)->substituteRegister(LoopCount, NewLoopCount, 0, getRegisterInfo());
+    (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI);
   PrevInsts.clear();
   PrevInsts.push_back(NewCmp);
   PrevInsts.push_back(NewAdd);
@@ -757,7 +742,7 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator I,
                                    const DebugLoc &DL, unsigned DestReg,
                                    unsigned SrcReg, bool KillSrc) const {
-  auto &HRI = getRegisterInfo();
+  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
   unsigned KillFlag = getKillRegState(KillSrc);
 
   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
@@ -812,12 +797,12 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       .addReg(SrcReg, KillFlag);
     return;
   }
-  if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) {
+  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
     BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
       addReg(SrcReg, KillFlag);
     return;
   }
-  if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) {
+  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
     unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
     unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
     BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
@@ -825,39 +810,27 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       .addReg(LoSrc, KillFlag);
     return;
   }
-  if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) {
+  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
     BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
       .addReg(SrcReg)
       .addReg(SrcReg, KillFlag);
     return;
   }
-  if (Hexagon::VecPredRegsRegClass.contains(SrcReg) &&
-      Hexagon::VectorRegsRegClass.contains(DestReg)) {
+  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
+      Hexagon::HvxVRRegClass.contains(DestReg)) {
     llvm_unreachable("Unimplemented pred to vec");
     return;
   }
-  if (Hexagon::VecPredRegsRegClass.contains(DestReg) &&
-      Hexagon::VectorRegsRegClass.contains(SrcReg)) {
+  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
+      Hexagon::HvxVRRegClass.contains(SrcReg)) {
     llvm_unreachable("Unimplemented vec to pred");
     return;
   }
-  if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) {
-    unsigned HiDst = HRI.getSubReg(DestReg, Hexagon::vsub_hi);
-    unsigned LoDst = HRI.getSubReg(DestReg, Hexagon::vsub_lo);
-    unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
-    unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
-    BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), HiDst)
-      .addReg(HiSrc, KillFlag);
-    BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), LoDst)
-      .addReg(LoSrc, KillFlag);
-    return;
-  }
 
 #ifndef NDEBUG
   // Show the invalid registers to ease debugging.
-  dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
-         << ": " << PrintReg(DestReg, &HRI)
-         << " = " << PrintReg(SrcReg, &HRI) << '\n';
+  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
+         << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
 #endif
   llvm_unreachable("Unimplemented");
 }
@@ -868,15 +841,15 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   DebugLoc DL = MBB.findDebugLoc(I);
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo &MFI = MF.getFrameInfo();
-  unsigned Align = MFI.getObjectAlignment(FI);
+  unsigned SlotAlign = MFI.getObjectAlignment(FI);
+  unsigned RegAlign = TRI->getSpillAlignment(*RC);
   unsigned KillFlag = getKillRegState(isKill);
   bool HasAlloca = MFI.hasVarSizedObjects();
-  const auto &HST = MF.getSubtarget<HexagonSubtarget>();
-  const HexagonFrameLowering &HFI = *HST.getFrameLowering();
+  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
 
   MachineMemOperand *MMO = MF.getMachineMemOperand(
       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
-      MFI.getObjectSize(FI), Align);
+      MFI.getObjectSize(FI), SlotAlign);
 
   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
     BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
@@ -894,50 +867,34 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     BuildMI(MBB, I, DL, get(Hexagon::STriw_mod))
       .addFrameIndex(FI).addImm(0)
       .addReg(SrcReg, KillFlag).addMemOperand(MMO);
-  } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
-    BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai_128B))
-      .addFrameIndex(FI).addImm(0)
-      .addReg(SrcReg, KillFlag).addMemOperand(MMO);
-  } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
+  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
     BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
       .addFrameIndex(FI).addImm(0)
       .addReg(SrcReg, KillFlag).addMemOperand(MMO);
-  } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
+  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
     // If there are variable-sized objects, spills will not be aligned.
     if (HasAlloca)
-      Align = HFI.getStackAlignment();
-    unsigned Opc = Align < 128 ? Hexagon::V6_vS32Ub_ai_128B
-                               : Hexagon::V6_vS32b_ai_128B;
+      SlotAlign = HFI.getStackAlignment();
+    unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai
+                                        : Hexagon::V6_vS32b_ai;
+    MachineMemOperand *MMOA = MF.getMachineMemOperand(
+        MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
+        MFI.getObjectSize(FI), SlotAlign);
     BuildMI(MBB, I, DL, get(Opc))
       .addFrameIndex(FI).addImm(0)
-      .addReg(SrcReg, KillFlag).addMemOperand(MMO);
-  } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
-    // If there are variable-sized objects, spills will not be aligned.
-    if (HasAlloca)
-      Align = HFI.getStackAlignment();
-    unsigned Opc = Align < 64 ? Hexagon::V6_vS32Ub_ai
-                              : Hexagon::V6_vS32b_ai;
-    BuildMI(MBB, I, DL, get(Opc))
-      .addFrameIndex(FI).addImm(0)
-      .addReg(SrcReg, KillFlag).addMemOperand(MMO);
-  } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
-    // If there are variable-sized objects, spills will not be aligned.
-    if (HasAlloca)
-      Align = HFI.getStackAlignment();
-    unsigned Opc = Align < 64 ? Hexagon::PS_vstorerwu_ai
-                              : Hexagon::PS_vstorerw_ai;
-    BuildMI(MBB, I, DL, get(Opc))
-      .addFrameIndex(FI).addImm(0)
-      .addReg(SrcReg, KillFlag).addMemOperand(MMO);
-  } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
+      .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
+  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
     // If there are variable-sized objects, spills will not be aligned.
     if (HasAlloca)
-      Align = HFI.getStackAlignment();
-    unsigned Opc = Align < 128 ? Hexagon::PS_vstorerwu_ai_128B
-                               : Hexagon::PS_vstorerw_ai_128B;
+      SlotAlign = HFI.getStackAlignment();
+    unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai
+                                        : Hexagon::PS_vstorerw_ai;
+    MachineMemOperand *MMOA = MF.getMachineMemOperand(
+        MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
+        MFI.getObjectSize(FI), SlotAlign);
     BuildMI(MBB, I, DL, get(Opc))
       .addFrameIndex(FI).addImm(0)
-      .addReg(SrcReg, KillFlag).addMemOperand(MMO);
+      .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
   } else {
     llvm_unreachable("Unimplemented");
   }
@@ -950,14 +907,14 @@ void HexagonInstrInfo::loadRegFromStackSlot(
   DebugLoc DL = MBB.findDebugLoc(I);
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo &MFI = MF.getFrameInfo();
-  unsigned Align = MFI.getObjectAlignment(FI);
+  unsigned SlotAlign = MFI.getObjectAlignment(FI);
+  unsigned RegAlign = TRI->getSpillAlignment(*RC);
   bool HasAlloca = MFI.hasVarSizedObjects();
-  const auto &HST = MF.getSubtarget<HexagonSubtarget>();
-  const HexagonFrameLowering &HFI = *HST.getFrameLowering();
+  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
 
   MachineMemOperand *MMO = MF.getMachineMemOperand(
       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
-      MFI.getObjectSize(FI), Align);
+      MFI.getObjectSize(FI), SlotAlign);
 
   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
     BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
@@ -971,44 +928,31 @@ void HexagonInstrInfo::loadRegFromStackSlot(
   } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
     BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg)
       .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
-  } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
-    BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai_128B), DestReg)
-      .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
-  } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
+  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
     BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
       .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
-  } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
-    // If there are variable-sized objects, spills will not be aligned.
-    if (HasAlloca)
-      Align = HFI.getStackAlignment();
-    unsigned Opc = Align < 128 ? Hexagon::PS_vloadrwu_ai_128B
-                               : Hexagon::PS_vloadrw_ai_128B;
-    BuildMI(MBB, I, DL, get(Opc), DestReg)
-      .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
-  } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
+  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
     // If there are variable-sized objects, spills will not be aligned.
     if (HasAlloca)
-      Align = HFI.getStackAlignment();
-    unsigned Opc = Align < 128 ? Hexagon::V6_vL32Ub_ai_128B
-                               : Hexagon::V6_vL32b_ai_128B;
+      SlotAlign = HFI.getStackAlignment();
+    unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai
+                                        : Hexagon::V6_vL32b_ai;
+    MachineMemOperand *MMOA = MF.getMachineMemOperand(
+        MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
+        MFI.getObjectSize(FI), SlotAlign);
     BuildMI(MBB, I, DL, get(Opc), DestReg)
-      .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
-  } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
-    // If there are variable-sized objects, spills will not be aligned.
-    if (HasAlloca)
-      Align = HFI.getStackAlignment();
-    unsigned Opc = Align < 64 ? Hexagon::V6_vL32Ub_ai
-                              : Hexagon::V6_vL32b_ai;
-    BuildMI(MBB, I, DL, get(Opc), DestReg)
-      .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
-  } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
+      .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
+  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
     // If there are variable-sized objects, spills will not be aligned.
     if (HasAlloca)
-      Align = HFI.getStackAlignment();
-    unsigned Opc = Align < 64 ? Hexagon::PS_vloadrwu_ai
-                              : Hexagon::PS_vloadrw_ai;
+      SlotAlign = HFI.getStackAlignment();
+    unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai
+                                        : Hexagon::PS_vloadrw_ai;
+    MachineMemOperand *MMOA = MF.getMachineMemOperand(
+        MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
+        MFI.getObjectSize(FI), SlotAlign);
     BuildMI(MBB, I, DL, get(Opc), DestReg)
-      .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
+      .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
   } else {
     llvm_unreachable("Can't store this register to stack slot");
   }
@@ -1029,12 +973,12 @@ static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
 /// new instructions and erase MI. The function should return true if
 /// anything was changed.
 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
-  const HexagonRegisterInfo &HRI = getRegisterInfo();
-  MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   MachineBasicBlock &MBB = *MI.getParent();
+  MachineFunction &MF = *MBB.getParent();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
   DebugLoc DL = MI.getDebugLoc();
   unsigned Opc = MI.getOpcode();
-  const unsigned VecOffset = 1;
 
   switch (Opc) {
     case TargetOpcode::COPY: {
@@ -1054,7 +998,6 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
           .addImm(-MI.getOperand(1).getImm());
       MBB.erase(MI);
       return true;
-    case Hexagon::V6_vassignp_128B:
     case Hexagon::V6_vassignp: {
       unsigned SrcReg = MI.getOperand(1).getReg();
       unsigned DstReg = MI.getOperand(0).getReg();
@@ -1065,7 +1008,6 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       MBB.erase(MI);
       return true;
     }
-    case Hexagon::V6_lo_128B:
     case Hexagon::V6_lo: {
       unsigned SrcReg = MI.getOperand(1).getReg();
       unsigned DstReg = MI.getOperand(0).getReg();
@@ -1075,7 +1017,6 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       MRI.clearKillFlags(SrcSubLo);
       return true;
     }
-    case Hexagon::V6_hi_128B:
     case Hexagon::V6_hi: {
       unsigned SrcReg = MI.getOperand(1).getReg();
       unsigned DstReg = MI.getOperand(0).getReg();
@@ -1086,25 +1027,14 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       return true;
     }
     case Hexagon::PS_vstorerw_ai:
-    case Hexagon::PS_vstorerwu_ai:
-    case Hexagon::PS_vstorerw_ai_128B:
-    case Hexagon::PS_vstorerwu_ai_128B: {
-      bool Is128B = (Opc == Hexagon::PS_vstorerw_ai_128B ||
-                     Opc == Hexagon::PS_vstorerwu_ai_128B);
-      bool Aligned = (Opc == Hexagon::PS_vstorerw_ai ||
-                      Opc == Hexagon::PS_vstorerw_ai_128B);
+    case Hexagon::PS_vstorerwu_ai: {
+      bool Aligned = Opc == Hexagon::PS_vstorerw_ai;
       unsigned SrcReg = MI.getOperand(2).getReg();
       unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
       unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
-      unsigned NewOpc;
-      if (Aligned)
-        NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
-                        : Hexagon::V6_vS32b_ai;
-      else
-        NewOpc = Is128B ? Hexagon::V6_vS32Ub_ai_128B
-                        : Hexagon::V6_vS32Ub_ai;
+      unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai;
+      unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
 
-      unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
       MachineInstr *MI1New =
           BuildMI(MBB, MI, DL, get(NewOpc))
               .add(MI.getOperand(0))
@@ -1122,23 +1052,12 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       return true;
     }
     case Hexagon::PS_vloadrw_ai:
-    case Hexagon::PS_vloadrwu_ai:
-    case Hexagon::PS_vloadrw_ai_128B:
-    case Hexagon::PS_vloadrwu_ai_128B: {
-      bool Is128B = (Opc == Hexagon::PS_vloadrw_ai_128B ||
-                     Opc == Hexagon::PS_vloadrwu_ai_128B);
-      bool Aligned = (Opc == Hexagon::PS_vloadrw_ai ||
-                      Opc == Hexagon::PS_vloadrw_ai_128B);
-      unsigned NewOpc;
-      if (Aligned)
-        NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B
-                        : Hexagon::V6_vL32b_ai;
-      else
-        NewOpc = Is128B ? Hexagon::V6_vL32Ub_ai_128B
-                        : Hexagon::V6_vL32Ub_ai;
-
+    case Hexagon::PS_vloadrwu_ai: {
+      bool Aligned = Opc == Hexagon::PS_vloadrw_ai;
       unsigned DstReg = MI.getOperand(0).getReg();
-      unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
+      unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai;
+      unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
+
       MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
                                      HRI.getSubReg(DstReg, Hexagon::vsub_lo))
               .add(MI.getOperand(1))
@@ -1248,8 +1167,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       MBB.erase(MI);
       return true;
     }
-    case Hexagon::PS_vselect:
-    case Hexagon::PS_vselect_128B: {
+    case Hexagon::PS_vselect: {
       const MachineOperand &Op0 = MI.getOperand(0);
       const MachineOperand &Op1 = MI.getOperand(1);
       const MachineOperand &Op2 = MI.getOperand(2);
@@ -1283,8 +1201,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       MBB.erase(MI);
       return true;
     }
-    case Hexagon::PS_wselect:
-    case Hexagon::PS_wselect_128B: {
+    case Hexagon::PS_wselect: {
       MachineOperand &Op0 = MI.getOperand(0);
       MachineOperand &Op1 = MI.getOperand(1);
       MachineOperand &Op2 = MI.getOperand(2);
@@ -1325,6 +1242,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       MBB.erase(MI);
       return true;
     }
+
     case Hexagon::PS_tailcall_i:
       MI.setDesc(get(Hexagon::J2_jump));
       return true;
@@ -1350,6 +1268,82 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     case Hexagon::PS_jmpretfnew:
       MI.setDesc(get(Hexagon::J2_jumprfnew));
       return true;
+
+    case Hexagon::V6_vgathermh_pseudo:
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
+          .add(MI.getOperand(1))
+          .add(MI.getOperand(2))
+          .add(MI.getOperand(3));
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
+          .add(MI.getOperand(0))
+          .addImm(0)
+          .addReg(Hexagon::VTMP);
+      MBB.erase(MI);
+      return true;
+
+    case Hexagon::V6_vgathermw_pseudo:
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
+          .add(MI.getOperand(1))
+          .add(MI.getOperand(2))
+          .add(MI.getOperand(3));
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
+          .add(MI.getOperand(0))
+          .addImm(0)
+          .addReg(Hexagon::VTMP);
+      MBB.erase(MI);
+      return true;
+
+    case Hexagon::V6_vgathermhw_pseudo:
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
+          .add(MI.getOperand(1))
+          .add(MI.getOperand(2))
+          .add(MI.getOperand(3));
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
+          .add(MI.getOperand(0))
+          .addImm(0)
+          .addReg(Hexagon::VTMP);
+      MBB.erase(MI);
+      return true;
+
+    case Hexagon::V6_vgathermhq_pseudo:
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
+          .add(MI.getOperand(1))
+          .add(MI.getOperand(2))
+          .add(MI.getOperand(3))
+          .add(MI.getOperand(4));
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
+          .add(MI.getOperand(0))
+          .addImm(0)
+          .addReg(Hexagon::VTMP);
+      MBB.erase(MI);
+      return true;
+
+    case Hexagon::V6_vgathermwq_pseudo:
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
+          .add(MI.getOperand(1))
+          .add(MI.getOperand(2))
+          .add(MI.getOperand(3))
+          .add(MI.getOperand(4));
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
+          .add(MI.getOperand(0))
+          .addImm(0)
+          .addReg(Hexagon::VTMP);
+      MBB.erase(MI);
+      return true;
+
+    case Hexagon::V6_vgathermhwq_pseudo:
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
+          .add(MI.getOperand(1))
+          .add(MI.getOperand(2))
+          .add(MI.getOperand(3))
+          .add(MI.getOperand(4));
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
+          .add(MI.getOperand(0))
+          .addImm(0)
+          .addReg(Hexagon::VTMP);
+      MBB.erase(MI);
+      return true;
+
   }
 
   return false;
@@ -1452,9 +1446,10 @@ bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
   return false;
 }
 
-bool HexagonInstrInfo::DefinesPredicate(
-    MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
-  auto &HRI = getRegisterInfo();
+bool HexagonInstrInfo::DefinesPredicate(MachineInstr &MI,
+      std::vector<MachineOperand> &Pred) const {
+  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
+
   for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
     MachineOperand MO = MI.getOperand(oper);
     if (MO.isReg()) {
@@ -1483,10 +1478,34 @@ bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
     return false;
 
   if (MI.isCall() || isTailCall(MI)) {
-    const MachineFunction &MF = *MI.getParent()->getParent();
-    if (!MF.getSubtarget<HexagonSubtarget>().usePredicatedCalls())
+    if (!Subtarget.usePredicatedCalls())
       return false;
   }
+
+  // HVX loads are not predicable on v60, but are on v62.
+  if (!Subtarget.hasV62TOps()) {
+    switch (MI.getOpcode()) {
+      case Hexagon::V6_vL32b_ai:
+      case Hexagon::V6_vL32b_pi:
+      case Hexagon::V6_vL32b_ppu:
+      case Hexagon::V6_vL32b_cur_ai:
+      case Hexagon::V6_vL32b_cur_pi:
+      case Hexagon::V6_vL32b_cur_ppu:
+      case Hexagon::V6_vL32b_nt_ai:
+      case Hexagon::V6_vL32b_nt_pi:
+      case Hexagon::V6_vL32b_nt_ppu:
+      case Hexagon::V6_vL32b_tmp_ai:
+      case Hexagon::V6_vL32b_tmp_pi:
+      case Hexagon::V6_vL32b_tmp_ppu:
+      case Hexagon::V6_vL32b_nt_cur_ai:
+      case Hexagon::V6_vL32b_nt_cur_pi:
+      case Hexagon::V6_vL32b_nt_cur_ppu:
+      case Hexagon::V6_vL32b_nt_tmp_ai:
+      case Hexagon::V6_vL32b_nt_tmp_pi:
+      case Hexagon::V6_vL32b_nt_tmp_ppu:
+        return false;
+    }
+  }
   return true;
 }
 
@@ -1562,10 +1581,8 @@ unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
 ScheduleHazardRecognizer*
 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
       const InstrItineraryData *II, const ScheduleDAG *DAG) const {
-  if (UseDFAHazardRec) {
-    auto &HST = DAG->MF.getSubtarget<HexagonSubtarget>();
-    return new HexagonHazardRecognizer(II, this, HST);
-  }
+  if (UseDFAHazardRec)
+    return new HexagonHazardRecognizer(II, this, Subtarget);
   return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
 }
 
@@ -1649,10 +1666,14 @@ bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
     case Hexagon::A4_cmpbgtui:
     case Hexagon::A4_cmpheqi:
     case Hexagon::A4_cmphgti:
-    case Hexagon::A4_cmphgtui:
+    case Hexagon::A4_cmphgtui: {
       SrcReg2 = 0;
+      const MachineOperand &Op2 = MI.getOperand(2);
+      if (!Op2.isImm())
+        return false;
       Value = MI.getOperand(2).getImm();
       return true;
+    }
   }
 
   return false;
@@ -1664,7 +1685,6 @@ unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
   return getInstrTimingClassLatency(ItinData, MI);
 }
 
-
 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
     const TargetSubtargetInfo &STI) const {
   const InstrItineraryData *II = STI.getInstrItineraryData();
@@ -1672,14 +1692,11 @@ DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
 }
 
 // Inspired by this pair:
-//  %R13<def> = L2_loadri_io %R29, 136; mem:LD4[FixedStack0]
-//  S2_storeri_io %R29, 132, %R1<kill>; flags:  mem:ST4[FixedStack1]
+//  %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
+//  S2_storeri_io %r29, 132, killed %r1; flags:  mem:ST4[FixedStack1]
 // Currently AA considers the addresses in these instructions to be aliasing.
 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
     MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
-  int OffsetA = 0, OffsetB = 0;
-  unsigned SizeA = 0, SizeB = 0;
-
   if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
       MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
     return false;
@@ -1689,27 +1706,47 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
   if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
     return true;
 
-  // Get base, offset, and access size in MIa.
-  unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA);
-  if (!BaseRegA || !SizeA)
+  // Get the base register in MIa.
+  unsigned BasePosA, OffsetPosA;
+  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
     return false;
+  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
+  unsigned BaseRegA = BaseA.getReg();
+  unsigned BaseSubA = BaseA.getSubReg();
 
-  // Get base, offset, and access size in MIb.
-  unsigned BaseRegB = getBaseAndOffset(MIb, OffsetB, SizeB);
-  if (!BaseRegB || !SizeB)
+  // Get the base register in MIb.
+  unsigned BasePosB, OffsetPosB;
+  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
     return false;
+  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
+  unsigned BaseRegB = BaseB.getReg();
+  unsigned BaseSubB = BaseB.getSubReg();
+
+  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
+    return false;
+
+  // Get the access sizes.
+  unsigned SizeA = getMemAccessSize(MIa);
+  unsigned SizeB = getMemAccessSize(MIb);
 
-  if (BaseRegA != BaseRegB)
+  // Get the offsets. Handle immediates only for now.
+  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
+  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
+  if (!MIa.getOperand(OffsetPosA).isImm() ||
+      !MIb.getOperand(OffsetPosB).isImm())
     return false;
+  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
+  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
 
   // This is a mem access with the same base register and known offsets from it.
   // Reason about it.
   if (OffsetA > OffsetB) {
-    uint64_t offDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
-    return (SizeB <= offDiff);
-  } else if (OffsetA < OffsetB) {
-    uint64_t offDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
-    return (SizeA <= offDiff);
+    uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
+    return SizeB <= OffDiff;
+  }
+  if (OffsetA < OffsetB) {
+    uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
+    return SizeA <= OffDiff;
   }
 
   return false;
@@ -1719,12 +1756,20 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
       int &Value) const {
   if (isPostIncrement(MI)) {
-    unsigned AccessSize;
-    return getBaseAndOffset(MI, Value, AccessSize);
-  }
-  if (MI.getOpcode() == Hexagon::A2_addi) {
-    Value = MI.getOperand(2).getImm();
-    return true;
+    unsigned BasePos = 0, OffsetPos = 0;
+    if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
+      return false;
+    const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
+    if (OffsetOp.isImm()) {
+      Value = OffsetOp.getImm();
+      return true;
+    }
+  } else if (MI.getOpcode() == Hexagon::A2_addi) {
+    const MachineOperand &AddOp = MI.getOperand(2);
+    if (AddOp.isImm()) {
+      Value = AddOp.getImm();
+      return true;
+    }
   }
 
   return false;
@@ -1739,6 +1784,7 @@ HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
 ArrayRef<std::pair<unsigned, const char*>>
 HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
   using namespace HexagonII;
+
   static const std::pair<unsigned, const char*> Flags[] = {
     {MO_PCREL,  "hexagon-pcrel"},
     {MO_GOT,    "hexagon-got"},
@@ -1757,6 +1803,7 @@ HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
 ArrayRef<std::pair<unsigned, const char*>>
 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
   using namespace HexagonII;
+
   static const std::pair<unsigned, const char*> Flags[] = {
     {HMOTF_ConstExtended, "hexagon-ext"}
   };
@@ -1790,23 +1837,11 @@ bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
 }
 
 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
-  const MachineFunction *MF = MI.getParent()->getParent();
-  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
-  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
-
-  if (!(isTC1(MI))
-      && !(QII->isTC2Early(MI))
-      && !(MI.getDesc().mayLoad())
-      && !(MI.getDesc().mayStore())
-      && (MI.getDesc().getOpcode() != Hexagon::S2_allocframe)
-      && (MI.getDesc().getOpcode() != Hexagon::L2_deallocframe)
-      && !(QII->isMemOp(MI))
-      && !(MI.isBranch())
-      && !(MI.isReturn())
-      && !MI.isCall())
-    return true;
-
-  return false;
+  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
+         !MI.getDesc().mayStore() &&
+         MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
+         MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
+         !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
 }
 
 // Return true if the instruction is a compund branch instruction.
@@ -1861,13 +1896,13 @@ bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
 
 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
-  case Hexagon::L4_return :
-  case Hexagon::L4_return_t :
-  case Hexagon::L4_return_f :
-  case Hexagon::L4_return_tnew_pnt :
-  case Hexagon::L4_return_fnew_pnt :
-  case Hexagon::L4_return_tnew_pt :
-  case Hexagon::L4_return_fnew_pt :
+  case Hexagon::L4_return:
+  case Hexagon::L4_return_t:
+  case Hexagon::L4_return_f:
+  case Hexagon::L4_return_tnew_pnt:
+  case Hexagon::L4_return_fnew_pnt:
+  case Hexagon::L4_return_tnew_pt:
+  case Hexagon::L4_return_fnew_pt:
     return true;
   }
   return false;
@@ -1878,8 +1913,7 @@ bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
       const MachineInstr &ConsMI) const {
   if (!ProdMI.getDesc().getNumDefs())
     return false;
-
-  auto &HRI = getRegisterInfo();
+  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
 
   SmallVector<unsigned, 4> DefsA;
   SmallVector<unsigned, 4> DefsB;
@@ -1914,8 +1948,6 @@ bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   case Hexagon::V6_vL32b_cur_pi:
   case Hexagon::V6_vL32b_cur_ai:
-  case Hexagon::V6_vL32b_cur_pi_128B:
-  case Hexagon::V6_vL32b_cur_ai_128B:
     return true;
   }
   return false;
@@ -2019,10 +2051,10 @@ bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
 
 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
-  case Hexagon::J2_callr :
-  case Hexagon::J2_callrf :
-  case Hexagon::J2_callrt :
-  case Hexagon::PS_call_nr :
+  case Hexagon::J2_callr:
+  case Hexagon::J2_callrf:
+  case Hexagon::J2_callrt:
+  case Hexagon::PS_call_nr:
     return true;
   }
   return false;
@@ -2030,13 +2062,13 @@ bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
 
 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
-  case Hexagon::L4_return :
-  case Hexagon::L4_return_t :
-  case Hexagon::L4_return_f :
-  case Hexagon::L4_return_fnew_pnt :
-  case Hexagon::L4_return_fnew_pt :
-  case Hexagon::L4_return_tnew_pnt :
-  case Hexagon::L4_return_tnew_pt :
+  case Hexagon::L4_return:
+  case Hexagon::L4_return_t:
+  case Hexagon::L4_return_f:
+  case Hexagon::L4_return_fnew_pnt:
+  case Hexagon::L4_return_fnew_pt:
+  case Hexagon::L4_return_tnew_pnt:
+  case Hexagon::L4_return_tnew_pt:
     return true;
   }
   return false;
@@ -2044,13 +2076,13 @@ bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
 
 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
-  case Hexagon::J2_jumpr :
-  case Hexagon::J2_jumprt :
-  case Hexagon::J2_jumprf :
-  case Hexagon::J2_jumprtnewpt :
-  case Hexagon::J2_jumprfnewpt  :
-  case Hexagon::J2_jumprtnew :
-  case Hexagon::J2_jumprfnew :
+  case Hexagon::J2_jumpr:
+  case Hexagon::J2_jumprt:
+  case Hexagon::J2_jumprf:
+  case Hexagon::J2_jumprtnewpt:
+  case Hexagon::J2_jumprfnewpt:
+  case Hexagon::J2_jumprtnew:
+  case Hexagon::J2_jumprfnew:
     return true;
   }
   return false;
@@ -2096,6 +2128,8 @@ bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
   // TODO: Add all the compound branches here. Can we do this in Relation model?
   case Hexagon::J4_cmpeqi_tp0_jump_nt:
   case Hexagon::J4_cmpeqi_tp1_jump_nt:
+  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
+  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
     return isInt<11>(offset);
   }
 }
@@ -2158,24 +2192,24 @@ bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
     default: return false;
-    case Hexagon::L4_iadd_memopw_io :
-    case Hexagon::L4_isub_memopw_io :
-    case Hexagon::L4_add_memopw_io :
-    case Hexagon::L4_sub_memopw_io :
-    case Hexagon::L4_and_memopw_io :
-    case Hexagon::L4_or_memopw_io :
-    case Hexagon::L4_iadd_memoph_io :
-    case Hexagon::L4_isub_memoph_io :
-    case Hexagon::L4_add_memoph_io :
-    case Hexagon::L4_sub_memoph_io :
-    case Hexagon::L4_and_memoph_io :
-    case Hexagon::L4_or_memoph_io :
-    case Hexagon::L4_iadd_memopb_io :
-    case Hexagon::L4_isub_memopb_io :
-    case Hexagon::L4_add_memopb_io :
-    case Hexagon::L4_sub_memopb_io :
-    case Hexagon::L4_and_memopb_io :
-    case Hexagon::L4_or_memopb_io :
+    case Hexagon::L4_iadd_memopw_io:
+    case Hexagon::L4_isub_memopw_io:
+    case Hexagon::L4_add_memopw_io:
+    case Hexagon::L4_sub_memopw_io:
+    case Hexagon::L4_and_memopw_io:
+    case Hexagon::L4_or_memopw_io:
+    case Hexagon::L4_iadd_memoph_io:
+    case Hexagon::L4_isub_memoph_io:
+    case Hexagon::L4_add_memoph_io:
+    case Hexagon::L4_sub_memoph_io:
+    case Hexagon::L4_and_memoph_io:
+    case Hexagon::L4_or_memoph_io:
+    case Hexagon::L4_iadd_memopb_io:
+    case Hexagon::L4_isub_memopb_io:
+    case Hexagon::L4_add_memopb_io:
+    case Hexagon::L4_sub_memopb_io:
+    case Hexagon::L4_and_memopb_io:
+    case Hexagon::L4_or_memopb_io:
     case Hexagon::L4_ior_memopb_io:
     case Hexagon::L4_ior_memoph_io:
     case Hexagon::L4_ior_memopw_io:
@@ -2362,8 +2396,8 @@ bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
 
 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
-  case Hexagon::STriw_pred :
-  case Hexagon::LDriw_pred :
+  case Hexagon::STriw_pred:
+  case Hexagon::LDriw_pred:
     return true;
   default:
     return false;
@@ -2426,45 +2460,38 @@ bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {
 }
 
 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
-//
-bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const {
-  if (VT == MVT::v16i32 || VT == MVT::v8i64 ||
-      VT == MVT::v32i16 || VT == MVT::v64i8) {
-      return (Offset >= Hexagon_MEMV_AUTOINC_MIN &&
-              Offset <= Hexagon_MEMV_AUTOINC_MAX &&
-              (Offset & 0x3f) == 0);
-  }
-  // 128B
-  if (VT == MVT::v32i32 || VT == MVT::v16i64 ||
-      VT == MVT::v64i16 || VT == MVT::v128i8) {
-      return (Offset >= Hexagon_MEMV_AUTOINC_MIN_128B &&
-              Offset <= Hexagon_MEMV_AUTOINC_MAX_128B &&
-              (Offset & 0x7f) == 0);
-  }
-  if (VT == MVT::i64) {
-      return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
-              Offset <= Hexagon_MEMD_AUTOINC_MAX &&
-              (Offset & 0x7) == 0);
-  }
-  if (VT == MVT::i32) {
-      return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
-              Offset <= Hexagon_MEMW_AUTOINC_MAX &&
-              (Offset & 0x3) == 0);
-  }
-  if (VT == MVT::i16) {
-      return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
-              Offset <= Hexagon_MEMH_AUTOINC_MAX &&
-              (Offset & 0x1) == 0);
-  }
-  if (VT == MVT::i8) {
-      return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
-              Offset <= Hexagon_MEMB_AUTOINC_MAX);
+bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
+  int Size = VT.getSizeInBits() / 8;
+  if (Offset % Size != 0)
+    return false;
+  int Count = Offset / Size;
+
+  switch (VT.getSimpleVT().SimpleTy) {
+    // For scalars the auto-inc is s4
+    case MVT::i8:
+    case MVT::i16:
+    case MVT::i32:
+    case MVT::i64:
+      return isInt<4>(Count);
+    // For HVX vectors the auto-inc is s3
+    case MVT::v64i8:
+    case MVT::v32i16:
+    case MVT::v16i32:
+    case MVT::v8i64:
+    case MVT::v128i8:
+    case MVT::v64i16:
+    case MVT::v32i32:
+    case MVT::v16i64:
+      return isInt<3>(Count);
+    default:
+      break;
   }
-  llvm_unreachable("Not an auto-inc opc!");
+
+  llvm_unreachable("Not an valid type!");
 }
 
 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
-      bool Extend) const {
+      const TargetRegisterInfo *TRI, bool Extend) const {
   // This function is to check whether the "Offset" is in the correct range of
   // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
   // inserted to calculate the final address. Due to this reason, the function
@@ -2473,7 +2500,6 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
   // there are cases where a misaligned pointer recast can cause this
   // problem, and we need to allow for it. The front end warns of such
   // misaligns with respect to load size.
-
   switch (Opcode) {
   case Hexagon::PS_vstorerq_ai:
   case Hexagon::PS_vstorerw_ai:
@@ -2486,22 +2512,13 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
   case Hexagon::V6_vL32b_nt_ai:
   case Hexagon::V6_vS32b_nt_ai:
   case Hexagon::V6_vL32Ub_ai:
-  case Hexagon::V6_vS32Ub_ai:
-    return isShiftedInt<4,6>(Offset);
-
-  case Hexagon::PS_vstorerq_ai_128B:
-  case Hexagon::PS_vstorerw_ai_128B:
-  case Hexagon::PS_vstorerw_nt_ai_128B:
-  case Hexagon::PS_vloadrq_ai_128B:
-  case Hexagon::PS_vloadrw_ai_128B:
-  case Hexagon::PS_vloadrw_nt_ai_128B:
-  case Hexagon::V6_vL32b_ai_128B:
-  case Hexagon::V6_vS32b_ai_128B:
-  case Hexagon::V6_vL32b_nt_ai_128B:
-  case Hexagon::V6_vS32b_nt_ai_128B:
-  case Hexagon::V6_vL32Ub_ai_128B:
-  case Hexagon::V6_vS32Ub_ai_128B:
-    return isShiftedInt<4,7>(Offset);
+  case Hexagon::V6_vS32Ub_ai: {
+    unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
+    assert(isPowerOf2_32(VectorSize));
+    if (Offset & (VectorSize-1))
+      return false;
+    return isInt<4>(Offset >> Log2_32(VectorSize));
+  }
 
   case Hexagon::J2_loop0i:
   case Hexagon::J2_loop1i:
@@ -2554,28 +2571,28 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
     return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
       (Offset <= Hexagon_ADDI_OFFSET_MAX);
 
-  case Hexagon::L4_iadd_memopw_io :
-  case Hexagon::L4_isub_memopw_io :
-  case Hexagon::L4_add_memopw_io :
-  case Hexagon::L4_sub_memopw_io :
-  case Hexagon::L4_and_memopw_io :
-  case Hexagon::L4_or_memopw_io :
+  case Hexagon::L4_iadd_memopw_io:
+  case Hexagon::L4_isub_memopw_io:
+  case Hexagon::L4_add_memopw_io:
+  case Hexagon::L4_sub_memopw_io:
+  case Hexagon::L4_and_memopw_io:
+  case Hexagon::L4_or_memopw_io:
     return (0 <= Offset && Offset <= 255);
 
-  case Hexagon::L4_iadd_memoph_io :
-  case Hexagon::L4_isub_memoph_io :
-  case Hexagon::L4_add_memoph_io :
-  case Hexagon::L4_sub_memoph_io :
-  case Hexagon::L4_and_memoph_io :
-  case Hexagon::L4_or_memoph_io :
+  case Hexagon::L4_iadd_memoph_io:
+  case Hexagon::L4_isub_memoph_io:
+  case Hexagon::L4_add_memoph_io:
+  case Hexagon::L4_sub_memoph_io:
+  case Hexagon::L4_and_memoph_io:
+  case Hexagon::L4_or_memoph_io:
     return (0 <= Offset && Offset <= 127);
 
-  case Hexagon::L4_iadd_memopb_io :
-  case Hexagon::L4_isub_memopb_io :
-  case Hexagon::L4_add_memopb_io :
-  case Hexagon::L4_sub_memopb_io :
-  case Hexagon::L4_and_memopb_io :
-  case Hexagon::L4_or_memopb_io :
+  case Hexagon::L4_iadd_memopb_io:
+  case Hexagon::L4_isub_memopb_io:
+  case Hexagon::L4_add_memopb_io:
+  case Hexagon::L4_sub_memopb_io:
+  case Hexagon::L4_and_memopb_io:
+  case Hexagon::L4_or_memopb_io:
     return (0 <= Offset && Offset <= 63);
 
   // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
@@ -2799,19 +2816,19 @@ bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
     // Check addressing mode and retrieve non-ext equivalent instruction.
 
     switch (getAddrMode(MI)) {
-    case HexagonII::Absolute :
+    case HexagonII::Absolute:
       // Load/store with absolute addressing mode can be converted into
       // base+offset mode.
-      NonExtOpcode = Hexagon::getBaseWithImmOffset(MI.getOpcode());
+      NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
       break;
-    case HexagonII::BaseImmOffset :
+    case HexagonII::BaseImmOffset:
       // Load/store with base+offset addressing mode can be converted into
       // base+register offset addressing mode. However left shift operand should
       // be set to 0.
-      NonExtOpcode = Hexagon::getBaseWithRegOffset(MI.getOpcode());
+      NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
       break;
     case HexagonII::BaseLongOffset:
-      NonExtOpcode = Hexagon::getRegShlForm(MI.getOpcode());
+      NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
       break;
     default:
       return false;
@@ -2841,10 +2858,9 @@ bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
 
 // Returns true, if a LD insn can be promoted to a cur load.
 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
-  auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>();
   const uint64_t F = MI.getDesc().TSFlags;
   return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
-         HST.hasV60TOps();
+         Subtarget.hasV60TOps();
 }
 
 // Returns true, if a ST insn can be promoted to a new-value store.
@@ -2880,10 +2896,8 @@ bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
   MachineBasicBlock::const_instr_iterator MII = BII;
   MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
 
-  if (!(*MII).isBundle()) {
-    const MachineInstr &J = *MII;
-    return producesStall(J, MI);
-  }
+  if (!MII->isBundle())
+    return producesStall(*MII, MI);
 
   for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
     const MachineInstr &J = *MII;
@@ -2926,10 +2940,6 @@ bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
   return !isPredicatedTrue(Cond[0].getImm());
 }
 
-short HexagonInstrInfo::getAbsoluteForm(const MachineInstr &MI) const {
-  return Hexagon::getAbsoluteForm(MI.getOpcode());
-}
-
 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
   const uint64_t F = MI.getDesc().TSFlags;
   return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
@@ -2937,6 +2947,8 @@ unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
 
 // Returns the base register in a memory access (load/store). The offset is
 // returned in Offset and the access size is returned in AccessSize.
+// If the base register has a subregister or the offset field does not contain
+// an immediate value, return 0.
 unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
       int &Offset, unsigned &AccessSize) const {
   // Return if it is not a base+offset type instruction or a MemOp.
@@ -2945,35 +2957,35 @@ unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
       !isMemOp(MI) && !isPostIncrement(MI))
     return 0;
 
-  // Since it is a memory access instruction, getMemAccessSize() should never
-  // return 0.
-  assert (getMemAccessSize(MI) &&
-          "BaseImmOffset or BaseLongOffset or MemOp without accessSize");
-
-  // Return Values of getMemAccessSize() are
-  // 0 - Checked in the assert above.
-  // 1, 2, 3, 4 & 7, 8 - The statement below is correct for all these.
-  // MemAccessSize is represented as 1+log2(N) where N is size in bits.
-  AccessSize = (1U << (getMemAccessSize(MI) - 1));
+  AccessSize = getMemAccessSize(MI);
 
-  unsigned basePos = 0, offsetPos = 0;
-  if (!getBaseAndOffsetPosition(MI, basePos, offsetPos))
+  unsigned BasePos = 0, OffsetPos = 0;
+  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
     return 0;
 
   // Post increment updates its EA after the mem access,
   // so we need to treat its offset as zero.
-  if (isPostIncrement(MI))
+  if (isPostIncrement(MI)) {
     Offset = 0;
-  else {
-    Offset = MI.getOperand(offsetPos).getImm();
+  } else {
+    const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
+    if (!OffsetOp.isImm())
+      return 0;
+    Offset = OffsetOp.getImm();
   }
 
-  return MI.getOperand(basePos).getReg();
+  const MachineOperand &BaseOp = MI.getOperand(BasePos);
+  if (BaseOp.getSubReg() != 0)
+    return 0;
+  return BaseOp.getReg();
 }
 
 /// Return the position of the base and offset operands for this instruction.
 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
       unsigned &BasePos, unsigned &OffsetPos) const {
+  if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
+    return false;
+
   // Deal with memops first.
   if (isMemOp(MI)) {
     BasePos = 0;
@@ -3063,20 +3075,6 @@ SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
   return Jumpers;
 }
 
-short HexagonInstrInfo::getBaseWithLongOffset(short Opcode) const {
-  if (Opcode < 0)
-    return -1;
-  return Hexagon::getBaseWithLongOffset(Opcode);
-}
-
-short HexagonInstrInfo::getBaseWithLongOffset(const MachineInstr &MI) const {
-  return Hexagon::getBaseWithLongOffset(MI.getOpcode());
-}
-
-short HexagonInstrInfo::getBaseWithRegOffset(const MachineInstr &MI) const {
-  return Hexagon::getBaseWithRegOffset(MI.getOpcode());
-}
-
 // Returns Operand Index for the constant extended instruction.
 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
   const uint64_t F = MI.getDesc().TSFlags;
@@ -3167,7 +3165,6 @@ HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
   case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
   case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
     return HexagonII::HCG_C;
-    break;
   }
 
   return HexagonII::HCG_None;
@@ -3180,15 +3177,24 @@ unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
   assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
   if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
       (GB.getOpcode() != Hexagon::J2_jumptnew))
-    return -1;
+    return -1u;
   unsigned DestReg = GA.getOperand(0).getReg();
   if (!GB.readsRegister(DestReg))
-    return -1;
-  if (DestReg == Hexagon::P0)
-    return Hexagon::J4_cmpeqi_tp0_jump_nt;
-  if (DestReg == Hexagon::P1)
-    return Hexagon::J4_cmpeqi_tp1_jump_nt;
-  return -1;
+    return -1u;
+  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
+    return -1u;
+  // The value compared against must be either u5 or -1.
+  const MachineOperand &CmpOp = GA.getOperand(2);
+  if (!CmpOp.isImm())
+    return -1u;
+  int V = CmpOp.getImm();
+  if (V == -1)
+    return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
+                                  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
+  if (!isUInt<5>(V))
+    return -1u;
+  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
+                                : Hexagon::J4_cmpeqi_tp1_jump_nt;
 }
 
 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
@@ -3214,15 +3220,6 @@ int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
     return Hexagon::V6_vL32b_nt_cur_pi;
   case Hexagon::V6_vL32b_nt_ai:
     return Hexagon::V6_vL32b_nt_cur_ai;
-  //128B
-  case Hexagon::V6_vL32b_pi_128B:
-    return Hexagon::V6_vL32b_cur_pi_128B;
-  case Hexagon::V6_vL32b_ai_128B:
-    return Hexagon::V6_vL32b_cur_ai_128B;
-  case Hexagon::V6_vL32b_nt_pi_128B:
-    return Hexagon::V6_vL32b_nt_cur_pi_128B;
-  case Hexagon::V6_vL32b_nt_ai_128B:
-    return Hexagon::V6_vL32b_nt_cur_ai_128B;
   }
   return 0;
 }
@@ -3239,20 +3236,10 @@ int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {
     return Hexagon::V6_vL32b_nt_pi;
   case Hexagon::V6_vL32b_nt_cur_ai:
     return Hexagon::V6_vL32b_nt_ai;
-  //128B
-  case Hexagon::V6_vL32b_cur_pi_128B:
-    return Hexagon::V6_vL32b_pi_128B;
-  case Hexagon::V6_vL32b_cur_ai_128B:
-    return Hexagon::V6_vL32b_ai_128B;
-  case Hexagon::V6_vL32b_nt_cur_pi_128B:
-    return Hexagon::V6_vL32b_nt_pi_128B;
-  case Hexagon::V6_vL32b_nt_cur_ai_128B:
-    return Hexagon::V6_vL32b_nt_ai_128B;
   }
   return 0;
 }
 
-
 // The diagram below shows the steps involved in the conversion of a predicated
 // store instruction to its .new predicated new-value form.
 //
@@ -3342,8 +3329,8 @@ int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
 
   switch (MI.getOpcode()) {
   default:
-    llvm::report_fatal_error(std::string("Unknown .new type: ") +
-      std::to_string(MI.getOpcode()).c_str());
+    report_fatal_error(std::string("Unknown .new type: ") +
+      std::to_string(MI.getOpcode()));
   case Hexagon::S4_storerb_ur:
     return Hexagon::S4_storerbnew_ur;
 
@@ -3367,13 +3354,6 @@ int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
 
   case Hexagon::V6_vS32b_pi:
     return Hexagon::V6_vS32b_new_pi;
-
-  // 128B
-  case Hexagon::V6_vS32b_ai_128B:
-    return Hexagon::V6_vS32b_new_ai_128B;
-
-  case Hexagon::V6_vS32b_pi_128B:
-    return Hexagon::V6_vS32b_new_pi_128B;
   }
   return 0;
 }
@@ -3485,15 +3465,13 @@ int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
 }
 
 int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
-  const MachineFunction &MF = *MI.getParent()->getParent();
-  const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
   int NewOp = MI.getOpcode();
   if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
     NewOp = Hexagon::getPredOldOpcode(NewOp);
     // All Hexagon architectures have prediction bits on dot-new branches,
     // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
     // to pick the right opcode when converting back to dot-old.
-    if (!HST.getFeatureBits()[Hexagon::ArchV60]) {
+    if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
       switch (NewOp) {
       case Hexagon::J2_jumptpt:
         NewOp = Hexagon::J2_jumpt;
@@ -3518,7 +3496,7 @@ int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
     assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
   }
 
-  if (HST.hasV60TOps())
+  if (Subtarget.hasV60TOps())
     return NewOp;
 
   // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
@@ -3540,7 +3518,7 @@ int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
       const MachineInstr &MI) const {
   unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
-  auto &HRI = getRegisterInfo();
+  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
 
   switch (MI.getOpcode()) {
   default:
@@ -3625,8 +3603,9 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
     return HexagonII::HSIG_L2;
   case Hexagon::EH_RETURN_JMPR:
   case Hexagon::PS_jmpret:
+  case Hexagon::SL2_jumpr31:
     // jumpr r31
-    // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
+    // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
     DstReg = MI.getOperand(0).getReg();
     if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
       return HexagonII::HSIG_L2;
@@ -3637,6 +3616,9 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
   case Hexagon::PS_jmpretfnewpt:
   case Hexagon::PS_jmprettnew:
   case Hexagon::PS_jmpretfnew:
+  case Hexagon::SL2_jumpr31_t:
+  case Hexagon::SL2_jumpr31_f:
+  case Hexagon::SL2_jumpr31_tnew:
     DstReg = MI.getOperand(1).getReg();
     SrcReg = MI.getOperand(0).getReg();
     // [if ([!]p0[.new])] jumpr r31
@@ -3645,12 +3627,12 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
         (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
       return HexagonII::HSIG_L2;
     break;
-  case Hexagon::L4_return_t :
-  case Hexagon::L4_return_f :
-  case Hexagon::L4_return_tnew_pnt :
-  case Hexagon::L4_return_fnew_pnt :
-  case Hexagon::L4_return_tnew_pt :
-  case Hexagon::L4_return_fnew_pt :
+  case Hexagon::L4_return_t:
+  case Hexagon::L4_return_f:
+  case Hexagon::L4_return_tnew_pnt:
+  case Hexagon::L4_return_fnew_pnt:
+  case Hexagon::L4_return_tnew_pt:
+  case Hexagon::L4_return_fnew_pt:
     // [if ([!]p0[.new])] dealloc_return
     SrcReg = MI.getOperand(0).getReg();
     if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
@@ -3730,8 +3712,8 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
       return HexagonII::HSIG_S2;
     break;
   case Hexagon::S2_allocframe:
-    if (MI.getOperand(0).isImm() &&
-        isShiftedUInt<5,3>(MI.getOperand(0).getImm()))
+    if (MI.getOperand(2).isImm() &&
+        isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
       return HexagonII::HSIG_S1;
     break;
   //
@@ -3816,7 +3798,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
   case Hexagon::C2_cmovenewif:
     // if ([!]P0[.new]) Rd = #0
     // Actual form:
-    // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
+    // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
     DstReg = MI.getOperand(0).getReg();
     SrcReg = MI.getOperand(1).getReg();
     if (isIntRegForSubInst(DstReg) &&
@@ -3908,14 +3890,15 @@ int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
                                         unsigned DefIdx,
                                         const MachineInstr &UseMI,
                                         unsigned UseIdx) const {
-  auto &RI = getRegisterInfo();
+  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
+
   // Get DefIdx and UseIdx for super registers.
   MachineOperand DefMO = DefMI.getOperand(DefIdx);
 
-  if (RI.isPhysicalRegister(DefMO.getReg())) {
+  if (HRI.isPhysicalRegister(DefMO.getReg())) {
     if (DefMO.isImplicit()) {
-      for (MCSuperRegIterator SR(DefMO.getReg(), &RI); SR.isValid(); ++SR) {
-        int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &RI);
+      for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
+        int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
         if (Idx != -1) {
           DefIdx = Idx;
           break;
@@ -3925,8 +3908,8 @@ int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
 
     MachineOperand UseMO = UseMI.getOperand(UseIdx);
     if (UseMO.isImplicit()) {
-      for (MCSuperRegIterator SR(UseMO.getReg(), &RI); SR.isValid(); ++SR) {
-        int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &RI);
+      for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
+        int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
         if (Idx != -1) {
           UseIdx = Idx;
           break;
@@ -3935,8 +3918,14 @@ int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
     }
   }
 
-  return TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
-                                            UseMI, UseIdx);
+  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
+                                                   UseMI, UseIdx);
+  if (!Latency)
+    // We should never have 0 cycle latency between two instructions unless
+    // they can be packetized together. However, this decision can't be made
+    // here.
+    Latency = 1;
+  return Latency;
 }
 
 // inverts the predication logic.
@@ -3975,9 +3964,52 @@ int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
     return ~(-1U << bits);
 }
 
+
+bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const {
+  switch (MI.getOpcode()) {
+  case Hexagon::L2_loadrbgp:
+  case Hexagon::L2_loadrdgp:
+  case Hexagon::L2_loadrhgp:
+  case Hexagon::L2_loadrigp:
+  case Hexagon::L2_loadrubgp:
+  case Hexagon::L2_loadruhgp:
+  case Hexagon::S2_storerbgp:
+  case Hexagon::S2_storerbnewgp:
+  case Hexagon::S2_storerhgp:
+  case Hexagon::S2_storerhnewgp:
+  case Hexagon::S2_storerigp:
+  case Hexagon::S2_storerinewgp:
+  case Hexagon::S2_storerdgp:
+  case Hexagon::S2_storerfgp:
+    return true;
+  }
+  const uint64_t F = MI.getDesc().TSFlags;
+  unsigned addrMode =
+    ((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
+  // Disallow any base+offset instruction. The assembler does not yet reorder
+  // based up any zero offset instruction.
+  return (addrMode == HexagonII::BaseRegOffset ||
+          addrMode == HexagonII::BaseImmOffset ||
+          addrMode == HexagonII::BaseLongOffset);
+}
+
 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
+  using namespace HexagonII;
+
   const uint64_t F = MI.getDesc().TSFlags;
-  return (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
+  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
+  unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
+  if (Size != 0)
+    return Size;
+
+  // Handle vector access sizes.
+  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
+  switch (S) {
+    case HexagonII::HVXVectorAccess:
+      return HRI.getSpillSize(Hexagon::HvxVRRegClass);
+    default:
+      llvm_unreachable("Unexpected instruction");
+  }
 }
 
 // Returns the min value that doesn't need to be extended.
@@ -4005,12 +4037,12 @@ short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
   if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
     // Check addressing mode and retrieve non-ext equivalent instruction.
     switch (getAddrMode(MI)) {
-    case HexagonII::Absolute :
-      return Hexagon::getBaseWithImmOffset(MI.getOpcode());
-    case HexagonII::BaseImmOffset :
-      return Hexagon::getBaseWithRegOffset(MI.getOpcode());
+    case HexagonII::Absolute:
+      return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
+    case HexagonII::BaseImmOffset:
+      return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
     case HexagonII::BaseLongOffset:
-      return Hexagon::getRegShlForm(MI.getOpcode());
+      return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
 
     default:
       return -1;
@@ -4091,8 +4123,7 @@ uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
 }
 
 unsigned HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
-  const TargetSubtargetInfo &ST = MI.getParent()->getParent()->getSubtarget();
-  const InstrItineraryData &II = *ST.getInstrItineraryData();
+  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
   const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
 
   return IS.getUnits();
@@ -4128,8 +4159,9 @@ void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
 
 bool HexagonInstrInfo::invertAndChangeJumpTarget(
       MachineInstr &MI, MachineBasicBlock *NewTarget) const {
-  DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
-               << NewTarget->getNumber(); MI.dump(););
+  DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
+               << printMBBReference(*NewTarget);
+        MI.dump(););
   assert(MI.isBranch());
   unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
   int TargetPos = MI.getNumOperands() - 1;
@@ -4190,6 +4222,51 @@ bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
   return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
 }
 
-short HexagonInstrInfo::xformRegToImmOffset(const MachineInstr &MI) const {
-  return Hexagon::xformRegToImmOffset(MI.getOpcode());
+void HexagonInstrInfo::
+setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const {
+  assert(MIB->isBundle());
+  MachineOperand &Operand = MIB->getOperand(0);
+  if (Operand.isImm())
+    Operand.setImm(Operand.getImm() | memShufDisabledMask);
+  else
+    MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
+}
+
+bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {
+  assert(MIB.isBundle());
+  const MachineOperand &Operand = MIB.getOperand(0);
+  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
+}
+
+// Addressing mode relations.
+short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {
+  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
+}
+
+short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const {
+  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
+}
+
+short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const {
+  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
+}
+
+short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const {
+  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
+}
+
+short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const {
+  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
+}
+
+short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const {
+  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
+}
+
+short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const {
+  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
+}
+
+short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const {
+  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
 }
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h
index 0436ce3ac475..4530d3b999cc 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -14,14 +14,13 @@
 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
 
-#include "HexagonRegisterInfo.h"
 #include "MCTargetDesc/HexagonBaseInfo.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
 #include "llvm/CodeGen/MachineValueType.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/ValueTypes.h"
 #include <cstdint>
 #include <vector>
 
@@ -30,11 +29,19 @@
 
 namespace llvm {
 
-struct EVT;
 class HexagonSubtarget;
+class MachineBranchProbabilityInfo;
+class MachineFunction;
+class MachineInstr;
+class MachineOperand;
+class TargetRegisterInfo;
 
 class HexagonInstrInfo : public HexagonGenInstrInfo {
-  const HexagonRegisterInfo RI;
+  const HexagonSubtarget &Subtarget;
+
+  enum BundleAttribute {
+    memShufDisabledMask = 0x4
+  };
 
   virtual void anchor();
 
@@ -42,7 +49,6 @@ public:
   explicit HexagonInstrInfo(HexagonSubtarget &ST);
 
   /// TargetInstrInfo overrides.
-  ///
 
   /// If the specified machine instruction is a direct
   /// load from a stack slot, return the virtual or physical register number of
@@ -84,7 +90,6 @@ public:
   ///
   /// If AllowModify is true, then this routine is allowed to modify the basic
   /// block (e.g. delete instructions after the unconditional branch).
-  ///
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
@@ -251,7 +256,7 @@ public:
   /// Allocate and return a hazard recognizer to use for this target when
   /// scheduling the machine instructions after register allocation.
   ScheduleHazardRecognizer*
-  CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
+  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
                                      const ScheduleDAG *DAG) const override;
 
   /// For a comparison instruction, return the source registers
@@ -325,14 +330,12 @@ public:
   bool isTailCall(const MachineInstr &MI) const override;
 
   /// HexagonInstrInfo specifics.
-  ///
 
-  const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
-
-  unsigned createVR(MachineFunction* MF, MVT VT) const;
+  unsigned createVR(MachineFunction *MF, MVT VT) const;
 
   bool isAbsoluteSet(const MachineInstr &MI) const;
   bool isAccumulator(const MachineInstr &MI) const;
+  bool isAddrModeWithOffset(const MachineInstr &MI) const;
   bool isComplex(const MachineInstr &MI) const;
   bool isCompoundBranchInstr(const MachineInstr &MI) const;
   bool isConstExtended(const MachineInstr &MI) const;
@@ -387,7 +390,8 @@ public:
                            const MachineInstr &MI2) const;
   bool isHVXVec(const MachineInstr &MI) const;
   bool isValidAutoIncImm(const EVT VT, const int Offset) const;
-  bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
+  bool isValidOffset(unsigned Opcode, int Offset,
+                     const TargetRegisterInfo *TRI, bool Extend = true) const;
   bool isVecAcc(const MachineInstr &MI) const;
   bool isVecALU(const MachineInstr &MI) const;
   bool isVecUsableNextPacket(const MachineInstr &ProdMI,
@@ -413,13 +417,9 @@ public:
   bool PredOpcodeHasJMP_c(unsigned Opcode) const;
   bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
 
-  short getAbsoluteForm(const MachineInstr &MI) const;
   unsigned getAddrMode(const MachineInstr &MI) const;
   unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset,
                             unsigned &AccessSize) const;
-  short getBaseWithLongOffset(short Opcode) const;
-  short getBaseWithLongOffset(const MachineInstr &MI) const;
-  short getBaseWithRegOffset(const MachineInstr &MI) const;
   SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
   unsigned getCExtOpNum(const MachineInstr &MI) const;
   HexagonII::CompoundGroup
@@ -438,7 +438,6 @@ public:
   HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
                                                          const;
   short getEquivalentHWInstr(const MachineInstr &MI) const;
-  MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const;
   unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
                                       const MachineInstr &MI) const;
   bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
@@ -462,12 +461,42 @@ public:
 
   void immediateExtend(MachineInstr &MI) const;
   bool invertAndChangeJumpTarget(MachineInstr &MI,
-                                 MachineBasicBlock* NewTarget) const;
+                                 MachineBasicBlock *NewTarget) const;
   void genAllInsnTimingClasses(MachineFunction &MF) const;
   bool reversePredSense(MachineInstr &MI) const;
   unsigned reversePrediction(unsigned Opcode) const;
   bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
-  short xformRegToImmOffset(const MachineInstr &MI) const;
+
+  void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const;
+  bool getBundleNoShuf(const MachineInstr &MIB) const;
+  // Addressing mode relations.
+  short changeAddrMode_abs_io(short Opc) const;
+  short changeAddrMode_io_abs(short Opc) const;
+  short changeAddrMode_io_pi(short Opc) const;
+  short changeAddrMode_io_rr(short Opc) const;
+  short changeAddrMode_pi_io(short Opc) const;
+  short changeAddrMode_rr_io(short Opc) const;
+  short changeAddrMode_rr_ur(short Opc) const;
+  short changeAddrMode_ur_rr(short Opc) const;
+
+  short changeAddrMode_abs_io(const MachineInstr &MI) const {
+    return changeAddrMode_abs_io(MI.getOpcode());
+  }
+  short changeAddrMode_io_abs(const MachineInstr &MI) const {
+    return changeAddrMode_io_abs(MI.getOpcode());
+  }
+  short changeAddrMode_io_rr(const MachineInstr &MI) const {
+    return changeAddrMode_io_rr(MI.getOpcode());
+  }
+  short changeAddrMode_rr_io(const MachineInstr &MI) const {
+    return changeAddrMode_rr_io(MI.getOpcode());
+  }
+  short changeAddrMode_rr_ur(const MachineInstr &MI) const {
+    return changeAddrMode_rr_ur(MI.getOpcode());
+  }
+  short changeAddrMode_ur_rr(const MachineInstr &MI) const {
+    return changeAddrMode_ur_rr(MI.getOpcode());
+  }
 };
 
 } // end namespace llvm
diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td
index 104a28654dd5..1df143de6e80 100644
--- a/lib/Target/Hexagon/HexagonIntrinsics.td
+++ b/lib/Target/Hexagon/HexagonIntrinsics.td
@@ -735,6 +735,28 @@ def : Pat <(int_hexagon_A2_not I32:$Rs),
 def : Pat <(int_hexagon_A2_neg I32:$Rs),
            (A2_subri 0, I32:$Rs)>;
 
+// Make sure the patterns with zero immediate value has higher complexity
+// otherwise, we need to updated the predicates for immediates to exclude zero
+let AddedComplexity = 200 in {
+def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, (i32 0)),
+           (A2_tfr I32:$Rs)>;
+def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, (i32 0)),
+           (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
+def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, (i32 0)),
+           (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
+def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, (i32 0)),
+           (S2_vsathub I64:$Rs)>;
+}
+
+def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, u5_0ImmPred:$imm),
+           (S2_asr_i_r_rnd I32:$Rs, (UDEC1 u5_0ImmPred:$imm))>;
+def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, u6_0ImmPred:$imm),
+           (S2_asr_i_p_rnd I64:$Rs, (UDEC1 u6_0ImmPred:$imm))>;
+def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, u4_0ImmPred:$imm),
+           (S5_vasrhrnd I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
+def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, u4_0ImmPred:$imm),
+           (S5_asrhub_rnd_sat I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
+
 // Transfer immediate
 def  : Pat <(int_hexagon_A2_tfril I32:$Rs, u16_0ImmPred:$Is),
             (A2_tfril I32:$Rs, u16_0ImmPred:$Is)>;
@@ -1348,17 +1370,11 @@ def: T_stc_pat<S2_storerd_pci, int_hexagon_circ_std,   s4_3ImmPred, I64>;
 def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred, I32>;
 
 multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> {
-  def : Pat<(IntID VecPredRegs:$src1, IntRegs:$src2, VectorRegs:$src3),
-            (MI VecPredRegs:$src1, IntRegs:$src2, #0, VectorRegs:$src3)>,
-        Requires<[UseHVXSgl]>;
-
-  def : Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
-                                             IntRegs:$src2,
-                                             VectorRegs128B:$src3),
-            (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
-                                            IntRegs:$src2, #0,
-                                            VectorRegs128B:$src3)>,
-        Requires<[UseHVXDbl]>;
+  def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
+            (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>;
+  def : Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2,
+                                             HvxVR:$src3),
+            (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>;
 }
 
 defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vmaskedstoreq>;
@@ -1366,6 +1382,11 @@ defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vmaskedstorenq>;
 defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>;
 defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>;
 
+defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vS32b_qpred_ai>;
+defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vS32b_nqpred_ai>;
+defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vS32b_nt_qpred_ai>;
+defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vS32b_nt_nqpred_ai>;
+
 //*******************************************************************
 //           SYSTEM
 //*******************************************************************
diff --git a/lib/Target/Hexagon/HexagonIntrinsicsDerived.td b/lib/Target/Hexagon/HexagonIntrinsicsDerived.td
deleted file mode 100644
index 400c17333f73..000000000000
--- a/lib/Target/Hexagon/HexagonIntrinsicsDerived.td
+++ /dev/null
@@ -1,40 +0,0 @@
-//===-- HexagonIntrinsicsDerived.td - Derived intrinsics ---*- tablegen -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Multiply 64-bit and use lower result
-//
-// Optimized with intrinisics accumulates
-//
-def : Pat <(mul DoubleRegs:$src1, DoubleRegs:$src2),
-      (i64
-       (A2_combinew
-        (M2_maci
-         (M2_maci
-          (i32
-           (EXTRACT_SUBREG
-            (i64
-             (M2_dpmpyuu_s0 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
-                                          isub_lo)),
-                     (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
-                                          isub_lo)))),
-            isub_hi)),
-          (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_lo)),
-          (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), isub_hi))),
-         (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), isub_lo)),
-         (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_hi))),
-        (i32
-         (EXTRACT_SUBREG
-          (i64
-           (M2_dpmpyuu_s0 
-             (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_lo)),
-                   (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
-                                        isub_lo)))), isub_lo))))>;
-
-
-
diff --git a/lib/Target/Hexagon/HexagonIntrinsicsV60.td b/lib/Target/Hexagon/HexagonIntrinsicsV60.td
index f438b3e0368f..5e5c77b38e8e 100644
--- a/lib/Target/Hexagon/HexagonIntrinsicsV60.td
+++ b/lib/Target/Hexagon/HexagonIntrinsicsV60.td
@@ -13,445 +13,286 @@
 
 
 let AddedComplexity = 100 in {
-def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
-            (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_lo)) >,
-            Requires<[UseHVXSgl]>;
+def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
+            (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
 
-def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
-            (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_hi)) >,
-            Requires<[UseHVXSgl]>;
+def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
+            (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
 
-def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
-            (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_lo)) >,
-            Requires<[UseHVXDbl]>;
+def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
+            (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
 
-def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
-            (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_hi)) >,
-            Requires<[UseHVXDbl]>;
+def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
+            (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
 }
 
-def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
-           (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXSgl]>;
+def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
+           (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
-           (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXSgl]>;
+def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
+           (v512i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v512i1 (bitconvert (v64i8  VectorRegs:$src1))),
-           (v512i1 (V6_vandvrt(v64i8  VectorRegs:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXSgl]>;
+def : Pat <(v512i1 (bitconvert (v64i8  HvxVR:$src1))),
+           (v512i1 (V6_vandvrt(v64i8  HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v512i1 (bitconvert (v8i64  VectorRegs:$src1))),
-           (v512i1 (V6_vandvrt(v8i64  VectorRegs:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXSgl]>;
+def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
+           (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
-           (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXSgl]>;
+def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
+           (v32i16 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
-           (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXSgl]>;
+def : Pat <(v64i8  (bitconvert (v512i1 HvxQR:$src1))),
+           (v64i8  (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v64i8  (bitconvert (v512i1 VecPredRegs:$src1))),
-           (v64i8  (V6_vandqrt(v512i1 VecPredRegs:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXSgl]>;
+def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
+           (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v8i64  (bitconvert (v512i1 VecPredRegs:$src1))),
-           (v8i64  (V6_vandqrt(v512i1 VecPredRegs:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXSgl]>;
+def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))),
+           (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
-           (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXDbl]>;
+def : Pat <(v1024i1 (bitconvert (v128i8  HvxVR:$src1))),
+           (v1024i1 (V6_vandvrt (v128i8  HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
-           (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXDbl]>;
+def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))),
+           (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v1024i1 (bitconvert (v128i8  VectorRegs128B:$src1))),
-           (v1024i1 (V6_vandvrt_128B(v128i8  VectorRegs128B:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXDbl]>;
+def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))),
+           (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(v1024i1 (bitconvert (v16i64  VectorRegs128B:$src1))),
-           (v1024i1 (V6_vandvrt_128B(v16i64  VectorRegs128B:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXDbl]>;
-
-def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
-           (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXDbl]>;
-
-def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
-           (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXDbl]>;
-
-def : Pat <(v128i8  (bitconvert (v1024i1 VecPredRegs128B:$src1))),
-           (v128i8  (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXDbl]>;
-
-def : Pat <(v16i64  (bitconvert (v1024i1 VecPredRegs128B:$src1))),
-           (v16i64  (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
-                                              (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXDbl]>;
+def : Pat <(v128i8  (bitconvert (v1024i1 HvxQR:$src1))),
+           (v128i8  (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
 
 let AddedComplexity = 140 in {
-def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)),
+def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)),
            (V6_vS32b_ai IntRegs:$addr, 0,
-           (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1),
-                                       (A2_tfrsi 0x01010101))))>,
-            Requires<[UseHVXSgl]>;
+           (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1),
+                                       (A2_tfrsi 0x01010101))))>;
 
 def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
            (v512i1 (V6_vandvrt
-           (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXSgl]>;
+           (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
 
-def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
-           (V6_vS32b_ai_128B IntRegs:$addr, 0,
-           (v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1),
-                                       (A2_tfrsi 0x01010101))))>,
-            Requires<[UseHVXDbl]>;
+def : Pat <(store (v1024i1 HvxQR:$src1), (i32 IntRegs:$addr)),
+           (V6_vS32b_ai IntRegs:$addr, 0,
+           (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1),
+                                       (A2_tfrsi 0x01010101))))>;
 
 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
-           (v1024i1 (V6_vandvrt_128B
-           (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)),
-                                       (A2_tfrsi 0x01010101)))>,
-            Requires<[UseHVXDbl]>;
+           (v1024i1 (V6_vandvrt
+           (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
 }
 
 multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
   def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
-           (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>,
-       Requires<[UseHVXDbl]>;
+           (MI IntRegs:$src1)>;
 }
 
 multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1),
-           (MI    VectorRegs:$src1)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxVR:$src1),
+           (MI    HvxVR:$src1)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1),
-           (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1),
+           (MI HvxVR:$src1)>;
 }
 
 multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1),
-           (MI    VecDblRegs:$src1)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxWR:$src1),
+           (MI    HvxWR:$src1)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1),
-           (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1),
+           (MI HvxWR:$src1)>;
 }
 
 multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecPredRegs:$src1),
-           (MI    VecPredRegs:$src1)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxQR:$src1),
+           (MI    HvxQR:$src1)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1),
-           (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1),
+           (MI HvxQR:$src1)>;
 }
 
 multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
-           (MI    VecDblRegs:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
+           (MI    HvxWR:$src1, IntRegs:$src2)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2),
-           (!cast<InstHexagon>(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2),
+           (MI HvxWR:$src1, IntRegs:$src2)>;
 }
 
 multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
-           (MI    VectorRegs:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
+           (MI    HvxVR:$src1, IntRegs:$src2)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2),
-           (!cast<InstHexagon>(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2),
+           (MI HvxVR:$src1, IntRegs:$src2)>;
 }
 
 multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2),
-           (MI    VecDblRegs:$src1, VectorRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
+           (MI    HvxWR:$src1, HvxVR:$src2)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
-                                            VectorRegs128B:$src2),
-           (!cast<InstHexagon>(MI#"_128B")  VecDblRegs128B:$src1,
-                                            VectorRegs128B:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2),
+           (MI  HvxWR:$src1, HvxVR:$src2)>;
 }
 
 multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2),
-           (MI    VecDblRegs:$src1, VecDblRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
+           (MI    HvxWR:$src1, HvxWR:$src2)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
-                                            VecDblRegs128B:$src2),
-           (!cast<InstHexagon>(MI#"_128B")  VecDblRegs128B:$src1,
-                                            VecDblRegs128B:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
+           (MI  HvxWR:$src1, HvxWR:$src2)>;
 }
 
 multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2),
-           (MI    VectorRegs:$src1, VectorRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
+           (MI    HvxVR:$src1, HvxVR:$src2)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
-                                            VectorRegs128B:$src2),
-           (!cast<InstHexagon>(MI#"_128B")  VectorRegs128B:$src1,
-                                            VectorRegs128B:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
+           (MI  HvxVR:$src1, HvxVR:$src2)>;
 }
 
 multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
-           (MI    VecPredRegs:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
+           (MI    HvxQR:$src1, IntRegs:$src2)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
-                                            IntRegs:$src2),
-           (!cast<InstHexagon>(MI#"_128B")  VecPredRegs128B:$src1,
-                                            IntRegs:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
+           (MI  HvxQR:$src1, IntRegs:$src2)>;
 }
 
 multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2),
-           (MI    VecPredRegs:$src1, VecPredRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
+           (MI    HvxQR:$src1, HvxQR:$src2)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
-                                            VecPredRegs128B:$src2),
-           (!cast<InstHexagon>(MI#"_128B")  VecPredRegs128B:$src1,
-                                            VecPredRegs128B:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
+           (MI  HvxQR:$src1, HvxQR:$src2)>;
 }
 
 multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
-           (MI    VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
+           (MI    HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
-                                            VecDblRegs128B:$src2,
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
                                             IntRegs:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VecDblRegs128B:$src1,
-                                            VecDblRegs128B:$src2,
-                                            IntRegs:$src3)>,
-       Requires<[UseHVXDbl]>;
+           (MI  HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
 }
 
 multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
-           (MI    VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
+           (MI    HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
-                                            VectorRegs128B:$src2,
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
                                             IntRegs:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VectorRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            IntRegs:$src3)>,
-       Requires<[UseHVXDbl]>;
+           (MI  HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
 }
 
 multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
-           (MI    VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
+           (MI    HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
-                                            VectorRegs128B:$src2,
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
                                             IntRegs:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VecDblRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            IntRegs:$src3)>,
-       Requires<[UseHVXDbl]>;
+           (MI  HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
 }
 
 multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
-           (MI    VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),
+           (MI    HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
-                                            VecDblRegs128B:$src2,
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxWR:$src2,
                                             IntRegs:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VectorRegs128B:$src1,
-                                            VecDblRegs128B:$src2,
-                                            IntRegs:$src3)>,
-       Requires<[UseHVXDbl]>;
+           (MI  HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
 }
 
 multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
-           (MI    VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),
+           (MI    HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            VectorRegs128B:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VectorRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            VectorRegs128B:$src3)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
+                                            HvxVR:$src3),
+           (MI  HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
 }
 
 multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
-           (MI    VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
+           (MI    HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            VectorRegs128B:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VecDblRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            VectorRegs128B:$src3)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
+                                            HvxVR:$src3),
+           (MI  HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
 }
 
 multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
-           (MI    VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
+           (MI    HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            VectorRegs128B:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VecPredRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            VectorRegs128B:$src3)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
+                                            HvxVR:$src3),
+           (MI  HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
 }
 
 multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
-           (MI    VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
+           (MI    HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
-                                            VecPredRegs128B:$src2,
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
                                             IntRegs:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VectorRegs128B:$src1,
-                                            VecPredRegs128B:$src2,
-                                            IntRegs:$src3)>,
-       Requires<[UseHVXDbl]>;
+           (MI  HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
 }
 
 
 multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
-           (MI    VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),
+           (MI    HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
-                                            VectorRegs128B:$src2,
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
                                             IntRegs:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VecPredRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            IntRegs:$src3)>,
-       Requires<[UseHVXDbl]>;
+           (MI  HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
 }
 
 multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3),
-           (MI    VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
+           (MI    HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
-                                            VectorRegs128B:$src2, imm:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VectorRegs128B:$src1,
-                                            VectorRegs128B:$src2, imm:$src3)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1,
+                                            HvxVR:$src2, imm:$src3),
+           (MI  HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
 }
 
 multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3),
-           (MI    VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3),
+           (MI    HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1,
                                             IntRegs:$src2, imm:$src3),
-           (!cast<InstHexagon>(MI#"_128B")  VecDblRegs128B:$src1,
-                                            IntRegs:$src2, imm:$src3)>,
-       Requires<[UseHVXDbl]>;
+           (MI  HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
 }
 
 multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4),
-           (MI   VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
+           (MI   HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
-                                            VecDblRegs128B:$src2,
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
                                             IntRegs:$src3, imm:$src4),
-           (!cast<InstHexagon>(MI#"_128B")  VecDblRegs128B:$src1,
-                                            VecDblRegs128B:$src2,
-                                            IntRegs:$src3, imm:$src4)>,
-       Requires<[UseHVXDbl]>;
+           (MI  HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
 }
 
 multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
-                  IntRegs:$src4),
-           (MI    VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
-                  IntRegs:$src4)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
+           (MI    HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            VectorRegs128B:$src3,
-                                            IntRegs:$src4),
-           (!cast<InstHexagon>(MI#"_128B")  VectorRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            VectorRegs128B:$src3,
-                                            IntRegs:$src4)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
+                                            HvxVR:$src3, IntRegs:$src4),
+           (MI  HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
 }
 
 multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
-                  IntRegs:$src4),
-           (MI    VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
-                  IntRegs:$src4)>,
-       Requires<[UseHVXSgl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
+           (MI    HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
 
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            VectorRegs128B:$src3,
-                                            IntRegs:$src4),
-           (!cast<InstHexagon>(MI#"_128B")  VecDblRegs128B:$src1,
-                                            VectorRegs128B:$src2,
-                                            VectorRegs128B:$src3,
-                                            IntRegs:$src4)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
+                                            HvxVR:$src3, IntRegs:$src4),
+           (MI  HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
 }
 
 defm : T_WR_pat <V6_vtmpyb, int_hexagon_V6_vtmpyb>;
@@ -793,11 +634,10 @@ defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>;
 //def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>;
 
 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
-         (v64i16 (V6_vpackwh_sat_128B
-                 (v32i32 (V6_hi_128B VecDblRegs128B:$Vdd)),
-                 (v32i32 (V6_lo_128B VecDblRegs128B:$Vdd))))>,
-     Requires<[UseHVXDbl]>;
+         (v64i16 (V6_vpackwh_sat
+                 (v32i32 (V6_hi HvxWR:$Vdd)),
+                 (v32i32 (V6_lo HvxWR:$Vdd))))>;
 
 def: Pat<(int_hexagon_V6_vd0),      (V6_vd0)>;
-def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0_128B)>;
+def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0)>;
 
diff --git a/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
index f82ad6cb3da6..fd602257934a 100644
--- a/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
+++ b/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonLoopIdiomRecognition.cpp ----------------------------------===//
+//===- HexagonLoopIdiomRecognition.cpp ------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -9,28 +9,66 @@
 
 #define DEBUG_TYPE "hexagon-lir"
 
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Analysis/InstructionSimplify.h"
+#include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Analysis/LoopPass.h"
+#include "llvm/Analysis/MemoryLocation.h"
 #include "llvm/Analysis/ScalarEvolution.h"
 #include "llvm/Analysis/ScalarEvolutionExpander.h"
 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Attributes.h"
+#include "llvm/IR/BasicBlock.h"
+#include "llvm/IR/Constant.h"
+#include "llvm/IR/Constants.h"
 #include "llvm/IR/DataLayout.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Dominators.h"
+#include "llvm/IR/Function.h"
 #include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/InstrTypes.h"
+#include "llvm/IR/Instruction.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/Module.h"
 #include "llvm/IR/PatternMatch.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/User.h"
+#include "llvm/IR/Value.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/KnownBits.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Transforms/Utils/Local.h"
-
 #include <algorithm>
 #include <array>
+#include <cassert>
+#include <cstdint>
+#include <cstdlib>
+#include <deque>
+#include <functional>
+#include <iterator>
+#include <map>
+#include <set>
+#include <utility>
+#include <vector>
 
 using namespace llvm;
 
@@ -67,17 +105,22 @@ static const char *HexagonVolatileMemcpyName
 
 
 namespace llvm {
+
   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
   Pass *createHexagonLoopIdiomPass();
-}
+
+} // end namespace llvm
 
 namespace {
+
   class HexagonLoopIdiomRecognize : public LoopPass {
   public:
     static char ID;
+
     explicit HexagonLoopIdiomRecognize() : LoopPass(ID) {
       initializeHexagonLoopIdiomRecognizePass(*PassRegistry::getPassRegistry());
     }
+
     StringRef getPassName() const override {
       return "Recognize Hexagon-specific loop idioms";
     }
@@ -97,7 +140,6 @@ namespace {
     bool runOnLoop(Loop *L, LPPassManager &LPM) override;
 
   private:
-    unsigned getStoreSizeInBytes(StoreInst *SI);
     int getSCEVStride(const SCEVAddRecExpr *StoreEv);
     bool isLegalStore(Loop *CurLoop, StoreInst *SI);
     void collectStores(Loop *CurLoop, BasicBlock *BB,
@@ -116,28 +158,18 @@ namespace {
     ScalarEvolution *SE;
     bool HasMemcpy, HasMemmove;
   };
-}
-
-char HexagonLoopIdiomRecognize::ID = 0;
-
-INITIALIZE_PASS_BEGIN(HexagonLoopIdiomRecognize, "hexagon-loop-idiom",
-    "Recognize Hexagon-specific loop idioms", false, false)
-INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LoopSimplify)
-INITIALIZE_PASS_DEPENDENCY(LCSSAWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(ScalarEvolutionWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(HexagonLoopIdiomRecognize, "hexagon-loop-idiom",
-    "Recognize Hexagon-specific loop idioms", false, false)
 
-
-namespace {
   struct Simplifier {
-    typedef std::function<Value* (Instruction*, LLVMContext&)> Rule;
+    struct Rule {
+      using FuncType = std::function<Value* (Instruction*, LLVMContext&)>;
+      Rule(StringRef N, FuncType F) : Name(N), Fn(F) {}
+      StringRef Name;   // For debugging.
+      FuncType Fn;
+    };
 
-    void addRule(const Rule &R) { Rules.push_back(R); }
+    void addRule(StringRef N, const Rule::FuncType &F) {
+      Rules.push_back(Rule(N, F));
+    }
 
   private:
     struct WorkListType {
@@ -147,10 +179,12 @@ namespace {
         // Do not push back duplicates.
         if (!S.count(V)) { Q.push_back(V); S.insert(V); }
       }
+
       Value *pop_front_val() {
         Value *V = Q.front(); Q.pop_front(); S.erase(V);
         return V;
       }
+
       bool empty() const { return Q.empty(); }
 
     private:
@@ -158,12 +192,13 @@ namespace {
       std::set<Value*> S;
     };
 
-    typedef std::set<Value*> ValueSetType;
+    using ValueSetType = std::set<Value *>;
+
     std::vector<Rule> Rules;
 
   public:
     struct Context {
-      typedef DenseMap<Value*,Value*> ValueMapType;
+      using ValueMapType = DenseMap<Value *, Value *>;
 
       Value *Root;
       ValueSetType Used;    // The set of all cloned values used by Root.
@@ -174,12 +209,15 @@ namespace {
         : Ctx(Exp->getParent()->getParent()->getContext()) {
         initialize(Exp);
       }
+
       ~Context() { cleanup(); }
-      void print(raw_ostream &OS, const Value *V) const;
 
+      void print(raw_ostream &OS, const Value *V) const;
       Value *materialize(BasicBlock *B, BasicBlock::iterator At);
 
     private:
+      friend struct Simplifier;
+
       void initialize(Instruction *Exp);
       void cleanup();
 
@@ -193,8 +231,6 @@ namespace {
       Value *subst(Value *Tree, Value *OldV, Value *NewV);
       void replace(Value *OldV, Value *NewV);
       void link(Instruction *I, BasicBlock *B, BasicBlock::iterator At);
-
-      friend struct Simplifier;
     };
 
     Value *simplify(Context &C);
@@ -202,6 +238,7 @@ namespace {
 
   struct PE {
     PE(const Simplifier::Context &c, Value *v = nullptr) : C(c), V(v) {}
+
     const Simplifier::Context &C;
     const Value *V;
   };
@@ -211,8 +248,22 @@ namespace {
     P.C.print(OS, P.V ? P.V : P.C.Root);
     return OS;
   }
-}
 
+} // end anonymous namespace
+
+char HexagonLoopIdiomRecognize::ID = 0;
+
+INITIALIZE_PASS_BEGIN(HexagonLoopIdiomRecognize, "hexagon-loop-idiom",
+    "Recognize Hexagon-specific loop idioms", false, false)
+INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(LoopSimplify)
+INITIALIZE_PASS_DEPENDENCY(LCSSAWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(ScalarEvolutionWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
+INITIALIZE_PASS_END(HexagonLoopIdiomRecognize, "hexagon-loop-idiom",
+    "Recognize Hexagon-specific loop idioms", false, false)
 
 template <typename FuncT>
 void Simplifier::Context::traverse(Value *V, FuncT F) {
@@ -230,7 +281,6 @@ void Simplifier::Context::traverse(Value *V, FuncT F) {
   }
 }
 
-
 void Simplifier::Context::print(raw_ostream &OS, const Value *V) const {
   const auto *U = dyn_cast<const Instruction>(V);
   if (!U) {
@@ -257,7 +307,6 @@ void Simplifier::Context::print(raw_ostream &OS, const Value *V) const {
     OS << ')';
 }
 
-
 void Simplifier::Context::initialize(Instruction *Exp) {
   // Perform a deep clone of the expression, set Root to the root
   // of the clone, and build a map from the cloned values to the
@@ -297,7 +346,6 @@ void Simplifier::Context::initialize(Instruction *Exp) {
   use(Root);
 }
 
-
 void Simplifier::Context::record(Value *V) {
   auto Record = [this](Instruction *U) -> bool {
     Clones.insert(U);
@@ -306,7 +354,6 @@ void Simplifier::Context::record(Value *V) {
   traverse(V, Record);
 }
 
-
 void Simplifier::Context::use(Value *V) {
   auto Use = [this](Instruction *U) -> bool {
     Used.insert(U);
@@ -315,7 +362,6 @@ void Simplifier::Context::use(Value *V) {
   traverse(V, Use);
 }
 
-
 void Simplifier::Context::unuse(Value *V) {
   if (!isa<Instruction>(V) || cast<Instruction>(V)->getParent() != nullptr)
     return;
@@ -329,7 +375,6 @@ void Simplifier::Context::unuse(Value *V) {
   traverse(V, Unuse);
 }
 
-
 Value *Simplifier::Context::subst(Value *Tree, Value *OldV, Value *NewV) {
   if (Tree == OldV)
     return NewV;
@@ -356,7 +401,6 @@ Value *Simplifier::Context::subst(Value *Tree, Value *OldV, Value *NewV) {
   return Tree;
 }
 
-
 void Simplifier::Context::replace(Value *OldV, Value *NewV) {
   if (Root == OldV) {
     Root = NewV;
@@ -391,7 +435,6 @@ void Simplifier::Context::replace(Value *OldV, Value *NewV) {
   use(Root);
 }
 
-
 void Simplifier::Context::cleanup() {
   for (Value *V : Clones) {
     Instruction *U = cast<Instruction>(V);
@@ -406,7 +449,6 @@ void Simplifier::Context::cleanup() {
   }
 }
 
-
 bool Simplifier::Context::equal(const Instruction *I,
                                 const Instruction *J) const {
   if (I == J)
@@ -431,7 +473,6 @@ bool Simplifier::Context::equal(const Instruction *I,
   return true;
 }
 
-
 Value *Simplifier::Context::find(Value *Tree, Value *Sub) const {
   Instruction *SubI = dyn_cast<Instruction>(Sub);
   WorkListType Q;
@@ -453,7 +494,6 @@ Value *Simplifier::Context::find(Value *Tree, Value *Sub) const {
   return nullptr;
 }
 
-
 void Simplifier::Context::link(Instruction *I, BasicBlock *B,
       BasicBlock::iterator At) {
   if (I->getParent())
@@ -467,7 +507,6 @@ void Simplifier::Context::link(Instruction *I, BasicBlock *B,
   B->getInstList().insert(At, I);
 }
 
-
 Value *Simplifier::Context::materialize(BasicBlock *B,
       BasicBlock::iterator At) {
   if (Instruction *RootI = dyn_cast<Instruction>(Root))
@@ -475,7 +514,6 @@ Value *Simplifier::Context::materialize(BasicBlock *B,
   return Root;
 }
 
-
 Value *Simplifier::simplify(Context &C) {
   WorkListType Q;
   Q.push_back(C.Root);
@@ -490,7 +528,7 @@ Value *Simplifier::simplify(Context &C) {
       continue;
     bool Changed = false;
     for (Rule &R : Rules) {
-      Value *W = R(U, C.Ctx);
+      Value *W = R.Fn(U, C.Ctx);
       if (!W)
         continue;
       Changed = true;
@@ -507,7 +545,6 @@ Value *Simplifier::simplify(Context &C) {
   return Count < Limit ? C.Root : nullptr;
 }
 
-
 //===----------------------------------------------------------------------===//
 //
 //          Implementation of PolynomialMultiplyRecognize
@@ -515,6 +552,7 @@ Value *Simplifier::simplify(Context &C) {
 //===----------------------------------------------------------------------===//
 
 namespace {
+
   class PolynomialMultiplyRecognize {
   public:
     explicit PolynomialMultiplyRecognize(Loop *loop, const DataLayout &dl,
@@ -523,13 +561,15 @@ namespace {
       : CurLoop(loop), DL(dl), DT(dt), TLI(tli), SE(se) {}
 
     bool recognize();
+
   private:
-    typedef SetVector<Value*> ValueSeq;
+    using ValueSeq = SetVector<Value *>;
 
     IntegerType *getPmpyType() const {
       LLVMContext &Ctx = CurLoop->getHeader()->getParent()->getContext();
       return IntegerType::get(Ctx, 32);
     }
+
     bool isPromotableTo(Value *V, IntegerType *Ty);
     void promoteTo(Instruction *In, IntegerType *DestTy, BasicBlock *LoopB);
     bool promoteTypes(BasicBlock *LoopB, BasicBlock *ExitB);
@@ -548,12 +588,17 @@ namespace {
     void cleanupLoopBody(BasicBlock *LoopB);
 
     struct ParsedValues {
-      ParsedValues() : M(nullptr), P(nullptr), Q(nullptr), R(nullptr),
-          X(nullptr), Res(nullptr), IterCount(0), Left(false), Inv(false) {}
-      Value *M, *P, *Q, *R, *X;
-      Instruction *Res;
-      unsigned IterCount;
-      bool Left, Inv;
+      ParsedValues() = default;
+
+      Value *M = nullptr;
+      Value *P = nullptr;
+      Value *Q = nullptr;
+      Value *R = nullptr;
+      Value *X = nullptr;
+      Instruction *Res = nullptr;
+      unsigned IterCount = 0;
+      bool Left = false;
+      bool Inv = false;
     };
 
     bool matchLeftShift(SelectInst *SelI, Value *CIV, ParsedValues &PV);
@@ -572,8 +617,8 @@ namespace {
     const TargetLibraryInfo &TLI;
     ScalarEvolution &SE;
   };
-}
 
+} // end anonymous namespace
 
 Value *PolynomialMultiplyRecognize::getCountIV(BasicBlock *BB) {
   pred_iterator PI = pred_begin(BB), PE = pred_end(BB);
@@ -607,7 +652,6 @@ Value *PolynomialMultiplyRecognize::getCountIV(BasicBlock *BB) {
   return nullptr;
 }
 
-
 static void replaceAllUsesOfWithIn(Value *I, Value *J, BasicBlock *BB) {
   for (auto UI = I->user_begin(), UE = I->user_end(); UI != UE;) {
     Use &TheUse = UI.getUse();
@@ -618,7 +662,6 @@ static void replaceAllUsesOfWithIn(Value *I, Value *J, BasicBlock *BB) {
   }
 }
 
-
 bool PolynomialMultiplyRecognize::matchLeftShift(SelectInst *SelI,
       Value *CIV, ParsedValues &PV) {
   // Match the following:
@@ -734,7 +777,6 @@ bool PolynomialMultiplyRecognize::matchLeftShift(SelectInst *SelI,
   return true;
 }
 
-
 bool PolynomialMultiplyRecognize::matchRightShift(SelectInst *SelI,
       ParsedValues &PV) {
   // Match the following:
@@ -810,11 +852,11 @@ bool PolynomialMultiplyRecognize::matchRightShift(SelectInst *SelI,
   return true;
 }
 
-
 bool PolynomialMultiplyRecognize::scanSelect(SelectInst *SelI,
       BasicBlock *LoopB, BasicBlock *PrehB, Value *CIV, ParsedValues &PV,
       bool PreScan) {
   using namespace PatternMatch;
+
   // The basic pattern for R = P.Q is:
   // for i = 0..31
   //   R = phi (0, R')
@@ -917,7 +959,6 @@ bool PolynomialMultiplyRecognize::scanSelect(SelectInst *SelI,
   return false;
 }
 
-
 bool PolynomialMultiplyRecognize::isPromotableTo(Value *Val,
       IntegerType *DestTy) {
   IntegerType *T = dyn_cast<IntegerType>(Val->getType());
@@ -955,7 +996,6 @@ bool PolynomialMultiplyRecognize::isPromotableTo(Value *Val,
   return false;
 }
 
-
 void PolynomialMultiplyRecognize::promoteTo(Instruction *In,
       IntegerType *DestTy, BasicBlock *LoopB) {
   // Leave boolean values alone.
@@ -997,7 +1037,6 @@ void PolynomialMultiplyRecognize::promoteTo(Instruction *In,
   }
 }
 
-
 bool PolynomialMultiplyRecognize::promoteTypes(BasicBlock *LoopB,
       BasicBlock *ExitB) {
   assert(LoopB);
@@ -1061,7 +1100,6 @@ bool PolynomialMultiplyRecognize::promoteTypes(BasicBlock *LoopB,
   return true;
 }
 
-
 bool PolynomialMultiplyRecognize::findCycle(Value *Out, Value *In,
       ValueSeq &Cycle) {
   // Out = ..., In, ...
@@ -1094,7 +1132,6 @@ bool PolynomialMultiplyRecognize::findCycle(Value *Out, Value *In,
   return !Cycle.empty();
 }
 
-
 void PolynomialMultiplyRecognize::classifyCycle(Instruction *DivI,
       ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) {
   // All the values in the cycle that are between the phi node and the
@@ -1131,7 +1168,6 @@ void PolynomialMultiplyRecognize::classifyCycle(Instruction *DivI,
     First.insert(Cycle[I]);
 }
 
-
 bool PolynomialMultiplyRecognize::classifyInst(Instruction *UseI,
       ValueSeq &Early, ValueSeq &Late) {
   // Select is an exception, since the condition value does not have to be
@@ -1184,7 +1220,6 @@ bool PolynomialMultiplyRecognize::classifyInst(Instruction *UseI,
   return true;
 }
 
-
 bool PolynomialMultiplyRecognize::commutesWithShift(Instruction *I) {
   switch (I->getOpcode()) {
     case Instruction::And:
@@ -1202,7 +1237,6 @@ bool PolynomialMultiplyRecognize::commutesWithShift(Instruction *I) {
   return true;
 }
 
-
 bool PolynomialMultiplyRecognize::highBitsAreZero(Value *V,
       unsigned IterCount) {
   auto *T = dyn_cast<IntegerType>(V->getType());
@@ -1214,7 +1248,6 @@ bool PolynomialMultiplyRecognize::highBitsAreZero(Value *V,
   return Known.countMinLeadingZeros() >= IterCount;
 }
 
-
 bool PolynomialMultiplyRecognize::keepsHighBitsZero(Value *V,
       unsigned IterCount) {
   // Assume that all inputs to the value have the high bits zero.
@@ -1239,7 +1272,6 @@ bool PolynomialMultiplyRecognize::keepsHighBitsZero(Value *V,
   return false;
 }
 
-
 bool PolynomialMultiplyRecognize::isOperandShifted(Instruction *I, Value *Op) {
   unsigned Opc = I->getOpcode();
   if (Opc == Instruction::Shl || Opc == Instruction::LShr)
@@ -1247,7 +1279,6 @@ bool PolynomialMultiplyRecognize::isOperandShifted(Instruction *I, Value *Op) {
   return true;
 }
 
-
 bool PolynomialMultiplyRecognize::convertShiftsToLeft(BasicBlock *LoopB,
       BasicBlock *ExitB, unsigned IterCount) {
   Value *CIV = getCountIV(LoopB);
@@ -1263,6 +1294,7 @@ bool PolynomialMultiplyRecognize::convertShiftsToLeft(BasicBlock *LoopB,
   // Find all value cycles that contain logical right shifts by 1.
   for (Instruction &I : *LoopB) {
     using namespace PatternMatch;
+
     Value *V = nullptr;
     if (!match(&I, m_LShr(m_Value(V), m_One())))
       continue;
@@ -1303,7 +1335,7 @@ bool PolynomialMultiplyRecognize::convertShiftsToLeft(BasicBlock *LoopB,
     }
   }
 
-  if (Users.size() == 0)
+  if (Users.empty())
     return false;
 
   // Verify that high bits remain zero.
@@ -1331,7 +1363,9 @@ bool PolynomialMultiplyRecognize::convertShiftsToLeft(BasicBlock *LoopB,
   // Finally, the work can be done. Unshift each user.
   IRBuilder<> IRB(LoopB);
   std::map<Value*,Value*> ShiftMap;
-  typedef std::map<std::pair<Value*,Type*>,Value*> CastMapType;
+
+  using CastMapType = std::map<std::pair<Value *, Type *>, Value *>;
+
   CastMapType CastMap;
 
   auto upcast = [] (CastMapType &CM, IRBuilder<> &IRB, Value *V,
@@ -1345,9 +1379,11 @@ bool PolynomialMultiplyRecognize::convertShiftsToLeft(BasicBlock *LoopB,
   };
 
   for (auto I = LoopB->begin(), E = LoopB->end(); I != E; ++I) {
+    using namespace PatternMatch;
+
     if (isa<PHINode>(I) || !Users.count(&*I))
       continue;
-    using namespace PatternMatch;
+
     // Match lshr x, 1.
     Value *V = nullptr;
     if (match(&*I, m_LShr(m_Value(V), m_One()))) {
@@ -1419,7 +1455,6 @@ bool PolynomialMultiplyRecognize::convertShiftsToLeft(BasicBlock *LoopB,
   return true;
 }
 
-
 void PolynomialMultiplyRecognize::cleanupLoopBody(BasicBlock *LoopB) {
   for (auto &I : *LoopB)
     if (Value *SV = SimplifyInstruction(&I, {DL, &TLI, &DT}))
@@ -1431,7 +1466,6 @@ void PolynomialMultiplyRecognize::cleanupLoopBody(BasicBlock *LoopB) {
   }
 }
 
-
 unsigned PolynomialMultiplyRecognize::getInverseMxN(unsigned QP) {
   // Arrays of coefficients of Q and the inverse, C.
   // Q[i] = coefficient at x^i.
@@ -1475,7 +1509,6 @@ unsigned PolynomialMultiplyRecognize::getInverseMxN(unsigned QP) {
   return QV;
 }
 
-
 Value *PolynomialMultiplyRecognize::generate(BasicBlock::iterator At,
       ParsedValues &PV) {
   IRBuilder<> B(&*At);
@@ -1517,9 +1550,30 @@ Value *PolynomialMultiplyRecognize::generate(BasicBlock::iterator At,
   return R;
 }
 
+static bool hasZeroSignBit(const Value *V) {
+  if (const auto *CI = dyn_cast<const ConstantInt>(V))
+    return (CI->getType()->getSignBit() & CI->getSExtValue()) == 0;
+  const Instruction *I = dyn_cast<const Instruction>(V);
+  if (!I)
+    return false;
+  switch (I->getOpcode()) {
+    case Instruction::LShr:
+      if (const auto SI = dyn_cast<const ConstantInt>(I->getOperand(1)))
+        return SI->getZExtValue() > 0;
+      return false;
+    case Instruction::Or:
+    case Instruction::Xor:
+      return hasZeroSignBit(I->getOperand(0)) &&
+             hasZeroSignBit(I->getOperand(1));
+    case Instruction::And:
+      return hasZeroSignBit(I->getOperand(0)) ||
+             hasZeroSignBit(I->getOperand(1));
+  }
+  return false;
+}
 
 void PolynomialMultiplyRecognize::setupSimplifier() {
-  Simp.addRule(
+  Simp.addRule("sink-zext",
     // Sink zext past bitwise operations.
     [](Instruction *I, LLVMContext &Ctx) -> Value* {
       if (I->getOpcode() != Instruction::ZExt)
@@ -1540,7 +1594,7 @@ void PolynomialMultiplyRecognize::setupSimplifier() {
                            B.CreateZExt(T->getOperand(0), I->getType()),
                            B.CreateZExt(T->getOperand(1), I->getType()));
     });
-  Simp.addRule(
+  Simp.addRule("xor/and -> and/xor",
     // (xor (and x a) (and y a)) -> (and (xor x y) a)
     [](Instruction *I, LLVMContext &Ctx) -> Value* {
       if (I->getOpcode() != Instruction::Xor)
@@ -1558,7 +1612,7 @@ void PolynomialMultiplyRecognize::setupSimplifier() {
       return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1->getOperand(0)),
                          And0->getOperand(1));
     });
-  Simp.addRule(
+  Simp.addRule("sink binop into select",
     // (Op (select c x y) z) -> (select c (Op x z) (Op y z))
     // (Op x (select c y z)) -> (select c (Op x y) (Op x z))
     [](Instruction *I, LLVMContext &Ctx) -> Value* {
@@ -1584,7 +1638,7 @@ void PolynomialMultiplyRecognize::setupSimplifier() {
       }
       return nullptr;
     });
-  Simp.addRule(
+  Simp.addRule("fold select-select",
     // (select c (select c x y) z) -> (select c x z)
     // (select c x (select c y z)) -> (select c x z)
     [](Instruction *I, LLVMContext &Ctx) -> Value* {
@@ -1603,23 +1657,19 @@ void PolynomialMultiplyRecognize::setupSimplifier() {
       }
       return nullptr;
     });
-  Simp.addRule(
+  Simp.addRule("or-signbit -> xor-signbit",
     // (or (lshr x 1) 0x800.0) -> (xor (lshr x 1) 0x800.0)
     [](Instruction *I, LLVMContext &Ctx) -> Value* {
       if (I->getOpcode() != Instruction::Or)
         return nullptr;
-      Instruction *LShr = dyn_cast<Instruction>(I->getOperand(0));
-      if (!LShr || LShr->getOpcode() != Instruction::LShr)
-        return nullptr;
-      ConstantInt *One = dyn_cast<ConstantInt>(LShr->getOperand(1));
-      if (!One || One->getZExtValue() != 1)
-        return nullptr;
       ConstantInt *Msb = dyn_cast<ConstantInt>(I->getOperand(1));
       if (!Msb || Msb->getZExtValue() != Msb->getType()->getSignBit())
         return nullptr;
-      return IRBuilder<>(Ctx).CreateXor(LShr, Msb);
+      if (!hasZeroSignBit(I->getOperand(0)))
+        return nullptr;
+      return IRBuilder<>(Ctx).CreateXor(I->getOperand(0), Msb);
     });
-  Simp.addRule(
+  Simp.addRule("sink lshr into binop",
     // (lshr (BitOp x y) c) -> (BitOp (lshr x c) (lshr y c))
     [](Instruction *I, LLVMContext &Ctx) -> Value* {
       if (I->getOpcode() != Instruction::LShr)
@@ -1641,7 +1691,7 @@ void PolynomialMultiplyRecognize::setupSimplifier() {
                 B.CreateLShr(BitOp->getOperand(0), S),
                 B.CreateLShr(BitOp->getOperand(1), S));
     });
-  Simp.addRule(
+  Simp.addRule("expose bitop-const",
     // (BitOp1 (BitOp2 x a) b) -> (BitOp2 x (BitOp1 a b))
     [](Instruction *I, LLVMContext &Ctx) -> Value* {
       auto IsBitOp = [](unsigned Op) -> bool {
@@ -1670,7 +1720,6 @@ void PolynomialMultiplyRecognize::setupSimplifier() {
     });
 }
 
-
 bool PolynomialMultiplyRecognize::recognize() {
   DEBUG(dbgs() << "Starting PolynomialMultiplyRecognize on loop\n"
                << *CurLoop << '\n');
@@ -1712,9 +1761,17 @@ bool PolynomialMultiplyRecognize::recognize() {
   // XXX: Currently this approach can modify the loop before being 100% sure
   // that the transformation can be carried out.
   bool FoundPreScan = false;
+  auto FeedsPHI = [LoopB](const Value *V) -> bool {
+    for (const Value *U : V->users()) {
+      if (const auto *P = dyn_cast<const PHINode>(U))
+        if (P->getParent() == LoopB)
+          return true;
+    }
+    return false;
+  };
   for (Instruction &In : *LoopB) {
     SelectInst *SI = dyn_cast<SelectInst>(&In);
-    if (!SI)
+    if (!SI || !FeedsPHI(SI))
       continue;
 
     Simplifier::Context C(SI);
@@ -1789,22 +1846,12 @@ bool PolynomialMultiplyRecognize::recognize() {
   return true;
 }
 
-
-unsigned HexagonLoopIdiomRecognize::getStoreSizeInBytes(StoreInst *SI) {
-  uint64_t SizeInBits = DL->getTypeSizeInBits(SI->getValueOperand()->getType());
-  assert(((SizeInBits & 7) || (SizeInBits >> 32) == 0) &&
-         "Don't overflow unsigned.");
-  return (unsigned)SizeInBits >> 3;
-}
-
-
 int HexagonLoopIdiomRecognize::getSCEVStride(const SCEVAddRecExpr *S) {
   if (const SCEVConstant *SC = dyn_cast<SCEVConstant>(S->getOperand(1)))
     return SC->getAPInt().getSExtValue();
   return 0;
 }
 
-
 bool HexagonLoopIdiomRecognize::isLegalStore(Loop *CurLoop, StoreInst *SI) {
   // Allow volatile stores if HexagonVolatileMemcpy is enabled.
   if (!(SI->isVolatile() && HexagonVolatileMemcpy) && !SI->isSimple())
@@ -1830,7 +1877,7 @@ bool HexagonLoopIdiomRecognize::isLegalStore(Loop *CurLoop, StoreInst *SI) {
   int Stride = getSCEVStride(StoreEv);
   if (Stride == 0)
     return false;
-  unsigned StoreSize = getStoreSizeInBytes(SI);
+  unsigned StoreSize = DL->getTypeStoreSize(SI->getValueOperand()->getType());
   if (StoreSize != unsigned(std::abs(Stride)))
     return false;
 
@@ -1855,7 +1902,6 @@ bool HexagonLoopIdiomRecognize::isLegalStore(Loop *CurLoop, StoreInst *SI) {
   return true;
 }
 
-
 /// mayLoopAccessLocation - Return true if the specified loop might access the
 /// specified pointer location, which is a loop-strided access.  The 'Access'
 /// argument specifies what the verboten forms of access are (read or write).
@@ -1882,13 +1928,14 @@ mayLoopAccessLocation(Value *Ptr, ModRefInfo Access, Loop *L,
 
   for (auto *B : L->blocks())
     for (auto &I : *B)
-      if (Ignored.count(&I) == 0 && (AA.getModRefInfo(&I, StoreLoc) & Access))
+      if (Ignored.count(&I) == 0 &&
+          isModOrRefSet(
+              intersectModRef(AA.getModRefInfo(&I, StoreLoc), Access)))
         return true;
 
   return false;
 }
 
-
 void HexagonLoopIdiomRecognize::collectStores(Loop *CurLoop, BasicBlock *BB,
       SmallVectorImpl<StoreInst*> &Stores) {
   Stores.clear();
@@ -1898,7 +1945,6 @@ void HexagonLoopIdiomRecognize::collectStores(Loop *CurLoop, BasicBlock *BB,
         Stores.push_back(SI);
 }
 
-
 bool HexagonLoopIdiomRecognize::processCopyingStore(Loop *CurLoop,
       StoreInst *SI, const SCEV *BECount) {
   assert((SI->isSimple() || (SI->isVolatile() && HexagonVolatileMemcpy)) &&
@@ -1908,7 +1954,7 @@ bool HexagonLoopIdiomRecognize::processCopyingStore(Loop *CurLoop,
   Value *StorePtr = SI->getPointerOperand();
   auto *StoreEv = cast<SCEVAddRecExpr>(SE->getSCEV(StorePtr));
   unsigned Stride = getSCEVStride(StoreEv);
-  unsigned StoreSize = getStoreSizeInBytes(SI);
+  unsigned StoreSize = DL->getTypeStoreSize(SI->getValueOperand()->getType());
   if (Stride != StoreSize)
     return false;
 
@@ -1963,12 +2009,12 @@ CleanupAndExit:
 
   SmallPtrSet<Instruction*, 2> Ignore1;
   Ignore1.insert(SI);
-  if (mayLoopAccessLocation(StoreBasePtr, MRI_ModRef, CurLoop, BECount,
+  if (mayLoopAccessLocation(StoreBasePtr, ModRefInfo::ModRef, CurLoop, BECount,
                             StoreSize, *AA, Ignore1)) {
     // Check if the load is the offending instruction.
     Ignore1.insert(LI);
-    if (mayLoopAccessLocation(StoreBasePtr, MRI_ModRef, CurLoop, BECount,
-                              StoreSize, *AA, Ignore1)) {
+    if (mayLoopAccessLocation(StoreBasePtr, ModRefInfo::ModRef, CurLoop,
+                              BECount, StoreSize, *AA, Ignore1)) {
       // Still bad. Nothing we can do.
       goto CleanupAndExit;
     }
@@ -1998,7 +2044,7 @@ CleanupAndExit:
 
     if (DisableMemmoveIdiom || !HasMemmove)
       goto CleanupAndExit;
-    bool IsNested = CurLoop->getParentLoop() != 0;
+    bool IsNested = CurLoop->getParentLoop() != nullptr;
     if (IsNested && OnlyNonNestedMemmove)
       goto CleanupAndExit;
   }
@@ -2010,8 +2056,8 @@ CleanupAndExit:
 
   SmallPtrSet<Instruction*, 2> Ignore2;
   Ignore2.insert(SI);
-  if (mayLoopAccessLocation(LoadBasePtr, MRI_Mod, CurLoop, BECount, StoreSize,
-                            *AA, Ignore2))
+  if (mayLoopAccessLocation(LoadBasePtr, ModRefInfo::Mod, CurLoop, BECount,
+                            StoreSize, *AA, Ignore2))
     goto CleanupAndExit;
 
   // Check the stride.
@@ -2098,9 +2144,10 @@ CleanupAndExit:
     Value *CmpA = Builder.CreateICmpULT(LowA, HighA);
     Value *Cond = CmpA;
 
-    // Check for distance between pointers.
-    Value *Dist = Builder.CreateSub(HighA, LowA);
-    Value *CmpD = Builder.CreateICmpSLT(NumBytes, Dist);
+    // Check for distance between pointers. Since the case LowA < HighA
+    // is checked for above, assume LowA >= HighA.
+    Value *Dist = Builder.CreateSub(LowA, HighA);
+    Value *CmpD = Builder.CreateICmpSLE(NumBytes, Dist);
     Value *CmpEither = Builder.CreateOr(Cond, CmpD);
     Cond = CmpEither;
 
@@ -2191,7 +2238,6 @@ CleanupAndExit:
   return true;
 }
 
-
 // \brief Check if the instructions in Insts, together with their dependencies
 // cover the loop in the sense that the loop could be safely eliminated once
 // the instructions in Insts are removed.
@@ -2270,7 +2316,6 @@ bool HexagonLoopIdiomRecognize::runOnLoopBlock(Loop *CurLoop, BasicBlock *BB,
   return MadeChange;
 }
 
-
 bool HexagonLoopIdiomRecognize::runOnCountableLoop(Loop *L) {
   PolynomialMultiplyRecognize PMR(L, *DL, *DT, *TLI, *SE);
   if (PMR.recognize())
@@ -2300,7 +2345,6 @@ bool HexagonLoopIdiomRecognize::runOnCountableLoop(Loop *L) {
   return Changed;
 }
 
-
 bool HexagonLoopIdiomRecognize::runOnLoop(Loop *L, LPPassManager &LPM) {
   const Module &M = *L->getHeader()->getParent()->getParent();
   if (Triple(M.getTargetTriple()).getArch() != Triple::hexagon)
@@ -2334,8 +2378,6 @@ bool HexagonLoopIdiomRecognize::runOnLoop(Loop *L, LPPassManager &LPM) {
   return false;
 }
 
-
 Pass *llvm::createHexagonLoopIdiomPass() {
   return new HexagonLoopIdiomRecognize();
 }
-
diff --git a/lib/Target/Hexagon/HexagonMCInstLower.cpp b/lib/Target/Hexagon/HexagonMCInstLower.cpp
index 072501d8260d..fb5752ade1de 100644
--- a/lib/Target/Hexagon/HexagonMCInstLower.cpp
+++ b/lib/Target/Hexagon/HexagonMCInstLower.cpp
@@ -14,22 +14,30 @@
 
 #include "Hexagon.h"
 #include "HexagonAsmPrinter.h"
-#include "HexagonMachineFunctionInfo.h"
+#include "MCTargetDesc/HexagonMCExpr.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
-
+#include "MCTargetDesc/HexagonMCTargetDesc.h"
+#include "llvm/ADT/APFloat.h"
+#include "llvm/ADT/APInt.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/IR/Constants.h"
-#include "llvm/IR/Mangler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cassert>
 
 using namespace llvm;
 
 namespace llvm {
-  void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
-                        MCInst &MCB, HexagonAsmPrinter &AP);
-}
+
+void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
+                      MCInst &MCB, HexagonAsmPrinter &AP);
+
+} // end namespace llvm
 
 static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
                               HexagonAsmPrinter &Printer, bool MustExtend) {
diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/lib/Target/Hexagon/HexagonMachineScheduler.cpp
index 1a26805d190d..b1c549aa13fa 100644
--- a/lib/Target/Hexagon/HexagonMachineScheduler.cpp
+++ b/lib/Target/Hexagon/HexagonMachineScheduler.cpp
@@ -13,20 +13,40 @@
 //===----------------------------------------------------------------------===//
 
 #include "HexagonMachineScheduler.h"
+#include "HexagonInstrInfo.h"
 #include "HexagonSubtarget.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/DFAPacketizer.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
-#include "llvm/CodeGen/ScheduleDAGMutation.h"
+#include "llvm/CodeGen/RegisterPressure.h"
+#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/Function.h"
-
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include <algorithm>
+#include <cassert>
 #include <iomanip>
+#include <limits>
+#include <memory>
 #include <sstream>
 
+using namespace llvm;
+
+#define DEBUG_TYPE "machine-scheduler"
+
 static cl::opt<bool> IgnoreBBRegPressure("ignore-bb-reg-pressure",
     cl::Hidden, cl::ZeroOrMore, cl::init(false));
 
-static cl::opt<bool> SchedPredsCloser("sched-preds-closer",
-    cl::Hidden, cl::ZeroOrMore, cl::init(true));
-
 static cl::opt<unsigned> SchedDebugVerboseLevel("misched-verbose-level",
     cl::Hidden, cl::ZeroOrMore, cl::init(1));
 
@@ -39,99 +59,11 @@ static cl::opt<bool> BotUseShorterTie("bot-use-shorter-tie",
 static cl::opt<bool> DisableTCTie("disable-tc-tie",
     cl::Hidden, cl::ZeroOrMore, cl::init(false));
 
-static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization",
-    cl::Hidden, cl::ZeroOrMore, cl::init(true));
-
 // Check if the scheduler should penalize instructions that are available to
 // early due to a zero-latency dependence.
 static cl::opt<bool> CheckEarlyAvail("check-early-avail", cl::Hidden,
     cl::ZeroOrMore, cl::init(true));
 
-using namespace llvm;
-
-#define DEBUG_TYPE "machine-scheduler"
-
-namespace {
-class HexagonCallMutation : public ScheduleDAGMutation {
-public:
-  void apply(ScheduleDAGInstrs *DAG) override;
-private:
-  bool shouldTFRICallBind(const HexagonInstrInfo &HII,
-                          const SUnit &Inst1, const SUnit &Inst2) const;
-};
-} // end anonymous namespace
-
-// Check if a call and subsequent A2_tfrpi instructions should maintain
-// scheduling affinity. We are looking for the TFRI to be consumed in
-// the next instruction. This should help reduce the instances of
-// double register pairs being allocated and scheduled before a call
-// when not used until after the call. This situation is exacerbated
-// by the fact that we allocate the pair from the callee saves list,
-// leading to excess spills and restores.
-bool HexagonCallMutation::shouldTFRICallBind(const HexagonInstrInfo &HII,
-      const SUnit &Inst1, const SUnit &Inst2) const {
-  if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
-    return false;
-
-  // TypeXTYPE are 64 bit operations.
-  unsigned Type = HII.getType(*Inst2.getInstr());
-  if (Type == HexagonII::TypeS_2op || Type == HexagonII::TypeS_3op ||
-    Type == HexagonII::TypeALU64 || Type == HexagonII::TypeM)
-    return true;
-  return false;
-}
-
-void HexagonCallMutation::apply(ScheduleDAGInstrs *DAG) {
-  SUnit* LastSequentialCall = nullptr;
-  unsigned VRegHoldingRet = 0;
-  unsigned RetRegister;
-  SUnit* LastUseOfRet = nullptr;
-  auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo();
-  auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
-
-  // Currently we only catch the situation when compare gets scheduled
-  // before preceding call.
-  for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) {
-    // Remember the call.
-    if (DAG->SUnits[su].getInstr()->isCall())
-      LastSequentialCall = &DAG->SUnits[su];
-    // Look for a compare that defines a predicate.
-    else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
-      DAG->SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier));
-    // Look for call and tfri* instructions.
-    else if (SchedPredsCloser && LastSequentialCall && su > 1 && su < e-1 &&
-             shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
-      DAG->SUnits[su].addPred(SDep(&DAG->SUnits[su-1], SDep::Barrier));
-    // Prevent redundant register copies between two calls, which are caused by
-    // both the return value and the argument for the next call being in %R0.
-    // Example:
-    //   1: <call1>
-    //   2: %VregX = COPY %R0
-    //   3: <use of %VregX>
-    //   4: %R0 = ...
-    //   5: <call2>
-    // The scheduler would often swap 3 and 4, so an additional register is
-    // needed. This code inserts a Barrier dependence between 3 & 4 to prevent
-    // this. The same applies for %D0 and %V0/%W0, which are also handled.
-    else if (SchedRetvalOptimization) {
-      const MachineInstr *MI = DAG->SUnits[su].getInstr();
-      if (MI->isCopy() && (MI->readsRegister(Hexagon::R0, &TRI) ||
-                           MI->readsRegister(Hexagon::V0, &TRI)))  {
-        // %vregX = COPY %R0
-        VRegHoldingRet = MI->getOperand(0).getReg();
-        RetRegister = MI->getOperand(1).getReg();
-        LastUseOfRet = nullptr;
-      } else if (VRegHoldingRet && MI->readsVirtualRegister(VRegHoldingRet))
-        // <use of %vregX>
-        LastUseOfRet = &DAG->SUnits[su];
-      else if (LastUseOfRet && MI->definesRegister(RetRegister, &TRI))
-        // %R0 = ...
-        DAG->SUnits[su].addPred(SDep(LastUseOfRet, SDep::Barrier));
-    }
-  }
-}
-
-
 /// Save the last formed packet
 void VLIWResourceModel::savePacket() {
   OldPacket = Packet;
@@ -254,12 +186,10 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) {
 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
 /// only includes instructions that have DAG nodes, not scheduling boundaries.
 void VLIWMachineScheduler::schedule() {
-  DEBUG(dbgs()
-        << "********** MI Converging Scheduling VLIW BB#" << BB->getNumber()
-        << " " << BB->getName()
-        << " in_func " << BB->getParent()->getFunction()->getName()
-        << " at loop depth "  << MLI->getLoopDepth(BB)
-        << " \n");
+  DEBUG(dbgs() << "********** MI Converging Scheduling VLIW "
+               << printMBBReference(*BB) << " " << BB->getName() << " in_func "
+               << BB->getParent()->getName() << " at loop depth "
+               << MLI->getLoopDepth(BB) << " \n");
 
   buildDAGWithRegPressure();
 
@@ -305,8 +235,8 @@ void VLIWMachineScheduler::schedule() {
   placeDebugValues();
 
   DEBUG({
-    unsigned BBNum = begin()->getParent()->getNumber();
-    dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
+    dbgs() << "*** Final schedule for "
+           << printMBBReference(*begin()->getParent()) << " ***\n";
     dumpSchedule();
     dbgs() << '\n';
   });
@@ -334,11 +264,8 @@ void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) {
   Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
   Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
 
-  assert((!llvm::ForceTopDown || !llvm::ForceBottomUp) &&
+  assert((!ForceTopDown || !ForceBottomUp) &&
          "-misched-topdown incompatible with -misched-bottomup");
-
-  DAG->addMutation(make_unique<HexagonSubtarget::HexagonDAGMutation>());
-  DAG->addMutation(make_unique<HexagonCallMutation>());
 }
 
 void ConvergingVLIWScheduler::releaseTopNode(SUnit *SU) {
@@ -419,7 +346,8 @@ void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpCycle() {
   unsigned Width = SchedModel->getIssueWidth();
   IssueCount = (IssueCount <= Width) ? 0 : IssueCount - Width;
 
-  assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
+  assert(MinReadyCycle < std::numeric_limits<unsigned>::max() &&
+         "MinReadyCycle uninitialized");
   unsigned NextCycle = std::max(CurrCycle + 1, MinReadyCycle);
 
   if (!HazardRec->isEnabled()) {
@@ -474,7 +402,7 @@ void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpNode(SUnit *SU) {
 void ConvergingVLIWScheduler::VLIWSchedBoundary::releasePending() {
   // If the available queue is empty, it is safe to reset MinReadyCycle.
   if (Available.empty())
-    MinReadyCycle = UINT_MAX;
+    MinReadyCycle = std::numeric_limits<unsigned>::max();
 
   // Check to see if any of the pending instructions are ready to issue.  If
   // so, add them to the available queue.
@@ -974,7 +902,7 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
     return nullptr;
   }
   SUnit *SU;
-  if (llvm::ForceTopDown) {
+  if (ForceTopDown) {
     SU = Top.pickOnlyChoice();
     if (!SU) {
       SchedCandidate TopCand;
@@ -985,7 +913,7 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
       SU = TopCand.SU;
     }
     IsTopNode = true;
-  } else if (llvm::ForceBottomUp) {
+  } else if (ForceBottomUp) {
     SU = Bot.pickOnlyChoice();
     if (!SU) {
       SchedCandidate BotCand;
diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.h b/lib/Target/Hexagon/HexagonMachineScheduler.h
index 810abf38863d..bf7fe2d484a2 100644
--- a/lib/Target/Hexagon/HexagonMachineScheduler.h
+++ b/lib/Target/Hexagon/HexagonMachineScheduler.h
@@ -1,4 +1,4 @@
-//===-- HexagonMachineScheduler.h - Custom Hexagon MI scheduler.      ----===//
+//===- HexagonMachineScheduler.h - Custom Hexagon MI scheduler --*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -14,25 +14,25 @@
 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
 
-#include "llvm/ADT/PriorityQueue.h"
-#include "llvm/Analysis/AliasAnalysis.h"
-#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/CodeGen/DFAPacketizer.h"
 #include "llvm/CodeGen/MachineScheduler.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/RegisterClassInfo.h"
 #include "llvm/CodeGen/RegisterPressure.h"
-#include "llvm/CodeGen/ResourcePriorityQueue.h"
-#include "llvm/CodeGen/ScheduleDAGInstrs.h"
 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
-
-using namespace llvm;
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <limits>
+#include <memory>
+#include <vector>
 
 namespace llvm {
 
+class SUnit;
+
 class VLIWResourceModel {
   /// ResourcesModel - Represents VLIW state.
   /// Not limited to VLIW targets per se, but assumes
@@ -43,19 +43,18 @@ class VLIWResourceModel {
 
   /// Local packet/bundle model. Purely
   /// internal to the MI schedulre at the time.
-  std::vector<SUnit*> Packet;
+  std::vector<SUnit *> Packet;
 
   /// Total packets created.
-  unsigned TotalPackets;
+  unsigned TotalPackets = 0;
 
 public:
   /// Save the last formed packet.
-  std::vector<SUnit*> OldPacket;
+  std::vector<SUnit *> OldPacket;
 
-public:
   VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
-      : SchedModel(SM), TotalPackets(0) {
-  ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI);
+      : SchedModel(SM) {
+    ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI);
 
     // This hard requirement could be relaxed,
     // but for now do not let it proceed.
@@ -89,7 +88,6 @@ public:
   bool reserveResources(SUnit *SU);
   void savePacket();
   unsigned getTotalPackets() const { return TotalPackets; }
-
   bool isInPacket(SUnit *SU) const { return is_contained(Packet, SU); }
 };
 
@@ -114,20 +112,19 @@ public:
 /// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics
 /// to balance the schedule.
 class ConvergingVLIWScheduler : public MachineSchedStrategy {
-
   /// Store the state used by ConvergingVLIWScheduler heuristics, required
   ///  for the lifetime of one invocation of pickNode().
   struct SchedCandidate {
     // The best SUnit candidate.
-    SUnit *SU;
+    SUnit *SU = nullptr;
 
     // Register pressure values for the best candidate.
     RegPressureDelta RPDelta;
 
     // Best scheduling cost.
-    int SCost;
+    int SCost = 0;
 
-    SchedCandidate(): SU(nullptr), SCost(0) {}
+    SchedCandidate() = default;
   };
   /// Represent the type of SchedCandidate found within a single queue.
   enum CandResult {
@@ -138,33 +135,30 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
   /// current cycle in whichever direction at has moved, and maintains the state
   /// of "hazards" and other interlocks at the current cycle.
   struct VLIWSchedBoundary {
-    VLIWMachineScheduler *DAG;
-    const TargetSchedModel *SchedModel;
+    VLIWMachineScheduler *DAG = nullptr;
+    const TargetSchedModel *SchedModel = nullptr;
 
     ReadyQueue Available;
     ReadyQueue Pending;
-    bool CheckPending;
+    bool CheckPending = false;
 
-    ScheduleHazardRecognizer *HazardRec;
-    VLIWResourceModel *ResourceModel;
+    ScheduleHazardRecognizer *HazardRec = nullptr;
+    VLIWResourceModel *ResourceModel = nullptr;
 
-    unsigned CurrCycle;
-    unsigned IssueCount;
+    unsigned CurrCycle = 0;
+    unsigned IssueCount = 0;
 
     /// MinReadyCycle - Cycle of the soonest available instruction.
-    unsigned MinReadyCycle;
+    unsigned MinReadyCycle = std::numeric_limits<unsigned>::max();
 
     // Remember the greatest min operand latency.
-    unsigned MaxMinLatency;
+    unsigned MaxMinLatency = 0;
 
     /// Pending queues extend the ready queues with the same ID and the
     /// PendingFlag set.
-    VLIWSchedBoundary(unsigned ID, const Twine &Name):
-      DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
-      Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P"),
-      CheckPending(false), HazardRec(nullptr), ResourceModel(nullptr),
-      CurrCycle(0), IssueCount(0),
-      MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
+    VLIWSchedBoundary(unsigned ID, const Twine &Name)
+        : Available(ID, Name+".A"),
+          Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P") {}
 
     ~VLIWSchedBoundary() {
       delete ResourceModel;
@@ -196,8 +190,8 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
     SUnit *pickOnlyChoice();
   };
 
-  VLIWMachineScheduler *DAG;
-  const TargetSchedModel *SchedModel;
+  VLIWMachineScheduler *DAG = nullptr;
+  const TargetSchedModel *SchedModel = nullptr;
 
   // State of the top and bottom scheduled instruction boundaries.
   VLIWSchedBoundary Top;
@@ -211,9 +205,7 @@ public:
     LogMaxQID = 2
   };
 
-  ConvergingVLIWScheduler()
-    : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
-      Bot(BotQID, "BotQ") {}
+  ConvergingVLIWScheduler() : Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
 
   void initialize(ScheduleDAGMI *dag) override;
 
@@ -249,7 +241,6 @@ protected:
 #endif
 };
 
-} // namespace
+} // end namespace llvm
 
-
-#endif
+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
diff --git a/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td b/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td
index 0b4ac14c7a47..b7b0de0efaea 100644
--- a/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td
+++ b/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td
@@ -8,147 +8,123 @@
 //===----------------------------------------------------------------------===//
 
 multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
-           (MI VectorRegs:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, IntRegs:$src2),
-           (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
+           (MI HvxVR:$src1, IntRegs:$src2)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
+           (MI HvxVR:$src1, IntRegs:$src2)>;
 }
 
 multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3),
-           (MI VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3),
-           (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
+           (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
+                                            IntRegsLow8:$src3),
+           (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
 }
 
 multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2),
-           (MI VectorRegs:$src1, VectorRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2),
-           (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
+           (MI HvxVR:$src1, HvxVR:$src2)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
+           (MI HvxVR:$src1, HvxVR:$src2)>;
 }
 
 multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2),
-           (MI VecDblRegs:$src1, VecDblRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2),
-           (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
+           (MI HvxWR:$src1, HvxWR:$src2)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
+           (MI HvxWR:$src1, HvxWR:$src2)>;
 }
 
 multiclass T_WVV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
-           (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
-           (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
+           (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
+                                            HvxVR:$src3),
+           (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
 }
 
 multiclass T_WR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
-           (MI VecDblRegs:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, IntRegs:$src2),
-           (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
+           (MI HvxWR:$src1, IntRegs:$src2)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, IntRegs:$src2),
+           (MI HvxWR:$src1, IntRegs:$src2)>;
 }
 
 multiclass T_WWR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
-           (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3),
-           (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
+           (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
+                                            IntRegs:$src3),
+           (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
 }
 
 multiclass T_VVR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
-           (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3),
-           (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
+           (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
+                                            IntRegs:$src3),
+           (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
 }
 
 multiclass T_ZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
-           (MI VecPredRegs:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, IntRegs:$src2),
-           (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, IntRegs:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
+           (MI HvxQR:$src1, IntRegs:$src2)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
+           (MI HvxQR:$src1, IntRegs:$src2)>;
 }
 
 multiclass T_VZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
-           (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3),
-           (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
+           (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
+                                            IntRegs:$src3),
+           (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
 }
 
 multiclass T_ZV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2),
-           (MI VecPredRegs:$src1, VectorRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2),
-           (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxQR:$src1, HvxVR:$src2),
+           (MI HvxQR:$src1, HvxVR:$src2)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2),
+           (MI HvxQR:$src1, HvxVR:$src2)>;
 }
 
 multiclass T_R_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
   def: Pat<(IntID IntRegs:$src1),
-           (MI IntRegs:$src1)>,
-       Requires<[UseHVXSgl]>;
+           (MI IntRegs:$src1)>;
   def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
-           (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>,
-       Requires<[UseHVXDbl]>;
+           (MI IntRegs:$src1)>;
 }
 
 multiclass T_ZZ_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2),
-           (MI VecPredRegs:$src1, VecPredRegs:$src2)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2),
-           (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
+           (MI HvxQR:$src1, HvxQR:$src2)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
+           (MI HvxQR:$src1, HvxQR:$src2)>;
 }
 
 multiclass T_VVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3),
-           (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3),
-           (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
+           (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
+                                            imm:$src3),
+           (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
 }
 
 multiclass T_VVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4),
-           (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4),
-           (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
+           (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
+                                            HvxVR:$src3, imm:$src4),
+           (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
 }
 
 multiclass T_WVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
-  def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4),
-           (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>,
-       Requires<[UseHVXSgl]>;
-  def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4),
-           (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>,
-       Requires<[UseHVXDbl]>;
+  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
+           (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
+  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
+                                            HvxVR:$src3, imm:$src4),
+           (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
 }
 
 def : T_R_pat <S6_vsplatrbp, int_hexagon_S6_vsplatrbp>;
diff --git a/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td b/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td
new file mode 100644
index 000000000000..718d3ac7d45a
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td
@@ -0,0 +1,86 @@
+//===--- HexagonMapAsm2IntrinV65.gen.td -----------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65T]>;
+def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2), (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2), (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vavguwrnd HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vavguwrnd_128B HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2), (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2), (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vnavgb HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vnavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpabuu_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpauhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpsuhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpyh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpyuhe HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpyuhe_128B HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vmpyuhe_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vprefixqb HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vprefixqb_128B HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vprefixqh HvxQR:$src1), (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vprefixqh_128B HvxQR:$src1), (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vprefixqw_128B HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vrmpyub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vrmpybub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vdd0),      (V6_vdd0)>, Requires<[HasV65T, UseHVX]>;
+def: Pat<(int_hexagon_V6_vdd0_128B), (V6_vdd0)>, Requires<[HasV65T, UseHVX]>;
diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp
index e93f075f4ccd..ffa447cc1311 100644
--- a/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -1,4 +1,4 @@
-//===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
+//===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -19,54 +19,60 @@
 // all, it collapses compare and jump instruction into a new valu jump
 // intstructions.
 //
-//
 //===----------------------------------------------------------------------===//
+
 #include "Hexagon.h"
 #include "HexagonInstrInfo.h"
-#include "HexagonMachineFunctionInfo.h"
 #include "HexagonRegisterInfo.h"
-#include "HexagonSubtarget.h"
-#include "HexagonTargetMachine.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/CodeGen/LiveVariables.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/ScheduleDAGInstrs.h"
-#include "llvm/PassSupport.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/BranchProbability.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include <cassert>
+#include <cstdint>
+#include <iterator>
+
 using namespace llvm;
 
 #define DEBUG_TYPE "hexagon-nvj"
 
 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
 
-static cl::opt<int>
-DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
-  "Maximum number of predicated jumps to be converted to New Value Jump"));
+static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden,
+    cl::desc("Maximum number of predicated jumps to be converted to "
+    "New Value Jump"));
 
 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
     cl::ZeroOrMore, cl::init(false),
     cl::desc("Disable New Value Jumps"));
 
 namespace llvm {
-  FunctionPass *createHexagonNewValueJump();
-  void initializeHexagonNewValueJumpPass(PassRegistry&);
-}
 
+FunctionPass *createHexagonNewValueJump();
+void initializeHexagonNewValueJumpPass(PassRegistry&);
+
+} // end namespace llvm
 
 namespace {
-  struct HexagonNewValueJump : public MachineFunctionPass {
-    const HexagonInstrInfo    *QII;
-    const HexagonRegisterInfo *QRI;
 
-  public:
+  struct HexagonNewValueJump : public MachineFunctionPass {
     static char ID;
 
     HexagonNewValueJump() : MachineFunctionPass(ID) {}
@@ -79,19 +85,23 @@ namespace {
     StringRef getPassName() const override { return "Hexagon NewValueJump"; }
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
+
     MachineFunctionProperties getRequiredProperties() const override {
       return MachineFunctionProperties().set(
           MachineFunctionProperties::Property::NoVRegs);
     }
 
   private:
+    const HexagonInstrInfo *QII;
+    const HexagonRegisterInfo *QRI;
+
     /// \brief A handle to the branch probability pass.
     const MachineBranchProbabilityInfo *MBPI;
 
     bool isNewValueJumpCandidate(const MachineInstr &MI) const;
   };
 
-} // end of anonymous namespace
+} // end anonymous namespace
 
 char HexagonNewValueJump::ID = 0;
 
@@ -101,7 +111,6 @@ INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
                     "Hexagon NewValueJump", false, false)
 
-
 // We have identified this II could be feeder to NVJ,
 // verify that it can be.
 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
@@ -110,7 +119,6 @@ static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
                                       MachineBasicBlock::iterator end,
                                       MachineBasicBlock::iterator skip,
                                       MachineFunction &MF) {
-
   // Predicated instruction can not be feeder to NVJ.
   if (QII->isPredicated(*II))
     return false;
@@ -121,9 +129,9 @@ static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
   // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
   // before the callsite of this function
   // But we can not as it comes in the following fashion.
-  //    %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
-  //    %R0<def> = KILL %R0, %D0<imp-use,kill>
-  //    %P0<def> = CMPEQri %R0<kill>, 0
+  //    %d0 = Hexagon_S2_lsr_r_p killed %d0, killed %r2
+  //    %r0 = KILL %r0, implicit killed %d0
+  //    %p0 = CMPEQri killed %r0, 0
   // Hence, we need to check if it's a KILL instruction.
   if (II->getOpcode() == TargetOpcode::KILL)
     return false;
@@ -131,6 +139,9 @@ static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
   if (II->isImplicitDef())
     return false;
 
+  if (QII->isSolo(*II))
+    return false;
+
   // Make sure there there is no 'def' or 'use' of any of the uses of
   // feeder insn between it's definition, this MI and jump, jmpInst
   // skipping compare, cmpInst.
@@ -145,16 +156,16 @@ static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
   //    p0 = cmp.eq(r21, #0)
   //    if (p0.new) jump:t .LBB29_45
   // and result WAR hazards if converted to New Value Jump.
-
   for (unsigned i = 0; i < II->getNumOperands(); ++i) {
     if (II->getOperand(i).isReg() &&
         (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
       MachineBasicBlock::iterator localII = II;
       ++localII;
       unsigned Reg = II->getOperand(i).getReg();
-      for (MachineBasicBlock::iterator localBegin = localII;
-                        localBegin != end; ++localBegin) {
-        if (localBegin == skip ) continue;
+      for (MachineBasicBlock::iterator localBegin = localII; localBegin != end;
+           ++localBegin) {
+        if (localBegin == skip)
+          continue;
         // Check for Subregisters too.
         if (localBegin->modifiesRegister(Reg, TRI) ||
             localBegin->readsRegister(Reg, TRI))
@@ -171,9 +182,8 @@ static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
 // 2. feeder to the compare instruction can be moved before jump.
 static bool commonChecksToProhibitNewValueJump(bool afterRA,
                           MachineBasicBlock::iterator MII) {
-
   // If store in path, bail out.
-  if (MII->getDesc().mayStore())
+  if (MII->mayStore())
     return false;
 
   // if call in path, bail out.
@@ -186,13 +196,13 @@ static bool commonChecksToProhibitNewValueJump(bool afterRA,
     // to new value jump. If they are in the path, bail out.
     // KILL sets kill flag on the opcode. It also sets up a
     // single register, out of pair.
-    //    %D0<def> = S2_lsr_r_p %D0<kill>, %R2<kill>
-    //    %R0<def> = KILL %R0, %D0<imp-use,kill>
-    //    %P0<def> = C2_cmpeqi %R0<kill>, 0
+    //    %d0 = S2_lsr_r_p killed %d0, killed %r2
+    //    %r0 = KILL %r0, implicit killed %d0
+    //    %p0 = C2_cmpeqi killed %r0, 0
     // PHI can be anything after RA.
     // COPY can remateriaze things in between feeder, compare and nvj.
     if (MII->getOpcode() == TargetOpcode::KILL ||
-        MII->getOpcode() == TargetOpcode::PHI  ||
+        MII->getOpcode() == TargetOpcode::PHI ||
         MII->getOpcode() == TargetOpcode::COPY)
       return false;
 
@@ -216,21 +226,27 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
                                      bool optLocation,
                                      MachineBasicBlock::iterator end,
                                      MachineFunction &MF) {
-
   MachineInstr &MI = *II;
 
   // If the second operand of the compare is an imm, make sure it's in the
   // range specified by the arch.
   if (!secondReg) {
-    int64_t v = MI.getOperand(2).getImm();
+    const MachineOperand &Op2 = MI.getOperand(2);
+    if (!Op2.isImm())
+      return false;
+
+    int64_t v = Op2.getImm();
     bool Valid = false;
 
     switch (MI.getOpcode()) {
       case Hexagon::C2_cmpeqi:
+      case Hexagon::C4_cmpneqi:
       case Hexagon::C2_cmpgti:
+      case Hexagon::C4_cmpltei:
         Valid = (isUInt<5>(v) || v == -1);
         break;
       case Hexagon::C2_cmpgtui:
+      case Hexagon::C4_cmplteui:
         Valid = isUInt<5>(v);
         break;
       case Hexagon::S2_tstbit_i:
@@ -267,9 +283,8 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
 
   // Walk the instructions after the compare (predicate def) to the jump,
   // and satisfy the following conditions.
-  ++II ;
-  for (MachineBasicBlock::iterator localII = II; localII != end;
-       ++localII) {
+  ++II;
+  for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
     if (localII->isDebugValue())
       continue;
 
@@ -298,7 +313,6 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
   return true;
 }
 
-
 // Given a compare operator, return a matching New Value Jump compare operator.
 // Make sure that MI here is included in isNewValueJumpCandidate.
 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
@@ -319,41 +333,40 @@ static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
       return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
                    : Hexagon::J4_cmpeq_t_jumpnv_nt;
 
-    case Hexagon::C2_cmpeqi: {
+    case Hexagon::C2_cmpeqi:
       if (reg >= 0)
         return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
                      : Hexagon::J4_cmpeqi_t_jumpnv_nt;
-      else
-        return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
-                     : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
-    }
+      return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
+                   : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
+
+    case Hexagon::C4_cmpneqi:
+      if (reg >= 0)
+        return taken ? Hexagon::J4_cmpeqi_f_jumpnv_t
+                     : Hexagon::J4_cmpeqi_f_jumpnv_nt;
+      return taken ? Hexagon::J4_cmpeqn1_f_jumpnv_t :
+                     Hexagon::J4_cmpeqn1_f_jumpnv_nt;
 
-    case Hexagon::C2_cmpgt: {
+    case Hexagon::C2_cmpgt:
       if (secondRegNewified)
         return taken ? Hexagon::J4_cmplt_t_jumpnv_t
                      : Hexagon::J4_cmplt_t_jumpnv_nt;
-      else
-        return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
-                     : Hexagon::J4_cmpgt_t_jumpnv_nt;
-    }
+      return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
+                   : Hexagon::J4_cmpgt_t_jumpnv_nt;
 
-    case Hexagon::C2_cmpgti: {
+    case Hexagon::C2_cmpgti:
       if (reg >= 0)
         return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
                      : Hexagon::J4_cmpgti_t_jumpnv_nt;
-      else
-        return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
-                     : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
-    }
+      return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
+                   : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
 
-    case Hexagon::C2_cmpgtu: {
+    case Hexagon::C2_cmpgtu:
       if (secondRegNewified)
         return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
                      : Hexagon::J4_cmpltu_t_jumpnv_nt;
-      else
-        return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
-                     : Hexagon::J4_cmpgtu_t_jumpnv_nt;
-    }
+      return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
+                   : Hexagon::J4_cmpgtu_t_jumpnv_nt;
 
     case Hexagon::C2_cmpgtui:
       return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
@@ -377,6 +390,17 @@ static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
       return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
                    : Hexagon::J4_cmpgtu_f_jumpnv_nt;
 
+    case Hexagon::C4_cmpltei:
+      if (reg >= 0)
+        return taken ? Hexagon::J4_cmpgti_f_jumpnv_t
+                     : Hexagon::J4_cmpgti_f_jumpnv_nt;
+      return taken ? Hexagon::J4_cmpgtn1_f_jumpnv_t
+                   : Hexagon::J4_cmpgtn1_f_jumpnv_nt;
+
+    case Hexagon::C4_cmplteui:
+      return taken ? Hexagon::J4_cmpgtui_f_jumpnv_t
+                   : Hexagon::J4_cmpgtui_f_jumpnv_nt;
+
     default:
        llvm_unreachable("Could not find matching New Value Jump instruction.");
   }
@@ -394,8 +418,11 @@ bool HexagonNewValueJump::isNewValueJumpCandidate(
   case Hexagon::C2_cmpgtu:
   case Hexagon::C2_cmpgtui:
   case Hexagon::C4_cmpneq:
+  case Hexagon::C4_cmpneqi:
   case Hexagon::C4_cmplte:
   case Hexagon::C4_cmplteu:
+  case Hexagon::C4_cmpltei:
+  case Hexagon::C4_cmplteui:
     return true;
 
   default:
@@ -403,14 +430,11 @@ bool HexagonNewValueJump::isNewValueJumpCandidate(
   }
 }
 
-
 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
-
   DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
-               << "********** Function: "
-               << MF.getName() << "\n");
+               << "********** Function: " << MF.getName() << "\n");
 
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   // If we move NewValueJump before register allocation we'll need live variable
@@ -430,11 +454,10 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
 
   // Loop through all the bb's of the function
   for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
-        MBBb != MBBe; ++MBBb) {
+       MBBb != MBBe; ++MBBb) {
     MachineBasicBlock *MBB = &*MBBb;
 
-    DEBUG(dbgs() << "** dumping bb ** "
-                 << MBB->getNumber() << "\n");
+    DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n");
     DEBUG(MBB->dump());
     DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
     bool foundJump    = false;
@@ -452,7 +475,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
     bool isSecondOpNewified = false;
     // Traverse the basic block - bottom up
     for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
-             MII != E;) {
+         MII != E;) {
       MachineInstr &MI = *--MII;
       if (MI.isDebugValue()) {
         continue;
@@ -495,11 +518,11 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
         // at the BB level.
         bool predLive = false;
         for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
-                            SIE = MBB->succ_end(); SI != SIE; ++SI) {
-          MachineBasicBlock* succMBB = *SI;
-         if (succMBB->isLiveIn(predReg)) {
+                                                    SIE = MBB->succ_end();
+             SI != SIE; ++SI) {
+          MachineBasicBlock *succMBB = *SI;
+          if (succMBB->isLiveIn(predReg))
             predLive = true;
-          }
         }
         if (predLive)
           break;
@@ -524,10 +547,8 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
 
       if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
           MI.getOperand(0).getReg() == predReg) {
-
         // Not all compares can be new value compare. Arch Spec: 7.6.1.1
         if (isNewValueJumpCandidate(MI)) {
-
           assert(
               (MI.getDesc().isCompare()) &&
               "Only compare instruction can be collapsed into New Value Jump");
@@ -554,7 +575,6 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
       }
 
       if (foundCompare && foundJump) {
-
         // If "common" checks fail, bail out on this BB.
         if (!commonChecksToProhibitNewValueJump(afterRA, MII))
           break;
@@ -584,9 +604,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
               foundFeeder = true;
           }
 
-          if (!foundFeeder &&
-               isSecondOpReg &&
-               feederReg == (unsigned) cmpOp2)
+          if (!foundFeeder && isSecondOpReg && feederReg == (unsigned)cmpOp2)
             if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
               break;
 
@@ -595,7 +613,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
             // to newify, swap the operands.
             unsigned COp = cmpInstr->getOpcode();
             if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) &&
-                (feederReg == (unsigned) cmpOp2)) {
+                (feederReg == (unsigned)cmpOp2)) {
               unsigned tmp = cmpReg1;
               cmpReg1 = cmpOp2;
               cmpOp2 = tmp;
@@ -654,18 +672,16 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
             opc = QII->getInvertedPredicatedOpcode(opc);
 
           if (isSecondOpReg)
-            NewMI = BuildMI(*MBB, jmpPos, dl,
-                                  QII->get(opc))
-                                    .addReg(cmpReg1, getKillRegState(MO1IsKill))
-                                    .addReg(cmpOp2, getKillRegState(MO2IsKill))
-                                    .addMBB(jmpTarget);
+            NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
+                        .addReg(cmpReg1, getKillRegState(MO1IsKill))
+                        .addReg(cmpOp2, getKillRegState(MO2IsKill))
+                        .addMBB(jmpTarget);
 
           else
-            NewMI = BuildMI(*MBB, jmpPos, dl,
-                                  QII->get(opc))
-                                    .addReg(cmpReg1, getKillRegState(MO1IsKill))
-                                    .addImm(cmpOp2)
-                                    .addMBB(jmpTarget);
+            NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
+                        .addReg(cmpReg1, getKillRegState(MO1IsKill))
+                        .addImm(cmpOp2)
+                        .addMBB(jmpTarget);
 
           assert(NewMI && "New Value Jump Instruction Not created!");
           (void)NewMI;
@@ -686,7 +702,6 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
   }
 
   return true;
-
 }
 
 FunctionPass *llvm::createHexagonNewValueJump() {
diff --git a/lib/Target/Hexagon/HexagonOperands.td b/lib/Target/Hexagon/HexagonOperands.td
index f80e0ef9e39f..232946ec1579 100644
--- a/lib/Target/Hexagon/HexagonOperands.td
+++ b/lib/Target/Hexagon/HexagonOperands.td
@@ -29,17 +29,5 @@ def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; }
 def n1ConstOperand : AsmOperandClass { let Name = "n1Const"; }
 def n1Const : Operand<i32> { let ParserMatchClass = n1ConstOperand; }
 
-// This complex pattern exists only to create a machine instruction operand
-// of type "frame index". There doesn't seem to be a way to do that directly
-// in the patterns.
-def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;
-
-// These complex patterns are not strictly necessary, since global address
-// folding will happen during DAG combining. For distinguishing between GA
-// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used.
-def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
-def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
-
-
 def bblabel : Operand<i32>;
 def bbl     : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">;
diff --git a/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/lib/Target/Hexagon/HexagonOptAddrMode.cpp
index 374ffa3799b0..4738a4d32409 100644
--- a/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+++ b/lib/Target/Hexagon/HexagonOptAddrMode.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonOptAddrMode.cpp -------------------------------------------===//
+//===- HexagonOptAddrMode.cpp ---------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -15,6 +15,8 @@
 #include "MCTargetDesc/HexagonBaseInfo.h"
 #include "RDFGraph.h"
 #include "RDFLiveness.h"
+#include "RDFRegisters.h"
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
@@ -25,6 +27,7 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
@@ -36,16 +39,18 @@
 
 #define DEBUG_TYPE "opt-addr-mode"
 
+using namespace llvm;
+using namespace rdf;
+
 static cl::opt<int> CodeGrowthLimit("hexagon-amode-growth-limit",
   cl::Hidden, cl::init(0), cl::desc("Code growth limit for address mode "
   "optimization"));
 
-using namespace llvm;
-using namespace rdf;
-
 namespace llvm {
+
   FunctionPass *createHexagonOptAddrMode();
   void initializeHexagonOptAddrModePass(PassRegistry&);
+
 } // end namespace llvm
 
 namespace {
@@ -54,9 +59,7 @@ class HexagonOptAddrMode : public MachineFunctionPass {
 public:
   static char ID;
 
-  HexagonOptAddrMode()
-      : MachineFunctionPass(ID), HII(nullptr), MDT(nullptr), DFG(nullptr),
-        LV(nullptr) {}
+  HexagonOptAddrMode() : MachineFunctionPass(ID) {}
 
   StringRef getPassName() const override {
     return "Optimize addressing mode of load/store";
@@ -72,13 +75,14 @@ public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 private:
-  typedef DenseSet<MachineInstr *> MISetType;
-  typedef DenseMap<MachineInstr *, bool> InstrEvalMap;
-  const HexagonInstrInfo *HII;
-  MachineDominatorTree *MDT;
-  DataFlowGraph *DFG;
+  using MISetType = DenseSet<MachineInstr *>;
+  using InstrEvalMap = DenseMap<MachineInstr *, bool>;
+
+  const HexagonInstrInfo *HII = nullptr;
+  MachineDominatorTree *MDT = nullptr;
+  DataFlowGraph *DFG = nullptr;
   DataFlowGraph::DefStackMap DefM;
-  Liveness *LV;
+  Liveness *LV = nullptr;
   MISetType Deleted;
 
   bool processBlock(NodeAddr<BlockNode *> BA);
@@ -124,10 +128,10 @@ bool HexagonOptAddrMode::hasRepForm(MachineInstr &MI, unsigned TfrDefR) {
 
   if (HII->getAddrMode(MI) == HexagonII::BaseRegOffset)
     // Tranform to Absolute plus register offset.
-    return (HII->getBaseWithLongOffset(MI) >= 0);
+    return (HII->changeAddrMode_rr_ur(MI) >= 0);
   else if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset)
     // Tranform to absolute addressing mode.
-    return (HII->getAbsoluteForm(MI) >= 0);
+    return (HII->changeAddrMode_io_abs(MI) >= 0);
 
   return false;
 }
@@ -333,7 +337,7 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
 
   if (ImmOpNum == 1) {
     if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) {
-      short NewOpCode = HII->getBaseWithLongOffset(*OldMI);
+      short NewOpCode = HII->changeAddrMode_rr_ur(*OldMI);
       assert(NewOpCode >= 0 && "Invalid New opcode\n");
       MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
       MIB.add(OldMI->getOperand(0));
@@ -343,7 +347,7 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
       OpStart = 4;
       Changed = true;
     } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) {
-      short NewOpCode = HII->getAbsoluteForm(*OldMI);
+      short NewOpCode = HII->changeAddrMode_io_abs(*OldMI);
       assert(NewOpCode >= 0 && "Invalid New opcode\n");
       MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
                 .add(OldMI->getOperand(0));
@@ -357,9 +361,9 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
       Changed = false;
 
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) {
-    short NewOpCode = HII->xformRegToImmOffset(*OldMI);
+    short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
     assert(NewOpCode >= 0 && "Invalid New opcode\n");
     MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
     MIB.add(OldMI->getOperand(0));
@@ -368,7 +372,7 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
     OpStart = 4;
     Changed = true;
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   }
 
   if (Changed)
@@ -390,7 +394,7 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
   MachineInstrBuilder MIB;
   if (ImmOpNum == 0) {
     if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) {
-      short NewOpCode = HII->getBaseWithLongOffset(*OldMI);
+      short NewOpCode = HII->changeAddrMode_rr_ur(*OldMI);
       assert(NewOpCode >= 0 && "Invalid New opcode\n");
       MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
       MIB.add(OldMI->getOperand(1));
@@ -399,7 +403,7 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
       MIB.add(OldMI->getOperand(3));
       OpStart = 4;
     } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) {
-      short NewOpCode = HII->getAbsoluteForm(*OldMI);
+      short NewOpCode = HII->changeAddrMode_io_abs(*OldMI);
       assert(NewOpCode >= 0 && "Invalid New opcode\n");
       MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
       const GlobalValue *GV = ImmOp.getGlobal();
@@ -410,18 +414,17 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
     }
     Changed = true;
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) {
-    short NewOpCode = HII->xformRegToImmOffset(*OldMI);
+    short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
     assert(NewOpCode >= 0 && "Invalid New opcode\n");
     MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
     MIB.add(OldMI->getOperand(0));
     MIB.add(ImmOp);
-    MIB.add(OldMI->getOperand(1));
-    OpStart = 2;
+    OpStart = 3;
     Changed = true;
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   }
   if (Changed)
     for (unsigned i = OpStart; i < OpEnd; ++i)
@@ -432,10 +435,10 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
 
 short HexagonOptAddrMode::getBaseWithLongOffset(const MachineInstr &MI) const {
   if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset) {
-    short TempOpCode = HII->getBaseWithRegOffset(MI);
-    return HII->getBaseWithLongOffset(TempOpCode);
-  } else
-    return HII->getBaseWithLongOffset(MI);
+    short TempOpCode = HII->changeAddrMode_io_rr(MI);
+    return HII->changeAddrMode_rr_ur(TempOpCode);
+  }
+  return HII->changeAddrMode_rr_ur(MI);
 }
 
 bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN,
@@ -458,7 +461,7 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN,
     DEBUG(dbgs() << "[InstrNode]: " << Print<NodeAddr<InstrNode *>>(UseIA, *DFG)
                  << "\n");
     MachineInstr *UseMI = UseIA.Addr->getCode();
-    DEBUG(dbgs() << "[MI <BB#" << UseMI->getParent()->getNumber()
+    DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent())
                  << ">]: " << *UseMI << "\n");
     const MCInstrDesc &UseMID = UseMI->getDesc();
     assert(HII->getAddrMode(*UseMI) == HexagonII::BaseImmOffset);
@@ -567,7 +570,7 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) {
 
       NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG);
       MachineInstr *UseMI = OwnerN.Addr->getCode();
-      DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber()
+      DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent())
                    << ">]: " << *UseMI << "\n");
 
       int UseMOnum = -1;
@@ -592,7 +595,7 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) {
 }
 
 bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   bool Changed = false;
diff --git a/lib/Target/Hexagon/HexagonPatterns.td b/lib/Target/Hexagon/HexagonPatterns.td
index 804a547d5b33..e2120d3de2ef 100644
--- a/lib/Target/Hexagon/HexagonPatterns.td
+++ b/lib/Target/Hexagon/HexagonPatterns.td
@@ -7,943 +7,1382 @@
 //
 //===----------------------------------------------------------------------===//
 
-// Pattern fragment that combines the value type and the register class
-// into a single parameter.
+// Table of contents:
+//     (0) Definitions
+//     (1) Immediates
+//     (2) Type casts
+//     (3) Extend/truncate
+//     (4) Logical
+//     (5) Compare
+//     (6) Select
+//     (7) Insert/extract
+//     (8) Shift/permute
+//     (9) Arithmetic/bitwise
+//    (10) Bit
+//    (11) PIC
+//    (12) Load
+//    (13) Store
+//    (14) Memop
+//    (15) Call
+//    (16) Branch
+//    (17) Misc
+
+// Guidelines (in no particular order):
+// 1. Avoid relying on pattern ordering to give preference to one pattern
+//    over another, prefer using AddedComplexity instead. The reason for
+//    this is to avoid unintended conseqeuences (caused by altering the
+//    order) when making changes. The current order of patterns in this
+//    file obviously does play some role, but none of the ordering was
+//    deliberately chosen (other than to create a logical structure of
+//    this file). When making changes, adding AddedComplexity to existing
+//    patterns may be needed.
+// 2. Maintain the logical structure of the file, try to put new patterns
+//    in designated sections.
+// 3. Do not use A2_combinew instruction directly, use Combinew fragment
+//    instead. It uses REG_SEQUENCE, which is more amenable to optimizations.
+// 4. Most selection macros are based on PatFrags. For DAGs that involve
+//    SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags
+//    whenever possible (see the Definitions section). When adding new
+//    macro, try to make is general to enable reuse across sections.
+// 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
+//    that the nested operation has only one use. Having it separated in case
+//    of multiple uses avoids duplication of (processor) work.
+// 6. The v4 vector instructions (64-bit) are treated as core instructions,
+//    for example, A2_vaddh is in the "arithmetic" section with A2_add.
+// 7. When adding a pattern for an instruction with a constant-extendable
+//    operand, allow all possible kinds of inputs for the immediate value
+//    (see AnyImm/anyimm and their variants in the Definitions section).
+
+
+// --(0) Definitions -----------------------------------------------------
+//
+
+// This complex pattern exists only to create a machine instruction operand
+// of type "frame index". There doesn't seem to be a way to do that directly
+// in the patterns.
+def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;
+
+// These complex patterns are not strictly necessary, since global address
+// folding will happen during DAG combining. For distinguishing between GA
+// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used.
+def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
+def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
+def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>;
+def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>;
+
+// Global address or a constant being a multiple of 2^n.
+def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>;
+def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>;
+def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>;
+def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>;
+
+
+// Type helper frags.
+def V2I1:   PatLeaf<(v2i1    PredRegs:$R)>;
+def V4I1:   PatLeaf<(v4i1    PredRegs:$R)>;
+def V8I1:   PatLeaf<(v8i1    PredRegs:$R)>;
+def V4I8:   PatLeaf<(v4i8    IntRegs:$R)>;
+def V2I16:  PatLeaf<(v2i16   IntRegs:$R)>;
+
+def V8I8:   PatLeaf<(v8i8    DoubleRegs:$R)>;
+def V4I16:  PatLeaf<(v4i16   DoubleRegs:$R)>;
+def V2I32:  PatLeaf<(v2i32   DoubleRegs:$R)>;
+
+def HQ8:    PatLeaf<(VecQ8   HvxQR:$R)>;
+def HQ16:   PatLeaf<(VecQ16  HvxQR:$R)>;
+def HQ32:   PatLeaf<(VecQ32  HvxQR:$R)>;
+
+def HVI8:   PatLeaf<(VecI8   HvxVR:$R)>;
+def HVI16:  PatLeaf<(VecI16  HvxVR:$R)>;
+def HVI32:  PatLeaf<(VecI32  HvxVR:$R)>;
+
+def HWI8:   PatLeaf<(VecPI8  HvxWR:$R)>;
+def HWI16:  PatLeaf<(VecPI16 HvxWR:$R)>;
+def HWI32:  PatLeaf<(VecPI32 HvxWR:$R)>;
 
 // Pattern fragments to extract the low and high subregisters from a
 // 64-bit value.
 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
 
-def IsOrAdd: PatFrag<(ops node:$Addr, node:$off),
-    (or node:$Addr, node:$off), [{ return isOrEquivalentToAdd(N); }]>;
-
-def Iss4_6 : PatLeaf<(i32 imm), [{
-  int32_t V = N->getSExtValue();
-  return isShiftedInt<4,6>(V);
+def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{
+  return isOrEquivalentToAdd(N);
 }]>;
 
-def Iss4_7 : PatLeaf<(i32 imm), [{
+def IsVecOff : PatLeaf<(i32 imm), [{
   int32_t V = N->getSExtValue();
-  return isShiftedInt<4,7>(V);
+  int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
+  assert(isPowerOf2_32(VecSize));
+  if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
+    return false;
+  int32_t L = Log2_32(VecSize);
+  return isInt<4>(V >> L);
 }]>;
 
-def IsPow2_32 : PatLeaf<(i32 imm), [{
+def IsPow2_32: PatLeaf<(i32 imm), [{
   uint32_t V = N->getZExtValue();
   return isPowerOf2_32(V);
 }]>;
 
-def IsPow2_64 : PatLeaf<(i64 imm), [{
+def IsPow2_64: PatLeaf<(i64 imm), [{
   uint64_t V = N->getZExtValue();
   return isPowerOf2_64(V);
 }]>;
 
-def IsNPow2_32 : PatLeaf<(i32 imm), [{
+def IsNPow2_32: PatLeaf<(i32 imm), [{
   uint32_t NV = ~N->getZExtValue();
   return isPowerOf2_32(NV);
 }]>;
 
-def IsPow2_64L : PatLeaf<(i64 imm), [{
+def IsPow2_64L: PatLeaf<(i64 imm), [{
   uint64_t V = N->getZExtValue();
   return isPowerOf2_64(V) && Log2_64(V) < 32;
 }]>;
 
-def IsPow2_64H : PatLeaf<(i64 imm), [{
+def IsPow2_64H: PatLeaf<(i64 imm), [{
   uint64_t V = N->getZExtValue();
   return isPowerOf2_64(V) && Log2_64(V) >= 32;
 }]>;
 
-def IsNPow2_64L : PatLeaf<(i64 imm), [{
+def IsNPow2_64L: PatLeaf<(i64 imm), [{
   uint64_t NV = ~N->getZExtValue();
   return isPowerOf2_64(NV) && Log2_64(NV) < 32;
 }]>;
 
-def IsNPow2_64H : PatLeaf<(i64 imm), [{
+def IsNPow2_64H: PatLeaf<(i64 imm), [{
   uint64_t NV = ~N->getZExtValue();
   return isPowerOf2_64(NV) && Log2_64(NV) >= 32;
 }]>;
 
-def SDEC1 : SDNodeXForm<imm, [{
+class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm),
+  "uint64_t V = N->getZExtValue();" #
+  "return isUInt<" # Width # ">(V) && V > " # Arg # ";"
+>;
+
+def SDEC1: SDNodeXForm<imm, [{
   int32_t V = N->getSExtValue();
   return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
 }]>;
 
-def UDEC1 : SDNodeXForm<imm, [{
+def UDEC1: SDNodeXForm<imm, [{
   uint32_t V = N->getZExtValue();
   assert(V >= 1);
   return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
 }]>;
 
-def UDEC32 : SDNodeXForm<imm, [{
+def UDEC32: SDNodeXForm<imm, [{
   uint32_t V = N->getZExtValue();
   assert(V >= 32);
   return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32);
 }]>;
 
-def Log2_32 : SDNodeXForm<imm, [{
+def Log2_32: SDNodeXForm<imm, [{
   uint32_t V = N->getZExtValue();
   return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32);
 }]>;
 
-def Log2_64 : SDNodeXForm<imm, [{
+def Log2_64: SDNodeXForm<imm, [{
   uint64_t V = N->getZExtValue();
   return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32);
 }]>;
 
-def LogN2_32 : SDNodeXForm<imm, [{
+def LogN2_32: SDNodeXForm<imm, [{
   uint32_t NV = ~N->getZExtValue();
   return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
 }]>;
 
-def LogN2_64 : SDNodeXForm<imm, [{
+def LogN2_64: SDNodeXForm<imm, [{
   uint64_t NV = ~N->getZExtValue();
   return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32);
 }]>;
 
-def ToZext64: OutPatFrag<(ops node:$Rs),
-  (i64 (A4_combineir 0, (i32 $Rs)))>;
-def ToSext64: OutPatFrag<(ops node:$Rs),
-  (i64 (A2_sxtw (i32 $Rs)))>;
+def NegImm8: SDNodeXForm<imm, [{
+  int8_t NV = -N->getSExtValue();
+  return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
+}]>;
 
+def NegImm16: SDNodeXForm<imm, [{
+  int16_t NV = -N->getSExtValue();
+  return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
+}]>;
 
-class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
-  : Pat<(i1 (OpNode I32:$src1, ImmPred:$src2)),
-        (MI IntRegs:$src1, ImmPred:$src2)>;
+def NegImm32: SDNodeXForm<imm, [{
+  int32_t NV = -N->getSExtValue();
+  return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
+}]>;
 
-def : T_CMP_pat <C2_cmpeqi,  seteq,  s10_0ImmPred>;
-def : T_CMP_pat <C2_cmpgti,  setgt,  s10_0ImmPred>;
-def : T_CMP_pat <C2_cmpgtui, setugt, u9_0ImmPred>;
 
-def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
-  [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
+// Helpers for type promotions/contractions.
+def I1toI32:  OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>;
+def I32toI1:  OutPatFrag<(ops node:$Rs), (i1 (C2_tfrrp (i32 $Rs)))>;
+def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>;
+def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>;
 
-def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
-def HexagonPACKHL  : SDNode<"HexagonISD::PACKHL",  SDTHexagonI64I32I32>;
+def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
+  (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>;
 
-// Pats for instruction selection.
-class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
-  : Pat<(ResT (Op I32:$Rs, I32:$Rt)),
-        (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
+def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
+def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
+def anyimm: PatLeaf<(i32 AnyImm:$Imm)>;
+def anyint: PatLeaf<(i32 AnyInt:$Imm)>;
 
-def: BinOp32_pat<add, A2_add, i32>;
-def: BinOp32_pat<and, A2_and, i32>;
-def: BinOp32_pat<or,  A2_or,  i32>;
-def: BinOp32_pat<sub, A2_sub, i32>;
-def: BinOp32_pat<xor, A2_xor, i32>;
+// Global address or an aligned constant.
+def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>;
+def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>;
+def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>;
+def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>;
 
-def: BinOp32_pat<HexagonCOMBINE, A2_combinew, i64>;
-def: BinOp32_pat<HexagonPACKHL,  S2_packhl,   i64>;
+def f32ImmPred : PatLeaf<(f32 fpimm:$F)>;
+def f64ImmPred : PatLeaf<(f64 fpimm:$F)>;
 
-// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
-// that reverse the order of the operands.
-class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
+// This complex pattern is really only to detect various forms of
+// sign-extension i32->i64. The selected value will be of type i64
+// whose low word is the value being extended. The high word is
+// unspecified.
+def Usxtw:  ComplexPattern<i64, 1, "DetectUseSxtw", [], []>;
 
-// Pats for compares. They use PatFrags as operands, not SDNodes,
-// since seteq/setgt/etc. are defined as ParFrags.
-class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
-  : Pat<(VT (Op I32:$Rs, I32:$Rt)),
-        (MI IntRegs:$Rs, IntRegs:$Rt)>;
+def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>;
+def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>;
+def Sext64: PatLeaf<(i64 Usxtw:$Rs)>;
 
-def: T_cmp32_rr_pat<C2_cmpeq,  seteq,  i1>;
-def: T_cmp32_rr_pat<C2_cmpgt,  setgt,  i1>;
-def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
+def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off),
+         (PS_fi (i32 AddrFI:$Rs), imm:$off)>;
 
-def: T_cmp32_rr_pat<C2_cmpgt,  RevCmp<setlt>,  i1>;
-def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
 
-def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt),
-         (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
+def alignedload: PatFrag<(ops node:$a), (load $a), [{
+  return isAlignedMemNode(dyn_cast<MemSDNode>(N));
+}]>;
 
-def: Pat<(add I32:$Rs, s32_0ImmPred:$s16),
-         (A2_addi I32:$Rs, imm:$s16)>;
+def unalignedload: PatFrag<(ops node:$a), (load $a), [{
+  return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
+}]>;
 
-def: Pat<(or I32:$Rs, s32_0ImmPred:$s10),
-         (A2_orir IntRegs:$Rs, imm:$s10)>;
-def: Pat<(and I32:$Rs, s32_0ImmPred:$s10),
-         (A2_andir IntRegs:$Rs, imm:$s10)>;
+def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
+  return isAlignedMemNode(dyn_cast<MemSDNode>(N));
+}]>;
 
-def: Pat<(sub s32_0ImmPred:$s10, IntRegs:$Rs),
-         (A2_subri imm:$s10, IntRegs:$Rs)>;
+def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
+  return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
+}]>;
 
-// Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
-def: Pat<(not I32:$src1),
-         (A2_subri -1, IntRegs:$src1)>;
 
-def TruncI64ToI32: SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
-}]>;
+// Converters from unary/binary SDNode to PatFrag.
+class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>;
+class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>;
 
-def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>;
-def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>;
+class Not2<PatFrag P>
+  : PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>;
 
-def : Pat<(select I1:$Pu, s32_0ImmPred:$s8, I32:$Rs),
-          (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
+class Su<PatFrag Op>
+  : PatFrag<Op.Operands, Op.Fragment, [{ return hasOneUse(N); }],
+            Op.OperandTransform>;
 
-def : Pat<(select I1:$Pu, I32:$Rs, s32_0ImmPred:$s8),
-          (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>;
+// Main selection macros.
 
-def : Pat<(select I1:$Pu, s32_0ImmPred:$s8, s8_0ImmPred:$S8),
-          (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>;
+class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred>
+  : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;
 
-def: Pat<(shl I32:$src1, (i32 16)),   (A2_aslh I32:$src1)>;
-def: Pat<(sra I32:$src1, (i32 16)),   (A2_asrh I32:$src1)>;
-def: Pat<(sext_inreg I32:$src1, i8),  (A2_sxtb I32:$src1)>;
-def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
+class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType,
+                 PatFrag RegPred, PatFrag ImmPred>
+  : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)),
+        (MI RegPred:$Rs, imm:$I)>;
 
-class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T>
-  : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))),
-        (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
+class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType,
+                 PatFrag RsPred, PatFrag RtPred = RsPred>
+  : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
+        (MI RsPred:$Rs, RtPred:$Rt)>;
 
-def: T_vcmp_pat<A2_vcmpbeq,  seteq,  v8i8>;
-def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>;
-def: T_vcmp_pat<A2_vcmpheq,  seteq,  v4i16>;
-def: T_vcmp_pat<A2_vcmphgt,  setgt,  v4i16>;
-def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>;
-def: T_vcmp_pat<A2_vcmpweq,  seteq,  v2i32>;
-def: T_vcmp_pat<A2_vcmpwgt,  setgt,  v2i32>;
-def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
+class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
+                 PatFrag RegPred, PatFrag ImmPred>
+  : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)),
+        (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>;
 
-// Add halfword.
-def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
-         (A2_addh_l16_ll I32:$src1, I32:$src2)>;
+class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
+                 PatFrag RsPred, PatFrag RtPred>
+  : Pat<(AccOp RsPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
+        (MI RsPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
 
-def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
-         (A2_addh_l16_hl I32:$src1, I32:$src2)>;
+multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val,
+                          InstHexagon InstA, InstHexagon InstB> {
+  def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B),
+           (InstA Val:$A, Val:$B)>;
+  def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A),
+           (InstB Val:$A, Val:$B)>;
+}
 
-def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
-         (A2_addh_h16_ll I32:$src1, I32:$src2)>;
 
-// Subtract halfword.
-def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
-         (A2_subh_l16_ll I32:$src1, I32:$src2)>;
+// Frags for commonly used SDNodes.
+def Add: pf2<add>;    def And: pf2<and>;    def Sra: pf2<sra>;
+def Sub: pf2<sub>;    def Or:  pf2<or>;     def Srl: pf2<srl>;
+def Mul: pf2<mul>;    def Xor: pf2<xor>;    def Shl: pf2<shl>;
 
-def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
-         (A2_subh_h16_ll I32:$src1, I32:$src2)>;
 
-// Here, depending on  the operand being selected, we'll either generate a
-// min or max instruction.
-// Ex:
-// (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
-// is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
-// (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
-// is selected and the corresponding HexagonInst is passed in 'SwapInst'.
+// --(1) Immediate -------------------------------------------------------
+//
 
-multiclass T_MinMax_pats <PatFrag Op, PatLeaf Val,
-                          InstHexagon Inst, InstHexagon SwapInst> {
-  def: Pat<(select (i1 (Op Val:$src1, Val:$src2)), Val:$src1, Val:$src2),
-           (Inst Val:$src1, Val:$src2)>;
-  def: Pat<(select (i1 (Op Val:$src1, Val:$src2)), Val:$src2, Val:$src1),
-           (SwapInst Val:$src1, Val:$src2)>;
-}
+def SDTHexagonCONST32
+  : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>;
 
-def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{
-  return isPositiveHalfWord(N);
+def HexagonJT:          SDNode<"HexagonISD::JT",          SDTIntUnaryOp>;
+def HexagonCP:          SDNode<"HexagonISD::CP",          SDTIntUnaryOp>;
+def HexagonCONST32:     SDNode<"HexagonISD::CONST32",     SDTHexagonCONST32>;
+def HexagonCONST32_GP:  SDNode<"HexagonISD::CONST32_GP",  SDTHexagonCONST32>;
+
+def TruncI64ToI32: SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
-multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
-  defm: T_MinMax_pats<Op, I32, Inst, SwapInst>;
+def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>;
+def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>;
 
-  def: Pat<(sext_inreg (select (i1 (Op IsPosHalf:$src1, IsPosHalf:$src2)),
-                               IsPosHalf:$src1, IsPosHalf:$src2),
-                       i16),
-           (Inst IntRegs:$src1, IntRegs:$src2)>;
+def: Pat<(HexagonCONST32    tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>;
+def: Pat<(HexagonCONST32    bbl:$A),            (A2_tfrsi imm:$A)>;
+def: Pat<(HexagonCONST32    tglobaladdr:$A),    (A2_tfrsi imm:$A)>;
+def: Pat<(HexagonCONST32_GP tblockaddress:$A),  (A2_tfrsi imm:$A)>;
+def: Pat<(HexagonCONST32_GP tglobaladdr:$A),    (A2_tfrsi imm:$A)>;
+def: Pat<(HexagonJT         tjumptable:$A),     (A2_tfrsi imm:$A)>;
+def: Pat<(HexagonCP         tconstpool:$A),     (A2_tfrsi imm:$A)>;
+// The HVX load patterns also match CP directly. Make sure that if
+// the selection of this opcode changes, it's updated in all places.
 
-  def: Pat<(sext_inreg (select (i1 (Op IsPosHalf:$src1, IsPosHalf:$src2)),
-                               IsPosHalf:$src2, IsPosHalf:$src1),
-                       i16),
-           (SwapInst IntRegs:$src1, IntRegs:$src2)>;
+def: Pat<(i1 0),        (PS_false)>;
+def: Pat<(i1 1),        (PS_true)>;
+def: Pat<(i64 imm:$v),  (CONST64 imm:$v)>;
+
+def ftoi : SDNodeXForm<fpimm, [{
+  APInt I = N->getValueAPF().bitcastToAPInt();
+  return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N),
+                                   MVT::getIntegerVT(I.getBitWidth()));
+}]>;
+
+def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>;
+def: Pat<(f64ImmPred:$f), (CONST64  (ftoi $f))>;
+
+def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>;
+
+// --(2) Type cast -------------------------------------------------------
+//
+
+let Predicates = [HasV5T] in {
+  def: OpR_R_pat<F2_conv_sf2df,      pf1<fpextend>,   f64, F32>;
+  def: OpR_R_pat<F2_conv_df2sf,      pf1<fpround>,    f32, F64>;
+
+  def: OpR_R_pat<F2_conv_w2sf,       pf1<sint_to_fp>, f32, I32>;
+  def: OpR_R_pat<F2_conv_d2sf,       pf1<sint_to_fp>, f32, I64>;
+  def: OpR_R_pat<F2_conv_w2df,       pf1<sint_to_fp>, f64, I32>;
+  def: OpR_R_pat<F2_conv_d2df,       pf1<sint_to_fp>, f64, I64>;
+
+  def: OpR_R_pat<F2_conv_uw2sf,      pf1<uint_to_fp>, f32, I32>;
+  def: OpR_R_pat<F2_conv_ud2sf,      pf1<uint_to_fp>, f32, I64>;
+  def: OpR_R_pat<F2_conv_uw2df,      pf1<uint_to_fp>, f64, I32>;
+  def: OpR_R_pat<F2_conv_ud2df,      pf1<uint_to_fp>, f64, I64>;
+
+  def: OpR_R_pat<F2_conv_sf2w_chop,  pf1<fp_to_sint>, i32, F32>;
+  def: OpR_R_pat<F2_conv_df2w_chop,  pf1<fp_to_sint>, i32, F64>;
+  def: OpR_R_pat<F2_conv_sf2d_chop,  pf1<fp_to_sint>, i64, F32>;
+  def: OpR_R_pat<F2_conv_df2d_chop,  pf1<fp_to_sint>, i64, F64>;
+
+  def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>;
+  def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>;
+  def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>;
+  def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>;
 }
 
-let AddedComplexity = 200 in {
-  defm: MinMax_pats<setge,  A2_max,  A2_min>;
-  defm: MinMax_pats<setgt,  A2_max,  A2_min>;
-  defm: MinMax_pats<setle,  A2_min,  A2_max>;
-  defm: MinMax_pats<setlt,  A2_min,  A2_max>;
-  defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
-  defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
-  defm: MinMax_pats<setule, A2_minu, A2_maxu>;
-  defm: MinMax_pats<setult, A2_minu, A2_maxu>;
+// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
+let Predicates = [HasV5T] in {
+  def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>;
+  def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>;
+  def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>;
+  def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>;
 }
 
-class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
-  : Pat<(i1 (CmpOp I64:$Rs, I64:$Rt)),
-        (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
+multiclass Cast_pat<ValueType Ta, ValueType Tb, RegisterClass RC> {
+  def: Pat<(Tb (bitconvert (Ta RC:$Rs))), (Tb RC:$Rs)>;
+  def: Pat<(Ta (bitconvert (Tb RC:$Rs))), (Ta RC:$Rs)>;
+}
 
-def: T_cmp64_rr_pat<C2_cmpeqp,  seteq>;
-def: T_cmp64_rr_pat<C2_cmpgtp,  setgt>;
-def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
-def: T_cmp64_rr_pat<C2_cmpgtp,  RevCmp<setlt>>;
-def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
+// Bit convert vector types to integers.
+defm: Cast_pat<v4i8,  i32, IntRegs>;
+defm: Cast_pat<v2i16, i32, IntRegs>;
+defm: Cast_pat<v8i8,  i64, DoubleRegs>;
+defm: Cast_pat<v4i16, i64, DoubleRegs>;
+defm: Cast_pat<v2i32, i64, DoubleRegs>;
 
-def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
-def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
 
-def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
-def: Pat<(i64 (or  I64:$Rs, I64:$Rt)), (A2_orp  I64:$Rs, I64:$Rt)>;
-def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
+// --(3) Extend/truncate -------------------------------------------------
+//
 
-def: Pat<(i1 (not I1:$Ps)), (C2_not PredRegs:$Ps)>;
+def: Pat<(sext_inreg I32:$Rs, i8),  (A2_sxtb I32:$Rs)>;
+def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>;
+def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>;
+def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>;
+def: Pat<(sext_inreg I64:$Rs, i8),  (A2_sxtw (A2_sxtb (LoReg $Rs)))>;
 
-def: Pat<(i1 (and I1:$Ps, I1:$Pt)),       (C2_and  I1:$Ps, I1:$Pt)>;
-def: Pat<(i1 (or  I1:$Ps, I1:$Pt)),       (C2_or   I1:$Ps, I1:$Pt)>;
-def: Pat<(i1 (xor I1:$Ps, I1:$Pt)),       (C2_xor  I1:$Ps, I1:$Pt)>;
-def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
-def: Pat<(i1 (or  I1:$Ps, (not I1:$Pt))), (C2_orn  I1:$Ps, I1:$Pt)>;
+def: Pat<(i64 (sext I1:$Pu)),
+         (Combinew (C2_muxii PredRegs:$Pu, -1, 0),
+                   (C2_muxii PredRegs:$Pu, -1, 0))>;
 
-def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
-                     [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
-def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
+def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>;
+def: Pat<(i32 (zext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>;
+def: Pat<(i64 (zext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>;
 
-def: Pat<(br bb:$dst),                  (J2_jump b30_2Imm:$dst)>;
-def: Pat<(brcond I1:$src1, bb:$block),  (J2_jumpt PredRegs:$src1, bb:$block)>;
-def: Pat<(brind I32:$dst),              (J2_jumpr IntRegs:$dst)>;
+def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>;
+def: Pat<(Zext64 I32:$Rs),     (ToZext64 $Rs)>;
+def: Pat<(Aext64 I32:$Rs),     (ToZext64 $Rs)>;
 
-def: Pat<(retflag),   (PS_jmpret (i32 R31))>;
-def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>;
+def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>;
+def: Pat<(i1 (trunc I64:$Rs)),  (C2_tfrrp (LoReg $Rs))>;
 
-// Patterns to select load-indexed (i.e. load from base+offset).
-multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
-                     InstHexagon MI> {
-  def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
-  def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
-           (VT (MI AddrFI:$fi, imm:$Off))>;
-  def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))),
-           (VT (MI AddrFI:$fi, imm:$Off))>;
-  def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))),
-           (VT (MI IntRegs:$Rs, imm:$Off))>;
-  def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>;
+let AddedComplexity = 20 in {
+  def: Pat<(and I32:$Rs, 255),   (A2_zxtb I32:$Rs)>;
+  def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>;
 }
 
-let AddedComplexity = 20 in {
-  defm: Loadx_pat<load,           i32, s30_2ImmPred, L2_loadri_io>;
-  defm: Loadx_pat<load,           i64, s29_3ImmPred, L2_loadrd_io>;
-  defm: Loadx_pat<atomic_load_8 , i32, s32_0ImmPred, L2_loadrub_io>;
-  defm: Loadx_pat<atomic_load_16, i32, s31_1ImmPred, L2_loadruh_io>;
-  defm: Loadx_pat<atomic_load_32, i32, s30_2ImmPred, L2_loadri_io>;
-  defm: Loadx_pat<atomic_load_64, i64, s29_3ImmPred, L2_loadrd_io>;
+def: Pat<(i32 (anyext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>;
+def: Pat<(i64 (anyext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>;
 
-  defm: Loadx_pat<extloadi1,      i32, s32_0ImmPred, L2_loadrub_io>;
-  defm: Loadx_pat<extloadi8,      i32, s32_0ImmPred, L2_loadrub_io>;
-  defm: Loadx_pat<extloadi16,     i32, s31_1ImmPred, L2_loadruh_io>;
-  defm: Loadx_pat<sextloadi8,     i32, s32_0ImmPred, L2_loadrb_io>;
-  defm: Loadx_pat<sextloadi16,    i32, s31_1ImmPred, L2_loadrh_io>;
-  defm: Loadx_pat<zextloadi1,     i32, s32_0ImmPred, L2_loadrub_io>;
-  defm: Loadx_pat<zextloadi8,     i32, s32_0ImmPred, L2_loadrub_io>;
-  defm: Loadx_pat<zextloadi16,    i32, s31_1ImmPred, L2_loadruh_io>;
-  // No sextloadi1.
-}
+def: Pat<(v4i16 (zext   V4I8:$Rs)),  (S2_vzxtbh V4I8:$Rs)>;
+def: Pat<(v2i32 (zext   V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
+def: Pat<(v4i16 (anyext V4I8:$Rs)),  (S2_vzxtbh V4I8:$Rs)>;
+def: Pat<(v2i32 (anyext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
+def: Pat<(v4i16 (sext   V4I8:$Rs)),  (S2_vsxtbh V4I8:$Rs)>;
+def: Pat<(v2i32 (sext   V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>;
 
-// Sign-extending loads of i1 need to replicate the lowest bit throughout
-// the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
-// do the trick.
-let AddedComplexity = 20 in
-def: Pat<(i32 (sextloadi1 I32:$Rs)),
-         (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
+def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
+         (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
 
-def: Pat<(i32 (mul   I32:$src1, I32:$src2)), (M2_mpyi    I32:$src1, I32:$src2)>;
-def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up  I32:$src1, I32:$src2)>;
-def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
+def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
+         (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
 
-def: Pat<(mul IntRegs:$Rs, u32_0ImmPred:$u8),
-         (M2_mpysip IntRegs:$Rs, imm:$u8)>;
-def: Pat<(ineg (mul IntRegs:$Rs, u8_0ImmPred:$u8)),
-         (M2_mpysin IntRegs:$Rs, imm:$u8)>;
-def: Pat<(mul IntRegs:$src1, s32_0ImmPred:$src2),
-         (M2_mpysmi IntRegs:$src1, imm:$src2)>;
-def: Pat<(add (mul IntRegs:$src2, u32_0ImmPred:$src3), IntRegs:$src1),
-         (M2_macsip IntRegs:$src1, IntRegs:$src2, imm:$src3)>;
-def: Pat<(add (mul I32:$src2, I32:$src3), I32:$src1),
-         (M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
-def: Pat<(add (add IntRegs:$src2, s32_0ImmPred:$src3), IntRegs:$src1),
-         (M2_accii IntRegs:$src1, IntRegs:$src2, imm:$src3)>;
-def: Pat<(add (add I32:$src2, I32:$src3), I32:$src1),
-         (M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
+// Truncate: from vector B copy all 'E'ven 'B'yte elements:
+// A[0] = B[0];  A[1] = B[2];  A[2] = B[4];  A[3] = B[6];
+def: Pat<(v4i8 (trunc V4I16:$Rs)),
+         (S2_vtrunehb V4I16:$Rs)>;
 
-class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
-                        PatLeaf ImmPred>
-  : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
-         (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
+// Truncate: from vector B copy all 'O'dd 'B'yte elements:
+// A[0] = B[1];  A[1] = B[3];  A[2] = B[5];  A[3] = B[7];
+// S2_vtrunohb
 
-class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
-  : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
-         (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
+// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements:
+// A[0] = B[0];  A[1] = B[2];  A[2] = C[0];  A[3] = C[2];
+// S2_vtruneh
 
-def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
-def : T_MType_acc_pat1 <M2_macsin, mul, sub, u32_0ImmPred>;
+def: Pat<(v2i16 (trunc V2I32:$Rs)),
+         (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
 
-def : T_MType_acc_pat1 <M2_naccii, add, sub, s32_0ImmPred>;
-def : T_MType_acc_pat2 <M2_nacci, add, sub>;
 
-def: T_MType_acc_pat2 <M4_or_xor, xor, or>;
-def: T_MType_acc_pat2 <M4_and_xor, xor, and>;
-def: T_MType_acc_pat2 <M4_or_and, and, or>;
-def: T_MType_acc_pat2 <M4_and_and, and, and>;
-def: T_MType_acc_pat2 <M4_xor_and, and, xor>;
-def: T_MType_acc_pat2 <M4_or_or, or, or>;
-def: T_MType_acc_pat2 <M4_and_or, or, and>;
-def: T_MType_acc_pat2 <M4_xor_or, or, xor>;
+// --(4) Logical ---------------------------------------------------------
+//
 
-class T_MType_acc_pat3 <InstHexagon MI, SDNode firstOp, SDNode secOp>
-  : Pat <(secOp I32:$src1, (firstOp I32:$src2, (not I32:$src3))),
-         (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
+def: Pat<(not I1:$Ps),      (C2_not I1:$Ps)>;
+def: Pat<(add I1:$Ps, -1),  (C2_not I1:$Ps)>;
 
-def: T_MType_acc_pat3 <M4_or_andn, and, or>;
-def: T_MType_acc_pat3 <M4_and_andn, and, and>;
-def: T_MType_acc_pat3 <M4_xor_andn, and, xor>;
+def: OpR_RR_pat<C2_and,   And,       i1, I1>;
+def: OpR_RR_pat<C2_or,    Or,        i1, I1>;
+def: OpR_RR_pat<C2_xor,   Xor,       i1, I1>;
+def: OpR_RR_pat<C2_andn,  Not2<And>, i1, I1>;
+def: OpR_RR_pat<C2_orn,   Not2<Or>,  i1, I1>;
 
-// This complex pattern is really only to detect various forms of
-// sign-extension i32->i64. The selected value will be of type i64
-// whose low word is the value being extended. The high word is
-// unspecified.
-def Usxtw : ComplexPattern<i64, 1, "DetectUseSxtw", [], []>;
+// op(Ps, op(Pt, Pu))
+def: AccRRR_pat<C4_and_and,   And, Su<And>,       I1, I1>;
+def: AccRRR_pat<C4_and_or,    And, Su<Or>,        I1, I1>;
+def: AccRRR_pat<C4_or_and,    Or,  Su<And>,       I1, I1>;
+def: AccRRR_pat<C4_or_or,     Or,  Su<Or>,        I1, I1>;
 
-def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>;
-def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>;
-def Sext64: PatLeaf<(i64 Usxtw:$Rs)>;
+// op(Ps, op(Pt, ~Pu))
+def: AccRRR_pat<C4_and_andn,  And, Su<Not2<And>>, I1, I1>;
+def: AccRRR_pat<C4_and_orn,   And, Su<Not2<Or>>,  I1, I1>;
+def: AccRRR_pat<C4_or_andn,   Or,  Su<Not2<And>>, I1, I1>;
+def: AccRRR_pat<C4_or_orn,    Or,  Su<Not2<Or>>,  I1, I1>;
 
-def: Pat<(i32 (trunc (sra (mul Sext64:$Rs, Sext64:$Rt), (i32 32)))),
-         (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
-def: Pat<(i32 (trunc (srl (mul Sext64:$Rs, Sext64:$Rt), (i32 32)))),
-         (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
 
-def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)),
-         (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>;
+// --(5) Compare ---------------------------------------------------------
+//
 
-def: Pat<(mul Sext64:$Rs, Sext64:$Rt),
-         (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+// Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)".
+// These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt).
 
-// Multiply and accumulate, use full result.
-// Rxx[+-]=mpy(Rs,Rt)
+def: OpR_RI_pat<C2_cmpeqi,    seteq,          i1, I32,  anyimm>;
+def: OpR_RI_pat<C2_cmpgti,    setgt,          i1, I32,  anyimm>;
+def: OpR_RI_pat<C2_cmpgtui,   setugt,         i1, I32,  anyimm>;
 
-def: Pat<(add I64:$Rx, (mul Sext64:$Rs, Sext64:$Rt)),
-         (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)),
+         (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>;
+def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)),
+         (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>;
 
-def: Pat<(sub I64:$Rx, (mul Sext64:$Rs, Sext64:$Rt)),
-         (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)),
+         (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>;
+def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)),
+         (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>;
 
-def: Pat<(add I64:$Rx, (mul (Aext64 I32:$Rs), (Aext64 I32:$Rt))),
-         (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
+// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
+// that reverse the order of the operands.
+class RevCmp<PatFrag F>
+  : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment, F.PredicateCode,
+            F.OperandTransform>;
 
-def: Pat<(add I64:$Rx, (mul (Zext64 I32:$Rs), (Zext64 I32:$Rt))),
-         (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
+def: OpR_RR_pat<C2_cmpeq,     seteq,          i1,   I32>;
+def: OpR_RR_pat<C2_cmpgt,     setgt,          i1,   I32>;
+def: OpR_RR_pat<C2_cmpgtu,    setugt,         i1,   I32>;
+def: OpR_RR_pat<C2_cmpgt,     RevCmp<setlt>,  i1,   I32>;
+def: OpR_RR_pat<C2_cmpgtu,    RevCmp<setult>, i1,   I32>;
+def: OpR_RR_pat<C2_cmpeqp,    seteq,          i1,   I64>;
+def: OpR_RR_pat<C2_cmpgtp,    setgt,          i1,   I64>;
+def: OpR_RR_pat<C2_cmpgtup,   setugt,         i1,   I64>;
+def: OpR_RR_pat<C2_cmpgtp,    RevCmp<setlt>,  i1,   I64>;
+def: OpR_RR_pat<C2_cmpgtup,   RevCmp<setult>, i1,   I64>;
+def: OpR_RR_pat<A2_vcmpbeq,   seteq,          i1,   V8I8>;
+def: OpR_RR_pat<A2_vcmpbeq,   seteq,          v8i1, V8I8>;
+def: OpR_RR_pat<A4_vcmpbgt,   RevCmp<setlt>,  i1,   V8I8>;
+def: OpR_RR_pat<A4_vcmpbgt,   RevCmp<setlt>,  v8i1, V8I8>;
+def: OpR_RR_pat<A4_vcmpbgt,   setgt,          i1,   V8I8>;
+def: OpR_RR_pat<A4_vcmpbgt,   setgt,          v8i1, V8I8>;
+def: OpR_RR_pat<A2_vcmpbgtu,  RevCmp<setult>, i1,   V8I8>;
+def: OpR_RR_pat<A2_vcmpbgtu,  RevCmp<setult>, v8i1, V8I8>;
+def: OpR_RR_pat<A2_vcmpbgtu,  setugt,         i1,   V8I8>;
+def: OpR_RR_pat<A2_vcmpbgtu,  setugt,         v8i1, V8I8>;
+def: OpR_RR_pat<A2_vcmpheq,   seteq,          i1,   V4I16>;
+def: OpR_RR_pat<A2_vcmpheq,   seteq,          v4i1, V4I16>;
+def: OpR_RR_pat<A2_vcmphgt,   RevCmp<setlt>,  i1,   V4I16>;
+def: OpR_RR_pat<A2_vcmphgt,   RevCmp<setlt>,  v4i1, V4I16>;
+def: OpR_RR_pat<A2_vcmphgt,   setgt,          i1,   V4I16>;
+def: OpR_RR_pat<A2_vcmphgt,   setgt,          v4i1, V4I16>;
+def: OpR_RR_pat<A2_vcmphgtu,  RevCmp<setult>, i1,   V4I16>;
+def: OpR_RR_pat<A2_vcmphgtu,  RevCmp<setult>, v4i1, V4I16>;
+def: OpR_RR_pat<A2_vcmphgtu,  setugt,         i1,   V4I16>;
+def: OpR_RR_pat<A2_vcmphgtu,  setugt,         v4i1, V4I16>;
+def: OpR_RR_pat<A2_vcmpweq,   seteq,          i1,   V2I32>;
+def: OpR_RR_pat<A2_vcmpweq,   seteq,          v2i1, V2I32>;
+def: OpR_RR_pat<A2_vcmpwgt,   RevCmp<setlt>,  i1,   V2I32>;
+def: OpR_RR_pat<A2_vcmpwgt,   RevCmp<setlt>,  v2i1, V2I32>;
+def: OpR_RR_pat<A2_vcmpwgt,   setgt,          i1,   V2I32>;
+def: OpR_RR_pat<A2_vcmpwgt,   setgt,          v2i1, V2I32>;
+def: OpR_RR_pat<A2_vcmpwgtu,  RevCmp<setult>, i1,   V2I32>;
+def: OpR_RR_pat<A2_vcmpwgtu,  RevCmp<setult>, v2i1, V2I32>;
+def: OpR_RR_pat<A2_vcmpwgtu,  setugt,         i1,   V2I32>;
+def: OpR_RR_pat<A2_vcmpwgtu,  setugt,         v2i1, V2I32>;
 
-def: Pat<(sub I64:$Rx, (mul (Aext64 I32:$Rs), (Aext64 I32:$Rt))),
-         (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
+let Predicates = [HasV5T] in {
+  def: OpR_RR_pat<F2_sfcmpeq,   seteq,          i1, F32>;
+  def: OpR_RR_pat<F2_sfcmpgt,   setgt,          i1, F32>;
+  def: OpR_RR_pat<F2_sfcmpge,   setge,          i1, F32>;
+  def: OpR_RR_pat<F2_sfcmpeq,   setoeq,         i1, F32>;
+  def: OpR_RR_pat<F2_sfcmpgt,   setogt,         i1, F32>;
+  def: OpR_RR_pat<F2_sfcmpge,   setoge,         i1, F32>;
+  def: OpR_RR_pat<F2_sfcmpgt,   RevCmp<setolt>, i1, F32>;
+  def: OpR_RR_pat<F2_sfcmpge,   RevCmp<setole>, i1, F32>;
+  def: OpR_RR_pat<F2_sfcmpgt,   RevCmp<setlt>,  i1, F32>;
+  def: OpR_RR_pat<F2_sfcmpge,   RevCmp<setle>,  i1, F32>;
+  def: OpR_RR_pat<F2_sfcmpuo,   setuo,          i1, F32>;
 
-def: Pat<(sub I64:$Rx, (mul (Zext64 I32:$Rs), (Zext64 I32:$Rt))),
-         (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
+  def: OpR_RR_pat<F2_dfcmpeq,   seteq,          i1, F64>;
+  def: OpR_RR_pat<F2_dfcmpgt,   setgt,          i1, F64>;
+  def: OpR_RR_pat<F2_dfcmpge,   setge,          i1, F64>;
+  def: OpR_RR_pat<F2_dfcmpeq,   setoeq,         i1, F64>;
+  def: OpR_RR_pat<F2_dfcmpgt,   setogt,         i1, F64>;
+  def: OpR_RR_pat<F2_dfcmpge,   setoge,         i1, F64>;
+  def: OpR_RR_pat<F2_dfcmpgt,   RevCmp<setolt>, i1, F64>;
+  def: OpR_RR_pat<F2_dfcmpge,   RevCmp<setole>, i1, F64>;
+  def: OpR_RR_pat<F2_dfcmpgt,   RevCmp<setlt>,  i1, F64>;
+  def: OpR_RR_pat<F2_dfcmpge,   RevCmp<setle>,  i1, F64>;
+  def: OpR_RR_pat<F2_dfcmpuo,   setuo,          i1, F64>;
+}
 
-class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset,
-                  InstHexagon MI>
-  : Pat<(Store Value:$src1, I32:$src2, Offset:$offset),
-        (MI I32:$src2, imm:$offset, Value:$src1)>;
+// Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds.
 
-def: Storepi_pat<post_truncsti8,  I32, s4_0ImmPred, S2_storerb_pi>;
-def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>;
-def: Storepi_pat<post_store,      I32, s4_2ImmPred, S2_storeri_pi>;
-def: Storepi_pat<post_store,      I64, s4_3ImmPred, S2_storerd_pi>;
+def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)),
+         (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>;
+def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)),
+         (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>;
+def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)),
+         (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>;
 
-// Patterns for generating stores, where the address takes different forms:
-// - frameindex,
-// - frameindex + offset,
-// - base + offset,
-// - simple (base address without offset).
-// These would usually be used together (via Storex_pat defined below), but
-// in some cases one may want to apply different properties (such as
-// AddedComplexity) to the individual patterns.
-class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
-  : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
-multiclass Storex_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
-                             InstHexagon MI> {
-  def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
-           (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
-  def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)),
-           (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
-}
-multiclass Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
-                          InstHexagon MI> {
-  def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)),
-           (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
-  def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)),
-           (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
+def: Pat<(i1 (setne I32:$Rs, I32:$Rt)),
+         (C2_not (C2_cmpeq I32:$Rs, I32:$Rt))>;
+def: Pat<(i1 (setle I32:$Rs, I32:$Rt)),
+         (C2_not (C2_cmpgt I32:$Rs, I32:$Rt))>;
+def: Pat<(i1 (setule I32:$Rs, I32:$Rt)),
+         (C2_not (C2_cmpgtu I32:$Rs, I32:$Rt))>;
+def: Pat<(i1 (setge I32:$Rs, I32:$Rt)),
+         (C2_not (C2_cmpgt I32:$Rt, I32:$Rs))>;
+def: Pat<(i1 (setuge I32:$Rs, I32:$Rt)),
+         (C2_not (C2_cmpgtu I32:$Rt, I32:$Rs))>;
+
+def: Pat<(i1 (setle I64:$Rs, I64:$Rt)),
+         (C2_not (C2_cmpgtp I64:$Rs, I64:$Rt))>;
+def: Pat<(i1 (setne I64:$Rs, I64:$Rt)),
+         (C2_not (C2_cmpeqp I64:$Rs, I64:$Rt))>;
+def: Pat<(i1 (setge I64:$Rs, I64:$Rt)),
+         (C2_not (C2_cmpgtp I64:$Rt, I64:$Rs))>;
+def: Pat<(i1 (setuge I64:$Rs, I64:$Rt)),
+         (C2_not (C2_cmpgtup I64:$Rt, I64:$Rs))>;
+def: Pat<(i1 (setule I64:$Rs, I64:$Rt)),
+         (C2_not (C2_cmpgtup I64:$Rs, I64:$Rt))>;
+
+let AddedComplexity = 100 in {
+  def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)),
+           (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
+  def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)),
+           (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
+  def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)),
+           (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
+  def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)),
+           (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
 }
-class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
-  : Pat<(Store Value:$Rt, I32:$Rs),
-        (MI IntRegs:$Rs, 0, Value:$Rt)>;
 
-// Patterns for generating stores, where the address takes different forms,
-// and where the value being stored is transformed through the value modifier
-// ValueMod.  The address forms are same as above.
-class Storexm_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
-                     InstHexagon MI>
-  : Pat<(Store Value:$Rs, AddrFI:$fi),
-        (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>;
-multiclass Storexm_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
-                              PatFrag ValueMod, InstHexagon MI> {
-  def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
-           (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
-  def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)),
-           (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
+// PatFrag for AsserZext which takes the original type as a parameter.
+def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>;
+def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>;
+class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>;
+
+multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
+                      PatLeaf ImmPred, int Mask> {
+  def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
+           (MI I32:$Rs, imm:$I)>;
+  def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
+           (MI I32:$Rs, imm:$I)>;
 }
-multiclass Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
-                           PatFrag ValueMod, InstHexagon MI> {
-  def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)),
-           (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
-  def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)),
-           (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
+
+multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
+                     PatLeaf ImmPred, int Mask> {
+  def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
+           (C2_not (MI I32:$Rs, imm:$I))>;
+  def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
+           (C2_not (MI I32:$Rs, imm:$I))>;
 }
-class Storexm_simple_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
-                         InstHexagon MI>
-  : Pat<(Store Value:$Rt, I32:$Rs),
-        (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
 
-multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
-                      InstHexagon MI> {
-  def:  Storex_fi_pat     <Store, Value,          MI>;
-  defm: Storex_fi_add_pat <Store, Value, ImmPred, MI>;
-  defm: Storex_add_pat    <Store, Value, ImmPred, MI>;
+multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
+                      PatLeaf ImmPred, int Mask> {
+  def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
+           (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>;
+  def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
+           (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>;
 }
 
-multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
-                       PatFrag ValueMod, InstHexagon MI> {
-  def:  Storexm_fi_pat     <Store, Value,          ValueMod, MI>;
-  defm: Storexm_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>;
-  defm: Storexm_add_pat    <Store, Value, ImmPred, ValueMod, MI>;
+let AddedComplexity = 200 in {
+  defm: Cmpb_pat  <A4_cmpbeqi,  seteq,  AssertZext<i8>,  IsUGT<8,31>,  255>;
+  defm: CmpbN_pat <A4_cmpbeqi,  setne,  AssertZext<i8>,  IsUGT<8,31>,  255>;
+  defm: Cmpb_pat  <A4_cmpbgtui, setugt, AssertZext<i8>,  IsUGT<32,31>, 255>;
+  defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>,  IsUGT<32,31>, 255>;
+  defm: Cmpb_pat  <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>;
+  defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>;
+  defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>,  IsUGT<32,32>, 255>;
+  defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>;
 }
 
-// Regular stores in the DAG have two operands: value and address.
-// Atomic stores also have two, but they are reversed: address, value.
-// To use atomic stores with the patterns, they need to have their operands
-// swapped. This relies on the knowledge that the F.Fragment uses names
-// "ptr" and "val".
-class SwapSt<PatFrag F>
-  : PatFrag<(ops node:$val, node:$ptr), F.Fragment, F.PredicateCode,
-            F.OperandTransform>;
+def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))),
+         (A4_rcmpeq I32:$Rs, I32:$Rt)>;
+def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))),
+         (A4_rcmpneq I32:$Rs, I32:$Rt)>;
+def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))),
+         (A4_rcmpeqi I32:$Rs, imm:$s8)>;
+def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))),
+         (A4_rcmpneqi I32:$Rs, imm:$s8)>;
 
-let AddedComplexity = 20 in {
-  defm: Storex_pat<truncstorei8,    I32, s32_0ImmPred, S2_storerb_io>;
-  defm: Storex_pat<truncstorei16,   I32, s31_1ImmPred, S2_storerh_io>;
-  defm: Storex_pat<store,           I32, s30_2ImmPred, S2_storeri_io>;
-  defm: Storex_pat<store,           I64, s29_3ImmPred, S2_storerd_io>;
+def: Pat<(i1 (setne I1:$Ps, I1:$Pt)),
+         (C2_xor I1:$Ps, I1:$Pt)>;
+
+def: Pat<(i1 (seteq V4I8:$Rs, V4I8:$Rt)),
+         (A2_vcmpbeq (ToZext64 $Rs), (ToZext64 $Rt))>;
+def: Pat<(i1 (setgt V4I8:$Rs, V4I8:$Rt)),
+         (A4_vcmpbgt (ToZext64 $Rs), (ToZext64 $Rt))>;
+def: Pat<(i1 (setugt V4I8:$Rs, V4I8:$Rt)),
+         (A2_vcmpbgtu (ToZext64 $Rs), (ToZext64 $Rt))>;
+
+def: Pat<(i1 (seteq V2I16:$Rs, V2I16:$Rt)),
+         (A2_vcmpheq (ToZext64 $Rs), (ToZext64 $Rt))>;
+def: Pat<(i1 (setgt V2I16:$Rs, V2I16:$Rt)),
+         (A2_vcmphgt (ToZext64 $Rs), (ToZext64 $Rt))>;
+def: Pat<(i1 (setugt V2I16:$Rs, V2I16:$Rt)),
+         (A2_vcmphgtu (ToZext64 $Rs), (ToZext64 $Rt))>;
+
+def: Pat<(v2i1 (setne V2I32:$Rs, V2I32:$Rt)),
+         (C2_not (v2i1 (A2_vcmpbeq V2I32:$Rs, V2I32:$Rt)))>;
+
+// Floating-point comparisons with checks for ordered/unordered status.
 
-  defm: Storex_pat<SwapSt<atomic_store_8>,  I32, s32_0ImmPred, S2_storerb_io>;
-  defm: Storex_pat<SwapSt<atomic_store_16>, I32, s31_1ImmPred, S2_storerh_io>;
-  defm: Storex_pat<SwapSt<atomic_store_32>, I32, s30_2ImmPred, S2_storeri_io>;
-  defm: Storex_pat<SwapSt<atomic_store_64>, I64, s29_3ImmPred, S2_storerd_io>;
+class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>
+  : OutPatFrag<(ops node:$Rs, node:$Rt),
+               (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
+
+class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType,
+                  PatFrag RsPred, PatFrag RtPred = RsPred>
+  : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
+        (Output RsPred:$Rs, RtPred:$Rt)>;
+
+class Cmpuf<InstHexagon MI>:  T3<C2_or,  F2_sfcmpuo, MI>;
+class Cmpud<InstHexagon MI>:  T3<C2_or,  F2_dfcmpuo, MI>;
+
+class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>;
+class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>;
+
+let Predicates = [HasV5T] in {
+  def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>,  setueq,         i1, F32>;
+  def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>,  setuge,         i1, F32>;
+  def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>,  setugt,         i1, F32>;
+  def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>,  RevCmp<setule>, i1, F32>;
+  def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>,  RevCmp<setult>, i1, F32>;
+  def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune,         i1, F32>;
+
+  def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>,  setueq,         i1, F64>;
+  def: OpmR_RR_pat<Cmpud<F2_dfcmpge>,  setuge,         i1, F64>;
+  def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>,  setugt,         i1, F64>;
+  def: OpmR_RR_pat<Cmpud<F2_dfcmpge>,  RevCmp<setule>, i1, F64>;
+  def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>,  RevCmp<setult>, i1, F64>;
+  def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune,         i1, F64>;
 }
 
-// Simple patterns should be tried with the least priority.
-def: Storex_simple_pat<truncstorei8,    I32, S2_storerb_io>;
-def: Storex_simple_pat<truncstorei16,   I32, S2_storerh_io>;
-def: Storex_simple_pat<store,           I32, S2_storeri_io>;
-def: Storex_simple_pat<store,           I64, S2_storerd_io>;
+class Outn<InstHexagon MI>
+  : OutPatFrag<(ops node:$Rs, node:$Rt),
+               (C2_not (MI $Rs, $Rt))>;
 
-def: Storex_simple_pat<SwapSt<atomic_store_8>,  I32, S2_storerb_io>;
-def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>;
-def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
-def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
+let Predicates = [HasV5T] in {
+  def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>;
+  def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne,  i1, F32>;
 
-let AddedComplexity = 20 in {
-  defm: Storexm_pat<truncstorei8,  I64, s32_0ImmPred, LoReg, S2_storerb_io>;
-  defm: Storexm_pat<truncstorei16, I64, s31_1ImmPred, LoReg, S2_storerh_io>;
-  defm: Storexm_pat<truncstorei32, I64, s30_2ImmPred, LoReg, S2_storeri_io>;
+  def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>;
+  def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne,  i1, F64>;
+
+  def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto,   i1, F32>;
+  def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto,   i1, F64>;
 }
 
-def: Storexm_simple_pat<truncstorei8,  I64, LoReg, S2_storerb_io>;
-def: Storexm_simple_pat<truncstorei16, I64, LoReg, S2_storerh_io>;
-def: Storexm_simple_pat<truncstorei32, I64, LoReg, S2_storeri_io>;
 
-def: Pat <(i64 (sext I32:$src)),            (A2_sxtw I32:$src)>;
-def: Pat <(i64 (sext_inreg I64:$src, i32)), (A2_sxtw (LoReg I64:$src))>;
+// --(6) Select ----------------------------------------------------------
+//
 
-def: Pat<(select (i1 (setlt I32:$src, 0)), (sub 0, I32:$src), I32:$src),
-         (A2_abs IntRegs:$src)>;
+def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt),
+         (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>;
+def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs),
+         (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
+def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8),
+         (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>;
+def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8),
+         (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>;
 
-let AddedComplexity = 50 in
-def: Pat<(xor (add (sra I32:$src, (i32 31)),
-                   I32:$src),
-              (sra I32:$src, (i32 31))),
-         (A2_abs IntRegs:$src)>;
+def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt),
+         (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>;
+def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8),
+         (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>;
+def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs),
+         (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>;
+def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8),
+         (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
 
-def: Pat<(sra I32:$src, u5_0ImmPred:$u5),
-         (S2_asr_i_r IntRegs:$src, imm:$u5)>;
-def: Pat<(srl I32:$src, u5_0ImmPred:$u5),
-         (S2_lsr_i_r IntRegs:$src, imm:$u5)>;
-def: Pat<(shl I32:$src, u5_0ImmPred:$u5),
-         (S2_asl_i_r IntRegs:$src, imm:$u5)>;
+// Map from a 64-bit select to an emulated 64-bit mux.
+// Hexagon does not support 64-bit MUXes; so emulate with combines.
+def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt),
+         (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
+                   (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
 
-def: Pat<(sra (add (sra I32:$src1, u5_0ImmPred:$src2), 1), (i32 1)),
-         (S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred:$src2)>;
+let Predicates = [HasV5T] in {
+  def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I),
+           (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>;
+  def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt),
+           (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>;
+  def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt),
+           (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>;
+  def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt),
+           (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
+                     (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
 
-def : Pat<(not I64:$src1),
-          (A2_notp DoubleRegs:$src1)>;
+  def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt),
+           (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>;
+  def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt),
+           (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>;
 
-// Count leading zeros.
-def: Pat<(ctlz I32:$Rs), (S2_cl0 I32:$Rs)>;
-def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
+  def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs),
+           (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>;
+  def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I),
+           (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>;
+}
 
-// Count trailing zeros: 32-bit.
-def: Pat<(cttz I32:$Rs), (S2_ct0 I32:$Rs)>;
+def: Pat<(select I1:$Pu, V4I8:$Rs, V4I8:$Rt),
+         (LoReg (C2_vmux I1:$Pu, (ToZext64 $Rs), (ToZext64 $Rt)))>;
+def: Pat<(select I1:$Pu, V2I16:$Rs, V2I16:$Rt),
+         (LoReg (C2_vmux I1:$Pu, (ToZext64 $Rs), (ToZext64 $Rt)))>;
+def: Pat<(select I1:$Pu, V2I32:$Rs, V2I32:$Rt),
+         (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
+                   (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
 
-// Count leading ones.
-def: Pat<(ctlz (not I32:$Rs)), (S2_cl1 I32:$Rs)>;
-def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
+def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt),
+         (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>;
+def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt),
+         (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>;
+def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt),
+         (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>;
 
-// Count trailing ones: 32-bit.
-def: Pat<(cttz (not I32:$Rs)), (S2_ct1 I32:$Rs)>;
 
-let AddedComplexity = 20 in { // Complexity greater than and/or/xor
-  def: Pat<(and I32:$Rs, IsNPow2_32:$V),
-           (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>;
-  def: Pat<(or I32:$Rs, IsPow2_32:$V),
-           (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>;
-  def: Pat<(xor I32:$Rs, IsPow2_32:$V),
-           (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>;
+class HvxSel_pat<InstHexagon MI, PatFrag RegPred>
+  : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt),
+        (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>;
 
-  def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))),
-           (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
-  def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)),
-           (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
-  def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)),
-           (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
+let Predicates = [HasV60T,UseHVX] in {
+  def: HvxSel_pat<PS_vselect, HVI8>;
+  def: HvxSel_pat<PS_vselect, HVI16>;
+  def: HvxSel_pat<PS_vselect, HVI32>;
+  def: HvxSel_pat<PS_wselect, HWI8>;
+  def: HvxSel_pat<PS_wselect, HWI16>;
+  def: HvxSel_pat<PS_wselect, HWI32>;
 }
 
-// Clr/set/toggle bit for 64-bit values with immediate bit index.
-let AddedComplexity = 20 in { // Complexity greater than and/or/xor
-  def: Pat<(and I64:$Rss, IsNPow2_64L:$V),
-           (REG_SEQUENCE DoubleRegs,
-                (i32 (HiReg $Rss)), isub_hi,
-                (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)), isub_lo)>;
-  def: Pat<(and I64:$Rss, IsNPow2_64H:$V),
-           (REG_SEQUENCE DoubleRegs,
-                (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))),
-                isub_hi,
-                (i32 (LoReg $Rss)), isub_lo)>;
+// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw).
+def: Pat<(select I1:$Pu, I1:$Pv, I1:$Pw),
+         (C2_or (C2_and  I1:$Pu, I1:$Pv),
+                (C2_andn I1:$Pw, I1:$Pu))>;
 
-  def: Pat<(or I64:$Rss, IsPow2_64L:$V),
-           (REG_SEQUENCE DoubleRegs,
-                (i32 (HiReg $Rss)), isub_hi,
-                (S2_setbit_i (LoReg $Rss), (Log2_64 $V)), isub_lo)>;
-  def: Pat<(or I64:$Rss, IsPow2_64H:$V),
-           (REG_SEQUENCE DoubleRegs,
-                (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
-                isub_hi,
-                (i32 (LoReg $Rss)), isub_lo)>;
 
-  def: Pat<(xor I64:$Rss, IsPow2_64L:$V),
-           (REG_SEQUENCE DoubleRegs,
-                (i32 (HiReg $Rss)), isub_hi,
-                (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)), isub_lo)>;
-  def: Pat<(xor I64:$Rss, IsPow2_64H:$V),
-           (REG_SEQUENCE DoubleRegs,
-                (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
-                isub_hi,
-                (i32 (LoReg $Rss)), isub_lo)>;
+def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{
+  return isPositiveHalfWord(N);
+}]>;
+
+multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA,
+                            InstHexagon InstB> {
+  def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)),
+                               IsPosHalf:$Rs, IsPosHalf:$Rt), i16),
+           (InstA IntRegs:$Rs, IntRegs:$Rt)>;
+  def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)),
+                               IsPosHalf:$Rt, IsPosHalf:$Rs), i16),
+           (InstB IntRegs:$Rs, IntRegs:$Rt)>;
 }
 
-let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
-  def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)),
-           (S2_tstbit_i IntRegs:$Rs, u5_0ImmPred:$u5)>;
-  def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)),
-           (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
-  def: Pat<(i1 (trunc I32:$Rs)),
-           (S2_tstbit_i IntRegs:$Rs, 0)>;
-  def: Pat<(i1 (trunc I64:$Rs)),
-           (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
+let AddedComplexity = 200 in {
+  defm: SelMinMax16_pats<setge,  A2_max,  A2_min>;
+  defm: SelMinMax16_pats<setgt,  A2_max,  A2_min>;
+  defm: SelMinMax16_pats<setle,  A2_min,  A2_max>;
+  defm: SelMinMax16_pats<setlt,  A2_min,  A2_max>;
+  defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>;
+  defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>;
+  defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>;
+  defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>;
 }
 
-let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
-  def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)),
-           (C2_bitsclri IntRegs:$Rs, u6_0ImmPred:$u6)>;
-  def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)),
-           (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
+let AddedComplexity = 200 in {
+  defm: SelMinMax_pats<setge,  I32, A2_max,   A2_min>;
+  defm: SelMinMax_pats<setgt,  I32, A2_max,   A2_min>;
+  defm: SelMinMax_pats<setle,  I32, A2_min,   A2_max>;
+  defm: SelMinMax_pats<setlt,  I32, A2_min,   A2_max>;
+  defm: SelMinMax_pats<setuge, I32, A2_maxu,  A2_minu>;
+  defm: SelMinMax_pats<setugt, I32, A2_maxu,  A2_minu>;
+  defm: SelMinMax_pats<setule, I32, A2_minu,  A2_maxu>;
+  defm: SelMinMax_pats<setult, I32, A2_minu,  A2_maxu>;
+
+  defm: SelMinMax_pats<setge,  I64, A2_maxp,  A2_minp>;
+  defm: SelMinMax_pats<setgt,  I64, A2_maxp,  A2_minp>;
+  defm: SelMinMax_pats<setle,  I64, A2_minp,  A2_maxp>;
+  defm: SelMinMax_pats<setlt,  I64, A2_minp,  A2_maxp>;
+  defm: SelMinMax_pats<setuge, I64, A2_maxup, A2_minup>;
+  defm: SelMinMax_pats<setugt, I64, A2_maxup, A2_minup>;
+  defm: SelMinMax_pats<setule, I64, A2_minup, A2_maxup>;
+  defm: SelMinMax_pats<setult, I64, A2_minup, A2_maxup>;
 }
 
-let AddedComplexity = 10 in   // Complexity greater than compare reg-reg.
-def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)),
-         (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
+let AddedComplexity = 100, Predicates = [HasV5T] in {
+  defm: SelMinMax_pats<setolt, F32, F2_sfmin, F2_sfmax>;
+  defm: SelMinMax_pats<setole, F32, F2_sfmin, F2_sfmax>;
+  defm: SelMinMax_pats<setogt, F32, F2_sfmax, F2_sfmin>;
+  defm: SelMinMax_pats<setoge, F32, F2_sfmax, F2_sfmin>;
+}
 
-def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add I32:$b, 3))),
-                               (i32 8)),
-                          (i32 (zextloadi8 (add I32:$b, 2)))),
-                      (i32 16)),
-                 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))),
-             (zextloadi8 I32:$b)),
-         (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
 
-// Patterns for loads of i1:
-def: Pat<(i1 (load AddrFI:$fi)),
-         (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
-def: Pat<(i1 (load (add I32:$Rs, s32_0ImmPred:$Off))),
-         (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
-def: Pat<(i1 (load I32:$Rs)),
-         (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
+// --(7) Insert/extract --------------------------------------------------
+//
 
-def I1toI32: OutPatFrag<(ops node:$Rs),
-                        (C2_muxii (i1 $Rs), 1, 0)>;
+def SDTHexagonINSERT:
+  SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
+                       SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
+def SDTHexagonINSERTRP:
+  SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
+                       SDTCisInt<0>, SDTCisVT<3, i64>]>;
 
-def I32toI1: OutPatFrag<(ops node:$Rs),
-                        (i1 (C2_tfrrp (i32 $Rs)))>;
+def HexagonINSERT:    SDNode<"HexagonISD::INSERT",   SDTHexagonINSERT>;
+def HexagonINSERTRP:  SDNode<"HexagonISD::INSERTRP", SDTHexagonINSERTRP>;
 
-defm: Storexm_pat<store, I1, s32_0ImmPred, I1toI32, S2_storerb_io>;
-def: Storexm_simple_pat<store, I1, I1toI32, S2_storerb_io>;
+def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2),
+         (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>;
+def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2),
+         (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>;
+def: Pat<(HexagonINSERTRP I32:$Rs, I32:$Rt, I64:$Ru),
+         (S2_insert_rp I32:$Rs, I32:$Rt, I64:$Ru)>;
+def: Pat<(HexagonINSERTRP I64:$Rs, I64:$Rt, I64:$Ru),
+         (S2_insertp_rp I64:$Rs, I64:$Rt, I64:$Ru)>;
 
-def: Pat<(sra (add (sra I64:$src, u6_0ImmPred:$u6), 1), (i32 1)),
-         (S2_asr_i_p_rnd DoubleRegs:$src, imm:$u6)>, Requires<[HasV5T]>;
-def: Pat<(sra I64:$src, u6_0ImmPred:$u6),
-         (S2_asr_i_p DoubleRegs:$src, imm:$u6)>;
-def: Pat<(srl I64:$src, u6_0ImmPred:$u6),
-         (S2_lsr_i_p DoubleRegs:$src, imm:$u6)>;
-def: Pat<(shl I64:$src, u6_0ImmPred:$u6),
-         (S2_asl_i_p DoubleRegs:$src, imm:$u6)>;
+def SDTHexagonEXTRACTU
+  : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>,
+                  SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
+def SDTHexagonEXTRACTURP
+  : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>,
+                  SDTCisVT<2, i64>]>;
 
-let AddedComplexity = 100 in
+def HexagonEXTRACTU:   SDNode<"HexagonISD::EXTRACTU",   SDTHexagonEXTRACTU>;
+def HexagonEXTRACTURP: SDNode<"HexagonISD::EXTRACTURP", SDTHexagonEXTRACTURP>;
+
+def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5),
+         (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>;
+def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6),
+         (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>;
+def: Pat<(HexagonEXTRACTURP I32:$Rs, I64:$Rt),
+         (S2_extractu_rp I32:$Rs, I64:$Rt)>;
+def: Pat<(HexagonEXTRACTURP I64:$Rs, I64:$Rt),
+         (S2_extractup_rp I64:$Rs, I64:$Rt)>;
+
+def SDTHexagonVSPLAT:
+  SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
+
+def HexagonVSPLAT: SDNode<"HexagonISD::VSPLAT", SDTHexagonVSPLAT>;
+
+def: Pat<(v4i8  (HexagonVSPLAT I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
+def: Pat<(v4i16 (HexagonVSPLAT I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
+def: Pat<(v2i32 (HexagonVSPLAT s8_0ImmPred:$s8)),
+         (A2_combineii imm:$s8, imm:$s8)>;
+def: Pat<(v2i32 (HexagonVSPLAT I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>;
+
+
+// --(8) Shift/permute ---------------------------------------------------
+//
+
+def SDTHexagonI64I32I32: SDTypeProfile<1, 2,
+  [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
+def SDTHexagonVCOMBINE: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>,
+  SDTCisSubVecOfVec<1, 0>]>;
+def SDTHexagonVPACK: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, SDTCisVec<1>]>;
+
+def HexagonCOMBINE:  SDNode<"HexagonISD::COMBINE",  SDTHexagonI64I32I32>;
+def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>;
+def HexagonVPACKE:   SDNode<"HexagonISD::VPACKE",   SDTHexagonVPACK>;
+def HexagonVPACKO:   SDNode<"HexagonISD::VPACKO",   SDTHexagonVPACK>;
+
+def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>;
+
+// The complexity of the combines involving immediates should be greater
+// than the complexity of the combine with two registers.
+let AddedComplexity = 50 in {
+  def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8),
+           (A4_combineri IntRegs:$Rs, imm:$s8)>;
+  def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs),
+           (A4_combineir imm:$s8, IntRegs:$Rs)>;
+}
+
+// The complexity of the combine with two immediates should be greater than
+// the complexity of a combine involving a register.
+let AddedComplexity = 75 in {
+  def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, anyimm:$u6),
+           (A4_combineii imm:$s8, imm:$u6)>;
+  def: Pat<(HexagonCOMBINE anyimm:$s8, s8_0ImmPred:$S8),
+           (A2_combineii imm:$s8, imm:$S8)>;
+}
+
+def: Pat<(bswap I32:$Rs),  (A2_swiz I32:$Rs)>;
+def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)),
+                                     (A2_swiz (HiReg $Rss)))>;
+
+def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt),  (S4_lsli imm:$s6, I32:$Rt)>;
+def: Pat<(shl I32:$Rs, (i32 16)),         (A2_aslh I32:$Rs)>;
+def: Pat<(sra I32:$Rs, (i32 16)),         (A2_asrh I32:$Rs)>;
+
+def: OpR_RI_pat<S2_asr_i_r,  Sra, i32,   I32,   u5_0ImmPred>;
+def: OpR_RI_pat<S2_lsr_i_r,  Srl, i32,   I32,   u5_0ImmPred>;
+def: OpR_RI_pat<S2_asl_i_r,  Shl, i32,   I32,   u5_0ImmPred>;
+def: OpR_RI_pat<S2_asr_i_p,  Sra, i64,   I64,   u6_0ImmPred>;
+def: OpR_RI_pat<S2_lsr_i_p,  Srl, i64,   I64,   u6_0ImmPred>;
+def: OpR_RI_pat<S2_asl_i_p,  Shl, i64,   I64,   u6_0ImmPred>;
+def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>;
+def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>;
+def: OpR_RI_pat<S2_asl_i_vh, Shl, v4i16, V4I16, u4_0ImmPred>;
+def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>;
+def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>;
+def: OpR_RI_pat<S2_asl_i_vh, Shl, v2i32, V2I32, u5_0ImmPred>;
+
+def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>;
+def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>;
+def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>;
+def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>;
+def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>;
+def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>;
+
+
+def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)),
+         (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>;
+def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)),
+         (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>, Requires<[HasV5T]>;
+
+// Prefer S2_addasl_rrri over S2_asl_i_r_acc.
+let AddedComplexity = 120 in
 def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)),
          (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>;
 
-def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
-def: Pat<(HexagonBARRIER), (Y2_barrier)>;
+let AddedComplexity = 100 in {
+  def: AccRRI_pat<S2_asr_i_r_acc,   Add, Su<Sra>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_asr_i_r_nac,   Sub, Su<Sra>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_asr_i_r_and,   And, Su<Sra>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_asr_i_r_or,    Or,  Su<Sra>, I32, u5_0ImmPred>;
 
-def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off),
-         (PS_fi (i32 AddrFI:$Rs), s32_0ImmPred:$off)>;
+  def: AccRRI_pat<S2_asr_i_p_acc,   Add, Su<Sra>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_asr_i_p_nac,   Sub, Su<Sra>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_asr_i_p_and,   And, Su<Sra>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_asr_i_p_or,    Or,  Su<Sra>, I64, u6_0ImmPred>;
 
+  def: AccRRI_pat<S2_lsr_i_r_acc,   Add, Su<Srl>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_lsr_i_r_nac,   Sub, Su<Srl>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_lsr_i_r_and,   And, Su<Srl>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_lsr_i_r_or,    Or,  Su<Srl>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_lsr_i_r_xacc,  Xor, Su<Srl>, I32, u5_0ImmPred>;
 
-// Support for generating global address.
-// Taken from X86InstrInfo.td.
-def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
-                                             SDTCisVT<1, i32>,
-                                             SDTCisPtrTy<0>]>;
-def HexagonCONST32    : SDNode<"HexagonISD::CONST32",    SDTHexagonCONST32>;
-def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
+  def: AccRRI_pat<S2_lsr_i_p_acc,   Add, Su<Srl>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_lsr_i_p_nac,   Sub, Su<Srl>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_lsr_i_p_and,   And, Su<Srl>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_lsr_i_p_or,    Or,  Su<Srl>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_lsr_i_p_xacc,  Xor, Su<Srl>, I64, u6_0ImmPred>;
 
-// Map TLS addressses to A2_tfrsi.
-def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s32_0Imm:$addr)>;
-def: Pat<(HexagonCONST32 bbl:$label),           (A2_tfrsi s32_0Imm:$label)>;
+  def: AccRRI_pat<S2_asl_i_r_acc,   Add, Su<Shl>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_asl_i_r_nac,   Sub, Su<Shl>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_asl_i_r_and,   And, Su<Shl>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_asl_i_r_or,    Or,  Su<Shl>, I32, u5_0ImmPred>;
+  def: AccRRI_pat<S2_asl_i_r_xacc,  Xor, Su<Shl>, I32, u5_0ImmPred>;
 
-def: Pat<(i64 imm:$v), (CONST64 imm:$v)>;
-def: Pat<(i1 0), (PS_false)>;
-def: Pat<(i1 1), (PS_true)>;
+  def: AccRRI_pat<S2_asl_i_p_acc,   Add, Su<Shl>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_asl_i_p_nac,   Sub, Su<Shl>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_asl_i_p_and,   And, Su<Shl>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_asl_i_p_or,    Or,  Su<Shl>, I64, u6_0ImmPred>;
+  def: AccRRI_pat<S2_asl_i_p_xacc,  Xor, Su<Shl>, I64, u6_0ImmPred>;
+}
 
-// Pseudo instructions.
-def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
-                                          SDTCisVT<1, i32> ]>;
-def SDT_SPCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
-                                        SDTCisVT<1, i32> ]>;
+let AddedComplexity = 100 in {
+  def: AccRRR_pat<S2_asr_r_r_acc,   Add, Su<Sra>, I32, I32>;
+  def: AccRRR_pat<S2_asr_r_r_nac,   Sub, Su<Sra>, I32, I32>;
+  def: AccRRR_pat<S2_asr_r_r_and,   And, Su<Sra>, I32, I32>;
+  def: AccRRR_pat<S2_asr_r_r_or,    Or,  Su<Sra>, I32, I32>;
 
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
-                    [SDNPHasChain, SDNPOutGlue]>;
-def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_SPCallSeqEnd,
-                    [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
+  def: AccRRR_pat<S2_asr_r_p_acc,   Add, Su<Sra>, I64, I32>;
+  def: AccRRR_pat<S2_asr_r_p_nac,   Sub, Su<Sra>, I64, I32>;
+  def: AccRRR_pat<S2_asr_r_p_and,   And, Su<Sra>, I64, I32>;
+  def: AccRRR_pat<S2_asr_r_p_or,    Or,  Su<Sra>, I64, I32>;
+  def: AccRRR_pat<S2_asr_r_p_xor,   Xor, Su<Sra>, I64, I32>;
 
-def SDT_SPCall  : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
+  def: AccRRR_pat<S2_lsr_r_r_acc,   Add, Su<Srl>, I32, I32>;
+  def: AccRRR_pat<S2_lsr_r_r_nac,   Sub, Su<Srl>, I32, I32>;
+  def: AccRRR_pat<S2_lsr_r_r_and,   And, Su<Srl>, I32, I32>;
+  def: AccRRR_pat<S2_lsr_r_r_or,    Or,  Su<Srl>, I32, I32>;
 
-// For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
-// Optional Flag and Variable Arguments.
-// Its 1 Operand has pointer type.
-def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
-                          [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
+  def: AccRRR_pat<S2_lsr_r_p_acc,   Add, Su<Srl>, I64, I32>;
+  def: AccRRR_pat<S2_lsr_r_p_nac,   Sub, Su<Srl>, I64, I32>;
+  def: AccRRR_pat<S2_lsr_r_p_and,   And, Su<Srl>, I64, I32>;
+  def: AccRRR_pat<S2_lsr_r_p_or,    Or,  Su<Srl>, I64, I32>;
+  def: AccRRR_pat<S2_lsr_r_p_xor,   Xor, Su<Srl>, I64, I32>;
 
+  def: AccRRR_pat<S2_asl_r_r_acc,   Add, Su<Shl>, I32, I32>;
+  def: AccRRR_pat<S2_asl_r_r_nac,   Sub, Su<Shl>, I32, I32>;
+  def: AccRRR_pat<S2_asl_r_r_and,   And, Su<Shl>, I32, I32>;
+  def: AccRRR_pat<S2_asl_r_r_or,    Or,  Su<Shl>, I32, I32>;
 
-def: Pat<(callseq_start timm:$amt, timm:$amt2),
-          (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>;
-def: Pat<(callseq_end timm:$amt1, timm:$amt2),
-         (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>;
+  def: AccRRR_pat<S2_asl_r_p_acc,   Add, Su<Shl>, I64, I32>;
+  def: AccRRR_pat<S2_asl_r_p_nac,   Sub, Su<Shl>, I64, I32>;
+  def: AccRRR_pat<S2_asl_r_p_and,   And, Su<Shl>, I64, I32>;
+  def: AccRRR_pat<S2_asl_r_p_or,    Or,  Su<Shl>, I64, I32>;
+  def: AccRRR_pat<S2_asl_r_p_xor,   Xor, Su<Shl>, I64, I32>;
+}
 
-//Tail calls.
-def: Pat<(HexagonTCRet tglobaladdr:$dst),
-         (PS_tailcall_i tglobaladdr:$dst)>;
-def: Pat<(HexagonTCRet texternalsym:$dst),
-         (PS_tailcall_i texternalsym:$dst)>;
-def: Pat<(HexagonTCRet I32:$dst),
-         (PS_tailcall_r I32:$dst)>;
 
-// Map from r0 = and(r1, 65535) to r0 = zxth(r1)
-def: Pat<(and I32:$src1, 65535),
-         (A2_zxth IntRegs:$src1)>;
+class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
+                  PatFrag RegPred, PatFrag ImmPred>
+  : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
+        (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>;
 
-// Map from r0 = and(r1, 255) to r0 = zxtb(r1).
-def: Pat<(and I32:$src1, 255),
-         (A2_zxtb IntRegs:$src1)>;
+let AddedComplexity = 200 in {
+  def: OpshIRI_pat<S4_addi_asl_ri,  Add, Su<Shl>, I32, u5_0ImmPred>;
+  def: OpshIRI_pat<S4_addi_lsr_ri,  Add, Su<Srl>, I32, u5_0ImmPred>;
+  def: OpshIRI_pat<S4_subi_asl_ri,  Sub, Su<Shl>, I32, u5_0ImmPred>;
+  def: OpshIRI_pat<S4_subi_lsr_ri,  Sub, Su<Srl>, I32, u5_0ImmPred>;
+  def: OpshIRI_pat<S4_andi_asl_ri,  And, Su<Shl>, I32, u5_0ImmPred>;
+  def: OpshIRI_pat<S4_andi_lsr_ri,  And, Su<Srl>, I32, u5_0ImmPred>;
+  def: OpshIRI_pat<S4_ori_asl_ri,   Or,  Su<Shl>, I32, u5_0ImmPred>;
+  def: OpshIRI_pat<S4_ori_lsr_ri,   Or,  Su<Srl>, I32, u5_0ImmPred>;
+}
 
-// Map Add(p1, true) to p1 = not(p1).
-//     Add(p1, false) should never be produced,
-//     if it does, it got to be mapped to NOOP.
-def: Pat<(add I1:$src1, -1),
-         (C2_not PredRegs:$src1)>;
+// Prefer this pattern to S2_asl_i_p_or for the special case of joining
+// two 32-bit words into a 64-bit word.
+let AddedComplexity = 200 in
+def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)),
+         (Combinew I32:$a, I32:$b)>;
 
-// Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
-def: Pat<(select (not I1:$src1), s8_0ImmPred:$src2, s32_0ImmPred:$src3),
-         (C2_muxii PredRegs:$src1, s32_0ImmPred:$src3, s8_0ImmPred:$src2)>;
+def: Pat<(or (or (or (shl (Zext64 (and I32:$b, (i32 65535))), (i32 16)),
+                     (Zext64 (and I32:$a, (i32 65535)))),
+                 (shl (Aext64 (and I32:$c, (i32 65535))), (i32 32))),
+             (shl (Aext64 I32:$d), (i32 48))),
+         (Combinew (A2_combine_ll I32:$d, I32:$c),
+                   (A2_combine_ll I32:$b, I32:$a))>;
 
-// Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
-// => r0 = C2_muxir(p0, r1, #i)
-def: Pat<(select (not I1:$src1), s32_0ImmPred:$src2,
-                 I32:$src3),
-         (C2_muxir PredRegs:$src1, IntRegs:$src3, s32_0ImmPred:$src2)>;
+def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add I32:$b, 3))),
+                               (i32 8)),
+                          (i32 (zextloadi8 (add I32:$b, 2)))),
+                      (i32 16)),
+                 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))),
+             (zextloadi8 I32:$b)),
+         (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
 
-// Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
-// => r0 = C2_muxri (p0, #i, r1)
-def: Pat<(select (not I1:$src1), IntRegs:$src2, s32_0ImmPred:$src3),
-         (C2_muxri PredRegs:$src1, s32_0ImmPred:$src3, IntRegs:$src2)>;
+let AddedComplexity = 200 in {
+  def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))),
+           (A2_combine_ll I32:$Rt, I32:$Rs)>;
+  def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))),
+           (A2_combine_lh I32:$Rt, I32:$Rs)>;
+  def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))),
+           (A2_combine_hl I32:$Rt, I32:$Rs)>;
+  def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))),
+           (A2_combine_hh I32:$Rt, I32:$Rs)>;
+}
 
-// Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
-def: Pat<(brcond (not I1:$src1), bb:$offset),
-         (J2_jumpf PredRegs:$src1, bb:$offset)>;
+def SDTHexagonVShift
+  : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>;
 
-// Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
-def: Pat<(i64 (sext_inreg I64:$src1, i32)),
-         (A2_sxtw (LoReg DoubleRegs:$src1))>;
+def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>;
+def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>;
+def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>;
 
-// Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(A2_sxth(Rss.lo)).
-def: Pat<(i64 (sext_inreg I64:$src1, i16)),
-         (A2_sxtw (A2_sxth (LoReg DoubleRegs:$src1)))>;
+def: OpR_RI_pat<S2_asl_i_vw, pf2<HexagonVASL>, v2i32, V2I32, u5_0ImmPred>;
+def: OpR_RI_pat<S2_asl_i_vh, pf2<HexagonVASL>, v4i16, V4I16, u4_0ImmPred>;
+def: OpR_RI_pat<S2_asr_i_vw, pf2<HexagonVASR>, v2i32, V2I32, u5_0ImmPred>;
+def: OpR_RI_pat<S2_asr_i_vh, pf2<HexagonVASR>, v4i16, V4I16, u4_0ImmPred>;
+def: OpR_RI_pat<S2_lsr_i_vw, pf2<HexagonVLSR>, v2i32, V2I32, u5_0ImmPred>;
+def: OpR_RI_pat<S2_lsr_i_vh, pf2<HexagonVLSR>, v4i16, V4I16, u4_0ImmPred>;
 
-// Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(A2_sxtb(Rss.lo)).
-def: Pat<(i64 (sext_inreg I64:$src1, i8)),
-         (A2_sxtw (A2_sxtb (LoReg DoubleRegs:$src1)))>;
+def: OpR_RR_pat<S2_asl_r_vw, pf2<HexagonVASL>, v2i32, V2I32, I32>;
+def: OpR_RR_pat<S2_asl_r_vh, pf2<HexagonVASL>, v4i16, V4I16, I32>;
+def: OpR_RR_pat<S2_asr_r_vw, pf2<HexagonVASR>, v2i32, V2I32, I32>;
+def: OpR_RR_pat<S2_asr_r_vh, pf2<HexagonVASR>, v4i16, V4I16, I32>;
+def: OpR_RR_pat<S2_lsr_r_vw, pf2<HexagonVLSR>, v2i32, V2I32, I32>;
+def: OpR_RR_pat<S2_lsr_r_vh, pf2<HexagonVLSR>, v4i16, V4I16, I32>;
 
-def: Pat<(brcond (i1 (setne I32:$Rs, I32:$Rt)), bb:$offset),
-         (J2_jumpf (C2_cmpeq I32:$Rs, I32:$Rt), bb:$offset)>;
-def: Pat<(brcond (i1 (setne I32:$Rs, s10_0ImmPred:$s10)), bb:$offset),
-         (J2_jumpf (C2_cmpeqi I32:$Rs, imm:$s10), bb:$offset)>;
-def: Pat<(brcond (i1 (setne I1:$Pu, (i1 -1))), bb:$offset),
-         (J2_jumpf PredRegs:$Pu, bb:$offset)>;
-def: Pat<(brcond (i1 (setne I1:$Pu, (i1 0))), bb:$offset),
-         (J2_jumpt PredRegs:$Pu, bb:$offset)>;
+def: Pat<(sra V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))),
+         (S2_asr_i_vw V2I32:$b, imm:$c)>;
+def: Pat<(srl V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))),
+         (S2_lsr_i_vw V2I32:$b, imm:$c)>;
+def: Pat<(shl V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))),
+         (S2_asl_i_vw V2I32:$b, imm:$c)>;
+def: Pat<(sra V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))),
+         (S2_asr_i_vh V4I16:$b, imm:$c)>;
+def: Pat<(srl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))),
+         (S2_lsr_i_vh V4I16:$b, imm:$c)>;
+def: Pat<(shl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))),
+         (S2_asl_i_vh V4I16:$b, imm:$c)>;
 
-// cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
-def: Pat<(brcond (i1 (setlt I32:$Rs, s8_0ImmPred:$s8)), bb:$offset),
-         (J2_jumpf (C2_cmpgti IntRegs:$Rs, (SDEC1 imm:$s8)), bb:$offset)>;
 
+// --(9) Arithmetic/bitwise ----------------------------------------------
+//
 
-// Map from a 64-bit select to an emulated 64-bit mux.
-// Hexagon does not support 64-bit MUXes; so emulate with combines.
-def: Pat<(select I1:$src1, I64:$src2,
-                 I64:$src3),
-         (A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2),
-                                              (HiReg DoubleRegs:$src3)),
-                      (C2_mux PredRegs:$src1, (LoReg DoubleRegs:$src2),
-                                              (LoReg DoubleRegs:$src3)))>;
+def: Pat<(abs I32:$Rs), (A2_abs   I32:$Rs)>;
+def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>;
+def: Pat<(not I64:$Rs), (A2_notp  I64:$Rs)>;
 
-// Map from a 1-bit select to logical ops.
-// From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
-def: Pat<(select I1:$src1, I1:$src2, I1:$src3),
-         (C2_or (C2_and PredRegs:$src1, PredRegs:$src2),
-                (C2_and (C2_not PredRegs:$src1), PredRegs:$src3))>;
+let Predicates = [HasV5T] in {
+  def: Pat<(fabs F32:$Rs), (S2_clrbit_i    F32:$Rs, 31)>;
+  def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>;
 
-// Map for truncating from 64 immediates to 32 bit immediates.
-def: Pat<(i32 (trunc I64:$src)),
-         (LoReg DoubleRegs:$src)>;
+  def: Pat<(fabs F64:$Rs),
+           (Combinew (S2_clrbit_i (HiReg $Rs), 31),
+                     (i32 (LoReg $Rs)))>;
+  def: Pat<(fneg F64:$Rs),
+           (Combinew (S2_togglebit_i (HiReg $Rs), 31),
+                     (i32 (LoReg $Rs)))>;
+}
 
-// Map for truncating from i64 immediates to i1 bit immediates.
-def: Pat<(i1 (trunc I64:$src)),
-         (C2_tfrrp (LoReg DoubleRegs:$src))>;
+let AddedComplexity = 50 in
+def: Pat<(xor (add (sra I32:$Rs, (i32 31)),
+                   I32:$Rs),
+              (sra I32:$Rs, (i32 31))),
+         (A2_abs I32:$Rs)>;
 
-// rs <= rt -> !(rs > rt).
-let AddedComplexity = 30 in
-def: Pat<(i1 (setle I32:$src1, s32_0ImmPred:$src2)),
-         (C2_not (C2_cmpgti IntRegs:$src1, s32_0ImmPred:$src2))>;
 
-// rs <= rt -> !(rs > rt).
-def : Pat<(i1 (setle I32:$src1, I32:$src2)),
-      (i1 (C2_not (C2_cmpgt I32:$src1, I32:$src2)))>;
+def: Pat<(add I32:$Rs, anyimm:$s16),   (A2_addi   I32:$Rs,  imm:$s16)>;
+def: Pat<(or  I32:$Rs, anyimm:$s10),   (A2_orir   I32:$Rs,  imm:$s10)>;
+def: Pat<(and I32:$Rs, anyimm:$s10),   (A2_andir  I32:$Rs,  imm:$s10)>;
+def: Pat<(sub anyimm:$s10, I32:$Rs),   (A2_subri  imm:$s10, I32:$Rs)>;
 
-// Rss <= Rtt -> !(Rss > Rtt).
-def: Pat<(i1 (setle I64:$src1, I64:$src2)),
-         (C2_not (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>;
+def: OpR_RR_pat<A2_add,       Add,        i32,   I32>;
+def: OpR_RR_pat<A2_sub,       Sub,        i32,   I32>;
+def: OpR_RR_pat<A2_and,       And,        i32,   I32>;
+def: OpR_RR_pat<A2_or,        Or,         i32,   I32>;
+def: OpR_RR_pat<A2_xor,       Xor,        i32,   I32>;
+def: OpR_RR_pat<A2_addp,      Add,        i64,   I64>;
+def: OpR_RR_pat<A2_subp,      Sub,        i64,   I64>;
+def: OpR_RR_pat<A2_andp,      And,        i64,   I64>;
+def: OpR_RR_pat<A2_orp,       Or,         i64,   I64>;
+def: OpR_RR_pat<A2_xorp,      Xor,        i64,   I64>;
+def: OpR_RR_pat<A4_andnp,     Not2<And>,  i64,   I64>;
+def: OpR_RR_pat<A4_ornp,      Not2<Or>,   i64,   I64>;
 
-// Map cmpne -> cmpeq.
-// Hexagon_TODO: We should improve on this.
-// rs != rt -> !(rs == rt).
-let AddedComplexity = 30 in
-def: Pat<(i1 (setne I32:$src1, s32_0ImmPred:$src2)),
-         (C2_not (C2_cmpeqi IntRegs:$src1, s32_0ImmPred:$src2))>;
+def: OpR_RR_pat<A2_svaddh,    Add,        v2i16, V2I16>;
+def: OpR_RR_pat<A2_svsubh,    Sub,        v2i16, V2I16>;
 
-// Convert setne back to xor for hexagon since we compute w/ pred registers.
-def: Pat<(i1 (setne I1:$src1, I1:$src2)),
-         (C2_xor PredRegs:$src1, PredRegs:$src2)>;
+def: OpR_RR_pat<A2_vaddub,    Add,        v8i8,  V8I8>;
+def: OpR_RR_pat<A2_vaddh,     Add,        v4i16, V4I16>;
+def: OpR_RR_pat<A2_vaddw,     Add,        v2i32, V2I32>;
+def: OpR_RR_pat<A2_vsubub,    Sub,        v8i8,  V8I8>;
+def: OpR_RR_pat<A2_vsubh,     Sub,        v4i16, V4I16>;
+def: OpR_RR_pat<A2_vsubw,     Sub,        v2i32, V2I32>;
 
-// Map cmpne(Rss) -> !cmpew(Rss).
-// rs != rt -> !(rs == rt).
-def: Pat<(i1 (setne I64:$src1, I64:$src2)),
-         (C2_not (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>;
+def: OpR_RR_pat<A2_and,       And,        v2i16, V2I16>;
+def: OpR_RR_pat<A2_xor,       Xor,        v2i16, V2I16>;
+def: OpR_RR_pat<A2_or,        Or,         v2i16, V2I16>;
 
-// rs >= rt -> rt <= rs
-def: Pat<(i1 (setge I32:$Rs, I32:$Rt)),
-         (C4_cmplte I32:$Rt, I32:$Rs)>;
+def: OpR_RR_pat<A2_andp,      And,        v8i8,  V8I8>;
+def: OpR_RR_pat<A2_andp,      And,        v4i16, V4I16>;
+def: OpR_RR_pat<A2_andp,      And,        v2i32, V2I32>;
+def: OpR_RR_pat<A2_orp,       Or,         v8i8,  V8I8>;
+def: OpR_RR_pat<A2_orp,       Or,         v4i16, V4I16>;
+def: OpR_RR_pat<A2_orp,       Or,         v2i32, V2I32>;
+def: OpR_RR_pat<A2_xorp,      Xor,        v8i8,  V8I8>;
+def: OpR_RR_pat<A2_xorp,      Xor,        v4i16, V4I16>;
+def: OpR_RR_pat<A2_xorp,      Xor,        v2i32, V2I32>;
 
-let AddedComplexity = 30 in
-def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)),
-         (C2_cmpgti IntRegs:$Rs, (SDEC1 imm:$s10))>;
+def: OpR_RR_pat<M2_mpyi,      Mul,        i32,   I32>;
+def: OpR_RR_pat<M2_mpy_up,    pf2<mulhs>, i32,   I32>;
+def: OpR_RR_pat<M2_mpyu_up,   pf2<mulhu>, i32,   I32>;
+def: OpR_RI_pat<M2_mpysip,    Mul,        i32,   I32, u32_0ImmPred>;
+def: OpR_RI_pat<M2_mpysmi,    Mul,        i32,   I32, s32_0ImmPred>;
 
-// Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
-// rss >= rtt -> !(rtt > rss).
-def: Pat<(i1 (setge I64:$src1, I64:$src2)),
-         (C2_not (C2_cmpgtp DoubleRegs:$src2, DoubleRegs:$src1))>;
+// Arithmetic on predicates.
+def: OpR_RR_pat<C2_xor,       Add,        i1,    I1>;
+def: OpR_RR_pat<C2_xor,       Add,        v2i1,  V2I1>;
+def: OpR_RR_pat<C2_xor,       Add,        v4i1,  V4I1>;
+def: OpR_RR_pat<C2_xor,       Add,        v8i1,  V8I1>;
+def: OpR_RR_pat<C2_xor,       Sub,        i1,    I1>;
+def: OpR_RR_pat<C2_xor,       Sub,        v2i1,  V2I1>;
+def: OpR_RR_pat<C2_xor,       Sub,        v4i1,  V4I1>;
+def: OpR_RR_pat<C2_xor,       Sub,        v8i1,  V8I1>;
+def: OpR_RR_pat<C2_and,       Mul,        i1,    I1>;
+def: OpR_RR_pat<C2_and,       Mul,        v2i1,  V2I1>;
+def: OpR_RR_pat<C2_and,       Mul,        v4i1,  V4I1>;
+def: OpR_RR_pat<C2_and,       Mul,        v8i1,  V8I1>;
 
-// Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
-// !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
-// rs < rt -> !(rs >= rt).
-let AddedComplexity = 30 in
-def: Pat<(i1 (setlt I32:$src1, s32_0ImmPred:$src2)),
-         (C2_not (C2_cmpgti IntRegs:$src1, (SDEC1 s32_0ImmPred:$src2)))>;
+let Predicates = [HasV5T] in {
+  def: OpR_RR_pat<F2_sfadd,     pf2<fadd>,    f32, F32>;
+  def: OpR_RR_pat<F2_sfsub,     pf2<fsub>,    f32, F32>;
+  def: OpR_RR_pat<F2_sfmpy,     pf2<fmul>,    f32, F32>;
+  def: OpR_RR_pat<F2_sfmin,     pf2<fminnum>, f32, F32>;
+  def: OpR_RR_pat<F2_sfmax,     pf2<fmaxnum>, f32, F32>;
+}
 
-// Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
-def: Pat<(i1 (setuge I32:$src1, 0)),
-         (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
+// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add,
+// over add-add with individual multiplies as inputs.
+let AddedComplexity = 10 in {
+  def: AccRRI_pat<M2_macsip,    Add, Su<Mul>, I32, u32_0ImmPred>;
+  def: AccRRI_pat<M2_macsin,    Sub, Su<Mul>, I32, u32_0ImmPred>;
+  def: AccRRR_pat<M2_maci,      Add, Su<Mul>, I32, I32>;
+}
 
-// Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
-def: Pat<(i1 (setuge I32:$src1, u32_0ImmPred:$src2)),
-         (C2_cmpgtui IntRegs:$src1, (UDEC1 u32_0ImmPred:$src2))>;
+def: AccRRI_pat<M2_naccii,    Sub, Su<Add>, I32, s32_0ImmPred>;
+def: AccRRI_pat<M2_accii,     Add, Su<Add>, I32, s32_0ImmPred>;
+def: AccRRR_pat<M2_acci,      Add, Su<Add>, I32, I32>;
 
-// Generate cmpgtu(Rs, #u9)
-def: Pat<(i1 (setugt I32:$src1, u32_0ImmPred:$src2)),
-         (C2_cmpgtui IntRegs:$src1, u32_0ImmPred:$src2)>;
 
-// Map from Rs >= Rt -> !(Rt > Rs).
-// rs >= rt -> !(rt > rs).
-def: Pat<(i1 (setuge I64:$src1, I64:$src2)),
-         (C2_not (C2_cmpgtup DoubleRegs:$src2, DoubleRegs:$src1))>;
+def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)),
+         (M2_mpysin IntRegs:$Rs, imm:$u8)>;
 
-// Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
-// Map from (Rs <= Rt) -> !(Rs > Rt).
-def: Pat<(i1 (setule I64:$src1, I64:$src2)),
-         (C2_not (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>;
+def n8_0ImmPred: PatLeaf<(i32 imm), [{
+  int64_t V = N->getSExtValue();
+  return -255 <= V && V <= 0;
+}]>;
 
-// Sign extends.
-// sext i1->i32
-def: Pat<(i32 (sext I1:$Pu)),
-         (C2_muxii I1:$Pu, -1, 0)>;
+// Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
+def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8),
+         (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>;
 
-// sext i1->i64
-def: Pat<(i64 (sext I1:$Pu)),
-         (A2_combinew (C2_muxii PredRegs:$Pu, -1, 0),
-                      (C2_muxii PredRegs:$Pu, -1, 0))>;
+def: Pat<(add Sext64:$Rs, I64:$Rt),
+         (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>;
 
-// Zero extends.
-// zext i1->i32
-def: Pat<(i32 (zext I1:$Pu)),
-         (C2_muxii PredRegs:$Pu, 1, 0)>;
+def: AccRRR_pat<M4_and_and,   And, Su<And>,       I32,  I32>;
+def: AccRRR_pat<M4_and_or,    And, Su<Or>,        I32,  I32>;
+def: AccRRR_pat<M4_and_xor,   And, Su<Xor>,       I32,  I32>;
+def: AccRRR_pat<M4_or_and,    Or,  Su<And>,       I32,  I32>;
+def: AccRRR_pat<M4_or_or,     Or,  Su<Or>,        I32,  I32>;
+def: AccRRR_pat<M4_or_xor,    Or,  Su<Xor>,       I32,  I32>;
+def: AccRRR_pat<M4_xor_and,   Xor, Su<And>,       I32,  I32>;
+def: AccRRR_pat<M4_xor_or,    Xor, Su<Or>,        I32,  I32>;
+def: AccRRR_pat<M2_xor_xacc,  Xor, Su<Xor>,       I32,  I32>;
+def: AccRRR_pat<M4_xor_xacc,  Xor, Su<Xor>,       I64,  I64>;
 
-// zext i1->i64
-def: Pat<(i64 (zext I1:$Pu)),
-         (ToZext64 (C2_muxii PredRegs:$Pu, 1, 0))>;
+// For dags like (or (and (not _), _), (shl _, _)) where the "or" with
+// one argument matches the patterns below, and with the other argument
+// matches S2_asl_r_r_or, etc, prefer the patterns below.
+let AddedComplexity = 110 in {  // greater than S2_asl_r_r_and/or/xor.
+  def: AccRRR_pat<M4_and_andn,  And, Su<Not2<And>>, I32,  I32>;
+  def: AccRRR_pat<M4_or_andn,   Or,  Su<Not2<And>>, I32,  I32>;
+  def: AccRRR_pat<M4_xor_andn,  Xor, Su<Not2<And>>, I32,  I32>;
+}
 
-// zext i32->i64
-def: Pat<(Zext64 I32:$Rs),
-         (ToZext64 IntRegs:$Rs)>;
+// S4_addaddi and S4_subaddi don't have tied operands, so give them
+// a bit of preference.
+let AddedComplexity = 30 in {
+  def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)),
+           (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>;
+  def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)),
+           (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>;
+  def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)),
+           (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
+  def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru),
+           (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
+  def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6),
+           (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
+}
 
-// Map from Rs = Pd to Pd = mux(Pd, #1, #0)
-def: Pat<(i32 (anyext I1:$Pu)),
-         (C2_muxii PredRegs:$Pu, 1, 0)>;
+def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)),
+         (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>;
+def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)),
+         (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>;
+def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)),
+         (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>;
 
-// Map from Rss = Pd to Rdd = combine(#0, (mux(Pd, #1, #0)))
-def: Pat<(i64 (anyext I1:$Pu)),
-         (ToZext64 (C2_muxii PredRegs:$Pu, 1, 0))>;
 
-// Clear the sign bit in a 64-bit register.
-def ClearSign : OutPatFrag<(ops node:$Rss),
-  (A2_combinew (S2_clrbit_i (HiReg $Rss), 31), (LoReg $Rss))>;
+def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))),
+         (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))),
+         (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+
+def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)),
+         (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>;
+def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)),
+         (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>;
+def: Pat<(mul Sext64:$Rs, Sext64:$Rt),
+         (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+
+def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)),
+         (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)),
+         (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))),
+         (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
+def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))),
+         (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
+def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))),
+         (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
+def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))),
+         (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
+
+// Add halfword.
+def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16),
+         (A2_addh_l16_ll I32:$Rt, I32:$Rs)>;
+def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)),
+         (A2_addh_l16_hl I32:$Rt, I32:$Rs)>;
+def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)),
+         (A2_addh_h16_ll I32:$Rt, I32:$Rs)>;
+
+// Subtract halfword.
+def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16),
+         (A2_subh_l16_ll I32:$Rt, I32:$Rs)>;
+def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)),
+         (A2_addh_l16_hl I32:$Rt, I32:$Rs)>;
+def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)),
+         (A2_subh_h16_ll I32:$Rt, I32:$Rs)>;
+
+def: Pat<(mul I64:$Rss, I64:$Rtt),
+         (Combinew
+           (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))),
+                             (LoReg $Rss),
+                             (HiReg $Rtt)),
+                    (LoReg $Rtt),
+                    (HiReg $Rss)),
+           (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>;
 
 def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt),
   (A2_addp
@@ -954,8 +1393,7 @@ def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt),
             (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32),
             (HiReg $Rss),
             (LoReg $Rtt)),
-          (A2_combinew (A2_tfrsi 0),
-                       (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))),
+          (A4_combineir 0, (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))),
         32),
       (HiReg $Rss),
       (HiReg $Rtt)),
@@ -975,6 +1413,10 @@ def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>;
 //      = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A']
 //      = (unsigned product AB) - 2^64 [s(A)B'+s(B)A']
 
+// Clear the sign bit in a 64-bit register.
+def ClearSign : OutPatFrag<(ops node:$Rss),
+  (Combinew (S2_clrbit_i (HiReg $Rss), 31), (i32 (LoReg $Rss)))>;
+
 def : Pat <(mulhs I64:$Rss, I64:$Rtt),
   (A2_subp
     (MulHU $Rss, $Rtt),
@@ -982,466 +1424,740 @@ def : Pat <(mulhs I64:$Rss, I64:$Rtt),
       (A2_andp (S2_asr_i_p $Rss, 63), (ClearSign $Rtt)),
       (A2_andp (S2_asr_i_p $Rtt, 63), (ClearSign $Rss))))>;
 
-// Hexagon specific ISD nodes.
-def SDTHexagonALLOCA : SDTypeProfile<1, 2,
-      [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
-def HexagonALLOCA : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA,
-      [SDNPHasChain]>;
+// Prefer these instructions over M2_macsip/M2_macsin: the macsi* instructions
+// will put the immediate addend into a register, while these instructions will
+// use it directly. Such a construct does not appear in the middle of a gep,
+// where M2_macsip would be preferable.
+let AddedComplexity = 20 in {
+  def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6),
+           (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>;
+  def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6),
+           (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>;
+}
 
+// Keep these instructions less preferable to M2_macsip/M2_macsin.
+def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)),
+         (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>;
+def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)),
+         (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>;
+def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)),
+         (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>;
 
-def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)),
-         (PS_alloca IntRegs:$Rs, imm:$A)>;
 
-def HexagonJT:     SDNode<"HexagonISD::JT", SDTIntUnaryOp>;
-def HexagonCP:     SDNode<"HexagonISD::CP", SDTIntUnaryOp>;
+let Predicates = [HasV5T] in {
+  def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx),
+           (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>;
+  def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx),
+           (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>;
+  def: Pat<(fma F32:$Rs, (fneg F32:$Rt), F32:$Rx),
+           (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>;
+}
 
-def: Pat<(HexagonJT tjumptable:$dst), (A2_tfrsi imm:$dst)>;
-def: Pat<(HexagonCP tconstpool:$dst), (A2_tfrsi imm:$dst)>;
 
-let AddedComplexity = 100 in
-def: Pat<(add I32:$src1, (sra I32:$Rs, u5_0ImmPred:$u5)), (S2_asr_i_r_acc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-def: Pat<(sub I32:$src1, (sra I32:$Rs, u5_0ImmPred:$u5)), (S2_asr_i_r_nac IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-def: Pat<(and I32:$src1, (sra I32:$Rs, u5_0ImmPred:$u5)), (S2_asr_i_r_and IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-def: Pat<(or I32:$src1, (sra I32:$Rs, u5_0ImmPred:$u5)), (S2_asr_i_r_or IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
+def: Pat<(mul V2I32:$Rs, V2I32:$Rt),
+         (PS_vmulw V2I32:$Rs, V2I32:$Rt)>;
+def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)),
+         (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>;
 
-let AddedComplexity = 100 in
-def: Pat<(add I64:$src1, (sra I64:$Rs, u6_0ImmPred:$u5)), (S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-def: Pat<(sub I64:$src1, (sra I64:$Rs, u6_0ImmPred:$u5)), (S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-def: Pat<(and I64:$src1, (sra I64:$Rs, u6_0ImmPred:$u5)), (S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-def: Pat<(or I64:$src1, (sra I64:$Rs, u6_0ImmPred:$u5)), (S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
+// Add/subtract two v4i8: Hexagon does not have an insn for this one, so
+// we use the double add v8i8, and use only the low part of the result.
+def: Pat<(add V4I8:$Rs, V4I8:$Rt),
+         (LoReg (A2_vaddub (ToZext64 $Rs), (ToZext64 $Rt)))>;
+def: Pat<(sub V4I8:$Rs, V4I8:$Rt),
+         (LoReg (A2_vsubub (ToZext64 $Rs), (ToZext64 $Rt)))>;
 
-let AddedComplexity = 100 in
-def: Pat<(add I32:$src1, (srl I32:$Rs, u5_0ImmPred:$u5)), (S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-def: Pat<(sub I32:$src1, (srl I32:$Rs, u5_0ImmPred:$u5)), (S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-def: Pat<(and I32:$src1, (srl I32:$Rs, u5_0ImmPred:$u5)), (S2_lsr_i_r_and IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-def: Pat<(or I32:$src1, (srl I32:$Rs, u5_0ImmPred:$u5)), (S2_lsr_i_r_or IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-let AddedComplexity = 100 in
-def: Pat<(xor I32:$src1, (srl I32:$Rs, u5_0ImmPred:$u5)), (S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
+// Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two
+// half-words, and saturates the result to a 32-bit value, except the
+// saturation never happens (it can only occur with scaling).
+def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)),
+         (LoReg (S2_vtrunewh (A2_combineii 0, 0),
+                             (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>;
+def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)),
+         (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)),
+                      (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>;
 
-let AddedComplexity = 100 in
-def: Pat<(add I64:$src1, (srl I64:$Rs, u6_0ImmPred:$u5)), (S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-def: Pat<(sub I64:$src1, (srl I64:$Rs, u6_0ImmPred:$u5)), (S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-def: Pat<(and I64:$src1, (srl I64:$Rs, u6_0ImmPred:$u5)), (S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-def: Pat<(or I64:$src1, (srl I64:$Rs, u6_0ImmPred:$u5)), (S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-let AddedComplexity = 100 in
-def: Pat<(xor I64:$src1, (srl I64:$Rs, u6_0ImmPred:$u5)), (S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
+// Multiplies two v4i8 vectors.
+def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)),
+         (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>,
+     Requires<[HasV5T]>;
 
-let AddedComplexity = 100 in
-def: Pat<(add I32:$src1, (shl I32:$Rs, u5_0ImmPred:$u5)), (S2_asl_i_r_acc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-def: Pat<(sub I32:$src1, (shl I32:$Rs, u5_0ImmPred:$u5)), (S2_asl_i_r_nac IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-def: Pat<(and I32:$src1, (shl I32:$Rs, u5_0ImmPred:$u5)), (S2_asl_i_r_and IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-def: Pat<(or I32:$src1, (shl I32:$Rs, u5_0ImmPred:$u5)), (S2_asl_i_r_or IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
-let AddedComplexity = 100 in
-def: Pat<(xor I32:$src1, (shl I32:$Rs, u5_0ImmPred:$u5)), (S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>;
+// Multiplies two v8i8 vectors.
+def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)),
+         (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))),
+                   (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>,
+     Requires<[HasV5T]>;
 
-let AddedComplexity = 100 in
-def: Pat<(add I64:$src1, (shl I64:$Rs, u6_0ImmPred:$u5)), (S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-def: Pat<(sub I64:$src1, (shl I64:$Rs, u6_0ImmPred:$u5)), (S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-def: Pat<(and I64:$src1, (shl I64:$Rs, u6_0ImmPred:$u5)), (S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-def: Pat<(or I64:$src1, (shl I64:$Rs, u6_0ImmPred:$u5)), (S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
-let AddedComplexity = 100 in
-def: Pat<(xor I64:$src1, (shl I64:$Rs, u6_0ImmPred:$u5)), (S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>;
 
-let AddedComplexity = 100 in
-def: Pat<(add I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_asl_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(sub I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_asl_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(and I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_asl_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(or I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_asl_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-let AddedComplexity = 100 in
-def: Pat<(add I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(sub I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(and I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(or I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(xor I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
+// --(10) Bit ------------------------------------------------------------
+//
 
-let AddedComplexity = 100 in
-def: Pat<(add I32:$src1, (sra I32:$Rs, I32:$Rt)), (S2_asr_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(sub I32:$src1, (sra I32:$Rs, I32:$Rt)), (S2_asr_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(and I32:$src1, (sra I32:$Rs, I32:$Rt)), (S2_asr_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(or I32:$src1, (sra I32:$Rs, I32:$Rt)), (S2_asr_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-let AddedComplexity = 100 in
-def: Pat<(add I64:$src1, (sra I64:$Rs, I32:$Rt)), (S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(sub I64:$src1, (sra I64:$Rs, I32:$Rt)), (S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(and I64:$src1, (sra I64:$Rs, I32:$Rt)), (S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(or I64:$src1, (sra I64:$Rs, I32:$Rt)), (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(xor I64:$src1, (sra I64:$Rs, I32:$Rt)), (S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
+// Count leading zeros.
+def: Pat<(ctlz I32:$Rs),                      (S2_cl0 I32:$Rs)>;
+def: Pat<(i32 (trunc (ctlz I64:$Rss))),       (S2_cl0p I64:$Rss)>;
 
-let AddedComplexity = 100 in
-def: Pat<(add I32:$src1, (srl I32:$Rs, I32:$Rt)), (S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(sub I32:$src1, (srl I32:$Rs, I32:$Rt)), (S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(and I32:$src1, (srl I32:$Rs, I32:$Rt)), (S2_lsr_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(or I32:$src1, (srl I32:$Rs, I32:$Rt)), (S2_lsr_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-let AddedComplexity = 100 in
-def: Pat<(add I64:$src1, (srl I64:$Rs, I32:$Rt)), (S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(sub I64:$src1, (srl I64:$Rs, I32:$Rt)), (S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(and I64:$src1, (srl I64:$Rs, I32:$Rt)), (S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(or I64:$src1, (srl I64:$Rs, I32:$Rt)), (S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(xor I64:$src1, (srl I64:$Rs, I32:$Rt)), (S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
+// Count trailing zeros.
+def: Pat<(cttz I32:$Rs),                      (S2_ct0 I32:$Rs)>;
+def: Pat<(i32 (trunc (cttz I64:$Rss))),       (S2_ct0p I64:$Rss)>;
 
+// Count leading ones.
+def: Pat<(ctlz (not I32:$Rs)),                (S2_cl1 I32:$Rs)>;
+def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
+
+// Count trailing ones.
+def: Pat<(cttz (not I32:$Rs)),                (S2_ct1 I32:$Rs)>;
+def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>;
+
+// Define leading/trailing patterns that require zero-extensions to 64 bits.
+def: Pat<(i64 (ctlz I64:$Rss)),               (ToZext64 (S2_cl0p I64:$Rss))>;
+def: Pat<(i64 (cttz I64:$Rss)),               (ToZext64 (S2_ct0p I64:$Rss))>;
+def: Pat<(i64 (ctlz (not I64:$Rss))),         (ToZext64 (S2_cl1p I64:$Rss))>;
+def: Pat<(i64 (cttz (not I64:$Rss))),         (ToZext64 (S2_ct1p I64:$Rss))>;
+
+def: Pat<(i64 (ctpop I64:$Rss)),  (ToZext64 (S5_popcountp I64:$Rss))>;
+def: Pat<(i32 (ctpop I32:$Rs)),   (S5_popcountp (A4_combineir 0, I32:$Rs))>;
+
+def: Pat<(bitreverse I32:$Rs),    (S2_brev I32:$Rs)>;
+def: Pat<(bitreverse I64:$Rss),   (S2_brevp I64:$Rss)>;
+
+
+let AddedComplexity = 20 in { // Complexity greater than and/or/xor
+  def: Pat<(and I32:$Rs, IsNPow2_32:$V),
+           (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>;
+  def: Pat<(or I32:$Rs, IsPow2_32:$V),
+           (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>;
+  def: Pat<(xor I32:$Rs, IsPow2_32:$V),
+           (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>;
+
+  def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))),
+           (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
+  def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)),
+           (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
+  def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)),
+           (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
+}
+
+// Clr/set/toggle bit for 64-bit values with immediate bit index.
+let AddedComplexity = 20 in { // Complexity greater than and/or/xor
+  def: Pat<(and I64:$Rss, IsNPow2_64L:$V),
+           (Combinew (i32 (HiReg $Rss)),
+                     (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>;
+  def: Pat<(and I64:$Rss, IsNPow2_64H:$V),
+           (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))),
+                     (i32 (LoReg $Rss)))>;
+
+  def: Pat<(or I64:$Rss, IsPow2_64L:$V),
+           (Combinew (i32 (HiReg $Rss)),
+                     (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>;
+  def: Pat<(or I64:$Rss, IsPow2_64H:$V),
+           (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
+                     (i32 (LoReg $Rss)))>;
+
+  def: Pat<(xor I64:$Rss, IsPow2_64L:$V),
+           (Combinew (i32 (HiReg $Rss)),
+                     (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>;
+  def: Pat<(xor I64:$Rss, IsPow2_64H:$V),
+           (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
+                     (i32 (LoReg $Rss)))>;
+}
+
+let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
+  def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)),
+           (S2_tstbit_i IntRegs:$Rs, imm:$u5)>;
+  def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)),
+           (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
+  def: Pat<(i1 (trunc I32:$Rs)),
+           (S2_tstbit_i IntRegs:$Rs, 0)>;
+  def: Pat<(i1 (trunc I64:$Rs)),
+           (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
+}
+
+let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
+  def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)),
+           (C2_bitsclri IntRegs:$Rs, imm:$u6)>;
+  def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)),
+           (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
+}
+
+let AddedComplexity = 10 in   // Complexity greater than compare reg-reg.
+def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)),
+         (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
+
+let AddedComplexity = 20 in {   // Complexity greater than cmp reg-imm.
+  def: Pat<(i1 (seteq (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)),
+           (S4_ntstbit_i I32:$Rs, imm:$u5)>;
+  def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)),
+           (S4_ntstbit_r I32:$Rs, I32:$Rt)>;
+}
+
+// Add extra complexity to prefer these instructions over bitsset/bitsclr.
+// The reason is that tstbit/ntstbit can be folded into a compound instruction:
+//   if ([!]tstbit(...)) jump ...
 let AddedComplexity = 100 in
-def: Pat<(add I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(sub I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(and I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_lsl_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(or I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_lsl_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>;
+def: Pat<(i1 (setne (and I32:$Rs, (i32 IsPow2_32:$u5)), (i32 0))),
+         (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>;
+
 let AddedComplexity = 100 in
-def: Pat<(add I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(sub I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(and I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(or I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(xor I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>;
+def: Pat<(i1 (seteq (and I32:$Rs, (i32 IsPow2_32:$u5)), (i32 0))),
+         (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>;
 
-def: Pat<(sra I64:$src1, I32:$src2), (S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2)>;
-def: Pat<(srl I64:$src1, I32:$src2), (S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2)>;
-def: Pat<(shl I64:$src1, I32:$src2), (S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2)>;
-def: Pat<(shl I64:$src1, I32:$src2), (S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2)>;
+// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
+// represented as a compare against "value & 0xFF", which is an exact match
+// for cmpb (same for cmph). The patterns below do not contain any additional
+// complexity that would make them preferable, and if they were actually used
+// instead of cmpb/cmph, they would result in a compare against register that
+// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
+def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)),
+         (C4_nbitsclri I32:$Rs, imm:$u6)>;
+def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
+         (C4_nbitsclr I32:$Rs, I32:$Rt)>;
+def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
+         (C4_nbitsset I32:$Rs, I32:$Rt)>;
 
-def: Pat<(sra I32:$src1, I32:$src2), (S2_asr_r_r IntRegs:$src1, IntRegs:$src2)>;
-def: Pat<(srl I32:$src1, I32:$src2), (S2_lsr_r_r IntRegs:$src1, IntRegs:$src2)>;
-def: Pat<(shl I32:$src1, I32:$src2), (S2_asl_r_r IntRegs:$src1, IntRegs:$src2)>;
-def: Pat<(shl I32:$src1, I32:$src2), (S2_lsl_r_r IntRegs:$src1, IntRegs:$src2)>;
+// Special patterns to address certain cases where the "top-down" matching
+// algorithm would cause suboptimal selection.
 
-def SDTHexagonINSERT:
-  SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
-                       SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
-def SDTHexagonINSERTRP:
-  SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
-                       SDTCisInt<0>, SDTCisVT<3, i64>]>;
+let AddedComplexity = 100 in {
+  // Avoid A4_rcmp[n]eqi in these cases:
+  def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))),
+           (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>;
+  def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))),
+           (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>;
+}
 
-def HexagonINSERT   : SDNode<"HexagonISD::INSERT",   SDTHexagonINSERT>;
-def HexagonINSERTRP : SDNode<"HexagonISD::INSERTRP", SDTHexagonINSERTRP>;
+// --(11) PIC ------------------------------------------------------------
+//
 
-def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2),
-         (S2_insert I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2)>;
-def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2),
-         (S2_insertp I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2)>;
-def: Pat<(HexagonINSERTRP I32:$Rs, I32:$Rt, I64:$Ru),
-         (S2_insert_rp I32:$Rs, I32:$Rt, I64:$Ru)>;
-def: Pat<(HexagonINSERTRP I64:$Rs, I64:$Rt, I64:$Ru),
-         (S2_insertp_rp I64:$Rs, I64:$Rt, I64:$Ru)>;
+def SDT_HexagonAtGot
+  : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>;
+def SDT_HexagonAtPcrel
+  : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
 
-let AddedComplexity = 100 in
-def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))),
-                                     (i32 (extloadi8  (add I32:$b, 3))),
-                                     24, 8),
-                      (i32 16)),
-                 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))),
-             (zextloadi8 I32:$b)),
-         (A2_swiz (L2_loadri_io I32:$b, 0))>;
+// AT_GOT address-of-GOT, address-of-global, offset-in-global
+def HexagonAtGot       : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>;
+// AT_PCREL address-of-global
+def HexagonAtPcrel     : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>;
+
+def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)),
+         (L2_loadri_io I32:$got, imm:$addr)>;
+def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off),
+         (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>;
+def: Pat<(HexagonAtPcrel I32:$addr),
+         (C4_addipc imm:$addr)>;
 
-def SDTHexagonEXTRACTU:
-  SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>,
-                       SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
-def SDTHexagonEXTRACTURP:
-  SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>,
-                       SDTCisVT<2, i64>]>;
+// The HVX load patterns also match AT_PCREL directly. Make sure that
+// if the selection of this opcode changes, it's updated in all places.
 
-def HexagonEXTRACTU   : SDNode<"HexagonISD::EXTRACTU",   SDTHexagonEXTRACTU>;
-def HexagonEXTRACTURP : SDNode<"HexagonISD::EXTRACTURP", SDTHexagonEXTRACTURP>;
 
-def: Pat<(HexagonEXTRACTU I32:$src1, u5_0ImmPred:$src2, u5_0ImmPred:$src3),
-         (S2_extractu I32:$src1, u5_0ImmPred:$src2, u5_0ImmPred:$src3)>;
-def: Pat<(HexagonEXTRACTU I64:$src1, u6_0ImmPred:$src2, u6_0ImmPred:$src3),
-         (S2_extractup I64:$src1, u6_0ImmPred:$src2, u6_0ImmPred:$src3)>;
-def: Pat<(HexagonEXTRACTURP I32:$src1, I64:$src2),
-         (S2_extractu_rp I32:$src1, I64:$src2)>;
-def: Pat<(HexagonEXTRACTURP I64:$src1, I64:$src2),
-         (S2_extractup_rp I64:$src1, I64:$src2)>;
+// --(12) Load -----------------------------------------------------------
+//
 
-def n8_0ImmPred: PatLeaf<(i32 imm), [{
-  int64_t V = N->getSExtValue();
-  return -255 <= V && V <= 0;
+def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{
+  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;
+}]>;
+def extloadv4i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{
+  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8;
 }]>;
 
-// Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
-def: Pat<(mul I32:$src1, (ineg n8_0ImmPred:$src2)),
-         (M2_mpysin IntRegs:$src1, u8_0ImmPred:$src2)>;
+def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
+  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;
+}]>;
+def zextloadv4i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
+  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8;
+}]>;
 
-multiclass MinMax_pats_p<PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
-  defm: T_MinMax_pats<Op, I64, Inst, SwapInst>;
+def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
+  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;
+}]>;
+def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
+  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8;
+}]>;
+
+// Patterns to select load-indexed: Rs + Off.
+// - frameindex [+ imm],
+multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
+                       InstHexagon MI> {
+  def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
+           (VT (MI AddrFI:$fi, imm:$Off))>;
+  def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))),
+           (VT (MI AddrFI:$fi, imm:$Off))>;
+  def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
 }
 
-def: Pat<(add Sext64:$Rs, I64:$Rt),
-         (A2_addsp (LoReg Sext64:$Rs), DoubleRegs:$Rt)>;
+// Patterns to select load-indexed: Rs + Off.
+// - base reg [+ imm]
+multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
+                       InstHexagon MI> {
+  def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))),
+           (VT (MI IntRegs:$Rs, imm:$Off))>;
+  def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))),
+           (VT (MI IntRegs:$Rs, imm:$Off))>;
+  def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>;
+}
 
-let AddedComplexity = 200 in {
-  defm: MinMax_pats_p<setge,  A2_maxp,  A2_minp>;
-  defm: MinMax_pats_p<setgt,  A2_maxp,  A2_minp>;
-  defm: MinMax_pats_p<setle,  A2_minp,  A2_maxp>;
-  defm: MinMax_pats_p<setlt,  A2_minp,  A2_maxp>;
-  defm: MinMax_pats_p<setuge, A2_maxup, A2_minup>;
-  defm: MinMax_pats_p<setugt, A2_maxup, A2_minup>;
-  defm: MinMax_pats_p<setule, A2_minup, A2_maxup>;
-  defm: MinMax_pats_p<setult, A2_minup, A2_maxup>;
+// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi.
+multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
+                      InstHexagon MI> {
+  defm: Loadxfi_pat<Load, VT, ImmPred, MI>;
+  defm: Loadxgi_pat<Load, VT, ImmPred, MI>;
 }
 
-def callv3 : SDNode<"HexagonISD::CALL", SDT_SPCall,
-           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
+// Patterns to select load reg indexed: Rs + Off with a value modifier.
+// - frameindex [+ imm]
+multiclass Loadxfim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
+                        PatLeaf ImmPred, InstHexagon MI> {
+  def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
+           (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
+  def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))),
+           (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
+  def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>;
+}
 
-def callv3nr : SDNode<"HexagonISD::CALLnr", SDT_SPCall,
-           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
+// Patterns to select load reg indexed: Rs + Off with a value modifier.
+// - base reg [+ imm]
+multiclass Loadxgim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
+                        PatLeaf ImmPred, InstHexagon MI> {
+  def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))),
+           (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
+  def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))),
+           (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
+  def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
+}
 
+// Patterns to select load reg indexed: Rs + Off with a value modifier.
+// Combines Loadxfim + Loadxgim.
+multiclass Loadxim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
+                       PatLeaf ImmPred, InstHexagon MI> {
+  defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>;
+  defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>;
+}
 
-// Map call instruction
-def : Pat<(callv3 I32:$dst),
-          (J2_callr I32:$dst)>;
-def : Pat<(callv3 tglobaladdr:$dst),
-          (J2_call tglobaladdr:$dst)>;
-def : Pat<(callv3 texternalsym:$dst),
-          (J2_call texternalsym:$dst)>;
-def : Pat<(callv3 tglobaltlsaddr:$dst),
-          (J2_call tglobaltlsaddr:$dst)>;
+// Pattern to select load reg reg-indexed: Rs + Rt<<u2.
+class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI>
+  : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))),
+        (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
 
-def : Pat<(callv3nr I32:$dst),
-          (PS_callr_nr I32:$dst)>;
-def : Pat<(callv3nr tglobaladdr:$dst),
-          (PS_call_nr tglobaladdr:$dst)>;
-def : Pat<(callv3nr texternalsym:$dst),
-          (PS_call_nr texternalsym:$dst)>;
+// Pattern to select load reg reg-indexed: Rs + Rt<<0.
+class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI>
+  : Pat<(VT (Load (add I32:$Rs, I32:$Rt))),
+        (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
 
+// Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier.
+class Loadxrm_shl_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
+                      InstHexagon MI>
+  : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))),
+        (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>;
 
-def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
-def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
+// Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier.
+class Loadxrm_add_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
+                      InstHexagon MI>
+  : Pat<(VT (Load (add I32:$Rs, I32:$Rt))),
+        (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>;
 
+// Pattern to select load long-offset reg-indexed: Addr + Rt<<u2.
+// Don't match for u2==0, instead use reg+imm for those cases.
+class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI>
+  : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))),
+        (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>;
 
-// Pats for instruction selection.
+class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod,
+                  InstHexagon MI>
+  : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))),
+        (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>;
 
-// A class to embed the usual comparison patfrags within a zext to i32.
-// The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
-// names, or else the frag's "body" won't match the operands.
-class CmpInReg<PatFrag Op>
-  : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
+// Pattern to select load absolute.
+class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
+  : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
 
-def: T_cmp32_rr_pat<A4_rcmpeq,  CmpInReg<seteq>, i32>;
-def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
+// Pattern to select load absolute with value modifier.
+class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod,
+                 InstHexagon MI>
+  : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
 
-def: T_cmp32_rr_pat<C4_cmpneq,  setne,  i1>;
-def: T_cmp32_rr_pat<C4_cmplte,  setle,  i1>;
-def: T_cmp32_rr_pat<C4_cmplteu, setule, i1>;
 
-def: T_cmp32_rr_pat<C4_cmplte,  RevCmp<setge>,  i1>;
-def: T_cmp32_rr_pat<C4_cmplteu, RevCmp<setuge>, i1>;
+let AddedComplexity = 20 in {
+  defm: Loadxi_pat<extloadi1,       i32,   anyimm0, L2_loadrub_io>;
+  defm: Loadxi_pat<extloadi8,       i32,   anyimm0, L2_loadrub_io>;
+  defm: Loadxi_pat<extloadi16,      i32,   anyimm1, L2_loadruh_io>;
+  defm: Loadxi_pat<extloadv2i8,     v2i16, anyimm1, L2_loadbzw2_io>;
+  defm: Loadxi_pat<extloadv4i8,     v4i16, anyimm2, L2_loadbzw4_io>;
+  defm: Loadxi_pat<sextloadi8,      i32,   anyimm0, L2_loadrb_io>;
+  defm: Loadxi_pat<sextloadi16,     i32,   anyimm1, L2_loadrh_io>;
+  defm: Loadxi_pat<sextloadv2i8,    v2i16, anyimm1, L2_loadbsw2_io>;
+  defm: Loadxi_pat<sextloadv4i8,    v4i16, anyimm2, L2_loadbzw4_io>;
+  defm: Loadxi_pat<zextloadi1,      i32,   anyimm0, L2_loadrub_io>;
+  defm: Loadxi_pat<zextloadi8,      i32,   anyimm0, L2_loadrub_io>;
+  defm: Loadxi_pat<zextloadi16,     i32,   anyimm1, L2_loadruh_io>;
+  defm: Loadxi_pat<zextloadv2i8,    v2i16, anyimm1, L2_loadbzw2_io>;
+  defm: Loadxi_pat<zextloadv4i8,    v4i16, anyimm2, L2_loadbzw4_io>;
+  defm: Loadxi_pat<load,            i32,   anyimm2, L2_loadri_io>;
+  defm: Loadxi_pat<load,            i64,   anyimm3, L2_loadrd_io>;
+  defm: Loadxi_pat<load,            f32,   anyimm2, L2_loadri_io>;
+  defm: Loadxi_pat<load,            f64,   anyimm3, L2_loadrd_io>;
+  // No sextloadi1.
 
-let AddedComplexity = 100 in {
-  def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt),
-                       255), 0)),
-           (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
-  def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt),
-                       255), 0)),
-           (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
-  def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt),
-                           65535), 0)),
-           (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
-  def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt),
-                           65535), 0)),
-           (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
+  defm: Loadxi_pat<atomic_load_8 ,  i32, anyimm0, L2_loadrub_io>;
+  defm: Loadxi_pat<atomic_load_16,  i32, anyimm1, L2_loadruh_io>;
+  defm: Loadxi_pat<atomic_load_32,  i32, anyimm2, L2_loadri_io>;
+  defm: Loadxi_pat<atomic_load_64,  i64, anyimm3, L2_loadrd_io>;
 }
 
-def: Pat<(i32 (zext (i1 (seteq I32:$Rs, s32_0ImmPred:$s8)))),
-         (A4_rcmpeqi IntRegs:$Rs, s32_0ImmPred:$s8)>;
-def: Pat<(i32 (zext (i1 (setne I32:$Rs, s32_0ImmPred:$s8)))),
-         (A4_rcmpneqi IntRegs:$Rs, s32_0ImmPred:$s8)>;
+let AddedComplexity = 30 in {
+  defm: Loadxim_pat<extloadi1,    i64, ToZext64, anyimm0, L2_loadrub_io>;
+  defm: Loadxim_pat<extloadi8,    i64, ToZext64, anyimm0, L2_loadrub_io>;
+  defm: Loadxim_pat<extloadi16,   i64, ToZext64, anyimm1, L2_loadruh_io>;
+  defm: Loadxim_pat<extloadi32,   i64, ToZext64, anyimm2, L2_loadri_io>;
+  defm: Loadxim_pat<zextloadi1,   i64, ToZext64, anyimm0, L2_loadrub_io>;
+  defm: Loadxim_pat<zextloadi8,   i64, ToZext64, anyimm0, L2_loadrub_io>;
+  defm: Loadxim_pat<zextloadi16,  i64, ToZext64, anyimm1, L2_loadruh_io>;
+  defm: Loadxim_pat<zextloadi32,  i64, ToZext64, anyimm2, L2_loadri_io>;
+  defm: Loadxim_pat<sextloadi8,   i64, ToSext64, anyimm0, L2_loadrb_io>;
+  defm: Loadxim_pat<sextloadi16,  i64, ToSext64, anyimm1, L2_loadrh_io>;
+  defm: Loadxim_pat<sextloadi32,  i64, ToSext64, anyimm2, L2_loadri_io>;
+}
 
-// Preserve the S2_tstbit_r generation
-def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, I32:$src2)),
-                                         I32:$src1)), 0)))),
-         (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
+let AddedComplexity  = 60 in {
+  def: Loadxu_pat<extloadi8,    i32,   anyimm0, L4_loadrub_ur>;
+  def: Loadxu_pat<extloadi16,   i32,   anyimm1, L4_loadruh_ur>;
+  def: Loadxu_pat<extloadv2i8,  v2i16, anyimm1, L4_loadbzw2_ur>;
+  def: Loadxu_pat<extloadv4i8,  v4i16, anyimm2, L4_loadbzw4_ur>;
+  def: Loadxu_pat<sextloadi8,   i32,   anyimm0, L4_loadrb_ur>;
+  def: Loadxu_pat<sextloadi16,  i32,   anyimm1, L4_loadrh_ur>;
+  def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>;
+  def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>;
+  def: Loadxu_pat<zextloadi8,   i32,   anyimm0, L4_loadrub_ur>;
+  def: Loadxu_pat<zextloadi16,  i32,   anyimm1, L4_loadruh_ur>;
+  def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>;
+  def: Loadxu_pat<zextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>;
+  def: Loadxu_pat<load,         f32,   anyimm2, L4_loadri_ur>;
+  def: Loadxu_pat<load,         f64,   anyimm3, L4_loadrd_ur>;
+  def: Loadxu_pat<load,         i32,   anyimm2, L4_loadri_ur>;
+  def: Loadxu_pat<load,         i64,   anyimm3, L4_loadrd_ur>;
 
-// The complexity of the combines involving immediates should be greater
-// than the complexity of the combine with two registers.
-let AddedComplexity = 50 in {
-def: Pat<(HexagonCOMBINE IntRegs:$r, s32_0ImmPred:$i),
-         (A4_combineri IntRegs:$r, s32_0ImmPred:$i)>;
+  def: Loadxum_pat<sextloadi8,  i64, anyimm0, ToSext64, L4_loadrb_ur>;
+  def: Loadxum_pat<zextloadi8,  i64, anyimm0, ToZext64, L4_loadrub_ur>;
+  def: Loadxum_pat<extloadi8,   i64, anyimm0, ToZext64, L4_loadrub_ur>;
+  def: Loadxum_pat<sextloadi16, i64, anyimm1, ToSext64, L4_loadrh_ur>;
+  def: Loadxum_pat<zextloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>;
+  def: Loadxum_pat<extloadi16,  i64, anyimm1, ToZext64, L4_loadruh_ur>;
+  def: Loadxum_pat<sextloadi32, i64, anyimm2, ToSext64, L4_loadri_ur>;
+  def: Loadxum_pat<zextloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>;
+  def: Loadxum_pat<extloadi32,  i64, anyimm2, ToZext64, L4_loadri_ur>;
+}
 
-def: Pat<(HexagonCOMBINE s32_0ImmPred:$i, IntRegs:$r),
-         (A4_combineir s32_0ImmPred:$i, IntRegs:$r)>;
+let AddedComplexity = 40 in {
+  def: Loadxr_shl_pat<extloadi8,     i32, L4_loadrub_rr>;
+  def: Loadxr_shl_pat<zextloadi8,    i32, L4_loadrub_rr>;
+  def: Loadxr_shl_pat<sextloadi8,    i32, L4_loadrb_rr>;
+  def: Loadxr_shl_pat<extloadi16,    i32, L4_loadruh_rr>;
+  def: Loadxr_shl_pat<zextloadi16,   i32, L4_loadruh_rr>;
+  def: Loadxr_shl_pat<sextloadi16,   i32, L4_loadrh_rr>;
+  def: Loadxr_shl_pat<load,          i32, L4_loadri_rr>;
+  def: Loadxr_shl_pat<load,          i64, L4_loadrd_rr>;
+  def: Loadxr_shl_pat<load,          f32, L4_loadri_rr>;
+  def: Loadxr_shl_pat<load,          f64, L4_loadrd_rr>;
 }
 
-// The complexity of the combine with two immediates should be greater than
-// the complexity of a combine involving a register.
-let AddedComplexity = 75 in {
-def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, u32_0ImmPred:$u6),
-         (A4_combineii imm:$s8, imm:$u6)>;
-def: Pat<(HexagonCOMBINE s32_0ImmPred:$s8, s8_0ImmPred:$S8),
-         (A2_combineii imm:$s8, imm:$S8)>;
+let AddedComplexity = 20 in {
+  def: Loadxr_add_pat<extloadi8,     i32, L4_loadrub_rr>;
+  def: Loadxr_add_pat<zextloadi8,    i32, L4_loadrub_rr>;
+  def: Loadxr_add_pat<sextloadi8,    i32, L4_loadrb_rr>;
+  def: Loadxr_add_pat<extloadi16,    i32, L4_loadruh_rr>;
+  def: Loadxr_add_pat<zextloadi16,   i32, L4_loadruh_rr>;
+  def: Loadxr_add_pat<sextloadi16,   i32, L4_loadrh_rr>;
+  def: Loadxr_add_pat<load,          i32, L4_loadri_rr>;
+  def: Loadxr_add_pat<load,          i64, L4_loadrd_rr>;
+  def: Loadxr_add_pat<load,          f32, L4_loadri_rr>;
+  def: Loadxr_add_pat<load,          f64, L4_loadrd_rr>;
 }
 
+let AddedComplexity = 40 in {
+  def: Loadxrm_shl_pat<extloadi8,    i64, ToZext64, L4_loadrub_rr>;
+  def: Loadxrm_shl_pat<zextloadi8,   i64, ToZext64, L4_loadrub_rr>;
+  def: Loadxrm_shl_pat<sextloadi8,   i64, ToSext64, L4_loadrb_rr>;
+  def: Loadxrm_shl_pat<extloadi16,   i64, ToZext64, L4_loadruh_rr>;
+  def: Loadxrm_shl_pat<zextloadi16,  i64, ToZext64, L4_loadruh_rr>;
+  def: Loadxrm_shl_pat<sextloadi16,  i64, ToSext64, L4_loadrh_rr>;
+  def: Loadxrm_shl_pat<extloadi32,   i64, ToZext64, L4_loadri_rr>;
+  def: Loadxrm_shl_pat<zextloadi32,  i64, ToZext64, L4_loadri_rr>;
+  def: Loadxrm_shl_pat<sextloadi32,  i64, ToSext64, L4_loadri_rr>;
+}
 
-// Patterns to generate indexed loads with different forms of the address:
-// - frameindex,
-// - base + offset,
-// - base (without offset).
-multiclass Loadxm_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
-                      PatLeaf ImmPred, InstHexagon MI> {
-  def: Pat<(VT (Load AddrFI:$fi)),
-           (VT (ValueMod (MI AddrFI:$fi, 0)))>;
-  def: Pat<(VT (Load (add AddrFI:$fi, ImmPred:$Off))),
-           (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
-  def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
-           (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
-  def: Pat<(VT (Load I32:$Rs)),
-           (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
+let AddedComplexity = 20 in {
+  def: Loadxrm_add_pat<extloadi8,    i64, ToZext64, L4_loadrub_rr>;
+  def: Loadxrm_add_pat<zextloadi8,   i64, ToZext64, L4_loadrub_rr>;
+  def: Loadxrm_add_pat<sextloadi8,   i64, ToSext64, L4_loadrb_rr>;
+  def: Loadxrm_add_pat<extloadi16,   i64, ToZext64, L4_loadruh_rr>;
+  def: Loadxrm_add_pat<zextloadi16,  i64, ToZext64, L4_loadruh_rr>;
+  def: Loadxrm_add_pat<sextloadi16,  i64, ToSext64, L4_loadrh_rr>;
+  def: Loadxrm_add_pat<extloadi32,   i64, ToZext64, L4_loadri_rr>;
+  def: Loadxrm_add_pat<zextloadi32,  i64, ToZext64, L4_loadri_rr>;
+  def: Loadxrm_add_pat<sextloadi32,  i64, ToSext64, L4_loadri_rr>;
 }
 
-defm: Loadxm_pat<extloadi1,   i64, ToZext64, s32_0ImmPred, L2_loadrub_io>;
-defm: Loadxm_pat<extloadi8,   i64, ToZext64, s32_0ImmPred, L2_loadrub_io>;
-defm: Loadxm_pat<extloadi16,  i64, ToZext64, s31_1ImmPred, L2_loadruh_io>;
-defm: Loadxm_pat<zextloadi1,  i64, ToZext64, s32_0ImmPred, L2_loadrub_io>;
-defm: Loadxm_pat<zextloadi8,  i64, ToZext64, s32_0ImmPred, L2_loadrub_io>;
-defm: Loadxm_pat<zextloadi16, i64, ToZext64, s31_1ImmPred, L2_loadruh_io>;
-defm: Loadxm_pat<sextloadi8,  i64, ToSext64, s32_0ImmPred, L2_loadrb_io>;
-defm: Loadxm_pat<sextloadi16, i64, ToSext64, s31_1ImmPred, L2_loadrh_io>;
+// Absolute address
 
-// Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs).
-def: Pat<(Aext64 I32:$src1), (ToZext64 IntRegs:$src1)>;
+let AddedComplexity  = 60 in {
+  def: Loada_pat<zextloadi1,      i32, anyimm0, PS_loadrubabs>;
+  def: Loada_pat<sextloadi8,      i32, anyimm0, PS_loadrbabs>;
+  def: Loada_pat<extloadi8,       i32, anyimm0, PS_loadrubabs>;
+  def: Loada_pat<zextloadi8,      i32, anyimm0, PS_loadrubabs>;
+  def: Loada_pat<sextloadi16,     i32, anyimm1, PS_loadrhabs>;
+  def: Loada_pat<extloadi16,      i32, anyimm1, PS_loadruhabs>;
+  def: Loada_pat<zextloadi16,     i32, anyimm1, PS_loadruhabs>;
+  def: Loada_pat<load,            i32, anyimm2, PS_loadriabs>;
+  def: Loada_pat<load,            i64, anyimm3, PS_loadrdabs>;
+  def: Loada_pat<load,            f32, anyimm2, PS_loadriabs>;
+  def: Loada_pat<load,            f64, anyimm3, PS_loadrdabs>;
 
-multiclass T_LoadAbsReg_Pat <PatFrag ldOp, InstHexagon MI, ValueType VT = i32> {
-  def  : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2_0ImmPred:$src2),
-                             (HexagonCONST32 tglobaladdr:$src3)))),
-              (MI IntRegs:$src1, u2_0ImmPred:$src2, tglobaladdr:$src3)>;
-  def  : Pat <(VT (ldOp (add IntRegs:$src1,
-                             (HexagonCONST32 tglobaladdr:$src2)))),
-              (MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
+  def: Loada_pat<atomic_load_8,   i32, anyimm0, PS_loadrubabs>;
+  def: Loada_pat<atomic_load_16,  i32, anyimm1, PS_loadruhabs>;
+  def: Loada_pat<atomic_load_32,  i32, anyimm2, PS_loadriabs>;
+  def: Loada_pat<atomic_load_64,  i64, anyimm3, PS_loadrdabs>;
+}
 
-  def  : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2_0ImmPred:$src2),
-                             (HexagonCONST32 tconstpool:$src3)))),
-              (MI IntRegs:$src1, u2_0ImmPred:$src2, tconstpool:$src3)>;
-  def  : Pat <(VT (ldOp (add IntRegs:$src1,
-                             (HexagonCONST32 tconstpool:$src2)))),
-              (MI IntRegs:$src1, 0, tconstpool:$src2)>;
+let AddedComplexity  = 30 in {
+  def: Loadam_pat<extloadi8,      i64, anyimm0, ToZext64, PS_loadrubabs>;
+  def: Loadam_pat<sextloadi8,     i64, anyimm0, ToSext64, PS_loadrbabs>;
+  def: Loadam_pat<zextloadi8,     i64, anyimm0, ToZext64, PS_loadrubabs>;
+  def: Loadam_pat<extloadi16,     i64, anyimm1, ToZext64, PS_loadruhabs>;
+  def: Loadam_pat<sextloadi16,    i64, anyimm1, ToSext64, PS_loadrhabs>;
+  def: Loadam_pat<zextloadi16,    i64, anyimm1, ToZext64, PS_loadruhabs>;
+  def: Loadam_pat<extloadi32,     i64, anyimm2, ToZext64, PS_loadriabs>;
+  def: Loadam_pat<sextloadi32,    i64, anyimm2, ToSext64, PS_loadriabs>;
+  def: Loadam_pat<zextloadi32,    i64, anyimm2, ToZext64, PS_loadriabs>;
 
-  def  : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2_0ImmPred:$src2),
-                             (HexagonCONST32 tjumptable:$src3)))),
-              (MI IntRegs:$src1, u2_0ImmPred:$src2, tjumptable:$src3)>;
-  def  : Pat <(VT (ldOp (add IntRegs:$src1,
-                             (HexagonCONST32 tjumptable:$src2)))),
-              (MI IntRegs:$src1, 0, tjumptable:$src2)>;
+  def: Loadam_pat<load,           i1,  anyimm0, I32toI1,  PS_loadrubabs>;
+  def: Loadam_pat<zextloadi1,     i64, anyimm0, ToZext64, PS_loadrubabs>;
 }
 
-let AddedComplexity  = 60 in {
-defm : T_LoadAbsReg_Pat <sextloadi8, L4_loadrb_ur>;
-defm : T_LoadAbsReg_Pat <zextloadi8, L4_loadrub_ur>;
-defm : T_LoadAbsReg_Pat <extloadi8,  L4_loadrub_ur>;
+// GP-relative address
 
-defm : T_LoadAbsReg_Pat <sextloadi16, L4_loadrh_ur>;
-defm : T_LoadAbsReg_Pat <zextloadi16, L4_loadruh_ur>;
-defm : T_LoadAbsReg_Pat <extloadi16,  L4_loadruh_ur>;
+let AddedComplexity  = 100 in {
+  def: Loada_pat<extloadi1,       i32, addrgp,  L2_loadrubgp>;
+  def: Loada_pat<zextloadi1,      i32, addrgp,  L2_loadrubgp>;
+  def: Loada_pat<extloadi8,       i32, addrgp,  L2_loadrubgp>;
+  def: Loada_pat<sextloadi8,      i32, addrgp,  L2_loadrbgp>;
+  def: Loada_pat<zextloadi8,      i32, addrgp,  L2_loadrubgp>;
+  def: Loada_pat<extloadi16,      i32, addrgp,  L2_loadruhgp>;
+  def: Loada_pat<sextloadi16,     i32, addrgp,  L2_loadrhgp>;
+  def: Loada_pat<zextloadi16,     i32, addrgp,  L2_loadruhgp>;
+  def: Loada_pat<load,            i32, addrgp,  L2_loadrigp>;
+  def: Loada_pat<load,            i64, addrgp,  L2_loadrdgp>;
+  def: Loada_pat<load,            f32, addrgp,  L2_loadrigp>;
+  def: Loada_pat<load,            f64, addrgp,  L2_loadrdgp>;
 
-defm : T_LoadAbsReg_Pat <load, L4_loadri_ur>;
-defm : T_LoadAbsReg_Pat <load, L4_loadrd_ur, i64>;
+  def: Loada_pat<atomic_load_8,   i32, addrgp,  L2_loadrubgp>;
+  def: Loada_pat<atomic_load_16,  i32, addrgp,  L2_loadruhgp>;
+  def: Loada_pat<atomic_load_32,  i32, addrgp,  L2_loadrigp>;
+  def: Loada_pat<atomic_load_64,  i64, addrgp,  L2_loadrdgp>;
 }
 
-// 'def pats' for load instructions with base + register offset and non-zero
-// immediate value. Immediate value is used to left-shift the second
-// register operand.
-class Loadxs_pat<PatFrag Load, ValueType VT, InstHexagon MI>
-  : Pat<(VT (Load (add I32:$Rs,
-                       (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))),
-        (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
+let AddedComplexity  = 70 in {
+  def: Loadam_pat<extloadi8,      i64, addrgp,  ToZext64, L2_loadrubgp>;
+  def: Loadam_pat<sextloadi8,     i64, addrgp,  ToSext64, L2_loadrbgp>;
+  def: Loadam_pat<zextloadi8,     i64, addrgp,  ToZext64, L2_loadrubgp>;
+  def: Loadam_pat<extloadi16,     i64, addrgp,  ToZext64, L2_loadruhgp>;
+  def: Loadam_pat<sextloadi16,    i64, addrgp,  ToSext64, L2_loadrhgp>;
+  def: Loadam_pat<zextloadi16,    i64, addrgp,  ToZext64, L2_loadruhgp>;
+  def: Loadam_pat<extloadi32,     i64, addrgp,  ToZext64, L2_loadrigp>;
+  def: Loadam_pat<sextloadi32,    i64, addrgp,  ToSext64, L2_loadrigp>;
+  def: Loadam_pat<zextloadi32,    i64, addrgp,  ToZext64, L2_loadrigp>;
 
-let AddedComplexity = 40 in {
-  def: Loadxs_pat<extloadi8,   i32, L4_loadrub_rr>;
-  def: Loadxs_pat<zextloadi8,  i32, L4_loadrub_rr>;
-  def: Loadxs_pat<sextloadi8,  i32, L4_loadrb_rr>;
-  def: Loadxs_pat<extloadi16,  i32, L4_loadruh_rr>;
-  def: Loadxs_pat<zextloadi16, i32, L4_loadruh_rr>;
-  def: Loadxs_pat<sextloadi16, i32, L4_loadrh_rr>;
-  def: Loadxs_pat<load,        i32, L4_loadri_rr>;
-  def: Loadxs_pat<load,        i64, L4_loadrd_rr>;
+  def: Loadam_pat<load,           i1,  addrgp,  I32toI1,  L2_loadrubgp>;
+  def: Loadam_pat<zextloadi1,     i64, addrgp,  ToZext64, L2_loadrubgp>;
 }
 
-// 'def pats' for load instruction base + register offset and
-// zero immediate value.
-class Loadxs_simple_pat<PatFrag Load, ValueType VT, InstHexagon MI>
-  : Pat<(VT (Load (add I32:$Rs, I32:$Rt))),
-        (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
 
-let AddedComplexity = 20 in {
-  def: Loadxs_simple_pat<extloadi8,   i32, L4_loadrub_rr>;
-  def: Loadxs_simple_pat<zextloadi8,  i32, L4_loadrub_rr>;
-  def: Loadxs_simple_pat<sextloadi8,  i32, L4_loadrb_rr>;
-  def: Loadxs_simple_pat<extloadi16,  i32, L4_loadruh_rr>;
-  def: Loadxs_simple_pat<zextloadi16, i32, L4_loadruh_rr>;
-  def: Loadxs_simple_pat<sextloadi16, i32, L4_loadrh_rr>;
-  def: Loadxs_simple_pat<load,        i32, L4_loadri_rr>;
-  def: Loadxs_simple_pat<load,        i64, L4_loadrd_rr>;
+// Sign-extending loads of i1 need to replicate the lowest bit throughout
+// the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
+// do the trick.
+let AddedComplexity = 20 in
+def: Pat<(i32 (sextloadi1 I32:$Rs)),
+         (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
+
+// Patterns for loads of i1:
+def: Pat<(i1 (load AddrFI:$fi)),
+         (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
+def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))),
+         (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
+def: Pat<(i1 (load I32:$Rs)),
+         (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
+
+// HVX loads
+
+multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType VT,
+                     PatFrag ImmPred> {
+  def: Pat<(VT (Load I32:$Rt)),                   (MI I32:$Rt, 0)>;
+  def: Pat<(VT (Load (add I32:$Rt, ImmPred:$s))), (MI I32:$Rt, imm:$s)>;
+  // The HVX selection code for shuffles can generate vector constants.
+  // Calling "Select" on the resulting loads from CP fails without these
+  // patterns.
+  def: Pat<(VT (Load (HexagonCP tconstpool:$A))), (MI (A2_tfrsi imm:$A), 0)>;
+  def: Pat<(VT (Load (HexagonAtPcrel tconstpool:$A))),
+           (MI (C4_addipc imm:$A), 0)>;
 }
 
-let AddedComplexity = 40 in
-multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT,
-                           PatFrag stOp> {
- def : Pat<(stOp (VT RC:$src4),
-                 (add (shl I32:$src1, u2_0ImmPred:$src2),
-                      u32_0ImmPred:$src3)),
-          (MI IntRegs:$src1, u2_0ImmPred:$src2, u32_0ImmPred:$src3, RC:$src4)>;
 
- def : Pat<(stOp (VT RC:$src4),
-                 (add (shl IntRegs:$src1, u2_0ImmPred:$src2),
-                      (HexagonCONST32 tglobaladdr:$src3))),
-           (MI IntRegs:$src1, u2_0ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
+let Predicates = [UseHVX] in {
+  multiclass HvxLdVs_pat<InstHexagon MI, PatFrag Load> {
+    defm: HvxLd_pat<MI, Load, VecI8,  IsVecOff>;
+    defm: HvxLd_pat<MI, Load, VecI16, IsVecOff>;
+    defm: HvxLd_pat<MI, Load, VecI32, IsVecOff>;
+  }
+  defm: HvxLdVs_pat<V6_vL32b_nt_ai, alignednontemporalload>;
+  defm: HvxLdVs_pat<V6_vL32b_ai,    alignedload>;
+  defm: HvxLdVs_pat<V6_vL32Ub_ai,   unalignedload>;
 
- def : Pat<(stOp (VT RC:$src4),
-                 (add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
-           (MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
+  multiclass HvxLdWs_pat<InstHexagon MI, PatFrag Load> {
+    defm: HvxLd_pat<MI, Load, VecPI8,  IsVecOff>;
+    defm: HvxLd_pat<MI, Load, VecPI16, IsVecOff>;
+    defm: HvxLd_pat<MI, Load, VecPI32, IsVecOff>;
+  }
+  defm: HvxLdWs_pat<PS_vloadrw_nt_ai, alignednontemporalload>;
+  defm: HvxLdWs_pat<PS_vloadrw_ai,    alignedload>;
+  defm: HvxLdWs_pat<PS_vloadrwu_ai,   unalignedload>;
 }
 
-defm : T_StoreAbsReg_Pats <S4_storerd_ur, DoubleRegs, i64, store>;
-defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, i32, store>;
-defm : T_StoreAbsReg_Pats <S4_storerb_ur, IntRegs, i32, truncstorei8>;
-defm : T_StoreAbsReg_Pats <S4_storerh_ur, IntRegs, i32, truncstorei16>;
 
-class Storexs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
-  : Pat<(Store Value:$Ru, (add I32:$Rs,
-                               (i32 (shl I32:$Rt, u2_0ImmPred:$u2)))),
-        (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
+// --(13) Store ----------------------------------------------------------
+//
 
-let AddedComplexity = 40 in {
-  def: Storexs_pat<truncstorei8,  I32, S4_storerb_rr>;
-  def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
-  def: Storexs_pat<store,         I32, S4_storeri_rr>;
-  def: Storexs_pat<store,         I64, S4_storerd_rr>;
+
+class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI>
+  : Pat<(Store Value:$Rt, I32:$Rx, Offset:$s4),
+        (MI I32:$Rx, imm:$s4, Value:$Rt)>;
+
+def: Storepi_pat<post_truncsti8,  I32, s4_0ImmPred, S2_storerb_pi>;
+def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>;
+def: Storepi_pat<post_store,      I32, s4_2ImmPred, S2_storeri_pi>;
+def: Storepi_pat<post_store,      I64, s4_3ImmPred, S2_storerd_pi>;
+
+// Patterns for generating stores, where the address takes different forms:
+// - frameindex,
+// - frameindex + offset,
+// - base + offset,
+// - simple (base address without offset).
+// These would usually be used together (via Storexi_pat defined below), but
+// in some cases one may want to apply different properties (such as
+// AddedComplexity) to the individual patterns.
+class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
+  : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
+
+multiclass Storexi_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
+                              InstHexagon MI> {
+  def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
+           (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
+  def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)),
+           (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
 }
 
-def s30_2ProperPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v);
-}]>;
-def RoundTo8 : SDNodeXForm<imm, [{
-  int32_t Imm = N->getSExtValue();
-  return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32);
-}]>;
+multiclass Storexi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
+                           InstHexagon MI> {
+  def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)),
+           (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
+  def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)),
+           (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
+}
 
-let AddedComplexity = 40 in
-def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)),
-         (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>;
+class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
+  : Pat<(Store Value:$Rt, I32:$Rs),
+        (MI IntRegs:$Rs, 0, Value:$Rt)>;
 
-class Store_rr_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
+// Patterns for generating stores, where the address takes different forms,
+// and where the value being stored is transformed through the value modifier
+// ValueMod.  The address forms are same as above.
+class Storexim_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
+                      InstHexagon MI>
+  : Pat<(Store Value:$Rs, AddrFI:$fi),
+        (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>;
+
+multiclass Storexim_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
+                               PatFrag ValueMod, InstHexagon MI> {
+  def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
+           (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
+  def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)),
+           (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
+}
+
+multiclass Storexim_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
+                            PatFrag ValueMod, InstHexagon MI> {
+  def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)),
+           (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
+  def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)),
+           (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
+}
+
+class Storexim_base_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
+                        InstHexagon MI>
+  : Pat<(Store Value:$Rt, I32:$Rs),
+        (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
+
+multiclass Storexi_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
+                       InstHexagon MI> {
+  defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>;
+  def:  Storexi_fi_pat     <Store, Value,          MI>;
+  defm: Storexi_add_pat    <Store, Value, ImmPred, MI>;
+}
+
+multiclass Storexim_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
+                        PatFrag ValueMod, InstHexagon MI> {
+  defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>;
+  def:  Storexim_fi_pat     <Store, Value,          ValueMod, MI>;
+  defm: Storexim_add_pat    <Store, Value, ImmPred, ValueMod, MI>;
+}
+
+// Reg<<S + Imm
+class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI>
+  : Pat<(Store Value:$Rt, (add (shl I32:$Ru, u2_0ImmPred:$u2), ImmPred:$A)),
+        (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>;
+
+// Reg<<S + Reg
+class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
+  : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))),
+        (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
+
+// Reg + Reg
+class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
   : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)),
         (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>;
 
-let AddedComplexity = 20 in {
-  def: Store_rr_pat<truncstorei8,  I32, S4_storerb_rr>;
-  def: Store_rr_pat<truncstorei16, I32, S4_storerh_rr>;
-  def: Store_rr_pat<store,         I32, S4_storeri_rr>;
-  def: Store_rr_pat<store,         I64, S4_storerd_rr>;
+class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
+  : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
+
+class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod,
+                  InstHexagon MI>
+  : Pat<(Store Value:$val, Addr:$addr),
+        (MI Addr:$addr, (ValueMod Value:$val))>;
+
+// Regular stores in the DAG have two operands: value and address.
+// Atomic stores also have two, but they are reversed: address, value.
+// To use atomic stores with the patterns, they need to have their operands
+// swapped. This relies on the knowledge that the F.Fragment uses names
+// "ptr" and "val".
+class AtomSt<PatFrag F>
+  : PatFrag<(ops node:$val, node:$ptr), F.Fragment, F.PredicateCode,
+            F.OperandTransform> {
+  let IsAtomic = F.IsAtomic;
+  let MemoryVT = F.MemoryVT;
 }
 
 
 def IMM_BYTE : SDNodeXForm<imm, [{
-  // -1 etc is  represented as 255 etc
+  // -1 can be represented as 255, etc.
   // assigning to a byte restores our desired signed value.
   int8_t imm = N->getSExtValue();
   return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
 }]>;
 
 def IMM_HALF : SDNodeXForm<imm, [{
-  // -1 etc is  represented as 65535 etc
+  // -1 can be represented as 65535, etc.
   // assigning to a short restores our desired signed value.
   int16_t imm = N->getSExtValue();
   return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
 }]>;
 
 def IMM_WORD : SDNodeXForm<imm, [{
-  // -1 etc can be represented as 4294967295 etc
+  // -1 can be represented as 4294967295, etc.
   // Currently, it's not doing this. But some optimization
   // might convert -1 to a large +ve number.
   // assigning to a word restores our desired signed value.
@@ -1453,258 +2169,329 @@ def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;
 def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>;
 def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>;
 
-// Emit store-immediate, but only when the stored value will not be constant-
-// extended. The reason for that is that there is no pass that can optimize
-// constant extenders in store-immediate instructions. In some cases we can
-// end up will a number of such stores, all of which store the same extended
-// value (e.g. after unrolling a loop that initializes floating point array).
-
-// Predicates to determine if the 16-bit immediate is expressible as a sign-
-// extended 8-bit immediate. Store-immediate-halfword will ignore any bits
-// beyond 0..15, so we don't care what is in there.
-
-def i16in8ImmPred: PatLeaf<(i32 imm), [{
-  int64_t v = (int16_t)N->getSExtValue();
-  return v == (int64_t)(int8_t)v;
-}]>;
-
-// Predicates to determine if the 32-bit immediate is expressible as a sign-
-// extended 8-bit immediate.
-def i32in8ImmPred: PatLeaf<(i32 imm), [{
-  int64_t v = (int32_t)N->getSExtValue();
-  return v == (int64_t)(int8_t)v;
-}]>;
-
+// Even though the offset is not extendable in the store-immediate, we
+// can still generate the fi# in the base address. If the final offset
+// is not valid for the instruction, we will replace it with a scratch
+// register.
 class SmallStackStore<PatFrag Store>
   : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{
   return isSmallStackStore(cast<StoreSDNode>(N));
 }]>;
 
-let AddedComplexity = 40 in {
-  // Even though the offset is not extendable in the store-immediate, we
-  // can still generate the fi# in the base address. If the final offset
-  // is not valid for the instruction, we will replace it with a scratch
-  // register.
-  def: Storexm_fi_pat <SmallStackStore<truncstorei8>, s32_0ImmPred,
-                       ToImmByte, S4_storeirb_io>;
-  def: Storexm_fi_pat <SmallStackStore<truncstorei16>, i16in8ImmPred,
-                       ToImmHalf, S4_storeirh_io>;
-  def: Storexm_fi_pat <SmallStackStore<store>, i32in8ImmPred,
-                       ToImmWord, S4_storeiri_io>;
+// This is the complement of SmallStackStore.
+class LargeStackStore<PatFrag Store>
+  : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{
+  return !isSmallStackStore(cast<StoreSDNode>(N));
+}]>;
 
-//  defm: Storexm_fi_add_pat <truncstorei8, s32_0ImmPred, u6_0ImmPred, ToImmByte,
-//                            S4_storeirb_io>;
-//  defm: Storexm_fi_add_pat <truncstorei16, i16in8ImmPred, u6_1ImmPred,
-//                            ToImmHalf, S4_storeirh_io>;
-//  defm: Storexm_fi_add_pat <store, i32in8ImmPred, u6_2ImmPred, ToImmWord,
-//                            S4_storeiri_io>;
+// Preferred addressing modes for various combinations of stored value
+// and address computation.
+// For stores where the address and value are both immediates, prefer
+// store-immediate. The reason is that the constant-extender optimization
+// can replace store-immediate with a store-register, but there is nothing
+// to generate a store-immediate out of a store-register.
+//
+//         C     R     F    F+C   R+C   R+R   R<<S+C   R<<S+R
+// --+-------+-----+-----+------+-----+-----+--------+--------
+// C |   imm | imm | imm |  imm | imm |  rr |     ur |     rr
+// R |  abs* |  io |  io |   io |  io |  rr |     ur |     rr
+//
+// (*) Absolute or GP-relative.
+//
+// Note that any expression can be matched by Reg. In particular, an immediate
+// can always be placed in a register, so patterns checking for Imm should
+// have a higher priority than the ones involving Reg that could also match.
+// For example, *(p+4) could become r1=#4; memw(r0+r1<<#0) instead of the
+// preferred memw(r0+#4). Similarly Reg+Imm or Reg+Reg should be tried before
+// Reg alone.
+//
+// The order in which the different combinations are tried:
+//
+//         C     F     R    F+C   R+C   R+R   R<<S+C   R<<S+R
+// --+-------+-----+-----+------+-----+-----+--------+--------
+// C |     1 |   6 |   - |    5 |   9 |   - |      - |      -
+// R |     2 |   8 |  12 |    7 |  10 |  11 |      3 |      4
 
-  defm: Storexm_add_pat<truncstorei8, s32_0ImmPred, u6_0ImmPred, ToImmByte,
-                        S4_storeirb_io>;
-  defm: Storexm_add_pat<truncstorei16, i16in8ImmPred, u6_1ImmPred, ToImmHalf,
-                        S4_storeirh_io>;
-  defm: Storexm_add_pat<store, i32in8ImmPred, u6_2ImmPred, ToImmWord,
-                        S4_storeiri_io>;
-}
 
-def: Storexm_simple_pat<truncstorei8,  s32_0ImmPred, ToImmByte, S4_storeirb_io>;
-def: Storexm_simple_pat<truncstorei16, s32_0ImmPred, ToImmHalf, S4_storeirh_io>;
-def: Storexm_simple_pat<store,         s32_0ImmPred, ToImmWord, S4_storeiri_io>;
+// First, match the unusual case of doubleword store into Reg+Imm4, i.e.
+// a store where the offset Imm4 is a multiple of 4, but not of 8. This
+// implies that Reg is also a proper multiple of 4. To still generate a
+// doubleword store, add 4 to Reg, and subtract 4 from the offset.
 
-// op(Ps, op(Pt, Pu))
-class LogLog_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
-  : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, I1:$Pu))),
-        (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
+def s30_2ProperPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v);
+}]>;
+def RoundTo8 : SDNodeXForm<imm, [{
+  int32_t Imm = N->getSExtValue();
+  return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32);
+}]>;
 
-// op(Ps, op(Pt, ~Pu))
-class LogLogNot_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
-  : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, (not I1:$Pu)))),
-        (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
+let AddedComplexity = 150 in
+def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)),
+         (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>;
 
-def: LogLog_pat<and, and, C4_and_and>;
-def: LogLog_pat<and, or,  C4_and_or>;
-def: LogLog_pat<or,  and, C4_or_and>;
-def: LogLog_pat<or,  or,  C4_or_or>;
+class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
+  : Pat<(Store Value:$val, anyimm:$addr),
+        (MI (ToI32 $addr), 0, Value:$val)>;
+class Storexim_abs_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
+                       InstHexagon MI>
+  : Pat<(Store Value:$val, anyimm:$addr),
+        (MI (ToI32 $addr), 0, (ValueMod Value:$val))>;
 
-def: LogLogNot_pat<and, and, C4_and_andn>;
-def: LogLogNot_pat<and, or,  C4_and_orn>;
-def: LogLogNot_pat<or,  and, C4_or_andn>;
-def: LogLogNot_pat<or,  or,  C4_or_orn>;
+let AddedComplexity = 140 in {
+  def: Storexim_abs_pat<truncstorei8,  anyint, ToImmByte, S4_storeirb_io>;
+  def: Storexim_abs_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>;
+  def: Storexim_abs_pat<store,         anyint, ToImmWord, S4_storeiri_io>;
 
-//===----------------------------------------------------------------------===//
-// PIC: Support for PIC compilations. The patterns and SD nodes defined
-// below are needed to support code generation for PIC
-//===----------------------------------------------------------------------===//
+  def: Storexi_abs_pat<truncstorei8,  anyimm, S4_storeirb_io>;
+  def: Storexi_abs_pat<truncstorei16, anyimm, S4_storeirh_io>;
+  def: Storexi_abs_pat<store,         anyimm, S4_storeiri_io>;
+}
 
-def SDT_HexagonAtGot
-  : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>;
-def SDT_HexagonAtPcrel
-  : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
+// GP-relative address
+let AddedComplexity = 120 in {
+  def: Storea_pat<truncstorei8,             I32, addrgp, S2_storerbgp>;
+  def: Storea_pat<truncstorei16,            I32, addrgp, S2_storerhgp>;
+  def: Storea_pat<store,                    I32, addrgp, S2_storerigp>;
+  def: Storea_pat<store,                    I64, addrgp, S2_storerdgp>;
+  def: Storea_pat<store,                    F32, addrgp, S2_storerigp>;
+  def: Storea_pat<store,                    F64, addrgp, S2_storerdgp>;
+  def: Storea_pat<AtomSt<atomic_store_8>,   I32, addrgp, S2_storerbgp>;
+  def: Storea_pat<AtomSt<atomic_store_16>,  I32, addrgp, S2_storerhgp>;
+  def: Storea_pat<AtomSt<atomic_store_32>,  I32, addrgp, S2_storerigp>;
+  def: Storea_pat<AtomSt<atomic_store_64>,  I64, addrgp, S2_storerdgp>;
 
-// AT_GOT address-of-GOT, address-of-global, offset-in-global
-def HexagonAtGot       : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>;
-// AT_PCREL address-of-global
-def HexagonAtPcrel     : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>;
+  def: Stoream_pat<truncstorei8,  I64, addrgp, LoReg,    S2_storerbgp>;
+  def: Stoream_pat<truncstorei16, I64, addrgp, LoReg,    S2_storerhgp>;
+  def: Stoream_pat<truncstorei32, I64, addrgp, LoReg,    S2_storerigp>;
+  def: Stoream_pat<store,         I1,  addrgp, I1toI32,  S2_storerbgp>;
+}
 
-def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)),
-         (L2_loadri_io I32:$got, imm:$addr)>;
-def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off),
-         (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>;
-def: Pat<(HexagonAtPcrel I32:$addr),
-         (C4_addipc imm:$addr)>;
+// Absolute address
+let AddedComplexity = 110 in {
+  def: Storea_pat<truncstorei8,             I32, anyimm0, PS_storerbabs>;
+  def: Storea_pat<truncstorei16,            I32, anyimm1, PS_storerhabs>;
+  def: Storea_pat<store,                    I32, anyimm2, PS_storeriabs>;
+  def: Storea_pat<store,                    I64, anyimm3, PS_storerdabs>;
+  def: Storea_pat<store,                    F32, anyimm2, PS_storeriabs>;
+  def: Storea_pat<store,                    F64, anyimm3, PS_storerdabs>;
+  def: Storea_pat<AtomSt<atomic_store_8>,   I32, anyimm0, PS_storerbabs>;
+  def: Storea_pat<AtomSt<atomic_store_16>,  I32, anyimm1, PS_storerhabs>;
+  def: Storea_pat<AtomSt<atomic_store_32>,  I32, anyimm2, PS_storeriabs>;
+  def: Storea_pat<AtomSt<atomic_store_64>,  I64, anyimm3, PS_storerdabs>;
 
-def: Pat<(i64 (and I64:$Rs, (i64 (not I64:$Rt)))),
-         (A4_andnp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
-def: Pat<(i64 (or  I64:$Rs, (i64 (not I64:$Rt)))),
-         (A4_ornp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
+  def: Stoream_pat<truncstorei8,  I64, anyimm0, LoReg,    PS_storerbabs>;
+  def: Stoream_pat<truncstorei16, I64, anyimm1, LoReg,    PS_storerhabs>;
+  def: Stoream_pat<truncstorei32, I64, anyimm2, LoReg,    PS_storeriabs>;
+  def: Stoream_pat<store,         I1,  anyimm0, I1toI32,  PS_storerbabs>;
+}
 
-def: Pat<(add I32:$Rs, (add I32:$Ru, s32_0ImmPred:$s6)),
-         (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>;
+// Reg<<S + Imm
+let AddedComplexity = 100 in {
+  def: Storexu_shl_pat<truncstorei8,  I32, anyimm0, S4_storerb_ur>;
+  def: Storexu_shl_pat<truncstorei16, I32, anyimm1, S4_storerh_ur>;
+  def: Storexu_shl_pat<store,         I32, anyimm2, S4_storeri_ur>;
+  def: Storexu_shl_pat<store,         I64, anyimm3, S4_storerd_ur>;
+  def: Storexu_shl_pat<store,         F32, anyimm2, S4_storeri_ur>;
+  def: Storexu_shl_pat<store,         F64, anyimm3, S4_storerd_ur>;
 
-// Rd=add(Rs,sub(#s6,Ru))
-def: Pat<(add I32:$src1, (sub s32_0ImmPred:$src2,
-                                        I32:$src3)),
-         (S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>;
+  def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)),
+           (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>;
+}
 
-// Rd=sub(add(Rs,#s6),Ru)
-def: Pat<(sub (add I32:$src1, s32_0ImmPred:$src2),
-                   I32:$src3),
-         (S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>;
+// Reg<<S + Reg
+let AddedComplexity = 90 in {
+  def: Storexr_shl_pat<truncstorei8,  I32, S4_storerb_rr>;
+  def: Storexr_shl_pat<truncstorei16, I32, S4_storerh_rr>;
+  def: Storexr_shl_pat<store,         I32, S4_storeri_rr>;
+  def: Storexr_shl_pat<store,         I64, S4_storerd_rr>;
+  def: Storexr_shl_pat<store,         F32, S4_storeri_rr>;
+  def: Storexr_shl_pat<store,         F64, S4_storerd_rr>;
 
-// Rd=add(sub(Rs,Ru),#s6)
-def: Pat<(add (sub I32:$src1, I32:$src3),
-                   (s32_0ImmPred:$src2)),
-         (S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>;
+  def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)),
+           (S4_storerb_ur IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>;
+}
 
-def: Pat<(xor I64:$dst2,
-              (xor I64:$Rss, I64:$Rtt)),
-         (M4_xor_xacc DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt)>;
-def: Pat<(or I32:$Ru, (and (i32 IntRegs:$_src_), s32_0ImmPred:$s10)),
-         (S4_or_andix IntRegs:$Ru, IntRegs:$_src_, imm:$s10)>;
+class SS_<PatFrag F> : SmallStackStore<F>;
+class LS_<PatFrag F> : LargeStackStore<F>;
 
-def: Pat<(or I32:$src1, (and I32:$Rs, s32_0ImmPred:$s10)),
-         (S4_or_andi IntRegs:$src1, IntRegs:$Rs, imm:$s10)>;
+multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> {
+  defm: Storexim_fi_add_pat<S, V, O, M, I>;
+}
+multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> {
+  defm: Storexi_fi_add_pat<S, V, O, I>;
+}
 
-def: Pat<(or I32:$src1, (or I32:$Rs, s32_0ImmPred:$s10)),
-         (S4_or_ori IntRegs:$src1, IntRegs:$Rs, imm:$s10)>;
+// Fi+Imm, store-immediate
+let AddedComplexity = 80 in {
+  defm: IMFA_<SS_<truncstorei8>,  anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>;
+  defm: IMFA_<SS_<truncstorei16>, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>;
+  defm: IMFA_<SS_<store>,         anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>;
 
+  defm: IFA_<SS_<truncstorei8>,   anyimm, u6_0ImmPred, S4_storeirb_io>;
+  defm: IFA_<SS_<truncstorei16>,  anyimm, u6_1ImmPred, S4_storeirh_io>;
+  defm: IFA_<SS_<store>,          anyimm, u6_2ImmPred, S4_storeiri_io>;
 
+  // For large-stack stores, generate store-register (prefer explicit Fi
+  // in the address).
+  defm: IMFA_<LS_<truncstorei8>,   anyimm, u6_0ImmPred, ToI32, S2_storerb_io>;
+  defm: IMFA_<LS_<truncstorei16>,  anyimm, u6_1ImmPred, ToI32, S2_storerh_io>;
+  defm: IMFA_<LS_<store>,          anyimm, u6_2ImmPred, ToI32, S2_storeri_io>;
+}
 
-// Count trailing zeros: 64-bit.
-def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>;
+// Fi, store-immediate
+let AddedComplexity = 70 in {
+  def: Storexim_fi_pat<SS_<truncstorei8>,  anyint, ToImmByte, S4_storeirb_io>;
+  def: Storexim_fi_pat<SS_<truncstorei16>, anyint, ToImmHalf, S4_storeirh_io>;
+  def: Storexim_fi_pat<SS_<store>,         anyint, ToImmWord, S4_storeiri_io>;
 
-// Count trailing ones: 64-bit.
-def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>;
+  def: Storexi_fi_pat<SS_<truncstorei8>,   anyimm, S4_storeirb_io>;
+  def: Storexi_fi_pat<SS_<truncstorei16>,  anyimm, S4_storeirh_io>;
+  def: Storexi_fi_pat<SS_<store>,          anyimm, S4_storeiri_io>;
 
-// Define leading/trailing patterns that require zero-extensions to 64 bits.
-def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>;
-def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>;
-def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>;
-def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>;
+  // For large-stack stores, generate store-register (prefer explicit Fi
+  // in the address).
+  def: Storexim_fi_pat<LS_<truncstorei8>,  anyimm, ToI32, S2_storerb_io>;
+  def: Storexim_fi_pat<LS_<truncstorei16>, anyimm, ToI32, S2_storerh_io>;
+  def: Storexim_fi_pat<LS_<store>,         anyimm, ToI32, S2_storeri_io>;
+}
 
-def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>;
-def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>;
+// Fi+Imm, Fi, store-register
+let AddedComplexity = 60 in {
+  defm: Storexi_fi_add_pat<truncstorei8,  I32, anyimm, S2_storerb_io>;
+  defm: Storexi_fi_add_pat<truncstorei16, I32, anyimm, S2_storerh_io>;
+  defm: Storexi_fi_add_pat<store,         I32, anyimm, S2_storeri_io>;
+  defm: Storexi_fi_add_pat<store,         I64, anyimm, S2_storerd_io>;
+  defm: Storexi_fi_add_pat<store,         F32, anyimm, S2_storeri_io>;
+  defm: Storexi_fi_add_pat<store,         F64, anyimm, S2_storerd_io>;
+  defm: Storexim_fi_add_pat<store, I1, anyimm, I1toI32, S2_storerb_io>;
 
-def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>;
-def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>;
+  def: Storexi_fi_pat<truncstorei8,   I32, S2_storerb_io>;
+  def: Storexi_fi_pat<truncstorei16,  I32, S2_storerh_io>;
+  def: Storexi_fi_pat<store,          I32, S2_storeri_io>;
+  def: Storexi_fi_pat<store,          I64, S2_storerd_io>;
+  def: Storexi_fi_pat<store,          F32, S2_storeri_io>;
+  def: Storexi_fi_pat<store,          F64, S2_storerd_io>;
+  def: Storexim_fi_pat<store, I1, I1toI32, S2_storerb_io>;
+}
 
-def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>;
-def: Pat<(bswap I64:$Rss), (A2_combinew (A2_swiz (LoReg $Rss)),
-                                        (A2_swiz (HiReg $Rss)))>;
 
-let AddedComplexity = 20 in {   // Complexity greater than cmp reg-imm.
-  def: Pat<(i1 (seteq (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)),
-           (S4_ntstbit_i I32:$Rs, u5_0ImmPred:$u5)>;
-  def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)),
-           (S4_ntstbit_r I32:$Rs, I32:$Rt)>;
+multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> {
+  defm: Storexim_add_pat<S, V, O, M, I>;
+}
+multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> {
+  defm: Storexi_add_pat<S, V, O, I>;
 }
 
-// Add extra complexity to prefer these instructions over bitsset/bitsclr.
-// The reason is that tstbit/ntstbit can be folded into a compound instruction:
-//   if ([!]tstbit(...)) jump ...
-let AddedComplexity = 100 in
-def: Pat<(i1 (setne (and I32:$Rs, (i32 IsPow2_32:$u5)), (i32 0))),
-         (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>;
+// Reg+Imm, store-immediate
+let AddedComplexity = 50 in {
+  defm: IMRA_<truncstorei8,   anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>;
+  defm: IMRA_<truncstorei16,  anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>;
+  defm: IMRA_<store,          anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>;
 
-let AddedComplexity = 100 in
-def: Pat<(i1 (seteq (and I32:$Rs, (i32 IsPow2_32:$u5)), (i32 0))),
-         (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>;
+  defm: IRA_<truncstorei8,    anyimm, u6_0ImmPred, S4_storeirb_io>;
+  defm: IRA_<truncstorei16,   anyimm, u6_1ImmPred, S4_storeirh_io>;
+  defm: IRA_<store,           anyimm, u6_2ImmPred, S4_storeiri_io>;
+}
 
-// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
-// represented as a compare against "value & 0xFF", which is an exact match
-// for cmpb (same for cmph). The patterns below do not contain any additional
-// complexity that would make them preferable, and if they were actually used
-// instead of cmpb/cmph, they would result in a compare against register that
-// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
-def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)),
-         (C4_nbitsclri I32:$Rs, u6_0ImmPred:$u6)>;
-def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
-         (C4_nbitsclr I32:$Rs, I32:$Rt)>;
-def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
-         (C4_nbitsset I32:$Rs, I32:$Rt)>;
+// Reg+Imm, store-register
+let AddedComplexity = 40 in {
+  defm: Storexi_pat<truncstorei8,   I32, anyimm0, S2_storerb_io>;
+  defm: Storexi_pat<truncstorei16,  I32, anyimm1, S2_storerh_io>;
+  defm: Storexi_pat<store,          I32, anyimm2, S2_storeri_io>;
+  defm: Storexi_pat<store,          I64, anyimm3, S2_storerd_io>;
+  defm: Storexi_pat<store,          F32, anyimm2, S2_storeri_io>;
+  defm: Storexi_pat<store,          F64, anyimm3, S2_storerd_io>;
 
+  defm: Storexim_pat<truncstorei8,  I64, anyimm0, LoReg,   S2_storerb_io>;
+  defm: Storexim_pat<truncstorei16, I64, anyimm1, LoReg,   S2_storerh_io>;
+  defm: Storexim_pat<truncstorei32, I64, anyimm2, LoReg,   S2_storeri_io>;
+  defm: Storexim_pat<store,         I1,  anyimm0, I1toI32, S2_storerb_io>;
 
-def: Pat<(add (mul I32:$Rs, u6_0ImmPred:$U6), u32_0ImmPred:$u6),
-         (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>;
-def: Pat<(add (mul I32:$Rs, u6_0ImmPred:$U6),
-              (HexagonCONST32 tglobaladdr:$global)),
-         (M4_mpyri_addi tglobaladdr:$global, IntRegs:$Rs, imm:$U6)>;
-def: Pat<(add (mul I32:$Rs, I32:$Rt), u32_0ImmPred:$u6),
-         (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(add (mul I32:$Rs, I32:$Rt),
-              (HexagonCONST32 tglobaladdr:$global)),
-         (M4_mpyrr_addi tglobaladdr:$global, IntRegs:$Rs, IntRegs:$Rt)>;
-def: Pat<(add I32:$src1, (mul I32:$src3, u6_2ImmPred:$src2)),
-         (M4_mpyri_addr_u2 IntRegs:$src1, imm:$src2, IntRegs:$src3)>;
-def: Pat<(add I32:$src1, (mul I32:$src3, u32_0ImmPred:$src2)),
-         (M4_mpyri_addr IntRegs:$src1, IntRegs:$src3, imm:$src2)>;
+  defm: Storexi_pat<AtomSt<atomic_store_8>,  I32, anyimm0, S2_storerb_io>;
+  defm: Storexi_pat<AtomSt<atomic_store_16>, I32, anyimm1, S2_storerh_io>;
+  defm: Storexi_pat<AtomSt<atomic_store_32>, I32, anyimm2, S2_storeri_io>;
+  defm: Storexi_pat<AtomSt<atomic_store_64>, I64, anyimm3, S2_storerd_io>;
+}
 
-def: Pat<(add I32:$Ru, (mul (i32 IntRegs:$_src_), I32:$Rs)),
-         (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs)>;
+// Reg+Reg
+let AddedComplexity = 30 in {
+  def: Storexr_add_pat<truncstorei8,  I32, S4_storerb_rr>;
+  def: Storexr_add_pat<truncstorei16, I32, S4_storerh_rr>;
+  def: Storexr_add_pat<store,         I32, S4_storeri_rr>;
+  def: Storexr_add_pat<store,         I64, S4_storerd_rr>;
+  def: Storexr_add_pat<store,         F32, S4_storeri_rr>;
+  def: Storexr_add_pat<store,         F64, S4_storerd_rr>;
 
-def: T_vcmp_pat<A4_vcmpbgt, setgt, v8i8>;
+  def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)),
+           (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>;
+}
 
-class T_Shift_CommOp_pat<InstHexagon MI, SDNode Op, SDNode ShOp>
-  : Pat<(Op (ShOp IntRegs:$Rx, u5_0ImmPred:$U5), u32_0ImmPred:$u8),
-        (MI u32_0ImmPred:$u8, IntRegs:$Rx, u5_0ImmPred:$U5)>;
+// Reg, store-immediate
+let AddedComplexity = 20 in {
+  def: Storexim_base_pat<truncstorei8,  anyint, ToImmByte, S4_storeirb_io>;
+  def: Storexim_base_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>;
+  def: Storexim_base_pat<store,         anyint, ToImmWord, S4_storeiri_io>;
 
-let AddedComplexity = 200 in {
-  def : T_Shift_CommOp_pat <S4_addi_asl_ri, add, shl>;
-  def : T_Shift_CommOp_pat <S4_addi_lsr_ri, add, srl>;
-  def : T_Shift_CommOp_pat <S4_andi_asl_ri, and, shl>;
-  def : T_Shift_CommOp_pat <S4_andi_lsr_ri, and, srl>;
+  def: Storexi_base_pat<truncstorei8,   anyimm, S4_storeirb_io>;
+  def: Storexi_base_pat<truncstorei16,  anyimm, S4_storeirh_io>;
+  def: Storexi_base_pat<store,          anyimm, S4_storeiri_io>;
 }
 
-let AddedComplexity = 30 in {
-  def : T_Shift_CommOp_pat <S4_ori_asl_ri,  or,  shl>;
-  def : T_Shift_CommOp_pat <S4_ori_lsr_ri,  or,  srl>;
-}
+// Reg, store-register
+let AddedComplexity = 10 in {
+  def: Storexi_base_pat<truncstorei8,   I32, S2_storerb_io>;
+  def: Storexi_base_pat<truncstorei16,  I32, S2_storerh_io>;
+  def: Storexi_base_pat<store,          I32, S2_storeri_io>;
+  def: Storexi_base_pat<store,          I64, S2_storerd_io>;
+  def: Storexi_base_pat<store,          F32, S2_storeri_io>;
+  def: Storexi_base_pat<store,          F64, S2_storerd_io>;
 
-class T_Shift_Op_pat<InstHexagon MI, SDNode Op, SDNode ShOp>
-  : Pat<(Op u32_0ImmPred:$u8, (ShOp IntRegs:$Rx, u5_0ImmPred:$U5)),
-        (MI u32_0ImmPred:$u8, IntRegs:$Rx, u5_0ImmPred:$U5)>;
+  def: Storexim_base_pat<truncstorei8,  I64, LoReg,   S2_storerb_io>;
+  def: Storexim_base_pat<truncstorei16, I64, LoReg,   S2_storerh_io>;
+  def: Storexim_base_pat<truncstorei32, I64, LoReg,   S2_storeri_io>;
+  def: Storexim_base_pat<store,         I1,  I1toI32, S2_storerb_io>;
 
-def : T_Shift_Op_pat <S4_subi_asl_ri, sub, shl>;
-def : T_Shift_Op_pat <S4_subi_lsr_ri, sub, srl>;
+  def: Storexi_base_pat<AtomSt<atomic_store_8>,   I32, S2_storerb_io>;
+  def: Storexi_base_pat<AtomSt<atomic_store_16>,  I32, S2_storerh_io>;
+  def: Storexi_base_pat<AtomSt<atomic_store_32>,  I32, S2_storeri_io>;
+  def: Storexi_base_pat<AtomSt<atomic_store_64>,  I64, S2_storerd_io>;
+}
 
-let AddedComplexity = 200 in {
-  def: Pat<(add addrga:$addr, (shl I32:$src2, u5_0ImmPred:$src3)),
-           (S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5_0ImmPred:$src3)>;
-  def: Pat<(add addrga:$addr, (srl I32:$src2, u5_0ImmPred:$src3)),
-           (S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5_0ImmPred:$src3)>;
-  def: Pat<(sub addrga:$addr, (shl I32:$src2, u5_0ImmPred:$src3)),
-           (S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5_0ImmPred:$src3)>;
-  def: Pat<(sub addrga:$addr, (srl I32:$src2, u5_0ImmPred:$src3)),
-           (S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5_0ImmPred:$src3)>;
+// HVX stores
+
+multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag ImmPred,
+                     PatFrag Value> {
+  def: Pat<(Store Value:$Vs, I32:$Rt),
+           (MI I32:$Rt, 0, Value:$Vs)>;
+  def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
+           (MI I32:$Rt, imm:$s, Value:$Vs)>;
 }
 
-def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt),
-         (S4_lsli imm:$s6, IntRegs:$Rt)>;
+let Predicates = [UseHVX] in {
+  multiclass HvxStVs_pat<InstHexagon MI, PatFrag Store> {
+    defm: HvxSt_pat<MI, Store, IsVecOff, HVI8>;
+    defm: HvxSt_pat<MI, Store, IsVecOff, HVI16>;
+    defm: HvxSt_pat<MI, Store, IsVecOff, HVI32>;
+  }
+  defm: HvxStVs_pat<V6_vS32b_nt_ai, alignednontemporalstore>;
+  defm: HvxStVs_pat<V6_vS32b_ai,    alignedstore>;
+  defm: HvxStVs_pat<V6_vS32Ub_ai,   unalignedstore>;
 
+  multiclass HvxStWs_pat<InstHexagon MI, PatFrag Store> {
+    defm: HvxSt_pat<MI, Store, IsVecOff, HWI8>;
+    defm: HvxSt_pat<MI, Store, IsVecOff, HWI16>;
+    defm: HvxSt_pat<MI, Store, IsVecOff, HWI32>;
+  }
+  defm: HvxStWs_pat<PS_vstorerw_nt_ai, alignednontemporalstore>;
+  defm: HvxStWs_pat<PS_vstorerw_ai,    alignedstore>;
+  defm: HvxStWs_pat<PS_vstorerwu_ai,   unalignedstore>;
+}
 
-//===----------------------------------------------------------------------===//
-// MEMOP
-//===----------------------------------------------------------------------===//
+
+// --(14) Memop ----------------------------------------------------------
+//
 
 def m5_0Imm8Pred : PatLeaf<(i32 imm), [{
   int8_t V = N->getSExtValue();
@@ -1751,25 +2538,10 @@ def LogN2_16 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
 }]>;
 
-def NegImm8 : SDNodeXForm<imm, [{
-  int8_t NV = -N->getSExtValue();
-  return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
-}]>;
-
-def NegImm16 : SDNodeXForm<imm, [{
-  int16_t NV = -N->getSExtValue();
-  return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
-}]>;
-
-def NegImm32 : SDNodeXForm<imm, [{
-  int32_t NV = -N->getSExtValue();
-  return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
-}]>;
-
 def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>;
 
-multiclass Memopxr_simple_pat<PatFrag Load, PatFrag Store, SDNode Oper,
-                              InstHexagon MI> {
+multiclass Memopxr_base_pat<PatFrag Load, PatFrag Store, SDNode Oper,
+                            InstHexagon MI> {
   // Addr: i32
   def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs),
            (MI I32:$Rs, 0, I32:$A)>;
@@ -1798,11 +2570,11 @@ multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
 
 multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
                        SDNode Oper, InstHexagon MI> {
-  defm: Memopxr_simple_pat <Load, Store,          Oper, MI>;
-  defm: Memopxr_add_pat    <Load, Store, ImmPred, Oper, MI>;
+  defm: Memopxr_base_pat <Load, Store,          Oper, MI>;
+  defm: Memopxr_add_pat  <Load, Store, ImmPred, Oper, MI>;
 }
 
-let AddedComplexity = 180 in {
+let AddedComplexity = 200 in {
   // add reg
   defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add,
         /*anyext*/  L4_add_memopb_io>;
@@ -1865,9 +2637,8 @@ let AddedComplexity = 180 in {
 }
 
 
-multiclass Memopxi_simple_pat<PatFrag Load, PatFrag Store, SDNode Oper,
-                              PatFrag Arg, SDNodeXForm ArgMod,
-                              InstHexagon MI> {
+multiclass Memopxi_base_pat<PatFrag Load, PatFrag Store, SDNode Oper,
+                            PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> {
   // Addr: i32
   def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs),
            (MI I32:$Rs, 0, (ArgMod Arg:$A))>;
@@ -1898,12 +2669,11 @@ multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
 multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
                        SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod,
                        InstHexagon MI> {
-  defm: Memopxi_simple_pat <Load, Store,          Oper, Arg, ArgMod, MI>;
-  defm: Memopxi_add_pat    <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>;
+  defm: Memopxi_base_pat <Load, Store,          Oper, Arg, ArgMod, MI>;
+  defm: Memopxi_add_pat  <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>;
 }
 
-
-let AddedComplexity = 200 in {
+let AddedComplexity = 220 in {
   // add imm
   defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred,
         /*anyext*/  IdImm, L4_iadd_memopb_io>;
@@ -1997,1369 +2767,219 @@ let AddedComplexity = 200 in {
 		    Log2_32, L4_ior_memopw_io>;
 }
 
-def : T_CMP_pat <C4_cmpneqi,  setne,  s32_0ImmPred>;
-def : T_CMP_pat <C4_cmpltei,  setle,  s32_0ImmPred>;
-def : T_CMP_pat <C4_cmplteui, setule, u9_0ImmPred>;
-
-// Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
-def: Pat<(i1 (setlt I32:$src1, s32_0ImmPred:$src2)),
-         (C4_cmpltei IntRegs:$src1, (SDEC1 s32_0ImmPred:$src2))>;
-
-// rs != rt -> !(rs == rt).
-def: Pat<(i1 (setne I32:$src1, s32_0ImmPred:$src2)),
-         (C4_cmpneqi IntRegs:$src1, s32_0ImmPred:$src2)>;
-
-// For the sequence
-//   zext( setult ( and(Rs, 255), u8))
-// Use the isdigit transformation below
 
-
-def u7_0PosImmPred : ImmLeaf<i32, [{
-  // True if the immediate fits in an 7-bit unsigned field and
-  // is strictly greater than 0.
-  return Imm > 0 && isUInt<7>(Imm);
-}]>;
-
-
-// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
-// for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
-// The isdigit transformation relies on two 'clever' aspects:
-// 1) The data type is unsigned which allows us to eliminate a zero test after
-//    biasing the expression by 48. We are depending on the representation of
-//    the unsigned types, and semantics.
-// 2) The front end has converted <= 9 into < 10 on entry to LLVM
+// --(15) Call -----------------------------------------------------------
 //
-// For the C code:
-//   retval = ((c>='0') & (c<='9')) ? 1 : 0;
-// The code is transformed upstream of llvm into
-//   retval = (c-48) < 10 ? 1 : 0;
-
-let AddedComplexity = 139 in
-def: Pat<(i32 (zext (i1 (setult (and I32:$src1, 255), u7_0PosImmPred:$src2)))),
-         (C2_muxii (A4_cmpbgtui IntRegs:$src1, (UDEC1 imm:$src2)), 0, 1)>;
-
-class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
-  : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
-
-class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod,
-                 InstHexagon MI>
-  : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
-
-class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
-  : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
-
-class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod,
-                  InstHexagon MI>
-  : Pat<(Store Value:$val, Addr:$addr),
-        (MI Addr:$addr, (ValueMod Value:$val))>;
-
-let AddedComplexity = 30 in {
-  def: Storea_pat<truncstorei8,  I32, addrga, PS_storerbabs>;
-  def: Storea_pat<truncstorei16, I32, addrga, PS_storerhabs>;
-  def: Storea_pat<store,         I32, addrga, PS_storeriabs>;
-  def: Storea_pat<store,         I64, addrga, PS_storerdabs>;
 
-  def: Stoream_pat<truncstorei8,  I64, addrga, LoReg, PS_storerbabs>;
-  def: Stoream_pat<truncstorei16, I64, addrga, LoReg, PS_storerhabs>;
-  def: Stoream_pat<truncstorei32, I64, addrga, LoReg, PS_storeriabs>;
-}
+// Pseudo instructions.
+def SDT_SPCallSeqStart
+  : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
+def SDT_SPCallSeqEnd
+  : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
 
-def: Storea_pat<SwapSt<atomic_store_8>,  I32, addrgp, S2_storerbgp>;
-def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhgp>;
-def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storerigp>;
-def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdgp>;
+def callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
+                          [SDNPHasChain, SDNPOutGlue]>;
+def callseq_end:   SDNode<"ISD::CALLSEQ_END",   SDT_SPCallSeqEnd,
+                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
-let AddedComplexity = 100 in {
-  def: Storea_pat<truncstorei8,  I32, addrgp, S2_storerbgp>;
-  def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>;
-  def: Storea_pat<store,         I32, addrgp, S2_storerigp>;
-  def: Storea_pat<store,         I64, addrgp, S2_storerdgp>;
+def SDT_SPCall: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
 
-  // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
-  //       to "r0 = 1; memw(#foo) = r0"
-  let AddedComplexity = 100 in
-  def: Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
-           (S2_storerbgp tglobaladdr:$global, (A2_tfrsi 1))>;
-}
+def HexagonTCRet: SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
+                         [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
+def callv3: SDNode<"HexagonISD::CALL", SDT_SPCall,
+                   [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
+def callv3nr: SDNode<"HexagonISD::CALLnr", SDT_SPCall,
+                     [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
 
-class LoadAbs_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
-  : Pat <(VT (ldOp (HexagonCONST32 tglobaladdr:$absaddr))),
-         (VT (MI tglobaladdr:$absaddr))>;
+def: Pat<(callseq_start timm:$amt, timm:$amt2),
+         (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>;
+def: Pat<(callseq_end timm:$amt1, timm:$amt2),
+         (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>;
 
-let AddedComplexity  = 30 in {
-  def: LoadAbs_pats <load,        PS_loadriabs>;
-  def: LoadAbs_pats <zextloadi1,  PS_loadrubabs>;
-  def: LoadAbs_pats <sextloadi8,  PS_loadrbabs>;
-  def: LoadAbs_pats <extloadi8,   PS_loadrubabs>;
-  def: LoadAbs_pats <zextloadi8,  PS_loadrubabs>;
-  def: LoadAbs_pats <sextloadi16, PS_loadrhabs>;
-  def: LoadAbs_pats <extloadi16,  PS_loadruhabs>;
-  def: LoadAbs_pats <zextloadi16, PS_loadruhabs>;
-  def: LoadAbs_pats <load,        PS_loadrdabs, i64>;
-}
+def: Pat<(HexagonTCRet tglobaladdr:$dst),   (PS_tailcall_i tglobaladdr:$dst)>;
+def: Pat<(HexagonTCRet texternalsym:$dst),  (PS_tailcall_i texternalsym:$dst)>;
+def: Pat<(HexagonTCRet I32:$dst),           (PS_tailcall_r I32:$dst)>;
 
-let AddedComplexity  = 30 in
-def: Pat<(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$absaddr))),
-         (ToZext64 (PS_loadrubabs tglobaladdr:$absaddr))>;
+def: Pat<(callv3 I32:$dst),                 (J2_callr I32:$dst)>;
+def: Pat<(callv3 tglobaladdr:$dst),         (J2_call tglobaladdr:$dst)>;
+def: Pat<(callv3 texternalsym:$dst),        (J2_call texternalsym:$dst)>;
+def: Pat<(callv3 tglobaltlsaddr:$dst),      (J2_call tglobaltlsaddr:$dst)>;
 
-def: Loada_pat<atomic_load_8,  i32, addrgp, L2_loadrubgp>;
-def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
-def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
-def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
+def: Pat<(callv3nr I32:$dst),               (PS_callr_nr I32:$dst)>;
+def: Pat<(callv3nr tglobaladdr:$dst),       (PS_call_nr tglobaladdr:$dst)>;
+def: Pat<(callv3nr texternalsym:$dst),      (PS_call_nr texternalsym:$dst)>;
 
-def: Loadam_pat<load, i1, addrga, I32toI1, PS_loadrubabs>;
-def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
+def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
+                     [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
 
-def: Stoream_pat<store, I1, addrga, I1toI32, PS_storerbabs>;
-def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>;
+def: Pat<(retflag),   (PS_jmpret (i32 R31))>;
+def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>;
 
-// Map from load(globaladdress) -> mem[u][bhwd](#foo)
-class LoadGP_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
-  : Pat <(VT (ldOp (HexagonCONST32_GP tglobaladdr:$global))),
-         (VT (MI tglobaladdr:$global))>;
 
-let AddedComplexity = 100 in {
-  def: LoadGP_pats <extloadi8,   L2_loadrubgp>;
-  def: LoadGP_pats <sextloadi8,  L2_loadrbgp>;
-  def: LoadGP_pats <zextloadi8,  L2_loadrubgp>;
-  def: LoadGP_pats <extloadi16,  L2_loadruhgp>;
-  def: LoadGP_pats <sextloadi16, L2_loadrhgp>;
-  def: LoadGP_pats <zextloadi16, L2_loadruhgp>;
-  def: LoadGP_pats <load,        L2_loadrigp>;
-  def: LoadGP_pats <load,        L2_loadrdgp, i64>;
-}
+// --(16) Branch ---------------------------------------------------------
+//
 
-// When the Interprocedural Global Variable optimizer realizes that a certain
-// global variable takes only two constant values, it shrinks the global to
-// a boolean. Catch those loads here in the following 3 patterns.
-let AddedComplexity = 100 in {
-  def: LoadGP_pats <extloadi1, L2_loadrubgp>;
-  def: LoadGP_pats <zextloadi1, L2_loadrubgp>;
-}
+def: Pat<(br      bb:$dst),         (J2_jump  b30_2Imm:$dst)>;
+def: Pat<(brind   I32:$dst),        (J2_jumpr I32:$dst)>;
 
-// Transfer global address into a register
-def: Pat<(HexagonCONST32 tglobaladdr:$Rs),      (A2_tfrsi imm:$Rs)>;
-def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi imm:$Rs)>;
-def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs),   (A2_tfrsi imm:$Rs)>;
+def: Pat<(brcond I1:$Pu, bb:$dst),
+         (J2_jumpt I1:$Pu, bb:$dst)>;
+def: Pat<(brcond (not I1:$Pu), bb:$dst),
+         (J2_jumpf I1:$Pu, bb:$dst)>;
+def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst),
+         (J2_jumpf I1:$Pu, bb:$dst)>;
+def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst),
+         (J2_jumpt I1:$Pu, bb:$dst)>;
 
-let AddedComplexity  = 30 in {
-  def: Storea_pat<truncstorei8,  I32, u32_0ImmPred, PS_storerbabs>;
-  def: Storea_pat<truncstorei16, I32, u32_0ImmPred, PS_storerhabs>;
-  def: Storea_pat<store,         I32, u32_0ImmPred, PS_storeriabs>;
-  def: Storea_pat<store,         I64, u32_0ImmPred, PS_storerdabs>;
 
-  def: Stoream_pat<truncstorei8,  I64, u32_0ImmPred, LoReg, PS_storerbabs>;
-  def: Stoream_pat<truncstorei16, I64, u32_0ImmPred, LoReg, PS_storerhabs>;
-  def: Stoream_pat<truncstorei32, I64, u32_0ImmPred, LoReg, PS_storeriabs>;
-}
+// --(17) Misc -----------------------------------------------------------
 
-let AddedComplexity  = 30 in {
-  def: Loada_pat<load,        i32, u32_0ImmPred, PS_loadriabs>;
-  def: Loada_pat<sextloadi8,  i32, u32_0ImmPred, PS_loadrbabs>;
-  def: Loada_pat<zextloadi8,  i32, u32_0ImmPred, PS_loadrubabs>;
-  def: Loada_pat<sextloadi16, i32, u32_0ImmPred, PS_loadrhabs>;
-  def: Loada_pat<zextloadi16, i32, u32_0ImmPred, PS_loadruhabs>;
-  def: Loada_pat<load,        i64, u32_0ImmPred, PS_loadrdabs>;
 
-  def: Loadam_pat<extloadi8,   i64, u32_0ImmPred, ToZext64, PS_loadrubabs>;
-  def: Loadam_pat<sextloadi8,  i64, u32_0ImmPred, ToSext64, PS_loadrbabs>;
-  def: Loadam_pat<zextloadi8,  i64, u32_0ImmPred, ToZext64, PS_loadrubabs>;
+// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
+// for C code of the form r = (c>='0' && c<='9') ? 1 : 0.
+// The isdigit transformation relies on two 'clever' aspects:
+// 1) The data type is unsigned which allows us to eliminate a zero test after
+//    biasing the expression by 48. We are depending on the representation of
+//    the unsigned types, and semantics.
+// 2) The front end has converted <= 9 into < 10 on entry to LLVM.
+//
+// For the C code:
+//   retval = (c >= '0' && c <= '9') ? 1 : 0;
+// The code is transformed upstream of llvm into
+//   retval = (c-48) < 10 ? 1 : 0;
 
-  def: Loadam_pat<extloadi16,  i64, u32_0ImmPred, ToZext64, PS_loadruhabs>;
-  def: Loadam_pat<sextloadi16, i64, u32_0ImmPred, ToSext64, PS_loadrhabs>;
-  def: Loadam_pat<zextloadi16, i64, u32_0ImmPred, ToZext64, PS_loadruhabs>;
+def u7_0PosImmPred : ImmLeaf<i32, [{
+  // True if the immediate fits in an 7-bit unsigned field and is positive.
+  return Imm > 0 && isUInt<7>(Imm);
+}]>;
 
-  def: Loadam_pat<extloadi32,  i64, u32_0ImmPred, ToZext64, PS_loadriabs>;
-  def: Loadam_pat<sextloadi32, i64, u32_0ImmPred, ToSext64, PS_loadriabs>;
-  def: Loadam_pat<zextloadi32, i64, u32_0ImmPred, ToZext64, PS_loadriabs>;
-}
+let AddedComplexity = 139 in
+def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))),
+         (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>;
 
-// Indexed store word - global address.
-// memw(Rs+#u6:2)=#S8
 let AddedComplexity = 100 in
-defm: Storex_add_pat<store, addrga, u6_2ImmPred, S4_storeiri_io>;
-
-// Load from a global address that has only one use in the current basic block.
-let AddedComplexity = 100 in {
-  def: Loada_pat<extloadi8,   i32, addrga, PS_loadrubabs>;
-  def: Loada_pat<sextloadi8,  i32, addrga, PS_loadrbabs>;
-  def: Loada_pat<zextloadi8,  i32, addrga, PS_loadrubabs>;
-
-  def: Loada_pat<extloadi16,  i32, addrga, PS_loadruhabs>;
-  def: Loada_pat<sextloadi16, i32, addrga, PS_loadrhabs>;
-  def: Loada_pat<zextloadi16, i32, addrga, PS_loadruhabs>;
-
-  def: Loada_pat<load,        i32, addrga, PS_loadriabs>;
-  def: Loada_pat<load,        i64, addrga, PS_loadrdabs>;
-}
-
-// Store to a global address that has only one use in the current basic block.
-let AddedComplexity = 100 in {
-  def: Storea_pat<truncstorei8,  I32, addrga, PS_storerbabs>;
-  def: Storea_pat<truncstorei16, I32, addrga, PS_storerhabs>;
-  def: Storea_pat<store,         I32, addrga, PS_storeriabs>;
-  def: Storea_pat<store,         I64, addrga, PS_storerdabs>;
-
-  def: Stoream_pat<truncstorei32, I64, addrga, LoReg, PS_storeriabs>;
-}
-
-// i8/i16/i32 -> i64 loads
-// We need a complexity of 120 here to override preceding handling of
-// zextload.
-let AddedComplexity = 120 in {
-  def: Loadam_pat<extloadi8,   i64, addrga, ToZext64, PS_loadrubabs>;
-  def: Loadam_pat<sextloadi8,  i64, addrga, ToSext64, PS_loadrbabs>;
-  def: Loadam_pat<zextloadi8,  i64, addrga, ToZext64, PS_loadrubabs>;
-
-  def: Loadam_pat<extloadi16,  i64, addrga, ToZext64, PS_loadruhabs>;
-  def: Loadam_pat<sextloadi16, i64, addrga, ToSext64, PS_loadrhabs>;
-  def: Loadam_pat<zextloadi16, i64, addrga, ToZext64, PS_loadruhabs>;
-
-  def: Loadam_pat<extloadi32,  i64, addrga, ToZext64, PS_loadriabs>;
-  def: Loadam_pat<sextloadi32, i64, addrga, ToSext64, PS_loadriabs>;
-  def: Loadam_pat<zextloadi32, i64, addrga, ToZext64, PS_loadriabs>;
-}
-
-let AddedComplexity = 100 in {
-  def: Loada_pat<extloadi8,   i32, addrgp, PS_loadrubabs>;
-  def: Loada_pat<sextloadi8,  i32, addrgp, PS_loadrbabs>;
-  def: Loada_pat<zextloadi8,  i32, addrgp, PS_loadrubabs>;
-
-  def: Loada_pat<extloadi16,  i32, addrgp, PS_loadruhabs>;
-  def: Loada_pat<sextloadi16, i32, addrgp, PS_loadrhabs>;
-  def: Loada_pat<zextloadi16, i32, addrgp, PS_loadruhabs>;
-
-  def: Loada_pat<load,        i32, addrgp, PS_loadriabs>;
-  def: Loada_pat<load,        i64, addrgp, PS_loadrdabs>;
-}
-
-let AddedComplexity = 100 in {
-  def: Storea_pat<truncstorei8,  I32, addrgp, PS_storerbabs>;
-  def: Storea_pat<truncstorei16, I32, addrgp, PS_storerhabs>;
-  def: Storea_pat<store,         I32, addrgp, PS_storeriabs>;
-  def: Storea_pat<store,         I64, addrgp, PS_storerdabs>;
-}
-
-def: Loada_pat<atomic_load_8,  i32, addrgp, PS_loadrubabs>;
-def: Loada_pat<atomic_load_16, i32, addrgp, PS_loadruhabs>;
-def: Loada_pat<atomic_load_32, i32, addrgp, PS_loadriabs>;
-def: Loada_pat<atomic_load_64, i64, addrgp, PS_loadrdabs>;
-
-def: Storea_pat<SwapSt<atomic_store_8>,  I32, addrgp, PS_storerbabs>;
-def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, PS_storerhabs>;
-def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, PS_storeriabs>;
-def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, PS_storerdabs>;
-
-// Prefer this pattern to S2_asl_i_p_or for the special case of joining
-// two 32-bit words into a 64-bit word.
-let AddedComplexity = 200 in
-def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)),
-         (A2_combinew I32:$a, I32:$b)>;
+def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))),
+                                     (i32 (extloadi8  (add I32:$b, 3))),
+                                     24, 8),
+                      (i32 16)),
+                 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))),
+             (zextloadi8 I32:$b)),
+         (A2_swiz (L2_loadri_io I32:$b, 0))>;
 
-def: Pat<(or (or (or (shl (i64 (zext (and I32:$b, (i32 65535)))), (i32 16)),
-                     (i64 (zext (i32 (and I32:$a, (i32 65535)))))),
-                 (shl (i64 (anyext (and I32:$c, (i32 65535)))), (i32 32))),
-             (shl (Aext64 I32:$d), (i32 48))),
-         (A2_combinew (A2_combine_ll I32:$d, I32:$c),
-                      (A2_combine_ll I32:$b, I32:$a))>;
 
 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
 // We don't really want either one here.
-def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
-def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
-                            [SDNPHasChain]>;
+def SDTHexagonDCFETCH: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
+def HexagonDCFETCH: SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
+                           [SDNPHasChain]>;
 
 def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3),
          (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>;
 def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)),
          (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>;
 
-def f32ImmPred : PatLeaf<(f32 fpimm:$F)>;
-def f64ImmPred : PatLeaf<(f64 fpimm:$F)>;
-
-def ftoi : SDNodeXForm<fpimm, [{
-  APInt I = N->getValueAPF().bitcastToAPInt();
-  return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N),
-                                   MVT::getIntegerVT(I.getBitWidth()));
-}]>;
-
-
-def: Pat<(sra (i64 (add (sra I64:$src1, u6_0ImmPred:$src2), 1)), (i32 1)),
-         (S2_asr_i_p_rnd I64:$src1, imm:$src2)>;
-
-let AddedComplexity = 20 in {
-  defm: Loadx_pat<load, f32, s30_2ImmPred, L2_loadri_io>;
-  defm: Loadx_pat<load, f64, s29_3ImmPred, L2_loadrd_io>;
-}
-
-let AddedComplexity = 60 in {
-  defm : T_LoadAbsReg_Pat <load, L4_loadri_ur, f32>;
-  defm : T_LoadAbsReg_Pat <load, L4_loadrd_ur, f64>;
-}
-
-let AddedComplexity = 40 in {
-  def: Loadxs_pat<load, f32, L4_loadri_rr>;
-  def: Loadxs_pat<load, f64, L4_loadrd_rr>;
-}
-
-let AddedComplexity = 20 in {
-  def: Loadxs_simple_pat<load, f32, L4_loadri_rr>;
-  def: Loadxs_simple_pat<load, f64, L4_loadrd_rr>;
-}
-
-let AddedComplexity  = 80 in {
-  def: Loada_pat<load, f32, u32_0ImmPred, PS_loadriabs>;
-  def: Loada_pat<load, f32, addrga, PS_loadriabs>;
-  def: Loada_pat<load, f64, addrga, PS_loadrdabs>;
-}
-
-let AddedComplexity = 100 in {
-  def: LoadGP_pats <load, L2_loadrigp, f32>;
-  def: LoadGP_pats <load, L2_loadrdgp, f64>;
-}
-
-let AddedComplexity = 20 in {
-  defm: Storex_pat<store, F32, s30_2ImmPred, S2_storeri_io>;
-  defm: Storex_pat<store, F64, s29_3ImmPred, S2_storerd_io>;
-}
-
-// Simple patterns should be tried with the least priority.
-def: Storex_simple_pat<store, F32, S2_storeri_io>;
-def: Storex_simple_pat<store, F64, S2_storerd_io>;
-
-let AddedComplexity = 60 in {
-  defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, f32, store>;
-  defm : T_StoreAbsReg_Pats <S4_storerd_ur, DoubleRegs, f64, store>;
-}
-
-let AddedComplexity = 40 in {
-  def: Storexs_pat<store, F32, S4_storeri_rr>;
-  def: Storexs_pat<store, F64, S4_storerd_rr>;
-}
-
-let AddedComplexity = 20 in {
-  def: Store_rr_pat<store, F32, S4_storeri_rr>;
-  def: Store_rr_pat<store, F64, S4_storerd_rr>;
-}
-
-let AddedComplexity = 80 in {
-  def: Storea_pat<store, F32, addrga, PS_storeriabs>;
-  def: Storea_pat<store, F64, addrga, PS_storerdabs>;
-}
-
-let AddedComplexity = 100 in {
-  def: Storea_pat<store, F32, addrgp, S2_storerigp>;
-  def: Storea_pat<store, F64, addrgp, S2_storerdgp>;
-}
-
-defm: Storex_pat<store, F32, s30_2ImmPred, S2_storeri_io>;
-defm: Storex_pat<store, F64, s29_3ImmPred, S2_storerd_io>;
-def: Storex_simple_pat<store, F32, S2_storeri_io>;
-def: Storex_simple_pat<store, F64, S2_storerd_io>;
-
-def: Pat<(fadd F32:$src1, F32:$src2),
-         (F2_sfadd F32:$src1, F32:$src2)>;
-
-def: Pat<(fsub F32:$src1, F32:$src2),
-         (F2_sfsub F32:$src1, F32:$src2)>;
-
-def: Pat<(fmul F32:$src1, F32:$src2),
-         (F2_sfmpy F32:$src1, F32:$src2)>;
-
-let Predicates = [HasV5T] in {
-  def: Pat<(f32 (fminnum F32:$Rs, F32:$Rt)), (F2_sfmin F32:$Rs, F32:$Rt)>;
-  def: Pat<(f32 (fmaxnum F32:$Rs, F32:$Rt)), (F2_sfmax F32:$Rs, F32:$Rt)>;
-}
-
-let AddedComplexity = 100, Predicates = [HasV5T] in {
-  class SfSel12<PatFrag Cmp, InstHexagon MI>
-    : Pat<(select (i1 (Cmp F32:$Rs, F32:$Rt)), F32:$Rs, F32:$Rt),
-          (MI F32:$Rs, F32:$Rt)>;
-  class SfSel21<PatFrag Cmp, InstHexagon MI>
-    : Pat<(select (i1 (Cmp F32:$Rs, F32:$Rt)), F32:$Rt, F32:$Rs),
-          (MI F32:$Rs, F32:$Rt)>;
-
-  def: SfSel12<setolt, F2_sfmin>;
-  def: SfSel12<setole, F2_sfmin>;
-  def: SfSel12<setogt, F2_sfmax>;
-  def: SfSel12<setoge, F2_sfmax>;
-  def: SfSel21<setolt, F2_sfmax>;
-  def: SfSel21<setole, F2_sfmax>;
-  def: SfSel21<setogt, F2_sfmin>;
-  def: SfSel21<setoge, F2_sfmin>;
-}
-
-class T_fcmp32_pat<PatFrag OpNode, InstHexagon MI>
-  : Pat<(i1 (OpNode F32:$src1, F32:$src2)),
-        (MI F32:$src1, F32:$src2)>;
-class T_fcmp64_pat<PatFrag OpNode, InstHexagon MI>
-  : Pat<(i1 (OpNode F64:$src1, F64:$src2)),
-        (MI F64:$src1, F64:$src2)>;
-
-def: T_fcmp32_pat<setoge, F2_sfcmpge>;
-def: T_fcmp32_pat<setuo,  F2_sfcmpuo>;
-def: T_fcmp32_pat<setoeq, F2_sfcmpeq>;
-def: T_fcmp32_pat<setogt, F2_sfcmpgt>;
-
-def: T_fcmp64_pat<setoge, F2_dfcmpge>;
-def: T_fcmp64_pat<setuo,  F2_dfcmpuo>;
-def: T_fcmp64_pat<setoeq, F2_dfcmpeq>;
-def: T_fcmp64_pat<setogt, F2_dfcmpgt>;
-
-let Predicates = [HasV5T] in
-multiclass T_fcmp_pats<PatFrag cmpOp, InstHexagon IntMI, InstHexagon DoubleMI> {
-  // IntRegs
-  def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
-           (IntMI F32:$src1, F32:$src2)>;
-  // DoubleRegs
-  def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
-           (DoubleMI F64:$src1, F64:$src2)>;
-}
-
-defm : T_fcmp_pats <seteq, F2_sfcmpeq, F2_dfcmpeq>;
-defm : T_fcmp_pats <setgt, F2_sfcmpgt, F2_dfcmpgt>;
-defm : T_fcmp_pats <setge, F2_sfcmpge, F2_dfcmpge>;
-
-//===----------------------------------------------------------------------===//
-// Multiclass to define 'Def Pats' for unordered gt, ge, eq operations.
-//===----------------------------------------------------------------------===//
-let Predicates = [HasV5T] in
-multiclass unord_Pats <PatFrag cmpOp, InstHexagon IntMI, InstHexagon DoubleMI> {
-  // IntRegs
-  def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
-           (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
-                  (IntMI F32:$src1, F32:$src2))>;
-
-  // DoubleRegs
-  def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
-           (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
-                  (DoubleMI F64:$src1, F64:$src2))>;
-}
-
-defm : unord_Pats <setuge, F2_sfcmpge, F2_dfcmpge>;
-defm : unord_Pats <setugt, F2_sfcmpgt, F2_dfcmpgt>;
-defm : unord_Pats <setueq, F2_sfcmpeq, F2_dfcmpeq>;
-
-//===----------------------------------------------------------------------===//
-// Multiclass to define 'Def Pats' for the following dags:
-// seteq(setoeq(op1, op2), 0) -> not(setoeq(op1, op2))
-// seteq(setoeq(op1, op2), 1) -> setoeq(op1, op2)
-// setne(setoeq(op1, op2), 0) -> setoeq(op1, op2)
-// setne(setoeq(op1, op2), 1) -> not(setoeq(op1, op2))
-//===----------------------------------------------------------------------===//
-let Predicates = [HasV5T] in
-multiclass eq_ordgePats <PatFrag cmpOp, InstHexagon IntMI,
-                         InstHexagon DoubleMI> {
-  // IntRegs
-  def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
-           (C2_not (IntMI F32:$src1, F32:$src2))>;
-  def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
-           (IntMI F32:$src1, F32:$src2)>;
-  def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
-           (IntMI F32:$src1, F32:$src2)>;
-  def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
-           (C2_not (IntMI F32:$src1, F32:$src2))>;
-
-  // DoubleRegs
-  def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
-            (C2_not (DoubleMI F64:$src1, F64:$src2))>;
-  def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
-            (DoubleMI F64:$src1, F64:$src2)>;
-  def : Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
-            (DoubleMI F64:$src1, F64:$src2)>;
-  def : Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
-            (C2_not (DoubleMI F64:$src1, F64:$src2))>;
-}
-
-defm : eq_ordgePats<setoeq, F2_sfcmpeq, F2_dfcmpeq>;
-defm : eq_ordgePats<setoge, F2_sfcmpge, F2_dfcmpge>;
-defm : eq_ordgePats<setogt, F2_sfcmpgt, F2_dfcmpgt>;
-
-//===----------------------------------------------------------------------===//
-// Multiclass to define 'Def Pats' for the following dags:
-// seteq(setolt(op1, op2), 0) -> not(setogt(op2, op1))
-// seteq(setolt(op1, op2), 1) -> setogt(op2, op1)
-// setne(setolt(op1, op2), 0) -> setogt(op2, op1)
-// setne(setolt(op1, op2), 1) -> not(setogt(op2, op1))
-//===----------------------------------------------------------------------===//
-let Predicates = [HasV5T] in
-multiclass eq_ordltPats <PatFrag cmpOp, InstHexagon IntMI,
-                         InstHexagon DoubleMI> {
-  // IntRegs
-  def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
-           (C2_not (IntMI F32:$src2, F32:$src1))>;
-  def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
-           (IntMI F32:$src2, F32:$src1)>;
-  def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
-           (IntMI F32:$src2, F32:$src1)>;
-  def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
-           (C2_not (IntMI F32:$src2, F32:$src1))>;
-
-  // DoubleRegs
-  def: Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
-           (C2_not (DoubleMI F64:$src2, F64:$src1))>;
-  def: Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
-           (DoubleMI F64:$src2, F64:$src1)>;
-  def: Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
-           (DoubleMI F64:$src2, F64:$src1)>;
-  def: Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
-           (C2_not (DoubleMI F64:$src2, F64:$src1))>;
-}
-
-defm : eq_ordltPats<setole, F2_sfcmpge, F2_dfcmpge>;
-defm : eq_ordltPats<setolt, F2_sfcmpgt, F2_dfcmpgt>;
-
-
-// o. seto inverse of setuo. http://llvm.org/docs/LangRef.html#i_fcmp
-let Predicates = [HasV5T] in {
-  def: Pat<(i1 (seto F32:$src1, F32:$src2)),
-           (C2_not (F2_sfcmpuo F32:$src2, F32:$src1))>;
-  def: Pat<(i1 (seto F32:$src1, f32ImmPred:$src2)),
-           (C2_not (F2_sfcmpuo (f32 (A2_tfrsi (ftoi $src2))), F32:$src1))>;
-  def: Pat<(i1 (seto F64:$src1, F64:$src2)),
-           (C2_not (F2_dfcmpuo F64:$src2, F64:$src1))>;
-  def: Pat<(i1 (seto F64:$src1, f64ImmPred:$src2)),
-           (C2_not (F2_dfcmpuo (CONST64 (ftoi $src2)), F64:$src1))>;
-}
-
-// Ordered lt.
-let Predicates = [HasV5T] in {
-  def: Pat<(i1 (setolt F32:$src1, F32:$src2)),
-           (F2_sfcmpgt F32:$src2, F32:$src1)>;
-  def: Pat<(i1 (setolt F32:$src1, f32ImmPred:$src2)),
-           (F2_sfcmpgt (f32 (A2_tfrsi (ftoi $src2))), F32:$src1)>;
-  def: Pat<(i1 (setolt F64:$src1, F64:$src2)),
-           (F2_dfcmpgt F64:$src2, F64:$src1)>;
-  def: Pat<(i1 (setolt F64:$src1, f64ImmPred:$src2)),
-           (F2_dfcmpgt (CONST64 (ftoi $src2)), F64:$src1)>;
-}
-
-// Unordered lt.
-let Predicates = [HasV5T] in {
-  def: Pat<(i1 (setult F32:$src1, F32:$src2)),
-           (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
-                  (F2_sfcmpgt F32:$src2, F32:$src1))>;
-  def: Pat<(i1 (setult F32:$src1, f32ImmPred:$src2)),
-           (C2_or (F2_sfcmpuo F32:$src1, (f32 (A2_tfrsi (ftoi $src2)))),
-                  (F2_sfcmpgt (f32 (A2_tfrsi (ftoi $src2))), F32:$src1))>;
-  def: Pat<(i1 (setult F64:$src1, F64:$src2)),
-           (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
-                  (F2_dfcmpgt F64:$src2, F64:$src1))>;
-  def: Pat<(i1 (setult F64:$src1, f64ImmPred:$src2)),
-           (C2_or (F2_dfcmpuo F64:$src1, (CONST64 (ftoi $src2))),
-                  (F2_dfcmpgt (CONST64 (ftoi $src2)), F64:$src1))>;
-}
-
-// Ordered le.
-let Predicates = [HasV5T] in {
-  // rs <= rt -> rt >= rs.
-  def: Pat<(i1 (setole F32:$src1, F32:$src2)),
-           (F2_sfcmpge F32:$src2, F32:$src1)>;
-  def: Pat<(i1 (setole F32:$src1, f32ImmPred:$src2)),
-           (F2_sfcmpge (f32 (A2_tfrsi (ftoi $src2))), F32:$src1)>;
-
-  // Rss <= Rtt -> Rtt >= Rss.
-  def: Pat<(i1 (setole F64:$src1, F64:$src2)),
-           (F2_dfcmpge F64:$src2, F64:$src1)>;
-  def: Pat<(i1 (setole F64:$src1, f64ImmPred:$src2)),
-           (F2_dfcmpge (CONST64 (ftoi $src2)), F64:$src1)>;
-}
-
-// Unordered le.
-let Predicates = [HasV5T] in {
-// rs <= rt -> rt >= rs.
-  def: Pat<(i1 (setule F32:$src1, F32:$src2)),
-           (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
-                  (F2_sfcmpge F32:$src2, F32:$src1))>;
-  def: Pat<(i1 (setule F32:$src1, f32ImmPred:$src2)),
-           (C2_or (F2_sfcmpuo F32:$src1, (f32 (A2_tfrsi (ftoi $src2)))),
-                  (F2_sfcmpge (f32 (A2_tfrsi (ftoi $src2))), F32:$src1))>;
-  def: Pat<(i1 (setule F64:$src1, F64:$src2)),
-           (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
-                  (F2_dfcmpge F64:$src2, F64:$src1))>;
-  def: Pat<(i1 (setule F64:$src1, f64ImmPred:$src2)),
-           (C2_or (F2_dfcmpuo F64:$src1, (CONST64 (ftoi $src2))),
-                  (F2_dfcmpge (CONST64 (ftoi $src2)), F64:$src1))>;
-}
-
-// Ordered ne.
-let Predicates = [HasV5T] in {
-  def: Pat<(i1 (setone F32:$src1, F32:$src2)),
-           (C2_not (F2_sfcmpeq F32:$src1, F32:$src2))>;
-  def: Pat<(i1 (setone F64:$src1, F64:$src2)),
-           (C2_not (F2_dfcmpeq F64:$src1, F64:$src2))>;
-  def: Pat<(i1 (setone F32:$src1, f32ImmPred:$src2)),
-           (C2_not (F2_sfcmpeq F32:$src1, (f32 (A2_tfrsi (ftoi $src2)))))>;
-  def: Pat<(i1 (setone F64:$src1, f64ImmPred:$src2)),
-           (C2_not (F2_dfcmpeq F64:$src1, (CONST64 (ftoi $src2))))>;
-}
-
-// Unordered ne.
-let Predicates = [HasV5T] in {
-  def: Pat<(i1 (setune F32:$src1, F32:$src2)),
-           (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
-                  (C2_not (F2_sfcmpeq F32:$src1, F32:$src2)))>;
-  def: Pat<(i1 (setune F64:$src1, F64:$src2)),
-           (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
-                  (C2_not (F2_dfcmpeq F64:$src1, F64:$src2)))>;
-  def: Pat<(i1 (setune F32:$src1, f32ImmPred:$src2)),
-           (C2_or (F2_sfcmpuo F32:$src1, (f32 (A2_tfrsi (ftoi $src2)))),
-                  (C2_not (F2_sfcmpeq F32:$src1,
-                                      (f32 (A2_tfrsi (ftoi $src2))))))>;
-  def: Pat<(i1 (setune F64:$src1, f64ImmPred:$src2)),
-           (C2_or (F2_dfcmpuo F64:$src1, (CONST64 (ftoi $src2))),
-                  (C2_not (F2_dfcmpeq F64:$src1,
-                                      (CONST64 (ftoi $src2)))))>;
-}
-
-// Besides set[o|u][comparions], we also need set[comparisons].
-let Predicates = [HasV5T] in {
-  // lt.
-  def: Pat<(i1 (setlt F32:$src1, F32:$src2)),
-           (F2_sfcmpgt F32:$src2, F32:$src1)>;
-  def: Pat<(i1 (setlt F32:$src1, f32ImmPred:$src2)),
-           (F2_sfcmpgt (f32 (A2_tfrsi (ftoi $src2))), F32:$src1)>;
-  def: Pat<(i1 (setlt F64:$src1, F64:$src2)),
-           (F2_dfcmpgt F64:$src2, F64:$src1)>;
-  def: Pat<(i1 (setlt F64:$src1, f64ImmPred:$src2)),
-           (F2_dfcmpgt (CONST64 (ftoi $src2)), F64:$src1)>;
-
-  // le.
-  // rs <= rt -> rt >= rs.
-  def: Pat<(i1 (setle F32:$src1, F32:$src2)),
-           (F2_sfcmpge F32:$src2, F32:$src1)>;
-  def: Pat<(i1 (setle F32:$src1, f32ImmPred:$src2)),
-           (F2_sfcmpge (f32 (A2_tfrsi (ftoi $src2))), F32:$src1)>;
-
-  // Rss <= Rtt -> Rtt >= Rss.
-  def: Pat<(i1 (setle F64:$src1, F64:$src2)),
-           (F2_dfcmpge F64:$src2, F64:$src1)>;
-  def: Pat<(i1 (setle F64:$src1, f64ImmPred:$src2)),
-           (F2_dfcmpge (CONST64 (ftoi $src2)), F64:$src1)>;
-
-  // ne.
-  def: Pat<(i1 (setne F32:$src1, F32:$src2)),
-           (C2_not (F2_sfcmpeq F32:$src1, F32:$src2))>;
-  def: Pat<(i1 (setne F64:$src1, F64:$src2)),
-           (C2_not (F2_dfcmpeq F64:$src1, F64:$src2))>;
-  def: Pat<(i1 (setne F32:$src1, f32ImmPred:$src2)),
-           (C2_not (F2_sfcmpeq F32:$src1, (f32 (A2_tfrsi (ftoi $src2)))))>;
-  def: Pat<(i1 (setne F64:$src1, f64ImmPred:$src2)),
-           (C2_not (F2_dfcmpeq F64:$src1, (CONST64 (ftoi $src2))))>;
-}
-
-
-def: Pat<(f64 (fpextend F32:$Rs)), (F2_conv_sf2df F32:$Rs)>;
-def: Pat<(f32 (fpround F64:$Rs)), (F2_conv_df2sf F64:$Rs)>;
-
-def: Pat<(f32 (sint_to_fp I32:$Rs)), (F2_conv_w2sf I32:$Rs)>;
-def: Pat<(f32 (sint_to_fp I64:$Rs)), (F2_conv_d2sf I64:$Rs)>;
-def: Pat<(f64 (sint_to_fp I32:$Rs)), (F2_conv_w2df I32:$Rs)>;
-def: Pat<(f64 (sint_to_fp I64:$Rs)), (F2_conv_d2df I64:$Rs)>;
-
-def: Pat<(f32 (uint_to_fp I32:$Rs)), (F2_conv_uw2sf I32:$Rs)>;
-def: Pat<(f32 (uint_to_fp I64:$Rs)), (F2_conv_ud2sf I64:$Rs)>;
-def: Pat<(f64 (uint_to_fp I32:$Rs)), (F2_conv_uw2df I32:$Rs)>;
-def: Pat<(f64 (uint_to_fp I64:$Rs)), (F2_conv_ud2df I64:$Rs)>;
-
-def: Pat<(i32 (fp_to_sint F32:$Rs)), (F2_conv_sf2w_chop F32:$Rs)>;
-def: Pat<(i32 (fp_to_sint F64:$Rs)), (F2_conv_df2w_chop F64:$Rs)>;
-def: Pat<(i64 (fp_to_sint F32:$Rs)), (F2_conv_sf2d_chop F32:$Rs)>;
-def: Pat<(i64 (fp_to_sint F64:$Rs)), (F2_conv_df2d_chop F64:$Rs)>;
-
-def: Pat<(i32 (fp_to_uint F32:$Rs)), (F2_conv_sf2uw_chop F32:$Rs)>;
-def: Pat<(i32 (fp_to_uint F64:$Rs)), (F2_conv_df2uw_chop F64:$Rs)>;
-def: Pat<(i64 (fp_to_uint F32:$Rs)), (F2_conv_sf2ud_chop F32:$Rs)>;
-def: Pat<(i64 (fp_to_uint F64:$Rs)), (F2_conv_df2ud_chop F64:$Rs)>;
-
-// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
-let Predicates = [HasV5T] in {
-  def: Pat <(i32 (bitconvert F32:$src)), (I32:$src)>;
-  def: Pat <(f32 (bitconvert I32:$src)), (F32:$src)>;
-  def: Pat <(i64 (bitconvert F64:$src)), (I64:$src)>;
-  def: Pat <(f64 (bitconvert I64:$src)), (F64:$src)>;
-}
-
-def : Pat <(fma F32:$src2, F32:$src3, F32:$src1),
-           (F2_sffma F32:$src1, F32:$src2, F32:$src3)>;
-
-def : Pat <(fma (fneg F32:$src2), F32:$src3, F32:$src1),
-           (F2_sffms F32:$src1, F32:$src2, F32:$src3)>;
-
-def : Pat <(fma F32:$src2, (fneg F32:$src3), F32:$src1),
-           (F2_sffms F32:$src1, F32:$src2, F32:$src3)>;
-
-def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$imm),
-         (C2_muxir I1:$Pu, F32:$Rs, (ftoi $imm))>,
-    Requires<[HasV5T]>;
-
-def: Pat<(select I1:$Pu, f32ImmPred:$imm, F32:$Rt),
-         (C2_muxri I1:$Pu, (ftoi $imm), F32:$Rt)>,
-    Requires<[HasV5T]>;
-
-def: Pat<(select I1:$src1, F32:$src2, F32:$src3),
-         (C2_mux I1:$src1, F32:$src2, F32:$src3)>,
-     Requires<[HasV5T]>;
-
-def: Pat<(select (i1 (setult F32:$src1, F32:$src2)), F32:$src3, F32:$src4),
-         (C2_mux (F2_sfcmpgt F32:$src2, F32:$src1), F32:$src4, F32:$src3)>,
-     Requires<[HasV5T]>;
-
-def: Pat<(select I1:$src1, F64:$src2, F64:$src3),
-         (C2_vmux I1:$src1, F64:$src2, F64:$src3)>,
-    Requires<[HasV5T]>;
+def SDTHexagonALLOCA
+  : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
+def HexagonALLOCA
+  : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>;
 
-def: Pat<(select (i1 (setult F64:$src1, F64:$src2)), F64:$src3, F64:$src4),
-         (C2_vmux (F2_dfcmpgt F64:$src2, F64:$src1), F64:$src3, F64:$src4)>,
-     Requires<[HasV5T]>;
-
-// Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
-// => r0 = mux(p0, #i, r1)
-def: Pat<(select (not I1:$src1), f32ImmPred:$src2, F32:$src3),
-         (C2_muxir I1:$src1, F32:$src3, (ftoi $src2))>,
-     Requires<[HasV5T]>;
-
-// Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
-// => r0 = mux(p0, r1, #i)
-def: Pat<(select (not I1:$src1), F32:$src2, f32ImmPred:$src3),
-         (C2_muxri I1:$src1, (ftoi $src3), F32:$src2)>,
-     Requires<[HasV5T]>;
-
-def: Pat<(i32 (fp_to_sint F64:$src1)),
-         (LoReg (F2_conv_df2d_chop F64:$src1))>,
-     Requires<[HasV5T]>;
-
-def : Pat <(fabs F32:$src1),
-           (S2_clrbit_i F32:$src1, 31)>,
-          Requires<[HasV5T]>;
-
-def : Pat <(fneg F32:$src1),
-           (S2_togglebit_i F32:$src1, 31)>,
-          Requires<[HasV5T]>;
-
-def: Pat<(fabs F64:$Rs),
-         (REG_SEQUENCE DoubleRegs,
-              (S2_clrbit_i (HiReg $Rs), 31), isub_hi,
-              (i32 (LoReg $Rs)), isub_lo)>;
-
-def: Pat<(fneg F64:$Rs),
-         (REG_SEQUENCE DoubleRegs,
-              (S2_togglebit_i (HiReg $Rs), 31), isub_hi,
-              (i32 (LoReg $Rs)), isub_lo)>;
-
-def: Pat<(mul I64:$Rss, I64:$Rtt),
-         (A2_combinew
-           (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))),
-                             (LoReg $Rss),
-                             (HiReg $Rtt)),
-                    (LoReg $Rtt),
-                    (HiReg $Rss)),
-           (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))))>;
-
-def alignedload : PatFrag<(ops node:$addr), (load $addr), [{
-  return isAlignedMemNode(dyn_cast<MemSDNode>(N));
-}]>;
-
-def unalignedload : PatFrag<(ops node:$addr), (load $addr), [{
-  return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
-}]>;
-
-def alignedstore : PatFrag<(ops node:$val, node:$addr), (store $val, $addr), [{
-  return isAlignedMemNode(dyn_cast<MemSDNode>(N));
-}]>;
-
-def unalignedstore : PatFrag<(ops node:$val, node:$addr), (store $val, $addr), [{
-  return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
-}]>;
-
-
-multiclass vS32b_ai_pats <ValueType VTSgl, ValueType VTDbl> {
-  // Aligned stores
-  def : Pat<(alignednontemporalstore (VTSgl VectorRegs:$src1), IntRegs:$addr),
-            (V6_vS32b_nt_ai IntRegs:$addr, 0, (VTSgl VectorRegs:$src1))>,
-            Requires<[UseHVXSgl]>;
-  def : Pat<(alignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr),
-            (V6_vS32b_ai IntRegs:$addr, 0, (VTSgl VectorRegs:$src1))>,
-            Requires<[UseHVXSgl]>;
-  def : Pat<(unalignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr),
-            (V6_vS32Ub_ai IntRegs:$addr, 0, (VTSgl VectorRegs:$src1))>,
-            Requires<[UseHVXSgl]>;
-
-  // 128B Aligned stores
-  def : Pat<(alignednontemporalstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr),
-            (V6_vS32b_nt_ai_128B IntRegs:$addr, 0, (VTDbl VectorRegs128B:$src1))>,
-            Requires<[UseHVXDbl]>;
-  def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr),
-            (V6_vS32b_ai_128B IntRegs:$addr, 0, (VTDbl VectorRegs128B:$src1))>,
-            Requires<[UseHVXDbl]>;
-  def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr),
-            (V6_vS32Ub_ai_128B IntRegs:$addr, 0, (VTDbl VectorRegs128B:$src1))>,
-            Requires<[UseHVXDbl]>;
-
-  // Fold Add R+OFF into vector store.
-  let AddedComplexity = 10 in {
-    def : Pat<(alignednontemporalstore (VTSgl VectorRegs:$src1),
-                     (add IntRegs:$src2, Iss4_6:$offset)),
-              (V6_vS32b_nt_ai IntRegs:$src2, Iss4_6:$offset,
-                           (VTSgl VectorRegs:$src1))>,
-              Requires<[UseHVXSgl]>;
-    def : Pat<(alignedstore (VTSgl VectorRegs:$src1),
-                     (add IntRegs:$src2, Iss4_6:$offset)),
-              (V6_vS32b_ai IntRegs:$src2, Iss4_6:$offset,
-                           (VTSgl VectorRegs:$src1))>,
-              Requires<[UseHVXSgl]>;
-    def : Pat<(unalignedstore (VTSgl VectorRegs:$src1),
-                     (add IntRegs:$src2, Iss4_6:$offset)),
-              (V6_vS32Ub_ai IntRegs:$src2, Iss4_6:$offset,
-                           (VTSgl VectorRegs:$src1))>,
-              Requires<[UseHVXSgl]>;
-
-    // Fold Add R+OFF into vector store 128B.
-    def : Pat<(alignednontemporalstore (VTDbl VectorRegs128B:$src1),
-                     (add IntRegs:$src2, Iss4_7:$offset)),
-              (V6_vS32b_nt_ai_128B IntRegs:$src2, Iss4_7:$offset,
-                                (VTDbl VectorRegs128B:$src1))>,
-              Requires<[UseHVXDbl]>;
-    def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1),
-                     (add IntRegs:$src2, Iss4_7:$offset)),
-              (V6_vS32b_ai_128B IntRegs:$src2, Iss4_7:$offset,
-                                (VTDbl VectorRegs128B:$src1))>,
-              Requires<[UseHVXDbl]>;
-    def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1),
-                     (add IntRegs:$src2, Iss4_7:$offset)),
-              (V6_vS32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset,
-                                (VTDbl VectorRegs128B:$src1))>,
-              Requires<[UseHVXDbl]>;
-  }
-}
-
-defm : vS32b_ai_pats <v64i8,  v128i8>;
-defm : vS32b_ai_pats <v32i16, v64i16>;
-defm : vS32b_ai_pats <v16i32, v32i32>;
-defm : vS32b_ai_pats <v8i64,  v16i64>;
-
-
-multiclass vL32b_ai_pats <ValueType VTSgl, ValueType VTDbl> {
-  // Aligned loads
-  def : Pat < (VTSgl (alignednontemporalload IntRegs:$addr)),
-              (V6_vL32b_nt_ai IntRegs:$addr, 0) >,
-              Requires<[UseHVXSgl]>;
-  def : Pat < (VTSgl (alignedload IntRegs:$addr)),
-              (V6_vL32b_ai IntRegs:$addr, 0) >,
-              Requires<[UseHVXSgl]>;
-  def : Pat < (VTSgl (unalignedload IntRegs:$addr)),
-              (V6_vL32Ub_ai IntRegs:$addr, 0) >,
-              Requires<[UseHVXSgl]>;
-
-  // 128B Load
-  def : Pat < (VTDbl (alignednontemporalload IntRegs:$addr)),
-              (V6_vL32b_nt_ai_128B IntRegs:$addr, 0) >,
-              Requires<[UseHVXDbl]>;
-  def : Pat < (VTDbl (alignedload IntRegs:$addr)),
-              (V6_vL32b_ai_128B IntRegs:$addr, 0) >,
-              Requires<[UseHVXDbl]>;
-  def : Pat < (VTDbl (unalignedload IntRegs:$addr)),
-              (V6_vL32Ub_ai_128B IntRegs:$addr, 0) >,
-              Requires<[UseHVXDbl]>;
-
-  // Fold Add R+OFF into vector load.
-  let AddedComplexity = 10 in {
-    def : Pat<(VTDbl (alignednontemporalload (add IntRegs:$src2, Iss4_7:$offset))),
-              (V6_vL32b_nt_ai_128B IntRegs:$src2, Iss4_7:$offset)>,
-               Requires<[UseHVXDbl]>;
-    def : Pat<(VTDbl (alignedload (add IntRegs:$src2, Iss4_7:$offset))),
-              (V6_vL32b_ai_128B IntRegs:$src2, Iss4_7:$offset)>,
-               Requires<[UseHVXDbl]>;
-    def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, Iss4_7:$offset))),
-              (V6_vL32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset)>,
-               Requires<[UseHVXDbl]>;
+def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)),
+         (PS_alloca IntRegs:$Rs, imm:$A)>;
 
-    def : Pat<(VTSgl (alignednontemporalload (add IntRegs:$src2, Iss4_6:$offset))),
-              (V6_vL32b_nt_ai IntRegs:$src2, Iss4_6:$offset)>,
-              Requires<[UseHVXSgl]>;
-    def : Pat<(VTSgl (alignedload (add IntRegs:$src2, Iss4_6:$offset))),
-              (V6_vL32b_ai IntRegs:$src2, Iss4_6:$offset)>,
-              Requires<[UseHVXSgl]>;
-    def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, Iss4_6:$offset))),
-              (V6_vL32Ub_ai IntRegs:$src2, Iss4_6:$offset)>,
-              Requires<[UseHVXSgl]>;
-  }
-}
+def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
+def: Pat<(HexagonBARRIER), (Y2_barrier)>;
 
-defm : vL32b_ai_pats <v64i8,  v128i8>;
-defm : vL32b_ai_pats <v32i16, v64i16>;
-defm : vL32b_ai_pats <v16i32, v32i32>;
-defm : vL32b_ai_pats <v8i64,  v16i64>;
+// Read cycle counter.
+def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
+def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf,
+  [SDNPHasChain]>;
 
-multiclass STrivv_pats <ValueType VTSgl, ValueType VTDbl> {
-  def : Pat<(alignednontemporalstore (VTSgl VecDblRegs:$src1), IntRegs:$addr),
-            (PS_vstorerw_nt_ai IntRegs:$addr, 0, (VTSgl VecDblRegs:$src1))>,
-           Requires<[UseHVXSgl]>;
-  def : Pat<(alignedstore (VTSgl VecDblRegs:$src1), IntRegs:$addr),
-            (PS_vstorerw_ai IntRegs:$addr, 0, (VTSgl VecDblRegs:$src1))>,
-           Requires<[UseHVXSgl]>;
-  def : Pat<(unalignedstore (VTSgl VecDblRegs:$src1), IntRegs:$addr),
-            (PS_vstorerwu_ai IntRegs:$addr, 0, (VTSgl VecDblRegs:$src1))>,
-           Requires<[UseHVXSgl]>;
+def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>;
 
-  def : Pat<(alignednontemporalstore (VTDbl VecDblRegs128B:$src1), IntRegs:$addr),
-            (PS_vstorerw_nt_ai_128B IntRegs:$addr, 0,
-                  (VTDbl VecDblRegs128B:$src1))>,
-            Requires<[UseHVXDbl]>;
-  def : Pat<(alignedstore (VTDbl VecDblRegs128B:$src1), IntRegs:$addr),
-            (PS_vstorerw_ai_128B IntRegs:$addr, 0,
-                  (VTDbl VecDblRegs128B:$src1))>,
-            Requires<[UseHVXDbl]>;
-  def : Pat<(unalignedstore (VTDbl VecDblRegs128B:$src1), IntRegs:$addr),
-            (PS_vstorerwu_ai_128B IntRegs:$addr, 0,
-                  (VTDbl VecDblRegs128B:$src1))>,
-            Requires<[UseHVXDbl]>;
-}
 
-defm : STrivv_pats <v128i8, v256i8>;
-defm : STrivv_pats <v64i16, v128i16>;
-defm : STrivv_pats <v32i32, v64i32>;
-defm : STrivv_pats <v16i64, v32i64>;
+def SDTHexagonVEXTRACTW: SDTypeProfile<1, 2,
+  [SDTCisVT<0, i32>, SDTCisVec<1>, SDTCisVT<2, i32>]>;
+def HexagonVEXTRACTW : SDNode<"HexagonISD::VEXTRACTW", SDTHexagonVEXTRACTW>;
 
-multiclass LDrivv_pats <ValueType VTSgl, ValueType VTDbl> {
-  def : Pat<(VTSgl (alignednontemporalload I32:$addr)),
-            (PS_vloadrw_nt_ai I32:$addr, 0)>,
-           Requires<[UseHVXSgl]>;
-  def : Pat<(VTSgl (alignedload I32:$addr)),
-            (PS_vloadrw_ai I32:$addr, 0)>,
-           Requires<[UseHVXSgl]>;
-  def : Pat<(VTSgl (unalignedload I32:$addr)),
-            (PS_vloadrwu_ai I32:$addr, 0)>,
-           Requires<[UseHVXSgl]>;
+def SDTHexagonVINSERTW0: SDTypeProfile<1, 2,
+  [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;
+def HexagonVINSERTW0 : SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>;
 
-  def : Pat<(VTDbl (alignednontemporalload I32:$addr)),
-            (PS_vloadrw_nt_ai_128B I32:$addr, 0)>,
-           Requires<[UseHVXDbl]>;
-  def : Pat<(VTDbl (alignedload I32:$addr)),
-            (PS_vloadrw_ai_128B I32:$addr, 0)>,
-           Requires<[UseHVXDbl]>;
-  def : Pat<(VTDbl (unalignedload I32:$addr)),
-            (PS_vloadrwu_ai_128B I32:$addr, 0)>,
-           Requires<[UseHVXDbl]>;
-}
+def Combinev: OutPatFrag<(ops node:$Rs, node:$Rt),
+  (REG_SEQUENCE HvxWR, $Rs, vsub_hi, $Rt, vsub_lo)>;
 
-defm : LDrivv_pats <v128i8, v256i8>;
-defm : LDrivv_pats <v64i16, v128i16>;
-defm : LDrivv_pats <v32i32, v64i32>;
-defm : LDrivv_pats <v16i64, v32i64>;
+def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;
+def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;
 
-let Predicates = [HasV60T,UseHVXSgl] in {
-  def: Pat<(select I1:$Pu, (v16i32 VectorRegs:$Vs), VectorRegs:$Vt),
-           (PS_vselect I1:$Pu, VectorRegs:$Vs, VectorRegs:$Vt)>;
-  def: Pat<(select I1:$Pu, (v32i32 VecDblRegs:$Vs), VecDblRegs:$Vt),
-           (PS_wselect I1:$Pu, VecDblRegs:$Vs, VecDblRegs:$Vt)>;
-}
-let Predicates = [HasV60T,UseHVXDbl] in {
-  def: Pat<(select I1:$Pu, (v32i32 VectorRegs128B:$Vs), VectorRegs128B:$Vt),
-           (PS_vselect_128B I1:$Pu, VectorRegs128B:$Vs, VectorRegs128B:$Vt)>;
-  def: Pat<(select I1:$Pu, (v64i32 VecDblRegs128B:$Vs), VecDblRegs128B:$Vt),
-           (PS_wselect_128B I1:$Pu, VecDblRegs128B:$Vs, VecDblRegs128B:$Vt)>;
+let Predicates = [UseHVX] in {
+  def: OpR_RR_pat<V6_vpackeb,  pf2<HexagonVPACKE>,     VecI8,  HVI8>;
+  def: OpR_RR_pat<V6_vpackob,  pf2<HexagonVPACKO>,     VecI8,  HVI8>;
+  def: OpR_RR_pat<V6_vpackeh,  pf2<HexagonVPACKE>,    VecI16, HVI16>;
+  def: OpR_RR_pat<V6_vpackoh,  pf2<HexagonVPACKO>,    VecI16, HVI16>;
 }
 
+let Predicates = [UseHVX] in {
+  def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
+           (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
+  def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)),
+           (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
+  def: Pat<(VecPI32 (concat_vectors HVI32:$Vs, HVI32:$Vt)),
+           (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
 
-def SDTHexagonVCOMBINE: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>,
-      SDTCisSubVecOfVec<1, 0>]>;
+  def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
+           (V6_extractw HvxVR:$Vu, I32:$Rs)>;
+  def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
+           (V6_extractw HvxVR:$Vu, I32:$Rs)>;
+  def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
+           (V6_extractw HvxVR:$Vu, I32:$Rs)>;
 
-def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>;
+  def: Pat<(HexagonVINSERTW0 HVI8:$Vu,  I32:$Rt),
+           (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
+  def: Pat<(HexagonVINSERTW0 HVI16:$Vu, I32:$Rt),
+           (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
+  def: Pat<(HexagonVINSERTW0 HVI32:$Vu, I32:$Rt),
+           (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
 
-def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs),
-                                  (v16i32 VectorRegs:$Vt))),
-         (V6_vcombine VectorRegs:$Vs, VectorRegs:$Vt)>,
-         Requires<[UseHVXSgl]>;
-def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs),
-                                  (v32i32 VecDblRegs:$Vt))),
-         (V6_vcombine_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>,
-         Requires<[UseHVXDbl]>;
+  def: Pat<(add HVI8:$Vs,  HVI8:$Vt),   (V6_vaddb HvxVR:$Vs, HvxVR:$Vt)>;
+  def: Pat<(add HVI16:$Vs, HVI16:$Vt),  (V6_vaddh HvxVR:$Vs, HvxVR:$Vt)>;
+  def: Pat<(add HVI32:$Vs, HVI32:$Vt),  (V6_vaddw HvxVR:$Vs, HvxVR:$Vt)>;
 
-def SDTHexagonVPACK: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, SDTCisVec<1>]>;
+  def: Pat<(sub HVI8:$Vs,  HVI8:$Vt),   (V6_vsubb HvxVR:$Vs, HvxVR:$Vt)>;
+  def: Pat<(sub HVI16:$Vs, HVI16:$Vt),  (V6_vsubh HvxVR:$Vs, HvxVR:$Vt)>;
+  def: Pat<(sub HVI32:$Vs, HVI32:$Vt),  (V6_vsubw HvxVR:$Vs, HvxVR:$Vt)>;
 
-def HexagonVPACKE: SDNode<"HexagonISD::VPACKE", SDTHexagonVPACK>;
-def HexagonVPACKO: SDNode<"HexagonISD::VPACKO", SDTHexagonVPACK>;
+  def: Pat<(and HVI8:$Vs,  HVI8:$Vt),   (V6_vand  HvxVR:$Vs, HvxVR:$Vt)>;
+  def: Pat<(or  HVI8:$Vs,  HVI8:$Vt),   (V6_vor   HvxVR:$Vs, HvxVR:$Vt)>;
+  def: Pat<(xor HVI8:$Vs,  HVI8:$Vt),   (V6_vxor  HvxVR:$Vs, HvxVR:$Vt)>;
 
-let Predicates = [UseHVXSgl] in {
-  def: Pat<(v64i8 (HexagonVPACKE (v64i8 VectorRegs:$Vs),
-                                 (v64i8 VectorRegs:$Vt))),
-           (V6_vpackeb VectorRegs:$Vs, VectorRegs:$Vt)>;
-  def: Pat<(v64i8 (HexagonVPACKO (v64i8 VectorRegs:$Vs),
-                                 (v64i8 VectorRegs:$Vt))),
-           (V6_vpackob VectorRegs:$Vs, VectorRegs:$Vt)>;
-  def: Pat<(v32i16 (HexagonVPACKE (v32i16 VectorRegs:$Vs),
-                                  (v32i16 VectorRegs:$Vt))),
-           (V6_vpackeh VectorRegs:$Vs, VectorRegs:$Vt)>;
-  def: Pat<(v32i16 (HexagonVPACKO (v32i16 VectorRegs:$Vs),
-                                  (v32i16 VectorRegs:$Vt))),
-           (V6_vpackoh VectorRegs:$Vs, VectorRegs:$Vt)>;
-}
+  def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
+           (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
+  def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt),
+           (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
+  def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),
+           (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
 
-let Predicates = [UseHVXDbl] in {
-  def: Pat<(v128i8 (HexagonVPACKE (v128i8 VecDblRegs:$Vs),
-                                  (v128i8 VecDblRegs:$Vt))),
-           (V6_vpackeb_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>;
-  def: Pat<(v128i8 (HexagonVPACKO (v128i8 VecDblRegs:$Vs),
-                                  (v128i8 VecDblRegs:$Vt))),
-           (V6_vpackob_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>;
-  def: Pat<(v64i16 (HexagonVPACKE (v64i16 VecDblRegs:$Vs),
-                                  (v64i16 VecDblRegs:$Vt))),
-           (V6_vpackeh_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>;
-  def: Pat<(v64i16 (HexagonVPACKO (v64i16 VecDblRegs:$Vs),
-                                  (v64i16 VecDblRegs:$Vt))),
-          (V6_vpackoh_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>;
-}
-
-def V2I1:  PatLeaf<(v2i1  PredRegs:$R)>;
-def V4I1:  PatLeaf<(v4i1  PredRegs:$R)>;
-def V8I1:  PatLeaf<(v8i1  PredRegs:$R)>;
-def V4I8:  PatLeaf<(v4i8  IntRegs:$R)>;
-def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
-def V8I8:  PatLeaf<(v8i8  DoubleRegs:$R)>;
-def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>;
-def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>;
+  def: Pat<(VecPI16 (sext HVI8:$Vs)),  (V6_vsb HvxVR:$Vs)>;
+  def: Pat<(VecPI32 (sext HVI16:$Vs)), (V6_vsh HvxVR:$Vs)>;
+  def: Pat<(VecPI16 (zext HVI8:$Vs)),  (V6_vzb HvxVR:$Vs)>;
+  def: Pat<(VecPI32 (zext HVI16:$Vs)), (V6_vzh HvxVR:$Vs)>;
 
+  def: Pat<(sext_inreg HVI32:$Vs, v16i16),
+           (V6_vpackeb (LoVec (V6_vsh HvxVR:$Vs)),
+                       (HiVec (V6_vsh HvxVR:$Vs)))>;
+  def: Pat<(sext_inreg HVI32:$Vs, v32i16),
+           (V6_vpackeb (LoVec (V6_vsh HvxVR:$Vs)),
+                       (HiVec (V6_vsh HvxVR:$Vs)))>;
 
-multiclass bitconvert_32<ValueType a, ValueType b> {
-  def : Pat <(b (bitconvert (a IntRegs:$src))),
-             (b IntRegs:$src)>;
-  def : Pat <(a (bitconvert (b IntRegs:$src))),
-             (a IntRegs:$src)>;
-}
+  def: Pat<(VecI16 (sext_invec HVI8:$Vs)),  (LoVec (V6_vsb HvxVR:$Vs))>;
+  def: Pat<(VecI32 (sext_invec HVI16:$Vs)), (LoVec (V6_vsh HvxVR:$Vs))>;
+  def: Pat<(VecI32 (sext_invec HVI8:$Vs)),
+           (LoVec (V6_vsh (LoVec (V6_vsb HvxVR:$Vs))))>;
 
-multiclass bitconvert_64<ValueType a, ValueType b> {
-  def : Pat <(b (bitconvert (a DoubleRegs:$src))),
-             (b DoubleRegs:$src)>;
-  def : Pat <(a (bitconvert (b DoubleRegs:$src))),
-             (a DoubleRegs:$src)>;
+  def: Pat<(VecI16 (zext_invec HVI8:$Vs)),  (LoVec (V6_vzb HvxVR:$Vs))>;
+  def: Pat<(VecI32 (zext_invec HVI16:$Vs)), (LoVec (V6_vzh HvxVR:$Vs))>;
+  def: Pat<(VecI32 (zext_invec HVI8:$Vs)),
+           (LoVec (V6_vzh (LoVec (V6_vzb HvxVR:$Vs))))>;
 }
-
-// Bit convert vector types to integers.
-defm : bitconvert_32<v4i8,  i32>;
-defm : bitconvert_32<v2i16, i32>;
-defm : bitconvert_64<v8i8,  i64>;
-defm : bitconvert_64<v4i16, i64>;
-defm : bitconvert_64<v2i32, i64>;
-
-def: Pat<(sra (v4i16 DoubleRegs:$src1), u4_0ImmPred:$src2),
-         (S2_asr_i_vh DoubleRegs:$src1, imm:$src2)>;
-def: Pat<(srl (v4i16 DoubleRegs:$src1), u4_0ImmPred:$src2),
-         (S2_lsr_i_vh DoubleRegs:$src1, imm:$src2)>;
-def: Pat<(shl (v4i16 DoubleRegs:$src1), u4_0ImmPred:$src2),
-         (S2_asl_i_vh DoubleRegs:$src1, imm:$src2)>;
-
-def: Pat<(sra (v2i32 DoubleRegs:$src1), u5_0ImmPred:$src2),
-         (S2_asr_i_vw DoubleRegs:$src1, imm:$src2)>;
-def: Pat<(srl (v2i32 DoubleRegs:$src1), u5_0ImmPred:$src2),
-         (S2_lsr_i_vw DoubleRegs:$src1, imm:$src2)>;
-def: Pat<(shl (v2i32 DoubleRegs:$src1), u5_0ImmPred:$src2),
-         (S2_asl_i_vw DoubleRegs:$src1, imm:$src2)>;
-
-def : Pat<(v2i16 (add (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
-          (A2_svaddh IntRegs:$src1, IntRegs:$src2)>;
-
-def : Pat<(v2i16 (sub (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
-          (A2_svsubh IntRegs:$src1, IntRegs:$src2)>;
-
-def SDTHexagonVSPLAT: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
-def HexagonVSPLAT: SDNode<"HexagonISD::VSPLAT", SDTHexagonVSPLAT>;
-
-// Replicate the low 8-bits from 32-bits input register into each of the
-// four bytes of 32-bits destination register.
-def: Pat<(v4i8 (HexagonVSPLAT I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
-
-// Replicate the low 16-bits from 32-bits input register into each of the
-// four halfwords of 64-bits destination register.
-def: Pat<(v4i16 (HexagonVSPLAT I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
-
-def: Pat<(v2i32 (HexagonVSPLAT s8_0ImmPred:$s8)),
-         (A2_combineii imm:$s8, imm:$s8)>;
-def: Pat<(v2i32 (HexagonVSPLAT I32:$Rs)), (A2_combinew I32:$Rs, I32:$Rs)>;
-
-
-class VArith_pat <InstHexagon MI, SDNode Op, PatFrag Type>
-  : Pat <(Op Type:$Rss, Type:$Rtt),
-         (MI Type:$Rss, Type:$Rtt)>;
-
-def: VArith_pat <A2_vaddub, add, V8I8>;
-def: VArith_pat <A2_vaddh,  add, V4I16>;
-def: VArith_pat <A2_vaddw,  add, V2I32>;
-def: VArith_pat <A2_vsubub, sub, V8I8>;
-def: VArith_pat <A2_vsubh,  sub, V4I16>;
-def: VArith_pat <A2_vsubw,  sub, V2I32>;
-
-def: VArith_pat <A2_and,    and, V2I16>;
-def: VArith_pat <A2_xor,    xor, V2I16>;
-def: VArith_pat <A2_or,     or,  V2I16>;
-
-def: VArith_pat <A2_andp,   and, V8I8>;
-def: VArith_pat <A2_andp,   and, V4I16>;
-def: VArith_pat <A2_andp,   and, V2I32>;
-def: VArith_pat <A2_orp,    or,  V8I8>;
-def: VArith_pat <A2_orp,    or,  V4I16>;
-def: VArith_pat <A2_orp,    or,  V2I32>;
-def: VArith_pat <A2_xorp,   xor, V8I8>;
-def: VArith_pat <A2_xorp,   xor, V4I16>;
-def: VArith_pat <A2_xorp,   xor, V2I32>;
-
-def: Pat<(v2i32 (sra V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c)))),
-         (S2_asr_i_vw V2I32:$b, imm:$c)>;
-def: Pat<(v2i32 (srl V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c)))),
-         (S2_lsr_i_vw V2I32:$b, imm:$c)>;
-def: Pat<(v2i32 (shl V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c)))),
-         (S2_asl_i_vw V2I32:$b, imm:$c)>;
-
-def: Pat<(v4i16 (sra V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c)))),
-         (S2_asr_i_vh V4I16:$b, imm:$c)>;
-def: Pat<(v4i16 (srl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c)))),
-         (S2_lsr_i_vh V4I16:$b, imm:$c)>;
-def: Pat<(v4i16 (shl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c)))),
-         (S2_asl_i_vh V4I16:$b, imm:$c)>;
-
-
-def SDTHexagonVShift
-  : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>;
-
-def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>;
-def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>;
-def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>;
-
-def: Pat<(v2i32 (HexagonVASL V2I32:$Rs, u5_0ImmPred:$u5)),
-         (S2_asl_i_vw V2I32:$Rs, imm:$u5)>;
-def: Pat<(v4i16 (HexagonVASL V4I16:$Rs, u4_0ImmPred:$u4)),
-         (S2_asl_i_vh V4I16:$Rs, imm:$u4)>;
-def: Pat<(v2i32 (HexagonVASR V2I32:$Rs, u5_0ImmPred:$u5)),
-         (S2_asr_i_vw V2I32:$Rs, imm:$u5)>;
-def: Pat<(v4i16 (HexagonVASR V4I16:$Rs, u4_0ImmPred:$u4)),
-         (S2_asr_i_vh V4I16:$Rs, imm:$u4)>;
-def: Pat<(v2i32 (HexagonVLSR V2I32:$Rs, u5_0ImmPred:$u5)),
-         (S2_lsr_i_vw V2I32:$Rs, imm:$u5)>;
-def: Pat<(v4i16 (HexagonVLSR V4I16:$Rs, u4_0ImmPred:$u4)),
-         (S2_lsr_i_vh V4I16:$Rs, imm:$u4)>;
-
-class vshift_rr_pat<InstHexagon MI, SDNode Op, PatFrag Value>
-  : Pat <(Op Value:$Rs, I32:$Rt),
-         (MI Value:$Rs, I32:$Rt)>;
-
-def: vshift_rr_pat <S2_asl_r_vw, HexagonVASL, V2I32>;
-def: vshift_rr_pat <S2_asl_r_vh, HexagonVASL, V4I16>;
-def: vshift_rr_pat <S2_asr_r_vw, HexagonVASR, V2I32>;
-def: vshift_rr_pat <S2_asr_r_vh, HexagonVASR, V4I16>;
-def: vshift_rr_pat <S2_lsr_r_vw, HexagonVLSR, V2I32>;
-def: vshift_rr_pat <S2_lsr_r_vh, HexagonVLSR, V4I16>;
-
-
-class vcmp_vi1_pat<InstHexagon MI, PatFrag Op, PatFrag InVal, ValueType OutTy>
-  : Pat <(OutTy (Op InVal:$Rs, InVal:$Rt)),
-         (MI InVal:$Rs, InVal:$Rt)>;
-
-def: vcmp_vi1_pat<A2_vcmpweq,  seteq,  V2I32, v2i1>;
-def: vcmp_vi1_pat<A2_vcmpwgt,  setgt,  V2I32, v2i1>;
-def: vcmp_vi1_pat<A2_vcmpwgtu, setugt, V2I32, v2i1>;
-
-def: vcmp_vi1_pat<A2_vcmpheq,  seteq,  V4I16, v4i1>;
-def: vcmp_vi1_pat<A2_vcmphgt,  setgt,  V4I16, v4i1>;
-def: vcmp_vi1_pat<A2_vcmphgtu, setugt, V4I16, v4i1>;
-
-def: Pat<(mul V2I32:$Rs, V2I32:$Rt),
-         (PS_vmulw DoubleRegs:$Rs, DoubleRegs:$Rt)>;
-def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)),
-         (PS_vmulw_acc DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt)>;
-
-
-// Adds two v4i8: Hexagon does not have an insn for this one, so we
-// use the double add v8i8, and use only the low part of the result.
-def: Pat<(v4i8 (add (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
-         (LoReg (A2_vaddub (ToZext64 $Rs), (ToZext64 $Rt)))>;
-
-// Subtract two v4i8: Hexagon does not have an insn for this one, so we
-// use the double sub v8i8, and use only the low part of the result.
-def: Pat<(v4i8 (sub (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
-         (LoReg (A2_vsubub (ToZext64 $Rs), (ToZext64 $Rt)))>;
-
-//
-// No 32 bit vector mux.
-//
-def: Pat<(v4i8 (select I1:$Pu, V4I8:$Rs, V4I8:$Rt)),
-         (LoReg (C2_vmux I1:$Pu, (ToZext64 $Rs), (ToZext64 $Rt)))>;
-def: Pat<(v2i16 (select I1:$Pu, V2I16:$Rs, V2I16:$Rt)),
-         (LoReg (C2_vmux I1:$Pu, (ToZext64 $Rs), (ToZext64 $Rt)))>;
-
-//
-// 64-bit vector mux.
-//
-def: Pat<(v8i8 (vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)),
-         (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>;
-def: Pat<(v4i16 (vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)),
-         (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>;
-def: Pat<(v2i32 (vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)),
-         (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>;
-
-//
-// No 32 bit vector compare.
-//
-def: Pat<(i1 (seteq V4I8:$Rs, V4I8:$Rt)),
-         (A2_vcmpbeq (ToZext64 $Rs), (ToZext64 $Rt))>;
-def: Pat<(i1 (setgt V4I8:$Rs, V4I8:$Rt)),
-         (A4_vcmpbgt (ToZext64 $Rs), (ToZext64 $Rt))>;
-def: Pat<(i1 (setugt V4I8:$Rs, V4I8:$Rt)),
-         (A2_vcmpbgtu (ToZext64 $Rs), (ToZext64 $Rt))>;
-
-def: Pat<(i1 (seteq V2I16:$Rs, V2I16:$Rt)),
-         (A2_vcmpheq (ToZext64 $Rs), (ToZext64 $Rt))>;
-def: Pat<(i1 (setgt V2I16:$Rs, V2I16:$Rt)),
-         (A2_vcmphgt (ToZext64 $Rs), (ToZext64 $Rt))>;
-def: Pat<(i1 (setugt V2I16:$Rs, V2I16:$Rt)),
-         (A2_vcmphgtu (ToZext64 $Rs), (ToZext64 $Rt))>;
-
-
-class InvertCmp_pat<InstHexagon InvMI, PatFrag CmpOp, PatFrag Value,
-                    ValueType CmpTy>
-  : Pat<(CmpTy (CmpOp Value:$Rs, Value:$Rt)),
-        (InvMI Value:$Rt, Value:$Rs)>;
-
-// Map from a compare operation to the corresponding instruction with the
-// order of operands reversed, e.g.  x > y --> cmp.lt(y,x).
-def: InvertCmp_pat<A4_vcmpbgt,  setlt,  V8I8,  i1>;
-def: InvertCmp_pat<A4_vcmpbgt,  setlt,  V8I8,  v8i1>;
-def: InvertCmp_pat<A2_vcmphgt,  setlt,  V4I16, i1>;
-def: InvertCmp_pat<A2_vcmphgt,  setlt,  V4I16, v4i1>;
-def: InvertCmp_pat<A2_vcmpwgt,  setlt,  V2I32, i1>;
-def: InvertCmp_pat<A2_vcmpwgt,  setlt,  V2I32, v2i1>;
-
-def: InvertCmp_pat<A2_vcmpbgtu, setult, V8I8,  i1>;
-def: InvertCmp_pat<A2_vcmpbgtu, setult, V8I8,  v8i1>;
-def: InvertCmp_pat<A2_vcmphgtu, setult, V4I16, i1>;
-def: InvertCmp_pat<A2_vcmphgtu, setult, V4I16, v4i1>;
-def: InvertCmp_pat<A2_vcmpwgtu, setult, V2I32, i1>;
-def: InvertCmp_pat<A2_vcmpwgtu, setult, V2I32, v2i1>;
-
-// Map from vcmpne(Rss) -> !vcmpew(Rss).
-// rs != rt -> !(rs == rt).
-def: Pat<(v2i1 (setne V2I32:$Rs, V2I32:$Rt)),
-         (C2_not (v2i1 (A2_vcmpbeq V2I32:$Rs, V2I32:$Rt)))>;
-
-
-// Truncate: from vector B copy all 'E'ven 'B'yte elements:
-// A[0] = B[0];  A[1] = B[2];  A[2] = B[4];  A[3] = B[6];
-def: Pat<(v4i8 (trunc V4I16:$Rs)),
-         (S2_vtrunehb V4I16:$Rs)>;
-
-// Truncate: from vector B copy all 'O'dd 'B'yte elements:
-// A[0] = B[1];  A[1] = B[3];  A[2] = B[5];  A[3] = B[7];
-// S2_vtrunohb
-
-// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements:
-// A[0] = B[0];  A[1] = B[2];  A[2] = C[0];  A[3] = C[2];
-// S2_vtruneh
-
-def: Pat<(v2i16 (trunc V2I32:$Rs)),
-         (LoReg (S2_packhl (HiReg $Rs), (LoReg $Rs)))>;
-
-def: Pat<(v4i16 (zext   V4I8:$Rs)),  (S2_vzxtbh V4I8:$Rs)>;
-def: Pat<(v2i32 (zext   V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
-def: Pat<(v4i16 (anyext V4I8:$Rs)),  (S2_vzxtbh V4I8:$Rs)>;
-def: Pat<(v2i32 (anyext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
-def: Pat<(v4i16 (sext   V4I8:$Rs)),  (S2_vsxtbh V4I8:$Rs)>;
-def: Pat<(v2i32 (sext   V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>;
-
-// Sign extends a v2i8 into a v2i32.
-def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
-         (A2_combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
-
-// Sign extends a v2i16 into a v2i32.
-def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
-         (A2_combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
-
-
-// Multiplies two v2i16 and returns a v2i32.  We are using here the
-// saturating multiply, as hexagon does not provide a non saturating
-// vector multiply, and saturation does not impact the result that is
-// in double precision of the operands.
-
-// Multiplies two v2i16 vectors: as Hexagon does not have a multiply
-// with the C semantics for this one, this pattern uses the half word
-// multiply vmpyh that takes two v2i16 and returns a v2i32.  This is
-// then truncated to fit this back into a v2i16 and to simulate the
-// wrap around semantics for unsigned in C.
-def vmpyh: OutPatFrag<(ops node:$Rs, node:$Rt),
-                      (M2_vmpy2s_s0 (i32 $Rs), (i32 $Rt))>;
-
-def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)),
-         (LoReg (S2_vtrunewh (A2_combineii 0, 0),
-                             (vmpyh V2I16:$Rs, V2I16:$Rt)))>;
-
-// Multiplies two v4i16 vectors.
-def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)),
-         (S2_vtrunewh (vmpyh (HiReg $Rs), (HiReg $Rt)),
-                      (vmpyh (LoReg $Rs), (LoReg $Rt)))>;
-
-def VMPYB_no_V5: OutPatFrag<(ops node:$Rs, node:$Rt),
-  (S2_vtrunewh (vmpyh (HiReg (S2_vsxtbh $Rs)), (HiReg (S2_vsxtbh $Rt))),
-               (vmpyh (LoReg (S2_vsxtbh $Rs)), (LoReg (S2_vsxtbh $Rt))))>;
-
-// Multiplies two v4i8 vectors.
-def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)),
-         (S2_vtrunehb (M5_vmpybsu V4I8:$Rs, V4I8:$Rt))>,
-     Requires<[HasV5T]>;
-
-def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)),
-         (S2_vtrunehb (VMPYB_no_V5 V4I8:$Rs, V4I8:$Rt))>;
-
-// Multiplies two v8i8 vectors.
-def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)),
-         (A2_combinew (S2_vtrunehb (M5_vmpybsu (HiReg $Rs), (HiReg $Rt))),
-                      (S2_vtrunehb (M5_vmpybsu (LoReg $Rs), (LoReg $Rt))))>,
-     Requires<[HasV5T]>;
-
-def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)),
-         (A2_combinew (S2_vtrunehb (VMPYB_no_V5 (HiReg $Rs), (HiReg $Rt))),
-                      (S2_vtrunehb (VMPYB_no_V5 (LoReg $Rs), (LoReg $Rt))))>;
-
-// Truncated store from v4i16 to v4i8.
-def truncstorev4i8: PatFrag<(ops node:$val, node:$ptr),
-                            (truncstore node:$val, node:$ptr),
-    [{ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4i8; }]>;
-
-// Truncated store from v2i32 to v2i16.
-def truncstorev2i16: PatFrag<(ops node:$val, node:$ptr),
-                             (truncstore node:$val, node:$ptr),
-    [{ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v2i16; }]>;
-
-def: Pat<(truncstorev2i16 V2I32:$Rs, I32:$Rt),
-         (S2_storeri_io I32:$Rt, 0, (LoReg (S2_packhl (HiReg $Rs),
-                                                      (LoReg $Rs))))>;
-
-def: Pat<(truncstorev4i8 V4I16:$Rs, I32:$Rt),
-         (S2_storeri_io I32:$Rt, 0, (S2_vtrunehb V4I16:$Rs))>;
-
-
-// Zero and sign extended load from v2i8 into v2i16.
-def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr),
-    [{ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; }]>;
-
-def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr),
-    [{ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; }]>;
-
-def: Pat<(v2i16 (zextloadv2i8 I32:$Rs)),
-         (LoReg (v4i16 (S2_vzxtbh (L2_loadruh_io I32:$Rs, 0))))>;
-
-def: Pat<(v2i16 (sextloadv2i8 I32:$Rs)),
-         (LoReg (v4i16 (S2_vsxtbh (L2_loadrh_io I32:$Rs, 0))))>;
-
-def: Pat<(v2i32 (zextloadv2i8 I32:$Rs)),
-         (S2_vzxthw (LoReg (v4i16 (S2_vzxtbh (L2_loadruh_io I32:$Rs, 0)))))>;
-
-def: Pat<(v2i32 (sextloadv2i8 I32:$Rs)),
-         (S2_vsxthw (LoReg (v4i16 (S2_vsxtbh (L2_loadrh_io I32:$Rs, 0)))))>;
-
-
-// Read cycle counter.
-//
-def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
-def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf,
-  [SDNPHasChain]>;
-
-def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>;
diff --git a/lib/Target/Hexagon/HexagonPatternsV65.td b/lib/Target/Hexagon/HexagonPatternsV65.td
new file mode 100644
index 000000000000..50b76847b563
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonPatternsV65.td
@@ -0,0 +1,70 @@
+//==- HexagonPatternsV65.td -------------------------------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+multiclass vgathermh<RegisterClass RC> {
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
+                           (ins  IntRegs:$_dst_, IntRegs:$Rt,
+                                 ModRegs:$Mu, RC:$Vv),
+                           ".error \"should not emit\" ",
+                           []>;
+}
+
+multiclass vgathermw<RegisterClass RC> {
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
+                           (ins IntRegs:$_dst_, IntRegs:$Rt,
+                                ModRegs:$Mu, RC:$Vv),
+                           ".error \"should not emit\" ",
+                           []>;
+}
+
+multiclass vgathermhw<RegisterClass RC> {
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
+                           (ins IntRegs:$_dst_, IntRegs:$Rt,
+                                ModRegs:$Mu, RC:$Vv),
+                           ".error \"should not emit\" ",
+                           []>;
+}
+
+defm V6_vgathermh_pseudo  : vgathermh<HvxVR>;
+defm V6_vgathermw_pseudo  : vgathermw<HvxVR>;
+defm V6_vgathermhw_pseudo  : vgathermhw<HvxWR>;
+
+multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
+                           (ins  IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
+                                 ModRegs:$Mu, RC1:$Vv),
+                           ".error \"should not emit\" ",
+                           []>;
+}
+
+multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
+                           (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
+                                ModRegs:$Mu, RC1:$Vv),
+                           ".error \"should not emit\" ",
+                           []>;
+}
+
+multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
+                           (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
+                                ModRegs:$Mu, RC1:$Vv),
+                           ".error \"should not emit\" ",
+                           []>;
+}
+
+defm V6_vgathermhq_pseudo  : vgathermhq<HvxVR, HvxQR>;
+defm V6_vgathermwq_pseudo  : vgathermwq<HvxVR, HvxQR>;
+defm V6_vgathermhwq_pseudo  : vgathermhwq<HvxWR, HvxQR>;
diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp
index 7d961a238ae2..3c588a89b0da 100644
--- a/lib/Target/Hexagon/HexagonPeephole.cpp
+++ b/lib/Target/Hexagon/HexagonPeephole.cpp
@@ -8,31 +8,30 @@
 // This peephole pass optimizes in the following cases.
 // 1. Optimizes redundant sign extends for the following case
 //    Transform the following pattern
-//    %vreg170<def> = SXTW %vreg166
+//    %170 = SXTW %166
 //    ...
-//    %vreg176<def> = COPY %vreg170:isub_lo
+//    %176 = COPY %170:isub_lo
 //
 //    Into
-//    %vreg176<def> = COPY vreg166
+//    %176 = COPY %166
 //
 //  2. Optimizes redundant negation of predicates.
-//     %vreg15<def> = CMPGTrr %vreg6, %vreg2
+//     %15 = CMPGTrr %6, %2
 //     ...
-//     %vreg16<def> = NOT_p %vreg15<kill>
+//     %16 = NOT_p killed %15
 //     ...
-//     JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
+//     JMP_c killed %16, <%bb.1>, implicit dead %pc
 //
 //     Into
-//     %vreg15<def> = CMPGTrr %vreg6, %vreg2;
+//     %15 = CMPGTrr %6, %2;
 //     ...
-//     JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
+//     JMP_cNot killed %15, <%bb.1>, implicit dead %pc;
 //
 // Note: The peephole pass makes the instrucstions like
-// %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
+// %170 = SXTW %166 or %16 = NOT_p killed %15
 // redundant and relies on some form of dead removal instructions, like
 // DCE or DIE to actually eliminate them.
 
-
 //===----------------------------------------------------------------------===//
 
 #include "Hexagon.h"
@@ -44,14 +43,14 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/PassSupport.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <algorithm>
 
 using namespace llvm;
@@ -109,7 +108,7 @@ INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
                 false, false)
 
 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
@@ -133,7 +132,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
       NextI = std::next(I);
       MachineInstr &MI = *I;
       // Look for sign extends:
-      // %vreg170<def> = SXTW %vreg166
+      // %170 = SXTW %166
       if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
         assert(MI.getNumOperands() == 2);
         MachineOperand &Dst = MI.getOperand(0);
@@ -144,14 +143,14 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
         if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
             TargetRegisterInfo::isVirtualRegister(SrcReg)) {
           // Map the following:
-          // %vreg170<def> = SXTW %vreg166
-          // PeepholeMap[170] = vreg166
+          // %170 = SXTW %166
+          // PeepholeMap[170] = %166
           PeepholeMap[DstReg] = SrcReg;
         }
       }
 
-      // Look for  %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
-      // %vreg170:DoublRegs, %vreg169:IntRegs
+      // Look for  %170 = COMBINE_ir_V4 (0, %169)
+      // %170:DoublRegs, %169:IntRegs
       if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) {
         assert(MI.getNumOperands() == 3);
         MachineOperand &Dst = MI.getOperand(0);
@@ -165,10 +164,10 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
       }
 
       // Look for this sequence below
-      // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
-      // %vregIntReg = COPY %vregDoubleReg1:isub_lo.
+      // %DoubleReg1 = LSRd_ri %DoubleReg0, 32
+      // %IntReg = COPY %DoubleReg1:isub_lo.
       // and convert into
-      // %vregIntReg = COPY %vregDoubleReg0:isub_hi.
+      // %IntReg = COPY %DoubleReg0:isub_hi.
       if (MI.getOpcode() == Hexagon::S2_lsr_i_p) {
         assert(MI.getNumOperands() == 3);
         MachineOperand &Dst = MI.getOperand(0);
@@ -193,14 +192,14 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
         if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
             TargetRegisterInfo::isVirtualRegister(SrcReg)) {
           // Map the following:
-          // %vreg170<def> = NOT_xx %vreg166
-          // PeepholeMap[170] = vreg166
+          // %170 = NOT_xx %166
+          // PeepholeMap[170] = %166
           PeepholeMap[DstReg] = SrcReg;
         }
       }
 
       // Look for copy:
-      // %vreg176<def> = COPY %vreg170:isub_lo
+      // %176 = COPY %170:isub_lo
       if (!DisableOptSZExt && MI.isCopy()) {
         assert(MI.getNumOperands() == 2);
         MachineOperand &Dst = MI.getOperand(0);
diff --git a/lib/Target/Hexagon/HexagonPseudo.td b/lib/Target/Hexagon/HexagonPseudo.td
index b42c1ab975a8..b2d66317b66e 100644
--- a/lib/Target/Hexagon/HexagonPseudo.td
+++ b/lib/Target/Hexagon/HexagonPseudo.td
@@ -247,11 +247,14 @@ def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
 // This simplifies the frame-index elimination code.
 //
 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
-    isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
+    isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0, isExtendable = 1,
+    isExtentSigned = 1, opExtentBits = 16, opExtentAlign = 0 in {
+  let opExtendable = 2 in
   def PS_fi  : Pseudo<(outs IntRegs:$Rd),
-                         (ins IntRegs:$fi, s32_0Imm:$off), "">;
+                      (ins IntRegs:$fi, s32_0Imm:$off), "">;
+  let opExtendable = 3 in
   def PS_fia : Pseudo<(outs IntRegs:$Rd),
-                         (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
+                      (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
 }
 
 class CondStr<string CReg, bit True, bit New> {
@@ -295,7 +298,7 @@ let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1,
   def PS_jmpretfnewpt : T_JMPr_c<1, 1, 1, J2_jumprfnewpt>, PredNewRel;
 }
 
-//defm V6_vtran2x2_map : HexagonMapping<(outs VectorRegs:$Vy32, VectorRegs:$Vx32), (ins VectorRegs:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, VectorRegs:$Vx32in, IntRegs:$Rt32)>;
+//defm V6_vtran2x2_map : HexagonMapping<(outs HvxVR:$Vy32, HvxVR:$Vx32), (ins HvxVR:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, HvxVR:$Vx32in, IntRegs:$Rt32)>;
 
 // The reason for the custom inserter is to record all ALLOCA instructions
 // in MachineFunctionInfo.
@@ -397,84 +400,53 @@ let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
 
 // Vector store pseudos
 let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1,
-    mayStore = 1, hasSideEffects = 0 in
+    mayStore = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in
 class STrivv_template<RegisterClass RC, InstHexagon rootInst>
   : InstHexagon<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src),
     "", [], "", rootInst.Itinerary, rootInst.Type>;
 
-def PS_vstorerw_ai: STrivv_template<VecDblRegs, V6_vS32b_ai>,
-      Requires<[HasV60T,UseHVXSgl]>;
-def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B, V6_vS32b_ai_128B>,
-      Requires<[HasV60T,UseHVXDbl]>;
+def PS_vstorerw_ai: STrivv_template<HvxWR, V6_vS32b_ai>,
+      Requires<[HasV60T,UseHVX]>;
+def PS_vstorerw_nt_ai: STrivv_template<HvxWR, V6_vS32b_nt_ai>,
+      Requires<[HasV60T,UseHVX]>;
+def PS_vstorerwu_ai: STrivv_template<HvxWR, V6_vS32Ub_ai>,
+      Requires<[HasV60T,UseHVX]>;
 
-def PS_vstorerw_nt_ai: STrivv_template<VecDblRegs, V6_vS32b_nt_ai>,
-      Requires<[HasV60T,UseHVXSgl]>;
-def PS_vstorerw_nt_ai_128B: STrivv_template<VecDblRegs128B, V6_vS32b_nt_ai_128B>,
-      Requires<[HasV60T,UseHVXDbl]>;
-
-def PS_vstorerwu_ai: STrivv_template<VecDblRegs, V6_vS32Ub_ai>,
-      Requires<[HasV60T,UseHVXSgl]>;
-def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B, V6_vS32Ub_ai_128B>,
-      Requires<[HasV60T,UseHVXDbl]>;
-
-let isPseudo = 1, isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0 in {
-  def PS_vstorerq_ai: Pseudo<(outs),
-        (ins IntRegs:$Rs, s32_0Imm:$Off, VecPredRegs:$Qt), "", []>,
-        Requires<[HasV60T,UseHVXSgl]>;
-  def PS_vstorerq_ai_128B: Pseudo<(outs),
-        (ins IntRegs:$Rs, s32_0Imm:$Off, VecPredRegs128B:$Qt), "", []>,
-        Requires<[HasV60T,UseHVXDbl]>;
-}
+let isPseudo = 1, isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0 in
+def PS_vstorerq_ai: Pseudo<(outs),
+      (ins IntRegs:$Rs, s32_0Imm:$Off, HvxQR:$Qt), "", []>,
+      Requires<[HasV60T,UseHVX]>;
 
 // Vector load pseudos
 let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1,
-    mayLoad = 1, hasSideEffects = 0 in
+    mayLoad = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in
 class LDrivv_template<RegisterClass RC, InstHexagon rootInst>
   : InstHexagon<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off),
     "", [], "", rootInst.Itinerary, rootInst.Type>;
 
-def PS_vloadrw_ai: LDrivv_template<VecDblRegs, V6_vL32b_ai>,
-      Requires<[HasV60T,UseHVXSgl]>;
-def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B, V6_vL32b_ai_128B>,
-      Requires<[HasV60T,UseHVXDbl]>;
+def PS_vloadrw_ai: LDrivv_template<HvxWR, V6_vL32b_ai>,
+      Requires<[HasV60T,UseHVX]>;
+def PS_vloadrw_nt_ai: LDrivv_template<HvxWR, V6_vL32b_nt_ai>,
+      Requires<[HasV60T,UseHVX]>;
+def PS_vloadrwu_ai: LDrivv_template<HvxWR, V6_vL32Ub_ai>,
+      Requires<[HasV60T,UseHVX]>;
 
-def PS_vloadrw_nt_ai: LDrivv_template<VecDblRegs, V6_vL32b_nt_ai>,
-      Requires<[HasV60T,UseHVXSgl]>;
-def PS_vloadrw_nt_ai_128B: LDrivv_template<VecDblRegs128B, V6_vL32b_nt_ai_128B>,
-      Requires<[HasV60T,UseHVXDbl]>;
-
-def PS_vloadrwu_ai: LDrivv_template<VecDblRegs, V6_vL32Ub_ai>,
-      Requires<[HasV60T,UseHVXSgl]>;
-def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B, V6_vL32Ub_ai_128B>,
-      Requires<[HasV60T,UseHVXDbl]>;
-
-let isPseudo = 1, isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in {
-  def PS_vloadrq_ai: Pseudo<(outs VecPredRegs:$Qd),
-        (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>,
-        Requires<[HasV60T,UseHVXSgl]>;
-  def PS_vloadrq_ai_128B: Pseudo<(outs VecPredRegs128B:$Qd),
-        (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>,
-        Requires<[HasV60T,UseHVXDbl]>;
-}
+let isPseudo = 1, isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in
+def PS_vloadrq_ai: Pseudo<(outs HvxQR:$Qd),
+      (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>,
+      Requires<[HasV60T,UseHVX]>;
 
 
 let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
 class VSELInst<dag outs, dag ins, InstHexagon rootInst>
   : InstHexagon<outs, ins, "", [], "", rootInst.Itinerary, rootInst.Type>;
 
-def PS_vselect: VSELInst<(outs VectorRegs:$dst),
-      (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
-      V6_vcmov>, Requires<[HasV60T,UseHVXSgl]>;
-def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst),
-      (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
-      V6_vcmov>, Requires<[HasV60T,UseHVXDbl]>;
-
-def PS_wselect: VSELInst<(outs VecDblRegs:$dst),
-      (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3),
-      V6_vccombine>, Requires<[HasV60T,UseHVXSgl]>;
-def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst),
-      (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3),
-      V6_vccombine>, Requires<[HasV60T,UseHVXDbl]>;
+def PS_vselect: VSELInst<(outs HvxVR:$dst),
+      (ins PredRegs:$src1, HvxVR:$src2, HvxVR:$src3), V6_vcmov>,
+      Requires<[HasV60T,UseHVX]>;
+def PS_wselect: VSELInst<(outs HvxWR:$dst),
+      (ins PredRegs:$src1, HvxWR:$src2, HvxWR:$src3), V6_vccombine>,
+      Requires<[HasV60T,UseHVX]>;
 
 // Store predicate.
 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
diff --git a/lib/Target/Hexagon/HexagonRDFOpt.cpp b/lib/Target/Hexagon/HexagonRDFOpt.cpp
index b3aba50b5625..413bc8edf2b6 100644
--- a/lib/Target/Hexagon/HexagonRDFOpt.cpp
+++ b/lib/Target/Hexagon/HexagonRDFOpt.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonRDFOpt.cpp ------------------------------------------------===//
+//===- HexagonRDFOpt.cpp --------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -9,49 +9,65 @@
 
 #include "HexagonInstrInfo.h"
 #include "HexagonSubtarget.h"
+#include "MCTargetDesc/HexagonBaseInfo.h"
 #include "RDFCopy.h"
 #include "RDFDeadCode.h"
 #include "RDFGraph.h"
 #include "RDFLiveness.h"
+#include "RDFRegisters.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SetVector.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineDominanceFrontier.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Format.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+#include <limits>
+#include <utility>
 
 using namespace llvm;
 using namespace rdf;
 
 namespace llvm {
+
   void initializeHexagonRDFOptPass(PassRegistry&);
   FunctionPass *createHexagonRDFOpt();
-}
+
+} // end namespace llvm
+
+static unsigned RDFCount = 0;
+
+static cl::opt<unsigned> RDFLimit("rdf-limit",
+    cl::init(std::numeric_limits<unsigned>::max()));
+static cl::opt<bool> RDFDump("rdf-dump", cl::init(false));
 
 namespace {
-  unsigned RDFCount = 0;
-  cl::opt<unsigned> RDFLimit("rdf-limit", cl::init(UINT_MAX));
-  cl::opt<bool> RDFDump("rdf-dump", cl::init(false));
 
   class HexagonRDFOpt : public MachineFunctionPass {
   public:
-    HexagonRDFOpt() : MachineFunctionPass(ID) {
-      initializeHexagonRDFOptPass(*PassRegistry::getPassRegistry());
-    }
+    HexagonRDFOpt() : MachineFunctionPass(ID) {}
+
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineDominatorTree>();
       AU.addRequired<MachineDominanceFrontier>();
       AU.setPreservesAll();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
+
     StringRef getPassName() const override {
       return "Hexagon RDF optimizations";
     }
+
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
@@ -66,32 +82,32 @@ namespace {
     MachineRegisterInfo *MRI;
   };
 
-  char HexagonRDFOpt::ID = 0;
-}
-
-INITIALIZE_PASS_BEGIN(HexagonRDFOpt, "rdfopt", "Hexagon RDF opt", false, false)
-INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
-INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier)
-INITIALIZE_PASS_END(HexagonRDFOpt, "rdfopt", "Hexagon RDF opt", false, false)
-
-
-namespace {
 struct HexagonCP : public CopyPropagation {
   HexagonCP(DataFlowGraph &G) : CopyPropagation(G) {}
+
   bool interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) override;
 };
 
-
 struct HexagonDCE : public DeadCodeElimination {
   HexagonDCE(DataFlowGraph &G, MachineRegisterInfo &MRI)
     : DeadCodeElimination(G, MRI) {}
+
   bool rewrite(NodeAddr<InstrNode*> IA, SetVector<NodeId> &Remove);
   void removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum);
 
   bool run();
 };
+
 } // end anonymous namespace
 
+char HexagonRDFOpt::ID = 0;
+
+INITIALIZE_PASS_BEGIN(HexagonRDFOpt, "hexagon-rdf-opt",
+      "Hexagon RDF optimizations", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier)
+INITIALIZE_PASS_END(HexagonRDFOpt, "hexagon-rdf-opt",
+      "Hexagon RDF optimizations", false, false)
 
 bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
   auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void {
@@ -130,7 +146,6 @@ bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
   return CopyPropagation::interpretAsCopy(MI, EM);
 }
 
-
 bool HexagonDCE::run() {
   bool Collected = collect();
   if (!Collected)
@@ -139,7 +154,8 @@ bool HexagonDCE::run() {
   const SetVector<NodeId> &DeadNodes = getDeadNodes();
   const SetVector<NodeId> &DeadInstrs = getDeadInstrs();
 
-  typedef DenseMap<NodeId,NodeId> RefToInstrMap;
+  using RefToInstrMap = DenseMap<NodeId, NodeId>;
+
   RefToInstrMap R2I;
   SetVector<NodeId> PartlyDead;
   DataFlowGraph &DFG = getDFG();
@@ -156,7 +172,6 @@ bool HexagonDCE::run() {
     }
   }
 
-
   // Nodes to remove.
   SetVector<NodeId> Remove = DeadInstrs;
 
@@ -171,7 +186,6 @@ bool HexagonDCE::run() {
   return erase(Remove) || Changed;
 }
 
-
 void HexagonDCE::removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum) {
   MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
 
@@ -198,7 +212,6 @@ void HexagonDCE::removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum) {
   }
 }
 
-
 bool HexagonDCE::rewrite(NodeAddr<InstrNode*> IA, SetVector<NodeId> &Remove) {
   if (!getDFG().IsCode<NodeAttrs::Stmt>(IA))
     return false;
@@ -246,7 +259,7 @@ bool HexagonDCE::rewrite(NodeAddr<InstrNode*> IA, SetVector<NodeId> &Remove) {
     if (&DA.Addr->getOp() != &Op)
       continue;
     Defs = DFG.getRelatedRefs(IA, DA);
-    if (!all_of(Defs, IsDead))
+    if (!llvm::all_of(Defs, IsDead))
       return false;
     break;
   }
@@ -266,9 +279,8 @@ bool HexagonDCE::rewrite(NodeAddr<InstrNode*> IA, SetVector<NodeId> &Remove) {
   return true;
 }
 
-
 bool HexagonRDFOpt::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   if (RDFLimit.getPosition()) {
@@ -324,7 +336,6 @@ bool HexagonRDFOpt::runOnMachineFunction(MachineFunction &MF) {
   return false;
 }
 
-
 FunctionPass *llvm::createHexagonRDFOpt() {
   return new HexagonRDFOpt();
 }
diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index 1fc157900ed5..85d6a6b4089e 100644
--- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -26,13 +26,13 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Type.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
@@ -41,8 +41,9 @@
 
 using namespace llvm;
 
-HexagonRegisterInfo::HexagonRegisterInfo()
-    : HexagonGenRegisterInfo(Hexagon::R31) {}
+HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode)
+    : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
+                             0/*PC*/, HwMode) {}
 
 
 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const {
@@ -80,11 +81,9 @@ HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF,
       return Int64;
     case PredRegsRegClassID:
       return Pred;
-    case VectorRegsRegClassID:
-    case VectorRegs128BRegClassID:
+    case HvxVRRegClassID:
       return VecSgl;
-    case VecDblRegsRegClassID:
-    case VecDblRegs128BRegClassID:
+    case HvxWRRegClassID:
       return VecDbl;
     default:
       break;
@@ -119,11 +118,12 @@ HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
 
   switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
-  case HexagonSubtarget::V4:
-  case HexagonSubtarget::V5:
-  case HexagonSubtarget::V55:
-  case HexagonSubtarget::V60:
-  case HexagonSubtarget::V62:
+  case Hexagon::ArchEnum::V4:
+  case Hexagon::ArchEnum::V5:
+  case Hexagon::ArchEnum::V55:
+  case Hexagon::ArchEnum::V60:
+  case Hexagon::ArchEnum::V62:
+  case Hexagon::ArchEnum::V65:
     return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
   }
 
@@ -144,6 +144,7 @@ BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
   Reserved.set(Hexagon::R29);
   Reserved.set(Hexagon::R30);
   Reserved.set(Hexagon::R31);
+  Reserved.set(Hexagon::VTMP);
   // Control registers.
   Reserved.set(Hexagon::SA0);         // C0
   Reserved.set(Hexagon::LC0);         // C1
@@ -213,7 +214,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
       break;
   }
 
-  if (!HII.isValidOffset(Opc, RealOffset)) {
+  if (!HII.isValidOffset(Opc, RealOffset, this)) {
     // If the offset is not valid, calculate the address in a temporary
     // register and use it with offset 0.
     auto &MRI = MF.getRegInfo();
@@ -257,23 +258,22 @@ unsigned HexagonRegisterInfo::getStackRegister() const {
 
 
 unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
-      const TargetRegisterClass *RC, unsigned GenIdx) const {
+      const TargetRegisterClass &RC, unsigned GenIdx) const {
   assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
 
   static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
   static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
 
-  switch (RC->getID()) {
+  switch (RC.getID()) {
     case Hexagon::CtrRegs64RegClassID:
     case Hexagon::DoubleRegsRegClassID:
       return ISub[GenIdx];
-    case Hexagon::VecDblRegsRegClassID:
-    case Hexagon::VecDblRegs128BRegClassID:
+    case Hexagon::HvxWRRegClassID:
       return VSub[GenIdx];
   }
 
-  if (const TargetRegisterClass *SuperRC = *RC->getSuperClasses())
-    return getHexagonSubRegIndex(SuperRC, GenIdx);
+  if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
+    return getHexagonSubRegIndex(*SuperRC, GenIdx);
 
   llvm_unreachable("Invalid register class");
 }
diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.h b/lib/Target/Hexagon/HexagonRegisterInfo.h
index 5f65fad2cc04..4ead57da8fa1 100644
--- a/lib/Target/Hexagon/HexagonRegisterInfo.h
+++ b/lib/Target/Hexagon/HexagonRegisterInfo.h
@@ -15,8 +15,7 @@
 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
 
-#include "llvm/MC/MachineLocation.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
 #include "HexagonGenRegisterInfo.inc"
@@ -30,7 +29,7 @@ namespace Hexagon {
 
 class HexagonRegisterInfo : public HexagonGenRegisterInfo {
 public:
-  HexagonRegisterInfo();
+  HexagonRegisterInfo(unsigned HwMode);
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
@@ -68,7 +67,7 @@ public:
   unsigned getFrameRegister() const;
   unsigned getStackRegister() const;
 
-  unsigned getHexagonSubRegIndex(const TargetRegisterClass *RC,
+  unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
         unsigned GenIdx) const;
 
   const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,
diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.td b/lib/Target/Hexagon/HexagonRegisterInfo.td
index 45dbb3a6d218..2ceed70c2497 100644
--- a/lib/Target/Hexagon/HexagonRegisterInfo.td
+++ b/lib/Target/Hexagon/HexagonRegisterInfo.td
@@ -15,7 +15,6 @@ let Namespace = "Hexagon" in {
 
   class HexagonReg<bits<5> num, string n, list<string> alt = [],
                    list<Register> alias = []> : Register<n, alt> {
-    field bits<5> Num;
     let Aliases = alias;
     let HWEncoding{4-0} = num;
   }
@@ -23,8 +22,6 @@ let Namespace = "Hexagon" in {
   class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs,
                          list<string> alt = []> :
         RegisterWithSubRegs<n, subregs> {
-    field bits<5> Num;
-
     let AltNames = alt;
     let HWEncoding{4-0} = num;
   }
@@ -32,28 +29,20 @@ let Namespace = "Hexagon" in {
   // Registers are identified with 5-bit ID numbers.
   // Ri - 32-bit integer registers.
   class Ri<bits<5> num, string n, list<string> alt = []> :
-        HexagonReg<num, n, alt> {
-    let Num = num;
-  }
+        HexagonReg<num, n, alt>;
 
   // Rf - 32-bit floating-point registers.
-  class Rf<bits<5> num, string n> : HexagonReg<num, n> {
-    let Num = num;
-  }
-
+  class Rf<bits<5> num, string n> : HexagonReg<num, n>;
 
   // Rd - 64-bit registers.
   class Rd<bits<5> num, string n, list<Register> subregs,
            list<string> alt = []> :
         HexagonDoubleReg<num, n, subregs, alt> {
-    let Num = num;
     let SubRegs = subregs;
   }
 
   // Rp - predicate registers
-  class Rp<bits<5> num, string n> : HexagonReg<num, n> {
-    let Num = num;
-  }
+  class Rp<bits<5> num, string n> : HexagonReg<num, n>;
 
 
   // Rq - vector predicate registers
@@ -63,22 +52,19 @@ let Namespace = "Hexagon" in {
 
   // Rc - control registers
   class Rc<bits<5> num, string n,
-           list<string> alt = [], list<Register> alias = []> : 
-        HexagonReg<num, n, alt, alias> {
-    let Num = num;
-  }
+           list<string> alt = [], list<Register> alias = []> :
+        HexagonReg<num, n, alt, alias>;
 
   // Rcc - 64-bit control registers.
   class Rcc<bits<5> num, string n, list<Register> subregs,
             list<string> alt = []> :
         HexagonDoubleReg<num, n, subregs, alt> {
-    let Num = num;
     let SubRegs = subregs;
   }
 
   // Mx - address modifier registers
-  class Mx<bits<1> num, string n> : HexagonReg<{0b0000, num}, n> {
-    let Num = !cast<bits<5>>(num);
+  class Mx<bits<1> num, string n> : Register<n, []> {
+    let HWEncoding{0} = num;
   }
 
   def isub_lo  : SubRegIndex<32>;
@@ -164,29 +150,30 @@ let Namespace = "Hexagon" in {
   def PKTCOUNTHI: Rc<19, "pktcounthi", ["c19"]>,   DwarfRegNum<[86]>;
   def UTIMERLO:   Rc<30, "utimerlo",   ["c30"]>,   DwarfRegNum<[97]>;
   def UTIMERHI:   Rc<31, "utimerhi",   ["c31"]>,   DwarfRegNum<[98]>;
-}
 
   // Control registers pairs.
   let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
-    def C1_0:     Rcc<0,  "c1:0",   [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>;
-    def C3_2:     Rcc<2,  "c3:2",   [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
-    def C5_4:     Rcc<4,  "c5:4",   [P3_0, C5]>,              DwarfRegNum<[71]>;
-    def C7_6:     Rcc<6,  "c7:6",   [M0, M1],   ["m1:0"]>,    DwarfRegNum<[72]>;
+    def C1_0   : Rcc<0,   "c1:0",  [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>;
+    def C3_2   : Rcc<2,   "c3:2",  [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
+    def C5_4   : Rcc<4,   "c5:4",  [P3_0, C5]>,              DwarfRegNum<[71]>;
+    def C7_6   : Rcc<6,   "c7:6",  [M0, M1],   ["m1:0"]>,    DwarfRegNum<[72]>;
     // Use C8 instead of USR as a subregister of C9_8.
-    def C9_8:     Rcc<8,  "c9:8",   [C8, PC]>,                DwarfRegNum<[74]>;
-    def C11_10:   Rcc<10, "c11:10", [UGP, GP]>,               DwarfRegNum<[76]>;
-    def CS:       Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>,   DwarfRegNum<[78]>;
-    def UPCYCLE:  Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI]>,  DwarfRegNum<[80]>;
-    def C17_16:   Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>,  DwarfRegNum<[83]>;
-    def PKTCOUNT: Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>,
+    def C9_8   : Rcc<8,   "c9:8",  [C8, PC]>,                DwarfRegNum<[74]>;
+    def C11_10 : Rcc<10, "c11:10", [UGP, GP]>,               DwarfRegNum<[76]>;
+    def CS     : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>,   DwarfRegNum<[78]>;
+    def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI], ["upcycle"]>,
+                                                              DwarfRegNum<[80]>;
+    def C17_16 : Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>,  DwarfRegNum<[83]>;
+    def PKTCOUNT : Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>,
                                                               DwarfRegNum<[85]>;
-    def UTIMER:   Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>,
+    def UTIMER :  Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>,
                                                               DwarfRegNum<[97]>;
   }
 
   foreach i = 0-31 in {
     def V#i  : Ri<i, "v"#i>,  DwarfRegNum<[!add(i, 99)]>;
   }
+  def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>;
 
   // Aliases of the V* registers used to hold double vec values.
   let SubRegIndices = [vsub_lo, vsub_hi], CoveredBySubRegs = 1 in {
@@ -213,6 +200,42 @@ let Namespace = "Hexagon" in {
   def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>;
   def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>;
   def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>;
+}
+
+// HVX types
+
+def VecI1
+  : ValueTypeByHwMode<[Hvx64,  Hvx64old,  Hvx128,  Hvx128old, DefaultMode],
+                      [v512i1, v512i1,    v1024i1, v1024i1,   v512i1]>;
+def VecI8
+  : ValueTypeByHwMode<[Hvx64,  Hvx64old,  Hvx128,  Hvx128old, DefaultMode],
+                      [v64i8,  v64i8,     v128i8,  v128i8,    v64i8]>;
+def VecI16
+  : ValueTypeByHwMode<[Hvx64,  Hvx64old,  Hvx128,  Hvx128old, DefaultMode],
+                      [v32i16, v32i16,    v64i16,  v64i16,    v32i16]>;
+def VecI32
+  : ValueTypeByHwMode<[Hvx64,  Hvx64old,  Hvx128,  Hvx128old, DefaultMode],
+                      [v16i32, v16i32,    v32i32,  v32i32,    v16i32]>;
+def VecPI8
+  : ValueTypeByHwMode<[Hvx64,  Hvx64old,  Hvx128,  Hvx128old, DefaultMode],
+                      [v128i8, v128i8,    v256i8,  v256i8,    v128i8]>;
+def VecPI16
+  : ValueTypeByHwMode<[Hvx64,  Hvx64old,  Hvx128,  Hvx128old, DefaultMode],
+                      [v64i16, v64i16,    v128i16, v128i16,   v64i16]>;
+def VecPI32
+  : ValueTypeByHwMode<[Hvx64,  Hvx64old,  Hvx128,  Hvx128old, DefaultMode],
+                      [v32i32, v32i32,    v64i32,  v64i32,    v32i32]>;
+def VecQ8
+  : ValueTypeByHwMode<[Hvx64,  Hvx64old,  Hvx128,  Hvx128old, DefaultMode],
+                      [v64i1,  v64i1,     v128i1,  v128i1,    v64i1]>;
+def VecQ16
+  : ValueTypeByHwMode<[Hvx64,  Hvx64old,  Hvx128,  Hvx128old, DefaultMode],
+                      [v32i1,  v32i1,     v64i1,   v64i1,     v32i1]>;
+def VecQ32
+  : ValueTypeByHwMode<[Hvx64,  Hvx64old,  Hvx128,  Hvx128old, DefaultMode],
+                      [v16i1,  v16i1,     v32i1,   v32i1,     v16i1]>;
+
+// HVX register classes
 
 // Register classes.
 //
@@ -220,56 +243,46 @@ let Namespace = "Hexagon" in {
 // allocation order...
 //
 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
-                            (add (sequence "R%u", 0, 9),
-                                 (sequence "R%u", 12, 28),
-                                 R10, R11, R29, R30, R31)> {
-}
+  (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28),
+       R10, R11, R29, R30, R31)>;
 
 // Registers are listed in reverse order for allocation preference reasons.
 def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32,
-                                   (add R23, R22, R21, R20, R19, R18, R17,
-                                        R16, R7, R6, R5, R4, R3, R2, R1, R0)>;
+  (add R23, R22, R21, R20, R19, R18, R17, R16,
+       R7, R6, R5, R4, R3, R2, R1, R0)>;
 
 def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32,
-                                (add R7, R6, R5, R4, R3, R2, R1, R0)> ;
+  (add R7, R6, R5, R4, R3, R2, R1, R0)> ;
 
 def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64,
-                               (add (sequence "D%u", 0, 4),
-                                    (sequence "D%u", 6, 13), D5, D14, D15)>;
+  (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>;
 
 def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64,
-                                          (add D11, D10, D9, D8, D3, D2, D1,
-                                               D0)>;
+  (add D11, D10, D9, D8, D3, D2, D1, D0)>;
 
-def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512,
-                               (add (sequence "V%u", 0, 31))>;
-
-def VecDblRegs : RegisterClass<"Hexagon",
-                         [v128i8, v64i16, v32i32, v16i64], 1024,
-                               (add (sequence "W%u", 0, 15))>;
-
-def VectorRegs128B : RegisterClass<"Hexagon",
-                         [v128i8, v64i16, v32i32, v16i64], 1024,
-                               (add (sequence "V%u", 0, 31))>;
-
-def VecDblRegs128B : RegisterClass<"Hexagon",
-                         [v256i8,v128i16,v64i32,v32i64], 2048,
-                               (add (sequence "W%u", 0, 15))>;
-
-def VecPredRegs : RegisterClass<"Hexagon", [v512i1], 512,
-                                (add (sequence "Q%u", 0, 3))>;
+def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32], 512,
+  (add (sequence "V%u", 0, 31), VTMP)> {
+  let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
+    [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>;
+}
 
-def VecPredRegs128B : RegisterClass<"Hexagon", [v1024i1], 1024,
-                                   (add (sequence "Q%u", 0, 3))>;
+def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32], 1024,
+  (add (sequence "W%u", 0, 15))> {
+  let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
+    [RegInfo<1024,1024,1024>, RegInfo<2048,2048,2048>, RegInfo<1024,1024,1024>]>;
+}
 
-def PredRegs : RegisterClass<"Hexagon", 
-                             [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32,
-                             (add (sequence "P%u", 0, 3))>
-{
-  let Size = 32;
+def HvxQR : RegisterClass<"Hexagon", [VecI1, VecQ8, VecQ16, VecQ32], 512,
+  (add Q0, Q1, Q2, Q3)> {
+  let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
+    [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>;
 }
 
 let Size = 32 in
+def PredRegs : RegisterClass<"Hexagon",
+  [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>;
+
+let Size = 32 in
 def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>;
 
 let Size = 32, isAllocatable = 0 in
@@ -291,9 +304,13 @@ def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64,
 // The function RegisterMatchesArch() uses this list for validation.
 let isAllocatable = 0 in
 def V62Regs : RegisterClass<"Hexagon", [i32], 32,
-                            (add FRAMELIMIT, FRAMEKEY,   C17_16,
-                                 PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT,
-                                 UTIMERLO,   UTIMERHI,   UTIMER)>;
+  (add FRAMELIMIT, FRAMEKEY,   C17_16, PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT,
+       UTIMERLO,   UTIMERHI,   UTIMER)>;
+
+// These registers are new for v65 and onward.
+let Size = 32, isAllocatable = 0 in
+def V65Regs : RegisterClass<"Hexagon", [i32], 32, (add VTMP)>;
+
 
 
 def HexagonCSR
diff --git a/lib/Target/Hexagon/HexagonSchedule.td b/lib/Target/Hexagon/HexagonSchedule.td
index ffee03e72639..a1dfb66017a5 100644
--- a/lib/Target/Hexagon/HexagonSchedule.td
+++ b/lib/Target/Hexagon/HexagonSchedule.td
@@ -79,3 +79,8 @@ include "HexagonScheduleV60.td"
 
 include "HexagonScheduleV62.td"
 
+//===----------------------------------------------------------------------===//
+// V65 Machine Info +
+//===----------------------------------------------------------------------===//
+
+include "HexagonScheduleV65.td"
diff --git a/lib/Target/Hexagon/HexagonScheduleV65.td b/lib/Target/Hexagon/HexagonScheduleV65.td
new file mode 100644
index 000000000000..e3b1313923f5
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonScheduleV65.td
@@ -0,0 +1,40 @@
+//=-HexagonScheduleV65.td - HexagonV65 Scheduling Definitions *- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//
+// ScalarItin and HVXItin contain some old itineraries
+// still used by a handful of instructions. Hopefully, we will be able
+// to get rid of them soon.
+
+def HexagonV65ItinList : DepScalarItinV65, ScalarItin,
+                         DepHVXItinV65, HVXItin, PseudoItin {
+  list<InstrItinData> ItinList =
+    !listconcat(DepScalarItinV65_list, ScalarItin_list,
+                DepHVXItinV65_list, HVXItin_list, PseudoItin_list);
+}
+
+def HexagonItinerariesV65 :
+      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
+                            CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
+                            CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
+                            CVI_ALL_NOMEM],
+                            [Hex_FWD, HVX_FWD],
+                            HexagonV65ItinList.ItinList>;
+
+def HexagonModelV65 : SchedMachineModel {
+  // Max issue per cycle == bundle width.
+  let IssueWidth = 4;
+  let Itineraries = HexagonItinerariesV65;
+  let LoadLatency = 1;
+  let CompleteModel = 0;
+}
+
+//===----------------------------------------------------------------------===//
+// Hexagon V65 Resource Definitions -
+//===----------------------------------------------------------------------===//
diff --git a/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp b/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
index 68484344fded..3fe4cc73d2f3 100644
--- a/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
+++ b/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
@@ -23,8 +23,8 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 
 using namespace llvm;
 
diff --git a/lib/Target/Hexagon/HexagonSplitDouble.cpp b/lib/Target/Hexagon/HexagonSplitDouble.cpp
index 4fa929a20810..c9f5400018e8 100644
--- a/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonSplitDouble.cpp -------------------------------------------===//
+//===- HexagonSplitDouble.cpp ---------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -25,6 +25,7 @@
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
@@ -32,7 +33,6 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
@@ -51,19 +51,18 @@ namespace llvm {
 
 } // end namespace llvm
 
-namespace {
+static cl::opt<int> MaxHSDR("max-hsdr", cl::Hidden, cl::init(-1),
+    cl::desc("Maximum number of split partitions"));
+static cl::opt<bool> MemRefsFixed("hsdr-no-mem", cl::Hidden, cl::init(true),
+    cl::desc("Do not split loads or stores"));
 
-  static cl::opt<int> MaxHSDR("max-hsdr", cl::Hidden, cl::init(-1),
-      cl::desc("Maximum number of split partitions"));
-  static cl::opt<bool> MemRefsFixed("hsdr-no-mem", cl::Hidden, cl::init(true),
-      cl::desc("Do not split loads or stores"));
+namespace {
 
   class HexagonSplitDoubleRegs : public MachineFunctionPass {
   public:
     static char ID;
 
-    HexagonSplitDoubleRegs() : MachineFunctionPass(ID), TRI(nullptr),
-        TII(nullptr) {
+    HexagonSplitDoubleRegs() : MachineFunctionPass(ID) {
       initializeHexagonSplitDoubleRegsPass(*PassRegistry::getPassRegistry());
     }
 
@@ -82,16 +81,16 @@ namespace {
   private:
     static const TargetRegisterClass *const DoubleRC;
 
-    const HexagonRegisterInfo *TRI;
-    const HexagonInstrInfo *TII;
+    const HexagonRegisterInfo *TRI = nullptr;
+    const HexagonInstrInfo *TII = nullptr;
     const MachineLoopInfo *MLI;
     MachineRegisterInfo *MRI;
 
-    typedef std::set<unsigned> USet;
-    typedef std::map<unsigned,USet> UUSetMap;
-    typedef std::pair<unsigned,unsigned> UUPair;
-    typedef std::map<unsigned,UUPair> UUPairMap;
-    typedef std::map<const MachineLoop*,USet> LoopRegMap;
+    using USet = std::set<unsigned>;
+    using UUSetMap = std::map<unsigned, USet>;
+    using UUPair = std::pair<unsigned, unsigned>;
+    using UUPairMap = std::map<unsigned, UUPair>;
+    using LoopRegMap = std::map<const MachineLoop *, USet>;
 
     bool isInduction(unsigned Reg, LoopRegMap &IRM) const;
     bool isVolatileInstr(const MachineInstr *MI) const;
@@ -117,17 +116,18 @@ namespace {
     bool splitPartition(const USet &Part);
 
     static int Counter;
+
     static void dump_partition(raw_ostream&, const USet&,
        const TargetRegisterInfo&);
   };
 
-  char HexagonSplitDoubleRegs::ID;
-  int HexagonSplitDoubleRegs::Counter = 0;
-  const TargetRegisterClass *const HexagonSplitDoubleRegs::DoubleRC
-      = &Hexagon::DoubleRegsRegClass;
-
 } // end anonymous namespace
 
+char HexagonSplitDoubleRegs::ID;
+int HexagonSplitDoubleRegs::Counter = 0;
+const TargetRegisterClass *const HexagonSplitDoubleRegs::DoubleRC =
+    &Hexagon::DoubleRegsRegClass;
+
 INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double",
   "Hexagon Split Double Registers", false, false)
 
@@ -136,7 +136,7 @@ LLVM_DUMP_METHOD void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os,
       const USet &Part, const TargetRegisterInfo &TRI) {
   dbgs() << '{';
   for (auto I : Part)
-    dbgs() << ' ' << PrintReg(I, &TRI);
+    dbgs() << ' ' << printReg(I, &TRI);
   dbgs() << " }";
 }
 #endif
@@ -217,8 +217,8 @@ bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
 }
 
 void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
-  typedef std::map<unsigned,unsigned> UUMap;
-  typedef std::vector<unsigned> UVect;
+  using UUMap = std::map<unsigned, unsigned>;
+  using UVect = std::vector<unsigned>;
 
   unsigned NumRegs = MRI->getNumVirtRegs();
   BitVector DoubleRegs(NumRegs);
@@ -244,7 +244,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
     if (FixedRegs[x])
       continue;
     unsigned R = TargetRegisterInfo::index2VirtReg(x);
-    DEBUG(dbgs() << PrintReg(R, TRI) << " ~~");
+    DEBUG(dbgs() << printReg(R, TRI) << " ~~");
     USet &Asc = AssocMap[R];
     for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end();
          U != Z; ++U) {
@@ -267,7 +267,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
         unsigned u = TargetRegisterInfo::virtReg2Index(T);
         if (FixedRegs[u])
           continue;
-        DEBUG(dbgs() << ' ' << PrintReg(T, TRI));
+        DEBUG(dbgs() << ' ' << printReg(T, TRI));
         Asc.insert(T);
         // Make it symmetric.
         AssocMap[T].insert(R);
@@ -501,7 +501,8 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
 
   // Get the set of all double registers defined by phi nodes in the
   // loop header.
-  typedef std::vector<unsigned> UVect;
+  using UVect = std::vector<unsigned>;
+
   UVect DP;
   for (auto &MI : *HB) {
     if (!MI.isPHI())
@@ -535,14 +536,15 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
   Rs.insert(CmpR2);
 
   DEBUG({
-    dbgs() << "For loop at BB#" << HB->getNumber() << " ind regs: ";
+    dbgs() << "For loop at " << printMBBReference(*HB) << " ind regs: ";
     dump_partition(dbgs(), Rs, *TRI);
     dbgs() << '\n';
   });
 }
 
 void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
-  typedef std::vector<MachineLoop*> LoopVector;
+  using LoopVector = std::vector<MachineLoop *>;
+
   LoopVector WorkQ;
 
   for (auto I : *MLI)
@@ -1097,8 +1099,9 @@ void HexagonSplitDoubleRegs::collapseRegPairs(MachineInstr *MI,
 }
 
 bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
+  using MISet = std::set<MachineInstr *>;
+
   const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
-  typedef std::set<MachineInstr*> MISet;
   bool Changed = false;
 
   DEBUG(dbgs() << "Splitting partition: "; dump_partition(dbgs(), Part, *TRI);
@@ -1119,8 +1122,8 @@ bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
 
     unsigned LoR = MRI->createVirtualRegister(IntRC);
     unsigned HiR = MRI->createVirtualRegister(IntRC);
-    DEBUG(dbgs() << "Created mapping: " << PrintReg(DR, TRI) << " -> "
-                 << PrintReg(HiR, TRI) << ':' << PrintReg(LoR, TRI) << '\n');
+    DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> "
+                 << printReg(HiR, TRI) << ':' << printReg(LoR, TRI) << '\n');
     PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR)));
   }
 
@@ -1160,7 +1163,7 @@ bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) {
   DEBUG(dbgs() << "Splitting double registers in function: "
         << MF.getName() << '\n');
 
-  if (skipFunction(*MF.getFunction()))
+  if (skipFunction(MF.getFunction()))
     return false;
 
   auto &ST = MF.getSubtarget<HexagonSubtarget>();
diff --git a/lib/Target/Hexagon/HexagonStoreWidening.cpp b/lib/Target/Hexagon/HexagonStoreWidening.cpp
index af1bf48b6320..300f6de33552 100644
--- a/lib/Target/Hexagon/HexagonStoreWidening.cpp
+++ b/lib/Target/Hexagon/HexagonStoreWidening.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonStoreWidening.cpp------------------------------------------===//
+//===- HexagonStoreWidening.cpp -------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -9,10 +9,10 @@
 // Replace sequences of "narrow" stores to adjacent memory locations with
 // a fewer "wide" stores that have the same effect.
 // For example, replace:
-//   S4_storeirb_io  %vreg100, 0, 0   ; store-immediate-byte
-//   S4_storeirb_io  %vreg100, 1, 0   ; store-immediate-byte
+//   S4_storeirb_io  %100, 0, 0   ; store-immediate-byte
+//   S4_storeirb_io  %100, 1, 0   ; store-immediate-byte
 // with
-//   S4_storeirh_io  %vreg100, 0, 0   ; store-immediate-halfword
+//   S4_storeirh_io  %100, 0, 0   ; store-immediate-halfword
 // The above is the general idea.  The actual cases handled by the code
 // may be a bit more complex.
 // The purpose of this pass is to reduce the number of outstanding stores,
@@ -27,7 +27,6 @@
 #include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
 #include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/ADT/StringRef.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Analysis/MemoryLocation.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
@@ -55,8 +54,8 @@ using namespace llvm;
 
 namespace llvm {
 
-  FunctionPass *createHexagonStoreWidening();
-  void initializeHexagonStoreWideningPass(PassRegistry&);
+FunctionPass *createHexagonStoreWidening();
+void initializeHexagonStoreWideningPass(PassRegistry&);
 
 } // end namespace llvm
 
@@ -91,8 +90,8 @@ namespace {
   private:
     static const int MaxWideSize = 4;
 
-    typedef std::vector<MachineInstr*> InstrGroup;
-    typedef std::vector<InstrGroup> InstrGroupList;
+    using InstrGroup = std::vector<MachineInstr *>;
+    using InstrGroupList = std::vector<InstrGroup>;
 
     bool instrAliased(InstrGroup &Stores, const MachineMemOperand &MMO);
     bool instrAliased(InstrGroup &Stores, const MachineInstr *MI);
@@ -109,9 +108,15 @@ namespace {
     bool storesAreAdjacent(const MachineInstr *S1, const MachineInstr *S2);
   };
 
+} // end anonymous namespace
+
 char HexagonStoreWidening::ID = 0;
 
-} // end anonymous namespace
+INITIALIZE_PASS_BEGIN(HexagonStoreWidening, "hexagon-widen-stores",
+                "Hexason Store Widening", false, false)
+INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
+INITIALIZE_PASS_END(HexagonStoreWidening, "hexagon-widen-stores",
+                "Hexagon Store Widening", false, false)
 
 // Some local helper functions...
 static unsigned getBaseAddressRegister(const MachineInstr *MI) {
@@ -143,12 +148,6 @@ static const MachineMemOperand &getStoreTarget(const MachineInstr *MI) {
   return **MI->memoperands_begin();
 }
 
-INITIALIZE_PASS_BEGIN(HexagonStoreWidening, "hexagon-widen-stores",
-                "Hexason Store Widening", false, false)
-INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(HexagonStoreWidening, "hexagon-widen-stores",
-                "Hexagon Store Widening", false, false)
-
 // Filtering function: any stores whose opcodes are not "approved" of by
 // this function will not be subjected to widening.
 inline bool HexagonStoreWidening::handledStoreType(const MachineInstr *MI) {
@@ -586,7 +585,7 @@ bool HexagonStoreWidening::processBasicBlock(MachineBasicBlock &MBB) {
 }
 
 bool HexagonStoreWidening::runOnMachineFunction(MachineFunction &MFn) {
-  if (skipFunction(*MFn.getFunction()))
+  if (skipFunction(MFn.getFunction()))
     return false;
 
   MF = &MFn;
diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp
index 0aada8a53c97..6f1f6c46a107 100644
--- a/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -53,14 +53,6 @@ static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
   cl::Hidden, cl::ZeroOrMore, cl::init(true));
 
-static cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double",
-  cl::Hidden, cl::ZeroOrMore, cl::init(false),
-  cl::desc("Enable Hexagon Double Vector eXtensions"));
-
-static cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx",
-  cl::Hidden, cl::ZeroOrMore, cl::init(false),
-  cl::desc("Enable Hexagon Vector eXtensions"));
-
 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
   cl::Hidden, cl::ZeroOrMore, cl::init(false));
 
@@ -87,68 +79,233 @@ static cl::opt<bool> EnablePredicatedCalls("hexagon-pred-calls",
   cl::Hidden, cl::ZeroOrMore, cl::init(false),
   cl::desc("Consider calls to be predicable"));
 
-void HexagonSubtarget::initializeEnvironment() {
-  UseMemOps = false;
-  ModeIEEERndNear = false;
-  UseBSBScheduling = false;
+static cl::opt<bool> SchedPredsCloser("sched-preds-closer",
+  cl::Hidden, cl::ZeroOrMore, cl::init(true));
+
+static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization",
+  cl::Hidden, cl::ZeroOrMore, cl::init(true));
+
+static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict",
+  cl::Hidden, cl::ZeroOrMore, cl::init(true),
+  cl::desc("Enable checking for cache bank conflicts"));
+
+
+HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
+                                   StringRef FS, const TargetMachine &TM)
+    : HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()),
+      CPUString(Hexagon_MC::selectHexagonCPU(CPU)),
+      InstrInfo(initializeSubtargetDependencies(CPU, FS)),
+      RegInfo(getHwMode()), TLInfo(TM, *this),
+      InstrItins(getInstrItineraryForCPU(CPUString)) {
+  // Beware of the default constructor of InstrItineraryData: it will
+  // reset all members to 0.
+  assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");
 }
 
 HexagonSubtarget &
 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
-  CPUString = Hexagon_MC::selectHexagonCPU(getTargetTriple(), CPU);
-
-  static std::map<StringRef, HexagonArchEnum> CpuTable {
-    { "hexagonv4", V4 },
-    { "hexagonv5", V5 },
-    { "hexagonv55", V55 },
-    { "hexagonv60", V60 },
-    { "hexagonv62", V62 },
+  static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
+      {"hexagonv4", Hexagon::ArchEnum::V4},
+      {"hexagonv5", Hexagon::ArchEnum::V5},
+      {"hexagonv55", Hexagon::ArchEnum::V55},
+      {"hexagonv60", Hexagon::ArchEnum::V60},
+      {"hexagonv62", Hexagon::ArchEnum::V62},
+      {"hexagonv65", Hexagon::ArchEnum::V65},
   };
 
-  auto foundIt = CpuTable.find(CPUString);
-  if (foundIt != CpuTable.end())
-    HexagonArchVersion = foundIt->second;
+  auto FoundIt = CpuTable.find(CPUString);
+  if (FoundIt != CpuTable.end())
+    HexagonArchVersion = FoundIt->second;
   else
     llvm_unreachable("Unrecognized Hexagon processor version");
 
-  UseHVXOps = false;
-  UseHVXDblOps = false;
+  UseHVX128BOps = false;
+  UseHVX64BOps = false;
   UseLongCalls = false;
+
+  UseMemOps = DisableMemOps ? false : EnableMemOps;
+  ModeIEEERndNear = EnableIEEERndNear;
+  UseBSBScheduling = hasV60TOps() && EnableBSBSched;
+
   ParseSubtargetFeatures(CPUString, FS);
 
-  if (EnableHexagonHVX.getPosition())
-    UseHVXOps = EnableHexagonHVX;
-  if (EnableHexagonHVXDouble.getPosition())
-    UseHVXDblOps = EnableHexagonHVXDouble;
   if (OverrideLongCalls.getPosition())
     UseLongCalls = OverrideLongCalls;
 
+  FeatureBitset Features = getFeatureBits();
+  if (HexagonDisableDuplex)
+    setFeatureBits(Features.set(Hexagon::FeatureDuplex, false));
+  setFeatureBits(Hexagon_MC::completeHVXFeatures(Features));
+
   return *this;
 }
 
-HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
-                                   StringRef FS, const TargetMachine &TM)
-    : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
-      InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {
-  initializeEnvironment();
+void HexagonSubtarget::UsrOverflowMutation::apply(ScheduleDAGInstrs *DAG) {
+  for (SUnit &SU : DAG->SUnits) {
+    if (!SU.isInstr())
+      continue;
+    SmallVector<SDep, 4> Erase;
+    for (auto &D : SU.Preds)
+      if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
+        Erase.push_back(D);
+    for (auto &E : Erase)
+      SU.removePred(E);
+  }
+}
 
-  // Initialize scheduling itinerary for the specified CPU.
-  InstrItins = getInstrItineraryForCPU(CPUString);
+void HexagonSubtarget::HVXMemLatencyMutation::apply(ScheduleDAGInstrs *DAG) {
+  for (SUnit &SU : DAG->SUnits) {
+    // Update the latency of chain edges between v60 vector load or store
+    // instructions to be 1. These instruction cannot be scheduled in the
+    // same packet.
+    MachineInstr &MI1 = *SU.getInstr();
+    auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
+    bool IsStoreMI1 = MI1.mayStore();
+    bool IsLoadMI1 = MI1.mayLoad();
+    if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
+      continue;
+    for (SDep &SI : SU.Succs) {
+      if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
+        continue;
+      MachineInstr &MI2 = *SI.getSUnit()->getInstr();
+      if (!QII->isHVXVec(MI2))
+        continue;
+      if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
+        SI.setLatency(1);
+        SU.setHeightDirty();
+        // Change the dependence in the opposite direction too.
+        for (SDep &PI : SI.getSUnit()->Preds) {
+          if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
+            continue;
+          PI.setLatency(1);
+          SI.getSUnit()->setDepthDirty();
+        }
+      }
+    }
+  }
+}
 
-  // UseMemOps on by default unless disabled explicitly
-  if (DisableMemOps)
-    UseMemOps = false;
-  else if (EnableMemOps)
-    UseMemOps = true;
-  else
-    UseMemOps = false;
+// Check if a call and subsequent A2_tfrpi instructions should maintain
+// scheduling affinity. We are looking for the TFRI to be consumed in
+// the next instruction. This should help reduce the instances of
+// double register pairs being allocated and scheduled before a call
+// when not used until after the call. This situation is exacerbated
+// by the fact that we allocate the pair from the callee saves list,
+// leading to excess spills and restores.
+bool HexagonSubtarget::CallMutation::shouldTFRICallBind(
+      const HexagonInstrInfo &HII, const SUnit &Inst1,
+      const SUnit &Inst2) const {
+  if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
+    return false;
 
-  if (EnableIEEERndNear)
-    ModeIEEERndNear = true;
-  else
-    ModeIEEERndNear = false;
+  // TypeXTYPE are 64 bit operations.
+  unsigned Type = HII.getType(*Inst2.getInstr());
+  return Type == HexagonII::TypeS_2op || Type == HexagonII::TypeS_3op ||
+         Type == HexagonII::TypeALU64 || Type == HexagonII::TypeM;
+}
 
-  UseBSBScheduling = hasV60TOps() && EnableBSBSched;
+void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAG) {
+  SUnit* LastSequentialCall = nullptr;
+  unsigned VRegHoldingRet = 0;
+  unsigned RetRegister;
+  SUnit* LastUseOfRet = nullptr;
+  auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo();
+  auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
+
+  // Currently we only catch the situation when compare gets scheduled
+  // before preceding call.
+  for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) {
+    // Remember the call.
+    if (DAG->SUnits[su].getInstr()->isCall())
+      LastSequentialCall = &DAG->SUnits[su];
+    // Look for a compare that defines a predicate.
+    else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
+      DAG->SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier));
+    // Look for call and tfri* instructions.
+    else if (SchedPredsCloser && LastSequentialCall && su > 1 && su < e-1 &&
+             shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
+      DAG->SUnits[su].addPred(SDep(&DAG->SUnits[su-1], SDep::Barrier));
+    // Prevent redundant register copies between two calls, which are caused by
+    // both the return value and the argument for the next call being in %r0.
+    // Example:
+    //   1: <call1>
+    //   2: %vreg = COPY %r0
+    //   3: <use of %vreg>
+    //   4: %r0 = ...
+    //   5: <call2>
+    // The scheduler would often swap 3 and 4, so an additional register is
+    // needed. This code inserts a Barrier dependence between 3 & 4 to prevent
+    // this. The same applies for %d0 and %v0/%w0, which are also handled.
+    else if (SchedRetvalOptimization) {
+      const MachineInstr *MI = DAG->SUnits[su].getInstr();
+      if (MI->isCopy() && (MI->readsRegister(Hexagon::R0, &TRI) ||
+                           MI->readsRegister(Hexagon::V0, &TRI)))  {
+        // %vreg = COPY %r0
+        VRegHoldingRet = MI->getOperand(0).getReg();
+        RetRegister = MI->getOperand(1).getReg();
+        LastUseOfRet = nullptr;
+      } else if (VRegHoldingRet && MI->readsVirtualRegister(VRegHoldingRet))
+        // <use of %X>
+        LastUseOfRet = &DAG->SUnits[su];
+      else if (LastUseOfRet && MI->definesRegister(RetRegister, &TRI))
+        // %r0 = ...
+        DAG->SUnits[su].addPred(SDep(LastUseOfRet, SDep::Barrier));
+    }
+  }
+}
+
+void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
+  if (!EnableCheckBankConflict)
+    return;
+
+  const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);
+
+  // Create artificial edges between loads that could likely cause a bank
+  // conflict. Since such loads would normally not have any dependency
+  // between them, we cannot rely on existing edges.
+  for (unsigned i = 0, e = DAG->SUnits.size(); i != e; ++i) {
+    SUnit &S0 = DAG->SUnits[i];
+    MachineInstr &L0 = *S0.getInstr();
+    if (!L0.mayLoad() || L0.mayStore() ||
+        HII.getAddrMode(L0) != HexagonII::BaseImmOffset)
+      continue;
+    int Offset0;
+    unsigned Size0;
+    unsigned Base0 = HII.getBaseAndOffset(L0, Offset0, Size0);
+    // Is the access size is longer than the L1 cache line, skip the check.
+    if (Base0 == 0 || Size0 >= 32)
+      continue;
+    // Scan only up to 32 instructions ahead (to avoid n^2 complexity).
+    for (unsigned j = i+1, m = std::min(i+32, e); j != m; ++j) {
+      SUnit &S1 = DAG->SUnits[j];
+      MachineInstr &L1 = *S1.getInstr();
+      if (!L1.mayLoad() || L1.mayStore() ||
+          HII.getAddrMode(L1) != HexagonII::BaseImmOffset)
+        continue;
+      int Offset1;
+      unsigned Size1;
+      unsigned Base1 = HII.getBaseAndOffset(L1, Offset1, Size1);
+      if (Base1 == 0 || Size1 >= 32 || Base0 != Base1)
+        continue;
+      // Check bits 3 and 4 of the offset: if they differ, a bank conflict
+      // is unlikely.
+      if (((Offset0 ^ Offset1) & 0x18) != 0)
+        continue;
+      // Bits 3 and 4 are the same, add an artificial edge and set extra
+      // latency.
+      SDep A(&S0, SDep::Artificial);
+      A.setLatency(1);
+      S1.addPred(A, true);
+    }
+  }
+}
+
+/// \brief Enable use of alias analysis during code generation (during MI
+/// scheduling, DAGCombine, etc.).
+bool HexagonSubtarget::useAA() const {
+  if (OptLevel != CodeGenOpt::None)
+    return true;
+  return false;
 }
 
 /// \brief Perform target specific adjustments to the latency of a schedule
@@ -204,59 +361,17 @@ void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
   updateLatency(*SrcInst, *DstInst, Dep);
 }
 
-void HexagonSubtarget::HexagonDAGMutation::apply(ScheduleDAGInstrs *DAG) {
-  for (auto &SU : DAG->SUnits) {
-    if (!SU.isInstr())
-      continue;
-    SmallVector<SDep, 4> Erase;
-    for (auto &D : SU.Preds)
-      if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
-        Erase.push_back(D);
-    for (auto &E : Erase)
-      SU.removePred(E);
-  }
-
-  for (auto &SU : DAG->SUnits) {
-    // Update the latency of chain edges between v60 vector load or store
-    // instructions to be 1. These instruction cannot be scheduled in the
-    // same packet.
-    MachineInstr &MI1 = *SU.getInstr();
-    auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
-    bool IsStoreMI1 = MI1.mayStore();
-    bool IsLoadMI1 = MI1.mayLoad();
-    if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
-      continue;
-    for (auto &SI : SU.Succs) {
-      if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
-        continue;
-      MachineInstr &MI2 = *SI.getSUnit()->getInstr();
-      if (!QII->isHVXVec(MI2))
-        continue;
-      if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
-        SI.setLatency(1);
-        SU.setHeightDirty();
-        // Change the dependence in the opposite direction too.
-        for (auto &PI : SI.getSUnit()->Preds) {
-          if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
-            continue;
-          PI.setLatency(1);
-          SI.getSUnit()->setDepthDirty();
-        }
-      }
-    }
-  }
-}
-
 void HexagonSubtarget::getPostRAMutations(
     std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
-  Mutations.push_back(
-      llvm::make_unique<HexagonSubtarget::HexagonDAGMutation>());
+  Mutations.push_back(llvm::make_unique<UsrOverflowMutation>());
+  Mutations.push_back(llvm::make_unique<HVXMemLatencyMutation>());
+  Mutations.push_back(llvm::make_unique<BankConflictMutation>());
 }
 
 void HexagonSubtarget::getSMSMutations(
     std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
-  Mutations.push_back(
-      llvm::make_unique<HexagonSubtarget::HexagonDAGMutation>());
+  Mutations.push_back(llvm::make_unique<UsrOverflowMutation>());
+  Mutations.push_back(llvm::make_unique<HVXMemLatencyMutation>());
 }
 
 // Pin the vtable to this file.
diff --git a/lib/Target/Hexagon/HexagonSubtarget.h b/lib/Target/Hexagon/HexagonSubtarget.h
index 753dca000065..678ef210d0ae 100644
--- a/lib/Target/Hexagon/HexagonSubtarget.h
+++ b/lib/Target/Hexagon/HexagonSubtarget.h
@@ -14,15 +14,17 @@
 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
 
+#include "HexagonDepArch.h"
 #include "HexagonFrameLowering.h"
-#include "HexagonInstrInfo.h"
 #include "HexagonISelLowering.h"
+#include "HexagonInstrInfo.h"
+#include "HexagonRegisterInfo.h"
 #include "HexagonSelectionDAGInfo.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/ScheduleDAGMutation.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/MC/MCInstrItineraries.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
 #include <memory>
 #include <string>
 #include <vector>
@@ -44,33 +46,45 @@ class Triple;
 class HexagonSubtarget : public HexagonGenSubtargetInfo {
   virtual void anchor();
 
-  bool UseMemOps, UseHVXOps, UseHVXDblOps;
+  bool UseMemOps, UseHVX64BOps, UseHVX128BOps;
   bool UseLongCalls;
   bool ModeIEEERndNear;
 
+  bool HasMemNoShuf = false;
+  bool EnableDuplex = false;
 public:
-#include "HexagonDepArch.h"
-
-  HexagonArchEnum HexagonArchVersion;
+  Hexagon::ArchEnum HexagonArchVersion;
+  Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::V4;
+  CodeGenOpt::Level OptLevel;
   /// True if the target should use Back-Skip-Back scheduling. This is the
   /// default for V60.
   bool UseBSBScheduling;
 
-  class HexagonDAGMutation : public ScheduleDAGMutation {
-  public:
+  struct UsrOverflowMutation : public ScheduleDAGMutation {
+    void apply(ScheduleDAGInstrs *DAG) override;
+  };
+  struct HVXMemLatencyMutation : public ScheduleDAGMutation {
+    void apply(ScheduleDAGInstrs *DAG) override;
+  };
+  struct CallMutation : public ScheduleDAGMutation {
+    void apply(ScheduleDAGInstrs *DAG) override;
+  private:
+    bool shouldTFRICallBind(const HexagonInstrInfo &HII,
+          const SUnit &Inst1, const SUnit &Inst2) const;
+  };
+  struct BankConflictMutation : public ScheduleDAGMutation {
     void apply(ScheduleDAGInstrs *DAG) override;
   };
 
 private:
   std::string CPUString;
   HexagonInstrInfo InstrInfo;
+  HexagonRegisterInfo RegInfo;
   HexagonTargetLowering TLInfo;
   HexagonSelectionDAGInfo TSInfo;
   HexagonFrameLowering FrameLowering;
   InstrItineraryData InstrItins;
 
-  void initializeEnvironment();
-
 public:
   HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
                    const TargetMachine &TM);
@@ -82,7 +96,7 @@ public:
   }
   const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const HexagonRegisterInfo *getRegisterInfo() const override {
-    return &InstrInfo.getRegisterInfo();
+    return &RegInfo;
   }
   const HexagonTargetLowering *getTargetLowering() const override {
     return &TLInfo;
@@ -102,19 +116,42 @@ public:
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   bool useMemOps() const { return UseMemOps; }
-  bool hasV5TOps() const { return getHexagonArchVersion() >= V5; }
-  bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; }
-  bool hasV55TOps() const { return getHexagonArchVersion() >= V55; }
-  bool hasV55TOpsOnly() const { return getHexagonArchVersion() == V55; }
-  bool hasV60TOps() const { return getHexagonArchVersion() >= V60; }
-  bool hasV60TOpsOnly() const { return getHexagonArchVersion() == V60; }
-  bool hasV62TOps() const { return getHexagonArchVersion() >= V62; }
-  bool hasV62TOpsOnly() const { return getHexagonArchVersion() == V62; }
+  bool hasV5TOps() const {
+    return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
+  }
+  bool hasV5TOpsOnly() const {
+    return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
+  }
+  bool hasV55TOps() const {
+    return getHexagonArchVersion() >= Hexagon::ArchEnum::V55;
+  }
+  bool hasV55TOpsOnly() const {
+    return getHexagonArchVersion() == Hexagon::ArchEnum::V55;
+  }
+  bool hasV60TOps() const {
+    return getHexagonArchVersion() >= Hexagon::ArchEnum::V60;
+  }
+  bool hasV60TOpsOnly() const {
+    return getHexagonArchVersion() == Hexagon::ArchEnum::V60;
+  }
+  bool hasV62TOps() const {
+    return getHexagonArchVersion() >= Hexagon::ArchEnum::V62;
+  }
+  bool hasV62TOpsOnly() const {
+    return getHexagonArchVersion() == Hexagon::ArchEnum::V62;
+  }
+  bool hasV65TOps() const {
+    return getHexagonArchVersion() >= Hexagon::ArchEnum::V65;
+  }
+  bool hasV65TOpsOnly() const {
+    return getHexagonArchVersion() == Hexagon::ArchEnum::V65;
+  }
 
   bool modeIEEERndNear() const { return ModeIEEERndNear; }
-  bool useHVXOps() const { return UseHVXOps; }
-  bool useHVXDblOps() const { return UseHVXOps && UseHVXDblOps; }
-  bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; }
+  bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }
+  bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
+  bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
+  bool hasMemNoShuf() const { return HasMemNoShuf; }
   bool useLongCalls() const { return UseLongCalls; }
   bool usePredicatedCalls() const;
 
@@ -138,7 +175,7 @@ public:
     return Hexagon_SMALL_DATA_THRESHOLD;
   }
 
-  const HexagonArchEnum &getHexagonArchVersion() const {
+  const Hexagon::ArchEnum &getHexagonArchVersion() const {
     return HexagonArchVersion;
   }
 
@@ -150,10 +187,33 @@ public:
       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
       const override;
 
+  /// \brief Enable use of alias analysis during code generation (during MI
+  /// scheduling, DAGCombine, etc.).
+  bool useAA() const override;
+
   /// \brief Perform target specific adjustments to the latency of a schedule
   /// dependency.
   void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
 
+  unsigned getVectorLength() const {
+    assert(useHVXOps());
+    if (useHVX64BOps())
+      return 64;
+    if (useHVX128BOps())
+      return 128;
+    llvm_unreachable("Invalid HVX vector length settings");
+  }
+
+  bool isHVXVectorType(MVT VecTy) const {
+    if (!VecTy.isVector() || !useHVXOps())
+      return false;
+    unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
+    if (ElemWidth < 8 || ElemWidth > 64)
+      return false;
+    unsigned VecWidth = VecTy.getSizeInBits();
+    return VecWidth == 8*getVectorLength() || VecWidth == 16*getVectorLength();
+  }
+
   unsigned getL1CacheLineSize() const;
   unsigned getL1PrefetchDistance() const;
 
diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 7d88b51f32dd..0c40a7b8f382 100644
--- a/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -28,6 +28,9 @@
 
 using namespace llvm;
 
+static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
+  cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
+
 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
   cl::init(true), cl::desc("Enable RDF-based optimizations"));
 
@@ -91,6 +94,10 @@ static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
   cl::Hidden, cl::ZeroOrMore, cl::init(false),
   cl::desc("Enable Hexagon Vector print instr pass"));
 
+static cl::opt<bool> EnableTrapUnreachable("hexagon-trap-unreachable",
+  cl::Hidden, cl::ZeroOrMore, cl::init(false),
+  cl::desc("Enable generating trap for unreachable"));
+
 /// HexagonTargetMachineModule - Note that this is used on hosts that
 /// cannot link in a library unless there are references into the
 /// library.  In particular, it seems that it is not possible to get
@@ -100,7 +107,13 @@ extern "C" int HexagonTargetMachineModule;
 int HexagonTargetMachineModule = 0;
 
 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
-  return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
+  ScheduleDAGMILive *DAG =
+    new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
+  DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
+  DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
+  DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
+  DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
+  return DAG;
 }
 
 static MachineSchedRegistry
@@ -109,23 +122,31 @@ SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
 
 namespace llvm {
   extern char &HexagonExpandCondsetsID;
+  void initializeHexagonConstExtendersPass(PassRegistry&);
+  void initializeHexagonEarlyIfConversionPass(PassRegistry&);
   void initializeHexagonExpandCondsetsPass(PassRegistry&);
   void initializeHexagonGenMuxPass(PassRegistry&);
+  void initializeHexagonHardwareLoopsPass(PassRegistry&);
   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
+  void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
   void initializeHexagonNewValueJumpPass(PassRegistry&);
   void initializeHexagonOptAddrModePass(PassRegistry&);
   void initializeHexagonPacketizerPass(PassRegistry&);
+  void initializeHexagonRDFOptPass(PassRegistry&);
   Pass *createHexagonLoopIdiomPass();
+  Pass *createHexagonVectorLoopCarriedReusePass();
 
   FunctionPass *createHexagonBitSimplify();
   FunctionPass *createHexagonBranchRelaxation();
   FunctionPass *createHexagonCallFrameInformation();
   FunctionPass *createHexagonCFGOptimizer();
   FunctionPass *createHexagonCommonGEP();
+  FunctionPass *createHexagonConstExtenders();
   FunctionPass *createHexagonConstPropagationPass();
   FunctionPass *createHexagonCopyToCombine();
   FunctionPass *createHexagonEarlyIfConversion();
   FunctionPass *createHexagonFixupHwLoops();
+  FunctionPass *createHexagonGatherPacketize();
   FunctionPass *createHexagonGenExtract();
   FunctionPass *createHexagonGenInsert();
   FunctionPass *createHexagonGenMux();
@@ -152,34 +173,48 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
   return *RM;
 }
 
+static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
+  if (CM)
+    return *CM;
+  return CodeModel::Small;
+}
+
 extern "C" void LLVMInitializeHexagonTarget() {
   // Register the target.
   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
+  initializeHexagonConstExtendersPass(PR);
+  initializeHexagonEarlyIfConversionPass(PR);
   initializeHexagonGenMuxPass(PR);
+  initializeHexagonHardwareLoopsPass(PR);
   initializeHexagonLoopIdiomRecognizePass(PR);
+  initializeHexagonVectorLoopCarriedReusePass(PR);
   initializeHexagonNewValueJumpPass(PR);
   initializeHexagonOptAddrModePass(PR);
   initializeHexagonPacketizerPass(PR);
+  initializeHexagonRDFOptPass(PR);
 }
 
 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
-                                           CodeModel::Model CM,
-                                           CodeGenOpt::Level OL)
+                                           Optional<CodeModel::Model> CM,
+                                           CodeGenOpt::Level OL, bool JIT)
     // Specify the vector alignment explicitly. For v512x1, the calculated
     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
     // the required minimum of 64 bytes.
     : LLVMTargetMachine(
-          T, "e-m:e-p:32:32:32-a:0-n16:32-"
-             "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
-             "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
-          TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
-          (HexagonNoOpt ? CodeGenOpt::None : OL)),
+          T,
+          "e-m:e-p:32:32:32-a:0-n16:32-"
+          "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
+          "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
+          TT, CPU, FS, Options, getEffectiveRelocModel(RM),
+          getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
       TLOF(make_unique<HexagonTargetObjectFile>()) {
+  if (EnableTrapUnreachable)
+    this->Options.TrapUnreachable = true;
   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
   initAsmInfo();
 }
@@ -216,6 +251,11 @@ void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
       PM.add(createHexagonLoopIdiomPass());
     });
+  PMB.addExtension(
+    PassManagerBuilder::EP_LoopOptimizerEnd,
+    [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
+      PM.add(createHexagonVectorLoopCarriedReusePass());
+    });
 }
 
 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
@@ -311,6 +351,8 @@ bool HexagonPassConfig::addInstSelector() {
 
 void HexagonPassConfig::addPreRegAlloc() {
   if (getOptLevel() != CodeGenOpt::None) {
+    if (EnableCExtOpt)
+      addPass(createHexagonConstExtenders());
     if (EnableExpandCondsets)
       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
     if (!DisableStoreWidening)
@@ -355,9 +397,15 @@ void HexagonPassConfig::addPreEmitPass() {
     // Generate MUX from pairs of conditional transfers.
     if (EnableGenMux)
       addPass(createHexagonGenMux());
+  }
+
+  // Create packets for 2 instructions that consitute a gather instruction.
+  // Do this regardless of the opt level.
+  addPass(createHexagonGatherPacketize(), false);
 
+  if (!NoOpt)
     addPass(createHexagonPacketizer(), false);
-  }
+
   if (EnableVectorPrint)
     addPass(createHexagonVectorPrint(), false);
 
diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h
index 3d01929fbfb8..acd41f920b53 100644
--- a/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -30,8 +30,8 @@ class HexagonTargetMachine : public LLVMTargetMachine {
 public:
   HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
-                       Optional<Reloc::Model> RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
+                       Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
+                       CodeGenOpt::Level OL, bool JIT);
   ~HexagonTargetMachine() override;
   const HexagonSubtarget *getSubtargetImpl(const Function &F) const override;
 
diff --git a/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
index aac810e29fe9..d638503990ad 100644
--- a/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
+++ b/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
@@ -1,4 +1,4 @@
-//===-- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass --------===//
+//===- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass ---------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -14,8 +14,13 @@
 //===----------------------------------------------------------------------===//
 
 #include "HexagonTargetTransformInfo.h"
+#include "HexagonSubtarget.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/IR/InstrTypes.h"
 #include "llvm/IR/Instructions.h"
-#include "llvm/Support/Debug.h"
+#include "llvm/IR/User.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
diff --git a/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/lib/Target/Hexagon/HexagonTargetTransformInfo.h
index ab5a6e07d873..d2cd05012afa 100644
--- a/lib/Target/Hexagon/HexagonTargetTransformInfo.h
+++ b/lib/Target/Hexagon/HexagonTargetTransformInfo.h
@@ -1,4 +1,4 @@
-//===-- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass --------===//
+//==- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass -*- C++ -*-==//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -17,16 +17,24 @@
 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
 
 #include "Hexagon.h"
+#include "HexagonSubtarget.h"
 #include "HexagonTargetMachine.h"
+#include "llvm/ADT/ArrayRef.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/BasicTTIImpl.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/IR/Function.h"
 
 namespace llvm {
 
+class Loop;
+class ScalarEvolution;
+class User;
+class Value;
+
 class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
-  typedef BasicTTIImplBase<HexagonTTIImpl> BaseT;
-  typedef TargetTransformInfo TTI;
+  using BaseT = BasicTTIImplBase<HexagonTTIImpl>;
+  using TTI = TargetTransformInfo;
+
   friend BaseT;
 
   const HexagonSubtarget *ST;
@@ -70,4 +78,4 @@ public:
 
 } // end namespace llvm
 
-#endif
+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index a3021e3dfe43..c2404235091c 100644
--- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -1,4 +1,4 @@
-//===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
+//===- HexagonPacketizer.cpp - VLIW packetizer ----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -16,18 +16,39 @@
 // prune the dependence.
 //
 //===----------------------------------------------------------------------===//
+
 #include "HexagonVLIWPacketizer.h"
+#include "Hexagon.h"
+#include "HexagonInstrInfo.h"
 #include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
-#include "HexagonTargetMachine.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseSet.h"
+#include "llvm/ADT/STLExtras.h"
 #include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
 #include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBundle.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+#include <cstdint>
+#include <iterator>
 
 using namespace llvm;
 
@@ -37,6 +58,10 @@ static cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden,
   cl::ZeroOrMore, cl::init(false),
   cl::desc("Disable Hexagon packetizer pass"));
 
+cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden,
+  cl::ZeroOrMore, cl::init(true),
+  cl::desc("Allow slot1 store and slot0 load"));
+
 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
   cl::ZeroOrMore, cl::Hidden, cl::init(true),
   cl::desc("Allow non-solo packetization of volatile memory references"));
@@ -51,15 +76,18 @@ static cl::opt<bool> DisableVecDblNVStores("disable-vecdbl-nv-stores",
 extern cl::opt<bool> ScheduleInlineAsm;
 
 namespace llvm {
-  FunctionPass *createHexagonPacketizer();
-  void initializeHexagonPacketizerPass(PassRegistry&);
-}
 
+FunctionPass *createHexagonPacketizer();
+void initializeHexagonPacketizerPass(PassRegistry&);
+
+} // end namespace llvm
 
 namespace {
+
   class HexagonPacketizer : public MachineFunctionPass {
   public:
     static char ID;
+
     HexagonPacketizer() : MachineFunctionPass(ID) {}
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
@@ -72,8 +100,10 @@ namespace {
       AU.addPreserved<MachineLoopInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
+
     StringRef getPassName() const override { return "Hexagon Packetizer"; }
     bool runOnMachineFunction(MachineFunction &Fn) override;
+
     MachineFunctionProperties getRequiredProperties() const override {
       return MachineFunctionProperties().set(
           MachineFunctionProperties::Property::NoVRegs);
@@ -84,8 +114,9 @@ namespace {
     const HexagonRegisterInfo *HRI;
   };
 
-  char HexagonPacketizer::ID = 0;
-}
+} // end anonymous namespace
+
+char HexagonPacketizer::ID = 0;
 
 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer",
                       "Hexagon Packetizer", false, false)
@@ -103,7 +134,9 @@ HexagonPacketizerList::HexagonPacketizerList(MachineFunction &MF,
   HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
   HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
 
-  addMutation(make_unique<HexagonSubtarget::HexagonDAGMutation>());
+  addMutation(llvm::make_unique<HexagonSubtarget::UsrOverflowMutation>());
+  addMutation(llvm::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
+  addMutation(llvm::make_unique<HexagonSubtarget::BankConflictMutation>());
 }
 
 // Check if FirstI modifies a register that SecondI reads.
@@ -165,9 +198,8 @@ static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI,
   return NextIt;
 }
 
-
 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
-  if (DisablePacketizer || skipFunction(*MF.getFunction()))
+  if (DisablePacketizer || skipFunction(MF.getFunction()))
     return false;
 
   HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
@@ -185,7 +217,6 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
   // DFA state table should not be empty.
   assert(Packetizer.getResourceTracker() && "Empty DFA table!");
 
-  //
   // Loop over all basic blocks and remove KILL pseudo-instructions
   // These instructions confuse the dependence analysis. Consider:
   // D0 = ...   (Insn 0)
@@ -194,7 +225,6 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
   // Here, Insn 1 will result in the dependence graph not emitting an output
   // dependence between Insn 0 and Insn 2. This can lead to incorrect
   // packetization
-  //
   for (auto &MB : MF) {
     auto End = MB.end();
     auto MI = MB.begin();
@@ -237,7 +267,6 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
   return true;
 }
 
-
 // Reserve resources for a constant extender. Trigger an assertion if the
 // reservation fails.
 void HexagonPacketizerList::reserveResourcesForConstExt() {
@@ -260,7 +289,6 @@ bool HexagonPacketizerList::tryAllocateResourcesForConstExt(bool Reserve) {
   return Avail;
 }
 
-
 bool HexagonPacketizerList::isCallDependent(const MachineInstr &MI,
       SDep::Kind DepType, unsigned DepReg) {
   // Check for LR dependence.
@@ -306,7 +334,6 @@ static bool isControlFlow(const MachineInstr &MI) {
   return MI.getDesc().isTerminator() || MI.getDesc().isCall();
 }
 
-
 /// Returns true if the instruction modifies a callee-saved register.
 static bool doesModifyCalleeSavedReg(const MachineInstr &MI,
                                      const TargetRegisterInfo *TRI) {
@@ -421,7 +448,7 @@ bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI,
 bool HexagonPacketizerList::promoteToDotNew(MachineInstr &MI,
       SDep::Kind DepType, MachineBasicBlock::iterator &MII,
       const TargetRegisterClass* RC) {
-  assert (DepType == SDep::Data);
+  assert(DepType == SDep::Data);
   int NewOpcode;
   if (RC == &Hexagon::PredRegsRegClass)
     NewOpcode = HII->getDotNewPredOp(MI, MBPI);
@@ -451,7 +478,7 @@ bool HexagonPacketizerList::useCallersSP(MachineInstr &MI) {
   unsigned FrameSize = MF.getFrameInfo().getStackSize();
   MachineOperand &Off = MI.getOperand(1);
   int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
-  if (HII->isValidOffset(Opc, NewOff)) {
+  if (HII->isValidOffset(Opc, NewOff, HRI)) {
     Off.setImm(NewOff);
     return true;
   }
@@ -474,6 +501,48 @@ void HexagonPacketizerList::useCalleesSP(MachineInstr &MI) {
   Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
 }
 
+/// Return true if we can update the offset in MI so that MI and MJ
+/// can be packetized together.
+bool HexagonPacketizerList::updateOffset(SUnit *SUI, SUnit *SUJ) {
+  assert(SUI->getInstr() && SUJ->getInstr());
+  MachineInstr &MI = *SUI->getInstr();
+  MachineInstr &MJ = *SUJ->getInstr();
+
+  unsigned BPI, OPI;
+  if (!HII->getBaseAndOffsetPosition(MI, BPI, OPI))
+    return false;
+  unsigned BPJ, OPJ;
+  if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ))
+    return false;
+  unsigned Reg = MI.getOperand(BPI).getReg();
+  if (Reg != MJ.getOperand(BPJ).getReg())
+    return false;
+  // Make sure that the dependences do not restrict adding MI to the packet.
+  // That is, ignore anti dependences, and make sure the only data dependence
+  // involves the specific register.
+  for (const auto &PI : SUI->Preds)
+    if (PI.getKind() != SDep::Anti &&
+        (PI.getKind() != SDep::Data || PI.getReg() != Reg))
+      return false;
+  int Incr;
+  if (!HII->getIncrementValue(MJ, Incr))
+    return false;
+
+  int64_t Offset = MI.getOperand(OPI).getImm();
+  MI.getOperand(OPI).setImm(Offset + Incr);
+  ChangedOffset = Offset;
+  return true;
+}
+
+/// Undo the changed offset. This is needed if the instruction cannot be
+/// added to the current packet due to a different instruction.
+void HexagonPacketizerList::undoChangedOffset(MachineInstr &MI) {
+  unsigned BP, OP;
+  if (!HII->getBaseAndOffsetPosition(MI, BP, OP))
+    llvm_unreachable("Unable to find base and offset operands.");
+  MI.getOperand(OP).setImm(ChangedOffset);
+}
+
 enum PredicateKind {
   PK_False,
   PK_True,
@@ -549,7 +618,6 @@ static const MachineOperand &getAbsSetOperand(const MachineInstr &MI) {
   return MI.getOperand(1);
 }
 
-
 // Can be new value store?
 // Following restrictions are to be respected in convert a store into
 // a new value store.
@@ -709,8 +777,8 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
 
   // If data definition is because of implicit definition of the register,
   // do not newify the store. Eg.
-  // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
-  // S2_storerh_io %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
+  // %r9 = ZXTH %r12, implicit %d6, implicit-def %r12
+  // S2_storerh_io %r8, 2, killed %r12; mem:ST2[%scevgep343]
   for (auto &MO : PacketMI.operands()) {
     if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))
       return false;
@@ -724,8 +792,8 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
   // Handle imp-use of super reg case. There is a target independent side
   // change that should prevent this situation but I am handling it for
   // just-in-case. For example, we cannot newify R2 in the following case:
-  // %R3<def> = A2_tfrsi 0;
-  // S2_storeri_io %R0<kill>, 0, %R2<kill>, %D1<imp-use,kill>;
+  // %r3 = A2_tfrsi 0;
+  // S2_storeri_io killed %r0, 0, killed %r2, implicit killed %d1;
   for (auto &MO : MI.operands()) {
     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
       return false;
@@ -799,7 +867,7 @@ bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI,
 
   const MCInstrDesc& MCID = PI.getDesc();
   const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
-  if (DisableVecDblNVStores && VecRC == &Hexagon::VecDblRegsRegClass)
+  if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass)
     return false;
 
   // predicate .new
@@ -829,12 +897,12 @@ bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI,
 // Go through the packet instructions and search for an anti dependency between
 // them and DepReg from MI. Consider this case:
 // Trying to add
-// a) %R1<def> = TFRI_cdNotPt %P3, 2
+// a) %r1 = TFRI_cdNotPt %p3, 2
 // to this packet:
 // {
-//   b) %P0<def> = C2_or %P3<kill>, %P0<kill>
-//   c) %P3<def> = C2_tfrrp %R23
-//   d) %R1<def> = C2_cmovenewit %P3, 4
+//   b) %p0 = C2_or killed %p3, killed %p0
+//   c) %p3 = C2_tfrrp %r23
+//   d) %r1 = C2_cmovenewit %p3, 4
 //  }
 // The P3 from a) and d) will be complements after
 // a)'s P3 is converted to .new form
@@ -867,7 +935,6 @@ bool HexagonPacketizerList::restrictingDepExistInPacket(MachineInstr &MI,
   return false;
 }
 
-
 /// Gets the predicate register of a predicated instruction.
 static unsigned getPredicatedRegister(MachineInstr &MI,
                                       const HexagonInstrInfo *QII) {
@@ -900,11 +967,11 @@ bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1,
 
   // One corner case deals with the following scenario:
   // Trying to add
-  // a) %R24<def> = A2_tfrt %P0, %R25
+  // a) %r24 = A2_tfrt %p0, %r25
   // to this packet:
   // {
-  //   b) %R25<def> = A2_tfrf %P0, %R24
-  //   c) %P0<def> = C2_cmpeqi %R26, 1
+  //   b) %r25 = A2_tfrf %p0, %r24
+  //   c) %p0 = C2_cmpeqi %r26, 1
   // }
   //
   // On general check a) and b) are complements, but presence of c) will
@@ -960,6 +1027,7 @@ void HexagonPacketizerList::initPacketizerState() {
   GlueToNewValueJump = false;
   GlueAllocframeStore = false;
   FoundSequentialDependence = false;
+  ChangedOffset = INT64_MAX;
 }
 
 // Ignore bundling of pseudo instructions.
@@ -987,6 +1055,10 @@ bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI,
 }
 
 bool HexagonPacketizerList::isSoloInstruction(const MachineInstr &MI) {
+  // Ensure any bundles created by gather packetize remain seperate.
+  if (MI.isBundle())
+    return true;
+
   if (MI.isEHLabel() || MI.isCFIInstruction())
     return true;
 
@@ -1013,7 +1085,6 @@ bool HexagonPacketizerList::isSoloInstruction(const MachineInstr &MI) {
   return false;
 }
 
-
 // Quick check if instructions MI and MJ cannot coexist in the same packet.
 // Limit the tests to be "one-way", e.g.  "if MI->isBranch and MJ->isInlineAsm",
 // but not the symmetric case: "if MJ->isBranch and MI->isInlineAsm".
@@ -1037,11 +1108,12 @@ static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
            MJ.isCall() || MJ.isTerminator();
 
   switch (MI.getOpcode()) {
-  case (Hexagon::S2_storew_locked):
-  case (Hexagon::S4_stored_locked):
-  case (Hexagon::L2_loadw_locked):
-  case (Hexagon::L4_loadd_locked):
-  case (Hexagon::Y4_l2fetch): {
+  case Hexagon::S2_storew_locked:
+  case Hexagon::S4_stored_locked:
+  case Hexagon::L2_loadw_locked:
+  case Hexagon::L4_loadd_locked:
+  case Hexagon::Y4_l2fetch:
+  case Hexagon::Y5_l2fetch: {
     // These instructions can only be grouped with ALU32 or non-floating-point
     // XTYPE instructions.  Since there is no convenient way of identifying fp
     // XTYPE instructions, only allow grouping with ALU32 for now.
@@ -1061,7 +1133,6 @@ static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
   return false;
 }
 
-
 // Full, symmetric check.
 bool HexagonPacketizerList::cannotCoexist(const MachineInstr &MI,
       const MachineInstr &MJ) {
@@ -1105,6 +1176,8 @@ static bool isSystemInstr(const MachineInstr &MI) {
   switch (Opc) {
     case Hexagon::Y2_barrier:
     case Hexagon::Y2_dcfetchbo:
+    case Hexagon::Y4_l2fetch:
+    case Hexagon::Y5_l2fetch:
       return true;
   }
   return false;
@@ -1277,11 +1350,9 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
     if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
       secondRegMatch = true;
 
-    for (auto T : CurrentPacketMIs) {
-      SUnit *PacketSU = MIToSUnit.find(T)->second;
-      MachineInstr &PI = *PacketSU->getInstr();
+    for (MachineInstr *PI : CurrentPacketMIs) {
       // NVJ can not be part of the dual jump - Arch Spec: section 7.8.
-      if (PI.isCall()) {
+      if (PI->isCall()) {
         Dependence = true;
         break;
       }
@@ -1293,22 +1364,22 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
       // 3. If the second operand of the nvj is newified, (which means
       //    first operand is also a reg), first reg is not defined in
       //    the same packet.
-      if (PI.getOpcode() == Hexagon::S2_allocframe || PI.mayStore() ||
-          HII->isLoopN(PI)) {
+      if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||
+          HII->isLoopN(*PI)) {
         Dependence = true;
         break;
       }
       // Check #2/#3.
       const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
-      if (OpR.isReg() && PI.modifiesRegister(OpR.getReg(), HRI)) {
+      if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
         Dependence = true;
         break;
       }
     }
 
+    GlueToNewValueJump = true;
     if (Dependence)
       return false;
-    GlueToNewValueJump = true;
   }
 
   // There no dependency between a prolog instruction and its successor.
@@ -1437,19 +1508,33 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
       // J is first, I is second.
       bool LoadJ = J.mayLoad(), StoreJ = J.mayStore();
       bool LoadI = I.mayLoad(), StoreI = I.mayStore();
-      if (StoreJ) {
-        // Two stores are only allowed on V4+. Load following store is never
-        // allowed.
-        if (LoadI) {
+      bool NVStoreJ = HII->isNewValueStore(J);
+      bool NVStoreI = HII->isNewValueStore(I);
+      bool IsVecJ = HII->isHVXVec(J);
+      bool IsVecI = HII->isHVXVec(I);
+
+      if (Slot1Store && MF.getSubtarget<HexagonSubtarget>().hasV65TOps() &&
+          ((LoadJ && StoreI && !NVStoreI) ||
+           (StoreJ && LoadI && !NVStoreJ)) &&
+          (J.getOpcode() != Hexagon::S2_allocframe &&
+           I.getOpcode() != Hexagon::S2_allocframe) &&
+          (J.getOpcode() != Hexagon::L2_deallocframe &&
+           I.getOpcode() != Hexagon::L2_deallocframe) &&
+          (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI))
+        setmemShufDisabled(true);
+      else
+        if (StoreJ && LoadI && alias(J, I)) {
+          FoundSequentialDependence = true;
+          break;
+        }
+
+      if (!StoreJ)
+        if (!LoadJ || (!LoadI && !StoreI)) {
+          // If J is neither load nor store, assume a dependency.
+          // If J is a load, but I is neither, also assume a dependency.
           FoundSequentialDependence = true;
           break;
         }
-      } else if (!LoadJ || (!LoadI && !StoreI)) {
-        // If J is neither load nor store, assume a dependency.
-        // If J is a load, but I is neither, also assume a dependency.
-        FoundSequentialDependence = true;
-        break;
-      }
       // Store followed by store: not OK on V2.
       // Store followed by load: not OK on all.
       // Load followed by store: OK on all.
@@ -1484,7 +1569,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
 
     // There are certain anti-dependencies that cannot be ignored.
     // Specifically:
-    //   J2_call ... %R0<imp-def>   ; SUJ
+    //   J2_call ... implicit-def %r0   ; SUJ
     //   R0 = ...                   ; SUI
     // Those cannot be packetized together, since the call will observe
     // the effect of the assignment to R0.
@@ -1549,15 +1634,52 @@ bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
     useCalleesSP(I);
     GlueAllocframeStore = false;
   }
+
+  if (ChangedOffset != INT64_MAX)
+    undoChangedOffset(I);
+
+  if (GlueToNewValueJump) {
+    // Putting I and J together would prevent the new-value jump from being
+    // packetized with the producer. In that case I and J must be separated.
+    GlueToNewValueJump = false;
+    return false;
+  }
+
+  if (ChangedOffset == INT64_MAX && updateOffset(SUI, SUJ)) {
+    FoundSequentialDependence = false;
+    Dependence = false;
+    return true;
+  }
+
   return false;
 }
 
+
+bool HexagonPacketizerList::foundLSInPacket() {
+  bool FoundLoad = false;
+  bool FoundStore = false;
+
+  for (auto MJ : CurrentPacketMIs) {
+    unsigned Opc = MJ->getOpcode();
+    if (Opc == Hexagon::S2_allocframe || Opc == Hexagon::L2_deallocframe)
+      continue;
+    if (HII->isMemOp(*MJ))
+      continue;
+    if (MJ->mayLoad())
+      FoundLoad = true;
+    if (MJ->mayStore() && !HII->isNewValueStore(*MJ))
+      FoundStore = true;
+  }
+  return FoundLoad && FoundStore;
+}
+
+
 MachineBasicBlock::iterator
 HexagonPacketizerList::addToPacket(MachineInstr &MI) {
   MachineBasicBlock::iterator MII = MI.getIterator();
   MachineBasicBlock *MBB = MI.getParent();
 
-  if (CurrentPacketMIs.size() == 0)
+  if (CurrentPacketMIs.empty())
     PacketStalls = false;
   PacketStalls |= producesStall(MI);
 
@@ -1627,15 +1749,37 @@ HexagonPacketizerList::addToPacket(MachineInstr &MI) {
 
 void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB,
                                       MachineBasicBlock::iterator MI) {
+  // Replace VLIWPacketizerList::endPacket(MBB, MI).
+
+  bool memShufDisabled = getmemShufDisabled();
+  if (memShufDisabled && !foundLSInPacket()) {
+    setmemShufDisabled(false);
+    DEBUG(dbgs() << "  Not added to NoShufPacket\n");
+  }
+  memShufDisabled = getmemShufDisabled();
+
+  if (CurrentPacketMIs.size() > 1) {
+    MachineBasicBlock::instr_iterator FirstMI(CurrentPacketMIs.front());
+    MachineBasicBlock::instr_iterator LastMI(MI.getInstrIterator());
+    finalizeBundle(*MBB, FirstMI, LastMI);
+
+    auto BundleMII = std::prev(FirstMI);
+    if (memShufDisabled)
+      HII->setBundleNoShuf(BundleMII);
+
+    setmemShufDisabled(false);
+  }
   OldPacketMIs = CurrentPacketMIs;
-  VLIWPacketizerList::endPacket(MBB, MI);
+  CurrentPacketMIs.clear();
+
+  ResourceTracker->clearResources();
+  DEBUG(dbgs() << "End packet\n");
 }
 
 bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) {
   return !producesStall(MI);
 }
 
-
 // V60 forward scheduling.
 bool HexagonPacketizerList::producesStall(const MachineInstr &I) {
   // If the packet already stalls, then ignore the stall from a subsequent
diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.h b/lib/Target/Hexagon/HexagonVLIWPacketizer.h
index adb92b6dc855..764d9ae9059a 100644
--- a/lib/Target/Hexagon/HexagonVLIWPacketizer.h
+++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.h
@@ -1,18 +1,33 @@
-#ifndef HEXAGONVLIWPACKETIZER_H
-#define HEXAGONVLIWPACKETIZER_H
+//===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
+#define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
 
 #include "llvm/CodeGen/DFAPacketizer.h"
-#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
-#include "llvm/CodeGen/ScheduleDAGInstrs.h"
+#include <vector>
 
 namespace llvm {
+
 class HexagonInstrInfo;
 class HexagonRegisterInfo;
+class MachineBranchProbabilityInfo;
+class MachineFunction;
+class MachineInstr;
+class MachineLoopInfo;
+class TargetRegisterClass;
 
 class HexagonPacketizerList : public VLIWPacketizerList {
   // Vector of instructions assigned to the packet that has just been created.
-  std::vector<MachineInstr*> OldPacketMIs;
+  std::vector<MachineInstr *> OldPacketMIs;
 
   // Has the instruction been promoted to a dot-new instruction.
   bool PromotedToDotNew;
@@ -23,6 +38,9 @@ class HexagonPacketizerList : public VLIWPacketizerList {
   // Has the feeder instruction been glued to new value jump.
   bool GlueToNewValueJump;
 
+  // This holds the offset value, when pruning the dependences.
+  int64_t ChangedOffset;
+
   // Check if there is a dependence between some instruction already in this
   // packet and this instruction.
   bool Dependence;
@@ -31,6 +49,8 @@ class HexagonPacketizerList : public VLIWPacketizerList {
   // schedule this instruction.
   bool FoundSequentialDependence;
 
+  bool MemShufDisabled = false;
+
   // Track MIs with ignored dependence.
   std::vector<MachineInstr*> IgnoreDepMIs;
 
@@ -48,7 +68,6 @@ private:
   const HexagonRegisterInfo *HRI;
 
 public:
-  // Ctor.
   HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
                         AliasAnalysis *AA,
                         const MachineBranchProbabilityInfo *MBPI);
@@ -72,6 +91,7 @@ public:
   // and SUJ.
   bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
 
+  bool foundLSInPacket();
   MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
   void endPacket(MachineBasicBlock *MBB,
                  MachineBasicBlock::iterator MI) override;
@@ -80,6 +100,12 @@ public:
   void unpacketizeSoloInstrs(MachineFunction &MF);
 
 protected:
+  bool getmemShufDisabled() {
+    return MemShufDisabled;
+  };
+  void setmemShufDisabled(bool val) {
+    MemShufDisabled = val;
+  };
   bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
                        unsigned DepReg);
   bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
@@ -103,14 +129,18 @@ protected:
   bool demoteToDotOld(MachineInstr &MI);
   bool useCallersSP(MachineInstr &MI);
   void useCalleesSP(MachineInstr &MI);
+  bool updateOffset(SUnit *SUI, SUnit *SUJ);
+  void undoChangedOffset(MachineInstr &MI);
   bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
   bool restrictingDepExistInPacket(MachineInstr&, unsigned);
   bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
   bool isCurifiable(MachineInstr &MI);
   bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
-  inline bool isPromotedToDotNew() const {
+
+  bool isPromotedToDotNew() const {
     return PromotedToDotNew;
   }
+
   bool tryAllocateResourcesForConstExt(bool Reserve);
   bool canReserveResourcesForConstExt();
   void reserveResourcesForConstExt();
@@ -120,6 +150,7 @@ protected:
   bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J);
   bool producesStall(const MachineInstr &MI);
 };
-} // namespace llvm
-#endif // HEXAGONVLIWPACKETIZER_H
 
+} // end namespace llvm
+
+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
diff --git a/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp b/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
new file mode 100644
index 000000000000..39395dbd3aec
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
@@ -0,0 +1,636 @@
+//===- HexagonVectorLoopCarriedReuse.cpp ----------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass removes the computation of provably redundant expressions that have
+// been computed earlier in a previous iteration. It relies on the use of PHIs
+// to identify loop carried dependences. This is scalar replacement for vector
+// types.
+//
+//-----------------------------------------------------------------------------
+// Motivation: Consider the case where we have the following loop structure.
+//
+// Loop:
+//  t0 = a[i];
+//  t1 = f(t0);
+//  t2 = g(t1);
+//  ...
+//  t3 = a[i+1];
+//  t4 = f(t3);
+//  t5 = g(t4);
+//  t6 = op(t2, t5)
+//  cond_branch <Loop>
+//
+// This can be converted to
+//  t00 = a[0];
+//  t10 = f(t00);
+//  t20 = g(t10);
+// Loop:
+//  t2 = t20;
+//  t3 = a[i+1];
+//  t4 = f(t3);
+//  t5 = g(t4);
+//  t6 = op(t2, t5)
+//  t20 = t5
+//  cond_branch <Loop>
+//
+// SROA does a good job of reusing a[i+1] as a[i] in the next iteration.
+// Such a loop comes to this pass in the following form.
+//
+// LoopPreheader:
+//  X0 = a[0];
+// Loop:
+//  X2 = PHI<(X0, LoopPreheader), (X1, Loop)>
+//  t1 = f(X2)   <-- I1
+//  t2 = g(t1)
+//  ...
+//  X1 = a[i+1]
+//  t4 = f(X1)   <-- I2
+//  t5 = g(t4)
+//  t6 = op(t2, t5)
+//  cond_branch <Loop>
+//
+// In this pass, we look for PHIs such as X2 whose incoming values come only
+// from the Loop Preheader and over the backedge and additionaly, both these
+// values are the results of the same operation in terms of opcode. We call such
+// a PHI node a dependence chain or DepChain. In this case, the dependence of X2
+// over X1 is carried over only one iteration and so the DepChain is only one
+// PHI node long.
+//
+// Then, we traverse the uses of the PHI (X2) and the uses of the value of the
+// PHI coming  over the backedge (X1). We stop at the first pair of such users
+// I1 (of X2) and I2 (of X1) that meet the following conditions.
+// 1. I1 and I2 are the same operation, but with different operands.
+// 2. X2 and X1 are used at the same operand number in the two instructions.
+// 3. All other operands Op1 of I1 and Op2 of I2 are also such that there is a
+//    a DepChain from Op1 to Op2 of the same length as that between X2 and X1.
+//
+// We then make the following transformation
+// LoopPreheader:
+//  X0 = a[0];
+//  Y0 = f(X0);
+// Loop:
+//  X2 = PHI<(X0, LoopPreheader), (X1, Loop)>
+//  Y2 = PHI<(Y0, LoopPreheader), (t4, Loop)>
+//  t1 = f(X2)   <-- Will be removed by DCE.
+//  t2 = g(Y2)
+//  ...
+//  X1 = a[i+1]
+//  t4 = f(X1)
+//  t5 = g(t4)
+//  t6 = op(t2, t5)
+//  cond_branch <Loop>
+//
+// We proceed until we cannot find any more such instructions I1 and I2.
+//
+// --- DepChains & Loop carried dependences ---
+// Consider a single basic block loop such as
+//
+// LoopPreheader:
+//  X0 = ...
+//  Y0 = ...
+// Loop:
+//  X2 = PHI<(X0, LoopPreheader), (X1, Loop)>
+//  Y2 = PHI<(Y0, LoopPreheader), (X2, Loop)>
+//  ...
+//  X1 = ...
+//  ...
+//  cond_branch <Loop>
+//
+// Then there is a dependence between X2 and X1 that goes back one iteration,
+// i.e. X1 is used as X2 in the very next iteration. We represent this as a
+// DepChain from X2 to X1 (X2->X1).
+// Similarly, there is a dependence between Y2 and X1 that goes back two
+// iterations. X1 is used as Y2 two iterations after it is computed. This is
+// represented by a DepChain as (Y2->X2->X1).
+//
+// A DepChain has the following properties.
+// 1. Num of edges in DepChain = Number of Instructions in DepChain = Number of
+//    iterations of carried dependence + 1.
+// 2. All instructions in the DepChain except the last are PHIs.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/LoopPass.h"
+#include "llvm/IR/BasicBlock.h"
+#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/Instruction.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/Use.h"
+#include "llvm/IR/User.h"
+#include "llvm/IR/Value.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Transforms/Scalar.h"
+#include <algorithm>
+#include <cassert>
+#include <cstddef>
+#include <map>
+#include <memory>
+#include <set>
+
+using namespace llvm;
+
+#define DEBUG_TYPE "hexagon-vlcr"
+
+STATISTIC(HexagonNumVectorLoopCarriedReuse,
+          "Number of values that were reused from a previous iteration.");
+
+static cl::opt<int> HexagonVLCRIterationLim("hexagon-vlcr-iteration-lim",
+    cl::Hidden,
+    cl::desc("Maximum distance of loop carried dependences that are handled"),
+    cl::init(2), cl::ZeroOrMore);
+
+namespace llvm {
+
+void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
+Pass *createHexagonVectorLoopCarriedReusePass();
+
+} // end namespace llvm
+
+namespace {
+
+  // See info about DepChain in the comments at the top of this file.
+  using ChainOfDependences = SmallVector<Instruction *, 4>;
+
+  class DepChain {
+    ChainOfDependences Chain;
+
+  public:
+    bool isIdentical(DepChain &Other) const {
+      if (Other.size() != size())
+        return false;
+      ChainOfDependences &OtherChain = Other.getChain();
+      for (int i = 0; i < size(); ++i) {
+        if (Chain[i] != OtherChain[i])
+          return false;
+      }
+      return true;
+    }
+
+    ChainOfDependences &getChain() {
+      return Chain;
+    }
+
+    int size() const {
+      return Chain.size();
+    }
+
+    void clear() {
+      Chain.clear();
+    }
+
+    void push_back(Instruction *I) {
+      Chain.push_back(I);
+    }
+
+    int iterations() const {
+      return size() - 1;
+    }
+
+    Instruction *front() const {
+      return Chain.front();
+    }
+
+    Instruction *back() const {
+      return Chain.back();
+    }
+
+    Instruction *&operator[](const int index) {
+      return Chain[index];
+    }
+
+   friend raw_ostream &operator<< (raw_ostream &OS, const DepChain &D);
+  };
+
+  LLVM_ATTRIBUTE_UNUSED
+  raw_ostream &operator<<(raw_ostream &OS, const DepChain &D) {
+    const ChainOfDependences &CD = D.Chain;
+    int ChainSize = CD.size();
+    OS << "**DepChain Start::**\n";
+    for (int i = 0; i < ChainSize -1; ++i) {
+      OS << *(CD[i]) << " -->\n";
+    }
+    OS << *CD[ChainSize-1] << "\n";
+    return OS;
+  }
+
+  struct ReuseValue {
+    Instruction *Inst2Replace = nullptr;
+
+    // In the new PHI node that we'll construct this is the value that'll be
+    // used over the backedge. This is teh value that gets reused from a
+    // previous iteration.
+    Instruction *BackedgeInst = nullptr;
+
+    ReuseValue() = default;
+
+    void reset() { Inst2Replace = nullptr; BackedgeInst = nullptr; }
+    bool isDefined() { return Inst2Replace != nullptr; }
+  };
+
+  LLVM_ATTRIBUTE_UNUSED
+  raw_ostream &operator<<(raw_ostream &OS, const ReuseValue &RU) {
+    OS << "** ReuseValue ***\n";
+    OS << "Instruction to Replace: " << *(RU.Inst2Replace) << "\n";
+    OS << "Backedge Instruction: " << *(RU.BackedgeInst) << "\n";
+    return OS;
+  }
+
+  class HexagonVectorLoopCarriedReuse : public LoopPass {
+  public:
+    static char ID;
+
+    explicit HexagonVectorLoopCarriedReuse() : LoopPass(ID) {
+      PassRegistry *PR = PassRegistry::getPassRegistry();
+      initializeHexagonVectorLoopCarriedReusePass(*PR);
+    }
+
+    StringRef getPassName() const override {
+      return "Hexagon-specific loop carried reuse for HVX vectors";
+    }
+
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
+      AU.addRequired<LoopInfoWrapperPass>();
+      AU.addRequiredID(LoopSimplifyID);
+      AU.addRequiredID(LCSSAID);
+      AU.addPreservedID(LCSSAID);
+      AU.setPreservesCFG();
+    }
+
+    bool runOnLoop(Loop *L, LPPassManager &LPM) override;
+
+  private:
+    SetVector<DepChain *> Dependences;
+    std::set<Instruction *> ReplacedInsts;
+    Loop *CurLoop;
+    ReuseValue ReuseCandidate;
+
+    bool doVLCR();
+    void findLoopCarriedDeps();
+    void findValueToReuse();
+    void findDepChainFromPHI(Instruction *I, DepChain &D);
+    void reuseValue();
+    Value *findValueInBlock(Value *Op, BasicBlock *BB);
+    bool isDepChainBtwn(Instruction *I1, Instruction *I2, int Iters);
+    DepChain *getDepChainBtwn(Instruction *I1, Instruction *I2);
+    bool isEquivalentOperation(Instruction *I1, Instruction *I2);
+    bool canReplace(Instruction *I);
+  };
+
+} // end anonymous namespace
+
+char HexagonVectorLoopCarriedReuse::ID = 0;
+
+INITIALIZE_PASS_BEGIN(HexagonVectorLoopCarriedReuse, "hexagon-vlcr",
+    "Hexagon-specific predictive commoning for HVX vectors", false, false)
+INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(LoopSimplify)
+INITIALIZE_PASS_DEPENDENCY(LCSSAWrapperPass)
+INITIALIZE_PASS_END(HexagonVectorLoopCarriedReuse, "hexagon-vlcr",
+    "Hexagon-specific predictive commoning for HVX vectors", false, false)
+
+bool HexagonVectorLoopCarriedReuse::runOnLoop(Loop *L, LPPassManager &LPM) {
+  if (skipLoop(L))
+    return false;
+
+  if (!L->getLoopPreheader())
+    return false;
+
+  // Work only on innermost loops.
+  if (!L->getSubLoops().empty())
+    return false;
+
+  // Work only on single basic blocks loops.
+  if (L->getNumBlocks() != 1)
+    return false;
+
+  CurLoop = L;
+
+  return doVLCR();
+}
+
+bool HexagonVectorLoopCarriedReuse::isEquivalentOperation(Instruction *I1,
+                                                          Instruction *I2) {
+  if (!I1->isSameOperationAs(I2))
+    return false;
+  // This check is in place specifically for intrinsics. isSameOperationAs will
+  // return two for any two hexagon intrinsics because they are essentially the
+  // same instruciton (CallInst). We need to scratch the surface to see if they
+  // are calls to the same function.
+  if (CallInst *C1 = dyn_cast<CallInst>(I1)) {
+    if (CallInst *C2 = dyn_cast<CallInst>(I2)) {
+      if (C1->getCalledFunction() != C2->getCalledFunction())
+        return false;
+    }
+  }
+
+  // If both the Instructions are of Vector Type and any of the element
+  // is integer constant, check their values too for equivalence.
+  if (I1->getType()->isVectorTy() && I2->getType()->isVectorTy()) {
+    unsigned NumOperands = I1->getNumOperands();
+    for (unsigned i = 0; i < NumOperands; ++i) {
+      ConstantInt *C1 = dyn_cast<ConstantInt>(I1->getOperand(i));
+      ConstantInt *C2 = dyn_cast<ConstantInt>(I2->getOperand(i));
+      if(!C1) continue;
+      assert(C2);
+      if (C1->getSExtValue() != C2->getSExtValue())
+        return false;
+    }
+  }
+
+  return true;
+}
+
+bool HexagonVectorLoopCarriedReuse::canReplace(Instruction *I) {
+  const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
+  if (II &&
+      (II->getIntrinsicID() == Intrinsic::hexagon_V6_hi ||
+       II->getIntrinsicID() == Intrinsic::hexagon_V6_lo)) {
+    DEBUG(dbgs() << "Not considering for reuse: " << *II << "\n");
+    return false;
+  }
+  return true;
+}
+void HexagonVectorLoopCarriedReuse::findValueToReuse() {
+  for (auto *D : Dependences) {
+    DEBUG(dbgs() << "Processing dependence " << *(D->front()) << "\n");
+    if (D->iterations() > HexagonVLCRIterationLim) {
+      DEBUG(dbgs() <<
+            ".. Skipping because number of iterations > than the limit\n");
+      continue;
+    }
+
+    PHINode *PN = cast<PHINode>(D->front());
+    Instruction *BEInst = D->back();
+    int Iters = D->iterations();
+    BasicBlock *BB = PN->getParent();
+    DEBUG(dbgs() << "Checking if any uses of " << *PN << " can be reused\n");
+
+    SmallVector<Instruction *, 4> PNUsers;
+    for (auto UI = PN->use_begin(), E = PN->use_end(); UI != E; ++UI) {
+      Use &U = *UI;
+      Instruction *User = cast<Instruction>(U.getUser());
+
+      if (User->getParent() != BB)
+        continue;
+      if (ReplacedInsts.count(User)) {
+        DEBUG(dbgs() << *User << " has already been replaced. Skipping...\n");
+        continue;
+      }
+      if (isa<PHINode>(User))
+        continue;
+      if (User->mayHaveSideEffects())
+        continue;
+      if (!canReplace(User))
+        continue;
+
+      PNUsers.push_back(User);
+    }
+    DEBUG(dbgs() << PNUsers.size() << " use(s) of the PHI in the block\n");
+
+    // For each interesting use I of PN, find an Instruction BEUser that
+    // performs the same operation as I on BEInst and whose other operands,
+    // if any, can also be rematerialized in OtherBB. We stop when we find the
+    // first such Instruction BEUser. This is because once BEUser is
+    // rematerialized in OtherBB, we may find more such "fixup" opportunities
+    // in this block. So, we'll start over again.
+    for (Instruction *I : PNUsers) {
+      for (auto UI = BEInst->use_begin(), E = BEInst->use_end(); UI != E;
+           ++UI) {
+        Use &U = *UI;
+        Instruction *BEUser = cast<Instruction>(U.getUser());
+
+        if (BEUser->getParent() != BB)
+          continue;
+        if (!isEquivalentOperation(I, BEUser))
+          continue;
+
+        int NumOperands = I->getNumOperands();
+
+        for (int OpNo = 0; OpNo < NumOperands; ++OpNo) {
+          Value *Op = I->getOperand(OpNo);
+          Instruction *OpInst = dyn_cast<Instruction>(Op);
+          if (!OpInst)
+            continue;
+
+          Value *BEOp = BEUser->getOperand(OpNo);
+          Instruction *BEOpInst = dyn_cast<Instruction>(BEOp);
+
+          if (!isDepChainBtwn(OpInst, BEOpInst, Iters)) {
+            BEUser = nullptr;
+            break;
+          }
+        }
+        if (BEUser) {
+          DEBUG(dbgs() << "Found Value for reuse.\n");
+          ReuseCandidate.Inst2Replace = I;
+          ReuseCandidate.BackedgeInst = BEUser;
+          return;
+        } else
+          ReuseCandidate.reset();
+      }
+    }
+  }
+  ReuseCandidate.reset();
+}
+
+Value *HexagonVectorLoopCarriedReuse::findValueInBlock(Value *Op,
+                                                       BasicBlock *BB) {
+  PHINode *PN = dyn_cast<PHINode>(Op);
+  assert(PN);
+  Value *ValueInBlock = PN->getIncomingValueForBlock(BB);
+  return ValueInBlock;
+}
+
+void HexagonVectorLoopCarriedReuse::reuseValue() {
+  DEBUG(dbgs() << ReuseCandidate);
+  Instruction *Inst2Replace = ReuseCandidate.Inst2Replace;
+  Instruction *BEInst = ReuseCandidate.BackedgeInst;
+  int NumOperands = Inst2Replace->getNumOperands();
+  std::map<Instruction *, DepChain *> DepChains;
+  int Iterations = -1;
+  BasicBlock *LoopPH = CurLoop->getLoopPreheader();
+
+  for (int i = 0; i < NumOperands; ++i) {
+    Instruction *I = dyn_cast<Instruction>(Inst2Replace->getOperand(i));
+    if(!I)
+      continue;
+    else {
+      Instruction *J = cast<Instruction>(BEInst->getOperand(i));
+      DepChain *D = getDepChainBtwn(I, J);
+
+      assert(D &&
+             "No DepChain between corresponding operands in ReuseCandidate\n");
+      if (Iterations == -1)
+        Iterations = D->iterations();
+      assert(Iterations == D->iterations() && "Iterations mismatch");
+      DepChains[I] = D;
+    }
+  }
+
+  DEBUG(dbgs() << "reuseValue is making the following changes\n");
+
+  SmallVector<Instruction *, 4> InstsInPreheader;
+  for (int i = 0; i < Iterations; ++i) {
+    Instruction *InstInPreheader = Inst2Replace->clone();
+    SmallVector<Value *, 4> Ops;
+    for (int j = 0; j < NumOperands; ++j) {
+      Instruction *I = dyn_cast<Instruction>(Inst2Replace->getOperand(j));
+      if (!I)
+        continue;
+      // Get the DepChain corresponding to this operand.
+      DepChain &D = *DepChains[I];
+      // Get the PHI for the iteration number and find
+      // the incoming value from the Loop Preheader for
+      // that PHI.
+      Value *ValInPreheader = findValueInBlock(D[i], LoopPH);
+      InstInPreheader->setOperand(j, ValInPreheader);
+    }
+    InstsInPreheader.push_back(InstInPreheader);
+    InstInPreheader->setName(Inst2Replace->getName() + ".hexagon.vlcr");
+    InstInPreheader->insertBefore(LoopPH->getTerminator());
+    DEBUG(dbgs() << "Added " << *InstInPreheader << " to " << LoopPH->getName()
+          << "\n");
+  }
+  BasicBlock *BB = BEInst->getParent();
+  IRBuilder<> IRB(BB);
+  IRB.SetInsertPoint(BB->getFirstNonPHI());
+  Value *BEVal = BEInst;
+  PHINode *NewPhi;
+  for (int i = Iterations-1; i >=0 ; --i) {
+    Instruction *InstInPreheader = InstsInPreheader[i];
+    NewPhi = IRB.CreatePHI(InstInPreheader->getType(), 2);
+    NewPhi->addIncoming(InstInPreheader, LoopPH);
+    NewPhi->addIncoming(BEVal, BB);
+    DEBUG(dbgs() << "Adding " << *NewPhi << " to " << BB->getName() << "\n");
+    BEVal = NewPhi;
+  }
+  // We are in LCSSA form. So, a value defined inside the Loop is used only
+  // inside the loop. So, the following is safe.
+  Inst2Replace->replaceAllUsesWith(NewPhi);
+  ReplacedInsts.insert(Inst2Replace);
+  ++HexagonNumVectorLoopCarriedReuse;
+}
+
+bool HexagonVectorLoopCarriedReuse::doVLCR() {
+  assert(CurLoop->getSubLoops().empty() &&
+         "Can do VLCR on the innermost loop only");
+  assert((CurLoop->getNumBlocks() == 1) &&
+         "Can do VLCR only on single block loops");
+
+  bool Changed = false;
+  bool Continue;
+
+  DEBUG(dbgs() << "Working on Loop: " << *CurLoop->getHeader() << "\n");
+  do {
+    // Reset datastructures.
+    Dependences.clear();
+    Continue = false;
+
+    findLoopCarriedDeps();
+    findValueToReuse();
+    if (ReuseCandidate.isDefined()) {
+      reuseValue();
+      Changed = true;
+      Continue = true;
+    }
+    llvm::for_each(Dependences, std::default_delete<DepChain>());
+  } while (Continue);
+  return Changed;
+}
+
+void HexagonVectorLoopCarriedReuse::findDepChainFromPHI(Instruction *I,
+                                                        DepChain &D) {
+  PHINode *PN = dyn_cast<PHINode>(I);
+  if (!PN) {
+    D.push_back(I);
+    return;
+  } else {
+    auto NumIncomingValues = PN->getNumIncomingValues();
+    if (NumIncomingValues != 2) {
+      D.clear();
+      return;
+    }
+
+    BasicBlock *BB = PN->getParent();
+    if (BB != CurLoop->getHeader()) {
+      D.clear();
+      return;
+    }
+
+    Value *BEVal = PN->getIncomingValueForBlock(BB);
+    Instruction *BEInst = dyn_cast<Instruction>(BEVal);
+    // This is a single block loop with a preheader, so at least
+    // one value should come over the backedge.
+    assert(BEInst && "There should be a value over the backedge");
+
+    Value *PreHdrVal =
+      PN->getIncomingValueForBlock(CurLoop->getLoopPreheader());
+    if(!PreHdrVal || !isa<Instruction>(PreHdrVal)) {
+      D.clear();
+      return;
+    }
+    D.push_back(PN);
+    findDepChainFromPHI(BEInst, D);
+  }
+}
+
+bool HexagonVectorLoopCarriedReuse::isDepChainBtwn(Instruction *I1,
+                                                      Instruction *I2,
+                                                      int Iters) {
+  for (auto *D : Dependences) {
+    if (D->front() == I1 && D->back() == I2 && D->iterations() == Iters)
+      return true;
+  }
+  return false;
+}
+
+DepChain *HexagonVectorLoopCarriedReuse::getDepChainBtwn(Instruction *I1,
+                                                            Instruction *I2) {
+  for (auto *D : Dependences) {
+    if (D->front() == I1 && D->back() == I2)
+      return D;
+  }
+  return nullptr;
+}
+
+void HexagonVectorLoopCarriedReuse::findLoopCarriedDeps() {
+  BasicBlock *BB = CurLoop->getHeader();
+  for (auto I = BB->begin(), E = BB->end(); I != E && isa<PHINode>(I); ++I) {
+    auto *PN = cast<PHINode>(I);
+    if (!isa<VectorType>(PN->getType()))
+      continue;
+
+    DepChain *D = new DepChain();
+    findDepChainFromPHI(PN, *D);
+    if (D->size() != 0)
+      Dependences.insert(D);
+    else
+      delete D;
+  }
+  DEBUG(dbgs() << "Found " << Dependences.size() << " dependences\n");
+  DEBUG(for (size_t i = 0; i < Dependences.size(); ++i) {
+      dbgs() << *Dependences[i] << "\n";
+    });
+}
+
+Pass *llvm::createHexagonVectorLoopCarriedReusePass() {
+  return new HexagonVectorLoopCarriedReuse();
+}
diff --git a/lib/Target/Hexagon/HexagonVectorPrint.cpp b/lib/Target/Hexagon/HexagonVectorPrint.cpp
index 085d4645df06..ddd668b2cb1e 100644
--- a/lib/Target/Hexagon/HexagonVectorPrint.cpp
+++ b/lib/Target/Hexagon/HexagonVectorPrint.cpp
@@ -1,4 +1,4 @@
-//===-- HexagonVectorPrint.cpp - Generate vector printing instructions -===//
+//===- HexagonVectorPrint.cpp - Generate vector printing instructions -----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -13,8 +13,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "hexagon-vector-print"
-
 #include "HexagonInstrInfo.h"
 #include "HexagonSubtarget.h"
 #include "llvm/ADT/StringRef.h"
@@ -24,6 +22,7 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/InlineAsm.h"
 #include "llvm/Pass.h"
@@ -36,29 +35,30 @@
 
 using namespace llvm;
 
+#define DEBUG_TYPE "hexagon-vector-print"
+
 static cl::opt<bool> TraceHexVectorStoresOnly("trace-hex-vector-stores-only",
   cl::Hidden, cl::ZeroOrMore, cl::init(false),
   cl::desc("Enables tracing of vector stores"));
 
 namespace llvm {
 
-  FunctionPass *createHexagonVectorPrint();
-  void initializeHexagonVectorPrintPass(PassRegistry&);
+FunctionPass *createHexagonVectorPrint();
+void initializeHexagonVectorPrintPass(PassRegistry&);
 
 } // end namespace llvm
 
 namespace {
 
 class HexagonVectorPrint : public MachineFunctionPass {
-  const HexagonSubtarget *QST;
-  const HexagonInstrInfo *QII;
-  const HexagonRegisterInfo *QRI;
+  const HexagonSubtarget *QST = nullptr;
+  const HexagonInstrInfo *QII = nullptr;
+  const HexagonRegisterInfo *QRI = nullptr;
 
 public:
   static char ID;
 
-  HexagonVectorPrint()
-      : MachineFunctionPass(ID), QST(nullptr), QII(nullptr), QRI(nullptr) {
+  HexagonVectorPrint() : MachineFunctionPass(ID) {
     initializeHexagonVectorPrintPass(*PassRegistry::getPassRegistry());
   }
 
@@ -67,10 +67,10 @@ public:
   bool runOnMachineFunction(MachineFunction &Fn) override;
 };
 
-char HexagonVectorPrint::ID = 0;
-
 } // end anonymous namespace
 
+char HexagonVectorPrint::ID = 0;
+
 static bool isVecReg(unsigned Reg) {
   return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31)
       || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15)
@@ -97,7 +97,6 @@ static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg,
                         MachineBasicBlock::instr_iterator I,
                         const DebugLoc &DL, const HexagonInstrInfo *QII,
                         MachineFunction &Fn) {
-
   std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg);
   const char *cstr = Fn.createExternalSymbolName(VDescStr);
   unsigned ExtraInfo = InlineAsm::Extra_HasSideEffects;
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
index 2a0edda8dcee..b3ab6763281c 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
@@ -65,7 +65,8 @@ public:
       OSABI(OSABI), CPU(CPU), MCII(T.createMCInstrInfo()),
       RelaxTarget(new MCInst *), Extender(nullptr) {}
 
-  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
+  std::unique_ptr<MCObjectWriter>
+  createObjectWriter(raw_pwrite_stream &OS) const override {
     return createHexagonELFObjectWriter(OS, OSABI, CPU);
   }
 
@@ -654,7 +655,8 @@ public:
     assert(HexagonMCInstrInfo::isBundle(Inst) &&
            "Hexagon relaxInstruction only works on bundles");
 
-    Res = HexagonMCInstrInfo::createBundle();
+    Res.setOpcode(Hexagon::BUNDLE);
+    Res.addOperand(MCOperand::createImm(Inst.getOperand(0).getImm()));
     // Copy the results into the bundle.
     bool Update = false;
     for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
@@ -768,6 +770,6 @@ MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
                                       const MCTargetOptions &Options) {
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
 
-  StringRef CPUString = Hexagon_MC::selectHexagonCPU(TT, CPU);
+  StringRef CPUString = Hexagon_MC::selectHexagonCPU(CPU);
   return new HexagonAsmBackend(T, TT, OSABI, CPUString);
 }
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
index 7f90e83fc8e9..f5a376033757 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
@@ -1,4 +1,4 @@
-//===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
+//===- HexagonBaseInfo.h - Top level definitions for Hexagon ----*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -18,15 +18,12 @@
 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
 
 #include "HexagonDepITypes.h"
-#include "HexagonMCTargetDesc.h"
-#include "llvm/Support/ErrorHandling.h"
-#include <stdint.h>
+#include "MCTargetDesc/HexagonMCTargetDesc.h"
 
 namespace llvm {
 
 /// HexagonII - This namespace holds all of the target specific flags that
 /// instruction info tracks.
-///
 namespace HexagonII {
   unsigned const TypeCVI_FIRST = TypeCVI_HIST;
   unsigned const TypeCVI_LAST = TypeCVI_VX_LATE;
@@ -48,16 +45,13 @@ namespace HexagonII {
     PostInc        = 6   // Post increment addressing mode
   };
 
-  // MemAccessSize is represented as 1+log2(N) where N is size in bits.
-  enum class MemAccessSize {
-    NoMemAccess = 0,            // Not a memory access instruction.
-    ByteAccess = 1,             // Byte access instruction (memb).
-    HalfWordAccess = 2,         // Half word access instruction (memh).
-    WordAccess = 3,             // Word access instruction (memw).
-    DoubleWordAccess = 4,       // Double word access instruction (memd)
-                    // 5,       // We do not have a 16 byte vector access.
-    Vector64Access = 7,         // 64 Byte vector access instruction (vmem).
-    Vector128Access = 8         // 128 Byte vector access instruction (vmem).
+  enum MemAccessSize {
+    NoMemAccess = 0,
+    ByteAccess,
+    HalfWordAccess,
+    WordAccess,
+    DoubleWordAccess,
+    HVXVectorAccess
   };
 
   // MCInstrDesc TSFlags
@@ -74,8 +68,8 @@ namespace HexagonII {
     SoloAXPos  = 7,
     SoloAXMask = 0x1,
     // Only A-type instruction in first slot or nothing.
-    SoloAin1Pos  = 8,
-    SoloAin1Mask = 0x1,
+    RestrictSlot1AOKPos  = 8,
+    RestrictSlot1AOKMask = 0x1,
 
     // Predicated instructions.
     PredicatedPos  = 9,
@@ -128,6 +122,16 @@ namespace HexagonII {
     ExtentAlignPos  = 33,
     ExtentAlignMask = 0x3,
 
+    CofMax1Pos = 35,
+    CofMax1Mask = 0x1,
+    CofRelax1Pos = 36,
+    CofRelax1Mask = 0x1,
+    CofRelax2Pos = 37,
+    CofRelax2Mask = 0x1,
+
+    RestrictNoSlot1StorePos  = 38,
+    RestrictNoSlot1StoreMask = 0x1,
+
     // Addressing mode for load/store instructions.
     AddrModePos  = 41,
     AddrModeMask = 0x7,
@@ -158,8 +162,9 @@ namespace HexagonII {
     PrefersSlot3Pos = 56,
     PrefersSlot3Mask = 0x1,
 
-    CofMax1Pos = 60,
-    CofMax1Mask = 0x1,
+    // v65
+    HasTmpDstPos = 59,
+    HasTmpDstMask = 0x1,
 
     CVINewPos = 61,
     CVINewMask = 0x1
@@ -266,8 +271,18 @@ namespace HexagonII {
     INST_ICLASS_ALU32_3   = 0xf0000000
   };
 
-} // End namespace HexagonII.
+  LLVM_ATTRIBUTE_UNUSED
+  static unsigned getMemAccessSizeInBytes(MemAccessSize S) {
+    switch (S) {
+      case ByteAccess:        return 1;
+      case HalfWordAccess:    return 2;
+      case WordAccess:        return 4;
+      case DoubleWordAccess:  return 8;
+      default:                return 0;
+    }
+  }
+} // end namespace HexagonII
 
-} // End namespace llvm.
+} // end namespace llvm
 
-#endif
+#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
index b975e3131094..12aa1bd9b2a0 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
@@ -11,6 +11,7 @@
 #include "MCTargetDesc/HexagonFixupKinds.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCELFObjectWriter.h"
+#include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
@@ -297,9 +298,9 @@ unsigned HexagonELFObjectWriter::getRelocType(MCContext &Ctx,
   }
 }
 
-MCObjectWriter *llvm::createHexagonELFObjectWriter(raw_pwrite_stream &OS,
-                                                   uint8_t OSABI,
-                                                   StringRef CPU) {
-  MCELFObjectTargetWriter *MOTW = new HexagonELFObjectWriter(OSABI, CPU);
-  return createELFObjectWriter(MOTW, OS, /*IsLittleEndian*/ true);
+std::unique_ptr<MCObjectWriter>
+llvm::createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
+                                   StringRef CPU) {
+  auto MOTW = llvm::make_unique<HexagonELFObjectWriter>(OSABI, CPU);
+  return createELFObjectWriter(std::move(MOTW), OS, /*IsLittleEndian*/ true);
 }
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
index 3bb658b84451..53f3cba052bc 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
@@ -12,17 +12,20 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "HexagonMCChecker.h"
-
-#include "HexagonBaseInfo.h"
-
+#include "MCTargetDesc/HexagonMCChecker.h"
+#include "Hexagon.h"
+#include "MCTargetDesc/HexagonBaseInfo.h"
+#include "MCTargetDesc/HexagonMCInstrInfo.h"
+#include "MCTargetDesc/HexagonMCShuffler.h"
+#include "MCTargetDesc/HexagonMCTargetDesc.h"
+#include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
-#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Debug.h"
 #include "llvm/Support/SourceMgr.h"
-#include "llvm/Support/raw_ostream.h"
+#include <cassert>
 
 using namespace llvm;
 
@@ -159,7 +162,7 @@ void HexagonMCChecker::init(MCInst const &MCI) {
                isPredicateRegister(*SRI))
         // Some insns produce predicates too late to be used in the same packet.
         LatePreds.insert(*SRI);
-      else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) ==
+      else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) ==
                              HexagonII::TypeCVI_VM_TMP_LD)
         // Temporary loads should be used in the same packet, but don't commit
         // results, so it should be disregarded if another insn changes the same
@@ -167,7 +170,7 @@ void HexagonMCChecker::init(MCInst const &MCI) {
         // TODO: relies on the impossibility of a current and a temporary loads
         // in the same packet.
         TmpDefs.insert(*SRI);
-      else if (i <= 1 && llvm::HexagonMCInstrInfo::hasNewValue2(MCII, MCI))
+      else if (i <= 1 && HexagonMCInstrInfo::hasNewValue2(MCII, MCI))
         // vshuff(Vx, Vy, Rx) <- Vx(0) and Vy(1) are both source and
         // destination registers with this instruction. same for vdeal(Vx,Vy,Rx)
         Uses.insert(*SRI);
@@ -176,35 +179,6 @@ void HexagonMCChecker::init(MCInst const &MCI) {
     }
   }
 
-  // Figure out register definitions that produce new values.
-  if (HexagonMCInstrInfo::hasNewValue(MCII, MCI)) {
-    unsigned R = HexagonMCInstrInfo::getNewValueOperand(MCII, MCI).getReg();
-
-    if (HexagonMCInstrInfo::isCompound(MCII, MCI))
-      compoundRegisterMap(R); // Compound insns have a limited register range.
-
-    for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
-         SRI.isValid(); ++SRI)
-      if (!MCSubRegIterator(*SRI, &RI).isValid())
-        // No super-registers defined indirectly.
-        NewDefs[*SRI].push_back(NewSense::Def(
-            PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),
-            HexagonMCInstrInfo::isFloat(MCII, MCI)));
-
-    // For fairly unique 2-dot-new producers, example:
-    // vdeal(V1, V9, R0) V1.new and V9.new can be used by consumers.
-    if (HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) {
-      unsigned R2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, MCI).getReg();
-
-      bool HasSubRegs = MCSubRegIterator(R2, &RI).isValid();
-      for (MCRegAliasIterator SRI(R2, &RI, !HasSubRegs); SRI.isValid(); ++SRI)
-        if (!MCSubRegIterator(*SRI, &RI).isValid())
-          NewDefs[*SRI].push_back(NewSense::Def(
-              PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),
-              HexagonMCInstrInfo::isFloat(MCII, MCI)));
-    }
-  }
-
   // Figure out definitions of new predicate registers.
   if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
     for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
@@ -214,21 +188,6 @@ void HexagonMCChecker::init(MCInst const &MCI) {
         if (isPredicateRegister(P))
           NewPreds.insert(P);
       }
-
-  // Figure out uses of new values.
-  if (HexagonMCInstrInfo::isNewValue(MCII, MCI)) {
-    unsigned N = HexagonMCInstrInfo::getNewValueOperand(MCII, MCI).getReg();
-
-    if (!MCSubRegIterator(N, &RI).isValid()) {
-      // Super-registers cannot use new values.
-      if (MCID.isBranch())
-        NewUses[N] = NewSense::Jmp(
-            llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNCJ);
-      else
-        NewUses[N] = NewSense::Use(
-            PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI));
-    }
-  }
 }
 
 HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
@@ -239,13 +198,17 @@ HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
   init();
 }
 
+HexagonMCChecker::HexagonMCChecker(HexagonMCChecker const &Other,
+                                   MCSubtargetInfo const &STI,
+                                   bool CopyReportErrors)
+    : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII),
+      STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false) {}
+
 bool HexagonMCChecker::check(bool FullCheck) {
-  bool chkB = checkBranches();
   bool chkP = checkPredicates();
   bool chkNV = checkNewValues();
   bool chkR = checkRegisters();
   bool chkRRO = checkRegistersReadOnly();
-  bool chkELB = checkEndloopBranches();
   checkRegisterCurDefs();
   bool chkS = checkSolo();
   bool chkSh = true;
@@ -255,32 +218,15 @@ bool HexagonMCChecker::check(bool FullCheck) {
   if (FullCheck)
     chkSl = checkSlots();
   bool chkAXOK = checkAXOK();
-  bool chk = chkB && chkP && chkNV && chkR && chkRRO && chkELB && chkS &&
-             chkSh && chkSl && chkAXOK;
+  bool chkCofMax1 = checkCOFMax1();
+  bool chkHWLoop = checkHWLoop();
+  bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl &&
+             chkAXOK && chkCofMax1 && chkHWLoop;
 
   return chk;
 }
 
-bool HexagonMCChecker::checkEndloopBranches() {
-  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
-    MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
-    if (Desc.isBranch() || Desc.isCall()) {
-      auto Inner = HexagonMCInstrInfo::isInnerLoop(MCB);
-      if (Inner || HexagonMCInstrInfo::isOuterLoop(MCB)) {
-        reportError(I.getLoc(),
-                    llvm::Twine("packet marked with `:endloop") +
-                        (Inner ? "0" : "1") + "' " +
-                        "cannot contain instructions that modify register " +
-                        "`" + llvm::Twine(RI.getName(Hexagon::PC)) + "'");
-        return false;
-      }
-    }
-  }
-  return true;
-}
-
-namespace {
-bool isDuplexAGroup(unsigned Opcode) {
+static bool isDuplexAGroup(unsigned Opcode) {
   switch (Opcode) {
   case Hexagon::SA1_addi:
   case Hexagon::SA1_addrx:
@@ -313,7 +259,7 @@ bool isDuplexAGroup(unsigned Opcode) {
   }
 }
 
-bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
+static bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
   unsigned Result = 0;
   unsigned Type = HexagonMCInstrInfo::getType(MCII, ID);
   if (Type == HexagonII::TypeDUPLEX) {
@@ -329,7 +275,6 @@ bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
         (Type != HexagonII::TypeALU64 || HexagonMCInstrInfo::isFloat(MCII, ID));
   return Result != 0;
 }
-} // namespace
 
 bool HexagonMCChecker::checkAXOK() {
   MCInst const *HasSoloAXInst = nullptr;
@@ -344,16 +289,75 @@ bool HexagonMCChecker::checkAXOK() {
     if (&I != HasSoloAXInst && isNeitherAnorX(MCII, I)) {
       reportError(
           HasSoloAXInst->getLoc(),
-          llvm::Twine("Instruction can only be in a packet with ALU or "
-                      "non-FPU XTYPE instructions"));
+          Twine("Instruction can only be in a packet with ALU or non-FPU XTYPE "
+                "instructions"));
       reportError(I.getLoc(),
-                  llvm::Twine("Not an ALU or non-FPU XTYPE instruction"));
+                  Twine("Not an ALU or non-FPU XTYPE instruction"));
+      return false;
+    }
+  }
+  return true;
+}
+
+void HexagonMCChecker::reportBranchErrors() {
+  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
+    MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
+    if (Desc.isBranch() || Desc.isCall() || Desc.isReturn())
+      reportNote(I.getLoc(), "Branching instruction");
+  }
+}
+
+bool HexagonMCChecker::checkHWLoop() {
+  if (!HexagonMCInstrInfo::isInnerLoop(MCB) &&
+      !HexagonMCInstrInfo::isOuterLoop(MCB))
+    return true;
+  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
+    MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
+    if (Desc.isBranch() || Desc.isCall() || Desc.isReturn()) {
+      reportError(MCB.getLoc(),
+                  "Branches cannot be in a packet with hardware loops");
+      reportBranchErrors();
       return false;
     }
   }
   return true;
 }
 
+bool HexagonMCChecker::checkCOFMax1() {
+  SmallVector<MCInst const *, 2> BranchLocations;
+  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
+    MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
+    if (Desc.isBranch() || Desc.isCall() || Desc.isReturn())
+      BranchLocations.push_back(&I);
+  }
+  for (unsigned J = 0, N = BranchLocations.size(); J < N; ++J) {
+    MCInst const &I = *BranchLocations[J];
+    if (HexagonMCInstrInfo::isCofMax1(MCII, I)) {
+      bool Relax1 = HexagonMCInstrInfo::isCofRelax1(MCII, I);
+      bool Relax2 = HexagonMCInstrInfo::isCofRelax2(MCII, I);
+      if (N > 1 && !Relax1 && !Relax2) {
+        reportError(I.getLoc(),
+                    "Instruction may not be in a packet with other branches");
+        reportBranchErrors();
+        return false;
+      }
+      if (N > 1 && J == 0 && !Relax1) {
+        reportError(I.getLoc(),
+                    "Instruction may not be the first branch in packet");
+        reportBranchErrors();
+        return false;
+      }
+      if (N > 1 && J == 1 && !Relax2) {
+        reportError(I.getLoc(),
+                    "Instruction may not be the second branch in packet");
+        reportBranchErrors();
+        return false;
+      }
+    }
+  }
+  return true;
+}
+
 bool HexagonMCChecker::checkSlots() {
   unsigned slotsUsed = 0;
   for (auto HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
@@ -373,45 +377,6 @@ bool HexagonMCChecker::checkSlots() {
   return true;
 }
 
-// Check legal use of branches.
-bool HexagonMCChecker::checkBranches() {
-  if (HexagonMCInstrInfo::isBundle(MCB)) {
-    bool hasConditional = false;
-    unsigned Branches = 0, Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE,
-             Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE;
-
-    for (unsigned i = HexagonMCInstrInfo::bundleInstructionsOffset;
-         i < MCB.size(); ++i) {
-      MCInst const &MCI = *MCB.begin()[i].getInst();
-
-      if (HexagonMCInstrInfo::isImmext(MCI))
-        continue;
-      if (HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch() ||
-          HexagonMCInstrInfo::getDesc(MCII, MCI).isCall()) {
-        ++Branches;
-        if (HexagonMCInstrInfo::isPredicated(MCII, MCI) ||
-            HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) {
-          hasConditional = true;
-          Conditional = i; // Record the position of the conditional branch.
-        } else {
-          Unconditional = i; // Record the position of the unconditional branch.
-        }
-      }
-    }
-
-    if (Branches > 1)
-      if (!hasConditional || Conditional > Unconditional) {
-        // Error out if more than one unconditional branch or
-        // the conditional branch appears after the unconditional one.
-        reportError(
-            "unconditional branch cannot precede another branch in packet");
-        return false;
-      }
-  }
-
-  return true;
-}
-
 // Check legal use of predicate registers.
 bool HexagonMCChecker::checkPredicates() {
   // Check for proper use of new predicate registers.
@@ -445,16 +410,85 @@ bool HexagonMCChecker::checkPredicates() {
 
 // Check legal use of new values.
 bool HexagonMCChecker::checkNewValues() {
-  for (auto &I : NewUses) {
-    unsigned R = I.first;
-    NewSense &US = I.second;
-
-    if (!hasValidNewValueDef(US, NewDefs[R])) {
-      reportErrorNewValue(R);
+  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
+    if (!HexagonMCInstrInfo::isNewValue(MCII, I))
+      continue;
+    auto Consumer = HexagonMCInstrInfo::predicateInfo(MCII, I);
+    bool Branch = HexagonMCInstrInfo::getDesc(MCII, I).isBranch();
+    MCOperand const &Op = HexagonMCInstrInfo::getNewValueOperand(MCII, I);
+    assert(Op.isReg());
+    auto Producer = registerProducer(Op.getReg(), Consumer);
+    if (std::get<0>(Producer) == nullptr) {
+      reportError(I.getLoc(), "New value register consumer has no producer");
+      return false;
+    }
+    if (!RelaxNVChecks) {
+      // Checks that statically prove correct new value consumption
+      if (std::get<2>(Producer).isPredicated() &&
+          (!Consumer.isPredicated() ||
+           llvm::HexagonMCInstrInfo::getType(MCII, I) == HexagonII::TypeNCJ)) {
+        reportNote(
+            std::get<0>(Producer)->getLoc(),
+            "Register producer is predicated and consumer is unconditional");
+        reportError(I.getLoc(),
+                    "Instruction does not have a valid new register producer");
+        return false;
+      }
+      if (std::get<2>(Producer).Register != Hexagon::NoRegister &&
+          std::get<2>(Producer).Register != Consumer.Register) {
+        reportNote(std::get<0>(Producer)->getLoc(),
+                   "Register producer does not use the same predicate "
+                   "register as the consumer");
+        reportError(I.getLoc(),
+                    "Instruction does not have a valid new register producer");
+        return false;
+      }
+    }
+    if (std::get<2>(Producer).Register == Consumer.Register &&
+        Consumer.PredicatedTrue != std::get<2>(Producer).PredicatedTrue) {
+      reportNote(
+          std::get<0>(Producer)->getLoc(),
+          "Register producer has the opposite predicate sense as consumer");
+      reportError(I.getLoc(),
+                  "Instruction does not have a valid new register producer");
+      return false;
+    }
+    MCInstrDesc const &Desc =
+        HexagonMCInstrInfo::getDesc(MCII, *std::get<0>(Producer));
+    if (Desc.OpInfo[std::get<1>(Producer)].RegClass ==
+        Hexagon::DoubleRegsRegClassID) {
+      reportNote(std::get<0>(Producer)->getLoc(),
+                 "Double registers cannot be new-value producers");
+      reportError(I.getLoc(),
+                  "Instruction does not have a valid new register producer");
+      return false;
+    }
+    if ((Desc.mayLoad() && std::get<1>(Producer) == 1) ||
+        (Desc.mayStore() && std::get<1>(Producer) == 0)) {
+      unsigned Mode =
+          HexagonMCInstrInfo::getAddrMode(MCII, *std::get<0>(Producer));
+      StringRef ModeError;
+      if (Mode == HexagonII::AbsoluteSet)
+        ModeError = "Absolute-set";
+      if (Mode == HexagonII::PostInc)
+        ModeError = "Auto-increment";
+      if (!ModeError.empty()) {
+        reportNote(std::get<0>(Producer)->getLoc(),
+                   ModeError + " registers cannot be a new-value "
+                               "producer");
+        reportError(I.getLoc(),
+                    "Instruction does not have a valid new register producer");
+        return false;
+      }
+    }
+    if (Branch && HexagonMCInstrInfo::isFloat(MCII, *std::get<0>(Producer))) {
+      reportNote(std::get<0>(Producer)->getLoc(),
+                 "FPU instructions cannot be new-value producers for jumps");
+      reportError(I.getLoc(),
+                  "Instruction does not have a valid new register producer");
       return false;
     }
   }
-
   return true;
 }
 
@@ -468,7 +502,7 @@ bool HexagonMCChecker::checkRegistersReadOnly() {
       unsigned Register = Operand.getReg();
       if (ReadOnly.find(Register) != ReadOnly.end()) {
         reportError(Inst.getLoc(), "Cannot write to read-only register `" +
-                                       llvm::Twine(RI.getName(Register)) + "'");
+                                       Twine(RI.getName(Register)) + "'");
         return false;
       }
     }
@@ -488,13 +522,41 @@ bool HexagonMCChecker::registerUsed(unsigned Register) {
   return false;
 }
 
+std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
+HexagonMCChecker::registerProducer(
+    unsigned Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) {
+  std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
+      WrongSense;
+  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
+    MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
+    auto ProducerPredicate = HexagonMCInstrInfo::predicateInfo(MCII, I);
+    for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J)
+      for (auto K = MCRegAliasIterator(I.getOperand(J).getReg(), &RI, true);
+           K.isValid(); ++K)
+        if (*K == Register) {
+          if (RelaxNVChecks ||
+              (ProducerPredicate.Register == ConsumerPredicate.Register &&
+               (ProducerPredicate.Register == Hexagon::NoRegister ||
+                ProducerPredicate.PredicatedTrue ==
+                    ConsumerPredicate.PredicatedTrue)))
+            return std::make_tuple(&I, J, ProducerPredicate);
+          std::get<0>(WrongSense) = &I;
+          std::get<1>(WrongSense) = J;
+          std::get<2>(WrongSense) = ProducerPredicate;
+        }
+    if (Register == Hexagon::VTMP && HexagonMCInstrInfo::hasTmpDst(MCII, I))
+      return std::make_tuple(&I, 0, HexagonMCInstrInfo::PredicateInfo());
+  }
+  return WrongSense;
+}
+
 void HexagonMCChecker::checkRegisterCurDefs() {
   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
     if (HexagonMCInstrInfo::isCVINew(MCII, I) &&
         HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) {
       unsigned Register = I.getOperand(0).getReg();
       if (!registerUsed(Register))
-        reportWarning("Register `" + llvm::Twine(RI.getName(Register)) +
+        reportWarning("Register `" + Twine(RI.getName(Register)) +
                       "' used with `.cur' "
                       "but not used in the same packet");
     }
@@ -568,17 +630,16 @@ bool HexagonMCChecker::checkRegisters() {
       // special case for vhist
       bool vHistFound = false;
       for (auto const &HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
-        if (llvm::HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) ==
+        if (HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) ==
             HexagonII::TypeCVI_HIST) {
           vHistFound = true; // vhist() implicitly uses ALL REGxx.tmp
           break;
         }
       }
       // Warn on an unused temporary definition.
-      if (vHistFound == false) {
-        reportWarning("register `" + llvm::Twine(RI.getName(R)) +
-                      "' used with `.tmp' "
-                      "but not used in the same packet");
+      if (!vHistFound) {
+        reportWarning("register `" + Twine(RI.getName(R)) +
+                      "' used with `.tmp' but not used in the same packet");
         return true;
       }
     }
@@ -591,7 +652,7 @@ bool HexagonMCChecker::checkRegisters() {
 bool HexagonMCChecker::checkSolo() {
   if (HexagonMCInstrInfo::bundleSize(MCB) > 1)
     for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
-      if (llvm::HexagonMCInstrInfo::isSolo(MCII, I)) {
+      if (HexagonMCInstrInfo::isSolo(MCII, I)) {
         reportError(I.getLoc(), "Instruction is marked `isSolo' and "
                                 "cannot have other instructions in "
                                 "the same packet");
@@ -638,56 +699,35 @@ void HexagonMCChecker::compoundRegisterMap(unsigned &Register) {
   }
 }
 
-bool HexagonMCChecker::hasValidNewValueDef(const NewSense &Use,
-                                           const NewSenseList &Defs) const {
-  bool Strict = !RelaxNVChecks;
-
-  for (unsigned i = 0, n = Defs.size(); i < n; ++i) {
-    const NewSense &Def = Defs[i];
-    // NVJ cannot use a new FP value [7.6.1]
-    if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0))
-      continue;
-    // If the definition was not predicated, then it does not matter if
-    // the use is.
-    if (Def.PredReg == 0)
-      return true;
-    // With the strict checks, both the definition and the use must be
-    // predicated on the same register and condition.
-    if (Strict) {
-      if (Def.PredReg == Use.PredReg && Def.Cond == Use.Cond)
-        return true;
-    } else {
-      // With the relaxed checks, if the definition was predicated, the only
-      // detectable violation is if the use is predicated on the opposing
-      // condition, otherwise, it's ok.
-      if (Def.PredReg != Use.PredReg || Def.Cond == Use.Cond)
-        return true;
-    }
-  }
-  return false;
-}
-
 void HexagonMCChecker::reportErrorRegisters(unsigned Register) {
-  reportError("register `" + llvm::Twine(RI.getName(Register)) +
+  reportError("register `" + Twine(RI.getName(Register)) +
               "' modified more than once");
 }
 
 void HexagonMCChecker::reportErrorNewValue(unsigned Register) {
-  reportError("register `" + llvm::Twine(RI.getName(Register)) +
+  reportError("register `" + Twine(RI.getName(Register)) +
               "' used with `.new' "
               "but not validly modified in the same packet");
 }
 
-void HexagonMCChecker::reportError(llvm::Twine const &Msg) {
+void HexagonMCChecker::reportError(Twine const &Msg) {
   reportError(MCB.getLoc(), Msg);
 }
 
-void HexagonMCChecker::reportError(SMLoc Loc, llvm::Twine const &Msg) {
+void HexagonMCChecker::reportError(SMLoc Loc, Twine const &Msg) {
   if (ReportErrors)
     Context.reportError(Loc, Msg);
 }
 
-void HexagonMCChecker::reportWarning(llvm::Twine const &Msg) {
+void HexagonMCChecker::reportNote(SMLoc Loc, llvm::Twine const &Msg) {
+  if (ReportErrors) {
+    auto SM = Context.getSourceManager();
+    if (SM)
+      SM->PrintMessage(Loc, SourceMgr::DK_Note, Msg);
+  }
+}
+
+void HexagonMCChecker::reportWarning(Twine const &Msg) {
   if (ReportErrors) {
     auto SM = Context.getSourceManager();
     if (SM)
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
index 027f78b4899c..7577baace20c 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
@@ -1,4 +1,4 @@
-//===----- HexagonMCChecker.h - Instruction bundle checking ---------------===//
+//===- HexagonMCChecker.h - Instruction bundle checking ---------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -12,17 +12,24 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef HEXAGONMCCHECKER_H
-#define HEXAGONMCCHECKER_H
+#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H
+#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H
 
-#include "MCTargetDesc/HexagonMCShuffler.h"
-#include <queue>
+#include "MCTargetDesc/HexagonMCInstrInfo.h"
+#include "MCTargetDesc/HexagonMCTargetDesc.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/SMLoc.h"
 #include <set>
-
-using namespace llvm;
+#include <utility>
 
 namespace llvm {
-class MCOperandInfo;
+
+class MCContext;
+class MCInst;
+class MCInstrInfo;
+class MCRegisterInfo;
+class MCSubtargetInfo;
 
 /// Check for a valid bundle.
 class HexagonMCChecker {
@@ -34,72 +41,36 @@ class HexagonMCChecker {
   bool ReportErrors;
 
   /// Set of definitions: register #, if predicated, if predicated true.
-  typedef std::pair<unsigned, bool> PredSense;
+  using PredSense = std::pair<unsigned, bool>;
   static const PredSense Unconditional;
-  typedef std::multiset<PredSense> PredSet;
-  typedef std::multiset<PredSense>::iterator PredSetIterator;
-
-  typedef llvm::DenseMap<unsigned, PredSet>::iterator DefsIterator;
-  llvm::DenseMap<unsigned, PredSet> Defs;
+  using PredSet = std::multiset<PredSense>;
+  using PredSetIterator = std::multiset<PredSense>::iterator;
 
-  /// Information about how a new-value register is defined or used:
-  ///   PredReg = predicate register, 0 if use/def not predicated,
-  ///   Cond    = true/false for if(PredReg)/if(!PredReg) respectively,
-  ///   IsFloat = true if definition produces a floating point value
-  ///             (not valid for uses),
-  ///   IsNVJ   = true if the use is a new-value branch (not valid for
-  ///             definitions).
-  struct NewSense {
-    unsigned PredReg;
-    bool IsFloat, IsNVJ, Cond;
-    // The special-case "constructors":
-    static NewSense Jmp(bool isNVJ) {
-      NewSense NS = {/*PredReg=*/0, /*IsFloat=*/false, /*IsNVJ=*/isNVJ,
-                     /*Cond=*/false};
-      return NS;
-    }
-    static NewSense Use(unsigned PR, bool True) {
-      NewSense NS = {/*PredReg=*/PR, /*IsFloat=*/false, /*IsNVJ=*/false,
-                     /*Cond=*/True};
-      return NS;
-    }
-    static NewSense Def(unsigned PR, bool True, bool Float) {
-      NewSense NS = {/*PredReg=*/PR, /*IsFloat=*/Float, /*IsNVJ=*/false,
-                     /*Cond=*/True};
-      return NS;
-    }
-  };
-  /// Set of definitions that produce new register:
-  typedef llvm::SmallVector<NewSense, 2> NewSenseList;
-  typedef llvm::DenseMap<unsigned, NewSenseList>::iterator NewDefsIterator;
-  llvm::DenseMap<unsigned, NewSenseList> NewDefs;
+  using DefsIterator = DenseMap<unsigned, PredSet>::iterator;
+  DenseMap<unsigned, PredSet> Defs;
 
   /// Set of weak definitions whose clashes should be enforced selectively.
-  typedef std::set<unsigned>::iterator SoftDefsIterator;
+  using SoftDefsIterator = std::set<unsigned>::iterator;
   std::set<unsigned> SoftDefs;
 
   /// Set of temporary definitions not committed to the register file.
-  typedef std::set<unsigned>::iterator TmpDefsIterator;
+  using TmpDefsIterator = std::set<unsigned>::iterator;
   std::set<unsigned> TmpDefs;
 
   /// Set of new predicates used.
-  typedef std::set<unsigned>::iterator NewPredsIterator;
+  using NewPredsIterator = std::set<unsigned>::iterator;
   std::set<unsigned> NewPreds;
 
   /// Set of predicates defined late.
-  typedef std::multiset<unsigned>::iterator LatePredsIterator;
+  using LatePredsIterator = std::multiset<unsigned>::iterator;
   std::multiset<unsigned> LatePreds;
 
   /// Set of uses.
-  typedef std::set<unsigned>::iterator UsesIterator;
+  using UsesIterator = std::set<unsigned>::iterator;
   std::set<unsigned> Uses;
 
-  /// Set of new values used: new register, if new-value jump.
-  typedef llvm::DenseMap<unsigned, NewSense>::iterator NewUsesIterator;
-  llvm::DenseMap<unsigned, NewSense> NewUses;
-
   /// Pre-defined set of read-only registers.
-  typedef std::set<unsigned>::iterator ReadOnlyIterator;
+  using ReadOnlyIterator = std::set<unsigned>::iterator;
   std::set<unsigned> ReadOnly;
 
   void init();
@@ -107,6 +78,9 @@ class HexagonMCChecker {
   void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
 
   bool registerUsed(unsigned Register);
+  std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
+  registerProducer(unsigned Register,
+                   HexagonMCInstrInfo::PredicateInfo Predicated);
 
   // Checks performed.
   bool checkBranches();
@@ -114,39 +88,43 @@ class HexagonMCChecker {
   bool checkNewValues();
   bool checkRegisters();
   bool checkRegistersReadOnly();
-  bool checkEndloopBranches();
   void checkRegisterCurDefs();
   bool checkSolo();
   bool checkShuffle();
   bool checkSlots();
   bool checkAXOK();
+  bool checkHWLoop();
+  bool checkCOFMax1();
 
   static void compoundRegisterMap(unsigned &);
 
   bool isPredicateRegister(unsigned R) const {
     return (Hexagon::P0 == R || Hexagon::P1 == R || Hexagon::P2 == R ||
             Hexagon::P3 == R);
-  };
+  }
+
   bool isLoopRegister(unsigned R) const {
     return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R ||
             Hexagon::LC1 == R);
-  };
-
-  bool hasValidNewValueDef(const NewSense &Use, const NewSenseList &Defs) const;
+  }
 
 public:
   explicit HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
                             MCSubtargetInfo const &STI, MCInst &mcb,
                             const MCRegisterInfo &ri, bool ReportErrors = true);
+  explicit HexagonMCChecker(HexagonMCChecker const &Check,
+                            MCSubtargetInfo const &STI, bool CopyReportErrors);
 
   bool check(bool FullCheck = true);
   void reportErrorRegisters(unsigned Register);
   void reportErrorNewValue(unsigned Register);
-  void reportError(SMLoc Loc, llvm::Twine const &Msg);
-  void reportError(llvm::Twine const &Msg);
-  void reportWarning(llvm::Twine const &Msg);
+  void reportError(SMLoc Loc, Twine const &Msg);
+  void reportNote(SMLoc Loc, Twine const &Msg);
+  void reportError(Twine const &Msg);
+  void reportWarning(Twine const &Msg);
+  void reportBranchErrors();
 };
 
-} // namespace llvm
+} // end namespace llvm
 
-#endif // HEXAGONMCCHECKER_H
+#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
index 50f00d1aaeac..631c38c2734f 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
@@ -1,4 +1,4 @@
-//===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
+//===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -11,19 +11,29 @@
 #include "Hexagon.h"
 #include "MCTargetDesc/HexagonBaseInfo.h"
 #include "MCTargetDesc/HexagonFixupKinds.h"
+#include "MCTargetDesc/HexagonMCExpr.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "MCTargetDesc/HexagonMCTargetDesc.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCFixup.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Endian.h"
 #include "llvm/Support/EndianStream.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
+#include <cassert>
+#include <cstddef>
+#include <cstdint>
+#include <string>
 
 #define DEBUG_TYPE "mccodeemitter"
 
@@ -89,7 +99,6 @@ void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
     *Addend += HEXAGON_INSTR_SIZE;
     ++*CurrentIndex;
   }
-  return;
 }
 
 static bool RegisterMatches(unsigned Consumer, unsigned Producer,
@@ -158,17 +167,16 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(
   ++MCNumEmitted;
 }
 
-namespace {
-void raise_relocation_error(unsigned bits, unsigned kind) {
+LLVM_ATTRIBUTE_NORETURN
+static void raise_relocation_error(unsigned bits, unsigned kind) {
   std::string Text;
   {
-    llvm::raw_string_ostream Stream(Text);
+    raw_string_ostream Stream(Text);
     Stream << "Unrecognized relocation combination bits: " << bits
            << " kind: " << kind;
   }
   report_fatal_error(Text);
 }
-}
 
 /// getFixupNoBits - Some insns are not extended and thus have no
 /// bits.  These cases require a more brute force method for determining
@@ -177,7 +185,7 @@ Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
     MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
     const MCSymbolRefExpr::VariantKind kind) const {
   const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
-  unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
+  unsigned insnType = HexagonMCInstrInfo::getType(MCII, MI);
 
   if (insnType == HexagonII::TypeEXTENDER) {
     switch (kind) {
@@ -282,14 +290,14 @@ Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
            ++ImpUses) {
         if (*ImpUses != Hexagon::GP)
           continue;
-        switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
-        case HexagonII::MemAccessSize::ByteAccess:
+        switch (HexagonMCInstrInfo::getMemAccessSize(MCII, MI)) {
+        case 1:
           return fixup_Hexagon_GPREL16_0;
-        case HexagonII::MemAccessSize::HalfWordAccess:
+        case 2:
           return fixup_Hexagon_GPREL16_1;
-        case HexagonII::MemAccessSize::WordAccess:
+        case 4:
           return fixup_Hexagon_GPREL16_2;
-        case HexagonII::MemAccessSize::DoubleWordAccess:
+        case 8:
           return fixup_Hexagon_GPREL16_3;
         default:
           raise_relocation_error(0, kind);
@@ -302,34 +310,34 @@ Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
 }
 
 namespace llvm {
+
 extern const MCInstrDesc HexagonInsts[];
-}
 
-namespace {
-  bool isPCRel (unsigned Kind) {
-    switch(Kind){
-    case fixup_Hexagon_B22_PCREL:
-    case fixup_Hexagon_B15_PCREL:
-    case fixup_Hexagon_B7_PCREL:
-    case fixup_Hexagon_B13_PCREL:
-    case fixup_Hexagon_B9_PCREL:
-    case fixup_Hexagon_B32_PCREL_X:
-    case fixup_Hexagon_B22_PCREL_X:
-    case fixup_Hexagon_B15_PCREL_X:
-    case fixup_Hexagon_B13_PCREL_X:
-    case fixup_Hexagon_B9_PCREL_X:
-    case fixup_Hexagon_B7_PCREL_X:
-    case fixup_Hexagon_32_PCREL:
-    case fixup_Hexagon_PLT_B22_PCREL:
-    case fixup_Hexagon_GD_PLT_B22_PCREL:
-    case fixup_Hexagon_LD_PLT_B22_PCREL:
-    case fixup_Hexagon_GD_PLT_B22_PCREL_X:
-    case fixup_Hexagon_LD_PLT_B22_PCREL_X:
-    case fixup_Hexagon_6_PCREL_X:
-      return true;
-    default:
-      return false;
-    }
+} // end namespace llvm
+
+static bool isPCRel (unsigned Kind) {
+  switch(Kind){
+  case fixup_Hexagon_B22_PCREL:
+  case fixup_Hexagon_B15_PCREL:
+  case fixup_Hexagon_B7_PCREL:
+  case fixup_Hexagon_B13_PCREL:
+  case fixup_Hexagon_B9_PCREL:
+  case fixup_Hexagon_B32_PCREL_X:
+  case fixup_Hexagon_B22_PCREL_X:
+  case fixup_Hexagon_B15_PCREL_X:
+  case fixup_Hexagon_B13_PCREL_X:
+  case fixup_Hexagon_B9_PCREL_X:
+  case fixup_Hexagon_B7_PCREL_X:
+  case fixup_Hexagon_32_PCREL:
+  case fixup_Hexagon_PLT_B22_PCREL:
+  case fixup_Hexagon_GD_PLT_B22_PCREL:
+  case fixup_Hexagon_LD_PLT_B22_PCREL:
+  case fixup_Hexagon_GD_PLT_B22_PCREL_X:
+  case fixup_Hexagon_LD_PLT_B22_PCREL_X:
+  case fixup_Hexagon_6_PCREL_X:
+    return true;
+  default:
+    return false;
   }
 }
 
@@ -338,7 +346,6 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
                                               const MCExpr *ME,
                                               SmallVectorImpl<MCFixup> &Fixups,
                                               const MCSubtargetInfo &STI) const
-
 {
   if (isa<HexagonMCExpr>(ME))
     ME = &HexagonMCInstrInfo::getExpr(*ME);
@@ -475,7 +482,7 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
       }
     } else
       switch (kind) {
-      case MCSymbolRefExpr::VK_None: {
+      case MCSymbolRefExpr::VK_None:
         if (HexagonMCInstrInfo::s27_2_reloc(*MO.getExpr()))
           FixupKind = Hexagon::fixup_Hexagon_27_REG;
         else
@@ -484,17 +491,17 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
                  ++ImpUses) {
               if (*ImpUses != Hexagon::GP)
                 continue;
-              switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
-              case HexagonII::MemAccessSize::ByteAccess:
+              switch (HexagonMCInstrInfo::getMemAccessSize(MCII, MI)) {
+              case 1:
                 FixupKind = fixup_Hexagon_GPREL16_0;
                 break;
-              case HexagonII::MemAccessSize::HalfWordAccess:
+              case 2:
                 FixupKind = fixup_Hexagon_GPREL16_1;
                 break;
-              case HexagonII::MemAccessSize::WordAccess:
+              case 4:
                 FixupKind = fixup_Hexagon_GPREL16_2;
                 break;
-              case HexagonII::MemAccessSize::DoubleWordAccess:
+              case 8:
                 FixupKind = fixup_Hexagon_GPREL16_3;
                 break;
               default:
@@ -504,7 +511,6 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
           } else
             raise_relocation_error(bits, kind);
         break;
-      }
       case MCSymbolRefExpr::VK_DTPREL:
         FixupKind = Hexagon::fixup_Hexagon_DTPREL_16;
         break;
@@ -786,7 +792,7 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
   if (MO.isReg()) {
     unsigned Reg = MO.getReg();
     if (HexagonMCInstrInfo::isSubInstruction(MI) ||
-        llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ)
+        HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ)
       return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg);
     return MCT.getRegisterInfo()->getEncodingValue(Reg);
   }
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h
index c3a4beec313f..14cabf1534a5 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h
@@ -1,4 +1,4 @@
-//===-- HexagonMCCodeEmitter.h - Hexagon Target Descriptions ----*- C++ -*-===//
+//===- HexagonMCCodeEmitter.h - Hexagon Target Descriptions -----*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -12,20 +12,26 @@
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef HEXAGONMCCODEEMITTER_H
-#define HEXAGONMCCODEEMITTER_H
+#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
+#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
 
 #include "MCTargetDesc/HexagonFixupKinds.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/raw_ostream.h"
+#include "llvm/MC/SubtargetFeature.h"
+#include <cstddef>
+#include <cstdint>
+#include <memory>
 
 namespace llvm {
 
+class MCContext;
+class MCInst;
+class MCInstrInfo;
+class MCOperand;
+class MCSubtargetInfo;
+class raw_ostream;
+
 class HexagonMCCodeEmitter : public MCCodeEmitter {
   MCContext &MCT;
   MCInstrInfo const &MCII;
@@ -73,8 +79,8 @@ private:
   uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
   void verifyInstructionPredicates(const MCInst &MI,
                                    uint64_t AvailableFeatures) const;
-}; // class HexagonMCCodeEmitter
+};
 
-} // namespace llvm
+} // end namespace llvm
 
-#endif /* HEXAGONMCCODEEMITTER_H */
+#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
index c7114c7f18a0..4c18af60efd1 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
@@ -1,4 +1,4 @@
-//===----- HexagonMCDuplexInfo.cpp - Instruction bundle checking ----------===//
+//===- HexagonMCDuplexInfo.cpp - Instruction bundle checking --------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -11,15 +11,22 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "HexagonBaseInfo.h"
+#include "MCTargetDesc/HexagonBaseInfo.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
-
+#include "MCTargetDesc/HexagonMCTargetDesc.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
-
+#include <cassert>
+#include <cstdint>
+#include <iterator>
 #include <map>
+#include <utility>
 
 using namespace llvm;
 using namespace Hexagon;
@@ -265,7 +272,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
   case Hexagon::J2_jumpr:
   case Hexagon::PS_jmpret:
     // jumpr r31
-    // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
+    // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0.
     DstReg = MCI.getOperand(0).getReg();
     if (Hexagon::R31 == DstReg)
       return HexagonII::HSIG_L2;
@@ -298,7 +305,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
   case Hexagon::L4_return_tnew_pt:
   case Hexagon::L4_return_fnew_pt:
     // [if ([!]p0[.new])] dealloc_return
-    SrcReg = MCI.getOperand(0).getReg();
+    SrcReg = MCI.getOperand(1).getReg();
     if (Hexagon::P0 == SrcReg) {
       return HexagonII::HSIG_L2;
     }
@@ -381,7 +388,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
     }
     break;
   case Hexagon::S2_allocframe:
-    if (inRange<5, 3>(MCI, 0))
+    if (inRange<5, 3>(MCI, 2))
       return HexagonII::HSIG_S2;
     break;
   //
@@ -464,7 +471,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
   case Hexagon::C2_cmovenewif:
     // if ([!]P0[.new]) Rd = #0
     // Actual form:
-    // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
+    // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
     DstReg = MCI.getOperand(0).getReg();  // Rd
     PredReg = MCI.getOperand(1).getReg(); // P0
     if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
@@ -735,7 +742,7 @@ MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
     break; //    1,2,3 SUBInst $Rx = add($_src_, $Rs)
   case Hexagon::S2_allocframe:
     Result.setOpcode(Hexagon::SS2_allocframe);
-    addOps(Result, Inst, 0);
+    addOps(Result, Inst, 2);
     break; //    1 SUBInst allocframe(#$u5_3)
   case Hexagon::A2_andir:
     if (minConstant(Inst, 2) == 255) {
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
index 47007e08a2ff..691e269cb91f 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
@@ -18,7 +18,9 @@
 #include "MCTargetDesc/HexagonMCShuffler.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/BinaryFormat/ELF.h"
+#include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
@@ -43,6 +45,19 @@ static cl::opt<unsigned> GPSize
    cl::Prefix,
    cl::init(8));
 
+HexagonMCELFStreamer::HexagonMCELFStreamer(
+    MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
+    raw_pwrite_stream &OS, std::unique_ptr<MCCodeEmitter> Emitter)
+    : MCELFStreamer(Context, std::move(TAB), OS, std::move(Emitter)),
+      MCII(createHexagonMCInstrInfo()) {}
+
+HexagonMCELFStreamer::HexagonMCELFStreamer(
+    MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
+    raw_pwrite_stream &OS, std::unique_ptr<MCCodeEmitter> Emitter,
+    MCAssembler *Assembler)
+    : MCELFStreamer(Context, std::move(TAB), OS, std::move(Emitter)),
+      MCII(createHexagonMCInstrInfo()) {}
+
 void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCB,
                                            const MCSubtargetInfo &STI, bool) {
   assert(MCB.getOpcode() == Hexagon::BUNDLE);
@@ -149,10 +164,11 @@ void HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol,
 
 
 namespace llvm {
-  MCStreamer *createHexagonELFStreamer(Triple const &TT, MCContext &Context,
-                                       MCAsmBackend &MAB,
-                                       raw_pwrite_stream &OS, MCCodeEmitter *CE) {
-    return new HexagonMCELFStreamer(Context, MAB, OS, CE);
+MCStreamer *createHexagonELFStreamer(Triple const &TT, MCContext &Context,
+                                     std::unique_ptr<MCAsmBackend> MAB,
+                                     raw_pwrite_stream &OS,
+                                     std::unique_ptr<MCCodeEmitter> CE) {
+  return new HexagonMCELFStreamer(Context, std::move(MAB), OS, std::move(CE));
   }
 
 } // end namespace llvm
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h
index 024dff1a2f97..c6fa0021d86b 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h
@@ -22,17 +22,14 @@ class HexagonMCELFStreamer : public MCELFStreamer {
   std::unique_ptr<MCInstrInfo> MCII;
 
 public:
-  HexagonMCELFStreamer(MCContext &Context, MCAsmBackend &TAB,
-                       raw_pwrite_stream &OS, MCCodeEmitter *Emitter)
-      : MCELFStreamer(Context, TAB, OS, Emitter),
-        MCII(createHexagonMCInstrInfo()) {}
+  HexagonMCELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
+                       raw_pwrite_stream &OS,
+                       std::unique_ptr<MCCodeEmitter> Emitter);
 
-  HexagonMCELFStreamer(MCContext &Context,
-                       MCAsmBackend &TAB,
-                       raw_pwrite_stream &OS, MCCodeEmitter *Emitter,
-                       MCAssembler *Assembler) :
-  MCELFStreamer(Context, TAB, OS, Emitter),
-  MCII (createHexagonMCInstrInfo()) {}
+  HexagonMCELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
+                       raw_pwrite_stream &OS,
+                       std::unique_ptr<MCCodeEmitter> Emitter,
+                       MCAssembler *Assembler);
 
   void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                        bool) override;
@@ -45,8 +42,9 @@ public:
 };
 
 MCStreamer *createHexagonELFStreamer(Triple const &TT, MCContext &Context,
-                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
-                                     MCCodeEmitter *CE);
+                                     std::unique_ptr<MCAsmBackend> MAB,
+                                     raw_pwrite_stream &OS,
+                                     std::unique_ptr<MCCodeEmitter> CE);
 
 } // end namespace llvm
 
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
index 5fe638a9996b..19308cd425e8 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
@@ -11,17 +11,31 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "HexagonMCInstrInfo.h"
-
+#include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "Hexagon.h"
-#include "HexagonBaseInfo.h"
-#include "HexagonMCChecker.h"
+#include "MCTargetDesc/HexagonBaseInfo.h"
+#include "MCTargetDesc/HexagonMCChecker.h"
+#include "MCTargetDesc/HexagonMCExpr.h"
+#include "MCTargetDesc/HexagonMCShuffler.h"
+#include "MCTargetDesc/HexagonMCTargetDesc.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/ErrorHandling.h"
+#include <cassert>
+#include <cstdint>
+#include <limits>
+
+using namespace llvm;
 
-namespace llvm {
+bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const {
+  return Register != Hexagon::NoRegister;
+}
 
 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
                                         MCInst const &Inst)
@@ -40,6 +54,7 @@ Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
     if (DuplexCurrent == DuplexEnd) {
       DuplexCurrent = BundleEnd;
       DuplexEnd = BundleEnd;
+      ++BundleCurrent;
     }
     return *this;
   }
@@ -80,6 +95,7 @@ void HexagonMCInstrInfo::addConstExtender(MCContext &Context,
   // Create the extender.
   MCInst *XMCI =
       new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
+  XMCI->setLoc(MCI.getLoc());
 
   MCB.addOperand(MCOperand::createInst(XMCI));
 }
@@ -121,7 +137,7 @@ bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
   // Examine the packet and convert pairs of instructions to duplex
   // instructions when possible.
   MCInst InstBundlePreDuplex = MCInst(MCB);
-  if (!HexagonDisableDuplex) {
+  if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) {
     SmallVector<DuplexCandidate, 8> possibleDuplexes;
     possibleDuplexes =
         HexagonMCInstrInfo::getDuplexPossibilties(MCII, STI, MCB);
@@ -159,13 +175,6 @@ void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII,
   }
 }
 
-MCInst HexagonMCInstrInfo::createBundle() {
-  MCInst Result;
-  Result.setOpcode(Hexagon::BUNDLE);
-  Result.addOperand(MCOperand::createImm(0));
-  return Result;
-}
-
 MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
                                           MCInst const &Inst,
                                           MCOperand const &MO) {
@@ -216,12 +225,18 @@ void HexagonMCInstrInfo::extendIfNeeded(MCContext &Context,
     addConstExtender(Context, MCII, MCB, MCI);
 }
 
-HexagonII::MemAccessSize
-HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) {
-  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
+unsigned HexagonMCInstrInfo::getMemAccessSize(MCInstrInfo const &MCII,
+      MCInst const &MCI) {
+  uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
+  unsigned S = (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
+  return HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(S));
+}
 
-  return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) &
-                                   HexagonII::MemAccesSizeMask));
+unsigned HexagonMCInstrInfo::getAddrMode(MCInstrInfo const &MCII,
+                                         MCInst const &MCI) {
+  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
+  return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
+                               HexagonII::AddrModeMask);
 }
 
 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
@@ -231,6 +246,7 @@ MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
 
 unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(unsigned Reg) {
   using namespace Hexagon;
+
   switch (Reg) {
   default:
     llvm_unreachable("unknown duplex register");
@@ -355,13 +371,20 @@ unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
 
 MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
                                                         MCInst const &MCI) {
-  unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
-  MCOperand const &MCO = MCI.getOperand(O);
+  if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
+    // VTMP doesn't actually exist in the encodings for these 184
+    // 3 instructions so go ahead and create it here.
+    static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
+    return (MCO);
+  } else {
+    unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
+    MCOperand const &MCO = MCI.getOperand(O);
 
-  assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
-          HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
-         MCO.isReg());
-  return (MCO);
+    assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
+            HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
+           MCO.isReg());
+    return (MCO);
+  }
 }
 
 /// Return the new value or the newly produced value.
@@ -429,8 +452,8 @@ bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
   if (!HexagonMCInstrInfo::isBundle(MCI))
     return false;
 
-  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCI)) {
-    if (HexagonMCInstrInfo::isDuplex(MCII, I))
+  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
+    if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
       return true;
   }
 
@@ -441,7 +464,7 @@ bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
   return extenderForIndex(MCB, Index) != nullptr;
 }
 
-bool HexagonMCInstrInfo::hasImmExt( MCInst const &MCI) {
+bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
   if (!HexagonMCInstrInfo::isBundle(MCI))
     return false;
 
@@ -530,6 +553,18 @@ bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
   return ((F >> HexagonII::CofMax1Pos) & HexagonII::CofMax1Mask);
 }
 
+bool HexagonMCInstrInfo::isCofRelax1(MCInstrInfo const &MCII,
+                                     MCInst const &MCI) {
+  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
+  return ((F >> HexagonII::CofRelax1Pos) & HexagonII::CofRelax1Mask);
+}
+
+bool HexagonMCInstrInfo::isCofRelax2(MCInstrInfo const &MCII,
+                                     MCInst const &MCI) {
+  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
+  return ((F >> HexagonII::CofRelax2Pos) & HexagonII::CofRelax2Mask);
+}
+
 bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
                                     MCInst const &MCI) {
   return (getType(MCII, MCI) == HexagonII::TypeCJ);
@@ -566,6 +601,11 @@ bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
   return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
 }
 
+bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
+  const uint64_t V = getType(MCII, MCI);
+  return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
+}
+
 bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
   return MCI.getOpcode() == Hexagon::A4_ext;
 }
@@ -645,10 +685,18 @@ bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
 }
 
 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
-bool HexagonMCInstrInfo::isSoloAin1(MCInstrInfo const &MCII,
-                                    MCInst const &MCI) {
+bool HexagonMCInstrInfo::isRestrictSlot1AOK(MCInstrInfo const &MCII,
+                                            MCInst const &MCI) {
   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
-  return ((F >> HexagonII::SoloAin1Pos) & HexagonII::SoloAin1Mask);
+  return ((F >> HexagonII::RestrictSlot1AOKPos) &
+          HexagonII::RestrictSlot1AOKMask);
+}
+
+bool HexagonMCInstrInfo::isRestrictNoSlot1Store(MCInstrInfo const &MCII,
+                                                MCInst const &MCI) {
+  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
+  return ((F >> HexagonII::RestrictNoSlot1StorePos) &
+          HexagonII::RestrictNoSlot1StoreMask);
 }
 
 /// Return whether the insn is solo, i.e., cannot be in a packet.
@@ -663,12 +711,6 @@ bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
   return (Flags & memReorderDisabledMask) != 0;
 }
 
-bool HexagonMCInstrInfo::isMemStoreReorderEnabled(MCInst const &MCI) {
-  assert(isBundle(MCI));
-  auto Flags = MCI.getOperand(0).getImm();
-  return (Flags & memStoreReorderEnabledMask) != 0;
-}
-
 bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) {
   switch (MCI.getOpcode()) {
   default:
@@ -769,11 +811,11 @@ bool HexagonMCInstrInfo::mustNotExtend(MCExpr const &Expr) {
 }
 void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
   HexagonMCExpr &HExpr =
-      const_cast<HexagonMCExpr &>(*llvm::cast<HexagonMCExpr>(&Expr));
+      const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
   HExpr.setS27_2_reloc(Val);
 }
 bool HexagonMCInstrInfo::s27_2_reloc(MCExpr const &Expr) {
-  HexagonMCExpr const *HExpr = llvm::dyn_cast<HexagonMCExpr>(&Expr);
+  HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
   if (!HExpr)
     return false;
   return HExpr->s27_2_reloc();
@@ -790,12 +832,29 @@ void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) {
     MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
 }
 
+HexagonMCInstrInfo::PredicateInfo
+HexagonMCInstrInfo::predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI) {
+  if (!isPredicated(MCII, MCI))
+    return {0, 0, false};
+  MCInstrDesc const &Desc = getDesc(MCII, MCI);
+  for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
+    if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
+      return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
+  return {0, 0, false};
+}
+
 bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
                                       MCInst const &MCI) {
   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
   return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask;
 }
 
+/// return true if instruction has hasTmpDst attribute.
+bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
+  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
+  return (F >> HexagonII::HasTmpDstPos) & HexagonII::HasTmpDstMask;
+}
+
 void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
                                        DuplexCandidate Candidate) {
   assert(Candidate.packetIndexI < MCB.size());
@@ -823,13 +882,6 @@ void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
   assert(isMemReorderDisabled(MCI));
 }
 
-void HexagonMCInstrInfo::setMemStoreReorderEnabled(MCInst &MCI) {
-  assert(isBundle(MCI));
-  MCOperand &Operand = MCI.getOperand(0);
-  Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask);
-  assert(isMemStoreReorderEnabled(MCI));
-}
-
 void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
   assert(isBundle(MCI));
   MCOperand &Operand = MCI.getOperand(0);
@@ -844,8 +896,7 @@ unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
   if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
     if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
       return (Consumer - Hexagon::V0) & 0x1;
-  if (Consumer == Producer2)
-    return 0x1;
+  if (Producer2 != Hexagon::NoRegister)
+    return Consumer == Producer;
   return 0;
 }
-} // namespace llvm
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
index ca44c3a11ba7..28d89429266b 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
@@ -14,24 +14,33 @@
 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
 
-#include "HexagonMCExpr.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/iterator_range.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/Support/MathExtras.h"
+#include <cstddef>
+#include <cstdint>
 
 namespace llvm {
+
 class HexagonMCChecker;
+class MCContext;
+class MCExpr;
 class MCInstrDesc;
 class MCInstrInfo;
 class MCSubtargetInfo;
-namespace HexagonII {
-enum class MemAccessSize;
-}
+
 class DuplexCandidate {
 public:
   unsigned packetIndexI, packetIndexJ, iClass;
+
   DuplexCandidate(unsigned i, unsigned j, unsigned iClass)
       : packetIndexI(i), packetIndexJ(j), iClass(iClass) {}
 };
+
 namespace Hexagon {
+
 class PacketIterator {
   MCInstrInfo const &MCII;
   MCInst::const_iterator BundleCurrent;
@@ -42,6 +51,7 @@ class PacketIterator {
 public:
   PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
   PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
+
   PacketIterator &operator++();
   MCInst const &operator*() const;
   bool operator==(PacketIterator const &Other) const;
@@ -49,8 +59,11 @@ public:
     return !(*this == Other);
   }
 };
-} // namespace Hexagon
+
+} // end namespace Hexagon
+
 namespace HexagonMCInstrInfo {
+
 size_t const innerLoopOffset = 0;
 int64_t const innerLoopMask = 1 << innerLoopOffset;
 
@@ -62,10 +75,6 @@ int64_t const outerLoopMask = 1 << outerLoopOffset;
 size_t const memReorderDisabledOffset = 2;
 int64_t const memReorderDisabledMask = 1 << memReorderDisabledOffset;
 
-// allow re-ordering of memory stores by default stores cannot be re-ordered
-size_t const memStoreReorderEnabledOffset = 3;
-int64_t const memStoreReorderEnabledMask = 1 << memStoreReorderEnabledOffset;
-
 size_t const bundleInstructionsOffset = 1;
 
 void addConstant(MCInst &MI, uint64_t Value, MCContext &Context);
@@ -97,16 +106,17 @@ MCInst deriveSubInst(MCInst const &Inst);
 // Clamp off upper 26 bits of extendable operand for emission
 void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI);
 
-MCInst createBundle();
-
 // Return the extender for instruction at Index or nullptr if none
 MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
                     MCInst const &MCI);
 
+// Return memory access size in bytes
+unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
+
 // Return memory access size
-HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
-                                       MCInst const &MCI);
+unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI);
+
 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
 
 // Return which duplex group this instruction belongs to
@@ -171,6 +181,7 @@ bool hasImmExt(MCInst const &MCI);
 // Return whether the instruction is a legal new-value producer.
 bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
 bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI);
+bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI);
 unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb);
 
 int64_t minConstant(MCInst const &MCI, size_t Index);
@@ -196,6 +207,8 @@ bool isBundle(MCInst const &MCI);
 // Return whether the insn is an actual insn.
 bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
 bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI);
+bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI);
+bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI);
 bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI);
 
 // Return whether the instruction needs to be constant extended.
@@ -223,6 +236,8 @@ bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI);
 /// Return whether it is a floating-point insn.
 bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
 
+bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI);
+
 // Returns whether this instruction is an immediate extender
 bool isImmext(MCInst const &MCI);
 
@@ -235,7 +250,6 @@ bool isIntReg(unsigned Reg);
 // Is this register suitable for use in a duplex subinst
 bool isIntRegForSubInst(unsigned Reg);
 bool isMemReorderDisabled(MCInst const &MCI);
-bool isMemStoreReorderEnabled(MCInst const &MCI);
 
 // Return whether the insn is a new-value consumer.
 bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
@@ -270,7 +284,8 @@ bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI);
 bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI);
 
 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
-bool isSoloAin1(MCInstrInfo const &MCII, MCInst const &MCI);
+bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI);
+bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI);
 bool isSubInstruction(MCInst const &MCI);
 bool isVector(MCInstrInfo const &MCII, MCInst const &MCI);
 bool mustExtend(MCExpr const &Expr);
@@ -278,6 +293,17 @@ bool mustNotExtend(MCExpr const &Expr);
 
 // Pad the bundle with nops to satisfy endloop requirements
 void padEndloop(MCInst &MCI, MCContext &Context);
+class PredicateInfo {
+public:
+  PredicateInfo() : Register(0), Operand(0), PredicatedTrue(false) {}
+  PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue)
+      : Register(Register), Operand(Operand), PredicatedTrue(PredicatedTrue) {}
+  bool isPredicated() const;
+  unsigned Register;
+  unsigned Operand;
+  bool PredicatedTrue;
+};
+PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI);
 bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI);
 
 // Replace the instructions inside MCB, represented by Candidate
@@ -287,7 +313,6 @@ bool s27_2_reloc(MCExpr const &Expr);
 // Marks a bundle as endloop0
 void setInnerLoop(MCInst &MCI);
 void setMemReorderDisabled(MCInst &MCI);
-void setMemStoreReorderEnabled(MCInst &MCI);
 void setMustExtend(MCExpr const &Expr, bool Val = true);
 void setMustNotExtend(MCExpr const &Expr, bool Val = true);
 void setS27_2_reloc(MCExpr const &Expr, bool Val = true);
@@ -303,7 +328,9 @@ unsigned SubregisterBit(unsigned Consumer, unsigned Producer,
 // Attempt to find and replace compound pairs
 void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
                  MCContext &Context, MCInst &MCI);
-} // namespace HexagonMCInstrInfo
-} // namespace llvm
+
+} // end namespace HexagonMCInstrInfo
+
+} // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp
index b2c7f1569380..7bd54fdfa3d5 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp
@@ -17,10 +17,14 @@
 #include "MCTargetDesc/HexagonMCShuffler.h"
 #include "Hexagon.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
-#include "MCTargetDesc/HexagonMCTargetDesc.h"
+#include "MCTargetDesc/HexagonShuffler.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/MC/MCInstrInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
+#include <cassert>
 
 using namespace llvm;
 
@@ -109,9 +113,10 @@ bool llvm::HexagonMCShuffle(MCContext &Context, bool Fatal,
 
   if (!HexagonMCInstrInfo::bundleSize(MCB)) {
     // There once was a bundle:
-    //    BUNDLE %D2<imp-def>, %R4<imp-def>, %R5<imp-def>, %D7<imp-def>, ...
-    //      * %D2<def> = IMPLICIT_DEF; flags:
-    //      * %D7<def> = IMPLICIT_DEF; flags:
+    //    BUNDLE implicit-def %d2, implicit-def %r4, implicit-def %r5,
+    //    implicit-def %d7, ...
+    //      * %d2 = IMPLICIT_DEF; flags:
+    //      * %d7 = IMPLICIT_DEF; flags:
     // After the IMPLICIT_DEFs were removed by the asm printer, the bundle
     // became empty.
     DEBUG(dbgs() << "Skipping empty bundle");
@@ -128,15 +133,15 @@ bool
 llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
                        MCSubtargetInfo const &STI, MCInst &MCB,
                        SmallVector<DuplexCandidate, 8> possibleDuplexes) {
-
   if (DisableShuffle)
     return false;
 
   if (!HexagonMCInstrInfo::bundleSize(MCB)) {
     // There once was a bundle:
-    //    BUNDLE %D2<imp-def>, %R4<imp-def>, %R5<imp-def>, %D7<imp-def>, ...
-    //      * %D2<def> = IMPLICIT_DEF; flags:
-    //      * %D7<def> = IMPLICIT_DEF; flags:
+    //    BUNDLE implicit-def %d2, implicit-def %r4, implicit-def %r5,
+    //    implicit-def %d7, ...
+    //      * %d2 = IMPLICIT_DEF; flags:
+    //      * %d7 = IMPLICIT_DEF; flags:
     // After the IMPLICIT_DEFs were removed by the asm printer, the bundle
     // became empty.
     DEBUG(dbgs() << "Skipping empty bundle");
@@ -165,7 +170,7 @@ llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
       break;
   }
 
-  if (doneShuffling == false) {
+  if (!doneShuffling) {
     HexagonMCShuffler MCS(Context, false, MCII, STI, MCB);
     doneShuffling = MCS.reshuffleTo(MCB); // shuffle
   }
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h
index dbe85b434dc4..59658999d24d 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h
@@ -1,4 +1,4 @@
-//=-- HexagonMCShuffler.h ---------------------------------------------------=//
+//===- HexagonMCShuffler.h --------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -12,13 +12,20 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef HEXAGONMCSHUFFLER_H
-#define HEXAGONMCSHUFFLER_H
+#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCSHUFFLER_H
+#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCSHUFFLER_H
 
+#include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "MCTargetDesc/HexagonShuffler.h"
+#include "llvm/ADT/SmallVector.h"
 
 namespace llvm {
+
+class MCContext;
 class MCInst;
+class MCInstrInfo;
+class MCSubtargetInfo;
+
 // Insn bundle shuffler.
 class HexagonMCShuffler : public HexagonShuffler {
 public:
@@ -26,16 +33,18 @@ public:
                     MCSubtargetInfo const &STI, MCInst &MCB)
       : HexagonShuffler(Context, Fatal, MCII, STI) {
     init(MCB);
-  };
+  }
+
   HexagonMCShuffler(MCContext &Context, bool Fatal, MCInstrInfo const &MCII,
                     MCSubtargetInfo const &STI, MCInst &MCB,
                     MCInst const &AddMI, bool InsertAtFront)
       : HexagonShuffler(Context, Fatal, MCII, STI) {
     init(MCB, AddMI, InsertAtFront);
-  };
+  }
 
   // Copy reordered bundle to another.
   void copyTo(MCInst &MCB);
+
   // Reorder and copy result to another.
   bool reshuffleTo(MCInst &MCB);
 
@@ -46,13 +55,14 @@ private:
 
 // Invocation of the shuffler.
 bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII,
-                      MCSubtargetInfo const &STI, MCInst &);
+                      MCSubtargetInfo const &STI, MCInst &MCB);
 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
-                      MCSubtargetInfo const &STI, MCInst &, MCInst const &,
-                      int);
+                      MCSubtargetInfo const &STI, MCInst &MCB,
+                      MCInst const &AddMI, int fixupCount);
 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
-                      MCSubtargetInfo const &STI, MCInst &,
-                      SmallVector<DuplexCandidate, 8>);
-} // namespace llvm
+                      MCSubtargetInfo const &STI, MCInst &MCB,
+                      SmallVector<DuplexCandidate, 8> possibleDuplexes);
+
+} // end namespace llvm
 
-#endif // HEXAGONMCSHUFFLER_H
+#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCSHUFFLER_H
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index 1a361548f938..3fbe2197f937 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -13,13 +13,17 @@
 
 #include "MCTargetDesc/HexagonMCTargetDesc.h"
 #include "Hexagon.h"
+#include "HexagonDepArch.h"
 #include "HexagonTargetStreamer.h"
 #include "MCTargetDesc/HexagonInstPrinter.h"
 #include "MCTargetDesc/HexagonMCAsmInfo.h"
 #include "MCTargetDesc/HexagonMCELFStreamer.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
+#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/BinaryFormat/ELF.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/MC/MCELFStreamer.h"
@@ -55,41 +59,55 @@ cl::opt<bool> llvm::HexagonDisableDuplex
   ("mno-pairing",
    cl::desc("Disable looking for duplex instructions for Hexagon"));
 
-static cl::opt<bool> HexagonV4ArchVariant("mv4", cl::Hidden, cl::init(false),
-  cl::desc("Build for Hexagon V4"));
+namespace { // These flags are to be deprecated
+cl::opt<bool> MV4("mv4", cl::Hidden, cl::desc("Build for Hexagon V4"),
+                  cl::init(false));
+cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
+                  cl::init(false));
+cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
+                   cl::init(false));
+cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
+                   cl::init(false));
+cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
+                   cl::init(false));
+cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
+                   cl::init(false));
+} // namespace
 
-static cl::opt<bool> HexagonV5ArchVariant("mv5", cl::Hidden, cl::init(false),
-  cl::desc("Build for Hexagon V5"));
+cl::opt<Hexagon::ArchEnum>
+    EnableHVX("mhvx",
+      cl::desc("Enable Hexagon Vector eXtensions"),
+      cl::values(
+        clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
+        clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
+        clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
+        // Sentinal for no value specified
+        clEnumValN(Hexagon::ArchEnum::V5, "", "")),
+      // Sentinal for flag not present
+      cl::init(Hexagon::ArchEnum::V4), cl::ValueOptional);
+static cl::opt<bool>
+  DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"));
 
-static cl::opt<bool> HexagonV55ArchVariant("mv55", cl::Hidden, cl::init(false),
-  cl::desc("Build for Hexagon V55"));
-
-static cl::opt<bool> HexagonV60ArchVariant("mv60", cl::Hidden, cl::init(false),
-  cl::desc("Build for Hexagon V60"));
-
-static cl::opt<bool> HexagonV62ArchVariant("mv62", cl::Hidden, cl::init(false),
-  cl::desc("Build for Hexagon V62"));
-
-static cl::opt<bool> EnableHVX("mhvx", cl::Hidden, cl::init(false),
-  cl::desc("Enable Hexagon Vector Extension (HVX)"));
 
 static StringRef DefaultArch = "hexagonv60";
 
 static StringRef HexagonGetArchVariant() {
-  if (HexagonV4ArchVariant)
+  if (MV4)
     return "hexagonv4";
-  if (HexagonV5ArchVariant)
+  if (MV5)
     return "hexagonv5";
-  if (HexagonV55ArchVariant)
+  if (MV55)
     return "hexagonv55";
-  if (HexagonV60ArchVariant)
+  if (MV60)
     return "hexagonv60";
-  if (HexagonV62ArchVariant)
+  if (MV62)
     return "hexagonv62";
+  if (MV65)
+    return "hexagonv65";
   return "";
 }
 
-StringRef Hexagon_MC::selectHexagonCPU(const Triple &TT, StringRef CPU) {
+StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) {
   StringRef ArchV = HexagonGetArchVariant();
   if (!ArchV.empty() && !CPU.empty()) {
     if (ArchV != CPU)
@@ -144,7 +162,11 @@ public:
         OS << Indent << InstTxt << Separator;
       HeadTail = HeadTail.second.split('\n');
     }
-    OS << "\t}" << PacketBundle.second;
+
+    if (HexagonMCInstrInfo::isMemReorderDisabled(Inst))
+      OS << "\n\t}:mem_noshuf" << PacketBundle.second;
+    else
+      OS << "\t}" << PacketBundle.second;
   }
 };
 
@@ -224,13 +246,13 @@ createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
   return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
 }
 
-static MCStreamer *createMCStreamer(Triple const &T,
-                                    MCContext &Context,
-                                    MCAsmBackend &MAB,
+static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
+                                    std::unique_ptr<MCAsmBackend> &&MAB,
                                     raw_pwrite_stream &OS,
-                                    MCCodeEmitter *Emitter,
+                                    std::unique_ptr<MCCodeEmitter> &&Emitter,
                                     bool RelaxAll) {
-  return createHexagonELFStreamer(T, Context, MAB, OS, Emitter);
+  return createHexagonELFStreamer(T, Context, std::move(MAB), OS,
+                                  std::move(Emitter));
 }
 
 static MCTargetStreamer *
@@ -249,15 +271,37 @@ static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo* STI, uint64_t F)
   return (FB & (1ULL << F)) != 0;
 }
 
-StringRef Hexagon_MC::ParseHexagonTriple(const Triple &TT, StringRef CPU) {
-  StringRef CPUName = Hexagon_MC::selectHexagonCPU(TT, CPU);
-  StringRef FS = "";
-  if (EnableHVX) {
-    if (CPUName.equals_lower("hexagonv60") ||
-        CPUName.equals_lower("hexagonv62"))
-      FS = "+hvx";
+namespace {
+std::string selectHexagonFS(StringRef CPU, StringRef FS) {
+  SmallVector<StringRef, 3> Result;
+  if (!FS.empty())
+    Result.push_back(FS);
+
+  switch (EnableHVX) {
+  case Hexagon::ArchEnum::V55:
+    break;
+  case Hexagon::ArchEnum::V60:
+    Result.push_back("+hvxv60");
+    break;
+  case Hexagon::ArchEnum::V62:
+    Result.push_back("+hvxv62");
+    break;
+  case Hexagon::ArchEnum::V65:
+    Result.push_back("+hvxv65");
+    break;
+  case Hexagon::ArchEnum::V5:{
+    Result.push_back(StringSwitch<StringRef>(CPU)
+             .Case("hexagonv60", "+hvxv60")
+             .Case("hexagonv62", "+hvxv62")
+             .Case("hexagonv65", "+hvxv65"));
+    break;
   }
-  return FS;
+  case Hexagon::ArchEnum::V4:
+    // Sentinal if -mhvx isn't specified
+    break;
+  }
+  return join(Result.begin(), Result.end(), ",");
+}
 }
 
 static bool isCPUValid(std::string CPU)
@@ -269,16 +313,76 @@ static bool isCPUValid(std::string CPU)
     "hexagonv55",
     "hexagonv60",
     "hexagonv62",
+    "hexagonv65",
   };
 
   return std::find(table.begin(), table.end(), CPU) != table.end();
 }
 
+namespace {
+std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
+                                                   StringRef FS) {
+  std::pair<std::string, std::string> Result;
+  Result.first = Hexagon_MC::selectHexagonCPU(CPU);
+  Result.second = selectHexagonFS(Result.first, FS);
+  return Result;
+}
+}
+
+FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
+  using namespace Hexagon;
+  // Make sure that +hvx-length turns hvx on, and that "hvx" alone
+  // turns on hvxvNN, corresponding to the existing ArchVNN.
+  FeatureBitset FB = S;
+  unsigned CpuArch = ArchV4;
+  for (unsigned F : {ArchV65, ArchV62, ArchV60, ArchV55, ArchV5, ArchV4}) {
+    if (!FB.test(F))
+      continue;
+    CpuArch = F;
+    break;
+  }
+  bool UseHvx = false;
+  for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B,
+                     ExtensionHVXDbl}) {
+    if (!FB.test(F))
+      continue;
+    UseHvx = true;
+    break;
+  }
+  bool HasHvxVer = false;
+  for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65}) {
+    if (!FB.test(F))
+      continue;
+    HasHvxVer = true;
+    UseHvx = true;
+    break;
+  }
+
+  if (!UseHvx || HasHvxVer)
+    return FB;
+
+  // HasHvxVer is false, and UseHvx is true.
+  switch (CpuArch) {
+    case ArchV65:
+      FB.set(ExtensionHVXV65);
+      LLVM_FALLTHROUGH;
+    case ArchV62:
+      FB.set(ExtensionHVXV62);
+      LLVM_FALLTHROUGH;
+    case ArchV60:
+      FB.set(ExtensionHVXV60);
+      break;
+  }
+  return FB;
+}
+
 MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
                                                           StringRef CPU,
                                                           StringRef FS) {
-  StringRef ArchFS = (FS.size()) ? FS : Hexagon_MC::ParseHexagonTriple(TT, CPU);
-  StringRef CPUName = Hexagon_MC::selectHexagonCPU(TT, CPU);
+  std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
+  StringRef CPUName = Features.first;
+  StringRef ArchFS = Features.second;
+
   if (!isCPUValid(CPUName.str())) {
     errs() << "error: invalid CPU \"" << CPUName.str().c_str()
            << "\" specified\n";
@@ -286,10 +390,12 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
   }
 
   MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
-  if (X->getFeatureBits()[Hexagon::ExtensionHVXDbl]) {
+  if (HexagonDisableDuplex) {
     llvm::FeatureBitset Features = X->getFeatureBits();
-    X->setFeatureBits(Features.set(Hexagon::ExtensionHVX));
+    X->setFeatureBits(Features.set(Hexagon::FeatureDuplex, false));
   }
+
+  X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
   return X;
 }
 
@@ -300,6 +406,7 @@ unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
     {"hexagonv55", ELF::EF_HEXAGON_MACH_V55},
     {"hexagonv60", ELF::EF_HEXAGON_MACH_V60},
     {"hexagonv62", ELF::EF_HEXAGON_MACH_V62},
+    {"hexagonv65", ELF::EF_HEXAGON_MACH_V65},
   };
 
   auto F = ElfFlags.find(STI.getCPU());
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
index 6bb69be6142e..05d17c368dcc 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
@@ -16,11 +16,13 @@
 
 #include "llvm/Support/CommandLine.h"
 #include <cstdint>
+#include <string>
 
 namespace llvm {
 
 struct InstrItinerary;
 struct InstrStage;
+class FeatureBitset;
 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
@@ -44,9 +46,9 @@ MCInstrInfo *createHexagonMCInstrInfo();
 MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT);
 
 namespace Hexagon_MC {
-  StringRef ParseHexagonTriple(const Triple &TT, StringRef CPU);
-  StringRef selectHexagonCPU(const Triple &TT, StringRef CPU);
+  StringRef selectHexagonCPU(StringRef CPU);
 
+  FeatureBitset completeHVXFeatures(const FeatureBitset &FB);
   /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser,
   /// etc. do not need to go through TargetRegistry.
   MCSubtargetInfo *createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU,
@@ -63,8 +65,9 @@ MCAsmBackend *createHexagonAsmBackend(const Target &T,
                                       const Triple &TT, StringRef CPU,
                                       const MCTargetOptions &Options);
 
-MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
-                                             uint8_t OSABI, StringRef CPU);
+std::unique_ptr<MCObjectWriter>
+createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
+                             StringRef CPU);
 
 unsigned HexagonGetLastSlot();
 
@@ -79,6 +82,7 @@ unsigned HexagonGetLastSlot();
 // Defines symbolic names for the Hexagon instructions.
 //
 #define GET_INSTRINFO_ENUM
+#define GET_INSTRINFO_SCHED_ENUM
 #include "HexagonGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_ENUM
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
index 1604e7c8dc54..7709a0f61624 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
@@ -1,4 +1,4 @@
-//===----- HexagonShuffler.cpp - Instruction bundle shuffling -------------===//
+//===- HexagonShuffler.cpp - Instruction bundle shuffling -----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -14,32 +14,40 @@
 
 #define DEBUG_TYPE "hexagon-shuffle"
 
-#include "HexagonShuffler.h"
+#include "MCTargetDesc/HexagonShuffler.h"
 #include "Hexagon.h"
 #include "MCTargetDesc/HexagonBaseInfo.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "MCTargetDesc/HexagonMCTargetDesc.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
-#include "llvm/Support/Format.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
+#include <cassert>
 #include <utility>
+#include <vector>
 
 using namespace llvm;
 
 namespace {
+
 // Insn shuffling priority.
 class HexagonBid {
   // The priority is directly proportional to how restricted the insn is based
   // on its flexibility to run on the available slots.  So, the fewer slots it
   // may run on, the higher its priority.
   enum { MAX = 360360 }; // LCD of 1/2, 1/3, 1/4,... 1/15.
-  unsigned Bid;
+  unsigned Bid = 0;
 
 public:
-  HexagonBid() : Bid(0) {}
+  HexagonBid() = default;
   HexagonBid(unsigned B) { Bid = B ? MAX / countPopulation(B) : 0; }
 
   // Check if the insn priority is overflowed.
@@ -58,7 +66,7 @@ class HexagonUnitAuction {
   unsigned isSold : HEXAGON_PACKET_SIZE;
 
 public:
-  HexagonUnitAuction(unsigned cs = 0) : isSold(cs){};
+  HexagonUnitAuction(unsigned cs = 0) : isSold(cs) {}
 
   // Allocate slots.
   bool bid(unsigned B) {
@@ -77,6 +85,7 @@ public:
       return false;
   }
 };
+
 } // end anonymous namespace
 
 unsigned HexagonResource::setWeight(unsigned s) {
@@ -107,6 +116,7 @@ void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) {
   (*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1);
   (*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2);
   (*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1);
+  (*TUL)[HexagonII::TypeCVI_VS_VX] = UnitsAndLanes(CVI_XLANE | CVI_SHIFT, 1);
   (*TUL)[HexagonII::TypeCVI_VINLANESAT] =
       (CPU == "hexagonv60")
           ? UnitsAndLanes(CVI_SHIFT, 1)
@@ -120,12 +130,20 @@ void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) {
   (*TUL)[HexagonII::TypeCVI_VM_NEW_ST] = UnitsAndLanes(CVI_NONE, 0);
   (*TUL)[HexagonII::TypeCVI_VM_STU] = UnitsAndLanes(CVI_XLANE, 1);
   (*TUL)[HexagonII::TypeCVI_HIST] = UnitsAndLanes(CVI_XLANE, 4);
+  (*TUL)[HexagonII::TypeCVI_GATHER] =
+      UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
+  (*TUL)[HexagonII::TypeCVI_SCATTER] =
+      UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
+  (*TUL)[HexagonII::TypeCVI_SCATTER_DV] =
+      UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2);
+  (*TUL)[HexagonII::TypeCVI_SCATTER_NEW_ST] =
+      UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
 }
 
 HexagonCVIResource::HexagonCVIResource(TypeUnitsAndLanes *TUL,
                                        MCInstrInfo const &MCII, unsigned s,
                                        MCInst const *id)
-    : HexagonResource(s), TUL(TUL) {
+    : HexagonResource(s) {
   unsigned T = HexagonMCInstrInfo::getType(MCII, *id);
 
   if (TUL->count(T)) {
@@ -149,10 +167,9 @@ struct CVIUnits {
   unsigned Units;
   unsigned Lanes;
 };
-typedef SmallVector<struct CVIUnits, 8> HVXInstsT;
+using HVXInstsT = SmallVector<struct CVIUnits, 8>;
 
 static unsigned makeAllBits(unsigned startBit, unsigned Lanes)
-
 {
   for (unsigned i = 1; i < Lanes; ++i)
     startBit = (startBit << 1) | startBit;
@@ -160,9 +177,7 @@ static unsigned makeAllBits(unsigned startBit, unsigned Lanes)
 }
 
 static bool checkHVXPipes(const HVXInstsT &hvxInsts, unsigned startIdx,
-                          unsigned usedUnits)
-
-{
+                          unsigned usedUnits) {
   if (startIdx < hvxInsts.size()) {
     if (!hvxInsts[startIdx].Units)
       return checkHVXPipes(hvxInsts, startIdx + 1, usedUnits);
@@ -206,30 +221,89 @@ static struct {
 } jumpSlots[] = {{8, 4}, {8, 2}, {8, 1}, {4, 2}, {4, 1}, {2, 1}};
 #define MAX_JUMP_SLOTS (sizeof(jumpSlots) / sizeof(jumpSlots[0]))
 
+void HexagonShuffler::restrictSlot1AOK() {
+  bool HasRestrictSlot1AOK = false;
+  SMLoc RestrictLoc;
+  for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
+    MCInst const &Inst = ISJ->getDesc();
+    if (HexagonMCInstrInfo::isRestrictSlot1AOK(MCII, Inst)) {
+      HasRestrictSlot1AOK = true;
+      RestrictLoc = Inst.getLoc();
+    }
+  }
+  if (HasRestrictSlot1AOK)
+    for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
+      MCInst const &Inst = ISJ->getDesc();
+      unsigned Type = HexagonMCInstrInfo::getType(MCII, Inst);
+      if (Type != HexagonII::TypeALU32_2op &&
+          Type != HexagonII::TypeALU32_3op &&
+          Type != HexagonII::TypeALU32_ADDI) {
+        unsigned Units = ISJ->Core.getUnits();
+        if (Units & 2U) {
+          AppliedRestrictions.push_back(std::make_pair(
+              Inst.getLoc(),
+              "Instruction was restricted from being in slot 1"));
+          AppliedRestrictions.push_back(
+              std::make_pair(RestrictLoc, "Instruction can only be combine "
+                                          "with an ALU instruction in slot 1"));
+          ISJ->Core.setUnits(Units & ~2U);
+        }
+      }
+    }
+}
+
+void HexagonShuffler::restrictNoSlot1Store() {
+  bool HasRestrictNoSlot1Store = false;
+  SMLoc RestrictLoc;
+  for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
+    MCInst const &Inst = ISJ->getDesc();
+    if (HexagonMCInstrInfo::isRestrictNoSlot1Store(MCII, Inst)) {
+      HasRestrictNoSlot1Store = true;
+      RestrictLoc = Inst.getLoc();
+    }
+  }
+  if (HasRestrictNoSlot1Store) {
+    bool AppliedRestriction = false;
+    for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
+      MCInst const &Inst = ISJ->getDesc();
+      if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) {
+        unsigned Units = ISJ->Core.getUnits();
+        if (Units & 2U) {
+          AppliedRestriction = true;
+          AppliedRestrictions.push_back(std::make_pair(
+              Inst.getLoc(),
+              "Instruction was restricted from being in slot 1"));
+          ISJ->Core.setUnits(Units & ~2U);
+        }
+      }
+    }
+    if (AppliedRestriction)
+      AppliedRestrictions.push_back(std::make_pair(
+          RestrictLoc, "Instruction does not allow a store in slot 1"));
+  }
+}
+
+void HexagonShuffler::applySlotRestrictions() {
+  restrictSlot1AOK();
+  restrictNoSlot1Store();
+}
+
 /// Check that the packet is legal and enforce relative insn order.
 bool HexagonShuffler::check() {
   // Descriptive slot masks.
-  const unsigned slotSingleLoad = 0x1, slotSingleStore = 0x1, slotOne = 0x2,
+  const unsigned slotSingleLoad = 0x1, slotSingleStore = 0x1,
                  slotThree = 0x8, // slotFirstJump = 0x8,
                  slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1;
   // Highest slots for branches and stores used to keep their original order.
   // unsigned slotJump = slotFirstJump;
   unsigned slotLoadStore = slotFirstLoadStore;
-  // Number of branches, solo branches, indirect branches.
-  unsigned jumps = 0, jump1 = 0;
   // Number of memory operations, loads, solo loads, stores, solo stores, single
   // stores.
   unsigned memory = 0, loads = 0, load0 = 0, stores = 0, store0 = 0, store1 = 0;
   // Number of duplex insns
   unsigned duplex = 0;
-  // Number of insns restricting other insns in slot #1 to A type.
-  unsigned onlyAin1 = 0;
-  // Number of insns restricting any insn in slot #1, except A2_nop.
-  unsigned onlyNo1 = 0;
   unsigned pSlot3Cnt = 0;
-  unsigned nvstores = 0;
   unsigned memops = 0;
-  unsigned deallocs = 0;
   iterator slot3ISJ = end();
   std::vector<iterator> foundBranches;
   unsigned reservedSlots = 0;
@@ -238,15 +312,11 @@ bool HexagonShuffler::check() {
   for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
     MCInst const &ID = ISJ->getDesc();
 
-    if (HexagonMCInstrInfo::isSoloAin1(MCII, ID))
-      ++onlyAin1;
     if (HexagonMCInstrInfo::prefersSlot3(MCII, ID)) {
       ++pSlot3Cnt;
       slot3ISJ = ISJ;
     }
     reservedSlots |= HexagonMCInstrInfo::getOtherReservedSlots(MCII, STI, ID);
-    if (HexagonMCInstrInfo::isCofMax1(MCII, ID))
-      ++jump1;
 
     switch (HexagonMCInstrInfo::getType(MCII, ID)) {
     case HexagonII::TypeS_2op:
@@ -254,30 +324,30 @@ bool HexagonShuffler::check() {
     case HexagonII::TypeALU64:
       break;
     case HexagonII::TypeJ:
-      ++jumps;
       foundBranches.push_back(ISJ);
       break;
     case HexagonII::TypeCVI_VM_VP_LDU:
-      ++onlyNo1;
-      LLVM_FALLTHROUGH;
     case HexagonII::TypeCVI_VM_LD:
     case HexagonII::TypeCVI_VM_TMP_LD:
+    case HexagonII::TypeCVI_GATHER:
+    case HexagonII::TypeCVI_GATHER_RST:
     case HexagonII::TypeLD:
       ++loads;
       ++memory;
       if (ISJ->Core.getUnits() == slotSingleLoad ||
           HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_VP_LDU)
         ++load0;
-      if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) {
-        ++deallocs, ++jumps, ++jump1; // DEALLOC_RETURN is of type LD.
+      if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn())
         foundBranches.push_back(ISJ);
-      }
       break;
     case HexagonII::TypeCVI_VM_STU:
-      ++onlyNo1;
-      LLVM_FALLTHROUGH;
     case HexagonII::TypeCVI_VM_ST:
     case HexagonII::TypeCVI_VM_NEW_ST:
+    case HexagonII::TypeCVI_SCATTER:
+    case HexagonII::TypeCVI_SCATTER_DV:
+    case HexagonII::TypeCVI_SCATTER_RST:
+    case HexagonII::TypeCVI_SCATTER_NEW_RST:
+    case HexagonII::TypeCVI_SCATTER_NEW_ST:
     case HexagonII::TypeST:
       ++stores;
       ++memory;
@@ -294,7 +364,6 @@ bool HexagonShuffler::check() {
       break;
     case HexagonII::TypeNCJ:
       ++memory; // NV insns are memory-like.
-      ++jumps, ++jump1;
       foundBranches.push_back(ISJ);
       break;
     case HexagonII::TypeV2LDST:
@@ -309,68 +378,38 @@ bool HexagonShuffler::check() {
         assert(HexagonMCInstrInfo::getDesc(MCII, ID).mayStore());
         ++memory;
         ++stores;
-        if (HexagonMCInstrInfo::isNewValue(MCII, ID))
-          ++nvstores;
       }
       break;
     case HexagonII::TypeCR:
     // Legacy conditional branch predicated on a register.
     case HexagonII::TypeCJ:
-      if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) {
-        ++jumps;
+      if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch())
         foundBranches.push_back(ISJ);
-      }
       break;
     case HexagonII::TypeDUPLEX: {
       ++duplex;
       MCInst const &Inst0 = *ID.getOperand(0).getInst();
       MCInst const &Inst1 = *ID.getOperand(1).getInst();
-      if (HexagonMCInstrInfo::isCofMax1(MCII, Inst0))
-        ++jump1;
-      if (HexagonMCInstrInfo::isCofMax1(MCII, Inst1))
-        ++jump1;
-      if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isBranch()) {
-        ++jumps;
+      if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isBranch())
         foundBranches.push_back(ISJ);
-      }
-      if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isBranch()) {
-        ++jumps;
+      if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isBranch())
         foundBranches.push_back(ISJ);
-      }
-      if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isReturn()) {
-        ++deallocs, ++jumps, ++jump1; // DEALLOC_RETURN is of type LD.
+      if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isReturn())
         foundBranches.push_back(ISJ);
-      }
-      if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn()) {
-        ++deallocs, ++jumps, ++jump1; // DEALLOC_RETURN is of type LD.
+      if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn())
         foundBranches.push_back(ISJ);
-      }
       break;
     }
     }
   }
+  applySlotRestrictions();
 
   // Check if the packet is legal.
-  if ((load0 > 1 || store0 > 1) ||
-      (duplex > 1 || (duplex && memory))) {
+  if ((load0 > 1 || store0 > 1) || (duplex > 1 || (duplex && memory))) {
     reportError(llvm::Twine("invalid instruction packet"));
     return false;
   }
 
-  if (jump1 && jumps > 1) {
-    // Error if single branch with another branch.
-    reportError(llvm::Twine("too many branches in packet"));
-    return false;
-  }
-  if ((nvstores || memops) && stores > 1) {
-    reportError(llvm::Twine("slot 0 instruction does not allow slot 1 store"));
-    return false;
-  }
-  if (deallocs && stores) {
-    reportError(llvm::Twine("slot 0 instruction does not allow slot 1 store"));
-    return false;
-  }
-
   // Modify packet accordingly.
   // TODO: need to reserve slots #0 and #1 for duplex insns.
   bool bOnlySlot3 = false;
@@ -382,35 +421,49 @@ bool HexagonShuffler::check() {
       return false;
     }
 
-    // Exclude from slot #1 any insn but A2_nop.
-    if (HexagonMCInstrInfo::getDesc(MCII, ID).getOpcode() != Hexagon::A2_nop)
-      if (onlyNo1)
-        ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne);
-
-    // Exclude from slot #1 any insn but A-type.
-    if (HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_2op &&
-        HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_3op &&
-        HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_ADDI)
-      if (onlyAin1)
-        ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne);
-
     // A single load must use slot #0.
     if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) {
       if (loads == 1 && loads == memory && memops == 0)
         // Pin the load to slot #0.
-        ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad);
+        switch (ID.getOpcode()) {
+        case Hexagon::V6_vgathermw:
+        case Hexagon::V6_vgathermh:
+        case Hexagon::V6_vgathermhw:
+        case Hexagon::V6_vgathermwq:
+        case Hexagon::V6_vgathermhq:
+        case Hexagon::V6_vgathermhwq:
+          // Slot1 only loads
+          break;
+        default:
+          ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad);
+          break;
+        }
+      else if (loads >= 1 && isMemReorderDisabled()) { // }:mem_noshuf
+        // Loads must keep the original order ONLY if
+        // isMemReorderDisabled() == true
+        if (slotLoadStore < slotLastLoadStore) {
+          // Error if no more slots available for loads.
+          reportError(
+              llvm::Twine("invalid instruction packet: too many loads"));
+          return false;
+        }
+        // Pin the load to the highest slot available to it.
+        ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore);
+        // Update the next highest slot available to loads.
+        slotLoadStore >>= 1;
+      }
     }
 
     // A single store must use slot #0.
     if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) {
       if (!store0) {
-        if (stores == 1)
+        if (stores == 1 && (loads == 0 || !isMemReorderDisabled()))
+          // Pin the store to slot #0 only if isMemReorderDisabled() == false
           ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore);
-        else if (stores > 1) {
+        else if (stores >= 1) {
           if (slotLoadStore < slotLastLoadStore) {
             // Error if no more slots available for stores.
-            reportError(
-                llvm::Twine("invalid instruction packet: too many stores"));
+            reportError(Twine("invalid instruction packet: too many stores"));
             return false;
           }
           // Pin the store to the highest slot available to it.
@@ -421,7 +474,7 @@ bool HexagonShuffler::check() {
       }
       if (store1 && stores > 1) {
         // Error if a single store with another store.
-        reportError(llvm::Twine("invalid instruction packet: too many stores"));
+        reportError(Twine("invalid instruction packet: too many stores"));
         return false;
       }
     }
@@ -432,16 +485,16 @@ bool HexagonShuffler::check() {
 
     if (!ISJ->Core.getUnits()) {
       // Error if insn may not be executed in any slot.
-      reportError(llvm::Twine("invalid instruction packet: out of slots"));
+      reportError(Twine("invalid instruction packet: out of slots"));
       return false;
     }
   }
 
   // preserve branch order
   bool validateSlots = true;
-  if (jumps > 1) {
+  if (foundBranches.size() > 1) {
     if (foundBranches.size() > 2) {
-      reportError(llvm::Twine("too many branches in packet"));
+      reportError(Twine("too many branches in packet"));
       return false;
     }
 
@@ -461,11 +514,11 @@ bool HexagonShuffler::check() {
       foundBranches[1]->Core.setUnits(jumpSlots[i].second);
 
       HexagonUnitAuction AuctionCore(reservedSlots);
-      std::sort(begin(), end(), HexagonInstr::lessCore);
+      std::stable_sort(begin(), end(), HexagonInstr::lessCore);
 
       // see if things ok with that instruction being pinned to slot "slotJump"
       bool bFail = false;
-      for (iterator I = begin(); I != end() && bFail != true; ++I)
+      for (iterator I = begin(); I != end() && !bFail; ++I)
         if (!AuctionCore.bid(I->Core.getUnits()))
           bFail = true;
 
@@ -477,13 +530,13 @@ bool HexagonShuffler::check() {
         // restore original values
         Packet = PacketSave;
     }
-    if (validateSlots == true) {
-      reportError(llvm::Twine("invalid instruction packet: out of slots"));
+    if (validateSlots) {
+      reportError(Twine("invalid instruction packet: out of slots"));
       return false;
     }
   }
 
-  if (jumps <= 1 && bOnlySlot3 == false && pSlot3Cnt == 1 &&
+  if (foundBranches.size() <= 1 && bOnlySlot3 == false && pSlot3Cnt == 1 &&
       slot3ISJ != end()) {
     validateSlots = true;
     // save off slot mask of instruction marked with A_PREFER_SLOT3
@@ -492,11 +545,11 @@ bool HexagonShuffler::check() {
     slot3ISJ->Core.setUnits(saveUnits & slotThree);
 
     HexagonUnitAuction AuctionCore(reservedSlots);
-    std::sort(begin(), end(), HexagonInstr::lessCore);
+    std::stable_sort(begin(), end(), HexagonInstr::lessCore);
 
     // see if things ok with that instruction being pinned to slot #3
     bool bFail = false;
-    for (iterator I = begin(); I != end() && bFail != true; ++I)
+    for (iterator I = begin(); I != end() && !bFail; ++I)
       if (!AuctionCore.bid(I->Core.getUnits()))
         bFail = true;
 
@@ -516,16 +569,16 @@ bool HexagonShuffler::check() {
   if (validateSlots) {
     HexagonUnitAuction AuctionCore(reservedSlots);
 
-    std::sort(begin(), end(), HexagonInstr::lessCore);
+    std::stable_sort(begin(), end(), HexagonInstr::lessCore);
 
     for (iterator I = begin(); I != end(); ++I)
       if (!AuctionCore.bid(I->Core.getUnits())) {
-        reportError(llvm::Twine("invalid instruction packet: slot error"));
+        reportError(Twine("invalid instruction packet: slot error"));
         return false;
       }
   }
   // Verify the CVI slot subscriptions.
-  std::sort(begin(), end(), HexagonInstr::lessCVI);
+  std::stable_sort(begin(), end(), HexagonInstr::lessCVI);
   // create vector of hvx instructions to check
   HVXInstsT hvxInsts;
   hvxInsts.clear();
@@ -541,9 +594,9 @@ bool HexagonShuffler::check() {
   if (hvxInsts.size() > 0) {
     unsigned startIdx, usedUnits;
     startIdx = usedUnits = 0x0;
-    if (checkHVXPipes(hvxInsts, startIdx, usedUnits) == false) {
+    if (!checkHVXPipes(hvxInsts, startIdx, usedUnits)) {
       // too many pipes used to be valid
-      reportError(llvm::Twine("invalid instruction packet: slot error"));
+      reportError(Twine("invalid instruction packet: slot error"));
       return false;
     }
   }
@@ -555,7 +608,7 @@ bool HexagonShuffler::shuffle() {
   if (size() > HEXAGON_PACKET_SIZE) {
     // Ignore a packet with with more than what a packet can hold
     // or with compound or duplex insns for now.
-    reportError(llvm::Twine("invalid instruction packet"));
+    reportError(Twine("invalid instruction packet"));
     return false;
   }
 
@@ -581,7 +634,7 @@ bool HexagonShuffler::shuffle() {
       if (slotWeight)
         // Sort the packet, favoring source order,
         // beginning after the previous slot.
-        std::sort(ISJ, Packet.end());
+        std::stable_sort(ISJ, Packet.end());
       else
         // Skip unused slot.
         ++emptySlots;
@@ -600,7 +653,13 @@ bool HexagonShuffler::shuffle() {
   return Ok;
 }
 
-void HexagonShuffler::reportError(llvm::Twine const &Msg) {
-  if (ReportErrors)
+void HexagonShuffler::reportError(Twine const &Msg) {
+  if (ReportErrors) {
+    for (auto const &I : AppliedRestrictions) {
+      auto SM = Context.getSourceManager();
+      if (SM)
+        SM->PrintMessage(I.first, SourceMgr::DK_Note, I.second);
+    }
     Context.reportError(Loc, Msg);
+  }
 }
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
index 10a959008f44..37f90bc46ac7 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
@@ -1,4 +1,4 @@
-//===----- HexagonShuffler.h - Instruction bundle shuffling ---------------===//
+//===- HexagonShuffler.h - Instruction bundle shuffling ---------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -12,19 +12,26 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef HEXAGONSHUFFLER_H
-#define HEXAGONSHUFFLER_H
+#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
+#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
 
 #include "Hexagon.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
-
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-
-using namespace llvm;
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/SMLoc.h"
+#include <cstdint>
+#include <utility>
 
 namespace llvm {
+
+class MCContext;
+class MCInst;
+class MCInstrInfo;
+class MCSubtargetInfo;
+
 // Insn resources.
 class HexagonResource {
   // Mask of the slots or units that may execute the insn and
@@ -32,32 +39,34 @@ class HexagonResource {
   unsigned Slots, Weight;
 
 public:
-  HexagonResource(unsigned s) { setUnits(s); };
+  HexagonResource(unsigned s) { setUnits(s); }
 
   void setUnits(unsigned s) {
     Slots = s & ((1u << HEXAGON_PACKET_SIZE) - 1);
     setWeight(s);
-  };
+  }
+
   unsigned setWeight(unsigned s);
 
-  unsigned getUnits() const { return (Slots); };
-  unsigned getWeight() const { return (Weight); };
+  unsigned getUnits() const { return (Slots); }
+  unsigned getWeight() const { return (Weight); }
 
   // Check if the resources are in ascending slot order.
   static bool lessUnits(const HexagonResource &A, const HexagonResource &B) {
     return (countPopulation(A.getUnits()) < countPopulation(B.getUnits()));
-  };
+  }
+
   // Check if the resources are in ascending weight order.
   static bool lessWeight(const HexagonResource &A, const HexagonResource &B) {
     return (A.getWeight() < B.getWeight());
-  };
+  }
 };
 
 // HVX insn resources.
 class HexagonCVIResource : public HexagonResource {
 public:
-  typedef std::pair<unsigned, unsigned> UnitsAndLanes;
-  typedef llvm::DenseMap<unsigned, UnitsAndLanes> TypeUnitsAndLanes;
+  using UnitsAndLanes = std::pair<unsigned, unsigned>;
+  using TypeUnitsAndLanes = DenseMap<unsigned, UnitsAndLanes>;
 
 private:
   // Available HVX slots.
@@ -69,8 +78,6 @@ private:
     CVI_MPY1 = 1 << 3
   };
 
-  TypeUnitsAndLanes *TUL;
-
   // Count of adjacent slots that the insn requires to be executed.
   unsigned Lanes;
   // Flag whether the insn is a load or a store.
@@ -78,19 +85,20 @@ private:
   // Flag whether the HVX resources are valid.
   bool Valid;
 
-  void setLanes(unsigned l) { Lanes = l; };
-  void setLoad(bool f = true) { Load = f; };
-  void setStore(bool f = true) { Store = f; };
+  void setLanes(unsigned l) { Lanes = l; }
+  void setLoad(bool f = true) { Load = f; }
+  void setStore(bool f = true) { Store = f; }
 
 public:
   HexagonCVIResource(TypeUnitsAndLanes *TUL, MCInstrInfo const &MCII,
                      unsigned s, MCInst const *id);
+
   static void SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU);
 
-  bool isValid() const { return Valid; };
-  unsigned getLanes() const { return Lanes; };
-  bool mayLoad() const { return Load; };
-  bool mayStore() const { return Store; };
+  bool isValid() const { return Valid; }
+  unsigned getLanes() const { return Lanes; }
+  bool mayLoad() const { return Load; }
+  bool mayStore() const { return Store; }
 };
 
 // Handle to an insn used by the shuffling algorithm.
@@ -106,30 +114,31 @@ public:
   HexagonInstr(HexagonCVIResource::TypeUnitsAndLanes *T,
                MCInstrInfo const &MCII, MCInst const *id,
                MCInst const *Extender, unsigned s)
-      : ID(id), Extender(Extender), Core(s), CVI(T, MCII, s, id) {};
-
-  MCInst const &getDesc() const { return *ID; };
+      : ID(id), Extender(Extender), Core(s), CVI(T, MCII, s, id) {}
 
+  MCInst const &getDesc() const { return *ID; }
   MCInst const *getExtender() const { return Extender; }
 
   // Check if the handles are in ascending order for shuffling purposes.
   bool operator<(const HexagonInstr &B) const {
     return (HexagonResource::lessWeight(B.Core, Core));
-  };
+  }
+
   // Check if the handles are in ascending order by core slots.
   static bool lessCore(const HexagonInstr &A, const HexagonInstr &B) {
     return (HexagonResource::lessUnits(A.Core, B.Core));
-  };
+  }
+
   // Check if the handles are in ascending order by HVX slots.
   static bool lessCVI(const HexagonInstr &A, const HexagonInstr &B) {
     return (HexagonResource::lessUnits(A.CVI, B.CVI));
-  };
+  }
 };
 
 // Bundle shuffler.
 class HexagonShuffler {
-  typedef SmallVector<HexagonInstr, HEXAGON_PRESHUFFLE_PACKET_SIZE>
-      HexagonPacket;
+  using HexagonPacket =
+      SmallVector<HexagonInstr, HEXAGON_PRESHUFFLE_PACKET_SIZE>;
 
   // Insn handles in a bundle.
   HexagonPacket Packet;
@@ -144,9 +153,13 @@ protected:
   MCSubtargetInfo const &STI;
   SMLoc Loc;
   bool ReportErrors;
+  std::vector<std::pair<SMLoc, std::string>> AppliedRestrictions;
+  void applySlotRestrictions();
+  void restrictSlot1AOK();
+  void restrictNoSlot1Store();
 
 public:
-  typedef HexagonPacket::iterator iterator;
+  using iterator = HexagonPacket::iterator;
 
   HexagonShuffler(MCContext &Context, bool ReportErrors,
                   MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
@@ -158,17 +171,22 @@ public:
   // Reorder the insn handles in the bundle.
   bool shuffle();
 
-  unsigned size() const { return (Packet.size()); };
+  unsigned size() const { return (Packet.size()); }
 
-  iterator begin() { return (Packet.begin()); };
-  iterator end() { return (Packet.end()); };
+  bool isMemReorderDisabled() const {
+    return (BundleFlags & HexagonMCInstrInfo::memReorderDisabledMask) != 0;
+  }
+
+  iterator begin() { return (Packet.begin()); }
+  iterator end() { return (Packet.end()); }
 
   // Add insn handle to the bundle .
   void append(MCInst const &ID, MCInst const *Extender, unsigned S);
 
   // Return the error code for the last check or shuffling of the bundle.
-  void reportError(llvm::Twine const &Msg);
+  void reportError(Twine const &Msg);
 };
-} // namespace llvm
 
-#endif // HEXAGONSHUFFLER_H
+} // end namespace llvm
+
+#endif //  LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
diff --git a/lib/Target/Hexagon/RDFCopy.cpp b/lib/Target/Hexagon/RDFCopy.cpp
index ea86ffba58f6..f8c766ac972c 100644
--- a/lib/Target/Hexagon/RDFCopy.cpp
+++ b/lib/Target/Hexagon/RDFCopy.cpp
@@ -1,4 +1,4 @@
-//===--- RDFCopy.cpp ------------------------------------------------------===//
+//===- RDFCopy.cpp --------------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -8,17 +8,27 @@
 //===----------------------------------------------------------------------===//
 //
 // RDF-based copy propagation.
+//
+//===----------------------------------------------------------------------===//
 
 #include "RDFCopy.h"
 #include "RDFGraph.h"
 #include "RDFLiveness.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "RDFRegisters.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+#include <cstdint>
+#include <utility>
+
 using namespace llvm;
 using namespace rdf;
 
@@ -50,13 +60,11 @@ bool CopyPropagation::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
   return false;
 }
 
-
 void CopyPropagation::recordCopy(NodeAddr<StmtNode*> SA, EqualityMap &EM) {
   CopyMap.insert(std::make_pair(SA.Id, EM));
   Copies.push_back(SA.Id);
 }
 
-
 bool CopyPropagation::scanBlock(MachineBasicBlock *B) {
   bool Changed = false;
   NodeAddr<BlockNode*> BA = DFG.findBlock(B);
@@ -77,7 +85,6 @@ bool CopyPropagation::scanBlock(MachineBasicBlock *B) {
   return Changed;
 }
 
-
 NodeId CopyPropagation::getLocalReachingDef(RegisterRef RefRR,
       NodeAddr<InstrNode*> IA) {
   NodeAddr<RefNode*> RA = L.getNearestAliasedRef(RefRR, IA);
@@ -91,7 +98,6 @@ NodeId CopyPropagation::getLocalReachingDef(RegisterRef RefRR,
   return 0;
 }
 
-
 bool CopyPropagation::run() {
   scanBlock(&DFG.getMF().front());
 
@@ -205,4 +211,3 @@ bool CopyPropagation::run() {
 
   return Changed;
 }
-
diff --git a/lib/Target/Hexagon/RDFCopy.h b/lib/Target/Hexagon/RDFCopy.h
index bbd625c5f5f6..7b2e78bdf633 100644
--- a/lib/Target/Hexagon/RDFCopy.h
+++ b/lib/Target/Hexagon/RDFCopy.h
@@ -1,4 +1,4 @@
-//===--- RDFCopy.h ----------------------------------------------*- C++ -*-===//
+//===- RDFCopy.h ------------------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -12,22 +12,22 @@
 
 #include "RDFGraph.h"
 #include "RDFLiveness.h"
+#include "RDFRegisters.h"
 #include "llvm/CodeGen/MachineFunction.h"
-
 #include <map>
 #include <vector>
 
 namespace llvm {
 
-  class MachineBasicBlock;
-  class MachineDominatorTree;
-  class MachineInstr;
+class MachineBasicBlock;
+class MachineDominatorTree;
+class MachineInstr;
 
 namespace rdf {
 
   struct CopyPropagation {
     CopyPropagation(DataFlowGraph &dfg) : MDT(dfg.getDT()), DFG(dfg),
-        L(dfg.getMF().getRegInfo(), dfg), Trace(false) {}
+        L(dfg.getMF().getRegInfo(), dfg) {}
 
     virtual ~CopyPropagation() = default;
 
@@ -36,14 +36,15 @@ namespace rdf {
     bool trace() const { return Trace; }
     DataFlowGraph &getDFG() { return DFG; }
 
-    typedef std::map<RegisterRef, RegisterRef> EqualityMap;
+    using EqualityMap = std::map<RegisterRef, RegisterRef>;
+
     virtual bool interpretAsCopy(const MachineInstr *MI, EqualityMap &EM);
 
   private:
     const MachineDominatorTree &MDT;
     DataFlowGraph &DFG;
     Liveness L;
-    bool Trace;
+    bool Trace = false;
 
     // map: statement -> (map: dst reg -> src reg)
     std::map<NodeId, EqualityMap> CopyMap;
diff --git a/lib/Target/Hexagon/RDFDeadCode.cpp b/lib/Target/Hexagon/RDFDeadCode.cpp
index 60a12dcf2f03..240d7c355bc7 100644
--- a/lib/Target/Hexagon/RDFDeadCode.cpp
+++ b/lib/Target/Hexagon/RDFDeadCode.cpp
@@ -58,7 +58,8 @@ private:
 bool DeadCodeElimination::isLiveInstr(const MachineInstr *MI) const {
   if (MI->mayStore() || MI->isBranch() || MI->isCall() || MI->isReturn())
     return true;
-  if (MI->hasOrderedMemoryRef() || MI->hasUnmodeledSideEffects())
+  if (MI->hasOrderedMemoryRef() || MI->hasUnmodeledSideEffects() ||
+      MI->isPosition())
     return true;
   if (MI->isPHI())
     return false;
diff --git a/lib/Target/Hexagon/RDFGraph.cpp b/lib/Target/Hexagon/RDFGraph.cpp
index 8d1272370899..d1f6e5a4c8ef 100644
--- a/lib/Target/Hexagon/RDFGraph.cpp
+++ b/lib/Target/Hexagon/RDFGraph.cpp
@@ -1,4 +1,4 @@
-//===--- RDFGraph.cpp -----------------------------------------------------===//
+//===- RDFGraph.cpp -------------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -10,6 +10,8 @@
 // Target-independent, SSA-based data flow graph for register data flow (RDF).
 //
 #include "RDFGraph.h"
+#include "RDFRegisters.h"
+#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
@@ -19,20 +21,23 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/Function.h"
 #include "llvm/MC/LaneBitmask.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
 #include <cstring>
 #include <iterator>
+#include <set>
 #include <utility>
 #include <vector>
 
@@ -201,7 +206,7 @@ namespace {
   struct PrintListV {
     PrintListV(const NodeList &L, const DataFlowGraph &G) : List(L), G(G) {}
 
-    typedef T Type;
+    using Type = T;
     const NodeList &List;
     const DataFlowGraph &G;
   };
@@ -242,7 +247,7 @@ raw_ostream &operator<< (raw_ostream &OS,
     if (T != MI.operands_end()) {
       OS << ' ';
       if (T->isMBB())
-        OS << "BB#" << T->getMBB()->getNumber();
+        OS << printMBBReference(*T->getMBB());
       else if (T->isGlobal())
         OS << T->getGlobal()->getName();
       else if (T->isSymbol())
@@ -279,13 +284,13 @@ raw_ostream &operator<< (raw_ostream &OS,
   auto PrintBBs = [&OS] (std::vector<int> Ns) -> void {
     unsigned N = Ns.size();
     for (int I : Ns) {
-      OS << "BB#" << I;
+      OS << "%bb." << I;
       if (--N)
         OS << ", ";
     }
   };
 
-  OS << Print<NodeId>(P.Obj.Id, P.G) << ": --- BB#" << BB->getNumber()
+  OS << Print<NodeId>(P.Obj.Id, P.G) << ": --- " << printMBBReference(*BB)
      << " --- preds(" << NP << "): ";
   for (MachineBasicBlock *B : BB->predecessors())
     Ns.push_back(B->getNumber());
@@ -761,7 +766,7 @@ unsigned DataFlowGraph::DefStack::nextDown(unsigned P) const {
 
 RegisterSet DataFlowGraph::getLandingPadLiveIns() const {
   RegisterSet LR;
-  const Function &F = *MF.getFunction();
+  const Function &F = MF.getFunction();
   const Constant *PF = F.hasPersonalityFn() ? F.getPersonalityFn()
                                             : nullptr;
   const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
@@ -898,15 +903,18 @@ void DataFlowGraph::build(unsigned Options) {
   NodeList Blocks = Func.Addr->members(*this);
 
   // Collect information about block references.
-  BlockRefsMap RefM;
-  buildBlockRefs(EA, RefM);
+  RegisterSet AllRefs;
+  for (NodeAddr<BlockNode*> BA : Blocks)
+    for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this))
+      for (NodeAddr<RefNode*> RA : IA.Addr->members(*this))
+        AllRefs.insert(RA.Addr->getRegRef(*this));
 
   // Collect function live-ins and entry block live-ins.
   MachineRegisterInfo &MRI = MF.getRegInfo();
   MachineBasicBlock &EntryB = *EA.Addr->getCode();
   assert(EntryB.pred_empty() && "Function entry block has predecessors");
-  for (auto I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I)
-    LiveIns.insert(RegisterRef(I->first));
+  for (std::pair<unsigned,unsigned> P : MRI.liveins())
+    LiveIns.insert(RegisterRef(P.first));
   if (MRI.tracksLiveness()) {
     for (auto I : EntryB.liveins())
       LiveIns.insert(RegisterRef(I.PhysReg, I.LaneMask));
@@ -959,9 +967,9 @@ void DataFlowGraph::build(unsigned Options) {
   // of references that will require phi definitions in that block.
   BlockRefsMap PhiM;
   for (NodeAddr<BlockNode*> BA : Blocks)
-    recordDefsForDF(PhiM, RefM, BA);
+    recordDefsForDF(PhiM, BA);
   for (NodeAddr<BlockNode*> BA : Blocks)
-    buildPhis(PhiM, RefM, BA);
+    buildPhis(PhiM, AllRefs, BA);
 
   // Link all the refs. This will recursively traverse the dominator tree.
   DefStackMap DM;
@@ -1115,8 +1123,8 @@ void DataFlowGraph::pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) {
     if (!Defined.insert(RR.Reg).second) {
       MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
       dbgs() << "Multiple definitions of register: "
-             << Print<RegisterRef>(RR, *this) << " in\n  " << *MI
-             << "in BB#" << MI->getParent()->getNumber() << '\n';
+             << Print<RegisterRef>(RR, *this) << " in\n  " << *MI << "in "
+             << printMBBReference(*MI->getParent()) << '\n';
       llvm_unreachable(nullptr);
     }
 #endif
@@ -1389,29 +1397,9 @@ void DataFlowGraph::buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In) {
   }
 }
 
-// Build a map that for each block will have the set of all references from
-// that block, and from all blocks dominated by it.
-void DataFlowGraph::buildBlockRefs(NodeAddr<BlockNode*> BA,
-      BlockRefsMap &RefM) {
-  RegisterSet &Refs = RefM[BA.Id];
-  MachineDomTreeNode *N = MDT.getNode(BA.Addr->getCode());
-  assert(N);
-  for (auto I : *N) {
-    MachineBasicBlock *SB = I->getBlock();
-    NodeAddr<BlockNode*> SBA = findBlock(SB);
-    buildBlockRefs(SBA, RefM);
-    const RegisterSet &RefsS = RefM[SBA.Id];
-    Refs.insert(RefsS.begin(), RefsS.end());
-  }
-
-  for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this))
-    for (NodeAddr<RefNode*> RA : IA.Addr->members(*this))
-      Refs.insert(RA.Addr->getRegRef(*this));
-}
-
 // Scan all defs in the block node BA and record in PhiM the locations of
 // phi nodes corresponding to these defs.
-void DataFlowGraph::recordDefsForDF(BlockRefsMap &PhiM, BlockRefsMap &RefM,
+void DataFlowGraph::recordDefsForDF(BlockRefsMap &PhiM,
       NodeAddr<BlockNode*> BA) {
   // Check all defs from block BA and record them in each block in BA's
   // iterated dominance frontier. This information will later be used to
@@ -1441,14 +1429,6 @@ void DataFlowGraph::recordDefsForDF(BlockRefsMap &PhiM, BlockRefsMap &RefM,
       IDF.insert(F->second.begin(), F->second.end());
   }
 
-  // Get the register references that are reachable from this block.
-  RegisterSet &Refs = RefM[BA.Id];
-  for (auto DB : IDF) {
-    NodeAddr<BlockNode*> DBA = findBlock(DB);
-    const RegisterSet &RefsD = RefM[DBA.Id];
-    Refs.insert(RefsD.begin(), RefsD.end());
-  }
-
   // Finally, add the set of defs to each block in the iterated dominance
   // frontier.
   for (auto DB : IDF) {
@@ -1459,7 +1439,7 @@ void DataFlowGraph::recordDefsForDF(BlockRefsMap &PhiM, BlockRefsMap &RefM,
 
 // Given the locations of phi nodes in the map PhiM, create the phi nodes
 // that are located in the block node BA.
-void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, BlockRefsMap &RefM,
+void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs,
       NodeAddr<BlockNode*> BA) {
   // Check if this blocks has any DF defs, i.e. if there are any defs
   // that this block is in the iterated dominance frontier of.
@@ -1483,9 +1463,8 @@ void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, BlockRefsMap &RefM,
     MaxDF.insert(MaxCoverIn(I, HasDF->second));
 
   std::vector<RegisterRef> MaxRefs;
-  RegisterSet &RefB = RefM[BA.Id];
   for (RegisterRef I : MaxDF)
-    MaxRefs.push_back(MaxCoverIn(I, RefB));
+    MaxRefs.push_back(MaxCoverIn(I, AllRefs));
 
   // Now, for each R in MaxRefs, get the alias closure of R. If the closure
   // only has R in it, create a phi a def for R. Otherwise, create a phi,
diff --git a/lib/Target/Hexagon/RDFGraph.h b/lib/Target/Hexagon/RDFGraph.h
index 52f390356b26..e3abb0e22f76 100644
--- a/lib/Target/Hexagon/RDFGraph.h
+++ b/lib/Target/Hexagon/RDFGraph.h
@@ -1,4 +1,4 @@
-//===--- RDFGraph.h ---------------------------------------------*- C++ -*-===//
+//===- RDFGraph.h -----------------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -111,7 +111,7 @@
 //
 //   DFG dump:[
 //   f1: Function foo
-//   b2: === BB#0 === preds(0), succs(0):
+//   b2: === %bb.0 === preds(0), succs(0):
 //   p3: phi [d4<r0>(,d12,u9):]
 //   p5: phi [d6<r1>(,,u10):]
 //   s7: add [d8<r2>(,,u13):, u9<r0>(d4):, u10<r1>(d6):]
@@ -183,7 +183,7 @@
 //   This is typically used to prevent keeping registers artificially live
 //   in cases when they are defined via predicated instructions. For example:
 //     r0 = add-if-true cond, r10, r11                (1)
-//     r0 = add-if-false cond, r12, r13, r0<imp-use>  (2)
+//     r0 = add-if-false cond, r12, r13, implicit r0  (2)
 //     ... = r0                                       (3)
 //   Before (1), r0 is not intended to be live, and the use of r0 in (3) is
 //   not meant to be reached by any def preceding (1). However, since the
@@ -226,17 +226,13 @@
 #define LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H
 
 #include "RDFRegisters.h"
-#include "llvm/ADT/BitVector.h"
-#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/LaneBitmask.h"
 #include "llvm/Support/Allocator.h"
 #include "llvm/Support/MathExtras.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include <cassert>
 #include <cstdint>
 #include <cstring>
-#include <functional>
 #include <map>
 #include <set>
 #include <unordered_map>
@@ -250,17 +246,19 @@ static_assert(sizeof(uint32_t) == sizeof(unsigned), "Those should be equal");
 
 namespace llvm {
 
-  class MachineBasicBlock;
-  class MachineFunction;
-  class MachineInstr;
-  class MachineOperand;
-  class MachineDominanceFrontier;
-  class MachineDominatorTree;
-  class TargetInstrInfo;
+class MachineBasicBlock;
+class MachineDominanceFrontier;
+class MachineDominatorTree;
+class MachineFunction;
+class MachineInstr;
+class MachineOperand;
+class raw_ostream;
+class TargetInstrInfo;
+class TargetRegisterInfo;
 
 namespace rdf {
 
-  typedef uint32_t NodeId;
+  using NodeId = uint32_t;
 
   struct DataFlowGraph;
 
@@ -335,7 +333,7 @@ namespace rdf {
   };
 
   template <typename T> struct NodeAddr {
-    NodeAddr() : Addr(nullptr) {}
+    NodeAddr() = default;
     NodeAddr(T A, NodeId I) : Addr(A), Id(I) {}
 
     // Type cast (casting constructor). The reason for having this class
@@ -351,7 +349,7 @@ namespace rdf {
       return !operator==(NA);
     }
 
-    T Addr;
+    T Addr = nullptr;
     NodeId Id = 0;
   };
 
@@ -408,11 +406,11 @@ namespace rdf {
     const uint32_t IndexMask;
     char *ActiveEnd = nullptr;
     std::vector<char*> Blocks;
-    typedef BumpPtrAllocatorImpl<MallocAllocator, 65536> AllocatorTy;
+    using AllocatorTy = BumpPtrAllocatorImpl<MallocAllocator, 65536>;
     AllocatorTy MemPool;
   };
 
-  typedef std::set<RegisterRef> RegisterSet;
+  using RegisterSet = std::set<RegisterRef>;
 
   struct TargetOperandInfo {
     TargetOperandInfo(const TargetInstrInfo &tii) : TII(tii) {}
@@ -437,10 +435,12 @@ namespace rdf {
     LaneBitmask getLaneMaskForIndex(uint32_t K) const {
       return K == 0 ? LaneBitmask::getAll() : get(K);
     }
+
     uint32_t getIndexForLaneMask(LaneBitmask LM) {
       assert(LM.any());
       return LM.all() ? 0 : insert(LM);
     }
+
     uint32_t getIndexForLaneMask(LaneBitmask LM) const {
       assert(LM.any());
       return LM.all() ? 0 : find(LM);
@@ -463,8 +463,10 @@ namespace rdf {
 
     // Insert node NA after "this" in the circular chain.
     void append(NodeAddr<NodeBase*> NA);
+
     // Initialize all members to 0.
     void init() { memset(this, 0, sizeof *this); }
+
     void setNext(NodeId N) { Next = N; }
 
   protected:
@@ -508,9 +510,8 @@ namespace rdf {
   static_assert(sizeof(NodeBase) <= NodeAllocator::NodeMemSize,
         "NodeBase must be at most NodeAllocator::NodeMemSize bytes");
 
-//  typedef std::vector<NodeAddr<NodeBase*>> NodeList;
-  typedef SmallVector<NodeAddr<NodeBase*>,4> NodeList;
-  typedef std::set<NodeId> NodeSet;
+  using NodeList = SmallVector<NodeAddr<NodeBase *>, 4>;
+  using NodeSet = std::set<NodeId>;
 
   struct RefNode : public NodeBase {
     RefNode() = default;
@@ -672,9 +673,9 @@ namespace rdf {
       bool empty() const { return Stack.empty() || top() == bottom(); }
 
     private:
-      typedef NodeAddr<DefNode*> value_type;
+      using value_type = NodeAddr<DefNode *>;
       struct Iterator {
-        typedef DefStack::value_type value_type;
+        using value_type = DefStack::value_type;
 
         Iterator &up() { Pos = DS.nextUp(Pos); return *this; }
         Iterator &down() { Pos = DS.nextDown(Pos); return *this; }
@@ -691,17 +692,19 @@ namespace rdf {
         bool operator!=(const Iterator &It) const { return Pos != It.Pos; }
 
       private:
+        friend struct DefStack;
+
         Iterator(const DefStack &S, bool Top);
 
         // Pos-1 is the index in the StorageType object that corresponds to
         // the top of the DefStack.
         const DefStack &DS;
         unsigned Pos;
-        friend struct DefStack;
       };
 
     public:
-      typedef Iterator iterator;
+      using iterator = Iterator;
+
       iterator top() const { return Iterator(*this, true); }
       iterator bottom() const { return Iterator(*this, false); }
       unsigned size() const;
@@ -713,7 +716,8 @@ namespace rdf {
 
     private:
       friend struct Iterator;
-      typedef std::vector<value_type> StorageType;
+
+      using StorageType = std::vector<value_type>;
 
       bool isDelimiter(const StorageType::value_type &P, NodeId N = 0) const {
         return (P.Addr == nullptr) && (N == 0 || P.Id == N);
@@ -727,7 +731,7 @@ namespace rdf {
 
     // Make this std::unordered_map for speed of accessing elements.
     // Map: Register (physical or virtual) -> DefStack
-    typedef std::unordered_map<RegisterId,DefStack> DefStackMap;
+    using DefStackMap = std::unordered_map<RegisterId, DefStack>;
 
     void build(unsigned Options = BuildOptions::None);
     void pushAllDefs(NodeAddr<InstrNode*> IA, DefStackMap &DM);
@@ -839,13 +843,11 @@ namespace rdf {
     locateNextRef(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA,
         Predicate P) const;
 
-    typedef std::map<NodeId,RegisterSet> BlockRefsMap;
+    using BlockRefsMap = std::map<NodeId, RegisterSet>;
 
     void buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In);
-    void buildBlockRefs(NodeAddr<BlockNode*> BA, BlockRefsMap &RefM);
-    void recordDefsForDF(BlockRefsMap &PhiM, BlockRefsMap &RefM,
-        NodeAddr<BlockNode*> BA);
-    void buildPhis(BlockRefsMap &PhiM, BlockRefsMap &RefM,
+    void recordDefsForDF(BlockRefsMap &PhiM, NodeAddr<BlockNode*> BA);
+    void buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs,
         NodeAddr<BlockNode*> BA);
     void removeUnusedPhis();
 
@@ -923,7 +925,6 @@ namespace rdf {
     return MM;
   }
 
-
   template <typename T> struct Print;
   template <typename T>
   raw_ostream &operator<< (raw_ostream &OS, const Print<T> &P);
@@ -931,6 +932,7 @@ namespace rdf {
   template <typename T>
   struct Print {
     Print(const T &x, const DataFlowGraph &g) : Obj(x), G(g) {}
+
     const T &Obj;
     const DataFlowGraph &G;
   };
diff --git a/lib/Target/Hexagon/RDFLiveness.cpp b/lib/Target/Hexagon/RDFLiveness.cpp
index 83e8968086d8..13d9a1741978 100644
--- a/lib/Target/Hexagon/RDFLiveness.cpp
+++ b/lib/Target/Hexagon/RDFLiveness.cpp
@@ -1,4 +1,4 @@
-//===--- RDFLiveness.cpp --------------------------------------------------===//
+//===- RDFLiveness.cpp ----------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -25,14 +25,29 @@
 //
 #include "RDFLiveness.h"
 #include "RDFGraph.h"
+#include "RDFRegisters.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineDominanceFrontier.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <iterator>
+#include <map>
+#include <utility>
+#include <vector>
 
 using namespace llvm;
 using namespace rdf;
@@ -42,11 +57,12 @@ static cl::opt<unsigned> MaxRecNest("rdf-liveness-max-rec", cl::init(25),
 
 namespace llvm {
 namespace rdf {
+
   template<>
   raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) {
     OS << '{';
     for (auto &I : P.Obj) {
-      OS << ' ' << PrintReg(I.first, &P.G.getTRI()) << '{';
+      OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{';
       for (auto J = I.second.begin(), E = I.second.end(); J != E; ) {
         OS << Print<NodeId>(J->first, P.G) << PrintLaneMaskOpt(J->second);
         if (++J != E)
@@ -57,8 +73,9 @@ namespace rdf {
     OS << " }";
     return OS;
   }
-} // namespace rdf
-} // namespace llvm
+
+} // end namespace rdf
+} // end namespace llvm
 
 // The order in the returned sequence is the order of reaching defs in the
 // upward traversal: the first def is the closest to the given reference RefA,
@@ -245,19 +262,17 @@ NodeList Liveness::getAllReachingDefs(RegisterRef RefRR,
   auto DeadP = [](const NodeAddr<DefNode*> DA) -> bool {
     return DA.Addr->getFlags() & NodeAttrs::Dead;
   };
-  RDefs.resize(std::distance(RDefs.begin(), remove_if(RDefs, DeadP)));
+  RDefs.resize(std::distance(RDefs.begin(), llvm::remove_if(RDefs, DeadP)));
 
   return RDefs;
 }
 
-
 std::pair<NodeSet,bool>
 Liveness::getAllReachingDefsRec(RegisterRef RefRR, NodeAddr<RefNode*> RefA,
       NodeSet &Visited, const NodeSet &Defs) {
   return getAllReachingDefsRecImpl(RefRR, RefA, Visited, Defs, 0, MaxRecNest);
 }
 
-
 std::pair<NodeSet,bool>
 Liveness::getAllReachingDefsRecImpl(RegisterRef RefRR, NodeAddr<RefNode*> RefA,
       NodeSet &Visited, const NodeSet &Defs, unsigned Nest, unsigned MaxNest) {
@@ -363,7 +378,6 @@ NodeAddr<RefNode*> Liveness::getNearestAliasedRef(RegisterRef RefRR,
   return NodeAddr<RefNode*>();
 }
 
-
 NodeSet Liveness::getAllReachedUses(RegisterRef RefRR,
       NodeAddr<DefNode*> DefA, const RegisterAggr &DefRRs) {
   NodeSet Uses;
@@ -410,7 +424,6 @@ NodeSet Liveness::getAllReachedUses(RegisterRef RefRR,
   return Uses;
 }
 
-
 void Liveness::computePhiInfo() {
   RealUseMap.clear();
 
@@ -668,7 +681,6 @@ void Liveness::computePhiInfo() {
   }
 }
 
-
 void Liveness::computeLiveIns() {
   // Populate the node-to-block map. This speeds up the calculations
   // significantly.
@@ -802,7 +814,7 @@ void Liveness::computeLiveIns() {
       for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I)
         LV.push_back(RegisterRef(I->PhysReg, I->LaneMask));
       std::sort(LV.begin(), LV.end());
-      dbgs() << "BB#" << B.getNumber() << "\t rec = {";
+      dbgs() << printMBBReference(B) << "\t rec = {";
       for (auto I : LV)
         dbgs() << ' ' << Print<RegisterRef>(I, DFG);
       dbgs() << " }\n";
@@ -822,7 +834,6 @@ void Liveness::computeLiveIns() {
   }
 }
 
-
 void Liveness::resetLiveIns() {
   for (auto &B : DFG.getMF()) {
     // Remove all live-ins.
@@ -840,13 +851,11 @@ void Liveness::resetLiveIns() {
   }
 }
 
-
 void Liveness::resetKills() {
   for (auto &B : DFG.getMF())
     resetKills(&B);
 }
 
-
 void Liveness::resetKills(MachineBasicBlock *B) {
   auto CopyLiveIns = [this] (MachineBasicBlock *B, BitVector &LV) -> void {
     for (auto I : B->liveins()) {
@@ -909,7 +918,6 @@ void Liveness::resetKills(MachineBasicBlock *B) {
   }
 }
 
-
 // Helper function to obtain the basic block containing the reaching def
 // of the given use.
 MachineBasicBlock *Liveness::getBlockWithRef(NodeId RN) const {
@@ -919,7 +927,6 @@ MachineBasicBlock *Liveness::getBlockWithRef(NodeId RN) const {
   llvm_unreachable("Node id not in map");
 }
 
-
 void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
   // The LiveIn map, for each (physical) register, contains the set of live
   // reaching defs of that register that are live on entry to the associated
@@ -956,7 +963,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
   }
 
   if (Trace) {
-    dbgs() << "\n-- BB#" << B->getNumber() << ": " << __func__
+    dbgs() << "\n-- " << printMBBReference(*B) << ": " << __func__
            << " after recursion into: {";
     for (auto I : *N)
       dbgs() << ' ' << I->getBlock()->getNumber();
@@ -1107,9 +1114,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
   }
 }
 
-
 void Liveness::emptify(RefMap &M) {
   for (auto I = M.begin(), E = M.end(); I != E; )
     I = I->second.empty() ? M.erase(I) : std::next(I);
 }
-
diff --git a/lib/Target/Hexagon/RDFLiveness.h b/lib/Target/Hexagon/RDFLiveness.h
index 6f2615b7c4f3..8cfb6a1e9554 100644
--- a/lib/Target/Hexagon/RDFLiveness.h
+++ b/lib/Target/Hexagon/RDFLiveness.h
@@ -1,4 +1,4 @@
-//===--- RDFLiveness.h ----------------------------------------------------===//
+//===- RDFLiveness.h --------------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -10,24 +10,27 @@
 // Recalculate the liveness information given a data flow graph.
 // This includes block live-ins and kill flags.
 
-#ifndef RDF_LIVENESS_H
-#define RDF_LIVENESS_H
+#ifndef LLVM_LIB_TARGET_HEXAGON_RDFLIVENESS_H
+#define LLVM_LIB_TARGET_HEXAGON_RDFLIVENESS_H
 
 #include "RDFGraph.h"
+#include "RDFRegisters.h"
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/MC/LaneBitmask.h"
 #include <map>
-
-using namespace llvm;
+#include <set>
+#include <utility>
 
 namespace llvm {
-  class MachineBasicBlock;
-  class MachineFunction;
-  class MachineRegisterInfo;
-  class TargetRegisterInfo;
-  class MachineDominatorTree;
-  class MachineDominanceFrontier;
+
+class MachineBasicBlock;
+class MachineDominanceFrontier;
+class MachineDominatorTree;
+class MachineRegisterInfo;
+class TargetRegisterInfo;
 
 namespace rdf {
+
   struct Liveness {
   public:
     // This is really a std::map, except that it provides a non-trivial
@@ -38,32 +41,36 @@ namespace rdf {
       RegisterAggr &operator[] (MachineBasicBlock *B) {
         return Map.emplace(B, Empty).first->second;
       }
+
     private:
       RegisterAggr Empty;
       std::map<MachineBasicBlock*,RegisterAggr> Map;
     };
 
-    typedef std::pair<NodeId,LaneBitmask> NodeRef;
-    typedef std::set<NodeRef> NodeRefSet;
+    using NodeRef = std::pair<NodeId, LaneBitmask>;
+    using NodeRefSet = std::set<NodeRef>;
     // RegisterId in RefMap must be normalized.
-    typedef std::map<RegisterId,NodeRefSet> RefMap;
+    using RefMap = std::map<RegisterId, NodeRefSet>;
 
     Liveness(MachineRegisterInfo &mri, const DataFlowGraph &g)
       : DFG(g), TRI(g.getTRI()), PRI(g.getPRI()), MDT(g.getDT()),
-        MDF(g.getDF()), LiveMap(g.getPRI()), Empty(),
-        NoRegs(g.getPRI()), Trace(false) {}
+        MDF(g.getDF()), LiveMap(g.getPRI()), NoRegs(g.getPRI()) {}
 
     NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA,
         bool TopShadows, bool FullChain, const RegisterAggr &DefRRs);
+
     NodeList getAllReachingDefs(NodeAddr<RefNode*> RefA) {
       return getAllReachingDefs(RefA.Addr->getRegRef(DFG), RefA, false,
                                 false, NoRegs);
     }
+
     NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA) {
       return getAllReachingDefs(RefRR, RefA, false, false, NoRegs);
     }
+
     NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA,
         const RegisterAggr &DefRRs);
+
     NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA) {
       return getAllReachedUses(RefRR, DefA, NoRegs);
     }
@@ -76,6 +83,7 @@ namespace rdf {
 
     LiveMapType &getLiveMap() { return LiveMap; }
     const LiveMapType &getLiveMap() const { return LiveMap; }
+
     const RefMap &getRealUses(NodeId P) const {
       auto F = RealUseMap.find(P);
       return F == RealUseMap.end() ? Empty : F->second;
@@ -98,12 +106,12 @@ namespace rdf {
     LiveMapType LiveMap;
     const RefMap Empty;
     const RegisterAggr NoRegs;
-    bool Trace;
+    bool Trace = false;
 
     // Cache of mapping from node ids (for RefNodes) to the containing
     // basic blocks. Not computing it each time for each node reduces
     // the liveness calculation time by a large fraction.
-    typedef DenseMap<NodeId,MachineBasicBlock*> NodeBlockMap;
+    using NodeBlockMap = DenseMap<NodeId, MachineBasicBlock *>;
     NodeBlockMap NBMap;
 
     // Phi information:
@@ -134,7 +142,9 @@ namespace rdf {
         NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs,
         unsigned Nest, unsigned MaxNest);
   };
-} // namespace rdf
-} // namespace llvm
 
-#endif // RDF_LIVENESS_H
+} // end namespace rdf
+
+} // end namespace llvm
+
+#endif // LLVM_LIB_TARGET_HEXAGON_RDFLIVENESS_H
diff --git a/lib/Target/Hexagon/RDFRegisters.cpp b/lib/Target/Hexagon/RDFRegisters.cpp
index 2aabf4ee1a38..9408c5dc3952 100644
--- a/lib/Target/Hexagon/RDFRegisters.cpp
+++ b/lib/Target/Hexagon/RDFRegisters.cpp
@@ -1,4 +1,4 @@
-//===--- RDFRegisters.cpp ---------------------------------------*- C++ -*-===//
+//===- RDFRegisters.cpp ---------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -10,6 +10,17 @@
 #include "RDFRegisters.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+#include <cstdint>
+#include <set>
+#include <utility>
 
 using namespace llvm;
 using namespace rdf;
@@ -227,7 +238,6 @@ RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const {
   llvm_unreachable("Invalid arguments: unrelated registers?");
 }
 
-
 bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
   if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
     return Units.anyCommon(PRI.getMaskUnits(RR.Reg));
@@ -355,7 +365,7 @@ RegisterRef RegisterAggr::makeRegRef() const {
 void RegisterAggr::print(raw_ostream &OS) const {
   OS << '{';
   for (int U = Units.find_first(); U >= 0; U = Units.find_next(U))
-    OS << ' ' << PrintRegUnit(U, &PRI.getTRI());
+    OS << ' ' << printRegUnit(U, &PRI.getTRI());
   OS << " }";
 }
 
@@ -369,4 +379,3 @@ RegisterAggr::rr_iterator::rr_iterator(const RegisterAggr &RG,
   Pos = End ? Masks.end() : Masks.begin();
   Index = End ? Masks.size() : 0;
 }
-
diff --git a/lib/Target/Hexagon/RDFRegisters.h b/lib/Target/Hexagon/RDFRegisters.h
index 09b733ce616b..459850d87df1 100644
--- a/lib/Target/Hexagon/RDFRegisters.h
+++ b/lib/Target/Hexagon/RDFRegisters.h
@@ -1,4 +1,4 @@
-//===--- RDFRegisters.h -----------------------------------------*- C++ -*-===//
+//===- RDFRegisters.h -------------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -11,16 +11,23 @@
 #define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
 
 #include "llvm/ADT/BitVector.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/MC/LaneBitmask.h"
+#include <cassert>
+#include <cstdint>
+#include <map>
 #include <set>
-#include <unordered_map>
 #include <vector>
 
 namespace llvm {
+
+class MachineFunction;
+class raw_ostream;
+
 namespace rdf {
 
-  typedef uint32_t RegisterId;
+  using RegisterId = uint32_t;
 
   // Template class for a map translating uint32_t into arbitrary types.
   // The map will act like an indexed set: upon insertion of a new object,
@@ -28,7 +35,7 @@ namespace rdf {
   // as invalid and is never allocated.
   template <typename T, unsigned N = 32>
   struct IndexedSet {
-    IndexedSet() : Map() { Map.reserve(N); }
+    IndexedSet() { Map.reserve(N); }
 
     T get(uint32_t Idx) const {
       // Index Idx corresponds to Map[Idx-1].
@@ -53,7 +60,8 @@ namespace rdf {
 
     uint32_t size() const { return Map.size(); }
 
-    typedef typename std::vector<T>::const_iterator const_iterator;
+    using const_iterator = typename std::vector<T>::const_iterator;
+
     const_iterator begin() const { return Map.begin(); }
     const_iterator end() const { return Map.end(); }
 
@@ -72,12 +80,15 @@ namespace rdf {
     operator bool() const {
       return Reg != 0 && Mask.any();
     }
+
     bool operator== (const RegisterRef &RR) const {
       return Reg == RR.Reg && Mask == RR.Mask;
     }
+
     bool operator!= (const RegisterRef &RR) const {
       return !operator==(RR);
     }
+
     bool operator< (const RegisterRef &RR) const {
       return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask);
     }
@@ -91,12 +102,15 @@ namespace rdf {
     static bool isRegMaskId(RegisterId R) {
       return TargetRegisterInfo::isStackSlot(R);
     }
+
     RegisterId getRegMaskId(const uint32_t *RM) const {
       return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM));
     }
+
     const uint32_t *getRegMaskBits(RegisterId R) const {
       return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R));
     }
+
     RegisterRef normalize(RegisterRef RR) const;
 
     bool alias(RegisterRef RA, RegisterRef RB) const {
@@ -104,16 +118,18 @@ namespace rdf {
         return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB);
       return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB);
     }
+
     std::set<RegisterId> getAliasSet(RegisterId Reg) const;
 
     RegisterRef getRefForUnit(uint32_t U) const {
       return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
     }
+
     const BitVector &getMaskUnits(RegisterId MaskId) const {
       return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units;
     }
-    RegisterRef mapTo(RegisterRef RR, unsigned R) const;
 
+    RegisterRef mapTo(RegisterRef RR, unsigned R) const;
     const TargetRegisterInfo &getTRI() const { return TRI; }
 
   private:
@@ -139,7 +155,6 @@ namespace rdf {
     bool aliasMM(RegisterRef RM, RegisterRef RN) const;
   };
 
-
   struct RegisterAggr {
     RegisterAggr(const PhysicalRegisterInfo &pri)
         : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
@@ -148,6 +163,7 @@ namespace rdf {
     bool empty() const { return Units.none(); }
     bool hasAliasOf(RegisterRef RR) const;
     bool hasCoverOf(RegisterRef RR) const;
+
     static bool isCoverOf(RegisterRef RA, RegisterRef RB,
                           const PhysicalRegisterInfo &PRI) {
       return RegisterAggr(PRI).insert(RA).hasCoverOf(RB);
@@ -167,26 +183,33 @@ namespace rdf {
     void print(raw_ostream &OS) const;
 
     struct rr_iterator {
-      typedef std::map<RegisterId,LaneBitmask> MapType;
+      using MapType = std::map<RegisterId, LaneBitmask>;
+
     private:
       MapType Masks;
       MapType::iterator Pos;
       unsigned Index;
       const RegisterAggr *Owner;
+
     public:
       rr_iterator(const RegisterAggr &RG, bool End);
+
       RegisterRef operator*() const {
         return RegisterRef(Pos->first, Pos->second);
       }
+
       rr_iterator &operator++() {
         ++Pos;
         ++Index;
         return *this;
       }
+
       bool operator==(const rr_iterator &I) const {
         assert(Owner == I.Owner);
+        (void)Owner;
         return Index == I.Index;
       }
+
       bool operator!=(const rr_iterator &I) const {
         return !(*this == I);
       }
@@ -204,7 +227,6 @@ namespace rdf {
     const PhysicalRegisterInfo &PRI;
   };
 
-
   // Optionally print the lane mask, if it is not ~0.
   struct PrintLaneMaskOpt {
     PrintLaneMaskOpt(LaneBitmask M) : Mask(M) {}
@@ -212,8 +234,8 @@ namespace rdf {
   };
   raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P);
 
-} // namespace rdf
-} // namespace llvm
+} // end namespace rdf
 
-#endif
+} // end namespace llvm
 
+#endif // LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
diff --git a/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp b/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
index 0554646bb6be..a330f27ed300 100644
--- a/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
+++ b/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
@@ -18,6 +18,6 @@ Target &llvm::getTheHexagonTarget() {
 }
 
 extern "C" void LLVMInitializeHexagonTargetInfo() {
-  RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(getTheHexagonTarget(),
-                                                      "hexagon", "Hexagon");
+  RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(
+      getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");
 }