diff options
author | Dimitry Andric <dim@FreeBSD.org> | 2019-08-20 20:50:12 +0000 |
---|---|---|
committer | Dimitry Andric <dim@FreeBSD.org> | 2019-08-20 20:50:12 +0000 |
commit | e6d1592492a3a379186bfb02bd0f4eda0669c0d5 (patch) | |
tree | 599ab169a01f1c86eda9adc774edaedde2f2db5b /lib/Target/Hexagon | |
parent | 1a56a5ead7a2e84bee8240f5f6b033b5f1707154 (diff) |
Notes
Diffstat (limited to 'lib/Target/Hexagon')
146 files changed, 996 insertions, 911 deletions
diff --git a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 2eb1f0fc8bd9..0881bf841f90 100644 --- a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -1,15 +1,13 @@ //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #define DEBUG_TYPE "mcasmparser" -#include "Hexagon.h" #include "HexagonTargetStreamer.h" #include "MCTargetDesc/HexagonMCChecker.h" #include "MCTargetDesc/HexagonMCELFStreamer.h" @@ -17,6 +15,7 @@ #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "MCTargetDesc/HexagonShuffler.h" +#include "TargetInfo/HexagonTargetInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" @@ -1684,8 +1683,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, int64_t Value; MCExpr const &Expr = *Imm.getExpr(); bool Absolute = Expr.evaluateAsAbsolute(Value); - assert(Absolute); - (void)Absolute; + if (!Absolute) + return Match_InvalidOperand; if (!HexagonMCInstrInfo::mustExtend(Expr) && ((Value <= -256) || Value >= 256)) return Match_InvalidOperand; @@ -1707,8 +1706,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, MCInst TmpInst; int64_t Value; bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); - assert(Absolute); - (void)Absolute; + if (!Absolute) + return Match_InvalidOperand; if (Value == 0) { // convert to $Rd = $Rs TmpInst.setOpcode(Hexagon::A2_tfr); MCOperand &Rd = Inst.getOperand(0); @@ -1737,8 +1736,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, MCOperand &Imm = Inst.getOperand(2); int64_t Value; bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); - assert(Absolute); - (void)Absolute; + if (!Absolute) + return Match_InvalidOperand; if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1]) MCInst TmpInst; unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); @@ -1861,8 +1860,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, MCOperand &Imm = Inst.getOperand(2); int64_t Value; bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); - assert(Absolute); - (void)Absolute; + if (!Absolute) + return Match_InvalidOperand; if (Value == 0) Inst.setOpcode(Hexagon::S2_vsathub); else { @@ -1881,8 +1880,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, MCOperand &Imm = Inst.getOperand(2); int64_t Value; bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); - assert(Absolute); - (void)Absolute; + if (!Absolute) + return Match_InvalidOperand; if (Value == 0) { MCInst TmpInst; unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); diff --git a/lib/Target/Hexagon/BitTracker.cpp b/lib/Target/Hexagon/BitTracker.cpp index 69529b0d1162..b7e95caf24fb 100644 --- a/lib/Target/Hexagon/BitTracker.cpp +++ b/lib/Target/Hexagon/BitTracker.cpp @@ -1,9 +1,8 @@ //===- BitTracker.cpp -----------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/BitTracker.h b/lib/Target/Hexagon/BitTracker.h index 058225c0d812..efb21805b801 100644 --- a/lib/Target/Hexagon/BitTracker.h +++ b/lib/Target/Hexagon/BitTracker.h @@ -1,9 +1,8 @@ //===- BitTracker.h ---------------------------------------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 428b42eba30d..99e3ee871570 100644 --- a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -1,9 +1,8 @@ //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -13,6 +12,7 @@ #include "MCTargetDesc/HexagonMCChecker.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" +#include "TargetInfo/HexagonTargetInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/STLExtras.h" #include "llvm/MC/MCContext.h" @@ -149,7 +149,7 @@ static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, const void *Decoder); static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); -#include "HexagonDepDecoders.h" +#include "HexagonDepDecoders.inc" #include "HexagonGenDisassemblerTables.inc" static MCDisassembler *createHexagonDisassembler(const Target &T, diff --git a/lib/Target/Hexagon/Hexagon.h b/lib/Target/Hexagon/Hexagon.h index c18492da803b..58dadf012da5 100644 --- a/lib/Target/Hexagon/Hexagon.h +++ b/lib/Target/Hexagon/Hexagon.h @@ -1,9 +1,8 @@ //=-- Hexagon.h - Top-level interface for Hexagon representation --*- C++ -*-=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index 868353e18832..26869391c7a3 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -1,9 +1,8 @@ //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp index f44fb16e2d8e..b07d15609ede 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -1,9 +1,8 @@ //===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -22,6 +21,7 @@ #include "MCTargetDesc/HexagonMCExpr.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" +#include "TargetInfo/HexagonTargetInfo.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Twine.h" @@ -92,9 +92,7 @@ void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, GetCPISymbol(MO.getIndex())->print(O, MAI); return; case MachineOperand::MO_GlobalAddress: - // Computing the address of a global symbol, not calling it. - getSymbol(MO.getGlobal())->print(O, MAI); - printOffset(MO.getOffset(), O); + PrintSymbolOperand(MO, O); return; } } @@ -114,7 +112,6 @@ bool HexagonAsmPrinter::isBlockOnlyReachableByFallthrough( /// PrintAsmOperand - Print out an operand for an inline asm expression. bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS) { // Does this asm operand have a single letter operand modifier? @@ -125,11 +122,7 @@ bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, switch (ExtraCode[0]) { default: // See if this is a generic print operand - return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, OS); - case 'c': // Don't print "$" before a global var name or constant. - // Hexagon never has a prefix. - printOperand(MI, OpNo, OS); - return false; + return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS); case 'L': case 'H': { // The highest-numbered register of a pair. const MachineOperand &MO = MI->getOperand(OpNo); @@ -161,7 +154,6 @@ bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) { if (ExtraCode && ExtraCode[0]) diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.h b/lib/Target/Hexagon/HexagonAsmPrinter.h index d0629d173a65..6c4b664e83f5 100755 --- a/lib/Target/Hexagon/HexagonAsmPrinter.h +++ b/lib/Target/Hexagon/HexagonAsmPrinter.h @@ -1,9 +1,8 @@ //===- HexagonAsmPrinter.h - Print machine code to an Hexagon .s file -----===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -14,7 +13,6 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONASMPRINTER_H #define LLVM_LIB_TARGET_HEXAGON_HEXAGONASMPRINTER_H -#include "Hexagon.h" #include "HexagonSubtarget.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineFunction.h" @@ -53,11 +51,9 @@ class TargetMachine; void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode, - raw_ostream &OS) override; + const char *ExtraCode, raw_ostream &OS) override; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode, - raw_ostream &OS) override; + const char *ExtraCode, raw_ostream &OS) override; }; } // end namespace llvm diff --git a/lib/Target/Hexagon/HexagonBitSimplify.cpp b/lib/Target/Hexagon/HexagonBitSimplify.cpp index 1bdebe557a8c..7b75d251ccd3 100644 --- a/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1,9 +1,8 @@ //===- HexagonBitSimplify.cpp ---------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonBitTracker.cpp b/lib/Target/Hexagon/HexagonBitTracker.cpp index 92b6da871a4c..ba50faac2cf9 100644 --- a/lib/Target/Hexagon/HexagonBitTracker.cpp +++ b/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -1,9 +1,8 @@ //===- HexagonBitTracker.cpp ----------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonBitTracker.h b/lib/Target/Hexagon/HexagonBitTracker.h index f0b7c9d91950..02607d50f686 100644 --- a/lib/Target/Hexagon/HexagonBitTracker.h +++ b/lib/Target/Hexagon/HexagonBitTracker.h @@ -1,9 +1,8 @@ //===- HexagonBitTracker.h --------------------------------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonBlockRanges.cpp b/lib/Target/Hexagon/HexagonBlockRanges.cpp index 48a4505458ae..999150fc8c6e 100644 --- a/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ b/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -1,9 +1,8 @@ //===- HexagonBlockRanges.cpp ---------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonBlockRanges.h b/lib/Target/Hexagon/HexagonBlockRanges.h index 4da5a970a659..61115e29a708 100644 --- a/lib/Target/Hexagon/HexagonBlockRanges.h +++ b/lib/Target/Hexagon/HexagonBlockRanges.h @@ -1,9 +1,8 @@ //===- HexagonBlockRanges.h -------------------------------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonBranchRelaxation.cpp b/lib/Target/Hexagon/HexagonBranchRelaxation.cpp index 2fa7888dd02b..ee93739b2c7b 100644 --- a/lib/Target/Hexagon/HexagonBranchRelaxation.cpp +++ b/lib/Target/Hexagon/HexagonBranchRelaxation.cpp @@ -1,9 +1,8 @@ //===--- HexagonBranchRelaxation.cpp - Identify and relax long jumps ------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp index a22ac8c9fdf5..11a455ce4347 100644 --- a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp +++ b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp @@ -1,9 +1,8 @@ //===- HexagonCFGOptimizer.cpp - CFG optimizations ------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonCallingConv.td b/lib/Target/Hexagon/HexagonCallingConv.td index ed2f87570d6b..5c31a81a1e87 100644 --- a/lib/Target/Hexagon/HexagonCallingConv.td +++ b/lib/Target/Hexagon/HexagonCallingConv.td @@ -1,9 +1,8 @@ //===- HexagonCallingConv.td ----------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonCommonGEP.cpp b/lib/Target/Hexagon/HexagonCommonGEP.cpp index f315e24eba62..cf1b0a0f7daa 100644 --- a/lib/Target/Hexagon/HexagonCommonGEP.cpp +++ b/lib/Target/Hexagon/HexagonCommonGEP.cpp @@ -1,9 +1,8 @@ //===- HexagonCommonGEP.cpp -----------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -12,6 +11,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/GraphTraits.h" +#include "llvm/ADT/SetVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/Analysis/LoopInfo.h" @@ -71,7 +71,7 @@ namespace { using NodeToValueMap = std::map<GepNode *, Value *>; using NodeVect = std::vector<GepNode *>; using NodeChildrenMap = std::map<GepNode *, NodeVect>; - using UseSet = std::set<Use *>; + using UseSet = SetVector<Use *>; using NodeToUsesMap = std::map<GepNode *, UseSet>; // Numbering map for gep nodes. Used to keep track of ordering for @@ -980,15 +980,13 @@ void HexagonCommonGEP::separateChainForNode(GepNode *Node, Use *U, assert(UF != Uses.end()); UseSet &Us = UF->second; UseSet NewUs; - for (UseSet::iterator I = Us.begin(); I != Us.end(); ) { - User *S = (*I)->getUser(); - UseSet::iterator Nx = std::next(I); - if (S == R) { - NewUs.insert(*I); - Us.erase(I); - } - I = Nx; + for (Use *U : Us) { + if (U->getUser() == R) + NewUs.insert(U); } + for (Use *U : NewUs) + Us.remove(U); // erase takes an iterator. + if (Us.empty()) { Node->Flags &= ~GepNode::Used; Uses.erase(UF); diff --git a/lib/Target/Hexagon/HexagonConstExtenders.cpp b/lib/Target/Hexagon/HexagonConstExtenders.cpp index ba9f638796eb..cfed0ecef272 100644 --- a/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -1,9 +1,8 @@ //===- HexagonConstExtenders.cpp ------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonConstPropagation.cpp b/lib/Target/Hexagon/HexagonConstPropagation.cpp index fa192391313e..d1fde5da5fe8 100644 --- a/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -1,9 +1,8 @@ //===- HexagonConstPropagation.cpp ----------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -80,18 +79,21 @@ namespace { // A representation of a register as it can appear in a MachineOperand, // i.e. a pair register:subregister. - struct Register { + + // FIXME: Use TargetInstrInfo::RegSubRegPair. Also duplicated in + // HexagonGenPredicate + struct RegisterSubReg { unsigned Reg, SubReg; - explicit Register(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {} - explicit Register(const MachineOperand &MO) + explicit RegisterSubReg(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {} + explicit RegisterSubReg(const MachineOperand &MO) : Reg(MO.getReg()), SubReg(MO.getSubReg()) {} void print(const TargetRegisterInfo *TRI = nullptr) const { dbgs() << printReg(Reg, TRI, SubReg); } - bool operator== (const Register &R) const { + bool operator== (const RegisterSubReg &R) const { return (Reg == R.Reg) && (SubReg == R.SubReg); } }; @@ -301,7 +303,7 @@ namespace { using CellMap = MachineConstPropagator::CellMap; virtual bool evaluate(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) = 0; - virtual bool evaluate(const Register &R, const LatticeCell &SrcC, + virtual bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC, LatticeCell &Result) = 0; virtual bool evaluate(const MachineInstr &BrI, const CellMap &Inputs, SetVector<const MachineBasicBlock*> &Targets, @@ -344,17 +346,17 @@ namespace { // Helper functions. - bool getCell(const Register &R, const CellMap &Inputs, LatticeCell &RC); + bool getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC); bool constToInt(const Constant *C, APInt &Val) const; bool constToFloat(const Constant *C, APFloat &Val) const; const ConstantInt *intToConst(const APInt &Val) const; // Compares. - bool evaluateCMPrr(uint32_t Cmp, const Register &R1, const Register &R2, + bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, const CellMap &Inputs, bool &Result); - bool evaluateCMPri(uint32_t Cmp, const Register &R1, const APInt &A2, + bool evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, bool &Result); - bool evaluateCMPrp(uint32_t Cmp, const Register &R1, uint64_t Props2, + bool evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1, uint64_t Props2, const CellMap &Inputs, bool &Result); bool evaluateCMPii(uint32_t Cmp, const APInt &A1, const APInt &A2, bool &Result); @@ -363,52 +365,52 @@ namespace { bool evaluateCMPpp(uint32_t Cmp, uint32_t Props1, uint32_t Props2, bool &Result); - bool evaluateCOPY(const Register &R1, const CellMap &Inputs, + bool evaluateCOPY(const RegisterSubReg &R1, const CellMap &Inputs, LatticeCell &Result); // Logical operations. - bool evaluateANDrr(const Register &R1, const Register &R2, + bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result); - bool evaluateANDri(const Register &R1, const APInt &A2, + bool evaluateANDri(const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, LatticeCell &Result); bool evaluateANDii(const APInt &A1, const APInt &A2, APInt &Result); - bool evaluateORrr(const Register &R1, const Register &R2, + bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result); - bool evaluateORri(const Register &R1, const APInt &A2, + bool evaluateORri(const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, LatticeCell &Result); bool evaluateORii(const APInt &A1, const APInt &A2, APInt &Result); - bool evaluateXORrr(const Register &R1, const Register &R2, + bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result); - bool evaluateXORri(const Register &R1, const APInt &A2, + bool evaluateXORri(const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, LatticeCell &Result); bool evaluateXORii(const APInt &A1, const APInt &A2, APInt &Result); // Extensions. - bool evaluateZEXTr(const Register &R1, unsigned Width, unsigned Bits, + bool evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits, const CellMap &Inputs, LatticeCell &Result); bool evaluateZEXTi(const APInt &A1, unsigned Width, unsigned Bits, APInt &Result); - bool evaluateSEXTr(const Register &R1, unsigned Width, unsigned Bits, + bool evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits, const CellMap &Inputs, LatticeCell &Result); bool evaluateSEXTi(const APInt &A1, unsigned Width, unsigned Bits, APInt &Result); // Leading/trailing bits. - bool evaluateCLBr(const Register &R1, bool Zeros, bool Ones, + bool evaluateCLBr(const RegisterSubReg &R1, bool Zeros, bool Ones, const CellMap &Inputs, LatticeCell &Result); bool evaluateCLBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result); - bool evaluateCTBr(const Register &R1, bool Zeros, bool Ones, + bool evaluateCTBr(const RegisterSubReg &R1, bool Zeros, bool Ones, const CellMap &Inputs, LatticeCell &Result); bool evaluateCTBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result); // Bitfield extract. - bool evaluateEXTRACTr(const Register &R1, unsigned Width, unsigned Bits, + bool evaluateEXTRACTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits, unsigned Offset, bool Signed, const CellMap &Inputs, LatticeCell &Result); bool evaluateEXTRACTi(const APInt &A1, unsigned Bits, unsigned Offset, bool Signed, APInt &Result); // Vector operations. - bool evaluateSplatr(const Register &R1, unsigned Bits, unsigned Count, + bool evaluateSplatr(const RegisterSubReg &R1, unsigned Bits, unsigned Count, const CellMap &Inputs, LatticeCell &Result); bool evaluateSplati(const APInt &A1, unsigned Bits, unsigned Count, APInt &Result); @@ -620,7 +622,7 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) { LLVM_DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN); const MachineOperand &MD = PN.getOperand(0); - Register DefR(MD); + RegisterSubReg DefR(MD); assert(TargetRegisterInfo::isVirtualRegister(DefR.Reg)); bool Changed = false; @@ -647,7 +649,7 @@ Bottomize: continue; } const MachineOperand &SO = PN.getOperand(i); - Register UseR(SO); + RegisterSubReg UseR(SO); // If the input is not a virtual register, we don't really know what // value it holds. if (!TargetRegisterInfo::isVirtualRegister(UseR.Reg)) @@ -690,7 +692,7 @@ void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) { for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg() || !MO.isDef()) continue; - Register DefR(MO); + RegisterSubReg DefR(MO); // Only track virtual registers. if (!TargetRegisterInfo::isVirtualRegister(DefR.Reg)) continue; @@ -1066,7 +1068,7 @@ bool MachineConstPropagator::run(MachineFunction &MF) { // -------------------------------------------------------------------- // Machine const evaluator. -bool MachineConstEvaluator::getCell(const Register &R, const CellMap &Inputs, +bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC) { if (!TargetRegisterInfo::isVirtualRegister(R.Reg)) return false; @@ -1092,8 +1094,8 @@ const ConstantInt *MachineConstEvaluator::intToConst(const APInt &Val) const { return ConstantInt::get(CX, Val); } -bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const Register &R1, - const Register &R2, const CellMap &Inputs, bool &Result) { +bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, + const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) { assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); LatticeCell LS1, LS2; if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2)) @@ -1131,7 +1133,7 @@ bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const Register &R1, return IsTrue || IsFalse; } -bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const Register &R1, +bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, bool &Result) { assert(Inputs.has(R1.Reg)); LatticeCell LS; @@ -1158,7 +1160,7 @@ bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const Register &R1, return IsTrue || IsFalse; } -bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const Register &R1, +bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1, uint64_t Props2, const CellMap &Inputs, bool &Result) { assert(Inputs.has(R1.Reg)); LatticeCell LS; @@ -1351,13 +1353,13 @@ bool MachineConstEvaluator::evaluateCMPpp(uint32_t Cmp, uint32_t Props1, return false; } -bool MachineConstEvaluator::evaluateCOPY(const Register &R1, +bool MachineConstEvaluator::evaluateCOPY(const RegisterSubReg &R1, const CellMap &Inputs, LatticeCell &Result) { return getCell(R1, Inputs, Result); } -bool MachineConstEvaluator::evaluateANDrr(const Register &R1, - const Register &R2, const CellMap &Inputs, LatticeCell &Result) { +bool MachineConstEvaluator::evaluateANDrr(const RegisterSubReg &R1, + const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); const LatticeCell &L1 = Inputs.get(R2.Reg); const LatticeCell &L2 = Inputs.get(R2.Reg); @@ -1387,7 +1389,7 @@ bool MachineConstEvaluator::evaluateANDrr(const Register &R1, return !Result.isBottom(); } -bool MachineConstEvaluator::evaluateANDri(const Register &R1, +bool MachineConstEvaluator::evaluateANDri(const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg)); if (A2 == -1) @@ -1423,8 +1425,8 @@ bool MachineConstEvaluator::evaluateANDii(const APInt &A1, return true; } -bool MachineConstEvaluator::evaluateORrr(const Register &R1, - const Register &R2, const CellMap &Inputs, LatticeCell &Result) { +bool MachineConstEvaluator::evaluateORrr(const RegisterSubReg &R1, + const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); const LatticeCell &L1 = Inputs.get(R2.Reg); const LatticeCell &L2 = Inputs.get(R2.Reg); @@ -1454,7 +1456,7 @@ bool MachineConstEvaluator::evaluateORrr(const Register &R1, return !Result.isBottom(); } -bool MachineConstEvaluator::evaluateORri(const Register &R1, +bool MachineConstEvaluator::evaluateORri(const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg)); if (A2 == 0) @@ -1490,8 +1492,8 @@ bool MachineConstEvaluator::evaluateORii(const APInt &A1, return true; } -bool MachineConstEvaluator::evaluateXORrr(const Register &R1, - const Register &R2, const CellMap &Inputs, LatticeCell &Result) { +bool MachineConstEvaluator::evaluateXORrr(const RegisterSubReg &R1, + const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); LatticeCell LS1, LS2; if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2)) @@ -1519,7 +1521,7 @@ bool MachineConstEvaluator::evaluateXORrr(const Register &R1, return !Result.isBottom(); } -bool MachineConstEvaluator::evaluateXORri(const Register &R1, +bool MachineConstEvaluator::evaluateXORri(const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg)); LatticeCell LS1; @@ -1552,7 +1554,7 @@ bool MachineConstEvaluator::evaluateXORii(const APInt &A1, return true; } -bool MachineConstEvaluator::evaluateZEXTr(const Register &R1, unsigned Width, +bool MachineConstEvaluator::evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg)); LatticeCell LS1; @@ -1583,7 +1585,7 @@ bool MachineConstEvaluator::evaluateZEXTi(const APInt &A1, unsigned Width, return true; } -bool MachineConstEvaluator::evaluateSEXTr(const Register &R1, unsigned Width, +bool MachineConstEvaluator::evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg)); LatticeCell LS1; @@ -1648,7 +1650,7 @@ bool MachineConstEvaluator::evaluateSEXTi(const APInt &A1, unsigned Width, return true; } -bool MachineConstEvaluator::evaluateCLBr(const Register &R1, bool Zeros, +bool MachineConstEvaluator::evaluateCLBr(const RegisterSubReg &R1, bool Zeros, bool Ones, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg)); LatticeCell LS1; @@ -1683,7 +1685,7 @@ bool MachineConstEvaluator::evaluateCLBi(const APInt &A1, bool Zeros, return true; } -bool MachineConstEvaluator::evaluateCTBr(const Register &R1, bool Zeros, +bool MachineConstEvaluator::evaluateCTBr(const RegisterSubReg &R1, bool Zeros, bool Ones, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg)); LatticeCell LS1; @@ -1718,7 +1720,7 @@ bool MachineConstEvaluator::evaluateCTBi(const APInt &A1, bool Zeros, return true; } -bool MachineConstEvaluator::evaluateEXTRACTr(const Register &R1, +bool MachineConstEvaluator::evaluateEXTRACTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits, unsigned Offset, bool Signed, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg)); @@ -1776,7 +1778,7 @@ bool MachineConstEvaluator::evaluateEXTRACTi(const APInt &A1, unsigned Bits, return true; } -bool MachineConstEvaluator::evaluateSplatr(const Register &R1, +bool MachineConstEvaluator::evaluateSplatr(const RegisterSubReg &R1, unsigned Bits, unsigned Count, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(R1.Reg)); @@ -1833,7 +1835,7 @@ namespace { bool evaluate(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) override; - bool evaluate(const Register &R, const LatticeCell &SrcC, + bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC, LatticeCell &Result) override; bool evaluate(const MachineInstr &BrI, const CellMap &Inputs, SetVector<const MachineBasicBlock*> &Targets, bool &FallsThru) @@ -1848,7 +1850,7 @@ namespace { const MachineOperand &MO); void replaceWithNop(MachineInstr &MI); - bool evaluateHexRSEQ32(Register RL, Register RH, const CellMap &Inputs, + bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs, LatticeCell &Result); bool evaluateHexCompare(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs); @@ -1922,14 +1924,14 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI, return false; unsigned Opc = MI.getOpcode(); - Register DefR(MD); + RegisterSubReg DefR(MD); assert(!DefR.SubReg); if (!TargetRegisterInfo::isVirtualRegister(DefR.Reg)) return false; if (MI.isCopy()) { LatticeCell RC; - Register SrcR(MI.getOperand(1)); + RegisterSubReg SrcR(MI.getOperand(1)); bool Eval = evaluateCOPY(SrcR, Inputs, RC); if (!Eval) return false; @@ -1951,7 +1953,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI, const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3); const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1); LatticeCell RC; - Register SrcRL(OpLo), SrcRH(OpHi); + RegisterSubReg SrcRL(OpLo), SrcRH(OpHi); bool Eval = evaluateHexRSEQ32(SrcRL, SrcRH, Inputs, RC); if (!Eval) return false; @@ -2038,7 +2040,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI, int64_t B = MI.getOperand(2).getImm(); assert(B >=0 && B < 32); APInt A(32, (1ull << B), false); - Register R(MI.getOperand(1)); + RegisterSubReg R(MI.getOperand(1)); LatticeCell RC = Outputs.get(DefR.Reg); bool Eval = evaluateORri(R, A, Inputs, RC); if (!Eval) @@ -2078,7 +2080,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI, using namespace Hexagon; bool Ones = (Opc == S2_ct1) || (Opc == S2_ct1p); - Register R1(MI.getOperand(1)); + RegisterSubReg R1(MI.getOperand(1)); assert(Inputs.has(R1.Reg)); LatticeCell T; bool Eval = evaluateCTBr(R1, !Ones, Ones, Inputs, T); @@ -2110,7 +2112,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI, bool OnlyZeros = (Opc == S2_cl0) || (Opc == S2_cl0p); bool OnlyOnes = (Opc == S2_cl1) || (Opc == S2_cl1p); - Register R1(MI.getOperand(1)); + RegisterSubReg R1(MI.getOperand(1)); assert(Inputs.has(R1.Reg)); LatticeCell T; bool Eval = evaluateCLBr(R1, !OnlyOnes, !OnlyZeros, Inputs, T); @@ -2138,7 +2140,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI, { bool Signed = (Opc == Hexagon::S4_extract) || (Opc == Hexagon::S4_extractp); - Register R1(MI.getOperand(1)); + RegisterSubReg R1(MI.getOperand(1)); unsigned BW = getRegBitWidth(R1.Reg); unsigned Bits = MI.getOperand(2).getImm(); unsigned Offset = MI.getOperand(3).getImm(); @@ -2189,7 +2191,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI, return true; } -bool HexagonConstEvaluator::evaluate(const Register &R, +bool HexagonConstEvaluator::evaluate(const RegisterSubReg &R, const LatticeCell &Input, LatticeCell &Result) { if (!R.SubReg) { Result = Input; @@ -2280,7 +2282,7 @@ Undetermined: if (SimpleBranch) { const MachineOperand &MD = BrI.getOperand(0); - Register PR(MD); + RegisterSubReg PR(MD); // If the condition operand has a subregister, this is not something // we currently recognize. if (PR.SubReg) @@ -2502,7 +2504,7 @@ void HexagonConstEvaluator::replaceWithNop(MachineInstr &MI) { MI.RemoveOperand(0); } -bool HexagonConstEvaluator::evaluateHexRSEQ32(Register RL, Register RH, +bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs, LatticeCell &Result) { assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg)); LatticeCell LSL, LSH; @@ -2571,7 +2573,7 @@ bool HexagonConstEvaluator::evaluateHexCompare(const MachineInstr &MI, if (Computed) { // Only create a zero/non-zero cell. At this time there isn't really // much need for specific values. - Register DefR(MI.getOperand(0)); + RegisterSubReg DefR(MI.getOperand(0)); LatticeCell L = Outputs.get(DefR.Reg); uint32_t P = Result ? ConstantProperties::NonZero : ConstantProperties::Zero; @@ -2591,9 +2593,9 @@ bool HexagonConstEvaluator::evaluateHexCompare2(unsigned Opc, bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg(); bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); if (Reg1) { - Register R1(Src1); + RegisterSubReg R1(Src1); if (Reg2) { - Register R2(Src2); + RegisterSubReg R2(Src2); return evaluateCMPrr(Cmp, R1, R2, Inputs, Result); } else if (Imm2) { APInt A2 = getCmpImm(Opc, 2, Src2); @@ -2602,7 +2604,7 @@ bool HexagonConstEvaluator::evaluateHexCompare2(unsigned Opc, } else if (Imm1) { APInt A1 = getCmpImm(Opc, 1, Src1); if (Reg2) { - Register R2(Src2); + RegisterSubReg R2(Src2); uint32_t NegCmp = Comparison::negate(Cmp); return evaluateCMPri(NegCmp, R2, A1, Inputs, Result); } else if (Imm2) { @@ -2621,7 +2623,7 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI, return false; const MachineOperand &Src1 = MI.getOperand(1); const MachineOperand &Src2 = MI.getOperand(2); - Register R1(Src1); + RegisterSubReg R1(Src1); bool Eval = false; LatticeCell RC; switch (Opc) { @@ -2629,7 +2631,7 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI, return false; case Hexagon::A2_and: case Hexagon::A2_andp: - Eval = evaluateANDrr(R1, Register(Src2), Inputs, RC); + Eval = evaluateANDrr(R1, RegisterSubReg(Src2), Inputs, RC); break; case Hexagon::A2_andir: { if (!Src2.isImm()) @@ -2640,7 +2642,7 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI, } case Hexagon::A2_or: case Hexagon::A2_orp: - Eval = evaluateORrr(R1, Register(Src2), Inputs, RC); + Eval = evaluateORrr(R1, RegisterSubReg(Src2), Inputs, RC); break; case Hexagon::A2_orir: { if (!Src2.isImm()) @@ -2651,11 +2653,11 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI, } case Hexagon::A2_xor: case Hexagon::A2_xorp: - Eval = evaluateXORrr(R1, Register(Src2), Inputs, RC); + Eval = evaluateXORrr(R1, RegisterSubReg(Src2), Inputs, RC); break; } if (Eval) { - Register DefR(MI.getOperand(0)); + RegisterSubReg DefR(MI.getOperand(0)); Outputs.update(DefR.Reg, RC); } return Eval; @@ -2664,7 +2666,7 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI, bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) { // Dst0 = Cond1 ? Src2 : Src3 - Register CR(MI.getOperand(1)); + RegisterSubReg CR(MI.getOperand(1)); assert(Inputs.has(CR.Reg)); LatticeCell LS; if (!getCell(CR, Inputs, LS)) @@ -2679,7 +2681,7 @@ bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI, return false; const MachineOperand &ValOp = MI.getOperand(TakeOp); - Register DefR(MI.getOperand(0)); + RegisterSubReg DefR(MI.getOperand(0)); LatticeCell RC = Outputs.get(DefR.Reg); if (ValOp.isImm()) { @@ -2692,7 +2694,7 @@ bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI, return true; } if (ValOp.isReg()) { - Register R(ValOp); + RegisterSubReg R(ValOp); const LatticeCell &LR = Inputs.get(R.Reg); LatticeCell LSR; if (!evaluate(R, LR, LSR)) @@ -2707,7 +2709,7 @@ bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI, bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) { // Dst0 = ext R1 - Register R1(MI.getOperand(1)); + RegisterSubReg R1(MI.getOperand(1)); assert(Inputs.has(R1.Reg)); unsigned Opc = MI.getOpcode(); @@ -2724,6 +2726,8 @@ bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI, case Hexagon::A2_sxtw: Bits = 32; break; + default: + llvm_unreachable("Unhandled extension opcode"); } bool Signed = false; @@ -2735,7 +2739,7 @@ bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI, break; } - Register DefR(MI.getOperand(0)); + RegisterSubReg DefR(MI.getOperand(0)); unsigned BW = getRegBitWidth(DefR.Reg); LatticeCell RC = Outputs.get(DefR.Reg); bool Eval = Signed ? evaluateSEXTr(R1, BW, Bits, Inputs, RC) @@ -2749,8 +2753,8 @@ bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI, bool HexagonConstEvaluator::evaluateHexVector1(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) { // DefR = op R1 - Register DefR(MI.getOperand(0)); - Register R1(MI.getOperand(1)); + RegisterSubReg DefR(MI.getOperand(0)); + RegisterSubReg R1(MI.getOperand(1)); assert(Inputs.has(R1.Reg)); LatticeCell RC = Outputs.get(DefR.Reg); bool Eval; @@ -2788,7 +2792,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI, for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg() || !MO.isUse() || MO.isImplicit()) continue; - Register R(MO); + RegisterSubReg R(MO); if (!TargetRegisterInfo::isVirtualRegister(R.Reg)) continue; HasUse = true; @@ -2954,10 +2958,10 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI, // to DefR += mpyi(R, #imm), // or DefR -= mpyi(R, #imm). { - Register DefR(MI.getOperand(0)); + RegisterSubReg DefR(MI.getOperand(0)); assert(!DefR.SubReg); - Register R2(MI.getOperand(2)); - Register R3(MI.getOperand(3)); + RegisterSubReg R2(MI.getOperand(2)); + RegisterSubReg R3(MI.getOperand(3)); assert(Inputs.has(R2.Reg) && Inputs.has(R3.Reg)); LatticeCell LS2, LS3; // It is enough to get one of the input cells, since we will only try @@ -2971,7 +2975,7 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI, if (Zero) { // DefR == R1 (tied operands). MachineOperand &Acc = MI.getOperand(1); - Register R1(Acc); + RegisterSubReg R1(Acc); unsigned NewR = R1.Reg; if (R1.SubReg) { // Generate COPY. FIXME: Replace with the register:subregister. @@ -3018,8 +3022,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI, case Hexagon::A2_and: { - Register R1(MI.getOperand(1)); - Register R2(MI.getOperand(2)); + RegisterSubReg R1(MI.getOperand(1)); + RegisterSubReg R2(MI.getOperand(2)); assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); LatticeCell LS1, LS2; unsigned CopyOf = 0; @@ -3037,8 +3041,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI, if (!CopyOf) return false; MachineOperand &SO = MI.getOperand(CopyOf); - Register SR(SO); - Register DefR(MI.getOperand(0)); + RegisterSubReg SR(SO); + RegisterSubReg DefR(MI.getOperand(0)); unsigned NewR = SR.Reg; if (SR.SubReg) { const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); @@ -3054,8 +3058,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI, case Hexagon::A2_or: { - Register R1(MI.getOperand(1)); - Register R2(MI.getOperand(2)); + RegisterSubReg R1(MI.getOperand(1)); + RegisterSubReg R2(MI.getOperand(2)); assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); LatticeCell LS1, LS2; unsigned CopyOf = 0; @@ -3069,8 +3073,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI, if (!CopyOf) return false; MachineOperand &SO = MI.getOperand(CopyOf); - Register SR(SO); - Register DefR(MI.getOperand(0)); + RegisterSubReg SR(SO); + RegisterSubReg DefR(MI.getOperand(0)); unsigned NewR = SR.Reg; if (SR.SubReg) { const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); diff --git a/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 28965b69e284..a09ccab483cf 100644 --- a/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -1,9 +1,8 @@ //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // This pass replaces transfer instructions by combine instructions. @@ -255,8 +254,8 @@ static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg, MI.isMetaInstruction(); } -static unsigned UseReg(const MachineOperand& MO) { - return MO.isReg() ? MO.getReg() : 0; +static Register UseReg(const MachineOperand& MO) { + return MO.isReg() ? MO.getReg() : Register(); } /// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such diff --git a/lib/Target/Hexagon/HexagonDepArch.h b/lib/Target/Hexagon/HexagonDepArch.h index dff2b2f471d0..529be7ef0ac7 100644 --- a/lib/Target/Hexagon/HexagonDepArch.h +++ b/lib/Target/Hexagon/HexagonDepArch.h @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepArch.td b/lib/Target/Hexagon/HexagonDepArch.td index f1aadae555c8..115cf2383a7a 100644 --- a/lib/Target/Hexagon/HexagonDepArch.td +++ b/lib/Target/Hexagon/HexagonDepArch.td @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepDecoders.h b/lib/Target/Hexagon/HexagonDepDecoders.inc index 9f78412f45d2..10068abce7ec 100644 --- a/lib/Target/Hexagon/HexagonDepDecoders.h +++ b/lib/Target/Hexagon/HexagonDepDecoders.inc @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepIICHVX.td b/lib/Target/Hexagon/HexagonDepIICHVX.td index 9e3dea9f3e9b..fefbbfd3f1ac 100644 --- a/lib/Target/Hexagon/HexagonDepIICHVX.td +++ b/lib/Target/Hexagon/HexagonDepIICHVX.td @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepIICScalar.td b/lib/Target/Hexagon/HexagonDepIICScalar.td index 9da25952fb1c..34da0be02d19 100644 --- a/lib/Target/Hexagon/HexagonDepIICScalar.td +++ b/lib/Target/Hexagon/HexagonDepIICScalar.td @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepITypes.h b/lib/Target/Hexagon/HexagonDepITypes.h index 81e3971e21d2..358345e027d8 100644 --- a/lib/Target/Hexagon/HexagonDepITypes.h +++ b/lib/Target/Hexagon/HexagonDepITypes.h @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepITypes.td b/lib/Target/Hexagon/HexagonDepITypes.td index f694062a5232..91c02b84b87c 100644 --- a/lib/Target/Hexagon/HexagonDepITypes.td +++ b/lib/Target/Hexagon/HexagonDepITypes.td @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepInstrFormats.td b/lib/Target/Hexagon/HexagonDepInstrFormats.td index ffe212ef9d97..c08d9a388d3e 100644 --- a/lib/Target/Hexagon/HexagonDepInstrFormats.td +++ b/lib/Target/Hexagon/HexagonDepInstrFormats.td @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepInstrInfo.td b/lib/Target/Hexagon/HexagonDepInstrInfo.td index 3ef1c49eb7ee..a49051888c77 100644 --- a/lib/Target/Hexagon/HexagonDepInstrInfo.td +++ b/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td b/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td index 2346fa572626..2ce1419e4790 100644 --- a/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td +++ b/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepMappings.td b/lib/Target/Hexagon/HexagonDepMappings.td index b3132d41b903..22ee495b25e6 100644 --- a/lib/Target/Hexagon/HexagonDepMappings.td +++ b/lib/Target/Hexagon/HexagonDepMappings.td @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepOperands.td b/lib/Target/Hexagon/HexagonDepOperands.td index ef2d4fa45702..fdba7b971258 100644 --- a/lib/Target/Hexagon/HexagonDepOperands.td +++ b/lib/Target/Hexagon/HexagonDepOperands.td @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonDepTimingClasses.h b/lib/Target/Hexagon/HexagonDepTimingClasses.h index 0fd55e8b7997..b6be74f848bb 100644 --- a/lib/Target/Hexagon/HexagonDepTimingClasses.h +++ b/lib/Target/Hexagon/HexagonDepTimingClasses.h @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Automatically generated file, please consult code owner before editing. diff --git a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index 8e2f5093038e..c1f32e54e98d 100644 --- a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -1,9 +1,8 @@ //===- HexagonEarlyIfConv.cpp ---------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/lib/Target/Hexagon/HexagonExpandCondsets.cpp index 1a762c0c9de7..c343e426ac7d 100644 --- a/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -1,9 +1,8 @@ //===- HexagonExpandCondsets.cpp ------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -734,7 +733,7 @@ bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { HasDef = true; } for (auto &Mo : MI->memoperands()) - if (Mo->isVolatile()) + if (Mo->isVolatile() || Mo->isAtomic()) return false; return true; } diff --git a/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/lib/Target/Hexagon/HexagonFixupHwLoops.cpp index e9067e2285a8..f7edc168de4a 100644 --- a/lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ b/lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -1,9 +1,8 @@ //===---- HexagonFixupHwLoops.cpp - Fixup HW loops too far from LOOPn. ----===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // // The loop start address in the LOOPn instruction is encoded as a distance // from the LOOPn instruction itself. If the start address is too far from diff --git a/lib/Target/Hexagon/HexagonFrameLowering.cpp b/lib/Target/Hexagon/HexagonFrameLowering.cpp index f5736546a87c..3368ee4fb3b9 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1,9 +1,8 @@ //===- HexagonFrameLowering.cpp - Define frame lowering -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // // //===----------------------------------------------------------------------===// @@ -375,17 +374,17 @@ static bool isRestoreCall(unsigned Opc) { } static inline bool isOptNone(const MachineFunction &MF) { - return MF.getFunction().hasFnAttribute(Attribute::OptimizeNone) || + return MF.getFunction().hasOptNone() || MF.getTarget().getOptLevel() == CodeGenOpt::None; } static inline bool isOptSize(const MachineFunction &MF) { const Function &F = MF.getFunction(); - return F.optForSize() && !F.optForMinSize(); + return F.hasOptSize() && !F.hasMinSize(); } static inline bool isMinSize(const MachineFunction &MF) { - return MF.getFunction().optForMinSize(); + return MF.getFunction().hasMinSize(); } /// Implements shrink-wrapping of the stack frame. By default, stack frame @@ -2102,7 +2101,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, } if (!Bad) { for (auto *Mo : In.memoperands()) { - if (!Mo->isVolatile()) + if (!Mo->isVolatile() && !Mo->isAtomic()) continue; Bad = true; break; diff --git a/lib/Target/Hexagon/HexagonFrameLowering.h b/lib/Target/Hexagon/HexagonFrameLowering.h index d65d870750f8..65e8c7686640 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.h +++ b/lib/Target/Hexagon/HexagonFrameLowering.h @@ -1,9 +1,8 @@ //==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonGenExtract.cpp b/lib/Target/Hexagon/HexagonGenExtract.cpp index 08a016b74650..3417c74e359b 100644 --- a/lib/Target/Hexagon/HexagonGenExtract.cpp +++ b/lib/Target/Hexagon/HexagonGenExtract.cpp @@ -1,9 +1,8 @@ //===- HexagonGenExtract.cpp ----------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -211,7 +210,7 @@ bool HexagonGenExtract::convert(Instruction *In) { Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu : Intrinsic::hexagon_S2_extractup; Module *Mod = BB->getParent()->getParent(); - Value *ExtF = Intrinsic::getDeclaration(Mod, IntId); + Function *ExtF = Intrinsic::getDeclaration(Mod, IntId); Value *NewIn = IRB.CreateCall(ExtF, {BF, IRB.getInt32(W), IRB.getInt32(SR)}); if (SL != 0) NewIn = IRB.CreateShl(NewIn, SL, CSL->getName()); diff --git a/lib/Target/Hexagon/HexagonGenInsert.cpp b/lib/Target/Hexagon/HexagonGenInsert.cpp index e3492e7374e9..81025c1c5325 100644 --- a/lib/Target/Hexagon/HexagonGenInsert.cpp +++ b/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -1,9 +1,8 @@ //===- HexagonGenInsert.cpp -----------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -437,7 +436,7 @@ namespace { } // end anonymous namespace void OrderedRegisterList::insert(unsigned VR) { - iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord); + iterator L = llvm::lower_bound(Seq, VR, Ord); if (L == Seq.end()) Seq.push_back(VR); else @@ -450,7 +449,7 @@ void OrderedRegisterList::insert(unsigned VR) { } void OrderedRegisterList::remove(unsigned VR) { - iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord); + iterator L = llvm::lower_bound(Seq, VR, Ord); if (L != Seq.end()) Seq.erase(L); } diff --git a/lib/Target/Hexagon/HexagonGenMux.cpp b/lib/Target/Hexagon/HexagonGenMux.cpp index e5af96468af1..cdafbc20ab86 100644 --- a/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/lib/Target/Hexagon/HexagonGenMux.cpp @@ -1,9 +1,8 @@ //===- HexagonGenMux.cpp --------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -304,8 +303,8 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) { std::advance(It2, MaxX); MachineInstr &Def1 = *It1, &Def2 = *It2; MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); - unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0; - unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0; + Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); + Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); bool Failure = false, CanUp = true, CanDown = true; for (unsigned X = MinX+1; X < MaxX; X++) { const DefUseInfo &DU = DUM.lookup(X); diff --git a/lib/Target/Hexagon/HexagonGenPredicate.cpp b/lib/Target/Hexagon/HexagonGenPredicate.cpp index c0d2de90467a..e991fa8b61c8 100644 --- a/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ b/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -1,9 +1,8 @@ //===- HexagonGenPredicate.cpp --------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -46,17 +45,19 @@ namespace llvm { namespace { - struct Register { + // FIXME: Use TargetInstrInfo::RegSubRegPair + struct RegisterSubReg { unsigned R, S; - Register(unsigned r = 0, unsigned s = 0) : R(r), S(s) {} - Register(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {} + RegisterSubReg(unsigned r = 0, unsigned s = 0) : R(r), S(s) {} + RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {} + RegisterSubReg(const Register &Reg) : R(Reg), S(0) {} - bool operator== (const Register &Reg) const { + bool operator== (const RegisterSubReg &Reg) const { return R == Reg.R && S == Reg.S; } - bool operator< (const Register &Reg) const { + bool operator< (const RegisterSubReg &Reg) const { return R < Reg.R || (R == Reg.R && S < Reg.S); } }; @@ -64,10 +65,10 @@ namespace { struct PrintRegister { friend raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR); - PrintRegister(Register R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {} + PrintRegister(RegisterSubReg R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {} private: - Register Reg; + RegisterSubReg Reg; const TargetRegisterInfo &TRI; }; @@ -99,8 +100,8 @@ namespace { private: using VectOfInst = SetVector<MachineInstr *>; - using SetOfReg = std::set<Register>; - using RegToRegMap = std::map<Register, Register>; + using SetOfReg = std::set<RegisterSubReg>; + using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; const HexagonInstrInfo *TII = nullptr; const HexagonRegisterInfo *TRI = nullptr; @@ -111,12 +112,12 @@ namespace { bool isPredReg(unsigned R); void collectPredicateGPR(MachineFunction &MF); - void processPredicateGPR(const Register &Reg); + void processPredicateGPR(const RegisterSubReg &Reg); unsigned getPredForm(unsigned Opc); bool isConvertibleToPredForm(const MachineInstr *MI); bool isScalarCmp(unsigned Opc); - bool isScalarPred(Register PredReg); - Register getPredRegFor(const Register &Reg); + bool isScalarPred(RegisterSubReg PredReg); + RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); bool convertToPredForm(MachineInstr *MI); bool eliminatePredCopies(MachineFunction &MF); }; @@ -211,7 +212,7 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) { case Hexagon::C2_tfrpr: case TargetOpcode::COPY: if (isPredReg(MI->getOperand(1).getReg())) { - Register RD = MI->getOperand(0); + RegisterSubReg RD = MI->getOperand(0); if (TargetRegisterInfo::isVirtualRegister(RD.R)) PredGPRs.insert(RD); } @@ -221,7 +222,7 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) { } } -void HexagonGenPredicate::processPredicateGPR(const Register &Reg) { +void HexagonGenPredicate::processPredicateGPR(const RegisterSubReg &Reg) { LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n"); using use_iterator = MachineRegisterInfo::use_iterator; @@ -240,7 +241,7 @@ void HexagonGenPredicate::processPredicateGPR(const Register &Reg) { } } -Register HexagonGenPredicate::getPredRegFor(const Register &Reg) { +RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { // Create a predicate register for a given Reg. The newly created register // will have its value copied from Reg, so that it can be later used as // an operand in other instructions. @@ -255,7 +256,7 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) { unsigned Opc = DefI->getOpcode(); if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) { assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); - Register PR = DefI->getOperand(1); + RegisterSubReg PR = DefI->getOperand(1); G2P.insert(std::make_pair(Reg, PR)); LLVM_DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n'); return PR; @@ -272,10 +273,10 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) { MachineBasicBlock::iterator DefIt = DefI; BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR) .addReg(Reg.R, 0, Reg.S); - G2P.insert(std::make_pair(Reg, Register(NewPR))); - LLVM_DEBUG(dbgs() << " -> !" << PrintRegister(Register(NewPR), *TRI) + G2P.insert(std::make_pair(Reg, RegisterSubReg(NewPR))); + LLVM_DEBUG(dbgs() << " -> !" << PrintRegister(RegisterSubReg(NewPR), *TRI) << '\n'); - return Register(NewPR); + return RegisterSubReg(NewPR); } llvm_unreachable("Invalid argument"); @@ -317,12 +318,12 @@ bool HexagonGenPredicate::isScalarCmp(unsigned Opc) { return false; } -bool HexagonGenPredicate::isScalarPred(Register PredReg) { - std::queue<Register> WorkQ; +bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) { + std::queue<RegisterSubReg> WorkQ; WorkQ.push(PredReg); while (!WorkQ.empty()) { - Register PR = WorkQ.front(); + RegisterSubReg PR = WorkQ.front(); WorkQ.pop(); const MachineInstr *DefI = MRI->getVRegDef(PR.R); if (!DefI) @@ -351,7 +352,7 @@ bool HexagonGenPredicate::isScalarPred(Register PredReg) { // Add operands to the queue. for (const MachineOperand &MO : DefI->operands()) if (MO.isReg() && MO.isUse()) - WorkQ.push(Register(MO.getReg())); + WorkQ.push(RegisterSubReg(MO.getReg())); break; // All non-vector compares are ok, everything else is bad. @@ -373,7 +374,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { MachineOperand &MO = MI->getOperand(i); if (!MO.isReg() || !MO.isUse()) continue; - Register Reg(MO); + RegisterSubReg Reg(MO); if (Reg.S && Reg.S != Hexagon::isub_lo) return false; if (!PredGPRs.count(Reg)) @@ -400,7 +401,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { // If it's a scalar predicate register, then all bits in it are // the same. Otherwise, to determine whether all bits are 0 or not // we would need to use any8. - Register PR = getPredRegFor(MI->getOperand(1)); + RegisterSubReg PR = getPredRegFor(MI->getOperand(1)); if (!isScalarPred(PR)) return false; // This will skip the immediate argument when creating the predicate @@ -411,19 +412,19 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { // Some sanity: check that def is in operand #0. MachineOperand &Op0 = MI->getOperand(0); assert(Op0.isDef()); - Register OutR(Op0); + RegisterSubReg OutR(Op0); // Don't use getPredRegFor, since it will create an association between // the argument and a created predicate register (i.e. it will insert a // copy if a new predicate register is created). const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass; - Register NewPR = MRI->createVirtualRegister(PredRC); + RegisterSubReg NewPR = MRI->createVirtualRegister(PredRC); MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R); // Add predicate counterparts of the GPRs. for (unsigned i = 1; i < NumOps; ++i) { - Register GPR = MI->getOperand(i); - Register Pred = getPredRegFor(GPR); + RegisterSubReg GPR = MI->getOperand(i); + RegisterSubReg Pred = getPredRegFor(GPR); MIB.addReg(Pred.R, 0, Pred.S); } LLVM_DEBUG(dbgs() << "generated: " << *MIB); @@ -441,7 +442,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { // then the output will be a predicate register. Do not visit the // users of it. if (!isPredReg(NewOutR)) { - Register R(NewOutR); + RegisterSubReg R(NewOutR); PredGPRs.insert(R); processPredicateGPR(R); } @@ -468,8 +469,8 @@ bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) { for (MachineInstr &MI : MBB) { if (MI.getOpcode() != TargetOpcode::COPY) continue; - Register DR = MI.getOperand(0); - Register SR = MI.getOperand(1); + RegisterSubReg DR = MI.getOperand(0); + RegisterSubReg SR = MI.getOperand(1); if (!TargetRegisterInfo::isVirtualRegister(DR.R)) continue; if (!TargetRegisterInfo::isVirtualRegister(SR.R)) diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 239cf49ca8a2..cecbaedb6d70 100644 --- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -1,9 +1,8 @@ //===- HexagonHardwareLoops.cpp - Identify and generate hardware loops ----===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonHazardRecognizer.cpp b/lib/Target/Hexagon/HexagonHazardRecognizer.cpp index 44f1f554c662..e45126bec6ef 100644 --- a/lib/Target/Hexagon/HexagonHazardRecognizer.cpp +++ b/lib/Target/Hexagon/HexagonHazardRecognizer.cpp @@ -1,9 +1,8 @@ //===-- HexagonHazardRecognizer.cpp - Hexagon Post RA Hazard Recognizer ---===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonHazardRecognizer.h b/lib/Target/Hexagon/HexagonHazardRecognizer.h index 2874d73ce819..53b9cb43b4b6 100644 --- a/lib/Target/Hexagon/HexagonHazardRecognizer.h +++ b/lib/Target/Hexagon/HexagonHazardRecognizer.h @@ -1,9 +1,8 @@ //===--- HexagonHazardRecognizer.h - Hexagon Post RA Hazard Recognizer ----===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // This file defines the hazard recognizer for scheduling on Hexagon. diff --git a/lib/Target/Hexagon/HexagonIICHVX.td b/lib/Target/Hexagon/HexagonIICHVX.td index a804c5a80d03..06e9c83cf306 100644 --- a/lib/Target/Hexagon/HexagonIICHVX.td +++ b/lib/Target/Hexagon/HexagonIICHVX.td @@ -1,9 +1,8 @@ //===--- HexagonIICHVX.td -------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -17,12 +16,14 @@ class HVXItin { InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>, - // Used by Gather Pseudo Instructions which are expanded into - // V6_vgather* and V6_vS32b_new_ai. Even though these instructions - // use CVI_ST resource, it's not included below to avoid having more than - // 4 InstrStages and thus changing 'MaxResTerms' to 5. + // Used by gather pseudo-instructions which are expanded into V6_vgather* + // and V6_vS32b_new_ai. Even though these instructions use CVI_LD resource, + // it's not included below to avoid having more than 4 InstrStages and + // thus changing 'MaxResTerms' to 5. Instead, both SLOT0 and SLOT1 are + // used, which should be sufficient. InstrItinData <CVI_GATHER_PSEUDO, [InstrStage<1, [SLOT0], 0>, - InstrStage<1, [CVI_LD], 0>, InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, InstrStage<1, [CVI_MPY01, CVI_XLSHF]>]>]; } diff --git a/lib/Target/Hexagon/HexagonIICScalar.td b/lib/Target/Hexagon/HexagonIICScalar.td index 5fe713346e38..d37cc3a2cc3e 100644 --- a/lib/Target/Hexagon/HexagonIICScalar.td +++ b/lib/Target/Hexagon/HexagonIICScalar.td @@ -1,9 +1,8 @@ //===--- HexagonIICScalar.td ----------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 470b05bda4c6..605fcfc25559 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1,9 +1,8 @@ //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -849,6 +848,9 @@ void HexagonDAGToDAGISel::SelectD2P(SDNode *N) { void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) { const SDLoc &dl(N); MVT ResTy = N->getValueType(0).getSimpleVT(); + // The argument to V2Q should be a single vector. + MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy; + assert(HST->getVectorLength() * 8 == OpTy.getSizeInBits()); SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32); SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C); @@ -860,6 +862,8 @@ void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) { void HexagonDAGToDAGISel::SelectQ2V(SDNode *N) { const SDLoc &dl(N); MVT ResTy = N->getValueType(0).getSimpleVT(); + // The result of V2Q should be a single vector. + assert(HST->getVectorLength() * 8 == ResTy.getSizeInBits()); SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32); SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C); diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/lib/Target/Hexagon/HexagonISelDAGToDAG.h index f4f09dd4e758..65edb09603b3 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -1,9 +1,8 @@ //===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Hexagon specific code to select Hexagon machine instructions for diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp index b796e442d4fa..e7f1c345af1d 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -1,9 +1,8 @@ //===-- HexagonISelDAGToDAGHVX.cpp ----------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index 1edf3e498dfa..fef5a98cdb00 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1,9 +1,8 @@ //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -579,7 +578,8 @@ HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const { const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); unsigned LR = HRI.getRARegister(); - if (Op.getOpcode() != ISD::INLINEASM || HMFI.hasClobberLR()) + if ((Op.getOpcode() != ISD::INLINEASM && + Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR()) return Op; unsigned NumOps = Op.getNumOperands(); @@ -1292,6 +1292,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::INLINEASM, MVT::Other, Custom); + setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom); setOperationAction(ISD::PREFETCH, MVT::Other, Custom); setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); @@ -1324,7 +1325,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, if (EmitJumpTables) setMinimumJumpTableEntries(MinimumJumpTables); else - setMinimumJumpTableEntries(std::numeric_limits<int>::max()); + setMinimumJumpTableEntries(std::numeric_limits<unsigned>::max()); setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::ABS, MVT::i32, Legal); @@ -1333,8 +1334,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit, // but they only operate on i64. for (MVT VT : MVT::integer_valuetypes()) { - setOperationAction(ISD::UADDO, VT, Expand); - setOperationAction(ISD::USUBO, VT, Expand); + setOperationAction(ISD::UADDO, VT, Custom); + setOperationAction(ISD::USUBO, VT, Custom); setOperationAction(ISD::SADDO, VT, Expand); setOperationAction(ISD::SSUBO, VT, Expand); setOperationAction(ISD::ADDCARRY, VT, Expand); @@ -2619,7 +2620,6 @@ HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const SDLoc &dl(Op); const DataLayout &DL = DAG.getDataLayout(); LLVMContext &Ctx = *DAG.getContext(); - unsigned AS = LN->getAddressSpace(); // If the load aligning is disabled or the load can be broken up into two // smaller legal loads, do the default (target-independent) expansion. @@ -2629,15 +2629,15 @@ HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) DoDefault = true; if (!AlignLoads) { - if (allowsMemoryAccess(Ctx, DL, LN->getMemoryVT(), AS, HaveAlign)) + if (allowsMemoryAccess(Ctx, DL, LN->getMemoryVT(), *LN->getMemOperand())) return Op; DoDefault = true; } - if (!DoDefault && 2*HaveAlign == NeedAlign) { + if (!DoDefault && (2 * HaveAlign) == NeedAlign) { // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)". - MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8*HaveAlign) + MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign) : MVT::getVectorVT(MVT::i8, HaveAlign); - DoDefault = allowsMemoryAccess(Ctx, DL, PartTy, AS, HaveAlign); + DoDefault = allowsMemoryAccess(Ctx, DL, PartTy, *LN->getMemOperand()); } if (DoDefault) { std::pair<SDValue, SDValue> P = expandUnalignedLoad(LN, DAG); @@ -2692,6 +2692,43 @@ HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) } SDValue +HexagonTargetLowering::LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const { + SDValue X = Op.getOperand(0), Y = Op.getOperand(1); + auto *CY = dyn_cast<ConstantSDNode>(Y); + if (!CY) + return SDValue(); + + const SDLoc &dl(Op); + SDVTList VTs = Op.getNode()->getVTList(); + assert(VTs.NumVTs == 2); + assert(VTs.VTs[1] == MVT::i1); + unsigned Opc = Op.getOpcode(); + + if (CY) { + uint32_t VY = CY->getZExtValue(); + assert(VY != 0 && "This should have been folded"); + // X +/- 1 + if (VY != 1) + return SDValue(); + + if (Opc == ISD::UADDO) { + SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y}); + SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, getZero(dl, ty(Op), DAG), + ISD::SETEQ); + return DAG.getMergeValues({Op, Ov}, dl); + } + if (Opc == ISD::USUBO) { + SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y}); + SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, + DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ); + return DAG.getMergeValues({Op, Ov}, dl); + } + } + + return SDValue(); +} + +SDValue HexagonTargetLowering::LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const { const SDLoc &dl(Op); unsigned Opc = Op.getOpcode(); @@ -2741,7 +2778,7 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { unsigned Opc = Op.getOpcode(); // Handle INLINEASM first. - if (Opc == ISD::INLINEASM) + if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR) return LowerINLINEASM(Op, DAG); if (isHvxOperation(Op)) { @@ -2768,6 +2805,8 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::BITCAST: return LowerBITCAST(Op, DAG); case ISD::LOAD: return LowerLoad(Op, DAG); case ISD::STORE: return LowerStore(Op, DAG); + case ISD::UADDO: + case ISD::USUBO: return LowerUAddSubO(Op, DAG); case ISD::ADDCARRY: case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG); case ISD::SRA: @@ -2923,7 +2962,8 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( /// isFPImmLegal - Returns true if the target can instruction select the /// specified FP immediate natively. If false, the legalizer will /// materialize the FP immediate as a load from a constant pool. -bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { +bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, + bool ForCodeSize) const { return true; } @@ -3047,7 +3087,7 @@ bool HexagonTargetLowering::IsEligibleForTailCallOptimization( /// determined using generic target-independent logic. EVT HexagonTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, - bool MemcpyStrSrc, MachineFunction &MF) const { + bool MemcpyStrSrc, const AttributeList &FuncAttributes) const { auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool { return (GivenA % MinA) == 0; @@ -3063,8 +3103,9 @@ EVT HexagonTargetLowering::getOptimalMemOpType(uint64_t Size, return MVT::Other; } -bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, - unsigned AS, unsigned Align, bool *Fast) const { +bool HexagonTargetLowering::allowsMisalignedMemoryAccesses( + EVT VT, unsigned AS, unsigned Align, MachineMemOperand::Flags Flags, + bool *Fast) const { if (Fast) *Fast = false; return Subtarget.isHVXVectorType(VT.getSimpleVT()); @@ -3111,13 +3152,21 @@ Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const { BasicBlock *BB = Builder.GetInsertBlock(); Module *M = BB->getParent()->getParent(); - Type *Ty = cast<PointerType>(Addr->getType())->getElementType(); + auto PT = cast<PointerType>(Addr->getType()); + Type *Ty = PT->getElementType(); unsigned SZ = Ty->getPrimitiveSizeInBits(); assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported"); Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked : Intrinsic::hexagon_L4_loadd_locked; - Value *Fn = Intrinsic::getDeclaration(M, IntID); - return Builder.CreateCall(Fn, Addr, "larx"); + Function *Fn = Intrinsic::getDeclaration(M, IntID); + + PointerType *NewPtrTy + = Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace()); + Addr = Builder.CreateBitCast(Addr, NewPtrTy); + + Value *Call = Builder.CreateCall(Fn, Addr, "larx"); + + return Builder.CreateBitCast(Call, Ty); } /// Perform a store-conditional operation to Addr. Return the status of the @@ -3128,10 +3177,17 @@ Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Module *M = BB->getParent()->getParent(); Type *Ty = Val->getType(); unsigned SZ = Ty->getPrimitiveSizeInBits(); + + Type *CastTy = Builder.getIntNTy(SZ); assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported"); Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked : Intrinsic::hexagon_S4_stored_locked; - Value *Fn = Intrinsic::getDeclaration(M, IntID); + Function *Fn = Intrinsic::getDeclaration(M, IntID); + + unsigned AS = Addr->getType()->getPointerAddressSpace(); + Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS)); + Val = Builder.CreateBitCast(Val, CastTy); + Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx"); Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), ""); Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext())); diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index 265c37e6ae61..4e467cb22727 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -1,9 +1,8 @@ //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -168,6 +167,7 @@ namespace HexagonISD { SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const; SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const; SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const; SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const; SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; @@ -285,7 +285,8 @@ namespace HexagonISD { /// is legal. It is frequently not legal in PIC relocation models. bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; - bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; + bool isFPImmLegal(const APFloat &Imm, EVT VT, + bool ForCodeSize) const override; /// isLegalICmpImmediate - Return true if the specified immediate is legal /// icmp immediate, that is the target has icmp instructions which can @@ -295,10 +296,10 @@ namespace HexagonISD { EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, - MachineFunction &MF) const override; + const AttributeList &FuncAttributes) const override; bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, - unsigned Align, bool *Fast) const override; + unsigned Align, MachineMemOperand::Flags Flags, bool *Fast) const override; /// Returns relocation base for the given PIC jumptable. SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) diff --git a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index a6400b5d8266..345c657787a0 100644 --- a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -1,9 +1,8 @@ //===-- HexagonISelLoweringHVX.cpp --- Lowering HVX operations ------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -1542,6 +1541,8 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::SRL: case ISD::SETCC: case ISD::VSELECT: + case ISD::SIGN_EXTEND: + case ISD::ZERO_EXTEND: case ISD::SIGN_EXTEND_INREG: return SplitHvxPairOp(Op, DAG); } diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index 2236140d5dd7..f156de671059 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -1,9 +1,8 @@ //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV5.td b/lib/Target/Hexagon/HexagonInstrFormatsV5.td index c8de5cbcc1e0..68ef2d2d3a8a 100644 --- a/lib/Target/Hexagon/HexagonInstrFormatsV5.td +++ b/lib/Target/Hexagon/HexagonInstrFormatsV5.td @@ -1,9 +1,8 @@ //==- HexagonInstrFormatsV5.td - Hexagon Instruction Formats --*- tablegen -==// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV60.td b/lib/Target/Hexagon/HexagonInstrFormatsV60.td index 1347a655353f..86a82183a1ad 100644 --- a/lib/Target/Hexagon/HexagonInstrFormatsV60.td +++ b/lib/Target/Hexagon/HexagonInstrFormatsV60.td @@ -1,9 +1,8 @@ //==- HexagonInstrFormatsV60.td - Hexagon Instruction Formats -*- tablegen -==// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV65.td b/lib/Target/Hexagon/HexagonInstrFormatsV65.td index cddb8777b417..eaecffe9c89e 100644 --- a/lib/Target/Hexagon/HexagonInstrFormatsV65.td +++ b/lib/Target/Hexagon/HexagonInstrFormatsV65.td @@ -1,9 +1,8 @@ //==- HexagonInstrFormatsV65.td - Hexagon Instruction Formats -*- tablegen -==// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index de0d6c4d9e4e..a156de5ba128 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1,9 +1,8 @@ //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -698,11 +697,11 @@ bool HexagonInstrInfo::analyzeLoop(MachineLoop &L, /// Generate code to reduce the loop iteration by one and check if the loop is /// finished. Return the value/register of the new loop count. this function /// assumes the nth iteration is peeled first. -unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB, - MachineInstr *IndVar, MachineInstr &Cmp, - SmallVectorImpl<MachineOperand> &Cond, - SmallVectorImpl<MachineInstr *> &PrevInsts, - unsigned Iter, unsigned MaxIter) const { +unsigned HexagonInstrInfo::reduceLoopCount( + MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, + MachineInstr &Cmp, SmallVectorImpl<MachineOperand> &Cond, + SmallVectorImpl<MachineInstr *> &PrevInsts, unsigned Iter, + unsigned MaxIter) const { // We expect a hardware loop currently. This means that IndVar is set // to null, and the compare is the ENDLOOP instruction. assert((!IndVar) && isEndLoopN(Cmp.getOpcode()) @@ -1314,6 +1313,38 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { return true; } + case Hexagon::PS_crash: { + // Generate a misaligned load that is guaranteed to cause a crash. + class CrashPseudoSourceValue : public PseudoSourceValue { + public: + CrashPseudoSourceValue(const TargetInstrInfo &TII) + : PseudoSourceValue(TargetCustom, TII) {} + + bool isConstant(const MachineFrameInfo *) const override { + return false; + } + bool isAliased(const MachineFrameInfo *) const override { + return false; + } + bool mayAlias(const MachineFrameInfo *) const override { + return false; + } + void printCustom(raw_ostream &OS) const override { + OS << "MisalignedCrash"; + } + }; + + static const CrashPseudoSourceValue CrashPSV(*this); + MachineMemOperand *MMO = MF.getMachineMemOperand( + MachinePointerInfo(&CrashPSV), + MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 8, 1); + BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13) + .addImm(0xBADC0FEE) // Misaligned load. + .addMemOperand(MMO); + MBB.erase(MI); + return true; + } + case Hexagon::PS_tailcall_i: MI.setDesc(get(Hexagon::J2_jump)); return true; @@ -1681,17 +1712,19 @@ bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI, /// Hexagon counts the number of ##'s and adjust for that many /// constant exenders. unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str, - const MCAsmInfo &MAI) const { + const MCAsmInfo &MAI, + const TargetSubtargetInfo *STI) const { StringRef AStr(Str); // Count the number of instructions in the asm. bool atInsnStart = true; unsigned Length = 0; + const unsigned MaxInstLength = MAI.getMaxInstLength(STI); for (; *Str; ++Str) { if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(), strlen(MAI.getSeparatorString())) == 0) atInsnStart = true; if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) { - Length += MAI.getMaxInstLength(); + Length += MaxInstLength; atInsnStart = false; } if (atInsnStart && strncmp(Str, MAI.getCommentString().data(), @@ -1823,7 +1856,8 @@ DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState( // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1] // Currently AA considers the addresses in these instructions to be aliasing. bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint( - MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const { + const MachineInstr &MIa, const MachineInstr &MIb, + AliasAnalysis *AA) const { if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) return false; @@ -2425,7 +2459,7 @@ bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const { const uint64_t F = get(Opcode).TSFlags; - return ~(F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask; + return (F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask; } bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const { @@ -2894,7 +2928,7 @@ bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, /// Get the base register and byte offset of a load/store instr. bool HexagonInstrInfo::getMemOperandWithOffset( - MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset, + const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const { unsigned AccessSize = 0; BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize); diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index 9b840762e88a..e0a999d0f4c4 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -1,9 +1,8 @@ //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -140,7 +139,7 @@ public: /// is finished. Return the value/register of the new loop count. We need /// this function when peeling off one or more iterations of a loop. This /// function assumes the nth iteration is peeled first. - unsigned reduceLoopCount(MachineBasicBlock &MBB, + unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl<MachineOperand> &Cond, SmallVectorImpl<MachineInstr *> &PrevInsts, @@ -216,7 +215,8 @@ public: bool expandPostRAPseudo(MachineInstr &MI) const override; /// Get the base register and byte offset of a load/store instr. - bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp, + bool getMemOperandWithOffset(const MachineInstr &LdSt, + const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const override; @@ -264,8 +264,10 @@ public: /// Measure the specified inline asm to determine an approximation of its /// length. - unsigned getInlineAsmLength(const char *Str, - const MCAsmInfo &MAI) const override; + unsigned getInlineAsmLength( + const char *Str, + const MCAsmInfo &MAI, + const TargetSubtargetInfo *STI = nullptr) const override; /// Allocate and return a hazard recognizer to use for this target when /// scheduling the machine instructions after register allocation. @@ -296,7 +298,8 @@ public: // memory addresses. This function returns true if two MIs access different // memory addresses and false otherwise. bool - areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, + areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, + const MachineInstr &MIb, AliasAnalysis *AA = nullptr) const override; /// For instructions with a base and offset, return the position of the diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td index 9cab5748bef2..cabfd783effa 100644 --- a/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/lib/Target/Hexagon/HexagonIntrinsics.td @@ -1,9 +1,8 @@ //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonIntrinsicsV5.td b/lib/Target/Hexagon/HexagonIntrinsicsV5.td index a852394f2160..44f39a3e9b16 100644 --- a/lib/Target/Hexagon/HexagonIntrinsicsV5.td +++ b/lib/Target/Hexagon/HexagonIntrinsicsV5.td @@ -1,9 +1,8 @@ //===- HexagonIntrinsicsV5.td - V5 Instruction intrinsics --*- tablegen -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonIntrinsicsV60.td b/lib/Target/Hexagon/HexagonIntrinsicsV60.td index 5e5c77b38e8e..a60c80beb5d6 100644 --- a/lib/Target/Hexagon/HexagonIntrinsicsV60.td +++ b/lib/Target/Hexagon/HexagonIntrinsicsV60.td @@ -1,9 +1,8 @@ //=- HexagonIntrinsicsV60.td - Target Description for Hexagon -*- tablegen *-=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp index 985f41f3a7d9..ac48e1dc30b0 100644 --- a/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ b/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -1,9 +1,8 @@ //===- HexagonLoopIdiomRecognition.cpp ------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -1001,6 +1000,7 @@ bool PolynomialMultiplyRecognize::isPromotableTo(Value *Val, void PolynomialMultiplyRecognize::promoteTo(Instruction *In, IntegerType *DestTy, BasicBlock *LoopB) { Type *OrigTy = In->getType(); + assert(!OrigTy->isVoidTy() && "Invalid instruction to promote"); // Leave boolean values alone. if (!In->getType()->isIntegerTy(1)) @@ -1081,7 +1081,8 @@ bool PolynomialMultiplyRecognize::promoteTypes(BasicBlock *LoopB, std::transform(LoopB->begin(), LoopB->end(), std::back_inserter(LoopIns), [](Instruction &In) { return &In; }); for (Instruction *In : LoopIns) - promoteTo(In, DestTy, LoopB); + if (!In->isTerminator()) + promoteTo(In, DestTy, LoopB); // Fix up the PHI nodes in the exit block. Instruction *EndI = ExitB->getFirstNonPHI(); @@ -1522,7 +1523,7 @@ Value *PolynomialMultiplyRecognize::generate(BasicBlock::iterator At, ParsedValues &PV) { IRBuilder<> B(&*At); Module *M = At->getParent()->getParent()->getParent(); - Value *PMF = Intrinsic::getDeclaration(M, Intrinsic::hexagon_M4_pmpyw); + Function *PMF = Intrinsic::getDeclaration(M, Intrinsic::hexagon_M4_pmpyw); Value *P = PV.P, *Q = PV.Q, *P0 = P; unsigned IC = PV.IterCount; @@ -2252,10 +2253,8 @@ CleanupAndExit: Type *Int32PtrTy = Type::getInt32PtrTy(Ctx); Type *VoidTy = Type::getVoidTy(Ctx); Module *M = Func->getParent(); - Constant *CF = M->getOrInsertFunction(HexagonVolatileMemcpyName, VoidTy, - Int32PtrTy, Int32PtrTy, Int32Ty); - Function *Fn = cast<Function>(CF); - Fn->setLinkage(Function::ExternalLinkage); + FunctionCallee Fn = M->getOrInsertFunction( + HexagonVolatileMemcpyName, VoidTy, Int32PtrTy, Int32PtrTy, Int32Ty); const SCEV *OneS = SE->getConstant(Int32Ty, 1); const SCEV *BECount32 = SE->getTruncateOrZeroExtend(BECount, Int32Ty); diff --git a/lib/Target/Hexagon/HexagonMCInstLower.cpp b/lib/Target/Hexagon/HexagonMCInstLower.cpp index fb5752ade1de..d1a153920e5e 100644 --- a/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ b/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -1,9 +1,8 @@ //===- HexagonMCInstLower.cpp - Convert Hexagon MachineInstr to an MCInst -===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp b/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp index 9579c8b6df16..aabae009d7c3 100644 --- a/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp +++ b/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp @@ -1,9 +1,8 @@ //= HexagonMachineFunctionInfo.cpp - Hexagon machine function info *- C++ -*-=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonMachineFunctionInfo.h b/lib/Target/Hexagon/HexagonMachineFunctionInfo.h index d83bcbc41553..2961e16cc9dc 100644 --- a/lib/Target/Hexagon/HexagonMachineFunctionInfo.h +++ b/lib/Target/Hexagon/HexagonMachineFunctionInfo.h @@ -1,9 +1,8 @@ //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 908ce24136c7..0e6555024303 100644 --- a/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -1,9 +1,8 @@ //===- HexagonMachineScheduler.cpp - MI Scheduler for Hexagon -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -113,6 +112,7 @@ bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) { case TargetOpcode::IMPLICIT_DEF: case TargetOpcode::COPY: case TargetOpcode::INLINEASM: + case TargetOpcode::INLINEASM_BR: break; } @@ -168,6 +168,7 @@ bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { case TargetOpcode::EH_LABEL: case TargetOpcode::COPY: case TargetOpcode::INLINEASM: + case TargetOpcode::INLINEASM_BR: break; } Packet.push_back(SU); diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.h b/lib/Target/Hexagon/HexagonMachineScheduler.h index 585a7858ad2b..fb0a7abd339b 100644 --- a/lib/Target/Hexagon/HexagonMachineScheduler.h +++ b/lib/Target/Hexagon/HexagonMachineScheduler.h @@ -1,9 +1,8 @@ //===- HexagonMachineScheduler.h - Custom Hexagon MI scheduler --*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td b/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td index b7b0de0efaea..2fcefe6a4ef6 100644 --- a/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td +++ b/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td @@ -1,9 +1,8 @@ //===--- HexagonMapAsm2IntrinV62.gen.td -----------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td b/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td index c29a75e6fe74..7293075532c6 100644 --- a/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td +++ b/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td @@ -1,9 +1,8 @@ //===--- HexagonMapAsm2IntrinV65.gen.td -----------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp index f2a6627c99be..db44901ca706 100644 --- a/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -1,9 +1,8 @@ //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonOperands.td b/lib/Target/Hexagon/HexagonOperands.td index 232946ec1579..212cf03bee67 100644 --- a/lib/Target/Hexagon/HexagonOperands.td +++ b/lib/Target/Hexagon/HexagonOperands.td @@ -1,9 +1,8 @@ //===--- HexagonOperands.td -----------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/lib/Target/Hexagon/HexagonOptAddrMode.cpp index c3a5bd5d57bf..547da9fd598f 100644 --- a/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -1,9 +1,8 @@ //===- HexagonOptAddrMode.cpp ---------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // This implements a Hexagon-specific pass to optimize addressing mode for diff --git a/lib/Target/Hexagon/HexagonOptimizeSZextends.cpp b/lib/Target/Hexagon/HexagonOptimizeSZextends.cpp index 101de3d8fbee..d00fc23102a5 100644 --- a/lib/Target/Hexagon/HexagonOptimizeSZextends.cpp +++ b/lib/Target/Hexagon/HexagonOptimizeSZextends.cpp @@ -1,9 +1,8 @@ //===- HexagonOptimizeSZextends.cpp - Remove unnecessary argument extends -===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonPatterns.td b/lib/Target/Hexagon/HexagonPatterns.td index 89177564057e..fb731f56bfbf 100644 --- a/lib/Target/Hexagon/HexagonPatterns.td +++ b/lib/Target/Hexagon/HexagonPatterns.td @@ -1,9 +1,8 @@ //==- HexagonPatterns.td - Target Description for Hexagon -*- tablegen -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -279,7 +278,7 @@ class Su_ni1<PatFrag Op> if (hasOneUse(N)){ // Check if Op1 is an immediate operand. SDValue Op1 = N->getOperand(1); - return !dyn_cast<ConstantSDNode>(Op1); + return !isa<ConstantSDNode>(Op1); } return false;}], Op.OperandTransform>; @@ -3082,7 +3081,7 @@ def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)), def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; def: Pat<(HexagonBARRIER), (Y2_barrier)>; -def: Pat<(trap), (J2_trap0 (i32 0))>; +def: Pat<(trap), (PS_crash)>; // Read cycle counter. def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; diff --git a/lib/Target/Hexagon/HexagonPatternsV65.td b/lib/Target/Hexagon/HexagonPatternsV65.td index 50b76847b563..4cd45ecbe1a1 100644 --- a/lib/Target/Hexagon/HexagonPatternsV65.td +++ b/lib/Target/Hexagon/HexagonPatternsV65.td @@ -1,9 +1,8 @@ //==- HexagonPatternsV65.td -------------------------------*- tablegen -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp index 3c588a89b0da..8f761d2d4805 100644 --- a/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/lib/Target/Hexagon/HexagonPeephole.cpp @@ -1,9 +1,8 @@ //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // // This peephole pass optimizes in the following cases. // 1. Optimizes redundant sign extends for the following case diff --git a/lib/Target/Hexagon/HexagonPseudo.td b/lib/Target/Hexagon/HexagonPseudo.td index b9748c7e189c..7dd25d7d93d5 100644 --- a/lib/Target/Hexagon/HexagonPseudo.td +++ b/lib/Target/Hexagon/HexagonPseudo.td @@ -1,9 +1,8 @@ //===--- HexagonPseudo.td -------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -560,3 +559,8 @@ defm PS_storerh : NewCircularStore<IntRegs, HalfWordAccess>; defm PS_storerf : NewCircularStore<IntRegs, HalfWordAccess>; defm PS_storeri : NewCircularStore<IntRegs, WordAccess>; defm PS_storerd : NewCircularStore<DoubleRegs, WordAccess>; + +// A pseudo that generates a runtime crash. This is used to implement +// __builtin_trap. +let hasSideEffects = 1, isPseudo = 1, isCodeGenOnly = 1, isSolo = 1 in +def PS_crash: InstHexagon<(outs), (ins), "", [], "", PSEUDO, TypePSEUDO>; diff --git a/lib/Target/Hexagon/HexagonRDFOpt.cpp b/lib/Target/Hexagon/HexagonRDFOpt.cpp index 413bc8edf2b6..910a17540e6e 100644 --- a/lib/Target/Hexagon/HexagonRDFOpt.cpp +++ b/lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -1,9 +1,8 @@ //===- HexagonRDFOpt.cpp --------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 9b8f4e07376f..4f5f750e5842 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -1,9 +1,8 @@ //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -287,7 +286,7 @@ unsigned HexagonRegisterInfo::getRARegister() const { } -unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction +Register HexagonRegisterInfo::getFrameRegister(const MachineFunction &MF) const { const HexagonFrameLowering *TFI = getFrameLowering(MF); if (TFI->hasFP(MF)) diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.h b/lib/Target/Hexagon/HexagonRegisterInfo.h index 3e7b63a462f0..fc166b5a3410 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.h +++ b/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -1,9 +1,8 @@ //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -67,7 +66,7 @@ public: // Debug information queries. unsigned getRARegister() const; - unsigned getFrameRegister(const MachineFunction &MF) const override; + Register getFrameRegister(const MachineFunction &MF) const override; unsigned getFrameRegister() const; unsigned getStackRegister() const; diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.td b/lib/Target/Hexagon/HexagonRegisterInfo.td index da90911e2c05..f12189052699 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -1,9 +1,8 @@ //===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonSchedule.td b/lib/Target/Hexagon/HexagonSchedule.td index 1024198e9b3f..0834e9000460 100644 --- a/lib/Target/Hexagon/HexagonSchedule.td +++ b/lib/Target/Hexagon/HexagonSchedule.td @@ -1,9 +1,8 @@ //===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonScheduleV5.td b/lib/Target/Hexagon/HexagonScheduleV5.td index 9a893f6dde02..ba0da2c196ab 100644 --- a/lib/Target/Hexagon/HexagonScheduleV5.td +++ b/lib/Target/Hexagon/HexagonScheduleV5.td @@ -1,9 +1,8 @@ //=-HexagonScheduleV5.td - HexagonV5 Scheduling Definitions --*- tablegen -*-=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonScheduleV55.td b/lib/Target/Hexagon/HexagonScheduleV55.td index ca738be5d6ef..f88dd5d2056d 100644 --- a/lib/Target/Hexagon/HexagonScheduleV55.td +++ b/lib/Target/Hexagon/HexagonScheduleV55.td @@ -1,9 +1,8 @@ //=-HexagonScheduleV55.td - HexagonV55 Scheduling Definitions -*- tablegen -*=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonScheduleV60.td b/lib/Target/Hexagon/HexagonScheduleV60.td index 861a8d2b0339..c6539597a9e7 100644 --- a/lib/Target/Hexagon/HexagonScheduleV60.td +++ b/lib/Target/Hexagon/HexagonScheduleV60.td @@ -1,9 +1,8 @@ //=-HexagonScheduleV60.td - HexagonV60 Scheduling Definitions *- tablegen -*-=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonScheduleV62.td b/lib/Target/Hexagon/HexagonScheduleV62.td index 1c274191277c..782d76760992 100644 --- a/lib/Target/Hexagon/HexagonScheduleV62.td +++ b/lib/Target/Hexagon/HexagonScheduleV62.td @@ -1,9 +1,8 @@ //=-HexagonScheduleV62.td - HexagonV62 Scheduling Definitions *- tablegen -*-=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonScheduleV65.td b/lib/Target/Hexagon/HexagonScheduleV65.td index 46a79d521795..ac64410e559b 100644 --- a/lib/Target/Hexagon/HexagonScheduleV65.td +++ b/lib/Target/Hexagon/HexagonScheduleV65.td @@ -1,9 +1,8 @@ //=-HexagonScheduleV65.td - HexagonV65 Scheduling Definitions *- tablegen -*-=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonScheduleV66.td b/lib/Target/Hexagon/HexagonScheduleV66.td index 38e3d21d3701..56dc59e2a948 100644 --- a/lib/Target/Hexagon/HexagonScheduleV66.td +++ b/lib/Target/Hexagon/HexagonScheduleV66.td @@ -1,9 +1,8 @@ //=-HexagonScheduleV66.td - HexagonV66 Scheduling Definitions *- tablegen -*-=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp b/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp index 002e87fb32ce..c5ba7ced4c30 100644 --- a/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp +++ b/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp @@ -1,9 +1,8 @@ //===-- HexagonSelectionDAGInfo.cpp - Hexagon SelectionDAG Info -----------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonSelectionDAGInfo.h b/lib/Target/Hexagon/HexagonSelectionDAGInfo.h index a83a8efb7588..af8b8318b059 100644 --- a/lib/Target/Hexagon/HexagonSelectionDAGInfo.h +++ b/lib/Target/Hexagon/HexagonSelectionDAGInfo.h @@ -1,9 +1,8 @@ //===-- HexagonSelectionDAGInfo.h - Hexagon SelectionDAG Info ---*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp b/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp index 55de25120943..bd4254aea276 100644 --- a/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp +++ b/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp @@ -1,9 +1,8 @@ //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonSplitDouble.cpp b/lib/Target/Hexagon/HexagonSplitDouble.cpp index e018785f24d8..013eede2d414 100644 --- a/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -1,9 +1,8 @@ //===- HexagonSplitDouble.cpp ---------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -153,8 +152,8 @@ bool HexagonSplitDoubleRegs::isInduction(unsigned Reg, LoopRegMap &IRM) const { } bool HexagonSplitDoubleRegs::isVolatileInstr(const MachineInstr *MI) const { - for (auto &I : MI->memoperands()) - if (I->isVolatile()) + for (auto &MO : MI->memoperands()) + if (MO->isVolatile() || MO->isAtomic()) return true; return false; } diff --git a/lib/Target/Hexagon/HexagonStoreWidening.cpp b/lib/Target/Hexagon/HexagonStoreWidening.cpp index 61c2121163b8..b8b61517ff95 100644 --- a/lib/Target/Hexagon/HexagonStoreWidening.cpp +++ b/lib/Target/Hexagon/HexagonStoreWidening.cpp @@ -1,9 +1,8 @@ //===- HexagonStoreWidening.cpp -------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Replace sequences of "narrow" stores to adjacent memory locations with @@ -338,8 +337,7 @@ bool HexagonStoreWidening::selectStores(InstrGroup::iterator Begin, return false; OG.push_back(FirstMI); - MachineInstr *S1 = FirstMI, *S2 = *(Begin+1); - InstrGroup::iterator I = Begin+1; + MachineInstr *S1 = FirstMI; // Pow2Num will be the largest number of elements in OG such that the sum // of sizes of stores 0...Pow2Num-1 will be a power of 2. @@ -351,8 +349,8 @@ bool HexagonStoreWidening::selectStores(InstrGroup::iterator Begin, // does not exceed the limit (MaxSize). // Keep track of when the total size covered is a power of 2, since // this is a size a single store can cover. - while (I != End) { - S2 = *I; + for (InstrGroup::iterator I = Begin + 1; I != End; ++I) { + MachineInstr *S2 = *I; // Stores are sorted, so if S1 and S2 are not adjacent, there won't be // any other store to fill the "hole". if (!storesAreAdjacent(S1, S2)) @@ -372,7 +370,6 @@ bool HexagonStoreWidening::selectStores(InstrGroup::iterator Begin, break; S1 = S2; - ++I; } // The stores don't add up to anything that can be widened. Clean up. diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp index 9c77135c2f2f..7ec63a642b0c 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -1,9 +1,8 @@ //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonSubtarget.h b/lib/Target/Hexagon/HexagonSubtarget.h index 3a5acb53682c..007423ef1902 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.h +++ b/lib/Target/Hexagon/HexagonSubtarget.h @@ -1,9 +1,8 @@ //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index ddfda7e27793..80b8480448fe 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -1,9 +1,8 @@ //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -17,6 +16,7 @@ #include "HexagonMachineScheduler.h" #include "HexagonTargetObjectFile.h" #include "HexagonTargetTransformInfo.h" +#include "TargetInfo/HexagonTargetInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/IR/LegacyPassManager.h" diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h index a7c6a3437fbc..7ee4474e90e3 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/lib/Target/Hexagon/HexagonTargetMachine.h @@ -1,9 +1,8 @@ //=-- HexagonTargetMachine.h - Define TargetMachine for Hexagon ---*- C++ -*-=// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/lib/Target/Hexagon/HexagonTargetObjectFile.cpp index 2185bf8eebc6..fdcc41a4ca41 100644 --- a/lib/Target/Hexagon/HexagonTargetObjectFile.cpp +++ b/lib/Target/Hexagon/HexagonTargetObjectFile.cpp @@ -1,9 +1,8 @@ //===-- HexagonTargetObjectFile.cpp ---------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -239,10 +238,7 @@ bool HexagonTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, return false; } - Type *GType = GVar->getType(); - if (PointerType *PT = dyn_cast<PointerType>(GType)) - GType = PT->getElementType(); - + Type *GType = GVar->getValueType(); if (isa<ArrayType>(GType)) { LLVM_DEBUG(dbgs() << "no, is an array\n"); return false; @@ -342,7 +338,7 @@ unsigned HexagonTargetObjectFile::getSmallestAddressableSize(const Type *Ty, MCSection *HexagonTargetObjectFile::selectSmallSectionForGlobal( const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const { - const Type *GTy = GO->getType()->getElementType(); + const Type *GTy = GO->getValueType(); unsigned Size = getSmallestAddressableSize(GTy, GO, TM); // If we have -ffunction-section or -fdata-section then we should emit the diff --git a/lib/Target/Hexagon/HexagonTargetObjectFile.h b/lib/Target/Hexagon/HexagonTargetObjectFile.h index 18863630fde2..b36282578950 100644 --- a/lib/Target/Hexagon/HexagonTargetObjectFile.h +++ b/lib/Target/Hexagon/HexagonTargetObjectFile.h @@ -1,9 +1,8 @@ //===-- HexagonTargetObjectFile.h -----------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonTargetStreamer.h b/lib/Target/Hexagon/HexagonTargetStreamer.h index e19c404450e6..c5200b76933e 100644 --- a/lib/Target/Hexagon/HexagonTargetStreamer.h +++ b/lib/Target/Hexagon/HexagonTargetStreamer.h @@ -1,9 +1,8 @@ //===-- HexagonTargetStreamer.h - Hexagon Target Streamer ------*- C++ -*--===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp index c942f645aa88..38062e8e922c 100644 --- a/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp +++ b/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp @@ -1,9 +1,8 @@ //===- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass ---------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // /// \file /// This file implements a TargetTransformInfo analysis pass specific to the @@ -161,14 +160,15 @@ unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned VecWidth = VecTy->getBitWidth(); if (useHVX() && isTypeForHVX(VecTy)) { unsigned RegWidth = getRegisterBitWidth(true); - Alignment = std::min(Alignment, RegWidth/8); + assert(RegWidth && "Non-zero vector register width expected"); // Cost of HVX loads. if (VecWidth % RegWidth == 0) return VecWidth / RegWidth; // Cost of constructing HVX vector from scalar loads. + Alignment = std::min(Alignment, RegWidth / 8); unsigned AlignWidth = 8 * std::max(1u, Alignment); unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth; - return 3*NumLoads; + return 3 * NumLoads; } // Non-HVX vectors. diff --git a/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/lib/Target/Hexagon/HexagonTargetTransformInfo.h index 5c6f85584ec2..27e8fc019007 100644 --- a/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -1,9 +1,8 @@ //==- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass -*- C++ -*-==// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // /// \file /// This file implements a TargetTransformInfo analysis pass specific to the diff --git a/lib/Target/Hexagon/HexagonVExtract.cpp b/lib/Target/Hexagon/HexagonVExtract.cpp index 929ac2bd0d93..a9692f42e468 100644 --- a/lib/Target/Hexagon/HexagonVExtract.cpp +++ b/lib/Target/Hexagon/HexagonVExtract.cpp @@ -1,9 +1,8 @@ //===- HexagonVExtract.cpp ------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // This pass will replace multiple occurrences of V6_extractw from the same diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 722699907ca0..3619e4c239d7 100644 --- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -1,9 +1,8 @@ //===- HexagonPacketizer.cpp - VLIW packetizer ----------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.h b/lib/Target/Hexagon/HexagonVLIWPacketizer.h index ca70cf967a46..daa86b6f5393 100644 --- a/lib/Target/Hexagon/HexagonVLIWPacketizer.h +++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.h @@ -1,9 +1,8 @@ //===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp b/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp index 9d1073346c72..e5df1d456c1e 100644 --- a/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp +++ b/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp @@ -1,9 +1,8 @@ //===- HexagonVectorLoopCarriedReuse.cpp ----------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -239,10 +238,17 @@ namespace { // used over the backedge. This is teh value that gets reused from a // previous iteration. Instruction *BackedgeInst = nullptr; + std::map<Instruction *, DepChain *> DepChains; + int Iterations = -1; ReuseValue() = default; - void reset() { Inst2Replace = nullptr; BackedgeInst = nullptr; } + void reset() { + Inst2Replace = nullptr; + BackedgeInst = nullptr; + DepChains.clear(); + Iterations = -1; + } bool isDefined() { return Inst2Replace != nullptr; } }; @@ -289,10 +295,10 @@ namespace { void findDepChainFromPHI(Instruction *I, DepChain &D); void reuseValue(); Value *findValueInBlock(Value *Op, BasicBlock *BB); - bool isDepChainBtwn(Instruction *I1, Instruction *I2, int Iters); - DepChain *getDepChainBtwn(Instruction *I1, Instruction *I2); + DepChain *getDepChainBtwn(Instruction *I1, Instruction *I2, int Iters); bool isEquivalentOperation(Instruction *I1, Instruction *I2); bool canReplace(Instruction *I); + bool isCallInstCommutative(CallInst *C); }; } // end anonymous namespace @@ -327,6 +333,70 @@ bool HexagonVectorLoopCarriedReuse::runOnLoop(Loop *L, LPPassManager &LPM) { return doVLCR(); } +bool HexagonVectorLoopCarriedReuse::isCallInstCommutative(CallInst *C) { + switch (C->getCalledFunction()->getIntrinsicID()) { + case Intrinsic::hexagon_V6_vaddb: + case Intrinsic::hexagon_V6_vaddb_128B: + case Intrinsic::hexagon_V6_vaddh: + case Intrinsic::hexagon_V6_vaddh_128B: + case Intrinsic::hexagon_V6_vaddw: + case Intrinsic::hexagon_V6_vaddw_128B: + case Intrinsic::hexagon_V6_vaddubh: + case Intrinsic::hexagon_V6_vaddubh_128B: + case Intrinsic::hexagon_V6_vadduhw: + case Intrinsic::hexagon_V6_vadduhw_128B: + case Intrinsic::hexagon_V6_vaddhw: + case Intrinsic::hexagon_V6_vaddhw_128B: + case Intrinsic::hexagon_V6_vmaxb: + case Intrinsic::hexagon_V6_vmaxb_128B: + case Intrinsic::hexagon_V6_vmaxh: + case Intrinsic::hexagon_V6_vmaxh_128B: + case Intrinsic::hexagon_V6_vmaxw: + case Intrinsic::hexagon_V6_vmaxw_128B: + case Intrinsic::hexagon_V6_vmaxub: + case Intrinsic::hexagon_V6_vmaxub_128B: + case Intrinsic::hexagon_V6_vmaxuh: + case Intrinsic::hexagon_V6_vmaxuh_128B: + case Intrinsic::hexagon_V6_vminub: + case Intrinsic::hexagon_V6_vminub_128B: + case Intrinsic::hexagon_V6_vminuh: + case Intrinsic::hexagon_V6_vminuh_128B: + case Intrinsic::hexagon_V6_vminb: + case Intrinsic::hexagon_V6_vminb_128B: + case Intrinsic::hexagon_V6_vminh: + case Intrinsic::hexagon_V6_vminh_128B: + case Intrinsic::hexagon_V6_vminw: + case Intrinsic::hexagon_V6_vminw_128B: + case Intrinsic::hexagon_V6_vmpyub: + case Intrinsic::hexagon_V6_vmpyub_128B: + case Intrinsic::hexagon_V6_vmpyuh: + case Intrinsic::hexagon_V6_vmpyuh_128B: + case Intrinsic::hexagon_V6_vavgub: + case Intrinsic::hexagon_V6_vavgub_128B: + case Intrinsic::hexagon_V6_vavgh: + case Intrinsic::hexagon_V6_vavgh_128B: + case Intrinsic::hexagon_V6_vavguh: + case Intrinsic::hexagon_V6_vavguh_128B: + case Intrinsic::hexagon_V6_vavgw: + case Intrinsic::hexagon_V6_vavgw_128B: + case Intrinsic::hexagon_V6_vavgb: + case Intrinsic::hexagon_V6_vavgb_128B: + case Intrinsic::hexagon_V6_vavguw: + case Intrinsic::hexagon_V6_vavguw_128B: + case Intrinsic::hexagon_V6_vabsdiffh: + case Intrinsic::hexagon_V6_vabsdiffh_128B: + case Intrinsic::hexagon_V6_vabsdiffub: + case Intrinsic::hexagon_V6_vabsdiffub_128B: + case Intrinsic::hexagon_V6_vabsdiffuh: + case Intrinsic::hexagon_V6_vabsdiffuh_128B: + case Intrinsic::hexagon_V6_vabsdiffw: + case Intrinsic::hexagon_V6_vabsdiffw_128B: + return true; + default: + return false; + } +} + bool HexagonVectorLoopCarriedReuse::isEquivalentOperation(Instruction *I1, Instruction *I2) { if (!I1->isSameOperationAs(I2)) @@ -361,13 +431,19 @@ bool HexagonVectorLoopCarriedReuse::isEquivalentOperation(Instruction *I1, bool HexagonVectorLoopCarriedReuse::canReplace(Instruction *I) { const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I); - if (II && - (II->getIntrinsicID() == Intrinsic::hexagon_V6_hi || - II->getIntrinsicID() == Intrinsic::hexagon_V6_lo)) { + if (!II) + return true; + + switch (II->getIntrinsicID()) { + case Intrinsic::hexagon_V6_hi: + case Intrinsic::hexagon_V6_lo: + case Intrinsic::hexagon_V6_hi_128B: + case Intrinsic::hexagon_V6_lo_128B: LLVM_DEBUG(dbgs() << "Not considering for reuse: " << *II << "\n"); return false; + default: + return true; } - return true; } void HexagonVectorLoopCarriedReuse::findValueToReuse() { for (auto *D : Dependences) { @@ -428,27 +504,85 @@ void HexagonVectorLoopCarriedReuse::findValueToReuse() { int NumOperands = I->getNumOperands(); - for (int OpNo = 0; OpNo < NumOperands; ++OpNo) { - Value *Op = I->getOperand(OpNo); - Instruction *OpInst = dyn_cast<Instruction>(Op); - if (!OpInst) - continue; - - Value *BEOp = BEUser->getOperand(OpNo); - Instruction *BEOpInst = dyn_cast<Instruction>(BEOp); - - if (!isDepChainBtwn(OpInst, BEOpInst, Iters)) { - BEUser = nullptr; - break; + // Take operands of each PNUser one by one and try to find DepChain + // with every operand of the BEUser. If any of the operands of BEUser + // has DepChain with current operand of the PNUser, break the matcher + // loop. Keep doing this for Every PNUser operand. If PNUser operand + // does not have DepChain with any of the BEUser operand, break the + // outer matcher loop, mark the BEUser as null and reset the ReuseCandidate. + // This ensures that DepChain exist for all the PNUser operand with + // BEUser operand. This also ensures that DepChains are independent of + // the positions in PNUser and BEUser. + std::map<Instruction *, DepChain *> DepChains; + CallInst *C1 = dyn_cast<CallInst>(I); + if ((I && I->isCommutative()) || (C1 && isCallInstCommutative(C1))) { + bool Found = false; + for (int OpNo = 0; OpNo < NumOperands; ++OpNo) { + Value *Op = I->getOperand(OpNo); + Instruction *OpInst = dyn_cast<Instruction>(Op); + Found = false; + for (int T = 0; T < NumOperands; ++T) { + Value *BEOp = BEUser->getOperand(T); + Instruction *BEOpInst = dyn_cast<Instruction>(BEOp); + if (!OpInst && !BEOpInst) { + if (Op == BEOp) { + Found = true; + break; + } + } + + if ((OpInst && !BEOpInst) || (!OpInst && BEOpInst)) + continue; + + DepChain *D = getDepChainBtwn(OpInst, BEOpInst, Iters); + + if (D) { + Found = true; + DepChains[OpInst] = D; + break; + } + } + if (!Found) { + BEUser = nullptr; + break; + } + } + } else { + + for (int OpNo = 0; OpNo < NumOperands; ++OpNo) { + Value *Op = I->getOperand(OpNo); + Value *BEOp = BEUser->getOperand(OpNo); + + Instruction *OpInst = dyn_cast<Instruction>(Op); + if (!OpInst) { + if (Op == BEOp) + continue; + // Do not allow reuse to occur when the operands may be different + // values. + BEUser = nullptr; + break; + } + + Instruction *BEOpInst = dyn_cast<Instruction>(BEOp); + DepChain *D = getDepChainBtwn(OpInst, BEOpInst, Iters); + + if (D) { + DepChains[OpInst] = D; + } else { + BEUser = nullptr; + break; + } } } if (BEUser) { LLVM_DEBUG(dbgs() << "Found Value for reuse.\n"); ReuseCandidate.Inst2Replace = I; ReuseCandidate.BackedgeInst = BEUser; + ReuseCandidate.DepChains = DepChains; + ReuseCandidate.Iterations = Iters; return; - } else - ReuseCandidate.reset(); + } + ReuseCandidate.reset(); } } } @@ -468,27 +602,10 @@ void HexagonVectorLoopCarriedReuse::reuseValue() { Instruction *Inst2Replace = ReuseCandidate.Inst2Replace; Instruction *BEInst = ReuseCandidate.BackedgeInst; int NumOperands = Inst2Replace->getNumOperands(); - std::map<Instruction *, DepChain *> DepChains; - int Iterations = -1; + std::map<Instruction *, DepChain *> &DepChains = ReuseCandidate.DepChains; + int Iterations = ReuseCandidate.Iterations; BasicBlock *LoopPH = CurLoop->getLoopPreheader(); - - for (int i = 0; i < NumOperands; ++i) { - Instruction *I = dyn_cast<Instruction>(Inst2Replace->getOperand(i)); - if(!I) - continue; - else { - Instruction *J = cast<Instruction>(BEInst->getOperand(i)); - DepChain *D = getDepChainBtwn(I, J); - - assert(D && - "No DepChain between corresponding operands in ReuseCandidate\n"); - if (Iterations == -1) - Iterations = D->iterations(); - assert(Iterations == D->iterations() && "Iterations mismatch"); - DepChains[I] = D; - } - } - + assert(!DepChains.empty() && "No DepChains"); LLVM_DEBUG(dbgs() << "reuseValue is making the following changes\n"); SmallVector<Instruction *, 4> InstsInPreheader; @@ -597,20 +714,11 @@ void HexagonVectorLoopCarriedReuse::findDepChainFromPHI(Instruction *I, } } -bool HexagonVectorLoopCarriedReuse::isDepChainBtwn(Instruction *I1, - Instruction *I2, - int Iters) { - for (auto *D : Dependences) { - if (D->front() == I1 && D->back() == I2 && D->iterations() == Iters) - return true; - } - return false; -} - DepChain *HexagonVectorLoopCarriedReuse::getDepChainBtwn(Instruction *I1, - Instruction *I2) { + Instruction *I2, + int Iters) { for (auto *D : Dependences) { - if (D->front() == I1 && D->back() == I2) + if (D->front() == I1 && D->back() == I2 && D->iterations() == Iters) return D; } return nullptr; diff --git a/lib/Target/Hexagon/HexagonVectorPrint.cpp b/lib/Target/Hexagon/HexagonVectorPrint.cpp index 18d2f2f4acde..65a8dcd75bdc 100644 --- a/lib/Target/Hexagon/HexagonVectorPrint.cpp +++ b/lib/Target/Hexagon/HexagonVectorPrint.cpp @@ -1,9 +1,8 @@ //===- HexagonVectorPrint.cpp - Generate vector printing instructions -----===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index af1e5429d0c2..7c0770926abe 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -1,13 +1,11 @@ //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -#include "Hexagon.h" #include "HexagonFixupKinds.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonMCChecker.h" diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index 6543d8313900..3c64893bae45 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -1,9 +1,8 @@ //===- HexagonBaseInfo.h - Top level definitions for Hexagon ----*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp index e82e6b559f62..f678bf49322e 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp @@ -1,14 +1,13 @@ //===-- HexagonELFObjectWriter.cpp - Hexagon Target Descriptions ----------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -#include "Hexagon.h" #include "MCTargetDesc/HexagonFixupKinds.h" +#include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCObjectWriter.h" diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h b/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h index 347327669ad9..8b0ddbcb949f 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h @@ -1,9 +1,8 @@ //===-- HexagonFixupKinds.h - Hexagon Specific Fixup Entries --------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp index 687e79a7dbab..6b9e63f5ac9e 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp @@ -1,9 +1,8 @@ //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -12,7 +11,6 @@ //===----------------------------------------------------------------------===// #include "HexagonInstPrinter.h" -#include "HexagonAsmPrinter.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "llvm/MC/MCAsmInfo.h" diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h b/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h index 17af046ce090..ca32c3c1f50f 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h @@ -1,9 +1,8 @@ //===-- HexagonInstPrinter.h - Convert Hexagon MCInst to assembly syntax --===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index 446b3b2ce668..f3da67562320 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -1,9 +1,8 @@ //===-- HexagonMCAsmInfo.cpp - Hexagon asm properties ---------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h index efeff2436234..e1f0a26cf858 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h @@ -1,9 +1,8 @@ //===-- HexagonTargetAsmInfo.h - Hexagon asm properties --------*- C++ -*--===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp index 53f3cba052bc..fcd3758600c1 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp @@ -1,9 +1,8 @@ //===----- HexagonMCChecker.cpp - Instruction bundle checking -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -13,7 +12,6 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/HexagonMCChecker.h" -#include "Hexagon.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCShuffler.h" diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h index 7577baace20c..bc55ade9ccd7 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h @@ -1,9 +1,8 @@ //===- HexagonMCChecker.h - Instruction bundle checking ---------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 3382684803aa..95e23c99868a 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -1,14 +1,12 @@ //===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #include "MCTargetDesc/HexagonMCCodeEmitter.h" -#include "Hexagon.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonFixupKinds.h" #include "MCTargetDesc/HexagonMCExpr.h" @@ -378,7 +376,7 @@ void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, State.Bundle = &MI; State.Index = 0; size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1; - uint64_t Features = computeAvailableFeatures(STI.getFeatureBits()); + FeatureBitset Features = computeAvailableFeatures(STI.getFeatureBits()); for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) { MCInst &HMI = const_cast<MCInst &>(*I.getInst()); diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h index fcea63db23a3..9e86dc8e4989 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h @@ -1,9 +1,8 @@ //===- HexagonMCCodeEmitter.h - Hexagon Target Descriptions -----*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// /// @@ -83,9 +82,10 @@ private: // Return parse bits for instruction `MCI' inside bundle `MCB' uint32_t parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const; - uint64_t computeAvailableFeatures(const FeatureBitset &FB) const; - void verifyInstructionPredicates(const MCInst &MI, - uint64_t AvailableFeatures) const; + FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const; + void + verifyInstructionPredicates(const MCInst &MI, + const FeatureBitset &AvailableFeatures) const; }; } // end namespace llvm diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp index 3eaef9ac7410..ed571188c1e8 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp @@ -1,9 +1,8 @@ //=== HexagonMCCompound.cpp - Hexagon Compound checker -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -11,7 +10,6 @@ // //===----------------------------------------------------------------------===// -#include "Hexagon.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCShuffler.h" diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp index f0654d612b4b..3cbb8600ce7a 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp @@ -1,9 +1,8 @@ //===- HexagonMCDuplexInfo.cpp - Instruction bundle checking --------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp index f304bc50530f..f2432883af6f 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp @@ -1,9 +1,8 @@ //=== HexagonMCELFStreamer.cpp - Hexagon subclass of MCELFStreamer -------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -60,7 +59,7 @@ HexagonMCELFStreamer::HexagonMCELFStreamer( MCII(createHexagonMCInstrInfo()) {} void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCB, - const MCSubtargetInfo &STI, bool) { + const MCSubtargetInfo &STI) { assert(MCB.getOpcode() == Hexagon::BUNDLE); assert(HexagonMCInstrInfo::bundleSize(MCB) <= HEXAGON_PACKET_SIZE); assert(HexagonMCInstrInfo::bundleSize(MCB) > 0); diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h index c02bef8f06f7..6248bd25d433 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h @@ -1,9 +1,8 @@ //===- HexagonMCELFStreamer.h - Hexagon subclass of MCElfStreamer ---------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -31,8 +30,7 @@ public: std::unique_ptr<MCCodeEmitter> Emitter, MCAssembler *Assembler); - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - bool) override; + void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; void EmitSymbol(const MCInst &Inst); void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp index f0689252b396..1e708ba1bcd3 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp @@ -1,10 +1,9 @@ //===-- HexagonMCExpr.cpp - Hexagon specific MC expression classes //----------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h index acfd996ccf82..59b1326adf0c 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h @@ -1,9 +1,8 @@ //==- HexagonMCExpr.h - Hexagon specific MC expression classes --*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp index a11aa92ccbe1..0750bfe74f76 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -1,9 +1,8 @@ //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -12,7 +11,6 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/HexagonMCInstrInfo.h" -#include "Hexagon.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonMCChecker.h" #include "MCTargetDesc/HexagonMCExpr.h" diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h index d040bea23b6d..829f872c453e 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h @@ -1,9 +1,8 @@ //===- HexagonMCInstrInfo.cpp - Utility functions on Hexagon MCInsts ------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp index 4281144acaee..7d45b4fcfdde 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp @@ -1,9 +1,8 @@ //===----- HexagonMCShuffler.cpp - MC bundle shuffling --------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -15,7 +14,6 @@ #define DEBUG_TYPE "hexagon-shuffle" #include "MCTargetDesc/HexagonMCShuffler.h" -#include "Hexagon.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonShuffler.h" #include "llvm/MC/MCInst.h" diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h index 59658999d24d..3410c0ddbd84 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h @@ -1,9 +1,8 @@ //===- HexagonMCShuffler.h --------------------------------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 92ce7345f358..9c50b25156c3 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -1,9 +1,8 @@ //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -12,13 +11,13 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/HexagonMCTargetDesc.h" -#include "Hexagon.h" #include "HexagonDepArch.h" #include "HexagonTargetStreamer.h" #include "MCTargetDesc/HexagonInstPrinter.h" #include "MCTargetDesc/HexagonMCAsmInfo.h" #include "MCTargetDesc/HexagonMCELFStreamer.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" +#include "TargetInfo/HexagonTargetInfo.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/BinaryFormat/ELF.h" diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h index d6ea664222d3..7b42460a2a1c 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -1,9 +1,8 @@ //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -64,7 +63,6 @@ class StringRef; class raw_ostream; class raw_pwrite_stream; -Target &getTheHexagonTarget(); extern cl::opt<bool> HexagonDisableCompound; extern cl::opt<bool> HexagonDisableDuplex; extern const InstrStage HexagonStages[]; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index f4ee2bbfaaaa..18c7790a17cc 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -1,9 +1,8 @@ //===- HexagonShuffler.cpp - Instruction bundle shuffling -----------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -15,7 +14,6 @@ #define DEBUG_TYPE "hexagon-shuffle" #include "MCTargetDesc/HexagonShuffler.h" -#include "Hexagon.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" @@ -23,6 +21,7 @@ #include "llvm/ADT/Twine.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h index ef50c5bebbfb..bf3bad36dfe5 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h @@ -1,9 +1,8 @@ //===- HexagonShuffler.h - Instruction bundle shuffling ---------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -15,8 +14,8 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H -#include "Hexagon.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" +#include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" diff --git a/lib/Target/Hexagon/RDFCopy.cpp b/lib/Target/Hexagon/RDFCopy.cpp index 4339fa2089d9..7702024f87bd 100644 --- a/lib/Target/Hexagon/RDFCopy.cpp +++ b/lib/Target/Hexagon/RDFCopy.cpp @@ -1,9 +1,8 @@ //===- RDFCopy.cpp --------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/RDFCopy.h b/lib/Target/Hexagon/RDFCopy.h index 7b2e78bdf633..1450ab884849 100644 --- a/lib/Target/Hexagon/RDFCopy.h +++ b/lib/Target/Hexagon/RDFCopy.h @@ -1,9 +1,8 @@ //===- RDFCopy.h ------------------------------------------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/RDFDeadCode.cpp b/lib/Target/Hexagon/RDFDeadCode.cpp index 8dcd485d65e9..52178931aa6d 100644 --- a/lib/Target/Hexagon/RDFDeadCode.cpp +++ b/lib/Target/Hexagon/RDFDeadCode.cpp @@ -1,9 +1,8 @@ //===--- RDFDeadCode.cpp --------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/RDFDeadCode.h b/lib/Target/Hexagon/RDFDeadCode.h index 8977e730b855..7f91977e1d6c 100644 --- a/lib/Target/Hexagon/RDFDeadCode.h +++ b/lib/Target/Hexagon/RDFDeadCode.h @@ -1,9 +1,8 @@ //===--- RDFDeadCode.h ----------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/RDFGraph.cpp b/lib/Target/Hexagon/RDFGraph.cpp index d8ca08e70505..9d8f706b8a0f 100644 --- a/lib/Target/Hexagon/RDFGraph.cpp +++ b/lib/Target/Hexagon/RDFGraph.cpp @@ -1,9 +1,8 @@ //===- RDFGraph.cpp -------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -55,7 +54,6 @@ raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P) { return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterRef> &P) { auto &TRI = P.G.getTRI(); if (P.Obj.Reg > 0 && P.Obj.Reg < TRI.getNumRegs()) @@ -66,7 +64,6 @@ raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterRef> &P) { return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<NodeId> &P) { auto NA = P.G.addr<NodeBase*>(P.Obj); uint16_t Attrs = NA.Addr->getAttrs(); @@ -116,7 +113,6 @@ static void printRefHeader(raw_ostream &OS, const NodeAddr<RefNode*> RA, OS << '!'; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<DefNode*>> &P) { printRefHeader(OS, P.Obj, P.G); OS << '('; @@ -134,7 +130,6 @@ raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<DefNode*>> &P) { return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<UseNode*>> &P) { printRefHeader(OS, P.Obj, P.G); OS << '('; @@ -146,7 +141,6 @@ raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<UseNode*>> &P) { return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<PhiUseNode*>> &P) { printRefHeader(OS, P.Obj, P.G); @@ -162,7 +156,6 @@ raw_ostream &operator<< (raw_ostream &OS, return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<RefNode*>> &P) { switch (P.Obj.Addr->getKind()) { case NodeAttrs::Def: @@ -178,7 +171,6 @@ raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<RefNode*>> &P) { return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<NodeList> &P) { unsigned N = P.Obj.size(); for (auto I : P.Obj) { @@ -189,7 +181,6 @@ raw_ostream &operator<< (raw_ostream &OS, const Print<NodeList> &P) { return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<NodeSet> &P) { unsigned N = P.Obj.size(); for (auto I : P.Obj) { @@ -224,16 +215,13 @@ namespace { } // end anonymous namespace -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<PhiNode*>> &P) { OS << Print<NodeId>(P.Obj.Id, P.G) << ": phi [" << PrintListV<RefNode*>(P.Obj.Addr->members(P.G), P.G) << ']'; return OS; } -template<> -raw_ostream &operator<< (raw_ostream &OS, - const Print<NodeAddr<StmtNode*>> &P) { +raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<StmtNode *>> &P) { const MachineInstr &MI = *P.Obj.Addr->getCode(); unsigned Opc = MI.getOpcode(); OS << Print<NodeId>(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc); @@ -258,7 +246,6 @@ raw_ostream &operator<< (raw_ostream &OS, return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<InstrNode*>> &P) { switch (P.Obj.Addr->getKind()) { @@ -275,7 +262,6 @@ raw_ostream &operator<< (raw_ostream &OS, return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<BlockNode*>> &P) { MachineBasicBlock *BB = P.Obj.Addr->getCode(); @@ -309,9 +295,7 @@ raw_ostream &operator<< (raw_ostream &OS, return OS; } -template<> -raw_ostream &operator<< (raw_ostream &OS, - const Print<NodeAddr<FuncNode*>> &P) { +raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<FuncNode *>> &P) { OS << "DFG dump:[\n" << Print<NodeId>(P.Obj.Id, P.G) << ": Function: " << P.Obj.Addr->getCode()->getName() << '\n'; for (auto I : P.Obj.Addr->members(P.G)) @@ -320,7 +304,6 @@ raw_ostream &operator<< (raw_ostream &OS, return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterSet> &P) { OS << '{'; for (auto I : P.Obj) @@ -329,13 +312,11 @@ raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterSet> &P) { return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterAggr> &P) { P.Obj.print(OS); return OS; } -template<> raw_ostream &operator<< (raw_ostream &OS, const Print<DataFlowGraph::DefStack> &P) { for (auto I = P.Obj.top(), E = P.Obj.bottom(); I != E; ) { diff --git a/lib/Target/Hexagon/RDFGraph.h b/lib/Target/Hexagon/RDFGraph.h index e3abb0e22f76..585f43e116f9 100644 --- a/lib/Target/Hexagon/RDFGraph.h +++ b/lib/Target/Hexagon/RDFGraph.h @@ -1,9 +1,8 @@ //===- RDFGraph.h -----------------------------------------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -925,10 +924,6 @@ namespace rdf { return MM; } - template <typename T> struct Print; - template <typename T> - raw_ostream &operator<< (raw_ostream &OS, const Print<T> &P); - template <typename T> struct Print { Print(const T &x, const DataFlowGraph &g) : Obj(x), G(g) {} @@ -943,6 +938,29 @@ namespace rdf { : Print<NodeAddr<T>>(x, g) {} }; + raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterRef> &P); + raw_ostream &operator<<(raw_ostream &OS, const Print<NodeId> &P); + raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<DefNode *>> &P); + raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<UseNode *>> &P); + raw_ostream &operator<<(raw_ostream &OS, + const Print<NodeAddr<PhiUseNode *>> &P); + raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<RefNode *>> &P); + raw_ostream &operator<<(raw_ostream &OS, const Print<NodeList> &P); + raw_ostream &operator<<(raw_ostream &OS, const Print<NodeSet> &P); + raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<PhiNode *>> &P); + raw_ostream &operator<<(raw_ostream &OS, + const Print<NodeAddr<StmtNode *>> &P); + raw_ostream &operator<<(raw_ostream &OS, + const Print<NodeAddr<InstrNode *>> &P); + raw_ostream &operator<<(raw_ostream &OS, + const Print<NodeAddr<BlockNode *>> &P); + raw_ostream &operator<<(raw_ostream &OS, + const Print<NodeAddr<FuncNode *>> &P); + raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterSet> &P); + raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterAggr> &P); + raw_ostream &operator<<(raw_ostream &OS, + const Print<DataFlowGraph::DefStack> &P); + } // end namespace rdf } // end namespace llvm diff --git a/lib/Target/Hexagon/RDFLiveness.cpp b/lib/Target/Hexagon/RDFLiveness.cpp index 9ff48d25a026..9cd304aa10bc 100644 --- a/lib/Target/Hexagon/RDFLiveness.cpp +++ b/lib/Target/Hexagon/RDFLiveness.cpp @@ -1,9 +1,8 @@ //===- RDFLiveness.cpp ----------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -58,7 +57,6 @@ static cl::opt<unsigned> MaxRecNest("rdf-liveness-max-rec", cl::init(25), namespace llvm { namespace rdf { - template<> raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) { OS << '{'; for (auto &I : P.Obj) { diff --git a/lib/Target/Hexagon/RDFLiveness.h b/lib/Target/Hexagon/RDFLiveness.h index eaeb4ea115b3..ea4890271726 100644 --- a/lib/Target/Hexagon/RDFLiveness.h +++ b/lib/Target/Hexagon/RDFLiveness.h @@ -1,9 +1,8 @@ //===- RDFLiveness.h --------------------------------------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -143,6 +142,8 @@ namespace rdf { unsigned Nest, unsigned MaxNest); }; + raw_ostream &operator<<(raw_ostream &OS, const Print<Liveness::RefMap> &P); + } // end namespace rdf } // end namespace llvm diff --git a/lib/Target/Hexagon/RDFRegisters.cpp b/lib/Target/Hexagon/RDFRegisters.cpp index 9408c5dc3952..6e0f33695f0e 100644 --- a/lib/Target/Hexagon/RDFRegisters.cpp +++ b/lib/Target/Hexagon/RDFRegisters.cpp @@ -1,9 +1,8 @@ //===- RDFRegisters.cpp ---------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/RDFRegisters.h b/lib/Target/Hexagon/RDFRegisters.h index 459850d87df1..646233bacda5 100644 --- a/lib/Target/Hexagon/RDFRegisters.h +++ b/lib/Target/Hexagon/RDFRegisters.h @@ -1,9 +1,8 @@ //===- RDFRegisters.h -------------------------------------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp b/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp index 78e2f2b2ddb3..d77b235d0077 100644 --- a/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp +++ b/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp @@ -1,14 +1,12 @@ //===-- HexagonTargetInfo.cpp - Hexagon Target Implementation ------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -#include "Hexagon.h" -#include "llvm/IR/Module.h" +#include "TargetInfo/HexagonTargetInfo.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; diff --git a/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.h b/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.h new file mode 100644 index 000000000000..902b61cb5b6c --- /dev/null +++ b/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.h @@ -0,0 +1,20 @@ +//===-- HexagonTargetInfo.h - Hexagon Target Implementation -----*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_HEXAGON_TARGETINFO_HEXAGONTARGETINFO_H +#define LLVM_LIB_TARGET_HEXAGON_TARGETINFO_HEXAGONTARGETINFO_H + +namespace llvm { + +class Target; + +Target &getTheHexagonTarget(); + +} // namespace llvm + +#endif // LLVM_LIB_TARGET_HEXAGON_TARGETINFO_HEXAGONTARGETINFO_H |