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| author | Dimitry Andric <dim@FreeBSD.org> | 2013-12-22 00:04:03 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2013-12-22 00:04:03 +0000 |
| commit | f8af5cf600354830d4ccf59732403f0f073eccb9 (patch) | |
| tree | 2ba0398b4c42ad4f55561327538044fd2c925a8b /lib/Target/Mips/Mips16RegisterInfo.cpp | |
| parent | 59d6cff90eecf31cb3dd860c4e786674cfdd42eb (diff) | |
| download | src-f8af5cf600354830d4ccf59732403f0f073eccb9.tar.gz src-f8af5cf600354830d4ccf59732403f0f073eccb9.zip | |
Notes
Diffstat (limited to 'lib/Target/Mips/Mips16RegisterInfo.cpp')
| -rw-r--r-- | lib/Target/Mips/Mips16RegisterInfo.cpp | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/lib/Target/Mips/Mips16RegisterInfo.cpp b/lib/Target/Mips/Mips16RegisterInfo.cpp index 7ad18f2b4d98..9d0f2c927e4d 100644 --- a/lib/Target/Mips/Mips16RegisterInfo.cpp +++ b/lib/Target/Mips/Mips16RegisterInfo.cpp @@ -41,17 +41,16 @@ using namespace llvm; -Mips16RegisterInfo::Mips16RegisterInfo(const MipsSubtarget &ST, - const Mips16InstrInfo &I) - : MipsRegisterInfo(ST), TII(I) {} +Mips16RegisterInfo::Mips16RegisterInfo(const MipsSubtarget &ST) + : MipsRegisterInfo(ST) {} bool Mips16RegisterInfo::requiresRegisterScavenging (const MachineFunction &MF) const { - return true; + return false; } bool Mips16RegisterInfo::requiresFrameIndexScavenging (const MachineFunction &MF) const { - return true; + return false; } bool Mips16RegisterInfo::useFPForScavengingIndex @@ -66,6 +65,7 @@ bool Mips16RegisterInfo::saveScavengerRegister const TargetRegisterClass *RC, unsigned Reg) const { DebugLoc DL; + const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo(); TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true); TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true); return true; @@ -134,11 +134,14 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II, DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); - if (!MI.isDebugValue() && ( ((FrameReg != Mips::SP) && !isInt<16>(Offset)) || - ((FrameReg == Mips::SP) && !isInt<15>(Offset)) )) { + if (!MI.isDebugValue() && + !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) { MachineBasicBlock &MBB = *MI.getParent(); DebugLoc DL = II->getDebugLoc(); unsigned NewImm; + const Mips16InstrInfo &TII = + *static_cast<const Mips16InstrInfo*>( + MBB.getParent()->getTarget().getInstrInfo()); FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm); Offset = SignExtend64<16>(NewImm); IsKill = true; |