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authorDimitry Andric <dim@FreeBSD.org>2017-12-18 20:10:56 +0000
committerDimitry Andric <dim@FreeBSD.org>2017-12-18 20:10:56 +0000
commit044eb2f6afba375a914ac9d8024f8f5142bb912e (patch)
tree1475247dc9f9fe5be155ebd4c9069c75aadf8c20 /lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
parenteb70dddbd77e120e5d490bd8fbe7ff3f8fa81c6b (diff)
Notes
Diffstat (limited to 'lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h')
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h b/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
index acea600fbb0d..603ac960133f 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
@@ -70,6 +70,22 @@ namespace PPC {
/// Assume the condition register is set by MI(a,b), return the predicate if
/// we modify the instructions such that condition register is set by MI(b,a).
Predicate getSwappedPredicate(Predicate Opcode);
+
+ /// Return the condition without hint bits.
+ inline unsigned getPredicateCondition(Predicate Opcode) {
+ return (unsigned)(Opcode & ~BR_HINT_MASK);
+ }
+
+ /// Return the hint bits of the predicate.
+ inline unsigned getPredicateHint(Predicate Opcode) {
+ return (unsigned)(Opcode & BR_HINT_MASK);
+ }
+
+ /// Return predicate consisting of specified condition and hint bits.
+ inline Predicate getPredicate(unsigned Condition, unsigned Hint) {
+ return (Predicate)((Condition & ~BR_HINT_MASK) |
+ (Hint & BR_HINT_MASK));
+ }
}
}