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authorRoman Divacky <rdivacky@FreeBSD.org>2010-02-16 09:30:23 +0000
committerRoman Divacky <rdivacky@FreeBSD.org>2010-02-16 09:30:23 +0000
commit6fe5c7aa327e188b7176daa5595bbf075a6b94df (patch)
tree4cfca640904d1896e25032757a61f8959c066919 /lib/Target/PowerPC/PPCISelDAGToDAG.cpp
parent989df958a10f0beb90b89ccadd8351cbe51d90b1 (diff)
Notes
Diffstat (limited to 'lib/Target/PowerPC/PPCISelDAGToDAG.cpp')
-rw-r--r--lib/Target/PowerPC/PPCISelDAGToDAG.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 32c1879cf713..004997fe8cdb 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -199,7 +199,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
// Check to see if this function uses vector registers, which means we have to
// save and restore the VRSAVE register and update it with the regs we use.
//
- // In this case, there will be virtual registers of vector type type created
+ // In this case, there will be virtual registers of vector type created
// by the scheduler. Detect them now.
bool HasVectorVReg = false;
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,