diff options
| author | Roman Divacky <rdivacky@FreeBSD.org> | 2010-05-04 16:11:02 +0000 |
|---|---|---|
| committer | Roman Divacky <rdivacky@FreeBSD.org> | 2010-05-04 16:11:02 +0000 |
| commit | d7f7719e5e082c0b8ea2182dcbd2242b7834aa26 (patch) | |
| tree | 70fbd90da02177c8e6ef82adba9fa8ace285a5e3 /lib/Target/PowerPC/PPCScheduleG3.td | |
| parent | 9f4a1da9a0a56a0b0a7f8249f34b3cdea6179c41 (diff) | |
Notes
Diffstat (limited to 'lib/Target/PowerPC/PPCScheduleG3.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG3.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCScheduleG3.td b/lib/Target/PowerPC/PPCScheduleG3.td index f72194d6de0e..73447631b2ad 100644 --- a/lib/Target/PowerPC/PPCScheduleG3.td +++ b/lib/Target/PowerPC/PPCScheduleG3.td @@ -12,7 +12,8 @@ //===----------------------------------------------------------------------===// -def G3Itineraries : ProcessorItineraries<[ +def G3Itineraries : ProcessorItineraries< + [IU1, IU2, FPU1, BPU, SRU, SLU], [ InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>, |