diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
| commit | 71d5a2540a98c81f5bcaeb48805e0e2881f530ef (patch) | |
| tree | 5343938942df402b49ec7300a1c25a2d4ccd5821 /lib/Target/RISCV/RISCVTargetMachine.cpp | |
| parent | 31bbf64f3a4974a2d6c8b3b27ad2f519caf74057 (diff) | |
Diffstat (limited to 'lib/Target/RISCV/RISCVTargetMachine.cpp')
| -rw-r--r-- | lib/Target/RISCV/RISCVTargetMachine.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/RISCV/RISCVTargetMachine.cpp b/lib/Target/RISCV/RISCVTargetMachine.cpp index afbbe004186e..a20331cd0a3e 100644 --- a/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -32,7 +32,7 @@ static std::string computeDataLayout(const Triple &TT) { return "e-m:e-i64:64-n32:64-S128"; } else { assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); - return "e-m:e-i64:64-n32-S128"; + return "e-m:e-p:32:32-i64:64-n32-S128"; } } @@ -51,7 +51,9 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, CodeGenOpt::Level OL) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), CM, OL), - TLOF(make_unique<TargetLoweringObjectFileELF>()) {} + TLOF(make_unique<TargetLoweringObjectFileELF>()) { + initAsmInfo(); +} TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { return new TargetPassConfig(this, PM); |