diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2023-02-11 12:38:04 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2023-02-11 12:38:11 +0000 |
| commit | e3b557809604d036af6e00c60f012c2025b59a5e (patch) | |
| tree | 8a11ba2269a3b669601e2fd41145b174008f4da8 /llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp | |
| parent | 08e8dd7b9db7bb4a9de26d44c1cbfd24e869c014 (diff) | |
Diffstat (limited to 'llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp index 252910fd9462..55d939de426e 100644 --- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp +++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp @@ -422,7 +422,7 @@ public: LLVM_DEBUG(dbgs() << "Insert spill before " << *InsertBefore); TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI, - RC, &TRI); + RC, &TRI, Register()); } } @@ -431,7 +431,7 @@ public: const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); int FI = RegToSlotIdx[Reg]; if (It != MBB->end()) { - TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI); + TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register()); return; } @@ -439,7 +439,7 @@ public: // and then swap them. assert(!MBB->empty() && "Empty block"); --It; - TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI); + TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register()); MachineInstr *Reload = It->getPrevNode(); int Dummy = 0; (void)Dummy; |
