diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2022-02-05 18:04:23 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2022-02-05 18:05:05 +0000 |
| commit | ecbca9f5fb7d7613d2b94982c4825eb0d33d6842 (patch) | |
| tree | 3a4038f3b7bafaeade9fd6146ea8021237616657 /llvm/lib/CodeGen/PostRASchedulerList.cpp | |
| parent | 6f8fc217eaa12bf657be1c6468ed9938d10168b3 (diff) | |
Diffstat (limited to 'llvm/lib/CodeGen/PostRASchedulerList.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/PostRASchedulerList.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index d7cd0a583cee..aac46cb22084 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -139,7 +139,7 @@ namespace { /// /// This is the instruction number from the top of the current block, not /// the SlotIndex. It is only used by the AntiDepBreaker. - unsigned EndIndex; + unsigned EndIndex = 0; public: SchedulePostRATDList( @@ -206,7 +206,7 @@ SchedulePostRATDList::SchedulePostRATDList( const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs) - : ScheduleDAGInstrs(MF, &MLI), AA(AA), EndIndex(0) { + : ScheduleDAGInstrs(MF, &MLI), AA(AA) { const InstrItineraryData *InstrItins = MF.getSubtarget().getInstrItineraryData(); |