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| author | Dimitry Andric <dim@FreeBSD.org> | 2024-01-03 16:57:07 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2024-01-03 16:57:07 +0000 |
| commit | 77dbea07356e1ab2f37a777d4d1ddc5dd3e301c2 (patch) | |
| tree | bdb0bc8db7a91e1f8b4bb8729fc391e2adf45380 /llvm/lib/Target/AVR/AVRISelLowering.cpp | |
| parent | 99aabd70801bd4bc72c4942747f6d62c675112f5 (diff) | |
| download | src-77dbea07356e1ab2f37a777d4d1ddc5dd3e301c2.tar.gz src-77dbea07356e1ab2f37a777d4d1ddc5dd3e301c2.zip | |
Diffstat (limited to 'llvm/lib/Target/AVR/AVRISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AVR/AVRISelLowering.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp index cd1dcfaea0eb..d36bfb188ed3 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -298,8 +298,7 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const { SDValue SrcHi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i16, Op.getOperand(0), DAG.getConstant(1, dl, MVT::i16)); - uint64_t ShiftAmount = - cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); + uint64_t ShiftAmount = N->getConstantOperandVal(1); if (ShiftAmount == 16) { // Special case these two operations because they appear to be used by the // generic codegen parts to lower 32-bit numbers. @@ -367,7 +366,7 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const { } } - uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); + uint64_t ShiftAmount = N->getConstantOperandVal(1); SDValue Victim = N->getOperand(0); switch (Op.getOpcode()) { |