diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
| commit | cfca06d7963fa0909f90483b42a6d7d194d01e08 (patch) | |
| tree | 209fb2a2d68f8f277793fc8df46c753d31bc853b /llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | |
| parent | 706b4fc47bbc608932d3b491ae19a3b9cde9497b (diff) | |
Notes
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index 799b85ed48b4..49edb0d99492 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1433,10 +1433,16 @@ unsigned ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C, .addImm(int32_t(Lo)); return Reg; } + MachineFunction *MF = B.getParent(); + auto &HST = MF->getSubtarget<HexagonSubtarget>(); - BuildMI(B, At, DL, HII.get(Hexagon::CONST64), Reg) - .addImm(C); - return Reg; + // Disable CONST64 for tiny core since it takes a LD resource. + if (!HST.isTinyCore() || + MF->getFunction().hasOptSize()) { + BuildMI(B, At, DL, HII.get(Hexagon::CONST64), Reg) + .addImm(C); + return Reg; + } } if (RC == &Hexagon::PredRegsRegClass) { |