diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2021-02-16 20:13:02 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2021-02-16 20:13:02 +0000 |
| commit | b60736ec1405bb0a8dd40989f67ef4c93da068ab (patch) | |
| tree | 5c43fbb7c9fc45f0f87e0e6795a86267dbd12f9d /llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp | |
| parent | cfca06d7963fa0909f90483b42a6d7d194d01e08 (diff) | |
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp index 903287e68c99..d8d2025c5d27 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -48,7 +48,8 @@ namespace { // FIXME: Use TargetInstrInfo::RegSubRegPair struct RegisterSubReg { - unsigned R, S; + Register R; + unsigned S; RegisterSubReg(unsigned r = 0, unsigned s = 0) : R(r), S(s) {} RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {} @@ -111,7 +112,7 @@ namespace { VectOfInst PUsers; RegToRegMap G2P; - bool isPredReg(unsigned R); + bool isPredReg(Register R); void collectPredicateGPR(MachineFunction &MF); void processPredicateGPR(const RegisterSubReg &Reg); unsigned getPredForm(unsigned Opc); @@ -133,8 +134,8 @@ INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) INITIALIZE_PASS_END(HexagonGenPredicate, "hexagon-gen-pred", "Hexagon generate predicate operations", false, false) -bool HexagonGenPredicate::isPredReg(unsigned R) { - if (!Register::isVirtualRegister(R)) +bool HexagonGenPredicate::isPredReg(Register R) { + if (!R.isVirtual()) return false; const TargetRegisterClass *RC = MRI->getRegClass(R); return RC == &Hexagon::PredRegsRegClass; @@ -214,7 +215,7 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) { case TargetOpcode::COPY: if (isPredReg(MI->getOperand(1).getReg())) { RegisterSubReg RD = MI->getOperand(0); - if (Register::isVirtualRegister(RD.R)) + if (RD.R.isVirtual()) PredGPRs.insert(RD); } break; @@ -246,7 +247,7 @@ RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { // Create a predicate register for a given Reg. The newly created register // will have its value copied from Reg, so that it can be later used as // an operand in other instructions. - assert(Register::isVirtualRegister(Reg.R)); + assert(Reg.R.isVirtual()); RegToRegMap::iterator F = G2P.find(Reg); if (F != G2P.end()) return F->second; @@ -472,9 +473,9 @@ bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) { continue; RegisterSubReg DR = MI.getOperand(0); RegisterSubReg SR = MI.getOperand(1); - if (!Register::isVirtualRegister(DR.R)) + if (!DR.R.isVirtual()) continue; - if (!Register::isVirtualRegister(SR.R)) + if (!SR.R.isVirtual()) continue; if (MRI->getRegClass(DR.R) != PredRC) continue; |